QUICK LOGIC QL4016-0CF100C, QL4016-0CF100I, QL4016-0PF100C, QL4016-0PF100I, QL4016-1PF100C Datasheet

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QL4016 QuickRAM Data Sheet

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16,000 Usable PLD Gate QuickRAM ESP Combining Performance, Density and Embedded RAM

Device Highlights

High Performance & High Density

• 16,000 Usable PLD Gates with 118 I/Os

• 300 MHz 16-bit Counters, 400 MHz

Datapaths, 160+ MHz FIFOs

• 0.35 µm four-layer metal non-volatile

CMOS process for smallest die sizes

High Speed Embedded SRAM

• 10 dual-port RAM modules, organized in

user-configurable 1,152 bit blocks

• 5 ns access times, each port independently

accessible

• Fast and efficient for FIFO, RAM, and ROM

functions

Advanced I/O Capabilities

• Interfaces with both 3.3 V and 5.0 V devices

• PCI compliant with 3.3 V and 5.0 V busses

for -1/-2/-3/-4 speed grades

• Full JTAG boundary scan

• I/O Cells with individually controlled

Registered Input Path and Output Enables

RA M

Blocks

Hi gh Sp eed

Logic Cells

320

Easy to Use / Fast Developm ent Cycles

• 100% routable with 100% utilization and

complete pin-out stability

• Variable-grain logic cells provide high

performance and 100% utilization

• Comprehensive design tools include high

quality Verilog/VHDL synthesis

Figure 1: QuickRAM Block Diagram

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Interface

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QL4016 QuickRAM Data Sheet Rev I

Architecture Overview

The QuickRAM family of ESPs (Embedded Standard Products) offers FPGA logic in combination with Dual-Port SRAM modules. The QL4016 is a 16,000 usable PLD gate

member of the QuickRAM family of ESPs. QuickRAM ESPs are fabricated on a 0.35 µm

four-layer metal process using QuickLogic's patented ViaLink unique combination of high performance, high density, low cost, and extreme ease-of-use.

The QL4016 contains 320 logic cells and 10 Dual Port RAM modules (see Figure 1). Each RAM module has 1,152 RAM bits, for a total of 11,520 bits. RAM Modules are Dual Port (one read port, one write port) and can be configured into one of four modes: 64 (deep) × 18 (wide), 128 × 9, 256 × 4, or 512 × 2 (see I/Os, the QL4016 is available in 84-pin PLCC, 100-pin TQFP, 100-pin CQFP and 144-pin TQFP packages.

Designers can cascade multiple RAM modules to increase the depth or width allowed in single modules by connecting corresponding address lines together and dividing the words between modules (see large as 16 bits wide in the smallest QuickRAM device and 44 bits wide in the largest device.

TM

technology to provide a

Figure 4). With a maximum of 82

Figure 2). This approach allows up to 512-deep configurations as

Software support for the complete QuickRAM family, including the QL4016, is available through two basic packages. The turnkey QuickWorks

TM

package provides the most complete ESP software solution from design entry to logic synthesis, to place and route, to simulation. The QuickTools package provides a solution for designers who use Cadence, Exemplar, Mentor, Synopsys, Synplicity, Viewlogic, Aldec, or other third-party tools for design entry, synthesis, or simulation.

The QuickLogic

TM

variable grain logic cell features up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see

RAM

Module

(1,152 bits)

WADDR

RAM

Module

(1,152 bits)

WDATA

Figure 3).

RDATAWDATA

RADDR

RDATA

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Figure 2: QuickRAM Module Bits

Product Summary

Total of 118 I/O Pins

• 110 bi-directional input/output pins, PCI-compliant for 5.0 V and 3.3 V buses for

-1/-2/-3/-4 speed grades

• 8 high-drive input/distributed network pins

Eight Low-Skew Distributed Networks

• Two array clock/control networks available to the logic cell flip-flop clock, set and reset

inputs—each driven by an input-only pin

• Six global clock/control networks available to the logic cell F1, clock, set and reset inputs

and the input and I/O register clock, reset and enable inputs as well as the output enable contro—each driven by an input-only or I/O pin, or any logic cell output or I/O cell feedback

High Performance Silicon

• Input + logic cell + output total delays = under 6 ns

• Data path speeds over 400 MHz

• Counter speeds over 300 MHz

• FIFO speeds over 160+ MHz

QL4016 QuickRAM Data Sheet Rev I

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QL4016 QuickRAM Data Sheet Rev I

Electrical Specifications

AC Characteristic s at VCC = 3.3 V, TA = 25°C (K = 1.00)

To calculate delays, multiply the appropriate K factor from Table 10: Operating Range by the following numbers in the tables provided.

A1 A2 A3 A4 A5 A6

QS OP B1 B2 C1

C2 MP MS

D1 D2 E1 E2 NP NS

F1 F2 F3 F4 F5 F6

QC QR

Figure 3: QuickRAM Logic Cell

Table 1: Logic Cell

Symbol Parameter

CLK

CWHI

CWLO

SET

RESET

Combinatorial Delay

Setup Time

Hold Time 0.0 0.0 0.0 0.0 0.0

Clock to Q Delay 0.7 1.0 1.2 1.5 2.5

Clock High Time 1.2 1.2 1.2 1.2 1.2

Clock Low Time 1.2 1.2 1.2 1.2 1.2

Set Delay 1.0 1.3 1.5 1.8 2.8

Reset Delay 0.8 1.1 1.3 1.6 2.6

Set Width 1.9 1.9 1.9 1.9 1.9

Reset Width 1.8 1.8 1.8 1.8 1.8

a. These limits are derived from a representative selection of the slowest paths through the Quick-

RAM logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design.

Propagation Delays (ns)

Fanout (5)

1 2 3 4 5

1.4 1.7 1.9 2.2 3.2

1.7 1.7 1.7 1.7 1.7

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QL4016 QuickRAM Data Sheet Rev I

[8:0]

[17:0]

[1:0]

Table 2: RAM Cell Synchronous Write Timing

Symbol Parameter

SWA

HWA

SWD

HWD

SWE

HWE

WCRD

WA Setup Time to WCLK 1.0 1.0 1.0 1.0 1.0

WA Hold Time to WCLK 0.0 0.0 0.0 0.0 0.0

WD Setup Time to WCLK 1.0 1.0 1.0 1.0 1.0

WD Hold Time to WCLK 0.0 0.0 0.0 0.0 0.0

WE Setup Time to WCLK 1.0 1.0 1.0 1.0 1.0

WE Hold Time to WCLK 0.0 0.0 0.0 0.0 0.0

WCLK to RD (WA=RA)

WCLK

RCLK

MODE ASYNCRD

Figure 4: QuickRAM Module

1 2 3 4 5

5.0 5.3 5.6 5.9 7.1

[8:0]

[17:0 ]

Propagation Delays (ns)

Fanout

a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and

TA = 25 settings as specified in the Operating Range.

Symbol Parameter

Logic Cells 1 2 3 4 5

SRA

HRA

SRE

HRE

RCRD

a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and

TA = 25 settings as specified in the Operating Range.

° C. Multiply by the approp riate Dela y Factor, K, f or speed gra de, voltag e and tempe rature

Table 3: RAM Cell Synchronous Read Timing

Propagation Delays (ns)

Fanout

RA Setup Time to RCLK 1.0 1.0 1.0 1.0 1.0

RA Hold Time to RCLK 0.0 0.0 0.0 0.0 0.0

RE Setup Time to RCLK 1.0 1.0 1.0 1.0 1.0

RE Hold Time to RCLK 0.0 0.0 0.0 0.0 0.0

RCLK to RD

4.0 4.3 4.6 4.9 6.1

× C. Multiply by the approp riate Delay Factor , K, for speed grade, volta ge and temperature

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QL4016 QuickRAM Data Sheet Rev I

Table 4: RAM Cell Asynchronous Read Timing

Symbol Parameter

Propagation Delays (ns)

Fanout

1 2 3 4 5

RPDRD RA to RD

3.0 3.3 3.6 3.9 5.1

a. Stated timing for worst case Propagation Delay over process variation at V

TA = 25

°C. Multiply by the appropr iate Delay Factor, K, for speed gra de, volta ge and tempe ratu re

settings as specified in the Operating Range.

Table 5: Input-Only / Clock Cells

Symbol Parameter

Propagation Delays (ns)

1 2 3 4 8 12 24

INI

ISU

ICLK

IRST

IESU

IEH

High Drive Input Delay 1.5 1.6 1.8 1.9 2.4 2.9 4.4

High Drive Input, Inverting Delay 1.6 1.7 .19 2.0 2.5 3.0 4.5

Input Register Set-Up Time 3.1 3.1 3.1 3.1 3.1 3.1 3.1

Input Register Hold Time 0.0 0.0 0.0 0.0 0.0 0.0 0.0

Input Register Clock To Q 0.7 0.8 1.0 1.1 1.6 2.1 3.6

Input Register Reset Delay 0.6 0.7 0.9 1.0 1.5 2.0 3.5

Input Register Clock Enable Setup Time 2.3 2.3 2.3 2.3 2.3 2.3 2.3

Input Register Clock Enable Hold Time 0.0 0.0 0.0 0.0 0.0 0.0 0.0

= 3.3 V and

Fanout

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Table 6: Clock Cells

Symbol Parameter

Propagation Delays (ns)

Fanout

1 2 3 4 8 10 11

ACK

GCKP

GCKB

Array Clock Delay 1.2 1.2 1.3 1.3 1.5 1.6 1.7

Global Clock Pin Delay 0.7 0.7 0.7 0.7 0.7 0.7 0.7

Global Clock Buffer Delay 0.8 0.8 0.9 0.9 1.1 1.2 1.3

a. The array dist ribu ted ne tw ork s co nsi st of 40 ha lf columns and the glo bal d is tributed networks con-

sist of 44 half columns, each driven by an independent buffer. The number of half columns used does not affect clo ck buffer delay . The arra y clock has up to eight loads per ha lf column. The global clock has up to 11 loads per half column.

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