■ Two array clock/control networks available to the
logic cell flip-flop clock, set and reset inputs - each
driven by an input-only pin
■ Up to six global clock/control networks available
to the logic cell F1, clock, set and reset inputs and
the input and I/O register clock, reset and enable
inputs as well as the output enable control - each
driven by an input-only or I/O pin, or any logic cell
output or I/O cell feedback
High Performance
■ Input + logic cell + output total delays under 6 ns
■ Data path speeds exceeding 400 MHz
■ Counter speeds over 300 MHz
Max
Package
I/O
Qualification
Level
Supply
Voltage
Rev B
8-23
P
Product Summary
Military Plastic pASIC 3 Family
RODUCT SUMMARY
The pASIC 3 FPGA family features up to 60,000
usable PLD gates. pASIC 3 FPGAs are fabricated
on a 0.35mm four-layer metal process using QuickLogic’s patented ViaLink technology to provide a
unique combination of high performance, high density, low cost, and extreme ease-of-use.
The pASIC 3 product family contains 1,584 logic
cells. With a maximum of 316 I/Os, and is available
in 208-PQFP and 84-PLCC packages.
P
INOUT DIAGRAM
Pinout Diagram 68-Pin CPGA
Software support for the complete pASIC 3 family is
available through three basic packages. The turnkey
®
QuickWorks
FPGA software solution from design entry to logic
synthesis, to place and route, to simulation. The
QuickWorks
vide a solution for designers who use Cadence,
Exemplar, Mentor, Synopsys, Synplicity, Viewlogic,
Veribest, or other third-party tools for design entry,
synthesis, or simulation.
VIHInput HIGH Voltage0.5VCC VCCIO+0.5 V
VILInput LOW Voltage-0.50.3VCCV
VOHOutput HIGH VoltageIOH = -12 mA2.4V
IOH = -500 µA
VOLOutput LOW VoltageIOL = 8 mA [1]0.45V
IOL = 1.5 mA0.1VCCV
III or I/O Input Leakage CurrentVI = VCCIO or GND-1010
IOZ3-State Output Leakage Current VI = VCCIO or GND-1010
CIInput Capacitance [2]10pF
IOSOutput Short Circuit Current [3]VO = GND-15-180mA
VO = VCC40210mA
ICCD.C. Supply Current [4]VI, VIO = VCCIO or GND 0.50 (typ)5mA
ICCIOD.C. Supply Current on VCCIO0100
0.9VCCV
°C
°C
°C
µA
µA
µA
Notes:
[1] Military devices have 8 mA IOL specifications.
[2] Capacitance is sample tested only. Clock pins are 12 pF maximum.
[3] Only one output at a time. Duration should not exceed 30 seconds.
[4] Maximum ICC is 5 mA for all military grade devices. For AC conditions, contact QuickLogic
customer engineering.
8-27
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