QUICK LOGIC QL3012-1PF100C, QL3012-1PF100I, QL3012-1PF100M, QL3012-1PF144C, QL3012-1PF144I Datasheet

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Device Highlights

High Performance & High Density

• 12,000 Usable PLD Gates with 118 I/Os

• 300 MHz 16-bit Counters,

400 MHz Datapaths

• 0.35 µm four-layer metal non-volatile

CMOS process for smallest die sizes

Easy to Use / Fast Development Cycles

• 100% routable with 100% utilization and

complete pin-out stability

• Variable-grain logic cells provide high

performance and 100% utilization

• Comprehensive design tools include high

quality Verilog/VHDL synthesis

Advanced I/O Capabilities

• Interfaces with both 3.3 V and 5.0 V devices

• PCI compliant with 3.3 V and 5.0 V buses

for -1/-2/-3/-4 speed grades

• Full JTAG boundary scan

• I/O Cells with individually controlled

Registered Input Path and Output Enables

Total of 118 I/O Pins

• 110 bidirectional input/output pins,

PCI-compliant for 5.0 V and 3.3 V buses for

-1/-2/-3/-4 speed grades

• Four High Drive input-only pins

• Four High Drive input-only/distributed

network pins

Four Low-Skew Distributed Networks

• Two array clock/control networks available

to the logic cell flip-flop clock, set and reset inputs — each driven by an input-only pin

• Two global clock/control networks available

to the logic cell; F1, clock set, reset inputs and the input, I/O register clock, reset, and enable inputs as well as the output enable control — each driven by an input-only or I/O pin, or any logic cell output or I/O cell feedback

High Performance

• Input + logic cell + output total delays

under 6 ns

• Data path speeds over 400 MHz

• Counter speeds over 300 MHz

Figure 1: 320 pASIC 3 Logic Cells

QL3012 pASIC 3 FPGA Data Sheet

12,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density

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QL3012 pASIC 3 FPGA Data Sheet Rev E

Architecture Overview

The QL3012 is a 12,000 usable PLD gate member of the pASIC 3 family of FPGAs. pASIC 3 FPGAs are fabricated on a 0.35 µm four-layer metal process using QuickLogic



's patented

ViaLink



technology to provide a unique combination of high performance, high density,

low cost, and extreme ease-of-use.

The QL3012 contains 320 logic cells. With a maximum of 118 I/Os, the QL3012 is available in 84-pin PLCC, 100-pin TQFP, and 144-pin TQFP packages.

Software support for the complete pASIC 3 family, including the QL3012, is available through three basic packages. The turnkey QuickWork s



package provides the most complete FPGA software solution from design entry to logic synthesis, to place and route, to simulation. The QuickTools

for Workstations package provides a solution for designers

who use Cadence



, ExemplarTM, Mentor, Synopsys, Synplicity, ViewlogicTM, AldecTM,

or other third-party tools for design entry, synthesis, or simulation.

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QL3012 pASIC 3 FPGA Data Sheet Rev E

Electrical Specifications

AC Characteristics at VCC = 3.3 V, TA = 25°C (K = 1.00)

To calculate delays, multiply the appropriate K factor from Table 7 by the numbers provided in

Table 1 through Table 5.

Table 1: Logic Cells

Symbol Parameter Propagation Delays (ns) Fanout

a. Stated timing for worst case Propagation Delay over process variation at V

= 3.3 V and TA = 25°C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and temperature settings as specified in

Table 7.

1 2 3 4 8

Combinatorial Delay

b. These limits are derived from a representative selection of the slowest paths through the pASIC

3 logic cell including typical net delays. Worst case delay values for sp ecific paths should be determined from timing analysis of your particular design.

1.4 1.7 1.9 2.2 3.2

Setup Time

1.7 1.7 1.7 1.7 1.7

Hold Time 0.0 0.0 0.0 0.0 0.0

CLK

Clock to Q Delay 0.7 1.0 1.2 1.5 2.5

CWHI

Clock High Time 1.2 1.2 1.2 1.2 1.2

CWLO

Clock Low Time 1.2 1.2 1.2 1.2 1.2

SET

Set Delay 1.0 1.3 1.5 1.8 2.8

RESET

Reset Delay 0.8 1.1 1.3 1.6 2.6

Set Width 1.9 1.9 1.9 1.9 1.9

Reset Width 1.8 1.8 1.8 1.8 1.8

Table 2: Input-Only/Clock Cells

Symbol Parameter Propagation Delays (ns) F a no ut

a. Stated timing for worst case Propagation Delay over process variation at V

= 3.3 V and TA = 25

°C. Multiply by the appropriate Delay Factor, K, for speed grade, voltag e, and tempera-

ture settings as specified in

Table 7.

1 2 3 4 8 12 24

High Drive Input Delay 1.5 1.6 1.8 1.9 2.4 2.9 4.4

INI

High Drive Input, Inverting Delay 1.6 1.7 1.9 2.0 2.5 3.0 4.5

ISU

Input Register Set-Up Time 3.1 3.1 3.1 3.1 3.1 3.1 3.1

Input Register Hold Time 0.0 0.0 0.0 0.0 0.0 0.0 0.0

lCLK

Input Register Clock To Q 0.7 0.8 1.0 1.1 1.6 2.1 3.6

lRST

Input Register Reset Delay 0.6 0.7 0.9 1.0 1.5 2.0 3.5

lESU

Input Register clock Enable Set-Up Time 2.3 2.3 2.3 2.3 2.3 2.3 2.3

lEH

Input Register Clock Enable Hold Time 0.0 0.0 0.0 0.0 0.0 0.0 0.0

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QL3012 pASIC 3 FPGA Data Sheet Rev E

Table 3: Clock Cells

Symbol Parameter Propagation Delays (ns) Loads per Half Column

a. The array distributed networks consist of 40 half columns and the global distributed networks con-

sist of 44 half columns, each driven by an independent buffer. The number of half columns used does not affect clock buffer delay. The array clock has up to eight loads per half column. The global clock has up to 11 loads per half column.

1 2 3 4 8 10 11

ACK

Array Clock Delay 1.2 1.2 1.3 1.3 1.5 1.6 1.7

GCKP

Global Clock Pin Delay 0.7 0.7 0.7 0.7 0.7 0.7 0.7

GCKB

Global Clock Buffer Delay 0.8 0.8 0.9 0.9 1.1 1.2 1.3

Table 4: Input-Only I/O Cells

Symbol Parameter Propagation Delays (ns) Fanout

a. Stated timing for worst case Propagation Delay over process variation at V

= 3.3 V and TA = 25°C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage, and temperature settings as specified in Table 7.

1 2 3 4 8 10

I/O

Input Delay (bidirectional pad) 1.3 1.6 1.8 2.1 3.1 3.6

ISU

Input Register Set-Up Time 3.1 3.1 3.1 3.1 3.1 3.1

Input Register Hold Time 0.0 0.0 0.0 0.0 0.0 0.0

lOCLK

Input Register Clock To Q 0.7 1.0 1.2 1.5 2.5 3.0

lORST

Input Register Reset Delay 0.6 0.9 1.1 1.4 2.4 2.9

lESU

Input Register clock Enable Set-Up Time 2.3 2.3 2.3 2.3 2.3 2.3

lEH

Input Register Clock Enable Hold Time 0.0 0.0 0.0 0.0 0.0 0.0

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QL3012 pASIC 3 FPGA Data Sheet Rev E

Figure 2: Loads used for t

PXZ

Table 5: Output-Only I/O Cells

Symbol Parameter

Propagation Delays (ns) Output Load

Capacitance (pF)

30 50 75 100 150

OUTLH

Output Delay Low to High 2.1 2.5 3.1 3.6 4.7

OUTHL

Output Delay High to Low 2.2 2.6 3.2 3.7 4.8

PZH

Output Delay Tri-state to High 1.2 1.7 2.2 2.8 3.9

PZL

Output Delay Tri-state to Low 1.6 2.0 2.6 3.1 4.2

PHZ

Output Delay High to Tri-State

a. The loads presented in Figure 2 are used for t

PXZ

2.0 - - - -

PLZ

Output Delay Low to Tri-State 1.2 - - - -

1ΚΩ

PHZ

PLZ

5 pF

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