Quatech QS-200M, QS-300M Owner's Manual

WARRANTY INFORMATION

Qua Tech Inc. warrants the QS-200M/QS-300M be free of defects for one purchase. Qua Tech Inc. will repair or replace any board that fails to perform under normal operating conditions and in accordance with the procedures outlined in this document during the warranty period. Any damage that results from improper installation, operation, or general misuse voids all warranty rights.

Although every attempt has been made to guarantee the accuracy of this manual, Qua Tech Inc. assumes no liability for damages resulting from errors in this document. Qua Tech Inc. reserves the right to edit or append to this document at any time without notice.

Please complete the following information and retain for your records. Have this information available when requesting warranty service.

DATE OF PURCHASE:

MODEL NUMBER: QS-200M/QS-300M

PRODUCT DESCRIPTION: FOUR ASYNC.

(1) year from the date of

CHANNEL RS-422/RS-485

COMMUNICATIONS ADAPTER

to

SERIAL NUMBER:

IBM PCTM, PC/XTTM, and PC/ATTM are trademarks of International Business Machines.

i

TABLE OF CONTENTS

WARRANTY INFORMATION . . . . . . . . . . . . i

LIST OF FIGURES . . . . . . . . . . . . . iii

I. INTRODUCTION . . . . . . . . . . . . . . . . 1

II. BOARD DESCRIPTION . . . . . . . . . . . . . 1

III. 16450/16550

A. INTERRUPT ENABLE REGISTER . . . . . . . . 4

B. INTERRUPT IDENTIFICATION REGISTER . . . . 5

C. FIFO CONTROL REGISTER

D. LINE CONTROL REGISTER . . . . . . . . . . 8

E. MODEM CONTROL REGISTER . . . . . . . . . 10

F. LINE STATUS REGISTER . . . . . . . . . . 11

G. MODEM STATUS REGISTER . . . . . . . . . . 13

H. SCRATCHPAD REGISTER . . . . . . . . . . . 14

IV. FIFO INTERRUPT MODE OPERATION

V. BAUD RATE SELECTION . . . . . . . . . . . . 14

VI. ADDRESSING . . . . . . . . . . . . . . . . . 16

VII. INTERRUPTS . . . . . . . . . . . . . . . . . 18

INTERRUPT STATUS REGISTER . . . . . . . . 19

VIII. OUTPUT CONFIGURATIONS . . . . . . . . . . . 20

IX. EXTERNAL CONNECTIONS . . . . . . . . . . . . 21

*

FUNCTIONAL DESCRIPTION . . . . 1

*

. . . . . . . . . . 7

*

. . . . . . . 14

X. INSTALLATION . . . . . . . . . . . . . . . . 22

XI. SPECIFICATIONS . . . . . . . . . . . . . . . 22

*

For optional 16550 only.

i

INTRODUCTION

LIST OF FIGURES

Figure 1. QS-200M/QS-300M board layout . . . . . 2

Figure 2. 16450/16550 internal registers . . . . 3

Figure 3. Interrupt enable register . . . . . . 4

Figure 4. Interrupt identification register . . 5

Figure 5. Interrupt source identification . . . 6

Figure 6. FIFO control register

Figure 7. FIFO receiver trigger levels

Figure 8. Line control register . . . . . . . . 8

Figure 9. Parity options . . . . . . . . . . . . 9

Figure 10. Word length and stop bit options . . . 9

Figure 11. MODEM control register . . . . . . . . 10

Figure 12. Line status register . . . . . . . . . 11

Figure 13. MODEM status register . . . . . . . . 13

Figure 14. Clock options . . . . . . . . . . . . 15

Figure 15. Divisor latch options . . . . . . . . 15

Figure 16. Address selection switches . . . . . . 16

Figure 17. Address selection examples . . . . . . 17

*

. . . . . . . . 7

*

. . . . . 7

Figure 18. Interrupt selection jumper . . . . . . 18

Figure 19. Interrupt status register selection . 19

Figure 20. Interrupt status register definition . 19

Figure 21. Half duplex configuration jumpers . . 20

Figure 22. Output connectors . . . . . . . . . . 21

*

For optional 16550 only.

iii

INTRODUCTION

I. INTRODUCTION

The QS-200M is a four channel RS-422 asynchronous serial communication adapter. The QS-300M is an RS-485 version of the adapter. Both are designed to be hardware compatible with the IBM PC/XT/AT personal computers. Data is communicated through four shielded RJ-11 "modular" phone jack connectors which provide shielding from environmental noise.

The serial interface is accomplished through four 16450 Asynchronous Communication Elements (ACEs). The 16450 is an improved specification version of the 8250 ACEs used in the IBM PC/XT models. Optional 16550 ACEs are available to reduce CPU overhead at higher data rates when used with software supporting this feature.

Addressing for the adapter is selected by a pair of six position switches. These switches allow a full range of address choices between 0 and FFFF hex. The QS200M/QS-300M has the option of selecting one of six possible Interrupt Request lines (IRQ 2 - IRQ 7). A hardware selectable clock divider is also available for producing unusual baud rates.

II. BOARD

DESCRIPTION

A component diagram of the QS-200M/QS-300M is shown in figure 1. The base address is controlled by the address selection switches SW1 & SW2. The interrupt level for the adapter is selected using jumper J3. Channels 1 - 4 are controlled by the 16450 ACEs labeled U5 - U8 and are output through connectors CON1 - CON4 respectively.

III. 16450/16550

FUNCTIONAL DESCRIPTION

The 16450 is an improved specification version of the 8250 Asynchronous Communications Element (ACE). Functionally, the 16450 is equivalent to the 8250. The ACE performs serial-to-parallel conversion on received data and parallel-to-serial conversion on data output from the CPU.

iii

BOARD DESCRIPTION

Figure 1. QS-200M/QS-300M board layout.

FUNCTIONAL DESCRIPTION

Designed to be compatible with the 16450, the 16550 ACE enters character mode on reset and in this mode appears as a 16450 to user software. An additional mode, FIFO mode, can be invoked through software to reduce CPU overhead. The FIFO mode increases performance by providing two 16-byte FIFOs (one transmit and one receive) to buffer data and reduce the number of interrupts issued to the CPU.

Other features of the 16450/16550 include: Programmable baud rate, character length, parity, and number of stop bits. Automatic addition and removal of start, stop, and parity bits. Independent and prioritized transmit, receive and status interrupts. Transmitter clock output to drive receive logic. External receiver clock input.

The following pages provide a brief summary of the internal registers available within the 16450 and 16550 ACEs. The registers are addressed as shown in figure 2 below. Registers and functions specific to the 16550 will be marked with an asterisk(*).

*

| | x 0 1 1 | Line control | | x 1 0 0 | MODEM control | | x 1 0 1 | Line status | | x 1 1 0 | MODEM status | | x 1 1 1 | Scratch | | 1 0 0 0 | Divisor latch (LSB) | | 1 0 0 1 | Divisor latch (MSB) | +---------------+-----------------------------------+

Figure 2. Internal Register map for 16450/16550 ACE. DLAB is accessed through the Line Control Register.

*

For optional 16550 only.

FUNCTIONAL DESCRIPTION

IIIA. INTERRUPT

ENABLE REGISTER

+-------+ D7 | 0 | +-------+ D6 | 0 | +-------+ D5 | 0 | +-------+ D4 | 0 | +-------+ D3 | EDSSI |----- MODEM status +-------+ D2 | ELSI |----- Receiver line status +-------+ D1 | ETBEI |----- Transmit holding register empty +-------+ D0 | ERBFI |----- Received data available +-------+

Figure 3. Interrupt Enable Register bit definitions.

EDSSI - MODEM Status Interrupt:

When set (logic 1), enables interrupt on clear to send, data set ready, ring indicator, and data carrier detect.

ELSI - Receiver Line Status Interrupt:

When set (logic 1), enables interrupt on overrun, parity, framing errors, and break indication.

ETBEI - Transmitter Holding Register Empty Interrupt:

When set (logic 1), enables interrupt on transmitter register empty.

ERBFI - Received Data Available Interrupt:

When set (logic 1), enables interrupt on received data available or FIFO trigger level.

FUNCTIONAL DESCRIPTION

IIIB. INTERRUPT

IDENTIFICATION REGISTER

+------+ D7 | FFE |----- FIFO enable (FIFO only)

*

+------+ D6 | 0 | +------+ D5 | 0 | +------+ D4 | 0 | +------+ D3 | IID2 |--+ +------+ | D2 | IID1 | +-- Interrupt identification +------+ | D1 | IID0 |--+ +------+ D0 | IP |----- Interrupt pending +------+

Figure 4. Interrupt Identification Register bit

definitions.

FFE - FIFO Enable:

*

When logic 1, indicates FIFO mode enabled.

IIDx - Interrupt Identification:

Indicates highest priority interrupt pending if any. See IP and figure 5. NOTE: IID2 is always a logic 0 in character mode.

IP - Interrupt Pending:

When logic 0, indicates that an interrupt is pending and the contents of the interrupt identification register may be used to determine the interrupt source. See IIDx and figure 5.

*

For optional 16550 only

FUNCTIONAL DESCRIPTION

*

Figure 5. Interrupt Identification bit definitions.

Receiver Line Status:

Indicates overrun, parity, framing errors or break interrupts. The interrupt is cleared by reading the line status register.

|

Received Data Ready:

Indicates receive data available. The interrupt is cleared by reading the receive buffer.

FIFO mode:* Indicates the receiver FIFO trigger level

has been reached. The interrupt is reset when the FIFO drops below the the trigger level.

Character Timeout:

*

(FIFO mode only) Indicates no characters have been removed from or input to the receiver FIFO for the last four character times and there is data present in the receiver FIFO. The interrupt is cleared by reading the receiver FIFO.

Transmitter Holding Register Empty:

Indicates the transmitter holding register is empty. The interrupt is cleared by reading the interrupt identification register or writing to the transmitter holding register.

MODEM Status:

Indicates clear to send, data set ready, ring indicator, or data carrier detect have changed state. The interrupt is cleared by reading the MODEM status register.

*

For optional 16550 only.

FUNCTION AL DESCRIPTION

IIIC. FIFO CONTROL REGISTER

*

+------+ D7 | RXT1 |--+ +------+ +-- Receiver trigger

*

D6 | RXT0 |--+ +------+ D5 | x |--+ +------+ +-- Reserved D4 | x |--+ +------+ D3 | DMAM |----- DMA mode select

*

*

+------+

Figure 6. FIFO Control Register bit definitions.

RXTx - Receiver FIFO Trigger Level:

*

Determines the trigger level for the receiver FIFO interrupt as given in figure 7 below.

*

+-----------+-----------------------+ | | RCVR FIFO | | RXT1 RXT0 | Trigger level (bytes) | +-----------+-----------------------+ | 0 0 | 1 | | 0 1 | 4 | | 1 0 | 8 | | 1 1 | 14 | +-----------+-----------------------+

Figure 7. FIFO Trigger Levels.

DMAM - DMA Mode Select:

*

When set (logic 1), RxRDY and TxRDY change from mode 0 to mode 1 for DMA transfers. (DMA mode not supported on QS-200M/QS-300M.)

XRST - Transmit FIFO Reset:

*

When set (logic 1), all bytes in the transmitter FIFO are cleared and the counter is reset. The shift register is not cleared. XRST is selfclearing.

*

For optional 16550 only.

FUNCTIONAL DESCRIPTION

RRST - Receive FIFO Reset:

*

When set (logic 1), all bytes in the receiver FIFO are cleared and the counter is reset. The shift register is not cleared. RRST is selfclearing.

FE - FIFO Enable:

* When set (logic 1), enables transmitter and

receiver FIFOs. When cleared (logic 0), all bytes in both FIFOs are cleared. This bit must be set when other bits in the FIFO control register are written to or the bits will be ignored.

IIID. LINE

CONTROL REGISTER

+------+ D7 | DLAB |----- Divisor latch access bit +------+ D6 | BKCN |----- Break control +------+ D5 | STKP |----- Stick parity +------+ D4 | EPS |----- Even parity select +------+ D3 | PEN |----- Parity enable +------+ D2 | STB |----- Number of stop bits +------+ D1 | WLS1 |--+ +------+ +-- Word length select D0 | WLS0 |--+ +------+

Figure 8. Line Control Register bit definitions.

DLAB - Divisor Latch Access Bit:

DLAB must be set to logic 1 to access the baud rate divisor latches. DLAB must be set to logic 0 to access the receiver buffer, transmitting holding register and interrupt enable register.

BKCN - Break Control:

When set (logic 1), the serial output (SOUT) is forced to the spacing state (logic 0).

*

For optional 16550 only.

F UNCTIONAL DESCRIPTION

STKP - Stick Parity:

Forces parity to logic 1 or logic 0 if parity is enabled. See EPS, PEN, and figure 9.

EPS - Even Parity Select:

Selects even or odd parity if parity is enabled. See STKP, PEN, and figure 9.

PEN - Parity Enable:

Enables parity on transmission and verification on reception. See EPS, STKP, and figure 9.

+--------------+---------+ | STKP EPS PEN | Parity | +--------------+---------+ | x x 0 | None | | 0 0 1 | Odd | | 0 1 1 | Even | | 1 0 1 | Logic 1 | | 1 1 1 | Logic 0 | +--------------+---------+

Figure 9. 16450 Parity Selections.

STB - Number of Stop Bits:

Sets the number of stop bits transmitted. See WLSx and figure 10.

WLSx - Word Length Select:

Determines the number of bits per transmitted word. See STB and figure 10.

+---------------+-------------+-----------+ | STB WLS1 WLS0 | Word length | Stop bits | +---------------+-------------+-----------+ | 0 0 0 | 5 bits | 1 | | 0 0 1 | 6 bits | 1 | | 0 1 0 | 7 bits | 1 | | 0 1 1 | 8 bits | 1 | | 1 0 0 | 5 bits | 1½ | | 1 0 1 | 6 bits | 2 | | 1 1 0 | 7 bits | 2 | | 1 1 1 | 8 bits | 2 | +---------------+-------------+-----------+

Figure 10. Word Length and Stop Bit selections.

FUNCTIONAL DESCRIPTION

IIIE. MODEM

CONTROL REGISTER

+------+ D7 | 0 | +------+ D6 | 0 | +------+ D5 | 0 | +------+ D4 | LOOP |----- Loopback enable +------+ D3 | OUT2 |----- Output 2 +------+ D2 | OUT1 |----- Output 1 +------+ D1 | RTS |----- Request to send +------+ D0 | DTR |----- Data terminal ready +------+

Figure 11. MODEM Control Register bit definitions.

LOOP - Loopback Enable:

When set (logic 1), the transmitter shift register is connected directly to the receiver shift register. The MODEM control inputs are internally connected to the MODEM control outputs and the outputs are forced to the inactive state. All characters transmitted are immediately received to verify transmit and receive data paths. Transmitter and receiver interrupts still operate normally. MODEM control interrupts are available but are now controlled through the MODEM control register.

Bits OUT2, OUT1, RTS, and DTR perform identical functions on their respective outputs. When these bits are set (logic 1) in the register, the associated output is forced to a logic 0. When cleared (logic 0), the output is forced to a logic1.

OUT2 - Output 2:

Controls the OUT2 output as described above.

OUT1 - Output 1:

Controls the OUT1 output as described above.

RTS - Request To Send:

Controls the RTS output as described above.

DTR - Data Terminal Ready:

Controls the DTR output as described above. Used for transmitter enable (see section VIII).

FUNCTIONAL DESCRIPTION

IIIF. LINE

STATUS REGISTER

Figure 12. Line Status register bit definitions.

FFRX - FIFO Receiver Error:

*

Always logic 0 in character mode.

FIFO mode:

*

Indicates one or more parity errors, framing errors, or break indications in the receiver FIFO. FFRX is reset by reading the line status register.

*

TEMT - Transmitter Empty:

Indicates the transmitter holding register (or FIFO*) and the transmitter shift register are empty and are ready to receive new data. TEMT is reset by writing a character to the transmitter holding register.

THRE - Transmitter Holding Register Empty:

Indicates the transmitter holding register (or FIFO*) is empty and it is ready to accept new data. THRE is reset by writing data to the transmitter holding register.

*

For optional 16550 only.

FUNCTIONAL DESCRIPTION

Bits BI, FE, PE, and OE are the sources of receiver line status interrupts. The bits are reset by reading the line status register. In FIFO mode*, these bits are associated with a specific character in the FIFO and the exception is revealed only when that character reaches the top of the FIFO.

BI - Break Interrupt:

Indicates the receive data input has been in the spacing state (logic 0) for longer than one full word transmission time.

FIFO mode:

*

Only one zero character is loaded into the FIFO and transfers are disabled until SIN goes to the mark state (logic 1) and a valid start bit is received.

FE - Framing Error:

Indicates the received character had an invalid stop bit. The stop bit following the last data or parity bit was a 0 bit (spacing level).

PE - Parity Error:

Indicates that the received data does not have the correct parity.

OE - Overrun Error:

Indicates the receive buffer was not read before the next character was received and the character is destroyed.

FIFO mode:

*

Indicates the FIFO is full and another character has been shifted in. The character in the shift register is destroyed but is not transferred to the FIFO.

DR - Data ready:

Indicates data is present in the receive buffer or FIFO. DR is reset by reading the receive buffer register or receiver FIFO.

*

For optional 16550 only.

FUNCTIONAL DESCRIPTION

IIIG. MODEM STATUS REGISTER

Figure 13. MODEM Status register bit definitions.

DCD - Data Carrier Detect:

Complement of the DCD input.

RI - Ring Indicator:

Complement of the RI input.

DSR - Data Set Ready:

Complement of the DSR input.

CTS - Clear To Send:

Complement of the CTS input.

Bits DDCD, TERI, DDSR, and DCTS are the sources of MODEM status interrupts. These bits are reset when the MODEM status register is read.

DDCD - Delta Data Carrier Detect:

Indicates the Data Carrier Detect input has changed state.

TERI - Trailing Edge Ring Indicator:

Indicates the Ring Indicator input has changed from a low to a high state.

DDSR - Delta Data Set Ready:

Indicates the Data Set Ready input has changed state.

DCTS - Delta Clear To Send:

Indicates the Clear to Send input has changed state.

FUNCTIONAL DESCRIPTION

IIIH. SCRATCHPAD REGISTER

This register is not used by the 16450/16550. It may be used by the programmer for data storage.

IV. FIFO

INTERRUPT MODE OPERATION

*

1. The receive data interrupt is issued when the FIFO reaches the trigger level. The interrupt is cleared as soon as the FIFO falls below the trigger level.

2. The interrupt identification register's receive data available indicator is set and cleared along with the receive data interrupt above.

3. The data ready indicator is set as soon as a character is transferred into the receiver FIFO and is cleared when the FIFO is empty.

V. BAUD

RATE SELECTION

The 16450 ACE determines the baud rate of the serial output and uses a combination of the clock input frequency and the value written to the divisor latches. Standard PC, PC/XT, PC/AT, and PS/2 serial interfaces use an input clock of 1.8432 MHz. To increase versatility, the QS-200M/QS-300M uses an 18.432 MHz crystal and a frequency divider circuit to produce the standard clock frequency.

Jumper block J1 is used to set the frequency input to the 16450. It may be connected to divide the clock input by 1, 2, 5, or 10. For compatibility as stated above, J1 should be configured to divide by 10 as shown in figure 14(d). A table of baud rates available using the 1.8432 MHz input is given in figure 14.

*

For optional 16550 only.

BAUD RATE SELECTION

J1 J1 +-----------+ +-----------+ 4| _ _+ _ |6 4| _ _--_ |6 1| _ _+ _ |3 1| _--_ _ |3 +-----------+ +-----------+ (a) ÷1 input clock (b) ÷2 input clock

J1 J1 +-----------+ +-----------+ 4| _--_ _ |6 4| _+ _--_ |6 1| _ _--_ |3 1| _+ _--_ |3 +-----------+ +-----------+ (c) ÷5 input clock (d) ÷10 input clock

Figure 14. Input Clock Frequency Options. For

compatibility, the jumper should be set at ÷10 ( 18.432 MHz ÷ 10 = 1.8432 MHz ).

+-----------+-------------+-----------------------+ | Desired | Divisor | Error Between Desired | | Baud Rate | Latch Value | and Actual Value (%) | +-----------+-------------+-----------------------+ | 50 | 2304 | - | | 75 | 1536 | - | | 110 | 1047 | 0.026 | | 150 | 768 | - | | 300 | 384 | - | | 600 | 192 | - | | 1200 | 96 | - | | 1800 | 64 | - | | 2000 | 58 | 0.69 | | 2400 | 48 | - | | 3600 | 32 | - | | 4800 | 24 | - | | 7200 | 16 | - | | 9600 | 12 | - | | 19200 | 6 | - | | 38400 | 3 | - | | 56000 | 2 | 2.86 | +-----------+-------------+-----------------------+

Figure 15. Divisor latch settings for common baud

rates using an 1.8432 MHz input clock. For compatibility, connect jumper in the divide by 10 configuration (figure 14(d)).

BAUD RATE SELECTION

VI. ADDRESSING

The QS-200M/QS-300M uses 8 I/O address locations per channel. Full sixteen bit address decoding allows base address selections in the range 0000 - FFFF Hex. Two six position switches, SW1 & SW2 are used to specify the base address of the adapter. SW1 controls the address setting for A15-A10 through positions 1-6 respectively. Switch SW2, positions 1-5 control address selections for A9-A5. The remaining address inputs are used by the adapter to determine the channel and register being accessed.

A switch in the "ON" position indicates that the corresponding address bit be a logic 0 for selection. A switch in the "OFF" position forces the corresponding address bit to be a logic 1 for selection. Some example switch settings for the QS-200M/QS-300M are shown in figures 16 and 17.

The base address of each channel is incremented by a factor of 8 from the base address of the adapter. Therefore 32 address locations are used by the QS-200M/ QS-300M.

PORT

ADDRESS RANGE

1 Base Address+0 - Base Address+7 2 Base Address+8 - Base Address+15 3 Base Address+16 - Base Address+23 4 Base Address+24 - Base Address+31

+--------------------+ +--------------------+ | 1 2 3 4 5 6 | | 1 2 3 4 5 6 | On| +-++-++-++-++-++-+ | On| +-++-++-++-++-++-+ | | |_||_||_||_||_||_| | | | || ||_||_||_|| | | | | || || || || || | | | |_||_|| || || || | | Off| +-++-++-++-++-++-+ | Off| +-++-++-++-++-++-+ | +--------------------+ +--------------------+ SW1 SW2

Figure 16. Factory address switch settings. Address shown is 0300H.

ADDRESSING

BASE ADDRESS = 0300H

1 2 3 4 5 6 1 2 3 4 5 6 On +-++-++-++-+ +-++-++-++-+ +-++-++-+ +-+ |_||_||_||_| |_||_|| || | |_||_||_| | | | || || || | | || ||_||_| | || || | | | Off +-++-++-++-+ +-++-++-++-+ +-++-++-+ +-+ 0 0 0 0 0 0 2 1 0 0 0 0 3 0 0 = 0300H

BASE ADDRESS = 06A0H

1 2 3 4 5 6 1 2 3 4 5 6 On +-++-++-++-+ +-++-++-++-+ +-++-++-+ +-+ |_||_||_||_| |_|| || ||_| | ||_|| | | | | || || || | | ||_||_|| | |_|| ||_| | | Off +-++-++-++-+ +-++-++-++-+ +-++-++-+ +-+ 0 0 0 0 0 4 2 0 8 0 2 0 6 A 0 = 06A0H

BASE ADDRESS = 5220H

1 2 3 4 5 6 1 2 3 4 5 6 On +-++-++-++-+ +-++-++-++-+ +-++-++-+ +-+ |_|| ||_|| | |_||_|| ||_| |_||_|| | | | | ||_|| ||_| | || ||_|| | | || ||_| | | Off +-++-++-++-+ +-++-++-++-+ +-++-++-+ +-+ 0 4 0 1 0 0 2 0 0 0 2 5 2 2 0 = 5220H

Figure 17. Address switch selection examples.

INTERRUPTS

VII. INTERRUPTS

The QS-200M/QS-300M is capable of supporting six interrupt levels, IRQ 2-7. All of the channels share the same interrupt. The selection of interrupt levels can be changed through a hardware jumper, J3, as shown below:

Source + | | 1 7 +--_ _-- IRQ 2(9) | _ _-- IRQ 3 | _ _-- IRQ 4 J3 | _ _-- IRQ 5 | _ _-- IRQ 6 | _ _-- IRQ 7 6 12

Figure 18. Interrupt level selection jumper.

The QS-200M/QS-300M is also equipped with an interrupt sharing circuit. This circuit allows the QS200M/QS-300M to share its interrupt with other Qua Tech adapters supporting this feature.

INTERRUPTS

INTERRUPT STATUS REGISTER

An interrupt status register is implemented on the QS-200M/QS-300M to reduce the interrupt servicing overhead associated with multi-port communications. Scratchpad / Interrupt Status register selection is controlled by position 6 on SW2. When position 6 is in the OFF position, there is no Interrupt Status register, and all of the 16450/16550s behave normally. When position 6 is in the ON position, the Interrupt Status register overrides the ACEs internal Scratchpad register. In this mode, an input from the Scratchpad register address (BASE ADDRESS + 7) of any channel will return the interrupt status of the entire card.

SW2 +---------------------------+ | 1 2 3 4 5 6 | |ON +-+ +-+ +-+ +-+ +-+ +-+ |Interrupt Status | | | | | | | | | | | |_| | | | | | | | | | | | | | | | | +-+ +-+ +-+ +-+ +-+ +-+ |Scratchpad +---------------------------+

Figure 19. Scratchpad/Interrupt Status select.

+------+ D7 | 0 | +------+ D6 | 0 | +------+ D5 | 0 | +------+ D4 | 0 | +------+ D3 | IP4 | +------+ D4 | IP3 | +------+ D1 | IP2 | +------+ D0 | IP1 | +------+

Figure 20. Interrupt Status register for the QS-200M/QS-300M. IPx set (logic 1), indicates an interrupt is pending on the associated channel.

OUTPUT CONFIGURATIONS

VIII. OUTPUT

CONFIGURATIONS

The function of jumper J2 is to configure the communication channels in half or full duplex mode. Half duplex operation is achieved by installing a jumper block over the pins for the specific channel (figure 21). This connection allows the transmitter to be enabled and disabled using the data terminal ready (DTR) output which is controlled through the modem control register of the 16450/16550. When DTR is set (logic 1), the transmitter driver is enabled for output on the channel. When cleared, (logic 0), the transmitter output enters a high impedance state. Full duplex operation is restored by removing the associated jumper.

CAUTION: When operating in half duplex mode, the

transmitter must be disabled before receiving any information. Failure to do so may result in multiple output drivers being connected together which may cause damage to the QS200M/QS-300M, the computer and the peripheral equipment.

+---------- Output enable 1 | +------- Output enable 2 | | +---- Output enable 3 | | | +- Output enable 4 +--------------+ 5 | _ _ _ _ | 8 1 | _ _ _ _ | 4

J2

+--------------+ DTR 1 -+ | | | DTR 2 ----+ | | DTR 3 -------+ | DTR 4 ----------+

Figure 21. Half duplex jumper configuration.

EXTERNAL CONNECTIONS

IX. EXTERNAL

CONNECTIONS

Figure 22. Output Connectors.

INSTALLATION

X. INSTALLATION

1. Set base address switches and interrupt and output configuration jumpers on the card.

2. Turn unit off.

3. Remove system cover as instructed in the computer reference guide.

4. Insert card into a vacant slot following the guidelines for installation.

5. Replace system cover.

XI. SPECIFICATIONS

Bus interface: IBM 8-bit bus (PC/XT) Dimensions: 8.25" x 3.9"

Controllers: 4 - 16450 Asynchronous Communication Elements Transmit drivers: MC3487 or compatible Receive buffers: MC3486 or compatible RS-422 interface: 4 - RJ-11 shielded connectors I/O Address range: 0000-FFFFH (See section VI) Interrupt levels: IRQ 2(9),3-7

Power requirements: +--------+--------+-----------+ | IT | I

| Supply |

MS

+--------+--------+-----------+ | 501mA | 576mA | +5 Volts | +--------+--------+-----------+ | -- | -- | +12 Volts | +--------+--------+-----------+ | -- | -- | -12 Volts | +--------+--------+-----------+ IT - Typical adapter current I

- Maximum statistical adapter current

MS

Quatech QS-200M, QS-300M Owner's Manual

Specifications and Main Features

Frequently Asked Questions

User Manual