Quatech QS-200M, QS-300M Owner's Manual

WARRANTY INFORMATION

Qua Tech Inc. warrants the QS-200M/QS-300M be free of defects for one purchase. Qua Tech Inc. will repair or replace any board that fails to perform under normal operating conditions and in accordance with the procedures outlined in this document during the warranty period. Any damage that results from improper installation, operation, or general misuse voids all warranty rights.

Although every attempt has been made to guarantee the accuracy of this manual, Qua Tech Inc. assumes no liability for damages resulting from errors in this document. Qua Tech Inc. reserves the right to edit or append to this document at any time without notice.

Please complete the following information and retain for your records. Have this information available when requesting warranty service.

DATE OF PURCHASE:

MODEL NUMBER: QS-200M/QS-300M

PRODUCT DESCRIPTION: FOUR ASYNC.

(1) year from the date of

CHANNEL RS-422/RS-485

COMMUNICATIONS ADAPTER

to

SERIAL NUMBER:

IBM PCTM, PC/XTTM, and PC/ATTM are trademarks of International Business Machines.

i

TABLE OF CONTENTS

WARRANTY INFORMATION . . . . . . . . . . . . i

LIST OF FIGURES . . . . . . . . . . . . . iii

I. INTRODUCTION . . . . . . . . . . . . . . . . 1

II. BOARD DESCRIPTION . . . . . . . . . . . . . 1

III. 16450/16550

A. INTERRUPT ENABLE REGISTER . . . . . . . . 4

B. INTERRUPT IDENTIFICATION REGISTER . . . . 5

C. FIFO CONTROL REGISTER

D. LINE CONTROL REGISTER . . . . . . . . . . 8

E. MODEM CONTROL REGISTER . . . . . . . . . 10

F. LINE STATUS REGISTER . . . . . . . . . . 11

G. MODEM STATUS REGISTER . . . . . . . . . . 13

H. SCRATCHPAD REGISTER . . . . . . . . . . . 14

IV. FIFO INTERRUPT MODE OPERATION

V. BAUD RATE SELECTION . . . . . . . . . . . . 14

VI. ADDRESSING . . . . . . . . . . . . . . . . . 16

VII. INTERRUPTS . . . . . . . . . . . . . . . . . 18

INTERRUPT STATUS REGISTER . . . . . . . . 19

VIII. OUTPUT CONFIGURATIONS . . . . . . . . . . . 20

IX. EXTERNAL CONNECTIONS . . . . . . . . . . . . 21

*

FUNCTIONAL DESCRIPTION . . . . 1

*

. . . . . . . . . . 7

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. . . . . . . 14

X. INSTALLATION . . . . . . . . . . . . . . . . 22

XI. SPECIFICATIONS . . . . . . . . . . . . . . . 22

*

For optional 16550 only.

i

INTRODUCTION

LIST OF FIGURES

Figure 1. QS-200M/QS-300M board layout . . . . . 2

Figure 2. 16450/16550 internal registers . . . . 3

Figure 3. Interrupt enable register . . . . . . 4

Figure 4. Interrupt identification register . . 5

Figure 5. Interrupt source identification . . . 6

Figure 6. FIFO control register

Figure 7. FIFO receiver trigger levels

Figure 8. Line control register . . . . . . . . 8

Figure 9. Parity options . . . . . . . . . . . . 9

Figure 10. Word length and stop bit options . . . 9

Figure 11. MODEM control register . . . . . . . . 10

Figure 12. Line status register . . . . . . . . . 11

Figure 13. MODEM status register . . . . . . . . 13

Figure 14. Clock options . . . . . . . . . . . . 15

Figure 15. Divisor latch options . . . . . . . . 15

Figure 16. Address selection switches . . . . . . 16

Figure 17. Address selection examples . . . . . . 17

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. . . . . . . . 7

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. . . . . 7

Figure 18. Interrupt selection jumper . . . . . . 18

Figure 19. Interrupt status register selection . 19

Figure 20. Interrupt status register definition . 19

Figure 21. Half duplex configuration jumpers . . 20

Figure 22. Output connectors . . . . . . . . . . 21

*

For optional 16550 only.

iii

INTRODUCTION

I. INTRODUCTION

The QS-200M is a four channel RS-422 asynchronous serial communication adapter. The QS-300M is an RS-485 version of the adapter. Both are designed to be hardware compatible with the IBM PC/XT/AT personal computers. Data is communicated through four shielded RJ-11 "modular" phone jack connectors which provide shielding from environmental noise.

The serial interface is accomplished through four 16450 Asynchronous Communication Elements (ACEs). The 16450 is an improved specification version of the 8250 ACEs used in the IBM PC/XT models. Optional 16550 ACEs are available to reduce CPU overhead at higher data rates when used with software supporting this feature.

Addressing for the adapter is selected by a pair of six position switches. These switches allow a full range of address choices between 0 and FFFF hex. The QS200M/QS-300M has the option of selecting one of six possible Interrupt Request lines (IRQ 2 - IRQ 7). A hardware selectable clock divider is also available for producing unusual baud rates.

II. BOARD

DESCRIPTION

A component diagram of the QS-200M/QS-300M is shown in figure 1. The base address is controlled by the address selection switches SW1 & SW2. The interrupt level for the adapter is selected using jumper J3. Channels 1 - 4 are controlled by the 16450 ACEs labeled U5 - U8 and are output through connectors CON1 - CON4 respectively.

III. 16450/16550

FUNCTIONAL DESCRIPTION

The 16450 is an improved specification version of the 8250 Asynchronous Communications Element (ACE). Functionally, the 16450 is equivalent to the 8250. The ACE performs serial-to-parallel conversion on received data and parallel-to-serial conversion on data output from the CPU.

iii

BOARD DESCRIPTION

Figure 1. QS-200M/QS-300M board layout.

FUNCTIONAL DESCRIPTION

Designed to be compatible with the 16450, the 16550 ACE enters character mode on reset and in this mode appears as a 16450 to user software. An additional mode, FIFO mode, can be invoked through software to reduce CPU overhead. The FIFO mode increases performance by providing two 16-byte FIFOs (one transmit and one receive) to buffer data and reduce the number of interrupts issued to the CPU.

Other features of the 16450/16550 include: Programmable baud rate, character length, parity, and number of stop bits. Automatic addition and removal of start, stop, and parity bits. Independent and prioritized transmit, receive and status interrupts. Transmitter clock output to drive receive logic. External receiver clock input.

The following pages provide a brief summary of the internal registers available within the 16450 and 16550 ACEs. The registers are addressed as shown in figure 2 below. Registers and functions specific to the 16550 will be marked with an asterisk(*).

*

| | x 0 1 1 | Line control | | x 1 0 0 | MODEM control | | x 1 0 1 | Line status | | x 1 1 0 | MODEM status | | x 1 1 1 | Scratch | | 1 0 0 0 | Divisor latch (LSB) | | 1 0 0 1 | Divisor latch (MSB) | +---------------+-----------------------------------+

Figure 2. Internal Register map for 16450/16550 ACE. DLAB is accessed through the Line Control Register.

*

For optional 16550 only.

FUNCTIONAL DESCRIPTION

IIIA. INTERRUPT

ENABLE REGISTER

+-------+ D7 | 0 | +-------+ D6 | 0 | +-------+ D5 | 0 | +-------+ D4 | 0 | +-------+ D3 | EDSSI |----- MODEM status +-------+ D2 | ELSI |----- Receiver line status +-------+ D1 | ETBEI |----- Transmit holding register empty +-------+ D0 | ERBFI |----- Received data available +-------+

Figure 3. Interrupt Enable Register bit definitions.

EDSSI - MODEM Status Interrupt:

When set (logic 1), enables interrupt on clear to send, data set ready, ring indicator, and data carrier detect.

ELSI - Receiver Line Status Interrupt:

When set (logic 1), enables interrupt on overrun, parity, framing errors, and break indication.

ETBEI - Transmitter Holding Register Empty Interrupt:

When set (logic 1), enables interrupt on transmitter register empty.

ERBFI - Received Data Available Interrupt:

When set (logic 1), enables interrupt on received data available or FIFO trigger level.

FUNCTIONAL DESCRIPTION

IIIB. INTERRUPT

IDENTIFICATION REGISTER

+------+ D7 | FFE |----- FIFO enable (FIFO only)

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+------+ D6 | 0 | +------+ D5 | 0 | +------+ D4 | 0 | +------+ D3 | IID2 |--+ +------+ | D2 | IID1 | +-- Interrupt identification +------+ | D1 | IID0 |--+ +------+ D0 | IP |----- Interrupt pending +------+

Figure 4. Interrupt Identification Register bit

definitions.

FFE - FIFO Enable:

*

When logic 1, indicates FIFO mode enabled.

IIDx - Interrupt Identification:

Indicates highest priority interrupt pending if any. See IP and figure 5. NOTE: IID2 is always a logic 0 in character mode.

IP - Interrupt Pending:

When logic 0, indicates that an interrupt is pending and the contents of the interrupt identification register may be used to determine the interrupt source. See IIDx and figure 5.

*

For optional 16550 only