Quatech ESCLP-100, ESC-100 User Manual

ESC(LP)-100

Eight Channel Low Profile RS-232

Asynchronous Communications Adapter

for PCI bus

User's Manual

QUATECH, INC. TEL: [phone]
5675 Hudson Industrial Parkway FAX: [phone]
Hudson, Ohio 44236 http://www.quatech.com

WARRANTY INFORMATION

Quatech, Inc. warrants the ESC(LP)-100 to be free of defects for

five (5) years from the date of purchase. Quatech, Inc. will repair or
replace any board that fails to perform under normal operating conditions
and in accordance with the procedures outlined in this document during
the warranty period. Any damage that results from improper installation,
operation, or general misuse voids all warranty rights.

Please complete the following information and retain for your
records. Have this information available when requesting warranty
service.

DATE OF PURCHASE:

MODEL NUMBER: ESC(LP)-100

PRODUCT DESCRIPTION: Eight Channel Low Profile RS-232

Asynchronous PCI Bus
Communications Adapter

SERIAL NUMBER:

ii ESC(LP)-100 User's Manual

© 2006, Quatech, Inc.

NOTICE

The information contained in this document cannot be reproduced
in any form without the written consent of Quatech, Inc. Likewise, any
software programs that might accompany this document can be used only
in accordance with any license agreement(s) between the purchaser and
Quatech, Inc. Quatech, Inc. reserves the right to change this
documentation or the product to which it refers at any time and without
notice.

The authors have taken due care in the preparation of this
document and every attempt has been made to ensure its accuracy and
completeness. In no event will Quatech, Inc. be liable for damages of any
kind, incidental or consequential, in regard to or arising out of the
performance or form of the materials presented in this document or any
software programs that might accompany this document.

Quatech, Inc. encourages feedback about this document. Please
send any written comments to the Technical Support department at the
address listed on the cover page of this document.

DOS, Windows 95/98/2000/ME, Windows NT are trademarks or registered
trademarks of Microsoft Corporation. OS/2 is a registered trademark of IBM
Corporation. All other trademarks or registered trademarks are property of their

respective owners.

iii ESC(LP)-100 User's Manual

Declaration of Conformity

Manufacturer's Name: Quatech Inc.

Manufacturer's Address: 5675 Hudson Industrial Parkway

Hudson, Ohio 44236 (USA)

Application of Council Directive: 89/336/EEC

Standards to which
Conformity is Declared: * EN50081-1 (EN55022,

EN60555-2, EN60555-3)
* EN50082-1 (IEC 801-2,
IEC 801-3, & IEC 801-4)

Type of Equipment: Information Technology

Equipment

Equipment Class: Commercial, Residential, & Light
Industrial

Product Name: PCI Eight-Port Serial
Communications
Card

Model Number : ESC(LP)-100

iv ESC(LP)-100 User's Manual

Table of Contents

1 General Information
2 Hardware Configuration
3 Hardware Installation

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4 Address Map and Special Registers

4.1 Base Address and Interrupt Level (IRQ)

4.2 Enabling the Special Registers

4.3 Interrupt Status Register

4.4 Options Register

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4.4.1 Enhanced Serial Adapter Identification

4.4.2 Clock Rate Multiplier

5 Windows Configurations

5.1 Windows Millennium

5.2 Windows 2000

5.3 Windows 98

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5.4 Windows 95

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5.4.1 Using the "New Hardware Found" Wizard

5.1 Viewing Resources with Device Manager

5.1.1 Changing Resource Settings with Device
Manager

6 Other Operating Systems

6.1 Windows NT

6.2 OS/2

6.3 DOS and other operating systems

6.3.1 QTPCI.EXE

7 External Connections
8 PCI Resource Map
9 Specifications
10 Troubleshooting

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v ESC(LP)-100 User's Manual

vi ESC(LP)-100 User's Manual

1 General Information

The Quatech, Inc. ESC(LP)-100 provides eight RS-232 asynchronous
serial communication interfaces for Low Profile IBM-compatible personal
computer systems using the PCI expansion bus. The ESC(LP)-100 uses
Quatech's new Enhanced Serial Adapter design. Legacy serial port data
rates are limited to a maximum of 115,200 bits per second. Quatech
Enhanced Serial Adapters can achieve data rates as high as 921,600 bits
per second.

As a PCI device, the ESC(LP)-100 requires no hardware
configuration. The card is automatically configured by the computer's
BIOS or operating system. The eight serial ports share a single interrupt
line and are addressed in a contiguous block of 64 bytes. A special
interrupt status register is provided to help software to manage the
shared interrupt.

The ESC(LP)-100's serial ports are implemented using
16750-compatible Universal Asynchronous Receiver/Transmitters
(UARTs). These UARTs contain hardware buffers (FIFOs) which reduce
processing overhead and allow higher data rates to be achieved.

The ESC(LP)-100 is supported under several popular operating
systems and environments. Contact the sales department for details on
current software offerings. Most device drivers are available for
download from the Quatech world wide web site at
http://www.quatech.com.

ESC(LP)-100 User's Manual 1

2 Hardware Configuration

The ESC(LP)-100 is automatically configured at boot time by the
computer's BIOS or operating system. There are no switches or jumpers to
set for installation. See Section 5.5 for instructions on how to use
Windows Device Manager to view and change resource settings.

ESC(LP)-100 User's Manual 2

3 Hardware Installation

1. Turn off the power of the computer system in which the
ESC(LP)-100 is to be installed.

2. Remove the system cover according to the instructions provided by
the computer manufacturer.

3. Install the ESC(LP)-100 in any empty PCI expansion slot. The board
should be secured by installing the Option Retaining Bracket (ORB)
screw.

4. Replace the system cover according to the instructions provided by
the computer manufacturer.

5. Attach and secure the cable connectors to the desired equipment.

6. Turn on the power of the computer system.

The output of the ESC(LP)-100 is a 68-pin VHDCI connector. A

choice of cables is provided to convert the VHDCI into either eight
standard male D-9 connectors or eight 10-pin RJ-45 connectors with all
control signals provided to each port (RTS, DTR, CTS, DSR, DCD, and
RI).

ESC(LP)-100 User's Manual 3

Figure 1: ESC(LP)-100 board outline

4 Address Map and Special Registers

This chapter explains how the eight UARTs and special registers

are addressed, as well as the layout of those registers. This material will
be of interest to programmers writing driver software for the
ESC(LP)-100.

4.1 Base Address and Interrupt Level (IRQ)

The base address and IRQ used by the ESC(LP)-100 are determined

by the BIOS or operating system. Each serial port uses 8 consecutive I/O
locations. The eight ports reside in a single block of I/O space in eight
byte increments, for a total of 64 contiguous bytes, as shown in Figure 2.

I/O Address RangePort

Base Address + 0 to Base Address + 7Serial 1
Base Address + 8 to Base Address + 15Serial 2
Base Address + 16 to Base Address + 23Serial 3
Base Address + 24 to Base Address + 31Serial 4
Base Address + 32 to Base Address + 39Serial 5
Base Address + 40 to Base Address + 47Serial 6
Base Address + 48 to Base Address + 55Serial 7
Base Address + 56 to Base Address + 63Serial 8

Figure 2 --- Port Address Map

All eight serial ports share the same IRQ. The ESC(LP)-100 signals

a hardware interrupt when any port requires service. The interrupt signal
is maintained until no port requires service. Interrupts are level-sensitive
on the PCI bus.

The base address and IRQ are automatically detected by the device

drivers Quatech supplies for various operating systems. For cases where
no device driver is available, such as for operation under DOS, Quatech
supplies the "QTPCI" DOS software utility for manually determining the
resources used. See Section 6.3.1 for details.

ESC(LP)-100 User's Manual 4

4.2 Enabling the Special Registers

The ESC(LP)-100 contains two unique registers, an Interrupt Status

Register and an Options Register. They replace the UART Scratchpad
Register on accesses to register address 7.

The Interrupt Status Register and Options Register are accessed

through the scratchpad location of any UART. The DLAB bit of the UART
(Line Control Register, bit 7) is used to select between the two registers.
The most recent write of a DLAB bit in any UART selects between the two
registers as shown in Figure 3.

DLAB Bit

Register selected for

address 7 accesses

Interrupt Status Register0

Options Register1

Figure 3 --- DLAB bit selects between special registers

4.3 Interrupt Status Register

The read-only Interrupt Status Register can be used to quickly

identify which serial ports require servicing after an interrupt. Reading
the Interrupt Status Register will return the interrupt status of the entire
ESC(LP)-100, as shown in Figure 4. The individual bits are cleared as the
interrupting ports are serviced. The interrupt service routine should
ensure that the interrupt status register reads zero before exiting.

DescriptionBit

Port 8 --- 1 if interrupt pending7 (MSB)
Port 7 --- 1 if interrupt pending6
Port 6 --- 1 if interrupt pending5

ESC(LP)-100 User's Manual 5

Port 5 --- 1 if interrupt pending4
Port 4 --- 1 if interrupt pending3
Port 3 --- 1 if interrupt pending2
Port 2 --- 1 if interrupt pending1
Port 1 --- 1 if interrupt pending0

Figure 4 --- Interrupt Status Register

4.4 Options Register

The Options Register allows software to identify the ESC(LP)-100

as a Quatech Enhanced Serial Adapter. It also allows software to set the
UART clock rate multiplier. Figure 5 shows the structure of the Options
Register.

The powerup default of the Options Register is all bits zero.

DescriptionNameBit

ID bit 1ID17 (MSB)

ID bit 0ID06
(reserved, 0)-5
(reserved, 0)-4
(reserved, 0)-3
(reserved, 0)-2

Clock rate multiplier bit 1RR11
Clock rate multiplier bit 0RR00

Figure 5--- Options Register bit definitions

4.4.1 Enhanced Serial Adapter Identification

The ID bits are used to identify the ESC(LP)-100 as a Quatech
Enhanced Serial Adapter. Logic operations are performed such that the
values read back from these bits will not necessarily be the values that
were written to them. Bit ID1 will return the logical-AND of the values
written to ID[1:0], while bit ID0 will return their exclusive-OR.

Software can thus identify a Quatech Enhanced Serial Adapter by
writing the ID bits with the patterns shown in the "write" column of
Figure 6, then reading the bits and comparing the result with the patterns
in the "read" column. Matching read patterns verify the presence of the
Options Register.

ReadWrite

ID0ID1ID0ID1

0000
1010
1001
0111

ESC(LP)-100 User's Manual 6

Figure 6 --- ID bit write/read table