Quantum QT60160, QT60240 Technical data

lQ QT60160, QT60240

16

AND

24 KEY QM

ATRIX

™ T

OUCH SENSOR

IC

s

/RST

Y2A

Y1A

Y0A

SDA

SCL

These devices are designed for low cost mobile and consumer electronics
applications.

QMatrix™ technology employs transverse charge-transfer sensing electrode
designs which can be made very compact and are easily wired. Charge is
forced from an emitting electrode into the overlying panel dielectric, and then
collected on a receiver electrode which directs the charge into a sampling
capacitor which is then converted directly to digital form without the use of
amplifiers.

Keys are configured in a matrix format that minimizes the number of required
scan lines and device pins. The key electrodes can be designed into a
conventional Printed Circuit Board (PCB) or Flexible Printed Circuit Board
(FPCB) as a copper pattern, or as printed conductive ink on plastic film.

M_SYNC

CHANGE

VSS
VDD
VSS
VDD

32

2
3
4
5
6

X6

7

X7 X5

817

910
LATCH

29 282726

QT60240
QT60160

MLF-32

13

11

12

VREF

S_SYNCX0X1X2X3

14

31 30

AT A GLANCE

Number of keys: 1 to 16 (QT60160), or 1 to 24 (QT60240)
Technology: Patented spread-spectrum charge-transfer (transverse mode)
Key outline sizes: 6mm x 6mm or larger (panel thickness dependent); widely different sizes and shapes possible
Key spacings: 8mm or wider, center to center (panel thickness dependent)
Electrode design: Two-part electrode shapes (drive-receive); wide variety of possible layouts
Layers required: One layer (with jumpers), two layers (no jumpers)

†

Electrode materials: PCB, FPCB, silver or carbon on film, ITO on film, Orgacon
Panel materials: Plastic, glass, composites, painted surfaces (low particle density metallic paints possible)
Adjacent Metal: Compatible with grounded metal immediately next to keys
Panel thickness: Up to 50mm glass, 20mm plastic (key size dependent)
Key sensitivity: Individually settable via simple commands over serial interface

2

Interface: I

C slave mode (100kHz), or parallel output via external shift registers

Moisture tolerance: Best in class.
Power: 1.8V ~ 5.5V, 40µA (16 keys at 1.8V, 2s Low Power mode). Guaranteed to 1.62V.
Package: 32-pin 5 x 5mm MLF RoHS compliant
Signal processing: Self-calibration, auto drift compensation, noise filtering, Adjacent Key Suppression
Applications: Mobile phones, remote controls, domestic appliances, PC peripherals, automotive

ink on film

TM

SMP

25

1615

Y2B

X4

24
23
22
21
20
19
18

Y1B1
Y0B
A0
VSS
VDD
A1
VDD

†

Orgacon is a registered trademark of Agfa-Gevaert N.V

LQ

AVAILABLE OPTIONS

KeysPart Number

-40

-400C to +850C24QT60240-ISG

T

A

0

C to +850C16QT60160-ISG

Copyright © 2006 QRG Ltd

QT60240-ISG R8.06/0906

Contents

1 Overview

1.1 Introduction

1.2 Part Differences

1.3 Enabling / Disabling Keys

2 Hardware and Functional

2.1 Matrix Scan Sequence

2.2 Burst Paring

2.3 Cs Sample Capacitor Operation

2.4 Sample Capacitor Saturation

2.5 Sample Resistors

2.6 Signal Levels

2.7 Matrix Series Resistors

2.8 Key Design

2.9 PCB Layout, Construction

2.10 Power Supply Considerations

2.11 Startup / Calibration Times

2.12 Reset Input

2.13 Spread Spectrum Acquisitions

2.14 Detection Integrators

2.15 Sleep

2.16 Wiring

3 Interfaces

3.1 Introduction

3.2 Shift Register Output Mode

3.3 I2C Port

3.4 CHANGE Pin

4 Control Commands

4.1 Introduction

4.2 Writing Data to the Device

4.3 Reading Data From the Device

4.4 Report Detections for All Keys

4.5 Raw Data Commands

4.6 Cal All

4.7 Setups

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2.9.1 Overview

2.9.2 LED Traces and Other Switching Signals

2.9.3 PCB Cleanliness

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5 I2C Operation

3

5.1 Interface Bus

3

5.2 Transferring Data Bits

3

5.3 START and STOP Conditions

3

5.4 Address Packet Format

3

5.5 Data Packet Format

3

5.6 Combining Address and Data Packets Into a Transmission

3

6 Setups

3

6.1 Introduction

4

6.2 Negative Threshold - NTHR

4

6.3 Positive Threshold - PTHR

4

6.4 Drift Compensation - NDRIFT, PDRIFT

5

6.5 Detect Integrators - NDIL, FDIL

6

6.6 Negative Recal Delay - NRD

6

6.7 Positive Recalibration Delay - PRD

6

6.8 Burst Length - BL

6

6.9 Adjacent Key Suppression - AKS

6

6.10 Oscilloscope Sync - SSYNC

6

6.11 Mains Sync - MSYNC

7

6.12 Sleep Duration - SLEEP

7

6.13 Wake on Key Touch - WAKE

7

6.14 Awake Timeout - AWAKE

7

6.15 Drift Hold Time - DHT

7

6.16 Setups Block

8

7 Specifications

10
10
10
10
11
12
12
12
12
12
13
13
13

7.1 Absolute Maximum Electrical Specifications

7.2 Recommended Operating Conditions

7.3 DC Specifications

7.4 Timing Specifications

7.5 Power Consumption

7.6 Mechanical Dimensions

7.7 Marking

7.8 Moisture Sensitivity Level (MSL)

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lQ

2 QT60240-ISG R8.06/0906

1 Overvie

w

1.1 Introduction

QT60xx0 devices are digital burst mode charge-transfer (QT)
sensors designed specifically for matrix layout touch controls;
they include all signal processing functions necessary to
provide stable sensing under a wide variety of changing
conditions. Only a few external parts are required for
operation. The entire circuit can be built within a few square
centimeters of single-sided PCB area. CEM-1 and FR1
punched, single-sided materials can be used for the lowest
possible cost. The PCB’s rear can be mounted flush on the
back of a glass or plastic panel using a conventional
adhesive, such as 3M VHB two-sided adhesive acrylic film.

1.3 Enabling / Disabling Keys

The NDIL parameter is used to enable and disable keys in the
matrix. Setting NDIL = 0 for a key disables it (Section 6.5). At
no time can the number of enabled keys exceed the
maximum specified for the device (see Section 1.2).

On the QT60160, only the first 2 Y lines (Y0, Y1) are
operational by default. On the QT60160, to use keys located
on line Y2, one or more of the pre-enabled keys must be
disabled simultaneously while enabling the desired new keys.
This can be done in one Setups block load operation.

2 Hardware and Functional

Figure 1.1 Field Flow Between X and Y Elements

overlying panel

X

element

QT60xx0 devices employ transverse charge-transfer ('QT')
sensing, a technology that senses changes in electrical
charge forced across two electrode elements by a pulse edge
(Figure 1.1). QT60xx0 devices allow a wide range of key sizes
and shapes to be mixed together in a single touch panel.

The devices use an I
extracted and to permit individual key parameter setup. The
command structure is designed to minimize the amount of
data traffic while maximizing the amount of information
conveyed.

In addition to normal operating and setup functions the device
can also report back actual signal strengths.

QmBtn™ software for the PC can be used to program the
operation of the IC, as well as read back key status and
signal levels in real time.

2

C interface to allow key data to be

Y

elem ent

2.1 Matrix Scan Sequence

The circuit operates by scanning each key sequentially, key
by key. Key scanning begins with location X=0 / Y=0 (key 0).
X axis keys are known as rows while Y axis keys are referred
to as columns although this has no reflection on actual wiring .
Keys are scanned sequentially by row, for example the

sequence X0Y0 X1Y0 .... X7Y0, X0Y1, X1Y1... etc. Keys are

also numbered from 0...23. Key 0 is located at X0Y0.
Table 2.1 shows the key numbering.

Table 2.1 Key Numbers

X0X1X2X3X4X5X6X7
Y0
Y1
Y2

Each key is sampled in a burst of acquisition pulses whose
length is determined by the Setups parameter BL (page 19);
this can be set on a per-key basis. A burst is completed
entirely before the next key is sampled; at the end of each
burst the resulting signal is converted to digital form and
processed. The burst length directly impacts key gain; each
key can have a unique burst length in order to allow tailoring
of key sensitivity on a key-by-key basis.

01234567
89101112131415

Key

1617181920212223

numbers

2.2 Burst Paring

Keys that are disabled by setting NDIL = 0 (Section 6.5,
page 18) have their bursts removed from the scan sequence
to save scan time. As a consequence, the fewer keys that are
used the faster the device can respond. All calibration times
are reduced when keys

are

disabled

.

1.2 Part Differences

There are two versions of the device; one is capable of a
maximum of 16 keys (QT60160), the other is capable of a
maximum of 24 keys (QT60240).

These devices are identical in all respects, except for the
maximum number of keys specified. The keys can be located
anywhere within an electrical grid of 8 X and 3 Y scan lines.

Unused keys are always pared from the burst sequence in
order to optimize speed. Similarly, in a given part a lesser
number of enabled keys will cause any unused acquisition
burst timeslots to be pared from the sampling sequence to
optimize acquire speed. Thus, if only 14 keys are actually
enabled, only 14 timeslots are used for scanning.

lQ

2.3 Cs Sample Capacitor Operation

Cs capacitors absorb charge from the key electrodes on the
rising edge of each X pulse. On each falling edge of X, the Y
matrix line is clamped to ground to allow the electrode and
wiring charges to neutralize in preparation for the next pulse.
With each X pulse charge accumulates on Cs causing a
staircase increase in its differential voltage.

After the burst completes, the device clamps the Y line to
ground causing the opposite terminal to go negative. The
charge on Cs is then measured using an external resistor to
ramp the negative terminal upwards until a zero crossing is
achieved. The time required to zero cross becomes the
measurement result.

3 QT60240-ISG R8.06/0906

The Cs should be connected as shown in Figure 2.7, page 9.
The value of these capacitors is not critical but 4.7nF is
recommended for most cases. They should be 10 percent
X7R ceramics. If the transverse capacitive coupling from X to
Y is large enough the voltage on a Cs capacitor can saturate,
destroying gain. In such cases the burst length should be
reduced and/or the Cs value increased. See Section 2.4.

If a Y line is not used its corresponding Cs capacitor may be
omitted and the pins left floating.

2.4 Sample Capacitor Saturation

Cs voltage saturation at a pin YnB is shown in Figure 2.1
Saturation begins to occur when the voltage at a YnB pin
becomes more negative than -0.25V at the end of the burst.
This nonlinearity is caused by excessive voltage
accumulation on Cs inducing conduction in the pin protection
diodes. This badly saturated signal destroys key gain and
introduces a strong thermal coefficient which can cause
'phantom' detection. The cause of this is either from the burst
length being too long, the Cs value being too small, or the
X-Y transfer coupling being too large. Solutions include
loosening up the key structure interleaving, more separation
of the X and Y lines on the PCB, increasing Cs, and
decreasing the burst length.

Increasing Cs will make the part slower; decreasing burst
length will make it less sensitive. A better PCB layout and a
looser key structure (up to a point) have no negative effects.

Cs voltages should be observed on an oscilloscope with the
matrix layer bonded to the panel material; if the Rs side of
any Cs ramps more negative than -0.25 volts during any burst
(not counting overshoot spikes which are probe artifacts),
there is a potential saturation problem.

Figure 2.2 shows a defective waveform similar to that of 2.1,
but in this case the distortion is caused by excessive stray
capacitance coupling from the Y line to AC ground; for
example, from running too near and too far alongside a
ground trace, ground plane, or other traces. The excess
coupling causes the charge-transfer effect to dissipate a
significant portion of the received charge from a key into the
stray capacitance. This phenomenon is more subtle; it can be
best detected by increasing BL to a high count and watching
what the waveform does as it descends towards and below

-0.25V. The waveform will appear deceptively straight, but it
will slowly start to flatten even before the -0.25V level is
reached.

A correct waveform is shown in Figure 2.3. Note that the
bottom edge of the bottom trace is substantially straight
(ignoring the downward spikes).

Unlike other QT circuits, the Cs capacitor values on QT60xx0
devices have no effect on conversion gain. However, they do
affect conversion time.

Unused Y lines should be left open.

2.5 Sample Resistors

There are three sample resistors (Rs) used to perform
single-slope ADC conversion of the acquired charge on each
Cs capacitor. These resistors directly control acquisition gain;
larger values of Rs will proportionately increase signal gain.
For most applications Rs should be 1M✡. Unused Y lines do
not require an Rs resistor.

Figure 2.1 VCs - Nonlinear During Burst

(Burst too long, or Cs too small, or X-Y transcapacitance too large)

X Drive

YnB

Figure 2.2 VCs - Poor Gain, Nonlinear During Burst

(Excess capacitance from Y line to Gnd)

X Drive

YnB

Figure 2.3 VCs - Correct

X Drive

YnB

Figure 2.4 X-Drive Pulse Roll-off and Dwell Time

The Dwell time is fixed at ~500ns - see Section 2.7

X drive

Dwell time

Y gate

Lost charge due to
inadequate settling
before end of dwell time

2.6 Signal Levels

Quantum’s QmBtn software makes it is easy to observe the
absolute level of signal received by the sensor on each key.
The signal values should normally be in the range of 200 to
750 counts with properly designed key shapes and values of
Rs. However, long adjacent runs of X and Y lines can also
artificially boost the signal values, and induce signal
saturation; this is to be avoided. The X-to-Y coupling should
come mostly from intra-key electrode coupling, not from stray
X-to-Y trace coupling.

lQ

4 QT60240-ISG R8.06/0906

Figure 2.5 Probing X-Drive

Waveforms With a Coin

Figure 2.6 Recommended Key Structure

‘T’ should ideally be similar to the complete thickness the fields
need to penetrate to the touch surface. Sm aller dimens ions will also
work but will give less signal strength. If in doubt, make the pattern
coarser. The lower figure shows a simpler structure used for
compact key layouts, for exam ple for m obile phones. A layout with a
common X drive and three receive electrodes is depicted.

Y0

QmBtn software is available free of charge on Quantum’s
website www.qprox.com.

The signal swing from the smallest finger touch should
preferably exceed 8 counts, with 12 being a reasonable
target. The signal threshold setting (NTHR) should be set to a
value guaranteed to be less than the signal swing caused by
the smallest touch.

Increasing the burst length (BL) parameter will increase the
signal strengths as will increasing the sampling resistor (Rs)
values.

2.7 Matrix Series Resistors

The X and Y matrix scan lines can use series resistors
(referred to as Rx and Ry respectively) for improved EMC
performance (Figure 2.7, page 9).

X drive lines require Rx in most cases to reduce edge rates
and thus reduce RF emissions. Typical values range from
1K

✡

to 20K✡.

Y lines need Ry to reduce EMC susceptibility problems and in
some extreme cases, ESD. Typical Y values are about 1K
Y resistors act to reduce noise susceptibility problems by
forming a natural low-pass filter with the Cs capacitors.

It is essential that the Rx and Ry resistors and Cs capacitors
be placed very close to the chip. Placing these parts more
than a few millimeters away opens the circuit up to high
frequency interference problems (above 20MHz) as the trace
lengths between the components and the chip start to act as
RF antennae.

✡

X0

Y1

Y2

The upper limits of Rx and Ry are reached when the signal
level and hence key sensitivity are clearly reduced. The limits
of Rx and Ry will depend on key geometry and stray
capacitance, and thus an oscilloscope is required to
determine optimum values of both.

Dwell time is the duration in which charge coupled from X to
Y is captured (Figure 2.4, page 4). Increasing Rx values will
cause the leading edge of the X pulses to increasingly roll off,
causing the loss of captured charge (and hence loss of signal

.

strength) from the keys.
The dwell time of these parts is fixed at 500ns. If the X pulses

have not settled within 500ns, key gain will be reduced; if this
happens, either the stray capacitance on the X line(s) should
be reduced (by a layout change, for example by reducing X
line exposure to nearby ground planes or traces), or, the Rx
resistor needs to be reduced in value (or a combination of
both approaches).

lQ

5 QT60240-ISG R8.06/0906

One way to determine X line settling time is to monitor the
fields using a patch of metal foil or a small coin over the key
(Figure 2.5). Only one key along a particular X line needs to
be observed, as each of the keys along that X line will be
identical. The 500ns dwell time should exceed the observed
95 percent settling of the X-pulse by 25 percent or more.

In almost all cases, Ry should be set equal to Rx, which will
ensure that the charge on the Y line is fully captured into the
Cs capacitor.

2.8 Key Design

Circuits can be constructed out of a variety of materials
including conventional FR-4, Flexible Printed Circuit Boards
(FPCB), silver silk-screened on PET plastic film, and even
inexpensive punched single-sided CEM-1 and FR-2.

The actual internal pattern style is not as important as the
need to achieve regular X and Y widths and spacings of
sufficient size to cover the desired graphical key area or a
little bit more; ~3mm oversize is acceptable in most cases,
since the key’s electric fields drop off near the edges anyway.
The overall key size can range from 6mm x 6mm up to
100mm x 100mm but these are not hard limits. The keys can
be any shape including round, rectangular, square, etc. The
internal pattern can be interdigitated as shown in Figure 2.6.

For small, dense keypads, electrodes such as shown in the
lower half of Figure 2.6 can be used. Where the panels are
thin (usually mobile phones have panels under 2mm thick)
the electrode density can be quite high.

For better surface moisture suppression, the outer perimeter
of X should be as wide as possible, and there should be no
ground planes near the keys. The variable ‘T’ in this drawing
represents the total thickness of all materials that the keys
must penetrate.

2.9 PCB Layout, Construction

Ground planes, if used, should be placed under or around the
QT chip itself and the associated resistors and capacitors in
the circuit, under or around the power supply, and back to a
connector, but nowhere else.

2.9.2 LED Traces and Other Switching Signals

Digital switching signals near the Y lines will induce transients
into the acquired signals, deteriorating the SNR perfomance
of the device. Such signals should be routed away from the Y
lines, or the design should be such that these lines are not
switched during the course of signal acquisition (bursts).

LED terminals which are multiplexed or switched into a
floating state and which are within or physically very near a
key structure (even if on another nearby PCB) should be
bypassed to either Vss or Vdd with at least a 10nF capacitor
to suppress capacitive coupling effects which can induce
false signal shifts. The bypass capacitor does not need to be
next to the LED, in fact it can be quite distant. The bypass
capacitor is noncritical and can be of any type.

LED terminals which are constantly connected to Vss or Vdd
do not need further bypassing.

2.9.3 PCB Cleanliness

All capacitive sensors should be treated as highly sensitive
circuits which can be influenced by stray conductive leakage
paths. QT devices have a basic resolution in the femtofarad
range; in this region, there is no such thing as ‘no clean flux’.
Flux absorbs moisture and becomes conductive between
solder joints, causing signal drift and resultant false
detections or transient losses of sensitivity or instability.
Conformal coatings will trap in existing amounts of moisture
which will then become highly temperature sensitive.

The designer should specify ultrasonic cleaning as part of the
manufacturing process, and in cases where a high level of
humidity is anticipated, the use of conformal coatings after
cleaning to keep out moisture.

2.9.1 Overview

It is best to place the chip near the touch keys on the same
PCB so as to reduce X and Y trace lengths, thereby reducing
the chances for EMC problems. Long connection traces act
as RF antennae. The Y (receive) lines are much more
susceptible to noise pickup than the X (drive) lines.

Even more importantly, all signal related discrete parts
(resistors and capacitors) should be very close to the body of
the chip. Wiring between the chip and the various resistors
and capacitors should be as short and direct as possible to
suppress noise pickup.

Ground planes and traces should NOT
be used around the keys and the Y lines
from the keys. Ground areas, traces, and
other adjacent signal conductors that act

as AC ground (such as Vdd and LED drive
lines etc.) will absorb the received key signals and
reduce signal-to-noise ratio (SNR) and thus will be
counterproductive. Ground planes around keys will also
make water film effects worse.

2.10 Power Supply Considerations

The power supply can range from +1.8V to +5V nominal. The
device can tolerate ±5mV/s short-term power supply
fluctuations. If the power supply fluctuates slowly with
temperature, the device will track and compensate for these
changes automatically with only minor changes in sensitivity.
If the supply voltage drifts or shifts quickly, the drift
compensation mechanism will not be able to keep up,
causing sensitivity anomalies or false detections.

As these devices use the power supply itself as an analog
reference, the power should be very clean and come from a
separate regulator. A standard inexpensive Low Dropout
(LDO) type regulator should be used that is not also used to
power other loads such as LEDs, relays, or other high current
devices. Load shifts on the output of the LDO can cause Vdd
to fluctuate enough to cause false detection or sensitivity
shifts.

Caution: A regulator IC shared with other logic can result in
erratic operation and is not advised.

A regulator can be shared among two or more QT devices on
one board. One such regulator known to work well with QT
chips is the S-817 series from Seiko Instruments
(Seiko Instruments - www.sii-ic.com).

lQ

6 QT60240-ISG R8.06/0906

A single ceramic 0.1uF bypass capacitor, with short traces,
should be placed very close to supply pins 3, 4, 5 and 6 of the
IC. Failure to do so can result in device oscillation, high
current consumption, erratic operation etc. Pins 18, 20, and
21 do not require bypassing.

2.11 Startup / Calibration Times

The devices require initialization times of up to 20ms. A
calibration takes one matrix scan.

Disabled keys are subtracted from the burst sequence and
thus the cal time is shortened. The scan time should be
measured on an oscilloscope.

2.12 Reset Input

The /RST pin can be used to reset the device to simulate a
power-down cycle, in order to bring the device up into a
known state should communications with the device be lost.
The pin is active low, and a low pulse lasting at least 10µs
must be applied to this pin to cause a reset.

The reset pin has an internal 30K
capacitor plus a diode to Vdd can be connected to this pin as
a traditional reset circuit, but this is not required.

If an external hardware reset is not used, the reset pin may
be connected to Vdd or left floating.

✡

- 60K✡ resistor. A 2.2µF

The QT60xx0 uses a two-tier confirmation mechanism having
two such counters for each key. These can be thought of as
‘inner loop’ and ‘outer loop’ confirmation counters.

The ‘inner’ counter is referred to as the ‘fast-DI’; this acts to
attempt to confirm a detection via rapid successive
acquisition bursts, at the expense of delaying the sampling of
the next key. Each key has its own fast-DI counter and limit
value; these limits can be changed via the Setups block on a
per-key basis.

The ‘outer’ counter is referred to as the ‘normal-DI’; this DI
counter increments whenever the fast-DI counter has reached
its limit value. If a fast-DI counter failed to reach its terminal
count, the corresponding normal-DI counter is also reset. The
normal-DI counter also has a limit value which is settable on
a per-key basis. If a normal-DI counter reaches its terminal
count, the corresponding key is declared to be touched and
becomes ‘active’. Note that the normal-DI can only be
incremented once per complete keyscan cycle, i.e. more
slowly, whereas the fast-DI is incremented ‘on the spot’
without interruption.

The net effect of this mechanism is a multiplication of the
inner and outer counters and hence a highly noise-resistance
sensing method. If the inner limit is set to 5, and the outer to
3, the net effect is 5x3=15 successive threshold crossings to
declare a key as active.

2.13 Spread Spectrum Acquisitions

QT60xx0 devices use spread-spectrum burst modulation.
This has the effect of drastically reducing the possibility of
EMI effects on the sensor keys, while simultaneously
spreading RF emissions. This feature is hard-wired into the
device and cannot be disabled or modified.

Spread spectrum is configured as a frequency chirp over a
wide range of frequencies for robust operation.

2.14 Detection Integrators

See also Section 6.5, page 18.
The devices feature a detection integration mechanism, which

acts to confirm a detection in a robust fashion. A per-key
counter is incremented each time the key has exceeded its
threshold and stayed there for a number of acquisitions.
When this counter reaches a preset limit the key is finally
declared to be touched.

For example, if the limit value is 10, then the device has to
exceed its threshold and stay there for 10 acquisitions in
succession without going below the threshold level, before
the key is declared to be touched. If on any acquisition the
signal is not seen to exceed the threshold level, the counter is
cleared and the process has to start from the beginning.

2.15 Sleep

The device will sleep whenever possible to conserve power.
Periodically, the part will wake automatically, scan the matrix,
and return to sleep unless there is activity which demands
further attention. The part will always return to sleep
automatically once all activity has ceased. The time for which
the part will sleep before automatically awakening can be
configured.

A new communication with the device while it is asleep will
cause it to wake up, service the communication and scan the
matrix. At least one full matrix scan is always performed after
waking up and before returning to sleep.

At the end of each matrix scan, the part will return to sleep
unless recent activity demands further attention. If there has
been recent activity, the part will perform another complete
matrix scan and then attempt to sleep once again. This
process is repeated indefinitely until the activity stops and the
part returns to sleep.

Key touch activity will prevent the part from sleeping. The part
will not sleep if any touch events were detected at any key in
the most recent scan of the key matrix.

lQ

7 QT60240-ISG R8.06/0906

2.16 Wiring

Table 2.2 Pin Listing

If Unused, Connect To...CommentsI/OFunctionPin

VddMains Sync inputIM_SYNC1

Leave openState change notification OCHANGE2

-Supply groundPVss3

-Power, +1.8V to +5VPVdd4

-Supply groundPVss5

-Power, +1.8V to +5VPVdd6
Leave openX matrix drive lineOX67
Leave openX matrix drive lineOX78
Leave openShift Register Latch OutputOLATCH9

-GroundIVref10
Leave openOscilloscope syncOS_SYNC11
Leave openX matrix drive lineOX012
Leave openX matrix drive lineOX113
Leave openX matrix drive lineOX214
Leave openX matrix drive lineOX315
Leave openX matrix drive lineOX416
Leave openX matrix drive lineOX517

-Power, +1.8V to +5VPVdd18

-Com port address 1IA119

-Power, +1.8V to +5VPVdd20

-Supply groundPVss21

-Com port address 0IA022
Leave openY line connectionIY0B23
Leave openY line connectionIY1B24
Leave openY line connectionIY2B25

-Sample output.OSMP26

-Serial Interface DataI/OSDA27

-Serial Interface ClockI/OSCL28

Leave open or VddReset low; has internal 30K - 60K pull-upI/RST29

Leave openY line connectionIY0A30
Leave openY line connectionIY1A31
Leave openY line connectionIY2A32

Input onlyI
Output only, push-pullO
Open drain outputOD
Input and outputI/O
Ground or powerP

lQ

8 QT60240-ISG R8.06/0906