Quantum QT1100A-ISG User Manual

lQ QT1100A-ISG

A

DVANCED INFORMATION

z 10 independent touch sensing fields
z 100% autocal for life - no adjustments required
z SPI and UART serial interfaces
z Scanport output - simulates a membrane keypad
z Simple external per channel passive circuit
z User-defined setups of operating parameters
z 3.3V~5.0V single supply operation
z AKS™ Adjacent Key Suppression for tight key layouts
z Sleep mode for low power operation
z Spread spectrum modulated bursts - superior noise rejection
z Sync pin for superior mains frequency noise rejection
z FMEA compliant design features - self detects faults
z Lower per key cost than many mechanical switches
z Lead-free package

10 KEY QT

OUCH

™ S

ENSOR

IC

APPLICATIONS

 PC peripherals
 Television controls
 Instrument panels

QT1100A charge-transfer (“QT”) QTouch ICs are self-contained digital controllers capable of detecting near-proximity or touch on up to
10 electrodes. This device allows each electrode to project an independent sense field through glass or plastic. These devices require
only a few inexpensive passive components per sensing channel. The devices are designed specifically for human interfaces, such as
control panels, appliances, gaming devices, lighting controls, or anywhere a mechanical switch may be found.

Each key channel operates independently, and can be tuned to a unique sensitivity level by simply changing setup values in an
EEPROM or via a serial interface. An external EEPROM can store the setups permanently for standalone applications, for example
when using the scanport, or, the EEPROM can be omitted if the serial port is used to send setup information after each power-up.

Included is patent pending AKS™ Adjacent Key Suppression which suppresses touch from weakly responding keys and allows only a
dominant key to detect, to solve the problem of large fingers on tightly spaced keys. Modulated burst technology provides superior
noise rejection. ‘Fast-DI’ operation works to further suppress false activations due to noise.

These devices also have a Sync pin to suppress some forms of external interference. A Sleep mode is also available for very low
power standby operation.

The QT1100A is designed specifically to assist in creating FMEA compliant designs, allowing it to be used in applications such as
appliance controls.

Using the charge transfer principle, these devices deliver a level of performance which is clearly superior to older technologies yet
extremely cost-effective.

 Appliance controls
 Pointing devices
 Gaming machines

Actual Size

LQ

AVAILABLE OPTIONS

A

1

LEAD-FREESSOP-48T

YesQT1100A-ISG-40ºC to +85ºC

Copyright © 2003-2005 QRG Ltd

QT1100A-ISG R3.02/1105

Contents

1 Overview

Table 1.1 Scanport / UART Pinlist

Table 1.2 Standalone Pinlist

Table 1.3 Standalone Pinlist

Table 1.4 SPI Pinlist

Table 1.5 Pin Descriptions

Figure 1.1 SPI Connection Diagram

Figure 1.2 UART / Scanport Connection Diagram

Figure 1.3 Scanport Only Connection Diagram+

2 Device Control & Wiring

2.1 Oscillator

2.2 Spread Spectrum Modulation

2.3 Cs Sample Capacitors

2.4 Sensitivity

2.5 Sensitivity Balance

2.6 Power Supply

2.7 PCB Layout and Construction

2.8 ESD Protection

2.9 Noise Issues

2.10 Start-up Time

2.11 Operating Parameter Setups

2.12 Standalone Operation, No EEPROM

2.13 EEPROM Functionality

2.14 Scanport Interface

2.15 Start-up Sequencing

2.16 Error Detection and Reporting

3 Serial Operation

3.1 UART Interface

3.2 SPI Operation

3.3 Communication Error Handling

3.4 Control Commands

3.5 Status Commands

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2.9.1 LED Traces and Other Switching Signals

2.9.2 External Fields

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3.1.1 TX Pin

3.1.2 Sleep/Wake Operation in UART Mode

3.1.3 CRDY Operation in UART Mode

3.2.1 Multi-Drop SPI Capability

3.2.2 Sleep/Wake Operation in SPI Mode

3.2.3 CRDY Operation in SPI Mode

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3.4.1 Null Command - 0x00

3.4.2 Enter Setups Load Mode - 0x01

3.4.3 Enter Run Mode - 0x02

3.4.4 Enter Cal Mode - 0x03

3.4.5 Force Reset - 0x04

3.4.6 Sleep - 0x05

3.4.7 Cal Key ‘k’ - 0x1k

3.5.1 Signal for 1 Key - 0x2k

3.5.2 Reference for Key ‘k’ - 0x4k

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3.5.3 Detect Integrator for Key ‘k’ - 0x6k

3.5.4 Status for Key ‘k’ - 0x8k

3.5.5 Report 1st Key - 0xC0

3.5.6 Report All Keys - 0xC1

3.5.7 Device Status - 0xC2

3.5.8 EEPROM CRC - 0xC3

3.5.9 RAM CRC - 0xC4

3.5.10 Error Flags for Group - 0xC5

3.5.11 Internal Code - 0xC6

3.5.12 Return Last Command - 0xC7

3.5.13 Dump Setups Block - 0xC8

3.5.14 Quick Report First Key - 0xC9

3.6 Command Sequencing

Figure 3-1 Suggested Serial Flow

Table 3-1 Control Commands

Table 3-2 Status Commands

4 Setup Block Functions

4.1 NTHR - Negative Threshold Bits

4.2 NHYS - Negative Hysteresis Bits

4.3 NDCR / PDCR - Drift Comp Bits

4.4 NRD - Negative Recal Delay Bits

4.5 PRD - Positive Recal Delay Bits

4.6 AKS - Adjacent Key Suppression Bits

4.7 EK - Error Key Control Bits

4.8 K2L / LEDP / KEYO Control Bits

4.9 NDIL, FDIL - Detect Integrator Bits

4.10 PTHR - Positive Threshold Bits

4.11 PHYS - Positive Hysteresis Bits

4.12 SE, SYNC Control Bits

4.13 LBLL - Lower Burst Length Limit

4.14 BS - Burst Spacing Control Bits

4.15 BR - Baud Rate Control Bits

4.16 HCRC - Host CRC

Table 4-1 Serial / EEPROM Setups Block

4.17 Timing Tables

5 - Specifications

5.1 Absolute Maximum Specifications

5.2 Recommended Operating Conditions

5.3 AC Specifications

5.4 DC Specifications

5.5 Burst / Sync Timing

5.6 SPI Timing Diagram

5.7 QT1100A Timing Parameters - with Fosc = 12MHz

5.8 Current vs Vdd

5.9 Mechanical

5.10 Marking

6 Appendix A - 8-Bit CRC C Algorithm

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Copyright © 2003-2005 QRG Ltd

QT1100A-ISG R3.02/1105

1 Overview

The QT1100A is a 10 touch-key sensor IC based on
Quantum’s patented charge-transfer principles for robust
operation and ease of design. This device has many
advanced features which provide for reliable, trouble-free
operation over the life of the product. It can operate in either
a standalone mode or under host control via a serial
interface. Output options include UART and SPI serial types
and parallel scanport. In any interface mode, a low-cost
optional EEPROM can be used to determine the device
configuration using a stored Setup block .

FMEA self-testing: This part has been designed specifically
for demanding appliance applications requiring FMEA
certification. The part has many advanced features that
check for and report failures, to allow the designer to create
a safer product. It also features two robust serial interfaces
with sophisticated CRC error checking to permit validation of
commands and responses in real time.

Burst mode: The device operates in ‘burst mode’. Each key
is acquired using a burst of charge-transfer sensing pulses
whose count can vary tremendously depending on the value
of the reference capacitor Cs and the load capacitance Cx.
The keys (also called ‘channels’) are acquired time
sequentially within fixed timeslots whose width can be
controlled by user-defined Setups.

Self-calibration: On power-up, all keys are self-calibrated
within a few hundred milliseconds to provide reliable
operation under almost any set of conditions.

Auto-recalibration: The device can time out and recalibrate
each key independently after a fixed interval of continuous
detection, so that the keys can never become ‘stuck on’ due
to foreign objects or sudden influences. After recalibration
the key will continue to function normally.

Drift compensation operates to correct the reference level
of each key slowly but automatically over time, to suppress
false detections caused by changes such as temperature,
humidity, dirt and other environmental effects.

Spread Spectrum operation: The bursts operate over a
spread of frequencies, so that external fields will have
minimal effect on key operation and emissions are very
weak. Spread-spectrum operation works with the ‘detect
integrator’ (DI) mechanism to dramatically reduce the
probability of false detection due to noise.

Detection confirmation occurs by means of a ‘detect
integrator’ mechanism that requires multiple confirmations of
detection over a number of key bursts. The bursts operate at
alternating frequencies, so that external fields will have a
minimal effect on key operation. This spread-spectrum
mode of operation also reduces RF noise emissions.

The device also features the ability to acquire and lock onto
touch signals very rapidly, greatly improving response time
through the use of the ‘fast detect integration’ or ‘Fast-DI’
feature.

Sync Mode: The QT1100A features a Sync mode to allow
the device to slave to an external signal source, such as a
mains signal (50/60Hz), to limit interference effects. This is
performed using a special Sync pin.

Low Power Sleep Mode: The device features a low power
Sleep mode for microamp levels of current drain when not in
use. The part can be put into sleep for a certain percentage
of the time, so that it can still respond to touch but with lower
levels of current drain.

AKS™ Adjacent Key Suppression works to prevent
multiple keys responding to a single touch, a common
complaint of capacitive touch panels. This system operates
by comparing signal strengths from keys within a defined
group to suppress touch detections from those with a weaker
signal change than the dominant key. The QT1100A allows
any AKS grouping of two or more keys, under user control.

Unique to this device is the ability for the designer to treat
each key as an individual sensor for configuration purposes.
Each key can be programmed separately for sensitivity, drift
compensation, recalibration timeouts, adjacent key
suppression, and the like.

The device is designed to support FMEA-qualified
applications using a variety of checks and redundancies.
Among other checks the component uses CRC codes in all
critical communication transfers, and can also output error
condition codes via redundant signaling paths.

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Copyright © 2003-2005 QRG Ltd

QT1100A-ISG R3.02/1105

Table 1.1 Scanport / UART Pinlist

With or without EEPROM; either UART or Scanport or both may be used

2
3
4

8
9

10

14
15
16

20
21
22

Sense pinI/OSNS3K

Sense pinI/OSNS4K

Sense pinI/OSNS5K6

Sense pinI/OSNS6K

Sense pinI/OSNS7K

Sense pinI/OSNS8K

Sense pinI/OSNS9K

If UnusedNotesFunctionTypeNamePin

OpenTo CS3Sense pinI/OSNS31

Vss or openTo CS3 + Key

OpenTo CS4Sense pinI/OSNS4

Vss or openTo CS4 + Key

OpenTo CS5Sense pinI/OSNS55

Vss or openTo CS5 + Key

OpenTo CS6Sense pinI/OSNS67

Vss or openTo CS6 + Key

OpenTo CS7Sense pinI/OSNS7

Vss or openTo CS7 + Key

--Unused-n/c11

--Unused-n/c12

OpenTo CS8Sense pinI/OSNS813

Vss or openTo CS8 + Key

OpenTo CS9Sense pinI/OSNS9

Vss or openTo CS9 + Key

-0VGroundPwrVss17
OpenClock to EEPROM EEPROMOCKEE18
OpenData out to EEPROMEEPROMODOEE19

VddData in from EEPROMEEPROMIDIEE
VssSerial to host; If used, use pull-up-R UARTODTX
VddSerial in / Wake from sleepUART, WakeupIRX/WAKE

10K ~ 220K to Vdd1 = Comms ready; use pull-up-RHandshakeI/O, ODCRDY23

OpenEEPROM chip select; use pull-down-REEPROMOCSEE24

OpenSee Table 2.1Scanport outOSCANO_025

26
27
28

32
33
34

38
39
40

44
45
46

OpenSee Table 2.1Scanport outOSCANO_1
OpenSee Table 2.1Scanport outOSCANO_2
OpenSee Table 2.1Scanport outOSCANO_3

VssSee Table 2.1Scanport inISCANI_229
VssSee Table 2.1Scanport inISCANI_130
VssSee Table 2.1Scanport inISCANI_031

-To VssComms selectICMODE

20K ~ 220K to VddAlways use pull-up RSync inI/OSYNC

Open-LED & StatusOLED/STAT

VddActive lowReset inputIRST35

-+3.3 ~ +5VPowerPwrVdd36

-12MHz - Can also be ext clock inResonatorIOSC137
Open-ResonatorOOSC2

--Unused-n/c

--Unused-n/c

--Unused-n/c41

--Unused-n/c42
OpenTo CS0 + KeySense pinI/OSNS043

Vss or openTo CS0Sense pinI/OSNS0K

OpenTo CS1 + KeySense pinI/OSNS1

Vss or openTo CS1Sense pinI/OSNS1K

OpenTo CS2 + KeySense pinI/OSNS247

Vss or openTo CS2Sense pinI/OSNS2K48

I CMOS input
I/O CMOS I/O
O CMOS output (push-pull)
OD CMOS open drain I/O
Pwr Power / ground

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Copyright © 2003-2005 QRG Ltd

QT1100A-ISG R3.02/1105

Table 1.2 Standalone Pinlist

Scanport, with EEPROM; no serial interface

2
3
4

8
9

10

14
15
16

20
21
22

If UnusedNotesFunctionTypeNamePin

OpenTo CS3Sense pinI/OSNS31

Sense pinI/OSNS3K

Sense pinI/OSNS4K

Sense pinI/OSNS5K6

Sense pinI/OSNS6K

Sense pinI/OSNS7K

Sense pinI/OSNS8K

Sense pinI/OSNS9K

Vss or openTo CS3 + Key

OpenTo CS4Sense pinI/OSNS4

Vss or openTo CS4 + Key

OpenTo CS5Sense pinI/OSNS55

Vss or openTo CS5 + Key

OpenTo CS6Sense pinI/OSNS67

Vss or openTo CS6 + Key

OpenTo CS7Sense pinI/OSNS7

Vss or openTo CS7 + Key

--Unused-n/c11

--Unused-n/c12
OpenTo CS8Sense pinI/OSNS813

Vss or openTo CS8 + Key

OpenTo CS9Sense pinI/OSNS9

Vss or openTo CS9 + Key

-0VGroundPwrVss17

-Clock to EEPROMEEPROMOCKEE18

-Data out to EEPROMEEPROMODOEE19

-Data in from EEPROMEEPROMIDIEE

-To VssUARTODTX

-To VddUART, WakeupIRX/WAKE

-Leave openHandshakeI/O, ODCRDY23

-EEPROM chip selectEEPROMOCSEE24

26
27
28

32
33
34

38
39
40

44
45
46

I CMOS input
I/O CMOS I/O
O CMOS output (push-pull)
OD CMOS open drain I/O
Pwr Power / ground

OpenSee Table 2.1Scanport outOSCANO_025
OpenSee Table 2.1Scanport outOSCANO_1
OpenSee Table 2.1Scanport outOSCANO_2
OpenSee Table 2.1Scanport outOSCANO_3

VssSee Table 2.1Scanport inISCANI_229
VssSee Table 2.1Scanport inISCANI_130
VssSee Table 2.1Scanport inISCANI_031

-To VssComms selectICMODE

20K ~ 220K to VddAlways use pull-up RSync inI/OSYNC

Open-LED & StatusOLED/STAT

VddActive lowReset inputIRST35

-+3.3 ~ +5VPowerPwrVdd36

-12MHz - Can also be ext clock inResonatorIOSC137
Open-ResonatorOOSC2

--Unused-n/c

--Unused-n/c

--Unused-n/c41

--Unused-n/c42
OpenTo CS0 + KeySense pinI/OSNS043

Vss or openTo CS0Sense pinI/OSNS0K

OpenTo CS1 + KeySense pinI/OSNS1

Vss or openTo CS1Sense pinI/OSNS1K

OpenTo CS2 + KeySense pinI/OSNS247

Vss or openTo CS2Sense pinI/OSNS2K48

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Copyright © 2003-2005 QRG Ltd

QT1100A-ISG R3.02/1105

Table 1.3 Standalone Pinlist

Scanport, without EEPROM; no serial interface

2
3
4

8
9

10

14
15
16

21

Sense pinI/OSNS3K

Sense pinI/OSNS4K

Sense pinI/OSNS5K6

Sense pinI/OSNS6K

Sense pinI/OSNS7K

Sense pinI/OSNS8K

Sense pinI/OSNS9K

EEPROMODOEE19

Connect DOEE, DIEE together

If UnusedNotesFunctionTypeNamePin

OpenTo CS3Sense pinI/OSNS31

Vss or openTo CS3 + Key

OpenTo CS4Sense pinI/OSNS4

Vss or openTo CS4 + Key

OpenTo CS5Sense pinI/OSNS55

Vss or openTo CS5 + Key

OpenTo CS6Sense pinI/OSNS67

Vss or openTo CS6 + Key

OpenTo CS7Sense pinI/OSNS7

Vss or openTo CS7 + Key

--Unused-n/c11

--Unused-n/c12

OpenTo CS8Sense pinI/OSNS813

Vss or openTo CS8 + Key

OpenTo CS9Sense pinI/OSNS9

Vss or openTo CS9 + Key

-0VGroundPwrVss17

-OpenEEPROMOCKEE18

-

-EEPROMIDIEE20

-To VssUARTODTX

-To VddUART, WakeupIRX/WAKE22

-Leave openHandshakeI/O, ODCRDY23

-OpenEEPROMOCSEE24

25
26
27

31
32
33

37
38
39

43
44
45

I CMOS input
I/O CMOS I/O
O CMOS output (push-pull)
OD CMOS open drain I/O
Pwr Power / ground

OpenSee Table 2.1Scanport outOSCANO_0
OpenSee Table 2.1Scanport outOSCANO_1
OpenSee Table 2.1Scanport outOSCANO_2
OpenSee Table 2.1Scanport outOSCANO_328

VssSee Table 2.1Scanport inISCANI_229
VssSee Table 2.1Scanport inISCANI_130
VssSee Table 2.1Scanport inISCANI_0

-To VssComms selectICMODE

20K ~ 220K to VddAlways use pull-up RSync inI/OSYNC

Open-LED & StatusOLED/STAT34

VddActive lowReset inputIRST35

-+3.3 ~ +5VPowerPwrVdd36

-12MHz - Can also be ext clock inResonatorIOSC1

Open-ResonatorOOSC2

--Unused-n/c

--Unused-n/c40

--Unused-n/c41

--Unused-n/c42

OpenTo CS0 + KeySense pinI/OSNS0

Vss or openTo CS0Sense pinI/OSNS0K

OpenTo CS1 + KeySense pinI/OSNS1

Vss or openTo CS1Sense pinI/OSNS1K46

OpenTo CS2 + KeySense pinI/OSNS247

Vss or openTo CS2Sense pinI/OSNS2K48

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Copyright © 2003-2005 QRG Ltd

QT1100A-ISG R3.02/1105

Table 1.4 SPI Pinlist

With or without EEPROM

1

4
5

8
9

12
13

16
17

20
21

24

If UnusedNotesFunctionTypeNamePin

OpenTo CS3Sense pinI/OSNS3

Vss or openTo CS3 + KeySense pinI/OSNS3K2

OpenTo CS4Sense pinI/OSNS43

Vss or openTo CS4 + KeySense pinI/OSNS4K

OpenTo CS5Sense pinI/OSNS5

Vss or openTo CS5 + KeySense pinI/OSNS5K6

OpenTo CS6Sense pinI/OSNS67

Vss or openTo CS6 + KeySense pinI/OSNS6K

OpenTo CS7Sense pinI/OSNS7

Vss or openTo CS7 + KeySense pinI/OSNS7K10

--Unused-n/c11

--Unused-n/c

OpenTo CS8Sense pinI/OSNS8

Vss or openTo CS8 + KeySense pinI/OSNS8K14

OpenTo CS9Sense pinI/OSNS915

Vss or openTo CS9 + KeySense pinI/OSNS9K

-0VGroundPwrVss
OpenClock to EEPROM EEPROMOCKEE18
OpenData out to EEPROMEEPROMODOEE19

VddData in from EEPROMEEPROMIDIEE

-To VssUnused-n/c

VddWake from sleepWakeIWAKE22

-1 = Comms ready; Use pull-up RSPI handshakeODCRDY23
OpenEEPROM chip select; Use pull-down REEPROMOCSEE

25

28
29

32
33

36
37

40
41

44
45

48

I CMOS input
I/O CMOS I/O
O CMOS output (push-pull)
OD CMOS open drain I/O
Pwr Power / ground

Vss-unusedIn/c

-From hostSPI clockICLK26

-To host; use pull-up RSPI dataI/ODO27

-From hostSPI dataIDI

-From hostSPI Slave selectI/SS

-To VssUnusedIn/c30

-To VssUnusedIn/c31

-To VddComms selectICMODE

20K ~ 220K to VddAlways use pull-up RSync InI/OSYNC

Open -LED & StatusOLED/STAT34

VddActive lowReset inputIRST35

-+3.3 ~ +5VPowerPwrVdd

-12MHz - Can also be ext clock inResonatorIOSC1
Open-ResonatorOOSC238

--Unused-n/c39

--Unused-n/c

--Unused-n/c

--Unused-n/c42
OpenTo CS0 + KeySense pinI/OSNS043

Vss or openTo CS0Sense pinI/OSNS0K

OpenTo CS1 + KeySense pinI/OSNS1

Vss or openTo CS1Sense pinI/OSNS1K46

OpenTo CS2 + KeySense pinI/OSNS247

Vss or openTo CS2Sense pinI/OSNS2K

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Copyright © 2003-2005 QRG Ltd

QT1100A-ISG R3.02/1105

Table 1.5 Pin Descriptions

DescriptionPin

Sense pin, to Cs reference capacitorSNSn

Sense pin, to Cs and to key electrodeSNSnK

Clock line output, to drive serial EEPROMCKEE

Output data line, to serial EEPROMDOEE

Input data line, from serial EEPROMDIEE

Serial port pin for UARTTX

Receive pin in UART mode; alternately or in addition, Wake from sleep RX/WAKE

CRDY

CMODE

SYNC

LED/STAT

/RST

Serial interface handshake pin; bidirectional in UART mode, output only in SPI
mode. Always use a pull-up resistor on this pin.

Chip select drive to serial EEPROM. Always use a pull-down resistor on this pin.CSEE

SPI clock input from hostCLK

SPI data output to host. Always use a pull-up resistor on this pin.DO

SPI data in from hostDI

SPI Slave select from host/SS

Output scan linesSCANO_x

Input scan linesSCANI_x

Communications mode select pin. For UART or scanport operation, connect to
Vss. For SPI mode, connect to Vdd.

Sync Input to synchronize acquisitions to an external source or another QT chip.
Always use a pull-up resistor on this pin.

LED & Status output pin. This pin can sink 1mA to drive a status LED, or be used
by a host controller to determine device error condition or status .

Reset input, low resets device. Normally this pin can be tied to Vdd, or driven from
a host controller.

Connect to 12MHz resonator; can also be an external clock inputOSC1

Connect to 12MHz resonator; leave open if external clock is usedOSC2

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Copyright © 2003-2005 QRG Ltd

QT1100A-ISG R3.02/1105

Figure 1.1 SPI Connection Diagram

VUNREG

*10uF

4.7K

KEY3

4.7K

KEY4

4.7K

KEY5

4.7K

KEY6

4.7K

KEY7

Regulator

VI VO

G

22nF

22nF

22nF

22nF

22nF

*4.7uF

2.2K

2.2K

2.2K

2.2K

2.2K

*100nF

VDD

*One bypass capacitor to be tightly coupled to pins 36 and 17.
Follow regulator manufacturer's recommendations
for input and output capacitors.

QT1100A-AS

2.2K

2.2K

2.2K

12MHz 3-TERM
RESONATOR

22nF

22nF

22nF

4.7K

KEY2

4.7K

KEY1

4.7K

KEY0

VDD

2.2K

DIN

CS

22nF

2.2K

22nF

4

3

2

1

10K

VDD

KEY8

KEY9

5

6

7

8

VDD

4.7K

4.7K

VSS

NC

CLK

NC

VDD

93LC46A

DOUT

22K

Note 1: EEPROM is optional when using SPI interface.

Note 2: See Table 1.4 for unused pin connections.

4.7K

VDD

VDD

22K

22K

/SS

DI

DO

CLK

CRDY

WAKE

RESET

VDD

SYNC

VDD

SPI TO/FROM HOST

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Copyright © 2003-2005 QRG Ltd

QT1100A-ISG R3.02/1105

Figure 1.2 UART / Scanport Connection Diagram

Shown with optional EEPROM

VUNREG

*10uF

4.7K

KEY3

4.7K

KEY4

4.7K

KEY5

4.7K

KEY6

4.7K

KEY7

Regulator

VI VO

G

22nF

22nF

22nF

22nF

22nF

2.2K

2.2K

2.2K

2.2K

2.2K

*4.7uF

*100nF

VDD

*One bypass capacitor to be tightly coupled to pins 36 and 17.
Follow regulator manufacturer's recommendations
for input and output capacitors.

QT1100A-AS

2.2K

2.2K

2.2K

12MHz 3-PIN
RESONATOR

22nF

22nF

22nF

4.7K

KEY2

4.7K

KEY1

4.7K

KEY0

VDD

VDD

KEY8

KEY9

VDD

VSS

5

NC

6

NC

7

VDD

8

4.7K

4.7K

DOUT

DIN

CLK

93LC46A

10K

10K

22K

CS

2.2K

22nF

2.2K

22nF

4

3

2

1

4.7K

22K

VDD

22K

VDD

SCANI_0

SCANI_1

SCANI_2

SCANO_3

SCANO_2

SCANO_1

SCANO_0

TX

CRDY

RX/WAKE

RESET

VDD

SYNC

SCANPORT

TO/FROM HOST

UART

TO/FROM HOST

Note 1: EEPROM is optional when using UART interface in this drawing.

Note 2: UART interface is not normally used when using Scanport interface and vice versa.

Note 3: See Table 1.1 for unused pin connections

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Copyright © 2003-2005 QRG Ltd

QT1100A-ISG R3.02/1105

Figure 1.3 Scanport Only Connection Diagram+

Without EEPROM

KEY3

KEY4

KEY5

KEY6

KEY7

KEY8

KEY9

VUNREG

*10uF

4.7K

4.7K

4.7K

4.7K

4.7K

4.7K

4.7K

Regulator

VI VO

G

22nF

22nF

22nF

22nF

22nF

22nF

22nF

2.2K

2.2K

2.2K

2.2K

2.2K

2.2K

2.2K

*4.7uF

*100nF

VDD

*One bypass capacitor to be tightly coupled to pins 36 and 17.
Follow regulator manufacturer's recommendations
for input and output capacitors.

QT1100A-AS

2.2K

2.2K

2.2K

12MHz 3-PIN
RESONATOR

4.7K

22K

22nF

22nF

22nF

VDD

4.7K

KEY2

4.7K

KEY1

4.7K

KEY0

VDD

22K

RESET

VDD

SYNC

VDD

SCANI_0

LQ

SCANI_1

SCANI_2

SCANO_3

VDD

11

Copyright © 2003-2005 QRG Ltd

SCANO_2

SCANO_1

SCANO_0

SCANPORT

TO/FROM HOST

QT1100A-ISG R3.02/1105

2 Device Control & Wiring

2.1 Oscillator

The QT1100A uses an external 12MHz resonator as its
frequency reference. This frequency can be lowered for
lower average power, however all functions will also slow
down including response time and communications
parameters. It is not advised to change the operating
frequency without a good reason.

The oscillator source can be from an external circuit, so that
two or more circuits can share the same oscillator. If an
external frequency source is used, it should be fed to OSC1,
pin 37. OSC2 should be left open-circuit.

2.2 Spread Spectrum Modulation

The device features spread spectrum modulation of its
acquisition bursts to dramatically reduce both RF emissions
and susceptibility to external AC fields. This feature cannot
be disabled or modified.

Spread spectrum modulation works together with the
detection integrator (‘DI’) process to eliminate external
interference in almost all cases.

2.3 Cs Sample Capacitors

The Cs sample capacitors accumulate the charge from the
key electrodes and determine sensitivity . (See Section 2.4)

The Cs capacitors can be virtually any plastic film or low to
medium-K ceramic capacitor. The ‘normal’ Cs range is 2.2nF
to 100nF depending on the sensitivity required; larger values
of Cs require higher stability to ensure reliable sensing.
Acceptable capacitor types for most uses include PPS film,
polypropylene film, and NP0 and X7R ceramics. Lower
grades than X7R are not advised.

The Cs capacitors and all associated wiring should be
placed and wired very tight to the body of the IC for noise
immunity to very high frequency RF fields. See Section 2.7.

2.4 Sensitivity

Sensitivity can be altered to suit various applications and
situations on a key-by-key basis. One way to impact
sensitivity is to alter the value of each Cs when the device is
in NTM = 0 mode (see page 25); higher values of Cs will
yield higher sensitivity; each key has its own Cs value and
so can be adjusted independently. The Setups block can
also be used to alter sensitivity, using an external EEPROM,
serial communications, or both (Section 4.1).

Sensitivity can also be increased by using bigger electrode
areas, reducing panel thickness, or using a panel material
with a higher dielectric constant (e.g. glass instead of
plastic).

In some cases the keys may be too sensitive. Gain ca n be
lowered by:

a) making the electrode smaller, or,

b) making the electrode into a sparse mesh using a high
space-to-conductor ratio, or,

c) by decreasing the Cs capacitors (if NTM = 0).

Sensitivity trimming is usually done through a process of trial
and error, using a range of ‘standard fingers’ made of
earthed conductive rubber on the end of a plastic rod.

2.5 Sensitivity Balance

A number of factors can cause sensitivity imbalances among
the keys. Notably, SNS wiring to electrodes can have
differing stray amounts of capacitance to ground, perhaps
due to trace length differences or the presence of ground,
power, or other signal wiring near the SNS traces. Increasing
load capacitance (Cx) will cause a decrease in gain. Key
size differences, and proximity to other metal surfaces can
also impact gain.

The keys may thus require ‘balancing’ to achieve similar
sensitivity levels. The NTHR parameter in the Setups
functions is one easy way to trim and balance key sensitivity
(Section 4.1).

Balancing can also be achieved by adjusting the Cs
capacitor values to achieve equilibrium. The Rs resistors
have no effect on sensitivity and should not be altered. Load
capacitance to ground (to boost Cx) can also be added to
overly sensitive channels to reduce gain; these should be on
the order of a few picofarads.

2.6 Power Supply

The power supply can range from 3.3 to 5.0 volts. If this
fluctuates slowly with temperature, the device will track and
compensate for these changes automatically with only minor
changes in sensitivity. If the supply voltage drifts or shifts
quickly, the drift compensation mechanism will not be able to
keep up, causing sensitivity anomalies or false detections.

The power supply should be locally regulated using a
3-terminal device. If the supply is shared with another
electronic system, care should be taken to ensure that the
supply is free of digital spikes, sags, and surges which can
cause adverse effects.

For proper operation a 0.1µF or greater bypass capacitor
must be used between Vdd and Vss; the bypass cap acitor
should be routed with very short tracks to the device’s Vss
and Vdd pins.

2.7 PCB Layout and Construction

Ground Planes: The PCB should if possible include a

copper pour under and around the IC, but not under the SNS
lines after the Rsns resistors. Ground planes increase
loading capacitance (Cx) on the SNS lines and can
dramatically degrade sensitivity.

Part Placement: The resistors and capacitors associated
with each key should be placed physically as close to the
body of the QT1100A as possible, with the shortest possible
trace lengths, to minimize the influence of external fields
(see Section 2.9.2). The QT1100A should be placed as close
to the key electrodes as possible to reduce wiring lengths, to
minimize stray capacitances on and between SNS traces
and to reduce interference problems.

PCB Cleanliness: All capacitive sensors should be treated
as highly sensitive analog circuits which can be influenced
by stray conductive leakage paths. QT devices have a basic
resolution in the femtofarad range; in this range, there is no
such thing as ‘no-clean flux’. Flux absorbs moisture and
becomes conductive between solder joints, causing signal
drift, false detections, and transient instabilities. Conformal
coatings will trap in existing amounts of moisture which will
then become highly temperature sensitive.

The designer should specify ultrasonic cleaning as part of
the manufacturing process, and in cases where a high level
of humidity is anticipated, the use of conformal coatings after
cleaning to keep out moisture.

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Copyright © 2003-2005 QRG Ltd

QT1100A-ISG R3.02/1105

2.8 ESD Protection

Normally, only a series resistor is required for ESD
suppression. A 10K to 22K Rsns resistor in series with each
sense trace to each key is normally sufficient. The dielectric
panel (glass or plastic) usually provides a high degree of
isolation to prevent ESD discharge from reaching the circuit.

The Rsns resistors should be placed close to and wired
tightly to the chip, not the keys.

If the Cx load is high, Rsns can prevent total charge and
transfer and as a result gain can deteriorate. If a reduction in
Rsns increases gain noticeably, the lower value should be
used. Conversely, increasing the Rsns can result in added
ESD and EMC benefits provided that the increase in
resistance does not decrease sensitivity.

2.9 Noise Issues

2.9.1 LED Traces and Other Switching Signals

Digital switching signals near the SNS lines will induce
transients into the acquired signals, deteriorating the SNR
performance of the device. Such signals should be routed
away from the SNS lines, or the design should be such that
these lines are not switched during the course of signal
acquisition (bursts).

LED terminals which are multiplexed or switched into a
floating state and which are within or physically very near a
key structure (even if on another nearby PCB) should be
bypassed to either Vss or Vdd with at least a 10nF capacitor
of any type, to suppress capacitive coupling effects which
can induce false signal shifts. LED terminals which are
constantly connected to Vss or Vdd do not need bypassing.

2.9.2 External Fields

External AC fields (EMI) due to RF transmitters or electrical
noise sources can cause false detections or unexplained
shifts in sensitivity.

The influence of external fields on the sensor is reduced by
means of the Rsns series resistors. The Cs capacitors and
the Rsns resistors form a natural low-pass filter for incoming
RF signals; the roll-off frequency of this network is defined
by -

FR=

If for example Cs = 4.7nF, and Rsns = 10K, the EMI rolloff
frequency is ~3.4kHz, which is much lower than most noise
sources (except for mains frequencies i.e. 50/60Hz).

Rsns and Cs must both be placed very close to the body of
the IC so that the lead lengths between them and the IC do
not form an unfiltered antenna at very high frequencies.

PCB layout, grounding, and the structure of the input
circuitry have a great bearing on the success of a design to
withstand electromagnetic fields and be relatively noise-free.

These design rules should be adhered to for best ESD and
EMC results:

1. Use only SMT components.

2. Keep all Cs, Rs, Rsns, and the Vdd/Vss bypass
capacitor components wired tightly to the IC.

3. Place the QT1100A as close to the keys themselves as
possible.

4. Do not place electrodes or associated wiring near
other signals, or near a ground plane. If a ground plane
is unavoidable, keep the SNS tracks very thin (e.g.

2✜R

1

SNSCS

0.15mm) and relieve the ground plane widely around
them (e.g. 5mm clear space on all sides).

5. Do use a ground plane under and around the chip
itself, back to the regulator and power connector (but
not beyond the Rs/Cs/Rsns networks).

6. To prevent cross interference, do not place an
electrode or SNS traces of one QT1100A near the
electrode or the SNS traces of another QT1100A or
similar device, unless they are synchronized with a
Sync signal in a way that adjacent traces and keys do
not have acquisition bursts on them at the same time.

7. Keep the electrodes (and wiring) away from other
traces carrying AC or switched signals.

8. If there are switched LEDs or related wiring near an
electrode or SNS traces (e.g. for backlighting of a key),
bypass the switched traces to ground.

9. Use a voltage regulator just for the QT1100A to
eliminate noise coupling from other switching sources
via Vdd. Make sure the regulator’s transient load
stability provides for a stable, settled voltage just
before each burst commences.

2.10 Start-up Time

After a reset or power-up event, the device requires 400ms
to read the EEPROM, if one is connected, initialize the
device, and start acquiring signals. After this time, the part
will calibrate all keys. The calibration time depends on the
burst spacing but is about 450ms for a burst spacing of 3ms.
This time is proportional to the burst spacing (Section 4.14).
The burst spacing governs the time from the start of one key
acquisition cycle to the next, and can be set via serial Setups
or via the external EEPROM. Thus, the total start-up time
after a reset is about 850ms if the burst spacing is set to
3ms.

The device will communicate immediately after the Setup
block is loaded (from EEPROM. if any, or from defaults).

2.11 Operating Parameter Setups

The device features a Setups block area in internal RAM that
holds numerous configuration parameters determin ing how
the part will operate. Each key can be configured individually
for a wide variety of parameters as discussed in Section 4. In
addition, the device can be configured for the AKS ™ function
which treats participating keys as a group in which only the
key with the strongest signal will generate a response.

Standalone (with EEPROM) Setups: In standalone mode
with EEPROM, device setups are configured using an
external 93LC46A byte-mode EEPROM (see Table 1.2, page

5). This part can be programmed separately using a
commercially obtainable programm ing device then inserted
into the circuit, or, it can be programmed using a QT1100A in
serial mode via a PC interface with the 93LC46A in a socket
so that it can be transferred to the target PCB.

The EEPROM contents and default values are detailed in
Table 4-1, page 31. The last EEPROM entry should be a
CRC check byte. If the CRC byte is set to 0xD6, the CRC will
be ignored.

In standalone mode the EEPROM must have the first byte in
location 0 set to the value 0xD6 for the EEPROM to be read.
The rest of the Setup table must follow, starting at location 1
in the EEPROM.

LQ

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Copyright © 2003-2005 QRG Ltd

QT1100A-ISG R3.02/1105