Quantum ST32A011, Fireball ST 6.4AT Manual

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4 GB AT

Product Manual

February 1997

81-113133-01

Quantum reserves the right to make changes and improvements to its products, without incurring
any obligation to incorporate such changes or improvements into units previously sold or shipped.

You can request Quantum publications from your Quantum Sales Representative or order them
directly from Quantum.

Publication Number: 81-113133-01

UL/CSA/TUV/CE

UL standard 1950 recognition granted under File No. E78016
CSA standard C22.2 No. 950 certification granted under File No. LR49896
TUV Rheinland EN 60 950 granted under File No. R 9677196
Tested to FCC Rules for Radiated and Conducted Emissions, Part 15, Sub Part J, for Class-B

Equipment.

SERVICE CENTERS

Quantum Service Center Quantum Asia-Pacific Pte. Ltd.
715 Sycamore Avenue 50 Tagore Lane #b1-04
Milpitas, California 95035 Singapore, 2678
Phone: [phone] Phone: [phone]
Fax: [phone] Fax: [phone]
http://www.quantum.com

PATENTS

These products are covered by or licensed under one or more of the following U.S. Patents:
4,419,701; 4, 538,193 4,625,109; 4,639,798; 4,647,769; 4,647,997; 4,661,696; 4,669,004;
4,675,652; 4,703,176; 4,730,321; 4,772,974; 4,783,705; 4,819,153; 4,882,671; 4,920,442;
4,920,434; 4,982,296; 5,005,089; 5,027,241; 5,031,061; 5,084,791; 5,119,254; 5,160,865;
5,170,229; 5,177,771; Other U.S. and Foreign Patents Pending.

Copyright
This product or document is protected by copyright and distributed under licenses restricting its

use, copying, distribution, and decompilation. No part of this product or document may be
reproduced in any form by any means without prior written authorization of Quantum and its
licensors, if any.

RESTRICTED RIGHTS LEGEND: Use, duplication, or disclosure by the government is subject to
restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in Technical Data and Computer
Software clause at DFARS 252.227-7013 and FAR 52.227-19.

THIS PUBLICATION IS PROVIDED “AS IS’ WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS
OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.



1996 Quantum Corporation. All rights reserved. Printed in U.S.A.

Quantum Fireball ST, AutoTransfer, AutoRead, AutoWrite, DisCache, DiskWare, Defect Free
Interface, and WriteCache are trademarks of Quantum Corporation, and AIRLOCK and the Quantum
logo are registered trademarks of Quantum Corporation.
PC-AT is a registered trademark of International Business Machine.
MS-DOS is a registered trademark of Microsoft Corporation.

Table of Contents

Table of Contents

Chapter 1

ABOUT THIS MANUAL

1.1 AUDIENCE DEFINITION ............................................................................................................. 1-1

1.2 MANUAL ORGANIZATION ........................................................................................................ 1-1

1.3 TERMINOLOGY AND CONVENTIONS ...................................................................................... 1-1

1.4 REFERENCES ............................................................................................................................... 1-3

Chapter 2

GENERAL DESCRIPTION

2.1 PRODUCT OVERVIEW ................................................................................................................ 2-1

2.2 KEY FEATURES ........................................................................................................................... 2-1

2.3 STANDARDS AND REGULATIONS........................................................................................... 2-2

2.4 HARDWARE REQUIREMENTS................................................................................................... 2-3

Chapter 3
INSTALLATION

3.1 SPACE REQUIREMENTS............................................................................................................. 3-1

3.2 UNPACKING INSTRUCTIONS .................................................................................................... 3-2

3.3 HARDWARE OPTIONS................................................................................................................ 3-3

3.3.1 Cable Select (CS) Jumper .................................................................................................3-4

3.3.2 Drive Select (DS) Jumper .................................................................................................3-5

3.3.3 Jumper Parking (PK) Position .........................................................................................3-5

3.3.4 Reserved Position .............................................................................................................3-5

3.3.5 Master with Slave Present Jumper configuration ........................................................3-5

3.4 IDE BUS ADAPTER ..................................................................................................................... 3-6

3.4.1 40-Pin IDE Bus Connector ..............................................................................................3-6

3.4.2 Adapter Board ...................................................................................................................3-6

3.5 MOUNTING .................................................................................................................................. 3-7

3.5.1 Orientation ........................................................................................................................3-7

3.5.2 Clearance ...........................................................................................................................3-9

3.5.3 Ventilation .........................................................................................................................3-9

3.6 COMBINATION CONNECTOR (J1) ............................................................................................. 3-9

3.6.1 DC Power (J1, Section A) ..............................................................................................3-10

3.6.2 External Drive Activity LED ..........................................................................................3-10

3.6.3 IDE Bus Interface Connector (J1, Section C) ...............................................................3-10

3.7 FOR SYSTEMS WITH A MOTHERBOARD IDE ADAPTER................................................... 3-11

3.8 FOR SYSTEMS WITH AN IDE ADAPTER BOARD................................................................ 3-11

3.8.1 Adapter Board Installation ............................................................................................3-11

3.9 TECHNIQUES IN DRIVE CONFIGURATION........................................................................... 3-13

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT v

Table of Contents

3.9.1 Manual Partition Size in MS-DOS 4.0 and Above ....................................................3-13

3.9.2 1024 Cylinder Limitation on Older Computer Systems ............................................ 3-13

3.10 SYSTEM STARTUP AND OPERATION................................................................................... 3-14

Chapter 4

SPECIFICATIONS

4.1 SPECIFICATION SUMMARY ..................................................................................................... 4-1

4.2 FORMATTED CAPACITY ........................................................................................................... 4-3

4.3 DATA TRANSFER RATES.......................................................................................................... 4-3

4.4 TIMING SPECIFICATIONS ......................................................................................................... 4-4

4.5 POWER......................................................................................................................................... 4-5

4.5.1 Power Sequencing ........................................................................................................... 4-5

4.5.2 Power Reset Limits ........................................................................................................... 4-5

4.5.3 Power Requirements ........................................................................................................4-6

4.6 ACOUSTICS ................................................................................................................................. 4-7

4.7 MECHANICAL DIMENSIONS..................................................................................................... 4-8

4.8 ENVIRONMENTAL CONDITIONS.............................................................................................. 4-8

4.9 SHOCK AND VIBRATION .......................................................................................................... 4-9

4.10 RELIABILITY.............................................................................................................................. 4-10

4.11 DISK ERRORS............................................................................................................................ 4-10

Chapter 5

BASIC PRINCIPLES OF OPERATION

5.1 Quantum Fireball ST DRIVE MECHANISM............................................................................. 5-1

5.1.1 Base Casting Assembly .................................................................................................... 5-3

5.1.2 DC Motor Assembly ......................................................................................................... 5-3

5.1.3 Disk Stack Assemblies ..................................................................................................... 5-3

5.1.4 Headstack Assembly ........................................................................................................5-3

5.1.5 Rotary Positioner Assembly ........................................................................................... 5-3

5.1.6 Automatic Actuator Lock ................................................................................................ 5-3

5.1.7 Air Filtration .....................................................................................................................5-4

5.2 DRIVE ELECTRONICS................................................................................................................. 5-4

5.2.1 µ Controller ........................................................................................................................ 5-5

5.2.2 DCIIA ................................................................................................................................. 5-5

5.2.3 Read/Write ASIC .............................................................................................................. 5-8

5.2.4 PreAmplifier and Write Driver .......................................................................................5-9

5.3 SERVO SYSTEM........................................................................................................................ 5-10

5.3.1 General Description .......................................................................................................5-10

5.3.2 Servo Burst and Track Information ............................................................................. 5-10

5.4 READ AND WRITE OPERATIONS........................................................................................... 5-11

5.4.1 The Read Channel ..........................................................................................................5-11

5.4.2 The Write Channel .........................................................................................................5-11

5.4.3 Interface Control ............................................................................................................5-12

5.4.4 ID-Less Format ...............................................................................................................5-12

5.5 FIRMWARE FEATURES ........................................................................................................... 5-13

5.5.1 Disk Caching ...................................................................................................................5-13

5.5.2 Track and Cylinder Skewing ........................................................................................5-15

5.5.3 Error Detection and Correction ....................................................................................5-16

vi Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

5.5.4 Defect Management .......................................................................................................5-22

Chapter 6

IDE BUS INTERFACE AND ATA COMMANDS

6.1 INTRODUCTION........................................................................................................................... 6-1

6.2 SOFTWARE INTERFACE............................................................................................................. 6-1

6.3 MECHANICAL DESCRIPTION .................................................................................................... 6-1

6.3.1 Drive Cable and Connector .............................................................................................6-1

6.4 ELECTRICAL INTERFACE........................................................................................................... 6-2

6.4.1 IDE Bus Interface ..............................................................................................................6-2

6.4.2 Host Interface Timing ......................................................................................................6-9

6.5 REGISTER ADDRESS DECODING........................................................................................... 6-19

6.6 REGISTER DESCRIPTIONS ...................................................................................................... 6-21

6.6.1 Control Block Registers ..................................................................................................6-21

6.6.2 Command Block Registers .............................................................................................6-22

6.7 COMMAND DESCRIPTIONS.................................................................................................... 6-27

6.7.1 Recalibrate 1xh ...............................................................................................................6-27

6.7.2 Read Sectors 20h (with retry), 21h (without retry) ....................................................6-27

6.7.3 Write Sector 30h (with retry), 31h (without retry) .....................................................6-28

6.7.4 Read Verify Sectors 40h (with retry), 41h (without retry) ........................................6-28

6.7.5 Format Track 50h ...........................................................................................................6-28

6.7.6 Seek 7xh ..........................................................................................................................6-28

6.7.7 Execute Drive Diagnostic 90h .......................................................................................6-29

6.7.8 Initialize Drive Parameters 91h ....................................................................................6-30

6.7.9 SMART .............................................................................................................................6-30

6.7.10 Read Multiple C4h ..........................................................................................................6-41

6.7.11 Write Multiple C5h .........................................................................................................6-41

6.7.12 Set Multiple Mode C6h ..................................................................................................6-42

6.7.13 Read Buffer E4h ..............................................................................................................6-42

6.7.14 Write Buffer E8h .............................................................................................................6-42

6.7.15 Power Management Commands ...................................................................................6-42

6.7.16 Identify Drive ..................................................................................................................6-44

6.7.17 Set Features EFh .............................................................................................................6-49

6.7.18 Set Features (Ultra DMA/33) .........................................................................................6-49

6.7.19 Read Defect List ..............................................................................................................6-49

6.7.20 Configuration ..................................................................................................................6-52

6.8 ERROR REPORTING ................................................................................................................. 6-56

Table of Contents

Glossary.......................................................................................................................................G-1

Index............................................................................................................................................. I-1

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT vii

Table of Contents

List of Figures

FIGURE DESCRIPTION PAGE

Figure 3-1 Mechanical Dimensions of Quantum Fireball ST Hard Disk Drive............................... 3-1

Figure 3-2 Drive Packing Assembly...................................................................................................... 3-2

Figure 3-3 Jumper Locations for the Quantum Fireball ST Hard Disk Drive................................... 3-3

Figure 3-4 Jumper Locations on the Interface Connector.................................................................. 3-3

Figure 3-5 AT Connector and Jumper Location .................................................................................. 3-5

Figure 3-6 Mounting Dimensions for the Quantum Fireball ST Hard Disk Drives........................ 3-7

Figure 3-7 Mounting Screw Clearance for the Quantum Fireball ST Hard Disk Drives................. 3-8

Figure 3-8 J1 DC Power and IDE Bus Combination Connector......................................................... 3-9

Figure 3-9 Drive Power Supply and IDE Bus Interface Cables........................................................ 3-12

Figure 3-10 Completing the Drive Installation.................................................................................... 3-13

Figure 5-1 Quantum Fireball ST Hard Disk Drive Exploded View.................................................... 5-2

Figure 5-2 Quantum Fireball ST Hard Disk Drive Block Diagram..................................................... 5-4

Figure 5-3 DCIIA Block Diagram........................................................................................................... 5-5

Figure 5-4 Read/Write ASIC Block Diagram........................................................................................ 5-8

Figure 5-5 Sector Data Field with ECC Check Bytes......................................................................... 5-17

Figure 5-6 Byte Interleaving ................................................................................................................ 5-18

Figure 5-7 Correctable and Uncorrectable Double-Burst Errors...................................................... 5-19

Figure 5-8 Correctable and Uncorrectable Triple-Burst Errors........................................................ 5-20

Figure 5-9 Nine Correctable Random Burst Errors............................................................................ 5-21

Figure 6-1 PIO Interface Timing.......................................................................................................... 6-10

Figure 6-2 Multiword DMA Bus Interface Timing............................................................................. 6-11

Figure 6-3 Initiating a Data In Burst................................................................................................... 6-13

Figure 6-4 Sustained Data In Burst..................................................................................................... 6-13

Figure 6-5 Host Pausing a Data In Burst............................................................................................ 6-14

Figure 6-6 Device Terminating a Data In Burst................................................................................. 6-14

Figure 6-7 Host Terminating a Data In Burst..................................................................................... 6-15

Figure 6-8 Initiating a Data Out Burst................................................................................................ 6-16

Figure 6-9 Sustained Data Out Burst................................................................................................... 6-16

Figure 6-10 Device Pausing a Data Out Burst...................................................................................... 6-17

Figure 6-11 Host Terminating a Data Out Burst.................................................................................. 6-17

Figure 6-12 Device Terminating a Data out Burst............................................................................... 6-18

Figure 6-13 Host Interface RESET Timing............................................................................................ 6-18

viii Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

Table of Contents

List of Tables

TABLE

Table 3-1 AT Jumper Options............................................................................................................... 3-4

Table 3-2 J1 Power Connector, Section A........................................................................................ 3-10

Table 3-3 Logical Addressing Format............................................................................................... 3-15

Table 4-1 Specifications......................................................................................................................... 4-1

Table 4-2 Formatted Capacity............................................................................................................... 4-3

Table 4-3 Timing Specifications........................................................................................................... 4-4

Table 4-4 Power Reset Limits................................................................................................................ 4-5

Table 4-5 Typical Power and Current Consumption.......................................................................... 4-6

Table 4-6 Acoustical Characteristics—Sound Pressure....................................................................... 4-7

Table 4-7 Acoustical Characteristics—Sound Power.......................................................................... 4-7

Table 4-8 Environmental Specifications.............................................................................................. 4-8

Table 4-9 Shock and Vibration Specifications.................................................................................... 4-9

Table 4-10 Error Rates........................................................................................................................... 4-10

Table 5-1 ID-Less Controller Descriptor Format.............................................................................. 5-12

Table 5-2 Skews Offsets...................................................................................................................... 5-16

Table 6-1 Drive Connector Pin Assignments (J1, Section C)............................................................ 6-3

Table 6-2 Series Termination for Ultra DMA/33................................................................................ 6-6

Table 6-3 Signal Line Definitions......................................................................................................... 6-7

Table 6-4 Interface Signal Name Assignments................................................................................... 6-8

Table 6-5 PIO Host Interface Timing.................................................................................................... 6-9

Table 6-6 Multiword DMA Host Interface Timing........................................................................... 6-10

Table 6-7 Ultra DMA Data Transfer Timing Requirements............................................................ 6-11

Table 6-8 Host Interface RESET Timing............................................................................................ 6-18

Table 6-9 I/O Port Functions and Selection Addresses................................................................... 6-19

Table 6-10 Command Block Register Initial Values.......................................................................... 6-20

Table 6-11 Device Control Register Bits ............................................................................................. 6-21

Table 6-12 Drive Address Register Bits............................................................................................... 6-22

Table 6-13 Error Register Bits.............................................................................................................. 6-23

Table 6-14 Drive Head Register Bits.................................................................................................... 6-24

Table 6-15 Status Register Bits ............................................................................................................ 6-25

Table 6-16 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT Command Codes and Parameters........ 6-26

Table 6-17 Diagnostic Codes................................................................................................................ 6-29

Table 6-18 Device attribute thresholds data structure...................................................................... 6-35

Table 6-19 Individual threshold data structure.................................................................................. 6-35

Table 6-20 Device attributes data structure ....................................................................................... 6-37

Table 6-21 Individual attribute data structure................................................................................... 6-37

Table 6-22 Valid Count Range............................................................................................................. 6-44

Table 6-23 Identify Drive Parameters ................................................................................................. 6-46

Table 6-24 Transfer/Mode Values........................................................................................................ 6-49

Table 6-25 READ DEFECT LIST LENGTH Command Bytes.............................................................. 6-50

Table 6-26 AT READ DEFECT LIST Command Bytes........................................................................ 6-50

Table 6-27 DEFECT LIST DATA FORMAT .......................................................................................... 6-51

Table 6-28 DEFECT ENTRY DATA FORMAT...................................................................................... 6-51

DESCRIPTION

PAGE

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT ix

Table of Contents

Table 6-29 Accessing the READ CONFIGURATION Command........................................................ 6-52

Table 6-30 Accessing the SET CONFIGURATION Command............................................................ 6-53

Table 6-31 Accessing the SET CONFIGURATION WITHOUT SAVING TO DISK Command ......... 6-54

Table 6-32 Configuration Command Format...................................................................................... 6-54

Table 6-33 Command Errors................................................................................................................. 6-56

x Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

Chapter 1

ABOUT THIS MANUAL

This chapter gives an overview of the contents of this manual, including the intended
audience, how the manual is organized, terminology and conventions, and references.

1.1 AUDIENCE DEFINITION

The Quantum Fireball ST  1.6/2.1/3.2/4.3/6.4AT Product Manual is intended for several
audiences. These audiences include: the end user, installer, developer, original equipment
manufacturer (OEM), and distributor. The manual provides information about
installation, principles of operation, interface command implementation, and
maintenance.

1.2 MANUAL ORGANIZATION

This manual is organized into the following chapters:

• Chapter 1 – About This Manual

• Chapter 2 – General Description

• Chapter 3 – Installation

• Chapter 4 – Specifications

• Chapter 5 – Basic Principles of Operation

• Chapter 6 – IDE Bus Interface and ATA Commands

1.3 TERMINOLOGY AND CONVENTIONS

In the Glossary at the back of this manual, you can find definitions for many of the terms
used in this manual. In addition, the following abbreviations are used in this manual:

• ASIC application-specific integrated circuit

• ATA advanced technology attachment

• bpi bits per inch

• dB decibels

• dBA decibels, A weighted

• ECC error correcting code

• fci flux changes per inch

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 1-1

About This Manual

• Hz hertz

• KB kilobytes

• LSB least significant bit

• mA milliamperes

• MB megabytes (1 MB = 1,000,000 bytes when referring to disk
storage and 1,048,576 bytes in all other cases)

• Mbit/s megabits per second

• MB/s megabytes per second

• MHz megahertz

• ms milliseconds

• MSB most significant bit

• mv millivolts

• ns nanoseconds

• tpi tracks per inch

• µ s microseconds

• V volts

The typographical and naming conventions used in this manual are listed below.
Conventions that are unique to a specific table appear in the notes that follow that table.

Typographical Conventions:

• Names of Bits: Bit names are presented in initial capitals. An example is
the Host Software Reset bit.

• Commands: Firmware commands are listed in all capitals. An example is
WRITE LONG.

• Register Names: Registers are given in this manual with initial capitals. An
example is the Alternate Status Register.

• Parameters: Parameters are given as initial capitals when spelled out, and
are given as all capitals when abbreviated. Examples are Prefetch Enable
(PE), and Cache Enable (CE).

• Hexadecimal Notation: The hexadecimal notation is given in 9-point
subscript form. An example is 30

.

H

• Signal Negation: A signal name that is defined as active low is listed with
a minus sign following the signal. An example is RD–.

• Messages: A message that is sent from the drive to the host is listed in all
capitals. An example is ILLEGAL COMMAND.

1-2 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

Naming Conventions:

• Host: In general, the system in which the drive resides is referred to as the
host.

• Computer Voice: This refers to items you type at the computer keyboard.
These items are listed in 10-point, all capitals, Courier font. An example is

FORMAT C:/S.

1.4 REFERENCES

For additional information about the AT interface, refer to:

• IBM Technical Reference Manual #6183355, March 1986.

• ATA Common Access Method Specification, Revision 4.0.

About This Manual

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 1-3

About This Manual

1-4 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 2-1

Chapter 2

GENERAL DESCRIPTION

This chapter summarizes the general functions and key features of the Quantum Fireball
ST 1.6/2.1/3.2/4.3/6.4AT hard disk drives, as well as the applicable standards and
regulations.

2.1 PRODUCT OVERVIEW

Quantum’s Fireball ST hard disk drives are part of a family of high performance, 1-inch­high hard disk drives manufactured to meet the highest product quality standards.

These hard disk drives use nonremovable, 3 1/2-inch hard disks and are available
either an ATA interface or Small Computer System Interface (SCSI-2, 3). A Quantum
Fireball ST 1.6/2.1/3.2/4.3/6.4AT hard disk drive is compatible with systems that
provide the IDE interface. The Quantum Fireball ST 1.6 GB model is available only
with the AT interface.

The Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT hard disk drives feature an embedded
hard disk drive controller, and use ATA commands to optimize system performance.
Because the drive manages media defects and error recovery internally, these operations
are fully transparent to the user.

The innovative design of the Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT hard disk drives
enables Quantum to produce a family of high-performance, high-reliability drives.

2.2 KEY FEATURES

The Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT hard disk drives include the following key
features:

General

• Formatted storage capacity of 1.6 GB (1 disk, 2 heads), 2.1 GB (2 disks, 3
heads), 3.2 GB (2 disks, 4 heads), 4.3 GB (3 disks, 6 heads), and 6.4 GB (4 disks,
8 heads)

• Low profile, 1-inch height

• Industry standard 3 1/2-inch form factor

• Emulation of IBM
commands

Performance



PC AT



task file register, and all AT fixed disk

• Average seek time of <10.0 ms

• Average rotational latency of 5.56 ms

General Description

• New Ultra ATA interface with Quantum-patented Ultra DMA/33 protocol
supporting burst data transfer rates of 33 MB/s.

• 128K buffer with 87 K dynamic segmentation cache. Look-ahead DisCache
feature with continuous prefetch and WriteCache write-buffering
capabilities

• AutoTask Register update, Multi-block AutoRead, and Multi-block
AutoWrite features in a custom ASIC

• Read-on-arrival firmware

• Triple burst ECC, and double burst ECC on-the-fly

• 1:1 interleave on read/write operations

• Support of all standard ATA data transfer modes with PIO mode 4 and
multiword DMA mode 2

Reliability

• 400,000 hours mean time between failure (MTBF) in the field

• Automatic retry on read errors

• 224-bit, interleaved Reed-Solomon Error Correcting Code (ECC), with cross
checking correction up to four separate bursts of 32 bits each totalling up
to 96 bits in length

• S.M.A.R.T. support (Self-Monitoring, Analysis and Reporting Technology)

• Patented Airlock



automatic shipping lock and dedicated landing zone

• Transparent media defect mapping

• High performance, in-line defective sector skipping

• Adaptive cache segmentation

• Reassignment of defective sectors discovered in the field, without reformatting

Versatility

• Power saving modes

• Downloadable firmware

• Cable select feature

• Ability to daisy-chain two drives on the interface

2.3 STANDARDS AND REGULATIONS

The Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT hard disk drives satisfy the following
standards and regulations:

• Underwriters Laboratory (U.L.): Standard 1950. Information technology
equipment including business equipment.

• Canadian Standards Association (CSA): Standard C22.2 No. 950-M93.
Information technology equipment including business equipment.

• European Standards (TUV): Standard EN 60 950 and IEC 950. Information
technology equipment including business equipment.

2-2 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

• Federal Communications Commission (FCC): FCC Rules for Radiated and
Conducted Emissions, Part 15, Sub Part J, For Class B Equipment.

• CISPR: CISPR 22 Rules for Radiated and Conducted Emissions, for Class B
Equipment.

• Drives comply with European Union (EU) for application of CE mark.

2.4 HARDWARE REQUIREMENTS

The Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT hard disk drives are compatible with the
IBM PC AT, and other computers that are compatible with the IBM PC AT. It connects to
the PC either by means of a third-party IDE-compatible adapter board, or by plugging a
cable from the drive directly into a PC motherboard that supplies an IDE interface.

General Description

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 2-3

General Description

2-4 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

Chapter 3

INSTALLATION

This chapter explains how to unpack, configure, mount, and connect the Quantum
Fireball ST 1.6/2.1/3.2/4.3/6.4AT hard disk drive prior to operation. It also explains how
to start up and operate the drive.

3.1 SPACE REQUIREMENTS

The Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT hard disk drives are shipped without a
faceplate. Figure 3-1 shows the external dimensions of the Quantum Fireball ST 1.6/

2.1/3.2/4.3/6.4AT drives.

25.4 mm
(1.00 inches)

146.1 mm
(5.75 inches)

101.6 mm
(4.00 inches)

Figure 3-1

Mechanical Dimensions of Quantum Fireball ST Hard Disk Drive

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 3-1

Installation

3.2 UNPACKING INSTRUCTIONS

CAUTION: The maximum limits for physical shock can be exceeded if the

drive is not handled properly. Special care should be
taken not to bump or drop the drive. It is highly recommended
that Quantum Fireball ST drives are not stacked or placed on any
hard surface after they are unpacked. Such handling could cause
media damage.

1. Open the shipping container and remove the packing assembly that contains
the drive.

2. Remove the drive from the packing assembly.

CAUTION: During shipment and handling, the antistatic electrostatic dis-

charge (ESD) bag prevents electronic component
damage due to electrostatic discharge. To avoid accidental damage
to the drive, do not use a sharp instrument to open the ESD bag.
Save the packing materials for possible future use.

3. When you are ready to install the drive, remove it from the ESD bag.

Figure 3-2 shows the packing assembly for a single Quantum Fireball ST 1.6/2.1/3.2/

4.3/6.4AT hard disk drive. A 12-pack shipping container is available for multiple drive
shipments.

Upper Pad

Hard Disk

Drive

Lower Pad

Container

Figure 3-2

Drive Packing Assembly

3-2 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

Installation

3.3 HARDWARE OPTIONS

The configuration of a Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT hard disk drive
depends on the host system in which it is to be installed. This section describes the
hardware options that you must take into account prior to installation. Figure 3-3
shows the printed circuit board (PCB) assembly, indicating the jumpers that control
some of these options.

DC Power
Connector

Jumpers

IDE Bus

Interface Header

Figure 3-3

Back
of
Drive

Jumper Locations for the Quantum Fireball ST Hard Disk Drive

RSVD

PK

Jumper Configurations

Master

CS

GND

Default
Setting

Back of Drive

CS

DS

Slave Cable Select

CS

GNDDSGND

Jumper
shown in
Parking
Position

Reserved
Position

AT Interface Connector

DS

GND

Front
of
Drive

Figure 3-4

Jumper Locations on the Interface Connector

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 3-3

Installation

The configuration of the following four jumpers controls the drive’s mode of operation:

• CS – Cable Select

• DS – Drive Select

• PK– Jumper Parking Position (Slave mode)

The AT PCB has two jumper locations provided for configuration options in a system.
These jumpers are used to configure the drive for master/slave operation in a system.
The default configuration for the drive as shipped from the factory is with a jumper
across the DS location, and open positions in the CS and PK positions.

Table 3-1 defines the operation of the jumpers and their function relative to pin 28 on
the interface. 1 indicates that the specified jumper is installed; 0 indicates that the
jumper is not installed.

Table 3-1

CS DS PK Pin 28 DESCRIPTION

0 0 X X Drive configured as a slave.
0 1 X X Drive configured as a Master.
1 0 X Open Drive configured as a slave.
1 0 X Gnd Drive configured as a Master.

Note: In Table 3-1, a 0 indicates that the jumper is removed, a 1 indicates

that the jumper is installed, and an X indicates that the jumper set­ting does not matter.

AT

Jumper Options

3.3.1 Cable Select (CS) Jumper

When two Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT hard disk drives are daisy­chained together, they can be configured as Master or Slave either by the CS or DS
jumpers. To configure the drive as a Master or Slave with the CS feature, the CS jumper
is installed (1).

Once you install the CS jumper, the drive is configured as a Master or Slave by the state
of the Cable Select signal: pin 28 of the IDE bus connector. Please note that pin 28 is a
vendor-specific pin that Quantum is using for a specific purpose. More than one
function is allocated to CS, according to the ATA CAM specification (see reference to
this specification in Chapter 1). If pin 28 is a 0 (grounded), the drive is configured as a
Master. If it is a 1 (high), the drive is configured as a Slave. In order to configure two
drives in a Master/Slave relationship using the CS jumper, you need to use a cable that
provides the proper signal level at pin 28 of the IDE bus connector. This allows two
drives to operate in a Master/Slave relationship according to the drive cable placement.

3-4 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

3.3.2 Drive Select (DS) Jumper

You can also daisy-chain two drives on the IDE bus interface by using their Drive Select
(DS) jumpers. To use the DS feature, the CS jumper must be removed.

To configure a drive as the Master (Drive 0), a jumper must be installed on the DS pins.
The Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT hard disk drives are shipped from the

factory as a Master (Drive 0 - DS jumper installed). To configure a drive as a Slave
(Drive 1), the DS jumper must be removed. In this configuration, the spare jumper
removed from the DS position may be stored on the PK jumper pins.

Note: The order in which drives are connected in a daisy chain has no sig-

nificance.

3.3.3 Jumper Parking (PK) Position

The PK position is used as a holding place for the jumper for a slave drive in systems
that do not support Cable Select. The pins used for the parking position are vendor
unique. The drive will bias the parking position pins to detect the presence of this
jumper. When doing so it will maintain a minimum impedance of 4.7 K Ω to the +5 volt
supply and 2.4K Ω to ground.

Installation

3.3.4 Master with Slave Present Jumper configuration

In combination with the current DS or CS jumper settings, the Slave Present (SP) jumper
can be implemented if necessary as follows:

• When the drive is configured as a Master

(

DS jumper installed or CS jumper
installed, and the Cable Select signal is set to ( 0 ), adding an additional
jumper (both jumpers DS and CS now installed) will indicate to the drive
that a Slave drive is present. This Master with Slave Present jumper
configuration should be installed on the Master drive only if the Slave drive
does not use the Drive Active/Slave Present (DASP–) signal to indicate its
presence.

3.3.5 Reserved Position

The unused position, RSVD, may also be used as a jumper parking position, if desired.

Pin 1 Pin 1

7.22±0.50
(to pin center)

45.02±0.50

(to pin center)

Pin 1 of AT Connector

29.78±0.50
(to pin center)

Connector Side

C

L

4.55±0.50

Figure 3-5

AT Connector and Jumper Location

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 3-5

Installation

3.4 IDE BUS ADAPTER

There are two ways you can configure a system to allow the Quantum Fireball ST 1.6/

2.1/3.2/4.3/6.4AT hard disk drives to communicate over the IDE bus of an IBM or IBM­compatible PC:

1. Connect the drive to a 40-pin IDE bus connector (if available) on the motherboard of
the PC.

2. Install an IDE-compatible adapter board in the PC, and connect the drive to the
adapter board.

3.4.1 40-Pin IDE Bus Connector

Most PC motherboards have a built-in 40-pin IDE bus connector that is compatible with
the 40-pin IDE interface of the Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT hard disk
drives. If the motherboard has an IDE connector, simply connect a 40-pin ribbon cable
between the drive and the motherboard.

You should also refer to the motherboard instruction manual, and refer to Chapter 6 of
this manual to ensure signal compatibility.

3.4.2 Adapter Board

If your PC motherboard does not contain a built-in 40-pin IDE bus interface connector,
you must install an IDE bus adapter board and connecting cable to allow the drive to
interface with the motherboard. Quantum does not supply such an adapter board, but
they are available from several third-party vendors.

Please carefully read the instruction manual that comes with your adapter board, as
well as Chapter 6 of this manual to ensure signal compatibility between the adapter
board and the drive. Also, make sure that the adapter board jumper settings are
appropriate.

3-6 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

3.5 MOUNTING

Drive mounting orientation, clearance, and ventilation requirements are described in
the following subsections.

3.5.1 Orientation

The mounting holes on the Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT hard disk drives
allow the drive to be mounted in any orientation. Figures 3-6 and 3-7 show the location
of the three mounting holes on each side of the drive. The drive can also be mounted
using the four mounting hole locations on the PCB side of the drive.

Note: It is highly recommended that the drive is hard mounted on to the

chassis of the system being used for general operation, as well as
for test purposes. Failure to hard mount the drive can result in er­roneous errors during testing.

All dimensions are in millimeters. For mounting, #6-32 UNC screws are recommended.

Installation

146.1
± 0.6

25.4

± 0.5

60.0

± 0.2

16.00
± 0.4

101.60
± 0.2

6.35 ± 0.2

60.33
± 0.5

44.45

± 0.5

3.05 ± 0.5

95.5

± 0.30

101.6
± 0.6

Figure 3-6

Mounting Dimensions for the Quantum Fireball ST Hard Disk Drives

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 3-7

Installation

6.35 mm Maximum
(0.25 Inches)

Figure 3-7

CAUTION: The PCB is very close to the mounting holes. Do not exceed the

6.35 mm Maximum (0.25 Inches)

Drive

Mounting

Screw

Printed­Circuit
Board

Head/Disk

Assembly

Printed­Circuit
Board

Mounting Screw Clearance for the Quantum Fireball ST Hard Disk Drives

specified length for the mounting screws. The specified screw
length allows full use of the mounting hole threads, while avoiding
damaging or placing unwanted stress on the PCB. Figure 3-7
specifies the minimum clearance between the PCB and the screws
in the mounting holes. To avoid stripping the mounting hole
threads, the maximum torque applied to the screws must not
exceed 8 inch-pounds. A maximum screw length of 0.25 inches may
be used.

3-8 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

3.5.2 Clearance

Clearance from the drive to any other surface (except mounting surfaces) must be a
minimum of 1.25 mm (0.05 inches).

3.5.3 Ventilation

The Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT hard disk drives operate without a
cooling fan, provided the ambient air temperature does not exceed 131 ° F (55 ° C) at any
point along the drive form factor envelope.

3.6 COMBINATION CONNECTOR (J1)

J1 is a three-in-one combination connector. The drive’s DC power can be applied to
section A. The IDE bus interface (40-pin) uses section C. The connector is mounted on
the back edge of the printed-circuit board (PCB), as shown in Figure 3-8.

Installation

Center

Key Slot

Pin 40

Figure 3-8

Pin 1

J1 IDE (40-Pin)/DC (4-Pin)

Combination Connector

40-Pin IDE

(J1 Section C)

Pin 1

4-Pin DC Power

(J1 Section A)

4321

J1 DC Power and IDE Bus Combination Connector

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 3-9

Installation

3.6.1 DC Power (J1, Section A)

The recommended mating connectors for the +5 VDC and +12 VDC input power are
listed in Table 3-2.

Table 3-2

PIN

NUMBER

J1 Section A (4-Pin):

1 +12 VDC 4-Pin Connector:
2 Ground

3 Ground

4 +5 VDC

VOLTAGE

LEVEL

Return for
+12 VDC

Return for +5
VDC

Note: Labels indicate the pin numbers on the connector. Pins 2 and 3 of

section A are the +5 and +12 volt returns and are connected togeth­er on the drive.

J1 Power Connector, Section A

MATING CONNECTOR TYPE AND PART NUMBER

AMP P/N 1-480424-0

Loose piece contacts:

AMP P/N VS 60619-4

Strip contacts:

AMP P/N VS 61117-4

3.6.2 External Drive Activity LED

An external drive activity LED may be connected to the DASP-I/O pin 39 on J1. For
more details, see the pin description in Table 6-1.

(OR EQUIVALENT)

3.6.3 IDE Bus Interface Connector (J1, Section C)

On the Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT hard disk drives, the IDE bus
interface cable connector (J1, section C) is a 40-pin Universal Header, as shown in
Figure 3-8.

To prevent the possibility of incorrect installation, the connector has been keyed by
removing Pin 20. This ensures that a connector cannot be installed upside down.

See Chapter 6, “IDE Bus Interface and ATA Commands,” for more detailed information
about the required signals. Refer to Table 6-1 for the pin assignments of the IDE bus
connector (J1, section C).

3-10 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

3.7 FOR SYSTEMS WITH A MOTHERBOARD IDE ADAPTER

You can install the Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT hard disk drives in an
AT-compatible system that contains a 40-pin IDE bus connector on the motherboard.

To connect the drive to the motherboard, use a 40-pin ribbon cable 18 inches in length
or shorter. Ensure that pin 1 of the drive is connected to pin 1 of the motherboard
connector.

3.8 FOR SYSTEMS WITH AN IDE ADAPTER BOARD

To install the Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT hard disk drive in an AT­compatible system without a 40-pin IDE bus connector on its motherboard, you need a
third-party IDE-compatible adapter board.

3.8.1 Adapter Board Installation

Carefully read the manual that accompanies your adapter board before installing it.
Make sure that all the jumpers are set properly and that there are no address or signal
conflicts. You must also investigate to see if your AT-compatible system contains a
combination floppy and hard disk controller board. If it does, you must disable the hard
disk drive controller functions on that controller board before proceeding.

Installation

Once you have disabled the hard disk drive controller functions on the floppy/hard
drive controller, install the adapter board. Again, make sure that you have set all jumper
straps on the adapter board to avoid addressing and signal conflicts.

Note: For Sections 3.7 and 3.8, power should be turned off on the com-

puter before installing the drive.

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 3-11

Installation

3.8.1.1 Connecting the Adapter Board and the Drive

Use a 40-pin ribbon cable to connect the drive to the board. See Figure 3-9. To connect
the drive to the board:

1. Insert the 40-pin cable connector into the mating connector of the adapter board.
Make sure that pin 1 of the connector matches with pin 1 on the cable.

2. Insert the other end of the cable into the header on the drive. When inserting
this end of the cable, make sure that pin 1 of the cable connects to pin 1 of the
drive connector.

3. Secure the drive to the system chassis by using the mounting screws, as shown
in Figure 3-10.

Pin 1

IDE-Bus
Interface Cable

Power Supply Cable

IDE-Bus
Interface
Connector

40-Pin Header

(3-Pin or 4-Pin)

Key Slot

DC Power
Connector

Bevel

Figure 3-9

Drive Power Supply and IDE Bus Interface Cables

3-12 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

Mounting Holes

IDE-Bus
Interface Cable

Side View

of Bay

Installation

Mounting
Bracket

Mounting Screws
(2 on each side)

Figure 3-10

Completing the Drive Installation

3.9 TECHNIQUES IN DRIVE CONFIGURATION

3.9.1 Manual Partition Size in MS-DOS 4.0 and Above

When using MS-DOS 4.0 and above, FDISK allows the user to partition a hard drive
with a total capacity of 4 GB (4,294,967, 296 bytes). However, the file allocation table
(FAT) only supports partition size of 2 GB (2, 147, 483, 648 bytes). Therefore, a hard
drive between the sizes of 2 and 4 GB must be divided into multiple partitions, each not
exceeding 2 GB.

3.9.2 1024 Cylinder Limitation on Older Computer Systems

Because the MS-DOS operating system uses the computer’s ROM BIOS to access the
hard drive, it is limited to viewing 1024 cylinders by the AT ROM BIOS. The CMOS
System Setup is able to scan the total number of cylinders, but the BIOS is still limited
to using only 1024 cylinders. Listed below are some techniques to resolve this difficulty.

• Use a third party software program that translates the hard drive
parameters to an acceptable configuration for MS-DOS.

• Use a hard disk controller that translates the hard drive parameters to an
appropriate setup for both MS-DOS, and the computer system’s ROM BIOS.

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 3-13

Installation

3.10 SYSTEM STARTUP AND OPERATION

Once you have installed the Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT hard disk drive,
and adapter board (if required) in the host system, you are ready to partition and format
the drive for operation. To set up the drive correctly, follow these steps:

1. Power on the system.

2. Run the SETUP program. This is generally on a Diagnostics or Utilities disk, or
within the system’s BIOS.

3. Enter the appropriate parameters.

The SETUP program allows you to enter the types of optional hardware installed—such
as the hard disk drive type, the floppy disk drive capacity, and the display adapter type.
The system’s BIOS uses this information to initialize the system when the power is
switched on. For instructions on how to use the SETUP program, refer to the system
manual for your PC.

During the AT system CMOS setup, you must enter the drive type for the Quantum
Fireball ST 1.6/2.1/3.2/4.3/6.4AT hard disk drives. The drive supports the translation of
its physical drive geometry parameters such as cylinders, heads, and sectors per track
to a logical addressing mode. The drive can work with different BIOS drive-type tables
of the various host systems.

You can choose any drive type that does not exceed the capacity of the drive. Table 3-3
gives the logical parameters that provide the maximum capacity on the Quantum
Fireball ST 1.6/2.1/3.2/4.3/6.4AT hard disk drives.

3-14 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

Installation

Table 3-3

LBA Capacity 1.6 GB 2.1 GB 3.2 GB 4.3 GB 6.4 GB
CHS Capacity 1,614 MB 2,111 MB 3,228 MB 4,310 MB 6,448 MB
Logical Cylinders 3128 4092 6256 14,848 13,328
Logical Heads 16 16 16 9 15
Logical Sectors/Track 63 63 63 63 63
Total Number Logical Sectors 3,153,024 4,124,736 6,306,048 8,418,816 12,594,960

Note: * The AT capacity is artificially limited to a 2.1 GB partition boundary.

To match the logical specifications of the drive to the drive type of a particular BIOS,
consult the system’s drive-type table. This table specifies the number of cylinders,
heads, and sectors for a particular drive type.

Note: The BIOS of some systems may not support a logical cylinder value

greater than 1,024, as is needed for taking advantage of the maxi­mum capacity of a Quantum Fireball ST 2.1AT hard disk drive. For
such systems, use a device driver, or run in LBA mode if the system
BIOS supports it.

Logical Addressing Format

QUANTUM FIREBALL ST

1.6 2.1 3.2 4.3 6.4

You must choose a drive type that meets the following requirements:
For the 1.6AT:

Logical Cylinders x Logical Heads x Logical Sectors/Track x 512 <= 3,153,024

For the 2.1AT:

Logical Cylinders x Logical Heads x Logical Sectors/Track x 512 <= 4,124,736

For the 3.2AT:

Logical Cylinders x Logical Heads x Logical Sectors/Track x 512 <= 6,306,048

For the 4.3AT:

Logical Cylinders x Logical Heads x Logical Sectors/Track x 512 <= 8,418,816

For the 6.4AT:

Logical Cylinders x Logical Heads x Logical Sectors/Track x 512 <= 12,594,960

4. Boot the system using the operating system installation disk—for example,

MS-DOS —then follow the installation instructions in the operating system

manual.

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 3-15

Installation

If you are using a version of MS-DOS below 4.01:

1. Run FDISK or a third-party partitioning program.

Note: If you use DOS version 3.2 or an earlier version, the DOS partition

will employ only 32 MB (33,554,432 bytes) of the drive’s capacity.
With DOS 3.3, you can partition the drive in multiples of 32 MB. If
you use DOS 4.01 or later, or if you use a third-party partitioning
program, you can create partitions that exceed 32 MB.

2. To format the drive with a high-level format, and to transfer the operating
system to the drive, type FORMAT C:/S . Once this command executes, you can
boot the system from the hard drive.

Note: The drive is shipped from the factory with a low-level format;

therefore, a low-level format is not required.

3-16 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

Chapter 4

SPECIFICATIONS

This chapter gives a detailed description of the physical, electrical, and environmental
characteristics of the Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT hard disk drives.

4.1 SPECIFICATION SUMMARY

Table 4-1 gives a summary of the Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT hard disk
drives.

Table 4-1 Specifications

QUANTUM FIREBALL ST

DESCRIPTION

1.6AT 2.1AT 3.2AT 4.3AT 6.4AT

Formatted Capacity 1614 MB 2111 MB 3228 MB 4310 MB 6448 MB
Nominal rotational speed (rpm) 5,400 5,400 5,400 5,400 5,400
Number of Disks 12234
Number of R/W heads 23468
Data Organization:

Zones per surface 15 15 15 15 15
Tracks per surface 7,066 7,066 7,066 7,066 7,066
Total tracks 14,132 21,198 28,264 42,396 56,528

Sectors per track:

Inside zone 160 144 154 143 154
Outside zone 273 252 277 239 277
Total User Sectors 3,153,024 4,124,736 6,306,048 8,418,816 12,594,960
Bytes per sector 512 512 512 512 512
Number of tracks per

cylinder

Recording:

Recording technology Multiple

Maximum linear density 168,650 fci 152,390 fci 168,650 fci 152,390 fci 168,650 fci

Encoding method 16/17 PRML 16/17 PRML 16/17 PRML 16/17 PRML 16/17 PRML

Interleave 1:1 1:1 1:1 1:1 1:1

23468

Zone

Multiple

Zone

Multiple

Zone

Multiple

Zone

Multiple

Zone

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 4-1

Specifications

QUANTUM FIREBALL ST

DESCRIPTION

1.6AT 2.1AT 3.2AT 4.3AT 6.4AT

Track density 7,777 tpi 7,777 tpi 7,777 tpi 7,777 tpi 7,777 tpi
Maximum effective

areal density

1230

Mbits/in

2

1115

Mbits/in

2

1230

Mbits/in

2

1115

Mbits/in

2

Performance:

Seek times:

Read-on-arrival 10.0 ms typ.

12.0 ms max.

Track-to-track 2.0 ms

typical

Average write 11.0 ms typ.

13.0 ms max.

Full stroke 20.0 ms typ.

24.0 ms max.

10.0 ms typ.

12.0 ms max.

2.0 ms
typical

11.0 ms typ.

13.0 ms max.

20.0 ms typ.

24.0 ms max.

10.0 ms typ.

12.0 ms max.

2.0 ms
typical

11.0 ms typ.

13.0 ms max.

20.0 ms typ.

24.0 ms max.

10.0 ms typ.

12.0 ms max.

2.0 ms
typical

11.0 ms typ.

13.0 ms max.

20.0 ms typ.

24.0 ms max.

Data transfer Rates:

Disk to Read Buffer

Read Buffer to IDE Bus
(PIO Mode with IORDY)

Read Buffer to IDE Bus
(Ultra A T A Mode)

1

78 Mb/sec.

minimum

132 Mb/sec.

maximum

16.7 MB/sec.
max.

33 MB/sec.

max.

70 Mb/sec.

minimum

119 Mb/sec.

maximum

16.7 MB/sec.
max.

33 MB/sec.

max.

78 Mb/sec.

minimum

132 Mb/sec.

maximum

16.7 MB/sec.
max.

33 MB/sec.

max.

70 Mb/sec.

minimum

119 Mb/sec.

maximum

16.7 MB/sec.
max.

33 MB/sec.

max.

Buffer Size 128 KB 128 KB 128 KB 128 KB 128 KB
Reliability:

Seek error rate

2

Unrecoverable error rate

Error correction method
(with cross check)

2

1 in 10

14

1 in 10

224-bit

Reed

Solomon

6

1 in 10

14

1 in 10

224-bit

Reed

Solomon

6

1 in 10

Solomon

1 in 10

224-bit

Reed

6

14

1 in 10

1 in 10

6

14

224-bit

Reed

Solomon

Projected MTBF 400,000 hrs 400,000 hrs 400,000 hrs 400,000 hrs 400,000 hrs

Contact Start/Stop Cycles

3

40,000 min. 40,000 min. 40,000 min. 40,000 min. 40,000 min.

(Ambient temperature)

Auto head-park method AirLock 

AirLock AirLock AirLock AirLock

1230

Mbits/in

2

10.0 ms typ.

12.0 ms max.

2.0 ms
typical

11.0 ms typ.

13.0 ms max.

20.0 ms typ.

24.0 ms max.

78 Mb/sec.

minimum

132 Mb/sec.

maximum

16.7 MB/sec.
max.

33 MB/sec.

max.

6

1 in 10

14

1 in 10

224-bit

Reed

Solomon

1. Disk to read buffer transfer rate is zone-dependent.

2. Refer to Section 4.11, “DISK ERRORS” for details on error rate definitions.

3. CSS specifications assumes a duty cycle of one power off operation for every one
idle spin down.

4-2 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

Specifications

4.2 FORMATTED CAPACITY

At the factory, the Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT hard disk drives receive a
low-level format that creates the actual tracks and sectors on the drive. Table 4-2 shows
the capacity resulting from this process. Formatting done at the user level, for operation
with DOS, UNIX, or other operating systems, will result in less capacity than the physical
capacity shown in Table 4-2.

Table 4-2 Formatted Capacity

QUANTUM FIREBALL ST

1.6AT 2.1AT 3.2AT 4.3AT 6.4AT

Formatted Capacity 1614 MB 2111 MB 3228 MB 4310 MB 6448 MB
Number of 512-byte

sectors available

Note: * The AT capacity is artificially limited to a 2.1 GB partition boundary.

3,153,024 4,124,736 6,306,048 8,418,816 12,594,960

4.3 DATA TRANSFER RATES

Data is transferred from the disk to the read buffer at a rate of up to 132 Mb/s in bursts.
Data is transferred from the read buffer to the IDE bus at a rate of up to 16.67 MB/s
using programmed I/O with IORDY, or at a rate of up to 33 MB/s using Ultra DMA/33.
For more detailed information on interface timing, refer to Chapter 6.

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 4-3

Specifications

4.4 TIMING SPECIFICATIONS

Table 4-3 illustrates the timing specifications of the Quantum Fireball ST 1.6/2.1/3.2/4.3/

6.4AT hard disk drives.

Table 4-3 Timing Specifications

PARAMETER

Sequential Cylinder Skew Time
Sequential Head Skew Time

4

TYPICAL

NOMINAL

3

3.7 ms 3.7 ms

1

WORST

CASE

2

Quantum Fireball ST 1.6, 2.1, & 3.2 GB 3.7 ms 3.7 ms

Quantum Fireball ST 4.3 and 6.4 GB 2.8 ms 2.8 ms
Random Average (Read or Seek)
Random Average (Write)

9

9

10.0 ms 12.0 ms

11.0 ms 13.0 ms
Full-Stroke Seek 20.0 ms 24.0 ms
Average Rotational Latency 5.56 ms —
Power On
Standby

7

5

to Drive Ready

to Interface Ready 10 seconds 30 seconds

6

15 seconds 45 seconds

Spindown Time, Standby Command 9 seconds 15 seconds
Spindown Time, Power Loss 18 seconds 30 seconds

1. Nominal conditions are as follows:

•Nominal temperature 77˚F (25˚C)

•Nominal supply voltages (12.0V, 5.0V)

•No applied shock or vibration

2. Worst case conditions are as follows:

•Worst case temperature extremes 32 to 131˚F (5˚C to 55˚C)

•Worst case supply voltages (12.0V ± 10%, 5.0 V ± 5%)

3. Sequential Cylinder Skew Time is the time from the conclusion of the last sector of
a cylinder to the first logical sector on the next cylinder (no more than 6% of cylinder
switches exceed this time).

4. Sequential Head Skew Time is the time from the last sector of a track to the
beginning of the first logical sector of the next track of the same cylinder (no more
than 6% of head switches exceed this time).

5. Power On is the time from when the supply voltages reach operating range to when
the drive is ready to accept any command.

6. Drive Ready is the condition in which the disks are rotating at the rated speed, and
the drive is able to accept and execute commands requiring disk access without
further delay at power or start up. Error recovery routines may extend the time to as
long as 45 seconds for drive ready.

7. Standby is the condition at which the microprocessor is powered, but not the HDA.
When the host sends the drive a shutdown command, the drive parks the heads away
from the data zone, and spins down to a complete stop.

8. After this time it is safe to move the disk drive.

9. Average random seek is defined as the average seek time between random logical
cylinders (LBA).

8
8

4-4 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

4.5 POWER

The Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT hard disk drives operate from two supply
voltages:

• +12V ± 10%

• +5V ± 5%

The allowable ripple and noise is 250 mV peak-to-peak for the +12 Volt supply and 100
mV peak-to-peak for the +5 Volt supply.

4.5.1 Power Sequencing

You may apply the power in any order, or open either the power or power return line
with no loss of data or damage to the disk drive. However, data may be lost in the sector
being written at the time of power loss. The drive can withstand transient voltages of
+10% to –100% from nominal while powering up or down.

4.5.2 Power Reset Limits

Specifications

When powering up, the drive remains reset until both V
exceeded. When powering down, the drive becomes reset when either supply voltage
drops below the V

threshold.

LT

reset limits in Table 4-4 are

HT

Table 4-4 Power Reset Limits

DC VOL T AGE THRESHOLD HYSTERESIS

V

= 4.65V maximum,

LT

+5 V

4.15V minimum

V

= 4.70V maximum,

HT

50 mV (typical)

4.25V minimum

V

= 9.70V maximum,

LT

+12 V

8.25V minimum

V

= 10.70V maximum,

HT

200 mV (typical)

8.40V minimum

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 4-5

Specifications

4.5.3 Power Requirements

Table 4-5 lists the voltages and typical average corresponding currents for the various
modes of operation of the Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT hard disk drives.

Table 4-5 Typical Power and Current Consumption

1

MODE OF

TYPICAL A VERAGE CURRENT

(mA RMS UNLESS OTHERWISE NOTED)

OPERATION

+12 V +5V

MODEL NUMBER 1.6 2.1 3.2 4.3 6.4 1.6 2.1 3.2 4.3 6.4

1

Startup

(peak) 1650 1650 1650 1690 1690 570 570 570 570 570

3

Idle
Operating
Maximum Seeking
Standby
Sleep

4

5

6

7

Read/Write On Track

MODE OF

OPERATION

240 240 240 270 330 430 430 430 450 400
570 570 570 600 625 630 630 630 650 700
770 770 770 810 850 550 550 550 550 550

20 20 20 20 20 150 150 150 150 150
20 20 20 20 20 150 150 150 150 150

8

310 310 310 330 375 660 660 660 700 700

TYPICAL A VERAGE POWER

2

(W A TTS)

MODEL NUMBER 1.6 2.1 3.2 4.3 6.4

1

Startup

(peak) 23 23 23 23 23

3

Idle
Operating
Maximum Seeking
Standby
Sleep

4

5

6

7

Read/Write On Track

8

5 5 5 5.5 6
10 10 10 10.5 11
12 12 12 12.5 13

11111

11111

7 7 7 7.5 8

1. Current is rms except for startup. Startup current is the typical peak current of the
peaks greater than 10 ms in duration.

2. Power requirements reflect nominal for +12V and +5V power.

3. Idle mode is in effect when the drive is not reading, writing, seeking, or executing
any commands. A portion of the R/W circuitry is powered down, the motor is up to
speed and the Drive Ready condition exists.

4-6 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

Specifications

4. Operating mode is defined as when data is being read from or written to the disk. It

is computed based on 40% seeking, 30% on-track read, 20% idle, and 10% on-track
write.

5. Maximum seeking is defined as continuous random seek operations with minimum

controller delay.

6. Standby mode is defined as when the motor is stopped, the actuator is parked, and

all electronics except the interface control are in low power state. Standby occurs
after a programmable time-out after the last host access. Drive ready and seek
complete status exist. The drive leaves standby upon receipt of a command that
requires disk access or upon receiving a spinup command.

7. Sleep is defined as when the spindle and actuator motors are off and the heads are

latched in the landing zone. Receipt of a reset causes the drive to transition from the
sleep to the standby mode.

8. Read/Write On Track is defined as 50% read operations and 50% write operations on

a single physical track.

4.6 ACOUSTICS

Table 4-6 and Table 4-7 specify the acoustical characteristics of the Quantum Fireball ST

1.6/2.1/3.2/4.3/6.4AT hard disk drives.

OPERATING MODE

Idle On Track

OPERATING MODE

Idle On Track

Table 4-6 Acoustical Characteristics—Sound Pressure

MEASURED NOISE

(SOUND PRESSURE)

32 dBA (typical)

35 dBA (maximum)

Table 4-7 Acoustical Characteristics—Sound Power

MEASURED NOISE

(SOUND POWER PER ISO 7779)

TYPICAL MAXIMUM

2, 3-Disk 3.6 Bels 3.9 Bels

4-Disk 3.7 Bels 3.9 Bels

DISTANCE

39.3 in (1 m)

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 4-7

Specifications

4.7 MECHANICAL DIMENSIONS

Height: 1.0 in. (25.4 mm)
Width: 4.0 in. (101.6 mm)
Depth: 5.75 in. (146.1 mm)

4.8 ENVIRONMENTAL CONDITIONS

Table 4-8 summarizes the environmental specifications of the Quantum Fireball ST 1.6/

2.1/3.2/4.3/6.4AT hard disk drives.

Table 4-8 Environmental Specifications

PARAMETER OPERATING NON-OPERATING

Temperature
(Non-condensing)

Temperature Gradient
(Non-condensing)

Humidity
Maximum W et Bulb
T emperature

1

2

(Non-condensing)

5˚ to 55˚C

(41˚ to 131˚F)

24˚C/hr maximum

(75.2˚F/hr)

5% to 85% rh

30˚C (86˚F)

-40˚ to 65˚C

(-40˚ to 149˚F)

48˚C/hr maximum

(118.4˚F/hr)

5% to 95% rh

40˚C (104˚F)

Humidity Gradient 30% / hour 30% / hour
Altitude

3, 4

–200 m to 3,000 m

(–650 to 10,000 ft.)

–200 m to 12, 000 m

(–650 to 40,000 ft.)

Altitude Gradient 1.5 kPa/min 8 kPa/min

1. Maximum operating temperature must not exceed the drive at any point along the
drive form factor envelope. Airflow or other means must be used as needed to meet
this requirement.

2. The humidity range shown is applicable for temperatures whose combination does
not result in condensation in violation of the wet bulb specifications.

3. Altitude is relative to sea level.

4. The specified drive uncorrectable error rate will not be exceeded over these
conditions.

4-8 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

4.9 SHOCK AND VIBRATION

The Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT hard disk drives can withstand levels of
shock and vibration applied to any of its three mutually perpendicular axes, or principal
base axis, as specified in Table 4-9. A functioning drive can be subjected to specified
operating levels of shock and vibration. When a drive has been subjected to specified
nonoperating levels of shock and vibration, with power to the drive off, there will be no
loss of user data at power on.

When packed in its 1-pack shipping container, the Quantum Fireball ST 1.6/2.1/3.2/4.3/

6.4AT drives can withstand a drop from 30 inches onto a concrete surface on any of its
surfaces, six edges, or three corners. The 12-pack shipping container can withstand a
drop from 30 inches onto a concrete surface on any of its surfaces, six edges, or three
corners.

Table 4-9 Shock and Vibration Specifications

OPERA TING NONOPERA TING

1

Shock

1/2 sine wave, 11 ms duration

10.0 G

Specifications

70 G (10 hits maximum)

1/2 sine wave, 3 ms duration
1/2 sine wave, 2ms duration

Vibration

1

Sine wave (peak to peak)
1/2 octave per minute sweep

1. The specified drive unrecovered error rate will not be exceeded over these conditions.

18 G

1.0 Gpp 5–400 Hz

0.2 Gpp 400–500 Hz

110 G (10 hits maximum)

150 G (6 hits maximum)

2.0 Gpp 5–500 Hz

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 4-9

Specifications

4.10 RELIABILITY

Mean Time Between Failures (MTBF): The projected field MTBF is 400,000 hours.

Component Life: 5 years
Preventive Maintenance (PM): Not required
Start/Stop: 40,000 cycles at ambient temperature

Note: CSS specification assumes a duty cycle of one power off operation

for every one idle mode spin downs.

4.11 DISK ERRORS

Table 4-10 provides the error rates for the Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT
hard disk drives.

The Quantum MTBF numbers represent Bell­Core TR-TSY-000332 MTBF predictions and
represent the minimum MTBF that Quantum or

a customer would expect from the drive.

(minimum)

ERROR TYPE MAXIMUM NUMBER OF ERRORS

Recovered read errors

1

Multi read recovered errors
Unrecovered data errors
Seek errors

4

3

1. Recovered read errors are errors which require retries for data correction. Errors
corrected by ECC on-the-fly are not considered recovered read errors. Read on arrival
is disabled to meet this specification.

2. Triple-burst recovered errors are those errors which require the triple-burst error
correction algorithm to be applied for data correction. This correction is typically
applied only after the programmed retry count is exhausted.

3. Unrecovered read errors are errors that are not correctable using ECC or retries. The
drive terminates retry reads either when a repeating error pattern occurs, or after the
programmed limit for unsuccessful retries and the application of triple-burst error
correction.

4. Seek errors occur when the actuator fails to reach (or remain) over the requested
cylinder and the drive requires the execution of a full recalibration routine to locate
the requested cylinder.

Table 4-10 Error Rates

1 event per 109 bits read

2

1 event per 1012 bits read
1 event per 1014 bits read
1 error per 106 seeks

Note: Error rates are for worst case temperature and voltage.

4-10 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

Chapter 5

BASIC PRINCIPLES OF OPERATION

This chapter describes the operation of Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT hard
disk drives’ functional subsystems. It is intended as a guide to the operation of the drive,
rather than a detailed theory of operation.

5.1 QUANTUM FIREBALL ST DRIVE MECHANISM

This section describes the drive mechanism. Section 5.2 describes the drive electronics.
The Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT hard disk drives consist of a mechanical
assembly and a PCB as shown in Figure 5-1. The drawing is illustrated with four disks,
showing the Quantum Fireball ST 6.4AT drive configuration.

The head/disk assembly (HDA) contains the mechanical subassemblies of the drive, which
are sealed under a metal cover. The HDA consists of the following components:

• Base casting

• DC motor assembly

• Disk stack assembly

• Headstack assembly

• Rotary positioner assembly

• Automatic actuator lock

• Air filter

The drive is assembled in a Class-100 clean room.

CAUTION:To ensure that the air in the HDA remains free of

contamination, never remove or adjust its cover and
seals. Tampering with the HDA will void your warranty.

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 5-1

Basic Principles of Operation

Cover

Rotary

Positioner

Assembly

Read/Write

Preamplifier

Head Stack Assembly

(8 Heads)

Disk Stack
Assembly

Automatic

Actuator Lock

and Air Filter

Printed Circuit

Board

Figure 5-1 Quantum Fireball ST Hard Disk Drive Exploded View

5-2 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

Base
Casting
Assembly

DC
Spindle
Motor

Basic Principles of Operation

5.1.1 Base Casting Assembly

A single-piece, aluminum-alloy base casting provides a mounting surface for the drive
mechanism and PCB. The base casting also acts as the flange for the DC motor assembly.
To provide a contamination-free environment for the HDA, a gasket provides a seal
between the base casting, and the metal cover that encloses the drive mechanism.

5.1.2 DC Motor Assembly

Integral with the base casting, the DC motor assembly is a fixed-shaft, brushless DC
spindle motor that drives the counter-clockwise rotation of the disks.

5.1.3 Disk Stack Assemblies

The disk stack assembly in the Quantum Fireball ST hard disk drives consist of disks
secured by a disk clamp. The aluminum-alloy disks have a sputtered thin-film magnetic
coating.

A carbon overcoat lubricates the disk surface. This prevents head and media wear due to
head contact with the disk surface during head takeoff and landing. Head contact with
the disk surface occurs only in the landing zone outside of the data area, when the disk
is not rotating at full speed. The landing zone is located at the inner diameter of the disk,
beyond the last cylinder of the data area.

5.1.4 Headstack Assembly

The headstack assembly consists of read/write heads, head arms, and coil joined together
by insertion molding to form a rotor subassembly, bearings, and a flex circuit. Read/write
heads mounted to spring-steel flexures are swage mounted onto the rotary positioner
assembly arms.

The flex circuit exits the HDA between the base casting and the cover. A cover gasket
seals the gap. The flex circuit connects the headstack assembly to the PCB. The flex
circuit contains a read preamplifier/write driver IC.

5.1.5 Rotary Positioner Assembly

The rotary positioner, or rotary voice-coil actuator, is a Quantum-proprietary design that
consists of upper and lower permanent magnet plates, a rotary single-phase coil molded
around the headstack mounting hub, and a bearing shaft. The single bi-polar magnet
consists of two alternating poles and is bonded to the magnet plate. A resilient crash stop
prevents the heads from being driven into the spindle or off the disk surface.

Current from the power amplifier induces a magnetic field in the voice coil. Fluctuations
in the field around the permanent magnet cause the voice coil to move. The movement
of the voice coil positions the heads over the requested cylinder.

5.1.6 Automatic Actuator Lock

To ensure data integrity and prevent damage during shipment, the drive uses a dedicated
landing zone and Quantum’s patented Airlock
landing zone whenever the disks are not rotating. It consists of an air vane mounted near
the perimeter of the disk stack, and a locking arm that restrains the actuator arm
assembly.



. The Airlock holds the headstack in the

When DC power is applied to the motor and the disk stack rotates, the rotation generates
an airflow on the surface of the disk. As the flow of air across the air vane increases with
disk rotation, the locking arm pivots away from the actuator arm, enabling the headstack
to move out of the landing zone. When DC power is removed from the motor, an
electronic return mechanism automatically pulls the actuator into the landing zone,
where the Airlock holds it in place.

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 5-3

Basic Principles of Operation

5.1.7 Air Filtration

The Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT hard disk drives are Winchester-type
drives. The heads fly very close to the media surface. Therefore, it is essential that the air
circulating within the drive be kept free of particles. Quantum assembles the drive in a
Class-100 purified air environment, then seals the drive with a metal cover. When the
drive is in use, the rotation of the disks forces the air inside of the drive through an
internal 0.3 micron filter.

5.2 DRIVE ELECTRONICS

Advanced circuit design, the use of miniature surface-mounted components, and
proprietary VLSI integrated circuits enable the drive electronics, including the IDE bus
interface, to reside on a single printed circuit board assembly (PCBA). The high level of
integration allows implementation of the AT PCBA with only 5 ICs.

Note: The components are mounted on only one side of the PCB.

Figure 5-3 contains a simplified block diagram of the Quantum Fireball ST 1.6/2.1/3.2/

4.3/6.4AT hard disk drives’ electronics.

The only electrical component not on the PCBA is the PreAmplifier and Write Driver IC.
It is on the flex circuit (inside of the sealed HDA). Mounting the preamplifier as close as
possible to the read/write heads improves the signal-to-noise ratio. The flex circuit
(including the PreAmplifier and Write Driver IC) provides the electrical connection
between the PCB, the rotary positioner assembly, and read/write heads.

HARD DISK
ASSEMBLY

RDX RDY

PREAMP &
WRITE

WR DATA

DRIVER

HD SEL

VOICE

COIL

MOTOR

SPINDLE

MOTOR

PCB

SPINDLE/VCM

POWER ASIC

RD DATA

WR DATA

–RESET

µ CONTROLLER

–RESET

VCM/Spindle Control

POR

ADDR

DATA

SERIAL

EEPROM

(128 BYTES)

READ/WRITE

ASIC

SERIAL

RD/WR DATA

BUS

SERIAL BUS

DISK

CONTROLLER

and IDE

INTERFACE

ASIC

CNTRDL

B ADDR B DATA

–POR

(0-7) (0-15)

REF
CLK

DRAM

(64K X 16)

DATA (0-15)

IDE BUS

SCSI CONTROL BUS

–WE

Figure 5-2 Quantum Fireball ST Hard Disk Drive Block Diagram

5-4 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

Basic Principles of Operation

5.2.1

µ Controller

The µ Controller provides local processor services to the drive electronics under program
control. The µ Controller manages the resources of the Disk Controller and IDE Interface
ASIC (DCIIA), the Read/Write ASIC, and the Spindle/VCM Driver. In addition, it controls
the head selection process.

An internal 32Kbyte ROM contained within the µ Controller provides program code that
the µ Controller executes to complete a drive spinup and recalibration procedure, after
which the µ Controller reads additional control code from the disk (diskware), and stores
it in the buffer DRAM.

5.2.2 DCIIA

The DCIIA (Disk Controller and IDE Interface ASIC) shown in Figure 5-3 provides control
functions to the drive under the direction of the µ Controller.

DRAM
BUFFER
64K x 16

DISK CONTROLLER &
IDE INTERFACE
ASIC (DCIIA)

16

Buffer

Addr/Ctrl

BUFFER

CONTROLLER

TO/FROM HOST

IDE

INTERFACE

µP

INTERFACE

MOTOR

Reset

µP

Reset

HDA

ECC

WRITE

PRECOMP

SERIAL

INTERFACE

PREAMP

Buffer Data

FORMATTER

VGA

CLK SYN­THESIZER

BUTTER-

WORTH

FILTER

µP Bus

ENDEC/

QBLOCK

PLL

ADC

SER

SERVO

CONTROLLER

READ/WRITE ASIC

FIR

FILTER

VITERBI

DETECTOR

SERVO DETECTOR

A/D CONVERTER

FLASH

ADC

RETRACT

& VCM

ACTUATOR

SPINDLE

MOTOR
CONTROLLER

SPINDLE MOTOR

POWER

ON

RESET

Figure 5-3 DCIIA Block Diagram

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 5-5

Basic Principles of Operation

The DCIIA is a proprietary ASIC developed by Quantum. The DCIIA is comprised of nine
functional modules (described below):

• Error Correction Control

• Motor Control

• Sequencer (Formatter)

• Buffer Controller

• µ Controller Interface

• Servo Controller, including PWM DAC

• Serial Interface

• IDE Interface Controller

• Analog PLL

5.2.2.1 Error Correction Control

The Error Correction Control block utilizes a Reed-Solomon encoder/decoder circuit that
is used for disk read/write operations. It uses a total of 28 redundancy bytes organized
as 24 ECC (Error Correction Code) bytes and four cross-check bytes. The ECC uses eight
bits per symbol and four interleaves. This allows triple-burst error correction of at least
81, and as many as 96 bits in error.

5.2.2.2 Formatter

The formatter controls the operation of the read and write channel portions of the DCIIA.
The design supports an ID-less format eliminating the need for storing sector format
information on each data track.

The sequencer also directly drives the read and write gates (
ASIC and the R/W Preamplifier, as well as passing write data to the Precompensator
circuit in the Read/Write ASIC.

5.2.2.3 Buffer Controller

The buffer controller supports a 128 Kbyte buffer, which is organized as 64 K x 16 bits.
The 16-bit width implementation provides a 66 MB/s maximum buffer bandwidth, with
the use of EDO-type DRAM. This increased bandwidth allows the µ Controller to have
direct access to the buffer, eliminating the need for a separate µ Controller RAM IC.

RG

,

WG

) of the Read/Write

5-6 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

µ

Basic Principles of Operation

5.2.2.4

Controller Interface

The µ Controller Interface provides the means for the µ Controller to read and write data
to the DCIIA modules to control their operation, or supply them with needed information.
It consists of both physical and logical components.

The physical component of the interface is comprised of 16-bit MAD (Multiplexed
Address/Data) bus, four additional address lines, read and write strobe, an address latch
enable (ALE) signal, and a wait control line.

The logical component of the interface is comprised of internal control and data registers
accessible to the µ Controller. By writing and reading these registers, the µ Controller loads
the Sequencer, controls and configures the Buffer controller, and passes coded servo
information to the Servo Controller.

5.2.2.5 Servo Controller

The Servo Controller decodes raw data from the disk to extract the current position
information. The position information is read by the µ Controller and is used to generate
the actuator control signal that is sent to the actuator driver which is an analog power
amplifier circuit external to the DCIIA. The Servo Controller operates under the direction
of the µ Controller.

5.2.2.6 Serial Interface

The Serial Interface provides a high speed Read/Write interface path to the Read/Write
ASIC under the direction of the µ Controller.

5.2.2.7 IDE Interface Controller

The IDE Interface Controller portion of the DCIIA provides data handling, bus control,
and transfer management services for the IDE interface. Configuration and control of the
interface is accomplished by the µ Controller across the MAD bus. Data transfer
operations are controlled by the DCIIA Buffer Controller module.

5.2.2.8 Motor Controller

The Motor Controller block of the DCIIA in conjunction with the spindle/VCM power
ASIC, µ P, and the required firmware provides all the necessary functionality for Motor
Spindle Commutation, Speed Control, as well as Actuator Voice Coil controls.

The Motor Controller consists of three basic functional blocks, the Motor Commutation
Logic, Motor Power Mode Logic, and the Voice Coil PWM Logic. The Voice Coil PWM
logic provides a 14-bit digital to analog converter (DAC) function in the form of a Pulse
Width Modulator (PWM). This PWM signal is output to the spindle/VCM power ASIC
where it is filtered and supplied to the VCM power amplifier.

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 5-7

Basic Principles of Operation

5.2.3 Read/Write ASIC

The Read/Write ASIC shown in Figure 5-4 provides write data precompensation and read
channel processing functions for the drive. The Read/Write ASIC receives the RD GATE
signal, reference oscillator, serial programming, and servo burst and sample gates from
the DCIIA. The Read/Write ASIC sends decoded read data and the read reference clock,
and receives write data from the DCIIA. This a highly integrated circuit which is
completely under digital control from the DCIIA.

The Read/Write ASIC comprises 11 main functional modules (described below):

• Pre-Compensator

• Variable Gain Amplifier (VGA)

• Butterworth Filter

• FIR Filter

• Flash A/D Converter

• Viterbi Detector

• ENDEC

• Servo Detector and Sample/Hold

• Clock Synthesizer

• PLL

• Serial Interface

PREAMP

&

WRITE

HDA

SERIAL

INTERFACE

DCIIA

INTERFACE

PRECOMP

SERIAL

VGA

WRITE

SYNTHESIZER

BUTTERWORTH

CLOCK

FORMATTER

FILTER

ADC

ENDEC

QBLOCK

PLL

SERVO

CONTROLLER

FILTER

Figure 5-4 Read/Write ASIC Block Diagram

READ/WRITE ASIC

FIR

SERVO DETECTOR

FLASH

ADC

VITERBI

DETECTOR

A/D CONVERTER

5-8 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

5.2.3.1 Pre-Compensator

The pre-compensator introduces pre-compensation to the write data received from the
sequencer module in the DCIIA. The pre-compensated data is then passed to the R/W Pre­Amplifier and written to the disk. Pre-compensation reduces the write interference from
adjacent write bit.

5.2.3.2 Variable Gain Amplifier (VGA)

Digital and analog controlled AGC function with input attenuator for extended range.

5.2.3.3 Butterworth Filter

Continuous time data filter which can be programmed for each zone rate.

5.2.3.4 FIR (Finite Impulse Response) Filter

Digitally controlled and programmable filter for partial response signal conditioning.

5.2.3.5 Flash A/D Converter

Provides very high speed digitization of the processed read signal.

Basic Principles of Operation

5.2.3.6 Viterbi Detector

Decodes ADC result into binary bit stream.

5.2.3.7 ENDEC/QBlock

Provides 16/17 code conversion to NRZ. Includes preamble and sync mark generation
and detection.

5.2.3.8 Servo Detector and Sample/Hold

Peak detection with weighted averaging and multiple sample and hold of servo bursts.

5.2.3.9 Clock Synthesizer

Provides programmable frequencies for each zone data rate.

5.2.3.10 PLL

Provides digital read clock recovery.

5.2.3.11 Serial Interface

High speed interface for digital control of all internal blocks.

5.2.3.12 Servo ADC

Provides 9 bit analog to digital conversion of servo burst amplitude.

5.2.4 PreAmplifier and Write Driver

The PreAmplifier and Write Driver provides write driver and read pre-amplifier functions,
and R/W head selection. The write driver receives precompensated write data from the
PreCompensator module in the Read/Write ASIC. The write driver then sends this data to
the heads in the form of a corresponding alternating current. The read pre-amplifier
amplifies the low-amplitude differential voltages generated by the R/W heads, and
transmits them to the VGA module in the Read/Write ASIC. Head select is determined by
the µ Controller. The preamp also contains internal compensation for thermal asperity
induced amplitude variation.

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 5-9

Basic Principles of Operation

5.3 SERVO SYSTEM

5.3.1 General Description

The servo system controls the positioning of the read/write heads and holds the read/
write heads, on track during read/write operations. The servo system also compensates
for thermal offsets between heads on different surfaces, and any shock and vibration the
drive is subjected to.

The Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT hard disk drives use a high performance
embedded sectored servo system. Positioning information is radially encoded in evenly­spaced servo bursts on each track. These servo burst wedges provide radial position
information for each data head. Because the drive uses multiple zone recording, where
each zone has a different bit density, split data fields are necessary to optimally utilize
the non-servo area of the disk. The split data fields are achieved by special processing
through the DCIIA, and their presence is transparent to the host system. The servo area
remains phase coherent across the surface of the disk, even though the disk is divided
into various data zones. The main advantage of the sectored servo systems is that the
data heads are also servo heads, which means that sectored servo systems eliminate the
problems of static and dynamic offsets between heads on different surfaces.

The Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT hard disk drives’ servo system is also
classified as a digital servo because track following compensation is done in firmware.
The bump detect, on-track, velocity profiles, and other “housekeeping” tasks are also
done in firmware.

The state of the servo system determines how the position information is derived.
During both track following and seeking, the position signal is the convolution of the
track number and A, B, C, or D burst values, and the resolution is at least 1/512th of a
track pitch—about 0.2%.

5.3.2 Servo Burst and Track Information

Positional information is encoded on all tracks on all data surfaces. All data heads are
also servo heads. The areas with servo/position information are called wedge areas. These
wedge areas are evenly spaced radially around the disk, like spokes on a wheel. There are
84 wedge areas per track. Since the disk rotation is 90.0 revolutions/second, the position
information is updated at 7560 Hz (84 x 90.0). This is also known as the sampling
frequency ƒs. The sample period, Ts, is 1/ƒs = 132 µ s. Every wedge area consists of four
separate fields: (1) Automatic Gain Control (AGC)/Sync field, (2) Servo Address Mark
(SAM) field, (3) Track number and (4) Burst area. Since a Phase Lock Loop (PLL) is not
used in the servo wedge area, time discrimination is used. Timing for all four fields is
generated from the same crystal reference.

5-10 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

5.4 READ AND WRITE OPERATIONS

The following paragraphs provide descriptions of the read channel, write channel, and
IDE interface control operations.

5.4.1 The Read Channel

The drive has one read/write head for each data surface. The signal path for the read
channel begins at the read/write heads. As the magnetic flux transitions recorded on a
disk pass under a head, they generate low-amplitude, differential output voltages. These
read signals pass from the read/write head to the flex circuit's read preamplifier, which
amplifies the signal. To ensure a high signal to noise ratio, preamplification occurs on
the flex circuit because of its proximity to the heads.

The flex circuit transmits the preamplified signal from the HDA to the drive PCB. On the
PCB, the Read/Write ASIC further processes the read signal to reduce ambiguities, for
example, drop-ins, drop-outs, and ISI (Inter-symbol Interferences). In addition, it
converts the signal from the serial encoded head data to a synchronized data stream, with
its accompanying clock. The Read/Write ASIC then sends the resynchronized and
decoded data output to Quantum's proprietary Disk Controller and IDE Interface ASIC
(DCIIA).

Basic Principles of Operation

The DCIIA manages the flow of data between the Read/Write ASIC and its IDE Interface
Controller. It also controls data access for the external RAM buffer. The DCIIA format
provides a serial bit stream. This NRZ (Non-Return to Zero) serial data is converted to an
8-bit byte. The Sequencer module identifies the data as belonging to the target sector.
Data is presented to the host in a 16-bit word.

After a full sector is read, the DCIIA checks to see if the firmware needs to apply ECC on­the-fly, or single-, double-, or triple-burst correction to the data. The buffer controller
section of the DCIIA stores the data in the Cache and transmits the data to the IDE
Interface Controller module, which transmits the data to the IDE bus.

5.4.2 The Write Channel

For the write channel, the signal path follows the reverse order of that for the read
channel. The host presents a 16-bit word of data, by means of the IDE bus, to the DCIIA
IDE Interface Controller. The Buffer Controller section of the DCIIA stores the data in the
cache. Because data can be presented to the drive at a rate that exceeds the rate at which
the drive can write data to a disk, data is stored temporarily in the cache. Thus, the host
can present data to the drive at a rate that is independent of the rate at which the drive
can write data to the disk.

Upon correct identification of the target address, the data is shifted to the Sequencer
where an error correcting code is generated and appended. The Sequencer then converts
the bytes of data to a serial bit stream. The DCIIA transmits the data to the Read/Write
ASIC, where the data is encoded and precompensated to reduce intersymbol interference.
The data is then transmitted to the Write Driver by means of the write data lines.

The drive's DCIIA switches the Preamplifier Write Driver IC to write mode and selects a
head. Once the Write driver receives a write gate signal, it transmits current reversals to
the head, which induces magnetic transitions on the disk.

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 5-11

Basic Principles of Operation

5.4.3 Interface Control

The interface with the host system is through a 40-pin IDE interface connector. The DCIIA
IDE Interface Controller module implements the IDE interface logic. Operating under the
drive's µ processor control, the DCIIA receives and transmits words of data over the IDE
bus.

The DCIIA Buffer Controller writes data to, or reads data from the Cache over 16 data
lines. Under µ Controller direction, the DCIIA controls the transfer of data and handles the
addressing of the Cache. The DCIIA can communicate over the IDE interface up to 16.67
MB/s with PIO using IORDY, or a DMA transfer rate of up to 33 MB/s while it
simultaneously controls disk-to-RAM transfers, and microcontroller access to control
code stored in the buffer RAM.

5.4.4 ID-Less Format

The Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT hard disk drives utilize an ID-Less format.
The ID-Less Format has several advantages over the traditional ‘ID After Wedge’ or ‘ID
Before Sector’ methods of tracking the location of the actuator. For example, the lack of
an ID field written on the disk gains approximately 4% of the overall track ‘real-estate’,
thus increasing the total capacity. Secondly, since no ID’s have to be read or corrected in
case of an error, overall throughput is increased. In ID-Less formatting, the ID of each
sector is not written on the disk after the servo wedge. Instead it is stored in the buffer
RAM and is called the Descriptor. Each sector has an associated descriptor which contains
the following basic information. The servo wedge number after which the sector is
located, the sector start time after the wedge, and when to skip over the next wedge. The
descriptor does not have defect information. The defect map is also stored in the buffer
RAM but in a separate location. The formatter section of the DCIIA will access both, the
descriptor and the defect lists through a request to the buffer block of the DCIIA. Only
the user data and the ECC information is actually written to the disk.

Table 5-1 ID-Less Controller Descriptor Format

BYTE

76543210

0 PARITY WEDGE NUMBER
1 BREAK COUNT 1 MSB SECTOR MARK

2 SECTOR MARK LSB

5.4.4.1 Descriptor Byte Functions

Parity

This is the odd parity bit for the 3-byte or 4-byte descriptor. If the parity bit in the
CONFIG register of the DCIIA is set, and the formatter detects a parity error in the
descriptor, then the State Machine will interrupt the µ P. If the parity bit is not set the
formatter will ignore any parity errors.

Wedge Number

This is the wedge number of this sector. It is compared to the internal wedge counter of
the formatter to determine if this is the right wedge for this sector.

Brk Count 1

This value is used in conjunction with the pre-wedge signal from the DCIIA’s servo
register. It provides the exact location where to split the sector and skip over the wedge.

BIT

5-12 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

Sector Mark

The Sector Mark is the starting time of this sector. This 12-bit value is sent to the DCIIA’s
servo register, and compared with the MSB of its Sector Timer to determine the start of
the sector.

5.5 FIRMWARE FEATURES

This section describes the following firmware features:

• Disk caching

• Track and cylinder skewing

• Error detection and correction

• Defect management

5.5.1 Disk Caching

Basic Principles of Operation

The Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT hard disk drives incorporate DisCache, a
87 K disk cache, to enhance drive performance. This integrated feature is user­programmable and can significantly improve system throughput. Read and write caching
can be enabled or disabled by using the Set Configuration command.

5.5.1.1 Adaptive Caching

The cache buffer for the Quantum Fireball ST drives features adaptive segmentation for
more efficient use of the buffer’s RAM. With this feature, the buffer space used for read
and write operations is dynamically allocated. The cache can be flexibly divided into
several segments under program control. Each segment contains one cache entry.

A cache entry consists of the requested read data plus its corresponding prefetch data.
Adaptive segmentation allows the drive to make optimum use of the buffer. The amount
of stored data can be increased.

5.5.1.2 Read Cache

DisCache anticipates host-system requests for data and stores that data for faster access.
When the host requests a particular segment of data, the caching feature uses a prefetch
strategy to “look ahead”, and automatically store the subsequent data from the disk into
high-speed RAM. If the host requests this subsequent data, the RAM is accessed rather
than the disk.

Since typically 50 percent or more of all disk requests are sequential, there is a high
probability that subsequent data requested will be in the cache. This cached data can be
retrieved in microseconds rather than milliseconds. As a result, DisCache can provide
substantial time savings during at least half of all disk requests. In these instances,
DisCache could save most of the disk transaction time by eliminating the seek and
rotational latency delays that dominate the typical disk transaction. For example, in a 1K
data transfer, these delays make up to 90 percent of the elapsed time.

DisCache works by continuing to fill its cache memory with adjacent data after
transferring data requested by the host. Unlike a noncaching controller, Quantum’s disk
controller continues a read operation after the requested data has been transferred to the
host system. This read operation terminates after a programmed amount of subsequent
data has been read into the cache segment.

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 5-13

Basic Principles of Operation

The cache memory consists of a 86 K DRAM buffer allocated to hold the data, which can
be directly accessed by the host by means of the READ and WRITE commands. The
memory functions as a group of segments with rollover points at the end of cache
memory. The unit of data stored is the logical block (that is, a multiple of the 512 byte
sector). Therefore, all accesses to the cache memory must be in multiples of the sector
size. All non-read/write commands force emptying of the cache:

5.5.1.3 Write Cache

When a write command is executed with write caching enabled, the drive stores the data
to be written in a DRAM cache buffer, and immediately sends a GOOD STATUS message
to the host before the data is actually written to the disk. The host is then free to move
on to other tasks, such as preparing data for the next data transfer, without having to
wait for the drive to seek to the appropriate track, or rotate to the specified sector.

While the host is preparing data for the next transfer, the drive immediately writes the
cached data to the disk, usually completing the operation in less than 20 ms after issuing
GOOD STATUS. With WriteCache, a single-block, random write, for example, requires
only about 3 ms of host time. Without WriteCache, the same operation would occupy the
host for about 20 ms.

WriteCache allows data to be transferred in a continuous flow to the drive, rather than
as individual blocks of data separated by disk access delays. This is achieved by taking
advantage of the ability to write blocks of data sequentially on a disk that is formatted
with a 1:1 interleave. This means that as the last byte of data is transferred out of the
write cache and the head passes over the next sector of the disk, the first byte of the of
the next block of data is ready to be transferred, thus there is no interruption or delay in
the data transfer process.

The WriteCache algorithm fills the cache buffer with new data from the host while
simultaneously transferring data to the disk that the host previously stored in the cache.

5.5.1.4 Performance Benefits

In a drive without DisCache, there is a delay during sequential reads because of the
rotational latency, even if the disk actuator already is positioned at the desired cylinder.
DisCache eliminates this rotational latency time (5.56 ms on average) when requested
data resides in the cache.

Moreover, the disk must often service requests from multiple processes in a multitasking
or multiuser environment. In these instances, while each process might request data
sequentially, the disk drive must share time among all these processes. In most disk
drives, the heads must move from one location to another. With DisCache, even if
another process interrupts, the drive continues to access the data sequentially from its
high-speed memory. In handling multiple processes, DisCache achieves its most
impressive performance gains, saving both seek and latency time when desired data
resides in the cache.

The cache can be flexibly divided into several segments under program control. Each
segment contains one cache entry. A cache entry consists of the requested read data plus
its corresponding prefetch data.

The requested read data takes up a certain amount of space in the cache segment. Hence,
the corresponding prefetch data can essentially occupy the rest of the space within the
segment. The other factors determining prefetch size are the maximum and minimum
prefetch. The drive’s prefetch algorithm dynamically controls the actual prefetch value
based on the current demand, with the consideration of overhead to subsequent
commands.

5-14 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

5.5.2 Track and Cylinder Skewing

Track and cylinder skewing in the Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT hard disk
drives minimize latency time and thus increases data throughput.

5.5.2.1 Track Skewing

Track skewing reduces the latency time that results when the drive must switch read/
write heads to access sequential data. A track skew is employed such that the next logical
sector of data to be accessed will be under the read/write head once the head switch is
made, and the data is ready to be accessed. Thus, when sequential data is on the same
cylinder but on a different disk surface, a head switch is needed but not a seek. Since the
sequential head-switch time is well defined on the Quantum Fireball ST 1.6/2.1/3.2/4.3/

6.4AT drives, the sector addresses can be optimally positioned across track boundaries to
minimize the latency time during a head switch. See Table 5-2.

5.5.2.2 Cylinder Skewing

Cylinder skewing is also used to minimize the latency time associated with a single­cylinder seek. The next logical sector of data that crosses a cylinder boundary is
positioned on the drive such that after a single-cylinder seek is performed, and when the
drive is ready to continue accessing data, the sector to be accessed is positioned directly
under the read/write head. Therefore, the cylinder skew takes place between the last
sector of data on the last head of a cylinder, and the first sector of data on the first head
of the next cylinder. Since single-cylinder seeks are well defined on the Quantum Fireball
ST 1.6/2.1/3.2/4.3/6.4AT drives, the sector addresses can be optimally positioned across
cylinder boundaries to minimize the latency time associated with a single-cylinder seek.
See Table 5-2.

Basic Principles of Operation

5.5.2.3 Skewing with ID-less

In the ID-less environment, the drive’s track and cylinder skewing will be based in unit
of wedges instead of the traditional sectors. The DCIIA controller contains a “Wedge
Skew Register” to assist in the task of skewing, where the skew offset must now be
calculated with every read/write operation. The firmware will program the skew offset
into this register every time the drive goes to a new track. The DCIIA will then add this
value to the wedge number in the sector descriptor, effectively relocating the “first” sector
of the track away from the index. For example, if without skew, sector 0 is to be found
following wedge 0, then if the skew register is set to 10, sector 0 will be found following
wedge 10.

Since the wedge-to-wedge time is constant over the entire disk, a single set of track and
cylinder skew off-sets will fulfill the requirement for all recording zones.

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 5-15

Basic Principles of Operation

5.5.2.4 Skew Offsets

Track Skew 2.5 ms 19

Cylinder Skew 3.0 ms 23

Note: Nominal wedge-to-wedge time of 132.229 µs is used. Worst case

instantaneous spindle variation (±0.25%) is used while calculating
to provide a safety margin.

Wedge offsets are rounded to the closest whole number.

5.5.2.5 Runtime Calculation

Since the wedge-to-wedge time is constant over the entire disk, a single set of track and
cylinder skew offsets will fulfill the requirement for all recording zones. The formula used
to compute the wedge skew for a given cylinder and head is:

Table 5-2 Skews Offsets

SWITCH TIME WEDGE OFFSET

Wedge skew = [C* ((# of heads – 1) * TS + CS) + H * TS] MOD 84
Where: C = Cylinder number

H = Head number
TS = Track Skew Offset
CS Cylinder Skew Offset
(wedges/track = 84)

5.5.3 Error Detection and Correction

As disk drive areal densities increase, obtaining extremely low error rates requires a new
generation of sophisticated error correction codes. Quantum Fireball ST 1.6/2.1/3.2/4.3/

6.4AT hard disk drive series implement 224-bit triple-burst Reed-Solomon error
correction techniques to reduce the uncorrectable read error rate to less than one bit in
1 x 1014 bits read.

When errors occur, an automatic retry, a double-burst, and a more rigorous triple-burst
correction algorithm enable the correction of any sector with three bursts of four
incorrect bytes each, or up to twelve multiple random one-byte burst errors. In addition
to these advanced error correction capabilities, the drive uses an additional cross­checking code and algorithm to double check the main ECC correction. This greatly
reduces the probability of a miscorrection.

5-16 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

Basic Principles of Operation

5.5.3.1 Background Information on Error Correction Code and ECC On-the-Fly

A sector on the Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT drive is comprised of 512
bytes of user data, followed by four cross-checking (XC) bytes (32 bits), followed by 24
ECC check bytes (192 bits). The four cross-checking bytes are used to double check the
main ECC correction and reduce the probability of miscorrection. Errors of up to 64 bits
within one sector can be corrected “on-the-fly,” in real time as they occur, allowing a
high degree of data integrity with no impact on the drive’s performance.

The drive does not need to re-read a sector on the next disk revolution or apply ECC for
those errors that are corrected on-the-fly. Errors corrected in this manner are invisible to
the host system.

When errors cannot be corrected on-the-fly, an automatic retry, and a more rigorous
triple-burst error correction algorithm enables the correction of any sector with three
bursts of four incorrect bytes each (up to 12 contiguous bytes), or up to 12 multiple
random one-byte burst errors. In addition to this error correction capability, the drive’s
implementation of an additional cross-checking code and algorithm double checks the
main ECC correction, and greatly decreases the likelihood of miscorrection.

The 24 ECC check bytes shown in Figure 5-5 are used to detect and correct errors. The
cross-checking and ECC data is computed and appended to the user data when the sector
is first written.

12345

d 1d 2d 3d 4d 5

512 data bytes 24 ECC bytes

Figure 5-5 Sector Data Field with ECC Check Bytes

512 513 516

d 512 xc 1

xc 2 • • • •• • • • • •

4

cross-check

bytes

518517

ecc 2ecc 1

540

ecc 24

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 5-17

Basic Principles of Operation

To obtain the ECC check byte values, each byte (including cross-checking and ECC bytes)
within the sector is interleaved into one of three groups, where the first byte is in
interleave 1, the second byte is in interleave 2, the third byte is in interleave 3, the fourth
byte is in interleave 1, the fifth byte is in interleave 2, and so on, as shown in Figure 5-6.

Interleave 1
Interleave 2
Interleave 3

Interleave 4

d1

d2

d3

Note: ECC interleaving is not the same as the sector interleaving that is

Each of the four interleaves is encoded with six ECC bytes, resulting in the 24 ECC bytes
at the end of the sector. The four cross checking bytes are derived from all 512 data bytes.
The combination of the interleaving, and the nature of the ECC formulas enable the drive
to know where the error occurs.

Because the ECC check bytes follow the cross checking bytes, errors found within the
cross-checking bytes can be corrected. Due to the power and sophistication of the code,
errors found within the ECC check bytes can also be corrected.

d5

• • • •

d6

d7

d4 d8 d512 xc4 ecc4 ecc8 ecc12 ecc16• • • • ecc20 ecc24

• • • •

• • • •

d509

d510

xc1

d511

xc2

ecc1

xc3

ecc2

ecc5

ecc3

ecc6

ecc9

ecc7

ecc10

ecc11

ecc13

ecc14

ecc17

ecc15

ecc18

ecc19

ecc21

ecc22

ecc23

Figure 5-6 Byte Interleaving

done on the disk.

Each time a sector of data is read, the Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT drives
will generate a new set of ECC check bytes and cross-checking bytes from the user data.
These new check bytes are compared to the ones originally written to the disk. The
difference between the newly computed and original check bytes is reflected in a set of
24 syndromes and four cross checking syndromes, which correspond to the number of
check bytes. If all the syndrome values equal zero, the data was read with no errors, and
the sector is transferred to the host system. If any of the syndromes do not equal zero, an
error has occurred. The type of correction the drive applies depends on the nature and
the extent of the error.

High speed on-the-fly error correction saves several milliseconds on each single-, or
double- burst error, because there is no need to wait for a disk revolution to bring the
sector under the head for re-reading.

Correction of Single-, or Double-Burst Errors On-the-Fly

Single-burst errors may have up to four erroneous bytes (32 bits) within a sector,
provided that each of the four bytes occur in a different interleave.

The Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT drives have the capability to correct
double-burst errors on-the-fly as well. Double-burst errors can be simply viewed as two
spans of errors within one sector. More specifically, correctable double-burst errors must
have two or fewer erroneous bytes per interleave.

The drive’s Reed-Solomon ECC corrects double-burst errors up to 64 bits long, (provided
that the error consists of two or fewer bytes residing in each of the interleaves).

5-18 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

Basic Principles of Operation

Double-Burst Error Examples

In the example shown in Figure 5-7 C, the 58-bit error is uncorrectable since it occupies
more than two erroneous bytes per interleave.

The other two 64-bit errors, shown in Figure 5-7 A and B, are correctable because no
more than two error bytes of the entire error reside in any one of the interleaves.

Note: Any 57-bit error burst can be corrected on-the-fly using double-

burst error correction because no more than two bytes can occupy
each interleave.

Byte 1

A

Byte 1

B

Byte 1

C

• • •

• • •

Interleave

3

• • •

CORRECTABLE

Interleave

Interleave1Interleave

4

Interleave1Interleave2Interleave

2

• • •
3

32 bits 32 bits

CORRECTABLE (On-the-Fly)

Interleave2Interleave

• • •

Interleave2Interleave

3

4

Interleave1Interleave2Interleave3Interleave

4

64 bits

UNCORRECTABLE

Interleave2Interleave

3

Interleave

Interleave1Interleave2Interleave3Interleave

4

4

56 bits

1 bit

Figure 5-7 Correctable and Uncorrectable Double-Burst Errors

Byte 526

Interleave

4

Interleave

1

Interleave1Interleave

• • •

Byte 526

• • •

2

1 bit

Byte 526

• • •

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 5-19

Basic Principles of Operation

Correction of Triple-Burst Errors

Through sophisticated algorithms, Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT drives
have the capability to correct triple-burst errors, even though the probability of their
occurrence is low. Triple-burst errors can be simply viewed as three spans of errors within
one sector. More specifically, correctable triple-burst errors must have three or fewer
erroneous bytes per interleave, and will not be corrected on-the-fly.

The drive’s Reed-Solomon ECC corrects triple-burst errors up to 96 bits long, (provided
that the error consists of three or fewer bytes residing in each of the interleaves).

If the triple-burst correction is successful, the data from the sector can be written to a
spare sector, and the logical address will be mapped to the new physical location.

Triple-Burst Error Examples

In the example shown in Figure 5-8 C, the 90-bit error is uncorrectable since it occupies
more than three erroneous bytes per interleave.

The other two 96-bit errors, shown in Figure 5-8 A and B, are correctable because no
more than three error bytes of the entire error reside in any one of the interleaves.

Note: Any 89-bit error burst can be corrected using triple-burst error

correction because no more than three bytes can occupy each in­terleave.

Interleave1Interleave2Interleave

A

Interleave1Interleave2Interleave

B

32 bits

Interleave1Interleave2Interleave

C

1 bit

CORRECTABLE

Interleave

Interleave

4

3

Interleave2Interleave3Interleave

1

Interleave1Interleave2Interleave3Interleave

4

96 bits

CORRECTABLE

Interleave

3

4

Interleave1Interleave2Interleave

• • •

Interleave

3

4

Interleave1Interleave2Interleave

• • •

32 bits

UNCORRECTABLE

Interleave

3

Interleave

4

Interleave2Interleave

1

Interleave

3

Interleave

4

Interleave2Interleave3Interleave4Interleave

1

88 bits

Figure 5-8 Correctable and Uncorrectable Triple-Burst Errors

32 bits

1 bit

4

Interleave

3

4

1

5-20 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

Basic Principles of Operation

Multiple Random Burst Errors

The drive’s ECC can correct up to 96 bits of multiple random errors, provided that the
incorrect bytes follow the guidelines for correctable triple-burst errors. Up to 64 bits of
multiple random errors can be corrected on-the-fly, provided that the incorrect bytes
follow the guidelines for correctable double-burst errors. Up to 24 bits of multiple
random errors can be corrected on-the-fly if two bytes per interleave contains an error.
If more than three bytes in any one interleave are in error, the sector cannot be corrected.
Figure 5-9 shows an example of a correctable random burst error consisting of 12 bytes
(96 bits). This random burst error is correctable because no more than three bytes within
each interleave are in error.

INTERLEAVE 1

1
5
9

•

•

•

85
89
93

•

•

•

INTERLEAVE 2

2
6

10

•

•

•

86
90
94

•

•

•

INTERLEAVE 3

3
7

11

•

•

•

87
91
95

•

•

•

INTERLEAVE 4

4
8

12

•

•

•

88
92
96

•

•

•

505

506

507

510 511509 512

513 XC 515 XC

•

•

•

BYTE CONTAINING AN ERROR

Figure 5-9 Nine Correctable Random Burst Errors

514 XC

•

•

•

•

•

•

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 5-21

508

516 XC

•

•

•

Basic Principles of Operation

5.5.3.2 ECC Error Handling

When a data error occurs, the Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT hard disk drives
check to see if the error is correctable on-the-fly. This process takes about 200 µs. If the
error is correctable on-the-fly, the error is corrected and the data is transferred to the host
system.

If the data is not correctable on-the-fly, the sector is re-read in an attempt to read the
data correctly without applying the triple-burst ECC correction. Before invoking the
complex triple-burst ECC algorithm, the drive will always try to recover from an error by
attempting to re-read the data correctly. This strategy prevents invoking correction on
non-repeatable errors. Each time a sector in error is re-read a set of ECC syndromes is
computed. If all of the syndrome values equal zero, the data was read with no errors, and
the sector is transferred to the host system. If any of the syndrome values do not equal
zero, an error has occurred, the syndrome values are retained, and another re-read is
invoked.

Note: Non-repeatable errors are usually related to the signal to noise ratio

of the system. They are not due to media defects.

When the sets of syndromes from two consecutive re-reads are the same, a stable
syndrome has been achieved. This event may be significant depending on whether the
automatic read reallocation or early correction features have been enabled. If the early
correction feature has been enabled and a stable syndrome has been achieved, triple­burst ECC correction is applied, and the appropriate message is transferred to the host
system (e.g., corrected data, etc.).

Note: These features can be enabled or disabled through the ATA Set

Configuration command. The EEC bit enables early ECC triple-burst
correction if a stable syndrome has been achieved before all of the
re-reads have been exhausted. The ARR bit enables the automatic
reallocation of defective sectors.

If the automatic read reallocation feature is enabled, the drive, when encountering triple­burst errors, will attempt to re-read up to 8 times the retry count set in the AT
Configuration bytes.

Note: The Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT drives are shipped

from the factory with the automatic read reallocation feature en­abled so that any new defective sectors can be easily and automat­ically reallocated for the average AT end user.

5.5.4 Defect Management

The Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT drives allocate 32 sectors per 65,504
sectors. In the factory, the media is scanned for defects. If a sector on a cylinder is found
to be defective, the address of the sector is added to the drive’s defect list. Sectors located
physically subsequent to the defective sector are assigned logical block addresses such
that a sequential ordering of logical blocks is maintained. This inline sparing technique
is employed in an attempt to eliminate slow data transfer that would result from a single
defective sector on a cylinder.

If more than 32 sectors are found defective within 65,504 sectors, the above inline
sparing technique is applied to the 32 sectors only. The remaining defective sectors are
replaced with the nearest available pool of spares.

5-22 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

Basic Principles of Operation

Defects that occur in the field are known as grown defects. If such a defective sector is
found in the field, the sector is reallocated according to the same algorithm used at the
factory for those sectors that are found defective after the first 32 spares per pool of
spares; that is, inline sparing is not performed on these grown defects. Instead, the sector
is reallocated to an available spare sector on a nearby available pool of spares.

Sectors are considered to contain grown defects if the triple-burst ECC algorithm must
be applied to recover the data. If this algorithm is successful, the corrected data is stored
in the newly allocated sector. If the algorithm is not successful, the erroneous data is
stored in the newly allocated sector, and a flag is set in the data ID field that causes the
drive to report an ECC error each time the sector is read. This condition remains until the
sector is rewritten.

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 5-23

Basic Principles of Operation

5-24 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

Chapter 6

IDE BUS INTERFACE AND ATA COMMANDS

This chapter describes the interface between Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT
hard disk drives and the IDE bus. The commands that are issued from the host to control
the drive are listed, as well as the electrical and mechanical characteristics of the
interface.

6.1 INTRODUCTION

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT hard disk drives use the standard IBM PC IDE
bus interface, and are compatible with systems that provide an IDE interface connector
on the motherboard. It may also be used with a third-party adapter board in systems that
do not have a built-in IDE adapter. The adapter board plugs into a standard 16-bit
expansion slot in an AT-compatible computer. A cable connects the drive to the adapter
board.

6.2 SOFTWARE INTERFACE

The Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT drives are controlled by the Basic Input/
Output System (BIOS) program residing in an IBM PC AT, or IBM compatible PC. The BIOS
communicates directly with the drive’s built-in controller. It issues commands to the drive
and receives status information from the drive.

6.3 MECHANICAL DESCRIPTION

6.3.1 Drive Cable and Connector

The hard disk drive connects to the host computer by means of a cable. This cable has a
40-pin connector that plugs into the drive, and a 40-pin connector that plugs into the
host computer. At the host end, the cable plugs into either an adapter board residing in
a host expansion slot, or an on-board IDE adapter.

If two drives are connected by a cable with two 40-pin drive connectors, the cable-select
feature of the Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT drive automatically configures
each as either drive 0 or drive 1 depending on the configuration of pin 28 on the
connector. See Section 3.3.1, "Cable Select (CS) Jumper," for more information about the
cable select jumper.

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 6-1

IDE Bus Interface and ATA Commands

6.4 ELECTRICAL INTERFACE

6.4.1 IDE Bus Interface

A 40-pin IDE interface connector on the motherboard or an adapter board provides an
interface between the drive and a host that uses an IBM PC AT bus. The IDE interface
contains bus drivers and receivers compatible with the standard AT bus. The AT-bus
interface signals D8–D15, INTRQ, and IOCS16– require the IDE adapter board to have an
extended I/O-bus connector.

The IDE interface buffers data and controls signals between the drive and the AT bus of
the host system, and decodes addresses on the host address bus. The Command Block
Registers on the drive accept commands from the host system BIOS.

Note: Some host systems do not read the Status Register after the drive

issues an interrupt. In such cases, the interrupt may not be
acknowledged. To overcome this problem, you may have to
configure a jumper on the motherboard or adapter board to allow
interrupts to be controlled by the drive’s interrupt logic. Read your
motherboard or adapter board manual carefully to find out how to
do this.

6.4.1.1 Electrical Characteristics

All signals are transistor-transistor logic (TTL) compatible—with logic 1 greater than 2.0
volts and less than 5.25 volts; and logic 0 greater than 0.0 volts and less than 0.8 volts.

6.4.1.2 Drive Signals

The drive connector (J1, section C) connects the drive to an adapter board or onboard IDE
adapter in the host computer. J1, section C is a 40-pin shrouded connector with two rows
of 20 pins on 100-mil centers. J1 has been keyed by removing pin 20. The connecting
cable is a 40-conductor flat ribbon cable with a maximum length of 18 inches.

Table 6-1 describes the signals on the drive connector (J1, section C). The drive does not
use all of the signals provided by the IDE bus. Table 6-4 shows the relationship between
the drive connector (J1, section C) and the IDE bus.

Note: In Table 6-1, the following conventions apply:

A minus sign follows the name of any signal that is asserted as
active low.
Direction (DIR) is in reference to the drive.
IN indicates input to the drive.
OUT indicates output from the drive.
I/O indicates that the signal is bidirectional.

6-2 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

µ

IDE Bus Interface and ATA Commands

Table 6-1

SIGNAL NAME DIR PIN DESCRIPTION

Reset RESET– IN 1 Drive reset signal from the host system, inverted on

Ground Ground — 2 Ground between the host system and the drive.

Data Bus I/O 3–18 An 8/16-bit, bidirectional data bus between the host

Drive Connector Pin Assignments (J1, Section C)

the adapter board or motherboard.
This signal from the host system will be asserted
beginning with the application of power, and held
asserted until at least 25 µ s after voltage levels have
stabilized within tolerance during power on. It will be
negated thereafter unless some event requires that the
device(s) be reset following power on.
ATA devices will not recognize a signal assertion
shorter than 20 ns as a valid reset signal. Devices may
respond to any signal assertion greater than 20 ns,
and will recognize a signal equal to or greater than 25

s.

The drive has a 10k Ω pull-up resistor on this signal.

and the drive. D0–D7 are used for 8-bit transfers, such

as registers and ECC bytes.
DD0 17 Bit 0
DD1 15 Bit 1
DD2 13 Bit 2
DD3 11 Bit 3
DD4 9 Bit 4
DD5 7 Bit 5
DD6 5 Bit 6
DD7 3 Bit 7
DD8 4 Bit 8
DD9 6 Bit 9

DD10 8 Bit 10
DD11 10 Bit 11
DD12 12 Bit 12
DD13 14 Bit 13
DD14 16 Bit 14
DD15 18 Bit 15

Ground Ground — 19 Ground between the host system and the drive.

Keypin KEYPIN — 20 Pin removed to key the interface connector.

DMA Request DMARQ OUT 21 Asserted by the drive when it is ready to exchange

data with the host. The direction of the data transfer is

determined by DIOW– and DIOR–. DMARQ is used in

conjunction with DMACK–. The drive has a 10k Ω

pull-down resistor on this signal.

Ground Ground — 22 Ground between the host system and the drive.

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 6-3

IDE Bus Interface and ATA Commands

Table 6-1

SIGNAL NAME DIR PIN DESCRIPTION

I/O Write DIOW– IN 23 The rising edge of this write strobe provides a clock

Ground Ground — 24 Ground between the host system and the drive.

I/O Read DIOR– IN 25 The rising edge of this read strobe provides a clock for

Ground Ground — 26 Ground between the host system and the drive.

I/O Channel Ready IORDY OUT 27 When the drive is not ready to respond to a data

Cable Select — 28 This is a signal from the host that allows the drive to

DMA Acknowledge DACK1– IN 29 Used by the host to respond to the drive’s DMARQ

Ground Ground — 30 Ground between the host system and the drive.

Interrupt Request INTRQ OUT 31 An interrupt to the host system. Asserted only when

Drive Connector Pin Assignments (J1, Section C) (Continued)

for data transfers from the host data bus (DD0–DD7 or
DD0–DD15) to a register or to the drive’s data port.

data transfers from a register or the drive’s data port
to the host data bus (DD0–DD7 or DD0–DD15). The
rising edge of DIOR– latches data at the host.

transfer request, the IORDY signal is asserted active
low to extend the host transfer cycle of any host
register read or write access. When IORDY is
deasserted, it is in a high-impedance state and it is the
host’s responsibility to pull this signal up to a high
level (if necessary).

be configured as drive 0 when the signal is 0
(grounded), and as drive 1 when the signal is 1 (high).
The drive has a 10k Ω pull-up resistor on this signal.

signal. DMARQ signals that there is more data
available for the host.

the drive microprocessor has a pending interrupt, the
drive is selected, and the host clears nIEN in the
Device Control Register. When nIEN is a 1 or the drive
is not selected, this output signal is in a high­impedance state, regardless of the presence or absence
of a pending interrupt.

INTRQ is deasserted by an assertion of RESET–, the
setting of SRST in the Device Control Register, or
when the host writes to the Command Register or
reads the Status Register.

When data is being transferred in programmed I/O
(PIO) mode, INTRQ is asserted at the beginning of each
data block transfer. Exception: INTRQ is not asserted
at the beginning of the first data block transfer that
occurs when any of the following commands
executes: FORMAT TRACK, Write Sector, WRITE
BUFFER, or WRITE LONG.

16-Bit I/O IOCS16– OUT 32 An open-collector output signal. Indicates to the host

system that the 16-bit data port has been addressed,
and that the drive is ready to send or receive a 16-bit
word. When transferring data in PIO mode, if IOCS16–
is not asserted, D0–D7 are used for 8-bit transfers; if
IOCS16– is asserted, D0–D15 are used for 16-bit data
transfers.

Drive Address Bus A 3-bit, binary-coded address supplied by the host

when accessing a register or the drive’s data port.

6-4 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

IDE Bus Interface and ATA Commands

Table 6-1

SIGNAL NAME DIR PIN DESCRIPTION

Bit 1 DA1 IN 33
Bit 0 DA0 IN 35
Bit 2 DA2 IN 36

Passed Diagnostics PDIAG– I/O 34 Drive 0 (Master) monitors this Drive 1 (Slave) open-

Drive Connector Pin Assignments (J1, Section C) (Continued)

collector output signal, which indicates the result of a

diagnostics command or reset. The drive has a 10K

pull-up resistor on this signal.

Following the receipt of a power-on reset, software

reset, or RESET– drive 1 negates PDIAG– within 1 ms.

PDIAG– indicates to drive 0 that drive 1 is busy

(BSY=1). Then, drive 1 asserts PDIAG– within 30

seconds, indicating that drive 1 is no longer busy

(BSY=0) and can provide status information.

Following the assertion of PDIAG–, drive 1 is unable

to accept commands until drive 1 is ready (DRDY=1)—

that is, until the reset procedure for drive 1 is

complete.

Following the receipt of a valid EXECUTE DRIVE

DIAGNOSTIC command, drive 1 negates PDIAG–

within 1 ms, indicating to drive 0 that it is busy and

has not yet passed its internal diagnostics. If drive 1 is

present, drive 0 waits for drive 1 to assert PDIAG– for

up to 5 seconds after the receipt of a valid EXECUTE

DRIVE DIAGNOSTIC command. Since PDIAG–

indicates that drive 1 has passed its internal

diagnostics and is ready to provide status, drive 1

clears BSY prior to asserting PDIAG–.

If drive 1 fails to respond during reset initialization,

drive 0 reports its own status after completing its

internal diagnostics. Drive 0 is unable to accept

commands until drive 0 is ready (DRDY=1)—that is,

until the reset procedure for drive 0 is complete.

Chip Select 0 CS1FX– IN 37 Chip-select signal decoded from the host address bus.

Used to select the host-accessible Command Block

Registers.

Chip Select 1 CS3FX– IN 38 Chip select signal decoded from the host address bus.

Used to select the host-accessible Control Block

Registers.

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 6-5

IDE Bus Interface and ATA Commands

Table 6-1

SIGNAL NAME DIR PIN DESCRIPTION

Drive Active/Slave

Present

Ground Ground — 40 Ground between the host system and the drive.

Series termination resistors are required at both the host and the device for operation in
any of the Ultra DMA/33 modes. Table 6-2 describes recommended values for series
termination at the host and the device.

Drive Connector Pin Assignments (J1, Section C) (Continued)

DASP– I/O 39 A time-multiplexed signal that indicates either drive

activity or that drive 1 is present. During power-on
initialization, DASP– is asserted by drive 1 within 400
ms to indicate that drive 1 is present. If drive 1 is not
present, drive 0 asserts DASP– after 450 ms to light
the drive-activity LED.

An open-collector output signal, DASP– is deasserted
following the receipt of a valid command by drive 1
or after the drive is ready, whichever occurs first. Once
DASP– is deasserted, either hard drive can assert
DASP– to light the drive-activity LED. Each drive has
a 10K pull-up resistor on this signal.

If an external drive-activity LED is used to monitor
this signal, an external resistor must be connected in
series between the signal and a +5 volt supply in order
to limit the current to 24 mA maximum.

Table 6-2

Series Termination for Ultra DMA/33

SIGNAL HOST TERMINA TION DEVICE TERMINATION

DIOR–/HDMARDY–/HSTROBE 33 Ω

DIOW–/STOP 33 Ω

CS0–, CS1– 33 Ω

DA0, DA1, DA2 33 Ω

DMACK– 33 Ω

DD 15 through DD0 33 Ω

DMARQ 82 Ω

INTRQ 82 Ω

IORDY/DDMARDY–/DSTROBE 82 Ω

Note: Only those signals requiring termination are listed in this table. If

a signal is not listed, series termination is not required for operation
in an Ultra DMA/33 mode.

82 Ω
82 Ω
82 Ω
82 Ω
82 Ω
33 Ω
33 Ω
33 Ω
22 Ω

6-6 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

6.4.1.3 IDE Bus Signals

See Table 6-4 for the relationship between the drive signals and the IDE bus.

Signal Line Definitions (Ultra DMA/33)

Several existing ATA signal lines are redefined during the Ultra DMA/33 protocol to
provide new functions. These lines change from old to new definitions the moment the
host decides to allow a DMA burst, if the Ultra DMA/33 transfer mode was previously
chosen via Set Features. The drive becomes aware of this change upon assertion of the
–DMACK line. These lines revert back to their original definitions upon the deassertion
of –DMACK at the termination of the DMA burst.

IDE Bus Interface and ATA Commands

Table 6-3

NEW DEFINITION OLD DEFINITION

DMARQ = DMARQ

–DMACK = –DMACK

(These two signals remain unchanged to ensure backward compatibility with

–DMARDY

STROBE

STOP = –DIOW

Signal Line Definitions

PIO modes)

= IORDY on WRITE commands

= –DIOR on READ commands

= –DIOR on WRITE commands

= IORDY on READ commands

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 6-7

IDE Bus Interface and ATA Commands

Table 6-4

J1 PIN

NUMBER

28 CABLE SELECT —> CSEL
37 CHIP SELECT 0 —> CS0–
38 CHIP SELECT 1 <—> CS1–
17 DATA BUS BIT 0 <—> DD0
15 DATA BUS BIT 1 <—> DD1
13 DATA BUS BIT 2 <—> DD2
11 DATA BUS BIT 3 <—> DD3

9 DATA BUS BIT 4 <—> DD4
7 DATA BUS BIT 5 <—> DD5
5 DATA BUS BIT 6 <—> DD6
3 DATA BUS BIT 7 <—> DD7
4 DATA BUS BIT 8 <—> DD8
6 DATA BUS BIT 9 <—> DD9

8 DATA BUS BIT 10 <—> DD10
10 DATA BUS BIT 11 <—> DD11
12 DATA BUS BIT 12 <—> DD12
14 DATA BUS BIT 13 <—> DD13
16 DATA BUS BIT 14 <—> DD14
18 DATA BUS BIT 15 <—> DD15
39 DEVICE ACTIVE OR SLAVE

35 DEVICE ADDRESS BIT 0 —> DA0
33 DEVICE ADDRESS BIT 1 —> DA1
36 DEVICE ADDRESS BIT 2 —> DA2
29 DMA ACKNOWLEDGE —> DMACK–
21 DMA REQUEST <— DMARQ
31 INTERRUPT REQUEST <— INTRQ
25 I/O READ

DMA ready on data in bursts (see note 2)

Data strobe on data out bursts (see note 2)

27 I/O READY

DMA ready on data out bursts (see note 2)

Data strobe on data in bursts (see note 2)

DESCRIPTION HOST DIR DEV ACRONYM

(DEVICE 1) PRESENT

Interface Signal Name Assignments

(See Note 1) DASP–

—>
—>
—>

<—
<—
<—

HDMARDY–

DDMARDY–

DIOR–

HSTROBE

IORDY

DSTROBE

23 I/O WRITE

STOP (see note 2)

34 PASSED DIAGNOSTCS (See Note 1) PDIAG–

1 RESET —> RESET
32 I/O CS16 <— IOCS16

Note: 1.See signal descriptions for information on source of these signals.

2.Used during Ultra DMA protocol only.

3.Pins numbered 2, 19, 22, 24, 26, 30, and 40 are ground.

4.Pin number 20 is the Key Pin.

6-8 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

—>
—>

DIOW–

STOP

6.4.2 Host Interface Timing

6.4.2.1 Programmed I/O (PIO) Transfer Mode

The PIO host interface timing shown in Table 6-5 is in reference to signals at 0.8 volts
and 2.0 volts. All times are in nanoseconds, unless otherwise noted. Figure 6-1 provides
a timing diagram.

IDE Bus Interface and ATA Commands

Table 6-5

SYMBOL DESCRIPTION MIN/MAX

t0 Cycle Time min 120 120

t1 Address Valid to DIOW–/DIOR–Setup min 25 25
t2 DIOW–/DIOR– Pulsewidth (8- or 16-bit) min 70 70

t2i DIOW–/DIOR– Negated Pulsewidth min 25 25

t3 DIOW–Data Setup min 20 20
t4 DIOW– Data Hold min 10 10
t5 DIOR– Data Setup min 20 20

t5a DIOR– to Data Valid max — —

t6 DIOR– Data Hold min 5 5

t6z DIOR– Data Tristate max 30 30

t7 Address Valid to IOCS16– Assertion max N/A N/A
t8 Address Valid to IOSC16– Deassertion max N/A N/A
t9 DIOW–/DIOR– to Address Valid Hold min 10 10

tA IORDY Setup Time min 35 35

tB IORDY Pulse Width max 1250 1250
tR

1. ATA Mode 4 timing is listed for reference only.

Read Data Valid to IORDY active

(if IORDY is initially low after tA)

PIO Host Interface Timing

min 0 0

MODE 4

(local bus)

1

FIREBALL ST

QUANTUM

AT

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 6-9

IDE Bus Interface and ATA Commands

Address

t 7

IOCS16

DIOW­DIOR-

IORDY

Read Data

Write Data

t 1

t A

t 5a

t 2

t B

t R

t 5

t 3

Figure 6-1

6.4.2.2 Multiword DMA Transfer Mode

The multiword DMA host interface timing shown in Table 6-6 is in reference to signals
at 0.8 volts and 2.0 volts. All times are in nanoseconds, unless otherwise noted. Figure 6­2 provides a timing diagram.

t 0

t 8

t 9

t 2i

t 6z

t 6

t 4

PIO Interface Timing

Table 6-6

SYMBOL DESCRIPTION MIN/MAX

t0 Cycle Time min

Multiword DMA Host Interface Timing

MODE 2

(local bus)

120 120

QUANTUM

1

FIREBALL ST

tD DIOR–/DIOW– Pulsewidth min 70 70

tE DIOR– to Data Valid max – –
tF DIOR– Data Hold min 5 5

tFz DIOR– Data Tristate

2

max 20 20
tG DIOW– Data Setup min 20 20
tH DIOW– Data Hold min 10 10

tI DMACK to DIOR–/DIOW– Setup min 0 0

tJ DIOR–/DIOW– to DMACK– Hold min 5 5

tK DIOR–/DIOW– Negated Pulsewidth min 25 25

tL DIOR–/DIOW– to DMARQ Delay max 35 35
tz DMACK– Data Tristate

3

max 25 25

1. ATA Mode 2 timing is listed for reference only.

2. The Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT drive tristates after each word
transferred.

3. Symbol tz only applies on the last tristate at the end of a multiword DMA transfer cycle.

AT

6-10 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

DMARQ
DMACK-

t 0

IDE Bus Interface and ATA Commands

t L

DIOW­DIOR-

Read DD0-15

Write DD0-15

NAME

t I

t E t F

t G t H

Figure 6-2

Table 6-7

Ultra DMA Data Transfer Timing Requirements

MODE 0

(ns)

MIN MAX MIN MAX MIN MAX

Multiword DMA Bus Interface Timing

MODE 1

(ns)

t Fz

t Kt D

MODE 2

(ns)

t J

t Z

COMMENTS

Tcyc 114 75 55 Cycle time (from STROBE edge to

STROBE edge)

T2cyc 235 156 117 Two cycle time (from rising edge to

next rising edge or from falling edge to
next falling edge of STROBE)

Tds 15 10 7 Data setup time (at receiver)

Tdh 5 5 5 Data hold time (at receiver)

Tdvs 70 48 34 Data valid setup time (at sender) - time

from data bus being valid until STROBE
edge

Tdvh 6 6 6 Data valid hold time (at sender) - time

from STROBE edge until data may go
invalid

Tfs 0 230 0 200 0 170 First STROBE - time for device to send

first STROBE.

Tli 0 150 0 150 0 150 Limited interlock time - time allowed

between an action by one agent (either
host or device) and the following action
by the other agent

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 6-11

IDE Bus Interface and ATA Commands

NAME

MODE 0

(ns)

MIN MAX MIN MAX MIN MAX

MODE 1

(ns)

MODE 2

(ns)

COMMENTS

Tmli 20 20 20 Interlock time with minimum

Tui 0 0 0 Unlimited interlock time
Taz 10 10 10 Maximum time allowed for outputs to

release
Tzah 20 20 20 Minimum delay time required for
Tzad 0 0 0

output drivers turning on (from released

state)
Tenv 20 70 20 70 20 70 Envelope time (all control signal

transitions are within the DMACK

envelope by this much time)

Tsr 50 30 20 STROBE to DMARDY- response time to

ensure the synchronous pause case

(when the receiver is pausing)

Trfs 75 60 50 Ready-to-final-STROBE time (this long

after receiving DMARDY- negation, no

more STROBE edges may be sent)

Trp 160 125 100 Ready-to-pause time—time until a

receiver may assume that the sender has

paused after negation of DMARDY-

Tiordyz 20 20 20 Pull-up time before allowing IORDY to

be released

Tziordy 0 0 0 Minimum time device shall wait before

driving IORDY
Tack 20 20 20 Setup and hold times before assertion

and negation of DMACK-

Tss 50 50 50 Time from STROBE edge to STOP

assertion (when the sender is stopping)

Notes:

1. The timing parameters Tui and Tli indicate device-to-host or host-to-device
interlocks, that is, one agent (either host or device) is waiting for the other agent to
respond with a signal on the bus before proceeding. Tui is an unlimited interlock,
or one which has no maximum time value. Tli is a limited time-out, or one which
has a defined maximum.

2. All timing parameters are measured at the connector of the device to which the
parameter applies. For example, the sender shall stop toggling STROBE Trfs ns
after the negation of DMARDY-. Both STROBE and DMARDY- timing
measurements are taken at the connector of the sender.

3. All timing measurement switching points (low to high and high to low) are to
be taken at 1.5V.

Figures 6-3 through 6-12 define the timings associated with all phases of Ultra DMA
transfers.

6-12 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

IDE Bus Interface and ATA Commands

Table 6-7 contains the values for the timings for each of the Ultra DMA transfer modes.

DMARQ

(device)

Tui

DMACK-

(host)

Tack

STOP

(host)

Tack

HDMARDY-

(host)

Tziordy

DSTROBE

(device)

DD(15:0)

Tenv

Taz

Tenv

Tzad
Tzad

Tfs

Tfs

Tdvs

Tdvh

DA0, DA1, DA2,

CS0-, CS1-

DSTROBE

at device

DD(15:0)

at device

DSTROBE

at host

DD(15:0)

at host

Tdh

Tack

Figure 6-3

Tcyc Tcyc

Tdvh

Figure 6-4

Initiating a Data In Burst

T2cyc

Tdvs Tdvs

Tdvh

Tds Tdh Tds

Sustained Data In Burst

T2cyc

Tdvh

Tdh

Note: DD(15:0) and DSTROBE signals are shown at both the host and the device

to emphasize that cable settling time as well as cable propagation delay
shall not allow the data signals to be considered stable at the host until well

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 6-13

IDE Bus Interface and ATA Commands

after they are driven by the device.

DMARQ
(device)

DMACK-

(host)

STOP

(host)

HDMARDY

(host)

DSTROBE

(device)

DD(15:0)

(device)

Note: The host knows the burst is fully paused Trp ns after HDMARDY- is negated and

Trp

Tsr

Trfs

Figure 6-5

Host Pausing a Data In Burst

may then assert STOP to terminate the burst. Tsr timing need not be met for an
asynchronous pause.

6-14 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

DMARQ
(device)

DMACK-

(host)

STOP

(host)

HDMARDY-

(host)

DSTROBE

(device)

Tss

Taz

Tli

Tli

Tzah

Tli

IDE Bus Interface and ATA Commands

Tdvs

Tmli

Tack

Tack

Tiordyz

Tdvh

DD(15:0)

DA0, DA1, DA2,

CS0-, CS1-

Figure 6-6

CRC

Tack

Device Terminating a Data In Burst

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 6-15

IDE Bus Interface and ATA Commands

DMARQ
(device)

DMACK-

(host)

Trp

STOP

(host)

HDMARDY-

(host)

Trfs

DSTROBE

(device)

DD(15:0)

Tli

Tli

Taz

Tzah

Tmli

Tmli

Tdvs

CRC

Tdvh

Tack

Tack

Tiordyz

DA0, DA1, DA2,

CS0-, CS1-

Figure 6-7

Tack

Host Terminating a Data In Burst

6-16 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

DMARQ
(device)

DMACK-

(host)

STOP
(host)

Tui

Tack Tenv

IDE Bus Interface and ATA Commands

DDMARDY-

(device)

HSTROBE

(host)

DD(15:0)

(host)

DA0, DA1, DA2,

CS0-, CS1-

HSTROBE

at host

DD(15:0)

at host

Tziordy Tli

Tack

Tack

Figure 6-8

Tcyc Tcyc

Tdvh

Initiating a Data Out Burst

T2cyc

Tdvs Tdvs

Tdvh

Tui

Tdvs

Tdvh

T2cyc

Tdvh

HSTROBE

at device

DD(15:0)
at device

Note: DD(15:0) and HSTROBE signals are shown at both the device and the host to

Tdh

Tds Td h

Figure 6-9

Tds

Sustained Data Out Burst

Tdh

emphasize that cable settling time as well as cable propagation delay shall not
allow the data signals to be considered stable at the device until well after they
are driven by the host.

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 6-17

IDE Bus Interface and ATA Commands

DMARQ
(device)

DMACK-

(host)

STOP

(host)

DDMARDY-

(device)

HSTROBE

(host)

DD(15:0)

(host)

Tsr

Trfs

Trp

Figure 6-10

Device Pausing a Data Out Burst

Note: The device knows the burst is fully paused Trp ns after DDMARDY- is negated

and may then negate DMARQ to terminate the burst. Tsr timing need not be met
for an asynchronous pause.

DMARQ

(device)

DMACK-

(host)

Tss

STOP

(host)

DDMARDY-

(device)

HSTROBE

(host)

DD(15:0)

(host)

DA0, DA1, DA2,

CS0-, CS1-

Tli

Tli

Tli

Tmli

Tack

Tiordyz

Tack

Tdvs

Tdvh

CRC

Tack

Figure 6-11

Host Terminating a Data Out Burst

6-18 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

DMARQ

(device)

DMACK-

(host)

TmliTrp
Tmli

IDE Bus Interface and ATA Commands

tM

STOP
(host)

DDMARDY-

(device)

Trfs

HSTROBE

(host)

DD(15:0)

(host)

DA0, DA1, DA2,

CS0-, CS1-

Figure 6-12

Device Terminating a Data out Burst

6.4.2.3 Host Interface RESET Timing

The host interface RESET timing shown in Table 6-8 is in reference to signals at 0.8 volts
and 2.0 volts. All times are in nanoseconds, unless otherwise noted. Figure 6-13 provides
a timing diagram.

Tli

Tli

Tack

Tiordyz

Tack

Tdvs

Tdvh

CRC

Tack

Table 6-8

Host Interface RESET Timing

SYMBOL DESCRIPTION MINIMUM MAXIMUM

RESET– Pulse width

t MRESET-

Figure 6-13

Host Interface RESET Timing

300 —

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 6-19

IDE Bus Interface and ATA Commands

6.5 REGISTER ADDRESS DECODING

The host addresses the drive by using programmed I/O. Host address lines A0–A2, chip­select CS1FX– and CS3FX–, and IOR– and IOW– address the disk registers. Host address
lines A3–A9 generate the two chip-select signals, CS1FX– and CS3FX–.

• Chip Select CS1FX– accesses the eight Command Block Registers.

• Chip Select CS3FX– is valid during 8-bit transfers to or from the Alternate
Status Register.

The drive selects the primary or secondary command block addresses by setting Address
bit A7.

Data bus lines 8–15 are valid only when IOCS16– is active and the drive is transferring
data. The drive transfers ECC information only on data bus lines 0–7. Data bus lines 8–
15 are invalid during transfers of ECC information.

I/O to or from the drive occurs over an I/O port that routes input or output data to or from
selected registers, by using the following encoded signals from the host: CS1FX–, CS3FX–
, DA2, DA1, DA0, DIOR–, and DIOW–. The host writes to the Command Block Registers
when transmitting commands to the drive, and to the Control Block Registers when
transmitting control, like a software reset. Table 6-9 lists the selection addresses for these
registers.

Table 6-9

I/O Port Functions and Selection Addresses

FUNCTION HOST SIGNALS

CONTROL BLOCK REGISTERS CS1FX– CS3FX– DA2 DA1 DA0

READ (DIOR–) WRITE (DIOW–)

Data Bus High Impedance Not Used N

1

Data Bus High Impedance Not Used N A

NX

3

2

XX

0XX

Data Bus High Impedance Not Used N A 1 0 X

Alternate Status Device Control N A 1 1 0

Drive Address Not Used N A 1 1 1

COMMAND BLOCK REGISTERS

READ (DIOR–) WRITE (DIOW–)

Data Port Data Port A N 0 0 0

Error Register Features A N 0 0 1

Sector Count Sector Count A N 0 1 0

Sector Number

LBA Bits 0–7
Cylinder Low

LBA Bits 8–15

Cylinder High

LBA Bits 16–23

Drive/Head

4

5

4

5

4

5

4

Sector Number A N 0 1 1

LBA Bits 0–7 A N 0 1 1

Cylinder Low A N 1 0 0

LBA Bits 8–15 A N 1 0 0

Cylinder High A N 1 0 1

LBA Bits 16–23 A N 1 0 1

Drive/Head A N 1 1 0

6-20 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

IDE Bus Interface and ATA Commands

FUNCTION HOST SIGNALS

LBA Bits 24–27

5

LBA Bits 24–27 A N 1 1 0

Status Command A N 1 1 1

Invalid Address Invalid Address A A X X X

1. N = signal deasserted

2. X = signal either asserted or deasserted

3. A = signal asserted

4. Mapping of registers in CHS mode

5. Mapping of registers in LBA mode
After power on or following a reset, the drive initializes the Command Block Registers to

the values shown in Table 6-10.

Table 6-10

Sector Count Register 01

Sector Number Register 01

Cylinder Low Register 00

Cylinder High Register 00

Drive/Head Register 00

Command Block Register Initial Values

REGISTER VALUE

Error Register 01

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 6-21

IDE Bus Interface and ATA Commands

6.6 REGISTER DESCRIPTIONS

The Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT hard disk drives emulate the ATA
Command and Control Block Registers. Functional descriptions of these registers are
given in the next two sections.

6.6.1 Control Block Registers

6.6.1.1 Alternate Status Register

The Alternate Status Register contains the same information as the Status Register in the
command block. Reading the Alternate Status Register does not imply the
acknowledgment of an interrupt by the host or clear a pending interrupt. See the
description of the Status Register in section 6.6.2.8 for definitions of bits in this register.

6.6.1.2 Device Control Register

This write-only register contains two control bits, as shown in Table 6-11.

Table 6-11

BIT MNEMONIC DESCRIPTION

7 Reserved –
6 Reserved –
5 Reserved –
4 Reserved –
3 1 Always 1
2 SRST
1 nIEN
0 0 Always 0

1. SRST = Host Software Reset bit. When the host sets this bit,
the drive is reset. When two drives are daisy-chained on the
interface, this bit resets both drives simultaneously.

2. nIEN = Drive Interrupt Enable bit. When nIEN equals 0 or
the host has selected the drive, the drive enables the host
interrupt signal INTRQ through a tristate buffer to the host.
When nIEN equals 1 or the drive is not selected, the host
interrupt signal INTRQ is in a high-impedance state,
regardless of the presence or absence of a pending
interrupt.

Device Control Register Bits

1

2

Host software reset bit

Drive interrupt enable bit

6-22 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

6.6.1.3 Drive Address Register

The Drive Address Register returns the head-select addresses for the drive currently
selected. Table 6-12 shows the Drive Address bits.

IDE Bus Interface and ATA Commands

Table 6-12

Drive Address Register Bits

BIT MNEMONIC DESCRIPTION

7 HiZ
6 nWTG
5 nHS3

1

2

3

High Impedance bit

Write Gate bit

Head Address msb
4 nHS2 –
3 nHS1 –
2 nHS0 Head Address lsb
1 nDS1

4

Drive 1 Select bit

0 nDS0 Drive 0 Select bit

1. HiZ = High Impedance bit. When the host
reads the register, this bit will be in a high
impedance state.

2. nWTG = Write Gate bit. When a write
operation to the drive is in progress, nWTG
equals 0.

3. nHS0–nHS3 = Head Address bits. These bits
are equivalent to the one’s complement of the
binary-coded address of the head currently
selected.

4. nDS0–nDS1 = Drive Select bits. When drive 1
is selected, nDS1 equals 0. When drive 0 is
selected, nDS0 equals 0.

6.6.2 Command Block Registers

6.6.2.1 Data Port Register

All data transferred between the device data buffer and the host passes through the Data
Port Register. The host transfers the sector table to this register during execution of the
FORMAT TRACK command. Transfers of ECC bytes during the execution of READ LONG
or WRITE LONG commands are 8-bit transfers.

6.6.2.2 Error Register

The Error Register contains status information about the last command executed by the
drive. The contents of this register are valid only when the Error bit (ERR) in the Status
Register is set to 1. The contents of the Error Register are also valid at power on, and at
the completion of the drive’s internal diagnostics, when the register contains a status
code. When the error bit in the Status Register is set to 1, the host interprets the Error
Register bits as shown in Table 6-13.

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 6-23

IDE Bus Interface and ATA Commands

Table 6-13 Error Register Bits

MNEMONIC BIT DESCRIPTION

BBK 7 Bad block detected in the required sector’s ID field.
UNC 6 Uncorrectable data error encountered.

– 5 Not used.

IDNF 4 Requested sector’s ID field not found.

– 3 Not used.

ABRT 2

Requested command aborted due to a drive status error, such as Not

Ready or Write Fault, or because the command code is invalid.

TK0NF 1 Track 0 not found during execution of RECALIBRATE command.

AMNF 0 Data Address Mark not found after correct ID field format.

6.6.2.3 Sector Count Register

The Sector Count Register defines the number of sectors of data to be transferred across
the host bus for a subsequent command. If the value in this register is 0, the sector count
is 256 sectors. If the Sector Count Register command executes successfully, the value in
this register at command completion is 0. As the drive transfers each sector, it decrements
the Sector Count Register to reflect the number of sectors remaining to be transferred. If
the command’s execution is unsuccessful, this register contains the number of sectors
that must be transferred to complete the original request.

When the drive executes an INITIALIZE DRIVE PARAMETERS or Format Track command,
the value in this register defines the number of sectors per track.

6.6.2.4 Sector Number Register

The Sector Number Register contains the ID number of the first sector to be accessed by
a subsequent command. The sector number is a value between one and the maximum
number of sectors per track. As the drive transfers each sector, it increments the Sector
Number Register. See the command descriptions in section 6.7 for information about the
contents of the Sector Number Register after successful or unsuccessful command
completion.

In LBA mode, this register contains bits 0 to 7. At command completion, the host updates
this register to reflect the current LBA bits 0 to 7.

6.6.2.5 Cylinder Low Register

The Cylinder Low Register contains the eight low-order bits of the starting cylinder
address for any disk access. On multiple sector transfers that cross cylinder boundaries,
the drive updates this register when command execution is complete, to reflect the
current cylinder number. The host loads the least significant bits of the cylinder address
into the Cylinder Low Register.

In LBA mode, this register contains bits 8 to 15. At command completion, the drive
updates this register to reflect the current LBA bits 8 to 15.

6.6.2.6 Cylinder High Register

The Cylinder High Register contains the eight high-order bits of the starting cylinder
address for any disk access. On multiple sector transfers that cross cylinder boundaries,
the drive updates this register at the completion of command execution, to reflect the
current cylinder number. The host loads the most significant bits of the cylinder address

6-24 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

into the Cylinder High Register.
In LBA mode, this register contains bits 16 to 23. At command completion, the host

updates this register to reflect the current LBA bits 16 to 23.

6.6.2.7 Drive/Head Register

The Drive/Head Register contains the drive ID number and its head numbers. At command
completion this register is updated by the drive to reflect the current head.

In LBA mode, this register contains bits 24 to 27. At command completion, the drive
updates this register to reflect the current LBA bits 24 to 27.

Table 6-14 shows the Drive/Head Register bits.

IDE Bus Interface and ATA Commands

Table 6-14

Drive Head Register Bits

MNEMONIC BIT DESCRIPTION

Reserved 7

L6

1

2

Always 1

0 for CHS mode
1 for LBA mode

Reserved 5 Always 1

DRV 4

HS3 3

HS2 2

HS1 1

HS0 0

3

4

0 indicates the Master drive is selected

1 indicates the Slave drive is selected

Most significant Head Address bit in CHS mode

Bit 24 of the LBA Address in LBA mode

Head Address bit for CHS mode

Bit 25 of the LBA Address in LBA mode

Head Address bit for CHS mode

Bit 26 of the LBA Address in LBA mode

Least significant Head Address bit in CHS mode

Bit 27 of the LBA Address in LBA mode

1. Bits 5–7 define the sector size set in hardware (512 bytes).

2. Bit 6 is the binary encoded Address Mode Select. When bit 6 is set to 0,
addressing is by CHS mode. When bit 6 is set to 1, addressing is by LBA mode.

3. Bit 4 (DRV) contains the binary encoded drive select number. The Master is the
primary drive; the Slave is the secondary drive

4. In CHS mode, bits 3–0 (HS0–HS3) contain the binary encoded address of the
selected head. At command completion, the host updates these bits to reflect
the address of the head currently selected. In LBA mode, bits 3–0 (HS0–HS3)
contain bits 24–27 of the LBA Address. At command completion, the host
updates this register to reflect the current LBA bits 24 to 27.

6.6.2.8 Status Register

The Status Register contains information about the status of the drive and the controller.
The drive updates the contents of this register at the completion of each command. When
the Busy bit is set (BSY=1), no other bits in the Command Block Registers are valid. When
the Busy bit is not set (BSY=0), the information in the Status Register and Command
Block Registers is valid.

When an interrupt is pending, the drive considers that the host has acknowledged the
interrupt when it reads the Status Register. Therefore, whenever the host reads this

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 6-25

IDE Bus Interface and ATA Commands

register, the drive clears any pending interrupt. Table 6-15 defines the Status Register
bits.

6.6.2.9 Command Register

The host sends a command to the drive by means of an 8-bit code written to the
Command Register. As soon as the drive receives the command in its Command Register,
it begins execution of the command. Table 6-16 lists the hexadecimal command codes
and parameters for each executable command. The code F0h is common to all of the
extended commands. Each of these commands is distinguished by a unique subcode. For
a detailed description of each command, see Section 6.7, "COMMAND DESCRIPTIONS,"
found later in this chapter.

Table 6-15

MNEMONIC BIT DESCRIPTION

BSY 7 Busy bit. Set by the controller logic of the drive whenever the

drive has access to, and the host is locked out of the Command
Block Registers.
BSY is set under the following conditions:

• Within 400 ns after the deassertion of RESET- or after SRST is set
in the Device Control Register. Following a reset, BSY will be set for
no longer than 30 seconds.

• Within 400 ns of a host write to the Command Block Registers with
a Read, READ LONG, READ BUFFER, SEEK, RECALIBRATE,
INITIALIZE DRIVE PARAMETERS, Read Verify, Identify Drive, or
EXECUTE DRIVE DIAGNOSTIC command.

When BSY=1, the host cannot write to a Command Block Register
and reading any Command Block Register returns the contents of
the Status Register.

DRDY 6 Drive Ready bit. Indicates that the drive is ready to accept a command.

At power on, this bit should be cleared, and should remain cleared until
the drive is up to speed and ready to accept a command.

DWF 5 Drive Write Fault bit. Indicates a write fault condition exists in the drive.

DSC 4 Drive Seek Complete bit. This bit is set when a seek operation is com-

plete and the heads have settled over a track.

DRQ 3 Data Request bit. When set, this bit indicates that the drive is ready to

transfer a word or byte of data from the host to the data port.

CORR 2 Corrected Data bit. The drive sets this bit when it encounters and cor-

rects a correctable data error. This condition does not terminate a multi­sector read operation.

IDX 1 Index bit. This bit is set when the drive detects the index mark, once per

disk revolution.

ERR 0 Error bit. When set, this bit indicates that the previous command resulted

in an error. The other bits in the Status Register and the bits in the Error
Register contain additional information about the cause of the error.

Status Register Bits

6-26 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

IDE Bus Interface and ATA Commands

Table 6-16 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT Command Codes and Parameters

COMMAND PARAMETER

NAME CODE SC SN CY DS HD FR

RECALIBRATE 1Xh V
READ SECTORS, with retry 20h VVVVV
READ SECTORS, no retry 21h VVVVV
READ LONG, with retry 22h VVVVV
READ LONG, no retry 23h VVVVV
WRITE SECTORS, with retry 30h VVVVV
WRITE SECTORS, no retry 31h VVVVV
WRITE LONG, with retry 32h VVVVV
WRITE LONG, no retry 33h VVVVV
READ VERIFY SECTORS, with retry 40h VVVVV
READ VERIFY SECTORS, no retry 41h VVVVV
FORMAT TRACK 50h V V V V
SEEK 7Xh VVVV
EXECUTE DRIVE DIAGNOSTIC 90h
INITIALIZE DRIVE PARAMETERS 91h V V V
DOWNLOAD MICROCODE 92h VVVVV
SMART B0h V V
READ MULTIPLE C4h VVVVV
WRITE MULTIPLE C5h VVVVV
SET MULTIPLE MODE C6h V V
READ DMA, with retry C8h VVVVV
READ DMA, no retry C9h VVVVV
WRITE DMA, with retry CAh VVVVV
WRITE DMA, no retry CBh VVVVV
STANDBY IMMEDIATE E0h V
IDLE IMMEDIATE E1h V
STANDBY MODE (AUTO POWER-DOWN) E2h V V
IDLE MODE (AUTO POWER-DOWN) E3h V V
READ BUFFER E4h V
CHECK POWER MODE E5h V V
SLEEP MODE E6h V
WRITE BUFFER E8h V
IDENTIFY DRIVE ECh V
READ DEFECT LIST—extended cmnd. F0h VVVVV
READ CONFIGURATION—extended cmnd. F0h VVVVV
SET CONFIGURATION—extended cmnd. F0h VVVVV

Note: The following information applies to Table 6-16:

SC = Sector Count Register
SN = Sector Number Register
CY = Cylinder Low and High Registers
DS = Drive Select bit (Bit 4 of Drive/Head Register)
HD = 4 Head Select Bits (Bits 0–3 of Drive Head Register)
V = Must contain valid information for this command

FR = Features Register

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 6-27

IDE Bus Interface and ATA Commands

6.7 COMMAND DESCRIPTIONS

The Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT hard disk drives support all standard ATA
drive commands. The drive decodes, then executes, commands loaded into the Command
Block Register. In applications involving two hard drives, both drives receive all
commands. However, only the selected drive executes commands—with the exception of
the EXECUTE DRIVE DIAGNOSTIC command, as explained below. The procedure for
executing a command on the selected drive is as follows:

1. Wait for the drive to indicate that it is no longer busy (BSY=0).

2. Activate the Interrupt Enable (–IEN) bit.

3. Wait for the drive to set RDY (RDY=1).

4. Load the required parameters into the Command Block Register.

5. Write the command code to the Command Register.

Execution of the command begins as soon as the drive loads the Command Block
Register. The remainder of this section describes the function of each command. The
commands are listed in the same order they appear in Table 6-16.

6.7.1 Recalibrate 1xh

The RECALIBRATE command moves the read/write heads from any location on the disk
to cylinder 0. On receiving this command, the drive sets the BSY bit and issues a seek
command to cylinder 0. The drive then waits for the seek operation to complete, updates
status, negates BSY, and generates an interrupt. If the drive cannot seek to cylinder 0, it
posts the message TRACK 0 NOT FOUND.

6.7.2 Read Sectors 20h (with retry), 21h (without retry)

The Read Sectors command reads from 1 to 256 sectors, beginning at the specified sector.
As specified in the Command Block Register, a sector count equal to 0 requests 256
sectors. When the drive accepts this command, it sets BSY and begins execution of the
command.

6.7.2.1 Read Long 22h (with retry), 23h (without retry)

When the Long bit is set in the command code, a READ LONG command executes,
returning the data and four ECC bytes contained in the data field of the requested sector.
During a READ LONG operation, the drive does not check the ECC bytes to determine if
a data error of any kind has occurred.

6.7.2.2 Multiple Sector Reads

Multiple sector reads set DRQ. After reading each sector, the drive generates an interrupt
when the sector buffer is full, and the drive is ready for the host to read the data. Once
the host empties the sector buffer, the drive immediately clears DRQ and sets BSY.

If an error occurs during a multiple sector read, the read terminates at the sector in which
the error occurred. The Command Block Register contains the cylinder, head, and sector
numbers of the sector in which the error occurred. The host can then read the Command
Block Register to determine what kind of error has occurred, and in which sector. Whether
the data error is correctable or uncorrectable, the drive loads the data into the sector
buffer.

6-28 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

IDE Bus Interface and ATA Commands

6.7.3 Write Sector 30h (with retry), 31h (without retry)

The WRITE SECTOR command writes from 1 to 256 sectors, beginning at the specified
sector. As specified in the Command Block Register, a sector count equal to 0 requests
256 sectors. When the drive accepts this command, it sets DRQ and waits for the host to
fill the sector buffer with the data to be written to the drive. The drive does not generate
an interrupt to start the first buffer-fill operation. Once the buffer is full, the drive clears
DRQ, sets BSY, and begins execution of the command.

6.7.3.1 Write Long 32h (with retry), 33h (without retry)

When the Long bit is set in the command code, a WRITE LONG command writes the data
and the ECC bytes directly from the sector buffer. The drive does not generate the ECC
bytes itself.

6.7.3.2 Multiple Sector Writes

The MULTIPLE SECTOR WRITES command sets DRQ. The drive generates an interrupt
whenever the sector buffer is ready to be filled. When the host fills the sector buffer, the
drive immediately clears DRQ and sets BSY.

If an error occurs during a multiple sector write operation, the write operation terminates
at the sector in which the error occurred. The Command Block Register contains the
cylinder, head, and sector numbers of the sector in which the error occurred. The host can
then read the Command Block Register to determine what kind of error has occurred, and
in which sector.

6.7.4 Read Verify Sectors 40h (with retry), 41h (without retry)

The execution of the READ VERIFY SECTORS command is identical to that of the READ
SECTORS command. However, the Read Verify command does not cause the drive to set
DRQ, the drive transfers no data to the host, and the Long bit is invalid. On receiving the
READ VERIFY command, the drive sets BSY. When the drive has verified the requested
sectors, it clears BSY and generates an interrupt. On command completion, the Command
Block Registers contain the cylinder, head, and sector numbers of the last sector verified.

If an error occurs during a multiple sector verify operation, the read operation terminates
at the sector in which the error occurred. The Command Block Registers contain the
cylinder, head, and sector numbers in which the error occurred.

6.7.5 Format Track 50h

The host specifies the track addresses by writing to the Cylinder and Head Registers.
When the drive accepts a FORMAT TRACK command, it sets the DRQ bit, then waits for
the host to fill the sector buffer. When the buffer is full, the drive clears DRQ, sets BSY,
and begins command execution. The contents of the sector buffer are not written to the
disk, and will be ignored.

On the Quantum Fireball ST series of hard disk drives, the FORMAT TRACK command
writes zeros to the data fields in the sectors on the specified logical track. The drive writes
no headers at these locations. The Sector Count register contains the number of sectors
per track.

6.7.6 Seek 7xh

The SEEK command causes the actuator to seek the track to which the Cylinder and Drive/
Head registers point. When the drive receives this command in its Command Block
Registers, it performs the following functions:

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 6-29

IDE Bus Interface and ATA Commands

1. Sets BSY

2. Initiates the seek operation

3. Resets BSY

4. Sets the Drive Seek Complete (DSC) bit in the Status Register

The drive does not wait for the seek to complete before it sends an interrupt. If the BSY
bit is not set in the Status Register, the drive can accept and queue subsequent commands
while performing the seek. If the Cylinder registers contain an illegal cylinder, the drive
sets the ERR bit in the Status Register and the IDNF bit in the Error Register.

6.7.7 Execute Drive Diagnostic 90h

The EXECUTE DRIVE DIAGNOSTIC command performs the internal diagnostic tests
implemented on the drive. Drive 0 sets BSY within 400 ns of receiving of the command.

If Drive 1 is present:

• Both drives execute diagnostics.

• Drive 0 waits up to six seconds for drive 1 to assert PDIAG–.

• If drive 1 does not assert PDIAG– to indicate a failure, drive 0 appends 80h
with its own diagnostic status.

• If the host detects a drive 1 diagnostic failure when reading drive 0 status,
it sets the DRV bit, then reads the drive 1 status.

If Drive 1 is not present:

• Drive 0 reports only its own diagnostic results.

• Drive 0 clears BSY and generates an interrupt.

If drive 1 fails diagnostics, drive 0 appends 80h with its own diagnostic status and loads
that code into the Error Register. If drive 1 passes its diagnostics or no drive 1 is present,
drive 0 appends 00h with its own diagnostic status and loads that code into the Error
Register.

The diagnostic code written to the Error Register is a unique 8-bit code. Table 6-17 lists
the diagnostic codes.

Table 6-17

DIAGNOSTIC

CODE

01h No Error Detected
02h Formatter Device Error
03h Sector Buffer Error
04h ECC Circuitry Error
05h Controlling Microprocessor Error

8Xh Drive 1 Failed

Diagnostic Codes

DESCRIPTION

6-30 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

6.7.8 Initialize Drive Parameters 91h

The INITIALIZE DRIVE PARAMETERS command enables the host to set the logical
number of heads and the logical number of sectors per track. On receiving the command,
the drive sets the BSY bit, saves the parameters, clears BSY, and generates an interrupt.

The only two register values used by this command are the Sector Count Register, which
specifies the number of sectors; and the Drive/Head Register, which specifies the number
of heads, minus 1. The DRV bit assigns these values to drive 0 or drive 1, as appropriate.

This command does not check the sector count and head values for validity. If these
values are invalid, the drive will not report an error until another command causes an
illegal access.

6.7.9 DOWNLOAD MICROCODE

COMMAND CODE - 92h
TYPE - Optional
PROTOCOL - PIO data out
INPUTS - The head bits of the device/head register will always be set to zero. The cylinder

high and low registers will be set to zero. The sector number and the sector count are used
together as a 16-bit sector count value. The feature register specifies the subcommand
code.

IDE Bus Interface and ATA Commands

Register 76543210

Features Subcommand code

Sector Count Sector count (low order)

Sector Number Sector count (high order)

Cylinder Low 00h

Cylinder High 00h

Device/Head 1 1 D 0000

Command 92h

NORMAL OUTPUTS- None. required.
ERROR OUTPUTS- Aborted command if the device does not support this command or did

not accept the microcode data. Aborted error if subcommand code is not a supported
value.

Status Register Error Register

DRDY DF CORR ERR BBK UNC IDNF ABRT TK0NF AMNF

VV V V

PREREQUISITES - DRDY set equal to one.
DESCRIPTION - This command enables the host to alter the device’s microcode. The data

transferred using the DOWNLOAD MICROCODE command is vendor specific.
All transfers will be an integer multiple of the sector size. The size of the data transfer is

determined by the contents of the Sector Number register and the Sector Count register.
The Sector Number register will be used to extend the Sector Count register, to create a

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 6-31

IDE Bus Interface and ATA Commands

sixteen bit sector count value. The Sector Number register will be the most significant
eight bits and the Sector Count register will be the least significant eight bits. A value of
zero in both the Sector Number register and the Sector Count register will indicate no
data is to transferred. This allows transfer sizes from 0 bytes to 33, 553, 920 bytes in 512
byte increments.

The Features register will be used to determine the effect of the DOWNLOAD MICROCODE
command. The values for the Feature Register are:

01h — download is for immediate, temporary use
07h — save downloaded code for immediate and future use.

Either or both values may be supported. All other values are reserved.

6.7.9.1 SMART B0h

SMART DISABLE OPERATIONS

COMMAND CODE - B0h
TYPE - Optional - SMART Feature set. If the SMART feature set is implemented, this

command shall be implemented.

PROTOCOL - Non-data command
INPUTS - The Features register shall be set to D9h. The Cylinder Low register shall be set

to 4Fh. The Cylinder High register shall be set to C2h.

Register 76543210

Features D9h

Sector Count

Sector Number

Cylinder Low 4Fh

Cylinder High C2h

Device/Head 1 1 D

Command B0h

NORMAL OUTPUTS - None
ERROR OUTPUTS - If the device does not support this command, if SMART is not enabled

or if the values in the Features, Cylinder Low or Cylinder High registers are invalid, an
Aborted command error is posted.

Status Register Error Register

DRDY DF CORR ERR BBK UNC IDNF ABRT TK0NF AMNF

VV V

PREREQUISITES - DRDY set equal to one. SMART enabled.

6-32 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT

IDE Bus Interface and ATA Commands

DESCRIPTION - This command disables all SMART capabilities within the device
including any and all timer functions related exclusively to this feature. After receipt of
this command the device will disable all SMART operations. Attribute values will no
longer be monitored or saved by the device. The state of SMART (either enabled or
disabled) will be preserved by the device across power cycles.

Upon receipt of the SMART DISABLE OPERATIONS command from the host, the device
sets BSY, disables SMART capabilities and functions, clears BSY and asserts INTRQ.

After receipt of this command by the device, all other SMART commands, with the
exception of SMART ENABLE OPERATIONS, are disabled and invalid and shall be aborted
by the device (including SMART DISABLE OPERATIONS commands), returning the
Aborted command error.

6.7.9.2 SMART ENABLE/DISABLE ATTRIBUTE AUTOSAVE

COMMAND CODE - B0h

TYPE - Optional - SMART Feature set. If the SMART feature set is implemented, this
command is optional and not recommended.

PROTOCOL - Non-data command
INPUTS - The Features register shall be set to D2h. The Cylinder Low register shall be set

to 4Fh. The Cylinder High register shall be set to C2h. The Sector Count register is set to
00h to disable attribute autosave and a value of F1h is set to enable attribute autosave.

Register 76543210

Features D2h

Sector Count 00h or F1h

Sector Number

Cylinder Low 4Fh

Cylinder High C2h

Device/Head 1 1 D

Command B0h

NORMAL OUTPUTS - None
ERROR OUTPUTS - If the device does not support this command, if SMART is disabled or

if the values in the Features, Cylinder Low or Cylinder High registers are invalid, an
Aborted command error is posted.

Status register Error register

DRDY DF CORR ERR BBK UNC IDNF ABRT TK0NF AMNF

VV V

PREREQUISITES - DRDY set equal to one. SMART enabled.

Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT 6-33

IDE Bus Interface and ATA Commands

DESCRIPTION - This command enables and disables the optional attribute autosave
feature of the device. Depending upon the implementation, this command may either
allow the device, after some vendor specified event, to automatically save its updated
attribute values to non-volatile memory; or this command may cause the autosave
feature to be disabled. The state of the attribute autosave feature (either enabled or
disabled) will be preserved by the device across power cycles.

A value of zero written by the host into the device’s Sector Count register before issuing
this command will cause this feature to be disabled. Disabling this feature does not
preclude the device from saving attribute values to non-volatile memory during some
other normal operation such as during a power-on or power-off sequence or during an
error recovery sequence.

A value of F1h written by the host into the device’s Sector Count register before issuing
this command will cause this feature to be enabled. Any other meaning of this value or
any other non-zero value written by the host into this register before issuing this
command is vendor specific. The meaning of any non-zero value written to this register
at this time will be preserved by the device across power cycles.

If the SMART ENABLE/DISABLE ATTRIBUTE AUTOSAVE command is supported by the
device, upon receipt of the command from the host, the device sets BSY, enables or
disables the autosave feature (depending on the implementation), clears BSY and asserts
INTRQ.

If this command is not supported by the device, the device shall abort the command upon
receipt from the host, returning the Aborted command error.

During execution of the autosave routine the device shall not assert BSY nor deassert
DRDY. If the device receives a command from the host while executing its autosave
routine it must respond to the host within two seconds.

6.7.9.3 SMART ENABLE OPERATIONS

COMMAND CODE - B0h

TYPE - Optional - SMART Feature set. If the SMART feature set is implemented, this
command shall be implemented.

PROTOCOL - Non-data command
INPUTS - The Features register shall be set to D8h. The Cylinder Low register shall be set

to 4Fh. The Cylinder High register shall be set to C2h.

Register 76543210

Features D8h

Sector Count

Sector Number

Cylinder Low 4Fh

Cylinder High C2h

Device/Head 1 1 D

Command B0h

NORMAL OUTPUTS - None

6-34 Quantum Fireball ST 1.6/2.1/3.2/4.3/6.4AT