Quanta Computer LA-2051 DFL10 Sapporo XA, Satellite A30, Satellite P10, Satellite P15 Schematic
A
B
COMPAL CONFIDENTIAL
C
D
E
1 1
MODEL NAME :
COMPAL P/N :
PCB NO :
LA-2051
Revision :
2 2
Sapporo XA
DFL10
1.0
Sappo ro XA Schematics Document
uFCBGA/ uF CP GA NorthWood MT
2003 11 07 v1.0
3 3
4 4
THIS SHEE T OF E N GINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTH ORIZED B Y COMPAL E LECTRON ICS, INC . NEITH ER THIS S HEET NOR THE INFO RMATION IT CONT AINS
A
B
MAY BE US ED B Y O R DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONI CS, INC.
C
D
Title
Size Docume nt Nu mb e r Re v
Date: Sheet
Compal Electronics, Inc.
LA-2051
Cover Sheet
E
1.0
of
151Friday, November 14, 2003
A
B
C
D
E
Compal confidential
Block Diagram
Model : DFL10 LA-2051
1 1
2 2
Fan Control 1
+12VALW
+5VALW
+12VALW
+5VALW
page 37
Fan Control 2
page 37
TV OUT Connector
+3VS
CRT Connector
+5VS
+3VS
LVDS Connector
B+
page 17
page 18
page 18
CPU B ypass
page 6
CRT Signal
LVDS Signal
USB2.0 CTRL.
NEC uPD720101
page 24
IEEE 1394
TSB43AB21
+3V
+3VS
1394 Conn.
PCI BUS
IDSEL:AD16
PIRQA#
page 19
page 19
+3VS 33MHz
IDSEL:AD20
PIRQB#
CardBus
CB1410
+3V
+3VS
page 20
PWR Controller & Slot
+12VALW +5VALW
+3VALW
page 21
LAN
RTL8101L
+3V
+2.5VLAN
RJ45
IDSEL:AD19
PIRQD#
page 22
page 23
IDSEL:AD18
PIRQC#
Minipci CONN
WIRELESS & Dubug
+3V
+3VS
+5VS
3 3
page 25
Super I/O
On/Off BTN &
User Keys
+3VALW
page 37
Powe r Circuit
DC/DC
page 40
4 4
A
SW Board Conn
+5VALW
page 37
RTC Batt.
page 37
DC/D C Interface
Suspend
page 36
B
LPC47N217
+3VS
Parallel
+5VS
page 34
Debug COM Port
+5V
page 34
FIR
+3VS
page 34
NorthWood-MT -- 533
Prescott-MT -- 533
Celeron-MT -- 400
+1.2VP
uFCPGA CPU
+CPU_CORE
ATI RC 300ML
+1.5VS
+2.5V
718 pin u-BGA
+3VS
+CPU_CORE
A LINK
+1.5VS
66MHz
+3VS
+3VALW
+1.5VS
+1.5VALW
+CPU_CORE
VCC5REF
VCC5REFSUS
LPC BUS
page 34
AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSF ERED FR OM TH E CUSTO DY OF THE COMPET ENT DIVISION OF R&D
Therm al S ensor
478pin
page 4,5,6
System Bus
400/533 MHz
page 7,8,9,10,11,12
HD#(0..63)HA#(3..31)
ATI IXP150
457 BGA
page 26,27,28,29
+3VS
33MHz
Embedded Controller
NS PC87591L
+3VS
+3VALW
THIS SHEET OF ENGINEERIN G DRAWI NG IS T HE PROPR IETARY PR OPERTY O F CO MPAL ELECT RONI CS, INC. AND CONTAINS C ONFIDENTIAL
C
DEPARTMENT EXCEPT AS AUTHORIZ ED BY CO MPAL ELECTR ONIC S, INC. N EITHER T HIS SHEET NOR THE INFORMATI ON IT CONTAINS
MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WIT HOUT PRIO R WRITT EN CO NSENT O F COMPAL ELECTRONICS , INC.
page 31
EC DEBUG & Int. KB
+3VALW
page 31
BIOS & Ext. IO
+3VALW
+5VALW
page 32
LID SW & Kill SW
+3VALW
page 31
Touch Pad
+5VS
page 31
LID Hib e rnation
+5VALW
+RTC_VREF
page 39
ADM1032AR
+5VS +3VS
Memory
BUS(DDR)
48MHz
24.576MHz
IDE HDD
+5VS
page 6
+2.5V 333MHz
USB 2.0/1.1
AC-LINK
ATA100
page 30
D
IDE ODD
+5VCD
page 30
PIDE IRQ15SIDE IRQ14
Clock Generator
ICS951402AGT
+5VALW
INT. Speaker
page 33
page 16
DDR-DIMM X2
BANK 0, 1, 2, 3
+2.5V
+1.25VS
page 13,14,15
USB Ports X3
( X1 reserve )
+5V
page 27
MDC
+5VS
+3VS
+3V
page 23
AC97 Codec
ALC202A
+5VALW -> +VDDA
+3VS
page32
AMP TPA0232
page 33
HeadPhone
+AUD_VREF
page 33
Title
Size Document Number Re v
Date: Sheet of
Compal Electronics, Inc.
Block Diagram
LA-2051
RJ11
Cable
MIC Phone
+5VDDA
LINE IN
+5VDDA
E
Cable
page 33
251Friday, November 14, 2003
1.0
5
Voltage Rails
Power Plane
VIN
D D
C C
B+
+CPU_C O R E Core voltage for CPU
+1.2V
+1.25VS
+1.5VS
+1.8VS
+2.5VALW
+2.5V
+2.5VS
+3VALW
+3V 3.3V system power rail for SB,LAN,CardReader and HUB.
+3VS OFF
+5V 5V system power rail .
+5VS
+12VALW
RTCVCC ON
Description
Adapter po w e r s up p ly (19V)
AC or ba tte ry p ow e r r ai l for power circuit.
The vol ta ge fo r Pr oc e ssor VID select
1.25V s w i tc he d po w er rail for DDR Vtt
1.5V I/O power rail for ATI-RS300M/RC300M NB AGP.
1.8V sw i tc h ed p ow e r r ai l f or A TI-RS300M/RC300M NB.
2.5V always on power rail
2.5V system power rail for DDR
2.5V switched power rail
3.3V always on power rail
3.3V switched power rail
5V switched power rail OFF
12V always on power rail
RTC power
4
S5
S3
S0-S1
N/AONN/A
N/A
N/A
N/A
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON ON OFF
ON
ON
ON
N/A
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ONON
ON*
ON
OFF
OFF
OFF
ON*
ON
OFF
ON
OFF
ON
ON*+5VALW 5V always on power rail
OFF
ON
ON*
ON
3
Power Managment table
State
S0
S1
S3
S5 S4/AC
S5 S4/AC don't exist
Signal
2
+3VALW
+5VALW
+12VALW
ON
ON ON ON
ON ON
ON OFF
OFF OFF OFF
+5V
+3V
+2.5V
+2.5VS
+1.8VS
+5VS
+3VS
+1.5VS
+CPU_CORE
+1.25VS
ON ON
1
OFF
OFF
Note : ON * m e a ns th a t th i s po w e r p l an e i s O N o nl y w i th A C p o w er av a i l ab l e, o therwise it is OFF.
External PCI Devices
IDSEL # PIRQREQ/GNT #DEVICE
NB Internal VGA
AGP BUS
SOUTHBRIDGE
USB
B B
AC97
ATA 100
ETHERNET
1394
LAN
CARD BUS
Wire les s LAN(MINI PCI)
EXT USB AD23(EXT.) 4 A,C,D
N/A
AGP_DEVSEL
AD31 (INT.)
AD30 (INT.)
AD31 (INT.)
AD31 (INT.)
AD24(INT.)
AD16
AD19
AD20
AD18
EC SM Bus1 address
Device Address Address
Smart Battery
A A
EEPROM(24C16)
I2C / SMB US ADDRESSING
1010 000X b
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
1
2
3
EC SM Bus2 address
DEVICE HEX ADDRESS
DDR SO- DIMM 0
DDR SO- DIMM 1
CLOCK GENERATOR (EXT.)A2D2
5
1 0 1 0 0 0 0 XA0
1 0 1 0 0 0 1 X
1 1 0 1 0 0 1 X
Device
ADM1032
4
N/A
A
A
D
B
A
C
A
D
A
C
1001 100X b0001 011X b
BOARD ID
Version
0
1
2
3
THIS SHEE T OF E N GINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTH ORIZED B Y COMPAL E LECTRON ICS, INC . NEITH ER THIS S HEET NOR THE INFO RMATION IT CONT AINS
MAY BE US ED B Y O R DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONI CS, INC.
3
SKU ID Table for AD channel
Vcc 3.3V +/- 5%
SKU ID
BID0BID1
0
0
1
11
100K +/- 5%Ra
0
1
8.2K +/- 5%
2
18K +/- 5%
3
33K +/- 5%
56K +/- 5%
4
100K +/- 5%
5
200K +/- 5%
6
7 NC
0
1
0
Rb V min
0
AD_BID
0 V
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
1.036 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
Sku ID
0
1
2
3
4
5
6
7
2
Vtyp
AD_BID
0 V 0 V
0.503 V
0.819 V
1.185 V 1.264 V
2.200 V
3.300 V
CD PLAY F UNCTION
YES YES
NO YES
NO NO
Compal Electronics, Inc.
Title
Note & Revision
Size Docume nt Nu mb e r Re v
LA-2051
Date: Sheet
V
max
AD_BID
0.538 V
0.875 V
2.341 V
3.300 V
Short cut key
NOYES
351Tuesday, November 18, 2003
1
1.0
of
5
D D
A10
A12
A14
HA#[3..31]7 HD#[0..63] 7
C C
H_REQ#[0..4]7
+CPU_CORE
B B
H_REQ#[0..4]
H_ADS#7
+CPU_CORE
R4 56 _0402_5%
1 2
H_BREQ0#7
H_BPRI#7
H_BNR#7
H_LOCK#7
CLK_CPU_BCLK16
CLK_CPU_BCLK#16
H_HIT#7
H_HITM#7
H_DEFER#7
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADS#
R36 51_0402_5%
1 2
CLK_CPU_BCLK
CLK_CPU_BCLK#
FOX_PZ47803-274A-42_Prescott
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
AF22
AF23
M6
M3
M4
N1
M1
N2
N4
N5
R2
P3
P4
R3
U1
P6
U3
V2
R6
W1
U4
V3
W2
Y1
AB1
K5
H3
G1
AC1
V5
AA3
AC3
H6
D2
G2
G4
E3
E2
K2
K4
L6
K1
L3
L2
T1
T2
T4
T5
J1
J4
J3
F3
JCPU1A
A#3
A#4
A#5
A#6
A#7
A#8
A#9
A#10
A#11
A#12
A#13
A#14
A#15
A#16
A#17
A#18
A#19
A#20
A#21
A#22
A#23
A#24
A#25
A#26
A#27
A#28
A#29
A#30
A#31
A#32
A#33
A#34
A#35
REQ#0
REQ#1
REQ#2
REQ#3
REQ#4
ADS#
AP#0
AP#1
BINIT#
IERR#
BR0#
BPRI#
BNR#
LOCK#
BCLK0
BCLK1
HIT#
HITM#
DEFER#
CON
TROL
VCC_0
VCC_1
VCC_2
HOST
ADDR
CONTROL
CLK
VSS_0H1VSS_1H4VSS_2
4
AA16
AA18
AA8
AB11
AB13
AB15
AB17
AB19
AB7
AB9
AC10
AC12
AC14
AC16
AC18
AC8
AD11
AD13
AD15
AD17
AD19
AD7
AD9
AE10
A16
A18
A20
AA10
AA12
AA14
VCC_3
VCC_4
VCC_5
VCC_6A8VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
AE12
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
Northwood-MT
Prescott-MT
GND
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12A3VSS_13A9VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
A11
A13
A15
A17
A19
A21
A24
H23
A26
H26
AA1
AA4
AA7
AA13
AA15
AA17
AA19
AA23
AA26
AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB21
AB24
AA11
AE14
AE16
AE18
VCC_35
VCC_36
VCC_37
POWER
VSS_33
VSS_34
VSS_35
AB3
AB6
AB8
AE20
VCC_38
VSS_36
AC11
AE6
VCC_39
VSS_37
AC13
AE8
AF11
VCC_40
VSS_38
AC15
AC17
AF13
VCC_41
VCC_42
VSS_39
VSS_40
AC19
3
AF15
VCC_43
VSS_41
AC2
AF17
VCC_44
VSS_42
AC22
AF19
VCC_45
VSS_43
AC25
AF2
VCC_46
VSS_44
AC5
AF21
VCC_47
VSS_45
AC7
AF5
VCC_48
VSS_46
AC9
AF7
VCC_49
VSS_47
AD10
AF9
VCC_50
VSS_48
AD12
B11
VCC_51
VSS_49
AD14
B13
VCC_52
VSS_50
AD16
B15
VCC_53
VSS_51
AD18
B17
VCC_54
VSS_52
AD21
B19
VCC_55
VSS_53
AD23
VCC_56B7VCC_57B9VCC_58
VSS_54
AD4
VSS_55
AD8
C10
C12
C14
VCC_59
BOOTSELECT
AD1
C16
C18
C20
VCC_61
VCC_62
VCC_63
POWER
VCC_81
VCC_82
F13
F15
F17
2
+CPU_CORE
D11
D13
D15
D17
D19
D9
E10
VCC_64
VCC_65C8VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71D7VCC_72
VCC_73
B21
D#0
B22
D#1
A23
D#2
A25
D#3
C21
D#4
D22
D#5
B24
D#6
C23
D#7
C24
D#8
B25
D#9
G22
D#10
H21
D#11
C26
D#12
D23
D#13
J21
D#14
D25
D#15
H22
D#16
E24
D#17
G23
D#18
F23
D#19
F24
D#20
E25
D#21
F26
D#22
D26
D#23
L21
D#24
G26
D#25
H24
D#26
M21
D#27
L22
D#28
J24
D#29
K23
D#30
HOST
ADDR
VCC_75
VCC_76
VCC_77
VCC_78
VCC_79E8VCC_80
VCC_83
VCC_84
VCC_85
F9
F11
F19
E14
E16
E18
E20
VCC_74
E12
+CPU_CORE
D#31
D#32
D#33
D#34
D#35
D#36
D#37
D#38
D#39
D#40
D#41
D#42
D#43
D#44
D#45
D#46
D#47
D#48
D#49
D#50
D#51
D#52
D#53
D#54
D#55
D#56
D#57
D#58
D#59
D#60
D#61
D#62
D#63
H25
M23
N22
P21
M24
N23
M26
N26
N25
R21
P24
R25
R24
T26
T25
T22
T23
U26
U24
U23
V25
U21
V22
V24
W26
Y26
W25
Y23
Y24
Y21
AA25
AA22
AA24
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
HD#[0..63]HA#[3..31]
1
BOOTSELECT
3
0_0402_5%
12
R8
Compal Electronics, Inc.
Title
Prescott / P4 uFCPGA (1/2)
Size Docume nt Nu mb e r Re v
LA-2051
Custom
2
Date: Sheet
451Friday, November 14, 2003
1
1.0
of
A A
THIS SHEE T OF E N GINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
5
4
DEPARTMENT EXCE PT AS AUTH ORIZED B Y COMPAL E LECTRON ICS, INC . NEITH ER THIS S HEET NOR THE INFO RMATION IT CONT AINS
5
+CPU_CORE
1 2
R56 51_0402_5%
D D
1 2
R59 51_0402_5%
1 2
R47 51_0402_5%
1 2
R46 51_0402_5%
1 2
R55 51_0402_5%
1 2
R57 51_0402_5%
+CPU_CORE
R2 150_0402_5%
R51 39.2_0603_1%
1 2
C C
R586 75_0402_5%
R43 680_0402_5%
R52 27.4_0603_1%
+CPU_CORE
1 2
LQG21F4R7N00_0805
1 2
LQG21F4R7N00_0805
B B
Comp0/1 need keep 25
mils trace width
+CPU_CORE
R560 56_0402_5%
R1 56_0402_5%
R66 56_0402_5%
A A
H_RS#[0..2]7
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TDI
12
ITP_TMS
12
ITP_TDO
ITP_TRST#
12
ITP_TCK
12
L27
1
L26
+
C423
@33U_D2_8M_R35
2
CLK_CPU_ITP16
CLK_CPU_ITP#16
Place near SB200
H_FERR#
1 2
Place near CPU
H_THERMTRIP#
1 2
H_RESET#
1 2
H_PWRGD
1 2
R64 300_0402_5%
PM_STPCPU#10,16, 26,47
5
H_TRDY#7
H_A20M#26
H_FERR#26
H_IGNNE#26
H_SMI#26
H_PWRGD26
H_STPCLK#26
H_INTR26
H_NMI26
H_INIT#26
H_RESET#7,26
H_DBSY#7
H_DRDY#7
BSEL012,16
BSEL112,16
H_THERMDA6
H_THERMDC6
H_THERMTRIP#6
1
+
C422
33U_D2_ 8M_R35
2
H_RS#[0..2]
VCCIOPLL
VCCA
VCCSENSE47
VSSSENSE47
1 2
+1.2V
R587 0_0402_5%
VSSA
1 2
R96 51.1 _0603_1%
1 2
R11 51.1 _0603_1%
If CP U is P 4 , Change the
resist o r R 53 9,R540 value to
51.1_0603_1%,or prescott
61.9_ 0603_1%
R7
1 2
4.7K_0402_5%
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
H_A20M#
H_FERR#
H_IG NNE#
H_SMI#
H_PWRGD
H_STPCLK#
H_INTR
H_NMI
H_INIT#
H_RESET#
H_DBSY#
H_DRDY#
BSEL0
BSEL1
H_THERMDA
H_THERMDC
H_THERMTRIP#
ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
VCCSENSE
VSSSENSE
COMP0
COMP1
+3VS
12
Q2
2
MMBT3904_SOT23
3 1
AB2
AB23
AB25
AD6
AD5
AC6
AB5
AC4
AA5
AB4
AD20
AE23
AF3
AD22
AC26
AD26
L24
R9
4.7K_0402_5%
2
JCPU1B
F1
RS#0
G5
RS#1
F4
RS#2
RSP#
J6
TRDY#
C6
A20M#
B6
FERR#
B2
IGNNE#
B5
SMI#
PWRGOOD
Y4
STPCLK#
D1
LINT0
E5
LINT1
W5
INIT#
RESET#
H5
DBSY#
H2
DRDY#
BSEL0
BSEL1
B3
THERMDA
C4
THERMDC
A2
THERMTRIP#
BPM#0
BPM#1
BPM#2
Y6
BPM#3
BPM#4
BPM#5
D4
TCK
C1
TDI
D5
TDO
F7
TMS
E6
TRST#
VCCIOPLL
VCCA
A5
VCCSENSE
A4
VSSSENSE
VCCVIDLB
VSSA
ITP_CLK0
ITP_CLK1
COMP0
P1
COMP1
Q1
MMBT3904_SOT23
3 1
4
GND
AE11
AE13
VSS_57
CON
TROL
LEGACY
ITP
CLK
VSS_129F8VSS_130
G21
H_DPSLPR#
4
VSS_58
AE15
AE17
AE19
AE22
AE24
AE7
AE9
AF1
AF10
AF12
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_65
VSS_66
VSS_67
VSS_68
MISC
THER
MAL
MISC
ITP
MISC
VSS_131
VSS_132G3VSS_133G6VSS_134J2VSS_135
VSS_136
VSS_137J5VSS_138
VSS_139
J22
J25
K21
K24
G24
FOX_PZ47803-274A-42_Prescott
AF14
AF16
AF18
AF20
AF6
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_140K3VSS_141K6VSS_142L1VSS_143
VSS_144
L23
L26
3
D14
D16
D18
D20
D21
D24
E11
E13
E15
E17
E19
E23
E26
VSS_112
VSS_113
VSS_114
VSS_115
F10
VSS_116
VSS_117E4VSS_118E7VSS_119E9VSS_120
AF8
VSS_75
VSS_76
B10
VSS_77
B12
VSS_78
B14
VSS_79
B16
VSS_80
B18
VSS_81
B20
B23
VSS_82
VSS_83
B26
VSS_84
C11
C13
VSS_85B4VSS_86B8VSS_87
VSS_88
C15
C17
VSS_89
C19
VSS_90
VSS_91
C22
C25
VSS_92C2VSS_93
VSS_94
D10
D12
VSS_95C5VSS_96C7VSS_97C9VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106D3VSS_107D6VSS_108D8VSS_109E1VSS_110
VSS_111
GROUND
Northwood-MT
Prescott-MT
GROUND MISC
VID0
VID1
VID2
VID3
VSS_145L4VSS_146M2VSS_147
VSS_148
VSS_149M5VSS_150
VSS_151
VSS_152N3VSS_153N6VSS_154P2VSS_155
VSS_156
VSS_157P5VSS_158R1VSS_159
VSS_160
VSS_161R4VSS_162
VSS_163
VSS_164T3VSS_165T6VSS_166U2VSS_167
VSS_168
VSS_169U5VSS_170V1VSS_171
VSS_172
VSS_173V4VSS_174
VSS_175
VSS_176W3VSS_177W6VSS_178Y2VSS_179
VSS_180
T21
T24
P22
P25
N21
N24
R23
M22
M25
R26
Reserve
for EMI.
Near CPU.
THIS SHEE T OF E N GINEERING DRAWING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAI NS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETEN T DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTH ORIZED B Y COMPAL E LECTRON ICS, INC . NEITH ER THIS S HEET NOR THE INFO RMATION IT CONT AINS
3
V23
V26
U22
U25
+3VS
1 8
2 7
3 6
4 5
R6 10 K_0402_5%
1 2
R5 10 K_0402_5%
1 2
CPU_VID[0..5]47
Y22
Y25
W21
W24
10K_1206_8P4R_5%
RP1
Y5
VSS_181
VID4
AE5
AE4
AE3
AE2
AE1
AD3
CPU_VID5
CPU_VID2
CPU_VID0
CPU_VID1
CPU_VID3
CPU_VID4
F12
VID5
F14
F16
VSS_121
VSS_122
AD2
VSS_123
VIDPWRGD
2
AF26
F18
F22
F25
F5
VSS_124
VSS_125F2VSS_126
VSS_127
VSS_128
SKTOCC#
REF
OPTIMIZED/COMPAT#
ITP
DATA
ADDR
DATA
MISC
VCCVID
AF4
Pop: Prescott
Depop: Northwood
R12
@2.43K_0603_1%
2
1
H_SKTOCC#
12
R403
@33_0402_5%
J26
DP#0
K25
DP#1
K26
DP#2
L25
DP#3
AA21
GTLREF0
AA6
GTLREF1
F20
GTLREF2
F6
GTLREF3
AE26
AD24
TESTHI0
AA2
TESTHI1
AC21
TESTHI2
AC20
TESTHI3
AC24
TESTHI4
AC23
TESTHI5
AA20
TESTHI6
AB22
TESTHI7
U6
TESTHI8
W4
TESTHI9
Y3
TESTHI10
A6
TESTHI11
AD25
TESTHI12
E22
DSTBN#0
K22
DSTBN#1
R22
DSTBN#2
W22
DSTBN#3
F21
DSTBP#0
J23
DSTBP#1
P23
DSTBP#2
W23
DSTBP#3
L5
ADSTB#0
R5
ADSTB#1
E21
DBI#0
G25
DBI#1
P26
DBI#2
V21
DBI#3
AE25
DBR#
C3
PROCHOT#
V6
MCERR#
AB26
SLP#
A22
NC1
A7
NC2
AF25
NC3
AF24
NC4
AE21
NC5
+1.2V
12
+1.2V
H_VID_PWRGD 38
Title
Size Docume nt Nu mb e r Re v
Custom
Date: Sheet
H_GHI#
1 2
R42
0_0402_5%
+H_GTLREF
C47
1 2
220P_0603_50V8J
R_G
R404 0_ 0402_5%
1 2
1 2
R408 56_0402_5%
1 2
R409 56_0402_5%
R58 56_0402_5%
1 2
R60 56_0402_5%
1 2
R38 56_0402_5%
1 2
R45 56_0402_5%
1 2
R39 56_0402_5%
1 2
H_GHI#
H_DPSLPR#
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_ADSTB#0
H_ADSTB#1
H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3
H_PROCHOT#
H_SLP#
1
C1
0.1U_0402_10V6K
2
R35 300_0402_5%
1 2
R405 56_0402_5%
1 2
H_DSTBN#[0..3]
H_DSTBP#[0..3]
H_DBI#[0..3]
R410 150_0402_5%
1 2
R10 100K_0402_1%
GTL Refe re n c e V o l tage
Layout note :
1. Place R_A and R _B near C PU (Wi thi n 1.5" ).
+CPU_CORE
12
12
R74
49.9_0603_1%
12
R67
100_0603_1%
H_DSTBN#[0..3] 7
H_DSTBP# [0..3] 7
H_ADSTB#0 7
H_ADSTB#1 7
H_DBI#[0..3] 7
+3VALW
+CPU_CORE
H_PROCHOT# 26,46
H_SLP# 26
Compal Electronics, Inc.
Prescott / P4 uFCPGA & Thermal sensor (2/2)
LA-2051
551Friday, November 14, 2003
1
CPU_GHI# 27
+CPU_CORE
+H_GTLREF
1
C50
1U_0603_6.3V6M
2
of
1.0
A
1 1
+CPU_CORE
1
2 2
2
+CPU_CORE
1
2
C396
22U_1206_6.3V6M
C384
22U_1206_6.3V6M
B
Layout note :
Place close to CPU, Use 2~3 vias per PAD.
Place 22uF caps x31 pcs, populated 14pcs.
Place on CPU inside
1
2
1
C380
22U_1206_6.3V6M
2
C388
22U_1206_6.3V6M
1
C383
22U_1206_6.3V6M
2
1
C398
22U_1206_6.3V6M
2
C
1
2
1
2
C379
22U_1206_6.3V6M
C390
22U_1206_6.3V6M
1
C397
22U_1206_6.3V6M
2
1
C385
22U_1206_6.3V6M
2
D
1
C389
22U_1206_6.3V6M
2
1
C381
22U_1206_6.3V6M
2
E
Layout note :
Place close to CPU power and
ground pin as possible
(<1inch)
For Desktop's CPU:
470uFx15/12mOhm H=1.8 each
Total 0.923m ohm
F
+CPU_CORE
1
+
2
+CPU_CORE
1
+
2
+CPU_CORE
1
+
2
G
C382
@470U_D2_2.5VM
C407
470U_D4_2.5VM
C40
470U_D4_2.5VM
1
+
2
1
+
2
1
+
2
C392
470U_D4_2.5VM
C419
470U_D4_2.5VM
C48
470U_D4_2.5VM
H
1
+
2
1
+
2
1
+
2
C401
470U_D4_2.5VM
C30
470U_D4_2.5VM
C58
470U_D4_2.5VM
1
+
2
1
+
C404
470U_D4_2.5VM
2
1
+
C33
470U_D4_2.5VM
2
C65
470U_D4_2.5VM
I
+
1
C36
470U_D4_2.5VM
2
J
3 3
+CPU_ CORE
1
+CPU_ CORE
1
2
+CPU_CORE
+CPU_CORE
2
C412
22U_1206_6.3V6M
1
C21
22U_1206_6.3V6M
2
1
C74
22U_1206_6.3V6M
2
4 4
5 5
6 6
7 7
H_THERMDA5
8 8
H_THERMDC5
A
Please place these cap on the socket north side
C409
22U_1206_6.3V6M
1
C413
22U_1206_6.3V6M
2
1
C408
22U_1206_6.3V6M
2
1
C414
22U_1206_6.3V6M
2
1
C418
22U_1206_6.3V6M
2
1
C415
22U_1206_6.3V6M
2
Please place these cap on the socket sourth side
1
C22
22U_1206_6.3V6M
2
1
C75
22U_1206_6.3V6M
2
1
C23
22U_1206_6.3V6M
2
1
C20
22U_1206_6.3V6M
2
CPU Temperature Sensor
H_THERMDA
1
C39
2200P_0402_50V7K
H_THERMDC
EC_SMC235
EC_SMD235
B
2
1
2
+3VS
C
1
C410
22U_1206_6.3V6M
2
C19
22U_1206_6.3V6M
R63
1 2
200_0402_5%
U4
2
D+
3
D-
8
SCLK
7
SDATA
ADM1032ARM_RM8
1
C416
22U_1206_6.3V6M
2
1
C72
22U_1206_6.3V6M
2
+3VS_VDD
1
C42
0.1U_0402_10V6K
2
VDD1
ALERT#
THERM#
GND
1
C411
22U_1206_6.3V6M
2
1
6
4
5
D
1
C417
22U_1206_6.3V6M
2
1
C73
22U_1206_6.3V6M
2
12
R54
10K_0402_5%
+CPU_CORE
1
C82
@0.22U_0603_10V7K
2
THIS SHEET OF ENGINEERIN G DRAWI NG IS T HE PROPR IETARY PR OPERTY O F CO MPAL ELECT RONI CS, INC. AND CONTAINS C ONFIDENTIAL
AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSF ERED FR OM TH E CUSTO DY OF THE COMPET ENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY CO MPAL ELECTR ONIC S, INC. N EITHER T HIS SHEET NOR THE INFORMATI ON IT CONTAINS
E
F
1
C81
@0.22U_0603_10V7K
2
+CPU_CORE
H_THERM TRIP#5 MAINPWON 41 ,42,44
G
1
C80
@0.22U_0603_10V7K
2
R3 300_0402_5%
12
H_THERM TRIP#
I
1
C16
@0.22U_0603_10V7K
2
1
C18
@0.22U_0603_10V7K
2
C2 @1U_0603_10V6K
2SC2411K_SC59
Q3
CBE
123
H
1
C17
@0.22U_0603_10V7K
2
12
Compal Electronics, Inc.
Title
CPU Decoupling CAP.
Size Document Number Re v
LA-2051
Custom
Date: Sheet of
651Friday, November 14, 2003
1.0
J
5
4
3
2
1
HA#[3..31]
H_REQ#[0..4]
HD#[0..63]
12
R469
4.7K_0402_5%
U24A
M28
CPU_A3#
P25
CPU_A4#
M25
CPU_A5#
N29
CPU_A6#
N30
CPU_A7#
M26
CPU_A8#
N28
CPU_A9#
P29
CPU_A10#
P26
CPU_A11#
R29
CPU_A12#
P30
CPU_A13#
P28
CPU_A14#
N26
CPU_A15#
N27
CPU_A16#
M29
CPU_REQ0#
N25
CPU_REQ1#
R26
CPU_REQ2#
L28
CPU_REQ3#
L29
CPU_REQ4#
R27
CPU_ADSTB0#
U30
CPU_A17#
T30
CPU_A18#
R28
CPU_A19#
R25
CPU_A20#
U25
CPU_A21#
T28
CPU_A22#
V29
CPU_A23#
T26
CPU_A24#
U29
CPU_A25#
U26
CPU_A26#
V26
CPU_A27#
T25
CPU_A28#
V25
CPU_A29#
U27
CPU_A30#
U28
CPU_A31#
T29
CPU_ADSTB1#
L27
CPU_ADS#
K25
CPU_BNR#
H26
CPU_BPRI#
J27
CPU_DEFER#
L26
CPU_DRDY#
G27
CPU_DBSY#
F25
CPU_BR0#
K26
CPU_LOCK#
A17
CPU_CPURSET#
G25
CPU_RS2#
G26
CPU_RS1#
J25
CPU_RS0#
F26
CPU_TRDY#
J26
CPU_HIT#
H25
CPU_HITM#
A9
CPU_RSET
AH5
SUS_STAT#
AG5
SYSRESET#
C7
POWERGOOD
V28
CPU_COMP_N
W29
CPU_COMP_P
H23
CPVDD
J23
CPVSS
W28
CPU_VREF
Y29
THERMALDIODE_N
Y28
THERMALDIODE_P
B17
TESTMODE
CHS-216IGP9050A21_BGA718
H_ADS#4
H_RS#25
H_RS#15
H_RS#05
H_HIT#4
1U_0603_10V6K
1 2
C492
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
H_ADSTB#1
H_ADS#
H_BNR#
H_BPRI#
H_DEFER#
H_DRDY#
H_DBSY#
H_BREQ0#
H_LOCK#
H_RESET#
H_RS#2
H_RS#1
H_RS#0
H_TRDY#
H_HIT#
H_HITM#
COMP_N
COMP_P
CPVDD
CPVSS
NB_GTLREF
D D
H_ADSTB#05
C C
H_ADSTB#15
H_BNR#4
H_BPRI#4
H_DEFER#4
H_DRDY#5
H_DBSY#5
H_BREQ0#4
H_LOCK#4
0.1U_0402_10V6K
--> 412_0402_1%
Note: PLACE CLOSE TO RC300M,
L
USE 10/10 WIDTH/SPACE
+CPU_CORE
PLACE CLOSE TO U27 Ball
W28, USE 20/20
B B
49.9_0603_1%
100_0603_1%
WIDTH/SPACE
R428
1 2
12
1
1
C433
R429
2
1U_0603_10V6K
C441
220P_0402_50V8K
2
C441 CLOSE
TO Ball W28
330_0402_5%
+CPU_CORE
+1.8VS
1 2
H_RESET#5,26
C590
12
H_TRDY#5
R485
H_HITM#4
SUS_STAT#27
NB_RST#26,30, 34,35
NB_PWRGD17
R437 24.9_0402_1%
1 2
R436 49.9_0402_1%
1 2
L31
1 2
HB-1M2012-121JT03_0805
HA#[3..31] 4
H_REQ#[0..4] 4
HD#[0..63] 4
HD#0
L30
CPU_D0#
CPU_D1#
CPU_D2#
CPU_D3#
CPU_D4#
CPU_D5#
CPU_D6#
CPU_D7#
CPU_D8#
PART 1 OF 6
CPU_D9#
CPU_D10#
CPU_D11#
DATA GROUP 0DATA GROUP 1DATA GROUP 2DATA GROUP 3
CPU_D12#
CPU_D13#
CPU_D14#
CPU_D15#
CPU_DBI0#
CPU_DSTBN0#
CPU_DSTBP0#
CPU_D16#
CPU_D17#
CPU_D18#
CPU_D19#
CPU_D20#
CPU_D21#
CPU_D22#
CPU_D23#
CPU_D24#
CPU_D25#
CPU_D26#
CPU_D27#
CPU_D28#
CPU_D29#
CPU_D30#
CPU_D31#
CPU_DBI1#
ADDR. GROUP 1 A DDR. GROUP 0CONTROL
CPU_DSTBN1#
CPU_DSTBP1#
AGTL+ I/F
CPU_D32#
CPU_D33#
CPU_D34#
CPU_D35#
CPU_D36#
CPU_D37#
CPU_D38#
CPU_D39#
CPU_D40#
CPU_D41#
PENTIUM
IV
CPU_D42#
CPU_D43#
CPU_D44#
CPU_D45#
CPU_D46#
CPU_D47#
CPU_DBI2#
CPU_DSTBN2#
CPU_DSTBP2#
CPU_D48#
CPU_D49#
CPU_D50#
CPU_D51#
CPU_D52#
CPU_D53#
CPU_D54#
CPU_D55#
CPU_D56#
CPU_D57#
CPU_D58#
CPU_D59#
CPU_D60#
MISC.
CPU_D61#
CPU_D62#
CPU_D63#
CPU_DBI3#
CPU_DSTBN3#
CPU_DSTBP3#
HD#1
K29
HD#2
J29
HD#3
H28
HD#4
K28
HD#5
K30
HD#6
H29
HD#7
J28
HD#8
F28
HD#9
H30
HD#10
E30
HD#11
D29
HD#12
G28
HD#13
E29
HD#14
D30
HD#15
F29
H_DBI#0
E28
H_DSTBN#0
G30
H_DSTBP#0
G29
B26
C30
A27
B29
C28
C29
B28
D28
D26
B27
C26
E25
E26
A26
B25
C25
H_DBI#1
A28
H_DSTBN#1
D27
H_DSTBP#1
E27
F24
D24
E23
E24
F23
C24
B24
A24
F21
A23
B23
C22
B22
C21
E21
D22
H_DBI#2
D23
H_DSTBN#2
E22
H_DSTBP#2
F22
B21
F20
A21
C20
E20
D20
A20
D19
C18
B20
E18
B19
D18
B18
C17
A18
H_DBI#3
F19
H_DSTBN#3
E19
H_DSTBP#3
F18
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
H_DBI#0 5
H_DSTBN#0 5
H_DSTBP#0 5
H_DBI#1 5
H_DSTBN#1 5
H_DSTBP#1 5
H_DBI#2 5
H_DSTBN#2 5
H_DSTBP#2 5
H_DBI#3 5
H_DSTBN#3 5
H_DSTBP#3 5
+CPU_CORE
0.1U_0402_10V6K
1
1
C486
C541
A A
5
4
22U_1 206_16V4Z_V1
C525
2
2
0.1U_0402_10V6K
THIS SHEET OF ENGINEERIN G DRAWI NG IS T HE PROPR IETARY PR OPERTY O F CO MPAL ELECT RONI CS, INC. AND CONTAINS C ONFIDENTIAL
AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSF ERED FR OM TH E CUSTO DY OF THE COMPET ENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY CO MPAL ELECTR ONIC S, INC. N EITHER T HIS SHEET NOR THE INFORMATI ON IT CONTAINS
MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WIT HOUT PRIO R WRITT EN CO NSENT O F COMPAL ELECTRONICS , INC.
3
1
C490
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C466
2
1
C465
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C464
2
1
C463
2
0.1U_0402_10V6K
1
1
C507
0.1U_0402_10V6K
2
2
Title
Size Document Number Re v
2
Date: Sheet of
Compal Electronics, Inc.
ATI RC300M-AGTL+
LA-2051
1
751Friday, November 14, 2003
1.0
5
DDR_SMA0
DDR_SMA1
DDR_SMA2 DDR_DQ2
DDR_SMA3
DDR_SMA4
D D
DDR_SBS013
DDR_SBS113
DDR_SMA1513
DDR_SRAS#13
DDR_SCAS#13
DDR_SWE#13
C C
DDR_CLK013
DDR_CLK0#13
DDR_CLK113
DDR_CLK1#13
DDR_CLK314
DDR_CLK3#14
DDR_CLK414
DDR_CLK4#14
DDR_SCKE013,14
DDR_SCKE113,14
DDR_SCKE214
DDR_SCKE314
DDR_SCS#013,14
DDR_SCS#113,14
DDR_SCS#214
DDR_SCS#314
L34
1 2
+1.8VS
B B
HB-1M2012-121JT03_0805
DDR_SMA5
DDR_SMA6
DDR_SMA7
DDR_SMA8
DDR_SMA9
DDR_SMA10
DDR_SMA11
DDR_SMA12
DDR_DM0
DDR_DM1
DDR_DM2
DDR_DM3
DDR_DM4
DDR_DM5
DDR_DM7
DDR_SRAS#
DDR_SCAS#
DDR_SWE#
DDR_DQS0
DDR_DQS1
DDR_DQS2
DDR_DQS3
DDR_DQS4
DDR_DQS5
DDR_DQS6
DDR_DQS7
DDR_CLK0
DDR_CLK0#
DDR_CLK1
DDR_CLK1#
DDR_CLK3
DDR_CLK3#
DDR_CLK4
DDR_CLK4#
DDR_SCKE0
DDR_SCKE1
DDR_SCKE2
DDR_SCKE3
DDR_SCS#0
DDR_SCS#1
DDR_SCS#2
DDR_SCS#3
MPVDD
C516
MPVSS
1 2
1U_0603_10V6K
U24B
AH19
MEM_A0
AJ17
MEM_A1
AK17
MEM_A2
AH16
MEM_A3
AK16
MEM_A4
AF17
MEM_A5
AE18
MEM_A6
AF16
MEM_A7
AE17
MEM_A8
AE16
MEM_A9
AJ20
MEM_A10
AG15
MEM_A11
AF15
MEM_A12
AE23
MEM_A13
AH20
MEM_A14
AE25
MEM_A15
AH7
MEM_DM0
AF10
MEM_DM1
AJ14
MEM_DM2
AF21
MEM_DM3
AH23
MEM_DM4
AK28
MEM_DM5
AD29
MEM_DM6
AB26
MEM_DM7
AF24
MEM_RAS#
AF25
MEM_CAS#
AE24
MEM_WE#
AJ8
MEM_DQS0
AF9
MEM_DQS1
AH13
MEM_DQS2
AE21
MEM_DQS3
AJ23
MEM_DQS4
AJ27
MEM_DQS5
AC28
MEM_DQS6
AA25
MEM_DQS7
AK10
MEM_CK0
AH10
MEM_CK0#
AH18
MEM_CK1
AJ19
MEM_CK1#
AG30
MEM_CK2
AG29
MEM_CK2#
AK11
MEM_CK3
AJ11
MEM_CK3#
AH17
MEM_CK4
AJ18
MEM_CK4#
AF28
MEM_CK5
AG28
MEM_CK5#
AF13
MEM_CKE0
AE13
MEM_CKE1
AG14
MEM_CKE2
AF14
MEM_CKE3
AH26
MEM_CS#0
AH27
MEM_CS#1
AF26
MEM_CS#2
AG27
MEM_CS#3
AC18
MPVDD
AD18
MPVSS
CHS-216IGP9050A21_BGA718
PART 2 OF 6
MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ8
MEM_DQ9
MEM_DQ10
MEM_DQ11
MEM_DQ12
MEM_DQ13
MEM_DQ14
MEM_DQ15
MEM_DQ16
MEM_DQ17
MEM_DQ18
MEM_DQ19
MEM_DQ20
MEM_DQ21
MEM_DQ22
MEM_DQ23
MEM_DQ24
MEM_DQ25
MEM_DQ26
MEM_DQ27
MEM_DQ28
MEM_DQ29
MEM_DQ30
MEM_DQ31
MEM_DQ32
MEM_DQ33
MEM_DQ34
MEM_DQ35
MEM_DQ36
MEM_DQ37
MEM_DQ38
MEM_DQ39
MEM I/F
MEM_DQ40
MEM_DQ41
MEM_DQ42
MEM_DQ43
MEM_DQ44
MEM_DQ45
MEM_DQ46
MEM_DQ47
MEM_DQ48
MEM_DQ49
MEM_DQ50
MEM_DQ51
MEM_DQ52
MEM_DQ53
MEM_DQ54
MEM_DQ55
MEM_DQ56
MEM_DQ57
MEM_DQ58
MEM_DQ59
MEM_DQ60
MEM_DQ61
MEM_DQ62
MEM_DQ63
MEM_CAP1
MEM_CAP2
MEM_COMP
MEM_DDRVREF
4
AG6
AJ7
AJ9
AJ10
AJ6
AH6
AH8
AH9
AE7
AE8
AE12
AF12
AF7
AF8
AE11
AF11
AJ12
AH12
AH14
AH15
AH11
AJ13
AJ15
AJ16
AF18
AG20
AG21
AF22
AF19
AF20
AE22
AF23
AJ21
AJ22
AJ24
AK25
AH21
AH22
AH24
AJ25
AK26
AK27
AJ28
AH29
AH25
AJ26
AJ29
AH30
AF29
AE29
AB28
AA28
AE28
AD28
AC29
AB29
AC26
AB25
Y26
W26
AE26
AD26
AA26
Y27
AF6
AA29
AK19
AK20
C489
0.1U_0402_10V6K
DDR_DQ0
DDR_DQ1
DDR_DQ3
DDR_DQ4
DDR_DQ5
DDR_DQ6
DDR_DQ7
DDR_DQ8
DDR_DQ9
DDR_DQ10
DDR_DQ11
DDR_DQ12
DDR_DQ13
DDR_DQ14
DDR_DQ15
DDR_DQ16
DDR_DQ17
DDR_DQ18
DDR_DQ19
DDR_DQ20
DDR_DQ21
DDR_DQ22
DDR_DQ23DDR_DM6
DDR_DQ24
DDR_DQ25
DDR_DQ26
DDR_DQ27
DDR_DQ28
DDR_DQ29
DDR_DQ30
DDR_DQ31
DDR_DQ32
DDR_DQ33
DDR_DQ34
DDR_DQ35
DDR_DQ36
DDR_DQ37
DDR_DQ38
DDR_DQ39
DDR_DQ40
DDR_DQ41
DDR_DQ42
DDR_DQ43
DDR_DQ44
DDR_DQ45
DDR_DQ46
DDR_DQ47
DDR_DQ48
DDR_DQ49
DDR_DQ50
DDR_DQ51
DDR_DQ52
DDR_DQ53
DDR_DQ54
DDR_DQ55
DDR_DQ56
DDR_DQ57
DDR_DQ58
DDR_DQ59
DDR_DQ60
DDR_DQ61
DDR_DQ62
DDR_DQ63
C645 0.47U_0603_16V7K
1 2
C432 0.47U_0603_16V7K
1 2
MEN_COMP
R468 49.9_0402_1%
1 2
2
+SDREF
1
3
DDR_DM[0..7]
DDR_DQ[0..63]
DDR_DQS[0..7]
DDR_SMA[0..12]
DDR_DM[0..7] 13,14
DDR_DQ[0..63] 13,14
DDR_DQS[0..7] 13,14
DDR_SMA[0..12] 13
2
1
C724
12
+2.5V+SDREF
0.1U_0402_10V6K
Close to U24.AK20
+2.5V
A A
C547
0.1U_0402_10V6K
1
C475
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C572
2
5
1
C450
2
0.1U_0402_10V6K
1
1
C600
0.1U_0402_10V6K
2
2
Title
Size Document Number Re v
4
3
2
Date: Sheet of
Compal Electronics, Inc.
ATI RC300M-DDR I/F
LA-2051
1
851Friday, November 14, 2003
1.0
5
A_AD[0..31]12,26
A_CBE #[0..3]12,26
D D
C C
?
B B
47U_B_6.3VM
A A
47U_B_6.3VM
A_AD[0..31]
A_CBE #[0..3]
C615
R504
@47K_0402
1 2
1
C548
2
1
2
U24C
AK5
ALINK_AD0
AJ5
ALINK_AD1
AJ4
ALINK_AD2
AH4
ALINK_AD3
AJ3
ALINK_AD4
AJ2
ALINK_AD5
AH2
ALINK_AD6
AH1
ALINK_AD7
AG2
ALINK_AD8
AG1
ALINK_AD9
AG3
ALINK_AD10
AF3
ALINK_AD11
AF1
ALINK_AD12
AF2
ALINK_AD13
AF4
ALINK_AD14
AE3
ALINK_AD15
AE4
ALINK_AD16
AE5
ALINK_AD17
AE6
ALINK_AD18
AC2
ALINK_AD19
AC4
ALINK_AD20
AB3
ALINK_AD21
AB2
ALINK_AD22
AB5
ALINK_AD23
AB6
ALINK_AD24
AA2
ALINK_AD25
AA4
ALINK_AD26
AA5
ALINK_AD27
AA6
ALINK_AD28
Y3
ALINK_AD29
Y5
ALINK_AD30
Y6
ALINK_AD31
AG4
ALINK_CBE#0
AE2
ALINK_CBE#1
AC3
ALINK_CBE#2
AA3
ALINK_CBE#3
AD5
PCI_PAR/ALINK_NC
AC6
PCI_FRAME#/ALINK_STROBE#
AC5
PCI_IRDY#/ALINK_ACAT#
AD2
PCI_TRDY#/ALINK_END#
W4
INTA#
AD3
ALINK_DEVSEL#
AD6
PCI_STOP#/ALINK_OFF#
W5
ALINK_SBREQ#
W6
ALINK_SBGNT#
R500
V5
PCI_REQ#0/ALINK_NC
V6
PCI_GNT#0/ALINK_NC
K5
AGP2_GNT#/AGP3_GNT
K6
AGP2_REQ#/AGP3_REQ
M5
AGP8X_DET#
J6
AGP_VREF/TMDS_VREF
J5
AGP_COMP
CHS-216IGP9050A21_BGA718
0.1U_0402_10V6K
1
C513
2
0.1U_0402_10V6K
Ra
Rb
Rc
1
C555
2
0.1U_0402_10V6K
0.1U_0402_10V6K
C549
A_AD0
A_AD1
A_AD2
A_AD3
A_AD4
A_AD5
A_AD6
A_AD7
A_AD8
A_AD9
A_AD10
A_AD11
A_AD12
A_AD13
A_AD14
A_AD15
A_AD16
A_AD17
A_AD18
A_AD19
A_AD20
A_AD21
A_AD22
A_AD23
A_AD24
A_AD25
A_AD26
A_AD27
A_AD28
A_AD29
A_AD30
A_AD31
A_CBE#0
A_CBE#1
A_CBE#2
A_CBE#3
A_PAR12,26
A_STROBE#26
A_ACAT#26
A_END#26
PCI_PIRQA#19,20 ,24,26
A_DEVSEL#26
A_SBREQ#26
A_SBGNT#26
+1.5VS
+1.5VS
12
R529
1K_0402_1%
Rb
AGPREF_8X
12
R533
1K_0402_1%
Rc
+1.5VS +3VS
0.1U_0402_10V6K
1
1
+
C540
C506
C557
2
2
0.1U_0402_10V6K
+1.5VS
0.1U_0402_10V6K
1
1
+
C487
C523
2
0.1U_0402_10V6K
C508
2
5
A_PAR
A_STROBE#
A_ACAT#
A_END#
R517 0_0402_5%
1 2
A_DEVSEL#
A_OFF#
A_OFF#26
A_SBREQ#
A_SBGNT#
1 2
+3VS
8.2K_0402_5%
AGP8X_DET#
AGPREF_8X
1 2
0.1U_0402_10V6K
R523
AGP_COMP
1 2
@52.3_0603_1%
Ra
+3VS
AGP8X_DET#
0.1U_0402_10V6K
1
1
C524
C530
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
C565
2
2
0.1U_0402_10V6K
8X(M9+M10@)
169_0402_1%
324_0402_1%
100_0402_1%
0.1U_0402_10V6K
1
1
C529
2
2
PIR LAYOUT 92.06.23
+1.5VS
1
C539
C564
2
0.1U_0402_10V6K
4
PART 3 OF 6
PCI Bus 0 / A-Link I/F
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C554
2
4
AGP2_SBSTB/AGP3_SBSTBF/NC/LVDS_BLON
AGP2_SBSTB#/AGP3_SBSTBS/NC/ENA_BL
AGP2_ADSTB0/AGP3_ADSTBF0/TMD2_CLK#
AGP2_ADSTB0#/AGP3_ADSTBS0/TMD2_CLK
AGP2_ADSTB1/AGP3_ADSTBF1/TMD1_CLK#
AGP2_ADSTB1#/AGP3_ADSTBS1/TMD1_CLK
AGP2_CBE#0/AGP3_CBE0/TMD2_D7
AGP2_CBE#1/AGP3_CBE1/TMD2_DE
AGP2_CBE#3/AGP3_CBE3/TMD1_D5
AGP2_IRDY#/AGP3_IRDY/GPIO8/I2C_CLK
AGP2_TRDY#/AGP3_TRDY/TMDS_DVI_CLK
AGP2_STOP#/AGP3_STOP/GPIO10/DDC_DATA
AGP2_FRAME#/AGP3_FRAME/TMDS_DVI_DATA
AGP2_DEVSEL#/AGP3_DEVSEL/GPIO9/I2C_DATA
PCI BUS 1 / AGP Bus (GPIO , TMDS , Z VPort )
AGP2_SBA0/AGP3_SBA#0/GPIO0/VDDC_CNTL0
AGP2_SBA1/AGP3_SBA#1/GPIO1/VDDC_CNTL1
AGP2_SBA2/AGP3_SBA#2/GPIO2/LVDS_BLON#
AGP2_SBA3/AGP3_SBA#3/GPIO3/LVDS_DIGON
AGP2_SBA4/AGP3_SBA#4/GPIO4/STP_AGP#
AGP2_SBA5/AGP3_SBA#5/GPIO5/AGP_BUSY#
AGP2_SBA6/AGP3_SBA#6/GPIO6/LVDS_SSOUT
AGP2_SBA7/AGP3_SBA#7/GPIO7/LVDS_SSIN
4X(NAGP@)
52.1_0402_1%
1K_0402_1%
1K_0402_1%
10U_0805_10V4Z
1
C515
2
1
2
C580
1
C640
2
0.1U_0402_10V6K
1
2
0.1U_0402_10V6K
1
C641
2
0.1U_0402_10V6K
L
3
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD31
AGP_PAR
AGP_ST0
AGP_ST1
AGP_ST2
1
C638
2
0.1U_0402_10V6K
1
C629
2
0.1U_0402_10V6K
Y2
W3
W2
V3
V2
V1
U1
U3
T2
R2
P3
P2
N3
N2
M3
M2
L1
L2
K3
K2
J3
J2
J1
H3
F3
G2
F2
F1
E2
E1
D2
D1
E5
E6
T3
U2
G3
H2
R3
M1
L3
H1
P5
R6
T6
T5
P6
R5
C1
D3
N6
N5
C3
C2
D4
E4
F6
F5
G6
G5
L6
M6
L5
0.1U_0402_10V6K
1
C617
2
0.1U_0402_10V6K
1
C630
2
@10U_0805_6.3V6M
DDC_CLK
DDC_DAT
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7
1
C618
2
0.1U_0402_10V6K
1
C631
2
0.1U_0402_10V6K
AGP_AD0/TMD2_HSYNC
AGP_AD1/TMD2_VSYNC
AGP_AD10/TMD2_D8
AGP_AD11/TMD2_D11
AGP_AD12/TMD2_D10
AGP_AD16/TMD1_VSYNC
AGP_AD17/TMD1_HSYNC
AGP_AD18/TMD1_DE
AGP_AD19/TMD1_D0
AGP_AD20/TMD1_D1
AGP_AD21/TMD1_D2
AGP_AD22/TMD1_D3
AGP_AD23/TMD1_D4
AGP_AD24/TMD1_D7
AGP_AD25/TMD1_D6
AGP_AD26/TMD1_D9
AGP_AD27/TMD1_D8
AGP_AD28/TMD1_D11
AGP_AD29/TMD1_D10
AGP_AD30/TMDS_HPD
AGP2_CBE#2/AGP3_CBE2
AGP2_PIPE#/AGP3_DBI_HI
AGP2_NC/AGP3_DBI_LO
AGP2_RBF#/AGP3_RBF
AGP2_WBF#/AGP3_WBF
0.1U_0402_10V6K
1
C633
C639
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C628
C627
2
AGP_AD2/TMD2_D1
AGP_AD3/TMD2_D0
AGP_AD4/TMD2_D3
AGP_AD5/TMD2_D2
AGP_AD6/TMD2_D5
AGP_AD7/TMD2_D4
AGP_AD8/TMD2_D6
AGP_AD9/TMD2_D9
Note: PLACE CLO SE TO U 27 (NB RC300M)
THIS SHEET OF ENGINEERIN G DRAWI NG IS T HE PROPR IETARY PR OPERTY O F CO MPAL ELECT RONI CS, INC. AND CONTAINS C ONFIDENTIAL
AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSF ERED FR OM TH E CUSTO DY OF THE COMPET ENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY CO MPAL ELECTR ONIC S, INC. N EITHER T HIS SHEET NOR THE INFORMATI ON IT CONTAINS
MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WIT HOUT PRIO R WRITT EN CO NSENT O F COMPAL ELECTRONICS , INC.
3
@0.1U_0402_10V6K
1
C653
2
@0_0402_5%
0.1U_0402_10V6K
1
C602
2
0.1U_0402_10V6K
1
C556
2
1
C656
12
12
2
R296
12
R277
@0_0402_5%
Note: PLACE CLO SE TO U 2 ( NB RC300M)
L
2.2K_0402_5%
0.1U_0402_10V6K
1
1
C601
2
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
1
C589
C571
2
2
0.1U_0402_10V6K
R295
@0_0402_5%
S0
S1
12
@SM561BS_SO8
R276
@0_0402_5%
+3VS
R518
ENBKL# 35
AGP_STP# 27
AGP_BUSY# 27
1
C605
2
1
C620
2
0.1U_0402_10V6K
U44
1
Xin/CLK
7
S0
6
S1
LVDS SPREAD SPECTRUM
R519
2.2K_0402_5%
1 2
1 2
C568
@0.01U _0402_16V7Z
0.1U_0402_10V6K
1
C608
2
2
+3VS_SSVDD
@0_0402_5%
R294
2
VDD
SSCLK
Xout
SSCC
VSS
3
R293
@0_0402_5%
R628
1.2K_0402_5%
1 2
+1.5VS
@0.01U _0402_16V7Z
1
C498
2
1
2
2
L42
1 2
@BLM21P300S_0805
12
12
R275
@0_0402_5%
4
8
1
C657
5
@10P_0402_25V8K
12
12
2
R274
@0_0402_5%
ENVDD 18
ATI request
@0.01U _0402_16V7Z
1
1
C569
2
2
@0.01U _0402_16V7Z
1
R600
12
@0_0402_5%
+3VS
R534
LVDS_SSOUT AGP_SBA6
1
C651
@10P_0402_25V8K
2
LVDS_SSIN
1
C585
C610
2
@0.01U _0402_16V7Z
12
@0_0402_5%
R535
AGP_SBA7
12
@0_0402_5%
R601
12
@0_0402_5%
@0.01U _0402_16V7Z
1
2
Title
Size Doc u m ent Number Re v
Date: Sheet of
@0.01U _0402_16V7Z
1
1
C609
2
2
@0.01U _0402_16V7Z
C514
C619
Compa l Electronics, Inc.
ATI RC300M-AGP, ALINK BUS
LA-2051
1
C595
2
@0.01U _0402_16V7Z
1
EXT_LVDS_SSOUT 38
EXT_LVDS_SSIN 38
@0.01U _0402_16V7Z
1
1
C558
2
2
951Friday, November 14, 2003
1.0
5
D D
KC FB M- L11-201209-221LMAT_0805
L37
1 2
+1.8VS
0.1U_ 0402_10V6K
1 2
+1.8VS
C C
CLK_ AGP_66M
12
R272
@10_0402_5%
1
C282
@15P_0402_50V8J
2
CLK_MEM_66M
12
B B
R271
@10_0402_5%
1
C271
@15P_0402_50V8J
2
+1.8VS
KC FB M- L11-201209-221LMAT_0805
REFCLK1_NB16
+3VS
X4
4
1
1
C592
@27M HZ_20P_6N
@0.1 U_0402_16V7K
2
VCC
ST
KC FB M- L11-201209-221LMAT_0805
1
C550
2
L33 10_0603_5%
0.1U_ 0402_10V6K
L38
1 2
10U_0 805_10V4Z
0.1U_ 0402_10V6K
R506
56_0402_5%
3
OUT
2
GND
4
L35
+1.8VS_ AVDDDI
1
1
C537
C536
0.1U_ 0402_10V6K
2
2
1
1
C577
C578
2
2
INTCRT_R18
INTCRT_G18
INTCRT_B18
INTCRT_HSYNC18
INTCRT_VSYNC18
R474 715 _0402_1%
1 2
12
R520
CLK_ NB_BCLK16
12
CLK_ NB_BCLK#16
@10_0402_5%
1
C634
@15P_0402_50V8J
2
CLK_ AGP_66M16
CLK_MEM_66M16
27M_TV
R497 @22_0402_5%
R505
@10_0402_5%
EXCLK_27M_TV38
+2.5VS
12
1
2
+1.8VS_ AVDDQ
1
2
27M_TV_R
12
+2.5VS_ AVDD
C551
0.1U_ 0402_10V6K
+PLL VDD_18
C586
0.1U_ 0402_10V6K
NB_RSET
RC300M_X1
RC300M_X2
CLK_NB_ BCLK
CLK_NB_ BCLK#
CLK_AGP_66M
CLK_MEM_66M
12
12
R588
4.7K_0402_5%
+3VS
L39
+3VS_VDDR
1 2
1
C622
0.1U_ 0402_10V6K
2
U24D
G9
VDDR3
H9
A14
B13
B14
C13
A15
B15
H11
G11
F14
F15
E14
C8
D9
C14
A4
B4
A5
B5
B6
A6
D8
B2
B3
A3
D7
B7
C5
PART 4 OF 6
VDDR3
AVDD_25
AVSSN
AVDDDI_18
AVSSDI
AVDDQ
AVSSQ
PLLVDD_18
PLLVSS
RED
GREEN
BLUE
DACHSYNC
DACVSYNC
RSET
XTALIN
XTALOUT
HCLKIN
HCLKIN#
SYS_FBCLKOUT
SYS_FBCLKOUT#
ALINK_CLK
AGPCLKOUT
AGPCLKIN
EXT_MEM_CLK
USBCLK
REF27
CLK. GEN.
OSC
CHS-216IGP9050A21_BGA718
Note: P L ACE CLOS E TO U27 ( N B CHIP)
L
RC300M_X1
@1M_0402_1%
RC300M_X2
3
+3VS
FBM-11-160808-121-T_0603
CRT
12
R531
TXOUT_U0N
TXOUT_U0P
TXOUT_U1N
TXOUT_U1P
TXOUT_U2N
TXOUT_U2P
TXCLK_UN
TXCLK_UP
TXOUT_L0N
TXOUT_L0P
TXOUT_L1N
TXOUT_L1P
TXOUT_L2N
TXOUT_L2P
TXCLK_LN
TXCLK_LP
LPVDD_18
LVDS
LPVSS
LVDDR_18
LVDDR_18
LVSSR
LVSSR
C_R
Y_G
COMP_B
SVID
DACSCL
DACSDA
CPUSTOP#
SYSCLK
SYSCLK#
C650
1 2
12
@18P_0402_50V8K
Y5
@14. 31818MHZ_20P_6X1430004201
C649
1 2
@18P_0402_50V8K
D12
E12
F11
F12
D13
D14
E13
F13
E10
D10
B9
C9
D11
E11
B10
C10
A12
A11
B12
C12
B11
C11
E15
C15
D15
D6
C6
D5
A8
B8
LCD_ B0- 18
LCD_ B0+ 18
LCD_ B1- 18
LCD_ B1+ 18
LCD_ B2- 18
LCD_ B2+ 18
LCD_ BCLK- 18
LCD_ BCLK+ 18
LCD_A0- 18
LCD_A0+ 18
LCD_A1- 18
LCD_A1+ 18
LCD_A2- 18
LCD_A2+ 18
LCD_ACLK- 18
LCD_ACLK+ 18
+1.8 VS_LPVDD
LPVSS
+1.8VS_LVDDR
LVSSR
TV_CRMA 17
TV_LUMA 17
0.1U_ 0402_10V6K
TV_COMPS 17
INTDDCCK 18
INTDDCDA 18
Q45
D
1 3
1 2
R457 @0_0402_5%
1 2
R461 1K_0402_5%
1
C591
2
0.1U_ 0402_10V6K
0.1U_ 0402_10V6K
1
C566
2
@2N70 02_SOT23
S
G
2
2
0.1U_ 0402_10V6K
1
C576
C518
2
10U_0 805_10V4Z
1
C587
C567
2
10U_0 805_10V4Z
PM_S TPCPU#
+3VS
KC FB M- L11-201209-221LMAT_0805
1 2
L32
1
2
KC FB M- L11-201209-221LMAT_0805
1 2
L36
1
2
PM_S TPCPU# 5,1 6,26,47
PCIRS T# 19,2 0,21, 22,24,25,26,34,35
1
+1.8VS
+1.8VS
A A
Compa l Electronics, Inc.
THIS SHEET OF ENGI NEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CO NF IDENTIAL
AND T R ADE SECRET INFORMATION. T HIS SHEET M AY NO T BE T RANSFERED FROM THE CUSTODY OF THE COM PET ENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHOR IZED BY COMPA L ELECTRONICS , INC. NEITH ER THIS SHEE T NOR THE INFORM ATION IT CONTAI NS
5
4
MAY BE USED BY OR DISCLOSED TO ANY TH IRD PART Y W IT H OUT PR IOR W RIT TEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2
Title
Size Do c ument Nu mbe r Re v
Date : Sheet
ATI RC300M-VIDEO I/F
LA-2051
1
1.0
of
10 51Friday, November 14, 2003
5
4
3
2
1
+1.5VS +2.5V
U24E
F10
VDD_CORE
F9
VDD_CORE
G12
VDD_CORE
H12
VDD_CORE
H13
VDD_CORE
M12
VDD_CORE
M13
VDD_CORE
M14
10U_0805_10V4Z
VDD_CORE
M17
VDD_CORE
M18
VDD_CORE
M19
VDD_CORE
N12
VDD_CORE
N13
VDD_CORE
N14
VDD_CORE
N17
VDD_CORE
N18
VDD_CORE
N19
VDD_CORE
P12
VDD_CORE
P13
VDD_CORE
P14
VDD_CORE
P17
VDD_CORE
P18
VDD_CORE
P19
VDD_CORE
U12
VDD_CORE
U13
VDD_CORE
U14
VDD_CORE
U17
VDD_CORE
U18
VDD_CORE
U19
VDD_CORE
V12
VDD_CORE
V13
VDD_CORE
V14
VDD_CORE
V17
VDD_CORE
V18
VDD_CORE
V19
VDD_CORE
W12
VDD_CORE
W13
VDD_CORE
W14
VDD_CORE
W17
VDD_CORE
W18
VDD_CORE
W19
VDD_CORE
C16
VDDR2_CPU
D16
VDDR2_CPU
D17
VDDR2_CPU
E16
VDDR2_CPU
E17
VDDR2_CPU
F16
VDDR2_CPU
F17
VDDR2_CPU
G17
VDDR2_CPU
G21
VDDR2_CPU
G23
VDDR2_CPU
G24
VDDR2_CPU
H16
VDDR2_CPU
H17
VDDR2_CPU
H19
VDDR2_CPU
H21
VDDR2_CPU
H24
VDDR2_CPU
K23
VDDR2_CPU
K24
VDDR2_CPU
M23
VDDR2_CPU
P23
VDDR2_CPU
P24
VDDR2_CPU
T23
VDDR2_CPU
T24
VDDR2_CPU
U23
VDDR2_CPU
U24
VDDR2_CPU
W30
VDDR2_CPU
AA1
VDDL_ALINK
AA7
VDDL_ALINK
AA8
VDDL_ALINK
AC7
VDDL_ALINK
AC8
VDDL_ALINK
AD1
VDDL_ALINK
AD7
VDDL_ALINK
AD8
VDDL_ALINK
AK3
VDDL_ALINK
W8
VDDL_ALINK
CHS-216IGP9050A21_BGA718
+1.8VS
1
C575
C581
2
0.1U_0402_10V6K
D D
C C
B B
A A
+CPU_ CORE
+3VS
CORE PWR
CPU I/F PWRALINK PWR
0.1U_0402_10V6K
1
C482
2
PART 5 OF 6
POWER
VDDP_AGP/VDDP33
VDDP_AGP/VDDP33
VDDP_AGP/VDDP33
1
C481
2
0.1U_0402_10V6K
MEM I/F PWR
AGP PWR
1
2
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDDP_AGP
VDD_18
VDD_18
VDD_18
VDD_18
AA23
AA27
AB30
AC10
AC12
AC13
AC15
AC17
AC19
AC21
AC23
AC24
AC25
AC27
AD10
AD12
AD13
AD15
AD17
AD19
AD21
AD23
AD24
AD25
AD27
AE10
AE14
AE15
AE19
AE20
AE30
AE9
AF27
AG11
AG12
AG17
AG18
AG23
AG24
AG26
AG8
AG9
AJ30
AK14
AK23
AK8
V23
W23
W24
W25
Y25
A2
G4
H5
H6
H7
J4
K8
L4
M7
M8
N4
P1
P7
P8
R4
T8
U4
U5
U6
E7
F7
G8
AC22
AC9
H10
H22
1
C588
0.1U_0402_10V6K
2
+1.5VS
+3VS
+1.8VS
C429
100U_D2_10VM
+2.5V
1
+
2
0.1U_0402_10V6K
C505
A29
AB23
AB24
AB27
AB4
AB8
AC1
AC11
AC14
AC16
AC20
AC30
AD11
AD14
AD16
AD20
AD4
AE27
AF30
AF5
AG10
AG13
AG16
AG19
AG22
AG25
AG7
AH28
AH3
AJ1
AK13
AK2
AK22
AK29
AK4
AK7
B1
B16
B30
C19
C23
C27
C4
D21
D25
E3
E8
E9
F27
G14
G15
G18
G20
H14
H15
H18
H20
H27
H4
H8
0.1U_0402_10V6K
1
C445
2
F4
F8
J7
U24F
PART 6 OF 6
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CHS-216IGP9050A21_BGA718
0.1U_0402_10V6K
1
1
C570
C462
2
2
0.1U_0402_10V6K
R23
VSS
R7
VSS
R8
VSS
T12
VSS
T13
VSS
T14
VSS
T15
VSS
T16
VSS
T17
VSS
T18
VSS
T19
VSS
T27
VSS
T4
VSS
U15
VSS
U16
VSS
U7
VSS
U8
VSS
V15
VSS
V16
VSS
V27
VSS
V4
VSS
V7
VSS
V8
VSS
W15
VSS
W16
VSS
W27
VSS
Y1
VSS
Y23
VSS
Y24
VSS
Y30
VSS
Y4
VSS
Y7
VSS
Y8
VSS
R19
VSS
R18
VSS
R17
VSS
R16
VSS
R15
VSS
R14
VSS
R13
VSS
R12
VSS
R1
VSS
P4
VSS
P27
VSS
P16
VSS
P15
VSS
N8
VSS
N24
VSS
N23
VSS
N16
VSS
N15
VSS
M4
VSS
M27
VSS
M16
VSS
M15
VSS
L8
VSS
L7
VSS
L25
VSS
L24
VSS
L23
VSS
K4
VSS
K27
VSS
J8
VSS
1
C436
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C553
2
1
C538
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C522
2
1
C461
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C446
2
1
C457
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C437
2
1
1
C438
0.1U_0402_10V6K
2
2
THIS SHEET OF ENGINEERIN G DRAWI NG IS T HE PROPR IETARY PR OPERTY O F CO MPAL ELECT RONI CS, INC. AND CONTAINS C ONFIDENTIAL
AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSF ERED FR OM TH E CUSTO DY OF THE COMPET ENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY CO MPAL ELECTR ONIC S, INC. N EITHER T HIS SHEET NOR THE INFORMATI ON IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WIT HOUT PRIO R WRITT EN CO NSENT O F COMPAL ELECTRONICS , INC.
3
2
Title
Size Doc u m ent Number Re v
Date: Sheet of
Compal Electronics, Inc.
ATI RC300M-POWER
LA-2051
1
11 51Friday, November 14, 2003
1.0
5
R418 10K_0402_5%
A_AD31
D D
C C
B B
A A
A_AD30
A_AD29
A_AD28
A_AD27
A_AD26
A_AD25
A_AD24
A_AD23
A_AD22
A_AD21
A_AD20
A_CBE#3
A_CBE#0
5
R420 4.7K_0402_5%
R419 4.7K_0402_5%
R549 10K_0402_5%
R278 @4.7K_0402_5%
R544 @10K_0402_5%
R283 4.7K_0402_5%
R548 10K_0402_5%
R279 @4.7K_0402_5%
R547 10K_0402_5%
R280 @4.7K_0402_5%
R545 10K_0402_5%
R282 @4.7K_0402_5%
R543 10K_0402_5%
R541 10K_0402_5%
R286 @4.7K_0402_5%
R284 @4.7K_0402_5%
R542 10K_0402_5%
R285 @4.7K_0402_5%
R540 @4.7K_0402_5%
R287 4.7K_0402_5%
R546 @4.7K_0402_5%
R281 @4.7K_0402_5%
R536 @4.7K_0402_5%
R291 @4.7K_0402_5%
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
R417 10K_0402_5%
1 2
2 1
D45
RB751 V_SOD323
2 1
D44
RB751 V_SOD323
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
+3VS
4
+3VS
+3VS
BSEL1 5,16
BSEL0 5,16
A_AD[31..30] : FSB CLK SPEED
DEFAULT: 01
A_AD29: STRAP CONFIGURATION
DEFAULT:1
0: REDUCEDE SET
1: FU LL SET( inter nal Pull high)
A_AD28: SPREAD SPECTRUM ENABLE
DEFAULT:0
0: DISABLE
1: ENABLE
A_AD2 7: F rcS hort Reset #
DEFAULT: 1
0: TEST MODE
1: NORMAL MODE
A_AD26 : ENABLE IOQ
DEFAULT: 1
0: IOQ=1
1: IOQ=12
A_AD25/ A _ A D 1 7 : C P U VOLTAGE[1..0]
DEFAULT: 10
00: 1.05V
01: 1.35V
11: 1.75V
10: 1.45V
A_AD24 : MOBILE CPU SELECT
DEFAULT: 1
0: BANIAS CPU
1: OTHER CPU
A_AD23 : CLOCK BYPASS DISABLE
DEFAULT: 1
0: TEST MODE
1: NORMAL(internal Pull high)
A_AD22 : OSC PAD OUTPUT PCICLK
DEFAULT : 1
0:PCICLK OUT
1: OSC CLK OUT
A_AD21 : AUTO_CAL ENABLE
DEFAULT : 1
0: DISABLE
1: ENABLE
A_AD20 : INTERNAL CLK GEN ENABLE
DEFAULT : 0
0: DISABLE
1: ENABLE
A_CBE#3: NOT USED
A_CBE#0 :NO USED
4
00: 100 MHZ
01: 133 MHZ
10: 2 00MHZ
11:166 MHZ
AD25=1 DESTOP CPU
AD25=0 MOBILE CPU
AD17--DON'T CARE
3
A_AD[0..31]9,26
A_CBE #[0..3]9,26
A_AD[0..31]
A_CBE #[0..3]
R537 @4.7K_0402_5%
A_AD18
A_AD17
A_PAR9,26
THIS SHEET OF ENGINEERIN G DRAWI NG IS T HE PROPR IETARY PR OPERTY O F CO MPAL ELECT RONI CS, INC. AND CONTAINS C ONFIDENTIAL
AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSF ERED FR OM TH E CUSTO DY OF THE COMPET ENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY CO MPAL ELECTR ONIC S, INC. N EITHER T HIS SHEET NOR THE INFORMATI ON IT CONTAINS
MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WIT HOUT PRIO R WRITT EN CO NSENT O F COMPAL ELECTRONICS , INC.
3
1 2
R290 4.7K_0402_5%
1 2
R538 @4.7K_0402_5%
1 2
R289 4.7K_0402_5%
1 2
A_PAR
2
R288 @4.7K_0402_5%
1 2
R539 4.7K_0402_5%
1 2
2
1
+3VS
+3VS
A_AD18 : ENABLE PHASE CALIBRATION
DEFAULT: 0
0: DISABLE
1:ENABLE
A_AD25/ A _ A D 1 7 : C P U VOLTAGE[1..0]
DEFAULT: 0
00: 1.05V
01: 1.35V
11: 1.75V
10: 1.45V
PAR: EXT EN D E D D EB U G MODE
DEFAULT : 1
+3VS
0: DEBUG MODE
1: NORMAL
Title
Size Doc u m ent Number Re v
Date: Sheet of
Compal Electronics, Inc.
ATI RC300M-SYSTEM STRAP
LA-2051
12 51Friday, November 14, 2003
1
1.0
A
1 1
2 2
DDR_DQ[0..63]
DDR_DQS[0..7]
DDR_DM[0..7]
DDR_SMA[0..12]
3 3
4 4
A
B
DDR_DQ[0..63] 8,14
DDR_DQS[0..7] 8,14
DDR_DM[0..7] 8,14
DDR_SMA[0..12] 8
B
C
C725
12
+2.5V+SDREF
0.1U_0402_10V6K
DDR_CLK08
DDR_CLK0#8
DDR_SCKE18,14
DDR_SCS#08,14
1 2
10_0402_5%
10_0402_5%
1 2
DDR_SMA158
Layout note
Place these resistors
close to DIMM0,
all trace length<500 mil
DDR TOPOLOGY 1 FOR SMAA[0, 3, 6:12], SBA[1, 0], SRAS#, SCAS#, SWE#
C
D
+2.5V
JP17
1
VREF
3
VSS
5
DDR_DQ 5
DDR_DQS0
DDR_DQ 1
DDR_DQ 3
DDR_DQ 8
DDR_DQ 9
DDR_DQS1
DDR_DQ11
DDR_DQ10
DDR_DQ20
DDR_DQ21
DDR_DQS2
DDR_DQ18
DDR_DQ28
DDR_DQS3
DDR_DQ27 DDR_DQ29
R592
DDR_SMA12
DDR_SMA9
DDR_SMA7
DDR_SMA5
DDR_SMA3
DDR_SMA1
DDR_SMA10
DDR_SBS0
R594
DDR_SWE#
DDR_SMA15
DDR_DQ32
DDR_DQ34
DDR_DQS4 DDR_DM4
DDR_DQ39
DDR_DQ37
DDR_DQ44
DDR_DQS5
DDR_DQ47
DDR_DQ43
DDR_DQ48
DDR_DQ49
DDR_DQ54
DDR_DQ55
DDR_DQ63
DDR_DQS7
DDR_DQ62
DDR_DQ57 DDR_DQ58
SMDATA14,16,27
SMCLK14,16,27
+3VS
D
DQ0
7
DQ1
9
VDD
11
DQS0
13
DQ2
15
VSS
17
DQ3
19
DQ8
21
VDD
23
DQ9
25
DQS1
27
VSS
29
DQ10
31
DQ11
33
VDD
35
CK0
37
CK0#
39
VSS
41
DQ16
43
DQ17
45
VDD
47
DQS2
49
DQ18
51
VSS
53
DQ19
55
DQ24
57
VDD
59
DQ25
61
DQS3
63
VSS
65
DQ26
67
DQ27
69
VDD
71
CB0
73
CB1
75
VSS
77
DQS8
79
CB2
81
VDD
83
CB3
85
DU
87
VSS
89
CK2
91
CK2#
93
VDD
95
CKE1
97
DU/A13
99
A12
101
A9
103
VSS
105
A7
107
A5
109
A3
111
A1
113
VDD
115
A10/AP
117
BA0
119
WE#
121
S0#
123
DU
125
VSS
127
DQ32
129
DQ33
131
VDD
133
DQS4
135
DQ34
137
VSS
139
DQ35
141
DQ40
143
VDD
145
DQ41
147
DQS5
149
VSS
151
DQ42
153
DQ43
155
VDD
157
VDD
159
VSS
161
VSS
163
DQ48
165
DQ49
167
VDD
169
DQS6
171
DQ50
173
VSS
175
DQ51
177
DQ56
179
VDD
181
DQ57
183
DQS7
185
VSS
187
DQ58
189
DQ59
191
VDD
193
SDA
195
SCL
197
VDD_SPD
199
VDD_ID
KLINK_5746-2-111
THIS SH E E T OF E N GI N E E R I N G D R A W I N G I S T H E PR O P R I E TA R Y P R OP E R T Y OF C OM P A L E L EC T R O N I C S , I N C . AND CONTAINS CONFIDENTIAL
AND TR AD E S E C R E T I N FO R M AT I ON. THIS S H E E T MA Y N O T B E T R AN S F E R E D FROM THE C U ST O D Y OF THE COMPETENT DIVISION OF R&D
DEPAR TM E N T E X C E P T AS A U T H OR I Z E D B Y C OM P A L E LE C T R ON I CS, INC . N E I TH E R T H I S S H E ET NOR THE INFORMATION IT CONTAINS
MAY BE U S E D B Y O R D I S C LO S E D TO A N Y TH I R D P A R T Y W I TH O U T PR I O R W R I T TE N C O N S E N T O F COMPAL ELECTRONICS, INC.
E
DU/RESET#
E
VREF
DQ12
DQ13
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQ30
DQ31
CKE0
DU/BA2
RAS#
CAS#
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQ46
DQ47
DQ52
DQ53
DQ54
DQ55
DQ60
DQ61
DQ62
DQ63
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
VDD
DM1
VSS
VDD
VDD
VSS
VSS
VDD
DM2
VSS
VDD
DM3
VSS
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
VSS
VSS
VDD
VDD
A11
A8
VSS
A6
A4
A2
A0
VDD
BA1
S1#
DU
VSS
VDD
DM4
VSS
VDD
DM5
VSS
VDD
CK1#
CK1
VSS
VDD
DM6
VSS
VDD
DM7
VSS
VDD
SA0
SA1
SA2
DU
F
+2.5V
2
4
DDR_DQ 6DDR_DQ 7
6
DDR_DQ 0
8
10
DDR_DM0
12
DDR_DQ4
14
16
DDR_DQ 2
18
DDR_DQ12
20
22
DDR_DQ13
24
DDR_DM1
26
28
DDR_DQ15
30
DDR_DQ14
32
34
36
38
40
DDR_DQ16
42
DDR_DQ17
44
46
DDR_DM2
48
DDR_DQ22DDR_DQ23
50
52
DDR_DQ19
54
DDR_DQ24
56
58
DDR_DQ25DDR_DQ26
60
DDR_DM3
62
64
66
DDR_DQ30DDR_DQ31
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DDR_SMA11
DDR_SMA8
DDR_SMA6
DDR_SMA4
DDR_SMA2
DDR_SMA0
DDR_SBS1
DDR_SRAS#
DDR_SCAS#
DDR_DQ33
DDR_DQ36
DDR_DQ35
DDR_DQ38
DDR_DQ40DDR_DQ41
DDR_DQ45
DDR_DM5
DDR_DQ42
DDR_DQ46
DDR_DQ53
DDR_DQ52
DDR_DM6DDR_DQS6
DDR_DQ50
DDR_DQ51
DDR_DQ60DDR_DQ61
DDR_DQ56
DDR_DM7
DDR_DQ59
R593
1 2
10_0402_5%
R595
1 2
10_0402_5%
1
2
DDR_CLK1# 8
DDR_CLK1 8
F
+SDREF
C679
0.1U_0402_10V6K
DDR_SWE#8
DDR_SBS08
DDR_SCAS#8
DDR_SRAS#8
DDR_SBS18
DDR_SCKE0 8,14
DDR_SCS#1 8,14
G
DDR_DQ[0..63]
DDR_DQS[0..7]
DDR_DM[0..7]
DDR_SMAA[0..12]
DDR_SMAA15
10_1206_8P4R_5%
DDR_SMA15 DDR_SMAA15
DDR_SWE#
DDR_SBS0
DDR_SMA10
DDR_SMA1
DDR_SMA3
DDR_SMA5
DDR_SMA7
DDR_SMA9
DDR_SMA12
DDR_SCAS#
DDR_SRAS#
DDR_SBS1
DDR_SMA0
DDR_SMA2
DDR_SMA4
DDR_SMA6
DDR_SMA8
RP19
10_1206_8P4R_5%
RP27
R234 10_0402_5%
R239 10_0402_5%
10_1206_8P4R_5%
10_1206_8P4R_5%
DDR_SMA11
R238 10_0402_5%
45
36
27
18
45
36
27
18
12
RP18
RP28
DDR_SMAA10
DDR_SMAA1
DDR_SMAA3
DDR_SMAA5
DDR_SMAA7
DDR_SMAA9
12
DDR_SMAA12
45
36
27
18
45
36
27
18
12
DDR_SMAA0
DDR_SMAA2
DDR_SMAA4
DDR_SMAA6
DDR_SMAA8
DDR_SMAA11
DDR_DQ[0..63] 8,14
DDR_DQS[0..7] 8,14
DDR_DM[0..7] 8,14
DDR_SMAA[0..12] 14
DDR_SMAA15 14
DDR_WE# 14
DDR_BS0 14
DDR_CAS# 14
DDR_RAS# 14
DDR_BS1 14
Layout note
Place these resistor
close by DIMM0,
all trace length
Max=1.4"
Title
Size D ocu m ent N u mber R ev
Date: Sheet
Compal Elect r onics, Inc.
DDR-SODIMM SLOT0
LA-2051
G
H
1.0
of
13 51Friday, Nove mber 14, 2003
H
A
+1.25VS
RP37
DDR_DQ7
DDR_DQ5
DDR_DQS0
DDR_DQ1
56_0804_8P4R_5%
1 1
DDR_DQ3
DDR_DQ8
DDR_DQ9
DDR_DQS1
56_0804_8P4R_5%
DDR_DQ11
DDR_DQ10
DDR_DQ20
DDR_DQ21
56_0804_8P4R_5%
DDR_DQS2
DDR_DQ23
DDR_DQ18
DDR_DQ28
DDR_DQ26
DDR_DQS3
DDR_DQ27
DDR_DQ31
DDR_DQ32
DDR_DQ34
DDR_DQS4
DDR_DQ39
DDR_DQ37
DDR_DQ41
DDR_DQ44
DDR_DQS5
DDR_DQ47
DDR_DQ43
DDR_DQ48
DDR_DQ49
DDR_DQS6
DDR_DQ54
DDR_DQ55
DDR_DQ61
DDR_DQ63
DDR_DQS7
DDR_DQ62
DDR_DQ57
56_0804_8P4R_5%
56_0804_8P4R_5%
56_0804_8P4R_5%
56_0804_8P4R_5%
56_0804_8P4R_5%
56_0804_8P4R_5%
56_0804_8P4R_5%
2 2
3 3
4 4
18
27
36
45
RP35
18
27
36
45
RP33
18
27
36
45
RP32
18
27
36
45
RP30
18
27
36
45
RP15
18
27
36
45
RP13
18
27
36
45
RP11
18
27
36
45
RP7
18
27
36
45
RP6
18
27
36
45
A
RP91
56_0804_8P4R_5%
RP84
56_0804_8P4R_5%
RP73
56_0804_8P4R_5%
RP71
56_0804_8P4R_5%
RP68
56_0804_8P4R_5%
RP58
56_0804_8P4R_5%
RP55
56_0804_8P4R_5%
RP52
56_0804_8P4R_5%
RP42
56_0804_8P4R_5%
RP41
56_0804_8P4R_5%
DDR_DQ6
18
DDR_DQ0
27
DDR_DM0
36
DDR_DQ4
45
DDR_DQ2
18
DDR_DQ12
27
DDR_DQ13
36
DDR_DM1
45
DDR_DQ15
18
DDR_DQ14
27
DDR_DQ16
36
DDR_DQ17
45
DDR_DM2
18
DDR_DQ22
27
DDR_DQ19
36
DDR_DQ24
45
DDR_DQ25
18
DDR_DM3
27
DDR_DQ29
36
DDR_DQ30
45
DDR_DQ33
18
DDR_DQ36
27
DDR_DM4
36
DDR_DQ35
45
DDR_DQ38
18
DDR_DQ40
27
DDR_DQ45
36
DDR_DM5
45
DDR_DQ42
18
DDR_DQ46
27
DDR_DQ53
36
DDR_DQ52
45
DDR_DM6
18
DDR_DQ50
27
DDR_DQ51
36
DDR_DQ60
45
DDR_DQ56
18
DDR_DM7
27
DDR_DQ59
36
DDR_DQ58
45
B
C726
12
+2.5V+SDREF
0.1U_0402_10V6K
DDR_CLK38
DDR_CLK3#8
DDR_SCKE38 DDR_SCKE2 8
DDR_BS013
DDR_WE#13
DDR_SCS#28 DDR_SCS#3 8
DDR_SCS#2 DDR_SCS#3
DDR_SMAA1513
Layout note
Place these resistor
closely DIMM1,
all trace
length<=800mil
SMDATA13,16,27
SMCLK13 ,16,27
DDR_DQ7
DDR_DQ5
DDR_DQS0
DDR_DQ1
DDR_DQ3
DDR_DQ8
DDR_DQ9
DDR_DQS1
DDR_DQ11
DDR_DQ10
DDR_DQ20
DDR_DQ21
DDR_DQS2
DDR_DQ18
DDR_DQ28
DDR_DQ26
DDR_DQS3
DDR_DQ27
DDR_DQ31
R596
DDR_CKE3DDR_SCKE3 DDR_SCKE2
1 2
DDR_SMAA12
10_0402_5%
DDR_SMAA9
DDR_SMAA7
DDR_SMAA5
DDR_SMAA3
DDR_SMAA1
DDR_SMAA10
DDR_BS0 DDR_RAS#
DDR_CS#2
R598
1 2
DDR_SMAA15
10_0402_5%
DDR_DQ32
DDR_DQ34
DDR_DQS4
DDR_DQ39
DDR_DQ37
DDR_DQ41
DDR_DQ44
DDR_DQS5
DDR_DQ47
DDR_DQ43
DDR_DQ48
DDR_DQ49
DDR_DQS6
DDR_DQ54
DDR_DQ55
DDR_DQ61
DDR_DQ63
DDR_DQS7
DDR_DQ62
DDR_DQ57 DDR_DQ58
+3VS
C
+2.5V
JP20
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VDD
11
DQS0
13
DQ2
15
VSS
17
DQ3
19
DQ8
21
VDD
23
DQ9
25
DQS1
27
VSS
29
DQ10
31
DQ11
33
VDD
35
CK0
37
CK0#
39
VSS
41
DQ16
43
DQ17
45
VDD
47
DQS2
49
DQ18
51
VSS
53
DQ19
55
DQ24
57
VDD
59
DQ25
61
DQS3
63
VSS
65
DQ26
67
DQ27
69
VDD
71
CB0
73
CB1
75
VSS
77
DQS8
79
CB2
81
VDD
83
CB3
85
DU
87
VSS
89
CK2
91
CK2#
93
VDD
95
CKE1
97
DU/A13
99
A12
101
A9
103
VSS
105
A7
107
A5
109
A3
111
A1
113
VDD
115
A10/AP
117
BA0
119
WE#
121
S0#
123
DU
125
VSS
127
DQ32
129
DQ33
131
VDD
133
DQS4
135
DQ34
137
VSS
139
DQ35
141
DQ40
143
VDD
145
DQ41
147
DQS5
149
VSS
151
DQ42
153
DQ43
155
VDD
157
VDD
159
VSS
161
VSS
163
DQ48
165
DQ49
167
VDD
169
DQS6
171
DQ50
173
VSS
175
DQ51
177
DQ56
179
VDD
181
DQ57
183
DQS7
185
VSS
187
DQ58
189
DQ59
191
VDD
193
SDA
195
SCL
197
VDD_SPD
199
VDD_ID
DDR-SODIMM_200_STD_H4.0
VREF
DU/RESET#
CKE0
DU/BA2
RAS#
CAS#
+2.5V
2
4
VSS
6
DQ4
8
DQ5
10
VDD
12
DM0
14
DQ6
16
VSS
18
DQ7
20
DQ12
22
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
VSS
VSS
VDD
VDD
A11
A8
VSS
A6
A4
A2
A0
VDD
BA1
S1#
DU
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
CK1#
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
DU
DDR_DQ13
24
26
28
DDR_DQ15
30
DDR_DQ14
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
DDR_DQ29
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
DDR_CKE2
96
98
DDR_SMAA11
100
DDR_SMAA8
102
104
DDR_SMAA6
106
DDR_SMAA4
108
DDR_SMAA2
110
DDR_SMAA0
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DDR_DQ6
DDR_DQ0
DDR_DM0
DDR_DQ4
DDR_DQ2
DDR_DQ12
DDR_DM1
DDR_DQ16
DDR_DQ17
DDR_DM2
DDR_DQ22DDR_DQ23
DDR_DQ19
DDR_DQ24
DDR_DQ25
DDR_DM3
DDR_DQ30
1 2
DDR_BS1
DDR_CAS#DDR_WE#
DDR_CS#3
1 2
R599 10_0402_5%
DDR_DQ33
DDR_DQ36
DDR_DM4
DDR_DQ35
DDR_DQ38
DDR_DQ40
DDR_DQ45
DDR_DM5
DDR_DQ42
DDR_DQ46
DDR_DQ53
DDR_DQ52
DDR_DM6
DDR_DQ50
DDR_DQ51
DDR_DQ60
DDR_DQ56
DDR_DM7
DDR_DQ59
+3VS
R597
D
1
C672
0.1U_0402_10V6K
2
10_0402_5%
DDR_SCS#18,13
DDR_SCS#08,13
DDR_SCKE08,13
DDR_SCKE18,13
DDR_CLK4# 8
DDR_CLK4 8
+SDREF
DDR_BS1 13
DDR_RAS# 13
DDR_CAS# 13
DDR_SMAA9
DDR_SMAA7
DDR_SMAA5
DDR_SMAA3
33_0804_8P4R_5%
DDR_SMAA1
DDR_SMAA10
DDR_BS0
DDR_WE#
33_0804_8P4R_5%
DDR_SCS#2
DDR_SMAA15
33_0804_8P4R_5%
DDR_SCKE3
DDR_SMAA12
33_0804_8P4R_5%
DDR_DQS[0..7]
DDR_DQ[0..63]
DDR_DM[0..7]
DDR_SMAA[0..12]
DDR TOPOLOGY 1 FOR SMAA[0, 3, 6:12], SBA[1, 0], SRAS#, SCAS#, SWE#
THIS SHEET OF ENGINEERIN G DRAWI NG IS T HE PROPR IETARY PR OPERTY O F CO MPAL ELECT RONI CS, INC. AND CONTAINS C ONFIDENTIAL
AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSF ERED FR OM TH E CUSTO DY OF THE COMPET ENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY CO MPAL ELECTR ONIC S, INC. N EITHER T HIS SHEET NOR THE INFORMATI ON IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WIT HOUT PRIO R WRITT EN CO NSENT O F COMPAL ELECTRONICS , INC.
C
D
Title
Size Doc u m ent Number Re v
Date: Sheet of
RP24
18
27
36
45
RP23
18
27
36
45
RP20
18
27
36
45
RP25
18
27
36
45
Compal Electronics, Inc.
DDR-SODIMM SLOT1
LA-2051
E
+1.25VS
RP62
18
27
36
45
33_0804_8P4R_5%
RP61
18
27
36
45
33_0804_8P4R_5%
RP60
18
27
36
45
33_0804_8P4R_5%
DDR_ DQS[0..7 ] 8,13
DDR_ DQ[0..63 ] 8,13
DDR_D M[0..7] 8,13
DDR_SMAA[0..12] 13
Layout note
Place these resistor
close by DIMM1,
all trace length
Max=0.8"
E
DDR_SCKE2
DDR_SMAA11
DDR_SMAA8
DDR_SMAA6
DDR_SMAA4
DDR_SMAA2
DDR_SMAA0
DDR_BS1
DDR_RAS#
DDR_CAS#
DDR_SCS#3
14 51Friday, November 14, 2003
1.0
A
Layout note :
Distribute as close as possible
to DDR-SODIMM0.
+2.5V
1
1 1
+
2
C686
220U_D2_4VM
1
2
C289
0.1U_0402_10V6K
1
C146
0.1U_0402_10V6K
2
1
C291
0.1U_0402_10V6K
2
1
2
C122
0.1U_0402_10V6K
B
1
C246
0.1U_0402_10V6K
2
1
C170
0.1U_0402_10V6K
2
1
C191
0.1U_0402_10V6K
2
1
C150
0.1U_0402_10V6K
2
C
Layout note :
Distribute as close as possible
to DDR-SODIMM1.
+2.5V
1
+
C92
220U_D2_4VM
2
1
C139
0.1U_0402_10V6K
2
1
C151
0.1U_0402_10V6K
2
D
1
C274
0.1U_0402_10V6K
2
1
C111
0.1U_0402_10V6K
2
1
C165
0.1U_0402_10V6K
2
1
C245
0.1U_0402_10V6K
2
E
1
C171
0.1U_0402_10V6K
2
1
C292
0.1U_0402_10V6K
2
1
2
1
+
2
2 2
+1.25VS
1
2
+1.25VS
1
2
+1.25VS
1
2
3 3
+1.25VS
1
2
+1.25VS
1
2
+1.25VS
4 4
1
2
1
C227
0.1U_0402_10V6K
2
1
C322
+
220U_D2_4VM
2
Layout note :
Place one cap close to every 2 pull up resistors termination to
+1.25VS
1
C283
0.1U_0402_10V6K
2
1
C425
0.1U_0402_10V6K
2
1
C197
0.1U_0402_10V6K
2
1
C208
0.1U_0402_10V6K
2
1
C294
0.1U_0402_10V6K
2
1
C428
0.1U_0402_10V6K
2
C184
0.1U_0402_10V6K
C93
220U_D2_4VM
C426
0.1U_0402_10V6K
C671
0.1U_0402_10V6K
C662
0.1U_0402_10V6K
C169
0.1U_0402_10V6K
C244
0.1U_0402_10V6K
C225
0.1U_0402_10V6K
A
1
C136
0.1U_0402_10V6K
2
1
C228
0.1U_0402_10V6K
2
1
C606
0.1U_0402_10V6K
2
1
C276
0.1U_0402_10V6K
2
1
C177
0.1U_0402_10V6K
2
1
C183
0.1U_0402_10V6K
2
1
C535
0.1U_0402_10V6K
2
1
C248
0.1U_0402_10V6K
2
1
C255
0.1U_0402_10V6K
2
1
C456
0.1U_0402_10V6K
2
1
C149
0.1U_0402_10V6K
2
1
C220
0.1U_0402_10V6K
2
1
C187
0.1U_0402_10V6K
2
1
C194
0.1U_0402_10V6K
2
1
C174
0.1U_0402_10V6K
2
1
C263
0.1U_0402_10V6K
2
1
C287
0.1U_0402_10V6K
2
1
C209
0.1U_0402_10V6K
2
1
C249
0.1U_0402_10V6K
2
1
C126
0.1U_0402_10V6K
2
1
C497
0.1U_0402_10V6K
2
1
C266
0.1U_0402_10V6K
2
1
C132
0.1U_0402_10V6K
2
1
C474
0.1U_0402_10V6K
2
1
C424
0.1U_0402_10V6K
2
1
C440
0.1U_0402_10V6K
2
1
C427
0.1U_0402_10V6K
2
1
C528
0.1U_0402_10V6K
2
B
1
C106
0.1U_0402_10V6K
2
1
C156
0.1U_0402_10V6K
2
1
C483
0.1U_0402_10V6K
2
1
C616
0.1U_0402_10V6K
2
1
C120
0.1U_0402_10V6K
2
1
C258
0.1U_0402_10V6K
2
1
C625
0.1U_0402_10V6K
2
1
C635
0.1U_0402_10V6K
2
1
C219
0.1U_0402_10V6K
2
1
C270
0.1U_0402_10V6K
2
1
C265
0.1U_0402_10V6K
2
1
C281
0.1U_0402_10V6K
2
1
C449
0.1U_0402_10V6K
2
1
C664
0.1U_0402_10V6K
2
1
C115
0.1U_0402_10V6K
2
THIS SHEET OF ENGINEERIN G DRAWI NG IS T HE PROPR IETARY PR OPERTY O F CO MPAL ELECT RONI CS, INC. AND CONTAINS C ONFIDENTIAL
AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSF ERED FR OM TH E CUSTO DY OF THE COMPET ENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY CO MPAL ELECTR ONIC S, INC. N EITHER T HIS SHEET NOR THE INFORMATI ON IT CONTAINS
MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WIT HOUT PRIO R WRITT EN CO NSENT O F COMPAL ELECTRONICS , INC.
1
2
1
2
1
2
1
2
C
1
2
C434
0.1U_0402_10V6K
C510
0.1U_0402_10V6K
C642
0.1U_0402_10V6K
C439
0.1U_0402_10V6K
C113
0.1U_0402_10V6K
Layout note :
for EM I solution
1000P_0402_50V7K
1
C277
0.1U_0402_10V6K
2
+2.5V
1
C714
2
1
C247
0.1U_0402_10V6K
2
1
C715
2
1000P_0402_50V7K
1000P_0402_50V7K
1
C716
2
1000P_0402_50V7K
1
C137
0.1U_0402_10V6K
2
C717
D
1
2
1
C226
0.1U_0402_10V6K
2
1000P_0402_50V7K
1
C718
2
1000P_0402_50V7K
1
2
C719
Title
Size Doc u m ent Number Re v
Date: Sheet of
C185
0.1U_0402_10V6K
1000P_0402_50V7K
1
C720
2
LA-2051
1
C261
0.1U_0402_10V6K
2
1000P_0402_50V7K
1
1
C721
2
1000P_0402_50V7K
C722
2
Compal Electronics, Inc.
DDR SODIMM Decoupling
1
2
C290
0.1U_0402_10V6K
1
2
E
1
2
15 51Friday, November 14, 2003
C176
0.1U_0402_10V6K
1.0
A
1 1
PM_STPCPU#5,10, 26,47
2 2
PCI_STP#26
B
EXCLK_CLKGEN38
R577
10K_0402_5%
R579 @0_0402_5%
1 2
1 2
R580 @0_0402_5%
CLK_SB_48M27
CLK_A UDIO_14M32
REFCLK1_NB10
CLK_SIO_14M34
CLK_SB_14M27
CLK_1 4M_APIC26
C
+3VS
R146 @10_0402_5%
1 2
C116 10P_0402_50V8K
+3VS
12
12
R578
10K_0402_5%
R109 33_0402_5%
1 2
R159 @33_0402_5%
1 2
R161 68_0402_5%
1 2
R165 33_0402_5%
1 2
R174 33_0402_5%
1 2
R173 @33_0402_5%
1 2
1 2
12
1 2
C112
14.31818MHZ_20P_6X1430004201
10P_0402_50V8K
SMCLK13 ,14,27
SMDATA13,14,27
VTT_PWRGD17,27
XTALIN_CLK
Y2
XTALOUT_CLK
12
VTT_PWRGD
PCI33/66#
CLK_48M
FS2
FS1
FS0
CLK_IREF
R144
475_0402_1%
1 2
R150
@1M_0402_5%
D
L7
1 2
HB-1M2012-121JT03_0805
U16
6
XIN
7
XOUT
35
SCLK
34
SDATA
10
VTTPWRGD/PD#
45
CPU_STP#
12
PCI_STOP#
26
24/48#SEL
11
PCI33/66#SEL
27
48MHz_1
28
48MHz_0
4
FS2/REF2
3
FS1/REF1
2
FS0/REF0
38
IREF
+3V_CLK
Width=40 mils
48
29
42
30
VDDSD
VDD48M
VDDCPU
VDDAGP
GNDREF5GNDXTAL
GNDPCI
GNDPCI
8
18
24
1
C145
2
10U_0805_10V4Z
+3VS_VDDA
13
19
1
9
VDDPCI
VDDPCI
VDDREF
VDDXTAL
SDRAMOUT
FS3/PCICLK_F0
FS4/PCICLK_F1
GNDSD
GNDCPU
GND48M
GNDAGP
ICS951402AGT_TSSOP48
46
41
25
33
0.1U_0402_10V6K
1
C141
2
0.1U_0402_10V6K
VDDA
VSSA
CPUT0
CPUC0
CPUT1
CPUC1
AGPCLK0
AGPCLK1
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
E
0.1U_0402_10V6K
1
C118
2
36
C104
0.1U_0402_10V6K
VSSA
37
CLK_BCLK
40
CLK_BCLK#
39
CLK_NB
44
CLK_NB#
43
MEM_66M
47
AGP_66M
32
31
FS3
14
FS4
15
16
17
20
21
22
23
1
C95
2
0.1U_0402_10V6K
+3VS_VDDA
1
1
C99
2
2
10U_0 805_10V4Z
R148 33_0402_5%
R142 33_0402_5%
R164 33_0402_5%
R156 33_0402_5%
R168 33_0402_5%
R125 33_0402_5%
R115 33_0402_5%
C105
C90
0.1U_0402_10V6K
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1
C89
2
0.1U_0402_10V6K
0.1U_0402_10V6K
1
C138
2
R147 49.9_0402_1%
R139 49.9_0402_1%
R163 49.9_0402_1%
R155 49.9_0402_1%
F
CLK_BCLK
CLK_BCLK#
1
2
1
2
1 2
1 2
1 2
1 2
R158 @0_0402_5%
1 2
R152 @0_0402_5%
1 2
L4
1 2
CHB20 12U121_0805
1
C110
0.1U_0402_10V6K
2
CLK_N B_BCLK 10
CLK_N B_BCLK# 10
CLK_MEM_66M 10
CLK_AGP_66M 10
CLK_A LINK_SB 26
+3VS
CLK_C PU_BCLK 4
CLK_C PU_BCLK# 4
G
CLK_C PU_ITP 5
CLK_C PU_ITP# 5
H
3 3
CLOCK FREQUENCY SELECT TABLE
FS2 MEMFS1
FS3
0 0 0 1 0
0 0 0 0 1
**
0 0 0 0 0
Note: 0 = PULL LOW
4 4
A-LINK FREQ
PCI33/66# = HIGH
**
PCI33/66# = LOW 33MHZ
A
1 = PULL HIGH
FS0
CPUFS4 With Spread Enabled…
200
200
133
100 100
*
133
10K_0402_5%
BSEL15,12
BSEL05,12
66MHZ
B
Spreaf OFF OR
Center spr ead +/-0.3%
+3VS +3VS
12
12
R167
R172
10K_0402_5%
D20 RB 751V_SOD323
D21 RB 751V_SOD323
C
+3V_CLK
12
R120
@10K_0402_5%
12
R123
10K_0402_5%
12
R127
10K_0402_5%
12
R133
@10K_0402_5%
Title
Size Doc u m ent Number Re v
Date: Sheet of
Compa l Electronics, Inc.
Clock Generator
LA-2051
G
16 51Friday, November 14, 2003
H
1.0
12
12
FS1
FS0
FS2
+3V_CLK
FS3
FS4
PCI33/66#
12
12
R169
10K_0402_5%
21
21
D
12
R171
10K_0402_5%
R166
4.7K_0402_5%
THIS SHEET OF ENGINEERIN G DRAWI NG IS T HE PROPR IETARY PR OPERTY O F CO MPAL ELECT RONI CS, INC. AND CONTAINS C ONFIDENTIAL
AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSF ERED FR OM TH E CUSTO DY OF THE COMPET ENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZ ED BY CO MPAL ELECTR ONIC S, INC. N EITHER T HIS SHEET NOR THE INFORMATI ON IT CONTAINS
MAY BE USED BY OR DISCLOSED TO AN Y THIRD PARTY WIT HOUT PRIO R WRITT EN CO NSENT O F COMPAL ELECTRONICS , INC.
12
R170
4.7K_0402_5%
E
12
R160
@10K_0402_5%
R153
10K_0402_5%
R124
@10K_0402_5%
12
R121
10K_0402_5%
F
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