Quanta Computer LA-5831P, Satellite L450D Schematic

A

1 1

B

C

D

E

Compal confidential

2 2

Low Cost Los Angeles 10AL+

NBWAE LA-5831P Schematics Document

Mobile AMD S1G2 RS780MN & RS780MC / SB700

3 3

2009-08-12 Rev. 1.0

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009-02-12 2009-02-12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Sheet

LA-5831P

1 44Wednesday, August 12, 2009

E

1.0

A

B

C

D

E

Compal Confidential

Fan Control

Model Name : NBWAE

page 5

File Name : LA-5831P

1 1

CRT

page 17

AMD S1G2 CPU

uFCPGA-638 Package

page 5,6,7.8

Hyper Transport Link 2.6GHz

16X16

ATI

Memory BUS(DDRII)

Dual Channel

1.8V DDRII 667/800MHZ

RS780MN

LCD Conn.

page 18

RS780MC

PCIe 4x

1.5V 2.5GHz(250MB/s)

Thermal Sensor

ADM1032ARMZ

page 7

200pin DDRII-SO-DIMM X2

BANK 0, 1, 2, 3

RTL8103E LAN 10/100M

PCIe port 3

page 26

Clock Generator

SLG8SP626

page 16

page 9,10

RJ45

page 26

PCIe Mini Card WLAN

HDMI Conn.

page 19

2 2

PCIE-Express 4X

page 11,12,13,14.15

A-Link Express II 4X PCI-E

USB

5V 480MHz

ATI

PCIe Port 2

USB Port 8

page 27

USB/B Right

USB port 0,1

page 25

3IN1 Card Reader RTS5159-VDD

USB port 4

page 28

USB/B Left

USB port 2

page 25

Int. Camera

USB port 9

page 18

SB700

page 20,21,22,23,24

3 3

LPC BUS

3.3V 33 MHz

Debug Port

page 31

ENE KB926D3

page 32

HD Audio

MDC 1.5 Conn

SATA port 1

5V 1.5GHz(150MB/s)

SATA port 3

5V 1.5GHz(150MB/s)

3.3V 24.576MHz/48Mhz

SATA HDD

SATA ODD

page 25

HDA Codec

page 31 page 29

ALC272

RTC CKT.

page 20

Power On/Off CKT.

page 33

DC/DC Interface CKT.

4 4

page 34

NBWAE Sub-boards

Power/B LS-4574P

page 33

Cap Sensor/B LS-5822P

page 33

Touch Pad

page 33

Int.KBD

page 31

SPI ROM

page 31

RJ11

page 31

MIC Conn

page 30

Int. MIC Conn

page 30

HP Conn

page 30

AMP. TPA6017

page 30

SPK Conn

page 30

USB/B

Power Circuit DC/DC

page 35,36,37,38 39,40,41.42

A

LS-5821P

page 25

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009-02-12 2009-02-12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

LA-5831P

2 44Wednesday, August 12, 2009

E

1.0

5

4

3

2

1

B+

DESIGN CURRENT 100mA DESIGN CURRENT 100mA

Ipeak=5A, Imax=3.5A, Iocp min=7.9

+3VL +5VL +5VALW

SUSP#

N-CHANNEL

D D

SI4800BDY

Ipeak=5A, Imax=3.5A, Iocp min=7.7

DESIGN CURRENT 5A

+5VS

+3VALW

SUSP#

TPS51125RGER

N-CHANNEL SI4800BDY

DESIGN CURRENT 5A

UMA_ENVDD

P-CHANNEL

AO-3413

DESIGN CURRENT 1.0A

+3VS

+LCD_VDD

SUSP

LDO

APL5331KAC

DESIGN CURRENT 2A

+1.5VS

WOL_EN#

P-CHANNEL

C C

AO-3413

LDO

APL5508

DESIGN CURRENT 330mA

DESIGN CURRENT 500mA

+3V_LAN

+2.5VS

POK

TPS51124RGER

Ipeak=5A, Imax=3.5A, Iocp min=7.78

N-CHANNEL IRF8113PBF

Ipeak=7A, Imax=4.9A, Iocp min=9.32

VLDT_EN

DESIGN CURRENT 4.5A

+1.2VALW

+1.2V_HT

+NB_CORE (+1.1VS)

SUSP#

B B

CPU_VCORE_ENABLE

ISL6265

Ipeak=18A, Imax=12.6A, Iocp min=30 Ipeak=18A, Imax=12.6A, Iocp min=30

DESIGN CURRENT 4A

+CPU_CORE0 +CPU_CORE1 +VDDNB

SYSON

TPS51117RGYR

Ipeak=8A, Imax=5.6A, Iocp min=8.87

SUSP#

N-CHANNEL IRF8113PBF

DESIGN CURRENT 1A

+1.8V

+1.8VS

SYSON#

LDO

APL5331KAC

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DESIGN CURRENT 2A

3

+0.9V

Compal Secret Data

2009-02-12 2009-02-12

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Power Map

LA-5831P

3 44Wednesday, August 12, 2009

1

1.0

A

B

C

D

E

Voltage Rails

O : ON X : OFF

1 1

2 2

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

State

S0

S1

S3

S5 S4/AC

power plane

B+ +3VL +5VL

O O O O O

X

+3VALW +1.2VALW +3V_LAN+RTCVCC

O O O O

X X X X

SB700 SM Bus0 Address

HEX

A0 H

D2 H

Address

1010 0000 b 1010 0100 bA4 H 1101 0010 b

Power

+3VS

3 3

+3VS +3VS

Device

DDR SO-DIMM 0 DDR SO-DIMM 1 Clock Generator

KB926 SM Bus1 Address

Device Address Address

+3VL

HEX HEX

16 H

0001 011X bSmart Battery

+5VS +3VS +2.5VS +1.8VS +1.5VS

+1.8V+5VALW

+1.1VS

+0.9V

+1.2V_HT +VDDNB +CPU_CORE_0 +CPU_CORE_1

OO OO

O

X X X X

X

SB700 SM Bus1 Address

DevicePower

+3VALW

KB926 SM Bus2 Address

PowerPower

+3VS

WLAN/WIMAX

Device

HEX Address

98 H

1001 100X bCPU_ADM1032-1

SMBUS Control Table

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 I2C_CLK I2C_DATA DDC_CLK0 DDC_DATA0 DDC_CLK1 DDC_DATA1 SCL0 SDA0 SCL1 SDA1 SCL2 SDA2 SCL3 SDA3

Platform

PUMA@

TIGRIS@

CPU SB S1G2 S1G2 S1G3 SB710

NB

RS780MC

SB700 RS780MN SB700 RS880MC RS880MS1G3 SB710

@ : just reserve , no build

BTO (Build-To-Order) Option Table

Function

Description (Y)

Explain

BTO

SOURCE

KB926

KB926 RS780MN

RS780MC RS780MN RS780MC RS780MN RS780MC

SB700

Modem

( R )

MDC@

BATTINVERTER

HDMI

HDMI@

V

CAMERA & MIC

(X)

CAMERA MIC

CAM@ MIC@

CPU

HDMI

THERMAL

CEC

SENSOR

SODIMM

I / II

V

CLK GEN

LCD DDC ROM

HDMI DDC ROM

NEW CARD

WLAN

V

VV

V

KB926 ESB Address

4 4

+3VL Cap. Sensor Virtual I2C

A

HEXDevice AddressPower

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009-02-12 2009-02-12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Notes List

LA-5831P

4 44Wednesday, August 12, 2009

E

1.0

A

B

C

D

E

+1.2V_HT

Near CPU SocketVLDT CAP.

250 mil

H_CADIP[0..15] H_CADIN[0..15]

H_CADIP0 H_CADIN0 H_CADIP1 H_CADIN1 H_CADIP2 H_CADIN2 H_CADIP3 H_CADIN3 H_CADIP4 H_CADIN4 H_CADIP5 H_CADIN5 H_CADIP6 H_CADIN6 H_CADIP7 H_CADIN7 H_CADIP8 H_CADIN8 H_CADIP9 H_CADIN9 H_CADIP10 H_CADIN10 H_CADIP11 H_CADIN11 H_CADIP12 H_CADIN12 H_CADIP13 H_CADIN13 H_CADIP14 H_CADIN14 H_CADIP15 H_CADIN15

1

PUMA@

C2

4.7U_0805_10V4Z

2

+1.2V_HT

D1 D2 D3 D4

E3 E2 E1

F1 G3 G2 G1 H1

J1 K1 L3 L2 L1

M1 N3 N2

E5 F5 F3 F4

G5 H5 H3 H4

K3 K4 L5

M5 M3 M4 N5

P5

J3

J2

J5 K5

N1

P1 P3 P4

VLDT_A0 VLDT_A1 VLDT_A2 VLDT_A3

L0_CADIN_H0 L0_CADIN_L0 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H2 L0_CADIN_L2 L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H4 L0_CADIN_L4 L0_CADIN_H5 L0_CADIN_L5 L0_CADIN_H6 L0_CADIN_L6 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H15 L0_CADIN_L15

L0_CLKIN_H0 L0_CLKIN_L0 L0_CLKIN_H1 L0_CLKIN_L1

L0_CTLIN_H0 L0_CTLIN_L0 L0_CTLIN_H1 L0_CTLIN_L1

6090022100G_B

TIGRIS@

C2

C2 10U_0805_10V6K

10U_0805_10V6K

JCPUA

HT LINK

L0_CADOUT_H0

L0_CADOUT_L0

L0_CADOUT_H1

L0_CADOUT_L1

L0_CADOUT_H2

L0_CADOUT_L2

L0_CADOUT_H3

L0_CADOUT_L3

L0_CADOUT_H4

L0_CADOUT_L4

L0_CADOUT_H5

L0_CADOUT_L5

L0_CADOUT_H6

L0_CADOUT_L6

L0_CADOUT_H7

L0_CADOUT_L7

L0_CADOUT_H8

L0_CADOUT_L8

L0_CADOUT_H9

L0_CADOUT_L9

L0_CADOUT_H10

L0_CADOUT_L10

L0_CADOUT_H11

L0_CADOUT_L11

L0_CADOUT_H12

L0_CADOUT_L12

L0_CADOUT_H13

L0_CADOUT_L13

L0_CADOUT_H14

L0_CADOUT_L14

L0_CADOUT_H15

L0_CADOUT_L15

L0_CLKOUT_H0

L0_CLKOUT_L0

L0_CLKOUT_H1

L0_CLKOUT_L1

L0_CTLOUT_H0

L0_CTLOUT_L0

L0_CTLOUT_H1

L0_CTLOUT_L1

1

PUMA@

C1

4.7U_0805_10V4Z

1 1

2

H_CADIP[0..15]<11>

TIGRIS@

C1

C1 10U_0805_10V6K

10U_0805_10V6K

VLDT=500mA

2 2

H_CLKIP0<11> H_CLKIN0<11> H_CLKIP1<11> H_CLKIN1<11>

H_CTLIP0<11>

3 3

H_CTLIN0<11> H_CTLIP1<11> H_CTLIN1<11>

VLDT_B0 VLDT_B1 VLDT_B2 VLDT_B3

@

1

C3

0.22U_0603_16V4Z

2

H_CADOP[0..15] H_CADON[0..15]

+VLDT_B

AE2 AE3 AE4 AE5

AD1 AC1 AC2 AC3 AB1 AA1 AA2 AA3 W2 W3 V1 U1 U2 U3 T1 R1 AD4 AD3 AD5 AC5 AB4 AB3 AB5 AA5 Y5 W5 V4 V3 V5 U5 T4 T3

Y1 W1 Y4 Y3

R2 R3 T5 R5

H_CADOP0 H_CADON0 H_CADOP1 H_CADON1 H_CADOP2 H_CADON2 H_CADOP3 H_CADON3 H_CADOP4 H_CADON4 H_CADOP5 H_CADON5 H_CADOP6 H_CADON6 H_CADOP7 H_CADON7 H_CADOP8 H_CADON8 H_CADOP9 H_CADON9 H_CADOP10 H_CADON10 H_CADOP11 H_CADON11 H_CADOP12 H_CADON12 H_CADOP13 H_CADON13 H_CADOP14 H_CADON14 H_CADOP15 H_CADON15

1

C4

0.22U_0603_16V4Z

2

H_CADOP[0..15] <11> H_CADON[0..15] <11>H_CADIN[0..15]<11>

< To NB >< From NB >

H_CLKOP0 <11> H_CLKON0 <11> H_CLKOP1 <11> H_CLKON1 <11>

H_CTLOP0 <11> H_CTLON0 <11> H_CTLOP1 <11> H_CTLON1 <11>

1 2

PUMA@

C7

4.7U_0805_10V4Z

TIGRIS@

C7

C7 10U_0805_10V6K

10U_0805_10V6K

1

C5

C5 180P_0402_50V8J

180P_0402_50V8J

2

1

C6

C6 180P_0402_50V8J

180P_0402_50V8J

2

< VLDT_A & VLDT_B : HyperTransport I/O ring power >

< FAN Control Circuit : Vout = 1.6 x Vset >

+5VS

1A

12

D1

@

GND GND GND GND

C183

2

1

8 7 6 5

12

@

1SS355_SOD323-2

D2

D2 BAS16_SOT23-3

BAS16_SOT23-3

JFAN

@JFAN

+FAN1

2

C9

@

1000P_0402_25V8J

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009-02-12 2009-02-12

@

1

2

3

4

GND

5

GND

ACES_85204-0300N

+3VS

12

R12

R12 10K_0402_5%

10K_0402_5%

2

C8

@

0.01U_0402_25V7K

1

Compal Secret Data

Deciphered Date

FAN_SPEED1 <32>

D

< To EC >

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

AMD CPU S1G3 HT I/F

LA-5831P

5 44Wednesday, August 12, 2009

E

1.0

+FAN1

1

C192

C192 10U_0805_10V4Z

10U_0805_10V4Z

2

< From EC >

4 4

EN_DFAN1<32>

A

10U_0805_10V4Z

U6

1

EN

2

VIN

3

VOUT

4

VSET

APL5607KI-TRG_SO8

B

A

B

C

D

E

< Processor DDR2 Memory Interface >

JCPUC

< DDR2 VREF is 0.5 ratio >

+1.8V

R1

R1 1K_0402_1%

1 1

2 2

3 3

1K_0402_1%

1 2

R2

R2 1K_0402_1%

1K_0402_1%

1 2

< To SO_DIMMA >

+MCH_REF

1

C12

0.1U_0402_16V7K

2

1

C13

C13 1000P_0402_25V8J

1000P_0402_25V8J

2

Place them close to CPU within 1"

R4 39.2_0402_1%R4 39.2_0402_1%

1 2

R3 39.2_0402_1%R3 39.2_0402_1%

+1.8V

1 2

T2 PADT2 PAD

DDR_A_ODT0<10> DDR_A_ODT1<10>

DDR_CS0_DIMMA#<10> DDR_CS1_DIMMA#<10> DDR_CS0_DIMMB# <9>

DDR_CKE0_DIMMA<10> DDR_CKE1_DIMMA<10>

DDR_A_CLK0<10> DDR_A_CLK#0<10> DDR_A_CLK1<10> DDR_A_CLK#1<10>

DDR_A_MA[15..0]<10>

DDR_A_BS#0<10> DDR_A_BS#1<10> DDR_A_BS#2<10>

DDR_A_RAS#<10> DDR_A_CAS#<10> DDR_A_WE#<10>

DDR_A_ODT0 DDR_A_ODT1

DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS0_DIMMB#

DDR_CKE0_DIMMA DDR_CKE1_DIMMA

DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

DDR_A_BS#0 DDR_A_BS#1 DDR_A_BS#2

DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

< PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH >

VTT5 VTT6 VTT7 VTT8 VTT9

VTT_SENSE

MEMVREF

RSVD_M2

MB0_ODT0 MB0_ODT1 MB1_ODT0

MB0_CS_L0 MB0_CS_L1 MB1_CS_L0

MB_CKE0 MB_CKE1

MB_CLK_H0

MB_CLK_L0

MB_CLK_H1

MB_CLK_L1

MB_CLK_H2

MB_CLK_L2

MB_CLK_H3

MB_CLK_L3

MB_ADD0 MB_ADD1 MB_ADD2 MB_ADD3 MB_ADD4 MB_ADD5 MB_ADD6 MB_ADD7 MB_ADD8

MB_ADD9 MB_ADD10 MB_ADD11 MB_ADD12 MB_ADD13 MB_ADD14 MB_ADD15

MB_BANK0 MB_BANK1 MB_BANK2

MB_RAS_L MB_CAS_L

MB_WE_L

DDR_B_CLK0

DDR_B_CLK#0

DDR_B_CLK1

DDR_B_CLK#1

W10 AC10 AB10 AA10 A10

Y10 W17 B18 W26

W23 Y26

V26 W25 U22

J25 H26

P22 R22 A17 A18 AF18 AF17 R26 R25

P24 N24 P26 N23 N26 L23 N25 L24 M26 K26 T26 L26 L25 W24 J23 J24

R24 U26 J26

U25 U24 U23

@

1

C14

1.5P_0402_50V9C

2

1

C15

1.5P_0402_50V9C

2

+0.9V+0.9V

+MCH_REF

DDR_B_ODT0 DDR_B_ODT1

DDR_CS1_DIMMB#

DDR_CKE0_DIMMB DDR_CKE1_DIMMB

DDR_B_CLK0 DDR_B_CLK#0 DDR_B_CLK1 DDR_B_CLK#1DDR_A_CLK#1

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

DDR_B_BS#0 DDR_B_BS#1 DDR_B_BS#2

DDR_B_RAS# DDR_B_CAS# DDR_B_WE#

DDR_A_CLK0

DDR_A_CLK#0

DDR_A_CLK1

DDR_A_CLK#1

AD10

MEM_P

AF10

MEM_N VTT_SENSE

AE10

AA16

M20 M19

M22 M24

D10 C10 B10

H16 T19

V22 U21 V19

T20 U19 U20 V20

J22 J20

N19 N20 E16 F16 Y16

P19 P20

N21 N22

L20 L21

L19 K22 R21

L22 K20 V24 K24 K19

R20 R23

J21 R19

T22 T24

1

2

1

2

VTT1

MEM:CMD/CTRL/CLK

VTT2 VTT3 VTT4

MEMZP MEMZN

RSVD_M1 MA0_ODT0

MA0_ODT1 MA1_ODT0 MA1_ODT1

MA0_CS_L0 MA0_CS_L1 MA1_CS_L0 MA1_CS_L1

MA_CKE0 MA_CKE1

MA_CLK_H0 MA_CLK_L0 MA_CLK_H1 MA_CLK_L1 MA_CLK_H2 MA_CLK_L2 MA_CLK_H3 MA_CLK_L3

MA_ADD0 MA_ADD1 MA_ADD2 MA_ADD3 MA_ADD4 MA_ADD5 MA_ADD6 MA_ADD7 MA_ADD8 MA_ADD9 MA_ADD10 MA_ADD11 MA_ADD12 MA_ADD13 MA_ADD14 MA_ADD15

MA_BANK0 MA_BANK1 MA_BANK2

MA_RAS_L MA_CAS_L MA_WE_L

C10

1.5P_0402_50V9C

C11

1.5P_0402_50V9C

JCPUB

< VTT regulator voltage >

T1PAD T1PAD

T3PAD T3PAD

DDR_B_ODT0 <9> DDR_B_ODT1 <9>

DDR_CS1_DIMMB# <9>

DDR_CKE0_DIMMB <9> DDR_CKE1_DIMMB <9>

DDR_B_CLK0 <9> DDR_B_CLK#0 <9> DDR_B_CLK1 <9> DDR_B_CLK#1 <9>

DDR_B_MA[15..0] <9>

DDR_B_BS#0 <9> DDR_B_BS#1 <9> DDR_B_BS#2 <9>

DDR_B_RAS# <9> DDR_B_CAS# <9> DDR_B_WE# <9>

< To SO_DIMMB >

DDR_B_D[63..0]<9>

< From/To SO_DIMMB >

DDR_B_DM[7..0]<9> DDR_A_DM[7..0] <10>

< To SO_DIMMB > < To SO_DIMMA >

DDR_B_DQS0<9> DDR_B_DQS#0<9> DDR_B_DQS1<9> DDR_B_DQS#1<9> DDR_B_DQS2<9> DDR_B_DQS#2<9> DDR_B_DQS3<9> DDR_B_DQS#3<9> DDR_B_DQS4<9> DDR_B_DQS#4<9> DDR_B_DQS5<9> DDR_B_DQS#5<9> DDR_B_DQS6<9> DDR_B_DQS#6<9> DDR_B_DQS7<9> DDR_B_DQS#7<9>

< From/To SO_DIMMB > < From/To SO_DIMMA >

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

DDR_B_DQS0

DDR_B_DQS#0

DDR_B_DQS1

DDR_B_DQS#1

DDR_B_DQS2

DDR_B_DQS#2

DDR_B_DQS3

DDR_B_DQS#3

DDR_B_DQS4

DDR_B_DQS#4

DDR_B_DQS5

DDR_B_DQS#5

DDR_B_DQS6

DDR_B_DQS#6

DDR_B_DQS7

DDR_B_DQS#7

JCPUC

C11 A11 A14 B14 G11 E11 D12 A13 A15 A16 A19 A20 C14 D14 C18 D18 D20 A21 D24 C25 B20 C20 B24 C24 E23 E24 G25 G26 C26 D26 G23

G24 AA24 AA23 AD24 AE24 AA26 AA25 AD26 AE25 AC22 AD22 AE20 AF20 AF24 AF23 AC20 AD20 AD18 AE18 AC14 AD14 AF19 AC18 AF16 AF15 AF13 AC12 AB11

Y11 AE14 AF14 AF11 AD11

A12

B16

A22

E25 AB26 AE22 AC16 AD12

C12

B12

D16

C16

A24

A23

F26

E26 AC25 AC26 AF21 AF22 AE16 AD16 AF12 AE12

6090022100G_B @

MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7 MB_DATA8 MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15 MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23 MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31 MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39 MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47 MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55 MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63

MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7

MB_DQS_H0 MB_DQS_L0 MB_DQS_H1 MB_DQS_L1 MB_DQS_H2 MB_DQS_L2 MB_DQS_H3 MB_DQS_L3 MB_DQS_H4 MB_DQS_L4 MB_DQS_H5 MB_DQS_L5 MB_DQS_H6 MB_DQS_L6 MB_DQS_H7 MB_DQS_L7

MEM:DATA

MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7 MA_DATA8

MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15 MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23 MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31 MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39 MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47 MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55 MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63

MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7

MA_DQS_H0

MA_DQS_L0

MA_DQS_H1

MA_DQS_L1

MA_DQS_H2

MA_DQS_L2

MA_DQS_H3

MA_DQS_L3

MA_DQS_H4

MA_DQS_L4

MA_DQS_H5

MA_DQS_L5

MA_DQS_H6

MA_DQS_L6

MA_DQS_H7

MA_DQS_L7

G12 F12 H14 G14 H11 H12 C13 E13 H15 E15 E17 H17 E14 F14 C17 G17 G18 C19 D22 E20 E18 F18 B22 C23 F20 F22 H24 J19 E21 E22 H20 H22 Y24 AB24 AB22 AA21 W22 W21 Y22 AA22 Y20 AA20 AA18 AB18 AB21 AD21 AD19 Y18 AD17 W16 W14 Y14 Y17 AB17 AB15 AD15 AB13 AD13 Y12 W11 AB14 AA14 AB12 AA12

E12 C15 E19 F24 AC24 Y19 AB16 Y13

G13 H13 G16 G15 C22 C21 G22 G21 AD23 AC23 AB19 AB20 Y15 W15 W12 W13

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9

DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS7 DDR_A_DQS#7

DDR_A_D[63..0] <10>

< From/To SO_DIMMA >

DDR_A_DQS0 <10> DDR_A_DQS#0 <10> DDR_A_DQS1 <10> DDR_A_DQS#1 <10> DDR_A_DQS2 <10> DDR_A_DQS#2 <10> DDR_A_DQS3 <10> DDR_A_DQS#3 <10> DDR_A_DQS4 <10> DDR_A_DQS#4 <10> DDR_A_DQS5 <10> DDR_A_DQS#5 <10> DDR_A_DQS6 <10> DDR_A_DQS#6 <10> DDR_A_DQS7 <10> DDR_A_DQS#7 <10>

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009-02-12 2009-02-12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

AMD CPU S1G3 DDRII I/F

LA-5831P

6 44Wednesday, August 12, 2009

E

1.0

A

+CPU_CORE_0

+CPU_CORE_1

1 1

< 200-MHz PLL Reference Clock >

CLK_CPU_BCLK<16>

CLK_CPU_BCLK#<16>

< Close to CPU >

R487

R487 10_0402_5%

1 2

10_0402_5% R486

R486 10_0402_5%

10_0402_5%

R489

R489 10_0402_5%PUMA@

10_0402_5%PUMA@ R488

R488 10_0402_5%PUMA@

10_0402_5%PUMA@

C20

C20 3900P_0402_50V7K

3900P_0402_50V7K

C21

C21 3900P_0402_50V7K

3900P_0402_50V7K

1 2

Un-Mount R488 & R489 For Caspian

1 2

CPU_VDD0_RUN_FB_H

CPU_VDD0_RUN_FB_L

CPU_VDD1_RUN_FB_H

CPU_VDD1_RUN_FB_L

12

R8

R8 169_0402_1%

169_0402_1%

Address:100_1100 Place close to CPU wihtin 1.5"

CPU_CLKIN_SC_P

CPU_CLKIN_SC_N

< Filtered PLL Supply Voltage >

L1 FBM_L11_201209_300L_0805L1 FBM_L11_201209_300L_0805

1

2 2

+

C16

@

100U_D2_10VM

2

< Serial VID Interface clock & data >

+1.8VS

LDT_RST#<20>

3 3

H_PWRGD<20,42>

CPU_LDT_REQ#<12,20>

4 4

+1.8V

CPU_PROCHOT#_1.8

1 2

R22

R22 1K_0402_5%

1K_0402_5%

12

R23

R23 1K_0402_5%

1K_0402_5%

12

R9

R9 300_0402_5%

300_0402_5%

1 2

1

C124

@

0.1U_0402_16V7K

2

For EMI

0718 AMD --> 1K ohm

+1.8VS

R15

R15 300_0402_5%

300_0402_5%

1 2

LDT_RST#

1

C22

@

0.01U_0402_25V7K

2

+1.8VS +1.8VS

R21

R21 300_0402_5%

300_0402_5%

1 2

H_PWRGD LDT_STOP#

1

C23

@

0.1U_0402_16V7K

2

+1.8VS

R30

300_0402_5%

A

1 2 1

C24

2

@ R11

@

1 2

@

CPU_LDT_REQ#

330P_0402_50V7K

1

C17

4.7U_0805_10V4Z

2

CPU_SVC

CPU_SVD

LDT_STOP#<12,20>

@

R967

PUMA@ R967

PUMA@

0_0402_5%

1 2

Un-Mount R27 For Caspian

R11 0_0402_5%

0_0402_5%

< To SB700 CPU block>

VDDA=300mA

1

C18

C18 3300P_0402_50V7K

3300P_0402_50V7K

2

R36

R36 300_0402_5%

300_0402_5%

1 2 1

C25

0.01U_0402_25V7K

2

CPU_LDT_REQ_R#

H_PROCHOT# <20>

B

< Sideband-Temperature Sensor Interface Clock & Data>

< Sideband-Temperature Sensor Interface interrupt >

< Compensation Resistor to VSS >

< Compensation Resistor to VLDT >

+2.5VDDA+2.5VS

+2.5VDDA

1

C19

0.22U_0603_16V4Z

2

+1.2V_HT

Add R497 and R500 for Caspian

TIGRIS@ R493

TIGRIS@

1 2

+1.8V

1 2

CPU_THERMTRIP#_R

Add R29 and R31 for Caspian

R968

TIGRIS@ R968

TIGRIS@

300_0402_5%

12

R969

TIGRIS@ R969

TIGRIS@

300_0402_5%

1 2

R26

R26 300_0402_5%

300_0402_5%

12

R28

R28 300_0402_5%

300_0402_5%

1 2

B

R493 510_0402_5%

510_0402_5%

R966

@ R966

@

510_0402_5%

R10

R10 10K_0402_5%

10K_0402_5%

R5

R5 300_0402_5%

300_0402_5%

CPU_TEST20_SCANCLK2

CPU_TEST23_TSTUPD

CPU_TEST21_SCANEN

CPU_TEST24_SCANCLK1

E

3 1

MMBT3904_NL_SOT23-3

R13 44.2_0402_1%R13 44.2_0402_1%

1 2

R14 44.2_0402_1%R14 44.2_0402_1%

1 2

CPU_VDD0_RUN_FB_H<42> CPU_VDD0_RUN_FB_L<42>

CPU_VDD1_RUN_FB_H<42> CPU_VDD1_RUN_FB_L<42>

< Debug ready >

< JTAG debug port >

CPU_TEST25_H_BYPASSCLK_H

CPU_TEST25_L_BYPASSCLK_L

D12

@ D12

@

CH751H-40PT_SOD323-2

21

B

2

Q3

C

D16

D16 CH751H-40PT_SOD323-2

CH751H-40PT_SOD323-2

21

< Differential feedback for VDDNB >

+VDDNB

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

T9 PADT9 PAD T10 PADT10 PAD T11 PADT11 PAD T12 PADT12 PAD T19 PADT19 PAD

Close to CPU

R484

R484 10_0402_5%

10_0402_5%

12

R485

R485 10_0402_5%

10_0402_5%

12

C

JCPUD

+2.5VDDA

CPU_CLKIN_SC_P CPU_CLKIN_SC_N

LDT_RST# H_PWRGD LDT_STOP# CPU_LDT_REQ_R#

CPU_HTREF0 CPU_HTREF1

CPU_VDD0_RUN_FB_H CPU_VDD0_RUN_FB_L

CPU_VDD1_RUN_FB_H CPU_VDD1_RUN_FB_L

CPU_TEST23_TSTUPD

CPU_TEST25_H_BYPASSCLK_H CPU_TEST25_L_BYPASSCLK_L

CPU_TEST21_SCANEN CPU_TEST20_SCANCLK2 CPU_TEST24_SCANCLK1

R25

1 2

0_0402_5%

R965

@ R965

@

510_0402_5%

1 2

R492

TIGRIS@ R492

TIGRIS@

510_0402_5%

1 2

< To power circuitry>

ENTRIP2 <36,38>

< To SB710 ACPI block>

H_THERMTRIP# <21>

CPU_VDDNB_RUN_FB_H

CPU_VDDNB_RUN_FB_L

2009-02-12 2009-02-12

F8 F9

A9 A8

B7 A7

F10

C6

AF4 AF5

AE6

R6

P6 F6

E6 Y6

AB6

G10 AA9 AC9 AD9 AF9

AD7 H10

G9

E9 E8

AB8 AF7 AE7 AE8 AC8 AF8

C2

AA6

A3 A5 B3 B5

C1

+1.8V

Compal Secret Data

VDDA1 VDDA2

CLKIN_H CLKIN_L

RESET_L PWROK LDTSTOP_L LDTREQ_L

SIC SID ALERT_L

HT_REF0 HT_REF1

VDD0_FB_H VDD0_FB_L

VDD1_FB_H VDD1_FB_L

DBRDY TMS TCK TRST_L TDI

TEST23 TEST18

TEST19 TEST25_H

TEST25_L TEST21

TEST20 TEST24 TEST22 TEST12 TEST27

TEST9 TEST6

RSVD1 RSVD2 RSVD3 RSVD4 RSVD5

6090022100G_B

0.1U_0402_16V7K

Deciphered Date

THERMTRIP_L

VDDNB_FB_H

VDDNB_FB_L

+1.8V

T23 PADT23 PAD

+1.8V

T24 PADT24 PAD

C26

D

M11

KEY1

W18

KEY2

A6

SVC

A4

SVD

AF6

MEMHOT_L

THERMDC THERMDA

DBREQ_L

TDO

TEST28_H

TEST28_L

TEST17 TEST16 TEST15 TEST14

TEST7

TEST10

TEST8

TEST29_H

TEST29_L

RSVD10

RSVD9 RSVD8 RSVD7 RSVD6

AC7 AA8

W7 W8

W9 Y9

H6 G6

E10 AE9

J7 H8

D7 E7 F7 C7

C3 K8

C4

C9 C8

H18 H19 AA7 D5 C5

@

PROCHOT_L

VDDIO_FB_H

VDDIO_FB_L

< R41 Close to CPU >

CPU_DBREQ#

R41 300_0402_5%R41 300_0402_5%

1 2

R40 220_0402_5%@ R40 220_0402_5%@ R39 220_0402_5%@ R39 220_0402_5%@ R38 220_0402_5%@ R38 220_0402_5%@ R37 220_0402_5%@ R37 220_0402_5%@

+3VS

1

1 2

2

< noise filter cap >

D

CPU_SVC CPU_SVD

CPU_THERMTRIP#_R CPU_PROCHOT#_1.8

THERMDC_CPU THERMDA_CPU

R42

12

300_0402_5%PUMA@

+1.8V sense no support

CPU_VDDNB_RUN_FB_H CPU_VDDNB_RUN_FB_L

CPU_DBREQ#

CPU_TEST28_H_PLLCHRZ_P CPU_TEST28_L_PLLCHRZ_N

CPU_TEST17_BP3 CPU_TEST16_BP2

CPU_TEST10_ANALOGOUT

CPU_TEST29_H_FBCLKOUT_P CPU_TEST29_L_FBCLKOUT_N

< R494 Close to CPU >

1 2 1 2 1 2 1 2

NOTE: HDT TERMINATION IS REQUIRED FOR REV. Ax SILICON ONLY.

< Thermal Sensor >

THERMDA_CPU THERMDC_CPU

C27

C27 2200P_0402_50V7K

2200P_0402_50V7K

E

CPU_SVC <42> CPU_SVD <42>

+1.8V

T22PAD T22PAD T21PAD T21PAD

CPU_VDDNB_RUN_FB_H <42> CPU_VDDNB_RUN_FB_L <42>

T20PAD T20PAD

T5PAD T5PAD T6PAD T6PAD

T7PAD T7PAD T8PAD T8PAD

R32

@ R32

@

300_0402_5%

12

T13PAD T13PAD T14PAD T14PAD

< Serial VID Interface clock & data >

< Thermal Sensor Trip output > < HTC-active state indication or command >

< Thermal diode cathode & anode >

< Differential feedback for VDDIO > < VDDIO : DDR SDRAM I/O ring power supply> < Differential feedback for VDDNB > < Northbridge power supply >

< Debug request >

route as differential as short as possible testpoint under package

+1.2V_HT

< HDT Connector >

JP3 @

2

1

4

R494

@ R494

@

0_0402_5%

1 2

+1.8V

U2

1

VDD

2 3

Custom

Date: Sheet of

SCLK

D+

SDATA

ALERT#

DTHERM#4GND

ADM1032ARM-1 ZREEL_MSOP8

Compal Electronics, Inc.

Title

Size Document Number Rev

Compal Electronics, Inc.

AMD CPU S1G3 CTRL

3 5 7 9 11 13 15 17 19 21

SAMTEC_ASP-68200-07

EC_SMB_CK2

8

EC_SMB_DA2

7 6 5

LA-5831P

6

8 10 12 14 16 18 20 22 2423 26

E

LDT_RST#

< From EC >

EC_SMB_CK2 <32> EC_SMB_DA2 <32>

7 44Wednesday, August 12, 2009

1.0

A

VDD decoupling : +CPU_CORE

+CPU_CORE_0

1

+

C30

C30 330U_X_2VM_R6M

330U_X_2VM_R6M

2

Near CPU Socket

1 1

+CPU_CORE_1 +CPU_CORE_1 +CPU_CORE_1

1

+

C31

C31 330U_X_2VM_R6M

330U_X_2VM_R6M

2

Near CPU Socket

VDDIO decoupling : DDR SDRAM I/O ring power

+1.8V

1

C46

C46 22U_0805_6.3V6M

22U_0805_6.3V6M

2

Under CPU Socket

+1.8V

2 2

1

C55

0.22U_0603_16V4Z

2

Between CPU Socket and DIMM

+1.8V

1

C60

0.01U_0402_25V7K

2

Between CPU Socket and DIMM

+1.8V

180PF Qt'y follow the distance between CPU socket and DIMM0. <2.5inch>

1

C62

C62 180P_0402_50V8J

180P_0402_50V8J

2

Between CPU Socket and DIMM

+1.8V

3 3

1

C74

4.7U_0805_10V4Z

2

Between CPU Socket and DIMM

+0.9V

VTT decoupling.

1

C66

4.7U_0805_10V4Z

2

Near CPU Socket Right side

+0.9V

1

C79

4.7U_0805_10V4Z

2

Near CPU Socket Left side

4 4

+VDDNB decoupling : Northbridge power

+VDDNB

1

C52

C52 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

+

2

1

+

2

1

C47

C47 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

C56

0.22U_0603_16V4Z

2

1

C63

C63 180P_0402_50V8J

180P_0402_50V8J

2

1

C75

4.7U_0805_10V4Z

2

1

C67

4.7U_0805_10V4Z

2

1

C80

4.7U_0805_10V4Z

2

1

C53

C53 22U_0805_6.3V6M

22U_0805_6.3V6M

2

A

C28

C28 330U_X_2VM_R6M

330U_X_2VM_R6M

C29

C29 330U_X_2VM_R6M

330U_X_2VM_R6M

+CPU_CORE_0 +CPU_CORE_0

1

C32

C32 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

C33

C33 22U_0805_6.3V6M

22U_0805_6.3V6M

2

Under CPU Socket Under CPU Socket

1

C36

C36 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

C37

C37 22U_0805_6.3V6M

22U_0805_6.3V6M

2

Under CPU Socket Under CPU Socket

1

C48

0.22U_0603_16V4Z

2

1

C57

0.22U_0603_16V4Z

2

1

C61

0.01U_0402_25V7K

2

1

C64

C64 180P_0402_50V8J

180P_0402_50V8J

2

1

C49

0.22U_0603_16V4Z

2

1

C58

0.22U_0603_16V4Z

2

1

C65

C65 180P_0402_50V8J

180P_0402_50V8J

2

1

C50

C50 180P_0402_50V8J

180P_0402_50V8J

2

Change to B2 size

1

C76

4.7U_0805_10V4Z

2

1

C68

0.22U_0603_16V4Z

2

1

C81

0.22U_0603_16V4Z

2

1

C77

4.7U_0805_10V4Z

2

1

C69

0.22U_0603_16V4Z

2

1

C82

0.22U_0603_16V4Z

2

@+C78

@

1

C70

C70 1000P_0402_25V8J

1000P_0402_25V8J

2

1

C83

C83 1000P_0402_25V8J

1000P_0402_25V8J

2

Add 22uF for Caspaian

1

C54

C54 22U_0805_6.3V6M

22U_0805_6.3V6M

2

TIGRIS@

1

C34

C34 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

C38

C38 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

+

C78 220U_B2_4VM_R45M

220U_B2_4VM_R45M

2

B

1

C51

C51 180P_0402_50V8J

180P_0402_50V8J

2

1

C71

C71 1000P_0402_25V8J

1000P_0402_25V8J

2

1

C84

C84 1000P_0402_25V8J

1000P_0402_25V8J

2

B

1

C35

C35 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

C39

C39 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

2

1

2

1

C40

0.22U_0603_16V4Z

2

1

C43

0.22U_0603_16V4Z

2

C72

C72 180P_0402_50V8J

180P_0402_50V8J

C85

C85 180P_0402_50V8J

180P_0402_50V8J

C

1

C41

0.01U_0402_25V7K

2

1

C44

0.01U_0402_25V7K

2

1

C73

C73 180P_0402_50V8J

180P_0402_50V8J

2

1

C86

C86 180P_0402_50V8J

180P_0402_50V8J

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

2

1

2

+0.9V

1. Near Power Supply

1

2. Change to B2 size

+

C59

C59 220U_B2_4VM_R45M

220U_B2_4VM_R45M

2

C

C42

C42 180P_0402_50V8J

180P_0402_50V8J

C45

C45 180P_0402_50V8J

180P_0402_50V8J

Compal Secret Data

2009-02-12 2009-02-12

Compal Secret Data

Deciphered Date

+CPU_CORE_0

+VDDNB

+1.8V

D

AA11 AA13 AA15 AA17 AA19

AB23 AB25 AC11 AC13 AC15 AC17 AC19 AC21

AD25 AE11 AE13 AE15 AE17 AE19 AE21 AE23

M10

N11

M16

H25

M18 M21 M23 M25 N17

AA4

AB2 AB7 AB9

AD6 AD8

D11 D13 D15 D17 D19 D21 D23 D25

H21 H23

G4 H2

J9 J11 J13 J15

K6 K10 K12 K14

L4

L7

L9 L11 L13 L15

M2 M6 M8

N7 N9

K16 P16

T16 V16

J17 K18 K21 K23 K25 L17

@

B4 B6 B8

B9 B11 B13 B15 B17 B19 B21 B23 B25

D6 D8 D9

E4

F2 F11 F13 F15 F17 F19 F21 F23 F25

H7 H9

J4

JCPUE

VDD0_1 VDD0_2 VDD0_3 VDD0_4 VDD0_5 VDD0_6 VDD0_7 VDD0_8 VDD0_9 VDD0_10 VDD0_11 VDD0_12 VDD0_13 VDD0_14 VDD0_15 VDD0_16 VDD0_17 VDD0_18 VDD0_19 VDD0_20 VDD0_21 VDD0_22 VDD0_23

VDDNB_1 VDDNB_2 VDDNB_3 VDDNB_4 VDDNB_5

VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO6 VDDIO7 VDDIO8 VDDIO9 VDDIO10 VDDIO11 VDDIO12

6090022100G_B

JCPUF

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65

6090022100G_B

@

E

VDD1_1 VDD1_2 VDD1_3 VDD1_4 VDD1_5 VDD1_6 VDD1_7 VDD1_8

VDD1_9 VDD1_10 VDD1_11 VDD1_12 VDD1_13 VDD1_14 VDD1_15 VDD1_16 VDD1_17 VDD1_18 VDD1_19 VDD1_20 VDD1_21 VDD1_22 VDD1_23 VDD1_24 VDD1_25 VDD1_26

VDDIO27 VDDIO26 VDDIO25 VDDIO24 VDDIO23 VDDIO22 VDDIO21 VDDIO20 VDDIO19 VDDIO18 VDDIO17 VDDIO16 VDDIO15 VDDIO14 VDDIO13

+CPU_CORE_1

P8 P10 R4 R7 R9 R11 T2 T6 T8 T10 T12 T14 U7 U9 U11 U13 U15 V6 V8 V10 V12 V14 W4 Y2 AC4

+1.8V

AD2 Y25

V25 V23 V21 V18 U17 T25 T23 T21 T18 R17 P25 P23 P21 P18

Athlon 64 S1 Processor Socket

J6

VSS66

J8

VSS67

J10

VSS68

J12

VSS69

J14

VSS70

J16

VSS71

J18

VSS72

K2

VSS73

K7

VSS74

K9

VSS75

K11

VSS76

K13

VSS77

K15

VSS78

K17

VSS79

L6

VSS80

L8

VSS81

L10

VSS82

L12

VSS83

L14

VSS84

L16

VSS85

L18

VSS86

M7

VSS87

M9

VSS88

AC6

VSS89

M17

VSS90

N4

VSS91

N8

VSS92

N10

VSS93

N16

VSS94

N18

VSS95

P2

VSS96

P7

VSS97

P9

VSS98

P11

VSS99

P17

VSS100

R8

VSS101

R10

VSS102

R16

VSS103

R18

VSS104

T7

VSS105

T9

VSS106

T11

VSS107

T13

VSS108

T15

VSS109

T17

VSS110

U4

VSS111

U6

VSS112

U8

VSS113

U10

VSS114

U12

VSS115

U14

VSS116

U16

VSS117

U18

VSS118

V2

VSS119

V7

VSS120

V9

VSS121

V11

VSS122

V13

VSS123

V15

VSS124

V17

VSS125

W6

VSS126

Y21

VSS127

Y23

VSS128

N6

VSS129

Athlon 64 S1 Processor Socket

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

AMD CPU S1G3 PWR & GND

LA-5831P

8 44Wednesday, August 12, 2009

E

1.0

A

B

C

D

E

+1.8V+1.8V

JDDRH

+V_DDR_MCH_REF<10>

1 1

2 2

3 3

4 4

A

1

C104

C104 1000P_0402_25V8J

1000P_0402_25V8J

2

DDR_CKE0_DIMMB<6>

DDR_B_BS#2<6>

DDR_B_BS#0<6> DDR_B_WE#<6>

DDR_B_CAS#<6> DDR_CS1_DIMMB#<6>

DDR_B_ODT1<6>

SMB_CK_DAT0<10,16,21>

SMB_CK_CLK0<10,16,21>

DDR_B_D0 DDR_B_D1

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D2 DDR_B_D3

DDR_B_D8 DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D10 DDR_B_D11

DDR_B_D16 DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D18 DDR_B_D22 DDR_B_D19

DDR_B_D24 DDR_B_D25

DDR_B_DM3

DDR_B_D26 DDR_B_D27

DDR_CKE0_DIMMB

DDR_B_BS#2 DDR_B_MA12

DDR_B_MA9

DDR_B_MA5 DDR_B_MA3 DDR_B_MA1

DDR_B_MA10 DDR_B_BS#0 DDR_B_WE#

DDR_B_CAS# DDR_CS1_DIMMB#

DDR_B_ODT1 DDR_B_D32

DDR_B_D33 DDR_B_DQS#4

DDR_B_DQS4 DDR_B_D34

DDR_B_D35 DDR_B_D40

DDR_B_D41 DDR_B_DM5 DDR_B_D42

DDR_B_D43 DDR_B_D47 DDR_B_D48

DDR_B_D49 DDR_B_D53

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D50 DDR_B_D51 DDR_B_D55

DDR_B_D56 DDR_B_D57

DDR_B_DM7 DDR_B_D58

DDR_B_D59 SMB_CK_DAT0

SMB_CK_CLK0

+3VS

1

C119

0.1U_0402_16V7K

2

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

P-TWO_A5692B-A0G16-P

@

DIMM0 STD H:9.2mm (Bot)

B

DQ12 DQ13

CK0#

DQ14 DQ15

DQ20 DQ21

DQ22 DQ23

DQ28 DQ29

DQS3#

DQS3 DQ30

DQ31

NC/CKE1

NC/A15 NC/A14

RAS#

ODT0

NC/A13

DQ36 DQ37

DQ38 DQ39

DQ44 DQ45

DQS5#

DQS5 DQ46

DQ47 DQ52

DQ53

CK1#

DQ54 DQ55

DQ60 DQ61

DQS7#

DQS7 DQ62

DQ63

VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS

VSS DM1 VSS CK0

VSS

VSS DM2

VSS

VSS VDD

VDD

VDD BA1

VDD

VDD VSS

VSS DM4 VSS

VSS

VSS CK1

VSS DM6 VSS

VSS

VSS SAO SA1

2

DDR_B_D4

4

DDR_B_D5

6 8

DDR_B_DM0

10 12

DDR_B_D6

14

DDR_B_D7

16 18

DDR_B_D12

20

DDR_B_D13

22 24

DDR_B_DM1

26 28

DDR_B_CLK0

30

DDR_B_CLK#0

32 34

DDR_B_D14

36

DDR_B_D15

38 40

42

DDR_B_D20

44

DDR_B_D21

46 48 50

NC

A11

A7 A6

A4 A2 A0

S0#

NC

52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200

DDR_B_DM2

DDR_B_D23 DDR_B_D28

DDR_B_D29 DDR_B_DQS#3

DDR_B_DQS3 DDR_B_D30

DDR_B_D31 DDR_CKE1_DIMMB DDR_B_MA15

DDR_B_MA14 DDR_B_MA11

DDR_B_MA7 DDR_B_MA6DDR_B_MA8

DDR_B_MA4 DDR_B_MA2 DDR_B_MA0

DDR_B_BS#1 DDR_B_RAS# DDR_CS0_DIMMB#

DDR_B_ODT0 DDR_B_MA13

DDR_B_D36 DDR_B_D37

DDR_B_DM4 DDR_B_D38

DDR_B_D39 DDR_B_D44

DDR_B_D45 DDR_B_DQS#5

DDR_B_DQS5 DDR_B_D46

DDR_B_D52

DDR_B_CLK1 DDR_B_CLK#1

DDR_B_DM6 DDR_B_D54

DDR_B_D60 DDR_B_D61

DDR_B_DQS#7 DDR_B_DQS7

DDR_B_D62 DDR_B_D63

DDR_B_D[0..63] DDR_B_DM[0..7] DDR_B_DQS[0..7] DDR_B_MA[0..15] DDR_B_DQS#[0..7]

DDR_B_CLK0 <6> DDR_B_CLK#0 <6>

DDR_CKE1_DIMMB <6>

DDR_B_BS#1 <6> DDR_B_RAS# <6> DDR_CS0_DIMMB# <6>

DDR_B_ODT0 <6>

DDR_B_CLK1 <6> DDR_B_CLK#1 <6>

+3VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

DDR_B_D[0..63] <6>

DDR_B_DM[0..7] <6>

DDR_B_DQS[0..7] <6>

DDR_B_MA[0..15] <6>

DDR_B_DQS#[0..7] <6>

2009-02-12 2009-02-12

DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 DDR_B_RAS#

DDR_B_MA14 DDR_B_MA11 DDR_B_MA7 DDR_B_MA6

DDR_CKE0_DIMMB DDR_B_BS#2 DDR_B_MA15 DDR_CKE1_DIMMB

DDR_B_MA3 DDR_B_MA8 DDR_B_MA12 DDR_B_MA9

DDR_B_BS#0 DDR_B_MA10 DDR_B_MA1 DDR_B_MA5

DDR_CS1_DIMMB# DDR_B_ODT1 DDR_B_CAS# DDR_B_WE#

DDR_B_BS#1 DDR_CS0_DIMMB# DDR_B_MA13 DDR_B_ODT0

Compal Secret Data

Deciphered Date

RP8

1 8 2 7 3 6 4 5

47_0804_8P4R_5%

RP9

1 8 2 7 3 6 4 5

47_0804_8P4R_5%

RP10

47_0804_8P4R_5%

RP11

47_0804_8P4R_5%

RP12

47_0804_8P4R_5%

RP13

47_0804_8P4R_5%

RP14

1 8 2 7 3 6 4 5

47_0804_8P4R_5%

@

1

C120

0.1U_0402_16V7K

2

+0.9V

C105 0.1U_0402_16V7KC105 0.1U_0402_16V7K C106 0.1U_0402_16V7KC106 0.1U_0402_16V7K

C108 0.1U_0402_16V7KC108 0.1U_0402_16V7K C107 0.1U_0402_16V7KC107 0.1U_0402_16V7K

C109 0.1U_0402_16V7KC109 0.1U_0402_16V7K

18 27

C110 0.1U_0402_16V7KC110 0.1U_0402_16V7K

36 45

C111 0.1U_0402_16V7KC111 0.1U_0402_16V7K

18 27

C112 0.1U_0402_16V7KC112 0.1U_0402_16V7K

36 45

C114 0.1U_0402_16V7KC114 0.1U_0402_16V7K

18 27

C113 0.1U_0402_16V7KC113 0.1U_0402_16V7K

36 45

C116 0.1U_0402_16V7KC116 0.1U_0402_16V7K

18 27

C115 0.1U_0402_16V7KC115 0.1U_0402_16V7K

36 45

C118 0.1U_0402_16V7KC118 0.1U_0402_16V7K C117 0.1U_0402_16V7KC117 0.1U_0402_16V7K

For EMI

@

1

C121

C122

0.1U_0402_16V7K

2

D

+1.8V

12 12

+1.8V

@

1

C123

0.1U_0402_16V7K

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

DDRII SO-DIMM 0

LA-5831P

E

1.0

9 44Wednesday, August 12, 2009

1.0

A

+1.8V

R43

R43 1K_0402_1%

1K_0402_1%

A

1 2

R44

R44 1K_0402_1%

1K_0402_1%

1 2

1

C96

0.1U_0402_16V7K

2

DDR_CKE0_DIMMA<6>

DDR_A_BS#2<6>

DDR_A_BS#0<6> DDR_A_WE#<6>

DDR_A_CAS#<6> DDR_CS1_DIMMA#<6>

DDR_A_ODT1<6>

SMB_CK_DAT0<9,16,21>

SMB_CK_CLK0<9,16,21>

1

2

+V_DDR_MCH_REF<9>

1 1

2 2

3 3

4 4

+V_DDR_MCH_REF

C95

C95 1000P_0402_25V8J

1000P_0402_25V8J

DDR_A_D0 DDR_A_D1

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D20 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_DM3

DDR_A_D26 DDR_A_D27

DDR_CKE0_DIMMA

DDR_A_BS#2 DDR_A_MA12

DDR_A_MA9 DDR_A_MA8

DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 DDR_A_MA0

DDR_A_MA10 DDR_A_BS#0 DDR_A_WE#

DDR_A_CAS# DDR_CS1_DIMMA#

DDR_A_ODT1 DDR_A_D32

DDR_A_D33 DDR_A_DQS#4

DDR_A_DQS4 DDR_A_D34

DDR_A_D35 DDR_A_D40

DDR_A_D41 DDR_A_DM5 DDR_A_D42

DDR_A_D43 DDR_A_D48

DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_DM7 DDR_A_D58

DDR_A_D59 SMB_CK_DAT0

SMB_CK_CLK0

+3VS

1

C103

0.1U_0402_16V7K

2

B

JDDRL

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

PTI_A5652D-A0G16-P

@

DM0

DQ12 DQ13

DM1

CK0#

DQ14 DQ15

DQ20 DQ21

DM2

DQ22 DQ23

DQ28 DQ29

DQS3#

DQS3 DQ30

DQ31

NC/CKE1

VDD NC/A15 NC/A14

VDD

RAS#

VDD

ODT0

NC/A13

VDD

DQ36 DQ37

DM4

DQ38 DQ39

DQ44 DQ45

DQS5#

DQS5 DQ46

DQ47 DQ52

DQ53

CK1#

DM6

DQ54 DQ55

DQ60 DQ61

DQS7#

DQS7 DQ62

DQ63

SAO

VSS DQ4 DQ5 VSS

VSS DQ6 DQ7 VSS

VSS VSS

CK0 VSS

VSS

BA1

VSS

VSS VSS

VSS

VSS CK1

VSS VSS

VSS

VSS SA1

+1.8V+1.8V

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

42 44 46 48 50

NC

52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90

A11

92

A7

94

A6

96 98

A4

100

A2

102

A0

104 106 108 110

S0#

112 114 116 118 120

NC

122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200

DIMM0 STD H:5.2mm (Bot)

B

C

DDR_A_D[0..63] DDR_A_DM[0..7] DDR_A_DQS[0..7] DDR_A_MA[0..15] DDR_A_DQS#[0..7]

DDR_A_D4 DDR_A_D5

DDR_A_DM0 DDR_A_D6

DDR_A_D7 DDR_A_D12

DDR_A_D13 DDR_A_DM1 DDR_A_CLK0

DDR_A_CLK#0 DDR_A_D14

DDR_A_D15

DDR_A_D21

DDR_A_DM2 DDR_A_D22

DDR_A_D23 DDR_A_D28

DDR_A_D29 DDR_A_DQS#3

DDR_A_DQS3 DDR_A_D30

DDR_A_D31 DDR_CKE1_DIMMA DDR_A_MA15

DDR_A_MA14 DDR_A_MA11

DDR_A_MA7 DDR_A_MA6

DDR_A_MA4 DDR_A_MA2

DDR_A_BS#1 DDR_A_RAS# DDR_CS0_DIMMA#

DDR_A_ODT0 DDR_A_MA13

DDR_A_D36 DDR_A_D37

DDR_A_DM4 DDR_A_D38

DDR_A_D39 DDR_A_D44

DDR_A_D45 DDR_A_DQS#5

DDR_A_DQS5 DDR_A_D46

DDR_A_D47 DDR_A_D52

DDR_A_D53 DDR_A_CLK1

DDR_A_CLK#1 DDR_A_DM6 DDR_A_D54

DDR_A_D55 DDR_A_D60

DDR_A_D61 DDR_A_DQS#7

DDR_A_DQS7 DDR_A_D62

DDR_A_D63

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Issued Date

DDR_A_CLK0 <6> DDR_A_CLK#0 <6>

DDR_CKE1_DIMMA <6>

DDR_A_BS#1 <6> DDR_A_RAS# <6> DDR_CS0_DIMMA# <6>

DDR_A_ODT0 <6>

DDR_A_CLK1 <6> DDR_A_CLK#1 <6>

2009-02-12 2009-02-12

C

DDR_A_D[0..63] <6> DDR_A_DM[0..7] <6>

DDR_A_DQS[0..7] <6>

DDR_A_MA[0..15] <6>

DDR_A_DQS#[0..7] <6>

DDR_A_MA6 DDR_A_MA14 DDR_A_MA7 DDR_A_MA11

DDR_CKE0_DIMMA DDR_A_BS#2 DDR_CKE1_DIMMA DDR_A_MA15

DDR_A_BS#1 DDR_A_MA2 DDR_A_MA0 DDR_A_MA4

DDR_A_MA5 DDR_A_MA8 DDR_A_MA9 DDR_A_MA12

DDR_A_BS#0 DDR_A_MA10 DDR_A_MA3 DDR_A_MA1

DDR_A_ODT1 DDR_CS1_DIMMA# DDR_A_CAS# DDR_A_WE#

DDR_A_MA13 DDR_A_ODT0 DDR_A_RAS# DDR_CS0_DIMMA#

Compal Secret Data

Deciphered Date

D

47_0804_8P4R_5%

D

RP1

1 8 2 7 3 6 4 5

RP2

RP3

1 8 2 7 3 6 4 5

RP4

RP5

RP6

RP7

1 8 2 7 3 6 4 5

18 27 36 45

E

+0.9V

C87 0.1U_0402_16V7KC87 0.1U_0402_16V7K

1 2

C88 0.1U_0402_16V7KC88 0.1U_0402_16V7K

1 2

C90 0.1U_0402_16V7KC90 0.1U_0402_16V7K

1 2

C89 0.1U_0402_16V7KC89 0.1U_0402_16V7K

1 2

C91 0.1U_0402_16V7KC91 0.1U_0402_16V7K

1 2

C92 0.1U_0402_16V7KC92 0.1U_0402_16V7K

1 2

C93 0.1U_0402_16V7KC93 0.1U_0402_16V7K

1 2

C94 0.1U_0402_16V7KC94 0.1U_0402_16V7K

1 2

C98 0.1U_0402_16V7KC98 0.1U_0402_16V7K

1 2

C97 0.1U_0402_16V7KC97 0.1U_0402_16V7K

1 2

C100 0.1U_0402_16V7KC100 0.1U_0402_16V7K

1 2

C99 0.1U_0402_16V7KC99 0.1U_0402_16V7K

1 2

C102 0.1U_0402_16V7KC102 0.1U_0402_16V7K

1 2

C101 0.1U_0402_16V7KC101 0.1U_0402_16V7K

1 2

Title

Size Document Number Rev

Custom

Date: Sheet of

+1.8V

Compal Electronics, Inc.

DDRII SO-DIMM 1

LA-5831P

E

1.0

10 44Wednesday, August 12, 2009

1.0

A

1 1

H_CLKOP0<5> H_CLKON0<5> H_CLKOP1<5> H_CLKON1<5>

H_CTLOP0<5> H_CTLON0<5>

H_CTLON1<5>

1 2

PCIE_PTX_C_IRX_P2 PCIE_PTX_C_IRX_N2 PCIE_PTX_C_IRX_P3 PCIE_PTX_C_IRX_N3

H_CADOP0 H_CADON0 H_CADOP1 H_CADON1 H_CADOP2 H_CADON2 H_CADOP3 H_CADON3 H_CADOP4 H_CADON4 H_CADOP5 H_CADON5 H_CADOP6 H_CADON6 H_CADOP7 H_CADON7

H_CADOP8 H_CADON8 H_CADOP9 H_CADON9 H_CADOP10 H_CADON10 H_CADOP11 H_CADON11 H_CADOP12 H_CADON12 H_CADOP13 H_CADON13 H_CADOP14 H_CADON14 H_CADOP15 H_CADON15

< To WLAN > < To LAN >

2 2

< From SB710 : x4 PCIE A-link >

H_CADON[0..15]

3 3

4 4

PCIE_PTX_C_IRX_P2<27> PCIE_PTX_C_IRX_N2<27> PCIE_PTX_C_IRX_P3<26> PCIE_PTX_C_IRX_N3<26>

SB_RX0P<20> SB_RX0N<20> SB_RX1P<20> SB_RX1N<20> SB_RX2P<20> SB_RX2N<20> SB_RX3P<20> SB_RX3N<20>

H_CADOP[0..15] <5> H_CADON[0..15] <5>

< From S1G3 CPU : x16 HT> < To S1G3 CPU : x16 HT>

0718 Place within 1" layout 1:2

R57301_0402_1% R57301_0402_1%

SB_RX0P SB_RX0N SB_RX1P SB_RX1N SB_RX2P SB_RX2N SB_RX3P SB_RX3N

H_CLKOP0 H_CLKON0 H_CLKOP1 H_CLKON1

H_CTLOP0 H_CTLON0 H_CTLOP1 H_CTLON1

HT_RXCALP HT_RXCALN

B

U3B

D4

GFX_RX0P

C4

GFX_RX0N

A3

GFX_RX1P

B3

GFX_RX1N

C2

GFX_RX2P

C1

GFX_RX2N

E5

GFX_RX3P

F5

GFX_RX3N

G5

GFX_RX4P

G6

GFX_RX4N

H5

GFX_RX5P

H6

GFX_RX5N

J6

GFX_RX6P

J5

GFX_RX6N

J7

GFX_RX7P

J8

GFX_RX7N

L5

GFX_RX8P

L6

GFX_RX8N

M8

GFX_RX9P

L8

GFX_RX9N

P7

GFX_RX10P

M7

GFX_RX10N

P5

GFX_RX11P

M5

GFX_RX11N

R8

GFX_RX12P

P8

GFX_RX12N

R6

GFX_RX13P

R5

GFX_RX13N

P4

GFX_RX14P

P3

GFX_RX14N

T4

GFX_RX15P

T3

GFX_RX15N

AE3

GPP_RX0P

AD4

GPP_RX0N

AE2

GPP_RX1P

AD3

GPP_RX1N

AD1

GPP_RX2P

AD2

GPP_RX2N

V5

GPP_RX3P

W6

GPP_RX3N

U5

GPP_RX4P

U6

GPP_RX4N

U8

GPP_RX5P

U7

GPP_RX5N

AA8

SB_RX0P

Y8

SB_RX0N

AA7

SB_RX1P

Y7

SB_RX1N

AA5

SB_RX2P

AA6

SB_RX2N

W5

SB_RX3P

Y5

SB_RX3N

RS780M_FCBGA528

U3A

Y25

HT_RXCAD0P

Y24 V22 V23 V25 V24 U24 U25 T25 T24 P22 P23 P25 P24 N24 N25

AC24 AC25 AB25 AB24 AA24 AA25

Y22

Y23 W21 W20

V21

V20

U20

U21

U19

U18

T22

T23

AB23 AA22

M22 M23

R21

R20

C23

A24

RS780M_FCBGA528 RS780MCR3@

HT_RXCAD0N HT_RXCAD1P HT_RXCAD1N HT_RXCAD2P HT_RXCAD2N HT_RXCAD3P HT_RXCAD3N HT_RXCAD4P HT_RXCAD4N HT_RXCAD5P HT_RXCAD5N HT_RXCAD6P HT_RXCAD6N HT_RXCAD7P HT_RXCAD7N

HT_RXCAD8P HT_RXCAD8N HT_RXCAD9P HT_RXCAD9N HT_RXCAD10P HT_RXCAD10N HT_RXCAD11P HT_RXCAD11N HT_RXCAD12P HT_RXCAD12N HT_RXCAD13P HT_RXCAD13N HT_RXCAD14P HT_RXCAD14N HT_RXCAD15P HT_RXCAD15N

HT_RXCLK0P HT_RXCLK0N HT_RXCLK1P HT_RXCLK1N

HT_RXCTL0P HT_RXCTL0N HT_RXCTL1P HT_RXCTL1N

HT_RXCALP HT_RXCALN

PART 1 OF 6

PART 2 OF 6

GFX_TX10P

GFX_TX10N

GFX_TX11P

GFX_TX11N

GFX_TX12P

GFX_TX12N

GFX_TX13P

GFX_TX13N

GFX_TX14P

GFX_TX14N

GFX_TX15P

GFX_TX15N

PCIE I/F GFX

PCIE I/F GPP

PCIE I/F SB

PCE_CALRP(PCE_BCALRP) PCE_CALRN(PCE_BCALRN)

RS780MCR3@

HT_TXCAD0P HT_TXCAD0N HT_TXCAD1P HT_TXCAD1N HT_TXCAD2P HT_TXCAD2N HT_TXCAD3P HT_TXCAD3N HT_TXCAD4P HT_TXCAD4N HT_TXCAD5P HT_TXCAD5N HT_TXCAD6P HT_TXCAD6N HT_TXCAD7P HT_TXCAD7N

HT_TXCAD8P HT_TXCAD8N HT_TXCAD9P

HT_TXCAD9N HT_TXCAD10P HT_TXCAD10N HT_TXCAD11P HT_TXCAD11N HT_TXCAD12P HT_TXCAD12N HT_TXCAD13P HT_TXCAD13N HT_TXCAD14P HT_TXCAD14N HT_TXCAD15P HT_TXCAD15N

HT_TXCLK0P

HT_TXCLK0N

HT_TXCLK1P

HT_TXCLK1N

HYPER TRANSPORT CPU I/F

HT_TXCTL0P HT_TXCTL0N HT_TXCTL1P HT_TXCTL1N

HT_TXCALP HT_TXCALN

GFX_TX0P GFX_TX0N GFX_TX1P GFX_TX1N GFX_TX2P GFX_TX2N GFX_TX3P GFX_TX3N GFX_TX4P GFX_TX4N GFX_TX5P GFX_TX5N GFX_TX6P GFX_TX6N GFX_TX7P GFX_TX7N GFX_TX8P GFX_TX8N GFX_TX9P GFX_TX9N

GPP_TX0P GPP_TX0N GPP_TX1P GPP_TX1N GPP_TX2P GPP_TX2N GPP_TX3P GPP_TX3N GPP_TX4P GPP_TX4N GPP_TX5P GPP_TX5N

SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N SB_TX3P SB_TX3N

C

HDMI_TXD2+

A5

HDMI_TXD2-

B5

HDMI_TXD1+

A4

HDMI_TXD1-

B4

HDMI_TXD0+

C3

HDMI_TXD0-

B2

HDMI_CLK0+

D1

HDMI_CLK0-

D2 E2 E1 F4 F3 F1 F2

< If integrated GFX is used, some PCIE pairs are used as HDMI signal pairs >

H4

RS880M Display Port Support (muxed on GFX)

H3 H1 H2 J2 J1 K4 K3 K1 K2 M4 M3 M1 M2 N2 N1 P1 P2

AC1 AC2 AB4 AB3 AA2 AA1 Y1 Y2 Y4 Y3 V1 V2

AD7 AE7 AE6 AD6 AB6 AC6 AD5 AE5

AC8 AB8

D24 D25 E24 E25 F24 F25 F23 F22 H23 H22 J25 J24 K24 K25 K23 K22

F21 G21 G20 H21 J20 J21 J18 K17 L19 J19 M19 L18 M21 P21 P18 M18

H24 H25 L21 L20

M24 M25 P19 R18

B24 B25

DP0 GFX_TX0,TX1,TX2 and TX3

DP1 GFX_TX4,TX5,TX6 and TX7

PCIE_ITX_PRX_P2 PCIE_ITX_PRX_N2 PCIE_ITX_PRX_P3 PCIE_ITX_PRX_N3

SB_TX0P_C SB_TX0N_C SB_TX1P_C SB_TX1N_C SB_TX2P_C SB_TX2N_C SB_TX3P_C SB_TX3N_C

PCIE_CALRP PCIE_CALRN

H_CADIP0 H_CADIN0 H_CADIP1 H_CADIN1 H_CADIP2 H_CADIN2 H_CADIP3 H_CADIN3 H_CADIP4 H_CADIN4 H_CADIP5 H_CADIN5 H_CADIP6 H_CADIN6 H_CADIP7 H_CADIN7

H_CADIP8 H_CADIN8 H_CADIP9 H_CADIN9 H_CADIP10 H_CADIN10 H_CADIP11 H_CADIN11 H_CADIP12 H_CADIN12 H_CADIP13 H_CADIN13 H_CADIP14 H_CADIN14 H_CADIP15 H_CADIN15

H_CLKIP0 H_CLKIN0 H_CLKIP1 H_CLKIN1

H_CTLIP0 H_CTLIN0 H_CTLIP1 H_CTLIN1

HT_TXCALP HT_TXCALN

0718 Place within 1" layout 1:2

H_CLKIP0 <5> H_CLKIN0 <5> H_CLKIP1 <5> H_CLKIN1 <5>

H_CTLIP0 <5>

H_CTLIN0 <5>

H_CTLIP1 <5>H_CTLOP1<5>

H_CTLIN1 <5>

R58 301_0402_1%R58 301_0402_1%

AUX0 and HPD0

AUX1 and HPD1

C156 0.1U_0402_16V7KC156 0.1U_0402_16V7K

1 2

C157 0.1U_0402_16V7KC157 0.1U_0402_16V7K

1 2

C158 0.1U_0402_16V7KC158 0.1U_0402_16V7K

1 2

C159 0.1U_0402_16V7KC159 0.1U_0402_16V7K

1 2

C162 0.1U_0402_16V7KC162 0.1U_0402_16V7K

1 2

C163 0.1U_0402_16V7KC163 0.1U_0402_16V7K

1 2

C164 0.1U_0402_16V7KC164 0.1U_0402_16V7K

1 2

C165 0.1U_0402_16V7KC165 0.1U_0402_16V7K

1 2

C166 0.1U_0402_16V7KC166 0.1U_0402_16V7K

1 2

C168 0.1U_0402_16V7KC168 0.1U_0402_16V7K

1 2

C169 0.1U_0402_16V7KC169 0.1U_0402_16V7K

1 2

C167 0.1U_0402_16V7KC167 0.1U_0402_16V7K

1 2

R55 1.27K_0402_1%R55 1.27K_0402_1%

1 2

R56 2K_0402_1%R56 2K_0402_1%

1 2

H_CADIP[0..15]H_CADOP[0..15] H_CADIN[0..15]

1 2

H_CADIP[0..15] <5> H_CADIN[0..15] <5>

< Transmitter Calibration Resistor to HT_TXCALN >

HDMI_TXD2+ <19> HDMI_TXD2- <19> HDMI_TXD1+ <19> HDMI_TXD1- <19> HDMI_TXD0+ <19> HDMI_TXD0- <19> HDMI_CLK0+ <19> HDMI_CLK0- <19>

D

PCIE_ITX_C_PRX_P2 <27> PCIE_ITX_C_PRX_N2 <27> PCIE_ITX_C_PRX_P3 <26> PCIE_ITX_C_PRX_N3 <26>

SB_TX0P <20> SB_TX0N <20> SB_TX1P <20> SB_TX1N <20> SB_TX2P <20> SB_TX2N <20> SB_TX3P <20> SB_TX3N <20>

+1.1VS

< To WLAN > < To LAN >

< To SB710 : x4 PCEI A-link>

< TX Impedance Calibration. Connect to GND > < RX Impedance Calibration. Connect to VDDPCIE >

E

/

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009-02-12 2009-02-12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

RS780M HT / PCIE

LA-5831P

11 44Wednesday, August 12, 2009

E

1.0Custom

A

UMA_CRT_R<17>

UMA_CRT_HSYNC<15,17> UMA_CRT_VSYNC<15,17> UMA_CRT_CLK<17> UMA_CRT_DATA<17>

LDT_STOP#<7,20> CPU_LDT_REQ#<7,20>

NB_OSC_14.318M<16>

NBGFX_CLK<16> NBGFX_CLK#<16>

CLK_SBLINK_BCLK<16> CLK_SBLINK_BCLK#<16>

UMA_LCD_DDC_CLK<18>

UMA_LCD_DDC_DAT<18>

HDMIDAT_UMA<19> HDMICLK_UMA<19>

UMA_CRT_G<17> UMA_CRT_B<17>

PLT_RST#<15,20,26,27,31,32> NB_PWRGD<21>

CLK_NBHT<16> CLK_NBHT#<16>

AUX_CAL<15>

L2

L2 BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

1 1

+1.1VS

R71

4.7K_0402_5%

1 2

2 2

12

R72

4.7K_0402_5%

Strap pin

< Dedicated power for the DAC which can affect display quality > < Dedicated power for the DAC which can affect display quality >

+3VS +1.8VS

3 3

1 2

B

AVDD=100mA

R65 715_0402_1%R65 715_0402_1%

1 2

+NB_PLLVDD +NB_HTPVDD

+VDDA18HTPLL

+VDDA18PCIEPLL

R67 0_0402_5%R67 0_0402_5%

1 2

R88 10K_0402_5%

+3VS

1

C170

2.2U_0603_6.3V4Z

2

U3C

+AVDD1 +AVDD2 +AVDDQ

UMA_CRT_R UMA_CRT_G UMA_CRT_B

UMA_CRT_HSYNC UMA_CRT_VSYNC UMA_CRT_CLK UMA_CRT_DATA

NB_RESET# NB_PWRGD LDT_STOP# CPU_LDT_REQ#

CLK_NBHT CLK_NBHT#

NB_OSC_14.318M

NBGFX_CLK NBGFX_CLK#

CLK_SBLINK_BCLK CLK_SBLINK_BCLK#

UMA_LCD_DDC_CLK UMA_LCD_DDC_DAT HDMIDAT_UMA HDMICLK_UMA

@

12

AUX_CAL

+AVDD1 +AVDD2

U3C

F12

AVDD1(NC)

E12

AVDD2(NC)

F14

AVDDDI(NC)

G15

AVSSDI(NC)

H15

AVDDQ(NC)

H14

AVSSQ(NC)

E17

C_Pr(DFT_GPIO5)

F17

Y(DFT_GPIO2)

F15

COMP_Pb(DFT_GPIO4)

G18

RED(DFT_GPIO0)

G17

REDb(NC)

E18

GREEN(DFT_GPIO1)

F18

GREENb(NC)

E19

BLUE(DFT_GPIO3)

F19

BLUEb(NC)

A11

DAC_HSYNC(PWM_GPIO4)

B11

DAC_VSYNC(PWM_GPIO6)

F8

DAC_SCL(PCE_RCALRN)

E8

DAC_SDA(PCE_TCALRN)

G14

DAC_RSET(PWM_GPIO1)

A12

PLLVDD(NC)

D14

PLLVDD18(NC)

B12

PLLVSS(NC)

H17

VDDA18HTPLL

D7

VDDA18PCIEPLL1

E7

VDDA18PCIEPLL2

D8

SYSRESETb

A10

POWERGOOD

C10

LDTSTOPb

C12

ALLOW_LDTSTOP

C25

HT_REFCLKP

C24

HT_REFCLKN

E11

REFCLK_P/OSCIN(OSCIN)

F11

REFCLK_N(PWM_GPIO3)

T2

GFX_REFCLKP

T1

GFX_REFCLKN

U1

GPP_REFCLKP

U2

GPP_REFCLKN

V4

GPPSB_REFCLKP(SB_REFCLKP)

V3

GPPSB_REFCLKN(SB_REFCLKN)

B9

I2C_CLK

A9

I2C_DATA

B8

DDC_DATA0/AUX0N(NC)

A8

DDC_CLK0/AUX0P(NC)

B7

DDC_CLK1/AUX1P(NC)

A7

DDC_DATA1/AUX1N(NC)

B10

STRP_DATA

G11

RSVD

C8

AUX_CAL(NC)

RS780M_FCBGA528

C

L4

L4 0_0603_5%

0_0603_5%

PART 3 OF 6

TXOUT_U1P(PCIE_RESET_GPIO3) TXOUT_U1N(PCIE_RESET_GPIO2)

TXOUT_U3P(PCIE_RESET_GPIO5)

CRT/TVOUT

TXCLK_UP(PCIE_RESET_GPIO4) TXCLK_UN(PCIE_RESET_GPIO1)

LVTM

PM

LVDS_DIGON(PCE_TCALRP)

LVDS_BLON(PCE_RCALRP)

LVDS_ENA_BL(PWM_GPIO2)

CLOCKs PLL PWR

MIS.

TXOUT_L0P(NC) TXOUT_L0N(NC) TXOUT_L1P(NC) TXOUT_L1N(NC) TXOUT_L2P(NC)

TXOUT_L2N(DBG_GPIO0)

TXOUT_L3P(NC)

TXOUT_L3N(DBG_GPIO2)

TXOUT_U0P(NC) TXOUT_U0N(NC)

TXOUT_U2P(NC) TXOUT_U2N(NC)

TXOUT_U3N(NC)

TXCLK_LP(DBG_GPIO1) TXCLK_LN(DBG_GPIO3)

VDDLTP18(NC) VSSLTP18(NC)

VDDLT18_1(NC) VDDLT18_2(NC) VDDLT33_1(NC) VDDLT33_2(NC)

VSSLT1(VSS) VSSLT2(VSS) VSSLT3(VSS) VSSLT4(VSS) VSSLT5(VSS) VSSLT6(VSS) VSSLT7(VSS)

TMDS_HPD(NC)

SUS_STAT#(PWM_GPIO5)

HPD(NC)

THERMALDIODE_P THERMALDIODE_N

TESTMODE

RS780MCR3@

1

C172

2.2U_0603_6.3V4Z

2

UMA_LCD_TXOUT0_A0+

A22

UMA_LCD_TXOUT0_A0-

B22

UMA_LCD_TXOUT0_A1+

A21

UMA_LCD_TXOUT0_A1-

B21

UMA_LCD_TXOUT0_A2+

B20

UMA_LCD_TXOUT0_A2-

A20 A19 B19

B18 A18 A17 B17 D20 D21 D18 D19

UMA_LCD_TXCLK_ACLK+

B16

UMA_LCD_TXCLK_ACLK-

A16 D16 D17

+VDDLTP18

A13 B13

+VDDLT18

A15 B15 A14 B14

C14 D15 C16 C18 C20 E20 C22

UMA_ENVDD

E9

UMA_ENBKL

F7 G12

T17PAD T17PAD

Reserve for INVT_PWM

HPD

D9 D10

SUS_STAT#

D12 AE8

AD8

R80 1.8K_0402_5%R80 1.8K_0402_5%

D13

1 2

1

C198

0.1U_0402_16V7K

2

D

UMA_LCD_TXOUT0_A0+ <18> UMA_LCD_TXOUT0_A0- <18> UMA_LCD_TXOUT0_A1+ <18> UMA_LCD_TXOUT0_A1- <18> UMA_LCD_TXOUT0_A2+ <18> UMA_LCD_TXOUT0_A2- <18>

UMA_LCD_TXCLK_ACLK+ <18> UMA_LCD_TXCLK_ACLK- <18>

< LVDS digital power enable >

< LVDS backlight enable >

< HDMI hot-plug detection >

< Strap option pin or gate side-port memory IO >

R371 300_0402_5%R371 300_0402_5%

1 2

R62 140_0402_1%R62 140_0402_1%

1 2

R63 150_0402_1%R63 150_0402_1%

1 2

R64 150_0402_1%R64 150_0402_1%

1 2

R73

UMA_ENVDD <18> UMA_ENBKL <32>

100K_0402_5%

12

HPD <19,21>

SUS_STAT# <15,21>

+1.8VS

E

NB_PWRGD

UMA_CRT_R

UMA_CRT_G UMA_CRT_B

< DAC Bandgap Reference Voltage >

+1.8VS

1 2

< IO power for HyperTransport PLL >

+1.8VS +VDDA18HTPLL

1 2

4 4

A

< 1.8V IO power for PCI-E PLLs >

+1.8VS

1 2

L6

L6 BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

L10

L10 BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

L11

L11 BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

B

+AVDDQ

1

C175

2.2U_0603_6.3V4Z

2

1

C179

2.2U_0603_6.3V4Z

2

1

C180

2.2U_0603_6.3V4Z

2

+VDDA18PCIEPLL

< 1.8V power for system PLLs >

+1.8VS

1 2

+1.1VS

1 2

/

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

L7

L7 BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

L9

L9 BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

C

1

C176

2.2U_0603_6.3V4Z

2

1

C178

2.2U_0603_6.3V4Z

2

Compal Secret Data

2009-02-12 2009-02-12

Compal Secret Data

Deciphered Date

+NB_HTPVDD

+NB_PLLVDD

< Power for integrated DVI/HDMI PLL macro >

+1.8VS

< 1.8V IO power for the integrated DVI/HDMI interface >< 1.1V Power for system PLLs >

+1.8VS

D

L3

L3 BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

12

L5

L5 BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

12

Title

Size Document Number Rev

Custom

Date: Sheet of

1

C174

4.7U_0805_10V4Z

2

Compal Electronics, Inc.

RS780M VEDIO/CLK GEN

1

2

LA-5831P

E

C171

2.2U_0603_6.3V4Z

1

C173

0.1U_0402_16V7K

2

12 44Wednesday, August 12, 2009

+VDDLTP18

+VDDLT18

1.0

2

U3D

PAR 4 OF 6

AB12

MEM_A0(NC)

AE16

MEM_A1(NC)

V11

MEM_A2(NC)

AE15

MEM_A3(NC)

AA12

MEM_A4(NC)

AB16

MEM_A5(NC)

AB14

MEM_A6(NC)

AD14

MEM_A7(NC)

AD13

MEM_A8(NC)

AD15

MEM_A9(NC)

AC16

MEM_A10(NC)

AE13

MEM_A11(NC)

AC14

MEM_A12(NC)

Y14

MEM_A13(NC)

AD16

MEM_BA0(NC)

AE17

MEM_BA1(NC)

AD17

MEM_BA2(NC)

W12

B B

MEM_RASb(NC)

Y12

MEM_CASb(NC)

AD18

MEM_WEb(NC)

AB13

MEM_CSb(NC)

AB18

MEM_CKE(NC)

V14

MEM_ODT(NC)

V15

MEM_CKP(NC)

W14

MEM_CKN(NC)

AE12

MEM_COMPP(NC)

AD12

MEM_COMPN(NC)

RS780M_FCBGA528 RS780MCR3@

PAR 4 OF 6

MEM_DQ0/DVO_VSYNC(NC)

MEM_DQ1/DVO_HSYNC(NC)

MEM_DQ2/DVO_DE(NC) MEM_DQ3/DVO_D0(NC)

MEM_DQ4(NC) MEM_DQ5/DVO_D1(NC) MEM_DQ6/DVO_D2(NC) MEM_DQ7/DVO_D4(NC) MEM_DQ8/DVO_D3(NC) MEM_DQ9/DVO_D5(NC)

MEM_DQ10/DVO_D6(NC) MEM_DQ11/DVO_D7(NC)

MEM_DQ12(NC)

MEM_DQ13/DVO_D9(NC) MEM_DQ14/DVO_D10(NC) MEM_DQ15/DVO_D11(NC)

MEM_DQS0P/DVO_IDCKP(NC)

MEM_DQS0N/DVO_IDCKN(NC)

MEM_DQS1P(NC)

MEM_DQS1N(NC)

MEM_DM0(NC)

MEM_DM1/DVO_D8(NC)

SBD_MEM/DVO_I/F

IOPLLVDD18(NC)

IOPLLVDD(NC)

IOPLLVSS(NC)

MEM_VREF(NC)

AA18 AA20 AA19 Y19 V17 AA17 AA15 Y15 AC20 AD19 AE22 AC18 AB20 AD22 AC22 AD21

Y17 W18 AD20 AE21

W17 AE19

AE23 AE24

AD23 AE18

+1.8VS +1.1VS

1

A A

/

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/04/14 2009/04/14

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

1

Date: Sheet of

Compal Electronics, Inc.

RS780M SIDE PORT

LA-5831P

13 44Wednesday, August 12, 2009

1.0

A

B

C

D

E

U3E

2A

L16 FBMA-L11-201209-221LMA30T_0805L16 FBMA-L11-201209-221LMA30T_0805

+1.1VS

1 1

+1.2V_HT

Change L16, L18, L19 and L22 to bead for EMI

+1.8VS

2 2

+1.8VS

1

2

3 3

4 4

12

1

C209

4.7U_0805_10V4Z

2

2A < IO power for HyperTransport receive interface >

L18 FBMA-L11-201209-221LMA30T_0805L18 FBMA-L11-201209-221LMA30T_0805

12

C215

C215 10U_0805_10V4Z

10U_0805_10V4Z

2A < IO power for HyperTransport transmit interface >

L19 FBMA-L11-201209-221LMA30T_0805L19 FBMA-L11-201209-221LMA30T_0805

12

1

C225

4.7U_0805_10V4Z

2

2A < 1.8V IO power for PCI-E graphics, SB, and GPP interfaces >

L22 FBMA-L11-201209-221LMA30T_0805L22 FBMA-L11-201209-221LMA30T_0805

12

1

C235

4.7U_0805_10V4Z

2

C251

C251 1U_0402_6.3V4Z

1U_0402_6.3V4Z

+1.8VS

1

C206

0.1U_0402_16V7K

2

1

C214

0.1U_0402_16V7K

2

1

C226

0.1U_0402_16V7K

2

1

C246

4.7U_0805_10V4Z

2

L89 0_0603_5%L89 0_0603_5%

1 2

< Digital IO power for HyperTransport interface >

1

C207

0.1U_0402_16V7K

2

1

C216

0.1U_0402_16V7K

2

1

C227

0.1U_0402_16V7K

2

1

C236

0.1U_0402_16V7K

2

1

C208

0.1U_0402_16V7K

2

1

C217

0.1U_0402_16V7K

2

1

C228

0.1U_0402_16V7K

2

1

C237

0.1U_0402_16V7K

2

< 1.8V IO transform power > < 1.8V power for side-port memory interface >

1

C252

@

1U_0402_6.3V4Z

2

1

C210

0.1U_0402_16V7K

2

1

C218

0.1U_0402_16V7K

2

1

C229

0.1U_0402_16V7K

2

1

C238

0.1U_0402_16V7K

2

1

C239

0.1U_0402_16V7K

2

+VDDHT

+VDDHTRX

+VDDHTTX

+VDDA18PCIE

U3E

J17

VDDHT_1

AE25 AD24 AC23 AB22 AA21

W19

AE11 AD11

W22 W24 W25

AD25

W11

W15 AC12 AA14

AB11 AB15 AB17 AB19 AE20 AB21

M16 R16

H18 G19

D22

U17 R17 M17

M10

R10 AA9

AB9 AD9 AE9 U10

D23 G22

G24 G25 H19

M20 N22

R19 R22 R24 R25 H20 U22

M14 N13

R11 R14

U14 U11 U15

K16 L16

P16 T16

F20 E21

B23 A23

Y20 V18 T17 P17

J10 P10 K10

L10 W9

H9

T10

Y9

F9

G9

A25 E22

J22 L17 L22 L24 L25

P20

V19

Y21

L12

P12 P15

T12

V12

Y18

K11

PART 5/6

VDDHT_2 VDDHT_3 VDDHT_4 VDDHT_5 VDDHT_6 VDDHT_7

VDDHTRX_1 VDDHTRX_2 VDDHTRX_3 VDDHTRX_4 VDDHTRX_5 VDDHTRX_6 VDDHTRX_7

VDDHTTX_1 VDDHTTX_2 VDDHTTX_3 VDDHTTX_4 VDDHTTX_5 VDDHTTX_6 VDDHTTX_7 VDDHTTX_8 VDDHTTX_9 VDDHTTX_10 VDDHTTX_11 VDDHTTX_12 VDDHTTX_13

VDDA18PCIE_1 VDDA18PCIE_2 VDDA18PCIE_3 VDDA18PCIE_4 VDDA18PCIE_5 VDDA18PCIE_6 VDDA18PCIE_7 VDDA18PCIE_8 VDDA18PCIE_9 VDDA18PCIE_10 VDDA18PCIE_11 VDDA18PCIE_12 VDDA18PCIE_13 VDDA18PCIE_14 VDDA18PCIE_15

VDD18_1 VDD18_2 VDD18_MEM1(NC) VDD18_MEM2(NC)

RS780M_FCBGA528 RS780MCR3@

U3F

VSSAHT1 VSSAHT2 VSSAHT3 VSSAHT4 VSSAHT5 VSSAHT6 VSSAHT7 VSSAHT8 VSSAHT9 VSSAHT10 VSSAHT11 VSSAHT12 VSSAHT13 VSSAHT14 VSSAHT15 VSSAHT16 VSSAHT17 VSSAHT18 VSSAHT19 VSSAHT20 VSSAHT21 VSSAHT22 VSSAHT23 VSSAHT24 VSSAHT25 VSSAHT26 VSSAHT27

VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34

RS780M_FCBGA528 RS780MCR3@

PART 6/6

POWER

GROUND

VDDPCIE_1 VDDPCIE_2 VDDPCIE_3 VDDPCIE_4 VDDPCIE_5 VDDPCIE_6 VDDPCIE_7 VDDPCIE_8

VDDPCIE_9 VDDPCIE_10 VDDPCIE_11 VDDPCIE_12 VDDPCIE_13 VDDPCIE_14 VDDPCIE_15 VDDPCIE_16 VDDPCIE_17

VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8

VDDC_9 VDDC_10 VDDC_11 VDDC_12 VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22

VDD_MEM1(NC) VDD_MEM2(NC) VDD_MEM3(NC) VDD_MEM4(NC) VDD_MEM5(NC) VDD_MEM6(NC)

VDD33_1(NC) VDD33_2(NC)

VSSAPCIE1 VSSAPCIE2 VSSAPCIE3 VSSAPCIE4 VSSAPCIE5 VSSAPCIE6 VSSAPCIE7 VSSAPCIE8

VSSAPCIE9 VSSAPCIE10 VSSAPCIE11 VSSAPCIE12 VSSAPCIE13 VSSAPCIE14 VSSAPCIE15 VSSAPCIE16 VSSAPCIE17 VSSAPCIE18 VSSAPCIE19 VSSAPCIE20 VSSAPCIE21 VSSAPCIE22 VSSAPCIE23 VSSAPCIE24 VSSAPCIE25 VSSAPCIE26 VSSAPCIE27 VSSAPCIE28 VSSAPCIE29 VSSAPCIE30 VSSAPCIE31 VSSAPCIE32 VSSAPCIE33 VSSAPCIE34 VSSAPCIE35 VSSAPCIE36 VSSAPCIE37 VSSAPCIE38 VSSAPCIE39 VSSAPCIE40

VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9

VSS10

< Main IO power for PCI-E graphics, SB, and GPP interfaces >

+VDDA11PCIE

A6 B6 C6

VDDA_12=2.5A

D6 E6 F6 G7 H8 J9 K9 M9 L9 P9 R9 T9 V9 U9

K12 J14 U16 J11 K15 M12 L14 L11 M13 M15 N12 N14 P11 P13 P14 R12 R15 T11 T15 U12 T14 J16

< Isolated power for side-port memory interface >

AE10 AA11 Y11 AD10 AB10 AC10

H11

< 3.3V IO power >

H12

A2 B1 D3 D5 E4 G1 G2 G4 H7 J4 R7 L1 L2 L4 L7 M6 N4 P6 R1 R2 R4 V7 U4 V8 V6 W1 W2 W4 W7 W8 Y6 AA4 AB5 AB1 AB7 AC3 AC4 AE1 AE4 AB2

AE14 D11 G8 E14 E15 J15 J12 K14 M11 L15

C2230.1U_0402_16V7K C2230.1U_0402_16V7K

C2240.1U_0402_16V7K C2240.1U_0402_16V7K

2

1

C2470.1U_0402_16V7K C2470.1U_0402_16V7K

C2400.1U_0402_16V7K C2400.1U_0402_16V7K

2

1

C250

0.1U_0402_16V4Z

2

L17

1 2

FBMA-L11-201209-221LMA30T_0805

C2211U_0402_6.3V4Z C2211U_0402_6.3V4Z

C2201U_0402_6.3V4Z C2201U_0402_6.3V4Z

C2221U_0402_6.3V4Z C2221U_0402_6.3V4Z

1

2

C2310.1U_0402_16V7K C2310.1U_0402_16V7K

C2300.1U_0402_16V7K C2300.1U_0402_16V7K

2

1

2

C21110U_0805_10V4Z C21110U_0805_10V4Z

C21210U_0805_10V4Z C21210U_0805_10V4Z

VDD_CORE:GM=5A/PM=10A< Core power >

C2440.1U_0402_16V7K C2440.1U_0402_16V7K

C2320.1U_0402_16V7K C2320.1U_0402_16V7K

2

1

C253

0.1U_0402_16V4Z

Change L90 to bead for EMI

+NB_CORE

1 2

FBMA-L11-201209-121LMA40T_0805

1

C24510U_0805_10V4Z C24510U_0805_10V4Z

C23310U_0805_10V4Z C23310U_0805_10V4Z

2

C234330U_D2E_2.5VM+C234330U_D2E_2.5VM

+

1 2

2

+3VS

L90

PJP3

PAD-OPEN 4x4m

C2191U_0402_6.3V4Z C2191U_0402_6.3V4Z

1

2

C2430.1U_0402_16V7K C2430.1U_0402_16V7K

C2420.1U_0402_16V7K C2420.1U_0402_16V7K

C2410.1U_0402_16V7K C2410.1U_0402_16V7K

2

1

+1.1VS

/

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009-02-12 2009-02-12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

RS780M PWR / GND

LA-5831P

14 44Wednesday, August 12, 2009

E

1.0Custom

A

B

C

D

E

< RS780 DFT_GPIO5 mux at CRT_VSYNC pull High to 3K >

SI2: Change to 3K pull high

R101

R101 3K_0402_5%

3K_0402_5%

UMA_CRT_VSYNC<12,17>

1 1

12

R102

R102 3K_0402_5%@

3K_0402_5%@

12

< RS780 use register to control PCI-E configure >

< RS780 DFT_GPIO1 >

R104

R104 150_0402_1%@

150_0402_1%@

PLT_RST# <12,20,26,27,31,32>

D4

D4 CH751H-40PT_SOD323-2@

CH751H-40PT_SOD323-2@

1 2

AUX_CAL<12>

2 2

SUS_STAT#<12,21>

2 1

< RS780 use HSYNC to enable SIDE PORT (internal pull high) >

< DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb >

Enables the Test Debug Bus using GPIO.

1 : Enable (RX780, RS780)

+3VS

0 : Disable (RX780, RS780)

PIN: RS740-->RS780_AUX_CAL; RX780-->NB_TV_C; RS780--> VSYNC#

< DFT_GPIO[4:2] : STRAP_PCIE_GPP_CFG[2:0] >

These pin straps are used to configure PCI-E GPP mode. 000 : 00001 001 : 00010 010 : 01011 011 : 00100 100 : 01010 101 : 01100 111 : 01011

< DFT_GPIO1 : LOAD_EEPROM_STRAPS >

Selects Loading of STRAPS from EPROM

1 : Bypass the loading of EEPROM straps and use Hardware Default Values 0 : I2C Master can load strap values from EEPROM if connected, or use default values if not connected

RS740/RX780: DFT_GPIO1 RS780:SUS_STAT

< DFT_GPIO0: STRAP_DEBUG_BUS_PCIE_ENABLEb >

RX780: Enables the Test Debug Bus using PCIE bus

R125

R125 3K_0402_5%

3K_0402_5%

UMA_CRT_HSYNC<12,17>

12

+3VS

1 : Disable ( Can still be enabled using nbcfg register access ) 0 : Enable

RS780: Enables Side port memory ( RS780 use HSYNC#)

1. Disable (RS780) 0 : Enable (RS780)

3 3

4 4

/

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009-02-12 2009-02-12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

RS780M STRAPS

LA-5831P

15 44Wednesday, August 12, 2009

E

1.0Custom

A

C458

0.1U_0402_16V4Z

+3VS_CLK

R179

@

1 2

+VDDCLK_IO

1

C452

C452 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

C459

0.1U_0402_16V4Z

2

SEL_SATA

1

C453

0.1U_0402_16V4Z

2

1

C460

0.1U_0402_16V4Z

2

SB LINK SB SRC

WLAN

1

C454

0.1U_0402_16V4Z

2

1

C461

0.1U_0402_16V4Z

2

SMB_CK_CLK0<9,10,21> SMB_CK_DAT0<9,10,21>

CLK_SBLINK_BCLK#<12>

CLK_SBLINK_BCLK<12> CLK_SBSRC_BCLK# <20>

CLK_PCIE_MCARD2#<27>

CLK_PCIE_MCARD2<27>

+3VS_CLK

+1.2V_HT

R168 0_0805_5%R168 0_0805_5%

1 2

+3VS_CLK

1 1

2 2

3 3

1

2

8.2K_0402_5%

B

1

C455

0.1U_0402_16V4Z

2

C464

22P_0402_50V8J

C

27M_SEL

SEL_SATA

64

65

66

VSS_REF

REF_1/SEL_SATA

REF_0/SEL_HTT66

+3VS_CLK

CLK_48M_CR_R

CLK_48M_USB_R

NB_OSC_14.318M_R

+3VS_CLK

63

62

61

60

59

58

57

VSS_HTT

VDD_HTT

VDD_REF

HTT_0/66M_0

HTT_0#/66M_1

REF_2/SEL_27

33

1

C444

C444 22U_0805_6.3V6M

22U_0805_6.3V6M

2

CLK_NBHT

CLK_NBHT#

CLK_CPU_BCLK_R

CLK_CPU_BCLK_R#

56

55

PD#

CPU_K8_0

CPU_K8_0#

VDD_CPU

VDD_CPU_I/O

VSS_CPU CLKREQ_1# CLKREQ_2#

VDD_A VSS_A

VSS_SATA

SRC_6/SATA

SRC_6#/SATA#

VDD_SATA CLKREQ_3# CLKREQ_4#

SB_SRC_SLOW#

SB_SRC_0

SB_SRC_0#

VDD_SB_SRC

VDD_SB_SRC_IO

SLG8SP626VTR_QFN72_10x10

1

C445

0.1U_0402_16V7K

2

R970 33_0402_5%R970 33_0402_5%

1 2

R170 33_0402_5%R170 33_0402_5%

1 2

R379 158_0402_1%R379 158_0402_1%

1 2

TIGRIS@

R971 33_0402_5%

1 2

R174 8.2K_0402_5%R174 8.2K_0402_5%

1 2

C629 1U_0402_6.3V4ZC629 1U_0402_6.3V4Z

1 2

R946 0_0402_5%R946 0_0402_5%

R945 0_0402_5%R945 0_0402_5%

54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37

+3VS_CLK +VDDCLK_IO

CLKREQ_NCARD# CLKREQ_NCARD# CLKREQ_MCARD2#

+3VS_CLK

CLK_SBSRC_BCLK#

+3VS_CLK

R372 10K_0402_5%R372 10K_0402_5%

1 2

+3VS_CLK +VDDCLK_IO

+3VS

R167 0_0805_5%R167 0_0805_5%

1 2

1

C456

0.1U_0402_16V4Z

2

CLK_XTAL_OUT CLK_XTAL_IN

Y2

12

14.31818MHZ_20P_6X1430004201

1

C465

C465 22P_0402_50V8J

2

+3VS_CLK

+VDDCLK_IO

+3VS_CLK

+VDDCLK_IO

22P_0402_50V8J

2

SMB_CK_CLK0 SMB_CK_DAT0

CLK_SBLINK_BCLK# CLK_SBSRC_BCLK CLK_SBLINK_BCLK

CLK_PCIE_MCARD2# CLK_PCIE_MCARD2

U10

1

SCL

2

SDA

3

VDD_DOT

4

SRC_7#/27M

5

SRC_7/27M_SS

6

VSS_DOT

7

SRC_5#

8

SRC_5

9

SRC_4#

10

SRC_4

11

VSS_SRC

12

VDD_SRC_IO

13

SRC_3#

14

SRC_3

15

SRC_2#

16

SRC_2

17

VDD_SRC

18

VDD_SRC_IO

1

C457

0.1U_0402_16V4Z

2

+3VS_CLK

CLK_XTAL_OUT

CLK_XTAL_IN

67

68

69

71

72

73

GND

VSS_48

VDD_48

XTAL_IN

48MHz_17048MHz_0

XTAL_OUT

VSS_SRC19SRC_1#20SRC_121SRC_0#22SRC_023CLKREQ_0#24ATIGCLK_2#25ATIGCLK_226VSS_ATIG27VDD_ATIG_IO28VDD_ATIG29ATIGCLK_1#30ATIGCLK_131ATIGCLK_0#32VSS_SB_SRC36SB_SRC_135SB_SRC_1#34ATIGCLK_0

D

1

C446

0.1U_0402_16V7K

2

R380 90.9_0402_1%R380 90.9_0402_1%

1 2

CLK_SBSRC_BCLK <20>

+3VS_CLK

1

C447

0.1U_0402_16V7K

2

R186

@

261_0402_1%

1 2

CLKREQ_MCARD2# <27>

RS780 1.1V 158R/90.9R

1

C448

0.1U_0402_16V7K

2

1

C449

0.1U_0402_16V7K

2

CLK_48M_CR <28>

CLK_48M_USB <21>

NB_OSC_14.318M <12>

SB_14.318M <20>

CLK_NBHT <12>

CLK_NBHT# <12>

+3VS_CLK

CLK_CPU_BCLK <7>

CLK_CPU_BCLK# <7>

Reserve Clock Request for NewCard

CLKREQ_MCARD2# CLKREQ_LAN#

OSC_14M_NB

E

1

C450

0.1U_0402_16V7K

2

1

C451

C451 1U_0402_6.3V4Z

1U_0402_6.3V4Z

2

< To Card Reader > < To SB700 USB host > < To RS780 Clock block >

< To RS780 Clock block >

< To CPU >

+3VS_CLK

1 2

R324 8.2K_0402_5%R324 8.2K_0402_5%

1 2

R325 8.2K_0402_5%R325 8.2K_0402_5%

1 2

R390 8.2K_0402_5%R390 8.2K_0402_5%

R181

8.2K_0402_5%

SEL_SATA

4 4

1 2

1*0configure as SATA output

configure as normal SRC(SRC_6) output

* default

Use voltage divider resistor R379 & R380 to pull low

NB_OSC_14.318M

configure as single-ended 66MHz output1

*0 configure as differential 100MHz output

* default

A

1 2

27M_SEL

R180

8.2K_0402_5%

27M_SEL

configure as 27M and 27M_SS output

1 * 0 configure as SRC_7 output

* default

/

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3VS_CLK

+VDDCLK_IO

CLKREQ_LAN# CLK_PCIE_LAN CLK_PCIE_LAN#

C

NBGFX_CLK <12> NBGFX_CLK# <12>

CLKREQ_LAN# <26> CLK_PCIE_LAN <26> CLK_PCIE_LAN# <26>

2009-02-12 2009-02-12

NB GFX

LAN

Compal Secret Data

Deciphered Date

D

NB CLOCK INPUT TABLE

NB CLOCKS HT_REFCLKP HT_REFCLKN REFCLK_P REFCLK_N GFX_REFCLK GPP_REFCLK GPPSB_REFCLK 100M DIFF 100M DIFF

Size Document Number Rev

Date: Sheet of

RX780 RS780

100M DIFF 100M DIFF

14M SE (1.8V) 14M SE (1.1V) NC vref

100M DIFF 100M DIFF

Compal Electronics, Inc.

Title

Compal Electronics, Inc.

100M DIFF 100M DIFF

100M DIFF(IN/OUT)*

NC or 100M DIFF OUTPUT

Clock Generator

LA-5831P

E

1.0Custom

16 44Wednesday, August 12, 2009

1.0Custom

A

< CRT CONNECTOR >

1 1

UMA_CRT_R<12>

UMA_CRT_G<12>

UMA_CRT_B<12>

12

R214

R214 140_0402_1%

140_0402_1%

12

R211

R211 150_0402_1%

150_0402_1%

B

12

R217

R217 150_0402_1%

150_0402_1%

1

C471

C471 6P_0402_50V8D

6P_0402_50V8D

2

1

C859

C859 6P_0402_50V8D

6P_0402_50V8D

2

L47

1 2

L48

1 2

L49

1 2

1

C469

C469 6P_0402_50V8D

6P_0402_50V8D

2

C

NBQ100505T-800Y_0402

1

C858

C858 6P_0402_50V8D

6P_0402_50V8D

2

D

+5VS

D36

2 3

RB491D_SOT23-3

1

D35

DAN217_SC59@

2

3

1

C476

C476 6P_0402_50V8D

6P_0402_50V8D

2

1

D37

DAN217_SC59@

2

3

2

1

C472

C472 6P_0402_50V8D

6P_0402_50V8D

2

+R_CRT_VCC

1

D34

D34 DAN217_SC59@

DAN217_SC59@

+3VS

3

RED_L

GREEN_L

BLUE_L

220P_0402_50V7K

+CRT_VCC

C706

F2

1.1A_6V_MINISMDC110F-2

21

1

2

RED_L D_DDCDATA

GREEN_L HSYNC

BLUE_L VSYNC

D_DDCCLK

E

+CRT_VCC

1

2

JCRT

6

11

1

7

12

2

8

13

3

9

14

4

10

15

5

ALLTO_C10532-11505-L_15P-T

C475

0.1U_0402_16V4Z

@JCRT

@

16

G

17

G

2 2

UMA_CRT_HSYNC<12,15>

UMA_CRT_VSYNC<12,15>

3 3

UMA_CRT_DATA<12>

UMA_CRT_CLK<12>

12

C177

C177 33P_0402_50V8K@

33P_0402_50V8K@

12

C181

C181 33P_0402_50V8K@

33P_0402_50V8K@

C473 0.1U_0402_16V4ZC473 0.1U_0402_16V4Z

1 2

C477 0.1U_0402_16V4ZC477 0.1U_0402_16V4Z

1 2

+3VS

12

R237

4.7K_0402_5%

1 2

R238

4.7K_0402_5%

4.7K_0402_5% R100

RS780 DAC_SCL & SDA is 5V tolerance

4 4

FOR EMI

+CRT_VCC

1 2

1

5

P

4

OE#

A2Y

G

U14

U14 SN74AHCT1G125GW_SOT353-5

SN74AHCT1G125GW_SOT353-5

3

+CRT_VCC

1 2

1

5

P

4

OE#

A2Y

G

U13

U13 SN74AHCT1G125GW_SOT353-5

SN74AHCT1G125GW_SOT353-5

3

4

+3VS

5

+3VS

2

R972

R972 10K_0402_5%

10K_0402_5%

R973

R973 10K_0402_5%

10K_0402_5%

Q10B

Q10B 2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

3

Q10A

Q10A 2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

61

D_HSYNC

D_VSYNC

L84 10_0402_5%L84 10_0402_5%

1 2

L83 10_0402_5%L83 10_0402_5%

1 2

R100

6.8K_0402_5%

1

C857

C857 470P_0402_50V8J@

470P_0402_50V8J@

2

+CRT_VCC

1

2

1

C474

C474 10P_0402_50V8J@

10P_0402_50V8J@

2

R218

6.8K_0402_5%

C856

C856 470P_0402_50V8J@

470P_0402_50V8J@

HSYNC

VSYNC

1

C470

C470 10P_0402_50V8J@

10P_0402_50V8J@

2

D_DDCDATA

D_DDCCLK

< SYNC SIGNAL >

< Display Data Channel >

/

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009-02-12 2009-02-12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

CRT Connector

LA-5831P

17 44Wednesday, August 12, 2009

E

1.0Custom

A

B

C

D

E

< Int. Camera, USB port 9 >

1 1

C882

1 2

0.1U_0402_16V4Z

12

1

C266

4.7U_0805_10V4Z

2

Int. Camera

R1009

+5VS

0_0603_5% @

JCAM

1

2

3

4

5

6

GND1

7

GND2

ACES_88266-05001

@

CAM@C882

CAM@

+LCD_VDD

+5V_CAM

W=20mils

12

USB20_N9_R_R USB20_P9_R_R

C888

@C888

@

1 2

0.1U_0402_16V4Z

UMA_ENVDD<12>

LCD/PANEL BD. Conn.

+LCD_VDD +3VS

12

R142

R142 150_0603_5%

150_0603_5%

61

Q1A

1 2

Q1A

R668

R668 0_0402_5%

0_0402_5%

2

2N7002DW-T/R7_SOT363-6

ENVDD

12

R144

R144 100K_0402_5%

100K_0402_5%

12

R143

R143 100K_0402_5%

100K_0402_5%

3

Q1B

5

2N7002DW-T/R7_SOT363-6

4

R140

1 2

47K_0402_5%

2

W=60mils

C874

0.1U_0402_16V7K

1

C875

0.01U_0402_25V7K

2

+3VS

S

G

Q2

2

D

AO3413_SOT23

1 3

Inrush current = 0A

1

C263

@

4.7U_0805_10V4Z

2

+LCD_VDD

1

2

W=60mils

C264

0.1U_0402_16V7K

< EMI require >

CAM@

R1030_0402_5%

12

L60

@L60

@

2

USB20_N9<21> USB20_P9<21>

2 2

2

3

WCM-2012-900T_0805

CAM@

1

4

R990_0402_5%

12

USB20_N9_R USB20_P9_R

4

reserve for test, close to JLVDS

LVDS & CAMERA

JLVDS

@JLVDS

@

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 GND

1 3 5 7

9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

GND

68P_0402_50V8J

1 3 5 7 9 11 13 15 17 19 21 23 25

+LCDVDD_R

27 29 31 33 35 37 39 41

C268

UMA_LCD_TXCLK_ACLK+ <12> UMA_LCD_TXCLK_ACLK- <12>

DAC_BRIG <32> INVT_PWM <32>

UMA_LCD_DDC_CLK <12> UMA_LCD_DDC_DAT <12>

+LCD_INV

Rated Current MAX:3000mA

FBMA-L11-201209-221LMA30T_0805

1

C269

0.1U_0402_25V4Z

2

UMA_LCD_TXOUT0_A0+<12> UMA_LCD_TXOUT0_A0-<12>

UMA_LCD_TXOUT0_A1+<12> UMA_LCD_TXOUT0_A1-<12>

UMA_LCD_TXOUT0_A2+<12> UMA_LCD_TXOUT0_A2-<12>

+5V_LVDS_CAM USB20_P9_R

USB20_N9_R

3 3

BKOFF#<32>

R146

10K_0402_5%

BKOFF#

1 2

4 6

8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42

ACES_88242-4001

R10040_0402_5%@R10040_0402_5%

R10050_0402_5%@R10050_0402_5%

12 12

+5VS

USB20_N9_R_R USB20_P9_R_R

12

R1006

0_0603_5%

CAM@

1

2

B+

+5V_LVDS_CAM

12

W=20mils

+5V_LVDS_CAM

1.5A

L8

0_0805_5%

C265

0.1U_0402_16V4Z

+3VS

1

C267

0.1U_0402_16V4Z

2

@ @

L12

For EMI

C707

1 2

220P_0402_50V7K

C708

1 2

220P_0402_50V7K

C709

1 2

220P_0402_50V7K

+3VS

R68 4.7K_0402_5%R68 4.7K_0402_5%

1 2

R69 4.7K_0402_5%R69 4.7K_0402_5%

1 2

UMA_LCD_DDC_CLK

UMA_LCD_DDC_DAT

DAC_BRIG

INVT_PWM

BKOFF#

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009-02-12 2009-02-12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

LCD CONN. / Camera

LA-5831P

18 44Wednesday, August 12, 2009

E

1.0

A

1 1

HDMI_TXD0+<11> HDMI_TXD0-<11> HDMI_TXD1+<11> HDMI_TXD1-<11> HDMI_TXD2+<11> HDMI_TXD2-<11>

HDMI_CLK0+<11> HDMI_CLK0-<11>

C189 0.1U_0402_16V7KHDMI@ C189 0.1U_0402_16V7KHDMI@

1 2

C188 0.1U_0402_16V7KHDMI@ C188 0.1U_0402_16V7KHDMI@

1 2

C190 0.1U_0402_16V7KHDMI@ C190 0.1U_0402_16V7KHDMI@

1 2

C184 0.1U_0402_16V7KHDMI@ C184 0.1U_0402_16V7KHDMI@

1 2

C187 0.1U_0402_16V7KHDMI@ C187 0.1U_0402_16V7KHDMI@

1 2

C191 0.1U_0402_16V7KHDMI@ C191 0.1U_0402_16V7KHDMI@

1 2

C185 0.1U_0402_16V7KHDMI@ C185 0.1U_0402_16V7KHDMI@

1 2

C186 0.1U_0402_16V7KHDMI@ C186 0.1U_0402_16V7KHDMI@

1 2

HDMI_TX0+ HDMI_TX0HDMI_TX1+ HDMI_TX1HDMI_TX2+

HDMI_TX2-

HDMI_CLK+ HDMI_CLK-

B

C

HDMI@

D53

D53 PMEG2010AEH_SOD123

PMEG2010AEH_SOD123

2 1

+5VS

Vf=0.25V when If=55mA

D

+HDMI_5V_OUT_M +HDMI_5V_OUT

F3

HDMI@ F3

HDMI@

1.1A_6V_MINISMDC110F-2

2 1

1

C258

HDMI@

0.1U_0402_16V7K

2

E

< HDMI DDC channel to device >

< HDMI Connector >

JHDMI

19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1

TYCO_1939864-1_19P

1 2 1 2

B

HDMI_HPD

HDMI_SDATA HDMI_SCLK

HDMI_R_CKHDMI_R_CK+

HDMI_R_D0HDMI_R_D0+

HDMI_R_D1HDMI_R_D1+

HDMI_R_D2HDMI_R_D2+

HDMI@ R307

HDMI@

HDMI@ R315

HDMI@

HDMI@ R304

HDMI@

HDMI@ R172

HDMI@

HDMI@ R297

HDMI@

HDMI@ R173

HDMI@

HDMI@ R141

HDMI@

HDMI@ R139

HDMI@

R307 715_0402_1%

715_0402_1%

715_0402_1% R315

R304 715_0402_1%

715_0402_1%

715_0402_1% R172

R297 715_0402_1%

715_0402_1%

715_0402_1% R173

R141 715_0402_1%

715_0402_1%

715_0402_1% R139

+HDMI_5V_OUT

2 2

< EMI solution >

R616

@ R616

HDMI_CLK-

HDMI_TX0-

3 3

HDMI_TX0+

HDMI_TX1-

HDMI_TX1+

4 4

HDMI_TX2+

@

1 2

L85

HDMI@L85

HDMI@

1

4

WCM-2012-900T_0805

@ R617

@

1 2

@ R618

@

1 2

L86

HDMI@L86

HDMI@

4

1

WCM-2012-900T_0805

@ R619

@

1 2

@ R620

@

1 2

L87

HDMI@L87

HDMI@

1

4

WCM-2012-900T_0805

@ R621

@

1 2

@ R623

@

1 2

L88

HDMI@L88

HDMI@

4

1

WCM-2012-900T_0805

@ R624

@

1 2

A

0_0402_5%

2

3

R617 0_0402_5%

0_0402_5% R618

0_0402_5%

3

2

R619 0_0402_5%

0_0402_5% R620

0_0402_5%

2

3

R621 0_0402_5%

0_0402_5% R623

0_0402_5%

3

2

R624 0_0402_5%

0_0402_5%

HDMI_R_CK-

HDMI_R_CK+HDMI_CLK+

HDMI_R_D0-

HDMI_R_D0+

HDMI_R_D1-

HDMI_R_D1+

HDMI_R_D2-HDMI_TX2-

HDMI_R_D2+

< Termination resistor >

HDMI_R_CK+ HDMI_R_CK-

HDMI_R_D0HDMI_R_D0+

HDMI_R_D1HDMI_R_D1+

HDMI_R_D2+ HDMI_R_D2-

HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKCK_shield CK+ D0D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+

HDMI@

6 1

2

5

3

HDMI@

6 1

2

5

3

HDMI@

@JHDMI

@

20

GND

21

GND

22

GND

23

GND

Q136A

2N7002DW-7-F_SOT363-6

+5VS

Q136B

4

2N7002DW-7-F_SOT363-6

Q137A

2N7002DW-7-F_SOT363-6

+5VS

Q137B

4

2N7002DW-7-F_SOT363-6

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

HDMIDAT_UMA<12>

HDMICLK_UMA<12>

< Hot-plug detection & level shift >

2009-02-12 2009-02-12

HDMI@

R176

4.7K_0402_5%

2

C851

HDMI@

0.1U_0402_16V4Z

1

Compal Secret Data

12

+HDMI_5V_OUT

Deciphered Date

HDMI@

R209

4.7K_0402_5%

1 2

1

5

P

OE#

A2Y

G

U39

U39 SN74AHCT1G125GW_SOT353-5

SN74AHCT1G125GW_SOT353-5

3

HDMI@

3 1

4

D

HPD

2

SGD

HDMI@

Q139

Q139 BSH111_SOT23-3

BSH111_SOT23-3

+3VS

+3VS+3VS

HDMI@

R210

2.2K_0402_5%

2

HDMI@

Q140

Q140 BSH111_SOT23-3

BSH111_SOT23-3

3 1

SGD

R628

HDMI@

100K_0402_5%

1 2

12

R588

2.2K_0402_5%

HDMI@

HPD <12,21>

R977

R977 100K_0402_5%

100K_0402_5%

1 2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

1 2

HDMI_HPD

2

C850

HDMI@

0.1U_0402_16V4Z

1

HDMI

+HDMI_5V_OUT

HDMI@

R236

2.2K_0402_5%

1 2

LA-5831P

E

HDMI_SDATA

HDMI_SCLK

19 44Wednesday, August 12, 2009

1.0Custom

< Place MOSFET close to HDMI connector >

A

1 1

< x4 PCIE A-link To NB >

< x4 PCIE A-link from NB >

2 2

3 3

R319 10K_0402_5%R319 10K_0402_5%

+3VS

4 4

1

C509

0.1U_0402_16V7K

2

+SB_VBAT

1

2

1 2

C510

C510 1U_0402_6.3V4Z

1U_0402_6.3V4Z

A

R316

R316 120_0402_5%

120_0402_5%

W=20mils

2

JUMP_43X39@J1JUMP_43X39@

1

1 2

J1

12

R317

R317 120_0402_5%

120_0402_5%

H_PROCHOT#

+RTCVCC

1 2

B

CLK_SBSRC_BCLK<16> CLK_SBSRC_BCLK#<16>

C643

C643 18P_0402_50V8J

18P_0402_50V8J

C652

C652 18P_0402_50V8J

18P_0402_50V8J

R184

R184 1K_0402_5%

1K_0402_5%

12

0.1U_0402_16V7K

B

SB_RX0P<11> SB_RX0N<11> SB_RX1P<11> SB_RX1N<11> SB_RX2P<11> SB_RX2N<11> SB_RX3P<11> SB_RX3N<11>

SB_TX0P<11> SB_TX0N<11> SB_TX1P<11> SB_TX1N<11> SB_TX2P<11> SB_TX2N<11> SB_TX3P<11> SB_TX3N<11>

+PCIE_VDDR

+1.2V_HT

SB_14.318M<16>

12

CPU_LDT_REQ#<7,12> H_PROCHOT#<7>

H_PWRGD<7,42>

LDT_STOP#<7,12>

LDT_RST#<7>

C297

C506

0.1U_0402_16V4Z

12

NB_RST#_R

L53 BLM18PG121SN1D_0603L53 BLM18PG121SN1D_0603

1 2

+3VALW

2 1

R312 33_0402_5%@R312 33_0402_5%@

C492 0.1U_0402_16V7KC492 0.1U_0402_16V7K

1 2

C493 0.1U_0402_16V7KC493 0.1U_0402_16V7K

1 2

C494 0.1U_0402_16V7KC494 0.1U_0402_16V7K

1 2

C495 0.1U_0402_16V7KC495 0.1U_0402_16V7K

1 2

C496 0.1U_0402_16V7KC496 0.1U_0402_16V7K

1 2

C497 0.1U_0402_16V7KC497 0.1U_0402_16V7K

1 2

C498 0.1U_0402_16V7KC498 0.1U_0402_16V7K

1 2

C499 0.1U_0402_16V7KC499 0.1U_0402_16V7K

1 2

R305 562_0402_1%R305 562_0402_1% R306 2.05K_0402_1%R306 2.05K_0402_1%

Close to SB

Y3

4

R389

R389 20M_0603_5%

20M_0603_5%

1

2

D10

3

2

BAS40-04_SOT23-3

+CHGRTC

OUT

1

IN

32.768KHZ_12.5P_1TJS125BJ4A421P

+RTCBATT

1

C

U16

U16 NC7SZ08P5X_NL_SC70-5

NC7SZ08P5X_NL_SC70-5

5

P

B A

1

2

PLT_RST#

4

Y

G

3

12

12 12

C504

2.2U_0603_6.3V4Z

CLK_SBSRC_BCLK CLK_SBSRC_BCLK#

SB_14.318M

3

NC

2

NC

CPU_LDT_REQ# H_PROCHOT# H_PWRGD LDT_STOP# LDT_RST#

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

SB_RX0P_C SB_RX0N_C SB_RX1P_C SB_RX1N_C SB_RX2P_C SB_RX2N_C SB_RX3P_C SB_RX3N_C

SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N SB_TX3P SB_TX3N

+SB_PCIEVDD

SB_32KHI

SB_32KHO

C

PLT_RST# <12,15,26,27,31,32>

U15A

N2

A_RST#

V23

PCIE_TX0P

V22

PCIE_TX0N

V24

PCIE_TX1P

V25

PCIE_TX1N

U25

PCIE_TX2P

U24

PCIE_TX2N

T23

PCIE_TX3P

T22

PCIE_TX3N

U22

PCIE_RX0P

U21

PCIE_RX0N

U19

PCIE_RX1P

V19

PCIE_RX1N

R20

PCIE_RX2P

R21

PCIE_RX2N

R18

PCIE_RX3P

R17

PCIE_RX3N

T25

PCIE_CALRP

T24

PCIE_CALRN

P24

PCIE_PVDD

P25

PCIE_PVSS

N25

PCIE_RCLKP/NB_LNK_CLKP

N24

PCIE_RCLKN/NB_LNK_CLKN

K23

NB_DISP_CLKP

K22

NB_DISP_CLKN

M24

NB_HT_CLKP

M25

NB_HT_CLKN

P17

CPU_HT_CLKP

M18

CPU_HT_CLKN

M23

SLT_GFX_CLKP

M22

SLT_GFX_CLKN

J19

GPP_CLK0P

J18

GPP_CLK0N

L20

GPP_CLK1P

L19

GPP_CLK1N

M19

GPP_CLK2P

M20

GPP_CLK2N

N22

GPP_CLK3P

P22

GPP_CLK3N

L18

25M_48M_66M_OSC

J21

25M_X1

J20

25M_X2

A3

X1

B3

X2

F23

ALLOW_LDTSTP

F24

PROCHOT#

F22

LDT_PG

G25

LDT_STP#

G24

LDT_RST#

218S7EALA11FG_BGA528_SB700

2009-02-12 2009-02-12

SB700

Part 1 of 5

PCI EXPRESS INTERFACE

RTC XTAL

CPU

Compal Secret Data

Deciphered Date

PCI CLKS

PCI INTERFACE

CLOCK GENERATOR

LPC

LDRQ1#/GNT5#/GPIO68

BMREQ#/REQ5#/GPIO65

INTRUDER_ALERT#

RTC

PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4

PCICLK5/GPIO41

PCIRST#

AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30

AD31 CBE0# CBE1# CBE2# CBE3#

FRAME#

DEVSEL#

IRDY#

TRDY# STOP#

PERR# SERR# REQ0# REQ1#

REQ2# REQ3#/GPIO70 REQ4#/GPIO71

GNT0# GNT1#

GNT2# GNT3#/GPIO72 GNT4#/GPIO73

CLKRUN#

LOCK#

INTE#/GPIO33 INTF#/GPIO34 INTG#/GPIO35 INTH#/GPIO36

LPCCLK0 LPCCLK1

LAD0 LAD1 LAD2 LAD3

LFRAME#

LDRQ0#

SERIRQ

RTCCLK

VBAT

SB700R3@

AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9

PAR

D

CLK_PCI_EC

CLK_PCI_SIO2

P4 P3

PCI_CLK2

P1

PCI_CLK3

P2

PCI_CLK4

T4

PCI_CLK5

T3

N1

U2 P7 V4 T1 V3 U1 V1 V2 T2 W1 T9 R6 R7 R5 U8 U5 Y7 W8 V9 Y8 AA8 Y4 Y3

PCI_AD23

Y2

PCI_AD24

AA2

PCI_AD25

AB4

PCI_AD26

AA1

PCI_AD27

AB3

PCI_AD28

AB2 AC1 AC2 AD1 W2 U7 AA7 Y1 AA6 W5 AA5 Y5 U6 W6 W4 V7 AC3 AD4 AB7 AE6 AB6 AD2 AE4 AD5 AC6 AE5 AD6 V5

AD3 AC4 AE2 AE3

CLK_PCI_EC1

G22

CLK_PCI_SIOC

E22

LPC_AD0

H24

LPC_AD1

H23

LPC_AD2

J25

LPC_AD3

J24 H25

LPC_FRAME#_SB

H22 AB8 AD7 V15

SERIRQ RTC_CLK

C3 C2 B2

+SB_VBAT

D

E

C501

R303

R303 100_0402_5%@

100_0402_5%@

1 2

R369

R369 100_0402_5%@

100_0402_5%@

1 2

PCI_CLK2 <24> PCI_CLK3 <24> PCI_CLK4 <24> PCI_CLK5 <24>

PCI_AD23 <24> PCI_AD24 <24> PCI_AD25 <24> PCI_AD26 <24> PCI_AD27 <24>

T18PAD T18PAD T26PAD T26PAD

T15PAD T15PAD

T16PAD T16PAD

R308 22_0402_5%R308 22_0402_5%

1 2

R310 22_0402_5%R310 22_0402_5%

1 2

LPC_AD0 <31,32> LPC_AD1 <31,32> LPC_AD2 <31,32> LPC_AD3 <31,32>

R979 0_0402_5%

1 2

TIGRIS@

RTC_CLK <24>

Title

SB700 - PCIE / PCI / ACPI / LPC / RTC

Size Document Number Rev

Custom

Date: Sheet of

PCI_AD28 <24>

EC & TPM &Debug

D84

D84 CH751H-40PT_SOD323-2PUMA@

CH751H-40PT_SOD323-2PUMA@

21

SERIRQ <31,32>

STRAP PIN

Compal Electronics, Inc.

C501 100P_0402_50V8J@

100P_0402_50V8J@

1 2

C503

C503 100P_0402_50V8J@

100P_0402_50V8J@

1 2

CLK_PCI_EC <24,32> CLK_PCI_SIO2 <24,31>

PUMA@ R978

PUMA@

LA-5831P

E

R978 300_0402_5%

300_0402_5%

12

LPC_FRAME# <31,32>

20 44Wednesday, August 12, 2009

+3VS

1.0

A

B

C

D

E

+3VALW

1 2

1 1

1 2

Reserve pull-high for EXP_CPPE#

+3VS

1 2

+3VALW

1 2

2 2

+3VS

3 3

1 2

R320

2.2K_0402_5%@

2.2K_0402_5%@ R321

R321

2.2K_0402_5%@

2.2K_0402_5%@ R322

R322

2.2K_0402_5%@

2.2K_0402_5%@ R561

R561 1K_0402_5%

1K_0402_5%

12

R330

R330 100K_0402_5%@

100K_0402_5%@

12

R328

1.2K_0402_5%

1.2K_0402_5% R329

R329

1.2K_0402_5%

R331

2.2K_0402_5%

2.2K_0402_5% R332

R332

2.2K_0402_5%

R327

R327 100K_0402_5%

100K_0402_5%

12

R388

4.7K_0402_5%

SB_TEST2

SB_TEST1

SB_TEST0

LAN_WAKE#

EXP_CPPE#

SMB_CK_CLK0

SMB_CK_DAT0

SMB_CK_CLK1

SMB_CK_DAT1

EC_RSMRST#

SUS_STAT#

<S0>

< S0~ S5 ASF only >

STRAP PIN

HDA_BITCLK_CODEC<29> HDA_BITCLK_MDC<31> HDA_SDOUT_MDC<31>

HDA_SDOUT_CODEC<29> HDA_SDIN0<29> HDA_SDIN1<31>

HDA_SYNC_MDC<31>

HDA_SYNC_CODEC<29> HDA_RST#_CODEC<29>

HDA_RST#_MDC<31> HDARST#<24>

HPD<12,19>

For EMI Close to U15

PM_SLP_S3#<32> PM_SLP_S5#<32> PBTN_OUT#<32> SB_PWRGD<32,42> SUS_STAT#<12,15>

GATEA20<32> KB_RST#<32> EC_SCI#<32> EC_SMI#<32>

LAN_WAKE#<26>

H_THERMTRIP#<7> NB_PWRGD<12>

EC_RSMRST#<32>

SB_SPKR<29> SMB_CK_CLK0<9,10,16> SMB_CK_DAT0<9,10,16>

SMB_CK_CLK1<27>

SMB_CK_DAT1<27>

R400

@ R400

@

4.7K_0402_5%

1 2

+3VS

HDMI@ R980

HDMI@

1 2

R980 0_0402_5%

0_0402_5%

For BIOS utility support

R333 33_0402_5%R333 33_0402_5%

1 2

R334 33_0402_5%MDC@R334 33_0402_5%MDC@

1 2

R335 33_0402_5%MDC@R335 33_0402_5%MDC@

1 2

R336 33_0402_5%R336 33_0402_5%

1 2

R337 33_0402_5%MDC@R337 33_0402_5%MDC@

1 2

R338 33_0402_5%R338 33_0402_5%

1 2

R339 33_0402_5%R339 33_0402_5%

1 2

R340 33_0402_5%MDC@R340 33_0402_5%MDC@

1 2

1

C619

C619 100P_0402_50V8J

100P_0402_50V8J

2

Reserve for EMI request

R311

U15D

SB700

E1

PCI_PME#/GEVENT4#

E2

RI#/EXTEVNT0#

H7

SLP_S2/GPM9#

F5

PM_SLP_S5# PBTN_OUT# SB_PWRGD SUS_STAT# SB_TEST2 SB_TEST1 SB_TEST0 GATEA20 KB_RST# EC_SCI# EC_SMI#

LAN_WAKE# H_THERMTRIP#

NB_PWRGD EC_RSMRST#

SB_SPKR SMB_CK_CLK0 SMB_CK_DAT0 SMB_CK_CLK1 SMB_CK_DAT1

HPD_R

EC_LID_OUT#<32>

USB_OC#2<25,32> USB_OC#0<25,32>

EC_LID_OUT# EXP_CPPE#

HDA_BITCLK HDA_SDOUT

HDA_SDIN0 HDA_SDIN1

HDA_SYNC

HDARST#

SLP_S3#

G1

SLP_S5#

H2

PWR_BTN#

H1

PWR_GOOD

K3

SUS_STAT#

H5

TEST2

H4

TEST1

H3

TEST0

Y15

GA20IN/GEVENT0#

W15

KBRST#/GEVENT1#

K4

LPC_PME#/GEVENT3#

K24

LPC_SMI#/EXTEVNT1#

F1

S3_STATE/GEVENT5#

J2

SYS_RESET#/GPM7#

H6

WAKE#/GEVENT8#

F2

BLINK/GPM6#

J6

SMBALERT#/THRMTRIP#/GEVENT2#

W14

NB_PWRGD

D3

RSMRST#

AE18

SATA_IS0#/GPIO10

AD18

CLK_REQ3#/SATA_IS1#/GPIO6

AA19

SMARTVOLT1/SATA_IS2#/GPIO4

W17

CLK_REQ0#/SATA_IS3#/GPIO0

V17

CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39

W20

CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40

W21

SPKR/GPIO2

AA18

SCL0/GPOC0#

W18

SDA0/GPOC1#

K1

SCL1/GPOC2#

K2

SDA1/GPOC3#

AA20

DDC1_SCL/GPIO9

Y18

DDC1_SDA/GPIO8

C1

LLB#/GPIO66

Y19

SMARTVOLT2/SHUTDOWN#/GPIO5

G5

DDR3_RST#/GEVENT7#

B9

USB_OC6#/IR_TX1/GEVENT6#

B8

USB_OC5#/IR_TX0/GPM5#

A8

USB_OC4#/IR_RX0/GPM4#

A9

USB_OC3#/IR_RX1/GPM3#

E5

USB_OC2#/GPM2#

F8

USB_OC1#/GPM1#

E4

USB_OC0#/GPM0#

M1

AZ_BITCLK

M2

AZ_SDOUT

J7

AZ_SDIN0/GPIO42

J8

AZ_SDIN1/GPIO43

L8

AZ_SDIN2/GPIO44

M3

AZ_SDIN3/GPIO46

L6

AZ_SYNC

M4

AZ_RST#

L5

AZ_DOCK_RST#/GPM8#

H19

IMC_GPIO0

H20

IMC_GPIO1

H21

SPI_CS2#/IMC_GPIO2

F25

IDE_RST#/F_RST#/IMC_GPO3

D22

IMC_GPIO4

E24

IMC_GPIO5

E25

IMC_GPIO6

D23

IMC_GPIO7

218S7EALA11FG_BGA528_SB700 SB700R3@

SB700

ACPI / WAKE UP EVENTS

USB OC

HD AUDIO

INTEGRATED uC

Part 4 of 5

USBCLK/14M_25M_48M_OSC

INTEGRATED uC

USB_RCOMP

USB_FSD13P

USB MISC

USB_FSD13N USB_FSD12P

USB_FSD12N

USB 1.1

USB_HSD11P USB_HSD11N

USB_HSD10P USB_HSD10N

USB_HSD9P USB_HSD9N

USB_HSD8P USB_HSD8N

USB_HSD7P USB_HSD7N

USB_HSD6P USB_HSD6N

USB_HSD5P USB_HSD5N

USB_HSD4P

USB 2.0

USB_HSD4N USB_HSD3P

USB_HSD3N

GPIO

USB_HSD2P USB_HSD2N

USB_HSD1P USB_HSD1N

USB_HSD0P USB_HSD0N

IMC_GPIO8 IMC_GPIO9

IMC_PWM0/IMC_GPIO10

SCL2/IMC_GPIO11

SDA2/IMC_GPIO12

SCL3_LV/IMC_GPIO13

SDA3_LV/IMC_GPIO14

IMC_PWM1/IMC_GPIO15

IMC_PWM2/IMC_GPO16 IMC_PWM3/IMC_GPO17

IMC_GPIO18 IMC_GPIO19 IMC_GPIO20 IMC_GPIO21 IMC_GPIO22 IMC_GPIO23 IMC_GPIO24 IMC_GPIO25

IMC_GPIO26 IMC_GPIO27 IMC_GPIO28 IMC_GPIO29 IMC_GPIO30 IMC_GPIO31 IMC_GPIO32 IMC_GPIO33 IMC_GPIO34 IMC_GPIO35 IMC_GPIO36 IMC_GPIO37 IMC_GPIO38 IMC_GPIO39 IMC_GPIO40 IMC_GPIO41

C8 G8

E6 E7

F7 E8

H11 J10

E11 F11

A11 B11

C10 D10

G11 H12

E12 E14

C12 D12

B12 A12

G12 G14

H14 H15

A13 B13

B14 A14

A18 B18 F21 D21 F19 E20 E21 E19 D19 E18

G20 G21 D25 D24 C25 C24 B25 C23

B24 B23 A23 C22 A22 B22 B21 A21 D20 C20 A20 B20 B19 A19 D18 C18

CLK_48M_USB

USB_RCOMPPM_SLP_S3#

USB20_P9 USB20_N9

USB20_P8 USB20_N8

USB20_P4 USB20_N4

USB20_P2 USB20_N2

USB20_P1 USB20_N1

USB20_P0 USB20_N0

GPIO16 GPIO17

1 2

R311 100_0402_5%

100_0402_5%

R323

1 2

USB20_P9 <18> USB20_N9 <18>

USB20_P8 <27> USB20_N8 <27>

USB20_P4 <28> USB20_N4 <28>

USB20_P2 <25> USB20_N2 <25>

USB20_P1 <25> USB20_N1 <25>

USB20_P0 <25> USB20_N0 <25>

GPIO16 <24> GPIO17 <24>

C617

C617 100P_0402_50V8J

100P_0402_50V8J

1 2

11.8K_0402_1%

USB-9 Int Camera USB-8 WLAN

USB-4 Card Reader (3 IN 1)

USB-2 Left USB USB-1 Right side USB-0 Right side

STRAP PIN STRAP PIN

CLK_48M_USB <16>

4 4

/

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009-02-12 2009-02-12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

SB700 USB / AC97

LA-5831P

21 44Wednesday, August 12, 2009

E

1.0Custom

A

U15B

AD9

SATA_TX0P

AE9

SATA_TX0N

AB10

SATA_RX0N

AC10

SATA_STX_DRX_P1<25>

HDD

1 1

ODD

2 2

+1.2V_HT

+3VS

3 3

SATA_STX_DRX_N1<25>

SATA_RXN1_C<25> SATA_RXP1_C<25>

SATA_STX_DRX_P3<25> SATA_STX_DRX_N3<25>

SATA_RXN3_C<25> SATA_RXP3_C<25>

+3VS

L54

C516

C517

L54

BLM18PG121SN1D_0603

10P_0402_50V8J

1 2

SATA_LED#<33>

2.2U_0603_6.3V4Z

L55

1U_0402_6.3V4Z

12

SATA_STX_DRX_P1 SATA_STX_DRX_N1

SATA_RXN1_C SATA_RXP1_C

SATA_STX_DRX_P3 SATA_STX_DRX_N3

SATA_RXN3_C SATA_RXP3_C

R342

R342 1K_0402_1%

1K_0402_1%

12

R343

R343 10K_0402_5%

10K_0402_5%

12

2

C522

1

2

1

SATA_X1

SATA_X2

+XTLVDD_SATA

1

2

12

C524

Y4

Y4 25MHz_20pF_6X25000017

25MHz_20pF_6X25000017

SATA_CAL SATA_X1 SATA_X2

SATA_LED#

+PLLVDD_SATA

2

C523

1

0.1U_0402_16V4Z

C625

0.1U_0402_16V4Z

12

R341

R341 10M_0402_5%

10M_0402_5%

SATA_RX0P

AE10

SATA_TX1P

AD10

SATA_TX1N

AD11

SATA_RX1N

AE11

SATA_RX1P

AB12

SATA_TX2P

AC12

SATA_TX2N

AE12

SATA_RX2N

AD12

SATA_RX2P

AD13

SATA_TX3P

AE13

SATA_TX3N

AB14

SATA_RX3N

AC14

SATA_RX3P

AE14

SATA_TX4P

AD14

SATA_TX4N

AD15

SATA_RX4N

AE15

SATA_RX4P

AB16

SATA_TX5P

AC16

SATA_TX5N

AE16

SATA_RX5N

AD16

SATA_RX5P

V12

SATA_CAL

Y12

SATA_X1

AA12

SATA_X2

W11

SATA_ACT#/GPIO67

AA11

PLLVDD_SATA

W12

XTLVDD_SATA

218S7EALA11FG_BGA528_SB700

B

SB700

Part 2 of 5

SATA PWR SERIAL ATA

HW MONITOR

IDE_IORDY

IDE_IRQ

IDE_A0 IDE_A1 IDE_A2

IDE_DACK#

IDE_DRQ

IDE_IOR# IDE_IOW# IDE_CS1# IDE_CS3#

IDE_D0/GPIO15 IDE_D1/GPIO16 IDE_D2/GPIO17 IDE_D3/GPIO18 IDE_D4/GPIO19 IDE_D5/GPIO20 IDE_D6/GPIO21 IDE_D7/GPIO22 IDE_D8/GPIO23

ATA 66/100/133

IDE_D9/GPIO24 IDE_D10/GPIO25 IDE_D11/GPIO26 IDE_D12/GPIO27 IDE_D13/GPIO28 IDE_D14/GPIO29 IDE_D15/GPIO30

SPI_DI/GPIO12

SPI_DO/GPIO11

SPI_CLK/GPIO47

SPI_HOLD#/GPIO31

SPI_CS1#/GPIO32

LAN_RST#/GPIO13

SPI ROM

ROM_RST#/GPIO14

FANOUT0/GPIO3 FANOUT1/GPIO48 FANOUT2/GPIO49

FANIN0/GPIO50 FANIN1/GPIO51 FANIN2/GPIO52

TEMP_COMM TEMPIN0/GPIO61 TEMPIN1/GPIO62 TEMPIN2/GPIO63

TEMPIN3/TALERT#/GPIO64

VIN0/GPIO53 VIN1/GPIO54 VIN2/GPIO55 VIN3/GPIO56 VIN4/GPIO57 VIN5/GPIO58 VIN6/GPIO59 VIN7/GPIO60

AVDD AVSS

SB700R3@

AA24 AA25 Y22 AB23 Y23 AB24 AD25 AC25 AC24 Y25 Y24

AD24 AD23 AE22 AC22 AD21 AE20 AB20 AD19 AE19 AC20 AD20 AE21 AB22 AD22 AE23 AC23

G6 D2 D1 F4 F3

U15 J1

M8 M5 M7

P5 P8 R8

C6 B6 A6 A5 B5

A4 B4 C4 D4 D5 D6 A7 B7

F6 G7

SPK_SEL EC_THERM#

ACIN_SB

+SB_AVDD

1

2

C525

0.1U_0402_16V4Z

C

SPK_SEL <29> EC_THERM# <32>

1

C526

2.2U_0603_6.3V4Z

2

D41

D41 CH751H-40PT_SOD323-2

CH751H-40PT_SOD323-2

2 1

R562

R562 150K_0402_5%

150K_0402_5%

1 2

L56 0_0603_5%L56 0_0603_5%

12

D

ACIN <32,33,35>

+3VALW

E

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009-02-12 2009-02-12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

SB700 SATA / IDE / SPI

LA-5831P

22 44Wednesday, August 12, 2009

E

1.0

A

+3VS

1 1

C528 22U_0805_6.3V6M@C528 22U_0805_6.3V6M@ C531 1U_0402_6.3V4Z@ C531 1U_0402_6.3V4Z@

C530 1U_0402_6.3V4Z@ C530 1U_0402_6.3V4Z@ C533 1U_0402_6.3V4Z@ C533 1U_0402_6.3V4Z@ C536 1U_0402_6.3V4Z@ C536 1U_0402_6.3V4Z@ C535 1U_0402_6.3V4Z@ C535 1U_0402_6.3V4Z@

C539 0.1U_0402_16V4Z@C539 0.1U_0402_16V4Z@ C541 0.1U_0402_16V4Z@C541 0.1U_0402_16V4Z@ C542 0.1U_0402_16V4Z@C542 0.1U_0402_16V4Z@

1 2 1 2 1 2 1 2 1 2

1 2 1 2 1 2

12

No IDE device unmount CAP

+3VS

L61

L61 0_0805_5%

0_0805_5%

+1.2V_HT

2 2

+1.2V_HT

+3VALW

3 3

12

C552 4.7U_0805_10V6KC552 4.7U_0805_10V6K

12

C553 1U_0402_6.3V4Z@C553 1U_0402_6.3V4Z@

1 2

C555 1U_0402_6.3V4ZC555 1U_0402_6.3V4Z

1 2

C554 1U_0402_6.3V4ZC554 1U_0402_6.3V4Z

1 2

C558 1U_0402_6.3V4ZC558 1U_0402_6.3V4Z

1 2

C557 0.1U_0402_16V4ZC557 0.1U_0402_16V4Z

1 2

C560 0.1U_0402_16V4ZC560 0.1U_0402_16V4Z

1 2

L63

L63 0_0805_5%

0_0805_5%

12

C566 22U_0805_6.3V6MC566 22U_0805_6.3V6M C567 1U_0402_6.3V4ZC567 1U_0402_6.3V4Z

1 2

C568 1U_0402_6.3V4ZC568 1U_0402_6.3V4Z

1 2

C571 0.1U_0402_16V4ZC571 0.1U_0402_16V4Z

1 2

C572 0.1U_0402_16V4ZC572 0.1U_0402_16V4Z

1 2

L66

L66 0_0805_5%

0_0805_5%

12

C576 10U_0805_10V4ZC576 10U_0805_10V4Z

1 2

C577 10U_0805_10V4ZC577 10U_0805_10V4Z

1 2

C580 1U_0402_6.3V4ZC580 1U_0402_6.3V4Z

1 2

C581 1U_0402_6.3V4ZC581 1U_0402_6.3V4Z

1 2

C583 0.1U_0402_16V4ZC583 0.1U_0402_16V4Z

1 2

C582 0.1U_0402_16V4ZC582 0.1U_0402_16V4Z

1 2

C584 0.1U_0402_16V4ZC584 0.1U_0402_16V4Z

1 2

+PCIE_VDDR

+1.2V_SATA

+AVDD_USB

B

U15C

L9

M9

T15

U9 U16 U17

V8

W7

Y6 AA4 AB5

AB21

Y20

AA21 AA22 AE25

P18 P19 P20 P21 R22 R24 R25

AA14 AB18 AA15 AA17 AC18 AD17 AE17

A16 B16 C16 D16 D17 E17 F15 F17 F18 G15 G17 G18

218S7EALA11FG_BGA528_SB700 SB700R3@

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 VDDQ_10 VDDQ_11 VDDQ_12

VDD33_18_1 VDD33_18_2 VDD33_18_3 VDD33_18_4

PCIE_VDDR_1 PCIE_VDDR_2 PCIE_VDDR_3 PCIE_VDDR_4 PCIE_VDDR_5 PCIE_VDDR_6 PCIE_VDDR_7

AVDD_SATA_1 AVDD_SATA_4 AVDD_SATA_2 AVDD_SATA_3 AVDD_SATA_5 AVDD_SATA_6 AVDD_SATA_7

AVDDTX_0 AVDDTX_1 AVDDTX_2 AVDDTX_3 AVDDTX_4 AVDDTX_5 AVDDRX_0 AVDDRX_1 AVDDRX_2 AVDDRX_3 AVDDRX_4 AVDDRX_5

SB700

Part 3 of 5

PCI/GPIO I/O

IDE/FLSH I/O

POWER

A-LINK I/O

SATA I/O

PLL CLKGEN I/O

USB I/O

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8

CORE S0

VDD_9

CKVDD_1.2V_1 CKVDD_1.2V_2 CKVDD_1.2V_3 CKVDD_1.2V_4

S5_3.3V_1 S5_3.3V_2 S5_3.3V_3 S5_3.3V_4 S5_3.3V_5 S5_3.3V_6 S5_3.3V_7

3.3V_S5 I/OCORE S5

S5_1.2V_1 S5_1.2V_2

USB_PHY_1.2V_1 USB_PHY_1.2V_2

V5_VREF AVDDCK_3.3V AVDDCK_1.2V

AVDDC

L15 M12 M14 N13 P12 P14 R11 R15 T16

L21 L22 L24 L25

A17 A24 B17 J4 J5 L1 L2

G2 G4

A10 B10

AE7 J16 K17 E9

+1.2V_HT_R

+1.2V_HT

+S5_3V

+S5_1.2V

+1.2_USB

+V5_VREF +AVDDCK_3.3V +AVDDCK_1.2V +AVDDC

C

1 2

2

C578

0.1U_0402_16V4Z

1

L64

L64 0_0603_5%

0_0603_5%

L65

L65 0_0603_5%

0_0603_5%

L67

L67 0_0603_5%

0_0603_5%

12

R593

R593 0_0805_5%

0_0805_5%

1 2

R564

R564 0_0805_5%

0_0805_5%

1 2

12 12 12 12

12 12

C52910U_0805_6.3V6M C52910U_0805_6.3V6M

C5321U_0402_6.3V4Z C5321U_0402_6.3V4Z C5341U_0402_6.3V4Z C5341U_0402_6.3V4Z C5381U_0402_6.3V4Z C5381U_0402_6.3V4Z C5371U_0402_6.3V4Z C5371U_0402_6.3V4Z

C5270.1U_0402_16V4Z C5270.1U_0402_16V4Z C5400.1U_0402_16V4Z C5400.1U_0402_16V4Z

C55622U_0805_6.3V6M @C55622U_0805_6.3V6M @

C5592.2U_0603_6.3V4Z C5592.2U_0603_6.3V4Z C5612.2U_0603_6.3V4Z C5612.2U_0603_6.3V4Z

C5621U_0402_6.3V4Z C5621U_0402_6.3V4Z C5630.1U_0402_16V4Z C5630.1U_0402_16V4Z

C5640.1U_0402_16V4Z C5640.1U_0402_16V4Z C5650.1U_0402_16V4Z C5650.1U_0402_16V4Z

C5691U_0402_6.3V4Z C5691U_0402_6.3V4Z C5701U_0402_6.3V4Z C5701U_0402_6.3V4Z

C57310U_0805_10V4Z @C57310U_0805_10V4Z @ C5741U_0402_6.3V4Z C5741U_0402_6.3V4Z C5750.1U_0402_16V4Z C5750.1U_0402_16V4Z

2

C579

C579 1U_0603_10V4Z

1U_0603_10V4Z

1

C5852.2U_0603_6.3V4Z C5852.2U_0603_6.3V4Z C5860.1U_0402_16V4Z C5860.1U_0402_16V4Z

+1.2V_HT

+3VALW

+1.2VALW

+3VALW

D

R346

R346 1K_0402_5%

1K_0402_5%

12

D14

D14 CH751H-40PT_SOD323-2

CH751H-40PT_SOD323-2

21

+5VS

+3VS

U15E

SB700

T10

AVSS_SATA_1

U10

AVSS_SATA_2

U11

AVSS_SATA_3

U12

AVSS_SATA_4

V11

AVSS_SATA_5

V14

AVSS_SATA_6

W9

AVSS_SATA_7

Y9

AVSS_SATA_8

Y11

AVSS_SATA_9

Y14

AVSS_SATA_10

Y17

AVSS_SATA_11

AA9

AVSS_SATA_12

AB9

AVSS_SATA_13

AB11

AVSS_SATA_14

AB13

AVSS_SATA_15

AB15

AVSS_SATA_16

AB17

AVSS_SATA_17

AC8

AVSS_SATA_18

AD8

AVSS_SATA_19

AE8

AVSS_SATA_20

A15

AVSS_USB_1

B15

AVSS_USB_2

C14

AVSS_USB_3

D8

AVSS_USB_4

D9

AVSS_USB_5

D11

AVSS_USB_6

D13

AVSS_USB_7

D14

AVSS_USB_8

D15

AVSS_USB_9

E15

AVSS_USB_10

F12

AVSS_USB_11

F14

AVSS_USB_12

G9

AVSS_USB_13

H9

AVSS_USB_14

H17

AVSS_USB_15

J9

AVSS_USB_16

J11

AVSS_USB_17

J12

AVSS_USB_18

J14

AVSS_USB_19

J15

AVSS_USB_20

K10

AVSS_USB_21

K12

AVSS_USB_22

K14

AVSS_USB_23

K15

AVSS_USB_24

H18

PCIE_CK_VSS_1

J17

PCIE_CK_VSS_2

J22

PCIE_CK_VSS_3

K25

PCIE_CK_VSS_4

M16

PCIE_CK_VSS_5

M17

PCIE_CK_VSS_6

M21

PCIE_CK_VSS_7

P16

PCIE_CK_VSS_8

F9

AVSSC

Part 5 of 5

218S7EALA11FG_BGA528_SB700

SB700R3@

E

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8

VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42

GROUND

VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50

PCIE_CK_VSS_9 PCIE_CK_VSS_10 PCIE_CK_VSS_11 PCIE_CK_VSS_12 PCIE_CK_VSS_13 PCIE_CK_VSS_14 PCIE_CK_VSS_15 PCIE_CK_VSS_16 PCIE_CK_VSS_17 PCIE_CK_VSS_18 PCIE_CK_VSS_19 PCIE_CK_VSS_20 PCIE_CK_VSS_21

AVSSCK

A2 A25 B1 D7 F20 G19 H8 K9 K11 K16 L4 L7 L10 L11 L12 L14 L16 M6 M10 M11 M13 M15 N4 N12 N14 P6 P9 P10 P11 P13 P15 R1 R2 R4 R9 R10 R12 R14 T11 T12 T14 U4 U14 V6 Y21 AB1 AB19 AB25 AE1 AE24

P23 R16 R19 T17 U18 U20 V18 V20 V21 W19 W22 W24 W25

L17

L68

+AVDDCK_1.2V

+AVDDCK_3.3V

4 4

/

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009-02-12 2009-02-12

L68 0_0603_5%

0_0603_5%

12

C5872.2U_0603_6.3V4Z C5872.2U_0603_6.3V4Z

12

C5880.1U_0402_16V4Z C5880.1U_0402_16V4Z

12

L69

L69 0_0603_5%

0_0603_5%

12

C5892.2U_0603_6.3V4Z C5892.2U_0603_6.3V4Z

12

C5900.1U_0402_16V4Z C5900.1U_0402_16V4Z

12

Compal Secret Data

Deciphered Date

+1.2V_HT

+3VS

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

SB700 Power / GND

LA-5831P

23 44Wednesday, August 12, 2009

E

1.0Custom

A

B

C

D

E

REQUIRED STRAPS

PCI_CLK3

@

BOOTFAIL TIMER ENABLED

BOOTFAIL TIMER DISABLED

DEFAULT

12

R348

R348 10K_0402_5%

10K_0402_5%

12

R358

R358 10K_0402_5%

10K_0402_5%

PULL

1 1

PCI_CLK2<20> PCI_CLK3<20> PCI_CLK4<20> PCI_CLK5<20> CLK_PCI_EC<20,32> CLK_PCI_SIO2<20,31> RTC_CLK<20> HDARST#<21>

2 2

GPIO17<21> GPIO16<21>

HIGH

PULL LOW

+3VS +3VS +3VS +3VS

12

R347

@

10K_0402_5%

12

R357

R357 10K_0402_5%

10K_0402_5%

USE DEBUG STRAPS

IGNORE DEBUG STRAPS

DEFAULT

12

@

12

@ R359

@

R349

R349 10K_0402_5%

10K_0402_5%

R359 10K_0402_5%

10K_0402_5%

PCI_CLK4 PCI_CLK5

RESERVED

@

@ R360

@

12

R350

R350 10K_0402_5%

10K_0402_5%

12

R360 10K_0402_5%

10K_0402_5%

RESERVED

NOTE: SB700 HAS INTERNAL 15K PULL UP RESISTOR FOR RTC_CLK

LPC_CLK0

ENABLE PCI MEM BOOT

DISABLE PCI MEM BOOT

DEFAULT

+3VALW +3VALW+3VALW +3VALW +3VALW +3VALW

12

R351

@

10K_0402_5%

12

R361

R361 10K_0402_5%

10K_0402_5%

@

CLKGEN ENABLED

CLKGEN DISABLED

DEFAULT

12

R352

R352 10K_0402_5%

10K_0402_5%

12

R362

R362 10K_0402_5%

10K_0402_5%

@

RTC_CLKLPC_CLK1

INTERNAL RTC

DEFAULT

EXT. RTC

(PD on X1, apply 32KHz to RTC_CLK)

12

R353

R353 10K_0402_5%

10K_0402_5%

12

R363

2.2K_0402_5%

AZ_RST_CD#

EC ENABLED

EC DISABLED

DEFAULT

12

R354

@

10K_0402_5%

12

R364

R364 10K_0402_5%

10K_0402_5%

GP17

GP16PCI_CLK2

Internal pull up

H,H = Reserved H,L = SPI ROM

L,H = LPC ROM (Default)

L,L = FWH ROM

12

R355

@

2.2K_0402_5%

12

R365

2.2K_0402_5%

@

12

R356

2.2K_0402_5%

SI2: mount 2.2K

12

R366

2.2K_0402_5%

Need to confirm if SB SPI ROM will mount

DEBUG STRAPS

SB700 HAS 15K INTERNAL PU FOR PCI_AD[28:23]

PCI_AD28

@

12

R373

2.2K_0402_5%

USE LONG RESET

DEFAULT

USE SHORT RESET

B

PULL

3 3

PCI_AD28<20> PCI_AD27<20> PCI_AD26<20> PCI_AD25<20> PCI_AD24<20> PCI_AD23<20>

4 4

A

HIGH

PULL LOW

PCI_AD27 PCI_AD26

R374

2.2K_0402_5%

USE ACPI BCLK

DEFAULT

BYPASS ACPI BCLK

@

USE PCI PLL

DEFAULT

BYPASS PCI PLL

@

12

PCI_AD25 PCI_AD24

USE IDE PLL

DEFAULT

BYPASS IDE PLL

12

R375

2.2K_0402_5%

PCI_AD23

USE DEFAULT PCIE STRAPS

DEFAULT

USE EEPROM PCIE STRAPS

12

R376

@

2.2K_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

RESERVED

12

R377

@

2.2K_0402_5%

C

12

R378

@

2.2K_0402_5%

Compal Secret Data

2009-02-12 2009-02-12

Compal Secret Data

Deciphered Date

D

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Title

Compal Electronics, Inc.

SB700 STRAPS

LA-5831P

24 44Wednesday, August 12, 2009

E

1.0

A

B

C

D

E

SATA HDD Conn.

+5VS

Place closely JHDD0 SATA CONN.

1.2A

1

C387

C387 10U_0805_10V4Z

10U_0805_10V4Z

2

1 1

2 2

1

C388

0.1U_0402_16V4Z

2

1

C389

0.1U_0402_16V4Z

2

1

C390

0.1U_0402_16V4Z

2

JHDD0

GND

A+

A-

GND

B-

B+

GND

V33 V33

V33 GND GND GND

V5 V5 V5

GND

Reserved

GND

GND GND

V12

24 23

OCTEK_SAT-22SO1G_RV

@JHDD0

@

1 2 3 4 5 6 7

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

SATA_TXP1 SATA_TXN1

SATA_IRX_DTX_N1 SATA_IRX_DTX_P1

C512 0.01U_0402_25V7KC512 0.01U_0402_25V7K

1 2

C513 0.01U_0402_25V7KC513 0.01U_0402_25V7K

1 2

C410 0.01U_0402_25V7KC410 0.01U_0402_25V7K

1 2

C412 0.01U_0402_25V7KC412 0.01U_0402_25V7K

1 2

+3VS

+5VS

SATA_STX_DRX_P1 <22>

SATA_STX_DRX_N1 <22>

SATA_RXN1_C <22>

SATA_RXP1_C <22>

USB Right Board

VOUT VOUT

W=60mils

8 7 6

1 2

5

FLG

R422 0_0402_5%R422 0_0402_5%

1

C438

@

4.7U_0805_10V4Z

2

USB_OC#0 <21,32>

USB_EN#2<32>

+5VALW +USB_VCCA

USB_EN#0<32>

3 3

USB_EN#0

2A

U25

1

GND

2

VIN VIN3VOUT

4

EN

RT9715BGS_SO8

SATA ODD Conn

+5VS

1.1A

1

C414

C414 10U_0805_10V4Z

10U_0805_10V4Z

2

JODD

15

GND

14

GND

SANTA_206401-1_RV

GND

GND GND

1

2

@JODD

@

1 2

A+

3

A-

4 5

B-

6

B+

7

8

DP

9

+5V

10

+5V

11

MD

12 13

USB Left Conn

U19

1

GND

2

VIN

USB_EN#2

VIN3VOUT

4

EN

RT9715BGS_SO8

C415

C415 10U_0805_10V4Z

10U_0805_10V4Z

SATA_TXP3 SATA_TXN3

SATA_IRX_DTX_N3 SATA_IRX_DTX_P3

2A

8

VOUT

7

VOUT

6 5

FLG

1

C416

@

1U_0402_6.3V4Z

2

C518 0.01U_0402_25V7KC518 0.01U_0402_25V7K

1 2

C519 0.01U_0402_25V7KC519 0.01U_0402_25V7K

1 2

C424 0.01U_0402_25V7KC424 0.01U_0402_25V7K

1 2

C425 0.01U_0402_25V7KC425 0.01U_0402_25V7K

1 2

+5VS

W=60mils

+USB_VCCB+5VALW

R584

1 2

0_0402_5%

1

C367

4.7U_0805_10V4Z

@

2

1

C417

0.1U_0402_16V4Z

2

1

C418

0.1U_0402_16V4Z

2

USB_OC#2 <21,32>

SATA_STX_DRX_P3 <22> SATA_STX_DRX_N3 <22>

SATA_RXN3_C <22> SATA_RXP3_C <22>

1 2

1

4

1 2

For ESD

D11

1

PJDLC05_SOT23-3

@L46

@

2

3

Deciphered Date

2 3

USB20_N2_R USB20_P2_R

W=60mils

+USB_VCCB

0.1U_0402_16V4Z

1

+

C352

C350

2

220U_6.3V_M

JUSB

@JUSB

@

1

GND

VCC

2

GND

D-

3

GND

D+

4

GND

P-TWO_CU304G-A0G1G-P

Title

Size Document Number Rev

Date: Sheet of

D

Date: Sheet of

1

C351

2

1000P_0402_50V7K

5 6 7 8

Compal Electronics, Inc.

SATA HDD/ODD

LA-5831P

E

1.0Custom

25 44Wednesday, August 12, 2009

1.0Custom

+USB_VCCA

R1026 0_0402_5%R1026 0_0402_5%

1 2

L50

USB20_N0<21>

USB20_P0<21>

4 4

USB20_N1<21>

USB20_P1<21>

1

4

WCM-2012-900T_0805

R1027 0_0402_5%R1027 0_0402_5%

R1028 0_0402_5%R1028 0_0402_5%

L51

1

4

WCM-2012-900T_0805

R1029 0_0402_5%R1029 0_0402_5%

A

1

4

1 2

1

4

1 2

@L50

@

2

3

@L51

@

2

3

W=60mils

USB20_N0_R USB20_P0_R

USB20_N1_R USB20_P1_R

JUSBB

1

2

3

4

5

6

7

8

9

10

11

GND

12

GND

ACES_85201-1205N

B

@

13 14

/

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

USB20_N2<21>

USB20_P2<21>

2008/04/14 2009/04/14

C

R95 0_0402_5%R95 0_0402_5%

L46

1

4

WCM-2012-900T_0805

R96 0_0402_5%R96 0_0402_5%

Compal Secret Data

A

Place Close to Chip

CL2 0.1U_0402_16V7KCL2 0.1U_0402_16V7K

PCIE_PTX_C_IRX_P3<11>

PCIE_PTX_C_IRX_N3<11> PCIE_ITX_C_PRX_P3<11> PCIE_ITX_C_PRX_N3<11>

CLK_PCIE_LAN<16> CLK_PCIE_LAN#<16>

@ RL4

@

+3VS

12

RL5

RL5 1K_0402_1%

1K_0402_1%

RL6

RL6 15K_0402_5%

15K_0402_5%

CLKREQ_LAN#<16>

PLT_RST#<12,15,20,27,31,32>

LAN_WAKE#<21>

RL4 10K_0402_5%

10K_0402_5%

ISOLATEB

LAN_WAKE#

1 2

Reserve R70 for cost down

0_0402_5%

1 1

+3V_LAN

1 2

2 2

1 2

CL1 0.1U_0402_16V7KCL1 0.1U_0402_16V7K

1 2

R70

@R70

@

RL3

2.49K_0402_1%

WOL_EN# <32,34>

PCIE_PTX_IRX_P3

PCIE_PTX_IRX_N3 PCIE_ITX_C_PRX_P3 PCIE_ITX_C_PRX_N3 CLK_PCIE_LAN

CLK_PCIE_LAN# CLKREQ_LAN# PLT_RST#

LAN_WAKE# ISOLATEB

LAN_X1 LAN_X2

B

UL1

20

HSOP

21

HSON

15

HSIP

16

HSIN

17

REFCLK_P

18

REFCLK_M

25

CLKREQB

27

PERSTB

46

RSET

26

LANWAKEB

28

ISOLATEB

41

CKXTAL1

42

CKXTAL2

23

NC

24

NC

7

GND

14

GND

31

GND

47

GND

22

GNDTX

RTL8103EL-GR_LQFP48_7X7

CL13

27P_0402_50V8J

RTL8103EL-GR

1

2

LED3/EEDO

LED2/EEDI/AUX

LED1/EESK

EECS

LED0

MDIP0 MDIN0 MDIP1 MDIN1

NC NC NC NC

NC

VCTRL12A

VDDTX DVDD12 DVDD12 DVDD12 DVDD12

NC NC

VCTRL12D

VDD33 VDD33

AVDD33

NC NC

YL1

12

25MHz_20pF_6X25000017

LAN_DO

33

LAN_DI

34

LAN_SK_LAN_LINK#

35

LAN_CS

32

LAN_ACTIVITY#

38

LAN_MDI0+

2

LAN_MDI0-

3

LAN_MDI1+

5

LAN_MDI1-

6 8 9 11 12

4

VCTRL12

48 19

30 36 13 10

39 44

45

R97 0_0402_5%R97 0_0402_5%

1 2

29

R98 0_0402_5%R98 0_0402_5%

1 2

37

R105 0_0402_5%R105 0_0402_5%

1 2

1 40 43

Reserve bead for EMI

LAN_X2LAN_X1

1

CL16

CL16 27P_0402_50V8J

27P_0402_50V8J

2

C

RL1 3.6K_0402_5%RL1 3.6K_0402_5%

1 2

RL2 1K_0402_5%RL2 1K_0402_5%

+EVDD12 +LAN_VDD12

+LAN_VDD12

12

+3V_LAN

T27 PADT27 PAD

+3V_LAN

D

Close to Pin10,13,30,36

2

CL3

0.1U_0402_16V4Z

1

2

CL4

0.1U_0402_16V4Z

1

Close to Pin1,37,29

2

CL10

0.1U_0402_16V4Z

1

VCTRL12

2

CL5

0.1U_0402_16V4Z

1

Close to Pin45

Close to Pin19

2

CL8

CL8 1U_0402_6.3V4Z

1U_0402_6.3V4Z

1

2

CL11

0.1U_0402_16V4Z

1

Close to Pin48

1

CL14

@

10U_0805_10V4Z

2

+LAN_VDD12

2

CL6

0.1U_0402_16V4Z

1

+LAN_VDD12

2

CL7

0.1U_0402_16V4Z

1

+EVDD12

2

CL9

CL9 1U_0402_6.3V4Z

1U_0402_6.3V4Z

1

+3V_LAN

2

CL12

0.1U_0402_16V4Z

1

2

CL15

0.1U_0402_16V4Z

1

E

2

CL21

68P_0402_50V8J

RL9

D

RL9 150_0402_1%

150_0402_1%

12

RL10

RL10 150_0402_1%

150_0402_1%

12

68P_0402_50V8J

RL11

RL11 150_0402_1%

150_0402_1%

12

RL12

RL12 150_0402_1%

150_0402_1%

12

RJ45_GND LANGND

LAN_ACTIVITY#

3 3

Place these components colsed to LAN chip

CL17

0.01U_0402_25V7K

12

CL19

0.01U_0402_25V7K

12

4 4

A

LAN_MDI0+ LAN_MDI0-

LAN_MDI1+ LAN_MDI1-

UL2

1

TD+

2

TD-

3

CT

4

NC

5

NC

6

CT

7

RD+ RD-8RX-

LF-H1201P-2

RX+

RJ45_MIDI0+

16

TX+

RJ45_MIDI0-

15

TX-

14

CT

13

NC

12

NC

11

CT

RJ45_MIDI1+

10

RJ45_MIDI1-

9

B

Add CL18, CL20 for customer request

CL18

CL18 1000P_0402_50V8-J

1000P_0402_50V8-J

1 2

CL20

CL20 1000P_0402_50V8-J

1000P_0402_50V8-J

1 2

RL7

RL7 75_0402_1%

75_0402_1%

1 2

RL8

RL8 75_0402_1%

75_0402_1%

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

RJ45_GND

2009-02-12 2009-02-12

C

+3V_LAN

LAN_SK_LAN_LINK#

+3V_LAN

Compal Secret Data

Deciphered Date

1

RJ45_MIDI1-

RJ45_MIDI1+

2

CL22

1 2

RJ45_MIDI0RJ45_MIDI0+

1

CL23

CL23 1000P_1808_3KV7K

1000P_1808_3KV7K

Title

Size Document Number Rev

Custom

Date: Sheet of

< LAN Conn >

JLAN

12

Yellow LED-

11

Yellow LED+

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

10

Green LED-

9

Green LED+

TYCO_2068888-1_12P-T

1

CL24

0.1U_0402_16V4Z

2

Compal Electronics, Inc.

RTL8103EL 10 / 100 LAN

LA-5831P

1

CL25

4.7U_0603_6.3V6K

2

E

SHLD2 SHLD1

@JLAN

@

14 13

26 44Wednesday, August 12, 2009

1.0

A

B

C

D

E

< PCIe Mini Card for WLAN/ WiMAX >

+1.5VS

1 1

2 2

1

CM20

0.01U_0402_25V7K

2

E51_TXD<32> E51_RXD<32>

1

CM21

0.1U_0402_16V4Z

2

CLKREQ_MCARD2#<16>

CLK_PCIE_MCARD2#<16> CLK_PCIE_MCARD2<16>

PCIE_PTX_C_IRX_N2<11> PCIE_PTX_C_IRX_P2<11>

PCIE_ITX_C_PRX_N2<11>

PCIE_ITX_C_PRX_P2<11>

RM6 0_0402_5%RM6 0_0402_5%

E51_RXD E51_RXD_R

1 2

RM7 0_0402_5%RM7 0_0402_5%

1 2

RM8

RM8 100K_0402_5%

100K_0402_5%

1 2

1

CM22

4.7U_0805_10V4Z

2

CLKREQ_MCARD2# CLK_PCIE_MCARD2#

CLK_PCIE_MCARD2

PCIE_PTX_C_IRX_N2 PCIE_PTX_C_IRX_P2

PCIE_ITX_C_PRX_N2 PCIE_ITX_C_PRX_P2

+3VS

E51_TXD_RE51_TXD

+3VS

1

2

JWLAN

1

3

5

7

9

11

13

15

17

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

49

51

53

GND1

ACES_88911-5204

CM17

0.01U_0402_25V7K

+1.5VS

@JWLAN

@

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

50

52

54

GND2

1

2

+3VS

WL_OFF# PLT_RST#

SMB_CK_CLK1 SMB_CK_DAT1

USB20_N8 USB20_P8

CM18

0.1U_0402_16V4Z

1

CM19

4.7U_0805_10V4Z

2

WL_OFF# <32>

PLT_RST# <12,15,20,26,31,32>

SMB_CK_CLK1 <21>

SMB_CK_DAT1 <21>

USB20_N8 <21> USB20_P8 <21>

1 2

RN3 100K_0402_5%RN3 100K_0402_5%

PLT_RST#

3 3

< R1 for customer BOM STRUCTURE >

U3

RS780MN

RS780MN R1

RS780MNR1@

U3

RS780MC

RS780MC R1

RS780MCR1@

U15

SB700

SB700R1

SB700R1@

4 4

A

SB700R1@

< R3 for mass production BOM STRUCTURE >

U3

RS780MN

RS780MN R3

RS780MNR3@

B

< PCB >

ZZZ

PCB

/

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009-02-12 2009-02-12

ZZZ

PCB 075 LA-5831P REV1 M/B

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

WLAN / CAMERA

LA-5831P

27 44Wednesday, August 12, 2009

E

1.0

5

RC2

RC2 0_0603_5%

0_0603_5%

+3VS

D D

+3VALW

1 2

RC3

RC3 0_0603_5%@

0_0603_5%@

+3VS_CR

1

2

confirm that whether can be removed

+3VS_CR

RC8

RC8 100K_0402_5%

100K_0402_5%

1 2

RST# RST#_R

1

CC8

CC8 1U_0402_6.3V4Z

1U_0402_6.3V4Z

2

1

CC9

C C

CC9

0.1U_0402_16V4Z

@

2

12

RC10

RC10 0_0402_5%

0_0402_5%

RC9

RC9 0_0402_5%

0_0402_5%

MODE SEL

CC3

0.1U_0402_16V4Z

4

+VCC_3IN1

RC11

6.19K_0402_1%

CC1 0.1U_0402_16V4ZCC1 0.1U_0402_16V4Z

12

CC2 0.1U_0402_16V4ZCC2 0.1U_0402_16V4Z

12

1

CC4

CC4 1U_0402_6.3V4Z

1U_0402_6.3V4Z

2

USB20_N4<21> USB20_P4<21>

1 2

+3VS_CR

RST#_R MODE SEL

XTLI USB20_N4

USB20_P4 CR_LED#

RC12

RC12 0_0402_5%

0_0402_5%

1 2

UC1

1

AV_PLL

3

NC

7

NC

9

CARD_3V3

11

D3V3

33

D3V3

8

3V3_IN

44

RST#

45

MODE_SEL

47

XTLO

48

XTLI

4

DM

5

DP

14

GPIO0

2

RREF

12

DGND

32

DGND

6

AGND

46

AGND

RTS5159-VDD-GR

3

RC1 0_0402_5%RC1 0_0402_5%

12

VREG

MS_D4

XD_CLE_SP19 XD_CE#_SP18 XD_ALE_SP17

SD_DAT2/XD_RE#_SP16

SD_DAT3/XD_WE#_SP15

SD_DAT4/XD_WP#/MS_D7_SP13

SD_DAT5/XD_D0/MS_D6_SP12 SD_CLK/XD_D1/MS_CLK_SP11 SD_DAT6/XD_D7/MS_D3_SP10

XD_RDY_SP14

MS_INS#_SP9 SD_DAT7/XD_D2/MS_D2_SP8 SD_DAT0/XD_D6/MS_D0_SP7 SD_DAT1/XD_D3/MS_D1_SP6

XD_D5_SP5

XD_D4/SD_DAT1_SP4

SD_CD#_SP3

SD_WP_SP2

XD_CD#_SP1

EEDI

XTAL_CTR

MS_D5

EEDO EECS EESK

SD_CMD

10 22 30

NC

43 42 41 40 39 38 37 35 34 31 29 28 27 26 25 23 21 20 19 18

13 24

15 16 17 36

1

2

SD_DATA2 SD_DATA3

SD_MS_CLK MS_DATA3_SD_DATA6 MSCD# MS_DATA2_SD_DATA7 SD_MS_DATA0 MS_DATA1 MSBS SD_DATA1 SDCD# SDWP#

XTAL_CTR

SDCMD

2

CC5

CC5 1U_0402_6.3V4Z

1U_0402_6.3V4Z

1 2

RC4

RC4 22_0402_5%

22_0402_5% RC6

RC6 22_0402_5%

22_0402_5%

SDCLK

MSCLK

1 2

RC5

RC5 10_0402_5%@

10_0402_5%@ RC7

RC7 10_0402_5%@

10_0402_5%@

1

For EMI

CC6

CC6 10P_0402_50V8J@

10P_0402_50V8J@ CC7

CC7 10P_0402_50V8J@

10P_0402_50V8J@

< Card Reader LED >

< 3 in 1 Card Reader >

JREAD

+3VS

12

RC13

RC13 120_0402_5%

120_0402_5%

21

DC1

DC1 HT-110UYG-CT_YEL/GRN

HT-110UYG-CT_YEL/GRN

Vf=1.9V(typ),2.4V(max)

B B

< 48MHz >

CLK_48M_CR<16>

A A

CR_LED#

CR_LED: Low when card reader is being accessed.

Cost-down option

RC14

RC14 0_0402_5%

0_0402_5%

1 2

RC15

+3VS_CR

1 2

5

RC15 0_0402_5%

0_0402_5%

XTAL_CTR

XTLI

For EMI

12

R925

R925 33_0402_5%

33_0402_5%

@

1

@

C919

C919 22P_0402_50V8J

22P_0402_50V8J

2

22 23

TAITW_R009-125-LR_RV

RNCC

USB AUTO DE-LINK

0

47P

NC

680P

NC

10K

180P

10K

680P

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

GND1 GND2

3

YES YES

YES

@JREAD

SD-WP SD-DAT1 SD-DAT0

SD-GND

MS-GND

MS-BS

SD-CLK MS-DAT1 MS-DAT0

SD-VCC

MS-DAT2

SD-GND

MS-INS

MS-DAT3

SD-CMD

MS-SCLK

MS-VCC SD-DAT3 MS-GND SD-DAT2

SD-CD

@

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

SDWP# SD_DATA1 SD_MS_DATA0

MSBS SDCLK MS_DATA1 SD_MS_DATA0

MS_DATA2_SD_DATA7 MSCD#

MS_DATA3_SD_DATA6 SDCMD MSCLK

SD_DATA3 SD_DATA2

SDCD#

MS FORMATTER

YES

Compatible with RTS5158E

YES

Compal Secret Data

2009-02-12 2009-02-12

Compal Secret Data

Deciphered Date

Description

Recommended

LED ON LED ON

2

1

CC10

0.1U_0402_16V4Z

2

+VCC_3IN1

1

CC11

CC11 1U_0402_6.3V4Z

1U_0402_6.3V4Z

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

RTS5159 Card Reader

LA-5831P

28 44Wednesday, August 12, 2009

1

1.0

A

1 1

2 2

For EMI

@

HDA_BITCLK_CODEC

3 3

@

1 2

R313 100_0402_5%

@

C618 100P_0402_50V8J

1 2

< SENSE_A & SENSE_B, place close to chip >

RA18

RA18 20K_0402_1%

20K_0402_1%

MIC_SENSE<30>

NBA_PLUG<30>

1 2

MIC@ RA17

MIC@

1 2

RA16

5.1K_0402_1%

5.1K_0402_1% RA17

20K_0402_1%

SENSE_A

SENSE_B

B

RA3

RA3 0_0603_5%

0_0603_5%

+5VS

Remove LDO

12

1

2

CA3

CA3 10U_0805_10V4Z

10U_0805_10V4Z

Int. Mic

Ext. Mic

CA14 100P_0402_50V8JCA14 100P_0402_50V8J

1 2

HDA_BITCLK_CODEC<21>

HDA_SDOUT_CODEC<21>

HDA_RST#_CODEC<21>

HDA_SYNC_CODEC<21>

GPIO63-->SPK_SEL HIGH: HARMAN LOW: NO-BRAND

C

40mil

1

CA4

CA4 10U_0805_10V4Z

10U_0805_10V4Z

2

MIC2_L<30> MIC2_R<30>

MIC1_C_L<30> MIC1_C_R<30>

HDA_SDIN0<21>

SPK_SEL<22>

MUTE#<30>

1

2

RA7

12

MUTE#

RA39 0_0402_5%RA39 0_0402_5%

CA5

0.1U_0402_16V4Z

MIC2_L MIC2_R

MIC1_C_L MIC1_C_R

MONO_IN

HDA_BITCLK_CODEC HDA_SDOUT_CODEC

HDA_SDIN0_R

33_0402_5%

HDA_RST#_CODEC HDA_SYNC_CODEC

SPK_SEL

SENSE_A SENSE_B

1 2

1

CA6

0.1U_0402_16V4Z

2

DGND

UA2

14

LINE2-L

15

LINE2-R

16

MIC2_L

17

MIC2_R

23

LINE1_L

24

LINE1_R

21

MIC1_L

22

MIC1_R

12

BEEP_IN

6

BITCLK

5

SDATA_OUT

8

SDATA_IN

11

RESET#

10

SYNC

2

GPIO0/DMIC_DATA1/2

3

GPIO1/DMIC_DATA3/4

13

SENSE A

34

SENSE B

47

EAPD

43

NC

4

DVSS

7

DVSS

ALC272-GR_LQFP48

+AVDD

AVDD125AVDD2

38

+3VS_DVDD

1

DVDD

9

DVDD_IO

LOUT1_L

LOUT1_R

LOUT2_L

LOUT2_R

SPDIFO1

SPDIFO2 HPOUT_L HPOUT_R

MONO_OUT

DMIC_CLK1/2

DMIC_CLK3/4 LINE2_VREFO LINE1_VREFO

MIC1_VREFO

MIC2_VREFO

CPVREF

VREF

JDREF

CBN CBP

AVSS1 AVSS2

1

CA1

0.1U_0402_16V4Z

2

1

CA7

0.1U_0402_16V4Z

2

D

30mil

35 36 39 41 48 45 33 32

37

46 44 20 18 28 19 31 27 40 30 29

26 42

1

2

1

2

AMP_SPK_L AMP_SPK_R

HPL

RA5 63.4_0402_1%RA5 63.4_0402_1%

HPR

RA6 63.4_0402_1%RA6 63.4_0402_1%

10mil 10mil

CA16 2.2U_0603_6.3V6KCA16 2.2U_0603_6.3V6K

AC_VREF AC_JDREF

CA17

1 2

2.2U_0603_6.3V6K

AGND

CA2

CA2 10U_0805_10V4Z

10U_0805_10V4Z

CA8

CA8 10U_0805_10V4Z

10U_0805_10V4Z

1 2 1 2

1 2

12

1 2

RA12 0_0603_5%RA12 0_0603_5%

1 2

RA13 0_0603_5%RA13 0_0603_5%

1 2

RA14 0_0603_5%RA14 0_0603_5%

1 2

RA15 0_0603_5%RA15 0_0603_5%

1 2

RA19 0_0603_5%RA19 0_0603_5%

+MIC1_VREFO +MIC2_VREFO

RA10

RA10 20K_0402_1%

20K_0402_1%

RA1

RA1 0_0603_5%

0_0603_5%

12

AMP_SPK_L <30>

AMP_SPK_R <30>

HP_L <30> HP_R <30>

1

CA18

CA18 10U_0805_10V4Z

10U_0805_10V4Z

2

+3VS

1

2

E

CA19

0.1U_0402_16V4Z

Add RA19 for EMI

< MONO_IN SOURCE >

RA8

Function

Ext. MIC

EC Beep

PCI Beep

EC_BEEP<32>

SB_SPKR<21>

SENSE A

ImpedanceSense Pin

39.2K 20K

Codec Signals

PORT-A (PIN 39, 41) PORT-B (PIN 21, 22)

10K PORT-C (PIN 23, 24)

4 4

SENSE B

5.1K

39.2K 20K 10K

5.1K

A

PORT-D (PIN 35, 36) PORT-E (PIN 14, 15) PORT-F (PIN 16, 17) PORT-H (PIN 37) PORT-I (PIN 32, 33)

SPK out

Int. MIC

Headphone out

B

/

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009-02-12 2009-02-12

Compal Secret Data

Deciphered Date

1 2

D

RA8 47K_0402_5%

47K_0402_5% RA9

RA9 47K_0402_5%

47K_0402_5%

CA15

0.1U_0402_16V4Z

1 2

12

RA11

RA11 10K_0402_5%

10K_0402_5%

Title

Size Document Number Rev

Date: Sheet of

MONO_IN

1

CA20

0.1U_0402_16V4Z

2

Compal Electronics, Inc.

HD Audio ALC272 Codec

LA-5831P

E

1.0Custom

29 44Wednesday, August 12, 2009

1.0Custom

A

< TPA6017 Medium Range Amplifier >

1 1

CA29

0.033U_0402_16V7K

CA30

0.033U_0402_16V7K

AMP_SPK_R<29>

AMP_SPK_L<29>

GAIN0 GAIN1 Av(db)

2 2

0 0 1 1 1 1

0

15.6

21.6

0.033U_0402_16V7K

CA31

0.033U_0402_16V7K

CA32

0.033U_0402_16V7K

MUTE#<29>

Rin(ohm)

6

90K

10

70K 45K 25K

LINE_C_OUTR

LINE_C_OUTL

MUTE#

17

19

UA3

7

9

5

RIN+

RIN-

LIN+

LIN-

SHUTDOWN

21

+5VS

16

15

6

VDD

PVDD1

GND41GND311GND213GND1

GND5

20

PVDD2

2

GAIN0

3

GAIN1

18

ROUT+

14

ROUT-

4

LOUT+

8

LOUT-

12

NC

10

BYPASS

TPA6017A2_TSSOP20

B

1

CA23

CA23 10U_0805_10V4Z

10U_0805_10V4Z

2

SPKR+

SPKR-

SPKL+

SPKL-

Keep 10 mil width

AMP_BYPASS

1

CA24

0.1U_0402_16V4Z

2

CA33

0.47U_0603_10V7K

1

2

12

RA27

RA27 100K_0402_5%

100K_0402_5%

12

RA29

@ RA29

@

100K_0402_5%

CA25

0.1U_0402_16V4Z

10 dB

@

+5VS

12

RA28

RA28 100K_0402_5%

100K_0402_5%

12

RA30

RA30 100K_0402_5%

100K_0402_5%

C

< Ext. Mic >

MIC1_C_L<29> MIC1_C_R<29>

< Int. Mic >

MIC2_L<29>

MIC2_R<29>

< Speaker Connector >

CA21 4.7U_0805_10V4ZCA21 4.7U_0805_10V4Z

12

CA22 4.7U_0805_10V4ZCA22 4.7U_0805_10V4Z

12

MIC@

CA26

CA26 1U_0402_6.3V4Z

1U_0402_6.3V4Z

12

1U_0402_6.3V4Z

12

CA28

MIC@

D

RA21

RA21 1K_0402_5%

1K_0402_5%

12

1K_0402_5%

12

RA22

+MIC2_VREFO

12

RA24

4.7K_0402_5%

MIC@

RA25

RA25 1K_0402_5%

1K_0402_5%

12

CA27

1K_0402_5%

12

RA26

MIC@

CA27

1 2

MIC@

close to Codec

Left Connector

LA3 FBMA-L11-160808-800LMT_0603LA3 FBMA-L11-160808-800LMT_0603

SPKL+ SPKL-

1 2 1 2

LA4 FBMA-L11-160808-800LMT_0603LA4 FBMA-L11-160808-800LMT_0603

Right Connector

LA5 FBMA-L11-160808-800LMT_0603LA5 FBMA-L11-160808-800LMT_0603

SPKR+ SPKR-

1 2 1 2

LA6 FBMA-L11-160808-800LMT_0603LA6 FBMA-L11-160808-800LMT_0603

INT_MIC

220P_0402_50V7K

RA20

4.7K_0402_5%

12

RA23

4.7K_0402_5%

12

For EMI

1 2

SBY100505T-121Y-N

1 2

SBY100505T-121Y-N

close to JMIC

DA9

1

PJDLC05_SOT23-3

DA10

1

PJDLC05_SOT23-3

DA1

DA1 CH751H-40PT_SOD323-2

CH751H-40PT_SOD323-2

21

DA2

DA2 CH751H-40PT_SOD323-2

CH751H-40PT_SOD323-2

21

MIC@

LA12

MIC@

LA11

@DA9

@

2 3

SPK_L1 SPK_L2

@DA10

@

SPK_R1 SPK_R2

E

INT_MIC_L

2 3

MIC1_L

MIC1_R

close to JMIC

DA3

MIC@DA3

MIC@

2 3

PJDLC05_SOT23-3

JMIC

@JMIC

@

1

NC1

2

NC2

ACES_85204-0200N

JSPKL

1

2

ACES_85204-0200N

@

JSPKR

1

2

ACES_85204-0200N

3 4

NC1 NC2

+MIC1_VREFO

1

3 4

@JSPKR

@

3 4

< Volume Control >

3 3

+3VS

CA35

5

SW2

DIP

COM

SW_XRE094_3P

4 4

DIP

4

12

2

A

1

3

B

A

RA33

RA33 10K_0402_5%

10K_0402_5%

12

RA34

RA34 10K_0402_5%

10K_0402_5%

1 2

0.01U_0402_25V7K

RA35

RA35 10K_0402_5%

10K_0402_5%

RA36

RA36 10K_0402_5%

10K_0402_5%

1

CA37

2

+3VS

1 2

5NC1

P

A2Y

G

3

1

CA38

0.01U_0402_25V7K

2

CA35

0.1U_0402_16V4Z

UA4

4

74LVC1G14GW_SOT353-5

B

+3VS

12

RA32

RA32 100K_0402_5%

100K_0402_5%

1

CA36

0.1U_0402_16V4Z

2

1 2 3 4 5 6 7

ENCODER_DIR <32> ENCODER_PULSE <32>

UA5

74LCX74MTC_TSSOP14

CD1# D1 CP1 SD1# Q1 Q1# GND

CD2#

SD2#

14

VCC

13 12

D2

11

CP2

10 09

Q2

08

Q2#

/

+3VS

1

0.1U_0402_16V4Z

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

< HeadPhone JACK >

< Ext.MIC/LINE IN JACK >

CA39

MIC_SENSE<29>

2009-02-12 2009-02-12

C

NBA_PLUG<29>

HP_R<29> HP_L<29>

MIC1_R

LA9 KC FBM-L11-160808-121LMT 0603LA9 KC FBM-L11-160808-121LMT 0603

1 2

LA10 KC FBM-L11-160808-121LMT 0603LA10 KC FBM-L11-160808-121LMT 0603

1 2

Compal Secret Data

L35 KC FBM-L11-160808-121LMT 0603L35 KC FBM-L11-160808-121LMT 0603

1 2

L36 KC FBM-L11-160808-121LMT 0603L36 KC FBM-L11-160808-121LMT 0603

1 2

DA7

1

PJDLC05_SOT23-3

Deciphered Date

JLINE

MIC1_L_R MIC1_L_LMIC1_L

LA-5831P

5 4 3

6 2 1

FOX_JA6333L-B3T0-7F

JEXMIC

5 4 3

6 2 1

FOX_JA6333L-B3T0-7F

E

NBA_PLUG

HP_R_L HP_L_L

DA8

1

PJDLC05_SOT23-3

2 3

D

1

CA40

CA40 100P_0402_50V8J

100P_0402_50V8J

@

2

2 3

MIC_SENSE

1

CA41

CA41 100P_0402_50V8J

100P_0402_50V8J

@

2

Compal Electronics, Inc.

Title

AMP / Audio Jack / HP / SPEAKER / VR

Size Document Number Rev

Date: Sheet of

@JLINE

@

@JEXMIC

@

1.0Custom

30 44W ednesday, August 12, 2009

1.0Custom

A

B

C

D

E

< SPI Flash 8Mb*1 >

1

C786

0.1U_0402_16V4Z

2

1 1

1

C877

@

10P_0402_50V8J

2

1

C878

@

10P_0402_50V8J

2

< LPC Debug Port >

Please place the PAD under DDR DIMM.

+3VS

H1

R622

1 2

R622 0_0402_5%

0_0402_5%

LPC_AD3

LPC_AD1

LPC_FRAME#

7

8

9

10

DEBUG_PAD

SERIRQ<20,32>

2 2

LPC_AD3<20,32>

LPC_AD1<20,32>

LPC_FRAME#<20,32>

SERIRQ

+3VL

20mils

SPI_CS#<32>

SPI_CLK<32>

@H1

@

56

4

3

2

1

SPI_CS# SPI_CLK

PLT_RST#

LPC_AD2

LPC_AD0

1 2 2

1

U46

8

VCC

3

W

7

HOLD

1

S

6

C

5

D

MX25L8005M2C-15G

R634

@

22_0402_5%

C639

@

22P_0402_50V8J

4

VSS

2

Q

PLT_RST# <12,15,20,26,27,32>

LPC_AD2 <20,32>

LPC_AD0 <20,32>

CLK_PCI_SIO2 <20,24>

EC_SI_SPI_SO <32>EC_SO_SPI_SI<32>

< MDC 1.5 Conn >

RES0 RES1

3.3V GND3 GND4

@

2 4 6 8 10 12

+3VALW

HDA_BITCLK_MDC

1

MDC@

C780

4.7U_0805_10V4Z

2

12

R496

@

10_0402_5%

2

C777

@

10P_0402_50V8J

1

HDA_BITCLK_MDC <21>

JMDC

1

HDA_SDOUT_MDC<21> HDA_SYNC_MDC<21>

HDA_SDIN1<21> HDA_RST#_MDC<21>

R495 33_0402_5%MDC@ R495 33_0402_5%MDC@

1 2

HDA_SDOUT_MDC HDA_SYNC_MDC

HDA_SDIN1_MDC HDA_RST#_MDC

GND1

3

IAC_SDATA_OUT

5

GND2

7

IAC_SYNC

9

IAC_SDATA_IN

11

IAC_RESET#

Connector for MDC Rev1.5

1

MDC@

C778

C778 1000P_0402_50V7K

1000P_0402_50V7K

2

IAC_BITCLK

GND13GND14GND15GND16GND17GND

+3VALW

1

MDC@

C779

0.1U_0402_16V4Z

2

ACES_88018-124G

18

For EMI

KEYBOARD CONN.

KSI[0..7]

KSO[0..15]

3 3

4 4

JKB

@JKB

@

34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1

ACES_88170-3400

CAPS_LED# CURS_LED# NUM_LED#

A

KSO2 KSO1 KSO0 KSO4 KSO3 KSO5 KSO14 KSO6 KSO7 KSO13 KSO8 KSO9 KSO10 KSO11 KSO12 KSO15 KSI7 KSI2 KSI3 KSI4 KSI0 KSI5 KSI6 KSI1

R509 300_0402_5%R509 300_0402_5%

KSI[0..7] <32> KSO[0..15] <32>

1 2

R502 300_0402_5%R502 300_0402_5%

1 2

R503 300_0402_5%R503 300_0402_5%

12

+3VS

+3VS CAPS_LED# <32> CURS_LED# <32> NUM_LED# <32>

KSO2 KSO1 KSO0 KSO4 KSO3 KSO5

KSO14

KSO6 KSO7

KSO13

KSO8

KSO9 KSO10 KSO11 KSO12 KSO15

KSI7 KSI2 KSI3 KSI4 KSI0 KSI5 KSI6

KSI1 CAPS_LED# CURS_LED# NUM_LED#

1 2

C725 100P_0402_50V8JC725 100P_0402_50V8J

1 2

C717 100P_0402_50V8JC717 100P_0402_50V8J

1 2

C721 100P_0402_50V8JC721 100P_0402_50V8J

1 2

C609 100P_0402_50V8JC609 100P_0402_50V8J

1 2

C724 100P_0402_50V8JC724 100P_0402_50V8J

1 2

C728 100P_0402_50V8JC728 100P_0402_50V8J

1 2

C730 100P_0402_50V8JC730 100P_0402_50V8J

1 2

C715 100P_0402_50V8JC715 100P_0402_50V8J

1 2

C732 100P_0402_50V8JC732 100P_0402_50V8J

1 2

C733 100P_0402_50V8JC733 100P_0402_50V8J

1 2

C740 100P_0402_50V8JC740 100P_0402_50V8J

1 2

C737 100P_0402_50V8JC737 100P_0402_50V8J

1 2

C729 100P_0402_50V8JC729 100P_0402_50V8J

1 2

C738 100P_0402_50V8JC738 100P_0402_50V8J

1 2

C718 100P_0402_50V8JC718 100P_0402_50V8J

1 2

C736 100P_0402_50V8JC736 100P_0402_50V8J

1 2

C716 100P_0402_50V8JC716 100P_0402_50V8J

1 2

C741 100P_0402_50V8JC741 100P_0402_50V8J

1 2

C726 100P_0402_50V8JC726 100P_0402_50V8J

1 2

C723 100P_0402_50V8JC723 100P_0402_50V8J

1 2

C731 100P_0402_50V8JC731 100P_0402_50V8J

1 2

C739 100P_0402_50V8JC739 100P_0402_50V8J

1 2

C735 100P_0402_50V8JC735 100P_0402_50V8J

1 2

C734 100P_0402_50V8JC734 100P_0402_50V8J

1 2

C722 100P_0402_50V8JC722 100P_0402_50V8J

1 2

C727 100P_0402_50V8JC727 100P_0402_50V8J

1 2

C714 100P_0402_50V8JC714 100P_0402_50V8J

B

Left switch Right Switch

SW7

SMT1-05_4P

1

2

D86

D86 PJDLC05_SOT23-3

PJDLC05_SOT23-3

@

2

TP_SWL<33> TP_SWR<33>

1

C889

180P_0402_50V8J

@

3

2

1

3 4

5

6

180P_0402_50V8J

For EMI For EMI

/

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009-02-12 2009-02-12

Compal Secret Data

Deciphered Date

D

SW8

SW8 SMT1-05_4P

SMT1-05_4P

1

TP_SWRTP_SWL

2

1

C890

2

@

Title

Size Document Number Rev

Date: Sheet of

2

3

D85

D85 PJDLC05_SOT23-3

PJDLC05_SOT23-3

@

1

Compal Electronics, Inc.

SPI / LPC / MDC

LA-5831P

E

3 4

5

6

31 44Wednesday, August 12, 2009

1.0Custom

A

B

C

D

E

+3VL +3VL_EC

12

R545

@ R545

@

20M_0402_5%

+3VL_EC

+EC_AVCC

GATEA20 KB_RST# SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

CLK_PCI_EC PLT_RST# ECRST# EC_SCI# WL_LED#

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

PM_SLP_S3# PM_SLP_S5# EC_SMI# LID_SW# ESB_CK ESB_DA

CAP_RST# FAN_SPEED1 VLDT_EN E51_TXD E51_RXD ON/OFFBTN# PWR_SUSP_LED# NUM_LED#

CRY1

CRY2

+3VL_EC

1

2

10 12

13 37 20 38

55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82

77 78 79 80

14 15 16 17 18 19 25 28 29 30 31 32 34 36

122 123

L80 0_0603_5%L80 0_0603_5%

1 2

C805

0.1U_0402_16V4Z

1 1

+3VS

2 2

+3VL

+5VS

+3VALW

+3VL

3 3

Add for KB926D2 issue. Please refer to KB926D-AN1-100 for detail

4 4

Reserve for EMI request

CLK_PCI_EC<20,24>

+3VL

1 2

C810

@ C810

@

15P_0402_50V8J

1 2

R533 47K_0402_5%R533 47K_0402_5%

1 2

C811 0.1U_0402_16V4ZC811 0.1U_0402_16V4Z

R9862.2K_0402_5% R9862.2K_0402_5%

12

R9872.2K_0402_5% R9872.2K_0402_5%

12

R9882.2K_0402_5% R9882.2K_0402_5%

12

R9892.2K_0402_5% R9892.2K_0402_5%

12

R9914.7K_0402_5% R9914.7K_0402_5%

12

R9924.7K_0402_5% R9924.7K_0402_5%

12

R995100K_0402_5% R995100K_0402_5%

R996100K_0402_5% R996100K_0402_5%

R99847K_0402_5% R99847K_0402_5%

R99947K_0402_5% R99947K_0402_5%

R99310K_0402_5% R99310K_0402_5%

12

R99410K_0402_5% R99410K_0402_5%

12

1 2

12

EC_SMB_DA2

EC_SMB_CK2

EC_SMB_DA1

EC_SMB_CK1

TP_CLK

TP_DATA

LID_SW#

ON/OFFBTN#

KSO1

KSO2

SYSON

SUSP#

R530

@ R530

@

33_0402_5%

KSI[0..7]<31>

KSO[0..15]<31>

1 2

Y7

2

NC

3

NC

32.768KHZ 12.5PF Q13MC14610002

1 2

GATEA20<21> KB_RST#<21>

SERIRQ<20,31>

LPC_FRAME#<20,31>

LPC_AD3<20,31> LPC_AD2<20,31> LPC_AD1<20,31> LPC_AD0<20,31>

PLT_RST#<12,15,20,26,27,31>

EC_SCI#<21>

WL_LED#<33>

KSI[0..7] KSO[0..15]

EC_SMB_CK1<36> EC_SMB_DA1<36> EC_SMB_CK2<7> EC_SMB_DA2<7>

PM_SLP_S3#<21> PM_SLP_S5#<21> EC_LID_OUT# <21> EC_SMI#<21> LID_SW#<33>

ESB_CK<33> ESB_DA<33>

CAP_RST#<33>

FAN_SPEED1<5> VLDT_EN<34> E51_TXD<27> E51_RXD<27>

ON/OFFBTN#<33>

PWR_SUSP_LED#<33>

NUM_LED#<31>

C813

C813 15P_0402_50V8J

15P_0402_50V8J

1

OSC

4

OSC

C815

C815 15P_0402_50V8J

15P_0402_50V8J

L25

L25 0_0603_5%

0_0603_5%

12

U33

1

GA20/GPIO00

2

KBRST#/GPIO01

3

SERIRQ#

4

LFRAME#

5

LAD3

7

LAD2

8

LAD1

LPC & MISC

LAD0 PCICLK

PCIRST#/GPIO05 ECRST# SCI#/GPIO0E CLKRUN#/GPIO1D

KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24

Int. K/B

KSO5/GPIO25

Matrix

KSO6/GPIO26 KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49

SCL1/GPIO44 SDA1/GPIO45 SCL2/GPIO46 SDA2/GPIO47

6

PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 LID_SW#/GPIO0A SUSP#/GPIO0B PBTN_OUT#/GPIO0C EC_PME#/GPIO0D EC_THERM#/GPIO11 FAN_SPEED1/FANFB1/GPIO14 FANFB2/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 ON_OFF/GPIO18 PWR_LED#/GPIO19 NUMLED#/GPIO1A

XCLK1 XCLK0

1 2

1

C806

0.1U_0402_16V4Z

2

SM Bus

+EC_AVCC

9

22

33

96

111

125

VCC

PWM Output

AD Input

DA Output

PS2 Interface

SPI Device Interface

SPI Flash ROM

GPIO

GND

11

24

35

94

113

C816

0.1U_0402_16V4Z

1

C807

C807 1000P_0402_50V7K

1000P_0402_50V7K

2

67

AVCC

INVT_PWM/PWM1/GPIO0F

BEEP#/PWM2/GPIO10

FANPWM1/GPIO12

ACOFF/FANPWM2/GPIO13

BATT_TEMP/AD0/GPIO38

BATT_OVP/AD1/GPIO39

ADP_I/AD2/GPIO3A

AD3/GPIO3B AD4/GPIO42

SELIO2#/AD5/GPIO43

DAC_BRIG/DA0/GPIO3C

EN_DFAN1/DA1/GPIO3D

IREF/DA2/GPIO3E

DA3/GPIO3F

PSCLK1/GPIO4A PSDAT1/GPIO4B PSCLK2/GPIO4C

PSDAT2/GPIO4D

TP_CLK/PSCLK3/GPIO4E

TP_DATA/PSDAT3/GPIO4F

SDICS#/GPXOA00 SDICLK/GPXOA01

SDIDO/GPXOA02

SDIDI/GPXID0

SPIDI/RD#

SPIDO/WR#

SPICLK/GPIO58

CIR_RX/GPIO40

CIR_RLC_TX/GPIO41

FSTCHG/SELIO#/GPIO50

BATT_CHGI_LED#/GPIO52

CAPS_LED#/GPIO53

BATT_LOW_LED#/GPIO54

SUSP_LED#/GPIO55

SYSON/GPIO56

VR_ON/XCLK32K/GPIO57

AC_IN/GPIO59

EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04

EC_ON/GPXO05

EC_SWI#/GPXO06

ICH_PWROK/GPXO06

GPO

BKOFF#/GPXO08

WL_OFF#/GPXO09

GPXO10 GPXO11

PM_SLP_S4#/GPXID1

ENBKL/GPXID2

GPI

AGND

KB926QFD3_LQFP128_14X14

69

ECAGND

L81 0_0603_5%L81 0_0603_5%

1

C808

0.1U_0402_16V4Z

2

SPICS#

GPXID3 GPXID4 GPXID5 GPXID6 GPXID7

V18R

INVT_PWM_R

21

EC_BEEP

23 26

ACOFF

27

BATT_TEMPA

63

BATT_OVP

64

ADP_I_R

65

ADP_V

66 75 76

DAC_BRIG

68

EN_DFAN1

70

IREF

71

CHGVADJ

72

USB_EN#2

83

USB_EN#0

84

ENCODER_DIR

85

ENCODER_PULSE

86

TP_CLK

87

TP_DATA

88

97

WOL_EN#

98

USB_OC#2

99

VGATE

109

EC_SI_SPI_SO

119

EC_SO_SPI_SI

120

SPI_CLK_R

126

SPI_CS#

128

73

CAP_INT#

74

FSTCHG

89

BATT_FULL_LED#

90

CAPS_LED#

91

BATT_CHG_LOW_LED#

92

PWR_ON_LED#

93

SYSON

95

CPU_VCORE_ENABLE

121

ACIN_D

127

EC_RSMRST#

100

EC_LID_OUT#

101

EC_ON

102 103

SB_PWRGD

104

BKOFF#_R

105

WL_OFF#

106

CURS_LED#

107 108

110

UMA_ENBKL

112 114

EC_THERM#

115

SUSP#

116

PBTN_OUT#

117

USB_OC#0

118

C814 4.7U_0805_10V4ZC814 4.7U_0805_10V4Z

124

12

1

C809

C809 1000P_0402_50V7K

1000P_0402_50V7K

2

12

EC_BEEP <29> ACOFF <37>

BATT_TEMPA <36>

BATT_OVP <37>

ADP_V <37>

DAC_BRIG <18> EN_DFAN1 <5> IREF <37> CHGVADJ <37>

USB_EN#2 <25>

USB_EN#0 <25> ENCODER_DIR <30> ENCODER_PULSE <30>

TP_CLK <33>

TP_DATA <33>

WOL_EN# <26,34>

USB_OC#2 <21,25>

VGATE <42>

EC_SI_SPI_SO <31> EC_SO_SPI_SI <31>

SPI_CS# <31>

CAP_INT# <33> FSTCHG <37> BATT_FULL_LED# <33> CAPS_LED# <31> BATT_CHG_LOW_LED# <33>

PWR_ON_LED# <33>

SYSON <34,40>

EC_RSMRST# <21>

EC_ON <33>

SB_PWRGD <21,42> WL_OFF# <27>

CURS_LED# <31>

UMA_ENBKL <12> EC_THERM# <22>

SUSP# <34,39>

PBTN_OUT# <21>

USB_OC#0 <21,25>

1 2

Power has removed OVP component

1 2

C812

C812 100P_0402_50V8J

100P_0402_50V8J

R1024

R1024 100K_0402_5%

100K_0402_5% C896

C896

0.22U_0603_16V4Z

ECAGND

ADP_I <37>

Reserve pull high for cap. sensor

CAP_INT#

ESB_CK

ESB_DA

R1025 4.7K_0402_5%

R1033 4.7K_0402_5%

R1034 4.7K_0402_5%

For EMI

R74

1 2

0_0402_5%

R541

1

2

10K_0402_5%

12

ACIN_D

C607

C607 10P_0402_50V8J

10P_0402_50V8J

@

SPI_CLK <31>

CPU_VCORE_ENABLE <42>

1 2

D33

2 1

CH751H-40PT_SOD323-2

C326

C326 100P_0402_50V8J

100P_0402_50V8J

12

R560

R560 150K_0402_5%

150K_0402_5%

Add R344 and R345 for EC pin damage issue

R344

BKOFF#_R

INVT_PWM_R

R344

1 2

R345

1 2

33_0402_5%

@

1 2

@

1 2

@

1 2

+3VL

ACIN <22,33,35>

BKOFF# <18>

INVT_PWM <18>

/

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009-02-12 2009-02-12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

ENE KB926 D3

LA-5831P

32 44Wednesday, August 12, 2009

E

1.0Custom

A

B

C

D

E

CS/B Connector

Power Button/ PWR/B Touch Pad Connector

@

JPOWER

1

2

G

3 4

13

D

Q19

Q19 2N7002_SOT23-3

2N7002_SOT23-3

S

ON/OFFBTN#

51_ON# <35>

+3VL

1 1

TOP side

BTM side

For Debug

SW5

1 2

6

SW6

1 2

6

3 4

SMT1-05-A_4P

5

3 4

SMT1-05-A_4P

5

R512

R512 100K_0402_5%

100K_0402_5%

1 2

ON/OFFBTN#

EC_ON<32>

10K_0402_5%

5

GND

6

GND

ACES_85201-04051

ON/OFFBTN# <32>

R514

1 2

+5VS

1U_0402_6.3V4Z

R111

0_0603_5%

C713

12

TP_CLK<32>

2

TP_DATA<32>

TP_SWL<31> TP_SWR<31>

1

PJDLC05_SOT23-3

D60

@

+5VS_TOUCH

TP_CLK TP_DATA TP_SWL TP_SWR

2

3

1

@

JTOUCH

1

2

3

4

5

6

7

GND

8

GND

ACES_85201-06051

ESB_CK<32> ESB_DA<32>

ESB_DA_L

ESB_CK_L

CAP_INT#<32> CAP_RST#<32>

L93 FBMA-11-100505-301T_0402@L93 FBMA-11-100505-301T_0402@ L94 FBMA-11-100505-301T_0402@L94 FBMA-11-100505-301T_0402@

For EMI

@

1 2

R1015

100_0402_5%

@

1 2

R1016

100_0402_5%

+3VL

1 2 1 2

1

D87 PJDLC05_SOT23-3

PJDLC05_SOT23-3

1 2

C894

100P_0402_25V8K

1 2

C895

100P_0402_25V8K

R1030 0_0603_5%@R1030 0_0603_5%@ R1031 0_0402_5%@R1031 0_0402_5%@

1 2

R1032 0_0402_5%@R1032 0_0402_5%@

1 2

2 3

@D87

@

12

@

20 mil width

+3VL_CS

ESB_CK_L ESB_DA_L

C898 10P_0402_50V8J@C898 10P_0402_50V8J

C897 10P_0402_50V8J@C897 10P_0402_50V8J

C899 10P_0402_50V8J@C899 10P_0402_50V8J

1

@

2

JCS

@JCS

@

1

2

3

4

5

6

7

GND

8

GND

ACES_85201-06051

DC-IN LED

2 2

1 2

+3VALW

R515 120_0402_5%R515 120_0402_5%

Vf=1.9V(typ),2.4V(max)

D54

2 1

HT-110UYG-CT_YEL/GRN

1 3

D

2N7002_SOT23-3

BATT CHARGE/FULL LED

D38

< Ultra Bright Yellow Green >

+3VALW

3 3

1 2

R549 120_0402_5%R549 120_0402_5%

1

HT-210UD/UYG_AMB/GRN

Vf=1.9V(typ),2.4V(max) for amber Vf=2.0V(typ),2.4V(max) for green If=30mA(max)

3

2

< Ultra Bright Amber >

ACIN <22,32,35>

2

G

Q20

S

BATT_FULL_LED# <32>

BATT_CHG_LOW_LED# <32>

+3VALW

POWER ON/SUSPEND LED

< Ultra Bright Yellow Green >

D49

1 2

R521 120_0402_5%R521 120_0402_5%

1

HT-210UD/UYG_AMB/GRN

Vf=1.9V(typ),2.4V(max) for amber Vf=2.0V(typ),2.4V(max) for green If=30mA(max)

3

2

< Ultra Bright Amber >

PWR_ON_LED# <32>

PWR_SUSP_LED# <32>

Lid SW

Screw Hole

For EMI

WLAN LED

+3VS

1 2

R550 120_0402_5%R550 120_0402_5%

HDD LED

4 4

+3VS

1 2

R548 120_0402_5%R548 120_0402_5%

Vf=1.9V(typ),2.4V(max)

D50

HT-110UD_1204_AMBER

R546

D46

R546

10K_0402_5%

+3VS

2 1

HT-110UYG-CT_YEL/GRN

Vf=1.9V(typ),2.4V(max)

A

12

3

Q18B 2N7002DW-T/R7_SOT363-6Q18B 2N7002DW-T/R7_SOT363-6

6 1

5

Q18A

Q18A 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

4

WL_LED# <32>

2

SATA_LED# <22>

C199 0.22U_0603_16V4Z@ C199 0.22U_0603_16V4Z@

+5VALW

B

1 2

C200 0.22U_0603_16V4Z@ C200 0.22U_0603_16V4Z@

1 2

C201 0.22U_0603_16V4Z@ C201 0.22U_0603_16V4Z@

1 2

C202 0.22U_0603_16V4Z@ C202 0.22U_0603_16V4Z@

1 2

C203 0.22U_0603_16V4Z@ C203 0.22U_0603_16V4Z@

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2008/04/14 2009/04/14

Compal Secret Data

Deciphered Date

MINI CARD-1

D

+3VALW

U34

U34 APX9132ATI-TRL_SOT23-3

MDC

APX9132ATI-TRL_SOT23-3

VDD2VOUT

1

C645

0.1U_0402_16V4Z

2

H2

H_3P0

1

@

H12

H_3P0

1

@

H16

H_3P0N

1

@

H32

H27

1

H3

1

H13

1

H_3P8

@

H_1P2

@

H_3P0

@

H_3P0

@

H37

H_5P0X3P0N

1

@

H34

H33

H4

H_3P0

1

@

H14

H_3P0

1

@

H38

CPU

H_3P8

1

@

H_1P2

1

@

GND

1

10P_0402_50V8J

H6

H_3P0

1

@

H15

H_3P0

1

@

H_11P0X4P0N

1

@

INS87990490

1

3

H7

1

H11

1

H_3P7

@

C647

H_3P0

@

H_5P0

@

1

2

H8

H_3P0

1

@

H22

H_3P8

1

@

PCB Fedical Mark PAD

FD1@FD1

FD2@FD2

@

1

FD4@FD4

FD3@FD3

@

1

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

LED/LID/PB/FB/SCREW HOLE

LID_SW# <32>

H9

H_3P0

1

@

H19

H_4P8X3P8

1

@

LA-5831P

E

H10

H_3P0

1

@

H21

H_3P8X4P8

1

@

1.0

33 44Wednesday, August 12, 2009

1.0

A

< +5VALW TO +5VS >

+5VALW

Q35

S

D

S

D

S

D

G

D

SI4800BDY_SO8

1 2 3

RUNON

4

8 7 6 5

1

C864

4.7U_0805_10V4Z

C864

2

1 1

+5VS

Inrush current = 0A

1

C833

C833 1U_0402_6.3V4Z

1U_0402_6.3V4Z

2

1

C835

4.7U_0805_10V4Z

2

< +3VALW TO +3VS >

+3VALW +3VS

Q14

8

S

D

7

S

D

6

S

D

5

G

D

1

SI4800BDY_SO8

C840

4.7U_0805_10V4Z

2 2

2

1 2 3 4

1

2

1

2

RUNON

C834

0.01U_0402_25V7K

Inrush current = 0A

1

C838

C839

C839 1U_0402_6.3V4Z

1U_0402_6.3V4Z

C838

4.7U_0805_10V4Z

2

12

R556

@

10M_0402_5%

< +3VALW TO +3V_LAN >

+3VALW

R17

R17 100K_0402_5%

100K_0402_5%

1 2

WOL_EN#

WOL_EN#<26,32>

3 3

1 2

R19

R19 47K_0402_5%

47K_0402_5%

2

C880

0.1U_0402_16V7K

1

C182

0.01U_0402_25V7K

2

< close to PQ20, must EMI confirm >

13

D

Q17

2

G

S

2N7002_SOT23-3

+3VALW +3V_LAN

G

2

1 3

1

@

2

SUSP

Vgs=-4.5V, Id=3A Rds<97m ohm

S

Q38

D

AO3413_SOT23

C679

Inrush current = 0A

4.7U_0805_10V4Z

B

R152

R152 750K_0402_1%

750K_0402_1%

12

@ PJ29

@

2

PJ29

2

JUMP_43X79

1

+VSB

1

C680

C680 1U_0402_6.3V4Z

1U_0402_6.3V4Z

2

C

< +1.8V TO +1.8VS >

+1.8V

1

C842

4.7U_0805_10V4Z

2

Q4

IRF8113PBF_SO8

8 7

5

4

1.8VS_ENABLE

12

R809

R809 10M_0402_5%

10M_0402_5%

1 2 36

< +1.2VALW TO +1.2V_HT >

+1.2VALW

1

C847

4.7U_0805_10V4Z

2

For +1.2VALW OVP issue Just mount for TPS51117

12

R367

@

1K_0402_5%

Q11

IRF8113PBF_SO8

8 7

5

< Inversion of SYSON, SUSP#, VLDT_EN, EC_ON >

+5VL+5VL

12

R596

R596 100K_0402_5%

100K_0402_5%

61

3

4

Q142A

Q142A 2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

2

SYSON#<41>

2N7002DW-7-F_SOT363-6

R595

100K_0402_5%

SYSON# SUSP

Q142B

5

+1.8VS

1

2

1

2

4

12

R808

R808 10M_0402_5%

10M_0402_5%

SUSP <41>

SUSP# <32,39>SYSON<32,40>

D

Inrush current = 0A

C848

C848 1U_0402_6.3V4Z

1U_0402_6.3V4Z

C849

0.01U_0402_25V7K

1 2 36

2

1

+1.2V_HT

1

2

1

2

C841

C841 10U_0805_10V4Z

10U_0805_10V4Z

1 2

61

SUSP

2

Q143A

Q143A 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

Inrush current = 0A

C846

C846 1U_0402_6.3V4Z

1U_0402_6.3V4Z

C837

0.01U_0402_25V7K

VLDT_EN<32>

1

2

R138

R138 750K_0402_1%

750K_0402_1%

For power noise issue

C862

4.7U_0805_10V4Z

61

VLDT_EN#

2

Q12A

Q12A 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

+5VL

12

R597

100K_0402_5%

VLDT_EN#

13

D

VLDT_EN

D

2

G

S

+VSB

1

+

C879

@

330U_D2E_2.5VM

2

R233

R233 330K_0402_5%

330K_0402_5%

12

Q53

Q53 2N7002_SOT23-3

2N7002_SOT23-3

E

+VSB

< Discharge circuit >

+5VS +3VS

R239

R239 470_0805_5%

470_0805_5%

1 2 61

Q144A

SUSP

4 4

Q144A 2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

2

A

+1.8VS +0.9V

R279

R279 470_0805_5%

470_0805_5%

1 2 13

D

2

G

D

Q48

Q48 2N7002_SOT23-3

2N7002_SOT23-3

S

VLDT_EN# SYSON#

SUSP

+1.2V_HT +1.8V

R280

R280 470_0805_5%

470_0805_5%

1 2 3

Q12B

Q12B 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

5

4

B

2N7002DW-T/R7_SOT363-6

Q143B

+1.5VS

R293

R292

R284

R284 470_0805_5%

470_0805_5%

1 2 3

5

4

SUSP

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

R288

R288 470_0805_5%

470_0805_5%

1 2 3

Q144B

Q144B 2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

5

4

C

SYSON#

2009-02-12 2009-02-12

R292 470_0805_5%

470_0805_5%

1 2 13

D

Q49

2

G

2N7002_SOT23-3

S

Compal Secret Data

Deciphered Date

SUSP

R293 470_0805_5%

470_0805_5%

1 2 13

D

Q50

2

G

2N7002_SOT23-3

S

D

+1.1VS

R294

R294 470_0805_5%

470_0805_5%

1 2 13

D

SUSP

D

Q52

2

G

2N7002_SOT23-3

S

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

DC / DC Circuits

LA-5831P

34 44Wednesday, August 12, 2009

E

1.0

A

SMB3025500YA_2P

PF1

DC301001M80

PJP1

1

+

2

+

3

1 1

-

4

-

SINGA_2DW -0005-B03@

DC_IN_S1

PF1

21

10A_125V_451010MRL

DC_IN_S2

12

PC1

PC1 1000P_0402_50V7K

1000P_0402_50V7K

SMB3025500YA_2P

12

PC2

100P_0402_50V8J

PL1

1 2

B

12

PC3

PC3 1000P_0402_50V7K

1000P_0402_50V7K

VIN

12

PC4

PC4 100P_0402_50V8J

100P_0402_50V8J

C

PR1

1M_0402_1%

1 2

VS

PR4

8

PU1A

PR2

PR5

ACIN<22,32,33>

1 2

PR7

10K_0402_1%

0_0402_5%

12

PR2

1 2

10K_0402_1%

PD2

PD2 GLZ4.3B_LL34-2

GLZ4.3B_LL34-2

PU1A

P

+

1

0

G

LM358DT_SO8

4

PR4 22K_0402_1%

22K_0402_1%

1 2

3 2

-

PC6

12

VIN

12

D

PR3

84.5K_0402_1%

PR6

20K_0402_1%

12

PC5

PC5 1000P_0402_50V7K

1000P_0402_50V7K

VIN

PD3

PD3 RLS4148_LL34-2

RLS4148_LL34-2

BATT+

RLS4148_LL34-2

CHGRTCP

2 2

51_ON#<33>

PR15

560_0603_5%

+CHGRTC

3 3

PJ1

+3VALW P +3VALW

+5VALW P

+VSBP +VSB

2

JUMP_43X118@

(5A,200mils ,Via NO.= 10)

JUMP_43X118@

OCP(min)=7.7A

PJ5

2

JUMP_43X118@

OCP(min)=7.9A

PJ8

2

JUMP_43X39@

1 2

112

PR16

560_0603_5%

1 2

+5VALW

(120mA,40mils ,Via NO.= 1)

PJ11

2

4 4

(0.5A,20mils ,Via NO.=1)

112

JUMP_43X39@

+2.5VS+2.5VSP

A

12

PD4

TP0610K-T1-E3_SOT23-3

PR11

200_0603_5%

1 2

12

PR12

100K_0402_1%

1 2

PR13

22K_0402_1%

RTCVREF

3.3V

12

PU2 G920AT24U_SOT89-3PU2 G920AT24U_SOT89-3

3

PC9

PC9 10U_0805_10V4Z

10U_0805_10V4Z

+1.8VP +1.8V

(8A,320mils ,Via NO.= 16)

+3VLP +3VL

(100mA,40mils ,Via NO.= 2)

(7.0A,280mils ,Via NO.=14)

(2A,80mils ,Via NO.= 4)

TP0610K-T1-E3_SOT23-3

N1

12

PC7

0.22U_1206_25V7K

OUT

IN

GND

1

PJ2

2

JUMP_43X118@

JUMP_43X118@ PJ4

PJ4

2

JUMP_43X118@

OCP(min)=8.87A

PJ6

2

JUMP_43X39@

PJ9

2

JUMP_43X118@

OCP(min)=9.32A

PJ12

2

JUMP_43X79@

2

112

PQ1

N2

112

2

12

PR14

PR14 200_0603_5%

200_0603_5%

12

PC10

1U_0805_25V4Z

1 2

12

PR10

PR9

68_1206_5%

13

PR10 68_1206_5%

68_1206_5%

12

PC8

0.1U_0603_25V7K

VS

RTC Battery

PBJ1

- +

MAXEL_ML1220T10@

SP093MX0000

PJ3

VL +5VL

+1.2VALW P

+NB_CORE+NB_COREP

+0.9V+0.9VP

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

2

112

JUMP_43X39@

(100mA,40mils ,Via NO.= 2)

(5A,200mils ,Via NO.=10)

JUMP_43X39@

PJ7

2

112

JUMP_43X118@

OCP(min)=7.78A

PJ10

2

112

JUMP_43X118@

+1.2VALW

(3A,120mils ,Via NO.=6)

PJ13

2

112

JUMP_43X79@

(2.0A,80mils ,Via NO.=4)

JUMP_43X79@

2008/04/14 2009/04/14

+VDDNB+VDDNBP

+1.5VS+1.5VSP

Compal Secret Data

+RTCBATT

12

Deciphered Date

C

+RTCBATT

Vin Detector

High 18.384 17.901 17.430 Low 17.728 17.257 16.976

Title

Size Document Number Rev

Date: Sheet of

0.1U_0603_25V7K

1 2

PR8

10K_0402_1%

Compal Electronics, Inc.

DCIN/DECTOR

RTCVREF

LA-5831P

D

35 44Wednesday, August 12, 2009

1.0

A

B

C

D

PH1 under CPU botten side :

CPU thermal protection at 92 degree C Recovery at 56 degree C

PF2

1 1

2 2

PJP2

1 2 3 4

10 11 12 13

5 6

GND GND

7 8

GND

9

GND

OCTEK_BTJ-09HA1G@

BATT_S1

1 2 3 4 5 6 7 8 9

EC_SMDA EC_SMCA

PR23

100_0402_1%

1 2

PF2

15A_65V_451015MRL

PR24

PR24 100_0402_1%

100_0402_1%

1 2

12

21

12

PR28

PR28 1K_0402_1%

1K_0402_1%

1 2

PR17

1K_0402_1%

PR21

PR21 1K_0402_1%

1K_0402_1%

1 2

PR26

6.49K_0402_1%

PR18

47K_0402_1%

12

VMB

+3VLP

BATT_TEMPA <32>

EC_SMB_DA1 <32> EC_SMB_CK1 <32>

SMB3025500YA_2P

1 2

12

PC11

PC11 1000P_0402_50V7K

1000P_0402_50V7K

+3VLP

PL2

BATT+

12

PC12

0.01U_0402_25V7K

100K_0402_1%_NCP15WF104F03RC

VL

12

PH1

12

PC14

0.22U_0805_16V7K

0.1U_0603_25V7K

13.7K_0402_1%

1 2

PR25

13.7K_0402_1%

PR22

PC13

TM_REF1

12

PC15

1000P_0402_50V7K

PH2 near main Battery CONN :

12

PR29

PR29 100K_0402_1%

100K_0402_1%

VL

47K_0402_1%

1 2

8

PU3A

3

P

+

2

-

G

LM393DG_SO8

4

PR27

100K_0402_1%

PR20

O

12

VL

PR19

PR19 47K_0402_1%

47K_0402_1%

1 2

1

RLS4148_LL34-2

VL

PD5

12

2

G

2

G

ENTRIP1 <38>

13

D

PQ2

PQ2 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

S

13

D

PQ3

PQ3 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

S

ENTRIP2 <7,38>

BAT. thermal protection at 92 degree C Recovery at 56 degree C

PR31

1 2

8

PU3B

P

O

G

LM393DG_SO8

4

VLVL

PR30

PR30 47K_0402_1%

47K_0402_1%

1 2

7

12

PD6

RLS4148_LL34-2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

BATTERY CONN / OTP

LA-5831P

D

1.0

36 44Wednesday, August 12, 2009

1.0

PQ4

TP0610K-T1-E3_SOT23-3

B+

3 3

VL

PR36

100K_0402_1%

POK<38,39>

4 4

A

1 2

PR37

PR37 0_0402_5%

0_0402_5%

12

2

G

PC19

.1U_0402_16V7K@

22K_0402_1%

13

D

PQ5

PQ5 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

S

PR35

1 2

12

PC16

PR32

100K_0402_1%

0.22U_1206_25V7K

@

13

2

B

+VSBP

12

PC17

0.1U_0603_25V7K

@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PC18

0.22U_0805_16V7K

2008/04/14 2009/04/14

12

PH2

PH2 100K_0402_1%_NCP15WF104F03RC

100K_0402_1%_NCP15WF104F03RC

PR33

13.7K_0402_1%

1 2

12

PR34

16.9K_0402_1%

Compal Secret Data

Deciphered Date

C

TM_REF1

47K_0402_1%

5

+

6

-

A

B

C

D

E

PQ8

12

PC21

0.022U_0402_25V7K

12

PC148

1000P_0402_50V7K

2

12

PR62

@ PR62

@

340K_0402_1%

PR64

@ PR64

@

499K_0402_1%

PR66

@ PR66

@

105K_0402_1%

PQ8 AO4407A_SO8

AO4407A_SO8

1 2 3 6

4

PR42

100K_0402_1%

PR162

1K_0402_1%

PR47

100K_0402_1%

1 2

VREF

PC35

0.01U_0402_25V7K@

PQ12

1 3

ACSET

CHGVADJ<32>

12

PC47

@ PC47

@

0.01U_0402_25V7K

B

1

8 7

2

5

.1U_0402_16V7K

12

PC29

0.1U_0603_25V7K

12

PC40

1U_0603_10V6K

RTCVREF

PR52

100K_0402_1%

1 2

PR60

210K_0402_1%

1 2

PR38

0.015_1206_1%

PC26

1 2

12

PR48

PR48 120K_0402_1%

120K_0402_1%

1 2

0.47U_0603_16V7K

VREF

12

/BATDRV

REGN

4 3

CHGEN#

PU4

ACSET

VADJ

12

PC37

12

1

CHGEN

PC30

0.1U_0603_25V7K

@

2

ACN

3

ACP

4

ACDRV

5

ACDET

6

ACSET

7

ACOP

8

OVPSET

9

AGND

10

VREF

11

VDAC

12

VADJ

13

ACGOOD

14

BATDRV

BQ24751ARHDR_QFN28_5X5

PR59

PR59 0_0402_5%@

0_0402_5%@

VADJ

PR61

PR61 499K_0402_1%

499K_0402_1%

CHGVADJ Pre Cell

3.28V 4.35V

PVCC

BTST

HIDRV

REGN

LODRV

PGND

LEARN

CELLS

SRP SRN BAT

SRSET

IADAPT

28

27

26

25

PH

24

23

22

21

20

19 18 17

29

TP

16

15

100P_0402_50V8J

0V 4V

CHGVADJ



EC DA pin

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

VIN

PR39

3.3_1210_5%

1 2

1 1

2 2

100K_0402_1%

ACOFF

3 3

1 2

PC43

.1U_0402_16V7K

PR41

3.3_1210_5%

PC28

2.2U_0805_25V6K

VREF

12

PR54

12

1 2 12

VREF

2

G

PR58

PR58 340K_0402_1%

340K_0402_1%

1 2

PC25

0.01U_0603_50V7K

1 2

12

PR53

PR53 200K_0402_1%

200K_0402_1%

2

G

13

D

PQ14

PQ14 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

S

OVPSET

8 7 6 5

PR44

PR44 340K_0402_1%

340K_0402_1%

1 2

PR46

54.9K_0402_1%

1 2

PR49

PR49 340K_0402_1%

340K_0402_1%

PR50

54.9K_0402_1%

13

D

PQ13

PQ13 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

S

PQ7

PQ7 FDS4435BZ_SO8

FDS4435BZ_SO8

S

D

S

D

S

D

G

D

ACDET

PR51

100K_0402_1%

1 2

0.1U_0603_25V7K

ACGOOD#

1 2 3 4

1 2

SI2301BDS-T1-E3_SOT23-3

PC41

75W,Iadapter=3.947A,PR38=0.015ohm,PR47=100K,PR48=120K,CP=3.63A

VMB

VS

12

4 4

BATT_OVP<32>

PR65

@ PR65

@

10K_0402_1%

1 2

A

8

PU1B

5

P

+

7

0

6

-

G

LM358DT_SO8

4

12

PC46

0.01U_0402_25V7K

12

B+

PL16

12

PR163

4.7_1206_5%

PR43

0_0603_5%

1 2

REGN

12

PC36

PC36 1U_0603_10V6K

1U_0603_10V6K

CELLS

12

1 2

PR57

10_0603_5%

12

PC141

0.1U_0402_25V6@

0.1U_0402_25V6@ PC27

PC27

0.22U_1206_25V7K

1 2

PD7

12

RLS4148_LL34-2

PC42

0.1U_0603_25V7K

12

PC45

PL16

HCB2012KF-121T50_0805

1 2

PC31

0.1U_0603_25V7K

ACOFF <32>

ADP_I <32>

CHG_B+

578

12

1 2

PQ10

PQ10 AO4466_SO8

AO4466_SO8

3 6

241

10UH_SIL1045RA-100PF_4.5A_30%

1 2

PQ11

PQ11 AO4466_SO8

AO4466_SO8

3 6

241

PR56

PR56 100K_0402_1%

100K_0402_1%

12

PC22

4.7U_1206_25V6K

PL3

49.9K_0402_1%

PC44

0.01U_0402_25V7K

@

IREF Current

2.968V 3A

1.484V 1.5A

Compal Secret Data

2008/04/14 2009/04/14

Compal Secret Data

Deciphered Date

D

PR55

PQ6

1 2 3

2

G

PR160

10K_0402_1%

1 2

LA-5831P

E

VREF

4

1 2 3 4

1 2

13

D

S

12

1 2

PR40

PC20

0.01U_0402_25V7K

100K_0402_1%

1 2

PC23

PC24

4.7U_1206_25V6K

PR45

0.02_1206_1%

1 2

.1U_0402_16V7K

PC38

0.1U_0603_25V7K

IREF <32>

/BATDRV

PC34

1 2

4.7U_1206_25V6K

12

PC32

10U_1206_25V6M

12

100K_0402_1%

4 3

12

PC39

0.1U_0603_25V7K

@

FSTCHG<32>

VIN

12

PR159

309K_0402_1%

12

PR161

47K_0402_1%

Title

Size Document Number Rev

Date: Sheet of

12

PC147

.1U_0402_16V7K

Compal Electronics, Inc.

CHARGER

8

S

D

7

S

D

6

S

D

5

G

D

FDS4435BZ_SO8

PQ9

8

S

D

7

S

D

6

S

D

5

G

D

FDS4435BZ_SO8@

12

PC33

10U_1206_25V6M

PR63

PR63 100K_0402_1%

100K_0402_1%

CHGEN#

PQ15

PQ15 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

ADP_V <32>

37 44Wednesday, August 12, 2009

BATT+

1.0

A

B

C

D

2VREF_51125

1 1

12

PC48

1U_0603_10V6K

PR67

13K_0402_1%

1 2

PR69

150K_0402_1%

BST_3V UG_3V LX_3V LG_3V

PR78

100K_0402_1%

2VREF_51125

PR69

20K_0402_1%

1 2

PR71

1 2

PU5

25

P PAD

7

VO2

8

VREG3

9

VBST2

10

DRVH2

11

LL2

12

DRVL2

12

ENTRIP2

5

6

ENTRIP2

EN0

14

13

1 2

PR79

0_0402_5%@

B++

3

4

VFB2

TONSEL

GND

SKIPSEL

15

16

12

B++

PJ15

2

B+

2 2

Ipeak = 5A Imax = 3.5A F = 305kHz Total Capacitor = 220 uF ESR = 15m Ohm

3 3

112

JUMP_43X118@

PC49

2200P_0402_50V7K

+3VALWP

SSM3K7002FU_SC70-3

12

PC50

10U_1206_25V6M

4.7U_LF919AS-4R7M-P3_5.2A_20%

12

PC142

PC56

220U_6.3V_M

.1U_0402_16V7K@

13

D

PQ20

S

1

+

2

G

PL4

1 2

PR75

4.7_1206_5%

PC58

680P_0603_50V7K

2

G

578

3 6

241

12

578

12

3 6

241

ENTRIP2 <7,36>ENTRIP1 <36>

13

D

PQ21

PQ21 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

S

PQ17

PQ17 AO4466_SO8

AO4466_SO8

PQ18

PQ18 AO4712_SO8

AO4712_SO8

PC53

4.7U_0805_10V6K

+3VLP

12

1 2

2.2_0603_1%

PC54

.1U_0402_16V7K

B+

PR73

PR77

499K_0402_1%

1 2

1

2

VFB1

VREF

ENTRIP1

PGOOD

VBST1

DRVH1

DRVL1

VREG5

VIN

VCLK

17

18

12

PC60

4.7U_0805_10V6K

PC61

0.1U_0603_25V7K

PR68

30K_0402_1%

1 2

PR70

19.6K_0402_1%

1 2

PR72

150K_0402_1%

ENTRIP1

1 2

24

VO1

23 22 21 20

LL1

19

TPS51125RGER_QFN24_4X4

BST_5V UG_5V LX_5V LG_5V

2.2_0603_1%

1 2

VL

PR74

B++

12

PC51

2200P_0402_50V7K

POK <36,39>

PC55

PC55 .1U_0402_16V7K

.1U_0402_16V7K

1 2

12

PC52

10U_1206_25V6M

AO4466_SO8

AO4712_SO8

PQ16

PQ19

578

3 6

241

4.7U_LF919AS-4R7M-P3_5.2A_20%

578

3 6

1 2

12

PR76

12

PC59

241

PL5

+5VALWP

1

4.7_1206_5%

680P_0603_50V7K

12

+

PC57

220U_6.3V_M

PC143

2

PC143

.1U_0402_16V7K@

Ipeak = 5A Imax = 3.5A F = 245kHz Total Capacitor = 220 uF ESR = 15m Ohm

VL

1 2

VS

PR81

100K_0402_1%

4 4

A

PR80

100K_0402_1%

12

PR82

49.9K_0402_1%

12

2

G

PC62

@ PC62

@

0.01U_0402_16V7K

13

D

PQ22

PQ22 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

S

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2008/04/14 2009/04/14

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

3VALW/5VALW

LA-5831P

D

38 44Wednesday, August 12, 2009

1.0

5

D D

51124_B+

12

PC63

PC64

4.7U_1206_25V6K

12

PC65

4.7U_1206_25V6K

4.7U_1206_25V6K 2200P_0402_50V7K

2200P_0402_50V7K

4

PR83

+1.2VALWP

PR83

44.2K_0402_1%

1 2

PR84

75K_0402_1%

1 2

0_0402_5%

PR87

3

PR86

PR85

75K_0402_1%

1 2

PR86

33K_0402_1%

12

+NB_COREP

12

2

51124_B+

PL14

HCB2012KF-121T50_0805

1 2

12

PC137

0.1U_0402_25V6

1

B+

12

PC138

PC139

0.1U_0402_25V6@

578

PQ23

AO4466_SO8

C C

3 6

241

12

4.7_1206_5%

12

680P_0603_50V7K

578

PQ25

PQ25 AO4712_SO8

AO4712_SO8

3 6

241

+1.2VALWP

Ipeak =5A Imax = 3.5A

+1.2VALWP

PC144

PL6

1.8UH_SIL104R-1R8PF_9.5A_30%

1 2

1

12

.1U_0402_16V7K@

12

+

PC71

2

220U_6.3V_M

PC72

4.7U_0805_6.3V6K

PR90

PC75

F = 300kHz Total Capacitor = 220 uF

B B

ESR = 15m Ohm

POK<36,38> SUSP# <32,34>

PC69

.1U_0402_16V7K

PR94

0_0402_5%

.1U_0402_16V7K@

PR88

2.2_0603_1%

12

PC77

12

BST_1.2V

UG_1.2V LX_1.2V LG_1.2V

PC78

1U_0603_10V6K

PU6

25

P PAD

7

PGOOD2

8

EN2

9

VBST2

10

DR VH2

11

LL2

12

DR VL2

PR93

13.7K_0402_1%

1 2

12

6

VO2

VFB2

TRIP2

PGND2

14

13

PR95

3.3_0402_5%

GND

TONSEL

V5FILT

V5IN

15

16

12

PC79

4.7U_0805_10V6K

VFB1

TRIP1

17

12

VO1

24

PGOOD1

23

EN1

BST_NB_COREP

22

VBST1

UG_NB_COREP

21

DR VH1

DR VL1

PGND1

TPS51124RGER_QFN24_4x4

18

PR92

16.5K_0402_1%

+5VALW

LX_NB_COREP

20

LL1

LG_NB_COREP

19

22K_0402_5%

1 2

12

PC80

PC80 .1U_0402_16V7K

.1U_0402_16V7K

PR89

2.2_0603_1%

PR96

.1U_0402_16V7K

12

PC70

1 2

AO4466_SO8

3

4

1

2

5

PQ24

PQ26

AO4712_SO8

578

3 6

241

1.8UH_SIL104R-1R8PF_9.5A_30%

578

3 6

241

PC66

4.7U_1206_25V6K

12

PC67

PL7

1 2

PR91

4.7_1206_5%

PC76

680P_0603_50V7K

12

PC68

4.7U_1206_25V6K

PC68

2200P_0402_50V7K

+1.1V

+NB_COREP

1

12

+

PC145

PC73

1 2

PC74

2

220U_6.3V_M

.1U_0402_16V7K@

4.7U_0805_6.3V6K

.1U_0402_16V7K@

Ipeak =7A Imax = 4.9A F = 240kHz Total Capacitor = 550 uF ESR = 7.5m Ohm

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/04/14 2009/04/14

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

NB_COREP/1.2VALWP

LA-5831P

39 44Wednesday, August 12, 2009

1

1.0

5

D D

PR98

0_0402_5%

SYSON<32,34>

+5VALW

C C

1 2

100_0603_1%

1 2

4.7U_0603_10V6K

PR101

PC86

4

12

PC83

PC83 .1U_0402_16V7K

.1U_0402_16V7K

@

12

PC88

47P_0402_50V8J@

1 2

PR103

28.7K_0402_1%

1 2

12

PR104

20.5K_0402_1%

3

578

PQ27

AO4466_SO8

PC84

1 2

0.1U_0603_25V7K

+5VALW

1 2

PC89

4.7U_0805_10V6K

AO4466_SO8

PQ28

AO4712_SO8

3 6

578

3 6

PR97

255K_0402_1%

1 2

1

PU7

2

TON

EN_PSV

3

VOUT

4

V5FILT

5

VFB

6

PGOOD

GND7PGND

8

PR99

2.2_0603_1%

1 2

14TP15

VBST

DRVH

LL

TRIP

V5DRV

DRVL

TPS51117RGYR_QFN14_3.5x3.5

13 12 11 10 9

BST_1.8VP DH_1.8VP LX_1.8VP

1 2

PR102

15.4K_0402_1%

DL_1.8VP

2

241

1.8UH_SIL104R-1R8PF_9.5A_30%

241

51117_B+

12

PC81

1 2

12

PR100

4.7_1206_5%

12

PC87

680P_0603_50V7K

HCB2012KF-121T50_0805

1 2

12

PC82

4.7U_1206_25V6K

PL8

PL15

PC85

1

B+

12

PC140

0.1U_0402_25V6@

+1.8VP

1

12

+

2

220U_D2_4VM

Ipeak = 8A

PC146

Imax = 5.6A F = 312kHz

.1U_0402_16V7K@

Total Capacitor = 220 uF ESR = 15m Ohm

B B

PU8

APL5508-25DC-TRL_SOT89-3

PJ18

+3VS

A A

5

4

112

JUMP_43X39@

2

PC90

1U_0603_10V6K

APL5508-25DC-TRL_SOT89-3

2

IN

12

3

OUT

GND

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

PC91

4.7U_0805_6.3V6K

3

+2.5VSP

Compal Secret Data

2008/04/14 2009/04/14

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

1.8VP/2.5VS

LA-5831P

40 44Wednesday, August 12, 2009

1

1.0

5

4

3

2

1

PC96

+3VS

1

PJ19

1

JUMP_43X79@

2

PC92

1 2

1.15K_0402_1%

13

D

2

G

12

S

+1.8V

1

2

12

PC97

13

D

2

G

12

PQ30

S

SSM3K7002FU_SC70-3

12

PR105

12

PR106

1K_0402_1%

.1U_0402_16V7K

PR108

PR109

.1U_0402_16V7K

12

.1U_0402_16V7K

PQ29

SSM3K7002FU_SC70-3

PJ20

PJ20 JUMP_43X79@

JUMP_43X79@

1K_0402_1%

PC94

PC99

12

PU9

2 3 4

APL5331KAC-TRL_SO8

+1.5VSP

12

PC95

PC95 10U_0805_6.3V6M

10U_0805_6.3V6M

PU10

2 3 4

APL5331KAC-TRL_SO8

12

PC100

PC100 10U_0805_6.3V6M

10U_0805_6.3V6M

VIN1VCNTL GND VREF VOUT

+0.9VP

6 5

NC

7

NC

8

NC

9

TP

6 5

NC

7

NC

8

NC

9

TP

+5VALW

12

PC93

PC93 1U_0603_6.3V6M

1U_0603_6.3V6M

12

PC98

PC98 1U_0603_6.3V6M

1U_0603_6.3V6M

+3VALW

D D

4.7U_0805_6.3V6K

SUSP

.1U_0402_16V7K@

0_0402_5%

1 2

.1U_0402_16V7K@

1 2

PR107

0_0402_5%

4.7U_0805_6.3V6K

PR110

PC101

SUSP<34>

C C

B B

SYSON#<34>

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2008/04/14 2009/04/14

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

0.9VP/1.5VSP

LA-5831P

41 44Wednesday, August 12, 2009

1

1.0

A

B

C

D

E

PQ31

PQ31 AO4466_SO8

AO4466_SO8

PQ32

AO4712_SO8

4

CPU_B+

1

12

+

PC106

PC103

220U_25V_M

2

10U_1206_25V6M

4.7U_LF919AS-4R7M-P3_5.2A_20%

1 2

12

PR114

4.7_1206_5%

12

PC111

PC111 680P_0603_50V7K

680P_0603_50V7K

PQ33

SI7686DP-T1-E3_SO8

3 5

241

4

123 5

PQ36

SI7686DP-T1-E3_SO8

3 5

241

4

123 5

D

1

12

+

PC136

PC104

220U_25V_M@

2

0.1U_0402_25V6

PL10

12

PC113

10U_1206_25V6M

PQ35

123 5

TPCA8028-H_SOP-ADVANCE8-5@

12

PC119

10U_1206_25V6M

PQ38

123 5

TPCA8028-H_SOP-ADVANCE8-5@

PC102

33P_0402_50V8J

12

PR111

44.2K_0402_1%

PR112

1 1

CPU_B+

+5VS +3VS

12

PR120

PR120 0_0402_5%

0_0402_5%

12

PR124

PR134

4.02K_0402_1%

+CPU_CORE_0

CPU_VDD0_RUN_FB_H<7> CPU_VDD0_RUN_FB_L<7> CPU_VDD1_RUN_FB_L<7>

VW0

12

PC125

180P_0402_50V8J

PC130

12

1200P_0402_50V7K

PR124 10K_0402_1%@

10K_0402_1%@

12

COMP0

CPU_VDD1_RUN_FB_H<7>

12

ISL6265_PWROK

PR131

0_0402_5%

PR137

10_0402_5%@

+CPU_CORE_1

12

PC126

1000P_0402_50V7K

PR151

6.81K_0402_1%

PR123

105K_0402_1%

2 2

VGATE<32>

113K_0402_1%

12

A

1 2 1 2

PR133

FB_0

54.9K_0402_1%

12

PR155

PR129 100K_0402_5%@ PR129 100K_0402_5%@ PR158 100K_0402_5%PR158 100K_0402_5%

12

PR150

36.5K_0402_1%@

H_PWRGD<7,20> SB_PWRGD<21,32>

3 3

255_0402_1%

4 4

CPU_VCORE_ENABLE<32>

PR147

1K_0402_5%

CPU_SVD<7> CPU_SVC<7>

DIFF_0

PC124

4700P_0402_25V7K

12

PR149

+5VS

PR121

PR121 105K_0402_1%@

105K_0402_1%@

PR126

PR126 105K_0402_1%@

105K_0402_1%@

12

PR132

0_0402_5%

12

PR112

2_0603_5%

1 2

0.1U_0603_16V7K

1 2

PR117

2_0603_5%

PC112

0.1U_0603_25V7K

1 2 3 4 5

12

6 7 8

9 10 11 12

PR135

0_0402_5%

12

PR142

10_0402_5%@

1 2

PR146

10_0402_5%@

PC108

PU11

OFS/VFIXEN PGOOD PWROK SVD SVC ENABLE RBIAS OCSET VDIFF0 FB0 COMP0 VW0

ISP0 ISN0

VSEN0

0_0402_5%

PR143

1 2

12

255_0402_1%

B

12

PR138

PR140

PR148

44.2K_0402_1%

12

46

47

48

VIN

VCC

FB_NB

ISL6265HRTZ-T_QFN48_6X6

ISN0

ISP0

15

14

13

RTN0

12

RTN1

12

PR145

0_0402_5%

DIFF_1

PC127

4700P_0402_25V7K

12

PR152

1K_0402_5%

12

1000P_0402_50V7K

44

45

FSET_NB

COMP_NB

RTN117VSEN0

RTN0

16

VSEN1

12

22K_0402_1%

43

VSEN_NB

VSEN1

18

54.9K_0402_1%

12

PC105

1000P_0402_50V7K

PC107

12

PR115

12

PR118

0_0402_5%

41

42

RTN_NB

OCSET_NB

VDIFF1

FB1

19

20

PC128

180P_0402_50V8J

PR153

PR156

36.5K_0402_1%@

12

UGATE_NB

PHASE_NB

PR113

2.2_0603_1%

BOOT_NB

PR116

10_0402_5%@

+VDDNBP

1 2

12

PR119

11.3K_0402_1%

38

39

40

PGND_NB

LGATE_NB

PHASE_NB

VW1

COMP121ISP1

22

23

ISP1

COMP1FB_1

12

PC131

12

1200P_0402_50V7K

PHASE_NB

12

LGATE_NB PHASE_NB UGATE_NB

12

PR122

0_0402_5%

37

36

BOOT_NB

UGATE_NB

35

BOOT0

34

UGATE0

33

PHASE0

32

PGND0

31

LGATE0

30

PVCC

29

LGATE1

28

PGND1

27

PHASE1

26

UGATE1

25

BOOT1

ISN1

TP

24

49

ISN1

VW1

12

PC129

1000P_0402_50V7K

PR154

6.81K_0402_1%

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1 2

0.22U_0603_10V7K

LGATE_NB

CPU_VDDNB_RUN_FB_H <7>

PR125

PR125 10_0402_5%@

10_0402_5%@

1 2

BOOT_NB BOOT0 UGATE0 PHASE0

LGATE0

LGATE1

PHASE1 UGATE1 BOOT1

12

C

0.22U_0603_10V7K

UGATE0

PHASE0

BOOT0

+5VS

12

PC118

PC118 1U_0603_16V6K

1U_0603_16V6K

UGATE1

PHASE1

BOOT1

TPCA8028-H_SOP-ADVANCE8-5

2008/04/14 2009/04/14

578

3 6

241

578

1 2

PC109

3 6

241

CPU_VDDNB_RUN_FB_L <7>

PR127

2.2_0603_1%

1 2

PC115

0.22U_0603_10V7K

PQ34

TPCA8028-H_SOP-ADVANCE8-5

PQ34

LGATE0

PR139

2.2_0603_1%

1 2

PC121

0.22U_0603_10V7K

PQ37

LGATE1

Compal Secret Data

Deciphered Date

PL13

HCB2012KF-121T50_0805

1 2

12

PC135

0.1U_0402_25V6@

1

AP

+

PC110

PC110 220U_D2_4VM

220U_D2_4VM

2

CPU_B+

12

PC114

10U_1206_25V6M

12

PR130

4.7_1206_5%

12

PC116

PC116 680P_0603_50V7K

680P_0603_50V7K

CPU_B+

12

PC120

10U_1206_25V6M

12

PR144

4.7_1206_5%

12

PC122

PC122 680P_0603_50V7K

680P_0603_50V7K

Size Document Number Rev

Custom

Date: Sheet of

12

PC132

PC133

0.1U_0402_25V6

+VDDNBP

0.36UH_PCMC104T-R36MN1R17_30A_20%

PR128

3.65K_0402_1%

1 2

ISP0

0.36UH_PCMC104T-R36MN1R17_30A_20%

ISP1

Compal Electronics, Inc.

Title

Compal Electronics, Inc.

12

0.1U_0402_25V6

PL11

1 2

PC117

0.1U_0603_16V7K

PR136

47K_0402_1%

PL12

1 2

PR141

3.65K_0402_1%

1 2

PC123

0.1U_0603_16V7K

PR157

47K_0402_1%

+CPU_CORE

HCB4532KF-800T90_1812

1 2

12

PC134

0.1U_0402_25V6@

PJ21

2

112

JUMP_43X118@

JUMP_43X118@ PJ22

PJ22

2

112

JUMP_43X118@

JUMP_43X118@ PJ23

PJ23

2

112

JUMP_43X118@

4 3

12

ISN0

4 3

12

ISN1

LA-5831P

E

PL9

B+

+CPU_CORE_1+CPU_CORE_0

+CPU_CORE_0

+CPU_CORE_1

1.0

42 44Wednesday, August 12, 2009

1.0

A

Version Change List ( P. I. R. List ) for Circuit

Version Change List ( P. I. R. List ) for CircuitVersion Change List ( P. I. R. List ) for Circuit

Page#

Item

Page#Page#

ItemItem

1 1

Title

TitleTitle

Date

DateDate

Change PC56 change to common circuit.

Pre-MP Change PH1,PH2

2 2

B

Request

RequestRequest Owner

Owner

OwnerOwner

Release2009/07/20PVT35-43 POWER2009/07/30Pre-MP39-40 POWER2009/07/30Pre-MP38 POWER2009/08/436 POWER2009/08/437 Pre-MP Change PR38,PR45

Issue Description

Issue DescriptionIssue Description

C

Solution Description

Solution DescriptionSolution Description

Change PL6,PL7,PL8 footprintChange PL6,PL7,PL8

change to common circuit. change to common circuit.

D

E

Rev.

Rev.Rev.

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2009-02-12 2009-02-12

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

List History

LA-5831P

43 44Wednesday, August 12, 2009

E

1.0

5

4

3

2

1

HW4 Product Improvement Record (P.I.R.)

NBWAE LA-5831P SCHEMATIC CHANGE LIST REVISION CHANGE: 0.1 TO 1.0

D D

C C

GERBER-OUT DATE: 2009/08/07 NO DATE PAGE MODIFICATION LIST PURPOSE

-------------------------------------------------------------------------------------------------------------1 7/21 25 Change JUSBB footprint back to E-T_6905-E12N-00R_12P USB/B pin define reverse 2 7/27 25 Add D11 For ESD 3 7/27 9 Add C120~C123 For EMI 4 7/27 32 Add R344 and R345 For EC pin damage issue 5 7/30 26 Add R97, R98 and R105 Reserve bead for EMI 6 8/6 18 Add C707, C708 and C709 For EMI 7 8/6 30 Add LA11 and LA12 For EMI 8 8/6 32 Add R74 and C607 For EMI 9 8/6 31 Delete R518 and C606 For EMI 10 8/6 7 Add C124 For EMI

--------------------------------------------------------------------------------------------------------------

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

2009-02-122009-02-12

2

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PIR

44 44Wednesday, August 12, 2009

1

1.0

Quanta Computer LA-5831P, Satellite L450D Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual