Quanta Computer LA-9869P VDKTE Rosetta 10ADT, Satellite L40D, LA-9869P VDKTE Rosetta 10ADTG Schematic

A

1 1

B

C

D

E

VDKTE

2 2

Rosetta 10ADT/10ADTG

LA-9869P SchematicREV 1.0

AMD APU RICHLAND FP2 / FCH BOLTON-M3

3 3

2013-03-20 Rev 1.0

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/03/12 2014/03/12

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Page

LA-9869P

1 51Wednesday, March 20, 2013

E

1.0

A

B

C

D

E

eDP Conn.

page 20

LVDS Conn.

1 1

page 20

LVDS Translator RTD2132R

page 19

DP0 (X2)

AMD APU

PWM Fan Control

page 5

GCLK SLG3NB283VTR (UMA)

page 29

GCLK SLG3NB302VTR (DIS)

page 29

FP2 Processor

GPU Sun Pro M2

page 12~18

HDMI Conn

2 2

RJ45

page 30

3 3

CRT

RTL8106E 10/100M

Cardreader Conn.

GL834L 2 in 1 MMC/SD

PCI-Express X8 5GHz

page 27

page 21

APU PCIe port 0

page 30

USB port 2

page 34

DP2 (X4)

USB2.0

5V 480MHz

SPI Bus

3.3V 33 MHz

PCIe X1

1.2V 5GT/s

BGA-827

27mm*31mm

page 5,6,7,8,9

DP1 (X4)

AMD FCH Hudson M3

FCBGA-656

24.5mm*24.5mm

page 23,24,25,26,27

LPC Bus

3.3V 33 MHz

UMI X4

2.5GT/s

HD Audio

Memory BUS(DDRIII)

Dual Channel

1.5V DDRIII 1333/1600 MT/s

PCIe X1

1.2V 5GT/s

Left USB2.0

Right USB 3.0

USB2.0

5V 480MHz

SB2.0

U

5V 480MHz

SATA port 0

5V 6GHz(600MB/s)

SATA port 1

5V 6GHz(600MB/s)

USB 3.0

5GHz

USB 3.0

5GHz

3.3V 24MHz

PCIeMini Card WLAN + BT

APU PCIe port 1

SATA HDD

SATA ODD

200pin DDRIII-SO-DIMM X2

BANK 0, 1, 2, 3

Int. Camera

USB port 0

page 30

USB port 1

page 25

Right USB 3.0

USB port 10

page 31

USB port 3

page 28

SATA port 0

page 28

SATA port 1

page 28

USB port 11

page 31

USB 3.0

page 10,11

Touch screen

USB3.0 port 0

page 31

USB3.0 port 1

page 31

USB port 4

page 25

HDA Codec

RTC CKT.

page 19

SPI ROM

(4MB)

page 25

ENE KB9012

page 35

ALC259/269

page 32

DC/DC Interface CKT.

page 38

4 4

Power Circuit DC/DC

page 39~50

Power On/Off CKT.

A

LAN/USB board LS-9861P

page 30

PWR/B LS-9862P

page 37page 36

B

Touch Pad

page 37

Int.KBD

page 36

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2013/03/20 2014/03/20

Compal Secret Data

Deciphered Date

MIC Conn

page 33

D

SPK ConnInt.

page 33

Title

Block Diagrams

Size Document Number Rev

Custom

Date: Sheet of

JCRIO (HP & MIC)

page 33

Compal Electronics, Inc.

LA-9869P

E

1.0

2 51Wednesday, March 20, 2013

1.0

5

4

3

2

1

DESIGN CURRENT 0.15A

B+

D D

Ipeak=12A, Imax=8.4A, Iocp min=14A

SUSP

N-CHANNEL

SI4800

DESIGN CURRENT 0A

DESIGN CURRENT 4A

+3VL +5VL

+5VALW

+5VS

RT8243A

Ipeak=8A, Imax=5.6A, Iocp min=10A

WOL_EN#

P-CHANNEL

SUSP

N-CHANNEL

SI4800

C C

AO-3413

LCD_ENVDD

P-CHANNEL

AO-3413

DGPU_PWR_EN

P-CHANNEL

AO-3413

VGA_PWRGD

SY8032

SYSON

RT8207M

Ipeak=12A, Imax=8.4A, Iocp min=13.8A

SUSP

N-CHANNEL FDS6676AS

APL5508

DESIGN CURRENT 330mA

DESIGN CURRENT 4A

DESIGN CURRENT 1.5A

DESIGN CURRENT 60mA

DESIGN CURRENT 0.5A

DESIGN CURRENT 0.75A

DESIGN CURRENT 2A

+3VALW

+3V_LAN

+3VS

+LCD_VDD

+3VS_DGPU

1.8VGSP

2.5VSP

+1.5V

+1.5V_CPU

B B

PJ1

1.1VPWR_EN

SY8208D

Ipeak=5.3A, Imax=3.71A, Iocp min=16A

SUSP#

DESIGN CURRENT 2A

DESIGN CURRENT 1.5A

FDS6676

VR_ON

SY8208D

VR_ON

ISL6277

A A

GPU_DPRSLPVR

ISL62881

5

Ipeak=7A, Imax=4.9A, Iocp min=16A

Ipeak=36A, Imax=25.2A, Iocp min=60A Ipeak=30A, Imax=21A, Iocp min=50A

Ipeak=21A, Imax=14.7A, Iocp min=40A

4

+1.5VS

+0.75VS

+1.1VALWP

+1.1VS

+1.2VS

APU_CORE APU_CORE_NB

VGA_CORE

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELE CTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS S HEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D

AND TRADE SECRET INFORMATION. THIS S HEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D

AND TRADE SECRET INFORMATION. THIS S HEET MAY NOT BE TRANSFERE D FROM THE CUSTODY OF THE COMPETENT DIV ISION OF R&D DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/03/20 2014/03/20

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

Power Tree

LA-9869P

1

3 51Wednesday, March 20, 2013

1.0

A

B

C

D

E

Voltage Rails

1 1

2 2

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

State

S0

S1

S3

S5 S4/AC

power plane

( O MEANS ON X MEANS OFF )

+RTCVCC

O O O O O O

B+

O O O O O

X

VL +3VL

O O O O O

X

+5VALW +3VALW

O O O O

X X

+1.5V

+5VS +3VS +2.5VS +1.5VS +1.2VS +1.1VS +0.75VS +APU_CORE +APU_CORE_NB +1.1VALW

O

X X X X X

BTO Option Table

Bolton

R1

BOLTONR1@

Clock

FCH

HUDM3R3@

No Green Clock

GPU

R1 R3

UMA/DIS

DIS

VGA@

UMA

UMA@

U1GK

Function

APU

description

explain

R1 R3

R3

BTO

Function

3D sensor

KB LED

description

explain

BTO

OO OO

X

Function

description

explain

BTO

G-sensor

GSENSOR@

LVDS eDP

LVDS@

KB LED

KBL@

Panel

S D

IEDP@

Green Clock

GCLK@ NOGCLK@

X

FCH SM Bus Address (SCL0/SDA0)

Power

3VS

3 3

+ +3VS +3VS

Device

DDR SO-DIMM 0 DDR SO-DIMM 1 WLAN

EC SM Bus1 Address

Power

+3VL +3VL

Device Address

Charger 12 H 0001 0010 b

EC SM Bus2 Address

DevicePower

4 4

+3VL +3VS +3VS VGA Thermal

SB-TSI

A

HEX

Address

1010 000X bA0 H 1010 001X bA2 H

HEX

16 H

0001 0110 bSmart Battery

HEX Address

98 H

1001 1001 b

40 H

0100 0000 bG-Sensor

82H

1000 0010 b

EC SM Bus3 Address

+3VS

B

HEX AddressDevicePower

94 H

1001 0100 bLVDS Translator

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2013/03/20 2014/03/20

Compal Secret Data

STATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

G3 LOW LOW

Deciphered Date

SIGNAL

D

SLP_S3# SLP_S5#

HIGHHIGH

HIGH HIGH

LOW

HIGH

LOW

LOWLOW

Title

Size Document Number Rev

Custom

Date: Sheet of

Compal Electronics, Inc.

Notes List

LA-9869P

E

1.0

4 51Wednesday, March 20, 2013

1.0

A

PCIE_GTX_C_ARX_P[0..3] PCIE_ATX_C_GRX_P[0..3] PCIE_GTX_C_ARX_N[0..3]

PCIE_GTX_C_ARX_P0 PCIE_GTX_C_ARX_N0 PCIE_GTX_C_ARX_P1 PCIE_GTX_C_ARX_N1

1 1

2 2

LAN WLAN

PCIE_FRX_C_LANTX_P0 PCIE_FRX_C_LANTX_N0 PCIE_FRX_WLANTX_P1 PCIE_FRX_WLANTX_N1

UMI_MTX_C_FRX_P0 UMI_MTX_C_FRX_N0 UMI_MTX_C_FRX_P1 UMI_MTX_C_FRX_N1 UMI_MTX_C_FRX_P2 UMI_MTX_C_FRX_N2 UMI_MTX_C_FRX_P3 UMI_MTX_C_FRX_N3

+1.2VS

PCIE_GTX_C_ARX_P2 PCIE_GTX_C_ARX_N2 PCIE_GTX_C_ARX_P3 PCIE_GTX_C_ARX_N3

1 2

R1 196_0402_1%R1 196_0402_1%

Close to AR11 Close to AP11

P_ZVDDP P_ZVSS

B

UAPUA

AP1

P_GFX_RXP[0]

AP2

P_GFX_RXN[0]

AM1

P_GFX_RXP[1]

AM2

P_GFX_RXN[1]

AK3

P_GFX_RXP[2]

AK4

P_GFX_RXN[2]

AJ1

P_GFX_RXP[3]

AJ2

P_GFX_RXN[3]

AH4

P_GFX_RXP[4]

AH3

P_GFX_RXN[4]

AF2

P_GFX_RXP[5]

AF1

P_GFX_RXN[5]

AD1

P_GFX_RXP[6]

AD2

P_GFX_RXN[6]

AB3

P_GFX_RXP[7]

AB4

P_GFX_RXN[7]

AA1

P_GFX_RXP[8]

AA2

P_GFX_RXN[8]

Y4

P_GFX_RXP[9]

Y3

P_GFX_RXN[9]

V2

P_GFX_RXP[10]

V1

P_GFX_RXN[10]

T1

P_GFX_RXP[11]

T2

P_GFX_RXN[11]

P3

P_GFX_RXP[12]

P4

P_GFX_RXN[12]

N1

P_GFX_RXP[13]

N2

P_GFX_RXN[13]

M4

P_GFX_RXP[14]

M3

P_GFX_RXN[14]

K2

P_GFX_RXP[15]

K1

P_GFX_RXN[15]

AH5

P_GPP_RXP[0]

AH6

P_GPP_RXN[0]

AG5

P_GPP_RXP[1]

AG6

P_GPP_RXN[1]

AE6

P_GPP_RXP[2]

AE5

P_GPP_RXN[2]

AD6

P_GPP_RXP[3]

AD5

P_GPP_RXN[3]

AM10

P_UMI_RXP[0]

AN10

P_UMI_RXN[0]

AN8

P_UMI_RXP[1]

AM8

P_UMI_RXN[1]

AP8

P_UMI_RXP[2]

AR8

P_UMI_RXN[2]

AR7

P_UMI_RXP[3]

AP7

P_UMI_RXN[3]

AR11

P_ZVDDP

TRINITY-A8-SERIES_BGA813

5745R1@

P_GFX_TXP[0] P_GFX_TXN[0] P_GFX_TXP[1] P_GFX_TXN[1] P_GFX_TXP[2] P_GFX_TXN[2] P_GFX_TXP[3] P_GFX_TXN[3] P_GFX_TXP[4] P_GFX_TXN[4] P_GFX_TXP[5] P_GFX_TXN[5] P_GFX_TXP[6] P_GFX_TXN[6] P_GFX_TXP[7] P_GFX_TXN[7] P_GFX_TXP[8]

GRAPHICSGPPUMI

P_GFX_TXN[8] P_GFX_TXP[9]

P_GFX_TXN[9] P_GFX_TXP[10] P_GFX_TXN[10] P_GFX_TXP[11] P_GFX_TXN[11] P_GFX_TXP[12] P_GFX_TXN[12] P_GFX_TXP[13] P_GFX_TXN[13] P_GFX_TXP[14] P_GFX_TXN[14] P_GFX_TXP[15] P_GFX_TXN[15]

P_GPP_TXP[0]

P_GPP_TXN[0]

P_GPP_TXP[1]

P_GPP_TXN[1]

P_GPP_TXP[2]

P_GPP_TXN[2]

P_GPP_TXP[3]

P_GPP_TXN[3]

P_UMI_TXP[0] P_UMI_TXN[0] P_UMI_TXP[1] P_UMI_TXN[1] P_UMI_TXP[2] P_UMI_TXN[2] P_UMI_TXP[3] P_UMI_TXN[3]

P_ZVSS

AN1 AN2 AM4 AM3 AK2 AK1 AH1 AH2 AF3 AF4 AE1 AE2 AD4 AD3 AB2 AB1 Y1 Y2 V3 V4 U1 U2 T4 T3 P2 P1 M1 M2 K3 K4 J1 J2

AG7 AG8 AE7 AE8 AD7 AD8 AB6 AB5

AN6 AM6 AP6 AR6 AP4 AR4 AP3 AR3

AP11

PCIE_ATX_GRX_P0 PCIE_ATX_GRX_N0 PCIE_ATX_GRX_P1 PCIE_ATX_GRX_N1 PCIE_ATX_GRX_P2 PCIE_ATX_GRX_N2 PCIE_ATX_GRX_P3 PCIE_ATX_GRX_N3

PCIE_FTX_LANRX_P0 PCIE_FTX_LANRX_N0 PCIE_FTX_WLANRX_P1 PCIE_FTX_WLANRX_N1

UMI_FTX_MRX_P0 UMI_FTX_MRX_N0 UMI_FTX_MRX_P1 UMI_FTX_MRX_N1 UMI_FTX_MRX_P2 UMI_FTX_MRX_N2 UMI_FTX_MRX_P3 UMI_FTX_MRX_N3

1 2

R2 196_0402_1%R2 196_0402_1%

C

PCIE_ATX_C_GRX_N[0..3]

1 2

C1 0.1U_0402_16V7KVGA@C1 0.1U_0402_16V7KVGA@

1 2

C15 0.1U_0402_16V7KVGA@C15 0.1U_0402_16V7KVGA@

1 2

C17 0.1U_0402_16V7KVGA@C17 0.1U_0402_16V7KVGA@

1 2

C11 0.1U_0402_16V7KVGA@C11 0.1U_0402_16V7KVGA@

1 2

C7 0.1U_0402_16V7KVGA@C7 0.1U_0402_16V7KVGA@

1 2

C14 0.1U_0402_16V7KVGA@C14 0.1U_0402_16V7KVGA@

1 2

C13 0.1U_0402_16V7KVGA@C13 0.1U_0402_16V7KVGA@

1 2

C8 0.1U_0402_16V7KVGA@C8 0.1U_0402_16V7KVGA@

1 2

C50 0.1U_0402_16V7KC50 0.1U_0402_16V7K

1 2

C55 0.1U_0402_16V7KC55 0.1U_0402_16V7K

1 2

C51 0.1U_0402_16V7KC51 0.1U_0402_16V7K

1 2

C54 0.1U_0402_16V7KC54 0.1U_0402_16V7K

1 2

C59 0.1U_0402_16V7KC59 0.1U_0402_16V7K

1 2

C60 0.1U_0402_16V7KC60 0.1U_0402_16V7K

1 2

C61 0.1U_0402_16V7KC61 0.1U_0402_16V7K

1 2

C62 0.1U_0402_16V7KC62 0.1U_0402_16V7K

1 2

C122 0.1U_0402_16V7KC122 0.1U_0402_16V7K

1 2

C123 0.1U_0402_16V7KC123 0.1U_0402_16V7K

1 2

C120 0.1U_0402_16V7KC120 0.1U_0402_16V7K

1 2

C121 0.1U_0402_16V7KC121 0.1U_0402_16V7K

D

PCIE_ATX_C_GRX_P0 PCIE_ATX_C_GRX_N0 PCIE_ATX_C_GRX_P1 PCIE_ATX_C_GRX_N1 PCIE_ATX_C_GRX_P2 PCIE_ATX_C_GRX_N2 PCIE_ATX_C_GRX_P3 PCIE_ATX_C_GRX_N3

PCIE_FTX_C_LANRX_P0 PCIE_FTX_C_LANRX_N0 PCIE_FTX_C_WLANRX_P1 PCIE_FTX_C_WLANRX_N1

UMI_FTX_C_MRX_P0 UMI_FTX_C_MRX_N0 UMI_FTX_C_MRX_P1 UMI_FTX_C_MRX_N1 UMI_FTX_C_MRX_P2 UMI_FTX_C_MRX_N2 UMI_FTX_C_MRX_P3 UMI_FTX_C_MRX_N3

E

LAN WLAN

3 3

+FAN1

D

+3VS

12

R6

R6 10K_0402_5%

10K_0402_5%

1

C4

0.01U_0402_25V7K

@

2

JFAN

6

G6

5

G5

4

C5

3

2

1

ACES_50273-0040N-001

@

1

@

C6

2

1000P_0402_50V7K

E

5 51Wednesday, March 20, 2013

FANPWM

+FAN1

12

D1

BAS16_SOT23-3

Title

AMD Trinity FP2 / GFX / UMI

Size Document Number Rev

Custom

LA-9869P

Date: Sheet of

1

2

10U_0603_6.3V6M

Compal Electronics, Inc.

1.0

FAN Control Circuit

FAN_SPEED1

+5VS

1A

1 2

@

R3 0_0603_5%

4 4

Security Classification

2013/03/20 2014/03/20

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/03/20 2014/03/20

C

Compal Secret Data

Deciphered Date

A

B

C

D

E

DDR_A_DQS[0..7]

DDR_A_DQS#[0..7]

1 1

UAPUB

DDR_A_MA[0..15]

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 DDR_A_DM[0..7]

2 2

DDR_A_CLK0 DDR_A_CLK0# DDR_A_CLK1 DDR_A_CLK1#

DDR_A_CKE0

3 3

DDR_A_CKE1 DDR_A_ODT0

DDR_A_ODT1

DDR_A_SCS0# DDR_A_SCS1#

DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

MEM_MA_RST# MEM_MA_EVENT#

+1.5V

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS7 DDR_A_DQS#7

+MEM_VREF

1 2

R60 39.2_0402_1%R60 39.2_0402_1%

M_ZVDDIO

Close to AJ32

UAPUB

AA28

MA_ADD[0]

R29

MA_ADD[1]

T30

MA_ADD[2]

R28

MA_ADD[3]

R26

MA_ADD[4]

P26

MA_ADD[5]

P27

MA_ADD[6]

P30

MA_ADD[7]

P29

MA_ADD[8]

M28

MA_ADD[9]

AB26

MA_ADD[10]

M26

MA_ADD[11]

M29

MA_ADD[12]

AE27

MA_ADD[13]

L26

MA_ADD[14]

L27

MA_ADD[15]

AB27

MA_BANK[0]

AA29

MA_BANK[1]

M30

MA_BANK[2]

D16

MA_DM[0]

D20

MA_DM[1]

E25

MA_DM[2]

F30

MA_DM[3]

AK29

MA_DM[4]

AL25

MA_DM[5]

AM20

MA_DM[6]

AM16

MA_DM[7]

G17

MA_DQS_H[0]

H17

MA_DQS_L[0]

F22

MA_DQS_H[1]

G22

MA_DQS_L[1]

E26

MA_DQS_H[2]

F26

MA_DQS_L[2]

H30

MA_DQS_H[3]

G30

MA_DQS_L[3]

AL29

MA_DQS_H[4]

AL30

MA_DQS_L[4]

AH25

MA_DQS_H[5]

AJ25

MA_DQS_L[5]

AK20

MA_DQS_H[6]

AL20

MA_DQS_L[6]

AK15

MA_DQS_H[7]

AL15

MA_DQS_L[7]

W29

MA_CLK_H[0]

Y30

MA_CLK_L[0]

W26

MA_CLK_H[1]

W27

MA_CLK_L[1]

U29

MA_CLK_H[2]

V30

MA_CLK_L[2]

U26

MA_CLK_H[3]

U27

MA_CLK_L[3]

L29

MA_CKE[0]

K30

MA_CKE[1]

AD30

MA0_ODT[0]

AG28

MA0_ODT[1]

AE26

MA1_ODT[0]

AG29

MA1_ODT[1]

AD26

MA0_CS_L[0]

AE29

MA0_CS_L[1]

AB30

MA1_CS_L[0]

AF30

MA1_CS_L[1]

AB29

MA_RAS_L

AD29

MA_CAS_L

AD28

MA_WE_L

J28

MA_RESET_L

AA26

MA_EVENT_L

G32

M_VREF

AJ32

M_ZVDDIO

TRINITY-A8-SERIES_BGA813

5745R1@

MA_DATA[0] MA_DATA[1] MA_DATA[2] MA_DATA[3] MA_DATA[4] MA_DATA[5] MA_DATA[6] MA_DATA[7]

MA_DATA[8]

MA_DATA[9] MA_DATA[10] MA_DATA[11] MA_DATA[12] MA_DATA[13] MA_DATA[14] MA_DATA[15]

MA_DATA[16] MA_DATA[17] MA_DATA[18] MA_DATA[19] MA_DATA[20] MA_DATA[21] MA_DATA[22] MA_DATA[23]

MA_DATA[24] MA_DATA[25] MA_DATA[26] MA_DATA[27] MA_DATA[28] MA_DATA[29] MA_DATA[30] MA_DATA[31]

MA_DATA[32] MA_DATA[33] MA_DATA[34] MA_DATA[35] MA_DATA[36] MA_DATA[37] MA_DATA[38] MA_DATA[39]

MA_DATA[40] MA_DATA[41] MA_DATA[42] MA_DATA[43] MA_DATA[44] MA_DATA[45] MA_DATA[46] MA_DATA[47]

MA_DATA[48] MA_DATA[49] MA_DATA[50] MA_DATA[51] MA_DATA[52] MA_DATA[53] MA_DATA[54] MA_DATA[55]

MA_DATA[56] MA_DATA[57] MA_DATA[58] MA_DATA[59] MA_DATA[60] MA_DATA[61] MA_DATA[62] MA_DATA[63]

+1.5V

F15 E15 H19 F19 E14 H15 E17 D18

G20 E20 H23 G23 E19 H20 E22 D22

H25 F25 D28 D29 E23 D24 D26 D27

G28 G29 H27 J29 E28 F27 H29 H28

AH29 AJ30 AM28 AM27 AH27 AH28 AJ29 AK27

AK26 AJ26 AK23 AJ23 AM26 AL26 AM24 AL23

AK22 AH22 AK19 AH19 AM22 AL22 AJ20 AL19

AK17 AJ17 AK14 AH14 AM18 AL17 AH15 AL14

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7

DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15

DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23

DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31

DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39

DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47

DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55

DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

DDR_A_D[0..63]

DDR_B_DQS[0..7]

DDR_B_DQS#[0..7]

DDR_B_MA[0..15]

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 DDR_B_DM[0..7]

DDR_B_CLK0 DDR_B_CLK0# DDR_B_CLK1 DDR_B_CLK1#

DDR_B_CKE0 DDR_B_CKE1

DDR_B_ODT0 DDR_B_ODT1

DDR_B_SCS0# DDR_B_SCS1#

DDR_B_RAS# DDR_B_CAS# DDR_B_WE#

MEM_MB_RST# MEM_MB_EVENT#

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2

DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7

DDR_B_DQS0 DDR_B_DQS#0 DDR_B_DQS1 DDR_B_DQS#1 DDR_B_DQS2 DDR_B_DQS#2 DDR_B_DQS3 DDR_B_DQS#3 DDR_B_DQS4 DDR_B_DQS#4 DDR_B_DQS5 DDR_B_DQS#5 DDR_B_DQS6 DDR_B_DQS#6 DDR_B_DQS7 DDR_B_DQS#7

UAPUC

Y33

MB_ADD[0]

R32

MB_ADD[1]

T31

MB_ADD[2]

P33

MB_ADD[3]

P32

MB_ADD[4]

P31

MB_ADD[5]

N32

MB_ADD[6]

M33

MB_ADD[7]

M32

MB_ADD[8]

L32

MB_ADD[9]

AB31

MB_ADD[10]

M31

MB_ADD[11]

K32

MB_ADD[12]

AF33

MB_ADD[13]

K33

MB_ADD[14]

J32

MB_ADD[15]

AB33

MB_BANK[0]

AA32

MB_BANK[1]

K31

MB_BANK[2]

C18

MB_DM[0]

B23

MB_DM[1]

C28

MB_DM[2]

D31

MB_DM[3]

AM31

MB_DM[4]

AN30

MB_DM[5]

AR24

MB_DM[6]

AN18

MB_DM[7]

B18

MB_DQS_H[0]

A18

MB_DQS_L[0]

B24

MB_DQS_H[1]

A24

MB_DQS_L[1]

B30

MB_DQS_H[2]

B29

MB_DQS_L[2]

D32

MB_DQS_H[3]

D33

MB_DQS_L[3]

AM32

MB_DQS_H[4]

AM33

MB_DQS_L[4]

AN28

MB_DQS_H[5]

AP29

MB_DQS_L[5]

AP23

MB_DQS_H[6]

AP24

MB_DQS_L[6]

AR18

MB_DQS_H[7]

AP18

MB_DQS_L[7]

W32

MB_CLK_H[0]

Y32

MB_CLK_L[0]

V33

MB_CLK_H[1]

V32

MB_CLK_L[1]

U32

MB_CLK_H[2]

V31

MB_CLK_L[2]

T33

MB_CLK_H[3]

T32

MB_CLK_L[3]

H32

MB_CKE[0]

H33

MB_CKE[1]

AF31

MB0_ODT[0]

AH31

MB0_ODT[1]

AE32

MB1_ODT[0]

AH33

MB1_ODT[1]

AD31

MB0_CS_L[0]

AF32

MB0_CS_L[1]

AC32

MB1_CS_L[0]

AG32

MB1_CS_L[1]

AB32

MB_RAS_L

AD32

MB_CAS_L

AD33

MB_WE_L

H31

MB_RESET_L

Y31

MB_EVENT_L

TRINITY-A8-SERIES_BGA813

5745R1@

MB_DATA[0] MB_DATA[1] MB_DATA[2] MB_DATA[3] MB_DATA[4] MB_DATA[5] MB_DATA[6] MB_DATA[7]

MB_DATA[8]

MB_DATA[9] MB_DATA[10] MB_DATA[11] MB_DATA[12] MB_DATA[13] MB_DATA[14] MB_DATA[15]

MB_DATA[16] MB_DATA[17] MB_DATA[18] MB_DATA[19] MB_DATA[20] MB_DATA[21] MB_DATA[22] MB_DATA[23]

MB_DATA[24] MB_DATA[25] MB_DATA[26] MB_DATA[27] MB_DATA[28] MB_DATA[29] MB_DATA[30] MB_DATA[31]

MB_DATA[32] MB_DATA[33] MB_DATA[34] MB_DATA[35] MB_DATA[36] MB_DATA[37] MB_DATA[38] MB_DATA[39]

MB_DATA[40] MB_DATA[41] MB_DATA[42] MB_DATA[43] MB_DATA[44] MB_DATA[45] MB_DATA[46] MB_DATA[47]

MB_DATA[48] MB_DATA[49] MB_DATA[50] MB_DATA[51] MB_DATA[52] MB_DATA[53] MB_DATA[54] MB_DATA[55]

MB_DATA[56] MB_DATA[57] MB_DATA[58] MB_DATA[59] MB_DATA[60] MB_DATA[61] MB_DATA[62] MB_DATA[63]

C16 B17 B20 C20 A16 B16 B19 A20

B22 C22 A26 B26 B21 A22 C24 B25

A28 B28 B31 A32 C26 B27 A30 C30

B33 C32 F33 F32 B32 C31 E32 F31

AK32 AL32 AP32 AN31 AK31 AK33 AN32 AP33

AP30 AR30 AP27 AN26 AR32 AP31 AR28 AP28

AP25 AN24 AR22 AP21 AP26 AR26 AN22 AP22

AR20 AP19 AP16 AR16 AN20 AP20 AP17 AN16

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7

DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15

DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23

DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31

DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39

DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47

DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55

DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

DDR_B_D[0..63]

0.75V Reference Voltage

4 4

EVENT# pull high

+1.5V

1 2

R15 1K_0402_5%R15 1K_0402_5%

1 2

R61 1K_0402_5%R61 1K_0402_5%

MEM_MA_EVENT# MEM_MB_EVENT#

A

R64

1K_0402_1%

R65

1K_0402_1%

1 2

B

1

C124

C124 1000P_0402_50V7K

1000P_0402_50V7K

2

+MEM_VREF

2

C125

0.1U_0402_25V6

1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2013/03/20 2014/03/20

Compal Secret Data

Deciphered Date

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Title

Size Document Number Rev

Compal Electronics, Inc.

AMD Trinity FP2 DDRIII I/F

LA-9869P

E

6 51Wednesday, March 20, 2013

1.0

A

1 2

LVDS/eDP

1 1

CRT

(To FCH)

HDMI

DP0_TXP0_C DP0_TXN0_C

DP0_TXP1_C DP0_TXN1_C

ML_VGA_TXP0 ML_VGA_TXN0

ML_VGA_TXP1 ML_VGA_TXN1

ML_VGA_TXP2 ML_VGA_TXN2

ML_VGA_TXP3 ML_VGA_TXN3

UMA_HDMI_TX2+

UMA_HDMI_TX2-

UMA_HDMI_TX1+

UMA_HDMI_TX1-

UMA_HDMI_TX0+

UMA_HDMI_TX0-

UMA_HDMI_TXC+

UMA_HDMI_TXC-

100MHz (SS)

100MHz (Non-spread spectrum)

2 2

+1.5V

Close to JHDT

RPC3

1 8 2 7 3 6 4 5

1K_0804_8P4R_5%

1 2

R117 1K_0402_5%R117 1K_0402_5%

3 3

C127 1000P_0402_50V7K@C127 1000P_0402_50V7K@

C140 1000P_0402_50V7K@C140 1000P_0402_50V7K@

C141 1000P_0402_50V7K@C141 1000P_0402_50V7K@

1 2

C145

1 2

ESD@

APU_TDI APU_TCK APU_TMS APU_TRST#

APU_DBREQ#

APU_VDD_RUN_FB_L

APU_VDDNB_SEN

APU_VDD_SEN

APU_THERMTRIP#

1000P_0402_50V7K

APU_SVC

APU_SVD

APU_SVT

C56 0.1U_0402_16V7KC56 0.1U_0402_16V7K

1 2

C48 0.1U_0402_16V7KC48 0.1U_0402_16V7K

1 2

C58 0.1U_0402_16V7KIEDP@C58 0.1U_0402_16V7KIEDP@

1 2

C75 0.1U_0402_16V7KIEDP@C75 0.1U_0402_16V7KIEDP@

1 2

C67 0.1U_0402_16V7KC67 0.1U_0402_16V7K

1 2

C71 0.1U_0402_16V7KC71 0.1U_0402_16V7K

1 2

C66 0.1U_0402_16V7KC66 0.1U_0402_16V7K

1 2

C69 0.1U_0402_16V7KC69 0.1U_0402_16V7K

1 2

C68 0.1U_0402_16V7KC68 0.1U_0402_16V7K

1 2

C72 0.1U_0402_16V7KC72 0.1U_0402_16V7K

1 2

C73 0.1U_0402_16V7KC73 0.1U_0402_16V7K

1 2

C70 0.1U_0402_16V7KC70 0.1U_0402_16V7K

clock no test point

APU_CLK APU_CLK#

APU_DISP_CLK APU_DISP_CLK#

1 2

R212 0_0402_5%@R212 0_0402_5%@

1 2

R214 0_0402_5%@R214 0_0402_5%@

1 2

R215 0_0402_5%@R215 0_0402_5%@

R31 0_0402_5%@R31 0_0402_5%@ R32 0_0402_5%@R32 0_0402_5%@

R33 0_0402_5%@R33 0_0402_5%@

APU_SIC APU_SID

APU_RST# APU_PWRGD

T15T15

T16T16

APU_SVC APU_SVD

APU_SVT

1 2 1 2

1 2

For ESD request and close APU

4 4

A

B

DP0_TXP0 DP0_TXN0

DP0_TXP1 DP0_TXN1

DP1_TXP0 DP1_TXN0

DP1_TXP1 DP1_TXN1

DP1_TXP2 DP1_TXN2

DP1_TXP3 DP1_TXN3

APU_PROCHOT# APU_THERMTRIP# APU_ALERT#

APU_TDI APU_TDO APU_TCK APU_TMS APU_TRST# APU_DBRDY APU_DBREQ#

VSS_SENSE

T13T13

VDDNB_SENSE

T21T21

VDD_SENSE

T28T28

B

APU_SVC_R APU_SVD_R

APU_SVT_R

UAPUD

H2

DP0_TXP[0]

H1

DP0_TXN[0]

H3

DP0_TXP[1]

H4

DP0_TXN[1]

F4

DP0_TXP[2]

F3

DP0_TXN[2]

F1

DP0_TXP[3]

F2

DP0_TXN[3]

E2

DP1_TXP[0]

E1

DP1_TXN[0]

D4

DP1_TXP[1]

D3

DP1_TXN[1]

D1

DP1_TXP[2]

D2

DP1_TXN[2]

C1

DP1_TXP[3]

C2

DP1_TXN[3]

B2

DP2_TXP[0]

A2

DP2_TXN[0]

B3

DP2_TXP[1]

A3

DP2_TXN[1]

B4

DP2_TXP[2]

A4

DP2_TXN[2]

B5

DP2_TXP[3]

A5

DP2_TXN[3]

AL9

CLKIN_H

AK9

CLKIN_L

AL7

DISP_CLKIN_H

AK7

DISP_CLKIN_L

E5

SVC

E6

SVD

D6

SVT

AJ11

SIC

AH11

SID

AK11

RESET_L

AH9

PWROK

AL12

PROCHOT_L

AK5

THERMTRIP_L

AR10

ALERT_L

E11

TDI

G11

TDO

H12

TCK

F11

TMS

H11

TRST_L

E8

DBRDY

E7

DBREQ_L

G6

VSS_SENSE

H6

VDDP_SENSE

H5

VDDNB_SENSE

G7

VDDIO_SENSE

G5

VDD_SENSE

H7

VDDR_SENSE

TRINITY-A8-SERIES_BGA813

5745R1@

DISPLAY PORT 0DISPLAY PORT 1DISPLAY PORT 2CLKSER.CTRLJTAGSENSE

DP0_AUXP DP0_AUXN

DP1_AUXP DP1_AUXN

DP2_AUXP DP2_AUXN

DP3_AUXP DP3_AUXN

DP4_AUXP DP4_AUXN

DP5_AUXP DP5_AUXN

DP0_HPD

DISPLAY PORT MISC.RSVD TEST

DP1_HPD DP2_HPD DP3_HPD DP4_HPD DP5_HPD

DP_BLON

DP_DIGON

DP_VARY_BL

DP_AUX_ZVSS

TEST6

TEST9 TEST10 TEST14 TEST15 TEST16 TEST17 TEST18 TEST19 TEST20 TEST24

TEST25_H TEST25_L TEST28_H TEST28_L TEST30_H TEST30_L

TEST31

TEST32_H TEST32_L

TEST35

DMAACTIVE_L

TEST4

TEST5

RSVD RSVD RSVD RSVD RSVD

C

M5

DP0_AUXP

M6

DP0_AUXN

L5

DP1_AUXP

L6

DP1_AUXN

J5 J6

P5

Aux signal are re-configured as I2C signals for DDC

P6

APU AUX pin are 3.3V tolerant

R5 R6

U5 U6

M7

LVDS_HPD

L7

FCH_CRT_HPD

J7

HDMI_HPD

P7 R7 U7

C6 D7 A6

B6

DP_AUX_ZVSS

AL6 Y23 V23 G9 F9 E9 G8 F12

APU_TEST18

E12

APU_TEST19

F14

APU_TEST20

G12

APU_TEST24

AJ8

TEST25_H

AH8

TEST25_L

G14 H14 V25 Y25 AH32

APU_TEST31

R25 T25 AL5

APU_TEST35

AP10 T23

R23

L8 P8 AH12 AJ12 AK12

1 2

C47 0.1U_0402_16V7KC47 0.1U_0402_16V7K

1 2

C49 0.1U_0402_16V7KC49 0.1U_0402_16V7K

1 2

C57 0.1U_0402_16V7KC57 0.1U_0402_16V7K

1 2

C52 0.1U_0402_16V7KC52 0.1U_0402_16V7K

1 2

R16 150_0402_1%R16 150_0402_1%

R23 510_0402_1%R23 510_0402_1% R24 510_0402_1%R24 510_0402_1%

T7T7 T8T8 T9T9 T10T10

R38 39.2_0402_1%R38 39.2_0402_1%

T17T17 T18T18

R29 300_0402_5%R29 300_0402_5% R30 300_0402_5%@R30 300_0402_5%@

TEST4 TEST5

@ESD@

APU_PROCHOT#

CK0402101V05_0402-2

D31

1 2

T11T11 T12T12

DP0_AUXP_C DP0_AUXN_C

ML_VGA_AUXP ML_VGA_AUXN

UMA_HDMI_CLK UMA_HDMI_DATA

LVDS_HPD FCH_CRT_HPD HDMI_HPD

DP_ENBKL DP_ENVDD DP_INT_PWM

1 2 1 2

1 2

1 2 1 2

DMA_ACTIVE#

Change TEST35 to pull-high for HDMI issue check list recommend mount R29 and R30 @

Asserted as an input to force the processor into the HTC-active state

+1.5V

1

2

ESD@

C142

0.1U_0402_16V7K

3.3V Tolerance

+1.2VS

+1.5V

H_THERMTRIP#

2

1

For ESD request and close Q5

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2013/03/20 2014/03/20

Compal Secret Data

Deciphered Date

C144

1000P_0402_50V7K

D

LVDS CRT (To FCH) HDMI

APU_PROCHOT#

ESD@

D

DP0_AUXP DP0_AUXN DP1_AUXP

DP1_AUXN LVDS_HPD FCH_CRT_HPD HDMI_HPD

DP0_AUXP

DP0_AUXN

RPC1

1 8

APU_TEST18

2 7

APU_TEST19

3 6

APU_TEST20

4 5

APU_TEST24

1K_0804_8P4R_5%

APU_RST#

APU_PWRGD

R55

1K_0402_5%

1 2

@

R136 0_0402_5%

1K_0402_5%

APU_THERMTRIP#

APU_SVT_R APU_SVC_R APU_SVD_R

APU_RST#

APU_PWRGD

Custom

Date: Sheet of

E

R25 1.8K_0402_5%R25 1.8K_0402_5% R58 1.8K_0402_5%R58 1.8K_0402_5% R10 1.8K_0402_5%R10 1.8K_0402_5% R11 1.8K_0402_5%R11 1.8K_0402_5% R74 100K_0402_5%R74 100K_0402_5% R75 100K_0402_5%R75 100K_0402_5% R95 100K_0402_5%R95 100K_0402_5%

12 12 12 12 12 12 12

For 2132R

1 2

C138 680P_0402_50V7KC138 680P_0402_50V7K

1 2

C139 680P_0402_50V7KC139 680P_0402_50V7K

+1.5V

R36 1K_0402_5%@R36 1K_0402_5%@ R39 1K_0402_5%@R39 1K_0402_5%@ R41 1K_0402_5%@R41 1K_0402_5%@

R52 300_0402_5%R52 300_0402_5% R54 300_0402_5%R54 300_0402_5%

+1.5V

1 2

+1.5V

R68

1 2

B

E

3 1

MMBT3904_NL_SOT23-3

Title

AMD Trinity FP2 Display / MISC / HDT

Size Document Number Rev

LA-9869P

12 12 12

+1.5V

RPC2

APU_SIC APU_SID APU_ALERT# DMA_ACTIVE#

1 2

C126 1000P_0402_50V7K

1 2

C130 180P_0402_50V8J

12

R69

R69 10K_0402_5%

10K_0402_5%

2

C

Compal Electronics, Inc.

1 8 2 7 3 6 4 5

1K_0804_8P4R_5%

12 12

ESD@

Thermal Shutdown Temperature: 115 degree

Q5

+1.5V

H_PROCHOT#APU_PROCHOT#

H_THERMTRIP#

E

7 51Wednesday, March 20, 2013

1.0

A

+1.5V

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB VDDNB

VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO

VDDR VDDR VDDR VDDR VDDR

C170 0.22U_0402_10V4ZC170 0.22U_0402_10V4Z

1

2

+APU_CORE

V17 V19 V20 V22 W8 AA8 AA9 AA11 AA12 AA14 AA15 AA17 AA19 AA20 AA22 AD9 AD11 AD12 AD14 AD15 AD17 AD19 AD20 AD22 AG12 AG14 AG15 AG17 AG19 AG20 AG22

B11 B12 B13 B14 B15 C8 C10 C12 C14 D8 D10 D12 D14

M9 N9

W33 AA23 AA25 AA27 AA30 AA33 AB28 AC30 AC33 AD23 AD25 AD27 AE28 AE30 AE33 AG23 AG25 AG27 AG30 AG33

AN14 AP14 AP15 AR14 AR15

+VDDA

C165 4.7U_0603_6.3V6KC165 4.7U_0603_6.3V6K

1

2

+APU_CORE_NB

+VDDNB_CAP

+1.5V +1.2VS

C158 180P_0402_50V8JC158 180P_0402_50V8J

C163 22U_0603_6.3V6MC163 22U_0603_6.3V6M

C196 22U_0603_6.3V6MC196 22U_0603_6.3V6M

1

2

close to APU

+VDDP_CAP

+APU_CORE

1 1

+APU_CORE_NB

2 2

+1.5V

3 3

+1.2VS

+VDDP_CAP

+VDDA

Other signals should keep 20 mil away with +VDDA

FBMA-L11-201209-300LMA30T

+2.5VS

4 4

UAPUE

J12

VDD

J14

VDD

J15

VDD

J17

VDD

J19

VDD

J20

VDD

J22

VDD

M11

VDD

M12

VDD

M14

VDD

M15

VDD

M17

VDD

M19

VDD

M20

VDD

M22

VDD

R8

VDD

R9

VDD

R11

VDD

R12

VDD

R14

VDD

R15

VDD

R17

VDD

R19

VDD

R20

VDD

R22

VDD

U8

VDD

V9

VDD

V11

VDD

V12

VDD

V14

VDD

V15

VDD

A7

VDDNB

A8

VDDNB

A9

VDDNB

A10

VDDNB

A11

VDDNB

A12

VDDNB

A13

VDDNB

A14

VDDNB

A15

VDDNB

B7

VDDNB

B8

VDDNB

B9

VDDNB

B10

VDDNB

J33

VDDIO

K23

VDDIO

K25

VDDIO

L28

VDDIO

L30

VDDIO

L33

VDDIO

M27

VDDIO

N23

VDDIO

N25

VDDIO

N30

VDDIO

N33

VDDIO

P28

VDDIO

R27

VDDIO

R30

VDDIO

R33

VDDIO

U28

VDDIO

U30

VDDIO

U33

VDDIO

W28

VDDIO

W30

VDDIO

AM12

VDDP

AN12

VDDP

AP12

VDDP

AP13

VDDP

AR12

VDDP

AR13

VDDP

AA6

VDDP_CAP

AA7

VDDP_CAP

AM13

VDDA

AM14

VDDA

TRINITY-A8-SERIES_BGA813

5745R1@

L1

1 2

36A

30A

VDDNB_CAP VDDNB_CAP

3.2A

3.5A

0.75A

C164 3300P_0402_50V7-KC164 3300P_0402_50V7-K

3.5A

1

2

B

C63 22U_0603_6.3V6MC63 22U_0603_6.3V6M

C65 22U_0603_6.3V6MC65 22U_0603_6.3V6M

C64 22U_0603_6.3V6MC64 22U_0603_6.3V6M

C74 22U_0603_6.3V6MC74 22U_0603_6.3V6M

1

2

C91 4.7U_0603_6.3V6KC91 4.7U_0603_6.3V6K

C90 4.7U_0603_6.3V6KC90 4.7U_0603_6.3V6K

C92 4.7U_0603_6.3V6KC92 4.7U_0603_6.3V6K

C89 4.7U_0603_6.3V6KC89 4.7U_0603_6.3V6K

1

2

C94 0.22U_0402_10V4ZC94 0.22U_0402_10V4Z

C93 0.22U_0402_10V4ZC93 0.22U_0402_10V4Z

1

2

C102 0.22U_0402_10V4ZC102 0.22U_0402_10V4Z

C117 0.22U_0402_10V4ZC117 0.22U_0402_10V4Z

C96 0.22U_0402_10V4ZC96 0.22U_0402_10V4Z

C97 0.22U_0402_10V4ZC97 0.22U_0402_10V4Z

C95 0.22U_0402_10V4ZC95 0.22U_0402_10V4Z

1

2

VDDR more different VDDP more different

+1.2VS

1

2

C169 22U_0805_6.3V6MC169 22U_0805_6.3V6M

C168 22U_0805_6.3V6MC168 22U_0805_6.3V6M

1

2

C149 0.01U_0402_16V7KC149 0.01U_0402_16V7K

C137 0.01U_0402_16V7KC137 0.01U_0402_16V7K

1

2

C115 0.22U_0402_10V4ZC115 0.22U_0402_10V4Z

C116 0.22U_0402_10V4ZC116 0.22U_0402_10V4Z

1

2

C110 180P_0402_50V8JC110 180P_0402_50V8J

C111 1000P_0402_50V7KC111 1000P_0402_50V7K

C109 180P_0402_50V8JC109 180P_0402_50V8J

1

2

C119 0.22U_0402_10V4ZC119 0.22U_0402_10V4Z

C118 0.22U_0402_10V4ZC118 0.22U_0402_10V4Z

1

2

C

C100 180P_0402_50V8JC100 180P_0402_50V8J

1

2

C131 4.7U_0603_6.3V6K@C131 4.7U_0603_6.3V6K

C103 180P_0402_50V8JC103 180P_0402_50V8J

1

2

@

+1.2VS

C106 180P_0402_50V8JC106 180P_0402_50V8J

C105 180P_0402_50V8JC105 180P_0402_50V8J

1

2

Power Sequence of APU

+1.5V

+2.5VS

+1.5VS

+CPU_CORE

+CPU_CORE_NB

+1.2VS

1

2

+1.5V

1

C150

C150 100U_1206_6.3V6K

100U_1206_6.3V6K

@

2

D

UAPUF

A17

VSS

A19

VSS

A21

VSS

A23

VSS

A25

VSS

A27

VSS

A29

VSS

A31

VSS

B1

VSS

C3

VSS

C4

VSS

C33

VSS

D5

VSS

D9

VSS

D11

VSS

D13

VSS

D15

VSS

D17

VSS

D19

VSS

D21

VSS

D23

VSS

D25

VSS

D30

VSS

E4

VSS

E27

VSS

E29

VSS

E30

VSS

E33

VSS

F5

VSS

F6

VSS

F7

VSS

C132 0.22U_0402_10V4ZC132 0.22U_0402_10V4Z

C152 0.22U_0402_10V4ZC152 0.22U_0402_10V4Z

C632 22U_0603_6.3V6MC632 22U_0603_6.3V6M

C77 22U_0603_6.3V6MC77 22U_0603_6.3V6M

1

2

C655 22U_0603_6.3V6M@C655 22U_0603_6.3V6M

1

@

2

Group A

Group B

F8

VSS

F17

VSS

F20

VSS

F23

VSS

F28

VSS

F29

VSS

G1

VSS

G2

VSS

G4

VSS

G15

VSS

G19

VSS

G25

VSS

G26

VSS

G27

VSS

G33

VSS

H8

VSS

H9

VSS

H22

VSS

H26

VSS

J4

VSS

J8

VSS

J9

VSS

J11

VSS

J23

VSS

J25

VSS

J26

VSS

J27

VSS

J30

VSS

K9

VSS

K11

VSS

K12

VSS

K14

VSS

K15

VSS

K17

VSS

K19

VSS

K20

VSS

K22

VSS

L1

VSS

L2

VSS

L4

VSS

M8

VSS

M23

VSS

M25

VSS

N4

VSS

N11

VSS

N12

VSS

N14

VSS

N15

VSS

N17

VSS

N19

VSS

N20

VSS

N22

VSS

R1

VSS

R2

VSS

R4

VSS

T9

VSS

T11

VSS

T12

VSS

T14

VSS

T15

VSS

T17

VSS

T19

VSS

T20

VSS

T22

VSS

U4

VSS

W1

VSS

W2

VSS

W4

VSS

W5

VSS

W6

VSS

W7

VSS

Y9

VSS

TRINITY-A8-SERIES_BGA813

5745R1@

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

E

Y11 Y12 Y14 Y15 Y17 Y19 Y20 Y22 AA4 AA5 AB7 AB8 AC1 AC2 AC4 AC9 AC11 AC12 AC14 AC15 AC17 AC19 AC20 AC22 AC23 AC25 AE4 AF9 AF11 AF12 AF14 AF15 AF17 AF19 AF20 AF22 AF23 AF25 AG1 AG2 AG4 AG9 AG11 AG26 AH7 AH17 AH20 AH23 AH26 AH30 AJ4 AJ5 AJ6 AJ7 AJ9 AJ14 AJ15 AJ19 AJ22 AJ27 AJ28 AJ33 AK6 AK8 AK25 AK28 AK30 AL1 AL2 AL4 AL8 AL11 AL27 AL28 AL33 AM5 AM7 AM9 AM11 AM15 AM17 AM19 AM21 AM23 AM25 AM29 AM30 AN3 AN4 AN33 AP5 AP9 AR2 AR5 AR9 AR17 AR19 AR21 AR23 AR25 AR27 AR29 AR31

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2013/03/20 2014/03/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

AMD Trinity FP2 PWR / GND

LA-9869P

E

1.0

of

8 51Wednesday, March 20, 2013

5

R49

0_0402_5%

@

APU_SID

BSH111_SOT23-3

Vg = 1.607 V

APU_SIC

BSH111_SOT23-3

+1.5V

Q16

Q16 AO3413_SOT23

AO3413_SOT23

S

G

2

D

@

1 2

1 3

+1.5V_SI

G

2

Q14

13

D

S

D

S

G

2

Q15

13

D

S

D

S

SUSP

D D

APU_SID

C C

APU_SIC

4

BSH111, the Vgs is: min = 0.4V Max = 1.3V

When APU High -> MOS OFF (Vgs < 0.4V )

APU Low -> MOS ON (Vgs > 1.3V)

EC_SMB_DA1

EC_SMB_CK1

3

Panel PWMSB-TSI

DP_INT_PW M

eDP Panel ENVDD

2

R93

LVDS@R93

R89

LVDS@R89

LVDS@

2.2K_0402_5%

Q21

LVDS@Q21

LVDS@

MMBT3904_NL_SOT23-3

MMBT3904_NL_SOT23-3 R92

LVDS@R92

LVDS@

47K_0402_5%

DP_INT_PW M APU_INVT_PWM

DP_INT_PW M

DP_ENVDD

R46 0_0402_5%

LVDS@

4.7K_0402_5%

Q28

LVDS@Q28

LVDS@

2N7002KW_SOT323-3

@

1 2

R89 2.2K_0402_5%

12

R76

4.7K_0402_5%

R141 2.2K_0402_5%

12

R147

R147 100K_0402_5%

100K_0402_5%

IEDP@

1 2

IEDP@

1 2

IEDP@

+3VS

12

R92

R92 47K_0402_5%

47K_0402_5%

IEDP@

C

2

Q21

B

MMBT3904_NL_SOT23-3

E

3 1

IEDP@

+3VS

12

R135

R135 47K_0402_5%

47K_0402_5%

IEDP@

C

2

Q26

B

MMBT3904_NL_SOT23-3

E

IEDP@

3 1

2

G

12

13

12

R137

4.7K_0402_5%

IEDP@

61

1

R93

4.7K_0402_5%

IEDP@

APU_INVT_PWM

D

Q28

Q28 2N7002KW_SOT323-3

2N7002KW_SOT323-3

IEDP@

S

LCD_ENVDD

IEDP@

Q29A

Q29A 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

APU_INVT_PWM

B B

+3VS

eDP Panel ENBKL

12

R144

R144 47K_0402_5%

47K_0402_5%

IEDP@

C

DP_ENBKL

A A

Security Classification

2013/03/20 2014/03/20

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/03/20 2014/03/20

3

Compal Secret Data

Deciphered Date

1 2

R146 2.2K_0402_5%

12

R142

R142 100K_0402_5%

100K_0402_5%

IEDP@

2

IEDP@

2

Q27

B

MMBT3904_NL_SOT23-3

E

IEDP@

3 1

Title

Size Document Number Rev

Custom

Date: Sheet of

Date: Sheet

12

R143

4.7K_0402_5%

IEDP@

3

IEDP@

5

Q29B

Q29B 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

4

AMD Trinity FP2 Singal Level Shifter

LA-9869P

LCD_ENBKL

1

9 51Wednesday, March 20, 2013

1.0

of

5

+1.5V

+VREF_DQA

D D

DDR_A_BS2

C C

DDR_A_CLK0 DDR_A_CLK0#

DDR_A_BS0

DDR_A_WE#

DDR_A_CAS#

DDR_A_SCS1#

B B

+3VS

A A

C182

1

2

0.1U_0402_16V4Z

DDR_A_D0 DDR_A_D1

DDR_A_DM0 DDR_A_D2

DDR_A_D3 DDR_A_D8

DDR_A_D9 DDR_A_DQS#1

DDR_A_DQS1 DDR_A_D10

DDR_A_D11 DDR_A_D16

DDR_A_D17 DDR_A_DQS#2

DDR_A_DQS2 DDR_A_D18

DDR_A_D19 DDR_A_D24

DDR_A_D25 DDR_A_DM3 DDR_A_D26

DDR_A_D27

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

DDR_A_MA10

DDR_A_MA13

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5 DDR_A_D42

DDR_A_D43 DDR_A_D48

DDR_A_D49 DDR_A_DQS#6

DDR_A_DQS6 DDR_A_D50

DDR_A_D51 DDR_A_D56

DDR_A_D57 DDR_A_DM7 DDR_A_D58

DDR_A_D59

+0.75VS

JDDR3L

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

LCN_DAN06-K4406-0103

@

VSS3

DQS#0

DQS0

VSS6

VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44

DQ45 VSS35 DQS#5

DQS5

VSS38

DQ46

DQ47 VSS40

DQ52

DQ53 VSS42

DM6

VSS43

DQ54

DQ55 VSS45

DQ60

DQ61 VSS47 DQS#7

DQS7

VSS50

DQ62

DQ63 VSS52

EVENT#

SDA

VTT2

DQ4 DQ5

DQ6 DQ7

CK1

BA1

NC2

SCL

A15 A14

A11

S0#

+1.5V

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86

A7

88 90

A6

92

A4

94 96

A2

98

A0

100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

G2

DDR_A_D4 DDR_A_D5

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D6 DDR_A_D7

DDR_A_D12 DDR_A_D13

DDR_A_DM1

DDR_A_D14 DDR_A_D15

DDR_A_D20 DDR_A_D21

DDR_A_DM2 DDR_A_D22

DDR_A_D23 DDR_A_D28

DDR_A_D29 DDR_A_DQS#3

DDR_A_DQS3 DDR_A_D30

DDR_A_D31

DDR_A_MA15 DDR_A_MA14

DDR_A_MA11 DDR_A_MA7

DDR_A_MA6 DDR_A_MA4

DDR_A_MA2 DDR_A_MA0

+VREF_CAA DDR_A_D36

DDR_A_D37 DDR_A_DM4 DDR_A_D38

DDR_A_D39 DDR_A_D44

DDR_A_D45 DDR_A_DQS#5

DDR_A_DQS5 DDR_A_D46

DDR_A_D47 DDR_A_D52

DDR_A_D53 DDR_A_DM6 DDR_A_D54

DDR_A_D55 DDR_A_D60

DDR_A_D61 DDR_A_DQS#7

DDR_A_DQS7 DDR_A_D62

DDR_A_D63

+0.75VS

4

DDR3 SO-DIMM A Reverse Type

MEM_MA_RST#

DDR_A_CKE1DDR_A_CKE0

DDR_A_CLK1 DDR_A_CLK1#

DDR_A_BS1 DDR_A_RAS#

DDR_A_SCS0# DDR_A_ODT0

DDR_A_ODT1

C162

Close to JDDR3H.126

MEM_MA_EVENT# FCH_SDATA0 FCH_SCLK0

3

+VREF_DQA

DDR_A_DQS[0..7] DDR_A_DQS#[0..7] DDR_A_D[0..63] DDR_A_MA[0..15] DDR_A_DM[0..7]

1

C156

C157

0.1U_0402_16V7K

2

+1.5V

12

R79

1K_0402_1%

12

R81

@

2.2U_0402_6.3V6M

R81

1

1K_0402_1%

2

1

Close to JDDR3H.1

+1.5V

1

C148

+1.5V

12

R80

1K_0402_1%

12

@

1

C161

2.2U_0402_6.3V6M

0.1U_0402_16V7K

2

R82

1K_0402_1%

2

C148 100U_1206_6.3V6K

100U_1206_6.3V6K

2

SE00000O000

Layout Note: Place near JDDR3H

+1.5V

C176 10U_0603_6.3V6MC176 10U_0603_6.3V6M C174 10U_0603_6.3V6MC174 10U_0603_6.3V6M C173 10U_0603_6.3V6MC173 10U_0603_6.3V6M C171 10U_0603_6.3V6MC171 10U_0603_6.3V6M C167 10U_0603_6.3V6MC167 10U_0603_6.3V6M C166 10U_0603_6.3V6MC166 10U_0603_6.3V6M

12 12 12 12 12 12

1 2

C179 0.1U_0402_16V4ZC179 0.1U_0402_16V4Z

1 2

C178 0.1U_0402_16V4ZC178 0.1U_0402_16V4Z

1 2

C185 0.1U_0402_16V4ZC185 0.1U_0402_16V4Z

1 2

C180 0.1U_0402_16V4ZC180 0.1U_0402_16V4Z

Layout Note: Place near JDDR3H.203 and 204

+0.75VS

1 2

C84 4.7U_0603_6.3V6KC84 4.7U_0603_6.3V6K

1 2

C186 0.1U_0402_16V4ZC186 0.1U_0402_16V4Z

1 2

C205 0.1U_0402_16V4ZC205 0.1U_0402_16V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2013/03/20 2014/03/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

DDRIII-SODIMM0

LA-9869P

1

10 51Wednesday, March 20, 2013

1.0

A

+1.5V

+VREF_DQB

1 1

DDR_B_CKE0

DDR_B_BS2

2 2

DDR_B_CLK0 DDR_B_CLK0#

DDR_B_WE# DDR_B_CAS#

DDR_B_SCS1#

3 3

+3VS

1

4 4

2

0.1U_0402_16V4Z

C208

DDR_B_D0 DDR_B_D1

DDR_B_DM0 DDR_B_D2

DDR_B_D3 DDR_B_D8

DDR_B_D9 DDR_B_DQS#1

DDR_B_DQS1 DDR_B_D10

DDR_B_D11 DDR_B_D16

DDR_B_D17 DDR_B_DQS#2

DDR_B_DQS2 DDR_B_D18

DDR_B_D19 DDR_B_D24

DDR_B_D25 DDR_B_DM3 DDR_B_D26

DDR_B_D27

DDR_B_MA12 DDR_B_MA9

DDR_B_MA8 DDR_B_MA5

DDR_B_MA3 DDR_B_MA1

DDR_B_MA10

DDR_B_MA13

DDR_B_D37 DDR_B_D36

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_DM5 DDR_B_D42

DDR_B_D43 DDR_B_D48

DDR_B_D49 DDR_B_DQS#6

DDR_B_DQS6 DDR_B_D54

DDR_B_D55 DDR_B_D56

DDR_B_D57 DDR_B_DM7 DDR_B_D58

DDR_B_D59

+0.75VS

JDDR3H

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

LCN_DAN06-K4806-0103

@

VSS3

DQS#0

DQS0

VSS6

VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44

DQ45 VSS35 DQS#5

DQS5

VSS38

DQ46

DQ47 VSS40

DQ52

DQ53 VSS42

DM6

VSS43

DQ54

DQ55 VSS45

DQ60

DQ61 VSS47 DQS#7

DQS7

VSS50

DQ62

DQ63 VSS52

EVENT#

SDA

VTT2

DQ4 DQ5

DQ6 DQ7

CK1

BA1

NC2

SCL

A15 A14

A11

S0#

+1.5V

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78 80 82 84 86

A7

88 90

A6

92

A4

94 96

A2

98

A0

100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

G2

DDR_B_D4 DDR_B_D5

DDR_B_DQS#0 DDR_B_DQS0

DDR_B_D6 DDR_B_D7

DDR_B_D12 DDR_B_D13

DDR_B_DM1

DDR_B_D14 DDR_B_D15

DDR_B_D20 DDR_B_D21

DDR_B_DM2 DDR_B_D22

DDR_B_D23 DDR_B_D28

DDR_B_D29 DDR_B_DQS#3

DDR_B_DQS3 DDR_B_D30

DDR_B_D31

DDR_B_MA15 DDR_B_MA14

DDR_B_MA11 DDR_B_MA7

DDR_B_MA6 DDR_B_MA4

DDR_B_MA2 DDR_B_MA0

+VREF_CAB DDR_B_D32

DDR_B_D33 DDR_B_DM4 DDR_B_D38

DDR_B_D39 DDR_B_D44

DDR_B_D45 DDR_B_DQS#5

DDR_B_DQS5 DDR_B_D46

DDR_B_D47 DDR_B_D52

DDR_B_D53 DDR_B_DM6 DDR_B_D50

DDR_B_D51 DDR_B_D60

DDR_B_D61 DDR_B_DQS#7

DDR_B_DQS7 DDR_B_D62

DDR_B_D63

+0.75VS

B

DDR3 SO-DIMM B Reverse Type

MEM_MB_RST#

DDR_B_CKE1

DDR_B_CLK1 DDR_B_CLK1#

DDR_B_BS1 DDR_B_RAS#DDR_B_BS0

DDR_B_SCS0# DDR_B_ODT0

DDR_B_ODT1

Close to JDDR3L.126

MEM_MB_EVENT# FCH_SDATA0 FCH_SCLK0

C188

C

DDR_B_DQS#[0..7] DDR_B_DQS[0..7] DDR_B_D[0..63] DDR_B_MA[0..15] DDR_B_DM[0..7]

+1.5V

12

R83

1K_0402_1%

+VREF_DQB

12

@

1

C184

1

C183

0.1U_0402_16V7K

2.2U_0402_6.3V6M

2

R84

1K_0402_1%

2

D

E

Close to JDDR3L.1

+1.5V

12

R86

1K_0402_1%

12

@

1

C187

0.1U_0402_16V7K

2.2U_0402_6.3V6M

2

R94

1K_0402_1%

2

Layout Note: Place near JDDR3L

+1.5V

12

C195 10U_0603_6.3V6MC195 10U_0603_6.3V6M

12

C189 10U_0603_6.3V6MC189 10U_0603_6.3V6M

12

C181 10U_0603_6.3V6MC181 10U_0603_6.3V6M

12

C177 10U_0603_6.3V6MC177 10U_0603_6.3V6M

12

C175 10U_0603_6.3V6MC175 10U_0603_6.3V6M

12

C172 10U_0603_6.3V6MC172 10U_0603_6.3V6M

1 2

C190 0.1U_0402_16V4ZC190 0.1U_0402_16V4Z

1 2

C191 0.1U_0402_16V4ZC191 0.1U_0402_16V4Z

1 2

C192 0.1U_0402_16V4ZC192 0.1U_0402_16V4Z

1 2

C193 0.1U_0402_16V4ZC193 0.1U_0402_16V4Z

Layout Note: Place near JDDRL.203 and 204

+0.75VS +1.5V

@

12

C197 10U_0603_6.3V6M

1 2

C194 0.1U_0402_16V4ZC194 0.1U_0402_16V4Z

1 2

C206 0.1U_0402_16V4ZC206 0.1U_0402_16V4Z

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2013/03/20 2014/03/20

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

DDRIII-SODIMM1

LA-9869P

E

11 51Wednesday, March 20, 2013

1.0

A

B

C

D

E

PCIE_ATX_C_GRX_P[3..0] PCIE_ATX_C_GRX_N[3..0]

1 1

2 2

3 3

CLK_PCIE_VGA CLK_PCIE_VGA#

3.3-V tolerant

PCIE_ATX_C_GRX_P[3..0] PCIE_ATX_C_GRX_N[3..0]

PCIE_ATX_C_GRX_P0 PCIE_ATX_C_GRX_N0

PCIE_ATX_C_GRX_P1 PCIE_ATX_C_GRX_N1

PCIE_ATX_C_GRX_P2 PCIE_ATX_C_GRX_N2

PCIE_ATX_C_GRX_P3 PCIE_ATX_C_GRX_N3

CLK_PCIE_VGA CLK_PCIE_VGA#

12

VGA@

RV2 1K_0402_5%

GPU_RST#

12

VGA@

RV212

RV212 100K_0402_5%

100K_0402_5%

AA38

W36

W38

AB35 AA36

AH16

AA30

U36

U38

R36

R38

N36

N38 M37

M35

H37

H35 G36

G38

Y37

Y35

V37

V35

T37

T35

P37

P35

L36

L38 K37

K35 J36

J38

F37

F35 E37

UV1A

PCIE_RX0P PCIE_RX0N

PCIE_RX1P PCIE_RX1N

PCIE_RX2P PCIE_RX2N

PCIE_RX3P PCIE_RX3N

PCIE_RX4P PCIE_RX4N

PCIE_RX5P PCIE_RX5N

PCIE_RX6P PCIE_RX6N

PCIE_RX7P PCIE_RX7N

NC NC

CLOCK

PCIE_REFCLKP PCIE_REFCLKN

TEST_PG

PERSTB

SUNR1@

PART 1 0F 9

PCI EXPRESS INTERFACE

SUN-PRO M2_FCBGA962

PCIE_TX0P PCIE_TX0N

PCIE_TX1P PCIE_TX1N

PCIE_TX2P PCIE_TX2N

PCIE_TX3P PCIE_TX3N

PCIE_TX4P PCIE_TX4N

PCIE_TX5P PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

CALIBRATION

PCIE_CALR_TX PCIE_CALR_RX

PCIE_GTX_C_ARX_P[3..0] PCIE_GTX_C_ARX_N[3..0]

.1U_0402_16V7K

Y33

PCIE_GTX_ARX_P0 PCIE_GTX_C_ARX_P0

Y32

W33

PCIE_GTX_ARX_P1

W32

PCIE_GTX_ARX_N1

U33

PCIE_GTX_ARX_P2

U32

PCIE_GTX_ARX_N2 PCIE_GTX_C_ARX_N2

U30

PCIE_GTX_ARX_P3

U29

PCIE_GTX_ARX_N3 PCIE_GTX_C_ARX_N3

T33 T32

T30 T29

P33 P32

P30 P29

N33

NC

N32

NC

N30

NC

N29

NC

L33

NC

L32

NC

L30

NC

L29

NC

K33

NC

K32

NC

J33

NC

J32

NC

K30

NC

K29

NC

H33

NC

H32

NC

Y30

VGA_PCIE_CALRP

Y29

VGA_PCIE_CALRN

.1U_0402_16V7K

.1U_0402_16V7K .1U_0402_16V7K

.1U_0402_16V7K

AC Coupling Capacitor PCIeR Gen1 and Gen2 only: Recommended value is 100 nF 10%. PCIeR Gen3: Recommended value is 220 nF 10%.

1 2

RV1 1.69K_0402_1%VGA@RV1 1.69K_0402_1%VGA@

1 2

RV3 1K_0402_1%VGA@RV3 1K_0402_1%VGA@

PCIE_GTX_C_ARX_P[3..0] PCIE_GTX_C_ARX_N[3..0]

1 2

CV1 CV2

CV3 CV4

CV5 CV6

CV7 CV8

1 2

1 2 1 2

1 2

VGA@CV1

VGA@ VGA@CV2

VGA@

VGA@CV3

VGA@ VGA@CV4

VGA@

VGA@CV5

VGA@ VGA@CV6

VGA@

VGA@CV7

VGA@ VGA@CV8

VGA@

PCIE_GTX_C_ARX_N0PCIE_GTX_ARX_N0

PCIE_GTX_C_ARX_P1 PCIE_GTX_C_ARX_N1

PCIE_GTX_C_ARX_P2

PCIE_GTX_C_ARX_P3

+0.95VGS +0.95VGS

LVDS Interface

UV1D

PART 7 0F 9

RSVD/VARY_BL

RSVD/DIGON

TXCBP_DPB3P TXCBM_DPB3N

TX3P_DPB2P TX3M_DPB2N

TX4P_DPB1P TX4M_DPB1N

TX5P_DPB0P TX5M_DPB0N

NC#AF35 NC#AG36

TXCAP_DPA3P TXCAM_DPA3N

TX0P_DPA2P TX0M_DPA2N

TX1P_DPA1P TX1M_DPA1N

TX2P_DPA0P TX2M_DPA0N

SUN-PRO M2_FCBGA962

NC NC

LVTMDP

SUNR1@

LVDS CONTROL

AK27 AJ27

AK35 AL36

AJ38 AK37

AH35 AJ36

AG38 AH37

AF35 AG36

AP34 AR34

AW37 AU35

AR37 AU39

AP35 AR35

AN36 AP37

+3VS

VGA@

5

UV13

4 4

PXS_RST#

APU_PCIE_RST#

A

UV13

2

P

B

4

Y

1

A

G

3

MC74VHC1G08DFT2G SC70 5P

GPU_RST#

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2013/03/20 2014/03/20

Compal Secret Data

Deciphered Date

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Compal Electronics, Inc.

PCIE/LVDS

LA-9869P

12 51Wednesday, March 20, 2013

E

1.0

A

+3VGS

1 1

RV12

1 8

JTAG_TRSTB

2 7 3 6 4 5

10K_8P4R_5%

+3VGS

2 2

+3VGS

3 3

4 4

10K_8P4R_5%

CHECK VR IF VR Suport PSI# and DPRSLPVR PU 10K to +3VGS: PSI# :Low load current flag DPRSLPVR : Deeper sleep enable flag

+3VGS

VGA@

1 2

RV15 10K_0402_5%

VGA@

RV14

1 2

10K_0402_5%

GENERIC_X Stereo-sync signal. Indicates left/right frame, or top/bottom field. Can be left unconnected if not used.

Enable JTAG access

RV7

5.11K_0402_5%

@

1 2

TESTEN

Reserved signal, for normal ASIC operation.

RV9

RV9 1K_0402_5%

1K_0402_5%

VGA@

TSVDD MarsCRB Design 120ohm 1 1

0.1u 1 1 1u 1 1 10u 1 1

JTAG_TDI JTAG_TMS JTAG_TCK

@

RV13

1 8

GPIO_16

2 7

GPIO_28_FDO

3 6

VGA_SMB_CK2

4 5

VGA_SMB_DA2

VGA@

GPU_DPRSLPVR

RV11 10K_0402_5%

GPU_DOWN#

GPU_VID5

GPU_DOWN#

GPU_VID1

GPU_VID2

CLKREQ_PEG#

GPU_VID3 GPU_VID4

PX_EN : H

igh (3.3 V) switches the regulators off (enter BACO mode). Low (0 V) switches the regulators on. (Default)

MLPS

GPIO_28_FDO

Disable

H

Enable

L

LV3

VGA@ LV3

VGA@

1 2

BLM15BD121SN1D_0402

A

VGA@

1 2

RV8

+TSVDD+1.8VGS

CV17

VGA@ CV17

VGA@

VGA_SMB_CK2 VGA_SMB_DA2

TV1TV1 TV2TV2 TV3TV3

1 2

TV4TV4 TV5TV5

TV9TV9

TV7TV7

(1.8V@13mA TSVDD)

1

CV18

2

10U_0603_6.3V6M

VGA@ CV18

VGA@

GPU_DPRSLPVR

GPU_DOWN#

GPU_VID5 GPU_GPIO8

GPU_GPIO9 GPU_GPIO10

GPU_VID1

GPIO_16

10K_0402_5%@

GPU_VID2 GPU_GPIO21 GPU_GPIO22 CLKREQ_PEG#

GPU_VID3 GPU_VID4

PX_EN

JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO

GPIO_28_FDO

+TSVDD

1

CV19

2

1U_0402_6.3V6K

VGA@ CV19

VGA@

UV1B

PART 2 0F 9

MUTI GFX

AD29

GENLK_CLK

AC29

GENLK_VSYNC

AJ21

SWAPLOCKA

AK21

SWAPLOCKB

AR8

NC

AU8

NC

AP8

DBG_CNTL0

AW8

NC

AR3

NC

AR1

NC

AU1

DBG_DATA0

AU3

DBG_DATA1

AW3

DBG_DATA2

AP6

DBG_DATA3

AW5

DBG_DATA4

AU5

DBG_DATA5

AR6

DBG_DATA6

AW6

DBG_DATA7

AU6

DBG_DATA8

AT7

DBG_DATA9

AV7

DBG_DATA10

AN7

DBG_DATA11

AV9

DBG_DATA12

AT9

DBG_DATA13

AR10

DBG_DATA14

AW10

DBG_DATA15

AU10

DBG_DATA16

AP10

DBG_DATA17

AV11

DBG_DATA18

AT11

DBG_DATA19

AR12

DBG_DATA20

AW12

DBG_DATA21

AU12

DBG_DATA22

AP12

DBG_DATA23

AJ23

SMBCLK

AH23

SMBDATA

AK26

SCL

AJ26

SDA

GENERAL PURPOSE I/O

AH20

GPIO_0

AH18

GPIO_1

AN16

GPIO_2

AH17

GPIO_5_AC_BATT

AJ17

GPIO_6_TACH

AK17

GPIO_7_BLON

AJ13

GPIO_8_ROMSO

AH15

GPIO_9_ROMSI

AJ16

GPIO_10_ROMSCK

AK16

GPIO_11

AL16

GPIO_12

AM16

GPIO_13

AM14

GPIO_14_HPD2

AM13

GPIO_15_PWRCNTL_0

AK14

GPIO_16

AG30

GPIO_17_THERMAL_INT

AN14

GPIO_18_HPD3

AM17

GPIO_19_CTF

AL13

GPIO_20_PWRCNTL_1

AJ14

GPIO_21

AK13

GPIO_22_ROMCSB

AN13

CLKREQB

AG32

GPIO_29

AG33

GPIO_30

AJ19

GENERICA

AK19

GENERICB

AJ20

GENERICC

AK20

GENERICD

AJ24

GENERICE_HPD4

AH26

GENERICF_HPD5

AH24

GENERICG_HPD6

AC30

CEC_1

AK24

HPD1

AH13

DBG_VREFG

AL21

PX_EN

AD28

TESTEN

AM23

JTAG_TRSTB

AN23

JTAG_TDI

AK23

JTAG_TCK

AL24

JTAG_TMS

AM24

JTAG_TDO

THERMAL

AF29

DPLUS

AG29

DMINUS

AK32

GPIO_28_FDO

AL31

TS_A

AJ32

TSVDD

AJ33

TSVSS

SUNR1@

0.1U_0402_16V4Z

DEBUG

DPA

DPB

DPC

DPD

SMBus

I2C

DAC1

MLPS

BACO

DDC/AUX

DDCVGACLK

DDCVGADATA

SUN-PRO M2_FCBGA962

AVSSN

AVSSN HSYNC

VSYNC

AVSSQ VDD1DI

VSS1DI

NC_SVI2 NC_SVI2 NC_SVI2

DDC1CLK

DDC1DATA

AUX1P AUX1N

DDC2CLK

DDC2DATA

AUX2P AUX2N

B

C

D

E

MLPS

AU24

NC

AV23

NC

AT25

NC

AR24

NC

AU26

NC

AV25

NC

AT27

NC

AR26

NC

AR30

NC

AT29

NC

AV31

NC

AU30

NC

AR32

NC

AT31

NC

AT33

NC

AU32

NC

AU14

NC

AV13

NC

AT15

NC

AR14

NC

AU16

NC

AV15

NC

AT17

NC

AR16

NC

AU20

NC

AT19

NC

AT21

NC

AR20

NC

AU22

NC

AV21

NC

AT23

NC

AR22

NC

AD39

R

AD37 AE36

G

AD35 AF37

B

AE38 AC36

AC38

AB34

RSET

AD34

AVDD

AE34 AC33

AC34

V13

NC

U13

NC

AF33

NC

AF32

NC

AA29

NC

AG21

NC

AC32

NC

AC31 AD30 AD32

AM34

PS_0

AD31

PS_1

AG31

PS_2

AD33

PS_3

AM26 AN26

AM27 AL27

AM19 AL19

AN20 AM20

AL30

NC

AM30

NC

AL29

NC

AM29

NC

AN21

NC

AM21

NC

AK30

NC

AK29

NC

AJ30 AJ31

B

Mars MLPS configuration

Bits[5:1]

xx000 xx001 xx010 xx011 xx100 xx101 xx110 xx111 00xxx 01xxx 10xxx 11xxx

Pin Name

GPIO_0

GPIO_5_AC_BATT

GPIO_6 GPIO_15_PWRCNTL_0 GPIO_20_PWRCNTL_1 GPIO_29 GPIO_30

GPIO_8_ROMSO

GPIO_9_ROMSI

GPIO_10_ROMSCK

GPIO_22_ROMCSB

GPIO_17_THERMAL_INT

GPIO_19_CTF

GPIO_21

GPIO_28_FDO

CLKREQB

PX_EN

PD(1%) CapPU(1%)

NC 4.75k

8.45k 2.00k

4.53k 2.00k

6.98k 4.99k

4.53k 4.99k

3.24k 5.62k

3.40k 10.0k

4.75k NC

Type PD/PU Description

I/O

3.3 V (VDDR3)

I/O

3.3 V (VDDR3)

I/O

3.3 V (VDDR3)

I

3.3 V (VDDR3)

O

3.3 V (VDDR3)

I/O

3.3 V (VDDR3)

O

3.3 V (VDDR3)

I/O

3.3 V (VDDR3)

I/O

3.3 V (VDDR3)

O

O PD

Primary Memory Aperture Size Requested at PCI Configuration

Size of the Primary Memory Apertures

ROM_CONFIG [2:0]

128 MB

256 MB

64 MB

Reserved

512 MB

680nF 82nF 10nF NC

PD-reset

1 GB

2 GB

4 GB Not supported

Power-state indicator. Permits the voltage regulator to activate power-saving features. IF VR Suport PSI# and DPRSLPVR PU 10K to +3VGS. PSI# :Low load current flag DPRSLPVR : Deeper sleep enable flag

(Optional) An input which allows the system to request a fastpower reduction by setting GPIO_5_AC_BATT to low (0 V). The resulting state transition may disturb the display momentarily. Power reductions that are less time critical should use the standard software methods in order to prevent display disturbances.

Voltage control signals for the core (VDDC and VDDCI). At reset, these signals will be inputs with weak internal pulldown resistors. The VBIOS can define all voltage-control signals to be either 3.3-V or open-drain outputs (all signals must be the same type). The output states (high/low) of these pins are programmable for each AMD PowerPlay state when they are used as voltage control signals. Note: GPIO_29 and GPIO_30 are only available on 28-nm ASICs, and are NC on earlier generation ASICs.

Serial-ROM output from ROM. General purpose I/O or open-drain output.

Design: No use external VGA ROM, so use the test point.

Serial-ROM input to ROM. General purpose I/O or open-drain output.

Serial-ROM clock to ROM. General purpose I/O or open-drain output.

BIOS-ROM chip select. Used to enable the ROM for ROM read and program operations.

Design: No use external VGA ROM, so use the test

oints.

p

Thermal monitor interrupt. An input from an external temperature sensor (ALERTb).

Critical temperature fault (CTF) (active high) will output 3.3 V if the on-die temperature sensor exceeds a critical temperature so that the motherboard can protect the ASIC from damage by removing power. The CTF setpoint is 109 by default, and is programmed during ASIC initialization. See the advisory for AMD PowerPlay states for more details.

(Optional) Voltage control signal for the memory-voltage regulator. Note: This signal must be low (0 V) at reset (failure to do so will prevent booting).

Disable MLPS: PU 10K ohm to 3.3V. (Do not install for Mars) Enable MLPS: PD 10K ohm to GND. (Install for Mars)

Supports the CLKREQB feature for saving power to turn on/off the REFCLK clock on the ASIC.

On/off regulator switch in AMD PowerXpress? (switchable graphics) BACO mode. High (3.3 V) switches the regulators off (enter BACO mode). Low (0 V) switches the regulators on. (Default) PX_EN is tri-state before internal TEST_PG is asserted and PERSTb is deasserted.

Not supported

℃℃℃℃

C

000

001

010

011

MLPS Bit Strap Name Description Settings

ROM_CONFIG[0]

PS_0[1]

ROM_CONFIG[1]

PS_0[2]

ROM_CONFIG[2]

PS_0[3]

PS_0[4] N/A

STRAP_BIF_

PS_1[1]

GEN3_EN_A

PS_1[2] STRAP_BIF_

CLK_PM_EN

PS_1[3] N/A Reserved for internal use only. Must be 0 at reset.

PS_1[4] TX_PWRS_ENB

PS_1[5] TX_DEEMPH_EN

PS_2[1]

N/A

PS_2[2]

N/A

PS_2[3] BIOS_ROM_EN

PS_2[4] BIF_VGA_DIS

PS_2[5] N/A Reserved.

PS_3[1]

BOARD_CONFIG[0]

PS_3[2]

BOARD_CONFIG[1]

PS_3[3]

BOARD_CONFIG[2]

PS_0[5]

AUD_PORT_CONN_

PS_3[4]

PINSTRAP[0]

PS_3[5]

AUD_PORT_CONN_ PINSTRAP[1]

AUD_PORT_CONN_ PINSTRAP[2]

For MEMCLK 1GHZ Brand Description Comment PS_3[3:1] R_pu (ohm) R_pd (ohm)

For MEMCLK 900MHZ Brand Description Comment PS_3[3:1] R_pu (ohm) R_pd (ohm)

MLPS Strap

1 1

PS_0[5:1]

1 1

PS_1[5:1]

0 0

PS_2[5:1]

1 1

PS_3[5:1]

PS_0 PS_1 PS_2 PS_3

VGA@

@

1

CV22

CV21

CV20

2

0.68U_0402_10V6K

0.01U_0402_16V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFEREDFROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFEREDFROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

ANDTRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFEREDFROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENTEXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC.NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC.NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENTEXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC.NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUTPRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAYBE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUTPRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Legacy

GPIO[13:11]

GENLK_VSYNC

GPIO_2

GPIO_8

If BIOS_ROM_EN = 1, ROM_CONFIG[2:0] define the ROM type. If BIOS_ROM_EN = 0, ROM_CONFIG[2:0] define the primary memory-aperture size. Refer to current databooks for details.

Reserved for internal use only. Must be 1 at reset.

Re-defined strap to indicate PCIe GEN3 capability. 1 = PCIe GEN3 supported. 0 = PCIe GEN3 not supported.

Determines whether or not the PCIe reference clock power management capability is reported in the PCI configuration space (otherwise known as CLKREQB). 0 = The CLKREQB power management capability is disabled 1 = The CLKREQB power management capability is enabled

GENLK_CLK

GPIO_0

GPIO_1

N/A

GPIO_22

GPIO_9

Transmitter (Tx) power savings enable. 0 = 50% Tx output swing. 1 = Full Tx output swing.

PCI EXPRESS transmitter, deemphasis enable. 0 = Tx deemphasis disabled. 1 = Tx deemphasis enabled.

Reserved.

To enable the external BIOS ROM device. 0 = Disable the external BIOS ROM device. 1 = Enable the external BIOS ROM device.

VGA disable determines whether or not the card will be recognized as the system's VGA controller. 0 = VGA controller capacity enabled. 1 = The device will not be recognized as the system’s VGA controller.

N/A

gDDR3-2Gbit

Board configuration related strapping (such as memory ID).

Together with PS_0[5] form the three-bit strap option to indicate the number of audio-capable display outputs. In a given ASIC there are as many endpoints as there are digital display outputs, though not all outputs are audio capable. 111 = No usable endpoints. 110 = One usable endpoint. 101 = Two usable endpoints. 100 = Three usable endpoints. 011 = Four usable endpoints. 010 = Five usable endpoints. 001 = Six usable endpoints. 000 = All endpoints are usable.

skHynix

H5TQ2G63DFR-N0C

Samsung

K4W2G1646E-BC1A

skHynix

H5TQ2G63DFR-11C

Micron

MT41K128M16JT-107G:K

Samsung K4W2G1646E-BC11 1.5V/900MHz 111 4750 NC

CapacitorBits[5:4]

Bits[3:1]

0 0 1

0 0 0

X X X

Mapping to VRAM type please refer to page 6

@

1

CV23

2

0.01U_0402_16V7K

R_pu R_pd

NC

8.45K 2K

NC

8.45K

680 nF

NC

@

RV20

8.45K_0402_1%

@

1

RV27

2K_0402_1%

2

0.01U_0402_16V7K

2013/03/20 2014/03/20

D

2K

NC

4.75K

X

12

@

RV21

8.45K_0402_1%

12

VGA@

RV28

4.75K_0402_1%

Compal Secret Data

Deciphered Date

12

8.45K_0402_1%

12

4.75K_0402_1%

@

RV22

VGA@

RV68

12

8.45K_0402_1%

12

2K_0402_1%

1.5V/1GHz

1.5V/900MHz

1.35V-1.5V/900MHz

+1.8VGS

12

VGA@

RV23

12

VGA@

RV30

000

111

VGA_SMB_CK2

VGA_SMB_DA2

NC

4750

000

001

DMN66D0LDW-7 2N_SOT363-6

Title

Size Document Number Rev

Custom

Date: Sheet of

Date: Sheet

NC

8450

+3VGS

2

VGA@

61

QV1A

4

DMN66D0LDW-7 2N_SOT363-6

Compal Electronics, Inc.

Main_MSIC

LA-9869P

E

001

1

0

1

0

Base on

RAM ID

V

111

4750

2000

VGA@QV1B

VGA@

EC_SMB_CK2

3

EC_SMB_DA2

1.0

of

13 51Wednesday, March 20, 2013

5

QV1B

A

MPLL_PVDD MarsCRB Design

1 1

2 2

220ohm 1 1

0.1u 1 1 1u 1 1

2.2u 1 1

SPLL_PVDD MarsCRB Design 120ohm 1 1

0.1u 1 1 1u 1 1

2.2u 1 1

SPLL_VDDC MarsCRB Design 120ohm 1 1

0.1u 1 1 1u 1 1

2.2u 1 1

+1.8VGS

1 2

BLM15BD121SN1D_0402

+1.8VGS

1 2

BLM15BD121SN1D_0402

+0.95VGS

1 2

BLM15BD121SN1D_0402

B

+MPV18

LV7

VGA@LV7

VGA@

LV8

VGA@LV8

VGA@

LV9

VGA@LV9

VGA@

(MPLL_PVDD:1.8V@130mA )

1

CV79

CV78

2

1U_0402_6.3V6K

0.1U_0402_16V7K

VGA@ CV79

VGA@

VGA@ CV78

VGA@

2.2U_0402_6.3V6M

+SPV18

(SPLL_PVDD:1.8V@75mA )

1

CV82

CV81

2

1U_0402_6.3V6K

0.1U_0402_16V7K

VGA@ CV81

VGA@

VGA@ CV82

VGA@

2.2U_0402_6.3V6M

+SPLL_VDDC

(SPLL_VDDC:0.95V@100mA )

1

CV92

CV93

2

1U_0402_6.3V6K

0.1U_0402_16V7K

VGA@ CV92

VGA@

VGA@ CV93

VGA@

2.2U_0402_6.3V6M

1

CV80

2

VGA@ CV80

VGA@

1

CV83

2

VGA@ CV83

VGA@

1

CV94

2

VGA@ CV94

VGA@

+MPV18

+SPV18

+SPLL_VDDC

C

AM10

AN9

AN10

AF30 AF31

H7 H8

UV1C

MPLL_PVDD MPLL_PVDD

SPLL_PVDD

SPLL_VDDC

SPLL_PVSS

NC_XTAL_PVDD NC_XTAL_PVSS

SUNR1@

PART 9 0F 9

PLLS/XTAL

SUN-PRO M2_FCBGA962

XTALIN

XTALOUT

XO_IN

XO_IN2

CLKTESTA CLKTESTB

D

AV33

VGA_X1

AU34

XTALOUT

AW34

AW35

AK10

Debug Only, for clock observation

AL10

As short as possible

VGA_X1

CV24

15P_0402_50V8J

NOGCLK@

1 2

RV31 1M_0402_5%

YV1

4

NC

OSC

1

2

1

VGA_X1

OSC

NOGCLK@

NC

27MHZ 10PF +-20PPM X3G027000DA1H

E

3

XTALOUT

2

CV25

CV25 15P_0402_50V8J

15P_0402_50V8J

1

NOGCLK@

+1.5V to +1.5VGS

RV45

VGA@

QV188

+5VALW

VGA@

B+

5

12

RV5530

100K_0402_5%

VGA@

13

D

2N7002KW_SOT323-3

VGA@

S

B

470_0805_5%

1 2 3

VGA@

QV8B

QV8B 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

4

1 2

RV48

220K_0402_5%

61

VGA@

2

VGA_PWRGD#

VGA@

QV8A

2N7002DW-T/R7_SOT363-6

VGA_PWRGD#

2

G

+3VGS

VGA@

RV43

470_0805_5%

1 2 3

VGA@

QV9B

PXS_PWREN

QV9B

4

PXS_PWREN

D

2N7002DW-T/R7_SOT363-6

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2013/03/20 2014/03/20

Compal Secret Data

Deciphered Date

100K_0402_5%

5

PXS_PWREN#

VGA@

RV44

VGA@

QV9A

A

+1.5V

VGA@

QV3

8

D

7

D

6

D

5

D

FDS6676AS_SO8

3 3

4 4

+1.5VGS

Vgs=10V,Id=14.5A,Rds=6mohm

1

S

2

S

3

S

4

G

1

12

RV49

CV106

2

VGA@ RV49

VGA@

VGA@ CV106

VGA@

0.1U_0402_25V6

820K_0402_5%

VGA_PWRGD

+3VS to +3VGS

+3VALW

@

2

CV103

0.1U_0402_16V7K

VGA@

RV46

1 2

47K_0402_5%

1 2

61

2

2N7002DW-T/R7_SOT363-6

Date: Sheet of

0.1U_0402_16V7K

1

2

CV104

1

VGA@ CV104

VGA@

0.01U_0402_25V7K

Title

Size Document Number Rev

Custom

G

2

QV4

VGA@

Compal Electronics, Inc.

BACO POWER

LA-9869P

+3VS

Vgs=-4.5V,Id=3A,Rds<97mohm

S

D

1 3

AO3413_SOT23

E

+3VGS

14 51Wednesday, March 20, 2013

1.0

A

B

C

D

E

VDDR1 MarsCRB Design

0.01u 5 0

0.1u 5 0

2.2u 5 5 10u 3 3

VDD_CT MarsCRB Design 120ohm 1 1

1 1

0.1u 1 1 1u 1 1 10u 1 1

VDDR3 Mars check list Design 120ohm 1 1 1u 3 2 10u 1 0

0.1u 0 1

+1.8VGS +VDDC_CT

BLM15BD121SN1D_0402

2 2

3 3

+3VGS

BLM15BD121SN1D_0402

LV4

VGA@LV4

VGA@

1 2

LV5

VGA@LV5

VGA@

1 2

+1.5VGS

10U_0603_6.3V6M

1

CV34

CV33

2

10U_0603_6.3V6M

VGA@ CV34

10U_0603_6.3V6M

VGA@

VGA@ CV33

VGA@

1

CV51

2

10U_0603_6.3V6M

VGA@ CV51

10U_0603_6.3V6M

VGA@

+VDDR3

1

CV42

2

1U_0402_6.3V6K

VGA@ CV42

VGA@

(VDDR1:1.5V@1.5A)

1

CV36

CV37

CV35

2

VGA@ CV36

VGA@

VGA@ CV37

VGA@

10U_0603_6.3V6M

VGA@ CV35

10U_0603_6.3V6M

VGA@

2.2U_0402_6.3V6M

(VDD_CT:1.8V@13mA )

1

CV52

CV53

2

1U_0402_6.3V6K

0.1U_0402_16V7K

VGA@ CV52

VGA@

VGA@ CV53

VGA@

(VDDR3:3.3V@25mA)

1

CV55

CV54

2

1U_0402_6.3V6K

0.1U_0402_16V7K

VGA@ CV55

VGA@

VGA@ CV54

VGA@

+1.5VGS

1

CV38

CV40

CV39

2

VGA@ CV38

VGA@

VGA@ CV40

VGA@

VGA@ CV39

VGA@

2.2U_0402_6.3V6M

+VDDC_CT

+VDDR3

Route as differential pair

VCC_GPU_SENSE

TV44TV44

VSS_GPU_SENSE

AD11 AG10

AF26 AF27 AG26 AG27

AF23 AF24 AG23 AG24

AD12 AF11 AF12 AF13

AF15 AG11 AG13 AG15

AF28

AG28

AH29

AC7

AF7 AJ7

AK8 AL9 G11 G14 G17 G20 G23 G26 G29 H10

K11 K13

L12 L16 L21 L23 L26

M11 N11

R11 U11

Y11

J7 J9

K8

L7

P7

U7 Y7

UV1E

MEM I/O

VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1 VDDR1

LEVEL

TRANSLATION

VDD_CT VDD_CT VDD_CT VDD_CT

I/O

VDDR3 VDDR3 VDDR3 VDDR3

DVP

VDDR4 VDDR4 VDDR4 VDDR4

VOLTAGE

VOLTAGE SENESE

SENESE

FB_VDDC

FB_VDDCI

FB_GND

SUNR1@

PART 5 0F 9

NC NC NC NC NC

NC NC_BIF_VDDC NC_BIF_VDDC

PCIE_PVDD

PCIE

PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC PCIE_VDDC

BIF_VDDC

BACO

BIF_VDDC

CORE

VDDCI

CORE I/O

ISOLATED

VDDCI

SUN-PRO M2_FCBGA962

VDDCI

VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC

VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC VDDC

AA31 AA32 AA33 AA34 W30 Y31 V28 W29 AB37

G30 G31 H29 H30 J29 J30 L28 M28 N28 R28 T28 U28

N27 T27

AA15 AA17 AA20 AA22 AA24 AA27 AB16 AB18 AB21 AB23 AB26 AB28 AC17 AC20 AC22 AC24 AC27 AD18 AD21 AD23 AD26 AF17 AF20 AF22 AG16 AG18

AH22 AH27 AH28 M26 N24 R18 R21 R23 R26 T17 T20 T22 T24 U16 U18 U21 U23 U26 V17 V20 V22 V24 V27 Y16 Y18 Y21 Y23 Y26 Y28

AA13 AB13 AC12 AC15 AD13 AD16 M15 M16 M18 M23 N13 N15 N17 N20 N22 R12 R13 R16 T12 T15 V15 Y13

(PCIE_PVDD: 1.80V@100mA)

+1.8VGS

1

CV30

2

1U_0402_6.3V6K

VGA@ CV30

VGA@

+0.95VGS

1

CV43

2

1U_0402_6.3V6K

VGA@ CV43

VGA@

(BIF_VDDC: 0.95V@1.4A)

+0.95VGS

1

CV67

2

@ CV67

@

1U_0402_6.3V6K

+VGA_CORE

1

CV31

2

1U_0402_6.3V6K

VGA@ CV31

VGA@

10U_0603_6.3V6M

1

CV44

2

1U_0402_6.3V6K

VGA@ CV44

VGA@

1

CV68

2

@ CV68

@

1U_0402_6.3V6K

10U_0603_6.3V6M

Maximum Current on +1.8VGS:

1

"Sun": ~0.5 A

CV32

2

VGA@ CV32

VGA@

PCIE_VDDC:

0.95 V @ 1.88 A (PCIe Gen 2.0)

0.95 V @ 2.50 A (PCIe Gen 3.0)

1

CV46

CV45

CV41

2

1U_0402_6.3V6K

VGA@ CV46

VGA@

VGA@ CV45

VGA@

VGA@ CV41

VGA@

Maximum Current on +0.95VGS:

1

CV69

"Sun": ~4.0 A for PCIe GEN 3.0 designs (estimated)

2

@ CV69

@

1U_0402_6.3V6K

1

CV47

2

VGA@ CV47

VGA@

+0.95VGS

+1.8VGS

+0.95VGS

1

CV50

CV49

CV48

2

1U_0402_6.3V6K

10U_0603_6.3V6M

VGA@ CV50

VGA@

VGA@ CV49

VGA@

VGA@ CV48

VGA@

PCIE_PVDD MarsCRB Design 1u 2 2 10u 1 1

PCIE_VDDC MarsCRB Design 1u 7 7 10u 2 2

BIF_VDDC Mars check list Design 1u 1 1 10u 1 1

+VGA_CORE

Need check all power current and decoupling capacitors

4 4

A

after got SUN databook and reference schematic.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVI SION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVI SION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVI SION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAI NS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAI NS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAI NS MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF C OMPAL ELECTRONICS, I NC.

MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF C OMPAL ELECTRONICS, I NC.

B

MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF C OMPAL ELECTRONICS, I NC.

C

2013/03/20 2014/03/20

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

Power

LA-9869P

E

15 51Wednesday, March 20, 2013

of

1.0

A

UV1H

PART 3 0F 9

PART 3 0F 9 GDDR5/DDR3

DQA0_0 DQA0_1 DQA0_2 DQA0_3 DQA0_4 DQA0_5 DQA0_6 DQA0_7 DQA0_8 DQA0_9 DQA0_10 DQA0_11 DQA0_12 DQA0_13 DQA0_14 DQA0_15 DQA0_16 DQA0_17 DQA0_18 DQA0_19 DQA0_20 DQA0_21 DQA0_22 DQA0_23 DQA0_24 DQA0_25 DQA0_26 DQA0_27 DQA0_28 DQA0_29 DQA0_30 DQA0_31 DQA1_0 DQA1_1 DQA1_2 DQA1_3 DQA1_4 DQA1_5 DQA1_6 DQA1_7 DQA1_8 DQA1_9 DQA1_10 DQA1_11 DQA1_12 DQA1_13 DQA1_14 DQA1_15 DQA1_16 DQA1_17 DQA1_18 DQA1_19 DQA1_20 DQA1_21 DQA1_22 DQA1_23 DQA1_24 DQA1_25 DQA1_26 DQA1_27 DQA1_28 DQA1_29 DQA1_30 DQA1_31

MVREFDA MVREFSA

NC NC NC

MEM_CALRP0 NC

NC

SUNR1@

GDDR5/DDR3

MEMORY INTERFACE A

SUN-PRO M2_FCBGA962

Compal P/N

SA00003YOG0

SA000065320

SA00005XB10

SA00005SH40

SA000068U20

MAA0_0/MAA_0 MAA0_1/MAA_1 MAA0_2/MAA_2 MAA0_3/MAA_3 MAA0_4/MAA_4 MAA0_5/MAA_5 MAA0_6/MAA_6 MAA0_7/MAA_7 MAA1_0/MAA_8

MAA1_1/MAA_9 MAA1_2/MAA_10 MAA1_3/MAA_11 MAA1_4/MAA_12

MAA1_5/MAA_BA2 MAA1_6/MAA_BA0 MAA1_7/MAA_BA1

WCKA0_0/DQMA_0

WCKA0B_0/DQMA_1

WCKA0_1/DQMA_2

WCKA0B_1/DQMA_3

WCKA1_0/DQMA_4

WCKA1B_0/DQMA_5

WCKA1_1/DQMA_6

WCKA1B_1/DQMA_7

EDCA0_0/QSA_0 EDCA0_1/QSA_1 EDCA0_2/QSA_2 EDCA0_3/QSA_3 EDCA1_0/QSA_4 EDCA1_1/QSA_5 EDCA1_2/QSA_6 EDCA1_3/QSA_7

DDBIA0_0/QSA_0B DDBIA0_1/QSA_1B DDBIA0_2/QSA_2B DDBIA0_3/QSA_3B DDBIA1_0/QSA_4B DDBIA1_1/QSA_5B DDBIA1_2/QSA_6B DDBIA1_3/QSA_7B

ADBIA0/ODTA0

ADBIA1/ODTA1

CLKA0B

CLKA1B RASA0B

RASA1B CASA0B

CASA1B

CSA0B_0 CSA0B_1

CSA1B_0 CSA1B_1

CKEA0 CKEA1

WEA0B WEA1B

MAA0_8/MAA_13 MAA1_8/MAA_14 MAA0_9/MAA_15

MAA1_9/RSVD

C37 C35

A35

E34 G32 D33

F32

E32 D31

F30 C30

A30

1 1

2 2

1 2

RV34 120_0402_1%VGA@RV34 120_0402_1%VGA@

3 3

GPU Type

SUN PRO-M2

Memory Bus Width

64bit

F28 C28

A28

E28 D27

F26 C26

A26

F24 C24

A24

E24 C22

A22

F22 D21

A20

F20 D19

E18 C18

A18

F18 D17

A16

F16 D15

E14

F14 D13

F12

A12 D11

F10

A10 C10 G13 H13

J13 H11 G10

G8

K9

K10

G9

A8

C8

E8 A6

C6

E6 A5

L18

L20

L27 N12

AG12

M27 M12

AH12

VRAM Vendor

Hynix

Micron

Samsung

B

G24 J23 H24 J24 H26 J26 H21 G21 H19 H20 L13 G16 J16 H16 J17 H17

A32 C32 D23 E22 C14 A14 E10 D9

C34 D29 D25 E20 E16 E12 J10 D7

A34 E30 E26 C20 C16 C12 J11 F8

J21 G19

H27

CLKA0

G27 J14

CLKA1

H14 K23

K19 K20

K17 K24

K27 M13

K16 K21

J20 K26

L15

H23 J19 M21 M20

Manufacturer P/N

H5TQ2G63DFR-11C

H5TQ2G63DFR-N0C

MT41K128M16JT-107G:K

K4W2G1646E-BC11

K4W2G1646E-BC1A

Close to pin Y12 and AA12

40.2_0402_1%

100_0402_1%

ZZZ2

S1G

S1G@

X76xxxxxLx1

X76 P/N

X7648051L01

X7648051L02

X7648051L03

X7648051L04

X7648051L05

C

MDB[0..63]

+1.5VGS

RV72

VGA@

RV73

VGA@

ZZZ3

H1G@

X76xxxxxLx2

H1G

MDB[0..63]

12

15mil

+MVREFDB_SB

12

1

CV159

CV159 1U_0402_6.3V6K

1U_0402_6.3V6K

VGA@

2

ZZZ5

S2G

S2G@

ZZZ5

H2G

H2G@

X76xxxxxLx4

ZZZ4

X76xxxxxLx3

Size per part Configuration Total Memory Size/Qty

2Gbit 128M*16

1GB/4pcs

2Gbit 128M*16 1GB/4pcs

2Gbit

128M*16

1GB/4pcs

+MVREFDB_SB

0 0

0 1

1

UV1I

PART 4 0F 9

GDDR5/DDR3

DQB0_0 DQB0_1 DQB0_2 DQB0_3 DQB0_4 DQB0_5 DQB0_6 DQB0_7 DQB0_8 DQB0_9 DQB0_10 DQB0_11 DQB0_12 DQB0_13 DQB0_14 DQB0_15 DQB0_16 DQB0_17 DQB0_18 DQB0_19 DQB0_20 DQB0_21 DQB0_22 DQB0_23 DQB0_24 DQB0_25 DQB0_26 DQB0_27 DQB0_28 DQB0_29 DQB0_30 DQB0_31 DQB1_0 DQB1_1 DQB1_2 DQB1_3 DQB1_4 DQB1_5 DQB1_6 DQB1_7 DQB1_8 DQB1_9 DQB1_10 DQB1_11 DQB1_12 DQB1_13 DQB1_14 DQB1_15 DQB1_16 DQB1_17 DQB1_18 DQB1_19 DQB1_20 DQB1_21 DQB1_22 DQB1_23 DQB1_24 DQB1_25 DQB1_26 DQB1_27 DQB1_28 DQB1_29 DQB1_30 DQB1_31

MVREFDB MVREFSB

SUNR1@

GDDR5/DDR3

C5

MDB0

C3

MDB1

E3

MDB2

E1

MDB3

F1

MDB4

F3

MDB5

F5

MDB6

G4

MDB7

H5

MDB8

H6

MDB9

J4

MDB10

K6

MDB11

K5

MDB12

L4

MDB13

M6

MDB14

M1

MDB15

M3

MDB16

M5

MDB17

N4

MDB18

P6

MDB19

P5

MDB20

R4

MDB21

T6

MDB22

T1

MDB23

U4

MDB24

V6

MDB25

V1

MDB26

V3

MDB27

Y6

MDB28

Y1

MDB29

Y3

MDB30

Y5

MDB31

AA4

MDB32

AB6

MDB33

AB1

MDB34

AB3

MDB35

AD6

MDB36

AD1

MDB37

AD3

MDB38

AD5

MDB39

AF1

MDB40

AF3

MDB41

AF6

MDB42

AG4

MDB43

AH5

MDB44

AH6

MDB45

AJ4

MDB46

AK3

MDB47

AF8

MDB48

AF9

MDB49

AG8

MDB50

AG7

MDB51

AK9

MDB52

AL7

MDB53

AM8

MDB54

AM7

MDB55

AK1

MDB56

AL4

MDB57

AM6

MDB58

AM1

MDB59

AN4

MDB60

AP3

MDB61

AP1

MDB62

AP5

MDB63

Y12

AA12

R_pu & R_pd resistor: 0

402 1% resistors are required.

PS_3[ 1]PS_3[ 2 ]PS_3[ 3 ]

0

00

1

0

D

MAB0_0/MAB_0 MAB0_1/MAB_1 MAB0_2/MAB_2 MAB0_3/MAB_3 MAB0_4/MAB_4 MAB0_5/MAB_5 MAB0_6/MAB_6 MAB0_7/MAB_7 MAB1_0/MAB_8

MAB1_1/MAB_9 MAB1_2/MAB_10 MAB1_3/MAB_11 MAB1_4/MAB_12

MAB1_5/BA2 MAB1_6/BA0 MAB1_7/BA1

WCKB0_0/DQMB_0

WCKB0B_0/DQMB_1

WCKB0_1/DQMB_2

WCKB0B_1/DQMB_3

WCKB1_0/DQMB_4

WCKB1B_0/DQMB_5

WCKB1_1/DQMB_6

MEMORY INTERFACE B

WCKB1B_1/DQMB_7

EDCB0_0/QSB_0 EDCB0_1/QSB_1 EDCB0_2/QSB_2 EDCB0_3/QSB_3 EDCB1_0/QSB_4 EDCB1_1/QSB_5 EDCB1_2/QSB_6 EDCB1_3/QSB_7

DDBIB0_0/QSB_0B DDBIB0_1/QSB_1B DDBIB0_2/QSB_2B DDBIB0_3/QSB_3B DDBIB1_0/QSB_4B DDBIB1_1/QSB_5B DDBIB1_2/QSB_6B DDBIB1_3/QSB_7B

ADBIB0/ODTB0 ADBIB1/ODTB1

MAB0_8/MAB_13 MAB1_8/MAB_14 MAB0_9/MAB_15

MAB1_9/RSVD

DRAM_RST

SUN-PRO M2_FCBGA962

R_pu R_pd

RV20 RV27

NC 4.75K

RV20 RV27

4.53K

RV20 RV27

8.45K 2K

RV20 RV27

4.75K

RV27

RV20

3.4K

CLKB0

CLKB0B

CLKB1

CLKB1B RASB0B

RASB1B CASB0B

CASB1B

CSB0B_0 CSB0B_1

CSB1B_0 CSB1B_1

CKEB0 CKEB1

WEB0B WEB1B

2K

NC

10K

E

MAB[0..15]

B_BA2 B_BA0 B_BA1

ODTB0 ODTB1

CLKB0 CLKB0#

CLKB1 CLKB1#

RASB0# RASB1#

CASB0# CASB1#

CSB0#_0

CSB1#_0

CKEB0 CKEB1

WEB0# WEB1#

1 2

10_0402_1%

120P_0402_50V9

1 2

RV36

DQMB#[0..7] QSB[0..7]

QSB#[0..7]

VGA@RV36

VGA@

CV158

P8

MAB0

T9

MAB1

P9

MAB2

N7

MAB3

N8

MAB4

N9

MAB5

U9

MAB6

U8

MAB7

Y9

MAB8

W9

MAB9

AC8

MAB10

AC9

MAB11

AA7

MAB12

AA8

B_BA2

Y8

B_BA0

AA9

B_BA1

H3

DQMB#0

H1

DQMB#1

T3

DQMB#2

T5

DQMB#3

AE4

DQMB#4

AF5

DQMB#5

AK6

DQMB#6

AK5

DQMB#7

F6

QSB0

K3

QSB1

P3

QSB2

V5

QSB3

AB5

QSB4

AH1

QSB5

AJ9

QSB6

AM5

QSB7

G7

QSB#0

K1

QSB#1

P1

QSB#2

W4

QSB#3

AC4

QSB#4

AH3

QSB#5

AJ8

QSB#6

AM3

QSB#7

T7

ODTB0

W7

ODTB1

L9

CLKB0

L8

CLKB0#

AD8

CLKB1

AD7

CLKB1#

T10

RASB0#

Y10

RASB1#

W10

CASB0#

AA10

CASB1#

P10

CSB0#_0

L10 AD10

CSB1#_0

AC10 U10

CKEB0

AA11

CKEB1

N10

WEB0#

AB11

WEB1#

T8

MAB13

W8

MAB14

U12

MAB15

V12 AH11

DRAM_RST#_R

VGA@

RV71

4.99K_0402_1%

Place all these components close to GPU (Within 25mm) and keep all component close to each other

12

RV70

1 2

51.1_0402_1%

MAB[0..15] DQMB#[0..7] QSB[0..7] QSB#[0..7]

VGA@RV70

VGA@

DRAM_RST#

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF C OMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVI SION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVI SION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF T HE COMPETENT DIVI SION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAI NS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAI NS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATI ON IT CONTAI NS MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF C OMPAL ELECTRONICS, I NC.

MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF C OMPAL ELECTRONICS, I NC.

A

B

MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF C OMPAL ELECTRONICS, I NC.

C

2013/03/20 2014/03/20

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet of

Compal Electronics, Inc.

MEM Interface

LA-9869P

E

16 51Wednesday, March 20, 2013

1.0