Quanta Computer LA-9869P VDKTE Rosetta 10ADT, Satellite L40D, LA-9869P VDKTE Rosetta 10ADTG Schematic

A

1 1

B

C

D

E

VDKTE

2 2

Rosetta 10ADT/10ADTG

LA-9869P SchematicREV 0.3

AMD APU RICHLAND FP2 / FCH BOLTON-M3

3 3

4 4

Sun Pro M2

2013-02-04 Rev 0.3

Security Class ification

Security Class ification

Security Class ification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2013/01/ 22 2014/01/ 21

2013/01/ 22 2014/01/ 21

2013/01/ 22 2014/01/ 21

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

Cover Page

Cover Page

Cover Page

LA-9869P

LA-9869P

LA-9869P

1 50Monday, February 04, 20 13

1 50Monday, February 04, 20 13

1 50Monday, February 04, 20 13

E

0.3

0.3

0.3

A

e

DP Conn.

p

age 20

L

LVDS Conn.

p

1 1

age 20

VDS Translator

R

TD2132S

p

age 19

B

C

D

E

GCLK

D

P0 (X2)

AMD APU

P

WM Fan Control

p

age 5

SLG3NB283VTR (UMA)

G

CLK

SLG3NB302VTR (DIS)

p

age 29

p

age 29

FP2 Processor

P

G

PU

Sun Pro M2

page 12~18

H

DMI Conn

CI-Express X8 5GHz

D

P2 (X4)

Trinity BGA-813

2

7mm*31mm

p

age 5,6,7,8,9

M

emory BUS(DDRIII)

D

ual Channel

1

.5V DDRIII 1333/1600 MT/s

2

00pin DDRIII-SO-DIMM X2

B

ANK 0, 1, 2, 3

p

age 10,11

age 28

age 28

IC Conn

page 33

D

I

nt. Camera

U

SB port 1

p

R

ight USB 3.0

U

SB port 11

p

H

DA Codec

A

LC259/269

SPK ConnInt.

T

ouch screen

U

SB port 4

age 25

age 31

U

SB 3.0

U

SB 3.0

p

age 32

p

age 32

T

T

T

itle

itle

itle

B

B

B

lock Diagrams

lock Diagrams

lock Diagrams

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

p

age 25

USB3.0 port 0

p

age 31

U

SB3.0 port 1

p

age 31

J

CRIO

(HP & MIC)

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

L

L

L

A-9869P

A-9869P

A-9869P

p

age 32

E

2 50Monday, February 04, 2013

2 50Monday, February 04, 2013

2 50Monday, February 04, 2013

0

0

0

.3

.3

.3

o

o

o

f

f

f

L

p

age 27

2 2

R

J45

page 30

3 3

R

TC CKT.

D

C/DC Interface CKT.

4 4

P

ower Circuit DC/DC

page 38,39,40,41,42,43,
44,45,46,47,48,49

P

ower On/Off CKT.

p

age 19

p

age 37

A

LAN/USB board
LS-9861P

P

WR/B

LS-9862P

p

p

age 36page 36

age 30

C

RT

p

age 21

R

TL8106E 10/100M

A

PU PCIe port 0

C

ardreader Conn.

GL834L
2 in 1
MMC/SD

S

PI ROM

(4MB)

p

age 25

p

age 30

U

SB port 2

p

age 33

B

U

5

SB2.0

V 480MHz

S

PI Bus

3

.3V 33 MHz

P

CIe X1

1

.2V 5GT/s

T

ouch Pad

page 36

D

P1

(X4)

AMD FCH

U

MI X4

2

.5GT/s

Hudson M3

F

CBGA-656

24.5mm*24.5mm

page 23,24,25,26,27

L

PC Bus

3

.3V 33 MHz

E

NE KB9012

p

age 34

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

I

nt.KBD

page 35

HD Audio

P

CIe X1

1

.2V 5GT/s

U

SB2.0

5

V 480MHz

USB2.0

5

V 480MHz

S

ATA port 0

5

V 6GHz(600MB/s)

S

ATA port 1

5

V 6GHz(600MB/s)

USB 3.0

5GHz

U

SB 3.0

5

GHz

3

.3V 24MHz

C

C

C

ompal Secret Data

ompal Secret Data

2

2

2

013/01/22 2014/01/21

013/01/22 2014/01/21

013/01/22 2014/01/21

ompal Secret Data

eft USB2.0

U

SB port 0

p

R

ight USB 3.0

U

SB port 10

p

PCIeMini Card
WLAN + BT

U

SB port 3

APU PCIe port 1

p

age 28

S

ATA HDD

SATA port 0

S

ATA ODD

S

ATA port 1

D

D

D

eciphered Date

eciphered Date

eciphered Date

age 30

age 31

p

p

M

5

B

+

D D

I

peak=12A, Imax=8.4A, Iocp min=14A

S

USP

N

-CHANNEL

SI4800

4

D

ESIGN CURRENT 0 .15A

DESIGN CURRENT 0A

D

ESIGN CURRENT 4 A

+

5VALW

+

3VL

+5VL

+

5VS

3

2

1

RT8243A

Ipeak=8A, Imax=5.6A, Iocp min=10A

W

OL_EN#

D

P

-CHANNEL
A

S

USP

N

-CHANNEL

SI4800

C C

S

YSON

R

T8207M

B B

1

.1VPWR_EN

S

Y8208D

I

peak=12A, Imax=8.4A, Iocp min=13.8A

S

USP

N-CHANNEL

FDS6676AS

I

peak=5.3A, Imax=3.71A, Iocp min=16A

O-3413

L

P

-CHANNEL
A

O-3413

D

GPU_PWR_EN

P-CHANNEL

A

O-3413

V

GA_PWRGD

S

Y8032

A

PL5508

P

J1

S

USP#

F

DS6676

CD_ENVDD

ESIGN CURRENT 3 30mA

DESIGN CURRENT 4A

D

ESIGN CURRENT 1 .5A

D

ESIGN CURRENT 6 0mA

D

ESIGN CURRENT 0 .5A

D

ESIGN CURRENT 0 .75A

D

ESIGN CURRENT 2 A

DESIGN CURRENT 2A

D

ESIGN CURRENT 1 .5A

+

+

3V_LAN

+

LCD_VDD

+

3VS_DGPU

1

.8VGSP

2

.5VSP

+1.5V

+

1.5V_CPU

+

1.5VS

+

0.75VS

+

1.1VALWP

+

1.1VS

3VALW

+

3VS

V

R_ON

S

Y8208D

V

R_ON

I

I

5

SL6277

G

PU_DPRSLPVR

SL62881

A A

I

peak=7A, Imax=4.9A, Iocp min=16A

I

peak=36A, Imax=25.2A, Iocp min=60A

I

peak=30A, Imax=21A, Iocp min=50A

I

peak=21A, Imax=14.7A, Iocp min=40A

4

+

1.2VS

A

PU_CORE

A

PU_CORE_NB

V

GA_CORE

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL EL ECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETE NT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELE CTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WI THOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

013/01/22 2014/01/21

013/01/22 2014/01/21

013/01/22 2014/01/21

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

P

P

P

ower Tree

ower Tree

ower Tree

L

L

L

A-9869P

A-9869P

A-9869P

3

o

3

3

o

o

f

50Monday, February 04, 2013

f

50Monday, February 04, 2013

f

1

50Monday, February 04, 2013

0

0

0

.3

.3

.3

A

(

V

oltage Rails

1 1

State

p

ower

plane

O MEANS ON X MEANS OFF )

B

+RTCVCC

+

B

VL

+

3VL

+5VALW

+

3VALW

+1.5V

+5VS

+3VS

+2.5VS

+1.5VS

+1.2VS

+1.1VS

+

0.75VS

+

APU_CORE

+

APU_CORE_NB

+1.1VALW

C

B

TO Option Table

F

unction

description

explain

BTO

TO

3D sensor

G-sensor

GSENSOR@

F

unction

d

escription

explain

B

D

F

APU

R

1 R3

KB LED

KB LED

KBL@

R3

BOLTONR1@

Green Clock

GCLK@ NOGCLK@

CH

Bolton

R1

HUDM3R3@

Clock

No Green Clock

GPU

R1 R3

UMA/DIS

D

IS

V

GA@

UMA

UMA@

E

U1GK

S0

S1

2 2

3 3

4 4

S

3

S5 S4/AC

S

5 S4/ Battery only

S5 S4/AC & Battery
don't exist

F

CH SM Bus Address (SCL0/SDA0)

Power

+3VS

+3VS

+3VS

Power

+3VL

+3VL

+3VL

+3VS

+3VS VGA Thermal

Device

DDR SO-DIMM 0

DDR SO-DIMM 1

WLAN

E

C SM Bus1 Address

D

evice Address

Charger 12 H 0001 0010 b

E

C SM Bus2 Address

D

evicePower

SB-TSI

O

O

O

O

O

O

HEX

O

O

O

O

O

X

Address

1

1010 001X bA2 H

HEX

0

16 H

001 0110 bSmart Battery

HEX Address

9

8 H

1001 1001 b

4

0 H

0

8

100 0000 bG-Sensor

2H

1

000 0010 b

O

O

O

O

O

X

010 000X bA0 H

+

3VS

O

O

O

O

X

X

E

C SM Bus3 Address

O

X

X

X

H

EX AddressDevicePower

9

4 H

OO

OO

X

X

F

unction

description

explain

B

TO

P

anel

S D

LVDS eDP

L

VDS@ IEDP@

X

X

S

1

001 0100 bLVDS Translator

TATE

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

G

3 LOW LOW

SIGNAL

SLP_S3# SLP_S5#

HIGHHIGH

HIGH HIGH

LOW

HIGH

H

LOW

IGH

L

OWLOW

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2

2

2

013/01/22 2014/01/21

013/01/22 2014/01/21

013/01/22 2014/01/21

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

D

Date: Sheet

ompal Electronics, Inc.

N

N

N

otes List

otes List

otes List

L

L

L

A-9869P

A-9869P

A-9869P

E

4 50Monday, February 04, 2013

0

0

0

.3

.3

.3

o

o

o

f

4 50Monday, February 04, 2013

f

4 50Monday, February 04, 2013

f

A

B

C

D

E

P

CIE_GTX_C _ARX_P[0..3]<12>

P

CIE_GTX_C _ARX_N[0..3]<12>

APUA

APUA

U

U

P

CIE_GTX_C _ARX_P0

P

CIE_GTX_C _ARX_N0

P

CIE_GTX_C _ARX_P1

P

CIE_GTX_C _ARX_N1

P

1 1

2 2

LAN

WLAN

P

CIE_FRX_C _LANTX_P0<30>

P

CIE_FRX_C _LANTX_N0<30>

P

CIE_FRX_W LANTX_P1<28>

P

CIE_FRX_W LANTX_N1<28>

U

MI_MTX_C_ FRX_P0<23>

U

MI_MTX_C_ FRX_N0<23>

U

MI_MTX_C_ FRX_P1<23>

U

MI_MTX_C_ FRX_N1<23>

U

MI_MTX_C_ FRX_P2<23>

U

MI_MTX_C_ FRX_N2<23>

U

MI_MTX_C_ FRX_P3<23>

U

MI_MTX_C_ FRX_N3<23>

+

1.2VS

CIE_GTX_C _ARX_P2

P

CIE_GTX_C _ARX_N2

P

CIE_GTX_C _ARX_P3

P

CIE_GTX_C _ARX_N3

1 2

R

R

1 196_040 2_1%

1 196_040 2_1%

C

lose to AR11 Close to AP11

P

_ZVDDP

AP1

_GFX_RXP[0]

P

AP2

_GFX_RXN[0]

P

AM1

_GFX_RXP[1]

P

AM2

_GFX_RXN[1]

P

AK3

_GFX_RXP[2]

P

AK4

_GFX_RXN[2]

P

AJ1

_GFX_RXP[3]

P

AJ2

_GFX_RXN[3]

P

AH4

_GFX_RXP[4]

P

AH3

_GFX_RXN[4]

P

AF2

_GFX_RXP[5]

P

AF1

_GFX_RXN[5]

P

AD1

_GFX_RXP[6]

P

AD2

_GFX_RXN[6]

P

AB3

_GFX_RXP[7]

P

AB4

_GFX_RXN[7]

P

AA1

_GFX_RXP[8]

P

AA2

_GFX_RXN[8]

P

Y4

_GFX_RXP[9]

P

Y3

_GFX_RXN[9]

P

V2

_GFX_RXP[10]

P

V1

_GFX_RXN[10]

P

T1

_GFX_RXP[11]

P

T2

_GFX_RXN[11]

P

P3

_GFX_RXP[12]

P

P4

_GFX_RXN[12]

P

N1

_GFX_RXP[13]

P

N2

_GFX_RXN[13]

P

M4

_GFX_RXP[14]

P

M3

_GFX_RXN[14]

P

K2

_GFX_RXP[15]

P

K1

_GFX_RXN[15]

P

AH5

_GPP_RXP[0]

P

AH6

_GPP_RXN[0]

P

AG5

_GPP_RXP[1]

P

AG6

_GPP_RXN[1]

P

AE6

_GPP_RXP[2]

P

AE5

_GPP_RXN[2]

P

AD6

_GPP_RXP[3]

P

AD5

_GPP_RXN[3]

P

AM10

_UMI_RXP[0]

P

AN10

_UMI_RXN[0]

P

AN8

_UMI_RXP[1]

P

AM8

_UMI_RXN[1]

P

AP8

_UMI_RXP[2]

P

AR8

_UMI_RXN[2]

P

AR7

_UMI_RXP[3]

P

AP7

_UMI_RXN[3]

P

AR11

_ZVDDP

P

TRINITY-A8-SERIES_ BGA813

TRINITY-A8-SERIES_ BGA813

5745R1@

5745R1@

_GFX_TXP[0]

P

_GFX_TXN[0]

P

_GFX_TXP[1]

P

_GFX_TXN[1]

P

_GFX_TXP[2]

P

_GFX_TXN[2]

P

_GFX_TXP[3]

P

_GFX_TXN[3]

P

_GFX_TXP[4]

P

_GFX_TXN[4]

P

_GFX_TXP[5]

P

_GFX_TXN[5]

P

_GFX_TXP[6]

P

_GFX_TXN[6]

P

_GFX_TXP[7]

P

_GFX_TXN[7]

P

_GFX_TXP[8]

P

RAPHICSGPPUMI

RAPHICSGPPUMI
G

G

_GFX_TXN[8]

P

_GFX_TXP[9]

P

_GFX_TXN[9]

P
_GFX_TXP[10]

P

_GFX_TXN[10]

P

_GFX_TXP[11]

P

_GFX_TXN[11]

P

_GFX_TXP[12]

P

_GFX_TXN[12]

P

_GFX_TXP[13]

P

_GFX_TXN[13]

P

_GFX_TXP[14]

P

_GFX_TXN[14]

P

_GFX_TXP[15]

P

_GFX_TXN[15]

P

_GPP_TXP[0]

P

_GPP_TXN[0]

P

_GPP_TXP[1]

P

_GPP_TXN[1]

P

_GPP_TXP[2]

P

_GPP_TXN[2]

P

_GPP_TXP[3]

P

_GPP_TXN[3]

P

_UMI_TXP[0]

P

_UMI_TXN[0]

P

_UMI_TXP[1]

P

_UMI_TXN[1]

P

_UMI_TXP[2]

P

_UMI_TXN[2]

P

_UMI_TXP[3]

P

_UMI_TXN[3]

P

P

_ZVSS

AN1
AN2
AM4
AM3
AK2
AK1
AH1
AH2
AF3
AF4
AE1
AE2
AD4
AD3
AB2
AB1
Y1
Y2
V3
V4
U1
U2
T4
T3
P2
P1
M1
M2
K3
K4
J1
J2

AG7
AG8
AE7
AE8
AD7
AD8
AB6
AB5

AN6
AM6
AP6
AR6
AP4
AR4
AP3
AR3

AP11

P

CIE_ATX_G RX_P0

P

CIE_ATX_G RX_N0

P

CIE_ATX_G RX_P1

P

CIE_ATX_G RX_N1

P

CIE_ATX_G RX_P2

P

CIE_ATX_G RX_N2

P

CIE_ATX_G RX_P3

P

CIE_ATX_G RX_N3

P

CIE_FTX_L ANRX_P0

P

CIE_FTX_L ANRX_N0

P

CIE_FTX_W LANRX_P1

P

CIE_FTX_W LANRX_N1

U

MI_FTX_MR X_P0

U

MI_FTX_MR X_N0

U

MI_FTX_MR X_P1

U

MI_FTX_MR X_N1

U

MI_FTX_MR X_P2

U

MI_FTX_MR X_N2

U

MI_FTX_MR X_P3

U

MI_FTX_MR X_N3

1 2

P

_ZVSS

2 196_040 2_1%

2 196_040 2_1%

R

R

P

CIE_ATX_C _GRX_P[0..3] <12>

P

CIE_ATX_C _GRX_N[0..3] <12>

1 2

C

C

1 0.1U_040 2_16V7KVG A@

1 0.1U_040 2_16V7KVG A@

C

C

15 0.1U_0402_16V 7KVGA@

15 0.1U_0402_16V 7KVGA@

C

C

17 0.1U_0402_16V 7KVGA@

17 0.1U_0402_16V 7KVGA@

C

C

11 0.1U_0402_16V 7KVGA@

11 0.1U_0402_16V 7KVGA@
7 0.1U_040 2_16V7KVG A@

7 0.1U_040 2_16V7KVG A@

C

C
C

C

14 0.1U_0402_16V 7KVGA@

14 0.1U_0402_16V 7KVGA@
13 0.1U_0402_16V 7KVGA@

13 0.1U_0402_16V 7KVGA@

C

C

8 0.1U_040 2_16V7KVG A@

8 0.1U_040 2_16V7KVG A@

C

C

2

1

1 2

1 2
1 2
1 2
1 2

2

1

2

1

C

C

50 0.1U_040 2_16V7K

50 0.1U_040 2_16V7K

1 2

55 0.1U_040 2_16V7K

55 0.1U_040 2_16V7K

C

C

1 2

51 0.1U_040 2_16V7K

51 0.1U_040 2_16V7K

C

C

1 2

C

C

54 0.1U_040 2_16V7K

54 0.1U_040 2_16V7K

1 2

C

C

59 0.1U_040 2_16V7K

59 0.1U_040 2_16V7K

1 2

C

C

60 0.1U_040 2_16V7K

60 0.1U_040 2_16V7K

1 2

C

C

61 0.1U_040 2_16V7K

61 0.1U_040 2_16V7K

1 2

C

C

62 0.1U_040 2_16V7K

62 0.1U_040 2_16V7K

1 2

122 0.1U _0402_16V7K

122 0.1U _0402_16V7K

C

C

2

1

123 0.1U _0402_16V7K

123 0.1U _0402_16V7K

C

C

2

1

C

C

120 0.1U _0402_16V7K

120 0.1U _0402_16V7K

1 2

C

C

121 0.1U _0402_16V7K

121 0.1U _0402_16V7K

P

CIE_ATX_C _GRX_P0

P

CIE_ATX_C _GRX_N0

P

CIE_ATX_C _GRX_P1

P

CIE_ATX_C _GRX_N1

P

CIE_ATX_C _GRX_P2

P

CIE_ATX_C _GRX_N2

P

CIE_ATX_C _GRX_P3

P

CIE_ATX_C _GRX_N3

P

CIE_FTX_C _LANRX_P0 <30>

P

CIE_FTX_C _LANRX_N0 <30>

P

CIE_FTX_C _WLANRX_P 1 <28>

P

CIE_FTX_C _WLANRX_N 1 <28>

U

MI_FTX_C_ MRX_P0 <23>

U

MI_FTX_C_ MRX_N0 <23>

U

MI_FTX_C_ MRX_P1 <23>

U

MI_FTX_C_ MRX_N1 <23>

U

MI_FTX_C_ MRX_P2 <23>

U

MI_FTX_C_ MRX_N2 <23>

U

MI_FTX_C_ MRX_P3 <23>

U

MI_FTX_C_ MRX_N3 <23>

LAN

W

LAN

3 3

+

FAN1

D

3VS

12

R

R

6

6

10K_040 2_5%

10K_040 2_5%

1

C

C

4

4

0.01U_04 02_25V7K

0.01U_04 02_25V7K

@

@

2

J

J

FAN

FAN

6

G

6

5

G

5

4

4

5

5

C

C

3

3

2

2

1

1

ACES_50 273-0040N-001

ACES_50 273-0040N-001

@

@

1

@

@

6

6

C

C

2

1000P_0 402_50V7K

1000P_0 402_50V7K

E

o

o

o

f

5 50Monday, February 04, 20 13

f

5 50Monday, February 04, 20 13

f

5 50Monday, February 04, 20 13

F

ANPW M<34>

+

FAN1

1

1

1

D

D

BAS16_S OT23-3

BAS16_S OT23-3

T

T

T

itle

itle

itle

A

A

A

MD Trinity FP2 / GFX / UMI

MD Trinity FP2 / GFX / UMI

MD Trinity FP2 / GFX / UMI

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

C

C

C

ustom

ustom

ustom

L

L

L

A-9869P

A-9869P

A-9869P

Date: Sheet

Date: Sheet

Date: Sheet

1

2

2

10U_060 3_6.3V6M

10U_060 3_6.3V6M

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

0

0

0

.3

.3

.3

F

AN Control Circuit

F

AN_SPEE D1<34>

+

5VS

R

R

3

3

1

A

2

1

+

0_0603_ 5%

0_0603_ 5%

reserve 0ohm

4 4

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

2

2

2

013/01/2 2 2014/01/2 1

013/01/2 2 2014/01/2 1

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

013/01/2 2 2014/01/2 1

C

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

for Power consumption

eciphered D ate

eciphered D ate

eciphered D ate

A

DR_A_DQS[0..7]<10>

D

DR_A_DQS#[0..7]<10>

D

1 1

APUB

APUB

U

DR_A_MA[0..15]<10>

D

DR_A_BS0<10>

D

DR_A_BS1<10>

D

DR_A_BS2<10>

D

DR_A_DM[0..7]<10>

D

2 2

DR_A_CLK0<10>

D

DR_A_CLK0#<10>

D

DR_A_CLK1<10>

D

DR_A_CLK1#<10>

D

DR_A_CKE0<10>

D

DR_A_CKE1<10>

3 3

D

DR_A_ODT0<10>

D

DR_A_ODT1<10>

D

DR_A_SCS0#<10>

D

DR_A_SCS1#<10>

D

DR_A_RAS#<10>

D

DR_A_CAS#<10>

D

DR_A_WE#<10>

D

EM_MA_RST#<10>

M

EM_MA_EVENT#<10>

M

1.5V

+

D

DR_A_MA0

D

DR_A_MA1

D

DR_A_MA2

D

DR_A_MA3

D

DR_A_MA4

D

DR_A_MA5

D

DR_A_MA6

D

DR_A_MA7

D

DR_A_MA8

D

DR_A_MA9

D

DR_A_MA10

D

DR_A_MA11

D

DR_A_MA12

D

DR_A_MA13

D

DR_A_MA14

D

DR_A_MA15

D

DR_A_BS0

D

DR_A_BS1

D

DR_A_BS2

D

DR_A_DM0

D

DR_A_DM1

D

DR_A_DM2

D

DR_A_DM3

D

DR_A_DM4

D

DR_A_DM5

D

DR_A_DM6

D

DR_A_DM7

D

DR_A_DQS0

D

DR_A_DQS#0

D

DR_A_DQS1

D

DR_A_DQS#1

D

DR_A_DQS2

D

DR_A_DQS#2

D

DR_A_DQS3

D

DR_A_DQS#3

D

DR_A_DQS4

D

DR_A_DQS#4

D

DR_A_DQS5

D

DR_A_DQS#5

D

DR_A_DQS6

D

DR_A_DQS#6

D

DR_A_DQS7

D

DR_A_DQS#7

+

MEM_VREF

1 2

M

R

R

60 39.2_0402_1%

60 39.2_0402_1%

_ZVDDIO

C

lose to AJ32

U

AA28

A_ADD[0]

M

R29

A_ADD[1]

M

T30

A_ADD[2]

M

R28

A_ADD[3]

M

R26

A_ADD[4]

M

P26

A_ADD[5]

M

P27

A_ADD[6]

M

P30

A_ADD[7]

M

P29

A_ADD[8]

M

M28

A_ADD[9]

M

AB26

A_ADD[10]

M

M26

A_ADD[11]

M

M29

A_ADD[12]

M

AE27

A_ADD[13]

M

L26

A_ADD[14]

M

L27

A_ADD[15]

M

AB27

A_BANK[0]

M

AA29

A_BANK[1]

M

M30

A_BANK[2]

M

D16

A_DM[0]

M

D20

A_DM[1]

M

E25

A_DM[2]

M

F30

A_DM[3]

M

AK29

A_DM[4]

M

AL25

A_DM[5]

M

AM20

A_DM[6]

M

AM16

A_DM[7]

M

G17

A_DQS_H[0]

M

H17

A_DQS_L[0]

M

F22

A_DQS_H[1]

M

G22

A_DQS_L[1]

M

E26

A_DQS_H[2]

M

F26

A_DQS_L[2]

M

H30

A_DQS_H[3]

M

G30

A_DQS_L[3]

M

AL29

A_DQS_H[4]

M

AL30

A_DQS_L[4]

M

AH25

A_DQS_H[5]

M

AJ25

A_DQS_L[5]

M

AK20

A_DQS_H[6]

M

AL20

A_DQS_L[6]

M

AK15

A_DQS_H[7]

M

AL15

A_DQS_L[7]

M

W29

A_CLK_H[0]

M

Y30

A_CLK_L[0]

M

W26

A_CLK_H[1]

M

W27

A_CLK_L[1]

M

U29

A_CLK_H[2]

M

V30

A_CLK_L[2]

M

U26

A_CLK_H[3]

M

U27

A_CLK_L[3]

M

L29

A_CKE[0]

M

K30

A_CKE[1]

M

AD30

A0_ODT[0]

M

AG28

A0_ODT[1]

M

AE26

A1_ODT[0]

M

AG29

A1_ODT[1]

M

AD26

A0_CS_L[0]

M

AE29

A0_CS_L[1]

M

AB30

A1_CS_L[0]

M

AF30

A1_CS_L[1]

M

AB29

A_RAS_L

M

AD29

A_CAS_L

M

AD28

A_WE_L

M

J28

A_RESET_L

M

AA26

A_EVENT_L

M

G32

_VREF

M

AJ32

_ZVDDIO

M

TRINITY-A8-SERIES_BGA813

TRINITY-A8-SERIES_BGA813

5745R1@

5745R1@

A_DATA[0]

M

A_DATA[1]

M

A_DATA[2]

M

A_DATA[3]

M

A_DATA[4]

M

A_DATA[5]

M

A_DATA[6]

M

A_DATA[7]

M

A_DATA[8]

M

A_DATA[9]

M

A_DATA[10]

M

A_DATA[11]

M

A_DATA[12]

M

A_DATA[13]

M

A_DATA[14]

M

A_DATA[15]

M

A_DATA[16]

M

A_DATA[17]

M

A_DATA[18]

M

A_DATA[19]

M

A_DATA[20]

M

A_DATA[21]

M

A_DATA[22]

M

A_DATA[23]

M

A_DATA[24]

M

A_DATA[25]

M

A_DATA[26]

M

A_DATA[27]

M

A_DATA[28]

M

A_DATA[29]

M

A_DATA[30]

M

A_DATA[31]

M

A_DATA[32]

M

A_DATA[33]

M

A_DATA[34]

M

A_DATA[35]

M

A_DATA[36]

M

A_DATA[37]

M

A_DATA[38]

M

A_DATA[39]

M

A_DATA[40]

M

A_DATA[41]

M

A_DATA[42]

M

A_DATA[43]

M

A_DATA[44]

M

A_DATA[45]

M

A_DATA[46]

M

A_DATA[47]

M

A_DATA[48]

M

A_DATA[49]

M

A_DATA[50]

M

A_DATA[51]

M

A_DATA[52]

M

A_DATA[53]

M

A_DATA[54]

M

A_DATA[55]

M

A_DATA[56]

M

A_DATA[57]

M

A_DATA[58]

M

A_DATA[59]

M

A_DATA[60]

M
M

A_DATA[61]

M

A_DATA[62]

M

A_DATA[63]

B

DR_A_D[0..63] <10>

F15

D

DR_A_D0

E15

D

DR_A_D1

H19

D

DR_A_D2

F19

D

DR_A_D3

E14

D

DR_A_D4

H15

D

DR_A_D5

E17

D

DR_A_D6

D18

D

DR_A_D7

G20

D

DR_A_D8

E20

D

DR_A_D9

H23

D

DR_A_D10

G23

D

DR_A_D11

E19

D

DR_A_D12

H20

D

DR_A_D13

E22

D

DR_A_D14

D22

D

DR_A_D15

H25

D

DR_A_D16

F25

D

DR_A_D17

D28

D

DR_A_D18

D29

D

DR_A_D19

E23

D

DR_A_D20

D24

D

DR_A_D21

D26

D

DR_A_D22

D27

D

DR_A_D23

G28

D

DR_A_D24

G29

D

DR_A_D25

H27

D

DR_A_D26

J29

D

DR_A_D27

E28

D

DR_A_D28

F27

D

DR_A_D29

H29

D

DR_A_D30

H28

D

DR_A_D31

AH29

D

DR_A_D32

AJ30

D

DR_A_D33

AM28

D

DR_A_D34

AM27

D

DR_A_D35

AH27

D

DR_A_D36

AH28

D

DR_A_D37

AJ29

D

DR_A_D38

AK27

D

DR_A_D39

AK26

D

DR_A_D40

AJ26

D

DR_A_D41

AK23

D

DR_A_D42

AJ23

D

DR_A_D43

AM26

D

DR_A_D44

AL26

D

DR_A_D45

AM24

D

DR_A_D46

AL23

D

DR_A_D47

AK22

D

DR_A_D48

AH22

D

DR_A_D49

AK19

D

DR_A_D50

AH19

D

DR_A_D51

AM22

D

DR_A_D52

AL22

D

DR_A_D53

AJ20

D

DR_A_D54

AL19

D

DR_A_D55

AK17

D

DR_A_D56

AJ17

D

DR_A_D57

AK14

D

DR_A_D58

AH14

D

DR_A_D59

AM18

D

DR_A_D60

AL17

D

DR_A_D61

AH15

D

DR_A_D62

AL14

D

DR_A_D63

1.5V

+

D

C

DR_B_DQS[0..7]<11>

D

DR_B_DQS#[0..7]<11>

D

DR_B_MA[0..15]<11>

D

DR_B_BS0<11>

D

DR_B_BS1<11>

D

DR_B_BS2<11>

D

DR_B_DM[0..7]<11>

D

DR_B_CLK0<11>

D

DR_B_CLK0#<11>

D

DR_B_CLK1<11>

D

DR_B_CLK1#<11>

D

DR_B_CKE0<11>

D

DR_B_CKE1<11>

D

DR_B_ODT0<11>

D

DR_B_ODT1<11>

D

DR_B_SCS0#<11>

D

DR_B_SCS1#<11>

D

DR_B_RAS#<11>

D

DR_B_CAS#<11>

D

DR_B_WE#<11>

D

EM_MB_RST#<11>

M

EM_MB_EVENT#<11>

M

D

DR_B_MA0

D

DR_B_MA1

D

DR_B_MA2

D

DR_B_MA3

D

DR_B_MA4

D

DR_B_MA5

D

DR_B_MA6

D

DR_B_MA7

D

DR_B_MA8

D

DR_B_MA9

D

DR_B_MA10

D

DR_B_MA11

D

DR_B_MA12

D

DR_B_MA13

D

DR_B_MA14

D

DR_B_MA15

DR_B_BS0

D

DR_B_BS1

D

DR_B_BS2

D

DR_B_DM0

D

DR_B_DM1

D

DR_B_DM2

D

DR_B_DM3

D

DR_B_DM4

D

DR_B_DM5

D

DR_B_DM6

D

DR_B_DM7

D

DR_B_DQS0

D

DR_B_DQS#0

D

DR_B_DQS1

D

DR_B_DQS#1

D

DR_B_DQS2

D

DR_B_DQS#2

D

DR_B_DQS3

D

DR_B_DQS#3

D

DR_B_DQS4

D

DR_B_DQS#4

D

DR_B_DQS5

D

DR_B_DQS#5

D

D

DR_B_DQS6

D

DR_B_DQS#6

DR_B_DQS7

D

DR_B_DQS#7

D

D

U

U

APUC

APUC

Y33

M

B_ADD[0]

R32

M

B_ADD[1]

T31

M

B_ADD[2]

P33

M

B_ADD[3]

P32

M

B_ADD[4]

P31

M

B_ADD[5]

N32

M

B_ADD[6]

M33

M

B_ADD[7]

M32

M

B_ADD[8]

L32

M

B_ADD[9]

AB31

M

B_ADD[10]

M31

M

B_ADD[11]

K32

M

B_ADD[12]

AF33

M

B_ADD[13]

K33

M

B_ADD[14]

J32

M

B_ADD[15]

AB33

M

B_BANK[0]

AA32

M

B_BANK[1]

K31

M

B_BANK[2]

C18

M

B_DM[0]

B23

M

B_DM[1]

C28

M

B_DM[2]

D31

M

B_DM[3]

AM31

M

B_DM[4]

AN30

M

B_DM[5]

AR24

M

B_DM[6]

AN18

M

B_DM[7]

B18

M

B_DQS_H[0]

A18

M

B_DQS_L[0]

B24

M

B_DQS_H[1]

A24

M

B_DQS_L[1]

B30

M

B_DQS_H[2]

B29

M

B_DQS_L[2]

D32

M

B_DQS_H[3]

D33

M

B_DQS_L[3]

AM32

M

B_DQS_H[4]

AM33

M

B_DQS_L[4]

AN28

M

B_DQS_H[5]

AP29

M

B_DQS_L[5]

AP23

M

B_DQS_H[6]

AP24

M

B_DQS_L[6]

AR18

M

B_DQS_H[7]

AP18

M

B_DQS_L[7]

W32

M

B_CLK_H[0]

Y32

M

B_CLK_L[0]

V33

M

B_CLK_H[1]

V32

M

B_CLK_L[1]

U32

M

B_CLK_H[2]

V31

M

B_CLK_L[2]

T33

M

B_CLK_H[3]

T32

M

B_CLK_L[3]

H32

M

B_CKE[0]

H33

M

B_CKE[1]

AF31

M

B0_ODT[0]

AH31

M

B0_ODT[1]

AE32

M

B1_ODT[0]

AH33

M

B1_ODT[1]

AD31

M

B0_CS_L[0]

AF32

M

B0_CS_L[1]

AC32

M

B1_CS_L[0]

AG32

M

B1_CS_L[1]

AB32

M

B_RAS_L

AD32

M

B_CAS_L

AD33

M

B_WE_L

H31

M

B_RESET_L

Y31

M

B_EVENT_L

TRINITY-A8-SERIES_BGA813

TRINITY-A8-SERIES_BGA813

5745R1@

5745R1@

M

B_DATA[0]

M

B_DATA[1]

M

B_DATA[2]

M

B_DATA[3]

M

B_DATA[4]

M

B_DATA[5]

M

B_DATA[6]

M

B_DATA[7]

M

B_DATA[8]

M

B_DATA[9]

M

B_DATA[10]

M

B_DATA[11]

M

B_DATA[12]

M

B_DATA[13]

M

B_DATA[14]

M

B_DATA[15]

M

B_DATA[16]

M

B_DATA[17]

M

B_DATA[18]

M

B_DATA[19]

M

B_DATA[20]

M

B_DATA[21]

M

B_DATA[22]

M

B_DATA[23]

M

B_DATA[24]

M

B_DATA[25]

M

B_DATA[26]

M

B_DATA[27]

M

B_DATA[28]

M

B_DATA[29]

M

B_DATA[30]

M

B_DATA[31]

M

B_DATA[32]

M

B_DATA[33]

M

B_DATA[34]

M

B_DATA[35]

M

B_DATA[36]

M

B_DATA[37]

M

B_DATA[38]

M

B_DATA[39]

M

B_DATA[40]

M

B_DATA[41]

M

B_DATA[42]

M

B_DATA[43]

M

B_DATA[44]

M

B_DATA[45]

M

B_DATA[46]

M

B_DATA[47]

M

B_DATA[48]

M

B_DATA[49]

M

B_DATA[50]

M

B_DATA[51]

B_DATA[52]

M

B_DATA[53]

M

B_DATA[54]

M

B_DATA[55]

M

B_DATA[56]

M

B_DATA[57]

M

B_DATA[58]

M

B_DATA[59]

M

B_DATA[60]

M

B_DATA[61]

M

B_DATA[62]

M

B_DATA[63]

M

C16
B17
B20
C20
A16
B16
B19
A20

B22
C22
A26
B26
B21
A22
C24
B25

A28
B28
B31
A32
C26
B27
A30
C30

B33
C32
F33
F32
B32
C31
E32
F31

AK32
AL32
AP32
AN31
AK31
AK33
AN32
AP33

AP30
AR30
AP27
AN26
AR32
AP31
AR28
AP28

AP25
AN24
AR22
AP21

AP26
AR26
AN22
AP22

AR20
AP19
AP16
AR16
AN20
AP20
AP17
AN16

DR_B_D0

D

DR_B_D1

D

DR_B_D2

D

DR_B_D3

D

DR_B_D4

D

DR_B_D5

D

DR_B_D6

D

DR_B_D7

D

DR_B_D8

D

DR_B_D9

D

DR_B_D10

D

DR_B_D11

D

DR_B_D12

D

DR_B_D13

D

DR_B_D14

D

DR_B_D15

D

DR_B_D16

D

DR_B_D17

D

DR_B_D18

D

DR_B_D19

D

DR_B_D20

D

DR_B_D21

D

DR_B_D22

D

DR_B_D23

D

DR_B_D24

D

DR_B_D25

D

DR_B_D26

D

DR_B_D27

D

DR_B_D28

D

DR_B_D29

D

DR_B_D30

D

DR_B_D31

D

DR_B_D32

D

DR_B_D33

D

DR_B_D34

D

DR_B_D35

D

DR_B_D36

D

DR_B_D37

D

DR_B_D38

D

DR_B_D39

D

DR_B_D40

D

DR_B_D41

D

DR_B_D42

D

DR_B_D43

D

DR_B_D44

D

DR_B_D45

D

DR_B_D46

D

DR_B_D47

D

DR_B_D48

D

DR_B_D49

D

DR_B_D50

D

DR_B_D51

D

DR_B_D52

D

DR_B_D53

D

DR_B_D54

D

DR_B_D55

D

DR_B_D56

D

DR_B_D57

D

DR_B_D58

D

DR_B_D59

D

DR_B_D60

D

DR_B_D61

D

DR_B_D62

D

DR_B_D63

D

E

DR_B_D[0..63] <11>

D

0.75V Reference Voltage

R

R

64

64

1K_0402_1%

1K_0402_1%

65

65

R

R

1K_0402_1%

1K_0402_1%

2

1

2

1

B

1

C

C

124

124

1000P_0402_50V7K

1000P_0402_50V7K

2

+

MEM_VREF

2

C

C

125

125

0.1U_0402_25V6

0.1U_0402_25V6

1

S

S

ecurity Classification

ecurity Classification

ecurity Classification

S

I

ssued Date

ssued Date

ssued Date

I

I

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2

013/01/22 2014/01/21

2013/01/22 2014/01/21

013/01/22 2014/01/21

2

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

C

C

D

D

eciphered Date

eciphered Date

eciphered Date

D

D

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

T

itle

itle

itle

T

T

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

ustom

ustom

ustom

C

C

Date: Sheet

Date: Sheet

Date: Sheet

C

A

A

MD Trinity FP2 DDRIII I/F

MD Trinity FP2 DDRIII I/F

MD Trinity FP2 DDRIII I/F

A

L

L

A-9869P

A-9869P

A-9869P

L

E

o

f

6 50Monday, February 04, 2013

f

6 50Monday, February 04, 2013

f

6 50Monday, February 04, 2013

o

o

0

.3

.3

.3

0

0

E

4 4

VENT# pull high

1.5V

+

1 2

R

R

15 1K_0402_5%

15 1K_0402_5%

1

R

R

61 1K_0402_5%

61 1K_0402_5%

M

A

EM_MA_EVENT#

M

EM_MB_EVENT#

2

A

1 2

56 0.1U_0402_16V7K

56 0.1U_0402_16V7K

C

D

U

U

MA_HDMI_TX2+<22>

U

U

MA_HDMI_TX1+<22>

U

U

MA_HDMI_TX0+<22>

U

MA_HDMI_TXC+<22>

U

MA_HDMI_TXC-<22>

D

D

D

M

L_VGA_TXP0<25>

M

L_VGA_TXN0<25>

M

L_VGA_TXP1<25>

M

L_VGA_TXN1<25>

M

L_VGA_TXP2<25>

M

L_VGA_TXN2<25>

M

L_VGA_TXP3<25>

M

L_VGA_TXN3<25>

MA_HDMI_TX2-<22>

MA_HDMI_TX1-<22>

MA_HDMI_TX0-<22>

P0_TXP0_C<19>
P0_TXN0_C<19>

P0_TXP1_C<20>

P0_TXN1_C<20>

1

00MHz (SS)

L

VDS/eDP

1 1

CRT

(To FCH)

HDMI

100MHz (Non-spread spectrum)

2 2

1.5V

+

Close to JHDT

PC3

PC3

R

R

1 8
2 7
3
4

1K_0804_8P4R_5%

1K_0804_8P4R_5%

1

117 1K_0402_5%

117 1K_0402_5%

R

R

3 3

C

C

C

4 4

1 2

127 1000P_0402_50V7K@C127 1000P_0402_50V7K@

1 2

140 1000P_0402_50V7K@C140 1000P_0402_50V7K@

1 2

141 1000P_0402_50V7K@C141 1000P_0402_50V7K@

A

PU_TDI

A

PU_TCK

6

A

PU_TMS

5

A

PU_TRST#

2

A

PU_DBREQ#

A

PU_VDD_RUN_FB_L<45>

A

PU_VDDNB_SEN<45>

A

PU_VDD_SEN<45>

A

PU_SVC

A

PU_SVD

A

PU_SVT

A

C

1 2

48 0.1U_0402_16V7K

48 0.1U_0402_16V7K

C

C

1 2

58 0.1U_0402_16V7KIED P@

58 0.1U_0402_16V7KIED P@

C

C

1 2

75 0.1U_0402_16V7KIED P@

75 0.1U_0402_16V7KIED P@

C

C

1 2

67 0.1U_0402_16V7K

67 0.1U_0402_16V7K

C

C

1 2

71 0.1U_0402_16V7KC71 0.1U_0402_16V7K

C

1 2

66 0.1U_0402_16V7K

66 0.1U_0402_16V7K

C

C

1 2

69 0.1U_0402_16V7K

69 0.1U_0402_16V7K

C

C

1 2

C

C

68 0.1U_0402_16V7K

68 0.1U_0402_16V7K

1 2

72 0.1U_0402_16V7K

72 0.1U_0402_16V7K

C

C

1 2

73 0.1U_0402_16V7K

73 0.1U_0402_16V7K

C

C

2

1

70 0.1U_0402_16V7K

70 0.1U_0402_16V7K

C

C

clock no test point

A

PU_CLK<23>

A

PU_CLK#<23>

A

PU_DISP_CLK<23>

A

PU_DISP_CLK#<23>

31 0_0402_5%@

31 0_0402_5%@

R

1 2

212 0_0402_5%@

212 0_0402_5%@

R

R

1

214 0_0402_5%@

214 0_0402_5%@

R

R

1

215 0_0402_5%@

215 0_0402_5%@

R

R

A

PU_RST#<23>

A

PU_PWRGD<23,45>

R

R

R

32 0_0402_5%@

32 0_0402_5%@

33 0_0402_5%@

33 0_0402_5%@

R

R

A

PU_SIC<9>

A

PU_SID<9>

15T15

T

16T16

T

2

2

A

PU_SVC<45>

A

PU_SVD<45>

A

PU_SVT<45>

1 2

1 2

1 2

A

PU_PROCHOT#

A

PU_THERMTRIP#

A

PU_ALERT#

A

PU_TDI

A

PU_TDO

A

PU_TCK

A

PU_TMS

A

PU_TRST#

A

PU_DBRDY

A

PU_DBREQ#

13

T13T

21

T21T

T28T

28

B

D

P0_TXP0

D

P0_TXN0

D

P0_TXP1

D

P0_TXN1

D

P1_TXP0

D

P1_TXN0

D

P1_TXP1

D

P1_TXN1

D

P1_TXP2

D

P1_TXN2

D

P1_TXP3

D

P1_TXN3

A
A

A

V

SS_SENSE

V

DDNB_SENSE

V

DD_SENSE

B

PU_SVC_R
PU_SVD_R

PU_SVT_R

U

U

APUD

APUD

H2

D

P0_TXP[0]

H1

D

P0_TXN[0]

H3

D

P0_TXP[1]

H4

D

P0_TXN[1]

F4

D

P0_TXP[2]

F3

D

P0_TXN[2]

F1

D

P0_TXP[3]

F2

D

P0_TXN[3]

E2

D

P1_TXP[0]

E1

D

P1_TXN[0]

D4

D

P1_TXP[1]

D3

D

P1_TXN[1]

D1

D

P1_TXP[2]

D2

D

P1_TXN[2]

C1

D

P1_TXP[3]

C2

D

P1_TXN[3]

B2

D

P2_TXP[0]

A2

D

P2_TXN[0]

B3

D

P2_TXP[1]

A3

D

P2_TXN[1]

B4

D

P2_TXP[2]

A4

D

P2_TXN[2]

B5

D

P2_TXP[3]

A5

D

P2_TXN[3]

AL9

C

LKIN_H

AK9

C

LKIN_L

AL7

D

ISP_CLKIN_H

AK7

D

ISP_CLKIN_L

E5

S

VC

E6

S

VD

D6

S

VT

AJ11

S

IC

AH11

S

ID

AK11

R

ESET_L

AH9

P

WROK

AL12

P

ROCHOT_L

AK5

T

HERMTRIP_L

AR10

A

LERT_L

E11

T

DI

G11

T

DO

H12

T

CK

F11

T

MS

H11

T

RST_L

E8

D

BRDY

E7

D

BREQ_L

G6

V

SS_SENSE

H6

V

DDP_SENSE

H5

V

DDNB_SENSE

G7

V

DDIO_SENSE

G5

V

DD_SENSE

H7

V

DDR_SENSE

TRINITY-A8-SERIES_BGA813

TRINITY-A8-SERIES_BGA813

5745R1@

5745R1@

ISPLAY PORT 0DISPLAY PORT 1DISPLAY PORT 2CLKSER.CTRLJTAGSENSE

ISPLAY PORT 0DISPLAY PORT 1DISPLAY PORT 2CLKSER.CTRLJTAGSENSE
D

D

D

P0_AUXP

D

P0_AUXN

D

P1_AUXP

D

P1_AUXN

D

P2_AUXP

D

P2_AUXN

D

P3_AUXP

D

P3_AUXN

D

P4_AUXP

D

P4_AUXN

D

P5_AUXP

D

P5_AUXN

D

P0_HPD

ISPLAY PORT MISC.RSVD TEST

ISPLAY PORT MISC.RSVD TEST
D

D

D

P1_HPD

D

P2_HPD

D

P3_HPD

D

P4_HPD

D

P5_HPD

D

P_BLON

D

P_DIGON

D

P_VARY_BL

D

P_AUX_ZVSS

T

EST25_H

T

EST25_L

T

EST28_H

T

EST28_L

T

EST30_H

T

EST30_L

T

EST32_H

T

EST32_L

D

MAACTIVE_L

C

M5

D

P0_AUXP

M6

D

P0_AUXN

L5

D

P1_AUXP

L6

D

P1_AUXN

J5
J6

P5

Aux signal are re-configured as I2C signals for DDC

P6

APU AUX pin are 3.3V tolerant

R5
R6

U5
U6

M7

L

VDS_HPD

L7

F

CH_CRT_HPD

J7

H

DMI_HPD

P7
R7
U7

C6
D7
A6

B6

D

P_AUX_ZVSS

AL6

T

EST6

Y23

T

EST9

V23

T

EST10

G9

T

EST14

F9

T

EST15

E9

T

EST16

G8

T

EST17

F12

A

T

EST18

T

EST19

T

EST20

T

EST24

T

EST31

T

EST35

T
T

R
R
R
R
R

EST4
EST5

SVD
SVD
SVD
SVD
SVD

PU_TEST18

E12

A

PU_TEST19

F14

A

PU_TEST20

G12

A

PU_TEST24

AJ8

T

EST25_H

AH8

T

EST25_L

G14
H14
V25
Y25
AH32

A

PU_TEST31

R25
T25
AL5

A

PU_TEST35

AP10

T23
R23

L8
P8
AH12
AJ12
AK12

ecurity Classification

ecurity Classification

ecurity Classification

S

S

S

ssued Date

ssued Date

ssued Date

I

I

I

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

T

T

T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

1 2

47 0.1U_0402_16V7K

47 0.1U_0402_16V7K

C

C

1 2

49 0.1U_0402_16V7K

49 0.1U_0402_16V7K

C

C

1 2

57 0.1U_0402_16V7K

57 0.1U_0402_16V7K

C

C

1 2

52 0.1U_0402_16V7K

52 0.1U_0402_16V7K

C

C

16 150_0402_1%

16 150_0402_1%

R

R

7

T7T

8T8

T

9

T9T

10

T10T

T17T

17

18

T18T

T

EST4

T

EST5

11

T11T

12

T12T

D

P0_AUXP_C <19>

D

P0_AUXN_C <19>

M

L_VGA_AUXP <25>

M

L_VGA_AUXN <25>

U

MA_HDMI_CLK <22>

U

MA_HDMI_DATA <22>

L

VDS_HPD <19,20>

F

CH_CRT_HPD <25>

H

DMI_HPD <22,24>

D

P_ENBKL <9>

D

P_ENVDD <9>

D

P_INT_PWM <9>

2

1

1 2

R

R

23 510_0402_1%

23 510_0402_1%

24 510_0402_1%

24 510_0402_1%

R

R

38 39.2_0402_1%

38 39.2_0402_1%

R

R

29 300_0402_5%

29 300_0402_5%

R

R

30 300_0402_5%@

30 300_0402_5%@

R

R

2

1

2

1

1 2

2

1

D

MA_ACTIVE# <23>

C

hange TEST35 to pull-high
for HDMI issue
check list recommend mount R29 and R30 @

A

sserted as an input to force the

processor into the HTC-active state

@ESD@

@ESD@

013/01/22 2014/01/21

013/01/22 2014/01/21

013/01/22 2014/01/21

2

2

2

3

.3V Tolerance

1.2VS

+

1.5V

+

A

PU_PROCHOT#<23>

A

PU_PROCHOT#

CK0402101V05_0402-2

CK0402101V05_0402-2

D

D
31

31

1 2

T

hermal Shutdown Temperature:

115 degree

ompal Secret Data

ompal Secret Data

ompal Secret Data

C

C

C

eciphered Date

eciphered Date

eciphered Date

D

D

D

D

L

VDS

C

RT (To FCH)

HDMI

A

PU_PROCHOT#

A

PU_THERMTRIP#

D

1K_0402_5%

1K_0402_5%

L

VDS_HPD

F

CH_CRT_HPD

H

DMI_HPD

A
A
A
A

1 8

PU_TEST18

2

PU_TEST19

3 6

PU_TEST20

4 5

PU_TEST24

1K_0804_8P4R_5%

1K_0804_8P4R_5%

1K_0402_5%

1K_0402_5%

1 2

@

@

136 0_0402_5%

136 0_0402_5%

R

R

1.5V

+

68

68

R

R

1 2

3 1

MMBT3904_NL_SOT23-3

MMBT3904_NL_SOT23-3

E

2

D

P0_AUXP

D

P0_AUXN

D

P1_AUXP

D

P1_AUXN

D

P0_AUXP

D

P0_AUXN

PC1

PC1

R

R

A

PU_RST#

A

PU_PWRGD

55

55

R

R

1

2

B

B

2

E

E

C

C

C

25 1.8K_0402_5%

25 1.8K_0402_5%

R

R

R

R

58 1.8K_0402_5%

58 1.8K_0402_5%

10 1.8K_0402_5%

10 1.8K_0402_5%

R

R

11 1.8K_0402_5%

11 1.8K_0402_5%

R

R

74 100K_0402_5%

74 100K_0402_5%

R

R

75 100K_0402_5%

75 100K_0402_5%

R

R

95 100K_0402_5%

95 100K_0402_5%

R

R

F

or 2132R

138 680P_0402_50V7K

138 680P_0402_50V7K

C

C

139 680P_0402_50V7K

139 680P_0402_50V7K

C

C

A

PU_SVT_R

R

A

A

A

A

Date: Sheet

Date: Sheet

Date: Sheet

R

PU_SVC_R

R

R

PU_SVD_R

R

R

7

R

R

R

R

PU_RST#

PU_PWRGD

1.5V

+

2

1

69

69

R

R
10K_0402_5%

10K_0402_5%

5

5

Q

Q

C

C

itle

itle

itle

T

T

T

MD Trinity FP2 Display / MISC / HDT

MD Trinity FP2 Display / MISC / HDT

MD Trinity FP2 Display / MISC / HDT

A

A

A

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

ustom

ustom

ustom

A-9869P

A-9869P

A-9869P

L

L

L

1

2

1

12

12

12

2

1

2

1

2

1

1 2

36 1K_0402_5%@

36 1K_0402_5%@

39 1K_0402_5%@

39 1K_0402_5%@

41 1K_0402_5%@

41 1K_0402_5%@

52 300_0402_5%

52 300_0402_5%

54 300_0402_5%

54 300_0402_5%

12

2

1

12

R

R

PC2

PC2

A

PU_SIC

A

PU_SID

A

PU_ALERT#

D

MA_ACTIVE#

1

C

126 1000P_0402_50V7K@C126 1000P_0402_50V7K@

1

130 180P_0402_50V8J

130 180P_0402_50V8J

C

C

C

C

C

1
2 7
3 6
4

1K_0804_8P4R_5%

1K_0804_8P4R_5%

12

12

2

2

@ESD@

@ESD@

H

H

_THERMTRIP# <24>

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

E

1.5V

+

1.5V

+

8

5

1.5V

+

_PROCHOT# <34,45>

7 50Monday, February 04, 2013

7 50Monday, February 04, 2013

7 50Monday, February 04, 2013

o

o

o

.3

.3

.3

0

0

0

f

f

f

A

+

1.5V

V
V
V
V
V
V
V
V
V
V
V
V
V

C
170 0.22U_0402_10V4ZC170 0.22U_0402_10V4Z

DDNB
DDNB
DDNB
DDNB
DDNB
DDNB
DDNB
DDNB
DDNB
DDNB
DDNB
DDNB
DDNB

V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V

V
V
V
V
V

V
V
V
V
V
V

V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V

DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO

DDR
DDR
DDR
DDR
DDR

1

2

+

APU_CORE

V17

DD

V19

DD

V20

DD

V22

DD

W8

DD

AA8

DD

AA9

DD

AA11

DD

AA12

DD

AA14

DD

AA15

DD

AA17

DD

AA19

DD

AA20

DD

AA22

DD

AD9

DD

AD11

DD

AD12

DD

AD14

DD

AD15

DD

AD17

DD

AD19

DD

AD20

DD

AD22

DD

AG12

DD

AG14

DD

AG15

DD

AG17

DD

AG19

DD

AG20

DD

AG22

DD

B11
B12
B13
B14
B15
C8
C10
C12
C14
D8
D10
D12
D14

M9
N9

W33
AA23
AA25
AA27
AA30
AA33
AB28
AC30
AC33
AD23
AD25
AD27
AE28
AE30
AE33
AG23
AG25
AG27
AG30
AG33

AN14
AP14
AP15
AR14
AR15

+

C
165 4.7U_0603_6.3V6KC165 4.7U_0603_6.3V6K

1

2

VDDA

+

APU_CORE_NB

+

VDDNB_CAP

+

1.5V

+

1.2VS

C

C

C

163 22U_0603_6.3V6MC163 22U_0603_6.3V6M

196 22U_0603_6.3V6MC196 22U_0603_6.3V6M

158 180P_0402_50V8JC158 180P_0402_50V8J

1

1

2

2

c

lose to APU

+

VDDP_CAP

+

APU_CORE

1 1

+

APU_CORE_NB

2 2

+

1.5V

3 3

+

1.2VS

+

VDDP_CAP

+

VDDA

O

ther signals
should keep 20
mil away with
+VDDA

FBMA-L11-201209-300LMA30T

FBMA-L11-201209-300LMA30T

+

2.5VS

4 4

U

U

APUE

APUE

J12

V

DD

J14

V

DD

J15

V

DD

J17

V

DD

J19

V

DD

J20

V

DD

J22

V

DD

M11

V

DD

M12

V

DD

M14

V

DD

M15

V

DD

M17

V

DD

M19

V

DD

M20

V

DD

M22

V

DD

R8

V

DD

R9

V

DD

R11

V

DD

R12

V

DD

R14

V

DD

R15

V

DD

R17

V

DD

R19

V

DD

R20

V

DD

R22

V

DD

U8

V

DD

V9

V

DD

V11

V

DD

V12

V

DD

V14

V

DD

V15

V

DD

A7

DDNB

V

A8

DDNB

V

A9

DDNB

V

A10

DDNB

V

A11

DDNB

V

A12

DDNB

V

A13

DDNB

V

A14

DDNB

V

A15

DDNB

V

B7

DDNB

V

B8

DDNB

V

B9

DDNB

V

B10

DDNB

V

J33

DDIO

V

K23

DDIO

V

K25

DDIO

V

L28

DDIO

V

L30

DDIO

V

L33

DDIO

V

M27

DDIO

V

N23

DDIO

V

N25

DDIO

V

N30

DDIO

V

N33

DDIO

V

P28

DDIO

V

R27

DDIO

V

R30

DDIO

V

R33

DDIO

V

U28

DDIO

V

U30

DDIO

V

U33

DDIO

V

W28

DDIO

V

W30

DDIO

V

AM12

DDP

V

AN12

DDP

V

AP12

DDP

V

AP13

DDP

V

AR12

DDP

V

AR13

DDP

V

AA6

DDP_CAP

V

AA7

DDP_CAP

V

AM13

DDA

V

AM14

DDA

V

TRINITY-A8-SERIES_BGA813

TRINITY-A8-SERIES_BGA813

5745R1@

5745R1@

L

L

1

1

1 2

3

6A

30A

V
V

3.2A

3.5A

0.75A

C
164 3300P_0402_50V7-KC164 3300P_0402_50V7-K

DDNB_CAP
DDNB_CAP

3.5A

1

2

B

C

C

C
65 22U_0603_6.3V6MC65 22U_0603_6.3V6M

74 22U_0603_6.3V6MC74 22U_0603_6.3V6M

1

1

2

2

+

1.2VS

1

2

C

C

168 22U_0805_6.3V6MC168 22U_0805_6.3V6M

169 22U_0805_6.3V6MC169 22U_0805_6.3V6M

1

1

2

2

C

C
64 22U_0603_6.3V6MC64 22U_0603_6.3V6M

1

2

C

C

89 4.7U_0603_6.3V6KC89 4.7U_0603_6.3V6K

63 22U_0603_6.3V6MC63 22U_0603_6.3V6M

90 4.7U_0603_6.3V6KC90 4.7U_0603_6.3V6K

1

1

1

2

2

2

C

C
149 0.01U_0402_16V7KC149 0.01U_0402_16V7K

137 0.01U_0402_16V7KC137 0.01U_0402_16V7K

1

1

2

2

C

C

C

93 0.22U_0402_10V4ZC93 0.22U_0402_10V4Z

91 4.7U_0603_6.3V6KC91 4.7U_0603_6.3V6K

92 4.7U_0603_6.3V6KC92 4.7U_0603_6.3V6K

1

1

1

2

2

2

V

DDR more differ ent VDDP more diffe rent

C

C

116 0.22U_0402_10V4ZC116 0.22U_0402_10V4Z

115 0.22U_0402_10V4ZC115 0.22U_0402_10V4Z

1

1

2

2

C

C

C

95 0.22U_0402_10V4ZC95 0.22U_0402_10V4Z

94 0.22U_0402_10V4ZC94 0.22U_0402_10V4Z

1

1

2

2

C
111 1000P_0402_50V7KC111 1000P_0402_50V7K

C

C

97 0.22U_0402_10V4ZC97 0.22U_0402_10V4Z

96 0.22U_0402_10V4ZC96 0.22U_0402_10V4Z

102 0.22U_0402_10V4ZC102 0.22U_0402_10V4Z

117 0.22U_0402_10V4ZC117 0.22U_0402_10V4Z

1

1

1

1

2

2

2

2

C

C
110 180P_0402_50V8JC110 180P_0402_50V8J

109 180P_0402_50V8JC109 180P_0402_50V8J

1

1

1

2

2

2

C

C

119 0.22U_0402_10V4ZC119 0.22U_0402_10V4Z

118 0.22U_0402_10V4ZC118 0.22U_0402_10V4Z

1

1

2

2

C

C

C
100 180P_0402_50V8JC100 180P_0402_50V8J

1

2

P

ower Sequence of APU

C

C

103 180P_0402_50V8JC103 180P_0402_50V8J

131 4.7U_0603_6.3V6K

131 4.7U_0603_6.3V6K

1

1

2

2

@

@

+

1.2VS

+

1.5V

C
105 180P_0402_50V8JC105 180P_0402_50V8J

+2.5VS

+

1.5VS

+CPU_CORE

+CPU_CORE_NB

+1.2VS

D

U

U

APUF

APUF

A17

V

+

1.5V

1

C

C

150

150

100U_1206_6.3V6K

100U_1206_6.3V6K

@

@

2

C

C

C

C

C

C
106 180P_0402_50V8JC106 180P_0402_50V8J

1

1

2

2

C

77 22U_0603_6.3V6MC77 22U_0603_6.3V6M

655 22U_0603_6.3V6M

152 0.22U_0402_10V4ZC152 0.22U_0402_10V4Z

132 0.22U_0402_10V4ZC132 0.22U_0402_10V4Z

1

1

2

2

655 22U_0603_6.3V6M

632 22U_0603_6.3V6MC632 22U_0603_6.3V6M

1

1

1

@

@

2

2

2

Group A

Group B

SS

A19

V

SS

A21

V

SS

A23

V

SS

A25

V

SS

A27

V

SS

A29

V

SS

A31

V

SS

B1

V

SS

C3

V

SS

C4

V

SS

C33

V

SS

D5

V

SS

D9

V

SS

D11

V

SS

D13

V

SS

D15

V

SS

D17

V

SS

D19

V

SS

D21

V

SS

D23

V

SS

D25

V

SS

D30

SS

V

E4

SS

V

E27

SS

V

E29

SS

V

E30

SS

V

E33

SS

V

F5

SS

V

F6

SS

V

F7

SS

V

F8

SS

V

F17

SS

V

F20

SS

V

F23

SS

V

F28

SS

V

F29

SS

V

G1

SS

V

G2

SS

V

G4

SS

V

G15

SS

V

G19

SS

V

G25

SS

V

G26

SS

V

G27

SS

V

G33

SS

V

H8

SS

V

H9

SS

V

H22

SS

V

H26

SS

V

J4

SS

V

J8

SS

V

J9

SS

V

J11

SS

V

J23

SS

V

J25

SS

V

J26

SS

V

J27

SS

V

J30

SS

V

K9

SS

V

K11

SS

V

K12

SS

V

K14

SS

V

K15

SS

V

K17

SS

V

K19

SS

V

K20

SS

V

K22

SS

V

L1

SS

V

L2

SS

V

L4

SS

V

M8

SS

V

M23

SS

V

M25

SS

V

N4

SS

V

N11

SS

V

N12

SS

V

N14

SS

V

N15

SS

V

N17

SS

V

N19

SS

V

N20

SS

V

N22

SS

V

R1

SS

V

R2

SS

V

R4

SS

V

T9

SS

V

T11

SS

V

T12

SS

V

T14

SS

V

T15

SS

V

T17

SS

V

T19

SS

V

T20

SS

V

T22

SS

V

U4

SS

V

W1

SS

V

W2

SS

V

W4

SS

V

W5

SS

V

W6

SS

V

W7

SS

V

Y9

SS

V

TRINITY-A8-SERIES_BGA813

TRINITY-A8-SERIES_BGA813

5745R1@

5745R1@

E

Y11

SS

V

Y12

SS

V

Y14

SS

V

Y15

SS

V

Y17

SS

V

Y19

SS

V

Y20

SS

V

Y22

SS

V

AA4

SS

V

AA5

SS

V

AB7

SS

V

AB8

SS

V

AC1

SS

V

AC2

SS

V

AC4

SS

V

AC9

SS

V

AC11

SS

V

AC12

SS

V

AC14

SS

V

AC15

SS

V

AC17

SS

V

AC19

SS

V

AC20

SS

V

AC22

SS

V

AC23

SS

V

AC25

SS

V

AE4

SS

V

AF9

SS

V

AF11

SS

V

AF12

SS

V

AF14

SS

V

AF15

SS

V

AF17

SS

V

AF19

SS

V

AF20

SS

V

AF22

SS

V

AF23

SS

V

AF25

SS

V

AG1

SS

V

AG2

SS

V

AG4

SS

V

AG9

SS

V

AG11

SS

V

AG26

SS

V

AH7

SS

V

AH17

SS

V

AH20

SS

V

AH23

SS

V

AH26

SS

V

AH30

SS

V

AJ4

SS

V

AJ5

SS

V

AJ6

SS

V

AJ7

SS

V

AJ9

SS

V

AJ14

SS

V

AJ15

SS

V

AJ19

SS

V

AJ22

SS

V

AJ27

SS

V

AJ28

SS

V

AJ33

SS

V

AK6

SS

V

AK8

V

SS

AK25

SS

V

AK28

V

SS

AK30

V

SS

AL1

V

SS

AL2

V

SS

AL4

V

SS

AL8

V

SS

AL11

V

SS

AL27

V

SS

AL28

V

SS

AL33

V

SS

AM5

V

SS

AM7

V

SS

AM9

V

SS

AM11

V

SS

AM15

V

SS

AM17

V

SS

AM19

V

SS

AM21

V

SS

AM23

V

SS

AM25

V

SS

AM29

V

SS

AM30

V

SS

AN3

V

SS

AN4

V

SS

AN33

V

SS

AP5

V

SS

AP9

V

SS

AR2

V

SS

AR5

V

SS

AR9

V

SS

AR17

V

SS

AR19

V

SS

AR21

V

SS

AR23

V

SS

AR25

V

SS

AR27

V

SS

AR29

V

SS

AR31

V

SS

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2

2

2

013/01/22 2014/01/21

013/01/22 2014/01/21

013/01/22 2014/01/21

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

Title

itle

itle

A

A

A

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

D

Date: Sheet

ompal Electronics, Inc.

MD Trinity FP2 PWR / GND

MD Trinity FP2 PWR / GND

MD Trinity FP2 PWR / GND

L

L

L

A-9869P

A-9869P

A-9869P

E

0

0

0

.3

.3

.3

o

o

o

f

8 50Monday, February 04, 2013

f

8 50Monday, February 04, 2013

f

8 50Monday, February 04, 2013

5

+

R

R

49

49

0_0402_ 5%

0_0402_ 5%

A

PU_SID

BSH111_ SOT23-3

BSH111_ SOT23-3

V

g = 1.607 V

A

PU_SIC

BSH111_ SOT23-3

BSH111_ SOT23-3

1.5V

16

16

Q

Q
AO3413_ SOT23

AO3413_ SOT23

S

S

G

G

2

D

D

@

@

1 2

1 3

+

1.5V_SI

G

G

2

Q

Q

14

14

13

D

S

D

S

G

G

2

Q

Q

15

15

13

D

S

D

S

S

USP <37>

D D

A

PU_SID<7>

A

C C

PU_SIC<7>

4

BSH111, the Vgs is:
min = 0.4V
Max = 1.3V

When APU High - > MOS OFF (Vgs < 0.4V )
APU Low - > MOS ON (Vgs > 1.3V)

E

C_SMB_D A1 <31,34,39,40>

E

C_SMB_C K1 <31,34,39,40>

3

P

anel PWMSB-TSI

D

P_INT_PW M<7>

e

DP Panel ENVDD

R

R

89

LVDS@

89

LVDS@

2.2K_040 2_5%

2.2K_040 2_5%

Q

Q

21

LVDS@

21

LVDS@

MMBT390 4_NL_SOT23-3

MMBT390 4_NL_SOT23-3

92

LVDS@

92

LVDS@

R

R
47K_040 2_5%

47K_040 2_5%

D

P_INT_PW M

D

P_INT_PW M

D

P_ENVDD< 7>

R

R

93

LVDS@

93

LVDS@

4.7K_040 2_5%

4.7K_040 2_5%

Q

Q

28

LVDS@

28

LVDS@

2N7002K W_SOT323 -3

2N7002K W_SOT323 -3

@

@

1 2

R

R

46 0_0402_ 5%

46 0_0402_ 5%

R

R

89 2.2K_040 2_5%

89 2.2K_040 2_5%

1

R

R

76

76

4.7K_040 2_5%

4.7K_040 2_5%

2

141 2.2K_0 402_5%

141 2.2K_0 402_5%

R

R

1

R

R

147

147

100K_04 02_5%

100K_04 02_5%

IEDP@

IEDP@

2

1

1

2

IEDP@

IEDP@

A

PU_INVT_P WM

2

2

IEDP@

IEDP@

+

3VS

1

R

R
47K_040 2_5%

47K_040 2_5%

IEDP@

IEDP@

2

1

C

C

2

Q

Q

B

B

MMBT390 4_NL_SOT23-3

MMBT390 4_NL_SOT23-3

E

E

3

IEDP@

IEDP@

+

3VS

12

R

R
47K_040 2_5%

47K_040 2_5%

IEDP@

IEDP@

1

C

C

2

Q

Q

B

B

MMBT390 4_NL_SOT23-3

MMBT390 4_NL_SOT23-3

E

E

IEDP@

IEDP@

3

1

12

R

13

D

D

2

G

G

S

S

12

R

R

137

137

4.7K_040 2_5%

4.7K_040 2_5%

IEDP@

IEDP@

61

IEDP@

IEDP@

Q

Q

29A

29A

2N7002D W-T/R7_SOT3 63-6

2N7002D W-T/R7_SOT3 63-6

R

93

93

4.7K_040 2_5%

4.7K_040 2_5%

IEDP@

IEDP@

A

PU_INVT_P WM

Q

Q

28

28

2N7002K W_SOT323 -3

2N7002K W_SOT323 -3

IEDP@

IEDP@

A

PU_INVT_P WM <19,20 >

L

CD_ENVD D <19>

92

92

21

21

135

135

2

26

26

B B

+

3VS

eDP Panel ENBKL

12

R

R

144

144

47K_040 2_5%

47K_040 2_5%

IEDP@

IEDP@

C

2

D

P_ENBKL<7>

A A

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

2

2

2

013/01/2 2 2014/01/2 1

013/01/2 2 2014/01/2 1

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

013/01/2 2 2014/01/2 1

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

1

R

R

146 2.2K_0 402_5%

146 2.2K_0 402_5%

1

R

R

142

142

100K_04 02_5%

100K_04 02_5%

IEDP@

IEDP@

2

IEDP@

IEDP@

2

C

2

Q

Q

27

27

B

B

MMBT390 4_NL_SOT23-3

MMBT390 4_NL_SOT23-3

E

E

IEDP@

IEDP@

3 1

T

T

Title

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

1

R

R

143

143

4.7K_040 2_5%

4.7K_040 2_5%

IEDP@

IEDP@

2

3

IEDP@

IEDP@

5

Q

Q

29B

29B

2N7002D W-T/R7_SOT3 63-6

2N7002D W-T/R7_SOT3 63-6

4

A

A

A

MD Trinity FP2 Singal Level Shifter

MD Trinity FP2 Singal Level Shifter

MD Trinity FP2 Singal Level Shifter

L

L

L

A-9869P

A-9869P

A-9869P

L

CD_ENBK L <20,34>

1

0

0

0

.3

.3

.3

o

o

o

f

9 5 0Monday, February 04, 2013

f

9 5 0Monday, February 04, 2013

f

9 5 0Monday, February 04, 2013

5

1.5V

+

VREF_DQA

+

D D

D

DR_A_CKE0<6>

D

DR_A_BS2<6>

C C

D

DR_A_CLK0<6>

D

DR_A_CLK0#<6>

D

DR_A_BS0<6>

D

DR_A_WE#<6>

D

DR_A_CAS#<6>

D

DR_A_SCS1#<6>

B B

3VS

+

A A

D

DR_A_D0

D

DR_A_D1

D

DR_A_DM0

D

DR_A_D2

D

DR_A_D3

D

DR_A_D8

D

DR_A_D9

D

DR_A_DQS#1

D

DR_A_DQS1

D

DR_A_D10

D

DR_A_D11

D

DR_A_D16

D

DR_A_D17

D

DR_A_DQS#2

D

DR_A_DQS2

D

DR_A_D18

D

DR_A_D19

D

DR_A_D24

D

DR_A_D25

D

DR_A_DM3

D

DR_A_D26

D

DR_A_D27

D

DR_A_MA12

D

DR_A_MA9

D

DR_A_MA8

D

DR_A_MA5

D

DR_A_MA3

D

DR_A_MA1

D

DR_A_MA10

D

DR_A_MA13

D

DR_A_D32

D

DR_A_D33

D

DR_A_DQS#4

D

DR_A_DQS4

D

DR_A_D34

D

DR_A_D35

D

DR_A_D40

D

DR_A_D41

D

DR_A_DM5

D

DR_A_D42

D

DR_A_D43

D

DR_A_D48

D

DR_A_D49

D

DR_A_DQS#6

D

DR_A_DQS6

D

DR_A_D50

D

DR_A_D51

D

DR_A_D56

D

DR_A_D57

D

DR_A_DM7

D

DR_A_D58

D

DR_A_D59

1

C

C

182

182

2

.1U_0402_16V4Z

.1U_0402_16V4Z
0

0

+

0.75VS

DDR3L

DDR3L

J

J

1

REF_DQ

V

3

SS2

V

5

Q0

D

7

Q1

D

9

SS4

V

11

M0

D

13

SS5

V

15

Q2

D

17

Q3

D

19

SS7

V

21

Q8

D

23

Q9

D

25

SS9

V

27

QS#1

D

29

QS1

D

31

SS11

V

33

Q10

D

35

Q11

D

37

SS13

V

39

Q16

D

41

Q17

D

43

SS15

V

45

QS#2

D

47

QS2

D

49

SS18

V

51

Q18

D

53

Q19

D

55

SS20

V

57

Q24

D

59

Q25

D

61

SS22

V

63

M3

D

65

SS23

V

67

Q26

D

69

Q27

D

71

SS25

V

73

KE0

C

75

DD1

V

77

C1

N

79

A2

B

81

DD3

V

83

12/BC#

A

85

9

A

87

DD5

V

89

8

A

91

5

A

93

DD7

V

95

3

A

97

1

A

99

DD9

V

101

K0

C

103

C

K0#

105

V

DD11

107

A

10/AP

109

B

A0

111

V

DD13

113

W

E#

115

C

AS#

117

V

DD15

119

A

13

121

S

1#

123

V

DD17

125

N

CTEST

127

V

SS27

129

D

Q32

131

D

Q33

133

V

SS29

135

D

QS#4

137

D

QS4

139

V

SS32

141

D

Q34

143

D

Q35

145

V

SS34

147

D

Q40

149

D

Q41

151

V

SS36

153

D

M5

155

V

SS37

157

D

Q42

159

D

Q43

161

V

SS39

163

D

Q48

165

D

Q49

167

V

SS41

169

D

QS#6

171

D

QS6

173

V

SS44

175

D

Q50

177

D

Q51

179

V

SS46

181

D

Q56

183

D

Q57

185

V

SS48

187

D

M7

189

V

SS49

191

D

Q58

193

D

Q59

195

V

SS51

197

S

A0

199

V

DDSPD

201

S

A1

203

V

TT1

205

G

1

LCN_DAN06-K4406-0103

LCN_DAN06-K4406-0103

@

@

R

V

REF_CA

E

SS1

V

D
D
SS3

V
QS#0

D

QS0

D

SS6

V

D
D
SS8

V

Q12

D

Q13

D
SS10

V

D

ESET#

SS12

V

Q14

D

Q15

D
SS14

V

Q20

D

Q21

D
SS16

V

D

SS17

V

Q22

D

Q23

D
SS19

V

Q28

D

Q29

D
SS21

V

QS#3

D

QS3

D

SS24

V

Q30

D

Q31

D
SS26

V

KE1

C

DD2

V

DD4

V

DD6

V

DD8

V

DD10

V

C

C

V

DD12

B

R

AS#

V

DD14

O

DT0

V

DD16

O

DT1
N

V

DD18

V

SS28
D

Q36

D

Q37

V

SS30

D

V

SS31
D

Q38

D

Q39

V

SS33
D

Q44

D

Q45

V

SS35

D

QS#5

D

QS5

V

SS38
D

Q46

D

Q47

V

SS40
D

Q52

D

Q53

V

SS42

D

V

SS43
D

Q54

D

Q55

V

SS45
D

Q60

D

Q61

V

SS47

D

QS#7

D

QS7

V

SS50
D

Q62

D

Q63

V

SS52

VENT#

S

S

V

Q4
Q5

Q6
Q7

M1

M2

15

A

14

A

11

A

A

A
A

A
A

K1

K1#

A1

S

0#

C2

M4

M6

DA
CL

TT2

G

1.5V

+

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86

7

88
90

6

92

4

94
96

2

98

0

100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

2

D

DR_A_D4

D

DR_A_D5

D

DR_A_DQS#0

D

DR_A_DQS0

D

DR_A_D6

D

DR_A_D7

D

DR_A_D12

D

DR_A_D13

D

DR_A_DM1

D

DR_A_D14

D

DR_A_D15

D

DR_A_D20

D

DR_A_D21

D

DR_A_DM2

D

DR_A_D22

D

DR_A_D23

D

DR_A_D28

D

DR_A_D29

D

DR_A_DQS#3

D

DR_A_DQS3

D

DR_A_D30

D

DR_A_D31

D

DR_A_MA15

D

DR_A_MA14

D

DR_A_MA11

D

DR_A_MA7

D

DR_A_MA6

D

DR_A_MA4

D

DR_A_MA2

D

DR_A_MA0

+

VREF_CAA

D

DR_A_D36

D

DR_A_D37

D

DR_A_DM4

D

DR_A_D38

D

DR_A_D39

D

DR_A_D44

D

DR_A_D45

D

DR_A_DQS#5

D

DR_A_DQS5

D

DR_A_D46

D

DR_A_D47

D

DR_A_D52

D

DR_A_D53

D

DR_A_DM6

D

DR_A_D54

D

DR_A_D55

D

DR_A_D60

D

DR_A_D61

D

DR_A_DQS#7

D

DR_A_DQS7

D

DR_A_D62

D

DR_A_D63

0.75VS

+

4

DDR3 SO-DIMM A
R

everse Type

M

EM_MA_RST# <6>

D

DR_A_CKE1 <6>

D

DR_A_CLK1 <6>

D

DR_A_CLK1# <6>

D

DR_A_BS1 <6>

D

DR_A_RAS# <6>

D

DR_A_SCS0# <6>

D

DR_A_ODT0 <6>

D

DR_A_ODT1 <6>

C

C

C

lose to JDDR3H.126

M

EM_MA_EVENT# <6>

F

CH_SDATA0 <11,24,28>

F

CH_SCLK0 <11,24,28>

3

D

DR_A_DQS[0..7] <6>

D

DR_A_DQS#[0..7] <6>

D

DR_A_D[0..63] <6>

D

DR_A_MA[0..15] <6>

DR_A_DM[0..7] <6>

D

1.5V

+

1

R

R

79

79

1K_0402_1%

1K_0402_1%

+

VREF_DQA

1

157

157

C

C

C

C

156

156

0

0
.1U_0402_16V7K

.1U_0402_16V7K

2

C

lose to JDDR3H.1

1.5V

+

1

C

C

148

1.5V

+

12

80

80

R

R

1K_0402_1%

1K_0402_1%

1

@

@

1

162

162

1

R

C

C

161

161

0

0

2

2
.2U_0402_6.3V6M

.2U_0402_6.3V6M

.1U_0402_16V7K

.1U_0402_16V7K

2

R

82

82

1K_0402_1%

1K_0402_1%

2

2

148

100U_1206_6.3V6K

100U_1206_6.3V6K

2

SE00000O000

L

ayout Note:

Place near JDDR3H

1.5V

+

C

C

176 10U_0603_6.3V6M

176 10U_0603_6.3V6M

C

C

174 10U_0603_6.3V6M

174 10U_0603_6.3V6M

2

C

C

173 10U_0603_6.3V6M

173 10U_0603_6.3V6M

C

C

171 10U_0603_6.3V6M

171 10U_0603_6.3V6M

2

167 10U_0603_6.3V6M

167 10U_0603_6.3V6M

C

C

166 10U_0603_6.3V6M

166 10U_0603_6.3V6M

C

C

1 2

179 0.1U_0402_16V4Z

179 0.1U_0402_16V4Z

C

C

1

C

C

178 0.1U_0402_16V4Z

178 0.1U_0402_16V4Z

1 2

185 0.1U_0402_16V4Z

185 0.1U_0402_16V4Z

C

C

1 2

180 0.1U_0402_16V4Z

180 0.1U_0402_16V4Z

C

C

2

12

@

@

1

2

2
.2U_0402_6.3V6M

.2U_0402_6.3V6M

2

12

12

1

12

1

12

2

81

81

R

R

1K_0402_1%

1K_0402_1%

2

Layout Note:
Place near JDDR3H.203 and 204

0.75VS

+

1 2

84 4.7U_0603_6.3V6K

84 4.7U_0603_6.3V6K

C

C

1 2

186 0.1U_0402_16V4Z

186 0.1U_0402_16V4Z

C

C

1 2

C

C

205 0.1U_0402_16V4Z

205 0.1U_0402_16V4Z

1

ecurity Classification

ecurity Classification

ecurity Classification

S

S

S

ssued Date

ssued Date

ssued Date

I

I

I

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

T

T

T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

013/01/22 2014/01/21

013/01/22 2014/01/21

013/01/22 2014/01/21

2

2

2

ompal Secret Data

ompal Secret Data

ompal Secret Data

C

C

C

eciphered Date

eciphered Date

eciphered Date

D

D

D

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

C

C

itle

itle

itle

T

T

T

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

ustom

ustom

ustom

C

C

C

Date: Sheet

Date: Sheet

2

Date: Sheet

C

DRIII-SODIMM0

DRIII-SODIMM0

DRIII-SODIMM0

D

D

D

A-9869P

A-9869P

A-9869P

L

L

L

.3

.3

.3

0

0

0

f

10 50Monday, February 04, 2013

f

10 50Monday, February 04, 2013

f

10 50Monday, February 04, 2013

o

o

1

o

A

1.5V

+

VREF_DQB

+

1 1

D

DR_B_CKE0<6>

D

DR_B_BS2<6>

2 2

D

DR_B_CLK0<6>

D

DR_B_CLK0#<6>

D

DR_B_BS0<6>

D

DR_B_WE#<6>

D

DR_B_CAS#<6>

D

DR_B_SCS1#<6>

3 3

3VS

+

1

4 4

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

D

DR_B_D0

D

DR_B_D1

D

DR_B_DM0

D

DR_B_D2

D

DR_B_D3

D

DR_B_D8

D

DR_B_D9

D

DR_B_DQS#1

D

DR_B_DQS1

D

DR_B_D10

D

DR_B_D11

D

DR_B_D16

D

DR_B_D17

D

DR_B_DQS#2

D

DR_B_DQS2

D

DR_B_D18

D

DR_B_D19

D

DR_B_D24

D

DR_B_D25

D

DR_B_DM3

D

DR_B_D26

D

DR_B_D27

D

DR_B_MA12

D

DR_B_MA9

D

DR_B_MA8

D

DR_B_MA5

D

DR_B_MA3

D

DR_B_MA1

D

DR_B_MA10

D

DR_B_MA13

D

DR_B_D37

D

DR_B_D36

D

DR_B_DQS#4

D

DR_B_DQS4

D

DR_B_D34

D

DR_B_D35

D

DR_B_D40

D

DR_B_D41

D

DR_B_DM5

D

DR_B_D42

D

DR_B_D43

D

DR_B_D48

D

DR_B_D49

D

DR_B_DQS#6

D

DR_B_DQS6

D

DR_B_D54

D

DR_B_D55

D

DR_B_D56

D

DR_B_D57

D

DR_B_DM7

D

DR_B_D58

D

DR_B_D59

0.75VS

+

208

208

C

C

DDR3H

DDR3H

J

J

1

REF_DQ

V

3

SS2

V

5

Q0

D

7

Q1

D

9

SS4

V

11

M0

D

13

SS5

V

15

Q2

D

17

Q3

D

19

SS7

V

21

Q8

D

23

Q9

D

25

SS9

V

27

QS#1

D

29

QS1

D

31

SS11

V

33

Q10

D

35

Q11

D

37

SS13

V

39

D

Q16

41

Q17

D

43

V

SS15

45

D

QS#2

47

D

QS2

49

V

SS18

51

D

Q18

53

D

Q19

55

V

SS20

57

D

Q24

59

D

Q25

61

V

SS22

63

D

M3

65

V

SS23

67

D

Q26

69

D

Q27

71

V

SS25

73

C

KE0

75

V

DD1

77

N

C1

79

B

A2

81

V

DD3

83

A

12/BC#

85

A

9

87

V

DD5

89

A

8

91

A

5

93

V

DD7

95

A

3

97

A

1

99

V

DD9

101

C

K0

103

C

K0#

105

V

DD11

107

A

10/AP

109

B

A0

111

V

DD13

113

W

E#

115

C

AS#

117

V

DD15

119

A

13

121

S

1#

123

V

DD17

125

N

CTEST

127

V

SS27

129

D

Q32

131

D

Q33

133

V

SS29

135

D

QS#4

137

D

QS4

139

V

SS32

141

D

Q34

143

D

Q35

145

V

SS34

147

D

Q40

149

D

Q41

151

V

SS36

153

D

M5

155

V

SS37

157

D

Q42

159

D

Q43

161

V

SS39

163

D

Q48

165

D

Q49

167

V

SS41

169

D

QS#6

171

D

QS6

173

V

SS44

175

D

Q50

177

D

Q51

179

V

SS46

181

D

Q56

183

D

Q57

185

V

SS48

187

D

M7

189

V

SS49

191

Q58

D

193

Q59

D

195

SS51

V

197

A0

S

199

DDSPD

V

201

A1

S

203

TT1

V

205

1

G

LCN_DAN06-K4806-0103

LCN_DAN06-K4806-0103

@

@

R

V

REF_CA

E

SS1

V

D
D
SS3

V
QS#0

D

QS0

D

SS6

V

D
D
SS8

V

Q12

D

Q13

D
SS10

V

D

ESET#

SS12

V

Q14

D

Q15

D
SS14

V

D

Q20

D

Q21

V

SS16

D

V

SS17
D

Q22

D

Q23

V

SS19
D

Q28

D

Q29

V

SS21

D

QS#3

D

QS3

V

SS24
D

Q30

D

Q31

V

SS26

C

KE1

V

DD2

V

DD4

V

DD6

V

DD8

V

DD10

C

C

V

DD12

B

R

AS#

V

DD14

O

DT0

V

DD16

O

DT1
N

V

DD18

V

SS28
D

Q36

D

Q37

V

SS30

D

V

SS31
D

Q38

D

Q39

V

SS33
D

Q44

D

Q45

V

SS35

D

QS#5

D

QS5

V

SS38
D

Q46

D

Q47

V

SS40
D

Q52

D

Q53

V

SS42

D

V

SS43
D

Q54

D

Q55

V

SS45
D

Q60

D

Q61

V

SS47

D

QS#7

D

QS7

SS50

V

Q62

D

Q63

D
SS52

V
VENT#

S

S

V

Q4
Q5

Q6
Q7

M1

M2

A

15

A

14

A

11
A

A
A

A
A

K1

K1#

A1

S

0#

C2

M4

M6

DA
CL

TT2

G

1.5V

+

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78
80
82
84
86

7

88
90

6

92

4

94
96

2

98

0

100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188

190
192
194
196
198
200
202
204

206

2

D

DR_B_D4

D

DR_B_D5

D

DR_B_DQS#0

D

DR_B_DQS0

D

DR_B_D6

D

DR_B_D7

D

DR_B_D12

D

DR_B_D13

D

DR_B_DM1

D

DR_B_D14

D

DR_B_D15

D

DR_B_D20

D

DR_B_D21

D

DR_B_DM2

D

DR_B_D22

D

DR_B_D23

D

DR_B_D28

D

DR_B_D29

D

DR_B_DQS#3

D

DR_B_DQS3

D

DR_B_D30

D

DR_B_D31

D

DR_B_MA15

D

DR_B_MA14

D

DR_B_MA11

D

DR_B_MA7

D

DR_B_MA6

D

DR_B_MA4

D

DR_B_MA2

D

DR_B_MA0

+

VREF_CAB

D

DR_B_D32

D

DR_B_D33

D

DR_B_DM4

D

DR_B_D38

D

DR_B_D39

D

DR_B_D44

D

DR_B_D45

D

DR_B_DQS#5

D

DR_B_DQS5

D

DR_B_D46

D

DR_B_D47

D

DR_B_D52

D

DR_B_D53

D

DR_B_DM6

D

DR_B_D50

D

DR_B_D51

D

DR_B_D60

D

DR_B_D61

D

DR_B_DQS#7

D

DR_B_DQS7

D

DR_B_D62

D

DR_B_D63

0.75VS

+

B

DDR3 SO-DIMM B
R

everse Type

M

EM_MB_RST# <6>

D

DR_B_CKE1 <6>

D

DR_B_CLK1 <6>

D

DR_B_CLK1# <6>

D

DR_B_BS1 <6>

D

DR_B_RAS# <6>

D

DR_B_SCS0# <6>

D

DR_B_ODT0 <6>

D

DR_B_ODT1 <6>

C

lose to JDDR3L.126

M

EM_MB_EVENT# <6>

F

CH_SDATA0 <10,24,28>

F

CH_SCLK0 <10,24,28>

C

D

DR_B_DQS#[0..7] <6>

D

DR_B_DQS[0..7] <6>

D

DR_B_D[0..63] <6>

D

DR_B_MA[0..15] <6>

DR_B_DM[0..7] <6>

D

1.5V

+

1

83

83

R

R

1K_0402_1%

1K_0402_1%

+

VREF_DQB

1

184

184

C

C

C

C

0

0
.1U_0402_16V7K

.1U_0402_16V7K

2

2

1

@

@

1

183

183

2

2
.2U_0402_6.3V6M

.2U_0402_6.3V6M

84

84

R

R

1K_0402_1%

1K_0402_1%

2

2

D

E

Close to JDDR3L.1

1.5V

+

12

86

86

R

R

1K_0402_1%

1K_0402_1%

1

@

@

1

1

188

188

187

187

C

C

C

C

2

2

0

0

.2U_0402_6.3V6M

.2U_0402_6.3V6M

.1U_0402_16V7K

.1U_0402_16V7K

2

94

94

R

R

1K_0402_1%

1K_0402_1%

2

2

L

ayout Note:

Place near JDDR3L

1.5V

+

195 10U_0603_6.3V6M

195 10U_0603_6.3V6M

C

C

2

189 10U_0603_6.3V6M

189 10U_0603_6.3V6M

C

C

181 10U_0603_6.3V6M

181 10U_0603_6.3V6M

C

C

2

177 10U_0603_6.3V6M

177 10U_0603_6.3V6M

C

C

175 10U_0603_6.3V6M

175 10U_0603_6.3V6M

C

C

172 10U_0603_6.3V6M

172 10U_0603_6.3V6M

C

C

1 2

190 0.1U_0402_16V4Z

190 0.1U_0402_16V4Z

C

C

1 2

191 0.1U_0402_16V4Z

191 0.1U_0402_16V4Z

C

C

1 2

192 0.1U_0402_16V4Z

192 0.1U_0402_16V4Z

C

C

1

193 0.1U_0402_16V4Z

193 0.1U_0402_16V4Z

C

C

Layout Note:

12

1

12

1

12

12

2

Place near JDDRL.203 and 204

0.75VS

+

@

@

12

197 10U_0603_6.3V6M

197 10U_0603_6.3V6M

C

C

2

1

194 0.1U_0402_16V4Z

194 0.1U_0402_16V4Z

C

C

1 2

206 0.1U_0402_16V4Z

206 0.1U_0402_16V4Z

C

C

1.5V

+

ecurity Classification

ecurity Classification

ecurity Classification

S

S

S

ssued Date

ssued Date

ssued Date

I

I

I

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

T

T

T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

013/01/22 2014/01/21

013/01/22 2014/01/21

013/01/22 2014/01/21

2

2

2

ompal Secret Data

ompal Secret Data

ompal Secret Data

C

C

C

eciphered Date

eciphered Date

eciphered Date

D

D

D

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

C

C

Title

itle

itle

T

T

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

ustom

ustom

ustom

C

C

C

Date: Sheet

Date: Sheet

D

Date: Sheet

C

DRIII-SODIMM1

DRIII-SODIMM1

DRIII-SODIMM1

D

D

D

A-9869P

A-9869P

A-9869P

L

L

L

.3

.3

.3

0

0

0

f

11 50Monday, February 04, 2013

f

11 50Monday, February 04, 2013

f

11 50Monday, February 04, 2013

o

o

E

o

A

P

P

CIE_ATX_C_GRX_P[3..0]<5>

P

CIE_ATX_C_GRX_N[3..0]<5>

1 1

2 2

3 3

C

LK_PCIE_VGA<23>

C

LK_PCIE_VGA#<23>

3.3-V tolerant

CIE_ATX_C_GRX_P[3..0]

P

CIE_ATX_C_GRX_N[3..0]

P

CIE_ATX_C_GRX_P0

P

CIE_ATX_C_GRX_N0

P

CIE_ATX_C_GRX_P1

P

CIE_ATX_C_GRX_N1

P

CIE_ATX_C_GRX_P2

P

CIE_ATX_C_GRX_N2

P

CIE_ATX_C_GRX_P3

P

CIE_ATX_C_GRX_N3

C

LK_PCIE_VGA

C

LK_PCIE_VGA#

VGA@

VGA@

R

R

V2 1K_0402_5%

V2 1K_0402_5%

G

PU_RST#

12

12

VGA@

VGA@

R

R
100K_0402_5%

100K_0402_5%

V212

V212

A

A38
Y

Y

W

W

V

V

U

U

T

T

R

R

P

P

N

N
M

M

L

L
K

K
J

J

H

H
G

G

F

F
E

A

B35

A

A36

A

H16

A

A30

37

35
36

38
37

35
36

38
37

35
36

38
37

35
36

38
37

35
36

38
37

35
36

38
37

35
36

38
37

35
37

U

U

V1A

V1A

PCIE_RX0P
PCIE_RX0N

PCIE_RX1P
PCIE_RX1N

PCIE_RX2P
PCIE_RX2N

PCIE_RX3P
PCIE_RX3N

PCIE_RX4P
PCIE_RX4N

PCIE_RX5P
PCIE_RX5N

PCIE_RX6P
PCIE_RX6N

PCIE_RX7P
PCIE_RX7N

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

CLOCK

CLOCK

PCIE_REFCLKP
PCIE_REFCLKN

TEST_PG

PERSTB

B

P

P

ART 1 0F 9

ART 1 0F 9

CI EXPRESS INTERFACE

CI EXPRESS INTERFACE
P

P

SUN-PRO M2_FCBGA962VGA@

SUN-PRO M2_FCBGA962VGA@

PCIE_TX0P
PCIE_TX0N

PCIE_TX1P
PCIE_TX1N

PCIE_TX2P
PCIE_TX2N

PCIE_TX3P
PCIE_TX3N

PCIE_TX4P
PCIE_TX4N

PCIE_TX5P
PCIE_TX5N

PCIE_TX6P
PCIE_TX6N

PCIE_TX7P
PCIE_TX7N

CALIBRATION

CALIBRATION

PCIE_CALR_TX

PCIE_CALR_RX

C

P

CIE_GTX_C_ARX_P[3..0]

P

CIE_GTX_C_ARX_N[3..0]

.1U_0402_16V7K

33

Y

P

CIE_GTX_ARX_P0

32

Y

P

CIE_GTX_ARX_N0

33

W

P

CIE_GTX_ARX_P1

32

W

P

CIE_GTX_ARX_N1

33

U

P

CIE_GTX_ARX_P2

32

U

P

CIE_GTX_ARX_N2

30

U

P

CIE_GTX_ARX_P3

29

U

P

CIE_GTX_ARX_N3

33

T

32

T

30

T

29

T

33

P

32

P

30

P

29

P

33

N

NC

32

N

NC

30

N

NC

29

N

NC

33

L

NC

32

L

NC

30

L

NC

29

L

NC

33

K

NC

32

K

NC

33

J

NC

32

J

NC

30

K

NC

29

K

NC

33

H

NC

H

32

NC

Y

30

V

GA_PCIE_CALRP

Y

29

V

GA_PCIE_CALRN

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

A

C Coupling Capa citor
PCIeR Gen1 and Gen2 only: Rec ommended value is 100 nF 10%.
PCIeR Gen3: Rec ommended value is 220 nF 10%.

1 2

V1 1.69K_0402_ 1%VGA@

V1 1.69K_0402_ 1%VGA@

R

R

1

V3 1K_04 02_1%VGA@

V3 1K_04 02_1%VGA@

R

R

P

CIE_GTX_C_ARX_P[3..0] <5>

P

CIE_GTX_C_ARX_N[3..0] <5>

1 2

V1

VGA@

V1

C

C

C

C

C

C

C

C

C

C
C

C

C

C

C

C

VGA@

2

1

V2

VGA@

V2

VGA@

1 2

V3

VGA@

V3

VGA@

2

1

V4

VGA@

V4

VGA@

1 2

V5

VGA@

V5

VGA@

2

1

V6

VGA@

V6

VGA@

2

1

V7

VGA@

V7

VGA@

1 2

V8

VGA@

V8

VGA@

2

P

CIE_GTX_C_ARX_P0

P

CIE_GTX_C_ARX_N0

P

CIE_GTX_C_ARX_P1

P

CIE_GTX_C_ARX_N1

P

CIE_GTX_C_ARX_P2
P

CIE_GTX_C_ARX_N2

P

CIE_GTX_C_ARX_P3

P

CIE_GTX_C_ARX_N3

+

0.95VGS

+

0.95VGS

D

L

VDS Interface

V1D

V1D

U

U

ART 7 0F 9

ART 7 0F 9

P

P

LVDS CONTROL

LVDS CONTROL

VTMDP

VTMDP
L

L

SUN-PRO M2_FCBGA962VGA@

SUN-PRO M2_FCBGA962VGA@

RSVD/VARY_BL

RSVD/DIGON

TXCBP_DPB3P
TXCBM_DPB3N

TX3P_DPB2P
TX3M_DPB2N

TX4P_DPB1P
TX4M_DPB1N

TX5P_DPB0P
TX5M_DPB0N

NC#AF35

NC#AG36

TXCAP_DPA3P
TXCAM_DPA3N

TX0P_DPA2P
TX0M_DPA2N

TX1P_DPA1P
TX1M_DPA1N

TX2P_DPA0P
TX2M_DPA0N

K27

A

J27

A

K35

A

L36

A

J38

A

K37

A

H35

A

J36

A

G38

A

H37

A

F35

A

G36

A

P34

A

R34

A

W37

A

U35

A

R37

A

U39

A

P35

A

R35

A

N36

A

NC

P37

A

NC

E

+

3VS

VGA@

VGA@

5

U

U

V13

4 4

P

XS_RST#<24>

A

PU_PCIE_RST#<23,28,30>

A

V13

2

P

B

4

Y

1

A

G

3

MC74VHC1G08DFT2G SC70 5P

MC74VHC1G08DFT2G SC70 5P

G

PU_RST#

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2

2

2

013/01/22 2014/01/21

013/01/22 2014/01/21

013/01/22 2014/01/21

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

D

Date: Sheet

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

P

P

P

CIE/LVDS

CIE/LVDS

CIE/LVDS

LA-9869P

LA-9869P

LA-9869P

E

0

0

0

.3

.3

.3

o

o

o

f

12 50Monday, February 04, 2013

f

12 50Monday, February 04, 2013

f

12 50Monday, February 04, 2013

A

+

3VGS

1 1

R

R

V12

V12

1 8

J

TAG_TRSTB

7

2
3 6
4 5

10K_8P4R_5%

10K_8P4R_5%

+

3VGS

2 2

+

3VGS

3 3

4 4

10K_8P4R_5%

10K_8P4R_5%

CHECK VR
IF VR Suport PSI# and DPRSLPVR PU 10K
to +3VGS:
PSI# :Low load current flag
DPRSLPVR : Deeper sleep enable flag

VGA@

VGA@

R

R

V14

V14

1

10K_0402_5%

10K_0402_5%

GENERIC_X
Stereo-sync signal.
Indicates left/right frame, or top/bottom field.
Can be left unconnected if not used.

Enable JTAG access

R

R

V7

V7

5.11K_0402_5%

5.11K_0402_5%

@

@

1 2

1 2

T

Reserved signal, for normal ASIC operation.

R

R

V9

V9

1K_0402_5%

1K_0402_5%

VGA@

VGA@

T

SVDD MarsCRB Design

120ohm 1 1

0.1u 1 1
1u 1 1
10u 1 1

J

TAG_TDI

J

TAG_TMS

J

TAG_TCK

@

@

R

V13

V13

R

1

8

G

PIO_16

2 7

G

PIO_28_FDO

6

3

V

GA_SMB_CK2

4 5

V

GA_SMB_DA2

VGA@

VGA@

G

PU_DPRSLPVR<46>

R

R

V11 10K_0402_5%

V11 10K_0402_5%

1 2

G

PU_VID5<46>

G

PU_VID1<46>

G

PU_VID2<46>

G

PU_VID3<46>

G

PU_VID4<46>

PX_EN :
High (3.3 V) switches the regulators
off (enter BACO mode).
Low (0 V) switches the regulators
on. (Default)

M

LPS

D

isable

H

E

nable

L

L

V3

VGA@LV3

VGA@
1 2

BLM15BD121SN1D_0402

BLM15BD121SN1D_0402

A

2

ESTEN

+

1.8VGS

G

C

LKREQ_PEG#<24>

G

PU_DOWN#<34>

PIO_28_FDO

VGA@

VGA@

R

R

V8

V8

+

TSVDD

1

V17

V17
C

C

2

VGA@

VGA@

V

GA_SMB_CK2

V

GA_SMB_DA2

G

PU_DPRSLPVR

G

PU_VID5

T

V1TV1

G

PU_GPIO8

TV2T

V2

G

PU_GPIO9

T

V3TV3

G

PU_GPIO10

G

PU_VID1

G

10K_0402_5%@

10K_0402_5%@

1 2

G

PU_VID2

TV4T

V4

G

PU_GPIO21

TV5T

V5

G

PU_GPIO22

C

LKREQ_PEG#

G

PU_VID3

G

PU_VID4

T

V9TV9

P

J

TAG_TRSTB

J

TAG_TDI

J

TAG_TCK

J

TAG_TMS

V7

TV7T

J

TAG_TDO

G

PIO_28_FDO

(

1.8V@13mA TSVDD)

+

1

1

V18

V18

V19

V19
C

C

C

C

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

VGA@

VGA@

VGA@

VGA@

PIO_16

X_EN

TSVDD

U

U

V1B

V1B

PART 2 0F 9

PART 2 0F 9

MUTI GFX

MUTI GFX

D29

A

ENLK_CLK

G

C29

A

ENLK_VSYNC

G

J21

A

WAPLOCKA

S

K21

A

WAPLOCKB

S

R8

A

C

N

U8

A

C

N

P8

A

BG_CNTL0

D

W8

A

C

N

R3

A

C

N

R1

A

C

N

U1

A

BG_DATA0

D

U3

A

BG_DATA1

D

W3

A

BG_DATA2

D

P6

A

BG_DATA3

D

W5

A

BG_DATA4

D

U5

A

BG_DATA5

D

R6

A

BG_DATA6

D

W6

A

BG_DATA7

D

U6

A

BG_DATA8

D

T7

A

BG_DATA9

D

V7

A

BG_DATA10

D

N7

A

BG_DATA11

D

V9

A

BG_DATA12

D

T9

A

BG_DATA13

D

R10

A

BG_DATA14

D

W10

A

BG_DATA15

D

U10

A

BG_DATA16

D

P10

A

BG_DATA17

D

V11

A

BG_DATA18

D

T11

A

BG_DATA19

D

R12

A

BG_DATA20

D

W12

A

BG_DATA21

D

U12

A

BG_DATA22

D

P12

A

BG_DATA23

D

J23

A

MBCLK

S

H23

A

MBDATA

S

K26

A

CL

S

J26

A

DA

S

G

G

ENERAL PURPOSE I/O

ENERAL PURPOSE I/O

H20

A

PIO_0

G

H18

A

PIO_1

G

N16

A

PIO_2

G

H17

A

PIO_5_AC_BATT

G

J17

A

PIO_6_TACH

G

K17

A

PIO_7_BLON

G

J13

A

PIO_8_ROMSO

G

H15

A

PIO_9_ROMSI

G

J16

A

PIO_10_ROMSCK

G

K16

A

PIO_11

G

L16

A

PIO_12

G

M16

A

PIO_13

G

M14

A

PIO_14_HPD2

G

A

M13

G

PIO_15_PWRCNTL_0

A

K14

G

PIO_16

A

G30

G

PIO_17_THERMAL_INT

A

N14

G

PIO_18_HPD3

A

M17

G

PIO_19_CTF

A

L13

G

PIO_20_PWRCNTL_1

A

J14

G

PIO_21

A

K13

G

PIO_22_ROMCSB

A

N13

C

LKREQB

A

G32

G

PIO_29

A

G33

G

PIO_30

A

J19

G

ENERICA

A

K19

G

ENERICB

A

J20

G

ENERICC

A

K20

G

ENERICD

A

J24

G

ENERICE_HPD4

A

H26

G

ENERICF_HPD5

A

H24

G

ENERICG_HPD6

A

C30

C

EC_1

A

K24

H

PD1

A

H13

D

BG_VREFG

A

L21

P

X_EN

A

D28

T

ESTEN

A

M23

J

TAG_TRSTB

A

N23

J

TAG_TDI

A

K23

J

TAG_TCK

A

L24

J

TAG_TMS

A

M24

J

TAG_TDO

THERMAL

THERMAL

A

F29

D

PLUS

A

G29

D

MINUS

A

K32

G

PIO_28_FDO

A

L31

T

S_A

A

J32

T

SVDD

A

J33

T

SVSS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

DEBUG

DEBUG

DPA

DPA

DPB

DPB

DPC

DPC

DPD

DPD

S

S

MBus

MBus

I2C

I2C

DAC1

DAC1

ML

ML

PS

PS

B

B

ACO

ACO

DDC/

DDC/

AUX

AUX

D
DCVGADATA

D

SUN-PRO M2_FCBGA962VGA@

SUN-PRO M2_FCBGA962VGA@

N
N
N

DC1CLK

D
DC1DATA

D

DC2CLK

D

DC2DATA

D

DCVGACLK

A

A

A

H
V

A

DD1DI

V
V

C_SVI2
C_SVI2
C_SVI2

A
A

A
A

B

C

D

E

MLPS

M

P

U24

A

C

N

V23

A

C

N

T25

A

C

N

R24

A

C

N

U26

A

C

N

V25

A

C

N

T27

A

C

N

R26

A

C

N

R30

A

C

N

T29

A

C

N

V31

A

C

N

U30

A

C

N

R32

A

C

N

T31

A

C

N

T33

A

C

N

U32

A

C

N

U14

A

C

N

V13

A

C

N

T15

A

C

N

R14

A

C

N

U16

A

C

N

V15

A

C

N

T17

A

C

N

R16

A

C

N

U20

A

C

N

T19

A

C

N

T21

A

C

N

R20

A

C

N

U22

A

C

N

V21

A

C

N

T23

A

C

N

R22

A

C

N

D39

A

R

D37

A

VSSN

E36

A

G

D35

A

VSSN

F37

A

B

E38

A

VSSN

C36

A

SYNC

C38

A

SYNC

B34

A

SET

R

D34

A

VDD

A

E34

A

VSSQ

C33

A

C34

A

SS1DI

13

V

C

N

13

U

C

N

F33

A

C

N

F32

A

C

N

A29

A

C

N

G21

A

C

N

C32

A

C

N

C31

A

D30

A

D32

A

M34

A

P

S_0

S_0

P

D31

A

P

S_1

S_1

P

G31

A

P

S_2

S_2

P

D33

A

P

S_3

S_3

P

M26

A

N26

A

M27

A

UX1P

L27

A

UX1N

M19

A

L19

A

N20

A

UX2P

M20

A

UX2N

L30

A

C

N

M30

A

C

N

L29

A

C

N

M29

A

C

N

N21

A

C

N

M21

A

C

N

K30

A

C

N

K29

A

C

N

J30

A

J31

A

B

M

ars MLPS configuration

Bits[5:1]

xx000

xx001

xx010

xx011

xx100

xx101

xx110

xx111

00xxx

01xxx

10xxx

11xxx

P

in Name

G

PIO_0

G

PIO_5_AC_BATT

GPIO_6

GPIO_15_PWRCNTL_0

GPIO_20_PWRCNTL_1

GPIO_29

GPIO_30

GPIO_8_ROMSO

GPIO_9_ROMSI

GPIO_10_ROMSCK

GPIO_22_ROMCSB

GPIO_17_THERMAL_INT

GPIO_19_CTF

GPIO_21

GPIO_28_FDO

CLKREQB

PX_EN

PD(1%) CapPU(1%)

NC 4.75k

8.45k 2.00k

4.53k 2.00k

6.98k 4.99k

4.53k 4.99k

3.24k 5.62k

3.40k 10.0k

4.75k NC

T

ype PD/PU Des cription

I/O

3.3 V
(VDDR3)

I/O

3.3 V
(VDDR3)

I/O

3.3 V
(VDDR3)

I

3.3 V
(VDDR3)

O

3.3 V
(VDDR3)

I/O

3.3 V
(VDDR3)

O

3.3 V
(VDDR3)

I/O

3.3 V
(VDDR3)

I/O

3.3 V
(VDDR3)

O

O PD

rimary Memory Aperture Size

Requested at PCI Configuration

S

ize of the Primary

Memory Apertures

1

28 MB

ROM_CONFIG [2:0]

256 MB

64 MB

Reserved

512 MB

680nF

82nF

10nF

NC

PD-reset

PD-reset

PD-reset

PD-reset

PD-reset

PD-reset

PD-reset

PD-reset

PD-reset

1 GB

2 GB

4 GB Not supported

Power-state indicator.
Permits the voltage regulator to activate power-saving
features.
IF VR Suport PSI# and DPRSLPVR PU 10K to +3VGS.
PSI# :Low load current flag
DPRSLPVR : Deeper sleep enable flag

(Optional) An input which allows the system to
request a fastpower reduction by setting
GPIO_5_AC_BATT to low (0 V). The resulting state
transition may disturb the display momentarily.
Power reductions that are less time critical
should use the standard software methods in order
to prevent display disturbances.

Voltage control signals for the core (VDDC and VDDCI).
At reset, these signals will be inputs with weak
internal pulldown resistors.
The VBIOS can define all voltage-control signals to be
either 3.3-V or open-drain outputs (all signals must
be the same type).
The output states (high/low) of these pins are
programmable for each AMD PowerPlay state when they
are used as voltage control signals.
Note: GPIO_29 and GPIO_30 are only available on 28-nm
ASICs, and are NC on earlier generation ASICs.

Serial-ROM output from ROM.
General purpose I/O or open-drain output.

Design: No use external VGA ROM, so use the test point.

Serial-ROM input to ROM.
General purpose I/O or open-drain output.

Serial-ROM clock to ROM.
General purpose I/O or open-drain output.

BIOS-ROM chip select.
Used to enable the ROM for ROM read and program
operations.

Design: No use external VGA ROM, so use the test
points.

Thermal monitor interrupt.
An input from an external temperature sensor (ALERTb).

Critical temperature fault (CTF) (active high) will
output 3.3 V if the on-die temperature sensor exceeds
a critical temperature so that the motherboard can
protect the ASIC from damage by removing power.
The CTF setpoint is 109 by default, and is
p

rogrammed during ASIC initialization. See the

advisory for AMD PowerPlay states for more details.

(Optional) Voltage control signal for the
memory-voltage regulator.
Note: This signal must be low (0 V) at reset
(failure to do so will prevent booting).

Disable MLPS: PU 10K ohm to 3.3V.
(Do not install for Mars)
Enable MLPS: PD 10K ohm to GND.
(Install for Mars)

Supports the CLKREQB feature for saving power to turn
on/off the REFCLK clock on the ASIC.

On/off regulator switch in AMD PowerXpress? (switchable
graphics) BACO mode.
High (3.3 V) switches the regulators off (enter BACO
mode).
Low (0 V) switches the regulators on. (Default)
PX_EN is tri-state before internal TEST_PG is asserted
and PERSTb is deasserted.

Not supported

Not supported

Not supported

℃℃℃℃

C

000

001

010

011

LPS Bit Strap Name Description Settings

ROM_CONFIG[0]

PS_0[1]

ROM_CONFIG[1]

PS_0[2]

ROM_CONFIG[2]

PS_0[3]

PS_0[4] N/A

STRAP_BIF_

PS_1[1]

GEN3_EN_A

PS_1[2] STRAP_BIF_

CLK_PM_EN

PS_1[3] N/A Reserved for internal use only. Must be 0 at reset.

PS_1[4] TX_PWRS_ENB

PS_1[5] TX_DEEMPH_EN

PS_2[1]

N/A

PS_2[2]

N/A

PS_2[3] BIOS_ROM_EN

PS_2[4] BIF_VGA_DIS

PS_2[5] N/A Reserved.

P

S_3[1]

BOARD_CONFIG[0]

PS_3[2]

BOARD_CONFIG[1]

PS_3[3]

BOARD_CONFIG[2]

PS_0[5]

AUD_PORT_CONN_

PS_3[4]

PINSTRAP[0]

PS_3[5]

AUD_PORT_CONN_
PINSTRAP[1]

AUD_PORT_CONN_
PINSTRAP[2]

For MEMCLK 1GHZ Brand Description Comment PS_3[3:1] R_pu (ohm) R_pd (ohm)

For MEMCLK 900MHZ Brand Description Comment PS_3[3:1] R_pu (ohm) R_pd (ohm)

M

LPS Strap

1

1

PS_0[5:1]

1 1

P

S_1[5:1]

0 0

PS_2[5:1]

1 1

PS_3[5:1]

P

S_0

P

S_1

P

S_2

P

S_3

@

@

V

V

GA@

GA@

1

1

C

C

C

C

C

C

V22

V22

V21

V21

V20

V20

2

2

.68U_0402_10V6K

.68U_0402_10V6K

.01U_0402_16V7K

.01U_0402_16V7K
0

0

0

0

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

L

egacy

G

PIO[13:11]

GENLK_VSYNC

GPIO_2

GPIO_8

If BIOS_ROM_EN = 1, ROM_CONFIG[2:0] define the ROM type. If BIOS_ROM_EN = 0,
ROM_CONFIG[2:0] define the primary memory-aperture size. Refer to current
databooks for details.

R

eserved for internal use only. Must be 1 at reset.

Re-defined strap to indicate PCIe GEN3 capability.
1 = PCIe GEN3 supported.
0 = PCIe GEN3 not supported.

Determines whether or not the PCIe reference clock power
management capability is reported in the PCI configuration space
(otherwise known as CLKREQB).
0 = The CLKREQB power management capability is disabled
1 = The CLKREQB power management capability is enabled

GENLK_CLK

GPIO_0

GPIO_1

N/A

N/A

GPIO_22

GPIO_9

Transmitter (Tx) power savings enable.
0 = 50% Tx output swing.
1 = Full Tx output swing.

PCI EXPRESS transmitter, deemphasis enable.
0 = Tx deemphasis disabled.
1 = Tx deemphasis enabled.

Reserved.

Reserved.

To enable the external BIOS ROM device.
0 = Disable the external BIOS ROM device.
1 = Enable the external BIOS ROM device.

VGA disable determines whether or not the card will be recognized as the
system's VGA controller.
0 = VGA controller capacity enabled.
1 = The device will not be recognized as the system’s VGA controller.

N/A

N/A

N/A

gDDR3-2Gbit

gDDR3-2Gbit

Board configuration related strapping (such as memory ID).

Together with PS_0[5] form the three-bit strap option to indicate the number of
audio-capable display outputs. In a given ASIC there are as many endpoints as
there are digital display outputs, though not all outputs are audio capable.
111 = No usable endpoints.
110 = One usable endpoint.
101 = Two usable endpoints.
100 = Three usable endpoints.
011 = Four usable endpoints.
010 = Five usable endpoints.
001 = Six usable endpoints.
000 = All endpoints are usable.

skHynix

H5TQ2G63DFR-N0C

Samsung

K4W2G1646E-BC1A

skHynix

H5TQ2G63DFR-11C

Micron

MT41K128M16JT-107G:K

Samsung K4W2G1646E-BC11 1.5V/900MHz 111 4750 NC

C

B

its[3:1]

0

0 1

0

0 1

0 0 0

X

X X

M

apping to VRAM type please refer to page 6

@

@

@

@

1

C

C

V23

V23

2

.01U_0402_16V7K

.01U_0402_16V7K
0

0

R

apacitorBits[5:4]

_pu R_pd

NC

8.45K 2K

8

NC

.45K

NC

X

1

@

@

R

R

V21

V21

8.45K_0402_1%

8.45K_0402_1%

2

12

VGA@

VGA@

V28

V28

R

R

4.75K_0402_1%

4.75K_0402_1%

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

2K

4.75K

X

1

8.45K_0402_1%

8.45K_0402_1%

2

1

4.75K_0402_1%

4.75K_0402_1%

2

Deciphered Date

Deciphered Date

Deciphered Date

680 nF

NC

@

@

V20

V20

R

R

8.45K_0402_1%

8.45K_0402_1%

@

@

1

V27

V27

R

R

2K_0402_1%

2K_0402_1%

2

.01U_0402_16V7K

.01U_0402_16V7K
0

0

2

2

2

013/01/22 2014/01/21

013/01/22 2014/01/21

013/01/22 2014/01/21

D

@

@

R

R

VGA@

VGA@

R

R

001

1

0

0

0

1

1

0

0

0

0

0

Base on
VRAM ID

111

1.5V/1GHz

1.5V/1GHz

1.5V/900MHz

1.35V-1.5V/900MHz

12

VGA@

VGA@

R

R

V23

V23

V22

V22

8.45K_0402_1%

8.45K_0402_1%

12

VGA@

VGA@

R

R

V68

V68

V30

V30

2K_0402_1%

2K_0402_1%

+

1.8VGS

000

111

1

2

12

V

GA_SMB_CK2

V

GA_SMB_DA2

NC

4750

4750

000

001

DMN66D0LDW-7 2N_SOT363-6

DMN66D0LDW-7 2N_SOT363-6

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheetof

Date: Sheetof

Date: Sheetof

NC

NC

4750

8450

2000

+

3VGS

2

VGA@

VGA@

61

5

Q

Q

V1A

V1A

4

3

Q

V1B

VGA@QV1B

VGA@

DMN66D0LDW-7 2N_SOT363-6

DMN66D0LDW-7 2N_SOT363-6

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

M

M

M

ain_MSIC

ain_MSIC

ain_MSIC

L

L

L

A-9869P

A-9869P

A-9869P

E

E

E

13 50Monday, February 04, 2013

13 50Monday, February 04, 2013

13 50Monday, February 04, 2013

C_SMB_CK2 <34,35>

C_SMB_DA2 <34,35>

0

0

0

.3

.3

.3

A

M

PLL_PVDD MarsCRB Design

1 1

2 2

220ohm 1 1

0.1u 1 1
1u 1 1

2.2u 1 1

S

PLL_PVDD MarsCRB Design

120ohm 1 1

0.1u 1 1
1u 1 1

2.2u 1 1

SPLL_VDDC MarsCRB Design
120ohm 1 1

0.1u 1 1
1u 1 1

2.2u 1 1

+

1.8VGS

L

1 2

BLM15BD121SN1D_0402

BLM15BD121SN1D_0402

+

1.8VGS

L

V8

1

BLM15BD121SN1D_0402

BLM15BD121SN1D_0402

+

0.95VGS

L

1

BLM15BD121SN1D_0402

BLM15BD121SN1D_0402

B

+

MPV18

(

V7

VGA@LV7

VGA@

VGA@LV8

VGA@

2

V9

VGA@LV9

VGA@

2

MPLL_PVDD:1.8V@130mA )

V79

V79

V78

V78

1

1

C

C

C

C

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V7K

0.1U_0402_16V7K

VGA@

VGA@

VGA@

VGA@

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

+

SPV18

(SPLL_PVDD:1.8V@75mA )

V81

V81

V82

V82

1

1

C

C

C

C

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V7K

0.1U_0402_16V7K

VGA@

VGA@

VGA@

VGA@

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

+

SPLL_VDDC

(SPLL_VDDC:0.95V@100mA )

V92

V92

V93

V93

1

1

C

C

C

C

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V7K

0.1U_0402_16V7K

VGA@

VGA@

VGA@

VGA@

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

V80

V80

1

C

C

2

VGA@

VGA@

V83

V83

1

C

C

2

VGA@

VGA@

V94

V94

1

C

C

2

VGA@

VGA@

+

MPV18

+

SPV18

+

SPLL_VDDC

C

H

7

H

8

A

M10

A

N9

A

N10

A

F30

A

F31

U

U

V1C

V1C

MPLL_PVDD
MPLL_PVDD

SPLL_PVDD

SPLL_VDDC

SPLL_PVSS

NC_XTAL_PVDD
NC_XTAL_PVSS

P

P

ART 9 0F 9

ART 9 0F 9

D

A

V33

V

XTALIN

XTALOUT

XO_IN

LLS/XTAL

LLS/XTAL
P

P

SUN-PRO M2_FCBGA962VGA@

SUN-PRO M2_FCBGA962VGA@

XO_IN2

CLKTESTA
CLKTESTB

GA_X1

A

U34

X

TALOUT

A

W34

A

W35

A

K10

D

ebug Only, for clock observat ion

A

L10

As short as pos sible

V

GA_X1 <29>

V24

V24

C

C

15P_0402_50V8J

15P_0402_50V8J

NOGCLK@

NOGCLK@

NOGCLK@

NOGCLK@

1

R

R

V31 1M_0402_5%

V31 1M_0402_5%

V1

V1

Y

Y

4

C

N

1

V

GA_X1

2

1

O

27MHZ 10PF +-20PPM X3G027000DA1H

27MHZ 10PF +-20PPM X3G027000DA1H

NOGCLK@

NOGCLK@

E

2

3

X

TALOUT

SC

O

2

SC

C

N

2

V25

V25

C

C
15P_0402_50V8J

15P_0402_50V8J

1

NOGCLK@

NOGCLK@

+

A

1.5V

VGA@

VGA@

V3

V3

Q

Q

8

D

7

D

6

D

5

D

FDS6676AS_SO8

FDS6676AS_SO8

3 3

4 4

+

1.5VGS

V

1

S

2

S

3

S

4

G

1

1

V49

V49

V106

V106

R

R

C

C

2

VGA@

VGA@

2

VGA@

VGA@

820K_0402_5%

820K_0402_5%

0.1U_0402_25V6

0.1U_0402_25V6

V

GA_PWRGD<24,43,46>

+1.5V to +1.5VGS

gs=10V,Id=14.5A ,Rds=6mohm

1 2

V48

V48

R

R

B

VGA@

VGA@

2

V

2

G

G

+

GA_PWRGD#

+

5VALW

12

13

Q

Q

V188

V188

B

100K_0402_5%

100K_0402_5%

D

D

S

S

220K_0402_5%

220K_0402_5%

61

VGA@

VGA@

Q

Q

V8A

V8A

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

V

GA_PWRGD#

R

R

V45

V45

V

V

GA@

GA@

70_0805_5%

70_0805_5%
4

4

1 2
3

VGA@

VGA@

Q

Q

V8B

V8B

5

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

4

R

R

V5530

V5530

VGA@

VGA@

2N7002KW_SOT323-3

2N7002KW_SOT323-3

VGA@

VGA@

+

3VGS

2

VGA@

VGA@

V43

R

R

V43

470_0805_5%

470_0805_5%

1
3

VGA@

VGA@

V9B

V9B

Q

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2

2

2

013/01/22 2014/01/21

013/01/22 2014/01/21

013/01/22 2014/01/21

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

Q

4

P

P

XS_PWREN<24,46,47>

XS_PWREN

D

5

P

XS_PWREN#

VGA@

VGA@

R

R

100K_0402_5%

100K_0402_5%

V

V

Q

Q

+

3VS to +3VGS

+

3VALW

@

@

V44

V44

GA@

GA@

V9A

V9A

2

1 2

61

47K_0402_5%

47K_0402_5%

1 2

N7002DW-T/R7_SOT363-6

N7002DW-T/R7_SOT363-6
2

2

2

C

C

0.1U_0402_16V7K

VGA@

VGA@

R

R

Date: Sheet

Date: Sheet

Date: Sheet

0.1U_0402_16V7K

1

V46

V46

2

V104

V104
C

C

1

VGA@

VGA@

0.01U_0402_25V7K

0.01U_0402_25V7K

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

+

3VS

V103

V103

C

C

C

Vgs=-4.5V,Id=3A ,Rds<97mohm

S

S

3

G

G

2

D

D

V4

V4

Q

Q

1

GA@

GA@

V

V

O3413_SOT23

O3413_SOT23
A

A

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

B

B

B

ACO POWER

ACO POWER

ACO POWER

L

L

L

A-9869P

A-9869P

A-9869P

E

+

3VGS

0

0

0

.3

.3

.3

o

o

o

f

14 50Monday, February 04, 2013

f

14 50Monday, February 04, 2013

f

14 50Monday, February 04, 2013

A

B

C

D

E

VDDR1 MarsCRB Design

0.01u 5 0

0.1u 5 0

2.2u 5 5
10u 3 3

VDD_CT MarsCRB Design
120ohm 1 1

1 1

0.1u 1 1
1u 1 1
10u 1 1

V

DDR3 Mars che ck list Design
120ohm 1 1
1u 3 2
10u 1 0

0.1u 0 1

+

1.8VGS

BLM15BD121SN1D_0402

BLM15BD121SN1D_0402

+

2 2

3 3

3VGS

BLM15BD121SN1D_0402

BLM15BD121SN1D_0402

L

V4

VGA@LV4

VGA@

1 2

L

L

V5

VGA@

V5

VGA@

1 2

+

1.5VGS

(VDDR1:1.5V@1.5A)

V37

V37

V35

V35

V36

V36

V34

V34

V33

V33

1

1

1

C

C

C

C

2

2

10U_0603_6.3V6M

VGA@

10U_0603_6.3V6M

VGA@

10U_0603_6.3V6M

VGA@

10U_0603_6.3V6M

VGA@

+

VDDC_CT

V51

V51

1

C

C

2

10U_0603_6.3V6M

VGA@

10U_0603_6.3V6M

VGA@

+

VDDR3

V42

V42

1

C

C

2

1U_0402_6.3V6K

1U_0402_6.3V6K

VGA@

VGA@

R

oute as differential pair

1

1

C

C

C

C

C

C

2

2

2

VGA@

VGA@

10U_0603_6.3V6M

VGA@

10U_0603_6.3V6M

VGA@

VGA@

VGA@

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

(

VDD_CT:1.8V@13mA )

V53

V52

V52

V53

1

1

C

C

C

C

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V7K

0.1U_0402_16V7K

VGA@

VGA@

VGA@

VGA@

(VDDR3:3.3V@25mA)

V55

V55

V54

V54

1

1

C

C

C

C

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V7K

0.1U_0402_16V7K

VGA@

VGA@

VGA@

VGA@

V

CC_GPU_SENSE<46>

V

SS_GPU_SENSE<46>

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

T

+

1.5VGS

V38

V38

V40

V40

V39

V39

1

1

1

C

C

C

C

C

C

2

2

2

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

+

VDDC_CT

+

VDDR3

V44TV44

U

U

V1E

V1E

P

P

ART 5 0F 9

ART 5 0F 9

MEM I/O

MEM I/O

C7

A

DDR1

V

D11

A

DDR1

V

F7

A

DDR1

V

G10

A

DDR1

V

J7

A

DDR1

V

K8

A

DDR1

V

L9

A

DDR1

V

11

G

DDR1

V

14

G

DDR1

V

17

G

DDR1

V

20

G

DDR1

V

23

G

DDR1

V

26

G

DDR1

V

29

G

DDR1

V

10

H

DDR1

V

7

J

DDR1

V

9

J

DDR1

V

11

K

DDR1

V

13

K

DDR1

V

8

K

DDR1

V

12

L

DDR1

V

16

L

DDR1

V

21

L

DDR1

V

23

L

DDR1

V

26

L

DDR1

V

7

L

DDR1

V

11

M

DDR1

V

11

N

DDR1

V

7

P

DDR1

V

11

R

DDR1

V

11

U

DDR1

V

7

U

DDR1

V

11

Y

DDR1

V

7

Y

DDR1

V

LEVEL

LEVEL

T

T

RANSLATION

RANSLATION

F26

A

DD_CT

V

F27

A

DD_CT

V

G26

A

DD_CT

V

A

G27

V

DD_CT

I/O

I/O

A

F23

V

DDR3

A

F24

V

DDR3

A

G23

V

DDR3

A

G24

V

DDR3

D

D

VP

VP

A

D12

V

DDR4

A

F11

V

DDR4

A

F12

V

DDR4

A

F13

V

DDR4

A

F15

V

DDR4

A

G11

V

DDR4

A

G13

V

DDR4

A

G15

V

DDR4

VOLTAGE

VOLTAGE
SENESE

SENESE

A

F28

F

B_VDDC

A

G28

F

B_VDDCI

A

H29

F

B_GND

N
N

CIE

CIE
P

P

BACO

BACO

CORE

CORE

ISOLATED

ISOLATED

SUN-PRO M2_FCBGA962VGA@

SUN-PRO M2_FCBGA962VGA@

C_BIF_VDDC
C_BIF_VDDC

CIE_PVDD

P

CIE_VDDC

P

CIE_VDDC

P

CIE_VDDC

P

CIE_VDDC

P

CIE_VDDC

P

CIE_VDDC

P

CIE_VDDC

P

CIE_VDDC

P

CIE_VDDC

P

CIE_VDDC

P

CIE_VDDC

P

CIE_VDDC

P

IF_VDDC

B

IF_VDDC

B

ORE I/O

ORE I/O
C

C

A31

A

C

N

A32

A

C

N

A33

A

C

N

A34

A

C

N

30

W

C

N

31

Y

C

N

28

V

29

W

B37

A

30

G

31

G

29

H

30

H

29

J

30

J

28

L

28

M

28

N

28

R

28

T

28

U

27

N

27

T

A15

A

DDC

V

A17

A

DDC

V

A20

A

DDC

V

A22

A

DDC

V

A24

A

DDC

V

A27

A

DDC

V

B16

A

DDC

V

B18

A

DDC

V

B21

A

DDC

V

B23

A

DDC

V

B26

A

DDC

V

B28

A

DDC

V

C17

A

DDC

V

C20

A

DDC

V

C22

A

DDC

V

C24

A

DDC

V

C27

A

DDC

V

D18

A

DDC

V

D21

A

DDC

V

D23

A

DDC

V

D26

A

DDC

V

F17

A

DDC

V

F20

A

DDC

V

F22

A

DDC

V

G16

A

DDC

V

G18

A

DDC

V

H22

A

DDC

V

H27

A

DDC

V

H28

A

DDC

V

26

M

DDC

V

24

N

DDC

V

18

R

DDC

V

21

R

DDC

V

23

R

DDC

V

26

R

DDC

V

17

T

DDC

V

20

T

DDC

V

22

T

DDC

V

24

T

DDC

V

16

U

DDC

V

18

U

DDC

V

21

U

DDC

V

23

U

DDC

V

26

U

DDC

V

17

V

DDC

V

20

V

DDC

V

22

V

DDC

V

24

V

DDC

V

27

V

DDC

V

16

Y

DDC

V

18

Y

DDC

V

21

Y

DDC

V

23

Y

DDC

V

26

Y

DDC

V

28

Y

DDC

V

A13

A

DDCI

V

B13

A

DDCI

V

C12

A

DDCI

V

C15

A

DDCI

V

D13

A

DDCI

V

D16

A

DDCI

V

15

M

DDCI

V

16

M

DDCI

V

18

M

DDCI

V

23

M

DDCI

V

13

N

DDCI

V

15

N

DDCI

V

17

N

DDCI

V

20

N

DDCI

V

22

N

DDCI

V

12

R

DDCI

V

13

R

DDCI

V

16

R

DDCI

V

12

T

DDCI

V

15

T

DDCI

V

15

V

DDCI

V

13

Y

DDCI

V

+

1.8VGS

+

0.95VGS

+

0.95VGS

+

VGA_CORE

+

VGA_CORE

+

VGA_CORE

(

V30

V30

1

C

C

2

1U_0402_6.3V6K

1U_0402_6.3V6K

VGA@

VGA@

V43

V43

1

C

C

2

1U_0402_6.3V6K

1U_0402_6.3V6K

VGA@

VGA@

(

V67

V67

1

C

C

2
@

@

1U_0402_6.3V6K

1U_0402_6.3V6K

PCIE_PVDD: 1.80V@100mA)

V31

V31

1

C

C

2

1U_0402_6.3V6K

1U_0402_6.3V6K

VGA@

VGA@

10U_0603_6.3V6M

10U_0603_6.3V6M

V44

V44

1

C

C

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

VGA@

VGA@

Maximum Current on +1.8VGS:

V32

V32

1

"Sun": ~0.5 A

C

C

2

VGA@

VGA@

P

CIE_VDDC:

0.95 V @ 1.88 A (PCIe Gen 2.0)

0.95 V @ 2.50 A (PCIe Gen 3.0)

V45

V45

V41

V41

V46

V46

1

1

1

C

C

C

C

C

C

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

VGA@

VGA@

VGA@

VGA@

VGA@

VGA@

BIF_VDDC: 0.95V@1.4A)

V68

V68

V69

V69

Maximum Current on +0.95VGS:

1

1

C

C

C

C

"Sun": ~4.0 A for PCIe GEN 3.0 designs
(estimated)

2

2
@

@

@

@

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

V47

V47

1

C

C

2

VGA@

VGA@

+

1U_0402_6.3V6K

1U_0402_6.3V6K

0.95VGS

+

1.8VGS

+

0.95VGS

V48

V48

V50

V50

V49

V49

1

1

1

C

C

C

C

C

C

2

2

2

VGA@

VGA@

10U_0603_6.3V6M

VGA@

10U_0603_6.3V6M

VGA@

10U_0603_6.3V6M

VGA@

10U_0603_6.3V6M

VGA@

P

CIE_PVDD Mars CRB Design
1u 2 2
10u 1 1

PCIE_VDDC Mar sCRB Design
1u 7 7
10u 2 2

B

IF_VDDC Mars check list D esign
1u 1 1
10u 1 1

+

VGA_CORE

N

eed check all power current and decoupling capacitors

4 4

A

after got SUN databook and reference schematic.

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONFI DENTIAL

HIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONFI DENTIAL

HIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONFI DENTIAL

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

B

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

C

2

2

2

013/01/22 2014/01/21

013/01/22 2014/01/21

013/01/22 2014/01/21

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

Title

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

D

Date: Sheet

ompal Electronics, Inc.

P

P

P

ower

ower

ower

L

L

L

A-9869P

A-9869P

A-9869P

E

1

1

1

5 50Monday, February 04, 2013

5 50Monday, February 04, 2013

5 50Monday, February 04, 2013

0

0

0

.3

.3

.3

o

o

o

f

f

f

A

V1H

V1H

U

U

ART 3 0F 9

ART 3 0F 9

P

P

GDDR5/DDR3

QA0_0

D

QA0_1

D

QA0_2

D

QA0_3

D

QA0_4

D

QA0_5

D

QA0_6

D

QA0_7

D

QA0_8

D

QA0_9

D

QA0_10

D

QA0_11

D

QA0_12

D

QA0_13

D

QA0_14

D

QA0_15

D

QA0_16

D

QA0_17

D

QA0_18

D

QA0_19

D

QA0_20

D

QA0_21

D

QA0_22

D

QA0_23

D

QA0_24

D

QA0_25

D

QA0_26

D

QA0_27

D

QA0_28

D

QA0_29

D

QA0_30

D

QA0_31

D

QA1_0

D

QA1_1

D

QA1_2

D

QA1_3

D

QA1_4

D

QA1_5

D

QA1_6

D

QA1_7

D

QA1_8

D

QA1_9

D

QA1_10

D

QA1_11

D

QA1_12

D

QA1_13

D

QA1_14

D

QA1_15

D

QA1_16

D

QA1_17

D

QA1_18

D

QA1_19

D

QA1_20

D

QA1_21

D

QA1_22

D

QA1_23

D

QA1_24

D

QA1_25

D

QA1_26

D

QA1_27

D

QA1_28

D

QA1_29

D

QA1_30

D

QA1_31

D

VREFDA

M

VREFSA

M

C

N

C

N

C

N

EM_CALRP0

M

C

N

C

N

VGA@

VGA@

GDDR5/DDR3

EMORY INTERFACE A

EMORY INTERFACE A
M

M

W

W

W

W

SUN-PRO M2_FCBGA962

SUN-PRO M2_FCBGA962

Compal P/N

SA00003YOG0

SA000065320

SA00005XB10

SA00005SH40

SA000068U20

M

AA0_0/MAA_0

M

AA0_1/MAA_1

M

AA0_2/MAA_2

M

AA0_3/MAA_3

M

AA0_4/MAA_4

M

AA0_5/MAA_5

M

AA0_6/MAA_6

M

AA0_7/MAA_7

M

AA1_0/MAA_8

M

AA1_1/MAA_9

M

AA1_2/MAA_10

M

AA1_3/MAA_11

M

AA1_4/MAA_12

M

AA1_5/MAA_BA2

M

AA1_6/MAA_BA0

M

AA1_7/MAA_BA1

W

CKA0_0/DQMA_0

CKA0B_0/DQMA_1

W

CKA0_1/DQMA_2

CKA0B_1/DQMA_3

W

CKA1_0/DQMA_4

CKA1B_0/DQMA_5

W

CKA1_1/DQMA_6

CKA1B_1/DQMA_7

E

DCA0_0/QSA_0

E

DCA0_1/QSA_1

E

DCA0_2/QSA_2

E

DCA0_3/QSA_3

E

DCA1_0/QSA_4

E

DCA1_1/QSA_5

E

DCA1_2/QSA_6

E

DCA1_3/QSA_7

D

DBIA0_0/QSA_0B

D

DBIA0_1/QSA_1B

D

DBIA0_2/QSA_2B

D

DBIA0_3/QSA_3B

D

DBIA1_0/QSA_4B

D

DBIA1_1/QSA_5B

D

DBIA1_2/QSA_6B

D

DBIA1_3/QSA_7B

A

DBIA0/ODTA0

A

DBIA1/ODTA1

C

C

R
R

C
C

CSA0B_0
C

SA0B_1

SA1B_0

C

SA1B_1

C

C
C

W
W

AA0_8/MAA_13

M

AA1_8/MAA_14

M

AA0_9/MAA_15

M

AA1_9/RSVD

M

37

C

35

C

35

A

34

E

32

G

33

D

32

F

32

E

31

D

30

F

30

C

30

A

28

1 1

2 2

1 2

V34 120_0402_1%VGA@

V34 120_0402_1%VGA@

R

R

3 3

GPU Type

SUN PRO-M2

SUN PRO-M2

SUN PRO-M2

SUN PRO-M2

SUN PRO-M2

Memory Bus Width

64bit

64bit

64bit

64bit

64bit

F

28

C

28

A

28

E

27

D

26

F

26

C

26

A

24

F

24

C

24

A

24

E

22

C

22

A

22

F

21

D

20

A

20

F

19

D

18

E

18

C

18

A

18

F

17

D

16

A

16

F

15

D

14

E

14

F

13

D

12

F

12

A

11

D

10

F

10

A

10

C

13

G

13

H

13

J

11

H

10

G

8

G

9

K
10

K

9

G

8

A

8

C

8

E

6

A

6

C

6

E

5

A

18

L

20

L

27

L

12

N
G12

A

27

M

12

M
H12

A

VRAM Vendor

Hynix

Hynix

Micron

Samsung

Samsung

B

G

24

J

23

H

24

J

24

H

26

J

26

H

21

G

21

H

19

H

20

L

13

G

16

J

16

H

16

J

17

H

17

A

32

C

32

D

23

E

22

C

14

A

14

E

10

D

9

C

34

D

29

D

25

E

20

E

16

E

12

J

10

D

7

A

34

E

30

E

26

C

20

C

16

C

12

J

11

F

8

J

21

G

19

H

27

C

LKA0

G

27

LKA0B

J

14

C

LKA1

H

14

LKA1B

K

23

ASA0B

K

19

ASA1B

K

20

ASA0B

K

17

ASA1B

K

24

K

27

13

M

16

K

21

K

KEA0

20

J

KEA1

26

K

EA0B

15

L

EA1B

23

H

19

J

21

M

20

M

Manufacturer P/N

H5TQ2G63DFR-11C

H5TQ2G63DFR-N0C

MT41K128M16JT-107G:K

K4W2G1646E-BC11

K4W2G1646E-BC1A

C

lose to pin Y12 and AA12

Z

Z

ZZ2

ZZ2

S

S

1G

1G

S1G@

S1G@

X

X

76xxxxxLx1

76xxxxxLx1

X76 P/N

X7648051L01

X7648051L02

X7648051L03

X7648051L04

X7648051L05

1.5VGS

+

12

V72

V72

R

R

40.2_0402_1%

40.2_0402_1%

VGA@

VGA@

100_0402_1%

100_0402_1%

VGA@

VGA@

Size per part

V73

V73

R

R

Z

Z

X

X

12

ZZ3

ZZ3

H

H

1G

1G

H1G@

H1G@

76xxxxxLx2

76xxxxxLx2

1

5mil

+

MVREFDB_SB

1

V159

V159

C

C
1U_0402_6.3V6K

1U_0402_6.3V6K

VGA@

VGA@

2

ZZ4

ZZ4

Z

Z

2G

2G

S

S

S2G@

S2G@

76xxxxxLx3

76xxxxxLx3

X

X

Configuration Total Memory Size/Qty

2Gbit 128M*16

2Gbit 128M*16

2Gbit 128M*16 1GB/4pcs

2Gbit 128M*16 1GB/4pcs

2Gbit

128M*16

C

ZZ5

ZZ5

Z

Z

H

H

H2G@

H2G@

76xxxxxLx4

76xxxxxLx4

X

X

DB[0..63]<18>

M

2G

2G

1GB/4pcs

1GB/4pcs

1GB/4pcs

M

DB[0..63]

+

MVREFDB_SB

U

U

V1I

V1I

C

5

M

DB0

D

QB0_0

C

3

M

DB1

D

QB0_1

E

3

M

DB2

D

QB0_2

E

1

M

DB3

D

QB0_3

F

1

M

DB4

D

QB0_4

F

3

M

DB5

D

QB0_5

F

5

M

DB6

D

QB0_6

G

4

M

DB7

D

QB0_7

H

5

M

DB8

D

QB0_8

H

6

M

DB9

D

QB0_9

J

4

M

DB10

D

QB0_10

K

6

M

DB11

D

QB0_11

K

5

M

DB12

D

QB0_12

L

4

M

DB13

D

QB0_13

M

6

M

DB14

D

QB0_14

M

1

M

DB15

D

QB0_15

M

3

M

DB16

D

QB0_16

M

5

M

DB17

D

QB0_17

N

4

M

DB18

D

QB0_18

P

6

M

DB19

D

QB0_19

P

5

M

DB20

D

QB0_20

R

4

M

DB21

D

QB0_21

T

6

M

DB22

D

QB0_22

T

1

M

DB23

D

QB0_23

U

4

M

DB24

D

QB0_24

V

6

M

DB25

D

QB0_25

V

1

M

DB26

D

QB0_26

V

3

M

DB27

D

QB0_27

Y

6

M

DB28

D

QB0_28

Y

1

M

DB29

D

QB0_29

Y

3

M

DB30

D

QB0_30

Y

5

M

DB31

D

QB0_31

A

A4

M

DB32

D

QB1_0

A

B6

M

DB33

D

QB1_1

A

B1

M

DB34

D

QB1_2

A

B3

M

DB35

D

QB1_3

A

D6

M

DB36

D

QB1_4

A

D1

M

DB37

D

QB1_5

A

D3

M

DB38

D

QB1_6

A

D5

M

DB39

D

QB1_7

A

F1

M

DB40

D

QB1_8

A

F3

M

DB41

D

QB1_9

A

F6

M

DB42

D

QB1_10

A

G4

M

DB43

D

QB1_11

A

H5

M

DB44

D

QB1_12

A

H6

M

DB45

D

QB1_13

A

J4

M

DB46

D

QB1_14

A

K3

M

DB47

D

QB1_15

A

F8

M

DB48

D

QB1_16

A

F9

M

DB49

D

QB1_17

A

G8

M

DB50

D

QB1_18

A

G7

M

DB51

D

QB1_19

A

K9

M

DB52

D

QB1_20

A

L7

M

DB53

D

QB1_21

A

M8

M

DB54

D

QB1_22

A

M7

M

DB55

D

QB1_23

A

K1

M

DB56

D

QB1_24

A

L4

M

DB57

D

QB1_25

A

M6

M

DB58

D

QB1_26

A

M1

M

DB59

D

QB1_27

A

N4

M

DB60

D

QB1_28

A

P3

M

DB61

D

QB1_29

A

P1

M

DB62

D

QB1_30

A

P5

M

DB63

D

QB1_31

Y

12

M

VREFDB

A

A12

M

VREFSB

R

_pu & R_pd resistor:

0402 1% resistors are required.

PS_3[ 1]PS_3[ 2 ]PS_3[ 3 ]

0 0

0 0

00

1

1

1

1

1

1

0

1

P

P

ART 4 0F 9

ART 4 0F 9

GDDR5/DDR3

GDDR5/DDR3

D

AB0_0/MAB_0

M

AB0_1/MAB_1

M

AB0_2/MAB_2

M

AB0_3/MAB_3

M

AB0_4/MAB_4

M

AB0_5/MAB_5

M

AB0_6/MAB_6

M

AB0_7/MAB_7

M

AB1_0/MAB_8

M

AB1_1/MAB_9

M

AB1_2/MAB_10

M

AB1_3/MAB_11

M

AB1_4/MAB_12

M

AB1_5/BA2

M

AB1_6/BA0

M

AB1_7/BA1

M

CKB0_0/DQMB_0

W

CKB0B_0/DQMB_1

W

CKB0_1/DQMB_2

W

CKB0B_1/DQMB_3

W

CKB1_0/DQMB_4

W

CKB1B_0/DQMB_5

W

CKB1_1/DQMB_6

W

EMORY INTERFACE B

EMORY INTERFACE B
M

M

CKB1B_1/DQMB_7

W

DCB0_0/QSB_0

E

DCB0_1/QSB_1

E

DCB0_2/QSB_2

E

DCB0_3/QSB_3

E

DCB1_0/QSB_4

E

DCB1_1/QSB_5

E

DCB1_2/QSB_6

E

DCB1_3/QSB_7

E

DBIB0_0/QSB_0B

D

DBIB0_1/QSB_1B

D

DBIB0_2/QSB_2B

D

DBIB0_3/QSB_3B

D

DBIB1_0/QSB_4B

D

DBIB1_1/QSB_5B

D

DBIB1_2/QSB_6B

D

DBIB1_3/QSB_7B

D

DBIB0/ODTB0

A

DBIB1/ODTB1

A

M

AB0_8/MAB_13

M

AB1_8/MAB_14

M

AB0_9/MAB_15

M

AB1_9/RSVD

D

RAM_RST

SUN-PRO M2_FCBGA962VGA@

SUN-PRO M2_FCBGA962VGA@

R_pu R_pd

RV20

N

C 4.75K

RV20

N

C04.75K

RV20 RV27

8.45K 2K

RV20 RV27

4.75K

RV27

RV20

4

.75K

C

C

R
R

C
C

C
C

C
C

W
W

RV27

RV27

N

C

NC

LKB0

C

LKB0B

LKB1

C

LKB1B

ASB0B
ASB1B

ASB0B
ASB1B

SB0B_0
SB0B_1

SB1B_0
SB1B_1

C

KEB0

C

KEB1

EB0B
EB1B

E

M

AB[0..15]

D

_BA2 <18>

B

_BA0 <18>

B

_BA1 <18>

B

DTB0 <18>

O

DTB1 <18>

O

LKB0 < 18>

C

LKB0# <18>

C

LKB1 < 18>

C

LKB1# <18>

C

ASB0# <18>

R

ASB1# <18>

R

ASB0# <18>

C

ASB1# <18>

C

SB0#_0 <18>

C

SB1#_0 <18>

C

KEB0 < 18>

C

KEB1 < 18>

C

EB0# < 18>

W

EB1# < 18>

W

1 2

10_0402_1%

10_0402_1%

2

120P_0402_50V9

120P_0402_50V9

1

QMB#[0..7]

Q

SB[0..7]

Q

SB#[0..7]

R

R

V36

VGA@

V36

VGA@

VGA@

VGA@

C

C

V158

V158

8

P

M

AB0

9

T

M

AB1

9

P

M

AB2

7

N

M

AB3

8

N

M

AB4

9

N

M

AB5

9

U

M

AB6

8

U

M

AB7

9

Y

M

AB8

9

W

M

AB9

C8

A

M

AB10

C9

A

M

AB11

A7

A

M

AB12

A8

A

B

_BA2

8

Y

B

_BA0

A9

A

B

_BA1

3

H

D

QMB#0

1

H

D

QMB#1

3

T

D

QMB#2

5

T

D

QMB#3

E4

A

D

QMB#4

F5

A

D

QMB#5

K6

A

D

QMB#6

K5

A

D

QMB#7

6

F

Q

SB0

3

K

Q

SB1

3

P

Q

SB2

5

V

Q

SB3

B5

A

Q

SB4

H1

A

Q

SB5

J9

A

Q

SB6

M5

A

Q

SB7

7

G

Q

SB#0

1

K

Q

SB#1

1

P

Q

SB#2

4

W

Q

SB#3

C4

A

Q

SB#4

H3

A

Q

SB#5

J8

A

Q

SB#6

M3

A

Q

SB#7

7

T

O

DTB0

7

W

O

DTB1

9

L

C

LKB0

8

L

C

LKB0#

D8

A

C

LKB1

D7

A

C

LKB1#

10

T

R

ASB0#

10

Y

R

ASB1#

W

10

C

ASB0#

A

A10

C

ASB1#

P

10

C

SB0#_0

L

10

A

D10

C

SB1#_0

A

C10

U

10

C

KEB0

A

A11

C

KEB1

N

10

W

EB0#

A

B11

W

EB1#

T

8

M

AB13

W

8

M

AB14

U

12

M

AB15

V

12

A

H11

RAM_RST#_R

D

VGA@

VGA@

V71

V71

R

R

4.99K_0402_1%

4.99K_0402_1%

Place all these components close to GPU (Within 25mm)
and keep all component close to each other

12

R

R

V70

V70

1 2

51.1_0402_1%

51.1_0402_1%

AB[0..15] <18>

M

QMB#[0..7] <18>

D

SB[0..7] <18>

Q

SB#[0..7] < 18>

Q

VGA@

VGA@

RAM_RST# <18>

D

4 4

ecurity Classification

ecurity Classification

ecurity Classification

S

S

S

ssued Date

ssued Date

ssued Date

I

I

I

HIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONFI DENTIAL

HIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONFI DENTIAL

HIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONFI DENTIAL

T

T

T
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

A

B

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

C

013/01/22 2014/01/21

013/01/22 2014/01/21

013/01/22 2014/01/21

2

2

2

ompal Secret Data

ompal Secret Data

ompal Secret Data

C

C

C

eciphered Date

eciphered Date

eciphered Date

D

D

D

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

C

C

itle

itle

itle

T

T

T

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

D

Date: Sheet

C

M

M

M

L

L

L

EM Interface

EM Interface

EM Interface

A-9869P

A-9869P

A-9869P

E

.3

.3

.3

0

0

0

f

6 50Monday, February 04, 2013

f

6 50Monday, February 04, 2013

f

6 50Monday, February 04, 2013

1

1

o

o

1

o

A

U

U

V1G

V1G

P

P

ART 6 0F 9

ART 6 0F 9

B39

A

GND

39

E

GND

34

F

GND

39

F

GND

33

G

GND

34

G

GND

31

H

GND

34

H

GND

39

H

GND

31

J

1 1

2 2

3 3

4 4

A

GND

34

J

GND

31

K

GND

34

K

GND

39

K

GND

31

L

GND

34

L

GND

34

M

GND

39

M

GND

31

N

GND

34

N

GND

31

P

GND

34

P

GND

39

P

GND

34

R

GND

31

T

GND

34

T

GND

39

T

GND

31

U

GND

34

U

GND

34

V

GND

39

V

GND

31

W

GND

34

W

GND

34

Y

GND

39

Y

GND

GND

15

F

GND

17

F

GND

19

F

GND

21

F

GND

23

F

GND

25

F

GND

27

F

GND

29

F

GND

31

F

GND

33

F

GND

7

F

GND

9

F

GND

2

G

GND

6

G

GND

9

H

GND

2

J

GND

27

J

GND

6

J

GND

8

J

GND

14

K

GND

7

K

GND

11

L

GND

17

L

GND

2

L

GND

22

L

GND

24

L

GND

6

L

GND

17

M

GND

22

M

GND

24

M

GND

16

N

GND

18

N

GND

N

2

GND

N

21

GND

N

23

GND

N

26

GND

N

6

GND

R

15

GND

R

17

GND

R

2

GND

R

20

GND

R

22

GND

R

24

GND

R

27

GND

R

6

GND

T

11

GND

T

13

GND

T

16

GND

T

18

GND

T

21

GND

T

23

GND

T

26

GND

U

15

GND

U

17

GND

U

2

GND

U

20

GND

U

22

GND

U

24

GND

U

27

GND

U

6

GND

V

11

GND

V

16

GND

V

18

GND

V

21

GND

V

23

GND

V

26

GND

W

2

GND

W

6

GND

Y

15

GND

Y

17

GND

Y

20

GND

Y

22

GND

Y

24

GND

Y

27

GND

GND

VSS_MECH
VSS_MECH
VSS_MECH

SUN-PRO M2_FCBGA962VGA@

SUN-PRO M2_FCBGA962VGA@

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

NC

A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
AC18
A
AC21
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A

A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A

A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
B
B
B
B
B
B
B
B
B
B
B
B
B
C
C
E
E
F
F

A

A
A
A

3
37
A16
A18
A2
A21
A23
A26
A28
A6
B12
B15
B17
B20
B22
B24
B27
C11
C13
C16

C2

C23
C26
C28
C6
D15
D17
D20
D22
D24
D27
D9
E2
E6
F10
F16
F18
F21
G17
G2
G20

G6
G9
H21
J10
J11
J2
J28
J6
K11
K31
K7
L11
L14
L17
L2
L20

L23
L26
L32
L6
L8
M11
M31
M9
N11
N2
N30
N6
N8
P11
P7
P9
R5
11
13
15
17
19
21
23
25
27
29
31
33
7
9
1
39
35
5
11
13

G22

39
W1
W39

B

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

+

1.8VGS

(DP_VDDR: 1.8V@ 20mA)

C

D

U

U

V1F

V1F

A

N24

NC

A

P24

NC

A

P25

NC

A

P26

NC

A

U28

NC

A

V29

NC

A

P20

NC

A

P21

NC

A

P22

NC

A

P23

NC

A

U18

NC

A

V19

NC

A

H34

DP_VDDR

A

J34

DP_VDDR

A

F34

DP_VDDR

A

G34

DP_VDDR

A

M37

DP_VDDR

A

L38

DP_VDDR

A

M32

DP_VDDR

A

W28

NC

A

W18

NC

A

M39

DP_CALR

2

2

2

013/01/22 2014/01/21

013/01/22 2014/01/21

013/01/22 2014/01/21

P

P

ART 8 0F 9

ART 8 0F 9

DP_VDDR DP_VDDC

DP_VDDR DP_VDDC

DP GND

DP GND

CALIBRATION

CALIBRATION

SUN-PRO M2_FCBGA962VGA@

SUN-PRO M2_FCBGA962VGA@

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC
DP_VDDC

DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR
DP_VSSR

D

NC
NC
NC
NC

A

P31

A

P32

A

N33

A

P33

A

L33

A

M33

A

K33

A

K34

(

DP_VDDC: 0.95V@ 20mA)

A

N31

A

P13

A

T13

A

P14

A

P15

A

N27

A

P27

A

P28

A

W24

A

W26

A

N29

A

P29

A

P30

A

W30

A

W32

A

N17

A

P16

A

P17

A

W14

A

W16

A

N19

A

P18

A

P19

A

W20

A

W22

A

N34

A

P39

A

R39

A

U37

A

F39

A

H39

A

K39

A

L34

A

V27

A

R28

A

V17

A

R18

A

N38

A

M35

A

N32

E

+

0.95VGS

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

Title

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

P

P

P

WR_GND

WR_GND

WR_GND

L

L

L

A-9869P

A-9869P

A-9869P

17 50Monday, February 04, 2013

17 50Monday, February 04, 2013

17 50Monday, February 04, 2013

E

o

o

o

f

f

f

0

0

0

.3

.3

.3

5

U

U

VREFC_A1_B

+

D D

DB[0..63]<16>

M

AB[15..0]<16>

M

QMB#[7..0]<16>

D

SB[7..0]<16>

Q

SB#[7..0]<16>

Q

C C

C

LKB0

V78 40.2_0402_1%

V78 40.2_0402_1%

R

R

C

LKB0#

V79 40.2_0402_1%

V79 40.2_0402_1%

R

R

1

C

LKB1

R

R

V84 40.2_0402_1%

V84 40.2_0402_1%

1 2

C

LKB1#

V85 40.2_0402_1%

V85 40.2_0402_1%

R

R

VGA@

VGA@

1

VGA@

VGA@

1 2

VGA@

VGA@

VGA@

VGA@

M

DB[0..63]

M

AB[15..0]

B
B

C
C
C

O
C
R
C
W

RAM_RST#<16>

D

243_0402_1%

243_0402_1%

B

LKB0<16>
LKB0#<16>
KEB0<16>

DTB0<16>
SB0#_0<16>
ASB0#<16>
ASB0#<16>

EB0#<16>

R

R

VGA@

VGA@

D

QMB#[7..0]

Q

SB[7..0]

Q

SB#[7..0]

2

VGA@

VGA@

1

C

C

V160

V160

0.01U_0402_16V7K

0.01U_0402_16V7K

2

2

VGA@

VGA@

1

V161

V161

C

C

0.01U_0402_16V7K

0.01U_0402_16V7K

2

M8
H1

N3

M

AB0

P7

M

AB1

P3

M

AB2

N2

M

AB3

P8

M

AB4

P2

M

AB5

R8

M

AB6

R2

M

AB7

T8

M

AB8

R3

M

AB9

L7

M

AB10

R7

M

AB11

N7

M

AB12

T3

M

AB13

T7

M

AB14

M7

AB15

M

M2

_BA0<16>

N8

_BA1<16>

M3

_BA2<16>

J7

K

7

K9

K1

L2
J

3

K

3

L

3

F3

SB3

Q

C7

SB0

Q

E7

D

QMB#3

D3

D

QMB#0

G

3

SB#3

Q

B

7

Q

SB#0

T

2

L8

12

J1
L

V80

V80

1
J9
L9

K4W1G1646G-BC11_FBGA96

K4W1G1646G-BC11_FBGA96

V5

V5

V

REFCA

V

REFDQ

A

0

A

1

A

2

A

3

A

4

A

5

A

6

A

7

A

8

A

9

A

10/AP

A

11

A

12

A

13

A

14

A

15/BA3

B

A0

B

A1

B

A2

C

K

C

K

C

KE/CKE0

O

DT/ODT0

C

S/CS0

R

AS

C

AS

W

E

D

QSL

D

QSU

D

ML

D

MU

D

QSL

D

QSU

R

ESET

Z

Q/ZQ0

N

C/ODT1

N

C/CS1

N

C/CE1

N

CZQ1

9

9

6-BALL

6-BALL

SDRAM DDR3

SDRAM DDR3

4

C

HANNEL B: 512MB/1024MB DDR3

V81

V81

M
M
M
M
M
M
M
M
M
M
M
M
M
M
M

M

B

_BA0

B

_BA1

B

_BA2

C

LKB0

C

LKB0#

C

KEB0

O

DTB0

C

SB0#_0

ASB0#

R

C

ASB0#

EB0#

W

SB2

Q

SB1

Q

D

QMB#2

D

QMB#1

SB#2

Q

SB#1

Q

D

RAM_RST#

12

AB0
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
AB11
AB12
AB13
AB14

AB15

M8
H1

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3

L7
R7
N7
T3
T7
M7

M2
N8
M3

J7

7

K
K9

K1

L2

3

J

3

K

3

L

F3
C7

E7
D3

3

G

7

B

2

T

L8

J1

1

L

J9

L9

E3

DB29

M

D

QL0

F7

DB26

M

D

QL1

F2

M

DB30

D

QL2

F8

M

DB27

D

QL3

H3

M

DB31

D

QL4

H8

M

DB25

D

QL5

G2

M

DB28

D

QL6

H7

M

DB24

D

QL7

D7

DB3

M

D

QU0

C3

DB5

M

D

QU1

C8

M

DB1

D

QU2

C2

M

DB6

D

QU3

A7

DB2

M

D

QU4

A2

M

DB7

D

QU5

B8

DB0

M

D

QU6

A3

DB4

M

D

QU7

V
V
V
V
V
V
V
V
V

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V
V
V
V
V
V
V
V
V
V
V
V

V

SSQ

V

SSQ

V

SSQ

V

SSQ

V

SSQ

V

SSQ

V

SSQ

V

SSQ

V

SSQ

1.5VGS

+

B2

DD

D9

DD

G7

DD

K2

DD

K8

DD

N1

DD

N9

DD

R1

DD

R9

DD

1.5VGS

+

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9

SS

B3

SS

E1

SS

G8

SS

J2

SS

J8

SS

M1

SS

M9

SS

P1

SS

P9

SS

T1

SS

T9

SS

B1
B9
D1
D8
E2
E8
F9
G1
G9

@

@

S

upported Memory Configurations: Up to 4 Gbit/part for DDR3.

VREFC_A2_B

+

R

R

243_0402_1%

243_0402_1%

VGA@

VGA@

3

V6

V6

U

U

QL0

REFCA

V

D

QL1

REFDQ

V

D

QL2

D

QL3

0

A

D

QL4

1

A

D

2

QL5

D

A

3

QL6

D

A

4

QL7

D

A

5

A

6

A

7

QU0

D

A

8

QU1

D

A

9

QU2

D

A

10/AP

QU3

D

A

11

QU4

D

A

12

QU5

D

A
A
A
A

B
B
B

C
C
C

O
C
R
C
W

D
D

D
D

D
D

R

Z

N
N
N
N

K4W1G1646G-BC11_FBGA96

K4W1G1646G-BC11_FBGA96

13
14
15/BA3

A0
A1
A2

K
K
KE/CKE0

DT/ODT0
S/CS0
AS
AS

E

QSL
QSU

ML
MU

QSL
QSU

ESET

Q/ZQ0

C/ODT1
C/CS1
C/CE1
CZQ1

6-BALL

6-BALL

9

9
SDRAM DDR3

SDRAM DDR3

QU6

D

QU7

D

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DD

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SSQ

V

SSQ

V

SSQ

V

SSQ

V

SSQ

V

SSQ

V

SSQ

V

SSQ

V

SSQ

V

2

U

U

V7

V7

V82

V82

M
M
M
M
M
M
M
M
M
M
M
M
M
M
M

M

B

_BA0

B

_BA1

B

_BA2

SB4

Q

SB5

Q

D

QMB#4

D

QMB#5

SB#4

Q

SB#5

Q

D

RAM_RST#

12

AB0
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
AB11
AB12
AB13
AB14

AB15

M8

H1

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7

M7

M2

N8

M3

J7

7

K

K9

K1

L2
J

3

K

3

L

3

F3
C7

E7
D3

3

G

7

B

2

T

L8

J1

1

L
J9
L9

REFCA

V

REFDQ

V

0

A

1

A

2

A

3

A

4

A

5

A

6

A

7

A

8

A

9

A

10/AP

A

11

A

12

A

13

A

14

A

15/BA3

A

A0

B

A1

B

A2

B

C

K

C

K

C

KE/CKE0

DT/ODT0

O

C

S/CS0

R

AS

C

AS

W

E

QSL

D

QSU

D

ML

D

MU

D

QSL

D

QSU

D

ESET

R

Q/ZQ0

Z

C/ODT1

N

C/CS1

N

C/CE1

N

CZQ1

N

9

9

6-BALL

6-BALL

SDRAM DDR3

SDRAM DDR3

K4W1G1646G-BC11_FBGA96

K4W1G1646G-BC11_FBGA96

E3

DB17

M

F7

M

DB19

F2

DB16

M

F8

M

DB22

H3

DB20

M

H8

M

DB21

G2

M

DB18

H7

M

DB23

D7

M

DB15

C3

M

DB10

C8

DB12

M

C2

DB8

M

A7

DB13

M

A2

M

DB9

B8

DB14

M

A3

DB11

M

1.5VGS

+

B2
D9
G7
K2
K8
N1
N9
R1
R9

1.5VGS

+

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

B1
B9
D1
D8
E2
E8
F9
G1
G9

@

@

VREFC_A3_B

+

LKB1<16>

C

LKB1#<16>

C

KEB1<16>

C

DTB1<16>

O

SB1#_0<16>

C

ASB1#<16>

R

ASB1#<16>

C

EB1#<16>

W

R

R

243_0402_1%

243_0402_1%

VGA@

VGA@

E3

M

QL0

D

QL1

D

QL2

D

QL3

D

QL4

D

QL5

D

QL6

D

QL7

D

QU0

D

QU1

D

QU2

D

QU3

D

QU4

D

QU5

D

QU6

D

QU7

D

V
V
V
V
V
V
V
V
V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

V
V
V
V
V
V
V
V
V
V
V
V

SSQ

V

SSQ

V

SSQ

V

SSQ

V

SSQ

V

SSQ

V

SSQ

V

SSQ

V

SSQ

V

DB33

F7

M

DB37

F2

M

DB35

F8

M

DB39

H3

M

DB32

H8

M

DB36

G2

M

DB34

H7

M

DB38

D7

DB45

M

C3

DB43

M

C8

M

DB47

C2

DB42

M

A7

DB44

M

A2

M

DB40

B8

M

DB46

A3

DB41

M

1.5VGS

+

B2

DD

D9

DD

G7

DD

K2

DD

K8

DD

N1

DD

N9

DD

R1

DD

R9

DD

1.5VGS

+

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9

SS

B3

SS

E1

SS

G8

SS

J2

SS

J8

SS

M1

SS

M9

SS

P1

SS

P9

SS

T1

SS

T9

SS

B1
B9
D1
D8
E2
E8
F9
G1
G9

@

@

VREFC_A4_B

+

R

R

243_0402_1%

243_0402_1%

VGA@

VGA@

V83

V83

M
M
M
M
M
M
M
M
M
M
M
M
M
M
M

M

B

_BA0

B

_BA1

B

_BA2

C

LKB1

C

LKB1#

C

KEB1

O

DTB1

C

SB1#_0

ASB1#

R

C

ASB1#

EB1#

W

SB6

Q

SB7

Q

D

QMB#6

D

QMB#7

SB#6

Q

SB#7

Q

D

RAM_RST#

12

AB0
AB1
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
AB11
AB12
AB13
AB14

AB15

M8

H1

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7

M7

M2

N8

M3

J7

K

7

K9

K1
L2

J

3

K

3

L

3

F3
C7

E7
D3

G

3

B

7

T

2

L8

J1

L

1

J9

L9

U

U

V8

V8

V

REFCA

V

REFDQ

A

0

A

1

A

2

A

3

A

4

A

5

A

6

A

7

A

8

A

9

A

10/AP

A

11

A

12

A

13

A

14

A

15/BA3

B

A0

B

A1

B

A2

C

K

C

K

C

KE/CKE0

O

DT/ODT0

C

S/CS0

R

AS

C

AS

W

E

D

QSL

D

QSU

D

ML

D

MU

D

QSL

D

QSU

R

ESET

Z

Q/ZQ0

N

C/ODT1

N

C/CS1

N

C/CE1

N

CZQ1

K4W1G1646G-BC11_FBGA96

K4W1G1646G-BC11_FBGA96

9

9

6-BALL

6-BALL

SDRAM DDR3

SDRAM DDR3

1

E3

DB53

D
D
D
D
D
D
D
D

D

QU0

D

QU1

D

QU2

D

QU3

D

QU4

D

QU5

D

QU6

D

QU7

V
V
V
V
V
V
V
V
V

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

SSQ

V

SSQ

V

SSQ

V

SSQ

V

SSQ

V

SSQ

V

SSQ

V

SSQ

V

SSQ

M

QL0

F7

DB50

M

QL1

F2

DB52

M

QL2

F8

DB51

M

QL3

H3

DB55

M

QL4

H8

DB49

M

QL5

G2

DB54

M

QL6

H7

DB48

M

QL7

D7

DB57

M

C3

DB59

M

C8

DB63

M

C2

DB62

M

A7

DB56

M

A2

DB61

M

B8

DB58

M

A3

DB60

M

1.5VGS

+

B2

DD

D9

DD

G7

DD

K2

DD

K8

DD

N1

DD

N9

DD

R1

DD

R9

DD

V
V
V
V
V
V
V
V
V
V
V
V

1.5VGS

+

A1
A8
C1
C9
D2
E9
F1
H2
H9

A9

SS

B3

SS

E1

SS

G8

SS

J2

SS

J8

SS

M1

SS

M9

SS

P1

SS

P9

SS

T1

SS

T9

SS

B1
B9
D1
D8
E2
E8
F9
G1
G9

@

@

1.5VGS

B B

1.5VGS

+

1

1

V166

V166
C

C

A A

c

lose to UV7 UV8

2

0.1U_0402_16V7K

0.1U_0402_16V7K

GA@

GA@

V

V

1

V167

V167

V168

V168

C

C

C

C

2

2

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

GA@

GA@

V

V

GA@

GA@

V

V

5

1

1

V169

V169
C

C

2

0.1U_0402_16V7K

0.1U_0402_16V7K

V

V

GA@

GA@

1

V170

V170

V171

V171

C

C

C

C

2

2

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

GA@

GA@

V

V

GA@

GA@

V

V

1

1

V173

V173

V172

V172

C

C

C

C

0.1U_0402_16V7K

0.1U_0402_16V7K

GA@

GA@

V

V

2

2

0.1U_0402_16V7K

0.1U_0402_16V7K

GA@

GA@

V

V

close to UV9 UV 10

VGA@

VGA@

V86

V86

R

R

4.99K_0402_1%

4.99K_0402_1%

VGA@

VGA@

V90

V90

R

R

4.99K_0402_1%

4.99K_0402_1%

+

12

1

5mil 15mil 15mil 15mil

VREFC_A1_B

+

12

1

V162

V162
C

C

2

V

V

GA@

GA@

0.1U_0402_16V7K

0.1U_0402_16V7K

1.5VGS

+

C

C
V179 22U_0603_6.3V6M

V179 22U_0603_6.3V6M

1

2

GA@

GA@

V

V

4

VGA@

VGA@

V87

V87

R

R

4.99K_0402_1%

4.99K_0402_1%

VGA@

VGA@

R

R

V91

V91

4.99K_0402_1%

4.99K_0402_1%

+

1.5VGS

1.5VGS

+

1

2

VREFC_A2_B

+

12

1

V163

V163
C

C

2

GA@

GA@

V

V

0.1U_0402_16V7K

0.1U_0402_16V7K

close to UV7 UV 8

1.5VGS

+

1

1

1

1

V183

V183

V184

V184

V185

V185
C

C

C

C

C

C

2

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

V

V

GA@

GA@

GA@

GA@

V

V

V

V

GA@

GA@

ecurity Classification

ecurity Classification

ecurity Classification

S

S

S

ssued Date

ssued Date

ssued Date

I

I

I

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

T

T

T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

V187

V187

V186

V186
C

C

C

C

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

V

V

1U_0402_6.3V6K

1U_0402_6.3V6K

GA@

GA@

GA@

GA@

V

V

V

V

013/01/22 2014/01/21

013/01/22 2014/01/21

013/01/22 2014/01/21

2

2

2

VGA@

VGA@

R

R

V88

V88

4.99K_0402_1%

4.99K_0402_1%

VGA@

VGA@

V92

V92

R

R

4.99K_0402_1%

4.99K_0402_1%

1

V188

V188
C

C

2

GA@

GA@

ompal Secret Data

ompal Secret Data

ompal Secret Data

C

C

C

Deciphered Date

Deciphered Date

Deciphered Date

12

12

V

V

2

GA@

GA@

V164

V164
C

C

VREFC_A3_B

+

1

2

0.1U_0402_16V7K

0.1U_0402_16V7K

1.5VGS

+

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

V194

V194

V193

V193

C

C

C

C

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

V

V

V

V

GA@

GA@

GA@

GA@

1.5VGS

+

1

VGA@

VGA@

V89

V89

R

R

4.99K_0402_1%

4.99K_0402_1%

2

VREFC_A4_B

+

12

VGA@

VGA@

V93

V93

R

R

4.99K_0402_1%

4.99K_0402_1%

1

V165

V165
C

C

2

V

V

GA@

GA@

0.1U_0402_16V7K

0.1U_0402_16V7K

close to UV9 UV 10

1

1

V196

V196

V195

V195

C

C

C

C

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

GA@

GA@

V

V

V

V

GA@

GA@

itle

itle

itle

T

T

T

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C 0

C 0

C 0

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

1

V197

V197

V198

V198
C

C

C

C

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

V

V

V

V

GA@

GA@

GA@

GA@

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

C

C

C

RAM Channel B

RAM Channel B

RAM Channel B

V

V

V

A-9869P

A-9869P

A-9869P

L

L

L

1

.3

.3

8 50Monday, February 04, 2013

8 50Monday, February 04, 2013

8 50Monday, February 04, 2013

1

1

1

.3

5

S

WR / LDO Mode select

L

DO SWR

2132R RT24 mount LT3

D D

※※※※

If use 2132R, please select LDO mode as default.

r

eserve 0ohm

for Power consumption

+

3VS

8

0mil 80mil

LVDS@

LVDS@

1 2

T1

T1

R

R

0_0603_5%

0_0603_5%

+

3VS_RT

4

D

P0_AUXP_C

D

P0_AUXN_C

D

D

P0_AUXP_C<7>

D

P0_AUXN_C<7>

D

P0_TXP0_C<7>

D

P0_TXN0_C<7>

P0_AUXP_C

D

P0_AUXN_C

D

P0_TXP0_C

D

P0_TXN0_C

D

P0_TXP0_C

D

P0_TXN0_C

3

R

476/481/480/482 need to place under UT2

In orfer to reduce sub-trace

1 2

476 0_0402_5%IEDP@

476 0_0402_5%IEDP@

R

R

1 2

481 0_0402_5%

481 0_0402_5%

R

R

IEDP@

IEDP@

1 2

480 0_0402_5%IEDP@

480 0_0402_5%IEDP@

R

R

482 0_0402_5%

482 0_0402_5%

R

R

1

IEDP@

IEDP@

2

L

CD_EDID_CLK

L

CD_EDID_DATA

L

CD_TXOUT0+

L

CD_TXOUT0-

2

M

ode Configure

R

OM only mode : PIN 30 4.7k pull low, Pin 31 4.7k pull high.

※

E

P mode : PIN 30 4.7k pull high, Pin 31 4.7k pull low.

E

EPROM : PIN 30 4.7k pull high, Pin 31 4.7k pull high.

〈 ※

D

efault mode

M

IIC_SDA

P

IN30 PIN31

+

@

@

〉

3VS_RT

1 2

1 2

T4

T4

R

R

4.7K_0402_5%

4.7K_0402_5%

R

R

T6

T6

4.7K_0402_5%LVDS@

4.7K_0402_5%LVDS@

M

IIC_SCL

1

LVDS@

LVDS@

+

3VS_RT

1 2

1 2

T12

T12

R

R

4.7K_0402_5%

4.7K_0402_5%

R

R

T7

T7

4.7K_0402_5%@

4.7K_0402_5%@

Close to Pin3

+

10U_0603_6.3V6M

10U_0603_6.3V6M

1

C

C
T1

T1

2

C C

VDS@

VDS@

L

L

VDS@

VDS@

L

L

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C

C
T2

T2

2

L

L

VDS@

VDS@

Close to LT2

22U_0603_6.3V6M

1

2

C

C
T5

T5

22U_0603_6.3V6M

VDS@

VDS@

L

L

Close to Pin13

10U_0603_6.3V6M

10U_0603_6.3V6M

VDS@

VDS@

L

L

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C

C
T4

T4

2

L

L

VDS@

VDS@

DP_V33

1

C

C
T3

T3

2

Close to Pin18

+

SWR_VDD

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C

C
T6

T6

2

VDS@

VDS@

L

L

0.1U_0402_16V4Z

1

2

1

C

C
T7

T7

C

C
T8

T8

2

VDS@

VDS@

L

L

Close to L29

+

SWR_V12

0.1U_0402_16V4Z

1

2

lose to

5

C

C
T11

T11

OUT

V

G

0.1U_0402_16V4Z

Close to Pin7

1

2

ND

3

N

E

1

C

C
T12

T12

2

VDS@

VDS@

L

L

W=80mils

112

112

R

R

100K_0402_5%

100K_0402_5%

IEDP@

IEDP@

+

LCD_VDD

1 2

IEDP@

IEDP@

1 2

R

R

104 0_0402_5%

104 0_0402_5%

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

10U_0603_6.3V6M

10U_0603_6.3V6M

1

C

C
T9

B B

A A

T9

2

L

L

L

L

VDS@

VDS@

VDS@

VDS@

L

CD POWER CIRCUIT (For eDP panel only)

+

3VS

W

=80mils

+

LCD_VDD_SS

12

2

2

C

C

1500P_0402_50V7K

1500P_0402_50V7K

IEDP@

IEDP@

0.1U_0402_16V4Z

1

C

C
T10

T10

2

L

L

VDS@

VDS@

C
Pin27

18

18

U

U

5

IN

V

4

S

S

APL3512ABI-TRG_SOT23-5

APL3512ABI-TRG_SOT23-5

IEDP@

IEDP@

SA00003AR00

C

lose to Pin15

+

3VS_RT

+

L

4

LVDS@

LVDS@

L

L

T1

T1

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

LVDS@

LVDS@

T2

T2

L

L

1

00mil

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

SWR_V12

E

C_SMB_CK3<34>

E

C_SMB_DA3<34>

L

VDS_HPD<2 0,7>

12K_0402_1%

12K_0402_1%

C

lose to Pin8

CD_ENVDD <9>

12

+

DP_V33

12

+

SWR_VDD

D

P0_AUXP_C

D

P0_AUXN_C

D

P0_TXP0_C

D

P0_TXN0_C

R

R

T8

T8

LVDS@

LVDS@

UT2

UT2

3

4

0mil

100mil
40mil

40mil
40mil
40mil
4

0mil

2

1

D

13

WR_VDD

S

18

VCC

P

12

WR_LX

S

11

WR_VCCK

S

27

CCK

V

7

D

2

UX_P

A

1

UX_N

A

5

ANE0P

L

6

ANE0N

L

9

C

10

C

32

H

8

D

4

D

LVDS@

LVDS@

S

A000069200

P_V33

P_V12

IICSCL1
IICSDA1

PD

P_REXT
P_GND

R

R

P

P
ower

ower

VDS

VDS
L

L

TD2132R

TD2132R

DP-IN

DP-IN

PIO(PWM OUT)

G

PIO(Panel_VCC)

G

PIO

PIO

PIO(PWM IN)

G

G

G

G

VDS

VDS

L

L

O

O

EDID

EDID

ther

ther

ROM

ROM

TD2132R-VE-CG_QFN32_5X5

TD2132R-VE-CG_QFN32_5X5

R

R

XEC+

T

XEC-

T

XE2+

T

XE2-

T

XE1+

T

XE1-

T

XE0+

T

XE0-

T

PIO(BL_EN)

IICSCL1

M

IICDA1

M

IICSCL0

M

IICSDA0

M

G

19
20

21
22

23
24

25

L

CD_TXOUT0+

26

L

CD_TXOUT0-

14
15

80mil

16
17

29

L

CD_EDID_CLK

28

L

CD_EDID_DATA

31

M

30

M

33

ND

IIC_SCL
IIC_SDA

T

L_INVT_PWM

+

LCD_VDD_R

L

CD_EDID_CLK <20>

L

CD_EDID_DATA <20>

L

CD_TXCLK+ <20 >

L

CD_TXCLK- <20>

L

CD_TXOUT2+ <20>

L

CD_TXOUT2- <20>

L

CD_TXOUT1+ <20>

L

CD_TXOUT1- <20>

L

CD_TXOUT0+ <20>

L

CD_TXOUT0- <20>

T

L_INVT_PWM <20>

A

PU_INVT_PWM <20,9>

E

C_ENBKL <34>

2132S

2132R

* Version R internal Power Switch, can
output 1A, Rds(on)=0.2 ohm

D

ifferent between 2132S and 2132R

L

L

R8 for power consumption
Remove on PVT phase

+

LCD_VDD_R

P

IN15

TL_ENVDD

+LCD_VDD *

CD_EDID_DATA

CD_EDID_CLK

LVDS@

LVDS@

2

1

T9 4.7K_0402_5%

T9 4.7K_0402_5%

R

R

LVDS@

LVDS@

1 2

R

R

T10 4.7K_0402_5%

T10 4.7K_0402_5%

LVDS@

LVDS@

12

8 0_0805_5%

8 0_0805_5%

R

R

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

C

C

LVDS@

LVDS@

+

LCD_VDD

1

2

R

R

T113

T13

T13

T113

100K_0402_5%

100K_0402_5%

LVDS@

LVDS@

1

2

Close to Panel conn.

A

PIN16

2132S

2132R

*

Version R has internal level shifter, remove

level shifter circuit on AMD platform

ccept voltage input (high level)

3.3V

1.5~3.3V

+

3VS_RT

+

LCD_VDD

2132S 2132R

1. Support SWR mode

1. Support LDO mode and SWR mode

2. Internal ROM

3. Support LCD_VDD(internal Power switch)

4. Integrates Level shifter

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2

2

2

013/01/22 2014/01/21

013/01/22 2014/01/21

013/01/22 2014/01/21

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

2

T

T

Title

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

L

L

L

VDS Translator - RTD2132S

VDS Translator - RTD2132S

VDS Translator - RTD2132S

L

L

L

A-9869P

A-9869P

A-9869P

1

19 50Monday, February 04, 2013

19 50Monday, February 04, 2013

19 50Monday, February 04, 2013

0

0

0

.3

.3

.3

o

o

o

f

f

f

A

F

or LVDS 1ch Panel

L

L

CD_TXOU T1+

L

CD_TXOU T1-

CD_TXOU T0+

L

CD_TXOU T0-

L

CD_TXOU T1+

L

CD_TXOU T1-

L

CD_TXOU T2+

L

CD_TXOU T2-

L

CD_TXCL K+

L

CD_TXCL K-

L

CD_EDID_C LK

L

CD_EDID_D ATA

+

3VS

L

CD_TXOU T0+< 19>

L

CD_TXOU T0-<1 9>

L

1 1

F

or eDP Panel

2 2

CD_TXOU T1+< 19>

L

CD_TXOU T1-<1 9>

L

CD_TXOU T2+< 19>

L

CD_TXOU T2-<1 9>

L

CD_TXCL K+< 19>

L

CD_TXCL K-<1 9>

L

CD_EDID_C LK<19>

L

CD_EDID_D ATA<19>

2

1

102 0_0402_ 5%IEDP@

102 0_0402_ 5%IEDP@

R

D

P0_TXP1 _C<7>

D

P0_TXN1 _C<7>

R

R

R

105 0_0402_ 5%IEDP@

105 0_0402_ 5%IEDP@

L

CD_EDID_D ATA

L

CD_EDID_C LK

1 2

IEDP@

IEDP@

149 100K_ 0402_5%

149 100K_ 0402_5%

R

R

R

R

150 100K_ 0402_5%

150 100K_ 0402_5%

12

2

1

IEDP@

IEDP@

B

EMI@

EMI@

U

SB20_P1 _R

U

SB20_N1 _R

U

SB20_N4 _R

U

SB20_P4 _R

1

1

4

4

WCM-2 012-900T_0805

WCM-2 012-900T_0805

55

55

L

L

@TOUCH_ EMI@

@TOUCH_ EMI@

1 2

R

R

155 0_040 2_5%

155 0_040 2_5%

TOUCH_E MI@

TOUCH_E MI@

1

1

4

4

L

L

56

56

WCM-2 012-900T_0805

WCM-2 012-900T_0805

@TOUCH_ EMI@

@TOUCH_ EMI@

1 2

R

R

156 0_040 2_5%

156 0_040 2_5%

2

2

3

3

2

2

3

3

C

U

SB20_P1 < 24>

U

SB20_N1 <24>

U

SB20_N4 <24>

U

SB20_P4 < 24>

D

D

D

32

32

U

SB20_P1 _R

4

4

+

3VS

5

V

bus

ESD@

ESD@

G

ND

E

3

U

3

SB20_N1 _R

2

I

R

eserve for eDP panel potience issue

1 2

IEDP@

IEDP@

103 0_040 2_5%

103 0_040 2_5%

R

R

12

L

ED_PW M

133

133

R

R

1 2

D

D

114

114

R

R
10K_040 2_5%

10K_040 2_5%

12

16 RB7 51V40_SC76-2

16 RB7 51V40_SC76-2

LVDS@

LVDS@

1

.5A

+

LCD_INV

1 2

RB751V4 0_SC76-2

RB751V4 0_SC76-2

A

B

KOFF#_R

3 3

4 4

47K_040 2_5%

47K_040 2_5%

+

3VS

IEDP@

IEDP@

5

19

19

U

U

1

P

N1

I

4

O

2

N2

I

G

3

SN74AHC 1G08DCKR_SC7 0-5

SN74AHC 1G08DCKR_SC7 0-5

1 2

R

R

152 0_040 2_5%

152 0_040 2_5%

LVDS@

LVDS@

B

L

2

EMI@L2

EMI@

FBMA-L11 -201209-221LMA 30T_0805

FBMA-L11 -201209-221LMA 30T_0805

IEDP@

IEDP@

1 2

108 0_040 2_5%

108 0_040 2_5%

R

R

17

17

D

D

+

12

L

CD_ENBK L <34,9>

B

KOFF# < 34>

A

PU_INVT_P WM <19,9>

T

L_INVT_PW M < 19>

+

LVDS @

LVDS @

J

J

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

0

1

11

1

1

12

2

1

13

3

1

14

4

1

15

5

1

16

6

1

17

7

1

18

8

1

19

9

1

20

0

2

21

1

2

22

2

2

23

3

2

24

4

2

25

5

2

26

6

2

27

7

2

28

8

2

29

9

2

30

0

3

31

ND

G

32

ND

G

33

ND

G

34

ND

G

35

ND

G

STARC_1 11H30-000000-G 4-R

STARC_1 11H30-000000-G 4-R

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

I

I

I

ssued Date

ssued Date

ssued Date

+

5VS_LVD S_TOUCH

U

SB20_N4 _R

U

SB20_P4 _R

B

KOFF#

U

SB20_P1 _R

U

SB20_N1 _R

+

3VS_LVD S_CAM

+

LCD_VDD

L

CD_EDID_C LK

L

CD_EDID_D ATA

L

CD_TXOU T0-

L

CD_TXOU T0+

L

CD_TXOU T1-

L

CD_TXOU T1+

L

CD_TXOU T2-

L

CD_TXOU T2+

L

CD_TXCL K-

L

CD_TXCL K+

L

ED_PW M

B

KOFF#_R

1 2

@

@

391 0_060 3_5%

391 0_060 3_5%

R

R

I

NT_MIC_DA TA

I

NT_MIC_CL K

1 2

@

@

392 0_060 3_5%

392 0_060 3_5%

R

R

+

LCD_INV

2

2

2

013/01/2 2 2014/01/2 1

013/01/2 2 2014/01/2 1

013/01/2 2 2014/01/2 1

C

5VS

+

3VS

+

LCD_VDD

+

3VS

1 2

IEDP@

IEDP@

154 0_040 2_5%

154 0_040 2_5%

R

R

1.5A

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

I

rush=1.5A

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

I

NT_MIC_DA TA <32>

I

NT_MIC_CL K <32 >

L

VDS_HPD <19,7>

D

NT_MIC_DATA

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

6

6

SC30000 1400

SC30000 1400

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

L

L

L

VDS

VDS

VDS

L

L

L

A-9869P

A-9869P

A-9869P

1

I

NT_MIC_CL K

1

close to LVDS conn.

o

o

o

f

20 50Monday, Febru ary 04, 2013

f

20 50Monday, Febru ary 04, 2013

f

20 50Monday, Febru ary 04, 2013

E

0

0

0

.3

.3

.3

A

1 1

U

MA_CRT_ R<2 5>

U

MA_CRT_ G<25>

U

MA_CRT_ B<25>

R

R

R

R

R

R

140

140

139

139

138

138

12

12

1

50_0402_1%

50_0402_1%

50_0402_1%

50_0402_1%

50_0402_1%

50_0402_1%
1

1

1

1

1

1

2

2 2

+

HDMI_5V_O UT

2

C

C

0.1U_040 2_10V7K

0.1U_040 2_10V7K

1

N

U

MA_CRT_ DATA<25>

U

3 3

MA_CRT_ CLK<25>

U

MA_CRT_ VSYNC<25>

U

MA_CRT_ HSYNC<25>

282

282

ear U3.1

B

238

238

C

C

MI@

MI@

E

E

1

1

C

C

239

239

2

2

.2P_0402_50V8C

.2P_0402_50V8C
2

2

E

E

MI@

MI@

+

HDMI_5V_O UT

U

MA_CRT_ DATA

U

MA_CRT_ CLK

U

MA_CRT_ VSYNC

U

MA_CRT_ HSYNC

EMI@

EMI@

1 2

L

L

3 N BQ100505T-800 Y_0402

3 N BQ100505T-800 Y_0402

EMI@

EMI@

1 2

L

L

4 N BQ100505T-800 Y_0402

4 N BQ100505T-800 Y_0402

EMI@

EMI@

2

1

L

L

5 N BQ100505T-800 Y_0402

5 N BQ100505T-800 Y_0402

1

C

C

240

240

2

.2P_0402_50V8C

.2P_0402_50V8C

.2P_0402_50V8C

.2P_0402_50V8C
2

2

2

2

E

E

MI@

MI@

+

3VS

+

3VS

1

C

C

C

C

242

241

241

242

2

.2P_0402_50V8C

.2P_0402_50V8C
2

2

E

E

MI@

MI@

E

E

1

2

7

10

11

13

15

6

C

1

2

MI@

MI@

U

U

CC_SYNC

V

CC_VIDEO

V

CC_DDC

V

DC_IN1

D

DC_IN2

D

YNC_IN1

S

YNC_IN2

S

ND

G

TPD7S01 9-15DBQR_SSOP 16

TPD7S01 9-15DBQR_SSOP 16

SA000068B00

1

243

243

C

C

2

.2P_0402_50V8C

.2P_0402_50V8C
2

2

4

4

.2P_0402_50V8C

.2P_0402_50V8C
2

2

D

D

YNC_OUT1

S

YNC_OUT2

S

MI@

MI@

E

E

IDEO1

V

IDEO2

V

IDEO3

V

DC_OUT1

DC_OUT2

D

C

RT_R_L

C

RT_G_L

C

RT_B_L

J

J

CRT

CRT

6

1

65 PADT65 PAD

T

C

RT_R_L

C

RT_DDC_ DAT

C

RT_G_L

H

SYNC

C

HDMI_5V_O UT

2

R

R

159

159

4.7K_040 2_5%

4.7K_040 2_5%

1

1 2

RT_B_L

V

SYNC

C

RT_DDC_ CLK

C

RT_DDC_ DAT

C

RT_DDC_ CLK

V

SYNC

H

SYNC

T

66 PADT66 PAD

+

HDMI_5V_O UT

R

R

4.7K_040 2_5%

4.7K_040 2_5%

+

153

153

22_0402 _5%

22_0402 _5%

22_0402 _5%

22_0402 _5%

8

YP

B

3

4

5

9

12

14

16

2

1

C

C

19 0.2 2U_0402_16V7 K

19 0.2 2U_0402_16V7 K

C

RT_B_L

C

RT_G_L

C

RT_R_L

V

SYNC_R

H

SYNC_R

67

67

R

R

R

R

66

66

1 2

1 2

1
1
7

1

2
2
8

1

3
3
9

1

4
4

1

0

1

5
5

C-H_13-12 201513CP

C-H_13-12 201513CP

E

@

@

1

6

G

G

1

7

G

G

4 4

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

2

2

2

013/01/2 2 2014/01/2 1

013/01/2 2 2014/01/2 1

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

013/01/2 2 2014/01/2 1

C

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

D

Date: Sheet

ompal Electronics, Inc.

C

C

C

RT

RT

RT

L

L

L

A-9869P

A-9869P

A-9869P

2

2

2

1 50Monday, February 04, 2 013

1 50Monday, February 04, 2 013

1 50Monday, February 04, 2 013

E

0

0

0

.3

.3

.3

o

o

o

f

f

f

5

1 2

V308 0. 1U_0402_16 V7K

V308 0. 1U_0402_16 V7K

C

U

MA_HDMI_TXC+<7>

U

MA_HDMI_TXC-<7>

U

MA_HDMI_TX0 +<7>

U

D D

C C

MA_HDMI_TX0 -<7>

U

MA_HDMI_TX1 +<7>

U

MA_HDMI_TX1 -<7>

U

MA_HDMI_TX2 +<7>

U

MA_HDMI_TX2 -<7>

V

GA_DVI_TX C-

V

GA_DVI_TX C+

V

GA_DVI_TX D0-

V

GA_DVI_TX D0+

V

GA_DVI_TX D1-

V

GA_DVI_TX D1+

C

2

1

V304 0. 1U_0402_16 V7K

V304 0. 1U_0402_16 V7K

C

C

1 2

V306 0. 1U_0402_16 V7K

V306 0. 1U_0402_16 V7K

C

C

1 2

V302 0. 1U_0402_16 V7K

V302 0. 1U_0402_16 V7K

C

C

1 2

V303 0. 1U_0402_16 V7K

V303 0. 1U_0402_16 V7K

C

C

1 2

V301 0. 1U_0402_16 V7K

V301 0. 1U_0402_16 V7K

C

C

2

1

V307 0. 1U_0402_16 V7K

V307 0. 1U_0402_16 V7K

C

C

2

1

V305 0. 1U_0402_16 V7K

V305 0. 1U_0402_16 V7K

C

C

8

EMI@L8

EMI@

L

1

1

4

4

WCM-201 2-900T_0805

WCM-201 2-900T_0805

EMI@L9

EMI@

1

1

4

4

WCM-201 2-900T_0805

WCM-201 2-900T_0805

EMI@L10

EMI@

1

1

4

4

WCM-201 2-900T_0805

WCM-201 2-900T_0805

2

2

3

3

9

L

2

2

3

3

L

10

2

2

3

3

H

DMI_R_CK-

H

DMI_R_CK+

H

DMI_R_D0-

H

DMI_R_D0+

H

DMI_R_D1-

H

DMI_R_D1+

V

GA_DVI_TX C+

V

GA_DVI_TX C-

V

GA_DVI_TX D0+

V

GA_DVI_TX D0-

V

GA_DVI_TX D1+

V

GA_DVI_TX D1-

V

GA_DVI_TX D2+

V

GA_DVI_TX D2-

4

2

1

H

DMI_R_CK+

195 60 4_0402_1 %

195 60 4_0402_1 %

R

R

1 2

H

DMI_R_CK-

197 60 4_0402_1 %

197 60 4_0402_1 %

R

R

2

1

H

DMI_R_D1-

198 60 4_0402_1 %

R

R

198 60 4_0402_1 %

1 2

H

DMI_R_D1+

202 60 4_0402_1 %

202 60 4_0402_1 %

R

R

1 2

H

DMI_R_D0+

201 60 4_0402_1 %

201 60 4_0402_1 %

R

R

1 2

H

DMI_R_D0-

203 60 4_0402_1 %

203 60 4_0402_1 %

R

R

2

1

H

DMI_R_D2-

205 60 4_0402_1 %

205 60 4_0402_1 %

R

R

2

1

H

DMI_R_D2+

R

R

206 60 4_0402_1 %

206 60 4_0402_1 %

+

5VS

C

hange R184 and R185 from 2K to 4.7K

for HDMI detect issue on Comal

+

U

U

MA_HDMI_CL K<7>

U

MA_HDMI_DA TA<7>

MA_HDMI_CL K

U

MA_HDMI_DA TA

S

S

G

G

2

3

1

D

S

D

S

19

19

Q

Q

FDV301N-NL _SOT23-3

FDV301N-NL _SOT23-3

Q18/Q19
Change to FDV301 due to BSH111 EOL

2

G

G

3VS

G

G

2

13

D

D

18

18

Q

Q

FDV301N-NL _SOT23-3

FDV301N-NL _SOT23-3

13

D

D

24

24

Q

Q
2N7002K W_SOT323-3

2N7002K W_SOT323-3

S

S

H

DMI_SCLK

H

DMI_SDATA

3

H

DMI POWER CIRCUIT

V

IN = 5V, IOUT = 0.5A , RDS(ON) TYP=95m ; MAX=115m

Current Limit: TYP=0.8A ; MAX=1A

+

C

C

0.1U_040 2_10V7K

0.1U_040 2_10V7K

HDMI_5V_O UT

1

284

284

2

+

HDMI_5V_O UT

H

DMI_HPD_U

5

1

U

U

P

E#

2

O

Y

A

G

74AHCT1G1 25GW_SO T353-5

74AHCT1G1 25GW_SO T353-5

3

H

DMI_HPD

9

9

4

U

U

17

17

1

O

UT

2

G

ND

3

F

LG

AP2151D WG-7_SOT25 -5

AP2151D WG-7_SOT25 -5

S

A00006H000

145

145

R

R

1 2

1K_0402 _5%

1K_0402 _5%

100K_04 02_5%

100K_04 02_5%

H

DMI_HPD

571

571

R

R

2.2K_04 02_5%

2.2K_04 02_5%

2

+

5VS

5

I

N

4

E

N

H

DMI_HPD_C

2

186

186

265

265

C

C

R

R

0.1U_040 2_16V4Z

0.1U_040 2_16V4Z

1

1 2

12

+

3VS

H

DMI_HPD <2 4,7>

+

HDMI_5V_O UT

H

DMI Royalty

H

DMI_HPD_C

H

DMI_SDATA

H

DMI_SCLK

H

DMI_R_CK-

H

DMI_R_CK+

H

DMI_R_D0-

H

DMI_R_D0+

H

DMI_R_D1-

H

DMI_R_D1+

H

DMI_R_D2-

H

DMI_R_D2+

H

DMI Connector

1

ZZ

HDMI45@

ZZ

HDMI45@

Z

Z

RO0000003HM

HDMI W/L ogo + HDCP

HDMI W/L ogo + HDCP

HDMI W/O Logo: RO0000001HM
HDMI W/Logo: RO0000002HM
HDMI W/Logo + HDCP: RO0000003HM

J

J

HDMI @

HDMI @

19

H

P_DET

18

+

5V

17

D

DC/CEC_GND

16

S

DA

15

S

CL

14

R

eserved

13

C

EC

12

C

K-

11

C

K_shield

10

C

K+

9

D

0-

8

D

0_shield

7

D

0+

6

D

1-

5

D

1_shield

4

D

3

D

2

D

1

D

TYCO_20413 43-1~D

TYCO_20413 43-1~D

1+
2­2_shield
2+

23

G

ND

22

G

ND

21

G

ND

20

G

ND

P1

11

EMI@L11

EMI@

V

GA_DVI_TX D2-

V

GA_DVI_TX D2+

B B

A A

1

4

5

L

1

2

3

4

WCM-201 2-900T_0805

WCM-201 2-900T_0805

2

H

DMI_R_D2-

3

H

DMI_R_D2+

+

HDMI_5V_O UT

+

3VS

4

P1

R

R

1 8
2
3 6
4 5

4.7K_8P 4R_5%

4.7K_8P 4R_5%

7

U

MA_HDMI_DA TA

U

MA_HDMI_CL K

H

DMI_SCLK

H

DMI_SDATA

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONFI DENTIAL

HIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONFI DENTIAL

HIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONFI DENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

3

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

2

2

2

013/01/22 2014/01/21

013/01/22 2014/01/21

013/01/22 2014/01/21

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

Title

itle

itle

Size Docu ment Number Rev

Size Docu ment Number Rev

Size Docu ment Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

H

H

H

DMI Conn./CEC

DMI Conn./CEC

DMI Conn./CEC

L

L

L

A-9869P

A-9869P

A-9869P

1

2

2

o

o

2

o

f

2 50Monday, February 04 , 2013

f

2 50Monday, February 04 , 2013

f

2 50Monday, February 04 , 2013

0

0

0

.3

.3

.3

A

A

PU_PCIE_RST#_R

L

1 2

202 0.1U_0402_16V7K

202 0.1U_0402_16V7K

C

U

MI_MTX_C_FRX_P0<5>

U

MI_MTX_C_FRX_N0<5>

U

MI_MTX_C_FRX_P1<5>

U

MI_MTX_C_FRX_N1<5>

U

MI_MTX_C_FRX_P2<5>

U

MI_MTX_C_FRX_N2<5>

U

MI_MTX_C_FRX_P3<5>

U

1 1

2 2

MI_MTX_C_FRX_N3<5>

U

MI_FTX_C_MRX_P0<5>

U

MI_FTX_C_MRX_N0<5>

U

MI_FTX_C_MRX_P1<5>

U

MI_FTX_C_MRX_N1<5>

U

MI_FTX_C_MRX_P2<5>

U

MI_FTX_C_MRX_N2<5>

U

MI_FTX_C_MRX_P3<5>

U

MI_FTX_C_MRX_N3<5>

+

PCIE_VDDR_FCH

+

1.1VS_CKVDD

SS

APU DISP

NSS

APU

F

or DIS

W

LAN

SS

L

AN

3 3

F

CH_RTCX1_R<29>

F

CH_X1_R<29>

C

1 2

203 0.1U_0402_16V7K

203 0.1U_0402_16V7K

C

C

2

1

204 0.1U_0402_16V7K

204 0.1U_0402_16V7K

C

C

1 2

C

C

209 0.1U_0402_16V7K

209 0.1U_0402_16V7K

1 2

C

C

210 0.1U_0402_16V7K

210 0.1U_0402_16V7K

1 2

211 0.1U_0402_16V7K

211 0.1U_0402_16V7K

C

C

1 2

213 0.1U_0402_16V7K

213 0.1U_0402_16V7K

C

C

1 2

C

C

212 0.1U_0402_16V7K

212 0.1U_0402_16V7K

1 2

220 590_0402_1%

220 590_0402_1%

R

R

1

221 2K_0402_1%

221 2K_0402_1%

R

R

1

228 2K_0402_1%

228 2K_0402_1%

R

R

I
NC for internal clock generator

A

PU_DISP_CLK<7>

A

PU_DISP_CLK#<7>

c

lock no test point

A

PU_CLK<7>

A

PU_CLK#<7>

C

LK_PCIE_VGA<12>

C

LK_PCIE_VGA#<12>

C

LK_WLAN<28>

C

LK_WLAN#<28>

C

LK_LAN<30>

C

LK_LAN#<30>

P

lace close to Y2

1 2

@

@

R

R

207 0_0402_5%

207 0_0402_5%

1 2

@

@

R

R

208 0_0402_5%

208 0_0402_5%

nput from external clock generator

PC_RST#_R

U

MI_MTX_FRX_P0

U

MI_MTX_FRX_N0

U

MI_MTX_FRX_P1

U

MI_MTX_FRX_N1

U

MI_MTX_FRX_P2

U

MI_MTX_FRX_N2

U

MI_MTX_FRX_P3

U

MI_MTX_FRX_N3

P

2

2

CIE_CALRP

P

CIE_CALRN

C

LK_CALRN

C

LK_PCIE_VGA

C

LK_PCIE_VGA#

3

2K_X1

2

5M_X1

Place close to Y1

1 2

220 27P_0402_50V8J

220 27P_0402_50V8J

C

C

NOGCLK@

NOGCLK@

NOGCLK@

NOGCLK@

2

1

27P_0402_50V8J

27P_0402_50V8J

230

230

C

4 4

C

2

1

248 18P_0402_50V8JNOGCLK@C248 18P_0402_50V8JNOGCLK@

C

12

R

R

230

230

20M_0402_5%

20M_0402_5%

NOGCLK@

NOGCLK@

1 2

249 18P_0402_50V8JNOGCLK@C249 18P_0402_50V8JNOGCLK@

C

C

hange C248/C249 to 18P

for RTC issue on pre-MP

1 2

A

25MHZ 12PF X3G025000DK1H-X

25MHZ 12PF X3G025000DK1H-X

1

1

NOGCLK@

NOGCLK@

Y

Y
3

2

G

4

G

2

2

Y

Y

32.768KHZ_12.5P_1TJF125DP1A000D

32.768KHZ_12.5P_1TJF125DP1A000D

NOGCLK@

NOGCLK@

3

ND

ND

3

3

229

229

R

R
1M_0402_5%

1M_0402_5%

NOGCLK@

NOGCLK@

3

3

2

2

2K_X1

2K_X2

5M_X1

5M_X2

B

1A

1A

U

U

UDSON-3

UDSON-3

H

AE2

CIE_RST#

P

AD5

_RST#

A

AE30

MI_TX0P

U

AE32

MI_TX0N

U

AD33

MI_TX1P

U

AD31

MI_TX1N

U

AD28

MI_TX2P

U

AD29

MI_TX2N

U

AC30

MI_TX3P

U

AC32

MI_TX3N

U

AB33

MI_RX0P

U

AB31

MI_RX0N

U

AB28

MI_RX1P

U

AB29

MI_RX1N

U

Y33

MI_RX2P

U

Y31

MI_RX2N

U

Y28

MI_RX3P

U

Y29

MI_RX3N

U

AF29

CIE_CALRP

P

AF31

CIE_CALRN

P

V33

PP_TX0P

G

V31

PP_TX0N

G

W30

PP_TX1P

G

W32

PP_TX1N

G

AB26

PP_TX2P

G

AB27

PP_TX2N

G

AA24

PP_TX3P

G

AA23

PP_TX3N

G

AA27

PP_RX0P

G

AA26

PP_RX0N

G

W27

PP_RX1P

G

V27

PP_RX1N

G

V26

PP_RX2P

G

W26

PP_RX2N

G

W24

PP_RX3P

G

W23

PP_RX3N

G

F27

LK_CALRN

C

G30

CIE_RCLKP

P

G28

CIE_RCLKN

P

R26

ISP_CLKP

D

T26

ISP_CLKN

D

H33

ISP2_CLKP

D

H31

ISP2_CLKN

D

T24

PU_CLKP

A

T23

PU_CLKN

A

J30

LT_GFX_CLKP

S

K29

S

LT_GFX_CLKN

H27

G

PP_CLK0P

H28

G

PP_CLK0N

J27

G

PP_CLK1P

K26

G

PP_CLK1N

F33

G

PP_CLK2P

F31

G

PP_CLK2N

E33

G

PP_CLK3P

E31

G

PP_CLK3N

M23

G

PP_CLK4P

M24

G

PP_CLK4N

M27

G

PP_CLK5P

M26

G

PP_CLK5N

N25

G

PP_CLK6P

N26

G

PP_CLK6N

R23

G

PP_CLK7P

R24

G

PP_CLK7N

N27

G

PP_CLK8P

R27

G

PP_CLK8N

J26

1

4M_25M_48M_OSC

C31

2

5M_X1

C33

2

5M_X2

2180755042A13HUDSON_FCBGA656 BOLTONR1@

2180755042A13HUDSON_FCBGA656 BOLTONR1@

@EMI@

2

5M_X1

B

@EMI@

H

CI CLKS

CI CLKS
P

P

CI EXPRESS INTERFACES

CI EXPRESS INTERFACES
P

P

CI INTERFACE

CI INTERFACE
P

P

INT 15K PU

INT 8.2K PU

INT 8.2K PU

LOCK GENERATOR

LOCK GENERATOR
C

C

PC

PC
L

L

INT 8.2K PU

PU

PU
A

A

5 PLUS

5 PLUS
S

S

507

507

C

C

2

1

12

11610_0402_5%

11610_0402_5%

R

R

10P_0402_50V8J

10P_0402_50V8J

P

R

EQ2#/CLK_REQ8#/GPIO41

R

EQ3#/CLK_REQ5#/GPIO42

G

NT3#/CLK_REQ7#/GPIO46

L

DRQ1#/CLK_REQ6#/GPIO49

@EMI@

@EMI@

P

CICLK0

P

CICLK1/GPO36

P

CICLK2/GPO37

P

CICLK3/GPO38

CICLK4/14M_OSC/GPO39

P

CIRST#

A

D0/GPIO0

A

D1/GPIO1

A

D2/GPIO2

A

D3/GPIO3

A

D4/GPIO4

A

D5/GPIO5

A

D6/GPIO6

A

D7/GPIO7

A

D8/GPIO8

A

D9/GPIO9

A

D10/GPIO10

A

D11/GPIO11

A

D12/GPIO12

A

D13/GPIO13

A

D14/GPIO14

A

D15/GPIO15

A

D16/GPIO16

A

D17/GPIO17

A

D18/GPIO18

A

D19/GPIO19

A

D20/GPIO20

A

D21/GPIO21

A

D22/GPIO22

A

D23/GPIO23

A

D24/GPIO24

A

D25/GPIO25

A

D26/GPIO26

A

D27/GPIO27

A

D28/GPIO28

A

D29/GPIO29

A

D30/GPIO30

A

D31/GPIO31

C

BE0#

C

BE1#

C

BE2#

C

BE3#

F

RAME#

D

EVSEL#

I

RDY#

T

RDY#

P

S

TOP#

P

ERR#

S

ERR#

R

EQ0#

R

EQ1#/GPIO40

G

NT0#

G

NT1#/GPO44

G

NT2#/SD_LED/GPO45

C

LKRUN#

L

OCK#

I

NTE#/GPIO32

I

NTF#/GPIO33

I

NTG#/GPIO34
I

NTH#/GPIO35

L

PCCLK0

L

PCCLK1

L

AD0

L

AD1

L

AD2

L

AD3

L

FRAME#

L

DRQ0#

S

ERIRQ/GPIO48

D

MA_ACTIVE#

P

ROCHOT#

A

PU_PG

L

DT_STP#

A

PU_RST#

S

5_CORE_EN

R

TCCLK

I

NTRUDER_ALERT#

V

DDBT_RTC_G

3

2K_X1

3

2K_X2

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

AF3
AF1
AF5
AG2
AF6

AB5

AJ3
AL5
AG4
AL6
AH3
AJ5
AL1
AN5
AN6
AJ1
AL8
AL3
AM7
AJ6
AK7
AN8
AG9
AM11
AJ10
AL12
AK11
AN12
AG12
AE12
AC12
AE13
AF13
AH13
AH14
AD15
AC15
AE16
AN3
AJ8
AN10
AD12
AG10
AK9
AL10
AF10
AE10

AR

AH1
AM9
AH8
AG15
AG13
AF15
AM17
AD16
AD13
AD21
AK17
AD19
AH9

AF18
AE18
AC16
AD18

B25

D25
D27
C28
A26
A29
A31
B27
AE27
AE19

G25
E28
E26
G26
F26

H7
F1
F3
E6

G2

G4

ssued Date

ssued Date

ssued Date

C

C

V

RAM_SEL

G

PIO30

G

PIO31

L

PC_CLK0

L

PC_CLK1

A

PU_PROCHOT#

A

PU_PWRGD

A

PU_RST#

+

RTCVCC_R

3

2K_X1

3

2K_X2

D

P

CI_CLK1 < 26>

P

CI_CLK3 < 26>

P

CI_CLK4 < 26>

P

CI_AD23 < 26>

P

CI_AD24 < 26>

P

CI_AD25 < 26>

P

CI_AD26 < 26>

P

CI_AD27 < 26>

X76

H:1G
L:900M

1 2

255 22_0402_5%EMI@

255 22_0402_5%EMI@

R

R

1 2

R

R

258 22_0402_5%EMI@

258 22_0402_5%EMI@

T

35T35

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

2

2

013/01/22 2014/01/21

013/01/22 2014/01/21

013/01/22 2014/01/21

2

1

@

@

R

R

260 0_0402_5%

260 0_0402_5%

2

0 mils

C

C

250

250

S

trap

V

RAM_SEL

1

1

C

C

252

252

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

+

3VS

2

C95

C95

R

R
10K_0402_5%

10K_0402_5%

@

@

1

2

C99

C99

R

R
10K_0402_5%

10K_0402_5%

@

@

1

C

LK_PCI_EC <26,34>

C

LK_PCI_DDR <26>

L

PC_AD0 <34>

L

PC_AD1 <34>

L

PC_AD2 <34>

L

PC_AD3 <34>

L

PC_FRAME# <34>

S

ERIRQ <34>

D

MA_ACTIVE# <7>

A

PU_PROCHOT# < 7>

A

PU_PWRGD <45,7>

A

PU_RST# <7>

R

TC_CLK <26,34>

1 2

120_0402_5%

120_0402_5%

+

RTCVCC

271

271

R

R

D

Near FCH

PCIE_RST# is for PCIE devices on APU

2

A

PU_PCIE_RST#_R

L

PC_RST#_R

1 2

337 10K_0402_5%

337 10K_0402_5%

R

R

1 2

R

R

340 10K_0402_5%

340 10K_0402_5%

1

225 33_0402_5%

225 33_0402_5%

R

R

150P_0402_50V8J

150P_0402_50V8J

1 2

226 33_0402_5%

226 33_0402_5%

R

R

150P_0402_50V8J

150P_0402_50V8J

VGA@

VGA@

VGA@

VGA@

G

G

PIO30

PIO31

1

221

221

C

C

2

1

C

C

222

222

2

1 2

R

R

332 10K_0402_5%

332 10K_0402_5%

1 2

339 10K_0402_5%

339 10K_0402_5%

R

R

UMA@

UMA@

UMA@

UMA@

Function GPIO30 GPIO31

PowerXpres s

0 0

Reserved

Discrete

UMA

D

MA active. The FCH drives the DMA_ACTIVE# to
APU to notify DMA activity. This will cause the APU
to reestablish the UMI link quicker.

APU_PG/APU_RST#/LDT_STP# : OD pin
D

MA_ACTIVE# : IN/OD, 0.8V threshold
PROCHOT# : IN, 0.8V threshold
LDT_STP : No use, NC

277

277

R

R

1 2

120_0402_5%

120_0402_5%

12

CMOS

CMOS

J

J

@

@

C

MOS Setting
Place under DDR
Door

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

1 1

+

RTCBATT_D

3

1

253

253
C

C

2

0.1U_0402_10V7K

0.1U_0402_10V7K

+

RTCBATT_D

1

C

C

295

295

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

H

H

H

udson-M3-UMI/PCI/CLOCK/LPC/RTC

udson-M3-UMI/PCI/CLOCK/LPC/RTC

udson-M3-UMI/PCI/CLOCK/LPC/RTC

L

L

L

A-9869P

A-9869P

A-9869P

E

A

223

223

R

R
100K_0402_5%

100K_0402_5%

@

@

1 2

PU_PCIE_RST# <12 ,28,30>

A_RST# is for LPC devices

2

R

R
100K_0402_5%

100K_0402_5%

@

@

1

L

+

3VS

PC_RST# <34>

224

224

10

01

+

D

D

H1

H1

BAS40-04_SOT23-3

BAS40-04_SOT23-3

2

E

RTCBATT

+

3VL

23 50Monday, February 04, 2013

23 50Monday, February 04, 2013

23 50Monday, February 04, 2013

1

0

0

0

.3

.3

.3

o

o

o

f

f

f

A

P

CIE_RST2# is for PCIE devices on FCH

3VALW _FCH

+

+

3VS

283

283

R

2

G

G

S

H

DMI_HPD<22,7>

1 1

@ESD@

@ESD@

1 2

505 18 0P_0402_5 0V8J

505 18 0P_0402_5 0V8J

C

C

V
L: MLDAC power on
H: MLDAC power off

2 2

F

or ESD request

@ESD@

@ESD@

2

1

503 1 80P_0402_ 50V8J

503 1 80P_0402_ 50V8J

C

C

2

1

504 1 80P_0402_ 50V8J

504 1 80P_0402_ 50V8J

C

C

ESD@

ESD@

+

3VALW _FCH

P12

P12

R

R

1
2 7
3 6
4

10K_8P4 R_5%

10K_8P4 R_5%

S

30

30

Q

Q
2N7002K W_SOT323-3

2N7002K W_SOT323-3

F

CH_PWRG D

GA_PD: Support CRT power saving

U

SB_OC2# is for right USB2.0 ports

USB_CHG_OC# is for right USB3.0 ports

U

SB_OC0# is for right USB3.0 ports

P

XS_RST#

O

DD_DA#_FC H

8

H

_THERMTRIP#

U

SB_OC#0

U

SB_CHG_O C#

5

U

SB_OC#2

R
10K_040 2_5%

10K_040 2_5%

1 2

13

D

D

H

DMI_HPD_FCH

+

3VS

S

M Bus 0-->S0 PWR domain
SM Bus 1-->S5 PWR domain
(for ASF device only)

C

or DIS

LKREQ_P EG#<13 >

A

Z_BITCLK_HD<32>

A

Z_SDOUT_HD<32>

A

Z_SDIN0_H D<32>

A

Z_SYNC_HD<32 >

A

Z_RST_HD#<32 >

F

2

1

279 10 K_0402_5%

279 10 K_0402_5%

R

R

F

or DIS

For DIS

+

3VALW _FCH

3 3

+

3VS

4 4

12

@

@

282 10 0K_0402_5 %

282 10 0K_0402_5 %

R

R

1 2

281 10 K_0402_5%

281 10 K_0402_5%

R

R

1 2

288 2. 2K_0402_5 %

288 2. 2K_0402_5 %

R

R

1 2

289 2. 2K_0402_5 %

289 2. 2K_0402_5 %

R

R

For FCH internal debug use

1 2

@

@

290 2. 2K_0402_5 %

290 2. 2K_0402_5 %

R

R

1 2

@

@

R

R

292 2. 2K_0402_5 %

292 2. 2K_0402_5 %

1 2

@

@

293 2. 2K_0402_5 %

293 2. 2K_0402_5 %

R

R

2

1

296 10 K_0402_5%

296 10 K_0402_5%

R

R

1 2

286 2. 2K_0402_5 %

286 2. 2K_0402_5 %

R

R

2

1

R

R

287 2. 2K_0402_5 %

287 2. 2K_0402_5 %

1 2

291 8. 2K_0402_5 %

291 8. 2K_0402_5 %

R

R

1 2

284 8. 2K_0402_5 %

284 8. 2K_0402_5 %

R

R

For DIS

1 2

@

@

297 10 K_0402_5%

297 10 K_0402_5%

R

R

2

1

280 2. 2K_0402_5 %

280 2. 2K_0402_5 %

R

R

1 2

@

@

324 10 K_0402_5%

324 10 K_0402_5%

R

R

2

1

@

@

269 1K _0402_5%

269 1K _0402_5%

R

R

P10

P10

R

R

1 8

A

7

2

A

3 6

A

4 5

10K_8P4 R_5%

10K_8P4 R_5%

A

@

@

E

F

P

XS_PW REN

F

CH_SCLK0

F

CH_SDATA0

C

LKREQ_W LAN#

C

LKREQ_L AN#

P

XS_PW REN

E

C_RSMRST#

H

DA_BITCLK

P

XS_RST#

Z_SDIN1_H D
Z_SDIN3_H D
Z_SDIN2_H D
Z_SDIN0_H D

C_LID_OUT#

CH_PCIE_W AKE#

F

CH_SCLK1

F

CH_SDATA1

T

EST0

T

EST1

T

EST2

For DIS

A

For DIS

P

XS_PW REN

2N7002K DWH_SOT363 -6

2N7002K DWH_SOT363 -6

Q

Q
2N7002K DWH_SOT363 -6

2N7002K DWH_SOT363 -6

4

E

C_LID_OUT#<34>

P

BTN_OUT#<34>

F

CH_PWRG D<34>

G

K
E
E

F

CH_PCIE_W AKE#<30>

H

_THERMTRIP#<7>

E

C_RSMRST#<34>

C

LKREQ_L AN#<30>

F

CH_SPKR<32 >

F

CH_SCLK0<10,1 1,28>

F

CH_SDATA0<10,11, 28>

F

CH_SCLK1<36>

F

CH_SDATA1<36>

C

LKREQ_W LAN#<28>

V

GA_PW RGD<14,43,46>

1 2

295 0 _0402_5%

295 0 _0402_5%

R

R

129 1 00K_0402_ 5%@R129 1 00K_0402_ 5%@

R

O

DD_PLUGIN #<28>

U

U

SB_CHG_O C#<31,34>

U

1

320 33_0402 _5%EMI@

320 33_0402 _5%EMI@

R

R

1

321 33_0402 _5%

321 33_0402 _5%

R

R

1 2

322 33_0402 _5%

322 33_0402 _5%

R

R

1

323 33_0402 _5%

323 33_0402 _5%

R

R

P

XS_RST#<12>

P

XS_PW REN<14,46,47 >

5530A

5530A

Q

Q

1

6

5530B

5530B

2

3

E

C_PXCONTROL

5

S

LP_S3#<34>

S

LP_S5#<34>

ATEA20<34>

B_RST#<34>
C_SCI#<34>
C_SMI#<34>

L

AN_EN<30>

12

SB_OC#2<30,34 >

SB_OC#0<31,34 >

2
2

2

P

XS_RST#

P

XS_PW REN

F

T
T
T

W

F
F
F
F

H

DMI_HPD_FCH

O

DD_DA#_FC H

U
U
U

H

DA_BITCLK

H

DA_SDOUT

A

Z_SDIN1_H D

A

Z_SDIN2_H D

A

Z_SDIN3_H D

H

DA_SYNC

H

DA_RST#

12

E

C_PXCONTROL <34>

B

50

T50T

CH_PWRG D

EST0
EST1
EST2

D_PWRG D

CH_SCLK0
CH_SDATA0
CH_SCLK1
CH_SDATA1

SB_OC#2
SB_CHG_O C#
SB_OC#0

26

T26T

+

3VALW

21610K_040 2_5%

21610K_040 2_5%

R

R

B

U

U

1D

1D

AB6

P

CIE_RST2#/ GEVENT4#

R2

R

I#/GEVEN T22#

W7

S

PI_CS3#/ GBE_STAT1/GEV ENT21#

T3

S

LP_S3#

W2

S

LP_S5#

J4

P

WR_BTN#

N7

P

WR_GOO D

T9

T

EST0

T10

T

EST1/TMS

V9

T

EST2

AE22

G

AG19

K

BRST#/GEV ENT1#

R9

P

ME#/GEVE NT3#

C26

L

PC_SMI#/G EVENT23#

T5

L

PC_PD#/G EVENT5#

U4

S

YS_RESET#/G EVENT19#

K1

W

V7

I

R_RX1/GE VENT20#

R10

T

HRMTRIP#/SMB ALERT#/GEVEN T2#

AF19

W

U2

R

AG24

C

AE24

C

AE26

S

MARTVOLT1/SA TA_IS2#/GPIO 50

AF22

C

AH17

S

ATA_IS4#/ FANOUT3/GPIO5 5

AG18

S

ATA_IS5#/ FANIN3/GPIO5 9

AF24

S

PKR/GPIO 66

AD26

S

CL0/GPIO 43

AD25

S

DA0/GPIO 47

T7

S

CL1/GPIO 227

R7

S

DA1/GPIO 228

AG25

C

AG22

C

J2

I

R_LED#/L LB#/GPIO18 4

AG26

S

MARTVOLT2/SH UTDOWN#/GPIO 51

V8

D

W8

G

Y6

S

PI_HOLD# /GBE_LED1/G EVENT9#

V10

G

AA8

G

AF25

C

M7

B

LINK/USB_ OC7#/GEVEN T18#

R8

U

T1

U

P6

U

F5

U

P5

U

J7

U

T8

U

AB3

A

Z_BITCLK

AB1

A

Z_SDOUT

AA2

A

Z_SDIN0/G PIO167

Y5

A

Z_SDIN1/G PIO168

Y3

A

Z_SDIN2/G PIO169

Y1

A

Z_SDIN3/G PIO170

AD6

A

Z_SYNC

AE4

A

Z_RST#

K19

P

S2_DAT/SDA 4/GPIO187

J19

P

S2_CLK/C EC/SCL4/GPIO 188

J21

S

PI_CS2#/ GBE_STAT2/GPI O166

D21

P

S2KB_DA T/GPIO189

C20

P

S2KB_CL K/GPIO190

D23

P

S2M_DAT/GP IO191

C22

P

S2M_CLK/ GPIO192

F21

K

SO_0/GP IO209

E20

K

SO_1/GP IO210

F20

K

SO_2/GP IO211

A22

K

SO_3/GP IO212

E18

K

SO_4/GP IO213

A20

K

SO_5/GP IO214

J18

K

SO_6/GP IO215

H18

K

SO_7/GP IO216

G18

K

SO_8/GP IO217

B21

K

SO_9/GP IO218

K18

K

SO_10/G PIO219

D19

K

SO_11/G PIO220

A18

K

SO_12/G PIO221

C18

K

SO_13/G PIO222

B19

K

SO_14/X DB0/GPIO22 3

B17

K

SO_15/X DB1/GPIO22 4

A24

K

SO_16/X DB2/GPIO22 5

D17

K

SO_17/X DB3/GPIO22 6

2180755 042A13HUDS ON_FCBGA65 6

2180755 042A13HUDS ON_FCBGA65 6

I

AKE#/GE VENT8#

D_PWRG D

NT 8.2K PU

INT 8.2K PU

INT 10K PU

A20IN/GE VENT0#

SMRST#

LK_REQ4 #/SATA_IS0#/ GPIO64
LK_REQ3 #/SATA_IS1#/ GPIO63

LK_REQ0 #/SATA_IS3#/ GPIO60

LK_REQ2 #/FANIN4/GPIO 62
LK_REQ1 #/FANOUT4/GPIO 61

DR3_RST#/GE VENT7#/VGA_ PD
BE_LED0 /GPIO183

BE_LED2 /GEVENT10#
BE_STAT0/GE VENT11#
LK_REQG #/GPIO65/O SCIN/IDLEEXIT#

SB_OC6# /IR_TX1/GEVEN T6#
SB_OC5# /IR_TX0/GEVEN T17#
SB_OC4# /IR_RX0/GEVE NT16#
SB_OC3# /AC_PRES/TDO/G EVENT15#
SB_OC2# /TCK/GEVENT14#
SB_OC1# /TDI/GEVENT13#
SB_OC0# /SPI_TPM_CS#/ TRST#/GEVENT12#

GEVENT#2~22 INT 10K PU

HUDSON-3

HUDSON-3

INT 8.2K PU

INT 10K PU

INT 50K PD

INT 10K PU

INT 10K PU

E

E

MBEDDED CTRL

MBEDDED CTRL

INT 10K PU

INT 10K PU

C

U

SBCLK/14 M_25M_48M_ OSC

U

SB MISC

SB MISC
U

U

INT 15K PD

INT 15K PD

SB 1.1

SB 1.1
U

U

CPI / WAKE UP EVENTS

CPI / WAKE UP EVENTS
A

A

SB 2.0

SB 2.0
U

U

PIO

PIO
G

G

SB OC

SB OC
U

U

D AUDIO

D AUDIO
H

H

SB 3.0

SB 3.0
U

U

E
E

E

C_PWM2 /EC_TIMER2/W OL_EN/GPIO 199

E

INT 10K PU

SB_RCOMP

U

SB_FSD1P /GPIO186

U

U

SB_FSD0P /GPIO185

U

U

SB_HSD13 P

U

SB_HSD13 N

U

SB_HSD12 P

U

SB_HSD12 N

U

SB_HSD11 P

U

SB_HSD11 N

U

SB_HSD10 P

U

SB_HSD10 N

U

SB_HSD9P

U

SB_HSD9N

U

SB_HSD8P

U

SB_HSD8N

SB_HSD7P

U

SB_HSD7N

U

SB_HSD6P

U

SB_HSD6N

U

SB_HSD5P

U

SB_HSD5N

U

SB_HSD4P

U

SB_HSD4N

U

SB_HSD3P

U

SB_HSD3N

U

SB_HSD2P

U

SB_HSD2N

U

SB_HSD1P

U

SB_HSD1N

U

SB_HSD0P

U

SB_HSD0N

U

SBSS_CA LRP

U

SBSS_CA LRN

U

SB_SS_TX 3P

U

SB_SS_TX 3N

U

SB_SS_R X3P

U

SB_SS_R X3N

U

SB_SS_TX 2P

U

SB_SS_TX 2N

U

SB_SS_R X2P

U

SB_SS_R X2N

U

SB_SS_TX 1P

U

SB_SS_TX 1N

U

SB_SS_R X1P

U

SB_SS_R X1N

U

SB_SS_TX 0P

U

SB_SS_TX 0N

U

SB_SS_R X0P

U

SB_SS_R X0N

U

S

CL2/GPIO 193

S

DA2/GPIO 194

S

CL3_LV/G PIO195

S

DA3_LV/G PIO196
C_PWM0 /EC_TIMER0/GPI O197
C_PWM1 /EC_TIMER1/GPI O198

C_PWM3 /EC_TIMER3/GPI O200

K

SI_0/GPI O201

K

SI_1/GPI O202

K

SI_2/GPI O203

K

SI_3/GPI O204

K

SI_4/GPI O205

K

SI_5/GPI O206

K

SI_6/GPI O207

K

SI_7/GPI O208

BOLTONR1@

BOLTONR1@

C

D

G8

B9

U

SB_RCOMP

H1
H3

SB_FSD1N

H6
H5

SB_FSD0N

H10
G10

K10
J12

G12
F12

K12
K13

B11
D11

E10
F10

C10
A10

H9
G9

A8
C8

F8
E8

C6
A6

C5
A5

C1
C3

E1
E3

C16

U

SBSS_CA LRP

A16

U

SBSS_CA LRN

A14
C14

C12
A12

D15
B15

E14
F14

F15
G15

H13
G13

J16
H16

J15
K15

H19
G19
G22
G21
E22
H22
J22
H21

K21
K22

F

or PCIE device reset on FS1

F22

(GFX,GLAN,WLAN,LVDS Travis)

F24
E24
B23
C24
F18

ecurity Classification

ecurity Classification

ecurity Classification

S

S

S

ssued Date

ssued Date

ssued Date

I

I

I

HIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONFI DENTIAL

HIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONFI DENTIAL

HIS SHEET OF ENGINEERING DRAWIN G IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONFI DENTIAL

T

T

T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FR OM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER TH IS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THIR D PARTY WITHOUT PRIOR WRITT EN CONSENT OF COMPAL ELECTRONICS, INC .

329 11.8K_0 402_1%

329 11.8K_0 402_1%

R

R

330 1K_0402 _1%

330 1K_0402 _1%

R

R

334 1K_0402 _1%

334 1K_0402 _1%

R

R

G

PIO193

G

PIO194

G

PIO195

G

PIO196

1 2

U

SB20_P1 1 <31>

U

SB20_N1 1 <31>

U

SB20_P1 0 <31>

U

SB20_N1 0 <31>

U

SB20_P4 <20>

U

SB20_N4 <20>

U

SB20_P3 <28>

U

SB20_N3 <28>

U

SB20_P2 <33>

U

SB20_N2 <33>

U

SB20_P1 <20>

U

SB20_N1 <20>

U

SB20_P0 <30>

U

SB20_N0 <30>

1 2

2

1

U

SB30_TX1 P < 31>

U

SB30_TX1 N <31>

U

SB30_RX 1P <31>

U

SB30_RX 1N <31>

U

SB30_TX0 P < 31>

U

SB30_TX0 N <31>

U

SB30_RX 0P <31>

U

SB30_RX 0N <31>

E

C_PWM2 <26>

013/01/22 2014/01/21

013/01/22 2014/01/21

013/01/22 2014/01/21

2

2

2

U

SB 3.0-Right 2

USB 3.0-Right 1

+

FCH_VDD_1 1_SSUSB_S

U

USB 3.0-Right 1

Strap

ompal Secret Data

ompal Secret Data

ompal Secret Data

C

C

C

eciphered Date

eciphered Date

eciphered Date

D

D

D

D

Touch

W

LAN (BT)

C

ard reader

Int. Camera

USB-Left 1

SB 3.0-Right 2

P8

P8

R

R

1 8
2 7

6

3

5

4

10K_8P4 R_5%

10K_8P4 R_5%

P

lace R425 and C363

close to FCH for ESD

O

DD_DA#_FC H

Hudson-M2/M3
OHCI (DEV-20, FUN-5)

Hudson-M2
OHCI (DEV-22, FUN-0)
EHCI (DEV-22, FUN-2)

Hudson-M3
XHCI (DEV-16, FUN-0)
XHCI (DEV-16, FUN-1)

Hudson-M2/M3
OHCI (DEV-19, FUN-0)
EHCI (DEV-19, FUN-2)

Hudson-M2/M3
OHCI (DEV-18, FUN-0)
EHCI (DEV-18, FUN-2)

<Support Wakeup>

H
XHCI (DEV-16, FUN-0)
XHCI (DEV-16, FUN-1)

1 2

425 0_ 0402_5%

425 0_ 0402_5%

R

R

udson-M3

@

@

E

+

3VS+3VS

2

311

311

R

R
10K_040 2_5%

2

32

32

Q

Q

1 3

O

DD_DA#_Q

2N7002K W_SOT323-3

2N7002K W_SOT323-3

D

D

@

@

itle

itle

itle

T

T

T

udson-M3-ACPI/USB/EC

udson-M3-ACPI/USB/EC

udson-M3-ACPI/USB/EC

H

H

H

Size Docu ment Number Rev

Size Docu ment Number Rev

Size Docu ment Number Rev

ustom

ustom

ustom

C

C

C

L

L

L

Date: Sheet

Date: Sheet

Date: Sheet

10K_040 2_5%

G

G

@

@

1

S

S

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

C

C

C

A-9869P

A-9869P

A-9869P

E

O

DD_DA# <28>

.3

.3

.3

0

0

0

f

24 50Monday, February 0 4, 2013

f

24 50Monday, February 0 4, 2013

f

24 50Monday, February 0 4, 2013

o

o

o

A

S

ATA_FTX_DRX_P0<28>

S

+

AVDD_SATA

lace JPW

+

3VALW_FCH

ATA_FTX_DRX_N0<28>

S

ATA_FRX_C_DTX_N0<28>

S

ATA_FRX_C_DTX_P0<28>

S

ATA_FTX_DRX_P1<28>

S

ATA_FTX_DRX_N1<28>

S

ATA_FRX_C_DTX_N1<28>

S

ATA_FRX_C_DTX_P1<28>

O

DD_PWR< 37>

U

U

13

13

8

V

CC

3

W

7

H

OLD

1

S

6

C

5

D

MX25L3206EM2I-12G_SO8

MX25L3206EM2I-12G_SO8

45@

45@

R

R

336 1K_0402_1%

336 1K_0402_1%

2

R

R

130 931_0402_1%

130 931_0402_1%

+

3VALW_FCH

4

M Byte

V

SS

Q

HDD

A

ODD

P

W_CLEAR#

12

J

J

PW

PW

P

@

@

under DDR Door

C

C

498

498

2

1

0.1U_0402_16V4Z

0.1U_0402_16V4Z

12

12

12

F

CH_SPI_CS1#

F

CH_SPI_CLK

F

CH_SPI_MOSI

S

ocket PN: SP07000F500/SP07000H900

1 1

2 2

1

0

269@

269@

E

C_CS0#<34>

E

SETUP

S&M
OPTION

+

3VS

1

2

12

1 8
2
3 6
4 5

10K_8P4R_5%

10K_8P4R_5%

C_SCK<34>

E

C_SDI<34>

BIOS

NO

R

R

439

439

10K_0402_5%

10K_0402_5%

R

R

438

438

10K_0402_5%

10K_0402_5%

R

R

P11

P11

SPK TYPE

HARMAN
KARDON

NO HARMAN

S

M_EN

7

G
G
G

R

R

88 33_0402_5%885@

88 33_0402_5%885@

R

R

107 33_0402_5%885@

107 33_0402_5%885@

R

R

110 33_0402_5%885@

110 33_0402_5%885@

PIO172
PIO182
PIO181

SM_EN

3 3

4 4

B

12

1

1 2

R

R

437 10K_0402_5%

437 10K_0402_5%

4

S

A00003K800

SA00004LI00

2

F

CH_SPI_MISO

B

S

ATA_CALRP

S

ATA_CALRN

P

W_CLEAR#

20

T20T

O

DD_PWR

G

PIO172

S

M_EN

F

CH_ALERT#

885@

885@

1B

1B

U

U

AK19

ATA_TX0P

S

AM19

ATA_TX0N

S

AL20

ATA_RX0N

S

AN20

ATA_RX0P

S

AN22

ATA_TX1P

S

AL22

ATA_TX1N

S

AH20

ATA_RX1N

S

AJ20

ATA_RX1P

S

AJ22

ATA_TX2P

S

AH22

ATA_TX2N

S

AM23

ATA_RX2N

S

AK23

ATA_RX2P

S

AH24

ATA_TX3P

S

AJ24

ATA_TX3N

S

AN24

ATA_RX3N

S

AL24

ATA_RX3P

S

AL26

ATA_TX4P

S

AN26

ATA_TX4N

S

AJ26

ATA_RX4N

S

AH26

ATA_RX4P

S

AN29

ATA_TX5P

S

AL28

ATA_TX5N

S

AK27

ATA_RX5N

S

AM27

ATA_RX5P

S

AL29

C6

N

AN31

C7

N

AL31

C8

N

AL33

C9

N

AH33

C10

N

AH31

C11

N

AJ33

C12

N

AJ31

C13

N

AF28

ATA_CALRP

S

AF27

ATA_CALRN

S

AD22

ATA_ACT#/GPIO67

S

AF21

ATA_X1

S

AG21

ATA_X2

S

AH16

ANOUT0/GPIO52

F

AM15

ANOUT1/GPIO53

F

AJ16

ANOUT2/GPIO54

F

AK15

ANIN0/GPIO56

F

AN16

ANIN1/GPIO57

F

AL16

ANIN2/GPIO58

F

K6

EMPIN0/GPIO171

T

K5

EMPIN1/GPIO172

T

K3

EMPIN2/GPIO173

T

M6

EMPIN3/TALERT#/GPIO174

T

2180755042A13HUDSON_FCBGA656

2180755042A13HUDSON_FCBGA656

12

R

R

10633_0402_5%

10633_0402_5%

E

C_SDIO <34>

C

UDSON-3

UDSON-3

H

H

I

NT 8.2K PU

ERIAL ATA

ERIAL ATA
S

S

INT 10K PU

W MONITOR

W MONITOR

H

H

D_CLK/SCLK_0/GPIO73

S

D_CMD/SLOAD_0/GPIO74

S

D_CD#/GPIO75

S

D_WP/GPIO76

S

D_DATA0/SDATI_0/GPIO77

S
D_DATA1/SDATO_0/GPIO78

S

D_DATA2/GPIO79

D CARD

D CARD
S

S

BE LANSPI ROM

BE LANSPI ROM
G

G

GA DAC

GA DAC
V

V

GA MAINLINK

GA MAINLINK
V

V

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

S

D_DATA3/GPIO80

S

G

BE_RXCTL/RXDV

G

G

BE_TXCTL/TXEN

G

G

BE_PHY_RST#

G

BE_PHY_INTR

G

PI_DI/GPIO164

S
PI_DO/GPIO163

S

PI_CLK/GPIO162

S
PI_CS1#/GPIO165

S

OM_RST#/SPI_WP#/GPIO161

R

V

GA_HSYNC/GPO68

V

GA_VSYNC/GPO69

V

GA_DDC_SDA/GPO70

V

GA_DDC_SCL/GPO71

V

GA_DAC_RSET

V

UX_VGA_CH_P

A

UX_VGA_CH_N

A

M

M

M

M

M

M

M

M

L_VGA_HPD/GPIO229

M

IN0/GPIO175

V

IN1/GPIO176

V

IN2/SDATI_1/GPIO177

V

IN3/SDATO_1/GPIO178

V

IN4/SLOAD_1/GPIO179

V

IN5/SCLK_1/GPIO180

V

IN6/GBE_STAT3/GPIO181

V

IN7/GBE_LED3/GPIO182

V

BOLTONR1@

BOLTONR1@

I

I

I

ssued Date

ssued Date

ssued Date

C

AL14
AN14
AJ12
AH12
AK13
AM13
AH15
AJ14

AC4

BE_COL

G

AD3

BE_CRS

G

AD9

BE_MDCK

G

W10

BE_MDIO

G

AB8

BE_RXCLK

AH7

BE_RXD3

G

AF7

BE_RXD2

G

AE7

BE_RXD1

G

AD7

BE_RXD0

G

AG8
AD1

BE_RXERR

AB7

BE_TXCLK

G

AF9

BE_TXD3

G

AG6

BE_TXD2

G

AE8

BE_TXD1

G

AD8

BE_TXD0

G

AB9
AC2

BE_PHY_PD

AA7
W9

G

V6

F

CH_SPI_MISO

V5

F

CH_SPI_MOSI

V3

F

CH_SPI_CLK_R

T6

F

CH_SPI_CS1#

V1

L30

GA_RED

V

L32

GA_GREEN

M29

GA_BLUE

V

M28
N30

M33
N32

K31

V

GA_DAC_RSET

V28
V29

U28

A

UXCAL

A

L_VGA_L0P
L_VGA_L0N
L_VGA_L1P
L_VGA_L1N
L_VGA_L2P
L_VGA_L2N
L_VGA_L3P
L_VGA_L3N

N
N
N
N
N

UXCAL

T31
T33
T29
T28
R32
R30
P29
P28

C29

N2

M3

L2

N4

P1

P3

M1

M5

AG16

C1

AH10

C2

A28

C3

G27

C4

L4

C5

2

2

2

013/01/22 2014/01/21

013/01/22 2014/01/21

013/01/22 2014/01/21

H

DMI_EN#

S

PK_DET

BE_PHY_INTR

M

L_VGA_TXP0

M

L_VGA_TXN0

M

L_VGA_TXP1

M

L_VGA_TXN1

M

L_VGA_TXP2

M

L_VGA_TXN2

M

L_VGA_TXP3

M

L_VGA_TXN3

F

CH_CRT_HPD

G

PIO175

G

PIO176

G

PIO177

G

PIO178

S

LP_CHG_CB1

S

LP_CHG_CB0

G

PIO181

G

PIO182

443 1K_0402_1%

443 1K_0402_1%

R

R

2

1

1 2

352 10K_0402_5%

352 10K_0402_5%

R

R

2

1

R

R

366 715_0402_1%

366 715_0402_1%

2

1

R

R

364 100_0402_1%

364 100_0402_1%

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

1 2

111 0_0402_5%

111 0_0402_5%

R

R

D

S

PK_DET <33>

+

3VALW_FCH

F

@

@

CH_SPI_CLK

U

MA_CRT_R <21>

U

MA_CRT_G <21>

U

MA_CRT_B <21>

U

MA_CRT_HSYNC <21>

U

MA_CRT_VSYNC <21>

U

MA_CRT_DATA <21>

U

MA_CRT_CLK <21>

M

L_VGA_AUXP <7>

M

L_VGA_AUXN <7>

+

VDDAN_11_ML

M

L_VGA_TXP0 <7>

M

L_VGA_TXN0 <7>

M

L_VGA_TXP1 <7>

M

L_VGA_TXN1 <7>

M

L_VGA_TXP2 <7>

M

L_VGA_TXN2 <7>

M

L_VGA_TXP3 <7>

M

L_VGA_TXN3 <7>

F

CH_CRT_HPD <7>

D

E

H

DMI_EN#

(Internal 8.2K PU)

HDMI_EN#

SKU

H L

Non-HDMI
SKU

HDMI SKU

For EMI re quest

C

R

R

118

118

F

CH_SPI_CLK_R

If an SPI ROM is sha red betwe en FCH
and the Em bedded Con troller, a 10-k
pull-up re sistor to +3.3V_S5 is install ed

F

CH_SPI_CS1#

U

MA_CRT_DATA

U

MA_CRT_CLK

U

MA_CRT_R

U

MA_CRT_G

U

MA_CRT_B

F

CH_CRT_HPD

S

LP_CHG_CB0<31>

S

LP_CHG_CB1<31>

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

2

10_0402_5%

10_0402_5%

EMI@

EMI@

885@

885@

1 2

113 10K_0402_5%

113 10K_0402_5%

R

R

1 2

R

R

455 2.2K_0402_5%

455 2.2K_0402_5%

1 2

R

R

462 2.2K_0402_5%

462 2.2K_0402_5%

1 2

R367 150_0402_1%R367 150_0402_1%

1 2

R

R

368 150_0402_1%

368 150_0402_1%

1

R

R

369 150_0402_1%

369 150_0402_1%

1 2

R

R

365 10K_0402_5%

365 10K_0402_5%

R

R

P9

P9

1 8

G

PIO175

2 7

G

PIO178

3 6

G

PIO176

4 5

G

PIO177

10K_8P4R_5%

10K_8P4R_5%

S

LP_CHG_CB0

S

LP_CHG_CB1

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

H

H

H

udson-M3-SATA/GBE/HWM

udson-M3-SATA/GBE/HWM

udson-M3-SATA/GBE/HWM

L

L

L

A-9869P

A-9869P

A-9869P

C

508

508

1 2

1

10P_0402_50V8J

10P_0402_50V8J

EMI@

EMI@

+

3VALW_FCH

+

2

+

FCH_VDDAN_33_DAC_R

1 2

@

@

R

R

134 10 K_0402_5%

134 10 K_0402_5%

1 2

@

@

R

R

151 10K _0402_5%

151 10K _0402_5%

E

3VS

25 50Monday, February 04, 2013

25 50Monday, February 04, 2013

25 50Monday, February 04, 2013

+

3VALW_FCH

o

o

o

f

f

f

0

0

0

.3

.3

.3

A

S

TRAP PINS

B

C

D

E

12

R

R

239

239

2.2K_0402_5%

2.2K_0402_5%

R

TC_CLK

R

TC_CLKLPC_CLK1

S

5 PLUS
MODE
DISABLED

D

EFAULT

S

5 PLUS
MODE
ENABLED

+

3VALW_FCH

12

R

R

240

240

10K_0402_5%

10K_0402_5%

+

3VALW

V

2

C

C

523

523

0.1U_0402_10V7K

0.1U_0402_10V7K

2

1

AO3413_SOT23

AO3413_SOT23

2

C

C

521

521

0.01U_0402_25V7K

0.01U_0402_25V7K

1

R

R

5

5

F

CH_PWR_EN#<37>

1

47K_0402_5%

47K_0402_5%

gs=-4.5V,Id=3A, Rds<97mohm

S

S

Q

Q

3

3

G

G

2

D

D

1 3

+

3VALW_FCH

1

R

R

238

238

10K_0402_5%

10K_0402_5%

2

E

C_PWM2

L

PC ROM
(INTERNAL
10K PULL-UP)

SPI ROM

DEFAULT

E

C_PWM2

P

CI_AD23

DISABLE PCI
MEM BOOT

D

EFAULTDEFAULT

ENABLE PCI
MEM BOOT

P

CI_CLK1

A

PULL

1 1

2 2

3 3

HIGH

P

ULL

LOW

P

CI_CLK1<23>

P

CI_CLK3<23>

P

CI_CLK4<23>

C

LK_PCI_EC<23,34>

C

LK_PCI_DDR<23>

E

C_PWM2<24>

R

TC_CLK<23,34>

LLOW

PCIE GEN2

D

EFAULT

F

ORCE

PCIE GEN1

P

CI_CLK1

D

EBUG STRAPS

F

CH HAS 15K INTERNAL PU-UP FOR PCI_AD[27:23]

P

ULL

HIGH

PULL
LOW

P

ENABLE
DEBUG
STRAP

D
DEBUG
STRAP

D

+

3VS

12

R

R

231

231

10K_0402_5%

10K_0402_5%

P

CI_CLK3

P

CI_AD27 PCI_AD26

USE PCI
PLL

D

EFAULT

B

YPASS

PCI PLL

CI_CLK3

ISABLE

EFAULT

+

3VS

12

12

P

CI_CLK4 LPC_CLK0

N

ON_FUSION

CLOCK MODE

F

USION
CLOCK
MODE

D

EFAULT

R

R

241

241

@

@

10K_0402_5%

10K_0402_5%

P

CI_CLK4

233

233

DISABLE
ILA
AUTORUN

D

E
ILA
AUTORUN

1

2

EFAULT

NABLE

R

R

10K_0402_5%

10K_0402_5%

E

C

ENABLED

EC
DISABLED

D

EFAULT

C

LK_PCI_EC

C

12

R

R

R

234

234

10K_0402_5%

10K_0402_5%

R

10K_0402_5%

10K_0402_5%

P

CI_AD25 PCI_AD24

U

SE FC

PLL

B

YPASS

FC PLL

CLKGEN
ENABLED

D

C
DISABLE

+

LK_PCI_DDR

237

237

USE DEFAULT
PCIE STRAPS

D

EFAULT

U

SE EEPROM

PCIE STRAPS

EFAULT

LKGEN

3VALW_FCH

P

P

CI_AD27<23>

P

CI_AD26<23>

P

CI_AD25<23>

P

CI_AD24<23>

P

CI_AD23<23>

4 4

A

CI_AD27

P

CI_AD26

1

R

R

247

247

@

@

2.2K_0402_5%

2.2K_0402_5%

2

C

heck with FAE w hether can del ete or reserve test point or not

12

R

R

248

248

@

@

2.2K_0402_5%

2.2K_0402_5%

P

CI_AD25

12

R

R

249

249

@

@

2.2K_0402_5%

2.2K_0402_5%

P

CI_AD24

12

R

R

250

250

@

@

2.2K_0402_5%

2.2K_0402_5%

B

P

CI_AD23

1

R

R

251

251

@

@

2.2K_0402_5%

2.2K_0402_5%

2

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2

2

2

013/01/22 2014/01/21

013/01/22 2014/01/21

013/01/22 2014/01/21

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

D

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

Title

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

H

H

H

udson-M3-STRAP

udson-M3-STRAP

udson-M3-STRAP

L

L

L

A-9869P

A-9869P

A-9869P

E

o

o

o

f

26 50Monday, February 04, 2013

f

26 50Monday, February 04, 2013

f

26 50Monday, February 04, 2013

0

0

0

.3

.3

.3

A

reserve 0ohm

+

3VS

L

L

32

32

1 2

+

30

30

L

L

2

@

@

L

L

33

33

@

@

L

L

31

31

34

34

L

L

35

35

L

L

36

36

L

L

FCH_VDDAN_33_DAC_R

2

+

FCH_VDDPL_33_MLDAC

2

2

+

FCH_VDDPL_33_SSUSB_S

+

FCH_VDDPL_33_USB_S

+

VDDPL_33_PCIE

2

+

VDDPL_33_SATA

+

VDDPL_3.3V

C

C
285

285

C

C
272

272

C

C
275

275

C

C
279

279

C

C
280

280

C

C
294

294

C

C
297

297

C

C

0.1U_0402_16V7K

0.1U_0402_16V7K

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

288

288

1

1

2

2

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

0.1U_0402_25V6

0.1U_0402_25V6

C

C
273

273

1

1

VDDPL_33_SSUSB_S

2

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

1

2

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

1

2

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

1

2

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

1

2

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

1

2

For Hudson M3 USB3.0 only

2

For Hudson M2, connect to GND

LDO_CAP: Internally generated 1.8V
supply for the RGB outputs

0.1U_0402_25V6

0.1U_0402_25V6

+

C

C
274

274

C

C
278

278

C

C
281

281

C

C
293

293

C

C
296

296

1.1VS

1

2

0.1U_0402_25V6

0.1U_0402_25V6

1

2

0.1U_0402_25V6

0.1U_0402_25V6

1

2

0.1U_0402_25V6

0.1U_0402_25V6

1

@

@

2

0.1U_0402_25V6

0.1U_0402_25V6

1

@

@

2

MBK1608221YZF_2P

MBK1608221YZF_2P

+

3VALW_FCH

+

1.1VALW

+

1.1VALW

BLM15BB221SN1D 0402

BLM15BB221SN1D 0402

1 2

220 ohm/2A

MBK1608221YZF_2P

MBK1608221YZF_2P

1 1

+

3VS

1

BLM15BB221SN1D 0402

BLM15BB221SN1D 0402

+

FCH_VDDAN_33_DAC_R

1

42 0_0402_5%

42 0_0402_5%

R

R

+

3VS

1

BLM15BB221SN1D 0402

BLM15BB221SN1D 0402

2 2

+

3VALW_FCH

1

BLM15BB221SN1D 0402

BLM15BB221SN1D 0402

+

3VALW_FCH

1 2

BLM15BB221SN1D 0402

BLM15BB221SN1D 0402

+

3VS

1 2

3 3

BLM15BB221SN1D 0402

BLM15BB221SN1D 0402

+

3VS

1

BLM15BB221SN1D 0402

BLM15BB221SN1D 0402

for Power consumption

+

3VS

1 2

R

R

20 0_0603_5%

20 0_0603_5%

+

FCH_VDDPL_33_MLDAC

24

24

L

L

MBK1608221YZF_2P

MBK1608221YZF_2P

BLM15BB221SN1D 0402

BLM15BB221SN1D 0402

1 2

20mA

200mA

For A11: Cap = 1nF
For A12, Cap = DNI

25

25

L

L

2

1

L

L

38

38

1 2

L

L

39

39

+

FCH_VDD_11_SSUSB_S

40mils

4 4

A

+

1.1VALW

L

L

61

61

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-201209-221LMA30T_0805

12

FCH_VDD_11_SSUSB_S
+

R

R

132 0_0603_5%

132 0_0603_5%

B

131mA

22U_0805_6.3V6M

22U_0805_6.3V6M

C

C

C

C

573

573

266

266

1

2

47mA

2

0mA

1

@

@

R

R

34 0_0402_5%

34 0_0402_5%

1

@

@

R

R

35 0_0402_5%

35 0_0402_5%

20mA

17mA

4

3mA

+

93mA

7mA

1 2

@

@

R

R

37 0_0402_5%

37 0_0402_5%

226mA

1 2

@

@

12 0_0603_5%

12 0_0603_5%

R

R

6

58mA

140mA

197mA

C

C
832

832

1

2

1 2

R

R

90

90

1

10U_0603_6.3V6M

10U_0603_6.3V6M

0_0402_5%

0_0402_5%

C

C
128

128

1U_0402_16V6K

1U_0402_16V6K

1U_0402_16V6K

1U_0402_16V6K

C

C

C

C

134

134

133

133

1

1

2

2

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

0.1U_0402_25V6

0.1U_0402_25V6

C

C

C

C

303

303

302

302

1

1

2

2

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

0.1U_0402_25V6

0.1U_0402_25V6

C

C

C

C

316

316

304

304

1

1

@

@

2

2

282mA

@

@

C

C
318

318

424mA

2

@

@

B

+

VDDIO_33_PCIGP

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

C

C

C

C
572

572

571

1

2

2

2

+

FCH_VDDPL_33_SSUSB_S

+

298 2.2U_0402_6.3V6M

298 2.2U_0402_6.3V6M

C

C

1

2

R

R

87 0_0402_5%

87 0_0402_5%

1

2

571

1

1

2

2

+

VDDPL_3.3V

+

VDDPL_33_DAC

+

VDDPL_33_ML

FCH_VDDAN_33_DAC_R

FCH_VDDPL_33_USB_S

+

VDDPL_33_PCIE

+

VDDPL_33_SATA

@

@

1 2

+

VDDPL_11_DAC

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

C

C

C

C

129

129

151

151

1

1

2

2

1 2

@

@

+

VDDAN_33_USB

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

C

C

C
136

136

1

2

+

VDDAN_11_USB_S

0.1U_0402_25V6

0.1U_0402_25V6

VDDCR_1.1V_USB

0.1U_0402_25V6

0.1U_0402_25V6

VDDAN_SSUSB

0.1U_0402_25V6

0.1U_0402_25V6
C

C

C

C
325

325

331

331

1

1

2

2

+

VDDCR_11_SSUSB

1U_0402_16V6K

1U_0402_16V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

C

C
319

319

1

2

C
310

310

0.1U_0402_25V6

0.1U_0402_25V6

C

C
332

332

C

C
135

135

1

2

C

C
305

305

1

2

+

C

C
324

324

1

2

+

1U_0402_16V6K

1U_0402_16V6K

C

C
155

155

1

2

+

VDDAN_11_ML

1

2

1

2

1

0mils

10mils

10mils

10mils

10mils

10mils

10mils

10mils

10mils

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

1C

1C

U

U

AB17

V

DDIO_33_PCIGP_1

AB18

V

DDIO_33_PCIGP_2

AE9

V

DDIO_33_PCIGP_3

AD10

V

DDIO_33_PCIGP_4

AG7

V

DDIO_33_PCIGP_5

AC13

V

DDIO_33_PCIGP_6

AB12

V

DDIO_33_PCIGP_7

AB13

V

DDIO_33_PCIGP_8

AB14

V

DDIO_33_PCIGP_9

AB16

V

DDIO_33_PCIGP_10

H24

V

DDPL_33_SYS

V22

V

DDPL_33_DAC

U22

V

DDPL_33_ML

T22

V

DDAN_33_DAC

L18

V

DDPL_33_SSUSB_S

D7

V

DDPL_33_USB_S

AH29

V

DDPL_33_PCIE

AG28

V

DDPL_33_SATA

M31

L

DO_CAP

10mils

V21

V

DDPL_11_DAC

20mils

Y22

V

DDAN_11_ML_1

V23

V

DDAN_11_ML_2

V24

V

DDAN_11_ML_3

V25

V

DDAN_11_ML_4

AB10

V

DDIO_33_GBE_S

AB11

V

DDCR_11_GBE_S_1

AA11

V

DDCR_11_GBE_S_2

AA9

V

DDIO_GBE_S_1

AA10

V

DDIO_GBE_S_2

30mils

G7

V

DDAN_33_USB_S_1

H8

V

DDAN_33_USB_S_2

J8

V

DDAN_33_USB_S_3

K8

V

DDAN_33_USB_S_4

K9

V

DDAN_33_USB_S_5

M9

V

DDAN_33_USB_S_6

M10

V

DDAN_33_USB_S_7

N9

V

DDAN_33_USB_S_8

N10

V

DDAN_33_USB_S_9

M12

V

DDAN_33_USB_S_10

N12

V

DDAN_33_USB_S_11

M11

V

DDAN_33_USB_S_12

10mils

U12

V

DDAN_11_USB_S_1

U13

V

DDAN_11_USB_S_2

10mils

T12

V

DDCR_11_USB_S_1

T13

V

DDCR_11_USB_S_2

20mils

P16

V

DDAN_11_SSUSB_S_1

M14

V

DDAN_11_SSUSB_S_2

N14

V

DDAN_11_SSUSB_S_3

P13

V

DDAN_11_SSUSB_S_4

P14

V

DDAN_11_SSUSB_S_5

30mils

N16

V

DDCR_11_SSUSB_S_1

N17

V

DDCR_11_SSUSB_S_2

P17

V

DDCR_11_SSUSB_S_3

M17

V

DDCR_11_SSUSB_S_4

0.1U_0402_25V6

0.1U_0402_25V6

2180755042A13HUDSON_FCBGA656

2180755042A13HUDSON_FCBGA656

C

C
333

333

1

2

C

+

VCC_FCH_R

1U_0402_16V6K

1U_0402_16V6K

1U_0402_16V6K

UDSON-3

UDSON-3

H

H

PCI/GPIO I/O

PCI/GPIO I/O

ORE S0

ORE S0
C

C

CLKGEN I/OPCI EXPRESSSERIAL ATA3.3V_S5 I/O

CLKGEN I/OPCI EXPRESSSERIAL ATA3.3V_S5 I/O

USB SS USB MAIN LINKGBE LAN

USB SS USB MAIN LINKGBE LAN

OWER

OWER

P

P

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

DDCR_11_1

V

DDCR_11_2

V

DDCR_11_3

V

DDCR_11_4

V

DDCR_11_5

V

DDCR_11_6

V

DDCR_11_7

V

DDCR_11_8

V

DDCR_11_9

V

DDAN_11_CLK_1

V
V

DDAN_11_CLK_2
DDAN_11_CLK_3

V
V

DDAN_11_CLK_4

V

DDAN_11_CLK_5

V

DDAN_11_CLK_6

V

DDAN_11_CLK_7

V

DDAN_11_CLK_8

V

DDAN_11_PCIE_1

V

DDAN_11_PCIE_2

V

DDAN_11_PCIE_3

V

DDAN_11_PCIE_4

V

DDAN_11_PCIE_5

V

DDAN_11_PCIE_6

V

DDAN_11_PCIE_7

V

DDAN_11_PCIE_8

V

DDAN_11_SATA_1

V

DDAN_11_SATA_4

V

DDAN_11_SATA_2

V

DDAN_11_SATA_3

V

DDAN_11_SATA_5

V

DDAN_11_SATA_6

V

DDAN_11_SATA_7

V

DDAN_11_SATA_8

V

DDAN_11_SATA_9

V

DDAN_11_SATA_10

V

DDIO_33_S_1

V

DDIO_33_S_2

V

DDIO_33_S_3

V

DDIO_33_S_4

V

DDIO_33_S_5

V

DDIO_33_S_6

V

DDIO_33_S_7

V

DDIO_33_S_8

V

DDXL_33_S

V

DDCR_11_S_1

V

DDCR_11_S_2

V

DDPL_11_SYS_S

V

DDAN_33_HWM_S

V

DDIO_AZ_S

BOLTONR1@

BOLTONR1@

50mils

T14
T17
T20
U16
U18
V14
V17
V20
Y17

20mils

H26
J25
K24
L22
M22
N21
N22
P22

50mils

AB24
Y21
AE25
AD24
AB23
AA22
AF26
AG27

60mils

AA21
Y20
AB21
AB22
AC22
AC21
AA20
AA18
AB20
AC19

10mils

N18
L19
M18
V12
V13
Y12
Y13
W11

10mils

G24

10mils

N20
M20

10mils

J24

10mils

M8

10mils

AA4

2

2

2

013/01/22 2014/01/21

013/01/22 2014/01/21

013/01/22 2014/01/21

1U_0402_16V6K

C

C

C

C

312

312

311

311

1

1

2

2

+

1.1VS_CKVDD

1U_0402_16V6K

1U_0402_16V6K

1U_0402_16V6K

1U_0402_16V6K

C

C

C

C
320

320

348

348

1

1

2

2

+

PCIE_VDDR_FCH

1U_0402_16V6K

1U_0402_16V6K

1U_0402_16V6K

1U_0402_16V6K

C

C

C

C

328

328

327

327

1

1

@

@

2

2

+

AVDD_SATA

1U_0402_16V6K

1U_0402_16V6K

1U_0402_16V6K

1U_0402_16V6K

C

C

C

C

502

502

501

501

1

1

2

2

+

VDDIO_33_S

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

C

C

C

C
343

343

342

342

1

1

2

2

+

VDDXL_3.3V

+

VDDCR_1.1V

+

VDDPL_1.1V

+

VDDAN_33_HWM

+

VDDIO_AZ

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

D

1007mA

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

C

C

C

C

C

C

335

335

334

334

1

2

C

C
336

336

1

2

C

C
338

338

1

@

@

2

C

C

341

341

1

@

@

2

C

C
506

506

1

2

C

C
510

510

1

2

C

C
512

512

1

2

C

C
514

514

1

2

C

C
516

516

1

2

315

315

1

@

@

2

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6
C

C

C

C
337

337

323

323

1

2

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

C

C

C

C

499

499

339

339

1

2

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

C

C

C

C

589

589

340

340

1

2

59mA

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

5mA

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

0.1U_0402_25V6

0.1U_0402_25V6

C

C
509

509

1

2

1

87mA

1U_0402_16V6K

1U_0402_16V6K

1U_0402_16V6K

1U_0402_16V6K

C

C
518

518

1

2

70mA

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

0.1U_0402_25V6

0.1U_0402_25V6

C

C
513

513

1

2

12mA

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

0.1U_0402_25V6

0.1U_0402_25V6

C

C
515

515

1

2

26mA

1 2

C

C

517 2.2U_0402_6.3V6M

517 2.2U_0402_6.3V6M

1 2

@

@

C

C

519 0.1U_0402_25V6

519 0.1U_0402_25V6

D

reserve 0ohm
for Power consumption

22U_0805_6.3V6M

22U_0805_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

1

2

340mA

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

1

2

1088mA

22U_0603_6.3V6M

22U_0603_6.3V6M

1

2

1337mA

22U_0805_6.3V6M

22U_0805_6.3V6M

1

2

1 2

26 0_0402_5%

26 0_0402_5%

R

R

BLM15BB221SN1D 0402

BLM15BB221SN1D 0402

BLM15BB221SN1D 0402

BLM15BB221SN1D 0402

R

R

R

R

R

R

C

C
317

317

1

1

@

@

2

2

R

R

44

44

1 2

@

@

C

C
620

620

0_0402_5%

0_0402_5%

22U_0805_6.3V6M

22U_0805_6.3V6M

1

2

1

@

@

R

R

14 0_0805_5%

14 0_0805_5%

1 2

@

@

R

R

40 0_0805_5%

40 0_0805_5%

C

C
500

500

22U_0805_6.3V6M

22U_0805_6.3V6M

1

2

@

@

L

L

37

37

1 2

1

@

@

167 0_0402_5%

167 0_0402_5%

R

R

41

41

L

L

1 2

1 2

@

@

43 0_0402_5%

43 0_0402_5%

1 2

45 0_0402_5%

45 0_0402_5%

+

1.1VS

1 2

28 0_0603_5%

28 0_0603_5%

C

C

831

831

10U_0805_25V6K

10U_0805_25V6K

+

1.1VS

+

1.1VS

2

+

1.1VS

+

3VALW_FCH

+

3VALW_FCH

+

1.1VALW

2

+

1.1VALW

+

3VALW_FCH

A
VDDAN_33_HWM_S: Please connect
it to +3.3V_S5 directly if HWM is not used.

+

3VS

V
+3.3/1.5V_S5 rail if Wake on Ring
is supported

reserve 0ohm
for Power consumption

E

No more than two balls sharing any single via.
Note: Use of a single via per ball is preferred.

U

U

1E

1E

H

H

UDSON-3

A3

A33

B7

B13

D9

D13

E5
E12
E16
E29

F7

F9

F11
F13
F16
F17
F19
F23
F25
F29

G6
G16
G32
H12
H15
H29

J6

J9
J10
J13
J28
J32

K7
K16
K27
K28

L6

L12
L13
L15
L16

L21
M13
M16
M21
M25

N6
N11
N13
N23
N24
P12
P18
P20
P21
P31
P33

R4
R11
R25
R28
T11
T16
T18

N8

K25

H25

C

onnect to GND through a dedicated via

MD reply:

DDIO_AZ_S should be tied to

T

T

Title

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

L

L

L

A-9869P

A-9869P

Date: Sheet

Date: Sheet

Date: Sheet

A-9869P

UDSON-3

V

SS_1

V

SS_2

V

SS_3

V

SS_4

V

SS_5

V

SS_6

V

SS_7

V

SS_8

V

SS_9

V

SS_10

V

SS_11

V

SS_12

SS_13

V

SS_14

V

SS_15

V

SS_16

V

SS_17

V

SS_18

V

SS_19

V

SS_20

V

SS_21

V

SS_22

V

SS_23

V

SS_24

V

SS_25

V

SS_26

V

SS_27

V

SS_28

V

SS_29

V

SS_30

V

SS_31

V

SS_32

V

SS_33

V

SS_34

V

SS_35

V

SS_36

V

SS_37

V

SS_38

V

SS_39

V

SS_40

V

SS_41

V

SS_42

V

SS_43

V

SS_44

V

SS_45

V

SS_46

V

SS_47

V

SS_48

V

SS_49

V

SS_50

V

SS_51

V

SS_52

V

SS_53

V

SS_54

V

SS_55

V

SS_56

V

SS_57

V

SS_58

V

SS_59

V

SS_60

V

SS_61

V

SS_62

V

SS_63

V

SS_64

V

SSAN_HWM

V

SSXL

V

SSPL_SYS

V

2180755042A13HUDSON_FCBGA656

2180755042A13HUDSON_FCBGA656

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

H

H

H

udson-M3-POWER/GND

udson-M3-POWER/GND

udson-M3-POWER/GND

ROUND

ROUND
G

G

V

SSANQ_DAC

V

V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V

SS_100

V

SS_101

V

SS_102

V

SS_103

V

SS_104

V

SS_105

V

SS_106

V

SS_107

V

SS_108

V

SS_109

V

SS_110

V

SS_111

V

SS_112

V

SS_113

V

SS_114

V

SS_115

V

SS_116

V

SS_117

V

SS_118

V

SS_119

V

SS_120

V

SS_121

V

SS_122

V

SS_123

V

SS_124

V

SS_125

V

SS_126

V

SS_127

V

SS_128

V

SSPL_DAC

V

SSAN_DAC

SSIO_DAC

V

E

BOLTONR1@

BOLTONR1@

E

SS_65
SS_66
SS_67
SS_68
SS_69
SS_70
SS_71
SS_72
SS_73
SS_74
SS_75
SS_76
SS_77
SS_78
SS_79
SS_80
SS_81
SS_82
SS_83
SS_84
SS_85
SS_86
SS_87
SS_88
SS_89
SS_90
SS_91
SS_92
SS_93
SS_94
SS_95
SS_96
SS_97
SS_98
SS_99

FUSE

T25
T27
U6
U14
U17
U20
U21
U30
U32
V11
V16
V18
W4
W6
W25
W28
Y14
Y16
Y18
AA6
AA12
AA13
AA14
AA16
AA17
AA25
AA28
AA30
AA32
AB25
AC6
AC18
AC28
AD27
AE6
AE15
AE21
AE28
AF8
AF12
AF16
AF33
AG30
AG32
AH5
AH11
AH18
AH19
AH21
AH23
AH25
AH27
AJ18
AJ28
AJ29
AK21
AK25
AL18
AM21
AM25
AN1
AN18
AN28
AN33

T21
L28
K33
N28

R6

27 50Monday, February 04, 2013

27 50Monday, February 04, 2013

27 50Monday, February 04, 2013

o

o

o

f

f

f

0

0

0

.3

.3

.3

A

S

ATA HDD Conn.

1 1

23
24

SUYIN_127043FR022G196ZR

SUYIN_127043FR022G196ZR

S

lot 1 Half PCIe Mini Card-WLAN

2 2

+

3V_WLAN

1

M1

M1

C

C

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

G

G

G

G
G
G

G

AS/DSS

D

G

ND

G

ND

G

4

0 mils

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

M2

M2

C

C

2

J

J

ND
A

A

ND

B
B
ND

33

V

33

V

33

V

ND
ND
ND
V
V
V
ND

ND

12

V

12

V

12

V

HDD@

HDD@

1
2

+

3

-

4
5

-

6

+

7

8
9
10
11
12
13
14

5

15

5

16

5

17
18
19
20
21
22

M3

M3

C

C

S
S

S
S

1

2

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

ATA_FTX_C_DRX_P0
ATA_FTX_C_DRX_N0

ATA_FRX_DTX_N0
ATA_FRX_DTX_P0

+

3VS

+

5VS

Close to JHDD

1 2

C

C

369 0.01U_0402_25V7K

369 0.01U_0402_25V7K

1 2

C

C

367 0.01U_0402_25V7K

367 0.01U_0402_25V7K

1 2

C

C

368 0.01U_0402_25V7K

368 0.01U_0402_25V7K

1 2

370 0.01U_0402_25V7K

370 0.01U_0402_25V7K

C

C

+

5VS

1

.2A

1

C

C

356

356

10U_0603_6.3V6M

10U_0603_6.3V6M

2

P

lace closely JHDD SATA CONN.

1

2

357

357

C

C

0.1U_0402_10V7K

0.1U_0402_10V7K

+

3VS

S

hort for WIFI

B

S

ATA_FTX_DRX_P0 <25>

S

ATA_FTX_DRX_N0 <25>

S

ATA_FRX_C_DTX_N0 <25>

S

ATA_FRX_C_DTX_P0 <25>

1

C

C

358

358

0.1U_0402_10V7K

0.1U_0402_10V7K

2

P

P

J6

J6

+

3V_WLAN

1

2

PAD-OPEN 2x2m@

PAD-OPEN 2x2m@

SATA ODD Conn

J

J

ODD

ODD

G

ND
A

+

A

-

G

ND

B

-

B

+

G

ND

D

P

5V

+

5V

+

D

ND

G

ND

G

SANTA_202401-1

SANTA_202401-1

@

@

M

ND

G

ND

G

15
14

C

1
2

S

3
4
5
6
7

8

9
10
11
12
13

ATA_FTX_C_DRX_P1

S

ATA_FTX_C_DRX_N1

S

ATA_FRX_DTX_N1

S

ATA_FRX_DTX_P1

+

5VS_ODD

W

LAN&BT Combo module circuits

B
on module

Enable Disable

BT_ON

C

lose to JODD

1 2

C

C

376 0.01U_0402_25V7K

376 0.01U_0402_25V7K

1 2

C

C

377 0.01U_0402_25V7K

377 0.01U_0402_25V7K

1 2

C

C

378 0.01U_0402_25V7K

378 0.01U_0402_25V7K

1

375 0.01U_0402_25V7K

375 0.01U_0402_25V7K

C

C

O

DD_PLUGIN# <24>

O

DD_DA# <24>

T

BT
on module

H L

D

P

ower Consumption

Peak 1800 mA

S

ATA_FTX_DRX_P1 <25>

S

ATA_FTX_DRX_N1 <25>

S

2

ATA_FRX_C_DTX_N1 <25>

S

ATA_FRX_C_DTX_P1 <25>

+

5VS_ODD

1

C

C

10U_0603_6.3V6M

10U_0603_6.3V6M

2

1

.1A

355

355

Read (CD) 1100 mA
Read (DVD) 950 mA
Write 1300 mA
Standby 20mA

P

lace components closely ODD CONN.

1

380

380

C

C

0.1U_0402_10V7K

0.1U_0402_10V7K

2

1

C

C

360

360

2

0.1U_0402_10V7K

0.1U_0402_10V7K

E

1 2

B

B

T_ON<34>

+

3V_WLAN

WLAN

WLAN

J

@

@

R

R

1443

1443

0_0402_5%

0_0402_5%

2

1

B

T_ON

C

LKREQ_WLAN#<24>

C

LK_WLAN#<23>

C

3 3

P
P

WLAN/ WiFi

E

51_TXD<34>

E

51_RXD<34>

D

ebug card using

LK_WLAN<23>

P

CIE_FRX_WLANTX_N 1<5>

P

CIE_FRX_WLANTX_P1<5>

CIE_FTX_C_WLANRX _N1<5>
CIE_FTX_C_WLANRX _P1<5>

+

3V_WLAN

B

T_CTRL_R

J

1

1

3

3

5

5

7

7

9

9

11

1

1

13

3

1

15

5

1

17

7

1

19

9

1

21

1

2

23

3

2

25

5

2

27

7

2

29

9

2

31

1

3

33

3

3

35

5

3

37

7

3

39

9

3

41

1

4

43

3

4

45

5

4

47

7

4

49

9

4

51

1

5

53

ND1

ND2

G

G

LCN_DAN08-52406-0500

LCN_DAN08-52406-0500

@

@

2

2

4

4

6

6

8

8

10

0

1

12

2

1

14

4

1

16

6

1

18

8

1

20

0

2

22

2

2

24

4

2

26

6

2

28

8

2

30

0

3

32

2

3

34

4

3

36

6

3

38

8

3

40

0

4

42

2

4

44

4

4

46

6

4

48

8

4

50

0

5

52

2

5

54

12

R

R

63

63

300_0402_5%

300_0402_5%

@

@

1

C

C

263

263

10P_0402_50V8J

10P_0402_50V8J

@

@

2

W

L_OFF# <34>

A

PU_PCIE_RST# <12 ,23,30>

F

CH_SCLK0 <10,11,24>

F

CH_SDATA0 <10 ,11,24>

U

SB20_N3 <24>

U

SB20_P3 <24>

B

T

T_ON

F

or isolate BT_C TRL and

Compal Debug Ca rd.

R

R

327

327

1K_0402_5%

1K_0402_5%

E

51_RXD

Reserved f or EHCI CR C errors

4 4

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2

2

2

013/01/22 2014/01/21

013/01/22 2014/01/21

013/01/22 2014/01/21

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

Title

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

D

Date: Sheet

ompal Electronics, Inc.

S

S

S

ATA-HDD/ODD/USB

ATA-HDD/ODD/USB

ATA-HDD/ODD/USB

L

L

L

A-9869P

A-9869P

A-9869P

E

0

0

0

.3

.3

2

2

2

8 50Monday, February 04, 2013

8 50Monday, February 04, 2013

8 50Monday, February 04, 2013

.3

o

o

o

f

f

f

A

G

reen Clock Generator

B

C

D

E

F

G

H

+

1 1

3V_LAN

.1U_0402_10V7K

.1U_0402_10V7K
0

0

1

2

+

3VL

1

C

C

C

CL13

CL13

@

@

C

2

.1U_0402_10V7K

.1U_0402_10V7K
0

0

+

1.8VGS

1

C

G

G

CL15

CL15

CLK@

CLK@

C

G

G

2

.1U_0402_10V7K

.1U_0402_10V7K
0

0

c

hange part number to

SJ10000EF00

2

C

LK_X1

2

C

C

CL11

CL11

18P_0402_50V8J

18P_0402_50V8J

1

GCLK@

GCLK@

1

+

3VALW_FCH

1

C

3VALW

.1U_0402_10V7K

.1U_0402_10V7K
0

0

GCLK@

GCLK@

C

CL14

CL14

G

G

CLK@

CLK@

2

.1U_0402_10V7K

.1U_0402_10V7K
0

0

1

C

C

CL20

CL20

G

G

CLK@

CLK@

2

3

C

LK_X2

3

G

ND

4

CL18

CL18

CLK@

CLK@

+

Y

Y

CL1 25M HZ 12PF X3G025000DK1H-X

CL1 25M HZ 12PF X3G025000DK1H-X

1

G

ND

2

2

C

C

CL12

CL12

18P_0402_50V8J

18P_0402_50V8J

1

GCLK@

GCLK@

+

3V_LAN

+

RTC

R

R

22U_0805_6.3V6M

22U_0805_6.3V6M

12

GCLK@

GCLK@

R

R

CL10 120_0603_5%

CL10 120_0603_5%

1 2

@

@

CL12 0_0402_5%

CL12 0_0402_5%

+

3VALW_FCH

1

C

C

CL1

CL1

GCLK@

GCLK@

2

+

VBAT

+

3VL

+

3VALW

+

1.8VGS

+

3V_LAN_R

C

LK_X1

C

LK_X2

SLG3NB238VTR_TQFN16_2X3

SLG3NB238VTR_TQFN16_2X3

S

A00005DO00

10

15

2

11

8

3

1

16

U

U

CL1

CL1

V

BAT

+

V3.3A

V

DD

V

DDIO_27M

V

DDIO_25M_A

V

DDIO_25M_B

X

TAL_IN

X

TAL_OUT

UGCLK@

UGCLK@

V

DD_RTC_OUT

C

C

CL2

CL2

1

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

GCLK@

GCLK@

2

14

+

VDD_RTC_OUT

9

3

2kHz

12

V

2

7MHz

2

5MHz_A

2

5MHz_B

ND1

ND2

ND3
G

G

G

4

7

13

GA_X1_R

6

L

AN_X1_R_R

5

F

CH_X1_R_R

ND4
G

17

VGA@

VGA@

10_0402_5%

10_0402_5%

1 2

1

12

33_0402_5%@

33_0402_5%@

2

33_0402_5%GCLK@

33_0402_5%GCLK@

R

R

CL11

CL11

R

R

CL8

CL8

R

R

CL7

CL7

F

CH_RTCX1_R <23>

V

GA_X1 <14>

F

CH_X1_R <23>

L

AN_X1_R <30>

L

AN_X1_R_R

C

C

CL10 5P_0402_50V8C

CL10 5P_0402_50V8C

R

eserved fo r Swing Le vel adjus tment

( Close GC LK side )

@

@

1 2

F

or DIS

U

U

CL1

VGA@

CL1

VGA@

SLG3NB302VTR_TQFN16_2X3

SLG3NB302VTR_TQFN16_2X3

SA00006D500

2

3 3

4 4

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

D

2

2

2

013/01/22 2014/01/21

013/01/22 2014/01/21

013/01/22 2014/01/21

E

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

F

Date: Sheet

M

M

M

onday, February 04, 2013

onday, February 04, 2013

onday, February 04, 2013

G

P

P

P

CIe-WLAN/GCLK

CIe-WLAN/GCLK

CIe-WLAN/GCLK

L

L

L

A-9869P

A-9869P

A-9869P

2

o

2

2

o

o

f

9 50

f

9 50

f

9 50

H

0

0

0

.3

.3

.3

A

L

eft USB 2.0 x 1

B

C

D

E

O

@

@

W

OL_EN#

O
O
O

CB

UT
UT
UT

W=60mils

+

USB_VCCC

6
7
8
5

Sx Enable
Wake up

LOW

@EMI@

@EMI@

1 2

C

C

76 1000P_0402_50V7K

76 1000P_0402_50V7K

U

SB_OC#2 <24,34>

W

Sx Disable
Wake up

HIGH HIGH

OL_EN# <34>

S0

J

J

LAN

@

LAN

@

+

A

PU_PCIE_RST#<12,23,28>

F

CH_PCIE_WAKE#<24>

L

AN_X1_R<29>

C

LK_LAN#<23>

C

P

CIE_FTX_C_LANRX_N0<5>

P

CIE_FTX_C_LANRX_P0<5>

P

CIE_FRX_C_LANTX_N0<5>

P

CIE_FRX_C_LANTX_P0<5>

LK_LAN<23>

+

USB_VCCC

3V_LAN

L

ANCLK_REQ#

I

SOLATE#

L

AN_X1_R

EMI@

EMI@

1 2

R

R

L8 0_0402_5%

L8 0_0402_5%

1 2

R

R

L9 0_0402_5%

L9 0_0402_5%

EMI@

EMI@

U

SB20_P0_L

U

SB20_N0_L

+

USB_VCCC

W

=60mils

1

1

2

2

2

3

3

4

4

4

5

5

6

6

6

7

7

8

8

8

9

9

10

1

0 10

11

1

1

12

1

2 12

13

1

3

14

1

4 14

15

1

5

16

1

6 16

17

1

7

18

1

8 18

19

1

9

20

2

0 20

21

G

1

22

G

2

23

G

3

24

G

4

ACES_50559-02001-001

ACES_50559-02001-001

+

5VALW

2

.0A

U

U

14

14

3VS

12

1K_0402_5%

1K_0402_5%
R

R

L6

L6

@

@

R

R

L7

L7

15K_0402_5%

15K_0402_5%

I

SOLATE#

2
3
4
1

SY6288DCAC_MSOP8

SY6288DCAC_MSOP8

S

A00004KB00

SA00003TV00

R

R

I

N

I

N

E

N/ENB

G

ND

1 2

L433 0_0402_5%

L433 0_0402_5%

U

U

1 1

2 2

+

3V_LAN rising time (10%~90%) need > 1ms and <100ms.

SB20_P0<24>

U

SB20_N0<24>

F

or LAN function

L

AN_EN<24>

C

LKREQ_LAN#<24>

+

3VALW_FCH

SB20_P0

U

SB20_N0

L

AN_EN

C

LKREQ_LAN#

@PJ29

@

2

2

JUMP_43X39

JUMP_43X39

P

3

2

1

2N7002KW_SOT323-3

2N7002KW_SOT323-3

+

3V_LAN

J29

1

1

3

2

WCM-2012-900T_0805

WCM-2012-900T_0805

2

G

G

D

D

Q

Q

L53

L53

3

S

S

4

4

1

1

L

ANCLK_REQ#

U

SB20_P0_L

U

SB20_N0_L

+

3VS

R

R
10K_0402_5%

10K_0402_5%

1 2

U

SB_EN#2<34>

+

333

333

L

R7

EMI@LR7

EMI@

LAN WOL LAN_EN ISOLATEB
S0 Sx S0 Sx

----------------------------------------------

3 3

0 0 0 0 1 1
0 1 0 0 1 1
1 0 1 1 1 1
1 1 1 1 1 0*

*
S3: after SUSP# assert low over 100ms
S4/S5: after SYSON assert low over 100ms

4 4

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C

2

2

2

013/01/22 2014/01/21

013/01/22 2014/01/21

013/01/22 2014/01/21

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

Title

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

D

Date: Sheet

ompal Electronics, Inc.

P

P

P

CIe-LAN-RTL8105E/8111F

CIe-LAN-RTL8105E/8111F

CIe-LAN-RTL8105E/8111F

L

L

L

A-9869P

A-9869P

A-9869P

E

30 50Monday, February 04, 2013

30 50Monday, February 04, 2013

30 50Monday, February 04, 2013

0

0

0

.3

.3

.3

o

o

o

f

f

f

5

15

14640@

15

14640@

U

U

C

SA00006KL00

MAX14640ETA

MAX14640ETA

D D

+

12

U

SB_CHG_EN#

+

5VALW

USB_VCCA

W

=100mils

R43 0.1U_0402_10V7K

R43 0.1U_0402_10V7K

C

C

1 2

R42 47U_0805_6.3V6M

R42 47U_0805_6.3V6M

C

C

U

SB_CHG_EN#<34>

S

2

.5A

R4

R4

U

U

2

N

I

3

N

I

4

N/ENB

E

1

ND

G

G547N2P81U_MSOP8

G547N2P81U_MSOP8

SA00006DN00

LP_CHG_CB1<25>

O
O
O
O

UT
UT
UT
CB

HG_PWR_GATE#<34>

W=100mils

+

USB_VCCA

6
7
8
5

2

R

R

R2

R2

0_0402_5%

0_0402_5%

14641@

14641@

@EMI@

@EMI@

1 2

78 1000P_0402_50V7K

78 1000P_0402_50V7K

C

C

U

SB_CHG_OC# <24,34>

U

SB20_DN10

U

SB20_DP10

1

C

4

S

A00006C400

U

U

1
2
3

HG_CB1

4
9

MAX14641ETA+TGH7_TDFN-EP8_2X 2

MAX14641ETA+TGH7_TDFN-EP8_2X 2

15

15

EN

C

M

D

P

D

B1

C
P

GND

14641@

14641@

3

R3

14641@RR3

14641@

8

C

HG_CB0

C

B0

7

U

SB20_N10

T

DM

6

U

SB20_P10

T

DP

5

CC

V

E

C_SMB_CK1<34,39,40,9>

E

C_SMB_DA1<34,39,40,9>

1

C

C

R10

R10

0.1U_0402_10V7K

0.1U_0402_10V7K

2

E

C_SMB_CK1

E

C_SMB_DA1

U

SB20_N10 <24>

U

SB20_P10 <24>

+

5VALW

3

R

12

0_0402_5%

0_0402_5%

+

3VALW

2

G

G

6 1

D

D

5

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

G

G

Q

Q

R1B

R1B

14640@

14640@

4

S

S

D

D

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

4.7K_0402_5%

4.7K_0402_5%

R1A

R1A

Q

Q

14640@

14640@

S

S

S

LP_CHG_CB0 <25>

R4

R4

R

R

14640@

14640@

1 2

+

3VALW

2

R

R

4.7K_0402_5%

4.7K_0402_5%

14640@

14640@

1

C

HG_CB1

C

HG_CB0

R5

R5

2

U

SB Sleep & Charge

State table for MAX14641

CB1

0

0

1

1

0

1

0

1

Mode

AM2

AP1

P

M

CM

1

STATUS CB0

2A auto-detection charger mode for Apple device.
Resistor dividers are connected to DP/DM. Including DCP

Forced 1A charger mode for Apple devices.
Resistor dividers are connected to DP/DM.

USB pass-through mode.DP/DM are connected to TDP/TDM

USB pass-through mode with CDP emulation.
Auto connects DP/DM to TDP/TDM depending
on CDP detection status.

Front with S&C

L

R1

EMI@

R1

EMI@

L

C C

U

SB30_RX0N<24>

U

SB30_RX0P<24>

U

SB30_TX0N<24>

U

SB30_TX0P<24>

U

SB30_RX0N

U

SB30_RX0P

1 2

1 2

U

U

C

C

B22 0.1U_0402_16V7K

B22 0.1U_0402_16V7K

C

C

B21 0.1U_0402_16V7K

B21 0.1U_0402_16V7K

SB30_TX0N_C

SB30_TX0P_C

L

4

1

KINGCORE WCM-2012HS-670T

KINGCORE WCM-2012HS-670T

L

L

4

1

KINGCORE WCM-2012HS-670T

KINGCORE WCM-2012HS-670T

3

4

2

1

R2

EMI@

R2

EMI@

4

3

1

2

3

2

3

2

U

SB30_RX0N_L

U

SB30_RX0P_L

U

SB30_TX0N_C_L

U

SB30_TX0P_C_L

U

SB20_DP10

U

SB20_DN10

L

R3

EMI@

R3

EMI@

1

1

4

4

WCM-2012-900T_0805

WCM-2012-900T_0805

2

U

SB20_P10_L

2

3

U

SB20_N10_L

3

U

SB30_TX0P_C_L

U

SB30_TX0N_C_L

U

SB30_RX0P_L

U

SB30_RX0N_L

R7

R7

D

D

@ESD@

@ESD@

1

2

4

5

3

TVWDF1004AD0_DFN 9

TVWDF1004AD0_DFN 9

9

8

7

6

U

SB30_TX0P_C_L

U

SB30_TX0N_C_L

U

SB30_RX0P_L

U

SB30_RX0N_L

U

SB30_TX0P_C_L

U

SB30_TX0N_C_L

U

SB30_RX0P_L

U

SB30_RX0N_L

U

SB20_P10_L

U

SB20_N10_L

+

USB_VCCA

USBF

USBF

J

J

9

tdA-SSTX+

G

S

8

tdA-SSTX-

G

S

7

ND-DRAIN

G

G

6

tdA-SSRX+

G

S

5

tdA-SSRX-

S

4

ND

G

3

+

D

2

-

D

1

BUS

V

LOTES_AUSB0015-P001A

LOTES_AUSB0015-P001A

@

@

13

ND

12

ND

11

ND

10

ND

Rear

W

+

U

SB_EN#0

5VALW

R3

R3

U

U

2

N

I

3

N

I

4

N/ENB

E

1

ND

G

SY6288DCAC_MSOP8

SY6288DCAC_MSOP8

SA00004KB00
SA00003TV00

R5

R5

L

L

4

4

1

1

KINGCORE WCM-2012HS-670T

KINGCORE WCM-2012HS-670T

R6

R6

L

L

4

4

1

1

KINGCORE WCM-2012HS-670T

KINGCORE WCM-2012HS-670T

B B

U

SB_EN#0< 34>

U

U

SB30_RX1N<24>

U

SB30_RX1P<24>

U

SB30_TX1N<24>

U

A A

SB30_TX1P<24>

SB30_RX1N

U

SB30_RX1P

1 2

U

1 2

SB30_TX1N_C

U

SB30_TX1P_C

C

C

B24 0.1U_0402_16V7K

B24 0.1U_0402_16V7K

B23 0.1U_0402_16V7K

B23 0.1U_0402_16V7K

C

C

=80mils

+

USB_VCCB

6

UT

O

7

UT

O

8

UT

O

5

CB

O

EMI@

EMI@

3

3

2

2

EMI@

EMI@

3

3

2

2

@EMI@

@EMI@

1 2

79 1000P_0402_50V7K

79 1000P_0402_50V7K

C

C

U

SB_OC#0 <24,34>

U

SB30_RX1N_L

U

SB30_RX1P_L

U

SB30_TX1N_C_L

U

SB30_TX1P_C_L

U

SB20_P11<24>

U

SB20_N11<24>

W=80mils

+

USB_VCCB

1

C

C

2

47U_0805_6.3V6M

47U_0805_6.3V6M

U

SB20_P11

U

SB20_N11

0.1U_0402_10V7K

0.1U_0402_10V7K

1

R46

R46

2

4

1

R44

R44

C

C

R4

R4

L

L

4

1

WCM-2012-900T_0805

WCM-2012-900T_0805

EMI@

EMI@

3

U

SB20_P11_L

3

2

U

SB20_N11_L

2

U

SB30_TX1P_C_L

U

SB30_TX1N_C_L

U

SB30_RX1P_L

U

SB30_RX1N_L

R8

R8

D

D

@ESD@

@ESD@

1

2

4

5

3

TVWDF1004AD0_DFN 9

TVWDF1004AD0_DFN 9

9

8

7

6

U

SB30_TX1P_C_L

U

SB30_TX1N_C_L

U

SB30_RX1P_L

U

SB30_RX1N_L

U

SB30_TX1P_C_L

U

SB30_TX1N_C_L

U

SB30_RX1P_L

U

SB30_RX1N_L

U

SB20_P11_L

U

SB20_N11_L

+

USB_VCCB

J

J

USBR

USBR

9
8
7
6
5
4
3
2
1

G

S

tdA-SSTX+

G

S

tdA-SSTX-

G

G

ND-DRAIN

G

S

tdA-SSRX+

S

tdA-SSRX-

G

ND

D

+

D

-

V

BUS

LOTES_AUSB0015-P001A

LOTES_AUSB0015-P001A

@

@

13

ND

12

ND

11

ND

10

ND

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2

2

2

013/01/22 2014/01/21

013/01/22 2014/01/21

013/01/22 2014/01/21

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

Title

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

2

Date: Sheet

ompal Electronics, Inc.

U

U

U

SB3.0

SB3.0

SB3.0

L

L

L

A-9869P

A-9869P

A-9869P

1

o

o

o

f

31 50Monday, February 04, 2013

f

31 50Monday, February 04, 2013

f

31 50Monday, February 04, 2013

0

0

0

.3

.3

.3

5

U

U

A1

A1

M

IC1_LINE1_R_R

M

IC1_LINE1_R_L

E

A6010U_0603_6.3V6M

A6010U_0603_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

1

@

@

EMI@

EMI@

I

NT_MIC_CLK_R

C_MUTE_INT<34>

A

c

lose to pin19

C

C

A54

A54

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

I

NT_MIC_DATA<20>

E

C_MUTE#<34>

D D

A

Z_RST_HD#<24>

close to pin 28

1 2

C

C

1

A55

A55

C

C

0.1U_0402_10V7K

0.1U_0402_10V7K

C C

2

2

R

R

A34 20K_0402_1%

A34 20K_0402_1%

F

or EMI reserve

I

NT_MIC_CLK<20>

A42

A42

R

R
FBMA-10-100505-301T

FBMA-10-100505-301T

+

MIC1_VREFO_L

+

MIC1_VREFO_R

Z_SYNC_HD<24>

R

R

A30

A30

20K_0402_1%

20K_0402_1%

2

1

C

C

A584.7U_0603_6.3V6KCA584.7U_0603_6.3V6K

C

A574.7U_0603_6.3V6KCA574.7U_0603_6.3V6K

C

12

2

1

A53

A53

I

NT_MIC_CLK_R

1 2

M

A

S
S

22
21

17
16

31
30
29

15
14

20

12

ONO_IN

10

11

10 mil

19

C_JDREF

28

L

DO_CAP

27

A

C_VREF

34

C

PVEE

35

C

BN

36

C

BP

2
3

13

ENSE_A

18

ENSE_B

47

4

ALC259-VC2-CG_MQFN48_6X6

A50

A50

R

R

4.7K_0402_5%

4.7K_0402_5%

269@

269@

T

ALC259-VC2-CG_MQFN48_6X6

o solve S&M noise issue

Internal AMP

E

C_MUTE#

Hight

Enable

LOW

Disable

4

259: SA000054P00

M

IC1_R

M

IC1_L

M

IC2_R

M

IC2_L

IC1_VREFO_L

M

IC1_VREFO_R

M

IC2_VREFO

M

L

INE2_R

L

INE2_L

M

ONO_OUT

P

CBEEP

S

YNC

R

ESET#

J

DREF

DO_CAP

L

REF

V

PVEE

C

C

BN

C

BP

PIO0/DMIC_DATA

G

PIO1/DMIC_CLK

G

S

ENSE_A

S

ENSE_B

APD

E

D#

P

PK_OUT_R+

S

S

PK_OUT_L+

S

S

S

VDD

D

VDD_IO

D

VDD1

A

VDD2

A

VDD1

P

VDD2

P

PK_OUT_R-

PK_OUT_L-

POUT_R

H

POUT_L

H

DATA_OUT

DATA_IN

S

CLK

B

L

INE1_L

L

INE1_R

VSS1

A

A

VSS2

VSS1

P

VSS2

P

VSS

D

hermal Pad

T

3

3

5mA for 3.3V level

+

1

+

DVDD

9

+

DVDD

25

+

AVDD

38

+

AVDD

39

+

PVDD

46

+

PVDD

45

S

PKR+

44

S

PKR-

40

S

PKL+

41

S

PKL-

75_0402_1%

75_0402_1%

33

R

R

A19

A19

32

R

R

A20

A20

75_0402_1%

75_0402_1%

5
8

A

Z_SDIN0_HD_R

6

A

Z_BITCLK_HD

23

L

INE1_R_C_L

24

L

INE1_R_C_R

48

C

N

26

37

42
43
7

A

GND

49

D

GND

H

P_R <33>

H

P_L <33>

R

R

A23 33_0402_5%

A23 33_0402_5%

269@

269@

C

C

A9 1U_0402_6.3V4Z

A9 1U_0402_6.3V4Z

2

A10 1U_0 402_6.3V4Z

A10 1U_0 402_6.3V4Z

C

C

269@

269@

F

or EMI reserve

placed close to codec

A

Z_BITCLK_HD

c

lose to pin1

c

lose to pin9

12

12

1

@EMI@

@EMI@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

A

A

Z_SDIN0_HD <24>

A

12

R

R

A4110_0402_5%

A4110_0402_5%

10P_0402_50V8J

10P_0402_50V8J

DVDD

1

C

C

A4

A4

2

1

A45

A45

C

C

2

Z_SDOUT_HD <24>

Z_BITCLK_HD <24>

M

IC1_LINE1_R_L

M

IC1_LINE1_R_R

C

C

A51

A51

1 2

@EMI@

@EMI@

F

or S&M

R

R

A22

A22

0_0402_5%

0_0402_5%

1

A3

A3

C

C

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2

@

@

1 2

A44 680P_0603_50V8J

A44 680P_0603_50V8J

R

R

@

@

2

1

A43 680P_0603_50V8J

A43 680P_0603_50V8J

R

R

@

@

2

1

A31 680P_0603_50V8J

A31 680P_0603_50V8J

R

R

1

@EMI@

@EMI@

A38 0_0603_5%

A38 0_0603_5%

R

R

1

@EMI@

@EMI@

R

R

A39 0_0603_5%

A39 0_0603_5%

2

6

40 mil20 mil

close to pin 25 close to pin 38

+

AVDD

+

3VS

C

C

A42

A42

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_10V7K

0.1U_0402_10V7K

c

lose to pin39

0.1U_0402_10V7K

0.1U_0402_10V7K

c

lose to pin46

F
Please place them to ISPD page

2

2

269: SA00006BW00

50mA for 5V level

0.1U_0402_10V7K

0.1U_0402_10V7K

2

1

A47

A47

C

C

1

2

60 mil

+

1

C

C

A33

A33

2

1

A32

A32

C

C

2

or P/N and footprint

A1

A1

U

U

ALC269Q-VB6-CG

ALC269Q-VB6-CG

269@

269@

0.1U_0402_10V7K

0.1U_0402_10V7K

2

C

C

C

C

A50

A50

A37

A37

1

10U_0603_6.3V6M

10U_0603_6.3V6M

PVDD

1

2

2

A35

A35

C

C

1

10U_0603_6.3V6M

10U_0603_6.3V6M

1

A18

A18

R

R

1 2

0_0603_5%

0_0603_5%

A24

A24

R

R

1 2

0_0603_5%

0_0603_5%

+

5VALW

+

5VALW

S

B

eep sound

PCI Beep

F

B B

Sense Pin

SENSE A

A A

CH_SPKR<24>

Impedance

39.2K

20K

10K

5.1K

39.2K

20K

10K

5

Codec Signals

PORT-I (PIN 32, 33)

PORT-B (PIN 21, 22)

PORT-C (PIN 23, 24)

(PIN 48)

PORT-E (PIN 14, 15)

PORT-F (PIN 16, 17)SENSE B

PORT-H (PIN 20)

A52

A52

R

R

1 2

47K_0402_5%

47K_0402_5%

A49

A49

R

R

4.7K_0402_5%

4.7K_0402_5%

Function

Headphone out

Ext. MIC

2

1

Add CA15 for better
sound by A51

0.1U_0402_10V7K

0.1U_0402_10V7K

1

A15

A15

C

C

2

100P_0402_50V8J

100P_0402_50V8J

4

C

C

A70

A70

2

1

M

ONO_IN

PK

2W 4ohm =40mil
1W 8ohm =20mil

S

PKL+

S

PKL-

S

PKR+

S

PKR-

For EMI reserve
close to codec

2

1

@

@

R

R

A7 0_0603_5%

A7 0_0603_5%

1 2

@

@

A8 0_0603_5%

A8 0_0603_5%

R

R

C

C

1000P_0402_50V7K

1000P_0402_50V7K

@EMI@

@EMI@

2

1

@

@

A9 0_0603_5%

A9 0_0603_5%

R

R

1 2

@

@

A10 0_0 603_5%

A10 0_0 603_5%

R

R

C

C

1000P_0402_50V7K

1000P_0402_50V7K

@EMI@

@EMI@

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2

2

2

013/01/22 2014/01/21

013/01/22 2014/01/21

013/01/22 2014/01/21

1

1

C

2

1

2

C
1000P_0402_50V7K

1000P_0402_50V7K

2

@EMI@

@EMI@

1

C

C
1000P_0402_50V7K

1000P_0402_50V7K

2

@EMI@

@EMI@

C

C

C

A31

A31

A34

A34

S

PK_L1 <33>

S

PK_L2 <33>

A30

A30

S

PK_R1 <33>

S

PK_R2 <33>

A36

A36

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

M

IC/LINE IN

M

M

S

M_SENSE#<34>

E

C

2

IC1_LINE1_R_R

IC1_LINE1_R_L

+

3VL

A47

A47

R

R

1K_0402_5%

1K_0402_5%

2

1

12

1K_0402_5%

1K_0402_5%

A45

A45

R

R

M

IC_SENSE

A1A

A1A

Q

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

R

R

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

Q

269@

269@

A35 100 K_0402_5%

A35 100 K_0402_5%

Q

Q

A1B

A1B

269@

269@

p

lace close to chip

M

IC_SENSE

R

R

N

BA_PLUG<33>

R

R

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

12

+

+

269@

269@

C

C

C

over Sheet

over Sheet

over Sheet

MIC1_VREFO_R

MIC1_VREFO_L

S

ENSE_A

1

R

R

A48 2.2K_0402_5%

A48 2.2K_0402_5%

12

R

R

A46 2.2K_0402_5%

A46 2.2K_0402_5%

6

R

R

A29

A29

100K_0402_5%

100K_0402_5%

2

1

3

5

4

12

A32 20K_0402_1%

A32 20K_0402_1%

A33 39.2K_0402_1%

A33 39.2K_0402_1%

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

M

IC1_R <33>

M

IC1_L <33>

R

R

A37

A37

0_0402_5%

0_0402_5%

259@

259@

J

ACK_SENSE < 33>

o

o

o

f

32 50Monday, February 04, 2013

f

32 50Monday, February 04, 2013

f

32 50Monday, February 04, 2013

0

0

0

.3

.3

.3

Card reader

SPK CONN.

Non-Harman detection

please close the pin4 of UW1

+

3VS_CR

30mils

W3

W3

C

C

2.2U_040 2_6.3V6M

2.2U_040 2_6.3V6M

For power consumption measurement
and remove it after Pre-MP phase

30mils

1

W4

W4

C

C

0.1U_040 2_16V4Z

0.1U_040 2_16V4Z

2

1 2

+

3VS

W2

W2

R

R

0_0402_ 5%

0_0402_ 5%

2.2U_040 2_6.3V6M

2.2U_040 2_6.3V6M

NC (default)

Power saving mode

Card Uninsertion

Card Insertion

< 2 in 1 Card Reader >

12

G

ND_SW

13

G

ND_SW

Close

Open CloseOpen

J

J

CARD

CARD

V

DD

C

MD
C
V

SS
V

SS

D

AT0

D

AT1

D

AT2

C

D/DAT3

W

P_SW

C

D_SW

T-SOL_15 6-2000302604@

T-SOL_15 6-2000302604@

LK

"Normal Close" type connector

please close the pin19 of UW1

+

1

2

3VS_CR

W1

W1

C

C

C

C

0.1U_040 2_16V4Z

0.1U_040 2_16V4Z

U

SB20_N2<24>

U

SB20_P2<24>

+

VCC_3IN1

1

30mils

2

C

C

W5

W5

0.1U_040 2_16V4Z

0.1U_040 2_16V4Z

+

3VS_CR

30mils

W8

W8

+

3VS_CR

+3VS_CR

+3VS_CR
+

VDD18

12mils

1

2

10K pull down

Normal modeGPIO0

WP_SWCD_SW

Protect disable Protect Enable

Close

5
3
6
7
4

8
9
1
2

10
11

S

DCMD

S

DCLK_R

S

D_DATA0

S

D_DATA1

S

D_DATA2

S

D_DATA3

S

DWP#

S

DCD

Close

+3VS_CR

1

C

C

W2

W2

0.1U_040 2_16V4Z

0.1U_040 2_16V4Z

2

1

U

U

W1

W1

2

22

2
3

1

24

19
23
20

4

18

25

SA00005M300

R

STZ

D

M

D

P

D

VDD

P

MOS

D

VDD

D

VDD

G

PIO0

A

VDD

V

DD18

T

hermal pad

GL834L-O GY01_QFN24_4X4

GL834L-O GY01_QFN24_4X4

S
S

S

S

Close to connector

1

W6

W6

C

C

0.1U_040 2_16V4Z

0.1U_040 2_16V4Z

2

S_INS

R

R

W5

W5

5
17
16
15
14
21
13
12
11
10
9
8
7
6

1 2

0_0402_ 5%

0_0402_ 5%

EMI@

EMI@

SD_DATA 2
SD_DATA 3
SDCMD
SDCLK
SDCD#
SD_DATA 0
S

D_DATA1

SDWP+3VS_CR

S

DCLK

M
D_D2/MS_D5/SB13
D_D3/MS_D4/SB12

S

D CMD/SD_CMD
S

D CLK/SD_CLK

S

D_CDZ

S

D_D0/MS_D6/SB9

S

D_D1/MS_D7/SB8

M

S BS/MS_BS

D_WP/MS_D1/SB5

S

D_D4/MS_D0/SB4

S

D_D5/MS_D2/SB3

S

D_D6/MS_D3/SB1

D_D7/MS_CLK/SB0

For normal close type connector invert circuit

+

3VS_CR

W4

W4

R

R
100K_04 02_5%

100K_04 02_5%

S

DWP#

+

3VS_CR

R

R

W3

W3

100K_04 02_5%

100K_04 02_5%

S

DCD

Close to IC

1

C

C

W7

W7

2.2U_040 2_6.3V6M

2.2U_040 2_6.3V6M

2

12

Q

Q

5

G

G

12

Q

Q

2

G

G

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

W1B

W1B

W1A

W1A

3

D

D

S

S

4

61

D

D

S

S

30mil

+

VCC_3IN1

S

DWP

2N7002K DWH_SOT36 3-6

2N7002K DWH_SOT36 3-6

S

DCD#

2N7002K DWH_SOT36 3-6

2N7002K DWH_SOT36 3-6

S

DCLK_R

2

W10

W10

C

C
10P_040 2_50V8J

10P_040 2_50V8J

1

@EMI@

@EMI@

For common design,
pull-high resistor should
be placed at connector
side.

S

PK_R1<32 >

S

PK_R2<32 >

S

PK_L1<32 >

S

PK_L2<32 >

S

PK_DET<25>

CK0402101V05_0402-2

CK0402101V05_0402-2

D

D

@ESD@

@ESD@

@ESD@

@ESD@

27

27

1 2

HeadPhone/LINE Out JACK

H

P_L<32>

H

P_R<32>

N

BA_PLUG<32>

1

A21 0_0402_5%

A21 0_0402_5%

R

R

1 2

A25 0_0402_5%

A25 0_0402_5%

R

R

Ext.MIC/LINE IN JACK

M

IC1_L<32>

M

IC1_R<32 >

C

C

C

ompal Secret Data

ompal Secret Data

2

2

2

013/01/2 2 2014/01/ 21

013/01/2 2 2014/01/ 21

013/01/2 2 2014/01/ 21

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

1

A26 0_0402_5%

A26 0_0402_5%

R

R

1

A27 0_0402_5%

A27 0_0402_5%

R

R

D

D

1

YSDA0502C _SOT23-3

YSDA0502C _SOT23-3
@ESD@

@ESD@

CK0402101V05_0402-2

CK0402101V05_0402-2

D

D

@ESD@

@ESD@

28

28

1 2

2

@

@

@

@

A6

A6

D

D

1

YSDA0502C _SOT23-3

YSDA0502C _SOT23-3
@ESD@

@ESD@

2

@

@

2

@

@

A7

A7

10K_040 2_5%

10K_040 2_5%

CK0402101V05_0402-2

CK0402101V05_0402-2

2

D

D
29

29

1

3

2

3

2

0

ONKYO

SPK_DET0

1

Non-Brand

Please check SPK_DET pull high 10K to +3VS

+

3VS

A95

A95

R

R

ACES_50 228-0067N-001

1 2

CK0402101V05_0402-2

CK0402101V05_0402-2

@ESD@

@ESD@

D

D
30

30

1 2

HP_R_L

H

P_R_R

M

IC1_R_L

MIC1_R_R

J

ACK_SEN SE<32>

+

3VL

A40

A40

R

R

4.7K_040 2_5%

4.7K_040 2_5%

269@

269@

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

M

M

M

onday, February 04, 2013

onday, February 04, 2013

onday, February 04, 2013

Date: Sheet

Date: Sheet

Date: Sheet

ACES_50 228-0067N-001

8

G

ND

7

G

ND

6

6

5

5

4

4

3

3

2

2

1

1

J

J

SPK@

SPK@

LINE

@

LINE

@

J

J

6
1
2

3

4

5

SINGA_2SJ -0960-D11

SINGA_2SJ -0960-D11

EXMIC

@

EXMIC

@

J

J

6
1
2

3

4

5

SINGA_2SJ -0960-D11

SINGA_2SJ -0960-D11

A36

A36

R

R
0_0402_ 5%

0_0402_ 5%

259@

259@

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

C

C

C

R & Audio Conn.

R & Audio Conn.

R & Audio Conn.

L

L

L

A-9869P

A-9869P

A-9869P

3

3

3

3 50

3 50

3 50

0

0

0

.3

.3

.3

o

o

o

f

f

f

5

0.1U_0402_10V7K

1

C

C

B2

B2

B4

B4

C

C

2

0.1U_0402_10V7K

0.1U_0402_10V7K

ATEA20<24>
B_RST#<24>
ERIRQ<23>

PC_AD3<23>
PC_AD2<23>
PC_AD1<23>
PC_AD0<23>

PC_RST#<23>

C_SCI#<24>

S

LP_S3#<24>

S

LP_S5#<24>
C_SMI#<24>

B_LED<35>

L_OFF#<28>

2
2

0.1U_0402_10V7K

1

2

C

HG_PWR_GATE#

E

C_MUTE_INT_R

100K_0402_5%

100K_0402_5%

0.1U_0402_10V7K

0.1U_0402_10V7K

1

B1

B1

C

C

0.1U_0402_10V7K

C_RST#

E

C_SMB_CK1

E

C_SMB_DA1

E

C_SMB_CK2

E

C_SMB_DA2

S

USP#

C_MUTE_INT<32>

E

51_TXD

R

TC_CLK<23,26>

0.1U_0402_10V7K

T

RANS_SEL

L

OW

HIGH

2

G
K
S

L

PC_FRAME#<23>

L
L
L
L

C

LK_PCI_EC<23,26>

L

E

HG_PWR_GATE#<31>

C

E

C_SMB_CK1<31,39,40,9>

E

C_SMB_DA1<31,39,40,9>

E

C_SMB_CK2<13,35>

E

C_SMB_DA2<13,35>

E

SB_OC#2<24,30>

U

SB_CHG_OC#<24,31>

U

U

SB_CHG_EN#<31>

U

SB_EN#2< 30>

K

F

AN_SPEED1<5>

W
E

51_TXD<28>

E

51_RXD<28>

CH_PWRGD<24>

F
T_ON<28>

B

M_SENSE#<32>

S

1

@

@

1

R

R

@

@

B38 0_0402_5%

B38 0_0402_5%

R

R

B20 0_0402_5%

B20 0_0402_5%

F

or EMI

C

LK_PCI_EC

12

R

R

B3

B3

10_0402_5%

10_0402_5%

@EMI@

D D

+

3VL

+

R

R

K

K

SO[0..15]<35>

C C

3VALW_FCH

+

B B

@EMI@

C

C

B11

B11

22P_0402_50V8J

22P_0402_50V8J

@EMI@

@EMI@

3VL

B2

B2

R

R

47K_0402_5%

47K_0402_5%

2

1

1 2

C

C

B12 0.1U_0402_10V7K

B12 0.1U_0402_10V7K

2

1

B25 10K _0402_5%

B25 10K _0402_5%

SI[0..7]<35>

B28 10K_0402_5%

B28 10K_0402_5%

R

R

3VL

+

3VS

+

1 8
2
3 6
4 5

2.2K_0804_8P4R_5%

2.2K_0804_8P4R_5%

@

@
1 2

B13 1U_0402_6.3V6K

B13 1U_0402_6.3V6K

C

C

@ESD@

@ESD@

1 2

C

C

B14 180P_0402_50V8J

B14 180P_0402_50V8J

1

2

E

C

HG_PWR_GATE#

K

SI[0..7]

K

SO[0..15]

LVDS@

LVDS@

12

PB1

PB1

R

R

7

L

PC_RST#

Close to EC

@ESD@

@ESD@

1 2

B17 180P_0402_50V8J

B17 180P_0402_50V8J

C

C

100K_0402_5%

100K_0402_5%

A A

V

oltage Comparator Pins FOR 9012 A3

V

CIN0 pin109

VCIN1 pin102

V

COUT0 pin104

VCOUT1 pin103

B37

B37

R

R

47K_0402_5%

47K_0402_5%

2

1

B27

B27

R

R

1 2

>1.2V <1.2V

F

CH_PWRGD

E

C_MUTE_INT_R

E

HIGH

L

OW

5

1

B5

B5

C

C

2

1000P_0402_50V7K

1000P_0402_50V7K

E

C_RST#

K
K
K
K
K
K
K
K

K

SO0

K

SO1

K

SO2

K

SO3

K

SO4

K

SO5

K

SO6

K

SO7

K

SO8

K

SO9

K

SO10

K

SO11

K

SO12

K

SO13

K

SO14

K

SO15

T

RANS_SEL

F

CH_PWRGD

X

CLKO

12

R

R

B22

B22

4

1

C

C

2

SI0
SI1
SI2
SI3
SI4
SI5
SI6
SI7

1

2

4

1000P_0402_50V7K

1000P_0402_50V7K

1

B7

B7

C

C

B6

B6

2

B1

B1

U

U

1

ATEA20/GPIO00

G

2

BRST#/GPIO01

K

3

ERIRQ

S

4

PC_FRAME#

L

5

PC_AD3

L

7

PC_AD2

L

8

PC_AD1

L

10

L

L

PC_AD0

L

12

LK_PCI_EC

C

13

CIRST#/GPIO05

P

37

C_RST#

E

20

C_SCII#/GPIO0E

E

38

PIO1D

G

55

SI0/GPIO30

K

56

SI1/GPIO31

K

57

SI2/GPIO32

K

58

SI3/GPIO33

K

59

SI4/GPIO34

K

60

SI5/GPIO35

K

61

SI6/GPIO36

K

62

SI7/GPIO37

K

39

SO0/GPIO20

K

40

SO1/GPIO21

K

41

SO2/GPIO22

K

42

SO3/GPIO23

K

43

SO4/GPIO24

K

44

SO5/GPIO25

K

45

SO6/GPIO26

K

46

SO7/GPIO27

K

47

SO8/GPIO28

K

48

SO9/GPIO29

K

49

SO10/GPIO2A

K

50

SO11/GPIO2B

K

51

SO12/GPIO2C

K

52

SO13/GPIO2D

K

53

SO14/GPIO2E

K

54

SO15/GPIO2F

K

81

K

SO16/GPIO48

82

K

SO17/GPIO49

77

E

C_SMB_CK1/GPIO44

78

E

C_SMB_DA1/GPIO45

79

E

C_SMB_CK2/GPIO46

80

E

C_SMB_DA2/GPIO47

6

M_SLP_S3#/GPIO04

P

14

M_SLP_S5#/GPIO07

P

15

C_SMI#/GPIO08

E

16

PIO0A

G

17

PIO0B

G

18

PIO0C

G

19

PIO0D

G

25

C_INVT_PWM/GPIO11

E

28

AN_SPEED1/GPIO14

F

29

C_PME#/GPIO15

E

30

C_TX/GPIO16

E

31

C_RX/GPIO17

E

32

CH_PWROK/GPIO18

P

34

USP_LED#/GPIO19

S

36

UM_LED#/GPIO1A

N

122

X

CLKI/GPIO5D

123

X

CLKO/GPIO5E

B16

B16

C

C
20P_0402_50V8

20P_0402_50V8

E

C_ON_R

8

85_EC_ON

3VL

+

PC & MISC

PC & MISC

nt. K/B

nt. K/B

I

I
Matrix

Matrix

R

B24

885@RB24

885@

10K_0402_5%

10K_0402_5%

9

22

33

96

111

125

C_VDD0
E

C_VDD/VCC

C_VDD/VCC

C_VDD/VCC

C_VDD/VCC
E

E

E

E

PWM Output

PWM Output

AD Input

AD Input

DA Output

DA Output

PS2 Interface

PS2 Interface

SPI Device Interface

SPI Device Interface

SPI Flash ROM

SPI Flash ROM

GPIO

GPIO

SM Bus

SM Bus

GPIO

GPIO

ND/GND

ND/GND

ND/GND

ND/GND
G

G

G

G

11

24

35

94

113

9012@

9012@

2

1

R

R

B36 0_0 402_5%

B36 0_0 402_5%

S

S

1 3

D

D

B2

B2

Q

Q
2N7002KW_SOT323-3

2N7002KW_SOT323-3

885@

885@

G

G

2

1 2

3VL

+

B3

B3

C

C

0.1U_0402_10V7K

0.1U_0402_10V7K

1 2

67

C_VDD/VCC
E

C_VDD/AVCC

EEP#/GPIO10

B

E

COFF/GPIO13

A

ATT_TEMP/GPIO38

B

DP_I/GPIO3A

A

I

MON/GPIO43

D

AC_BRIG/GPIO3C

E

N_DFAN1/GPIO3D

I

REF/GPIO3E

C

HGVADJ/GPIO3F

E

C_MUTE#/GPIO4A

U

SB_EN#/GPIO4B

C

AP_INT#/GPIO4C

E

APD/GPIO4D

T

P_CLK/GPIO4E

T

P_DATA/GPIO4F

C

PU1.5V_S3_GATE/GPXIOA00

W

OL_EN/GPXIOA01

M

E_EN/GPXIOA02

V

CIN0_PH/GPXIOD00

S

PIDI/GPIO5B

S

PIDO/GPIO5C

S

PICLK/GPIO58

S

PICS#/GPIO5A

E

NBKL/GPIO40

P

ECI_KB930/GPIO41

F

STCHG/GPIO50

B

ATT_CHG_LED#/GPIO52

C

APS_LED#/GPIO53

P

WR_LED#/GPIO54

B

ATT_LOW_LED#/GPIO55

S

YSON/GPIO56

V

R_ON/GPIO57

P

M_SLP_S4#/GPIO59

E

C_RSMRST#/GPXIOA03

E

C_LID_OUT#/GPXIOA04

P

ROCHOT_IN/GPXIOA05

H

_PROCHOT#_EC/GPXIOA06

V

COUT0_PH/GPXIOA07

GPO

GPO

B

KOFF#/GPXIOA08

P

BTN_OUT#/GPXIOA09

P

CH_APWROK/GPXIOA10

S

A_PGOOD/GPXIOA11

A

C_IN/GPXIOD01

E

C_ON/GPXIOD02

O

N/OFF/GPXIOD03

GPI

GPI

L

ID_SW#/GPXIOD04

S

USP#/GPXIOD05

G

P

ND0
G

69

PXIOD06

ECI_KB9012/GPXIOD07

GND/AGND
A

KB9012QF-A3_LQFP128_14X14

KB9012QF-A3_LQFP128_14X14

9012@

9012@

1

2

S

S

S

T

T

T
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

21

PIO0F

G

23
26

PIO12

G

27

63
64

PIO39

G

65
66

G

PIO3B

75

G

PIO42

76

68
70

8

85_EC_ON

71
72

83
84
85
86
87
88

97
98
99
109

119
120
126
128

73
74
89
90

B

ATT_FULL_LED#

91
92
93
95
121
127

100
101
102
103

H

_PROCHOT_EC

104

V

COUT0_PH_L

105
106
107
108

110

A

CIN_D

112

E

C_ON_R

114
115
116
117
118

124

+

V

18R

U

U
NPCE885NB0DX LQFP 128P

NPCE885NB0DX LQFP 128P

R

R

1U_0402_6.3V6K

1U_0402_6.3V6K

B50

B50

C

C

@

@

ecurity Classification

ecurity Classification

ecurity Classification

ssued Date

ssued Date

ssued Date

I

I

I

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

EC_V18R

B1

885@

B1

885@

885@

885@

12

B19 330K_0402_5%

B19 330K_0402_5%

3

W

L_BT_LED# <35>

U

SB_EN#0 <31>

ANPWM <5>

F

B

ATT_PRES <39>

SB_OC#0 <24,31>

U

A

DP_I <39,40>

DP_V <40>

A

H

DPLOCK <35>

E

C_ENBKL <19>

H

DPINT < 35>

E

C_MUTE# <32>

C_SMB_CK3 <19>

E

C_SMB_DA3 <19>

E

T

P_CLK <36>

T

P_DATA <36>

V

GATE <45>

PU_DOWN# <13>

G

OK <41>

P

V

CIN0_PH <39>

C_SDIO <25>

E

C_SDI <25 >

E

C_SCK <25>

E

C_CS0# <25>

E

L

CD_ENBKL <20,9>
W

OL_EN# <30>

H

DPACT <35>

B

ATT_FULL_LED# <35>

C

APS_LED# <35>

B

ATT_CHG_LOW_LED# <35>

S

YSON <37,42>

V

R_ON <37,44,45>

.1VPWR_EN <43>

1

E

C_RSMRST# <24>

E

C_LID_OUT# < 24>

P

ROCHOT_IN <39>

B

KOFF# <20>

P

BTN_OUT# <24>
F

CH_PWR_EN <37>

C_PXCONTROL <24>

E

O

N/OFFBTN# <36>

L

ID_SW# <36>
S

USP# <37,42>

1

C

C

B15

B15

4.7U_0805_10V4Z

4.7U_0805_10V4Z

2

3VL

+

E

C_ON <41>

013/01/22 2014/01/21

013/01/22 2014/01/21

013/01/22 2014/01/21

2

2

2

V

CIN0_PH connect to

power portion ( 9012 only)

Nuvoton EC shar e ROM

ompal Secret Data

ompal Secret Data

ompal Secret Data

C

C

C

eciphered Date

eciphered Date

eciphered Date

D

D

D

2

2

1

@

@

R

R

B14 0_0402_5%

B14 0_0402_5%

H

_PROCHOT_EC

H

_PROCHOT_EC

H

igh Active

H

_PROCHOT_EC

2

CK0402101V05_0402-2

CK0402101V05_0402-2

D

D

@ESD@

@ESD@

B2

B2

1 2

1 2

R

R

B6 10K_0402_5%

B6 10K_0402_5%

P

WR_SUSP_LED# <35>

1

D

D

2

G

G

S

S

3

@

@

B1

B1

Q

Q
2N7002KW_SOT323-3

2N7002KW_SOT323-3

+

Date: Sheet

Date: Sheet

Date: Sheet

1

B

ATT_PRES

A

CIN_D

E

C_SMB_CK3

E

C_SMB_DA3

L

ID_SW#

T

P_CLK

T

P_DATA

S

YSON

V

COUT0_PH_L

V

COUT0_PH connect to power portion (9012 only)

A

CIN_D

S

USP#

V

R_ON

Low Active (+1. 5V)

3VS

itle

itle

itle

T

T

T

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

1 2

C

C

B9 100P_0402_50V8J

B9 100P_0402_50V8J

1 2

C

C

B10 100P_0402_50V8J

B10 100P_0402_50V8J

LVDS@

LVDS@

1

2

B135 4.7K_0402_5%

B135 4.7K_0402_5%

R

R

1 2

R

R

B136 4.7K_0402_5%

B136 4.7K_0402_5%

LVDS@

LVDS@

1 2

R

R

B35 47K _0402_5%

B35 47K _0402_5%

1 2

B8 4.7K_0402_5%

B8 4.7K_0402_5%

R

R

2

1

R

R

B9 4.7K_0402_5%

B9 4.7K_0402_5%

1 2

R

R

B10 4.7K_0 402_5%

B10 4.7K_0 402_5%

1 2

@

@

B34 0_0402_5%

B34 0_0402_5%

R

R

B18

B18

R

R

330K_0402_5%

330K_0402_5%

12

2

1 2

R

R

B21 10K _0402_5%

B21 10K _0402_5%

2

1

R

R

B23 10K _0402_5%

B23 10K _0402_5%

H

_PROCHOT# <45,7>

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

C

C

C

PC-EC-KB9012

PC-EC-KB9012

PC-EC-KB9012

L

L

L

A-9869P

A-9869P

A-9869P

L

L

L

onday, February 04, 2013

onday, February 04, 2013

onday, February 04, 2013

M

M

M

3VS

+

3VL

+

3VS

+

V

S_ON <41>

3VL

+

1

A

B1RB751V40_SC76-2DB1RB751V40_SC76-2

D

1

CIN <40>

f

4 50

f

4 50

f

4 50

3

3

o

3

o

o

.3

.3

.3

0

0

0

1

B

attery Reset

2

3

4

5

6

7

8

G-SENSOR

P

S

ELF_TEST

1

2

5

4

+

3VS_HDP

G2

G2

C

C

12

@

@

0.22U_0402_10V4Z

0.22U_0402_10V4Z

1

2

3

4

5

6

7

8

9

10

1

G9

G9

C

C

GSENSOR@

GSENSOR@

0.1U_0402_10V7K

0.1U_0402_10V7K

2

1

G1

G1

C

C

1U_0402_6.3V6K

1U_0402_6.3V6K

GSENSOR@

GSENSOR@

2

U

U

G1

G1

P

3_5/SSCK/SCL/CMP1_2

P

3_7/CNTR0#/SSO/TXD1

R

ESET#

X

OUT/P4_7

V

SS/AVSS

X

IN/P4_6

V

CC/AVCC

M

ODE

P

4_5/INT0#/RXD1

P

1_7/CNTR00/INT10#

+

3VS_HDP

S

ELF_TEST

+

3VS_HDP

GSENSOR@

GSENSOR@

SA00003A600

R5F211B4D34SP

R5F211B4D34SP

U

U

G3

GSENSOR@

G3

GSENSOR@

2

dd1

V

12

V

4

S

6

P

8

F

9

R

TSH352TR LGA 16P

TSH352TR LGA 16P

SA00004GB00

P

1_5/RXD0/CNTR01/INT11#

P

P

P

P

P

3_3/TCIN/INT3#/SSI00/CMP1_0

P

3_4/SCS#/SDA/CMP1_1

V

dd2

V
V

T
D

S

ev

G
G

P

1_6/CLK0/SSI01

P

1_4/TXD0

1_3/KI3#/AN11/TZOUT

1_2/KI2#/AN10/CMP0_2

P

4_2/VREF

1_1/KI1#/AN9/CMP0_1

1_0/KI0#/AN8/CMP0_0

N
N
N
N
N

ND1
ND2

3

outx

5

outy

7

outz

10

C1

11

C2

14

C3

15

C4

16

C5

1
13

11

12

13

14

15

16

17

18

19

20

1 2

V

OUTX

C

C

G4 0.033U_04 02_16V7K GSENSOR@

G4 0.033U_04 02_16V7K GSENSOR@

1 2

V

OUTY

G5 0.033U_04 02_16V7K GSENSOR@

G5 0.033U_04 02_16V7K GSENSOR@

C

C

2

1

V

OUTZ

C

C

G6 0.033U_04 02_16V7K GSENSOR@

G6 0.033U_04 02_16V7K GSENSOR@

H

DPACT <34>

R

R

G2

G2

47K_0402_5%

47K_0402_5%

GSENSOR@

GSENSOR@

1 2

H

DPLOCK <34>

R

R

G4 47K _0402_5%

G4 47K _0402_5%

V

V

V

OUTZ

OUTX

OUTY

GSENSOR@

GSENSOR@

+

3VS_HDP

1

G7

G7

C

C

0.1U_0402_10V7K

0.1U_0402_10V7K

GSENSOR@

GSENSOR@

2

E

C_SMB_DA2 <13,34>

12

+

5VS

1

G2

GSENSOR@

G2

G3

G3

C

C

1U_0402_6.3V6K

1U_0402_6.3V6K

GSENSOR@

GSENSOR@

A A

E

NLDO<41>

Keyboard LED

Q

Q

38

38

KBL@

KBL@

AO3413_SOT23

AO3413_SOT23

D

S

D

S

13

G

G

2

Q

Q

52

52

2N7002KW_SOT323-3

2N7002KW_SOT323-3

KBL@

KBL@

587

587

R

R

10K_0402_5%

B

K

B_LED<34>

N

EW KEYBOARD CONN.

10K_0402_5%

KBL@

KBL@

2

G

G

+

5VS

1

2

13

D

D

S

S

+

5VS_LED

W6

W6

S

S
TJG-533-V-T/R_6P

TJG-533-V-T/R_6P

3

4

6

5

1

2

+

3VS_HDP

1 8
2 7
3
4 5

H

DPINT<34>

+

5VS_LED

BLG @

BLG @

J

J

1

1

2

2

3

3

4

4

5

ND

G

6

ND

G

ACES_50578-0040N-001

ACES_50578-0040N-001

LED

2

E

C_SMB_CK2<13,34>

PG1

PG1

R

R

G

_RESET#

G

XOUT

6

G

XIN

G

_MODE

4.7K_8P4R_5%

4.7K_8P4R_5%

GSENSOR@

GSENSOR@

BATT CHARGE(Blink) /FULL LED

GSENSOR@

U

U

1

IN

OUT

V

V

2

ND

G

3

HDN#

B

S

G9191-330T1U_SOT23-5

G9191-330T1U_SOT23-5

S

A000022I00

G

_RESET#

G

XOUT

G

XIN

+

3VS_HDP

G

_MODE

G7 1K_0402_5%

G7 1K_0402_5%

R

R

12

GSENSOR@

GSENSOR@

C

C

G8

G8

0.1U_0402_10V7K

0.1U_0402_10V7K

GSENSOR@

GSENSOR@

B

K

SI[0..7]

K

SO[0..15]

C C

C

APS_LED#<34>

+

D D

1

K

SI[0..7] <34>

K

SO[0..15] <34>

KB

KB

J

J

1

1

2

2

3

3

2

7 300_0402_5%

7 300_0402_5%

1

3VS

R

R

K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K

SI1
SI6
SI5
SI0
SI4
SI3
SI2
SI7
SO15
SO12
SO11
SO10
SO9
SO8
SO13
SO7
SO6
SO14
SO5
SO3
SO4
SO0
SO1
SO2

4

4

5

5

6

6

7

7

8

8

9

9

10

0

1

11

1

1

12

2

1

13

3

1

14

4

1

15

5

1

16

6

1

17

7

1

18

8

1

19

9

1

20

0

2

21

1

2

22

2

2

23

3

2

24

4

2

25

5

2

26

6

2

27

7

2

28

8

2

29

9

2

30

0

3

31

1

3

32

2

3

33

3

3

34

4

3
ND1

G

ND2

G

CVILU_CF17341U0R0-NH

CVILU_CF17341U0R0-NH

@

@

2

35
36

3

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

4

+

5VALW

W

hite LED bright when both AC-adaptor is plugged in and Battery is full charged
Amber LED bright while charging battery from AC-adaptor.
Amber LED blink during Critical Low Battery

POWER LED(Blink)

+

5VALW

White LED bright when system is power on.
White LED blink when system is sleep mode.

WLAN LED

+

5VS

7

7

D

D

2 1

HT-F196BP5_WHITE

HT-F196BP5_WHITE

D

D

9

9

2

HT-191UD5_AMBER_0603

HT-191UD5_AMBER_0603

D

D

2 1

HT-F196BP5_WHITE

HT-F196BP5_WHITE

2 1

HT-191UD5_AMBER_0603

HT-191UD5_AMBER_0603

2

2

2

013/01/22 2014/01/21

013/01/22 2014/01/21

013/01/22 2014/01/21

5

1

8

8

26

26

D

D

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

R

19

19

R

1 2

390_0402_5%

390_0402_5%

R

R

21

21

1 2

510_0402_5%

510_0402_5%

R

R

1

390_0402_5%

390_0402_5%

R

R

1 2

510_0402_5%

510_0402_5%

D

D

D

eciphered Date

eciphered Date

eciphered Date

B

ATT_FULL_LED# <34>

B

ATT_CHG_LOW_LED# <34>

18

18

2

22

22

P

WR_SUSP_LED# <34>

W

6

L_BT_LED# <34>

C

ompal Electronics, Inc.

T

T

Title

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

7

D

D

D

ebug/KB

ebug/KB

ebug/KB

L

L

L

A-9869P

A-9869P

A-9869P

M

M

M

onday, February 04, 2013

onday, February 04, 2013

onday, February 04, 2013

3

3

o

3

o

o

f

5 50

f

5 50

f

5 50

8

0

0

0

.3

.3

.3

5

+

3VL

2

R

R

397

For debug

S

S

W5

D D

P

lace on TOP

T

ouchpad Connector

TP

TP

J

C C

J

15

5

1

13

3

1

11

1

1

9

9

7

7

5

5

3

3

1

1

@

@

HB_A060 877-SAVR01

HB_A060 877-SAVR01

1
1
1
1

W5

1

3

16

6

14

4

12

2

10

0

8

8

6

6

4

4

2

2

2

4

G

G

G

G

NTC017-D A1J-D160T_4P

NTC017-D A1J-D160T_4P

5

6

+

3VS

T

P_FCH_S DATA1

T

P_FCH_S CLK1

T

P_DATA <34>

T

P_CLK <34>

397

100K_04 02_5%

100K_04 02_5%

1

O

N/OFFBTN #

4

O

N/OFFBTN # <34 >

4.7K_040 2_5%

4.7K_040 2_5%

T

P_FCH_S CLK1

T

P_FCH_S DATA1

C

onn.

J

J

PWR

PWR

112
334
556
778

ACES_50 611-0040N-001

ACES_50 611-0040N-001

@

@

3

2
4
6
8

O

N/OFFBTN #

+

5VS

2

S

crew Hole

CPU

1

1

H

H

1

H_4P2

H_4P2

@

@

H

H

2

2

H_4P6

H_4P6

@

@

1

H

H

3

3

1

H_4P2x4P6

H_4P2x4P6

@

@

1

V

GA

H

H

H

H

5

H_3P3

H_3P3

@

@

5

H_3P3

H_3P3

@

@

1

4

4

1

FCH

H

H

8

8

1

H_3P0

H_3P0

@

@

PTH

7

7

H

H

H

H

18

18

+

3VS

+

2

299

298

298

R

R

299

R

R

4.7K_040 2_5%

4.7K_040 2_5%

1

1 2

DMN66D0 LDW-7 2N_SO T363-6

DMN66D0 LDW-7 2N_SO T363-6

300 0_0402_ 5%

300 0_0402_ 5%

R

R

R

R

301 0_0402_ 5%

301 0_0402_ 5%

3VS

2

61

5

Q

Q

5331A

5331A

4

3

Q

Q

5331B

DMN66D0 LDW-7 2N_SO T363-6

DMN66D0 LDW-7 2N_SO T363-6

1 2

1 2

5331B

@

@

@

@

F

CH_SCLK 1 <24>

F

CH_SDAT A1 <24>

PCB Fedical Mark PAD

@

@

10

10

H

H

H_3P0

H_3P0

@

@

1

H

H

29

29

H_4P0

H_4P0

@

@

1

D1

D1

F

F

F

F

D2

D2

@

@

1

1

1

1

H_3P0

H_3P0

@

@

H_3P3

H_3P3

@

@

F

F

@

@

11

11

H

H

H

H

21

21

D3

D3

@

@

1

1

1

F

F

D4

D4

1

H_3P0

H_3P0

@

@

H_7P0

H_7P0

@

@

12

12

13

13

H

H

H

H

H_3P0

H_3P0

@

@

1

H_3P0

H_3P0

@

@

1

H

H

H

H

15

15

17

17

H_3P2

H_3P2

H_3P0

H_3P0

@

@

@

@

1

1

NPTH

22

22

H

H

H_3P2N

H_3P2N

@

@

1

H

H

9

9

1

H_3P2x3P7 N

H_3P2x3P7 N

@

@

H

H

16

16

H_3P2N

H_3P2N

@

@

1

I

SPD

ZZ

ZZ

Z

U

U

APU

5745R3@

APU

5745R3@

5745R1@

B B

SA00006KH00

APU

5545R1@

APU

5545R1@

U

U

A10-5745 M-AM5745SIE44HL

A10-5745 M-AM5745SIE44HL

APU

5545R3@

APU

5545R3@

U

U

SA00006KE00

A8-5545M -AM5545SHE44H L

A8-5545M -AM5545SHE44H L

APU

5345R1@

APU

5345R1@

U

U

A8-5545M -AM5545SHE44H L

A8-5545M -AM5545SHE44H L

U

U

APU

5345R3@

APU

5345R3@

U

U

APU1

5357R1@

APU1

5357R1@

SA00006KK00

A6-5357M -AM5357DFE24H L

A6-5357M -AM5357DFE24H L

APU3

5145R1@

U

U

APU3

5145R1@

SA00006KC00

A4-5145M -AM5145SHE23H L

A4-5145M -AM5145SHE23H L

U

U

APU2

5357R3@

APU2

5357R3@

A6-5357M -AM5357DFE24H L

A6-5357M -AM5357DFE24H L

APU4

5145R3@

APU4

5145R3@

U

U

A4-5145M -AM5145SHE23H L

A4-5145M -AM5145SHE23H L

Z

D

A8000XI000

PCB LA-98 69P

PCB LA-98 69P

U

U

1

BOLTONR 3@

1

BOLTONR 3@

218-0755 097 A14 BOLTON -M3

218-0755 097 A14 BOLTON -M3

JP1

45@

JP1

45@

P

P

CONN SET 0CL DCJACK-MB 32 2215-3

CONN SET 0CL DCJACK-MB 32 2215-3

SA00006KD00

A6-5345M -AM5345SHE24H L

A6-5345M -AM5345SHE24H L

APU

5757R1@

APU

5757R1@

U

U

A6-5345M -AM5345SHE24H L

A6-5345M -AM5345SHE24H L

U

U

APU

5757R3@

APU

5757R3@

SA00006KI00

A A

A10-5757 M-AM5757DFE44 HL

A10-5757 M-AM5757DFE44 HL

APU

5557R1@

APU

5557R1@

U

U

SA00006KJ00

A8-5557M -AM5557DFE44H L

A8-5557M -AM5557DFE44H L

5

A10-5757 M-AM5757DFE44 HL

A10-5757 M-AM5757DFE44 HL

U

U

APU

5557R3@

APU

5557R3@

A8-5557M -AM5557DFE44H L

A8-5557M -AM5557DFE44H L

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

2

2

2

013/01/2 2 2014/01/ 21

013/01/2 2 2014/01/ 21

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

013/01/2 2 2014/01/ 21

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

Lid SW

B

+

1

475

475
C

C

2

0.1U_0402_25V6

0.1U_0402_25V6

C

lose to PR816

2

+

3VL

1

C

C

453

453

0.1U_040 2_25V6

0.1U_040 2_25V6

2

B

+

1

2

10U_0805_25V6K

10U_0805_25V6K

21

21

U

U
APX9132 ATI-TRL_SOT23-3

APX9132 ATI-TRL_SOT23-3

2

DD

V

833

833
C

C

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

Date: Sheet

Date: Sheet

Date: Sheet

OUT

V

ND
G

1

10P_040 2_50V8J

10P_040 2_50V8J

M

M

M

onday, February 04, 2013

onday, February 04, 2013

onday, February 04, 2013

3

1

452

452

C

C

2

T

T

T

P/HDD LED/Screw

P/HDD LED/Screw

P/HDD LED/Screw

L

L

L

A-9869P

A-9869P

A-9869P

L

ID_SW# <34>

1

3

3

3

6 50

6 50

6 50

0

0

0

.3

.3

.3

o

o

o

f

f

f

A

+

5VALW TO +5VS
+3VALW TO +3VS
Load switch

1 1

+

3VL

2 2

F

CH_PWR_EN<34>

R

R

10K_0402_5%

10K_0402_5%

885@

885@

5546

5546

1 2

12

5529

5529

R

R
100K_0402_5%

100K_0402_5%

9012@

9012@

1U_0402_6.3V6K

1U_0402_6.3V6K

R

R

5545

5545

10K_0402_5%

10K_0402_5%

2

G

G

+

C

C

5VALW

+

5VALW

45

45

1

@

@

2

+

1 2

F

CH_PWR_EN#

1

D

D

25

25

Q

Q
2N7002KW_SOT323-3

2N7002KW_SOT323-3

S

S

3

V

IN 5V and 3.3V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm

S

USP#

S

USP#

F

CH_PWR_EN# <26>

3VALW

1

C

@C44

@

1U_0402_6.3V6K

1U_0402_6.3V6K

2

+

5VALW

44

B

2

2

U

U

1

OUT1

IN1

V

V

2

OUT1

IN1

V

V

3

N1

O

4

5

6
7

C

BIAS

V

G

N2

C

O

IN2

OUT2

V

V

IN2

OUT2

V

V

PAD

G

TPS22966DPUR_SON14_2X3

TPS22966DPUR_SON14_2X3

SA00004MM00

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

C

+

5VS

P

P

J3

J5

J5

P

P

1 2

PAD-OPEN 4x4m

PAD-OPEN 4x4m

@

@

100K_0402_5%

100K_0402_5%

S

YSON#

J3

1 2

PAD-OPEN 4x4m

PAD-OPEN 4x4m

@

@

+

5VALW

432

432

R

R

1 2

6

2

1

1

46

@C46

@

C

0.1U_0402_25V6

0.1U_0402_25V6

2

+

3VS

1

53

@C53

@

C

0.1U_0402_25V6

0.1U_0402_25V6

2

Q

Q

22A

22A

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

+

1.2VS

+

100K_0402_5%

100K_0402_5%

V

R_ON#

2

5VALW

2

448

448

R

R

1

6

1

Q

Q

13A

13A

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

479

479

R

R
470_0805_5%

470_0805_5%

1 2

3

Q

Q

13B

13B

5

4

V

R_ON<34,44,45>

14

+

5VS_LS

13

12

T1

11

ND

10

T2

9
8

15

C

C

C

C

+

3VS_LS

+

1.5V

1 2

3

22B

22B

Q

Q

4

S

20 180P_0402_50V8J

20 180P_0402_50V8J

1 2

21 330P_0402_50V7K

21 330P_0402_50V7K

2

1

R

R

478

478

470_0805_5%

470_0805_5%

5

YSON<34,42>

D

+

0.75VS

R

R

477

477

470_0805_5%

470_0805_5%

1 2

34

6B

6B

Q

Q

5

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

E

+

5VALW

422

422

R

R
100K_0402_5%

100K_0402_5%

1 2

S

S

USP<9>

S

USP

S

USP#<34,42>

USP

6

6A

6A

Q

Q

2

S

USP#

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

1

+

5VS_ODD

3 3

V

gs=10V,Id=14.5A,Rds=6mohm

4 4

+

1.1VALW

.7U_0805_10V4Z

.7U_0805_10V4Z
4

4

A

1

2

+

1.1VALW to +1.1VS

+

1.1VS

1

476

44

44

Q

Q

8

D

7

D

6

D

5

D

FDS6676AS_SO8

FDS6676AS_SO8

474

474

C

C

476

C

C

1

S

2

S

2

3

S

4

G

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

416

477

477

C

C

416

R

R
820K_0402_5%

820K_0402_5%

2

2

.1U_0402_25V6

.1U_0402_25V6
0

0

4.7U_0805_10V4Z

4.7U_0805_10V4Z

472

472

C

C

1 2

R

R

415

415

220K_0402_5%

220K_0402_5%

61

Q

Q

23A

23A

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

2

1

2

B

+

2

200

200

C

C

0.1U_0402_16V4Z

0.1U_0402_16V4Z

@

@

1

N
+3VS ramp up

1 2

@

@

R

R

385 0_0402_5%

385 0_0402_5%

eed to delay after

+

1.1VS

R

R

417

417

470_0805_5%

470_0805_5%

1 2
34

Q

Q

23B

23B

5

S

USP

S

USP

B

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

C

457

457

R

R

470_0805_5%

470_0805_5%

ZP@

ZP@

1 2
34

53B

53B

Q

Q

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

5

ZP@

ZP@

O

O

DD_PWR#

DD_PWR<25>

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONFI DENTIAL

HIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONFI DENTIAL

HIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONFI DENTIAL

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

+

5VS TO +5VS_ODD

+

5VS

ZP@

ZP@

441

441

R

R
100K_0402_5%

100K_0402_5%

1 2

1 2

O

DD_PWR#

47K_0402_5%

47K_0402_5%

61

Q

Q

53A

53A

2

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

ZP@

ZP@

2

2

2

013/01/22 2014/01/21

013/01/22 2014/01/21

013/01/22 2014/01/21

ZP@

ZP@

R

R

440

440

2

471

471

C

C

0.1U_0402_16V7K

0.1U_0402_16V7K

ZP@

ZP@

1

2

217

217

C

C

0.01U_0402_25V7K

0.01U_0402_25V7K

1

ZP@

ZP@

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

D

+

5VS

V

gs=-4.5V,Id=3A,Rds<97mohm

2

S

S

3

45

45

Q

Q

G

G

2

AO3413_SOT23

AO3413_SOT23

ZP@

ZP@

2

1

D

D

1

1

P

P

J28

J28

JUMP_43X79

JUMP_43X79

@

@

+

5VS_ODD

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

Title

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

D

D

D

C-DC INTERFACE

C-DC INTERFACE

C-DC INTERFACE

L

L

L

A-9869P

A-9869P

A-9869P

E

3

3

3

o

o

o

f

7 50Monday, February 04, 2013

f

7 50Monday, February 04, 2013

f

7 50Monday, February 04, 2013

0

0

0

.3

.3

.3

A

E

MI Part (47.1)

O

ther component (37.1)

A

51 need add fuse

1 1

@

@

P

P

JP1

JP1

1

1

2

2

3

3

4

4

ACES_50299-00401-001

ACES_50299-00401-001

P

P

F1

F1

21

7A_32V_S1206-H-7.0A

7A_32V_S1206-H-7.0A

D

C_IN_S1

12

EMI@

EMI@

P

P

C102

C102

1000P_0603_50V7K

1000P_0603_50V7K

1

2

EMI@

EMI@

P

P

L1

L1

HCB2012KF-121T50_0805

HCB2012KF-121T50_0805

1 2

EMI@

EMI@

P

P

L3

L3

HCB2012KF-121T50_0805

HCB2012KF-121T50_0805

P

P

100P_0603_50V8

100P_0603_50V8

1

C103

C103

EMI@

EMI@

2

B

1

P

P

C101

C101

100P_0603_50V8

100P_0603_50V8

2

EMI@

EMI@

V

IN

12

EMI@

EMI@

P

P

C104

C104

1000P_0603_50V7K

1000P_0603_50V7K

C

D

2 2

P

P

BJ101 @

BJ101 @

- +

ML1220T13RE

ML1220T13RE

3 3

4 4

For ML1220 RTC (38.2)

P

P

R102

12

+

RTC

P

P

R101

R101

560_0603_5%

560_0603_5%

1 2

560_0603_5%

560_0603_5%

1 2

+

RTC_R

R102

+

RTCBATT

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

011/06/24 2012/07/12

011/06/24 2012/07/12

011/06/24 2012/07/12

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

C

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

Title

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

D

D

D

CIN/PRECHARGE

CIN/PRECHARGE

CIN/PRECHARGE

L

L

L

A-9869P

A-9869P

A-9869P

D

o

o

o

f

38 49

f

38 49

f

38 49

0

0

0

.1

.1

.1

A

0

.1

0

.1

0

.1

Other component (37.1)

@

@

ACES_50299-01001-W01

ACES_50299-01001-W01

1

1

2

2

3

3

4

4

5

5

6

6

7

7

1 1

2 2

8

8

9

9

10

1

0

P

P

JP2

JP2

B

ATT_S1

E

C_SMCA

P

P

R20

R20

100_0402_1%

100_0402_1%

B

ATT_P4

B

ATT_P5

E

C_SMDA

1 2

P

P

F2

F2

10A_125V_TR2/6125FF10-R

10A_125V_TR2/6125FF10-R

2

P

P

R21

R21

100_0402_1%

100_0402_1%

1

21

12

P

P

R14

R14

1K_0402_1%

1K_0402_1%

P

P

R16

R16

6.49K_0402_1%

6.49K_0402_1%

P

P

R19

R19

1 2

1K_0402_1%

1K_0402_1%

12

E

C_SMB_DA1 <31,34,40,9>

E

C_SMB_CK1 <31,34,40,9>

V

MB

+

3VL

B

ATT_PRES <34>

B

HCB2012KF-121T50_0805

HCB2012KF-121T50_0805

1 2

HCB2012KF-121T50_0805

HCB2012KF-121T50_0805

1 2

12

EMI@

EMI@

P

P

C7

C7

1000P_0402_50V7K

1000P_0402_50V7K

EMI@

EMI@

P

P

L4

L4

EMI@

EMI@

P

P

L5

L5

EMI Part (47.1)

B

ATT+

1

P

C8

EMI@PC8

EMI@

0.01U_0402_25V7K

0.01U_0402_25V7K

2

C

O

TP (39.7)

P

ROCHOT_IN<34>

A

DP_I<34,40>

R1

R1
P

P

1 2

1K_0402_1%

P

R2

@PR2

@

0_0402_5%

0_0402_5%

1 2

1K_0402_1%

V

CIN0_PH<34>

2

R3

R3
P

P

1

20K_0402_1%

20K_0402_1%

D

P

R5

@PR5

@

0_0402_5%

0_0402_5%

1

12

P

C11

@PC11

@

0.1U_0402_10V7K

0.1U_0402_10V7K

+

3VL

12

R4

R4
P

P

12.1K_0402_1%

12.1K_0402_1%

2

1

H1

H1
P

P

2

100K_0402_1%_TSM0B104F4251RZ

100K_0402_1%_TSM0B104F4251RZ

3 3

4 4

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

2

2

2

011/06/24 2012/07/12

011/06/24 2012/07/12

011/06/24 2012/07/12

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

C

eciphered Date

eciphered Date

eciphered Date

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

B

B

B

ATTERY CONN / OTP

ATTERY CONN / OTP

ATTERY CONN / OTP

L

L

L

A-9869P

A-9869P

A-9869P

D

o

o

o

f

39 49

f

39 49

f

39 49

A

B

C

D

for reverse input protection

C

1

D

D

2

P

P

Q209

Q209

G

G

SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

S

S

3

R226

R226

P

P

P

R225

R225

1 2

1M_0402_5%

1 1

2 2

3 3

1M_0402_5%

TPCA 8057

TPCA 8057

V

IN

P

P

Q203

Q203

5

12

4

C230

C230
P

P

B

2200P_0402_50V7K

2200P_0402_50V7K

1 2

3M_0402_5%

3M_0402_5%

P

1

1
2
3

Q24725_ACDRV_1

P

Q205

Q205

P

SI7716ADN-T1-GE3_POWERPAK8-5

SI7716ADN-T1-GE3_POWERPAK8-5

1
2
3

12

C231

C231
P

P

0.1U_0402_25V6

0.1U_0402_25V6

1

1

R235

R235

R234

R234

P

P

P

P

2

2

4.12K_0603_1%

4.12K_0603_1%

4.12K_0603_1%

4.12K_0603_1%

P

4

P

2

5

+

3VL

A

CIN<34>

V

IN

1

2

0.1U_0402_25V6

0.1U_0402_25V6

1

C238

C238
P

P

2

0.1U_0402_25V6

0.1U_0402_25V6

B
Q24725_ACP

B

Q24725_CMSRC

B

Q24725_ACDRV

1 2

P

P

R239 10K_0402_1%

R239 10K_0402_1%

Vin Dectector

Min. Typ Max.
H-->L 17.23V
L--> H 17.63V

ILIM and external DPM

3.97A

4 4

A

harger controller (40.1), Support component (40.2)

E

R211

R211

P

P

0.01_1206_1%

0.01_1206_1%

1 2

C236

C236

P

P

B
Q24725_ACN

12

MI Part (47.1)

B

+

1UH_NRS4018T1R0NDGJ_3.2A_30%

4

3

12

C235

C235
P

P

0.1U_0402_25V6

0.1U_0402_25V6

P

P

1

1U_0603_25V6K

1U_0603_25V6K

21

1

2

3

4

5

12

R244

R244
P

P

422K_0402_1%

422K_0402_1%

1

R245

R245

C244

C244

P

P

P

P

2

0.1U_0402_25V6

0.1U_0402_25V6

66.5K_0402_1%

66.5K_0402_1%

100P_0402_50V8J

100P_0402_50V8J

1UH_NRS4018T1R0NDGJ_3.2A_30%

V

IN

2

3

P

P

D230

D230

BAS40CW_SOT323-3

BAS40CW_SOT323-3

0.047U_0402_25V7K

0.047U_0402_25V7K

1
12

P

P

1

R228

R228
P

P

10_1206_1%

10_1206_1%

C239

C239

Q24725_VCC

2

B

Q24725_LX
B

19

20

P

P

U200

U200

CC
V

P

AD

HASE

A

A

C

A

A

2

B

P

CN

CP

MSRC

CDRV

COK

CDET

OUT

A

I

6

7

Q24725_ACDET
B

C245

C245

P

P

1

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

C237

C237

2

R229

R229
P

P

H_CHG
D

18

IDRV
H

DA
S

8

@PR246

@

0_0402_5%

0_0402_5%

1

P

P

1 2

12

2.2_0603_5%

2.2_0603_5%

Q24725_BST
B

17

TST
B

CL
S

9

R246

P

2

L201

L201

12

Q24725_REGN
B

16

B

10

12

EGN
R

L

ODRV

ATDRV

LIM

I

B

12

C211

C211
P

EMI@

EMI@

D231

D231

P

P
RB751V-40_SOD323-2

RB751V-40_SOD323-2

1U_0603_25V6K

1U_0603_25V6K

G

ND

S

RP

S

RN

BQ24725RGRR_QFN20_3P5X3P5

BQ24725RGRR_QFN20_3P5X3P5

Q24725_ILIM

R242

R242
P

P

100K_0402_1%

100K_0402_1%

12

0.1U_0402_10V7K

0.1U_0402_10V7K

P

10U_0805_25V6K

10U_0805_25V6K

12

12

C213

C213

C214

C214

P

P

P

P

10U_0805_25V6K

10U_0805_25V6K

2200P_0402_25V7K

2200P_0402_25V7K

@EMI@

@EMI@

P

P

R210

R210

0_0603_5%

0_0603_5%

1

D

H_CHG

C205

C205

P

P

1 2

15

D

L_CHG

14

R236

R236

P

P

10_0603_1%

10_0603_1%

1 2

13

S

RP

R237

R237

P

P

6.8_0603_5%

6.8_0603_5%

1 2

12

S

RN

11

B

Q24725_BATDRV

1 2

R241

R241

P

P

357K_0402_1%

357K_0402_1%

1

C243

C243
P

P

2

0.01U_0402_25V7K

0.01U_0402_25V7K

E

C_SMB_CK1 <31,34,39,9>

E

C_SMB_DA1 <31,34,39,9>

A

DP_I <34,39>

P

C246

@PC246

@

P

lease locate th e RC
Near EC chip
2011-02-22

2

2

2

011/06/24 2012/07/12

011/06/24 2012/07/12

011/06/24 2012/07/12

4

2

C

SOP1

C

SON1

0.1U_0603_16V7K

0.1U_0603_16V7K

+

3VALW

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

5

5

4

3

12

C242

C242

P

P

D

D

D

eciphered Date

eciphered Date

eciphered Date

B

Q24725_BATDRV

P

P

Q201

Q201

AON7408L

AON7408L

L202

L202

P

123

2

B

Q24725_LX

AON7406L

AON7406L

1

P

P

P

4.7UH_ETQP3W4R7WF N_5.5A_20%

4.7UH_ETQP3W4R7WF N_5.5A_20%

1 2

1

Q202

Q202

R206

R206
P

P

4.7_1206_5%

4.7_1206_5%

2

EMI@

EMI@
@

@

12

C206

C206

P

P

680P_0603_50V8J

680P_0603_50V8J

@EMI@

@EMI@

EMI Part (35.33)

309K_0402_1%

309K_0402_1%

47K_0402_1%

47K_0402_1%

For A51 ADP_V function

C

1 2

R233

R233

P

P

4.12K_0603_1%

4.12K_0603_1%

C

HG

SOP1
C

1

2

V

IN

12

R247

R247

P

P

12

R249

R249

P

P

S TR SI7716ADN

S TR SI7716ADN
P

P

Q207

Q207

5

B

Q24725_BATDRV_1

R227

R227

P

P

0.01_1206_1%

0.01_1206_1%

1

2

C240

C240
P

P

0.1U_0402_25V6

0.1U_0402_25V6

1
2
3

4

1

0.1U_0402_10V7K

0.1U_0402_10V7K

2

T

T

T

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

4

3

SON1
C

12

10K_0402_1%

10K_0402_1%

1

P

C247

@PC247

@

itle

itle

itle

ustom

ustom

ustom

12

C234

C234
P

P

0.01U_0402_50V7K

0.01U_0402_50V7K

1

12

C221

C221

C222

C222
P

P

P

P

2

@

@

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6

0.1U_0402_25V6

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

C

C

C

HARGER

HARGER

HARGER

P

P

R248

R248

C241

C241
P

P

10U_0805_25V6K

10U_0805_25V6K

A

DP_V <34>

12

C223

C223
P

P

10U_0805_25V6K

10U_0805_25V6K

B

ATT+

o

o

o

f

40 49

f

40 49

f

40 49

D

0

0

0

.1

.1

.1

A

3

/5VALW controller (35.1), Support component (35.2)

5

1 1

E

MI Part (47.1)

B

+

EMI@

EMI@

P

P

L331

L331

HCB2012KF-121T50_0805

HCB2012KF-121T50_0805

1 2

2 2

+

3VALWP

@EMI@

@EMI@

C339

C339
P

P

3

/5V_B+

2200P_0402_50V7K

2200P_0402_50V7K

12

12

C340

C340
P

P

10U_0805_25V6K

10U_0805_25V6K

P

P

L332

L332

4.7UH_ETQP3W4R7W FN_5.5A_20%

4.7UH_ETQP3W4R7W FN_5.5A_20%

1

1

+

+

C354

C354
P

P

2

150U_D2_6.3VY_R15M

150U_D2_6.3VY_R15M

2

12

R336

R336
P

P

4.7_1206_5%

4.7_1206_5%

@EMI@

@EMI@

NUB_3V
S

1

C336

C336
P

P

2

680P_0603_50V8J

680P_0603_50V8J

@EMI@

@EMI@

5

Q331

Q331
P

P

AON7408L

AON7408L

2

3

1

5

123

V_3.3V controller (35.1), Support component (35.2)

4

P

P

C335

C335

0.1U_0402_10V7K

0.1U_0402_10V7K

1 2

4

AON7406L

AON7406L
P

P

Q332

Q332

EMI Part (35.33)

3 3

3

.3V

Peak Current 8A

V

OCP current 10A
Delta I=1.160A ,ripple=1.160 x17m=19.27mV
FSW=455kHz
DCR 35mohm +/-15%
TYP MAX
H/S Rds(on) :27mohm , 34mohm
L/S Rds(on) :19mohm , 23.5mohm

B

R350

R350

P

P

30K_0402_1%

30K_0402_1%

R330

R330

P

P

14K_0402_1%

14K_0402_1%

2

1

R331

R331

P

P

20K_0402_1%

20K_0402_1%

1 2

P

OK<34>

R333

R333

P

P

0_0402_5%

0_0402_5%

1 2

B

ST1_3V

3

/5V_B+

E

C_ON<34>

S_ON<34>

V

L

1

R335

R335
P

P

2

B

ST_3V

U

G_3V

L

X_3V

L

G_3V

P

P

499K_0402_1%

499K_0402_1%

1 2

12

C360

C360
P

P

0.1U_0603_25V7K

0.1U_0603_25V7K

@PR341

@

P

0_0402_5%

0_0402_5%

1 2

F

B_3V

100K_0402_1%

100K_0402_1%

6

7

8

9

10

R334

R334

R340

R340

P

P

2.2K_0402_1%

2.2K_0402_1%

1

R341

1

12

1

R342

R342

R357

R357

R337

R337
P

P

P

P

P

P

2

2

56K_0402_1%

56K_0402_1%

174K_0402_1%

174K_0402_1%

210K_0402_1%

210K_0402_1%

2

3

4

5

B2

ON

F

GOOD

P

OOT2

B

GATE2

U

HASE2

P

GATE2

L

11

1

R338

R338
P

P

2

100K_0402_1%

100K_0402_1%

2

T

NTRIP1

NTRIP2
E

E

IN

NLDO

ECFB

DO5

S

V

12

12

C342

C342
P

P

1U_0603_10V6K

1U_0603_10V6K

12

C343

C343
P

P

@

@

L

E

13

14

15

V

L

12

E

NLDO<35>

4.7U_0603_10V6K

4.7U_0603_10V6K

R332

R332
P

P

@

@

1 2

100K_0402_5%

100K_0402_5%

4.7U_0805_25V6-K

4.7U_0805_25V6-K

1

R351

R351

P

P

19.1K_0402_1%

19.1K_0402_1%

1 2

F

B_5V

1

B1

21

F

AD

P

20

YP1

B

19

OOT1

B

18

GATE1

U

17

HASE1

P

16

GATE1

L

DO3
L

PU330

PU330

T8243AZQW_WQFN20_3X 3

T8243AZQW_WQFN20_3X 3

R

R

12

C344

C344

P

P

+

3VLP

(

100mA,20mils ,Via NO.= 1)

B

U

L

L

ST_5V

G_5V

X_5V

G_5V

2

0_0402_5%

0_0402_5%

1 2

+

3VLP

C341

C341

P

P

4.7U_0603_10V6K

4.7U_0603_10V6K

2

JUMP_43X39

JUMP_43X39

C

R355

R355

P

P

@PJ332

@

2

D

3

/5V_B+

12

C361

C361
P

0.1U_0402_10V7K

0.1U_0402_10V7K

B

ST1_5V

P

10U_0805_25V6K

10U_0805_25V6K

P

P

C355

C355

2

1

FDMC7692S_MLP8-5

FDMC7692S_MLP8-5

P

P

Q352

Q352

P

P

Q351

Q351

AON7408L

AON7408L

4

1

3 5

2

P

P

L352

1

2

NUB_5V
S

12

L352

1 2

R356

R356
P

P

4.7_1206_5%

4.7_1206_5%

@EMI@

@EMI@

C356

C356
P

P

680P_0603_50V8J

680P_0603_50V8J

@EMI@

@EMI@

EMI Part (47.1)

1

+

+

C353

C353
P

P

2

150U_D2_6.3VY_R15M

150U_D2_6.3VY_R15M

+

5VALWP

2.2UH_MMD-06CZ-2R2M-V1_8A_20%

2.2UH_MMD-06CZ-2R2M-V1_8A_20%

5

4

123

5V
Peak Current 10A
OCP current 12A
FSW=390kHz
Delta I=2.791A,ripple=2.791*15m=41.865mV
DCR 18~20mohm
TYP MAX
H/S Rds(on) ::27mohm , 34mohm
L/S Rds(on) :10.8mohm , 13.6mohm

J332

P

1

1

+

3VL

+

3VALWP

(

8A,160mils ,Via NO.= 16)

+

5VALWP

(12A,240mils ,Via NO.= 24)

P

@PJ331

@

112

JUMP_43X118

JUMP_43X118

@PJ351

@

112

JUMP_43X118

JUMP_43X118

J331

P

J351

2

2

+

3VALW

+

5VALW

4 4

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

B

2

2

2

011/06/24 2012/07/12

011/06/24 2012/07/12

011/06/24 2012/07/12

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

C

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

3

3

3

VALW/5VALW

VALW/5VALW

VALW/5VALW

D

o

o

o

f

41 49

f

41 49

f

41 49

0

0

0

.1

.1

.1

DDR controller (35.3), Support component (35.4)

EMI@

EMI@

P

P

L151

B

+

L151

HCB2012KF-121T50_0805

HCB2012KF-121T50_0805

2

1

1.5V_B+

EMI Part (47.1)

B

ST_1.5V-1

P

P

R155

R155

0_0603_5%

0_0603_5%

1 2

A

BST_1.5V

+

1.5V

P

P

R158

R158

17.4K_0402_1%

17.4K_0402_1%

1 2

P

P

C162

C162

1U_0603_10V6K

1U_0603_10V6K

1 2

V

N_1.5V

S

DD_1.5V

USP#<34,37>

DH_1.5V

CS_1.5V

+

5VALW

1.5V_B+

15

L

GATE

14

P

GND

13

C

S

12

V

DDP

11

V

DD

R161

R161

P

P

887K_0402_1%

887K_0402_1%

1 2

16

18

17

19

OOT

GATE

HASE

B

P

U

RT8207MZQW_W QFN20_3X3

RT8207MZQW_W QFN20_3X3

5

GOOD

ON
T

S

P

8

7

9

10

TON_1.5V

P

P

R164

R164

0_0402_5%

0_0402_5%

N_0.75VSP

12

E

12

20

P

P

U150

U150

TT
V

P

AD
LDOIN
V

V

TTGND

V

TTSNS

G

ND

V

TTREF

V

DDQ

3

B

S

F

6

F

B_1.5V

@

@

P

P

C167

C167

0.1U_0402_10V7K

0.1U_0402_10V7K

21

1

2

3

4

5

V

TTREF_1.5V

P

P
10K_0402_1%

10K_0402_1%

1 2

P

P

R160

R160

10.2K_0402_1%

10.2K_0402_1%

2

R162

R162

1

+

1.5VP

12

1

C160

C160

C159

C159
P

P

P

P

2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

+

1.5VP

12

@EMI@

@EMI@

C152

C152
P

P

2200P_0402_50V7K

2200P_0402_50V7K

P

P

L152

1UH_VMPI0703AR-1R0M-Z01_11A_20%

+

1.5VP

1 1

@PJ750

@

+

0.75VSP

(0.5A,40mils ,Via NO.= 1)

2

JUMP_43X79

JUMP_43X79

1UH_VMPI0703AR-1R0M-Z01_11A_20%

1

+

+

2

J750

P

112

L152

12

12

C157

C157
P

P

330U_D2_2V_Y

330U_D2_2V_Y

SNUB_+1.5VP

12

+

0.75VS

12

C154

C154
P

P

10U_0805_25V6K

10U_0805_25V6K

Q151

Q151
P

P

AON7408L

AON7408L

1

@EMI@

@EMI@

R156

R156

P

P

4.7_1206_5%

4.7_1206_5%

@EMI@

@EMI@

C156

C156

P

P

680P_0402_50V7K

680P_0402_50V7K

+

1.5VP

(12A, 480mils ,Via NO.= 24)
OCP=13.8A

Q152

Q152
P

P

FDMC7692S_MLP8-5

FDMC7692S_MLP8-5

1

S

YSON<34,37>

@

@

2

2

JUMP_43X118

JUMP_43X118

@

@

2

2

JUMP_43X118

JUMP_43X118

P

P

P

P

2

2

J151

J151

1

J152

J152

1

2

C155

C155
P

P

5

3

5

3

1

0.1U_0603_25V7K

0.1U_0603_25V7K

4

P

P

R159

R159

5.1_0603_5%

5.1_0603_5%

+

5VALW

1 2

1U_0603_10V6K

1U_0603_10V6K

1

0.1U_0402_10V7K

0.1U_0402_10V7K

2

4

P

R163

@PR163

@

0_0402_5%

0_0402_5%

1 2

1

1

+

1.5V

P

P

P

C166

@PC166

@

C164

C164

SW_1.5V

DL_1.5V

12

E

1

C163

C163

P

P

0.033U_0402_16V7K

0.033U_0402_16V7K

2

+

0.75VSP

1.5V
Peak Current 12A
OCP current 13.34A
FSW=300kHz
DCR 8.3 ~ 10mohm
TYP MAX
H/S Rds(on) :27mohm , 34mohm
L/S Rds(on) :10.8mohm , 13.6mohm

STATE S3 S5 1.5VP VTT_REFP 0.75VSP

S0

S3

S4/S5

Hi Hi

HiLo

Lo Lo

On

On

Off
(Discharge)

On

On

Off
(Discharge)

On

Off
(Hi-Z)

Off
(Discharge)

Note: S3 - sleep ; S5 - power off

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

A

2

2

2

011/06/24 2012/07/12

011/06/24 2012/07/12

011/06/24 2012/07/12

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

Title

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

1

1

1

.5VP/0.75VSP/1.8VSP

.5VP/0.75VSP/1.8VSP

.5VP/0.75VSP/1.8VSP

L

L

L

A-9869P

A-9869P

A-9869P

o

o

o

f

42 49

f

42 49

f

42 49

0

0

0

.1

.1

.1

A

1

.8V controller (35.15), Support component (35.16)

1 1

+

3VS

12

C458

C458
P

P

22U_0603_6.3V6M

12

+

1.8_EN

22U_0603_6.3V6M

R452

R452

P

P

220K_0402_1%

220K_0402_1%

V

GA_PWRGD<14,24,46>

@

@

P

P

J451

J451

2

1

2

+

2 2

1.8VGSP

1

JUMP_43X79

JUMP_43X79

(

0.5A,20mils ,Via NO.=1)

+

1.8VGS

1 2

P

P

C453

C453

0.1U_0402_16V7K

0.1U_0402_16V7K

B

N

ote:Iload(max)=3A

U450

U450

P

P

4

N

I

5

G

P

6

B

F

12

P

R454

@PR454

@

22K_0402_5%

22K_0402_5%

1UH_NRS4018T1R0NDGJ _3.2A_30%

1UH_NRS4018T1R0NDGJ _3.2A_30%

3

X

L

2

ND

G

1

N

E

SY8032ABC_SOT23-6

SY8032ABC_SOT23-6

P

C456

@EMI@PC456

@EMI@

680P_0603_50V7K

680P_0603_50V7K

1

12

P

P

4.7_1206_5%

4.7_1206_5%

FB=0.6V

S
NB_1.8V

12

P

P

L451

L451

@EMI@

@EMI@

R456

R456

100K_0402_1%

100K_0402_1%

P

P

49.9K_0402_1%

49.9K_0402_1%

P

P

R453

R453

2

R451

R451

C

+

12

1

12

C450

C450
P

P

22P_0402_50V8J

22P_0402_50V8J

12

C452

C452
P

P

22U_0603_6.3V6M

22U_0603_6.3V6M

1.8VGSP

12

C451

C451
P

P

22U_0603_6.3V6M

22U_0603_6.3V6M

1.8V
Peak Current 0.5A
OCP current 3.5A

D

FSW=800kHz

2

H/S Rds(on) :100mohm ,
L/S Rds(on) :80mohm ,

1.1V controller (35.27), Support component (35.28)

@

@

P

P

J401

J401

2

1

2

+

1.1VALWP

3 3

1

JUMP_43X79

JUMP_43X79

(5.3A,220mils ,Via NO.=10)

1.1V
Peak Current 5.3A
OCP current 12A
FSW=800kHz

H/S Rds(on) :22mohm ,
L/S Rds(on) :11mohm ,

+

1.1VALW

B+

E

MI Part (47.1)

P

P

L402

L402

EMI@

HCB2012KF-121T50_0805

HCB2012KF-121T50_0805

EMI@

12

C404

C404
P

P

@EMI@

@EMI@

R405

R405

P

P
10K_0402_1%

10K_0402_1%

1 2

@EMI@

@EMI@

4.7_1206_5%

4.7_1206_5%

P

P

U400

U400

B

+_1.1V

1

12

C410

C410
P

P

2

10U_0805_25V6K

10U_0805_25V6K

2200P_0402_50V7K

2200P_0402_50V7K

+3VALW

8

I

N

9

G

ND

3

I

LMT

2

P

G

SY8206DQNC_QFN10_3X3

SY8206DQNC_QFN10_3X3

E

N

B

S

L

X

F

B

B

YP

L

DO

1

C405

C405

P

P

0.1U_0603_25V7K

0.1U_0603_25V7K

2

1

6

10

L

X_1.1V

4

7

5

12

C402

C402
P

P

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

1 2

P

P

1UH_PCMB063T-1R0M S_12A_20%

1UH_PCMB063T-1R0M S_12A_20%

1

+

3VALW

12

C411

C411
P

P

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

L401

L401

P

P

R401

R401

@EMI@

@EMI@

680P_0603_50V7K

680P_0603_50V7K

S

NB_1.1V

2

FB=0.6V

P

P

100K_0402_1%

100K_0402_1%

1

R403

R403

R404

R404

P

P

0_0402_5%

0_0402_5%

2

1

EMI Part (47.1)

C403

C403

P

P

2

12

12

R402

R402
P

P

C409

C409
P

P

84.5K_0402_1%

84.5K_0402_1%

12

R406

R406

P

P

1K_0402_1%

1K_0402_1%

12

12

S CER CAP 4700P 25V K X7R 0402

S CER CAP 4700P 25V K X7R 0402

1

.1VPWR_EN <34>

12

C408

C408

C407

C407
P

P

P

P

22U_0603_6.3V6M

22U_0603_6.3V6M

+1.1VALWP

1

1

C401

C401

2

P

P

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

1

2

C406

C406

C412

C412

2

P

P

P

P

@

@

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

4 4

A

The current limit is set to 8A, 12A or 16A when this pin
is pull low, floating or pull high respectively.

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

B

2

2

2

012/09/06 2015/09/06

012/09/06 2015/09/06

012/09/06 2015/09/06

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

C

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size D ocument Number Rev

Size D ocument Number Rev

Size D ocument Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

+1.8VALWP

L

A-9869P

D

43 49Monday, February 04, 2013

43 49Monday, February 04, 2013

43 49Monday, February 04, 2013

o

o

o

f

f

f

0

0

0

.1Custom

.1Custom

.1Custom

5

D D

E

MI Part (47.1)

EMI@

EMI@

HCB2012 KF-121T50_080 5

HCB2012 KF-121T50_080 5

B+

C C

1.2V
Peak Current 7A
OCP current 12A
FSW=800kHz

H/S Rds(on) :22mohm ,

4

1

.2V controller (35.7), Support component (35.8)

3

P

P

0_0402_ 5%

0_0402_ 5%

2

R702

R702

2

1

V

R_ON <34,37,45>

1

EMI Part (47.1)

@EMI@

@EMI@

P

R706

@EMI@PR706

@EMI@

4.7_1206 _5%

P

P

L702

L702

12

12

C702

C702
P

P

2200P_0402_50V7K

2200P_0402_50V7K

@EMI@

@EMI@

C709

C709
P

P

B

+_1.2V

12

10U_0805_25V6K

10U_0805_25V6K

+3VS

P

P

U700

U700

8

9

3

2

SY8206DQN C_QFN10_3X3

SY8206DQN C_QFN10_3X3

E

I

N

B

G

I

P

LMT

L

ND

F

B

YP

L

G

DO

1

N

0.1U_060 3_25V7K

0.1U_060 3_25V7K

6

S

10

X

4

B

7

5

P

P

C704

C704

1 2

L

X_1.2V

12

1

2

C707

C707
P

P

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7_1206 _5%

2

1

1UH_MMD -05CZ-1R0M-M7L_ 7A_20%

1UH_MMD -05CZ-1R0M-M7L_ 7A_20%

+

3VS

C701

C701
P

P

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

680P_06 03_50V7K

680P_06 03_50V7K

S

NB_1.2V

P

P

L701

L701

1 2

P

P

100K_04 02_1%

100K_04 02_1%

1

R703

R703

P

P

C706

C706

2

1

2

1K_0402 _1%

1K_0402 _1%

1

2

P

P

R701

R701
P

P

R407

R407

(

7A,280mils ,Via NO.= 14)

+1.2VS

12

12

12

C711

C711

C708

C708

C710

C710
P

P

P

P

P

102K_0402_1%

102K_0402_1%

12

S CER CAP 4700P 25V K X7R 0402

S CER CAP 4700P 25V K X7R 0402

P

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

1

12

2

C703

C703
P

P

22U_0603_6.3V6M

22U_0603_6.3V6M

12

C713

C712

C712
P

P

C713
P

P

@

@

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

L/S Rds(on) :11mohm ,

2.5V controller (35.13), Support component (35.14)

P

P

U702

U702

APL5508 -25DC-TRL_SOT8 9-3

B B

+

3VS

12

1U_0402 _6.3V6K

1U_0402 _6.3V6K

@

@

J702

J702

P

P

+

2.5VSP

112

JUMP_43 X39

JUMP_43 X39

2

+

2.5VS

(0.75A,30mils ,Via NO.= 2)

A A

5

APL5508 -25DC-TRL_SOT8 9-3

P

P

C798

C798

2

I

N

3

O

UT

G

ND

1

4

12

12

C799

C799
P

P

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K

+

2.5VSP

P

R798

@PR798

@

150_120 6_5%

150_120 6_5%

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

2

2

2

012/09/0 6 2015/09/0 6

012/09/0 6 2015/09/0 6

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

012/09/0 6 2015/09/0 6

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered D ate

eciphered D ate

eciphered D ate

2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

+

+

+

1.2VSP/+2.5VSP

1.2VSP/+2.5VSP

1.2VSP/+2.5VSP

L

L

L

A-9869P

A-9869P

A-9869P

44 49Monday, Febru ary 04, 2013

44 49Monday, Febru ary 04, 2013

44 49Monday, Febru ary 04, 2013

1

o

o

o

f

f

f

0

0

0

.1

.1

.1

10/9 NB_Vdroop=-4m ohm

R503

R503

P

+

APU_CORE_NB

1 1

2 2

3 3

4 4

1

10_0402_1%

10_0402_1%

A

PU_VDDNB_SEN<7>

2.61K_0402_1%

2.61K_0402_1%

0.1U_0402_25V6

0.1U_0402_25V6

P

P

127K_0402_1%

127K_0402_1%

H

_PROCHOT#<34,7>

+

1.5V

100K_0402_1%

100K_0402_1%

P

P

C517

C517

1000P_0402_50V7K

1000P_0402_50V7K

1 2

P

P

R537

R537

118K_0402_1%

118K_0402_1%

1 2

P

P

R538

R538

10.5K_0402_1%

10.5K_0402_1%

P

V

P

P

V

P

P

C551

C551

1 2

10.5K_0402_1%

10.5K_0402_1%

C514

C514

1000P_0402_50V7K

1000P_0402_50V7K

P

P

R528

R528

1 2

@PR559

@

A

2

P

R507

@PR507

@

1 2

P

C507

@PC507

@

0_0402_5%

0_0402_5%

1 2

330P_0402_50V7K

330P_0402_50V7K

SUM+_NB

12

1

R511

R511

R512

R512

12

P

P

2

H502

H502

P

P

10K_0402_1%_ERTJ0EG103FA

10K_0402_1%_ERTJ0EG103FA

SUM-_NB

1

2

R523

R523

P

P

R522

R522

27.4K_0402_1%

27.4K_0402_1%

P

P

1

P

P

H501

H501

1 2

12

P

R559

A

PU_PWRGD<23,7>

12

1 2

R539

R539

P

P

P

P

H503

H503

12

470K_0402_5%_TSM0B474J4702RE

470K_0402_5%_TSM0B474J4702RE

A

R502

R502

P

R504

R504

P

P

2.94K_0402_1%

2.94K_0402_1%

1 2

P

P

C504

C504

1000P_0402_50V7K

1000P_0402_50V7K

1 2

1 2

P

P

R508

R508

301_0402_1%

301_0402_1%

12

12

C509

C509
P

P

C510

C510
P

P

@

@

11K_0402_1%

11K_0402_1%

2

12

470K_0402_5%_TSM0B474J4702RE

470K_0402_5%_TSM0B474J4702RE

A

PU_SVC<7>

A

PU_SVD<7>

+

1.5V

A

PU_SVT<7>

V

R_ON<34,37,44>

27.4K_0402_1%

27.4K_0402_1%

2.61K_0402_1%

2.61K_0402_1%

P

P

0.1U_0402_25V6

0.1U_0402_25V6

0.022U_0402_25V7K

0.022U_0402_25V7K

100_0402_1%

100_0402_1%

+

5VS

12

C555 0.1U_0402_25V6

C555 0.1U_0402_25V6

P

P

+

V

SUM-

V

SUM+

12

R544

R544

P

P

12

P

P

10K_0402_1%_ERTJ0EG103FA

10K_0402_1%_ERTJ0EG103FA

V

SUM-

1

C533

C533

2

0.1U_0402_10V6K

0.1U_0402_10V6K

0_0402_5%

0_0402_5%

1 2

@

@
1

1 2

@

@
1

5VS

R545

R545
P

P

H504

H504

P

2K_0402_1%

2K_0402_1%

P

P

R505

R505

137K_0402_1%

137K_0402_1%

1 2

100P_0402_50V8J

100P_0402_50V8J

10/9 OCP=50A for 35W(511 ohm)

P

P

R518

R518

681_0402_1%

681_0402_1%

1 2

P

R519

@PR519

@

1

C560

C560

P

P

@

@

0.22U_0402_16V7K

0.22U_0402_16V7K

12

R564

R564

P

P

P

P

R532

R532

0_0402_5%

0_0402_5%

R533

R533

P

P

@

@

0_0402_5%

0_0402_5%

1 2

P

P

R535

R535

@

@

0_0402_5%

0_0402_5%

P

P

R536

R536

0_0402_5%

0_0402_5%

0_0402_5%

0_0402_5%

1

@PR540

@

1

2

11K_0402_1%

11K_0402_1%

12

1 2

P

P

390P_0402_50V7K

390P_0402_50V7K

1 2

C505

C505

P

P

1 2

C512

@PC512

@

P

2

1

220P_0402_50V7K

220P_0402_50V7K

R562

R562

P

P

10K_0402_1%

10K_0402_1%

1 2

2

2

10

11

12

1 2

2

R540

P

P

P

R563

R563

10K_0402_1%@

10K_0402_1%@

1 2

1

C527

C527
P

P

2

@

@

0.15U_0402_10V6K

0.15U_0402_10V6K

P

P

C502

C502

330P_0402_50V7K

330P_0402_50V7K

C503

C503

2

P

P

U501

U501

1

I

SEN2_NB

2

N

TC_NB

3

I

MON_NB

4

S

VC

5

V

R_HOT_L

6

S

VD

7

V

DDIO

8

S

VT

9

E

NABLE

P

WROK

I

MON

N

TC

R5680_0402_5%PR5680_0402_5%

P

I

SEN2

1

2

C529

C529
P

P

100_0402_1%

100_0402_1%

10/9 OCP=62.5A for 35W (634)

P

P

42.2K_0402_1%

42.2K_0402_1%

1 2

@

@

P

P

C559

C559

12

0.22U_0402_16V7K

0.22U_0402_16V7K

48

13

2

C522

C522

1

P

P

0.022U_0402_16V7K

0.022U_0402_16V7K
422_0402_1%

422_0402_1%

1 2

R553

@PR553

@

P

1

B

C

PU controller (36.1),Driver (36.2) Support component (36.3)

+

APU_CORE

R509

R509

TDC (AB)22A (C)36A
EDC (AB)35A (C)50A

C

R542

R542

P

P

0_0603_5%

0_0603_5%

1 2

U

GATE1

OCP current (AB)43.56A
Load line -2.1mV/A
FSW=450kHz
DCR 1mohm~1.2mohm
TYP MAX
H/S Rds(on) :8.5mohm , 11mohm

2.2_0603_5%

2.2_0603_5%

1

B

OOT1

0.22U_0603_25V7K

0.22U_0603_25V7K

R510

R510

P

P

P

P

L/S Rds(on) :2.6mohm , 3.2mohm

+APU_CORE_NB

L

GATE1

TDC (AB)22A (C)30A
EDC (AB)33A (C)40A
OCP current (AB)41.51A
Load line -4mV/A
FSW=450kHz
DCR 1mohm ~1.2mohm

1 2

R520

R520

P

P

121K_0402_1%

121K_0402_1%

TYP MAX
H/S Rds(on) :7.4mohm , 8.8mohm
L/S Rds(on) :2.6mohm , 3.1mohm

36

N

U

P

P

U

R548

R548

2

B

L

P

L

OOTX

B

OOT2

GATE2

HASE2

GATE2

V

DDP

V

WM_Y

GATE1

HASE1

GATE1

49

V

DD

1

B_BOOT1

35

IN

34

B

OOT2

33

U

GATE2

32

P

HASE2

31

L

GATE2

30

1

29

28

27

L

GATE1

26

P

HASE1

25

U

GATE1

P
T

+

3VS

12

R558

R558

P

P
100K_0402_1%

100K_0402_1%

P

P

1 2

10P_0402_50V8J

10P_0402_50V8J

P

P

R546

R546

301_0402_1%

301_0402_1%

2

+

P

P

2

1 2

100P_0402_50V8J

100P_0402_50V8J

P

P

1

137K_0402_1%

137K_0402_1%

2K_0402_1%

2K_0402_1%

1 2
2

680P_0402_50V7K

680P_0402_50V7K

1

APU_CORE

10/9 CPU_Vdroop=-2.1m ohm

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

P

P

0_0402_5%

0_0402_5%

1

2

V

GATE <34>

C525

C525

C530

C530

R549

R549

R551

R551

P

P

C536

C536

P

P

P

P

R527

R527

0_0603_5%

0_0603_5%

1 2

12

C515

C515

P

P

0.22U_0603_50V7K

0.22U_0603_50V7K

R569

R569

2

1 2

R501

R501

P

P

1_0603_5%

1_0603_5%

C518

C518
P

P

1U_0603_16V6K

1U_0603_16V6K

P

P

C532

C532

1 2

2

390P_0402_50V7K

390P_0402_50V7K

C

+

5VALW

1 2

C

P

PU_B+

12

P

P

C519

C519

1U_0603_16V6K

1U_0603_16V6K

WM2_NB

@

@

ISL6208BCRZ-T_QFN8_2X2

ISL6208BCRZ-T_QFN8_2X2

N

B_UGATE1

N

B_PHASE1

R552

@PR552

@

P

32.4K_0402_1%

32.4K_0402_1%

N

B_BOOT1

N

B_LGATE1

2

2

2

011/07/29

011/07/29

011/07/29

U502

U502

P

P

1

GATE

U

2

OOT

B

3

WM

P

4

ND

G

P

P

2.2_0603_5%

2.2_0603_5%

1 2

0.22U_0603_25V7K

0.22U_0603_25V7K

HASE

P

CCM

F

CC

V

GATE

L

P

P

0_0603_5%

0_0603_5%

1 2

R572

R572

P

P

C557

C557

C

C

C

42

43

44

45

46

47

B_NB
F

SEN_NB

SUMN_NB

I

SEN1

I

16

C523

C523
P

P

P

C534

1

1 2

V

SUMN

SUMP

I

I

17

0.22U_0402_16V7K

0.22U_0402_16V7K

C531

C531
P

P

@

@

2

P

P

R556

R556

10_0402_5%

10_0402_5%

B

OMP_NB
C

GOOD_NB
P

TN

SEN
V

R

19

18

12

330P_0402_50V8J

330P_0402_50V8J

1

2

SEN1_NB

I

SUMP_NB

I

S IC ISL6277HRZ-TR5570 QFN 48P PWM

S IC ISL6277HRZ-TR5570 QFN 48P PWM

SEN2

SEN3

I

I

15

14

SEN1

I

2

1

0.22U_0402_16V7K

0.22U_0402_16V7K

R550

R550

P

P

@PC534

@

2

820P_0402_50V7K

820P_0402_50V7K

A

PU_VDD_RUN_FB_L<7>

CCM_NB

WM2_NB

F

P

40

41

CCM_NB
F

B2
F

21

20

2

C535

C535

P

P

0.01U_0402_50V7K

0.01U_0402_50V7K

1

R554

@PR554

@

P
0_0402_5%

0_0402_5%

B_LGATE1

B_PHASE1NB_UGATE1

N

N

37

38

39

GATEX

HASEX

L

P

WM2_NB
P

OMP

GOOD

B
F

P

C

22

23

24

C528

C528

P

P

1 2

1000P_0402_50V7K

1000P_0402_50V7K

1.65K_0402_1%

1.65K_0402_1%

12

P

R555

@PR555

@

0_0402_5%

0_0402_5%

R557

R557

P

P

1

10_0402_5%

10_0402_5%

A

PU_VDD_SEN <7>

GATEX
U

OOT1
B

OOT1
B

P

P

1

2

1 2

C508

C508

U

GATE2

B

OOT2

0.22U_0603_25V7K

0.22U_0603_25V7K

L

GATE2

8

@

@

7

P

P

R570

R570

0_0402_5%

0_0402_5%

1

6

5

EMI Part (35.33)

P

P

Q504

R574

R574

Q504

CSD87351Q5D_SON8~D

CSD87351Q5D_SON8~D

2

3

4

2

1

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

1

2

1

1
D

G

2

2
S

S

4

3

0_0603_5%

0_0603_5%

1 2

R521

R521

P

P

2.2_0603_5%

2.2_0603_5%

1 2

+

5VALW

2

1

@

@

2

1

8

D

7

1/D2
S

Q501

Q501
P

P

2

2

G

S

6

5

FDMS3664S_POWER56-8-7

FDMS3664S_POWER56-8-7

EMI Part (47.1)

R560

R560

P

P

2

1

C513

C513

P

P

P

P

R561

R561

@

@

0_0603_5%

0_0603_5%

1 2

R541

R541

P

P

@

@

2.2_0603_5%

2.2_0603_5%

1 2

C524

C524

P

P

0.22U_0603_25V7K

0.22U_0603_25V7K

1U_0603_16V6K

1U_0603_16V6K

7
6
5

D

C

12

C537

C537
P

P

10U_0805_25V6K

10U_0805_25V6K

1

2

12

R506

R506
P

P

3

C538

C538
P

P

P

@EMI@

@EMI@

HASE1

4.7_1206_5%

4.7_1206_5%

C506

C506
P

P

@EMI@

@EMI@

2

2
S

12

1

C539

C539
P

P

2

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10K_0402_1%

10K_0402_1%

1 2

I

SEN1

3.65K_0402_1%

3.65K_0402_1%

1 2

V

SUM+

1 2

V

SUM-

680P_0603_50V7K

680P_0603_50V7K

7

1

1

1
D

G

1/D2
S

2

2

2

G

S

S

4

6

5

EMI Part (47.1)

@

@

Q503

Q503

P

P

CSD87351Q5D_SON8~D

CSD87351Q5D_SON8~D

2

@

@

3

C521

C521

P

P

1 2

4

EMI Part (35.33)

1

12

C556

C556
P

P

2

C552

C552
P

P

10U_0805_25V6K

10U_0805_25V6K

@EMI@

@EMI@

2200P_0402_50V7K

2200P_0402_50V7K

A

PU_NB_SW

12

1

2

@

@

P

P

R571

R571

10K_0402_1%

10K_0402_1%

4.7_1206_5%

4.7_1206_5%

1 2

I

SEN1_NB

R573

R573
P

P

@EMI@

@EMI@

C558

C558
P

P

@EMI@

@EMI@

V

V

680P_0603_50V7K

680P_0603_50V7K

R575

R575

P

P

3.65K_0402_1%

3.65K_0402_1%

1 2

SUM+_NB

R566

R566

P

P
1_0402_1%

1_0402_1%

1

SUM-_NB

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

Date: Sheet

E

MI Part (47.1)

PU_B+

1

1

+

+

C545

C545
P

P

2

2

2200P_0402_50V7K

2200P_0402_50V7K

@EMI@

@EMI@

P

P

R513

R513

R515

R515

P

P

R517

R517

P

P
1_0402_1%

1_0402_1%

12

C548

C548
P

P

2200P_0402_50V7K

@EMI@

2200P_0402_50V7K

@EMI@

P

HASE2

1

I

SEN2

Q502

Q502
P

P

4.7_1206_5%

4.7_1206_5%

R516

R516
P

P

@

@

3.65K_0402_1%

3.65K_0402_1%

EMI@

EMI@

2

V

SUM+

12

C516

C516
P

P

V

SUM-

@

@

EMI@

EMI@

680P_0603_50V7K

680P_0603_50V7K

FDMS3664S_POWER56-8-7

FDMS3664S_POWER56-8-7

12

C550

C550
P

1

8

C553

C553
P

P

2

P

@

@

2200P_0402_50V7K

@EMI@

2200P_0402_50V7K

@EMI@

7
6

A

PU_NB_SW2

5

4.7_1206_5%

4.7_1206_5%

C

PU_B+_NB

680P_0603_50V7K

680P_0603_50V7K

12

12

C554

C554
P

P

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

P

P

L505

L505

0.22UH_MMD-06DZNR22ME_ 25A_20%

0.22UH_MMD-06DZNR22ME_ 25A_20%

@

@

P

P

R576

R576

10K_0402_1%

10K_0402_1%

1 2

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

ompal Electronics, Inc.

+

+

+

CPU_CORE/VDDNBP

CPU_CORE/VDDNBP

CPU_CORE/VDDNBP

E

P

P

L501

L501

HCB2012KF-121T50_0805

HCB2012KF-121T50_0805

1 2

P

P

L506

L506

HCB2012KF-121T50_0805

HCB2012KF-121T50_0805

1 2

1

+

+

C501

C501

C511

C511

100U_25V_M

100U_25V_M

100U_25V_M

100U_25V_M

P

P

P

P

2

@

@

L502

L502

P

P

0.22UH_MMD-06DZNR22ME_ 25A_20%

0.22UH_MMD-06DZNR22ME_ 25A_20%

+

APU_CORE

R514

R514

P

P

10K_0402_1%

10K_0402_1%

1 2

I

SEN2

C

PU_B+_NB

HCB2012KF-121T50_0805

HCB2012KF-121T50_0805

1 2

C

PU_B+

1

12

1

C542

C540

C540
P

P

10U_0805_25V6K

10U_0805_25V6K

P

P

R524

R524

10K_0402_1%

10K_0402_1%

1 2

P

P

R530

R530

1 2

R531

R531

P

P
1_0402_1%

1_0402_1%

1 2

12

C543

C543
P

P

10U_0805_25V6K

10U_0805_25V6K

12

R526

R526
P

P

EMI@

EMI@

@

@

1

C526

C526
P

P

2

@

@

EMI@

EMI@

+

APU_CORE_NB

Q

ML70 LA-8371P

C542

C541

C541

P

P

P

P

2

@

@

I

SEN2_NB

2

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

0.22UH_MMD-06DZNR22ME_ 25A_20%

0.22UH_MMD-06DZNR22ME_ 25A_20%

12

1

C544

C544

C520

C520

P

P

P

P

2

@

@

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

0.22UH_MMD-06DZNR22ME_ 25A_20%

0.22UH_MMD-06DZNR22ME_ 25A_20%

@

@

R578

R578

P

P

10K_0402_1%

10K_0402_1%

1 2

I

SEN2_NB

@

@

P

P

R579

R579

3.65K_0402_1%

3.65K_0402_1%

1 2

V

SUM+_NB

R577

P

P

R577

@

@

1_0402_1%

1_0402_1%

1 2

V

SUM-_NB

E

EMI@

EMI@

EMI@

EMI@

L507

L507

P

P

L503

L503

P

P

+

APU_CORE

R525

R525

P

P

10K_0402_1%

10K_0402_1%

1 2

C

PU_B+_NB

@

@

P

P

L504

L504

@

@

10K_0402_1%

10K_0402_1%

45 49Monday, February 04, 2013

45 49Monday, February 04, 2013

45 49Monday, February 04, 2013

B

+

EMI@

EMI@

C

PU_B+

I

SEN1

APU_CORE_NB
+

2

R580

R580

P

P

1

SEN1_NB

I

0

0

0

.1

.1

.1

o

o

o

f

f

f

5

D D

E

MI Part (47.1)

EMI@

EMI@

P

P

L801

L801

HCB2012KF-121T50_0805

HCB2012KF-121T50_0805

B

+

R804

R804

P

P

10_0402_5%

10_0402_5%

12

V

C C

B B

A A

SS_GPU_SENSE<15>

V

CC_GPU_SENSE<15>

+

VGA_CORE

1 2

P

P

10_0402_5%

10_0402_5%

R806

R806

1000P_0402_50V7K

1000P_0402_50V7K

GPIO6

VID5

1 2

P

P

C809

C809

1000P_0402_50V7K

1000P_0402_50V7K

12

12

C811

C811

P

P

330P_0402_50V7K

330P_0402_50V7K

R812

R812

P

P

2.37K_0402_1%

2.37K_0402_1%

1 2

1 2

2

1

0

1

1

1

1

1

1

1

1

1

1

1

1

1

P

P

R816

R816

C818

C818

715_0402_1%

715_0402_1%

P

P

GPIO30

VID4

1

0

0

0

0

0 1 0 0

0

11 000

1

1

1

1

G

PU_B+

12

1

C803

C803

C802

C802

P

P

P

P

2

10U_0805_25V6K

10U_0805_25V6K

2200P_0402_50V7K

2200P_0402_50V7K

@EMI@

@EMI@

2

C812

C812

P

P

330P_0402_50V7K

330P_0402_50V7K

1

R813

R813

P

P

226K_0402_1%

226K_0402_1%

1 2

390P_0402_50V7K

390P_0402_50V7K

56P_0402_50V8

56P_0402_50V8

1 2

120K_0402_1%

120K_0402_1%

GPIO29

VID3

1 1

0

0

1

1

0

0

0

1

11 0.775V

C819

C819

P

P

1 2

C814

C814

P

P

P

P

R835

R835

GPIO20

VID2

0

0

1

10

0

1

10

0

1

1

0

1000P_0402_50V7K

1000P_0402_50V7K

2

2

1

8.06K_0402_1%

8.06K_0402_1%

2

V

GA_PWRGD<14,24,43>

1

C804

C804
P

P

2

10U_0805_25V6K

10U_0805_25V6K

P

P

C815

C815

1

1

47K for CPU

47K for GPU

1

P

P

R817

R817

GPIO15

VID1

0

1

0

101.075V

0

1

110

0

1

1

0

1

0

10

4

VDDC

1.15V

1.125V1110

1.100V

1.050V

1.025V

1.000V

0.975V

0.950V

0.925V

0.900V

0.875V

0.850V

0.825V

0.800V

P

P

R718

R718

1.8K_0402_1%

1.8K_0402_1%

Default

+

5VALW

3

V

GA controller (43.1),Driver (43.2) Support component (43.3)

1

R802

R802

P

P

1_0603_5%

1_0603_5%

1

P

P

C806

C806

1U_0603_6.3V6M

1U_0603_6.3V6M

2

G

PU_ISUM+

G

PU_ISUM-

10

9

8

29

GND
A

ISL62881CHRTZ-T_TQFN28_4X4

ISL62881CHRTZ-T_TQFN28_4X4

P

P

R29

R29

11

TN
R

SUM-

SUM+

I

I

P

P

U801

U801

PRSLPVR

ID6

R_ON

V

V

D

25

26

27

28

1

2

PU_DPRSLPVR
G

0.1U_0402_25V6

0.1U_0402_25V6

12

R828

R828
P

P

12

C822

C822
P

P

1 2

@

@

47K_0402_5%

47K_0402_5%

XS_PWREN
P

2

C807

C807
P

P

12

0.22U_0603_25V7K

0.22U_0603_25V7K

+

5VALW

12

B

ST_GPU

P

P

R841

R841

0_0402_5%

0_0402_5%

12

13

14

IN

DD

V

V

OOT

MON
I

B

U

GATE

P

HASE

L

GATE

V

ID5

ID2

ID3

ID4

V

V

V

V

22

23

24

<13>

2

2

R824 0_0402_5%

R824 0_0402_5%

R826 0_0402_5%

R826 0_0402_5%

R827 0_0402_5%

R827 0_0402_5%

R825 0_0402_5%

R825 0_0402_5%

P

P

P

P

P

P

P

P

1 2

1

1

@

@

@

@

@

@

<13>

PU_VID2

PU_VID4

PU_VID3

<14,24,47>

PU_VID5

G

G

G

G

P

P

2.2_0603_5%

2.2_0603_5%

15

D

H_GPU

16

L

X_GPU

17

V

SSP

18

D

L_GPU

19

CCP

20

V

ID0

21

V

ID1

12

12

R821 0_0402_5%

R821 0_0402_5%
P

P

1 2

@

@

<13>

<13>

<13>

PU_VID1
G

R805

R805

0.1U_0603_25V7K

0.1U_0603_25V7K

12

1_0603_5%

1_0603_5%

12

2.2U_0603_6.3V6K

2.2U_0603_6.3V6K

12

R823

R823

R830

R830
P

P

P

P

@

@

10K_0402_1%

10K_0402_1%

12

R837

R837

R836

R836

P

P

P

P

@

@

10K_0402_1%

10K_0402_1%

<13>

C810

C810

P

P

12

+

5VALW

+

3VGS

12

10K_0402_1%

10K_0402_1%

1

2

10K_0402_1%

10K_0402_1%

4

R833

R833
P

P

@

@

10K_0402_1%

10K_0402_1%

R840

R840
P

P

10K_0402_1%

10K_0402_1%

12

P

P

R814

R814

C817

C817

P

P

12

12

R832

R832

R831

R831

P

P

P

P

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

1

12

R838

R838

R839

R839
P

P

P

P

@

@

@

@

2

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

47K_0402_1%

47K_0402_1%

+

3VS

12

1_0603_5%

1_0603_5%

1 2

P

P

R809

R809

P

P

R801

R801

7

V

SEN

6

F

B

5

C

OMP

4

V

W

12

3

R

BIAS

2

P

GOOD

1

C

LK_EN#

0_0402_5%

0_0402_5%

2

+VGA_CORE
TDC 21A
EDC 31.5A
OCP current 40 A
FSW=300kHz
DCR 1.4m ohm +- 5%
T YP MAX
H/S Rds(on) :11 .7mohm , 14.5m ohm

5

Q801

Q801
P

P

4

123

TR TPCA8065-H 1N PPAK56-8

TR TPCA8065-H 1N PPAK56-8

5

123

5

Q802

Q802
P

P

4

S TR TPCA8059-H 1N PPAK56-8

S TR TPCA8059-H 1N PPAK56-8

L/S Rds(on) :3. 8mohm , 4.8mo hm

P

P

0.36UH_PDME064T-R36MS_24A_20%

0.36UH_PDME064T-R36MS_24A_20%

1

12

@EMI@

@EMI@

R808

R808

P

P

4.7_1206_5%

4.7_1206_5%

Q803

Q803
P

P

@EMI@

@EMI@

P

P

C816

C816

123

680P_0603_50V7K

680P_0603_50V7K

1 2

S TR TPCA8059-H 1N PPAK56-8

S TR TPCA8059-H 1N PPAK56-8

Layout Note:
Place near Choke

G

PU_ISUM+

G

PU_ISUM-

2

12

P

P

3.65K_0805_1%

3.65K_0805_1%

R815

R815

P

P

1 2

2.61K_0402_1%

2.61K_0402_1%

11K_0402_1%

11K_0402_1%

.047U_0402_16V7K

.047U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

R810

R810

1 2

L802

L802

4

3

H7

H7

P

P

1

10KB_0402_5%_ERTJ1VR103J

10KB_0402_5%_ERTJ1VR103J

B value:4250K±2%

P

P

R818

R818

1 2

C820

C820

P

P

2

1

C821

C821

P

P

R822

R822

P

P

1.2K_0402_1%

1.2K_0402_1%

1

2

2

1

2

P

R811

@PR811

@

0_0402_5%

0_0402_5%

1

+

VGA_CORE

1

+

+

C899

C899
P

P

2

560U_D2_2VM_R4.5M

560U_D2_2VM_R4.5M

0.1U_0402_16V7K

0.1U_0402_16V7K

12

C823

C823
P

P

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONFI DENTIAL

HIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONFI DENTIAL

HIS SHEET OF ENGINEERING DRAWI NG IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONI CS, INC. AND CONTAINS CONFI DENTIAL

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D

AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

5

4

MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .

3

2

2

2

012/07/10 2013/07/10

012/07/10 2013/07/10

012/07/10 2013/07/10

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

2

Date: Sheet

ompal Electronics, Inc.

+

+

+

VPU_COREP

VPU_COREP

VPU_COREP

L

L

L

A-9869P

A-9869P

A-9869P

0

0

0

.1

.1

4

4

4

6 49Monday, February 04, 2013

6 49Monday, February 04, 2013

1

6 49Monday, February 04, 2013

.1

o

o

o

f

f

f

A

1 1

0

.95V controller (35.11), Support component (35.12)

B

C

D

1

P

P

C601

C601

1U_0603_6.3V6M

1U_0603_6.3V6M

2

+

0.95VS_POK

+

5VS

P

P

U600

U600

6

V

CNTL

5

V

IN

9

V

IN

8

E

N

7

P

OK

3

V

OUT

4

V

OUT

2

F

B

ND
G

1

APL5916KAI-TRL_SO8

APL5916KAI-TRL_SO8

10K_0402_1%

10K_0402_1%

+

0.95VS_FB

56K_0402_1%

56K_0402_1%

+

1

1

P

P

R604

R604

2

12

P

P

R603

R603

12

C603

C603

C600

C600

2

P

P

P

P

39P_0402_50V8J

39P_0402_50V8J

0.95VGSP

@

@

P

P

J601

J601

+

22U_0805_6.3V6M

22U_0805_6.3V6M

0.95VGSP

0

.95V

1 2

JUMP_43X118

JUMP_43X118

(

4A,160mils ,Via NO.= 4)

+

0.95VGS

+

1.1VALW

12

P

P

C604

C604

22U_0805_6.3V6M

22U_0805_6.3V6M

+

1 2

+

3VS

12

1

P

P

J602

J602

1

JUMP_43X79

JUMP_43X79

2

2

+

0.95VS_VIN

0.95VS_EN

P

P

R601

R601

@1K_0402_1%

@1K_0402_1%

2 2

P

P

R602

R602

10K_0402_1%

10K_0402_1%

P

XS_PWR EN<14,24,46>

3 3

1 2

P

P

C602

C602

0.01U_0402_25V6

0.01U_0402_25V6

Peak Current 4A
OCP current 16A
FSW=800kHz

H/S Rds(on) :22mohm ,
L/S Rds(on) :11mohm ,

4 4

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2

2

2

011/08/16 2012/08/15

011/08/16 2012/08/15

011/08/16 2012/08/15

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

C

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size D ocument Number Rev

Size D ocument Number Rev

Size D ocument Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

ompal Electronics, Inc.

+1.5VPCIE/0.935V

+1.5VPCIE/0.935V

+1.5VPCIE/0.935V

L

L

L

A-9869P

A-9869P

A-9869P

D

o

o

o

f

47 49Monday, February 04, 2013

f

47 49Monday, February 04, 2013

f

47 49Monday, February 04, 2013

0

0

0

.1

.1

.1

5

CPU_Core output CAP (Including MLCC) 36.4

+

APU_CORE

12

C1000

D D

C1000
P

P

22U_0603_6.3V6M

22U_0603_6.3V6M

12

C1010

C1010
P

P

22U_0603_6.3V6M

22U_0603_6.3V6M

12

C1001

C1001
P

P

22U_0603_6.3V6M

22U_0603_6.3V6M

1

2

C1011

C1011
P

P

22U_0603_6.3V6M

22U_0603_6.3V6M

+

APU_CORE

12

C1002

C1002
P

P

22U_0603_6.3V6M

22U_0603_6.3V6M

12

C1013

C1013
P

P

22U_0603_6.3V6M

22U_0603_6.3V6M

12

C1003

C1003
P

P

22U_0603_6.3V6M

22U_0603_6.3V6M

1

2

C1014

C1014
P

P

22U_0603_6.3V6M

22U_0603_6.3V6M

4

+APU_CORE_NB

1

+

2

C1004

C1004
P

P

22U_0603_6.3V6M

22U_0603_6.3V6M

12

C1012

C1012
P

P

22U_0603_6.3V6M

22U_0603_6.3V6M

APU_CORE_NB

12

C1029

C1028

C1028
P

P

22U_0603_6.3V6M

22U_0603_6.3V6M

C1029
P

P

3

2

1

GFX output CAP (Including MLCC) 36.5

+

APU_CORE_NB

Local

1

1

12

2

C1030

C1030
P

P

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

12

C1031

C1031
P

P

22U_0603_6.3V6M

22U_0603_6.3V6M

2

1

+

+

+

+

C1032

C1032
P

P

C1033

C1033
P

P

2

@

@

330U_D2_2V_Y

330U_D2_2V_Y

560U_D2_2VM_R4.5M

560U_D2_2VM_R4.5M

12

C1027

C1027
P

P

22U_0603_6.3V6M

22U_0603_6.3V6M

C C

B B

12

C1019

C1019

C1020

C1020
P

P

P

P

0.22U_0402_16V7K

0.22U_0402_16V7K

12

C1006

C1006

C1007

C1007

P

P

P

P

0.22U_0402_16V7K

0.22U_0402_16V7K

+

APU_CORE

1

2

C1018

C1018
P

P

22U_0603_6.3V6M

22U_0603_6.3V6M

1

12

2

C1022

C1022

C1021

C1021

P

P

P

P

0.01U_0402_50V7K

0.01U_0402_50V7K

0.22U_0402_16V7K

0.22U_0402_16V7K

1

12

2

C1009

C1009

C1008

C1008

P

P

P

P

0.01U_0402_50V7K

0.01U_0402_50V7K

0.22U_0402_16V7K

0.22U_0402_16V7K

Local

1

2

C1015

C1015
P

P

22U_0603_6.3V6M

22U_0603_6.3V6M

1

1

2

2

C1005

C1023

C1023
P

P

0.01U_0402_50V7K

0.01U_0402_50V7K

0.01U_0402_50V7K

0.01U_0402_50V7K

1

2

0.01U_0402_50V7K

0.01U_0402_50V7K

1

+

+

C1100

C1100
P

P

2

560U_D2_2VM_R4.5M

560U_D2_2VM_R4.5M

C1005
P

P

12

C1016

C1016
P

P

22U_0603_6.3V6M

22U_0603_6.3V6M

1

12

2

180P_0402_50V8J

180P_0402_50V8J

1

+

+

C1101

C1101
P

P

2

C1026

C1026

C1024

C1024

P

P

P

P

180P_0402_50V8J

180P_0402_50V8J

330U_D2_2V_Y

330U_D2_2V_Y

12

PC1017

PC1017

12

12

20P_0402_25V8K

20P_0402_25V8K
2

2

12

12

C1025

C1025
P

P

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J

+

VGA_CORE

12

C1043

C1043
P

P

10U_0603_6.3V6M

10U_0603_6.3V6M

1

C1076

C1076

2

P

P

1

+

+

C1102

C1102
P

P

2

@

@

330U_D2_2V_Y

330U_D2_2V_Y

1U_0402_6.3V6K

1U_0402_6.3V6K

12

C1050

C1050
P

P

1U_0402_6.3V6K

1U_0402_6.3V6K

C1034

C1034

C1035

C1035

P

P

P

P

0.22U_0402_16V7K

0.22U_0402_16V7K

+VGA_CORE

+VDDC

12

1

C1042

C1042

C1040

C1040

P

P

10U_0603_6.3V6M

10U_0603_6.3V6M

C1077

C1077
P

P

1U_0402_6.3V6K

1U_0402_6.3V6K

C1051

C1051
P

P

1U_0402_6.3V6K

1U_0402_6.3V6K

2

P

P

10U_0603_6.3V6M

10U_0603_6.3V6M

12

12

C1078

C1078
P

P

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

C1052

C1052

2

2

P

P

1U_0402_6.3V6K

1U_0402_6.3V6K

12

C1036

C1036

C1037

C1037
P

P

P

P

180P_0402_50V8J

180P_0402_50V8J

0.22U_0402_16V7K

0.22U_0402_16V7K

12

C1041

C1041
P

P

10U_0603_6.3V6M

10U_0603_6.3V6M

1

12

C1044

C1044

C1045

C1045

2

P

P

P

P

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

12

12

C1054

C1054

C1053

C1053

P

P

P

P

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

12

12

C1038

C1038
P

P

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J

12

12

C1046

C1046

C1079

C1079

P

P

P

P

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

12

12

C1055

C1055

C1056

C1056

P

P

P

P

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

Richland

VDD

VDD_NB

VGA 560u x1

330uF*9m 22uF 0.01u

4

1

15

4

10u x 4 1u x30

VGA_Core output CAP (Including MLCC 43.9)

12

C1047

C1047

C1048

C1048

P

P

P

P

1U_0402_6.3V6K

1U_0402_6.3V6K

1

C1057

C1057

C1058

C1058

2

P

P

P

P

1U_0402_6.3V6K

1U_0402_6.3V6K

12

12

C1049

C1049
P

P

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

12

1

C1059

C1059

2

P

P

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

0.22uF

5

4

2

180P

4

3

12

1U_0402_6.3V6K

1U_0402_6.3V6K

2

2

2

011/07/2 9

011/07/2 9

011/07/2 9

1

12

C1064

C1064

C1065

C1065

C1066

2

P

P

1U_0402_6.3V6K

1U_0402_6.3V6K

C1066
P

P

P

P

1U_0402_6.3V6K

1U_0402_6.3V6K

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

12

C1067

C1067
P

P

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

eciphered D ate

eciphered D ate

eciphered D ate

12

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size Document N umber Rev

Size Document N umber Rev

Size Document N umber Rev

A

A

A

3

3

3

Date: Sheet

Date: Sheet

2

Date: Sheet

ompal Electronics, Inc.

P

P

P

ROCESSOR DECOUPLING

ROCESSOR DECOUPLING

ROCESSOR DECOUPLING

L

A-8712P

1

o

o

o

f

48 49Monday, Febru ary 04, 2013

f

48 49Monday, Febru ary 04, 2013

f

48 49Monday, Febru ary 04, 2013

0

0

0

.1

.1

.1

1

C1061

C1061

2

P

P

I

I

I

ssued Date

ssued Date

ssued Date

12

C1063

C1063

C1062

C1062
P

P

P

P

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

3

12

1

C1069

C1069

2

P

P

1U_0402_6.3V6K

A A

5

4

1U_0402_6.3V6K

C1068

C1068

C1060

C1060
P

P

P

P

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

S

S

S

ecurity Classif ication

ecurity Classif ication

ecurity Classif ication

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

5

c

hange PF2 vandor for cost down plane

P

WR

c

hange PR337 235K to 210K & PR5357 156k to 174k

P

WR

P

WR

4

3

2

1

Version change list (P.I.R. List) Page 1 of 1

for PWR

Reason for change PG# Modify List Date

D D

I

tem Time (When) Page (Where) Location / Discription ( How / What) Request (Who)

PhaseItem

1 EVT--2012/11/28 P39-PWR-BATTERY CONN / OTP
2

EVT--2012/11/28 P41-PWR-+3VALW/5VALW

3

EVT--2012/11/28 P41-PWR-+3VALW/5VALW Delate PC351 add PC353 150u D2 cap

4

EVT--2012/11/28 P43-PWR_+1.8VSGP/+1.1VALWP change PC157 220u H=4.5mm to 330u D2 cap H=2mm PWR

5 EVT--2012/11/28 P43-PWR_+1.8VSGP/+1.1VALWP change PR158 16.2K to 17.4K PWR

C C

6 EVT--2012/11/28 P50-PWR-CPU_CORE change the PC1101 560u to 330u PWR

B B

A A

S

S

S

ecurity Classification

ecurity Classification

5

4

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.

2

2

2

012/12/13 2013/12/13

012/12/13 2013/12/13

012/12/13 2013/12/13

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

D

D

D

eciphered Date

eciphered Date

eciphered Date

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

T

T

T

itle

itle

itle

Size D ocument Number Rev

Size D ocument Number Rev

Size D ocument Number Rev

C

C

C

ustom

ustom

ustom

Date: Sheet

Date: Sheet

2

Date: Sheet

ompal Electronics, Inc.

P

P

P

IR (PWR)

IR (PWR)

IR (PWR)

V

CUAA

49 50Monday, February 04, 2013

49 50Monday, February 04, 2013

49 50Monday, February 04, 2013

1

0

0

0

o

o

o

f

f

f

.2

.2

.2

5

H

W PIR (Product Improve Record)

V

DKTE LA-9869P SCHEMATIC CHANGE LIST
REVISION CHANGE: 0.2
GERBER-OUT DATE: 2012/12/25

-

------------------------------------------------------------------------------------------------------------------------------------------------------------------

Item Page Date Request Solution

-------------------------------------------------------------------------------------------------------------------------------------------------------------------

1) 21 2012/12/04a For CRT undershoot issue Add R66 & R67 for CRT issue.

2) 14 2012/12/04a For VGA_CORE display unomunt CR103.

3) 22 2012/12/13a For EMI request Change L8/L9/L10/L11 part number for EMI requesrt.

4) 34 2012/12/13a For change EC PIN Change 1.1VPWR_EN from pin 71 to pin 127 and USB_EN#0 from pin84 to pin 23.

5) 19 2012/12/14a For LVDS translator Delete all of RTD2132S components.

D D

6) 31 2012/12/14a For S&C port wake Add CHG_PWR_GATE# on U15 pin 1 and connect to EC pin82.

7) 24 2012/12/17a For leakage with PXS_PWREN Change Power rail from +3VALW_FCH to +3VALW on R216 pin1

8) 07 2012/12/22a For leakge Delete R47, D18.

9) 24 2012/12/22a For NV suggestion Add R283 & Q30.

10) 34 2012/12/25a For S&C port wake Add RB25.

C C

4

3

2

1

B B

A A

S

S

S

ecurity Classification

ecurity Classification

ecurity Classification

I

I

I

ssued Date

ssued Date

ssued Date

T

T

T

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

HIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

2

2

013/01/22 2014/01/21

013/01/22 2014/01/21

013/01/22 2014/01/21

3

C

C

C

ompal Secret Data

ompal Secret Data

ompal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

C

C

C

ompal Electronics, Inc.

ompal Electronics, Inc.

itle

itle

itle

C

C

C

ustom

ustom

ustom

ompal Electronics, Inc.

H

H

H

W-PIR

W-PIR

W-PIR

N

HQAA LA-6831P M/B

50 50Monday, February 04, 2013

50 50Monday, February 04, 2013

50 50Monday, February 04, 2013

1

0

0

0

T

T

T

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheetof

Date: Sheetof

2

Date: Sheetof

.3

.3

.3