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Satellite C660D
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Quanta Computer LA-6843P PWWAE LC-Marseille 10AD, Satellite C660, Satellite C660D Schematic

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A
1 1
B
C
D
E
Compal confidential
2 2
LC-Marseille 10AD
PWWAE LA-6843P Schematics Document
Mobile AMD S1G4/ RS880M / SB820M
3 3
2010-08-16 Rev. 1.0
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
401982
401982
140Wednesday, September 01, 2010
140Wednesday, September 01, 2010
140Wednesday, September 01, 2010
E
B
B
B
A
B
C
D
E
Compal Confidential
Model Name : PWWAA File Name : LA-6843P
1 1
Thermal Sensor Fan Control
ADM1032ARMZ
page 7
page 5
AMD S1G4 CPU
uFCPGA-638 Package
page 5,6,7,8
Hyper Transport Link 2.6GHz
16X16
Memory BUS(DDRIII)
Dual Channel
1.5V DDRIII 1066/1333MHZ
200pin DDRIII-SO-DIMM X2
BANK 0, 1, 2, 3
RTL8105E 10/100M
PCIe port 3
page 24
page 9,10
RJ45
page 24
AMD
CRT
page 16
LCD Conn.
page 17
2 2
A-Link Express II 4X PCI-E
IO/B-- USB Right
USB port 0,1
page 23
Card Reader
USB port 5
3 3
page 25
Int. Camera
USB port 9
WLAN
USB port 8
page 17
page 27
USB
5V 480MHz
USB
5V 480MHz
RS880M
page 11,12,13,14,15
AMD
SB820M
page 18,19,20,21,22
PCIe 4x
1.5V 2.5GHz(250MB/s)
SATA port 0
5V 1.5GHz(150MB/s)
SATA port 1
5V 1.5GHz(150MB/s)
SATA HDD
page 23
SATA ODD
page 23
WLAN
LAN
PCIe port 2
page 23
PCIe port 3
page 24
HD Audio
RTC CKT.
Power On/Off CKT.
page 30
DC/DC Interface CKT.
page 31
Power Circuit DC/DC
4 4
page 31,32,33,34,35 36,37,38,39
A
Power/B
page 30
B
Debug Port
page 29
Touch Pad
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
ENE KB926 E0
C
3.3V 33 MHz
LPC BUS
page 28
Int.KBD
page 29page 30
EC ROM
page 29
Compal Secret Data
Compal Secret Data
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
Compal Secret Data
3.3V/1.5V 24MHz
Deciphered Date
Deciphered Date
Deciphered Date
HDA Codec
ALC259
page 26
Int.
MIC CONN
page 17
D
MIC CONN
page 27
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
HP CONN
SPK CONN
page 27
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
401982
401982
E
page 27
240Wednesday, September 01, 2010
240Wednesday, September 01, 2010
240Wednesday, September 01, 2010
B
B
B
5
4
3
2
1
DESIGN CURRENT 0.1A
B+
RT8205EGQW
D D
SUSP
N-CHANNEL
DESIGN CURRENT 0.1A
DESIGN CURRENT 1A
DESIGN CURRENT 3.5A
DESIGN CURRENT 2A
+3VL +5VL +3VALW +5VALW
+5VS
SI4800
WOL_EN#
P-CHANNEL
DESIGN CURRENT 330mA
+3V_LAN
AO-3413
SUSP
N-CHANNEL SI4800
ENVDD
P-CHANNEL
DESIGN CURRENT 1.5A
DESIGN CURRENT 1A
+3VS
+LCD_VDD
AO-3413
C C
APL5508
PWWAE LC-Marseille AMD
SUSP#
MP2121DQ
DESIGN CURRENT 300mA
DESIGN CURRENT 2.5A
+2.5VS
+1.8VS
POK
RT8209BGQW
N-CHANNEL
VLDT_EN#
DESIGN CURRENT 0.3A
DESIGN CURRENT 3.5A
+1.1VALW
+1.1VS
IRF8113
VR_ON
B B
N-CHANNEL IRF8113
ISL6265A
VLDT_EN#
DESIGN CURRENT 6A
DESIGN CURRENT 18A
DESIGN CURRENT 18A
DESIGN CURRENT 4A
+NB_CORE
+CPU_CORE0 +CPU_CORE1 +VDDNB
SYSON
RT8209BGQW
SUSP
N-CHANNEL
DESIGN CURRENT 5A
DESIGN CURRENT 1A
+1.5V
+1.5VS
IRF8113
SUSP
APL5331KAC
DESIGN CURRENT 1A
+0.75VS
VR_ON#
A A
5
APL5331KAC
4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
DESIGN CURRENT 1.5A
3
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
+1.05VS
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
401982
401982
340Wednesday, September 01, 2010
340Wednesday, September 01, 2010
340Wednesday, September 01, 2010
1
B
B
B
A
B
C
D
E
Voltage Rails
O : ON X : OFF
+5VS
+1.5V
+3VS +2.5VS +1.8VS +1.5VS +1.1VS +1.05VS +0.75VS +VGA_CORE +VDDNB +CPU_CORE
1 1
State
power plane
+B +3VL +5VL
+RTCVCC
+5VALW +3VALW +1.1VALW
Platform Danube
@ : just reserve , no build
SB820MR1@ : just reserve for SB820MR1 only
R3@ : just reserve for R3 only
CONN@ : just reserve for Connector only
CAM@ : just reserve for WebCam only
BT@ : just reserve for Blue Tooth only
880MR1@: just reserve for 880MR1 only 8105E_VC@: just reserve for 10/100 LAN VC version only 8105E_VB@: just reserve for 10/100 LAN VBversion only
CPU SB S1G4 SB820M
NB
RS880M
VGA NA
Comment
S0
S1
2 2
S3
S5 S4/AC
S5 S4/ Battery only
S5 S4/AC & Battery don't exist
O O O O O
X
O O O O
X
O
XX X
OO OO
X
X
XX X
BTO (Build-To-Order) Option Table
Function
Description
Explain
BTO
Camera
( C )
CAM@
SMBUS Control Table
I2C / SMBUS ADDRESSING
3 3
DEVICE
DDR SO-DIMM 0 DDR SO-DIMM 1
EC SM Bus1 address
Device Address Smart Battery EC KB926E0
HEX 16H
0001 011X b
HEX
ADDRESS
1 0 1 0 0 0 0 0A0 1 0 1 0 0 0 1 0A2
EC SM Bus2 address
HEX
Device EMC1032-1 CPU EC KB926E0
98H
Address
1001 100X b
EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 I2C_CLK I2C_DATA DDC_CLK0 DDC_DATA0
SCL0 SDA0 SCL1 SDA1
SOURCE
KB926
KB926
RS880M
RS880M
SB820
SB820
BATT
V
CPU THERMAL SENSOR
V
SODIMM
I / II
CLK GEN
VV
WLAN
V
LCD DDC ROM
V
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
401982
401982
440Wednesday, September 01, 2010
440Wednesday, September 01, 2010
440Wednesday, September 01, 2010
E
B
B
B
A
+1.1VS
250 mil
1
C1
C1 10U_0805_10V6K
10U_0805_10V6K
1 1
2
1
C2
C2 10U_0805_10V6K
10U_0805_10V6K
2
Near CPU SocketVLDT CAP.
1
C3
C3
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C4
C4
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
B
1
C5
C5 180P_0402_50V8J
180P_0402_50V8J
2
1
C6
C6 180P_0402_50V8J
180P_0402_50V8J
2
C
D
E
VLDT_B0 VLDT_B1 VLDT_B2 VLDT_B3
H_CADOP[0..15] H_CADON[0..15]
+1.1VS
AE2 AE3 AE4 AE5
AD1 AC1 AC2 AC3 AB1 AA1 AA2 AA3 W2 W3 V1 U1 U2 U3 T1 R1 AD4 AD3 AD5 AC5 AB4 AB3 AB5 AA5 Y5 W5 V4 V3 V5 U5 T4 T3
Y1 W1 Y4 Y3
R2 R3 T5 R5
1 2
H_CADOP0 H_CADON0 H_CADOP1 H_CADON1 H_CADOP2 H_CADON2 H_CADOP3 H_CADON3 H_CADOP4 H_CADON4 H_CADOP5 H_CADON5 H_CADOP6 H_CADON6 H_CADOP7 H_CADON7 H_CADOP8 H_CADON8 H_CADOP9 H_CADON9 H_CADOP10 H_CADON10 H_CADOP11 H_CADON11 H_CADOP12 H_CADON12 H_CADOP13 H_CADON13 H_CADOP14 H_CADON14 H_CADOP15 H_CADON15
H_CADOP[0..15] <11> H_CADON[0..15] <11>H_CADIN[0..15]<11>
C7
C7 10U_0805_10V6K
10U_0805_10V6K
< To NB >< From NB >
H_CLKOP0 <11> H_CLKON0 <11> H_CLKOP1 <11> H_CLKON1 <11>
H_CTLOP0 <11> H_CTLON0 <11> H_CTLOP1 <11> H_CTLON1 <11>
< VLDT_A & VLDT_B : HyperTransport I/O ring power >
H_CADIP[0..15]<11>
2 2
H_CLKIP0<11> H_CLKIN0<11> H_CLKIP1<11> H_CLKIN1<11>
H_CTLIP0<11>
3 3
H_CTLIN0<11> H_CTLIP1<11> H_CTLIN1<11>
H_CADIP[0..15] H_CADIN[0..15]
VLDT=500mA
H_CADIP0 H_CADIN0 H_CADIP1 H_CADIN1 H_CADIP2 H_CADIN2 H_CADIP3 H_CADIN3 H_CADIP4 H_CADIN4 H_CADIP5 H_CADIN5 H_CADIP6 H_CADIN6 H_CADIP7 H_CADIN7 H_CADIP8 H_CADIN8 H_CADIP9 H_CADIN9 H_CADIP10 H_CADIN10 H_CADIP11 H_CADIN11 H_CADIP12 H_CADIN12 H_CADIP13 H_CADIN13 H_CADIP14 H_CADIN14 H_CADIP15 H_CADIN15
+1.1VS
JCPUA
JCPUA
D1
VLDT_A0
D2
VLDT_A1
D3
VLDT_A2
D4
VLDT_A3
E3
L0_CADIN_H0
E2
L0_CADIN_L0
E1
L0_CADIN_H1
F1
L0_CADIN_L1
G3
L0_CADIN_H2
G2
L0_CADIN_L2
G1
L0_CADIN_H3
H1
L0_CADIN_L3
J1
L0_CADIN_H4
K1
L0_CADIN_L4
L3
L0_CADIN_H5
L2
L0_CADIN_L5
L1
L0_CADIN_H6
M1
L0_CADIN_L6
N3
L0_CADIN_H7
N2
L0_CADIN_L7
E5
L0_CADIN_H8
F5
L0_CADIN_L8
F3
L0_CADIN_H9
F4
L0_CADIN_L9
G5
L0_CADIN_H10
H5
L0_CADIN_L10
H3
L0_CADIN_H11
H4
L0_CADIN_L11
K3
L0_CADIN_H12
K4
L0_CADIN_L12
L5
L0_CADIN_H13
M5
L0_CADIN_L13
M3
L0_CADIN_H14
M4
L0_CADIN_L14
N5
L0_CADIN_H15
P5
L0_CADIN_L15
J3
L0_CLKIN_H0
J2
L0_CLKIN_L0
J5
L0_CLKIN_H1
K5
L0_CLKIN_L1
N1
L0_CTLIN_H0
P1
L0_CTLIN_L0
P3
L0_CTLIN_H1
P4
L0_CTLIN_L1
FOX_PZ6382A-284S-41F_Champlian
FOX_PZ6382A-284S-41F_Champlian CONN@
CONN@
HT LINK
HT LINK
L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15
L0_CLKOUT_H0 L0_CLKOUT_L0 L0_CLKOUT_H1 L0_CLKOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
< FAN Control Circuit : Vout = 1.6 x Vset >
+5VS
1A
GND GND GND GND
C1119
C1119
8 7 6 5
2
1
B
2
@
@ C1121
C1121 1000P_0402_25V8J
1000P_0402_25V8J
1
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
+FAN1
JFAN
JFAN
1
1
2
2
3
3
4
GND
5
GND
ACES_85204-0300N
ACES_85204-0300N CONN@
CONN@
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
+3VS
12
R795
R795 10K_0402_5%
10K_0402_5%
2
@
@ C1122
C1122
0.01U_0402_25V7K
0.01U_0402_25V7K
1
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
FAN_SPEED1 <28>
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
401982
401982
540Wednesday, September 01, 2010
540Wednesday, September 01, 2010
540Wednesday, September 01, 2010
E
of
B
B
B
+FAN1
1
C1120
C1120 10U_0805_10V4Z
10U_0805_10V4Z
2
4 4
EN_DFAN1<28>
A
10U_0805_10V4Z
10U_0805_10V4Z
U31
U31
1
EN
2
VIN
3
VOUT
4
VSET
APL5607KI-TRG_SO8
APL5607KI-TRG_SO8
+1.5V
< DDR2 VREF is 0.5 ratio >
A
B
C
D
E
< Processor DDR3 Memory Interface >
< Close to CPU >
R1
R1 1K_0402_1%
1K_0402_1%
1 2
R2
R2
1 1
1K_0402_1%
1K_0402_1%
1 2
2 2
< To SO_DIMMA >
< To SO_DIMMA >
< To SO_DIMMA >
< To SO_DIMMA >
< To SO_DIMMA >
3 3
< To SO_DIMMA >
< To SO_DIMMA >
+MCH_REF
1
C9
C9
0.1U_0402_16V7K
0.1U_0402_16V7K
2
Place them close to CPU within 1"
+1.5V
DDR_A_ODT0<9> DDR_A_ODT1<9>
DDR_CS0_DIMMA#<9> DDR_CS1_DIMMA#<9> DDR_CS0_DIMMB# <10>
DDR_CKE0_DIMMA<9> DDR_CKE1_DIMMA<9>
DDR_A_CLK0<9> DDR_A_CLK#0<9>
DDR_A_CLK1<9> DDR_A_CLK#1<9> DDR_A_MA[15..0]<9>
DDR_A_BS#0<9> DDR_A_BS#1<9> DDR_A_BS#2<9>
DDR_A_RAS#<9> DDR_A_CAS#<9> DDR_A_WE#<9>
1
C8
C8 1000P_0402_25V8J
1000P_0402_25V8J
2
R4 39.2_0402_1%R4 39.2_0402_1%
1 2
R5 39.2_0402_1%R5 39.2_0402_1%
1 2
MEM_MA_RST#<9>
VDDR5 VDDR6 VDDR7 VDDR8 VDDR9
+1.05VS+1.05VS
W10 AC10 AB10
< VTT regulator voltage >
AA10 A10
Y10
+MCH_REF
W17
MEM_MB_RST#
B18
DDR_B_ODT0
W26
DDR_B_ODT1
W23 Y26
V26
DDR_CS1_DIMMB#
W25 U22
DDR_CKE0_DIMMB
J25
DDR_CKE1_DIMMB
H26
DDR_B_CLK0
P22
DDR_B_CLK#0
R22 A17 A18 AF18 AF17
DDR_B_CLK1
R26
DDR_B_CLK#1
R25
DDR_B_MA0
P24
DDR_B_MA1
N24
DDR_B_MA2
P26
DDR_B_MA3
N23
DDR_B_MA4
N26
DDR_B_MA5
L23
DDR_B_MA6
N25
DDR_B_MA7
L24
DDR_B_MA8
M26
DDR_B_MA9
K26
DDR_B_MA10
T26
DDR_B_MA11
L26
DDR_B_MA12
L25
DDR_B_MA13
W24
DDR_B_MA14
J23
DDR_B_MA15
J24
DDR_B_BS#0
R24
DDR_B_BS#1
U26
DDR_B_BS#2
J26
DDR_B_RAS#
U25
DDR_B_CAS#
U24
DDR_B_WE#
U23
JCPUB
JCPUB
D10
VDDR1
MEM:CMD/CTRL/CLK
MEM:CMD/CTRL/CLK
C10
VDDR2
B10
VDDR3
AD10
MEM_P MEM_N VTT_SENSE
MEM_MA_RST#
DDR_A_ODT0 DDR_A_ODT1
DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS0_DIMMB#
DDR_CKE0_DIMMA DDR_CKE1_DIMMA
DDR_A_CLK0 DDR_A_CLK#0
DDR_A_CLK1 DDR_A_CLK#1
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15
DDR_A_BS#0 DDR_A_BS#1 DDR_A_BS#2
DDR_A_RAS# DDR_A_CAS# DDR_A_WE#
VDDR4
AF10
MEMZP
AE10
MEMZN
H16
MA_RESET_L
T19
MA0_ODT0
V22
MA0_ODT1
U21
MA1_ODT0
V19
MA1_ODT1
T20
MA0_CS_L0
U19
MA0_CS_L1
U20
MA1_CS_L0
V20
MA1_CS_L1
J22
MA_CKE0
J20
MA_CKE1
N19
MA_CLK_H5
N20
MA_CLK_L5
E16
MA_CLK_H1
F16
MA_CLK_L1
Y16
MA_CLK_H7
AA16
MA_CLK_L7
P19
MA_CLK_H4
P20
MA_CLK_L4
N21
MA_ADD0
M20
MA_ADD1
N22
MA_ADD2
M19
MA_ADD3
M22
MA_ADD4
L20
MA_ADD5
M24
MA_ADD6
L21
MA_ADD7
L19
MA_ADD8
K22
MA_ADD9
R21
MA_ADD10
L22
MA_ADD11
K20
MA_ADD12
V24
MA_ADD13
K24
MA_ADD14
K19
MA_ADD15
R20
MA_BANK0
R23
MA_BANK1
J21
MA_BANK2
R19
MA_RAS_L
T22
MA_CAS_L
T24
MA_WE_L
FOX_PZ6382A-284S-41F_Champlian
FOX_PZ6382A-284S-41F_Champlian CONN@
CONN@
VDDR_SENSE
MEMVREF
MB_RESET_L
MB0_ODT0 MB0_ODT1 MB1_ODT0
MB0_CS_L0 MB0_CS_L1 MB1_CS_L0
MB_CKE0 MB_CKE1
MB_CLK_H5 MB_CLK_L5 MB_CLK_H1 MB_CLK_L1 MB_CLK_H7 MB_CLK_L7 MB_CLK_H4 MB_CLK_L4
MB_ADD0 MB_ADD1 MB_ADD2 MB_ADD3 MB_ADD4 MB_ADD5 MB_ADD6 MB_ADD7 MB_ADD8
MB_ADD9 MB_ADD10 MB_ADD11 MB_ADD12 MB_ADD13 MB_ADD14 MB_ADD15
MB_BANK0 MB_BANK1 MB_BANK2
MB_RAS_L MB_CAS_L
MB_WE_L
DDR_B_MA[15..0] <10>
T1PAD T1PAD
MEM_MB_RST# <10> DDR_B_ODT0 <10>
DDR_B_ODT1 <10>
DDR_CS1_DIMMB# <10>
DDR_CKE0_DIMMB <10> DDR_CKE1_DIMMB <10>
DDR_B_CLK0 <10> DDR_B_CLK#0 <10>
DDR_B_CLK1 <10> DDR_B_CLK#1 <10>
DDR_B_BS#0 <10> DDR_B_BS#1 <10> DDR_B_BS#2 <10>
DDR_B_RAS# <10> DDR_B_CAS# <10> DDR_B_WE# <10>
< To SO_DIMMB >
< To SO_DIMMB >
< To SO_DIMMB >
< To SO_DIMMB >
< To SO_DIMMB >
< To SO_DIMMB >
< To SO_DIMMB >
DDR_B_D[63..0]<10>
< From/To SO_DIMMB >
DDR_B_DM[7..0]<10> DDR_A_DM[7..0] <9>
< To SO_DIMMB > < To SO_DIMMA >
DDR_B_DQS0<10> DDR_B_DQS#0<10> DDR_B_DQS1<10> DDR_B_DQS#1<10> DDR_B_DQS2<10> DDR_B_DQS#2<10> DDR_B_DQS3<10> DDR_B_DQS#3<10> DDR_B_DQS4<10> DDR_B_DQS#4<10> DDR_B_DQS5<10> DDR_B_DQS#5<10> DDR_B_DQS6<10> DDR_B_DQS#6<10> DDR_B_DQS7<10> DDR_B_DQS#7<10>
< From/To SO_DIMMB > < From/To SO_DIMMA >
DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63
DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7
DDR_B_DQS0 DDR_B_DQS#0 DDR_B_DQS1 DDR_B_DQS#1 DDR_B_DQS2 DDR_B_DQS#2 DDR_B_DQS3 DDR_B_DQS#3 DDR_B_DQS4 DDR_B_DQS#4 DDR_B_DQS5 DDR_B_DQS#5 DDR_B_DQS6 DDR_B_DQS#6 DDR_B_DQS7 DDR_B_DQS#7
JCPUC
JCPUC
MEM:DATA
MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7 MB_DATA8 MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15 MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23 MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31 MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39 MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47 MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55 MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63
MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7
MB_DQS_H0 MB_DQS_L0 MB_DQS_H1 MB_DQS_L1 MB_DQS_H2 MB_DQS_L2 MB_DQS_H3 MB_DQS_L3 MB_DQS_H4 MB_DQS_L4 MB_DQS_H5 MB_DQS_L5 MB_DQS_H6 MB_DQS_L6 MB_DQS_H7 MB_DQS_L7
MEM:DATA C11 A11 A14 B14 G11 E11 D12 A13 A15 A16 A19 A20 C14 D14 C18 D18 D20 A21 D24 C25 B20 C20 B24 C24 E23 E24 G25 G26 C26 D26 G23 G24
AA24 AA23 AD24 AE24 AA26 AA25 AD26 AE25 AC22 AD22 AE20 AF20 AF24 AF23 AC20 AD20 AD18 AE18 AC14 AD14 AF19 AC18 AF16 AF15 AF13 AC12 AB11
Y11
AE14 AF14 AF11 AD11
A12 B16 A22 E25
AB26 AE22 AC16 AD12
C12 B12 D16 C16 A24 A23 F26 E26
AC25 AC26 AF21 AF22 AE16 AD16 AF12 AE12
FOX_PZ6382A-284S-41F_Champlian
FOX_PZ6382A-284S-41F_Champlian CONN@
CONN@
MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7 MA_DATA8
MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15 MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23 MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31 MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39 MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47 MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55 MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63
MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7
MA_DQS_H0 MA_DQS_L0 MA_DQS_H1 MA_DQS_L1 MA_DQS_H2 MA_DQS_L2 MA_DQS_H3 MA_DQS_L3 MA_DQS_H4 MA_DQS_L4 MA_DQS_H5 MA_DQS_L5 MA_DQS_H6 MA_DQS_L6 MA_DQS_H7 MA_DQS_L7
G12 F12 H14 G14 H11 H12 C13 E13 H15 E15 E17 H17 E14 F14 C17 G17 G18 C19 D22 E20 E18 F18 B22 C23 F20 F22 H24 J19 E21 E22 H20 H22 Y24 AB24 AB22 AA21 W22 W21 Y22 AA22 Y20 AA20 AA18 AB18 AB21 AD21 AD19 Y18 AD17 W16 W14 Y14 Y17 AB17 AB15 AD15 AB13 AD13 Y12 W11 AB14 AA14 AB12 AA12
E12 C15 E19 F24 AC24 Y19 AB16 Y13
G13 H13 G16 G15 C22 C21 G22 G21 AD23 AC23 AB19 AB20 Y15 W15 W12 W13
DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9
DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63
DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7
DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS7 DDR_A_DQS#7
DDR_A_D[63..0] <9>
< From/To SO_DIMMA >
DDR_A_DQS0 <9> DDR_A_DQS#0 <9> DDR_A_DQS1 <9> DDR_A_DQS#1 <9> DDR_A_DQS2 <9> DDR_A_DQS#2 <9> DDR_A_DQS3 <9> DDR_A_DQS#3 <9> DDR_A_DQS4 <9> DDR_A_DQS#4 <9> DDR_A_DQS5 <9> DDR_A_DQS#5 <9> DDR_A_DQS6 <9> DDR_A_DQS#6 <9> DDR_A_DQS7 <9> DDR_A_DQS#7 <9>
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
401982
401982
640Wednesday, September 01, 2010
640Wednesday, September 01, 2010
640Wednesday, September 01, 2010
E
B
B
B
A
< Filtered PLL Supply Voltage >
12
R10
R10 169_0402_1%
169_0402_1%
+2.5VDDA+2.5VS
+2.5VDDA
1
C14
C14
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
CPU_CLKIN_SC_P
CPU_CLKIN_SC_N
L1 FBM_L11_201209_300L_0805L1 FBM_L11_201209_300L_0805
1 2
1
+
+
C11
C11
@
@
150U_B2_6.3VM_R45M
150U_B2_6.3VM_R45M
2
1 1
< 200-MHz PLL Reference Clock >
CLK_CPU_BCLK<18>
CLK_CPU_BCLK#<18>
+1.5V
R22 510_0402_5%R22 510_0402_5%
2 2
R28 1K_0402_5%R28 1K_0402_5%
R27 510_0402_5%R27 510_0402_5%
1 2 R29 1K_0402_5%R29 1K_0402_5% R30 1K_0402_5%R30 1K_0402_5% R31 1K_0402_5%R31 1K_0402_5% R32 1K_0402_5%R32 1K_0402_5% R33 1K_0402_5%R33 1K_0402_5% R34 1K_0402_5%R34 1K_0402_5% R265 1K_0402_5%R265 1K_0402_5% R35 1K_0402_5%R35 1K_0402_5%
1
C12
C12
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
C16
C16 3900P_0402_50V7K
3900P_0402_50V7K
1 2
C15
C15 3900P_0402_50V7K
3900P_0402_50V7K
1 2
Address:100_1100 Place close to CPU wihtin 1.5"
12 12
12 12 12 12 12 12 12 12
VDDA=300mA
1
C13
C13 3300P_0402_50V7K
3300P_0402_50V7K
2
CPU_TEST25H
CPU_TEST27
CPU_TEST25L CPU_TEST12 CPU_TEST18 CPU_TEST19 CPU_TEST20 CPU_TEST21 CPU_TEST22 CPU_TEST23 CPU_TEST24
B
+2.5VDDA
CPU_CLKIN_SC_P CPU_CLKIN_SC_N
LDT_RST# H_PWRGD LDT_STOP#
R12 1K_0402_5%R12 1K_0402_5%
+1.5V
R14 1K_0402_5%R14 1K_0402_5%
+1.5V
R15 44.2_0402_1%R15 44.2_0402_1% R16 44.2_0402_1%R16 44.2_0402_1%
+1.1VS
CPU_VDD0_RUN_FB_H<38> CPU_VDD0_RUN_FB_L<38>
1 2 1 2
1 2 1 2
CPU_SIC CPU_SID
CPU_HTREF0 CPU_HTREF1
CPU_VDD0_RUN_FB_H CPU_VDD0_RUN_FB_L
CPU_DBRDY CPU_TMS CPU_TCK CPU_TRST# CPU_TDI
CPU_TEST23 CPU_TEST18
CPU_TEST19 CPU_TEST25H
CPU_TEST25L CPU_TEST21
CPU_TEST20 CPU_TEST24 CPU_TEST22 CPU_TEST12 CPU_TEST27
R24 0_0402_5%R24 0_0402_5%
1 2
T2 PADT2 PAD
C
JCPUD
JCPUD
F8
VDDA1
F9
VDDA2
A9
CLKIN_H
A8
CLKIN_L
B7
RESET_L
A7
PWROK
F10
LDTSTOP_L
C6
LDTREQ_L
AF4
SIC
AF5
SID
AE6
ALERT_L
R6
HT_REF0
P6
HT_REF1
F6
VDD0_FB_H
E6
VDD0_FB_L
Y6
VDD1_FB_H
AB6
VDD1_FB_L
G10
DBRDY
AA9
TMS
AC9
TCK
AD9
TRST_L
AF9
TDI
AD7
TEST23
H10
TEST18
G9
TEST19
E9
TEST25_H
E8
TEST25_L
AB8
TEST21
AF7
TEST20
AE7
TEST24
AE8
TEST22
AC8
TEST12
AF8
TEST27
C2
TEST9
AA6
TEST6
A3
RSVD1
A5
RSVD2
B3
RSVD3
B5
RSVD4
C1
RSVD5
FOX_PZ6382A-284S-41F_Champlian
FOX_PZ6382A-284S-41F_Champlian CONN@
CONN@
VSS
RSVD11
SVC SVD
THERMTRIP_L
PROCHOT_L
MEMHOT_L
THERMDC THERMDA
VDDIO_FB_H VDDIO_FB_L
VDDNB_FB_H VDDNB_FB_L
DBREQ_L
TDO
TEST28_H
TEST28_L
TEST17 TEST16 TEST15 TEST14
TEST7
TEST10
TEST8
TEST29_H
TEST29_L
RSVD10
RSVD9 RSVD8 RSVD7 RSVD6
M11 W18
CPU_SVC
A6
CPU_SVD
A4
< Serial VID Interface clock & data >
CPU_THERMTRIP#_R
AF6
CPU_PROCHOT#
AC7 AA8
W7 W8
W9 Y9
H6 G6
E10 AE9
J7 H8
D7 E7 F7 C7
C3 K8
C4
C9 C8
H18 H19 AA7 D5 C5
T3PAD T3PAD
THERMDC_CPU THERMDA_CPU
T15PAD T15PAD T16PAD T16PAD
CPU_VDDNB_RUN_FB_H CPU_VDDNB_RUN_FB_L
CPU_DBREQ#
CPU_TDO
CPU_TEST17 CPU_TEST16 CPU_TEST15 CPU_TEST14
CPU_TEST29_H_FBCLKOUT_P CPU_TEST29_L_FBCLKOUT_N
D
CPU_SVC <38> CPU_SVD <38>
CPU_VDDNB_RUN_FB_H <38> CPU_VDDNB_RUN_FB_L <38>
+1.5V
T4PAD T4PAD T5PAD T5PAD T6PAD T6PAD T7PAD T7PAD
CPU_THERMTRIP#_R
R25 80.6_0402_1%R25 80.6_0402_1%
R11 300_0402_5%R11 300_0402_5%
+1.5V
CPU_PROCHOT#
route as differential as short as possible testpoint under package
1 2
R7
R7 1K_0402_5%
1K_0402_5%
1 2
12
1 2
R6
R6 10K_0402_5%
10K_0402_5%
B
B
2
Q1
Q1
E
E
3 1
C
C
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
CPU_SVC CPU_SVD
R13 0_0402_5%@R13 0_0402_5%@
1 2
H_THERMTRIP# <19>
E
1 2 1 2
+1.5V
R191K_0402_5% R191K_0402_5% R201K_0402_5% R201K_0402_5%
H_PROCHOT# <18>
+1.5VS
R17
R17 300_0402_5%
3 3
LDT_RST#<18>
H_PWRGD<18,38>
4 4
LDT_STOP#<12,18>
300_0402_5%
1 2
LDT_RST#
1
C17
C17
@
@
0.01U_0402_25V7K
0.01U_0402_25V7K
2
+1.5VS
R21
R21 300_0402_5%
300_0402_5%
1 2
H_PWRGD
1
C19
C19
@
@
0.1U_0402_16V7K
0.1U_0402_16V7K
2
+1.5VS
R18
R18 300_0402_5%
300_0402_5%
1 2
LDT_STOP#
1
C18
C18
@
@
0.01U_0402_25V7K
0.01U_0402_25V7K
2
A
R40 300_0402_5%R40 300_0402_5%
+1.5V
+1.5V
1 2 R39 220_0402_5%R39 220_0402_5%
1 2
R38 220_0402_5%R38 220_0402_5%
1 2
R37 220_0402_5%R37 220_0402_5%
1 2
R36 220_0402_5%R36 220_0402_5%
1 2
B
CPU_DBREQ# CPU_DBRDY CPU_TCK CPU_TMS CPU_TDI CPU_TRST# CPU_TDO
+1.5V
< HDT Connector >
JP2
JP2
2
1
4
3
6
5
8
7
10
9
12
11
14
13
16
15
18
17
20
19
22
21
2423 26
SAMTEC_ASP-68200-07
SAMTEC_ASP-68200-07 CONN@
CONN@
Security Classification
Security Classification
Security Classification
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Issued Date
Issued Date
LDT_RST#
C
0.1U_0402_16V7K
0.1U_0402_16V7K
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
+3VS
1
C20
C20
Compal Secret Data
Compal Secret Data
Compal Secret Data
C21
C21
1 2
2
@
@
R44
R44 1 2
+3VS
10K_0402_5%
10K_0402_5%
Deciphered Date
Deciphered Date
Deciphered Date
2200P_0402_50V7K
2200P_0402_50V7K
3/30 Change U1 ADM1032 to EMC1402 for cost down
THERMDC_CPU
CPU_THERM#
D
< Thermal Sensor >
U1
U1
1
VDD
2
DP
3
DN
4
THERM#
EMC1402-1-ACZL-TR_MSOP8
EMC1402-1-ACZL-TR_MSOP8
Address:0100_1100 EMC1402-1 Address:0100_1101 EMC1402-2
8
SMCLK
7
SMDATA
6
ALERT#
5
GND
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
EC_SMB_CK2 EC_SMB_DA2THERMDA_CPU
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
EC_SMB_CK2 <28> EC_SMB_DA2 <28>
1 2
R41 10K_0402_5%
R41 10K_0402_5%
@
@
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
401982
401982
+3VS
740Wednesday, September 01, 2010
740Wednesday, September 01, 2010
740Wednesday, September 01, 2010
E
B
B
B
A
VDD decoupling : +CPU_CORE
+CPU_CORE
1
+
+
C90
C90 @
@
2
1
+
+
C89
C89
2
1
+
+
C25
C25
2
330U_X_2VM_R6M
330U_X_2VM_R6M
1
+
+
C24
C24 @
@
2
330U_X_2VM_R6M
330U_X_2VM_R6M
1
C45
C45 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C51
C51
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C67
C67 180P_0402_50V8J
180P_0402_50V8J
2
1
C72
C72
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C58
C58
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C77
C77
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C43
C43 22U_0805_6.3V6M
22U_0805_6.3V6M
2
A
1
+
+
C26
C26
2
330U_6.3V_M_R15
330U_6.3V_M_R15
330U_X_2VM_R6M
330U_X_2VM_R6M
1 1
Near CPU Socket
1
+
+
C23
C23 @
@
2
330U_6.3V_M_R15
330U_6.3V_M_R15
330U_X_2VM_R6M
330U_X_2VM_R6M
Near CPU Socket
VDDIO decoupling : DDR SDRAM I/O ring power
+1.5V
1
C44
C44 22U_0805_6.3V6M
22U_0805_6.3V6M
2
Under CPU Socket
+1.5V
2 2
1
C54
C54
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
Between CPU Socket and DIMM
+1.5V
1
C64
C64
0.01U_0402_25V7K
0.01U_0402_25V7K
2
Between CPU Socket and DIMM
+1.5V
180PF Qt'y follow the distance between CPU socket and DIMM0. <2.5inch>
1
C66
C66 180P_0402_50V8J
180P_0402_50V8J
2
Between CPU Socket and DIMM
+1.5V
3 3
1
C71
C71
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
Between CPU Socket and DIMM
+1.05VS
VDDR decoupling.
1
C57
C57
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
Near CPU Socket Right side
+1.05VS
1
C76
C76
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
Near CPU Socket Left side
4 4
+VDDNB decoupling : Northbridge power
+VDDNB
1
C42
C42 22U_0805_6.3V6M
22U_0805_6.3V6M
2
+CPU_CORE +CPU_CORE
1
+
+
2
330U_6.3V_M_R15
330U_6.3V_M_R15
1
+
+
2
330U_6.3V_M_R15
330U_6.3V_M_R15
C96
C96 @
@
C95
C95 @
@
1
C35
C35 22U_0805_6.3V6M
22U_0805_6.3V6M
2
Under CPU Socket
+CPU_CORE +CPU_CORE+CPU_CORE
1
C30
C30 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C46
C46
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C52
C52
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C65
C65
0.01U_0402_25V7K
0.01U_0402_25V7K
2
1
C68
C68 180P_0402_50V8J
180P_0402_50V8J
2
1
C34
C34 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C31
C31 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C47
C47
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C53
C53
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C69
C69 180P_0402_50V8J
180P_0402_50V8J
2
1
C48
C48 180P_0402_50V8J
180P_0402_50V8J
2
C56 Co-layout with C75
1
C73
C73
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C59
C59
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C78
C78
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C49
C49 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C74
C74
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
1
C60
C60
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
1
C79
C79
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
@
@ C75
C75
1
C61
C61 1000P_0402_25V8J
1000P_0402_25V8J
2
1
C80
C80 1000P_0402_25V8J
1000P_0402_25V8J
2
1
C28
C28 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C32
C32 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
+
+
2
330U_D2E_2.5VM_R6M
330U_D2E_2.5VM_R6M
B
1
C50
C50 180P_0402_50V8J
180P_0402_50V8J
2
+1.5V
1
+
+
C56
C56
2
1
C62
C62 1000P_0402_25V8J
1000P_0402_25V8J
2
1
C81
C81 1000P_0402_25V8J
1000P_0402_25V8J
2
B
1
C29
C29 22U_0805_6.3V6M
22U_0805_6.3V6M
2
1
C33
C33 22U_0805_6.3V6M
22U_0805_6.3V6M
2
390U_2.5V_M_R10
390U_2.5V_M_R10
1
C63
C63 180P_0402_50V8J
180P_0402_50V8J
2
1
C82
C82 180P_0402_50V8J
180P_0402_50V8J
2
1
C36
C36
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
Under CPU Socket
1
C39
C39
0.22U_0603_16V4Z
0.22U_0603_16V4Z
2
Under CPU SocketUnder CPU Socket
1
C70
C70 180P_0402_50V8J
180P_0402_50V8J
2
1
C83
C83 180P_0402_50V8J
180P_0402_50V8J
2
C
1
C37
C37
0.01U_0402_25V7K
0.01U_0402_25V7K
2
1
C40
C40
0.01U_0402_25V7K
0.01U_0402_25V7K
2
1
C38
C38 180P_0402_50V8J
180P_0402_50V8J
2
1
C41
C41 180P_0402_50V8J
180P_0402_50V8J
2
C1124 Co-layout with C1125
+1.05VS
+1.05VS
330U_D2E_2.5VM
330U_D2E_2.5VM
@
@
1
C1125
C1125
+
+
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
390U_2.5V_M_R10
390U_2.5V_M_R10
1
C1124
C1124
+
+
2
Compal Secret Data
Compal Secret Data
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
+CPU_CORE
+VDDNB
+1.5V
D
JCPUE
JCPUE
G4
VDD0_1
H2
VDD0_2
J9
VDD0_3
J11
VDD0_4
J13
VDD0_5
J15
VDD0_6
K6
VDD0_7
K10
VDD0_8
K12
VDD0_9
K14
VDD0_10
L4
VDD0_11
L7
VDD0_12
L9
VDD0_13
L11
VDD0_14
L13
VDD0_15
L15
VDD0_16
M2
VDD0_17
M6
VDD0_18
M8
VDD0_19
M10
VDD0_20
N7
VDD0_21
N9
VDD0_22
N11
VDD0_23
K16
VDDNB_1
M16
VDDNB_2
P16
VDDNB_3
T16
VDDNB_4
V16
VDDNB_5
H25
VDDIO1
J17
VDDIO2
K18
VDDIO3
K21
VDDIO4
K23
VDDIO5
K25
VDDIO6
L17
VDDIO7
M18
VDDIO8
M21
VDDIO9
M23
VDDIO10
M25
VDDIO11
N17
VDDIO12
FOX_PZ6382A-284S-41F_Champlian
FOX_PZ6382A-284S-41F_Champlian CONN@
CONN@
JCPUF
JCPUF
AA4
VSS1
AA11
VSS2
AA13
VSS3
AA15
VSS4
AA17
VSS5
AA19
VSS6
AB2
VSS7
AB7
VSS8
AB9
VSS9
AB23
VSS10
AB25
VSS11
AC11
VSS12
AC13
VSS13
AC15
VSS14
AC17
VSS15
AC19
VSS16
AC21
VSS17
AD6
VSS18
AD8
VSS19
AD25
VSS20
AE11
VSS21
AE13
VSS22
AE15
VSS23
AE17
VSS24
AE19
VSS25
AE21
VSS26
AE23
VSS27
B4
VSS28
B6
VSS29
B8
VSS30
B9
VSS31
B11
VSS32
B13
VSS33
B15
VSS34
B17
VSS35
B19
VSS36
B21
VSS37
B23
VSS38
B25
VSS39
D6
VSS40
D8
VSS41
D9
VSS42
D11
VSS43
D13
VSS44
D15
VSS45
D17
VSS46
D19
VSS47
D21
VSS48
D23
VSS49
D25
VSS50
E4
VSS51
F2
VSS52
F11
VSS53
F13
VSS54
F15
VSS55
F17
VSS56
F19
VSS57
F21
VSS58
F23
VSS59
F25
VSS60
H7
VSS61
H9
VSS62
H21
VSS63
H23
VSS64
J4
VSS65
FOX_PZ6382A-284S-41F_Champlian
FOX_PZ6382A-284S-41F_Champlian CONN@
CONN@
D
401982
401982
401982
E
840Wednesday, September 01, 2010
840Wednesday, September 01, 2010
840Wednesday, September 01, 2010
E
+CPU_CORE
P8
VDD1_1
P10
VDD1_2
R4
VDD1_3
R7
VDD1_4
R9
VDD1_5
R11
VDD1_6
T2
VDD1_7
T6
VDD1_8
T8
VDD1_9
T10
VDD1_10
T12
VDD1_11
T14
VDD1_12
U7
VDD1_13
U9
VDD1_14
U11
VDD1_15
U13
VDD1_16
U15
VDD1_17
V6
VDD1_18
V8
VDD1_19
V10
VDD1_20
V12
VDD1_21
V14
VDD1_22
W4
VDD1_23
Y2
VDD1_24
AC4
VDD1_25 VDD1_26
VDDIO27 VDDIO26 VDDIO25 VDDIO24 VDDIO23 VDDIO22 VDDIO21 VDDIO20 VDDIO19 VDDIO18 VDDIO17 VDDIO16 VDDIO15 VDDIO14 VDDIO13
VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98
VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
+1.5V
AD2 Y25
V25 V23 V21 V18 U17 T25 T23 T21 T18 R17 P25 P23 P21 P18
J6 J8 J10 J12 J14 J16 J18 K2 K7 K9 K11 K13 K15 K17 L6 L8 L10 L12 L14 L16 L18 M7 M9 AC6 M17 N4 N8 N10 N16 N18 P2 P7 P9 P11 P17 R8 R10 R16 R18 T7 T9 T11 T13 T15 T17 U4 U6 U8 U10 U12 U14 U16 U18 V2 V7 V9 V11 V13 V15 V17 W6 Y21 Y23 N6
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
B
B
B
A
+1.5V +1.5V
JDDRL
+VREF_DQ
1 1
2 2
3 3
4 4
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
2
C84
C84
DDR_CKE0_DIMMA<6>
DDR_CS1_DIMMA#<6>
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1000P_0402_25V8J
1000P_0402_25V8J
0.01U_0402_25V7K
0.01U_0402_25V7K
2
C85
C85
1
DDR_A_DQS#1<6> DDR_A_DQS1<6>
DDR_A_DQS#2<6> DDR_A_DQS2<6>
DDR_A_BS#2<6>
DDR_A_CLK0<6> DDR_A_CLK#0<6>
DDR_A_BS#0<6>
DDR_A_WE#<6>
DDR_A_CAS#<6> DDR_A_ODT0 <6>
DDR_A_DQS#4<6> DDR_A_DQS4<6>
DDR_A_DQS#6<6> DDR_A_DQS6<6>
+3VS
C91
C91
DDR_A_D0 DDR_A_D1
1
DDR_A_DM0
C10
C10
DDR_A_D2
2
DDR_A_D3 DDR_A_D8
DDR_A_D9 DDR_A_DQS#1
DDR_A_DQS1 DDR_A_D10
DDR_A_D11 DDR_A_D16
DDR_A_D17 DDR_A_DQS#2
DDR_A_DQS2 DDR_A_D18
DDR_A_D19 DDR_A_D24
DDR_A_D25 DDR_A_DM3 DDR_A_D26
DDR_A_D27
DDR_CKE0_DIMMA
DDR_A_BS#2 DDR_A_MA12
DDR_A_MA9 DDR_A_MA8
DDR_A_MA5 DDR_A_MA3
DDR_A_MA1 DDR_A_CLK0
DDR_A_CLK#0 DDR_A_MA10
DDR_A_BS#0 DDR_A_WE#
DDR_A_CAS# DDR_A_ODT0 DDR_A_MA13
DDR_CS1_DIMMA#
DDR_A_D32 DDR_A_D33
DDR_A_DQS#4 DDR_A_DQS4
DDR_A_D34 DDR_A_D35
DDR_A_D40 DDR_A_D41
DDR_A_DM5 DDR_A_D42
DDR_A_D43 DDR_A_D48
DDR_A_D49 DDR_A_DQS#6
DDR_A_DQS6 DDR_A_D50
DDR_A_D51 DDR_A_D56
DDR_A_D57 DDR_A_DM7 DDR_A_D58
DDR_A_D59
+0.75VS
1
2
JDDRL
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1 DQS129RESET#
31
VSS11
33
DQ10
35
DQ11
37
VSS13
39
DQ16
41
DQ17
43
VSS15
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25 VSS2261DQS#3
63
DM3
65
VSS23
67
DQ26
69
DQ27
71
VSS25
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
TYCO_2-2013289-1
TYCO_2-2013289-1 CONN@
CONN@
DQ4 DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6 DQ7
VSS8 DQ12 DQ13
VSS10
DM1
VSS12
DQ14 DQ15
VSS14
DQ20 DQ21
VSS16
DM2
VSS17
DQ22 DQ23
VSS19
DQ28 DQ29
VSS21
DQS3
VSS24
DQ30 DQ31
VSS26
CKE1 VDD2
VDD4
VDD6
VDD8
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36 DQ37
VSS30
DM4
VSS31
DQ38 DQ39
VSS33
DQ44 DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46 DQ47
VSS40
DQ52 DQ53
VSS42
DM6
VSS43
DQ54 DQ55
VSS45
DQ60 DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62 DQ63
VSS52
EVENT#
SDA
SCL
VTT2
B
2
DDR_A_D4
4
DDR_A_D5
6 8
DDR_A_DQS#0
10
DDR_A_DQS0
12 14
DDR_A_D6
16
DDR_A_D7
18 20
DDR_A_D12
22
DDR_A_D13
24 26
DDR_A_DM1
28
MEM_MA_RST#
30 32
DDR_A_D14
34
DDR_A_D15
36 38
DDR_A_D20
40
DDR_A_D21
42 44
DDR_A_DM2
46 48
DDR_A_D22
50
DDR_A_D23
52 54
DDR_A_D28
56
DDR_A_D29
58 60
DDR_A_DQS#3
62
DDR_A_DQS3
64 66
DDR_A_D30
68
DDR_A_D31
70 72
DDR_CKE1_DIMMA
74 76
DDR_A_MA15
78
A15 A14
A11
A7 A6
A4 A2
A0
S0#
G2
DDR_A_MA14
80 82
DDR_A_MA11
84
DDR_A_MA7
86 88
DDR_A_MA6
90
DDR_A_MA4
92 94
DDR_A_MA2
96
DDR_A_MA0
98 100
DDR_A_CLK1
102
DDR_A_CLK#1
104 106
DDR_A_BS#1
108
DDR_A_RAS#
110 112
DDR_CS0_DIMMA#
114 116 118
DDR_A_ODT1
120 122 124 126 128
DDR_A_D36
130
DDR_A_D37
132 134
DDR_A_DM4
136 138
DDR_A_D38
140
DDR_A_D39
142 144
DDR_A_D44
146
DDR_A_D45
148 150
DDR_A_DQS#5
152
DDR_A_DQS5
154 156
DDR_A_D46
158
DDR_A_D47
160 162
DDR_A_D52
164
DDR_A_D53
166 168
DDR_A_DM6
170 172
DDR_A_D54
174
DDR_A_D55
176 178
DDR_A_D60
180
DDR_A_D61
182 184
DDR_A_DQS#7
186
DDR_A_DQS7
188 190
DDR_A_D62
192
DDR_A_D63
194 196 198 200 202 204
206
+0.75VS
DDR_A_DQS#0 <6> DDR_A_DQS0 <6>
MEM_MA_RST# <6>
DDR_A_DQS#3 <6> DDR_A_DQS3 <6>
DDR_CKE1_DIMMA <6>
DDR_A_CLK1 <6> DDR_A_CLK#1 <6>
DDR_A_BS#1 <6> DDR_A_RAS# <6>
DDR_CS0_DIMMA# <6>
DDR_A_ODT1 <6>
1
C680
C680
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1000P_0402_25V8J
1000P_0402_25V8J
DDR_A_DQS#5 <6> DDR_A_DQS5 <6>
DDR_A_DQS#7 <6> DDR_A_DQS7 <6>
SMB_CK_DAT0 <10,19> SMB_CK_CLK0 <10,19>
1
C235
C235
2
2
1
0.01U_0402_25V7K
0.01U_0402_25V7K
C
DDR_A_D[0..63] DDR_A_DM[0..7]
DDR_A_MA[0..15]
C351
C351
+VREF_CA
0.1U_0402_16V4Z
0.1U_0402_16V4Z
D
DDR_A_D[0..63] <6>
DDR_A_DM[0..7] <6>
DDR_A_MA[0..15] <6>
+1.5V
R48
R48 1K_0402_1%
1K_0402_1%
+VREF_DQ +VREF_CA
1 2
R49
R49 1K_0402_1%
1K_0402_1%
1 2
< Close to JDDRH & JDDRL >
+1.5V
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C87
C87
1
+0.75VS
2
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C665
C665
2
C88
C88
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C664
C664
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z 2
C640
C640
1
1
C961
C961
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
C641
C641
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C642
C642
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z 2
C643
C643
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C644
C644
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z 2
C645
C645
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.5V
2
C646
C646
1
E
R310
R310 1K_0402_1%
1K_0402_1%
1 2
R315
R315 1K_0402_1%
1K_0402_1%
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z 2
C647
C647
1
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
DIMM_A STD H:5.2 mm
<Address: 00>
A
B
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
401982
401982
940Wednesday, September 01, 2010
940Wednesday, September 01, 2010
940Wednesday, September 01, 2010
E
B
B
B
A
B
C
D
E
DQ4 DQ5
VSS3
VSS6
DQ6 DQ7
VSS8
DM1
DM2
CKE1
CK1
CK1#
BA1
RAS#
NC2
DM4
DM6
SDA SCL
VTT2
+1.5V+1.5V
2
DDR_B_D4
4
DDR_B_D5
6 8
DDR_B_DQS#0
10
DDR_B_DQS0
12 14
DDR_B_D6
16
DDR_B_D7
18 20
DDR_B_D12
22
DDR_B_D13
24 26
DDR_B_DM1
28
MEM_MB_RST#
30 32
DDR_B_D14
34
DDR_B_D15
36 38
DDR_B_D20
40
DDR_B_D21
42 44
DDR_B_DM2
46 48
DDR_B_D22
50
DDR_B_D23
52 54
DDR_B_D28
56
DDR_B_D29
58 60
DDR_B_DQS#3
62
DDR_B_DQS3
64 66
DDR_B_D30
68
DDR_B_D31
70 72
DDR_CKE1_DIMMB
74 76
DDR_B_MA15
78
A15 A14
A11
A7 A6
A4 A2
A0
S0#
G2
DDR_B_MA14
80 82
DDR_B_MA11
84
DDR_B_MA7
86 88
DDR_B_MA6
90
DDR_B_MA4
92 94
DDR_B_MA2
96
DDR_B_MA0
98 100
DDR_B_CLK1
102
DDR_B_CLK#1
104 106
DDR_B_BS#1
108
DDR_B_RAS#
110 112
DDR_CS0_DIMMB#
114
DDR_B_ODT0DDR_B_CAS#
116 118
DDR_B_ODT1
120 122 124 126 128
DDR_B_D36
130
DDR_B_D37
132 134
DDR_B_DM4
136 138
DDR_B_D38
140
DDR_B_D39
142 144
DDR_B_D44
146
DDR_B_D45
148 150
DDR_B_DQS#5
152
DDR_B_DQS5
154 156
DDR_B_D46
158
DDR_B_D47
160 162
DDR_B_D52
164
DDR_B_D53
166 168
DDR_B_DM6
170 172
DDR_B_D54
174
DDR_B_D55
176 178
DDR_B_D60
180
DDR_B_D61
182 184
DDR_B_DQS#7
186
DDR_B_DQS7
188 190
DDR_B_D62
192
DDR_B_D63
194 196 198 200 202 204
206
+0.75VS
DDR_B_DQS#0 <6> DDR_B_DQS0 <6>
MEM_MB_RST# <6>
DDR_B_DQS#3 <6> DDR_B_DQS3 <6>
DDR_CKE1_DIMMB <6>
DDR_B_CLK1 <6> DDR_B_CLK#1 <6>
DDR_B_BS#1 <6> DDR_B_RAS# <6>
DDR_CS0_DIMMB# <6> DDR_B_ODT0 <6>
DDR_B_ODT1 <6>
1000P_0402_25V8J
1000P_0402_25V8J
1
C683
C683
2
DDR_B_DQS#5 <6> DDR_B_DQS5 <6>
DDR_B_DQS#7 <6> DDR_B_DQS7 <6>
SMB_CK_DAT0 <9,19> SMB_CK_CLK0 <9,19>
DDR_B_D[0..63]
DDR_B_DM[0..7]
DDR_B_MA[0..15]
C353
C353
+VREF_CA
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C352
C352
0.1U_0402_16V4Z
1
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
2
+1.5V
2
C666
C666
1
+0.75VS
2
1
DDR_B_D[0..63] <6>
DDR_B_DM[0..7] <6>
DDR_B_MA[0..15] <6>
0.1U_0402_16V4Z
0.1U_0402_16V4Z 2
C667
C667
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z 2
C676
C676
C675
C675
1
2
C668
C668
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C925
C925
2
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z 2
C669
C669
1
2
C670
C670
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.5V
1
+
+
C86
C86 330U_X_2VM_R6M@
330U_X_2VM_R6M@
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z 2
C671
C671
1
2
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C128 Co-layout with C86
0.1U_0402_16V4Z
0.1U_0402_16V4Z 2
C672
C672
1
+1.5V
1
+
+
C128
C128
390U_2.5V_M_R10
390U_2.5V_M_R10
2
C673
C673
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C674
C674
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z 2
C677
C677
1
Place near DIMM2
JDDRH
+VREF_DQ
0.1U_0402_16V4Z
0.1U_0402_16V4Z 1
1
C92
C92
1 1
2 2
3 3
4 4
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
1
C93
C93
C682
C682
2
2
1000P_0402_25V8J
1000P_0402_25V8J
DDR_B_DQS#1<6> DDR_B_DQS1<6>
DDR_B_DQS#2<6> DDR_B_DQS2<6>
DDR_CKE0_DIMMB<6>
DDR_B_BS#2<6>
DDR_B_CLK0<6> DDR_B_CLK#0<6>
DDR_B_BS#0<6>
DDR_B_WE#<6>
DDR_B_CAS#<6>
DDR_CS1_DIMMB#<6>
DDR_B_DQS#4<6> DDR_B_DQS4<6>
DDR_B_DQS#6<6> DDR_B_DQS6<6>
+3VS
+0.75VS
DDR_B_D0 DDR_B_D1
DDR_B_DM0 DDR_B_D2
DDR_B_D3 DDR_B_D8
DDR_B_D9 DDR_B_DQS#1
DDR_B_DQS1 DDR_B_D10
DDR_B_D11 DDR_B_D16
DDR_B_D17 DDR_B_DQS#2
DDR_B_DQS2 DDR_B_D18
DDR_B_D19 DDR_B_D24
DDR_B_D25 DDR_B_DM3 DDR_B_D26
DDR_B_D27
DDR_CKE0_DIMMB
DDR_B_BS#2 DDR_B_MA12
DDR_B_MA9 DDR_B_MA8
DDR_B_MA5 DDR_B_MA3
DDR_B_MA1 DDR_B_CLK0
DDR_B_CLK#0 DDR_B_MA10
DDR_B_BS#0 DDR_B_WE#
DDR_B_MA13 DDR_CS1_DIMMB#
DDR_B_D32 DDR_B_D33
DDR_B_DQS#4 DDR_B_DQS4
DDR_B_D34 DDR_B_D35
DDR_B_D40 DDR_B_D41
DDR_B_DM5 DDR_B_D42
DDR_B_D43 DDR_B_D48
DDR_B_D49 DDR_B_DQS#6
DDR_B_DQS6 DDR_B_D50
DDR_B_D51 DDR_B_D56
DDR_B_D57 DDR_B_DM7 DDR_B_D58
DDR_B_D59
JDDRH
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
9
VSS4
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
25
VSS9
27
DQS#1 DQS129RESET#
31
VSS11
33
DQ10
35
DQ11
37
VSS13
39
DQ16
41
DQ17
43
VSS15
45
DQS#2
47
DQS2
49
VSS18
51
DQ18
53
DQ19
55
VSS20
57
DQ24
59
DQ25 VSS2261DQS#3
63
DM3
65
VSS23
67
DQ26
69
DQ27
71
VSS25
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
83
A12/BC#
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
99
VDD9
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
LOTES_AAA-DDR-111-K01
LOTES_AAA-DDR-111-K01 CONN@
CONN@
DQS#0
DQS0
DQ12 DQ13
VSS10
VSS12
DQ14 DQ15
VSS14
DQ20 DQ21
VSS16 VSS17
DQ22 DQ23
VSS19
DQ28 DQ29
VSS21
DQS3
VSS24
DQ30 DQ31
VSS26
VDD2
VDD4
VDD6
VDD8
VDD10
VDD12
VDD14
ODT0
VDD16
ODT1
VDD18
VREF_CA
VSS28
DQ36 DQ37
VSS30 VSS31
DQ38 DQ39
VSS33
DQ44 DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46 DQ47
VSS40
DQ52 DQ53
VSS42 VSS43
DQ54 DQ55
VSS45
DQ60 DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62 DQ63
VSS52
EVENT#
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
DIMM_B STD H:9.2 mm
<Address: 01>
A
B
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
401982
401982
10 40Wednesday, September 01, 2010
10 40Wednesday, September 01, 2010
10 40Wednesday, September 01, 2010
E
B
B
B
of
A
1 1
< WLAN > < LAN >
2 2
< From SB820 : x4 PCIE A-link >
H_CADON[0..15]
3 3
4 4
H_CADOP[0..15] <5> H_CADON[0..15] <5>
PCIE_PTX_C_IRX_P2<23> PCIE_PTX_C_IRX_N2<23> PCIE_PTX_C_IRX_P3<24> PCIE_PTX_C_IRX_N3<24>
SB_RX0P<18> SB_RX0N<18> SB_RX1P<18> SB_RX1N<18> SB_RX2P<18> SB_RX2N<18> SB_RX3P<18> SB_RX3N<18>
H_CADOP0 H_CADON0 H_CADOP1 H_CADON1 H_CADOP2 H_CADON2 H_CADOP3 H_CADON3 H_CADOP4 H_CADON4 H_CADOP5 H_CADON5 H_CADOP6 H_CADON6 H_CADOP7
H_CLKOP0<5>
H_CLKON0<5>
H_CLKOP1<5>
H_CLKON1<5>
H_CTLOP0<5> H_CTLON0<5>
H_CTLON1<5>
1 2
H_CADON7 H_CADOP8
H_CADON8 H_CADOP9 H_CADON9 H_CADOP10 H_CADON10 H_CADOP11 H_CADON11 H_CADOP12 H_CADON12 H_CADOP13 H_CADON13 H_CADOP14 H_CADON14 H_CADOP15 H_CADON15
< From S1G4 CPU : x16 HT> < To S1G4 CPU : x16 HT>
0718 Place within 1" layout 1:2
R60301_0402_1% R60301_0402_1%
B
H_CTLOP0 H_CTLON0 H_CTLOP1 H_CTLON1
HT_RXCALP HT_RXCALN
AC24 AC25 AB25 AB24 AA24 AA25
W21 W20
AB23 AA22
M22 M23
D4 C4 A3 B3 C2 C1 E5 F5 G5 G6 H5 H6
M8
P7
M7
P5
M5
R8 P8 R6 R5 P4 P3 T4 T3
AE3 AD4 AE2 AD3 AD1 AD2
V5
W6
U5 U6 U8 U7
AA8
Y8
AA7
Y7 AA5 AA6
W5
Y5
Y25 Y24 V22 V23 V25 V24 U24 U25 T25 T24 P22 P23 P25 P24 N24 N25
Y22 Y23
V21 V20 U20 U21 U19 U18
T22 T23
R21 R20
C23 A24
U3B
U3B
GFX_RX0P GFX_RX0N GFX_RX1P GFX_RX1N GFX_RX2P GFX_RX2N GFX_RX3P GFX_RX3N GFX_RX4P GFX_RX4N GFX_RX5P GFX_RX5N
J6
GFX_RX6P
J5
GFX_RX6N
J7
GFX_RX7P
J8
GFX_RX7N
L5
GFX_RX8P
L6
GFX_RX8N GFX_RX9P
L8
GFX_RX9N GFX_RX10P GFX_RX10N GFX_RX11P GFX_RX11N GFX_RX12P GFX_RX12N GFX_RX13P GFX_RX13N GFX_RX14P GFX_RX14N GFX_RX15P GFX_RX15N
GPP_RX0P GPP_RX0N GPP_RX1P GPP_RX1N GPP_RX2P GPP_RX2N GPP_RX3P GPP_RX3N GPP_RX4P GPP_RX4N GPP_RX5P GPP_RX5N
SB_RX0P SB_RX0N SB_RX1P SB_RX1N SB_RX2P SB_RX2N SB_RX3P SB_RX3N
U3A
U3A
HT_RXCAD0P HT_RXCAD0N HT_RXCAD1P HT_RXCAD1N HT_RXCAD2P HT_RXCAD2N HT_RXCAD3P HT_RXCAD3N HT_RXCAD4P HT_RXCAD4N HT_RXCAD5P HT_RXCAD5N HT_RXCAD6P HT_RXCAD6N HT_RXCAD7P HT_RXCAD7N
HT_RXCAD8P HT_RXCAD8N HT_RXCAD9P HT_RXCAD9N HT_RXCAD10P HT_RXCAD10N HT_RXCAD11P HT_RXCAD11N HT_RXCAD12P HT_RXCAD12N HT_RXCAD13P HT_RXCAD13N HT_RXCAD14P HT_RXCAD14N HT_RXCAD15P HT_RXCAD15N
HT_RXCLK0P HT_RXCLK0N HT_RXCLK1P HT_RXCLK1N
HT_RXCTL0P HT_RXCTL0N HT_RXCTL1P HT_RXCTL1N
HT_RXCALP HT_RXCALN
A5
GFX_TX0P
PART 2 OF 6
PART 2 OF 6
PCIE I/F GFX
PCIE I/F GFX
PCIE I/F GPP
PCIE I/F GPP
PCIE I/F SB
PCIE I/F SB
PCE_CALRP(PCE_BCALRP) PCE_CALRN(PCE_BCALRN)
RS780M_FCBGA528880MR1@
RS780M_FCBGA528880MR1@
PART 1 OF 6
PART 1 OF 6
RS780M_FCBGA528880MR1@
RS780M_FCBGA528880MR1@
HT_TXCAD0P HT_TXCAD0N HT_TXCAD1P HT_TXCAD1N HT_TXCAD2P HT_TXCAD2N HT_TXCAD3P HT_TXCAD3N HT_TXCAD4P HT_TXCAD4N HT_TXCAD5P HT_TXCAD5N HT_TXCAD6P HT_TXCAD6N HT_TXCAD7P HT_TXCAD7N
HT_TXCAD8P HT_TXCAD8N HT_TXCAD9P
HT_TXCAD9N HT_TXCAD10P HT_TXCAD10N HT_TXCAD11P HT_TXCAD11N HT_TXCAD12P HT_TXCAD12N HT_TXCAD13P HT_TXCAD13N HT_TXCAD14P HT_TXCAD14N HT_TXCAD15P HT_TXCAD15N
HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N
HYPER TRANSPORT CPU I/F
HYPER TRANSPORT CPU I/F
HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N
GFX_TX0N GFX_TX1P GFX_TX1N GFX_TX2P GFX_TX2N GFX_TX3P GFX_TX3N GFX_TX4P GFX_TX4N GFX_TX5P GFX_TX5N GFX_TX6P GFX_TX6N GFX_TX7P GFX_TX7N GFX_TX8P GFX_TX8N GFX_TX9P GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
GPP_TX0P GPP_TX0N GPP_TX1P GPP_TX1N GPP_TX2P GPP_TX2N GPP_TX3P GPP_TX3N GPP_TX4P GPP_TX4N GPP_TX5P GPP_TX5N
SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N SB_TX3P SB_TX3N
HT_TXCALP HT_TXCALN
B5 A4 B4 C3 B2 D1 D2 E2 E1 F4 F3 F1 F2 H4 H3 H1 H2 J2 J1 K4 K3 K1 K2 M4 M3 M1 M2 N2 N1 P1 P2
AC1 AC2 AB4 AB3 AA2 AA1 Y1 Y2 Y4 Y3 V1 V2
AD7 AE7 AE6 AD6 AB6 AC6 AD5 AE5
AC8 AB8
D24 D25 E24 E25 F24 F25 F23 F22 H23 H22 J25 J24 K24 K25 K23 K22
F21 G21 G20 H21 J20 J21 J18 K17 L19 J19 M19 L18 M21 P21 P18 M18
H24 H25 L21 L20
M24 M25 P19 R18
B24 B25
C
PCIE_ITX_PRX_P2 PCIE_ITX_PRX_N2 PCIE_ITX_PRX_P3 PCIE_ITX_PRX_N3
SB_TX0P_C SB_TX0N_C SB_TX1P_C SB_TX1N_C SB_TX2P_C SB_TX2N_C SB_TX3P_C SB_TX3N_C
PCIE_CALRP PCIE_CALRN
H_CADIP0 H_CADIN0 H_CADIP1 H_CADIN1 H_CADIP2 H_CADIN2 H_CADIP3 H_CADIN3 H_CADIP4 H_CADIN4 H_CADIP5 H_CADIN5 H_CADIP6 H_CADIN6 H_CADIP7 H_CADIN7
H_CADIP8 H_CADIN8 H_CADIP9 H_CADIN9 H_CADIP10 H_CADIN10 H_CADIP11 H_CADIN11 H_CADIP12 H_CADIN12 H_CADIP13 H_CADIN13 H_CADIP14 H_CADIN14 H_CADIP15 H_CADIN15
H_CLKIP0 <5> H_CLKIN0 <5> H_CLKIP1 <5>
H_CTLIP0 H_CTLIN0 H_CTLIP1 H_CTLIN1
HT_TXCALP HT_TXCALN
0718 Place within 1" layout 1:2
H_CLKIN1 <5>
H_CTLIP0 <5>
H_CTLIN0 <5>
H_CTLIP1 <5>H_CTLOP1<5>
H_CTLIN1 <5>
R61 301_0402_1%R61 301_0402_1%
C129 0.1U_0402_16V7KC129 0.1U_0402_16V7K
1 2
C130 0.1U_0402_16V7KC130 0.1U_0402_16V7K
1 2
C131 0.1U_0402_16V7KC131 0.1U_0402_16V7K
1 2
C132 0.1U_0402_16V7KC132 0.1U_0402_16V7K
1 2
C133 0.1U_0402_16V7KC133 0.1U_0402_16V7K
1 2
C134 0.1U_0402_16V7KC134 0.1U_0402_16V7K
1 2
C135 0.1U_0402_16V7KC135 0.1U_0402_16V7K
1 2
C136 0.1U_0402_16V7KC136 0.1U_0402_16V7K
1 2
C137 0.1U_0402_16V7KC137 0.1U_0402_16V7K
1 2
C138 0.1U_0402_16V7KC138 0.1U_0402_16V7K
1 2
C139 0.1U_0402_16V7KC139 0.1U_0402_16V7K
1 2
C140 0.1U_0402_16V7KC140 0.1U_0402_16V7K
1 2
R59 1.27K_0402_1%R59 1.27K_0402_1%
1 2
R58 2K_0402_1%R58 2K_0402_1%
1 2
H_CADIP[0..15]H_CADOP[0..15] H_CADIN[0..15]
1 2
D
PCIE_ITX_C_PRX_P2 <23> PCIE_ITX_C_PRX_N2 <23> PCIE_ITX_C_PRX_P3 <24> PCIE_ITX_C_PRX_N3 <24>
SB_TX0P <18> SB_TX0N <18> SB_TX1P <18> SB_TX1N <18> SB_TX2P <18> SB_TX2N <18> SB_TX3P <18> SB_TX3N <18>
+1.1VS
H_CADIP[0..15] <5> H_CADIN[0..15] <5>
< Transmitter Calibration Resistor to HT_TXCALN >
E
PCIE PORT LIST
PORT PCIE-2
< WLAN > < LAN >
< To SB820 : x4 PCEI A-link>
< TX Impedance Calibration. Connect to GND > < RX Impedance Calibration. Connect to VDDPCIE >
PCIE-3
DEVICE
WLAN LAN
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
401982
401982
11 40Wednesday, September 01, 2010
11 40Wednesday, September 01, 2010
11 40Wednesday, September 01, 2010
E
B
B
B
of
A
+3VS
1 2
+1.8VS
L4 0_0603_5%L4 0_0603_5%
1 1
+1.8VS
1 2
+1.1VS
1 2
+1.8VS
1 2
2 2
+1.8VS
1 2
+1.8VS
1 2
L3
L3 BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
1
C142
C142
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
L6
L6 BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
L2
L2 BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
L5
L5 BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
L7
L7 BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
L9
L9 BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
+AVDD1
1
C144
C144
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
+AVDD2
1
C145
C145
0.1U_0402_16V7K
0.1U_0402_16V7K
2
+AVDDQ
1
C148
C148
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
+NB_PLLVDD
1
C141
C141
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
+NB_HTPVDD
1
C146
C146
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
+VDDA18HTPLL
1
C150
C150
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
+VDDA18PCIEPLL
1
C154
C154
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
UMA_CRT_R<16> UMA_CRT_G<16> UMA_CRT_B<16>
UMA_CRT_HSYNC<15,16> UMA_CRT_VSYNC<15,16> UMA_CRT_CLK<16> UMA_CRT_DATA<16>
PLT_RST#<15,18,23,24,28,29> NB_PWRGD<19>
CPU_LDT_REQ#<18>
HT_REFCLKP<18> HT_REFCLKN<18>
NB_REFCLK_P<18> NB_REFCLK_N<18>
CLK_SBSRC_BCLK<18> CLK_SBSRC_BCLK#<18>
LCD_EDID_CLK<17>
LCD_EDID_DATA<17>
Strap pin
AUX_CAL<15>
B
+AVDD1 +AVDD2 +AVDDQ
R65 715_0402_1%R65 715_0402_1%
1 2
+NB_PLLVDD +NB_HTPVDD
+VDDA18HTPLL +VDDA18PCIEPLL
R66 0_0402_5%R66 0_0402_5%
1 2
NB_LDTSTOP#
NB_REFCLK_P NB_REFCLK_N
R330 4.7K_0402_5%R330 4.7K_0402_5%
R331 4.7K_0402_5%R331 4.7K_0402_5%
LCD_EDID_CLK LCD_EDID_DATA
12 12
T10 PADT10 PAD
T8 PADT8 PAD
AVDD=100mA
NB_RESET#
U3C
U3C
F12
AVDD1(NC)
E12
AVDD2(NC)
F14
AVDDDI(NC)
G15
AVSSDI(NC)
H15
AVDDQ(NC)
H14
AVSSQ(NC)
E17
C_Pr(DFT_GPIO5)
F17
Y(DFT_GPIO2)
F15
COMP_Pb(DFT_GPIO4)
G18
RED(DFT_GPIO0)
G17
REDb(NC)
E18
GREEN(DFT_GPIO1)
F18
GREENb(NC)
E19
BLUE(DFT_GPIO3)
F19
BLUEb(NC)
A11
DAC_HSYNC(PWM_GPIO4)
B11
DAC_VSYNC(PWM_GPIO6)
F8
DAC_SCL(PCE_RCALRN)
E8
DAC_SDA(PCE_TCALRN)
G14
DAC_RSET(PWM_GPIO1)
A12
PLLVDD(NC)
D14
PLLVDD18(NC)
B12
PLLVSS(NC)
H17
VDDA18HTPLL
D7
VDDA18PCIEPLL1
E7
VDDA18PCIEPLL2
D8
SYSRESETb
A10
POWERGOOD
C10
LDTSTOPb
C12
ALLOW_LDTSTOP
C25
HT_REFCLKP
C24
HT_REFCLKN
E11
REFCLK_P/OSCIN(OSCIN)
F11
REFCLK_N(PWM_GPIO3)
T2
GFX_REFCLKP
T1
GFX_REFCLKN
U1
GPP_REFCLKP
U2
GPP_REFCLKN
V4
GPPSB_REFCLKP(SB_REFCLKP)
V3
GPPSB_REFCLKN(SB_REFCLKN)
B9
I2C_CLK
A9
I2C_DATA
B8
DDC_DATA0/AUX0N(NC)
A8
DDC_CLK0/AUX0P(NC)
B7
DDC_CLK1/AUX1P(NC)
A7
DDC_DATA1/AUX1N(NC)
B10
STRP_DATA
G11
RSVD
C8
AUX_CAL(NC)
C
PART 3 OF 6
PART 3 OF 6
RS780M_FCBGA528880MR1@
RS780M_FCBGA528880MR1@
< Dedicated power for the DAC which can affect display quality >
TXOUT_L0P(NC) TXOUT_L0N(NC) TXOUT_L1P(NC) TXOUT_L1N(NC) TXOUT_L2P(NC)
TXOUT_L2N(DBG_GPIO0)
TXOUT_L3P(NC)
TXOUT_L3N(DBG_GPIO2)
TXOUT_U0P(NC)
TXOUT_U1P(PCIE_RESET_GPIO3) TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U3P(PCIE_RESET_GPIO5)
CRT/TVOUT
CRT/TVOUT
PM
PM
CLOCKs PLL PWR
CLOCKs PLL PWR
MIS.
MIS.
TXOUT_U0N(NC)
TXOUT_U2P(NC)
TXOUT_U2N(NC) TXOUT_U3N(NC)
TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3) TXCLK_UP(PCIE_RESET_GPIO4) TXCLK_UN(PCIE_RESET_GPIO1)
VDDLTP18(NC) VSSLTP18(NC)
VDDLT18_1(NC) VDDLT18_2(NC) VDDLT33_1(NC)
LVTM
LVTM
VDDLT33_2(NC)
VSSLT1(VSS) VSSLT2(VSS) VSSLT3(VSS) VSSLT4(VSS) VSSLT5(VSS) VSSLT6(VSS) VSSLT7(VSS)
LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PWM_GPIO2)
TMDS_HPD(NC)
SUS_STAT#(PWM_GPIO5)
THERMALDIODE_P THERMALDIODE_N
HPD(NC)
TESTMODE
LCD_TXOUT0+
A22
LCD_TXOUT0-
B22
LCD_TXOUT1+
A21
LCD_TXOUT1-
B21
LCD_TXOUT2+
B20
LCD_TXOUT-
A20 A19
< LVDS dual channel : channel 1 >
B19 B18
A18 A17 B17 D20 D21 D18
< LVDS dual channel : channel 2 >
D19
LCD_TXCLK+
B16
LCD_TXCLK-
A16 D16 D17
+VDDLTP18
A13 B13
+VDDLT18
A15 B15 A14 B14
C14 D15 C16 C18 C20 E20 C22
E9 F7 G12
TMDS_HPD
D9 D10
D12 AE8
AD8 D13
R84 1.8K_0402_5%R84 1.8K_0402_5%
D
UMA_ENBKL
1 2
LCD_TXOUT0+ <17> LCD_TXOUT0- <17> LCD_TXOUT1+ <17> LCD_TXOUT1- <17> LCD_TXOUT2+ <17> LCD_TXOUT2- <17>
LCD_TXCLK+ <17> LCD_TXCLK- <17>
T9PAD T9PAD
0.1U_0402_16V7K
0.1U_0402_16V7K
R71 0_0402_5%@R71 0_0402_5%@
1 2
SUS_STAT# <15,19>
+VDDLTP18
+VDDLT18
C156
C156
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
1
C153
C153
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
1
4.7U_0805_10V4Z
4.7U_0805_10V4Z 2
2
BLM18PG121SN1D_0603
BLM18PG121SN1D_0603
1
C157
C157
2
UMA_ENVDD <17> UMA_ENBKL <28> UMA_INVT_PWM <17>
< Strap option pin or gate side-port memory IO >
E
L8
L8
L10
L10
+1.8VS
1 2
+1.8VS
1 2
3 3
R68 300_0402_5%R68 300_0402_5%
+1.8VS
4 4
1 2
R366 1K_0402_1%R366 1K_0402_1%
1 2
R987 140_0402_1%R987 140_0402_1%
1 2
R988 150_0402_1%R988 150_0402_1%
1 2
R989 150_0402_1%R989 150_0402_1%
1 2
A
NB_PWRGD
CPU_LDT_REQ#
UMA_CRT_R UMA_CRT_G UMA_CRT_B
+1.8VS
C1256
C1256
1 2
0.1U_0402_16V7K
0.1U_0402_16V7K 2
B
LDT_STOP#<7,18>
1
A
1 2
R981 0_0402_5%
R981 0_0402_5%
B
5
U57
U57
P
4
Y
G
NC7SZ08P5X_NL_SC70-5
NC7SZ08P5X_NL_SC70-5
3
@
@
+1.8VS
R980
R980
2.2K_0402_5%
2.2K_0402_5%
1 2
NB_LDTSTOP#
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
401982
401982
12 40Wednesday, September 01, 2010
12 40Wednesday, September 01, 2010
12 40Wednesday, September 01, 2010
E
B
B
B
2
U3D
U3D
AB12 AE16
V11 AE15 AA12 AB16 AB14 AD14 AD13 AD15 AC16 AE13 AC14
Y14 AD16
AE17 AD17
W12
Y12 AD18 AB13 AB18
V14
V15
B B
W14
AE12 AD12
880MR1@
880MR1@
MEM_A0(NC) MEM_A1(NC) MEM_A2(NC) MEM_A3(NC) MEM_A4(NC) MEM_A5(NC) MEM_A6(NC) MEM_A7(NC) MEM_A8(NC) MEM_A9(NC) MEM_A10(NC) MEM_A11(NC) MEM_A12(NC) MEM_A13(NC)
MEM_BA0(NC) MEM_BA1(NC) MEM_BA2(NC)
MEM_RASb(NC) MEM_CASb(NC) MEM_WEb(NC) MEM_CSb(NC) MEM_CKE(NC) MEM_ODT(NC)
MEM_CKP(NC) MEM_CKN(NC)
MEM_COMPP(NC) MEM_COMPN(NC)
PAR 4 OF 6
PAR 4 OF 6
MEM_DQ0/DVO_VSYNC(NC) MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC) MEM_DQ3/DVO_D0(NC)
MEM_DQ4(NC) MEM_DQ5/DVO_D1(NC) MEM_DQ6/DVO_D2(NC) MEM_DQ7/DVO_D4(NC) MEM_DQ8/DVO_D3(NC) MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC) MEM_DQ11/DVO_D7(NC)
MEM_DQ12(NC)
MEM_DQ13/DVO_D9(NC) MEM_DQ14/DVO_D10(NC) MEM_DQ15/DVO_D11(NC)
MEM_DQS0P/DVO_IDCKP(NC) MEM_DQS0N/DVO_IDCKN(NC)
MEM_DQS1P(NC) MEM_DQS1N(NC)
MEM_DM0(NC)
MEM_DM1/DVO_D8(NC)
SBD_MEM/DVO_I/F
SBD_MEM/DVO_I/F
RS780M_FCBGA528
RS780M_FCBGA528
IOPLLVDD18(NC)
IOPLLVDD(NC)
IOPLLVSS(NC)
MEM_VREF(NC)
AA18 AA20 AA19 Y19 V17 AA17 AA15 Y15 AC20 AD19 AE22 AC18 AB20 AD22 AC22 AD21
Y17 W18 AD20 AE21
W17 AE19
AE23 AE24
AD23 AE18
+1.8VS +1.1VS
1
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet of
1
Date: Sheet of
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
401982
401982
13 40Wednesday, September 01, 2010
13 40Wednesday, September 01, 2010
13 40Wednesday, September 01, 2010
B
B
B
of
A
B
C
D
E
U3E
AE25 AD24 AC23 AB22 AA21
AE11 AD11
AD25
AC12 AA14
AB11 AB15 AB17 AB19 AE20 AB21
M16 R16
H18 G19
D22
W19 U17 R17 M17
M10
R10 AA9
AB9 AD9 AE9 U10
D23 G22
G24 G25 H19
M20 N22
R19 R22 R24 R25 H20 U22
W22 W24 W25
M14 N13
R11 R14
U14 U11 U15
W11 W15
J17 K16 L16
P16 T16
F20 E21
B23 A23
Y20 V18 T17 P17
J10 P10 K10
L10 W9
H9
T10
Y9
F9
G9
A25 E22
J22 L17 L22 L24 L25
P20
V19
Y21
L12
P12 P15
T12
V12
Y18
K11
U3E
VDDHT_1 VDDHT_2 VDDHT_3 VDDHT_4 VDDHT_5 VDDHT_6 VDDHT_7
VDDHTRX_1 VDDHTRX_2 VDDHTRX_3 VDDHTRX_4 VDDHTRX_5 VDDHTRX_6 VDDHTRX_7
VDDHTTX_1 VDDHTTX_2 VDDHTTX_3 VDDHTTX_4 VDDHTTX_5 VDDHTTX_6 VDDHTTX_7 VDDHTTX_8 VDDHTTX_9 VDDHTTX_10 VDDHTTX_11 VDDHTTX_12 VDDHTTX_13
VDDA18PCIE_1 VDDA18PCIE_2 VDDA18PCIE_3 VDDA18PCIE_4 VDDA18PCIE_5 VDDA18PCIE_6 VDDA18PCIE_7 VDDA18PCIE_8 VDDA18PCIE_9 VDDA18PCIE_10 VDDA18PCIE_11 VDDA18PCIE_12 VDDA18PCIE_13 VDDA18PCIE_14 VDDA18PCIE_15
VDD18_1 VDD18_2 VDD18_MEM1(NC) VDD18_MEM2(NC)
U3F
U3F
VSSAHT1 VSSAHT2 VSSAHT3 VSSAHT4 VSSAHT5 VSSAHT6 VSSAHT7 VSSAHT8 VSSAHT9 VSSAHT10 VSSAHT11 VSSAHT12 VSSAHT13 VSSAHT14 VSSAHT15 VSSAHT16 VSSAHT17 VSSAHT18 VSSAHT19 VSSAHT20 VSSAHT21 VSSAHT22 VSSAHT23 VSSAHT24 VSSAHT25 VSSAHT26 VSSAHT27
VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34
PART 5/6
PART 5/6
RS780M_FCBGA528880MR1@
RS780M_FCBGA528880MR1@
PART 6/6
PART 6/6
RS780M_FCBGA528880MR1@
RS780M_FCBGA528880MR1@
VDDPCIE_1 VDDPCIE_2 VDDPCIE_3 VDDPCIE_4 VDDPCIE_5 VDDPCIE_6 VDDPCIE_7 VDDPCIE_8
VDDPCIE_9 VDDPCIE_10 VDDPCIE_11 VDDPCIE_12 VDDPCIE_13 VDDPCIE_14 VDDPCIE_15 VDDPCIE_16 VDDPCIE_17
VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8
VDDC_9 VDDC_10 VDDC_11 VDDC_12
POWER
POWER
VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22
VDD_MEM1(NC) VDD_MEM2(NC) VDD_MEM3(NC) VDD_MEM4(NC) VDD_MEM5(NC) VDD_MEM6(NC)
VDD33_1(NC) VDD33_2(NC)
VSSAPCIE1 VSSAPCIE2 VSSAPCIE3 VSSAPCIE4 VSSAPCIE5 VSSAPCIE6 VSSAPCIE7 VSSAPCIE8
VSSAPCIE9 VSSAPCIE10 VSSAPCIE11 VSSAPCIE12 VSSAPCIE13 VSSAPCIE14 VSSAPCIE15 VSSAPCIE16 VSSAPCIE17 VSSAPCIE18 VSSAPCIE19 VSSAPCIE20 VSSAPCIE21 VSSAPCIE22 VSSAPCIE23 VSSAPCIE24 VSSAPCIE25 VSSAPCIE26 VSSAPCIE27 VSSAPCIE28 VSSAPCIE29 VSSAPCIE30
GROUND
GROUND
VSSAPCIE31 VSSAPCIE32 VSSAPCIE33 VSSAPCIE34 VSSAPCIE35 VSSAPCIE36 VSSAPCIE37 VSSAPCIE38 VSSAPCIE39 VSSAPCIE40
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9
VSS10
2A
L11 0_0805_5%L11 0_0805_5%
+1.1VS
1 1
+1.1VS
+1.8VS
2 2
+1.8VS
1
2
3 3
4 4
12
1
C165
C165
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
2A < IO power for HyperTransport receive interface >
L13 0_0805_5%L13 0_0805_5%
12
C179
C179 10U_0805_10V4Z
10U_0805_10V4Z
2A < IO power for HyperTransport transmit interface >
L14 0_0805_5%L14 0_0805_5%
12
1
C1127
C1127
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
2A < 1.8V IO power for PCI-E graphics, SB, and GPP interfaces >
L15 0_0805_5%L15 0_0805_5%
12
1
C181
C181
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
C197
C197 1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
C166
C166
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C164
C164
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C175
C175
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C1128
C1128
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
< Digital IO power for HyperTransport interface >
1
C167
C167
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C169
C169
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C176
C176
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C185
C185
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C168
C168
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C170
C170
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C177
C177
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C190
C190
0.1U_0402_16V7K
0.1U_0402_16V7K
2
< 1.8V IO transform power >
1
C159
C159
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C161
C161
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C178
C178
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C186
C186
0.1U_0402_16V7K
0.1U_0402_16V7K
2
1
C192
C192
0.1U_0402_16V7K
0.1U_0402_16V7K
2
+VDDHT
+VDDHTRX
+VDDHTTX
+VDDA18PCIE
< Main IO power for PCI-E graphics, SB, and GPP interfaces >
+VDDA11PCIE
A6 B6 C6
VDDA_12=2.5A
A2 B1 D3 D5 E4 G1 G2 G4 H7 J4 R7 L1 L2 L4 L7 M6 N4 P6 R1 R2 R4 V7 U4 V8 V6 W1 W2 W4 W7 W8 Y6 AA4 AB5 AB1 AB7 AC3 AC4 AE1 AE4 AB2
AE14 D11 G8 E14 E15 J15 J12 K14 M11 L15
D6 E6 F6 G7 H8 J9 K9 M9 L9 P9 R9 T9 V9 U9
K12 J14 U16 J11 K15 M12 L14 L11 M13 M15 N12 N14 P11 P13 P14 R12 R15 T11 T15 U12 T14 J16
AE10 AA11 Y11 AD10 AB10 AC10
H11 H12
< 3.3V IO power >
C1820.1U_0402_16V7K C1820.1U_0402_16V7K
C1910.1U_0402_16V7K C1910.1U_0402_16V7K
C1870.1U_0402_16V7K C1870.1U_0402_16V7K
2
2
2
1
1
1
1
C198
C198
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C1731U_0402_6.3V4Z C1731U_0402_6.3V4Z
C1601U_0402_6.3V4Z C1601U_0402_6.3V4Z
C1741U_0402_6.3V4Z C1741U_0402_6.3V4Z
1
1
2
2
C1940.1U_0402_16V7K C1940.1U_0402_16V7K
C1930.1U_0402_16V7K C1930.1U_0402_16V7K
C1800.1U_0402_16V7K C1800.1U_0402_16V7K
2
2
1
1
C1621U_0402_6.3V4Z C1621U_0402_6.3V4Z
1
1
2
2
VDD_CORE:GM=5A/PM=10A< Core power >
C1880.1U_0402_16V7K C1880.1U_0402_16V7K 2
2
1
1
C1630.1U_0402_16V7K C1630.1U_0402_16V7K
2
1
C1950.1U_0402_16V7K C1950.1U_0402_16V7K
C1830.1U_0402_16V7K C1830.1U_0402_16V7K
2
2
1
1
1
C199
C199
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1 2
C17110U_0805_10V4Z C17110U_0805_10V4Z
C17210U_0805_10V4Z C17210U_0805_10V4Z
C11260.1U_0402_16V7K C11260.1U_0402_16V7K
2
1
+NB_CORE
L44FBMA-L11-201209-221LMA30T_0805 L44FBMA-L11-201209-221LMA30T_0805
+1.1VS
C1129 Co-layout with C189
+NB_CORE
1
1
1
C19610U_0805_10V4Z C19610U_0805_10V4Z
C18410U_0805_10V4Z C18410U_0805_10V4Z
2
+3VS
C189330U_D2E_2.5VM
C189330U_D2E_2.5VM
+
+
1
+
+
C1129
2
2
C1129 330U_2.5V_M
330U_2.5V_M
@
@
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
401982
401982
14 40Wednesday, September 01, 2010
14 40Wednesday, September 01, 2010
14 40Wednesday, September 01, 2010
E
B
B
B
of
A
B
C
D
E
< RS880 VSYNC mux at CRT_VSYNC pull High to 3K >
< VSYNC : STRAP_DEBUG_BUS_GPIO_ENABLEb >
Enables the Test Debug Bus using GPIO.
R92
R92 3K_0402_5%
3K_0402_5%
UMA_CRT_VSYNC<12,16>
1 1
12
R93
R93 3K_0402_5%@
3K_0402_5%@
12
< RS880 use register to control PCI-E configure >
< RS880 SUS_STAT# >
R85
R85 150_0402_1%
150_0402_1%
PLT_RST# <12,18,23,24,28,29>
D1
D1 CH751H-40PT_SOD323-2@
CH751H-40PT_SOD323-2@
1 2
AUX_CAL<12>
2 2
SUS_STAT#<12,19>
2 1
< RS880 use HSYNC to enable SIDE PORT (internal pull high) >
1 : Disable (RX881, RS880)
+3VS
0 : Enable (RX881, RS880)
PIN: RS880--> VSYNC#
< DFT_GPIO[4:2] : STRAP_PCIE_GPP_CFG[2:0] >
These pin straps are used to configure PCI-E GPP mode. 000 : 00001 001 : 00010 010 : 01011 011 : 00100 100 : 01010 101 : 01100 111 : 01011
< SUS_SATA# : LOAD_EEPROM_STRAPS >
Selects Loading of STRAPS from EPROM
1 : Bypass the loading of EEPROM straps and use Hardware Default Values 0 : I2C Master can load strap values from EEPROM if connected, or use default values if not connected
RS880:SUS_STAT#
< HSYNC : STRAP_DEBUG_BUS_PCIE_ENABLEb >
RX881: Enables the Test Debug Bus using PCIE bus
R94
R94 3K_0402_5%
3K_0402_5%
UMA_CRT_HSYNC<12,16>
12
+3VS
1 : Disable ( Can still be enabled using nbcfg register access ) 0 : Enable
RS880: Enables Side port memory ( RS780 use HSYNC#)
1. Disable (RS880) 0 : Enable (RS880)
3 3
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
401982
401982
15 40Wednesday, September 01, 2010
15 40Wednesday, September 01, 2010
15 40Wednesday, September 01, 2010
E
B
B
B
of
A
B
< CRT CONNECTOR >
C
+5VS
D
D7
D7
2 3
1
RB491D_SOT23-3
RB491D_SOT23-3
+R_CRT_VCC
E
F1
F1
1.1A_6V_MINISMDC110F-2
1.1A_6V_MINISMDC110F-2
21
+CRT_VCC
1
2
C237
C237
0.1U_0402_16V4Z@
0.1U_0402_16V4Z@
1
D19
D19
DAN217_SC59@
2
3
C242
C242 6P_0402_50V8K
6P_0402_50V8K
R817
R817 10K_0402_5%
10K_0402_5%
D_HSYNC
D_VSYNC
DAN217_SC59@
1 1
L22
L22 NBQ100505T-800Y-N_2P
UMA_CRT_R<12>
UMA_CRT_G<12>
UMA_CRT_B<12>
R99
R99 150_0402_1%
150_0402_1%
UMA_CRT_HSYNC<12,15>
UMA_CRT_VSYNC<12,15>
12
R98
R98 140_0402_1%
140_0402_1%
12
12
2 2
R100
R100 150_0402_1%
150_0402_1%
1
C239
C239 6P_0402_50V8K
6P_0402_50V8K
2
1
C240
C240 6P_0402_50V8K
6P_0402_50V8K
2
C245 0.1U_0402_16V4ZC245 0.1U_0402_16V4Z
1 2
1 2
1 2
1 2
1
C241
C241 6P_0402_50V8K
6P_0402_50V8K
2
NBQ100505T-800Y-N_2P L23
L23 NBQ100505T-800Y-N_2P
NBQ100505T-800Y-N_2P L24
L24 NBQ100505T-800Y-N_2P
NBQ100505T-800Y-N_2P
+CRT_VCC
1
5
P
4
OE#
A2Y
G
U5
U5 SN74AHCT1G125GW_SOT353-5
SN74AHCT1G125GW_SOT353-5
3
+CRT_VCC
1
5
P
4
OE#
A2Y
G
U6
U6 SN74AHCT1G125GW_SOT353-5
SN74AHCT1G125GW_SOT353-5
3
1
2
1 2
1
D20
D20
DAN217_SC59@
DAN217_SC59@
2
3
1
C243
C243 6P_0402_50V8K
6P_0402_50V8K
2
L25 10_0402_5%L25 10_0402_5%
1 2
L26 10_0402_5%L26 10_0402_5%
1 2
2
1
C244
C244 6P_0402_50V8K
6P_0402_50V8K
2
1
2
C247
C247 10P_0402_50V8J@
10P_0402_50V8J@
1
D21
3
D21
DAN217_SC59@
DAN217_SC59@
RED_L
GREEN_L
BLUE_L
+3VS
RED_L D_DDCDATA
GREEN_L HSYNC
+CRT_VCC
HSYNC
VSYNC
1
C248
C248 10P_0402_50V8J@
10P_0402_50V8J@
2
BLUE_L VSYNC
D_DDCCLK
< SYNC SIGNAL >
JCRT
JCRT
6
6
11
11
1
1
7
7
12
12
2
2
8
8
13
13
3
3
9
9
14
4 10 15
5
ALLTO_C10532-11505-L_15P-T
ALLTO_C10532-11505-L_15P-T CONN@
CONN@
16
14
G
17
4
G 10 15 5
12
1
C251
C251 470P_0402_50V8J@
470P_0402_50V8J@
2
+CRT_VCC
R805
R805 2K_0402_1%
2K_0402_1%
12
1
C252
C252 470P_0402_50V8J@
470P_0402_50V8J@
2
R806
R806 2K_0402_1%
2K_0402_1%
D_DDCDATA
< Display Data Channel >
D_DDCCLK
3 3
12
R824
R824
4.7K_0402_5%
4.7K_0402_5%
UMA_CRT_DATA<12>
UMA_CRT_CLK<12>
12
C255
C255
@
@
33P_0402_50V8K
33P_0402_50V8K
12
C256
C256
@
@
33P_0402_50V8K
33P_0402_50V8K
+3VS
R825
R825
4.7K_0402_5%
4.7K_0402_5%
1 2
+3VS
5
Q32B
Q32B 2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
3
4
+3VS
2
Q32A
Q32A 2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
61
FOR EMI
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
401982
401982
16 40Wednesday, September 01, 2010
16 40Wednesday, September 01, 2010
16 40Wednesday, September 01, 2010
E
B
B
B
A
B
C
D
E
+LCD_VDD
12
LCD/PANEL BD. Conn.
D84
CAM@
W=20mils
CAM@
CAM@
1 1
2 2
+3VS
LCD_TXOUT0+<12> LCD_TXOUT0-<12> LCD_TXOUT1+<12> LCD_TXOUT1-<12> LCD_TXOUT2+<12> LCD_TXOUT2-<12> LCD_TXCLK+<12> LCD_TXCLK-<12>
1 2
R808 0_0603_5%
R808 0_0603_5%
USB20_P9_L USB20_N9_L
+3VS_LVDS_CAM
0.1U_0402_16V4Z
0.1U_0402_16V4Z 1 2
C265
C265
JLVDS
JLVDS
112
3
3
5
5
7
7 9910 111112
13
14
13
15
16
15
17
18
17
19
20
19
21
21
22
23
24
23
25
25
26
27
27
28
29
29
30
31
GND1
32
GND2
ACES_87242-3001-09
ACES_87242-3001-09 CONN@
CONN@
CAM@
4 6 8
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
INT_MIC_CLK INT_MIC_DATA INVT_PWM
R983 33_0402_5%R983 33_0402_5% R200 10K_0402_5%R200 10K_0402_5%
+LCDVDD_R
+LCD_INV
68P_0402_50V8J
68P_0402_50V8J
LCD_EDID_CLK <12> LCD_EDID_DATA <12>
12
1 2
2A
L12
L12
12
0_0805_5%
0_0805_5%
1
C266
C266
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
+LCD_INV B+
1
1
C268
C268
0.1U_0402_25V6
0.1U_0402_25V6 2
2
1
2
L45
L45
FBMA-L11-201209-221LMA30T_0805
FBMA-L11-201209-221LMA30T_0805 C263
C263
2 3
AZ5125-02S.R7G
AZ5125-02S.R7G
BKOFF#BKOFF#_R
+LCD_VDD
C267
C267
4.7U_0805_10V4Z
4.7U_0805_10V4Z
12
D84
1
INT_MIC_CLK <26> INT_MIC_DATA <26>
BKOFF# <28>
C152
@C152
@
680P_0402_50V7K
680P_0402_50V7K
EMI
USB20_P9<19>
USB20_N9<19>
EC_INVT_PWM<28>
UMA_INVT_PWM<12>
1
2
+3VS
1
C264
C264
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
4
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
UMA_ENVDD<12>
CAM@
CAM@
1 2
R134 0_0402_5%
R134 0_0402_5%
L20
@L20
@
1
4
WCM-2012-900T_0805
WCM-2012-900T_0805
1 2
R133 0_0402_5%
R133 0_0402_5%
CAM@
CAM@
R96 0_0402_5%@ R96 0_0402_5%@
R897 0_0402_5%R897 0_0402_5%
2
3
1 2
1 2
2
3
R896
R896
100K_0402_5%
100K_0402_5%
Q33A
Q33A
12
USB20_P9_L
USB20_N9_L
INVT_PWMINVT_PWM
R807
R807
150_0603_5%
150_0603_5%
61
12
2
ENVDD
5
R319
R319 10K_0402_5%
10K_0402_5%
+3VS
12
R90
R90 100K_0402_5%
100K_0402_5%
1 2
R91
R91
47K_0402_5%
47K_0402_5%
3
Q33B
Q33B 2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
4
@
@ C27
C27
10P_0402_50V8J
10P_0402_50V8J
Reserve C27, R231 for EMI
C259
C259
C260
C260
+3VS
+LCD_VDD
2
W=60mils
1
1
2
S
S
G
G
0.1U_0402_16V7K
0.1U_0402_16V7K
2
Q4
Q4
D
D
1 3
AO3413_SOT23
AO3413_SOT23
W=60mils Inrush current = 0A
@
@ R23
R23
1 2
10_0402_5%
10_0402_5%
1
2
C262
C262
0.1U_0402_16V7K
0.1U_0402_16V7K
INT_MIC_CLK
0.01U_0402_25V7K
0.01U_0402_25V7K
12
3 3
LCD_EDID_CLK
LCD_EDID_DATA
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
+3VS
R1172.2K_0402_5% R1172.2K_0402_5%
12
R1182.2K_0402_5% R1182.2K_0402_5%
12
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
401982
401982
17 40Wednesday, September 01, 2010
17 40Wednesday, September 01, 2010
17 40Wednesday, September 01, 2010
E
B
B
B
A
B
C
D
E
C572 150P_0402_50V8JC572 150P_0402_50V8J
1 2
A_RST#
C579 0.1U_0402_16V7KC579 0.1U_0402_16V7K
SB_RX0P<11> SB_RX0N<11> SB_RX1P<11> SB_RX1N<11> SB_RX2P<11> SB_RX2N<11> SB_RX3P<11>
1 1
+3VALW
C581
C581
12
5
U21
0.1U_0402_16V4Z
0.1U_0402_16V4Z
A_RST#
@
@
2 2
12
R328 8.2K_0402_5%
R328 8.2K_0402_5%
+1.8VS
G
G
2
H_PWRGD
S
S
Q21
Q21
13
D
D
FDV301N_NL_SOT23-3
FDV301N_NL_SOT23-3
U21
2
P
B
4
Y
1
A
G
3
+3VS
R329
R329
4.7K_0402_5%
4.7K_0402_5%
1 2
SB_RX3N<11> SB_TX0P<11>
SB_TX0N<11> SB_TX1P<11> SB_TX1N<11> SB_TX2P<11> SB_TX2N<11> SB_TX3P<11> SB_TX3N<11>
+1.1VS_PCIE
NC7SZ08P5X_NL_SC70-5
NC7SZ08P5X_NL_SC70-5
H_PWRGD_L <38>
level shift to ISL6265
1 2
C573 0.1U_0402_16V7KC573 0.1U_0402_16V7K
1 2
C574 0.1U_0402_16V7KC574 0.1U_0402_16V7K
1 2
C575 0.1U_0402_16V7KC575 0.1U_0402_16V7K
1 2
C576 0.1U_0402_16V7KC576 0.1U_0402_16V7K
1 2
C580 0.1U_0402_16V7KC580 0.1U_0402_16V7K
1 2
C577 0.1U_0402_16V7KC577 0.1U_0402_16V7K
1 2
C578 0.1U_0402_16V7KC578 0.1U_0402_16V7K
1 2
R326 590_0402_1%R326 590_0402_1% R327 2K_0402_1%R327 2K_0402_1%
PLT_RST# <12,15,23,24,28,29>
CLK_SBSRC_BCLK<12> CLK_SBSRC_BCLK#<12>
NB_REFCLK_P<12> NB_REFCLK_N<12>
HT_REFCLKP<12> HT_REFCLKN<12>
CLK_CPU_BCLK<7> CLK_CPU_BCLK#<7>
CLK_PCIE_LAN<24> CLK_PCIE_LAN#<24>
CLK_PCIE_MCARD2<23> CLK_PCIE_MCARD2#<23>
R325 33_0402_5%R325 33_0402_5%
12 12
NB_REFCLK_P NB_REFCLK_N
HT_REFCLKP HT_REFCLKN
12
SB_RX0P_C SB_RX0N_C SB_RX1P_C SB_RX1N_C SB_RX2P_C SB_RX2N_C SB_RX3P_C SB_RX3N_C
ISL6265 PWROK input, TTL level: 0.8V~2.0V When this pin is high, the SVI interface is
active and I2C protocol is running. While this pin is low, the SVC, SVD, and VFIXEN input states determine the pre-PWROK metal VID or
3 3
VFIX mode voltage. This pin must be low prior to the ISL6265 PGOOD output going high
1 2
C1254
C1254 27P_0402_50V8J
27P_0402_50V8J
25MHZ_20PF_7A25000012
25MHZ_20PF_7A25000012
1 2
C1255
C1255 27P_0402_50V8J
27P_0402_50V8J
4 4
1 2
R332 20M_0402_5%@R332 20M_0402_5%@
1 2
C582
C582
1 2
18P_0402_50V8J
18P_0402_50V8J
R335
R335
20M_0603_5%
20M_0603_5%
C586
C586
1 2
18P_0402_50V8J
18P_0402_50V8J
Y6
Y6
12
A
25M_CLK_X1
12
R971
R971 1M_0402_5%
1M_0402_5%
25M_CLK_X2
4/26 Add test point T38 to T64 for debug 7/2 Add Net RTCCLK for EC Crystal cost down
Y3
Y3
4
OSC
NC
1
OSC
32.768KHZ_12.5PF_Q13MC14610002
32.768KHZ_12.5PF_Q13MC14610002
NC
3 2
CLK_48M_CR<25>
SB_32KHI
Close to SB
SB_32KHO
CLK_48M_CR
25M_CLK_X1
25M_CLK_X2
B
U8A
U8A
P1
PCIE_RST#
L1
A_RST#
AD26
A_TX0P
AD27
A_TX0N
AC28
A_TX1P
AC29
A_TX1N
AB29
A_TX2P
AB28
A_TX2N
AB26
A_TX3P
AB27
A_TX3N
AE24
A_RX0P
AE23
A_RX0N
AD25
A_RX1P
AD24
A_RX1N
AC24
A_RX2P
AC25
A_RX2N
AB25
A_RX3P
AB24
A_RX3N
AD29
PCIE_CALRP
AD28
PCIE_CALRN
AA28
GPP_TX0P
AA29
GPP_TX0N
Y29
GPP_TX1P
Y28
GPP_TX1N
Y26
GPP_TX2P
Y27
GPP_TX2N
W28
GPP_TX3P
W29
GPP_TX3N
AA22
GPP_RX0P
Y21
GPP_RX0N
AA25
GPP_RX1P
AA24
GPP_RX1N
W23
GPP_RX2P
V24
GPP_RX2N
W24
GPP_RX3P
W25
GPP_RX3N
M23
PCIE_RCLKP/NB_LNK_CLKP
P23
PCIE_RCLKN/NB_LNK_CLKN
U29
NB_DISP_CLKP
U28
NB_DISP_CLKN
T26
NB_HT_CLKP
T27
NB_HT_CLKN
V21
CPU_HT_CLKP
T21
CPU_HT_CLKN
V23
SLT_GFX_CLKP
T23
SLT_GFX_CLKN
L29
GPP_CLK0P
L28
GPP_CLK0N
N29
GPP_CLK1P
N28
GPP_CLK1N
M29
GPP_CLK2P
M28
GPP_CLK2N
T25
GPP_CLK3P
V25
GPP_CLK3N
L24
GPP_CLK4P
L23
GPP_CLK4N
P25
GPP_CLK5P
M25
GPP_CLK5N
P29
GPP_CLK6P
P28
GPP_CLK6N
N26
GPP_CLK7P
N27
GPP_CLK7N
T29
GPP_CLK8P
T28
GPP_CLK8N
L25
14M_25M_48M_OSC
L26
25M_X1
L27
25M_X2
SB820M_FCBGA605
SB820M_FCBGA605
SB820MR1@
SB820MR1@
Part 1 of 5
Part 1 of 5
SB800
SB800
PCI CLKS
PCI CLKS
PCI EXPRESS INTERFACES
PCI EXPRESS INTERFACES
REQ2#/CLK_REQ8#/GPIO41 REQ3#/CLK_REQ5#/GPIO42
GNT3#/CLK_REQ7#/GPIO46
LDRQ1#/CLK_REQ6#/GPIO49
CLOCK GENERATOR
CLOCK GENERATOR
ALLOW_LDTSTP/DMA_ACTIVE#
PCICLK0 PCICLK1/GPO36 PCICLK2/GPO37 PCICLK3/GPO38
PCICLK4/14M_OSC/GPO39
AD10/GPIO10 AD11/GPIO11 AD12/GPIO12 AD13/GPIO13 AD14/GPIO14 AD15/GPIO15 AD16/GPIO16 AD17/GPIO17 AD18/GPIO18 AD19/GPIO19 AD20/GPIO20 AD21/GPIO21 AD22/GPIO22 AD23/GPIO23 AD24/GPIO24 AD25/GPIO25 AD26/GPIO26 AD27/GPIO27 AD28/GPIO28 AD29/GPIO29 AD30/GPIO30 AD31/GPIO31
PCI INTERFACELPC
PCI INTERFACELPC
REQ1#/GPIO40
GNT1#/GPO44 GNT2#/GPO45
INTE#/GPIO32
INTF#/GPIO33 INTG#/GPIO34 INTH#/GPIO35
SERIRQ/GPIO48
CPU
CPU
INTRUDER_ALERT#
RTC
RTC
VDDBT_RTC_G
PCIRST#
AD0/GPIO0 AD1/GPIO1 AD2/GPIO2 AD3/GPIO3 AD4/GPIO4 AD5/GPIO5 AD6/GPIO6 AD7/GPIO7 AD8/GPIO8 AD9/GPIO9
CBE0# CBE1# CBE2# CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
STOP# PERR# SERR#
REQ0#
GNT0#
CLKRUN#
LOCK#
LPCCLK0 LPCCLK1
LAD0 LAD1 LAD2 LAD3
LFRAME#
LDRQ0#
PROCHOT#
LDT_PG LDT_STP# LDT_RST#
32K_X1 32K_X2
RTCCLK
7/21 Change U8 P/N to SA00003IWA0 (A13)
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
W2 W1 W3 W4 Y1
V2
AA1 AA4 AA3 AB1 AA5 AB2 AB6 AB5 AA6 AC2 AC3 AC4 AC1 AD1 AD2 AC6 AE2 AE1 AF8 AE3 AF1 AG1 AF2 AE9 AD9 AC11 AF6 AF4 AF3 AH2 AG2 AH3 AA8 AD5 AD8 AA10 AE8 AB9 AJ3 AE7 AC5
PAR
AF5 AE6 AE4 AE11 AH5 AH4 AC12 AD12 AJ5 AH6 AB12 AB11
1 2
R796 10K_0402_5%R796 10K_0402_5%
AD7 AJ6
AG6 AG4 AJ4
H24 H25 J27 J26 H29 H28 G28 J25 AA18 AB19
G21 H21 K19 G22
R26 0_0402_5%R26 0_0402_5%
J24
C1 C2 D2
B2 B1
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
1 2
SB_32KHI SB_32KHO
C584
C584
0.1U_0402_16V4Z
0.1U_0402_16V4Z
BT_DET#
1
2
Compal Secret Data
Compal Secret Data
Compal Secret Data
PCI_CLK1 <22> PCI_CLK2 <22> PCI_CLK3 <22> PCI_CLK4 <22>
PCI_AD23 <22> PCI_AD24 <20,22> PCI_AD25 <22> PCI_AD26 <22> PCI_AD27 <22> PCI_AD28 <22> PCI_AD29 <22>
2/23 Reserve R796 pull-down to CLKRUN#
BT_PWR# <23>
CLK_PCI_EC <22,28>
CLK_PCI_SIO <22,29>
LPC_AD0 <28,29> LPC_AD1 <28,29> LPC_AD2 <28,29> LPC_AD3 <28,29> LPC_FRAME# <28,29>
SERIRQ <28,29>
CPU_LDT_REQ# <12> H_PROCHOT# <7> H_PWRGD <7,38> LDT_STOP# <7,12> LDT_RST# <7>
RTCCLK <28>
1 2
R333 120_0402_5%R333 120_0402_5%
C585
C585
W=20mils
1
2
1U_0402_6.3V4Z
1U_0402_6.3V4Z
Deciphered Date
Deciphered Date
Deciphered Date
7/15 Add R260 pull up to +3VS
BT_DET#
BT_PWR#
1 2
R142 120_0402_5%R142 120_0402_5%
2
J1
2
JUMP_43X39@J1JUMP_43X39@
1
for Clear CMOS
1
1 2
R260 8.2K_0402_5%R260 8.2K_0402_5%
1 2
R95 100K_0402_5%R95 100K_0402_5%
+RTCVCC
1
7/22 Change D8 from DAN202U to CHN202UPT
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
D
Date: Sheet
+3VS
+3VS
D8
D8
2 3
CHN202UPT SC-70
CHN202UPT SC-70
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
+3VL
R141
R141
1 2
1K_0402_5%
1K_0402_5%
1
C583
C583 @
@
2
SUYIN_060003HA002G202ZL
SUYIN_060003HA002G202ZL
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
401982
401982
401982
0.1U_0402_16V4Z
0.1U_0402_16V4Z
E
+RTCBATT
1
+
-
2
18 40Wednesday, September 01, 2010
18 40Wednesday, September 01, 2010
18 40Wednesday, September 01, 2010
JRTC
@JRTC
@
of
of
of
B
B
B
A
B
C
D
E
7/2 Add D27 for abnormal shutdown RSMRST#
SB_PWRGD
HDMI_DET
A
EC_RSMRST#
SMB_CK_CLK0 SMB_CK_DAT0
SUS_STAT#
R135
@R135
@
10_0402_5%
10_0402_5%
GBE_MDIO
GBE_PHY_INTR
GBE_COL
GBE_RXERR
GBE_CRS
EC_LID_OUT#
SB_SIC SB_SID
H_THERMTRIP#
SMB_CK_CLK1 SMB_CK_DAT1
AZ_BITCLK_HD
12
+3VALW
12
12
R984
R984 10K_0402_5%
10K_0402_5%
CIR_EN#
@
@ R985
R985 1K_0402_5%
1K_0402_5%
1 2
1 1
2 2
3 3
4 4
R339 2.2K_0402_5%R339 2.2K_0402_5%
+3VS
R342 2.2K_0402_5%R342 2.2K_0402_5%
1 2
R343 2.2K_0402_5%R343 2.2K_0402_5%
1 2
R344 4.7K_0402_5%R344 4.7K_0402_5%
1 2
+3VS
R105
R105 10K_0402_5%
10K_0402_5%
@
@
1 2
R107
R107 10K_0402_5%
10K_0402_5%
1 2
C143 10P_0402_50V8J@C143 10P_0402_50V8J@
12
+3VALW
1 2
R352 10K_0402_5%R352 10K_0402_5%
1 2
R358 10K_0402_5%R358 10K_0402_5%
1 2
R353 10K_0402_5%R353 10K_0402_5%
1 2
R356 10K_0402_5%R356 10K_0402_5%
1 2
R354 10K_0402_5%R354 10K_0402_5%
+3VALW
1 2
R357 100K_0402_5%R357 100K_0402_5%
1 2
R359 2.2K_0402_5%R359 2.2K_0402_5%
1 2
R360 2.2K_0402_5%R360 2.2K_0402_5%
1 2
R361 10K_0402_5%R361 10K_0402_5%
1 2
R362 2.2K_0402_5%R362 2.2K_0402_5%
1 2
R363 2.2K_0402_5%R363 2.2K_0402_5%
D27
D27
2 1
CH751H-40PT_SOD323-2
CH751H-40PT_SOD323-2
PM_SLP_S3#<28> PM_SLP_S5#<28> PBTN_OUT#<28> SB_PWRGD<28>
SUS_STAT#<12,15>
EC_SWI#<24>
H_THERMTRIP#<7>
NB_PWRGD<12>
EC_RSMRST#<28>
CLKREQ_LAN#<24>
PCH_SPKR<26> SMB_CK_CLK0<9,10> SMB_CK_DAT0<9,10> SMB_CK_CLK1<23> SMB_CK_DAT1<23>
CLKREQ_MCARD2#<23>
EC_LID_OUT#<28>
AZ_BITCLK_HD<26>
AZ_SDOUT_HD<26>
HDA_SDOUT<22>
AZ_SDIN0_HD<26>
AZ_SYNC_HD<26>
AZ_RST_HD#<26>
GATEA20<28> KB_RST#<28> EC_SCI#<28> EC_SMI#<28>
USB_OC#0<23,28>
R345 33_0402_5%R345 33_0402_5% R346 33_0402_5%R346 33_0402_5%
R351 33_0402_5%R351 33_0402_5% R402 33_0402_5%R402 33_0402_5%
B
POK <33,35,36>
HDMI_DET
1 2 1 2
1 2 1 2
T14 PADT14 PAD T12 PADT12 PAD T13 PADT13 PAD
GBE_COL GBE_CRS
GBE_MDIO
GBE_RXERR
GBE_PHY_INTR
CIR_EN#
U8D
U8D
J2
PCI_PME#/GEVENT4#
K1
RI#/GEVENT22#
D3
SPI_CS3#/GBE_STAT1/GEVENT21#
F1
SLP_S3#
H1
SLP_S5#
F2
PWR_BTN#
H5
PWR_GOOD
G6
SUS_STAT#
B3
TEST0
C4
TEST1/TMS
F6
TEST2
AD21
GA20IN/GEVENT0#
AE21
KBRST#/GEVENT1#
K2
LPC_PME#/GEVENT3#
J29
LPC_SMI#/GEVENT23#
H2
GEVENT5#
J1
SYS_RESET#/GEVENT19#
H6
WAKE#/GEVENT8#
F3
IR_RX1/GEVENT20#
J6
THRMTRIP#/SMBALERT#/GEVENT2#
AC19
NB_PWRGD
G1
RSMRST#
AD19
CLK_REQ4#/SATA_IS0#/GPIO64
AA16
CLK_REQ3#/SATA_IS1#/GPIO63
AB21
SMARTVOLT1/SATA_IS2#/GPIO50
AC18
CLK_REQ0#/SATA_IS3#/GPIO60
AF20
SATA_IS4#/FANOUT3/GPIO55
AE19
SATA_IS5#/FANIN3/GPIO59
AF19
SPKR/GPIO66
AD22
SCL0/GPIO43
AE22
SDA0/GPIO47
F5
SCL1/GPIO227
F4
SDA1/GPIO228
AH21
CLK_REQ2#/FANIN4/GPIO62
AB18
CLK_REQ1#/FANOUT4/GPIO61
E1
IR_LED#/LLB#/GPIO184
AJ21
SMARTVOLT2/SHUTDOWN#/GPIO51
H4
DDR3_RST#/GEVENT7#
D5
GBE_LED0/GPIO183
D7
GBE_LED1/GEVENT9#
G5
GBE_LED2/GEVENT10#
K3
GBE_STAT0/GEVENT11#
AA20
CLK_REQG#/GPIO65/OSCIN
H3
BLINK/USB_OC7#/GEVENT18#
D1
USB_OC6#/IR_TX1/GEVENT6#
E4
USB_OC5#/IR_TX0/GEVENT17#
D4
USB_OC4#/IR_RX0/GEVENT16#
E8
USB_OC3#/AC_PRES/TDO/GEVENT15#
F7
USB_OC2#/TCK/GEVENT14#
E7
USB_OC1#/TDI/GEVENT13#
F8
USB_OC0#/TRST#/GEVENT12#
M3
AZ_BITCLK
N1
AZ_SDOUT
L2
AZ_SDIN0/GPIO167
M2
AZ_SDIN1/GPIO168
M1
AZ_SDIN2/GPIO169
M4
AZ_SDIN3/GPIO170
N2
AZ_SYNC
P2
AZ_RST#
T1
GBE_COL
T4
GBE_CRS
L6
GBE_MDCK
L5
GBE_MDIO
T9
GBE_RXCLK
U1
GBE_RXD3
U3
GBE_RXD2
T2
GBE_RXD1
U2
GBE_RXD0
T5
GBE_RXCTL/RXDV
V5
GBE_RXERR
P5
GBE_TXCLK
M5
GBE_TXD3
P9
GBE_TXD2
T7
GBE_TXD1
P7
GBE_TXD0
M7
GBE_TXCTL/TXEN
P4
GBE_PHY_PD
M9
GBE_PHY_RST#
V7
GBE_PHY_INTR
E23
PS2_DAT/SDA4/GPIO187
E24
PS2_CLK/SCL4/GPIO188
F21
SPI_CS2#/GBE_STAT2/GPIO166
G29
FC_RST#/GPO160
D27
PS2KB_DAT/GPIO189
F28
PS2KB_CLK/GPIO190
F29
PS2M_DAT/GPIO191
E27
PS2M_CLK/GPIO192
SB820M_FCBGA605
SB820M_FCBGA605 SB820MR1@
SB820MR1@
SB800
SB800
Part 4 of 5
Part 4 of 5
GBE LAN
GBE LAN
ACPI / WAKE UP EVENTS
ACPI / WAKE UP EVENTS
EC_PWM0/EC_TIMER0/GPIO197 EC_PWM1/EC_TIMER1/GPIO198 EC_PWM2/EC_TIMER2/GPIO199 EC_PWM3/EC_TIMER3/GPIO200
HD AUDIO
HD AUDIO
EMBEDDED CTRL
EMBEDDED CTRL
USBCLK/14M_25M_48M_OSC
GPIO
GPIO
USB OC
USB OC
USB_FSD1P/GPIO186
USB_FSD0P/GPIO185
USB 1.1 USB MISCEMBEDDED CTRL
USB 1.1 USB MISCEMBEDDED CTRL
USB 2.0
USB 2.0
SCL2/GPIO193 SDA2/GPIO194
SCL3_LV/GPIO195
SDA3_LV/GPIO196
KSI_0/GPIO201 KSI_1/GPIO202 KSI_2/GPIO203 KSI_3/GPIO204 KSI_4/GPIO205 KSI_5/GPIO206 KSI_6/GPIO207 KSI_7/GPIO208
KSO_0/GPIO209 KSO_1/GPIO210 KSO_2/GPIO211 KSO_3/GPIO212 KSO_4/GPIO213 KSO_5/GPIO214 KSO_6/GPIO215 KSO_7/GPIO216 KSO_8/GPIO217
KSO_9/GPIO218 KSO_10/GPIO219 KSO_11/GPIO220 KSO_12/GPIO221 KSO_13/GPIO222 KSO_14/GPIO223 KSO_15/GPIO224 KSO_16/GPIO225 KSO_17/GPIO226
USB_RCOMP
USB_HSD13P USB_HSD13N
USB_HSD12P USB_HSD12N
USB_HSD11P USB_HSD11N
USB_HSD10P USB_HSD10N
USB_FSD1N
USB_FSD0N
USB_HSD9P
USB_HSD9N
USB_HSD8P
USB_HSD8N
USB_HSD7P
USB_HSD7N
USB_HSD6P
USB_HSD6N
USB_HSD5P
USB_HSD5N
USB_HSD4P
USB_HSD4N
USB_HSD3P
USB_HSD3N
USB_HSD2P
USB_HSD2N
USB_HSD1P
USB_HSD1N
USB_HSD0P
USB_HSD0N
A10 G19
J10 H11
H9 J8
B12 A12
F11 E11
E14 E12
J12 J14
A13 B13
D13 C13
G12 G14
G16 G18
D16 C16
B14 A14
E18 E16
J16 J18
B17 A17
A16 B16
D25 F23 B26 E26 F25 E22 F22 E21
G24 G25 E28 E29 D29 D28 C29 C28
B28 A27 B27 D26 A26 C26 A24 B25 A25 D24 B24 C24 B23 A23 D22 C22 A22 B22
USB_RCOMP
SB_SIC SB_SID
GPIO201 GPIO202 GPIO203 GPIO204 GPIO205
GPIO204 GPIO205
Madison LP
None
1 2
USB20_P9 <17> USB20_N9 <17>
USB20_P8 <23> USB20_N8 <23>
USB20_P5 <25> USB20_N5 <25>
USB20_P1 <23> USB20_N1 <23>
USB20_P0 <23> USB20_N0 <23>
1 2
1 2
Park XT
M92 XTX
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
T20PAD T20PAD
R33811.8K_0402_1% R33811.8K_0402_1%
GPIO199 <22> GPIO200 <22>
R922
R922 10K_0402_5%
10K_0402_5%
@
@
R926
R926 10K_0402_5%
10K_0402_5%
GPIO204
Low
Low
High
USB PORT LIST
PORT USB0 USB1
USB5
USB8
USB9
USB-9 Int Camera USB-8 WLAN
USB-5 Card Reader 2 IN 1
USB-1 Right side USB-0 Right side
STRAP PIN
@R919
+3VALW
GPIO201 GPIO202 GPIO203
R923
R923 10K_0402_5%
10K_0402_5%
1 2
R927
R927 10K_0402_5%
10K_0402_5%
@
@
1 2
GPIO205
Low
High
LowHigh
Nile-M
Nile-S
Danube Marseille
Danube Hamburg
Danube LC Marseille
High
Title
Title
Title
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
@ 10K_0402_5%
10K_0402_5%
1 2
R924
R924 1K_0402_1%
1K_0402_1%
1 2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
DEVICE
USB0(Right) USB1(Right) Card Reader WLAN Int Camera
R919
GPIO201
High High
High High
Low
Low
Low Low High
401982
401982
401982
E
R920
@R920
@ 10K_0402_5%
10K_0402_5%
1 2
R925
R925 1K_0402_1%
1K_0402_1%
1 2
+3VALW
1 2
@
@ 10K_0402_5%
10K_0402_5%
1 2
GPIO202
GPIO203
High
Low
Low Low
Low
High
19 40Wednesday, September 01, 2010
19 40Wednesday, September 01, 2010
19 40Wednesday, September 01, 2010
R921
R921
10K_0402_5%
10K_0402_5%
R928
R928
*
B
B
B
A
+1.1VS_SATA
SATA_STX_DRX_P0<23> SATA_STX_DRX_N0<23>
SATA_SRX_C_DTX_N0<23> SATA_SRX_C_DTX_P0<23>
SATA_STX_DRX_P1<23> SATA_STX_DRX_N1<23>
SATA_SRX_C_DTX_N1<23> SATA_SRX_C_DTX_P1<23>
R364 1K_0402_1%R364 1K_0402_1% R365 931_0402_1%R365 931_0402_1%
1 1
HDD
ODD
2 2
B
U8B
U8B
AH9
SATA_TX0P
AJ9
SATA_TX0N
AJ8
SATA_RX0N
AH8
SATA_RX0P
AH10
SATA_TX1P
AJ10
SATA_TX1N
AG10
SATA_RX1N
AF10
SATA_RX1P
AG12
SATA_TX2P
AF12
SATA_TX2N
AJ12
SATA_RX2N
AH12
SATA_RX2P
AH14
SATA_TX3P
AJ14
SATA_TX3N
AG14
SATA_RX3N
AF14
SATA_RX3P
AG17
SATA_TX4P
AF17
SATA_TX4N
AJ17
SATA_RX4N
AH17
SATA_RX4P
AJ18
SATA_TX5P
AH18
SATA_TX5N
AH19
SATA_RX5N
AJ19
SATA_RX5P
12 12
SATA_CALRP SATA_CALRN
SATA_X1
SATA_X2
AB14 AA14
AD11
AD16
AC16
SATA_CALRP SATA_CALRN
SATA_ACT#/GPIO67
SATA_X1
SATA_X2
C
SB800
SB800
Part 2 of 5
Part 2 of 5
SERIAL ATA
SERIAL ATA
HW MONITOR
HW MONITOR
FC_CLK
FC_FBCLKOUT
FC_FBCLKIN
FC_OE#/GPIOD145
FC_AVD#/GPIOD146
FC_WE#/GPIOD148 FC_CE1#/GPIOD149 FC_CE2#/GPIOD150
FC_INT1/GPIOD144 FC_INT2/GPIOD147
FC_ADQ0/GPIOD128 FC_ADQ1/GPIOD129 FC_ADQ2/GPIOD130 FC_ADQ3/GPIOD131 FC_ADQ4/GPIOD132 FC_ADQ5/GPIOD133 FC_ADQ6/GPIOD134 FC_ADQ7/GPIOD135 FC_ADQ8/GPIOD136 FC_ADQ9/GPIOD137
FC_ADQ10/GPIOD138 FC_ADQ11/GPIOD139 FC_ADQ12/GPIOD140
FLASH
FLASH
FC_ADQ13/GPIOD141 FC_ADQ14/GPIOD142 FC_ADQ15/GPIOD143
FANOUT0/GPIO52 FANOUT1/GPIO53 FANOUT2/GPIO54
FANIN0/GPIO56 FANIN1/GPIO57 FANIN2/GPIO58
TEMPIN0/GPIO171 TEMPIN1/GPIO172 TEMPIN2/GPIO173
TEMPIN3/TALERT#/GPIO174
TEMP_COMM
VIN0/GPIO175 VIN1/GPIO176 VIN2/GPIO177 VIN3/GPIO178 VIN4/GPIO179 VIN5/GPIO180
VIN6/GBE_STAT3/GPIO181
VIN7/GBE_LED3/GPIO182
AH28 AG28 AF26
AF28 AG29 AG26 AF27 AE29 AF29 AH27
AJ27 AJ26 AH25 AH24 AG23 AH23 AJ22 AG21 AF21 AH22 AJ23 AF23 AJ24 AJ25 AG25 AH26
W5 W6 Y9
W7 V9 W8
B6 A6 A5 B5 C7
A3 B4 A4 C5 A7 B7 B8 A8
R43 150K_0402_5%R43 150K_0402_5%
2 1
MEM_1V5
1 2
D22
D22 CH751H-40PT_SOD323-2
CH751H-40PT_SOD323-2
D
+3VALW
ACIN <28,34>
E
DO DI CLK CS#
3 3
1
C445
C445
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
4 4
A
+3VALW
20mils
CS# CLK DI DO
@
@ R86
R86
10_0402_5%
10_0402_5%
1 2
1
@
@
C155
C155 10P_0402_50V8J
10P_0402_50V8J
2
U47
U47
8
VCC
3
W
7
HOLD
1
S
6
C
5
D
MX25L1605DM2I-12G_SO8-200mil
MX25L1605DM2I-12G_SO8-200mil
4
VSS
2
Q
B
4/16 Change U47 from SA00002TO00 to SA00003FO00
J5
SPI_DI/GPIO164
E2
SPI_DO/GPIO163
K4
SPI_CLK/GPIO162
K9
SPI_CS1#/GPIO165
G2
ROM_RST#/GPIO161
SB820M_FCBGA605
SB820M_FCBGA605 SB820MR1@
SB820MR1@
G27
NC1
Y2
NC2
SPI ROM
SPI ROM
MEM_1V5 is for gating the glitch on PCI_AD24
PCI_AD24<18,22>
PCI_AD24 1 : VDDR=1.05V 0 : VDDR=0.9V
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2/23 Reserve MEM_1V5 circuit for unsupport DDR-1333
C688
@C688
@
12
0.1U_0402_16V4Z
MEM_1V5
R422 0_0402_5%@R422 0_0402_5%@
1 2
0.1U_0402_16V4Z 2 1
D
+3VS
5
@U23
@
P
B
Y
A
G
NC7SZ08P5X_NL_SC70-5
NC7SZ08P5X_NL_SC70-5
3
1 2
R423 0_0402_5%@R423 0_0402_5%@
U23
4
1 2
R424 33_0402_5%@R424 33_0402_5%@
2
C689
@C689
@
150P_0402_50V8J
150P_0402_50V8J
1
VDDR_SW <37>
For VDDR Voltage Switch, AMD suggest
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
401982
401982
20 40Wednesday, September 01, 2010
20 40Wednesday, September 01, 2010
20 40Wednesday, September 01, 2010
E
B
B
B
A
1 2
R371 0_0402_5%R371 0_0402_5%
+VDDPL_3V_PCIE
+1.1VS_PCIE
12
+VDDPL_3V_SATA
+1.1VS_SATA
12
L72
L72
12
12
131mA
567mA
+AVDD_USB
+1.1V_USB
+3VS
1 1
+1.1VS
2 2
+1.1VS
1 2 C591 22U_0805_6.3V6MC591 22U_0805_6.3V6M C592 0.1U_0402_16V4ZC592 0.1U_0402_16V4Z
1 2 C593 0.1U_0402_16V4ZC593 0.1U_0402_16V4Z
1 2 C599 0.1U_0402_16V4ZC599 0.1U_0402_16V4Z
1 2
L70
L70
FBMA-L11-201209-221LMA30T_0805
FBMA-L11-201209-221LMA30T_0805
C604 22U_0805_6.3V6MC604 22U_0805_6.3V6M
1 2
C605 1U_0402_6.3V4ZC605 1U_0402_6.3V4Z
1 2
C606 0.1U_0402_16V4ZC606 0.1U_0402_16V4Z
1 2
C607 0.1U_0402_16V4ZC607 0.1U_0402_16V4Z
1 2
L71
FBMA-L11-201209-221LMA30T_0805
FBMA-L11-201209-221LMA30T_0805
L71
C610 22U_0805_6.3V6MC610 22U_0805_6.3V6M
1 2
C611 1U_0402_6.3V4ZC611 1U_0402_6.3V4Z
1 2
C612 1U_0402_6.3V4ZC612 1U_0402_6.3V4Z
1 2
C613 0.1U_0402_16V4ZC613 0.1U_0402_16V4Z
1 2
C614 0.1U_0402_16V4ZC614 0.1U_0402_16V4Z
1 2
check 220ohm bead
+3VALW
FBMA-L11-201209-221LMA30T_0805
FBMA-L11-201209-221LMA30T_0805
C617 10U_0805_10V4ZC617 10U_0805_10V4Z
1 2
C618 10U_0805_10V4ZC618 10U_0805_10V4Z
1 2
C619 1U_0402_6.3V4ZC619 1U_0402_6.3V4Z
1 2
C620 1U_0402_6.3V4ZC620 1U_0402_6.3V4Z
1 2
C621 0.1U_0402_16V4ZC621 0.1U_0402_16V4Z
1 2
L74
3 3
+1.1VALW
L74
FBMA-L11-160808-221LMT 0603
FBMA-L11-160808-221LMT 0603
C625 2.2U_0603_6.3V4ZC625 2.2U_0603_6.3V4Z
12
C626 0.1U_0402_16V4ZC626 0.1U_0402_16V4Z
12
71mA
43mA
600mA
93mA
658mA
200mA
AH1
AC21
AC8
AA19
AF22 AE25 AF24 AC22
AE28
W22 W26
AD14
AJ20 AF18 AH20 AG19 AE18 AD18 AE16
V6 Y19 AE5
AA2 AB4
AA7 AA9 AF7
U26 V22 V26 V27 V28 V29
A18 A19 A20 B18 B19 B20 C18 C20 D18 D19 D20 E19
C11 D11
B
U8C
U8C
SB820M_FCBGA605
SB820M_FCBGA605 SB820MR1@
SB820MR1@
SB800
SB800
VDDIO_33_PCIGP_1 VDDIO_33_PCIGP_2 VDDIO_33_PCIGP_3 VDDIO_33_PCIGP_4 VDDIO_33_PCIGP_5 VDDIO_33_PCIGP_6 VDDIO_33_PCIGP_7 VDDIO_33_PCIGP_8 VDDIO_33_PCIGP_9 VDDIO_33_PCIGP_10 VDDIO_33_PCIGP_11 VDDIO_33_PCIGP_12
VDDIO_18_FC_1 VDDIO_18_FC_2 VDDIO_18_FC_3 VDDIO_18_FC_4
POWER
POWER
VDDPL_33_PCIE
VDDAN_11_PCIE_1 VDDAN_11_PCIE_2 VDDAN_11_PCIE_3 VDDAN_11_PCIE_4 VDDAN_11_PCIE_5 VDDAN_11_PCIE_6 VDDAN_11_PCIE_7 VDDAN_11_PCIE_8
VDDPL_33_SATA VDDAN_11_SATA_1
VDDAN_11_SATA_4 VDDAN_11_SATA_2 VDDAN_11_SATA_3 VDDAN_11_SATA_5 VDDAN_11_SATA_6 VDDAN_11_SATA_7
VDDAN_33_USB_S_1 VDDAN_33_USB_S_2 VDDAN_33_USB_S_3 VDDAN_33_USB_S_4 VDDAN_33_USB_S_5 VDDAN_33_USB_S_6 VDDAN_33_USB_S_7 VDDAN_33_USB_S_8 VDDAN_33_USB_S_9 VDDAN_33_USB_S_10 VDDAN_33_USB_S_11 VDDAN_33_USB_S_12
VDDAN_11_USB_S_1 VDDAN_11_USB_S_2
Part 3 of 5
Part 3 of 5
PCI/GPIO I/O
PCI/GPIO I/O
FLASH I/O
FLASH I/O
GBE LAN
GBE LAN
PCI EXPRESSSERIAL ATA
PCI EXPRESSSERIAL ATA
CORE S5
CORE S5
USB I/O
USB I/O
PLL CLKGEN I/O
PLL CLKGEN I/O
VDDCR_11_1 VDDCR_11_2 VDDCR_11_3 VDDCR_11_4 VDDCR_11_5 VDDCR_11_6 VDDCR_11_7
CORE S03.3V_S5 I/O
CORE S03.3V_S5 I/O
VDDCR_11_8 VDDCR_11_9
VDDAN_11_CLK_1 VDDAN_11_CLK_2 VDDAN_11_CLK_3 VDDAN_11_CLK_4 VDDAN_11_CLK_5 VDDAN_11_CLK_6 VDDAN_11_CLK_7 VDDAN_11_CLK_8
VDDRF_GBE_S
VDDIO_33_GBE_S
VDDCR_11_GBE_S_1 VDDCR_11_GBE_S_2
VDDIO_GBE_S_1 VDDIO_GBE_S_2
VDDIO_33_S_1 VDDIO_33_S_2 VDDIO_33_S_3 VDDIO_33_S_4 VDDIO_33_S_5 VDDIO_33_S_6 VDDIO_33_S_7 VDDIO_33_S_8
VDDCR_11_S_1 VDDCR_11_S_2
VDDIO_AZ_S
VDDCR_11_USB_S_1 VDDCR_11_USB_S_2
VDDPL_33_SYS
VDDPL_11_SYS_S
VDDPL_33_USB_S
VDDAN_33_HWM_S
VDDXL_33_S
N13 R15 N17 U13 U17 V12 V18 W12 W18
K28 K29 J28 K26 J21 J20 K21 J22
V1 M10
L7 L9
M6 P8
A21 D21 B21 K10 L10 J9 T6 T8
F26 G26
M8 A11
B11
M21 L22 F19 D6 L20
510mA
400mA
32mA
113mA TBD
197mA
47mA 62mA 17mA 5mA 197mA
+1.1VS_VDDC
+1.1VS_CKVDD
1 2
R372 0_0402_5%R372 0_0402_5%
1 2
R373 0_0402_5%R373 0_0402_5%
1 2
R374 0_0402_5%R374 0_0402_5%
1 2
R375 0_0402_5%R375 0_0402_5%
+VDDIO_AZ
+VDDPL_3V +VDDPL_11V +VDDPL_3V_USB +3V_HWM
C
1 2
R369 0_0805_5%R369 0_0805_5%
1 2
12 12 12 12
L69
L69
FBMA-L11-201209-221LMA30T_0805
FBMA-L11-201209-221LMA30T_0805
1 2
+3VALW
C6082.2U_0603_6.3V4Z C6082.2U_0603_6.3V4Z
1 2
C6092.2U_0603_6.3V4Z C6092.2U_0603_6.3V4Z
1 2
C615 1U_0402_6.3V4ZC615 1U_0402_6.3V4Z C616 1U_0402_6.3V4ZC616 1U_0402_6.3V4Z
+VDDCR_USB
L73 FBMA-L11-160808-221LMT 0603L73 FBMA-L11-160808-221LMT 0603 C622 10U_0805_10V4ZC622 10U_0805_10V4Z
1 2
C623 0.1U_0402_16V4ZC623 0.1U_0402_16V4Z C624 0.1U_0402_16V4ZC624 0.1U_0402_16V4Z
+VDDLX_3V
L75 FBMA-L11-160808-221LMT 0603L75 FBMA-L11-160808-221LMT 0603
C627 2.2U_0603_6.3V4ZC627 2.2U_0603_6.3V4Z
1 2
D
U8E
+1.1VS
C59010U_0805_10V4Z C59010U_0805_10V4Z
C5961U_0402_6.3V4Z C5961U_0402_6.3V4Z C5941U_0402_6.3V4Z C5941U_0402_6.3V4Z C5970.1U_0402_16V4Z C5970.1U_0402_16V4Z C5980.1U_0402_16V4Z C5980.1U_0402_16V4Z
12
12 12 12 12
12 12
+1.1VS
C59522U_0805_6.3V6M C59522U_0805_6.3V6M
C6001U_0402_6.3V4Z C6001U_0402_6.3V4Z C6011U_0402_6.3V4Z C6011U_0402_6.3V4Z C6020.1U_0402_16V4Z C6020.1U_0402_16V4Z C6030.1U_0402_16V4Z C6030.1U_0402_16V4Z
12 12
External Clock, connect to +1.1VS directly, no need thick trace
check can be removed?
+1.1VALW
+1.1VALW
12
+3VALW
12
Y14
VSSIO_SATA_1
Y16
VSSIO_SATA_2
AB16
VSSIO_SATA_3
AC14
VSSIO_SATA_4
AE12
VSSIO_SATA_5
AE14
VSSIO_SATA_6
AF9
VSSIO_SATA_7
AF11
VSSIO_SATA_8
AF13
VSSIO_SATA_9
AF16
VSSIO_SATA_10
AG8
VSSIO_SATA_11
AH7
VSSIO_SATA_12
AH11
VSSIO_SATA_13
AH13
VSSIO_SATA_14
AH16
VSSIO_SATA_15
AJ7
VSSIO_SATA_16
AJ11
VSSIO_SATA_17
AJ13
VSSIO_SATA_18
AJ16
VSSIO_SATA_19
A9
VSSIO_USB_1
B10
VSSIO_USB_2
K11
VSSIO_USB_3
B9
VSSIO_USB_4
D10
VSSIO_USB_5
D12
VSSIO_USB_6
D14
VSSIO_USB_7
D17
VSSIO_USB_8
E9
VSSIO_USB_9
F9
VSSIO_USB_10
F12
VSSIO_USB_11
F14
VSSIO_USB_12
F16
VSSIO_USB_13
C9
VSSIO_USB_14
G11
VSSIO_USB_15
F18
VSSIO_USB_16
D9
VSSIO_USB_17
H12
VSSIO_USB_18
H14
VSSIO_USB_19
H16
VSSIO_USB_20
H18
VSSIO_USB_21
J11
VSSIO_USB_22
J19
VSSIO_USB_23
K12
VSSIO_USB_24
K14
VSSIO_USB_25
K16
VSSIO_USB_26
K18
VSSIO_USB_27
H19
VSSIO_USB_28
Y4
EFUSE
D8
VSSAN_HWM
M19
VSSXL
P21
VSSIO_PCIECLK_1
P20
VSSIO_PCIECLK_2
M22
VSSIO_PCIECLK_3
M24
VSSIO_PCIECLK_4
M26
VSSIO_PCIECLK_5
P22
VSSIO_PCIECLK_6
P24
VSSIO_PCIECLK_7
P26
VSSIO_PCIECLK_8
T20
VSSIO_PCIECLK_9
T22
VSSIO_PCIECLK_10
T24
VSSIO_PCIECLK_11
V20
VSSIO_PCIECLK_12
J23
VSSIO_PCIECLK_13
SB820M_FCBGA605
SB820M_FCBGA605
U8E
SB800
SB800
GROUND
GROUND
VSSIO_PCIECLK_14 VSSIO_PCIECLK_15 VSSIO_PCIECLK_16 VSSIO_PCIECLK_17 VSSIO_PCIECLK_18 VSSIO_PCIECLK_19 VSSIO_PCIECLK_20 VSSIO_PCIECLK_21 VSSIO_PCIECLK_22 VSSIO_PCIECLK_23 VSSIO_PCIECLK_24 VSSIO_PCIECLK_25 VSSIO_PCIECLK_26 VSSIO_PCIECLK_27
Part 5 of 5
Part 5 of 5
VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8
VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52
VSSPL_SYS
E
AJ2 A28 A2 E5 D23 E25 E6 F24 N15 R13 R17 T10 P10 V11 U15 M18 V19 M11 L12 L18 J7 P3 V4 AD6 AD4 AB7 AC9 V8 W9 W10 AJ28 B29 U4 Y18 Y10 Y12 Y11 AA11 AA12 G4 J4 G8 G9 M12 AF25 H7 AH29 V10 P6 N4 L4 L8
M20
H23 H26 AA21 AA23 AB23 AD23 AA26 AC26 Y20 W21 W20 AE26 L21 K20
+VDDPL_3V_PCIE +3VS
1
C628
C628
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4 4
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
+VDDPL_3V_SATA +3VS
1
C636
C636
2
L79
L79
C634
C634
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
L81
L81
C637
C637
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
A
12
12
FBMA-L11-160808-221LMT 0603
FBMA-L11-160808-221LMT 0603
1
2
FBMA-L11-160808-221LMT 0603
FBMA-L11-160808-221LMT 0603
1
2
1
2
+VDDIO_AZ
1
2
C635
C635
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
C638
C638
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
L80
L80
FBMA-L11-160808-221LMT 0603
FBMA-L11-160808-221LMT 0603
1 2
R376 0_0402_5%R376 0_0402_5%
1 2
R52 0_0402_5%
R52 0_0402_5%
@
@
+3VS+VDDPL_3V
12
+3VALW
For 3V AZ device
B
+VDDPL_11V +1.1VALW +VDDPL_3V_USB +3VALW +3V_HWM +3VALW
L76
+1.5VS
L76
FBMA-L11-160808-221LMT 0603
FBMA-L11-160808-221LMT 0603
1
C629
C629
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
12
1
C630
C630
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2
C
L77
L77
12
0_0603_5%
0_0603_5%
1
C631
C631
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
2
Compal Secret Data
Compal Secret Data
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
C632
C632
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
2
2
D
L78
L78
C633
C633
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
12
FBMA-L11-160808-221LMT 0603
FBMA-L11-160808-221LMT 0603
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
401982
401982
21 40Wednesday, September 01, 2010
21 40Wednesday, September 01, 2010
21 40Wednesday, September 01, 2010
E
B
B
B
A
B
C
D
E
REQUIRED STRAPS
AZ_SDOUT
PULL
1 1
2 2
HIGH
PULL LOW
HDA_SDOUT<19>
PCI_CLK1<18> PCI_CLK2<18> PCI_CLK3<18> PCI_CLK4<18>
CLK_PCI_EC<18,28> CLK_PCI_SIO<18,29>
GPIO200<19> GPIO199<19>
LOW POWER MODE
Performance MODE
DEFAULT
R377
R377
@
@
R386
R386
PCI_CLK1
ALLOW PCIE GEN2
FORCE PCIE GEN1
DEFAULT
+VDDIO_AZ +3VS +3VS +3VS +3VS +3VALW +3VALW +3VALW +3VALW
R378
R378
10K_0402_5%
10K_0402_5%
@
@
R387
R387
10K_0402_5%
10K_0402_5%
12
12
12
10K_0402_5%
10K_0402_5%
12
10K_0402_5%
10K_0402_5%
Check Internal PU/PD
PCI_CLK2 PCI_CLK3
WATCHDOG TIMER ENABLE
WATCHDOG TIMER DISABLE
DEFAULT
R379
R379
10K_0402_5%
10K_0402_5%
@
@
R388
R388
10K_0402_5%
10K_0402_5%
USE DEBUG STRAP
IGNORE DEBUG STRAP
DEFAULT
12
12
R380
R380
10K_0402_5%
10K_0402_5%
@
@
R389
R389
10K_0402_5%
10K_0402_5%
12
12
PCI_CLK4
Inter CLK Gen Mode
Enable
DEFAULT
Inter CLK Gen Mode
Disable
12
R381
R381
10K_0402_5%
10K_0402_5%
12
R390
R390
10K_0402_5%
10K_0402_5%
@
@
EC ENABLE
EC DISABLE
DEFAULT
12
R382
R382
10K_0402_5%
10K_0402_5%
@
@
12
R391
R391
10K_0402_5%
10K_0402_5%
LPC_CLK1LPC_CLK0
CLOCKGEN ENABLE
DEFAULT
CLOCKGEN DISABLE
12
R383
R383
10K_0402_5%
10K_0402_5%
12
R392
R392
10K_0402_5%
10K_0402_5%
@
@
GPIO200
H,H = Reserved
H,L = SPI ROM (Default )
L,H = LPC ROM
L,L = FWH ROM
12
R384
R384
10K_0402_5%
10K_0402_5%
12
R393
R393
2.2K_0402_5%
2.2K_0402_5%
@
@
GPIO199
12
R385
R385
2.2K_0402_5%
2.2K_0402_5%
@
@
12
R394
R394
2.2K_0402_5%
2.2K_0402_5%
+3VS+3VS
12
DEBUG STRAPS
SB800 HAS 15K INTERNAL PU FOR PCI_AD[27:23]
3 3
PULL HIGH
PULL LOW
PCI_AD27 PCI_AD26
DISABLE ILA
PLL
DEFAULT
BYPASS PCI PLL
AUTORUN
DEFAULT
ENABLE ILA AUTORUN
Check AD29,AD28 strap function
4 4
A
PCI_AD25 PCI_AD24
USE FC PLLUSE PCI
DEFAULT
BYPASS FC PLL
USE DEFAULT PCIE STRAPS
DEFAULT
USE EEPROM PCIE STRAPS
check default
B
PCI_AD23
DISABLE PCI MEM BOOT
DEFAULT
ENABLE PCI MEM BOOT
PCI_AD29<18> PCI_AD28<18> PCI_AD27<18> PCI_AD26<18> PCI_AD25<18> PCI_AD24<18,20> PCI_AD23<18>
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
12
R396
R396
R395
R395
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
R397
R397
2.2K_0402_5%
2.2K_0402_5%
@
@
R398
R398
D
2.2K_0402_5%
2.2K_0402_5%
@
@
12
R399
R399
2.2K_0402_5%
2.2K_0402_5%
@
@
12
12
12
R400
R400
2.2K_0402_5%
2.2K_0402_5%
@
@
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet
12
R401
R401
2.2K_0402_5%
2.2K_0402_5%
@
@
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
401982
401982
22 40Wednesday, September 01, 2010
22 40Wednesday, September 01, 2010
22 40Wednesday, September 01, 2010
E
of
B
B
B
5
SATA HDD Conn.
+5VS
+3VS
D D
C C
24 23
Place closely JHDD SATA CONN.
1.2A
1
C1247
C1247 10U_0805_10V4Z
10U_0805_10V4Z
2
1
C1248
C1248
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
SSD HDD need 400mA for 3V(PHISON)
+3VS rail reserve for SSD
1
C1251
C1251 10U_0805_10V4Z
10U_0805_10V4Z @
@
2
Reserved
GND GND
SANTA_191201-1
SANTA_191201-1 CONN@
CONN@
JHDD
JHDD
GND
GND
GND
GND GND GND
GND GND
1
C1159
C1159
0.1U_0402_16V4Z
0.1U_0402_16V4Z @
@
2
1
SATA_STX_C_DRX_P0
2
A+
A­B-
B+
V33 V33 V33
V5 V5 V5
V12 V12 V12
3 4 5 6 7
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
SATA_STX_C_DRX_N0 SATA_SRX_DTX_N0
SATA_SRX_DTX_P0
+3VS
+5VS
1
C1249
C1249
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C1152
C1152
0.1U_0402_16V4Z
0.1U_0402_16V4Z @
@
2
Close to JHDD
1
C1250
C1250
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C1253
C1253
0.1U_0402_16V4Z
0.1U_0402_16V4Z @
@
2
C1153 0.01U_0402_25V7KC1153 0.01U_0402_25V7K
1 2
C1154 0.01U_0402_25V7KC1154 0.01U_0402_25V7K
1 2
C1155 0.01U_0402_25V7KC1155 0.01U_0402_25V7K
1 2
C1156 0.01U_0402_25V7KC1156 0.01U_0402_25V7K
1 2
7310
9
8
8
45162
2/23 Reserve D91 for ESD
D91
D91 RCLAMP0524P.TCT~D
RCLAMP0524P.TCT~D @
@
Slot#1 Half PCIe Mini Card-WLAN
2
+3VS +3V_WLAN
Short PJ27 for WLAN
+1.5VS
0.1U_0402_16V4Z
0.1U_0402_16V4Z
B B
1
CM18
CM18
CM21
CM21
2
0.01U_0402_25V7K
0.01U_0402_25V7K
PJ27 JUMP_43X79@PJ27 JUMP_43X79@
CLKREQ_MCARD2#
1
CM17
CM17
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
112
47P_0402_50V8J
47P_0402_50V8J
1
12
2
CM24
CM24 @
@
1 2
R259 8.2K_0402_5%@ R259 8.2K_0402_5%@
+3V_WLAN
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
CM20
CM20
CM22
CM22
2
0.01U_0402_25V7K
0.01U_0402_25V7K
+3V_WLAN
1
CM23
CM23
2
4.7U_0805_10V4Z
4.7U_0805_10V4Z
For SEDFor SED
47P_0402_50V8J
47P_0402_50V8J
1
12
2
CM19
CM19 @
@
4
SATA_STX_DRX_P0 <20> SATA_STX_DRX_N0 <20>
SATA_SRX_C_DTX_N0 <20> SATA_SRX_C_DTX_P0 <20>
WLAN&BT Combo module circuits
BT_CRTL
BT_PWR#
**If +3V_WLAN is +3VS, please remove DM2
SUSP#<28,31,37>
@DM2
@
CH751H-40PT_SOD323-2
CH751H-40PT_SOD323-2
BT_PWR#<18>
SATA ODD Conn
BT on module
Enable Disable
DM2
BT on module
HL
LH
21
2
G
G
BT_CTRLSUSP#
13
D
D
QM1
QM1 BT@
BT@
2N7002_SOT23-3
2N7002_SOT23-3
S
S
3
JODD
JODD
15
GND
14
GND
SANTA_206401-1_RV
SANTA_206401-1_RV CONN@
CONN@
GND
GND
GND
GND GND
1
SATA_STX_C_DRX_P1
2
A+
SATA_STX_C_DRX_N1
3
A-
4
SATA_SRX_DTX_N1
5
B-
SATA_SRX_DTX_P1
6
B+
7
8
DP
9
+5V
10
+5V
11
MD
12 13
+5VS
USB Port 0 & Port1
C339
C339 220U_6.3V_M
220U_6.3V_M
USB_EN#
1
C340
C340
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
USB_EN#<28>
+USB_VCCA
1
+
+
2
W=40mils
C1143 0.01U_0402_25V7KC1143 0.01U_0402_25V7K C1138 0.01U_0402_25V7K C1138 0.01U_0402_25V7K
C1137 0.01U_0402_25V7K C1137 0.01U_0402_25V7K C1136 0.01U_0402_25V7K C1136 0.01U_0402_25V7K
+5VS
1.1A
1
C1144
C1144 10U_0805_10V4Z
10U_0805_10V4Z
2
1.4A
U48
U48
1
GND
VOUT
2
VOUT
VIN VIN3VOUT
4
FLG
EN
RT9715BGS_SO8
RT9715BGS_SO8
1
C341
C341 1000P_0402_50V7K
1000P_0402_50V7K
2
2
Close to JODD
1 2 1 2
1 2 1 2
Place components closely ODD CONN.
1
C1145
C1145 10U_0805_10V4Z
10U_0805_10V4Z
2
W=60mils
+USB_VCCA+5VALW
@
8 7 6 5
@
C1157 1000P_0402_50V7K
C1157 1000P_0402_50V7K
1
C1158
C1158
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
@
@
1
C1146
C1146 @
@
1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
For EMI request
12
USB_OC#0 <19,28>
SATA_STX_DRX_P1 <20> SATA_STX_DRX_N1 <20>
SATA_SRX_C_DTX_N1 <20> SATA_SRX_C_DTX_P1 <20>
1
C1147
C1147
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
+USB_VCCA
1
1
C1148
C1148
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
Reserve for EMI request
R828 0_0402_5%@R828 0_0402_5%@
1 2
L82
L82
USB20_P0<19>
USB20_N0<19>
USB20_N1<19>
USB20_P1<19>
4
4
1
1
WCM-2012-900T_0805
WCM-2012-900T_0805
1 2
R829 0_0402_5%@R829 0_0402_5%@ R830 0_0402_5%@R830 0_0402_5%@
1 2
L83
L83
1
1
4
4
WCM-2012-900T_0805
WCM-2012-900T_0805
1 2
R831 0_0402_5%@R831 0_0402_5%@
USB20_P0_R
3
3
USB20_N0_R
2
2
USB20_N1_R
2
2
USB20_P1_R
3
3
7/9 Mount L82,L83 ,Reserve R828,R830 for EMI request
W=40mils
1
C342
C342
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
1
C343
C343
1000P_0402_50V7K
1000P_0402_50V7K
2
JUSB1
@JUSB1
@
VCC D­D+ GND
GND GND GND GND
5 6 7 8
2
USB20_N1_R USB20_P1_R
2
3
D10
D10 @
@
PJDLC05_SOT23-3
PJDLC05_SOT23-3
1
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
401982
401982
+3V_WLAN
+1.5VS
JWLAN
JWLAN
1
1
3
CLKREQ_MCARD2#<19>
CLK_PCIE_MCARD2#<18> CLK_PCIE_MCARD2<18>
PCIE_PTX_C_IRX_N2<11> PCIE_PTX_C_IRX_P2<11>
PCIE_ITX_C_PRX_N2<11>
A A
E51_TXD<28> E51_RXD<28>
PCIE_ITX_C_PRX_P2<11>
WLAN/ WiFi
RM16 0_0402_5%RM16 0_0402_5%
1 2 1 2
RM15 0_0402_5%RM15 0_0402_5%
BT_CTRL BT_CTRL E51_RXD_R
+3V_WLAN
E51_RXD_R
Debug card using
5
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
33
33
35
35
37
37
39
39
41
41
43
43
45
45
47
47
49
49
51
51
53
GND1
FOX_AS0B226-S40N-7F
FOX_AS0B226-S40N-7F CONN@
CONN@
GND2
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
1 A1 A
PLT_RST#
7/25 Reserver DM2 for +3V_WLAN is +3VS
R50 1K_0402_5%R50 1K_0402_5%
1 2
7/25 Add R50 for Intel Rainbow Peak module
WL_OFF# <28>
PLT_RST# <12,15,18,24,28,29>
SMB_CK_CLK1 <19> SMB_CK_DAT1 <19>
USB20_N8 <19> USB20_P8 <19>
4
USB20_N0_R USB20_P0_R
2
3
D9
D9 @
@
PJDLC05_SOT23-3
PJDLC05_SOT23-3
1
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
1 2 3 4
ALLTOP C107L8-10405-L
ALLTOP C107L8-10405-L
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
JUSB2
@JUSB2
@
1 2 3 4
ALLTOP C107L8-10405-L
ALLTOP C107L8-10405-L
5
GND
VCC
6
GND
D-
7
GND
D+
8
GND
GND
1
B
B
B
of
23 40Wednesday, September 01, 2010
of
23 40Wednesday, September 01, 2010
of
23 40Wednesday, September 01, 2010
A
CL1 0.1U_0402_16V7KCL1 0.1U_0402_16V7K
PCIE_PTX_C_IRX_P3<11> PCIE_PTX_C_IRX_N3<11>
CLKREQ_LAN#<19>
YL1
1 1
1
CL26
CL26
27P_0402_50V8J
27P_0402_50V8J
1K_0402_1%
1K_0402_1%
2
+3VS
12
RL6
RL6 @
@
ISOLATEB
YL1
LAN_X1 LAN_X2
1 2
25MHZ_20PF_7A25000012
25MHZ_20PF_7A25000012
CL27
CL27
27P_0402_50V8J
27P_0402_50V8J
RTL8105E
Pin14
2 2
RL7
RL7
15K_0402_5%
15K_0402_5%
Pin15 Pin38
1 2
CL2 0.1U_0402_16V7KCL2 0.1U_0402_16V7K
1 2
PCIE_ITX_C_PRX_P3<11>
PCIE_ITX_C_PRX_N3<11>
RL19 0_0402_5%RL19 0_0402_5%
PLT_RST#<12,15,18,23,28,29>
CLK_PCIE_LAN<18>
1
2
CLK_PCIE_LAN#<18>
EC_SWI#<19>
+3V_LAN
RTL8111E
NC
NC NC 10K ohm PD 1K ohm Pull-high
PCIE_PTX_IRX_P3
PCIE_PTX_IRX_N3
PCIE_ITX_C_PRX_P3 PCIE_ITX_C_PRX_N3
CLKREQ_LAN#_R PLT_RST# CLK_PCIE_LAN
CLK_PCIE_LAN#
LAN_X1
LAN_X2
EC_SWI#
ISOLATEB
RL22 1K_0402_5%RL22 1K_0402_5%
1 2
ENSWREG
+LAN_VDDREG
1 2
RL5 2.49K_0402_1%RL5 2.49K_0402_1%
B
UL1
UL1
22
HSOP
23
HSON
17
HSIP
18
HSIN
16
CLKREQB
25
PERSTB
19
REFCLK_P
20
REFCLK_N
43
CKXTAL1
44
CKXTAL2
28
LANWAKEB
26
ISOLATEB
14
NC/SMBCLK
15
NC/SMBDATA
38
GPO/SMBALERT
33
ENSWREG
34
VDDREG
35
VDDREG
46
RSET
24
GND
49
PGND
RTL8105E-VB QFN _6X6
RTL8105E-VB QFN _6X6
8105E_VB@
8105E_VB@
LED3/EEDO LED1/EESK
LED0
EECS/SCL
EEDI/SDA
MDIP0 MDIN0 MDIP1
MDIN1 NC/MDIP2 NC/MDIN2 NC/MDIP3 NC/MDIN3
DVDD10 DVDD10 DVDD10
DVDD33 DVDD33
AVDD33 AVDD33 AVDD33 AVDD33
EVDD10 AVDD10
AVDD10 AVDD10 AVDD10
REGOUT
31 37 40
RL2 10K_0402_5%RL2 10K_0402_5%
30
RL1 10K_0402_5%RL1 10K_0402_5%
32
LAN_MDI0+
1
LAN_MDI0-
2
LAN_MDI1+
4
LAN_MDI1-
5 7 8 10 11
13 29 41
27 39
12 42 47 48
21 3
6 9 45
36
+LAN_VDD10
+3V_LAN
+LAN_EVDD10 +LAN_VDD10
+LAN_REGOUT
12 12
UL1
UL1
8105E_VC@
8105E_VC@
C
LL1,CL13 will be changed to
2.2uH&4.7uF after EVT test
LL1
8105E_VB@LL1
8105E_VB@
1 2
2.2UH +-5% NLC252018T-2R2J-N
2.2UH +-5% NLC252018T-2R2J-N
8105E_VB@
8105E_VB@
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
12
LL20_0603_5% LL20_0603_5%
CL18
CL18
1U_0402_6.3V4Z
1U_0402_6.3V4Z
+3V_LAN
+LAN_REGOUT
Layout Note: LL1 must be within 200mil to Pin36, CL13,CL9 must be within 200mil to LL1 +LAN_REGOUT: Width =60mil
+LAN_VDD10
Close to Pin 21
+3V_LAN
8105E_VB@
8105E_VB@
12
LL30_0603_5%
LL30_0603_5%
8105E_VB@
8105E_VB@
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
CL28
CL28
CL13
CL13
+LAN_EVDD10
1
2
1
2
D
2
1
1
2
2
CL17
CL17
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
+LAN_VDDREG
2
CL29
CL29 8105E_VB@
8105E_VB@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
+LAN_VDD10
CL9
CL9 8105E_VB@
8105E_VB@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
E
Close to Pin 27,39,12,47,48
1 2 1 2 1 2 1 2
Close to Pin 3,6,9,13,29,41,45
1 2 1 2 1 2 1 2
+3V_LAN
CL100.1U_0402_16V4Z CL100.1U_0402_16V4Z CL40.1U_0402_16V4Z CL40.1U_0402_16V4Z CL50.1U_0402_16V4Z CL50.1U_0402_16V4Z CL60.1U_0402_16V4Z CL60.1U_0402_16V4Z
+LAN_VDD10
CL190.1U_0402_16V4Z CL190.1U_0402_16V4Z CL200.1U_0402_16V4Z CL200.1U_0402_16V4Z CL210.1U_0402_16V4Z CL210.1U_0402_16V4Z CL220.1U_0402_16V4Z CL220.1U_0402_16V4Z
+3VALW TO +3V_LAN
+3VALW
RL25
RL25
100K_0402_5%
100K_0402_5%
@
@
WOL_EN#<28>
3 3
4 4
CL12
CL12
0.1U_0402_16V7K
0.1U_0402_16V7K
1 2
1 2
RL16 47K_0402_5%
RL16 47K_0402_5%
@
@
CL14
CL14
0.01U_0402_25V7K
0.01U_0402_25V7K
A
+3VALW
Vgs=-4.5V,Id=3A,Rds<97mohm
2
QL1
QL1
@
@
G
G
1
2
@
@
1
AO3413_SOT23
AO3413_SOT23
@
@
2
CL15
CL15
@
@
4.7U_0805_10V4Z
4.7U_0805_10V4Z
Place these components colsed to LAN chip
S
S
D
D
1 3
1
CL8
CL8
2
LAN_MDI1­LAN_MDI1+
LAN_MDI0­LAN_MDI0+
1
PJ28
PJ28
1
JUMP_43X39
JUMP_43X39 @
@
2
2
1
2
@
@
CL710U_0805_10V4Z CL710U_0805_10V4Z
1U_0402_6.3V4Z
1U_0402_6.3V4Z
1
CL34
CL34
0.1U_0402_25V6
0.1U_0402_25V6
2
+3V_LAN
7/16 Change UL1 from RTL8105E-VB (SA00003PO10) to RTL8105E-VC (SA00003PO20)
7/16 For LDO mode :
1. Remove RL4, mount RL23.
2. Remove LL1, CL13, CL9, LL3, CL28, CL29.
CL310U_0805_10V4Z CL310U_0805_10V4Z
CLKREQ_LAN#_R
EC_SWI#
RL10 10K_0402_5%@ RL10 10K_0402_5%@
RL3 10K_0402_5%@RL3 10K_0402_5%@
8/7 Chagne UL4 from NS681680 to NS681695
UL4
UL4
1
TD+
2
TD-
3
CT
4
NC
5
NC
6
CT
7
RD+ RD-8RX-
NS681610
NS681610
TX+
RX+
RJ45_MIDI1-
16
RJ45_MIDI1+
15
TX-
14
CT
13
NC
12
NC
11
CT
RJ45_MIDI0-
10
RJ45_MIDI0+
9
7/23 Chagne UL4 from LF-H1201P-2 to NS681680 8/7 Chagne UL4 from NS681680 to NS681695
B
+3V_LAN
RL4
RL4 8105E_VB@
8105E_VB@ 0_0402_5%
ENSWREG
+3V_LAN
12
12
WOL_EN<28>
CL42 1000P_0402_50V7KCL42 1000P_0402_50V7K
12
CL41 1000P_0402_50V7KCL41 1000P_0402_50V7K
12
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1 2
RL15 75_0402_1%RL15 75_0402_1%
1 2
RL13 75_0402_1%RL13 75_0402_1%
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
C
0_0402_5%
RL23
RL23 8105E_VC@
8105E_VC@ 0_0402_5%
0_0402_5%
RL11 0_0402_5%@RL11 0_0402_5%@
RL12 0_0402_5%RL12 0_0402_5%
RJ45_GND
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
ISOLATEBWOL_EN#
RJ45_GND LANGND
D
CL36
CL36
1 2
1000P_1808_3KV7K
1000P_1808_3KV7K
LAN Conn.
change connector to w/o LED (use NPVAA LAN conn. before LAN symol ready)
JLAN
CONN@JLAN
CONN@
8
PR4-
7
RJ45_MIDI1-
RJ45_MIDI1+ RJ45_MIDI0­RJ45_MIDI0+
2
3
1
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
PR4+
6
PR2-
5
PR3-
4
PR3+
3
PR2+
2
PR1-
1
PR1+
SANTA_130452-C
SANTA_130452-C
1
CL37
CL37 120P_0402_ 50VJ
120P_0402_ 50VJ
2
D13
D13 PJDLC05_SOT23-3
PJDLC05_SOT23-3
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
401982
401982
E
1
CL38
CL38
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
2
@
@
24 40Wednesday, September 01, 2010
24 40Wednesday, September 01, 2010
24 40Wednesday, September 01, 2010
SHLD1 SHLD2
9 10
B
B
B
A
1 1
CC2
@ CC2
@
100P_0402_50V8J
100P_0402_50V8J
1 2
RC1
RC1
6.19K_0402_1%
6.19K_0402_1% 12
1
CC3
CC3
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
USB20_N5<19>
+VCC_3IN1
1
CC4
CC4 1U_0402_6.3V4Z
1U_0402_6.3V4Z
SDWP_MSCLK
2
SD_DATA0
+3VS_CR
1 2
+3VS
RC4 0_0603_5%RC4 0_0603_5%
2 2
1
CC1
CC1
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
8/6 Change Net name from v1_8 to +V1_8
USB20_N5 USB20_P5
+V1_8
B
UC1
UC1
1 2
3 4
5 6
7 8
9 10 11 12
REFE DM
DP 3V3_IN
CARD_3V3 V18
XD_CD# SP1
SP2 SP3 SP4 SP5
EPAD
25
17
GPIO0
24
CLK_IN
23
XD_D7
22
SP14
21
SP13
20
SP12
19
SP11
18
SP10
16
SP9
15
SP8
14
SP7
13
SP6
RTS5137-GR QFN 24P_4X4
RTS5137-GR QFN 24P_4X4
CLK_48M_CR_R
SD_DATA2_MS_DATA5 MS_DATA1_SD_DATA3
SDCMD MS_DATA2_SDCLKSD_DATA1 SDCD#
RC5 0_0402_5%RC5 0_0402_5%
RC6 0_0402_5%RC6 0_0402_5%
1 2
1 2
C
MS_DATA2_SDCLK_R
D
CLK_48M_CR <18>USB20_P5<19>
< 48MHz >
7/16 Change UC1 from RTS5138 (SA000030600) to RTS5137 (SA000043500)
for EMI request
CC7
@CC7
@
10P_0402_50V8J
10P_0402_50V8J
@
@
CC8
CC8
10P_0402_50V8J
10P_0402_50V8J
CC9
@CC9
@
10P_0402_50V8J
10P_0402_50V8J
3 3
4 4
A
< 2 in 1 Card Reader >
JREAD
JREAD
D3
CMD
VSS1
VDD
CLK
VSS2
D0 D1 D2
WP
CD
GND1 GND2 GND3 GND4
TAITW_PSDAT3-09GLAS1N14N
TAITW_PSDAT3-09GLAS1N14N
CONN@
CONN@
1 2 3 4 5 6
7 8 9 10 11
12 13 14 15
RC2
@RC2
@
12
1 2
10_0402_5%
10_0402_5%
@
@
RC3
RC3
1 2
12
10_0402_5%
10_0402_5%
RC7
@RC7
@
1 2
12
10_0402_5%
10_0402_5%
MS_DATA1_SD_DATA3
SDCMD
MS_DATA2_SDCLK_R
SD_DATA0
SD_DATA1 SD_DATA2_MS_DATA5 SDWP_MSCLK
SDCD#
MS_DATA2_SDCLK
SDWP_MSCLK
CLK_48M_CR_R
+VCC_3IN1
1
CC5
CC5
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
1
CC6
CC6 1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
Compal Secret Data
Compal Secret Data
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
C
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
401982
401982
401982
of
25 40Wednesday, September 01, 2010
of
25 40Wednesday, September 01, 2010
of
D
25 40Wednesday, September 01, 2010
B
B
B
5
4
3
2
1
Codec
0.1U_0402_16V4Z
1 2
+3VS
RA19 0_0603_5%RA19 0_0603_5%
CA2
D D
+1.5VS
@
@
1 2
RA20 0_0603_5%
RA20 0_0603_5%
CA2
place close to chip
RA1
RA1
+3VS
C C
INT_MIC_CLK<17>
EC_MUTE#
RA22
RA22
4.7K_0402_5%
4.7K_0402_5%
EC control EC_MUTE# behavior: High-state / low-state
B B
INT_MIC_CLK
12
Ext. Mic
INT_MIC_DATA<17>
MIC1_R_L<27> MIC1_R_R<27>
INT_MIC_DATA
RA48
CAM@RA48
CAM@
FBMA-10-100505-301T
FBMA-10-100505-301T
1
CA28
CA28 27P_0402_50V8J
27P_0402_50V8J @
@
2
CA47 0.1U_0603_50V7KCA47 0.1U_0603_50V7K
1 2
CA48 0.1U_0603_50V7KCA48 0.1U_0603_50V7K
1 2
CA49 0.1U_0603_50V7KCA49 0.1U_0603_50V7K
1 2
CA50 0.1U_0603_50V7KCA50 0.1U_0603_50V7K
1 2
1 2
RA27 0_0603_5%RA27 0_0603_5%
12
0_0603_5%
0_0603_5%
EC_MUTE#<28>
AZ_RST_HD#<19>
CA12 100P_0402_50V8JCA12 100P_0402_50V8J
CA8
CA8
1 2
+MIC1_VREFO_L
0.1U_0402_16V4Z
1
CA1
CA1
10U_0805_10V4Z
10U_0805_10V4Z
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
CA7
CA7
10U_0805_10V4Z
10U_0805_10V4Z
2
CA214.7U_0805_10V4Z CA214.7U_0805_10V4Z
12 12
CA224.7U_0805_10V4Z CA224.7U_0805_10V4Z
EC_MUTE#
MONO_IN
SENSE_A
1 2
CA15
CA15
2.2U_0603_6.3V4Z
2.2U_0603_6.3V4Z
DGND
+DVDD_IO
1
+3VS_DVDD
2
35 mA
1
2
1
DVDD
23
LINE1_L
24
LINE1_R
14
LINE2_L
15
LINE2_R
21
MIC1_L
22
MIC1_R
16
MIC2_L
17
MIC2_R
2
GPIO0/DMIC_DATA
3
GPIO1/DMIC_CLK
4
PD#
11
RESET#
12
PCBEEP
13
SENSE A
18
SENSE B
36
CBP
35
CBN
31
MIC1_VREFO_L
43
PVSS2
42
PVSS1
49
DVSS2
7
DVSS1
JUMP_43X39
JUMP_43X39
9
46
PVDD139PVDD2
DVDD_IO
SPK_OUT_L+
SPK_OUT_L-
SPK_OUT_R+
SPK_OUT_R-
SDATA_OUT
MIC2_VREFO
MIC1_VREFO_R
ALC259-GR_QFN48_7X7
ALC259-GR_QFN48_7X7
+PVDD1
JA1
JA1
@
@
+PVDD2
+PVDD2
1
CA61
CA61
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
+AVDD
AVDD125AVDD2
HP_OUT_L
HP_OUT_R
SYNC BCLK
SDATA_IN
EAPD
SPDIFO
MONO_OUT
LDO_CAP
VREF
JDREF
CPVEE
AVSS1 AVSS2
600 mA
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
CA57
CA57
2
2
1
place close to chip
1
68 mA
38
UA1
UA1
40 41
45 44
32 33
10 6
5 8
47 48 20
29 30
28 27 19 34 26
37
2
10U_0805_10V4Z
10U_0805_10V4Z
1
CA3
CA3
CA4
CA4
2
10U_0805_10V4Z
10U_0805_10V4Z
RA4 75_0402_1%RA4 75_0402_1% RA5 75_0402_1%RA5 75_0402_1%
AZ_SDIN0_HD_R
AC_VREF AC_JDREF
RA9 20K_0402_1%RA9 20K_0402_1%
1 2
CA14 2.2U_0603_6.3V4ZCA14 2.2U_0603_6.3V4Z
AGND
10U_0805_10V4Z
10U_0805_10V4Z
10U_0805_10V4Z
10U_0805_10V4Z
1 2
0_0603_5%
0_0603_5%
1
CA56
CA56
2
1 2
0_0603_5%
0_0603_5%
1
CA63
@ CA63
@
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
CA5
CA5
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
SPKL+ <27> SPKL- <27>
SPKR+ <27> SPKR- <27>
RA6 33_0402_5%RA6 33_0402_5%
+MIC2_VREFO +MIC1_VREFO_R
12
RA2
RA2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
CA44
CA44
2
RA11
RA11
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
CA62
CA62
@
@
CA6
CA6
12
@
@
2
RA3
RA3
1 2
0_0603_5%
0_0603_5%
1
place close to chip
2
HP_L <27> HP_R <27>
AZ_SYNC_HD <19>
AZ_BITCLK_HD <19>
AZ_SDOUT_HD <19>
AZ_SDIN0_HD <19>
CA23 10U_0805_10V4ZCA23 10U_0805_10V4Z
1 2
1
CA17
CA17
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
place close to chip
+5VS
1
CA43
CA43
2
10U_0805_10V4Z
10U_0805_10V4Z
+5VS
1
CA58
@ CA58
@
2
10U_0805_10V4Z
10U_0805_10V4Z
+5VS
1
CA16
CA16 10U_0805_10V4Z
10U_0805_10V4Z
2
@
@
Beep sound
EC Beep
EC_BEEP#<28>
PCI Beep
PCH_SPKR<19>
place close to chip
+MIC1_VREFO_R +MIC1_VREFO_L +MIC2_VREFO
1
@
@
CA52
CA52 1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
1 2
47K_0402_5%
47K_0402_5%
1 2
47K_0402_5%
47K_0402_5%
1
@
@
CA51
CA51 1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
RA7
RA7
RA8
RA8
10K_0402_5%
10K_0402_5%
RA12
RA12
12
1
2
CA46
CA46 1U_0402_6.3V4Z
1U_0402_6.3V4Z
CA13
CA13
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
CA18
CA18
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
@
@
MONO_IN
Sense Pin
SENSE A
A A
Impedance
39.2K 20K 10K
5.1K
39.2K 20K 10K
5
Codec Signals
PORT-I (PIN 32, 33) PORT-B (PIN 21, 22) PORT-C (PIN 23, 24) (PIN 48) PORT-E (PIN 14, 15) PORT-F (PIN 16, 17)SENSE B PORT-H (PIN 20)
Function
Headphone out Ext. MIC
place close to chip
MIC_SENSE<27>
NBA_PLUG<27>
4
RA10 20K_0402_1%RA10 20K_0402_1%
RA21 39.2K_0402_1%RA21 39.2K_0402_1%
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
12
SENSE_A
Compal Secret Data
Compal Secret Data
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
3
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843 401982
401982
401982
Wednesday, September 01, 2010
Wednesday, September 01, 2010
Wednesday, September 01, 2010
1
26 40
26 40
26 40
B
B
B
5
4
3
2
1
Speaker Connector
D D
placement near Audio Codec
RA30
SPKL+<26>
SPKL-<26>
SPKR+<26>
C C
SPKR-<26>
SPKL+
SPKL-
SPKR+
SPKR-
RA30
0_0603_5%
0_0603_5%
RA34
RA34
0_0603_5%
0_0603_5%
RA23
RA23
0_0603_5%
0_0603_5%
RA24
RA24
0_0603_5%
0_0603_5%
12
CA31
CA31
CA33
CA33
12
12
CA34
CA34
CA36
CA36
12
1
10U_0805_10V4Z@
10U_0805_10V4Z@ 2
1
10U_0805_10V4Z@
10U_0805_10V4Z@ 2
1
10U_0805_10V4Z@
10U_0805_10V4Z@ 2
1
10U_0805_10V4Z@
10U_0805_10V4Z@ 2
SPK_L1
2
CA32
CA32 1U_0402_6.3V4Z
1U_0402_6.3V4Z @
@
1
SPK_L2
SPK_R1
2
CA35
CA35 1U_0402_6.3V4Z
1U_0402_6.3V4Z @
@
1
SPK_R2
SPK_L1 SPK_L2 SPK_R1 SPK_R2
DA5 AZ5125-02S.R7G@ DA5 AZ5125-02S.R7G@
1
DA10 AZ5125-02S.R7G@DA10 AZ5125-02S.R7G@
1
2 3
3 2
JSPK
JSPK
1
1
2
2
3
3
4
4
ACES_85204-0400N
ACES_85204-0400N CONN@
CONN@
Ext.MIC/LINE IN JACK
MIC1_R_R<26>
MIC1_R_L<26>
RA33
RA33
1K_0402_5%
1K_0402_5%
1K_0402_5%
1K_0402_5%
RA32
RA32
RA31
RA31
12
2.2K_0402_5%
2.2K_0402_5%
12
12
12
2.2K_0402_5%
2.2K_0402_5%
RA29
RA29
MIC1_R
MIC1_L
+MIC1_VREFO_R
+MIC1_VREFO_L
HeadPhone/LINE Out JACK
B B
NBA_PLUG<26>
HP_R<26> HP_L<26>
LA10
LA10
1 2
KC FBM-L11-160808-121LMT 0603
KC FBM-L11-160808-121LMT 0603 LA12
LA12
1 2
KC FBM-L11-160808-121LMT 0603
KC FBM-L11-160808-121LMT 0603
1
DA8 PJDLC05_SOT23-3
PJDLC05_SOT23-3
HP_R_L HP_L_L
3 2
@DA8
@
CA53
CA53
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
CA54
CA54
1
CA11
@CA11
@
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
For EMI
Ext.MIC/LINE IN JACK
MIC_SENSE<26>
MIC1_R
A A
LA8
LA8
1 2
KC FBM-L11-160808-121LMT 0603
KC FBM-L11-160808-121LMT 0603 LA13
LA13
1 2
KC FBM-L11-160808-121LMT 0603
KC FBM-L11-160808-121LMT 0603
5
MIC1_L_R MIC1_L_LMIC1_L
1
DA9
@DA9
@
PJDLC05_SOT23-3
PJDLC05_SOT23-3
3 2
CA55
CA55
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
CA59
CA59
1
CA30
@CA30
@
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
For EMI
4
JLINE
JLINE
5
5
5
4
4
4
3
3
3
6 7
6
6
2
2
2
1
1
1
FOX_JA63331-B39S4-7F
FOX_JA63331-B39S4-7F CONN@
CONN@
10
GND
GND
9
GND
GND
8
8
8 7
7
7/23 Change JLINE/JEXMIC to FOX_JA6331-B39S4-7F for DFX
JEXMIC
JEXMIC
5
5
5
4
4
4
3
3
3
6 7
6
6
2
2
2
1
1
1
FOX_JA63331-B39S4-7F
FOX_JA63331-B39S4-7F CONN@
CONN@
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
10
GND
GND
9
GND
GND
8
8
8 7
7
Compal Secret Data
Compal Secret Data
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
3
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
401982
401982
27 40Wednesday, September 01, 2010
27 40Wednesday, September 01, 2010
27 40Wednesday, September 01, 2010
1
B
B
B
of
of
of
5
4
3
2
1
+3VL
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C1190
C1190
0.1U_0402_16V4Z
0.1U_0402_16V4Z
for EMI request
D D
@
@
10_0402_5%
10_0402_5%
@
@
10P_0402_50V8J
10P_0402_50V8J
+3VL
R859
R859 47K_0402_5%
47K_0402_5%
C1197 0.1U_0402_16V4ZC1197 0.1U_0402_16V4Z
C C
+3VL
1 2
R862 47K_0402_5%R862 47K_0402_5%
1 2
R864 47K_0402_5%R864 47K_0402_5%
R855
R855
C1196
C1196
12
12
CLK_PCI_EC
12
1
2
ECRST#
KSI[0..7]<29>
KSO[0..17]<29>
KSO1 KSO2
1
2
2
GATEA20<19> KB_RST#<19> SERIRQ<18,29>
LPC_FRAME#<18,29>
LPC_AD3<18,29>
LPC_AD2<18,29>
LPC_AD1<18,29>
LPC_AD0<18,29>
CLK_PCI_EC<18,22>
PLT_RST#<12,15,18,23,24,29> EC_SCI#<19>
KSI[0..7]
KSO[0..17]
to avoid EC entry ENE test mode
RP1
RP1
EC_SMB_CK1
+3VL +3VS
1 8
EC_SMB_DA1
2 7
EC_SMB_CK2
3 6
EC_SMB_DA2
4 5
2.2K_0804_8P4R_5%
2.2K_0804_8P4R_5%
7/7 Change WOL_EN from pin 103 to pin 17
B B
7/6 For Power LED PWM function
R872
R872
CRY2CRY1
1 2
10M_0402_5%
10M_0402_5%
@
@
1
C1199
C1199
@
@
18P_0402_50V8J
18P_0402_50V8J
1
2
2
32.768KHZ_12.5PF_Q13MC14610002
32.768KHZ_12.5PF_Q13MC14610002
1
C1200
C1200
Y5
Y5
2
@
@
OSC4OSC
NC3NC
18P_0402_50V8J
18P_0402_50V8J
RTCCLK<18>
@
@
EC_SMB_CK1<33> EC_SMB_DA1<33> EC_SMB_CK2<7> EC_SMB_DA2<7>
PM_SLP_S3#<19>
PM_SLP_S5#<19>
EC_SMI#<19> 75W_65W<34> WOL_EN<24>
EC_INVT_PWM<17>
FAN_SPEED1<5>
E51_TXD<23>
E51_RXD<23>
ON/OFFBTN#<30>
PWR_LED#<30> NUM_LED#<29>
CRY1 CRY2
7/2 For EC Crystal cost down
0.1U_0402_16V4Z
1
C1192
C1192
C1191
C1191
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
GATEA20 SERIRQ
LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0
CLK_PCI_EC PLT_RST# ECRST# EC_SCI#
EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2
PM_SLP_S3# PM_SLP_S5# EC_SMI#
EC_INVT_PWM FAN_SPEED1
E51_TXD E51_RXD ON/OFFBTN# PWR_LED# NUM_LED#
R991 0_0402_5%@R991 0_0402_5%@ R992 0_0402_5%@R992 0_0402_5%@ R990 0_0402_5%R990 0_0402_5%
R246
R246
100K_0402_5%
100K_0402_5%
1
C1193
C1193
2
1000P_0402_50V7K
1000P_0402_50V7K
KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6
KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9
KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17
12
2
2
C1195
C1195
C1194
C1194
1000P_0402_50V7K
1000P_0402_50V7K
1
1
U52
U52
1
GA20/GPIO00
2
KBRST#/GPIO01
3
SERIRQ#
4
LFRAME#
5
LAD3
7
LAD2
8
LAD1
10
LPC & MISC
LPC & MISC
LAD0
12
PCICLK
13
PCIRST#/GPIO05
37
ECRST#
20
SCI#/GPIO0E
38
CLKRUN#/GPIO1D
55
KSI0/GPIO30
56
KSI1/GPIO31
57
KSI2/GPIO32
58
KSI3/GPIO33
59
KSI4/GPIO34
60
KSI5/GPIO35
61
KSI6/GPIO36
62
KSI7/GPIO37
39
KSO0/GPIO20
40
KSO1/GPIO21
41
KSO2/GPIO22
42
KSO3/GPIO23
43
KSO4/GPIO24
44
KSO5/GPIO25
45
KSO6/GPIO26
46
KSO7/GPIO27
47
KSO8/GPIO28
48
KSO9/GPIO29
49
KSO10/GPIO2A
50
KSO11/GPIO2B
51
KSO12/GPIO2C
52
KSO13/GPIO2D
53
KSO14/GPIO2E
54
KSO15/GPIO2F
81
KSO16/GPIO48
82
KSO17/GPIO49
77
SCL1/GPIO44
78
SDA1/GPIO45
79
SCL2/GPIO46
80
SDA2/GPIO47
6
PM_SLP_S3#/GPIO04
14
PM_SLP_S5#/GPIO07
15
EC_SMI#/GPIO08
16
LID_SW#/GPIO0A
17
SUSP#/GPIO0B
18
PBTN_OUT#/GPIO0C
19
EC_PME#/GPIO0D
25
EC_THERM#/GPIO11
28
FAN_SPEED1/FANFB1/GPIO14
29
FANFB2/GPIO15
30
EC_TX/GPIO16
31
EC_RX/GPIO17
32
ON_OFF/GPIO18
34
PWR_LED#/GPIO19
36
NUMLED#/GPIO1A
122
XCLK1
123
XCLK0
1
@
@ C1206
C1206
2
18P_0402_50V8J
18P_0402_50V8J
Int. K/B
Int. K/B Matrix
Matrix
SM Bus
SM Bus
7/20 PVT reserve C1199,Y5, C1200
A A
R874 100K_0402_5%R874 100K_0402_5% R783 100K_0402_5%R783 100K_0402_5%
12
1 2
12
C1238 0.1U_0402_16V4Z@C1238 0.1U_0402_16V4Z@
For ESD request
5
E51_TXD
PLT_RST#
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
+3VL
9
22
33
96
111
125
VCC
VCC
VCC
VCC
VCC
VCC
INVT_PWM/PWM1/GPIO0F
ACOFF/FANPWM2/GPIO13
PWM Output
PWM Output
AD Input
AD Input
DA Output
DA Output
PS2 Interface
PS2 Interface
TP_DATA/PSDAT3/GPIO4F
SPI Device Interface
SPI Device Interface
SPI Flash ROM
SPI Flash ROM
BATT_CHGI_LED#/GPIO52
GPIO
GPIO
GPO
GPO
GPIO
GPIO
GPI
GPI
GND
GND
GND
GND
GND
11
24
35
94
113
C1188
C1188
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
67
AVCC
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
AD3/GPIO3B
SELIO2#/AD5/GPIO43
DAC_BRIG/DA0/GPIO3C EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
PSCLK1/GPIO4A PSDAT1/GPIO4B PSCLK2/GPIO4C PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
SDICS#/GPXOA00 SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0
SPICLK/GPIO58
CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59
EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
BKOFF#/GPXO08
WL_OFF#/GPXO09
PM_SLP_S4#/GPXID1
ENBKL/GPXID2
AGND
KB926QFE0_LQFP128_14X14
KB926QFE0_LQFP128_14X14
69
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
3
AD4/GPIO42
DA3/GPIO3F
SPIDI/RD#
SPIDO/WR#
SPICS#
GPXO10 GPXO11
GPXID3 GPXID4 GPXID5 GPXID6 GPXID7
V18R
21
EC_BEEP#
23 26
ACOFF
27
BATT_TEMPA
63 64 65
ADP_V
66 75 76
68
EN_DFAN1
70
IREF
71
CHGVADJ
72
EC_MUTE#
83
USB_EN#
84 85 86
TP_CLK
87
TP_DATA
88
VGATE
97
WOL_EN#
98
VLDT_EN
99
LID_SW#
109
EC_SI_SPI_SO
119
EC_SO_SPI_SI
120
SPI_CLK
126
SPI_CS#
128
73 74
FSTCHG
89
BATT_FULL_LED#
90
CAPS_LED#
91
BATT_CHG_LOW_LED#
92 93
SYSON
95
VR_ON
121
ACIN_D
127
EC_RSMRST#
100
EC_LID_OUT#
101
EC_ON
102 103
SB_PWRGD
104
BKOFF#
105
WL_OFF#
106
EC_ID
107 108
7/7 Change ED_ID from pin 108 to pin 107
110 112 114 115
SUSP#
116
PBTN_OUT#
117
USB_OC#0
118
+EC_V18R
124
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
EC_BEEP# <26> ACOFF <32,34>
BATT_TEMPA <33>
ADP_V <34>
EN_DFAN1 <5> IREF <34>
CHGVADJ <34>
EC_MUTE# <26>
USB_EN# <23>
TP_DATA <30>
VGATE <31,38>
WOL_EN# <24> VLDT_EN <31> LID_SW# <29>
EC_SO_SPI_SI <29> SPI_CLK <29> SPI_CS# <29>
BATT_FULL_LED# <30> CAPS_LED# <29>
SYSON <31,36>
EC_RSMRST# <19> EC_LID_OUT# <19> EC_ON <30,31,35>
BKOFF# <17>
WL_OFF# <23>
SUSP# <23,31,37> PBTN_OUT# <19>
USB_OC#0 <19,23>
C448
C448
4.7U_0805_10V4Z
4.7U_0805_10V4Z
TP_CLK <30>
EC_SI_SPI_SO <29>
FSTCHG <34>
SB_PWRGD <19>
1 2
1 2
BATT_CHG_LOW_LED# <30>
VR_ON <31,38>
EC_ID
HL
EC ver. KB926D3
2
R208
R208 100K_0402_5%
100K_0402_5% C387
C387
0.22U_0603_16V4Z
0.22U_0603_16V4Z
+3VL
ACIN_D
BATT_TEMPA ACIN_D
ADP_I <34>
TP_CLK TP_DATA
LID_SW#
SYSON
R867 330K_0402_5%R867 330K_0402_5%
1 2
1 2
C1187 100P_0402_50V8JC1187 100P_0402_50V8J
1 2
C1189 100P_0402_50V8JC1189 100P_0402_50V8J
1 2
R861 4.7K_0402_5%R861 4.7K_0402_5%
1 2
R863 4.7K_0402_5%R863 4.7K_0402_5%
+3VALW
12
R86547K_0402_5% R86547K_0402_5%
1 2
R866 4.7K_0402_5%R866 4.7K_0402_5%
D26
D26
2 1
CH751H-40PT_SOD323-2
CH751H-40PT_SOD323-2
+5VS
7/27 Change R867 pull up from +3VALW to +3VL
SUSP#
R869 10K_0402_5%R869 10K_0402_5%
VR_ON
R462 10K_0402_5%R462 10K_0402_5%
UMA_ENBKL <12>
+3VALW
EC_ID
KB926E0
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
401982
401982
Wednesday, September 01, 2010
Wednesday, September 01, 2010
Wednesday, September 01, 2010
R435
R435 100K_0402_5%
100K_0402_5% @
@
1 2
R436
R436 100K_0402_5%
100K_0402_5% @
@
1 2
1
12 12
ACIN <20,34>
of
28 40
of
28 40
of
28 40
B
B
B
SPI Flash (256KB)
+3VL
20mils
1
C1201
C1201
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
SPI_CS#<28>
SPI_CLK<28>
SPI_CLK
SPI_CS# SPI_CLK
R877
1 2
10_0402_5%
10_0402_5%
reserve for EMI, close to U13
KEYBOARD CONN.
KSI[0..7]
KSO[0..17]
JKB
JKB
ACES_88170-3400
ACES_88170-3400 CONN@
CONN@
34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9 8 7 6 5 4 3 2 1
KSI[0..7] <28>
KSO[0..17] <28>
JKB34 KSO16
KSO17
KSO2 KSO1 KSO0 KSO4 KSO3 KSO5 KSO14 KSO6 KSO7 KSO13 KSO8 KSO9 KSO10 KSO11 KSO12 KSO15 KSI7 KSI2 KSI3 KSI4 KSI0 KSI5 KSI6 KSI1 JKB4
CAPS_LED# NUM_LED#
1 2
R881 300_0402_5%R881 300_0402_5%
R882 300_0402_5%R882 300_0402_5%
7/7 Change U13 from MXIC to WINBOND for EOL
U13
U13
8
VCC
3
W
7
HOLD
1
S
6
C
5
D
W25X20BVSNIG SOIC 8P
W25X20BVSNIG SOIC 8P
VSS
4
2
Q
EC_SI_SPI_SO <28>EC_SO_SPI_SI<28>
8/6 Change U13 footprint to M25P10-AVMN6T_SO8
@R877
@
1 2
C1205 10P_0402_50V8J@C1205 10P_0402_50V8J@
please close to JKB1
12
+3VS
+3VS
CAPS_LED# <28> NUM_LED# <28>
KSO16 KSO17 KSO2 KSO1 KSO0 KSO4 KSO3 KSO5
KSO14
KSO6 KSO7
KSO13
KSO8
KSO9 KSO10 KSO11 KSO12 KSO15
KSI7 KSI2 KSI3 KSI4 KSI0 KSI5 KSI6 KSI1
CAPS_LED#
NUM_LED#
1 2
C1207 100P_0402_50V8JC1207 100P_0402_50V8J
1 2
C1208 100P_0402_50V8JC1208 100P_0402_50V8J
1 2
C1209 100P_0402_50V8JC1209 100P_0402_50V8J
1 2
C1210 100P_0402_50V8JC1210 100P_0402_50V8J
1 2
C1211 100P_0402_50V8JC1211 100P_0402_50V8J
1 2
C1212 100P_0402_50V8JC1212 100P_0402_50V8J
1 2
C1213 100P_0402_50V8JC1213 100P_0402_50V8J
1 2
C1214 100P_0402_50V8JC1214 100P_0402_50V8J
1 2
C1215 100P_0402_50V8JC1215 100P_0402_50V8J
1 2
C1216 100P_0402_50V8JC1216 100P_0402_50V8J
1 2
C1217 100P_0402_50V8JC1217 100P_0402_50V8J
1 2
C1218 100P_0402_50V8JC1218 100P_0402_50V8J
1 2
C1219 100P_0402_50V8JC1219 100P_0402_50V8J
1 2
C1220 100P_0402_50V8JC1220 100P_0402_50V8J
1 2
C1221 100P_0402_50V8JC1221 100P_0402_50V8J
1 2
C1222 100P_0402_50V8JC1222 100P_0402_50V8J
1 2
C1223 100P_0402_50V8JC1223 100P_0402_50V8J
1 2
C1224 100P_0402_50V8JC1224 100P_0402_50V8J
1 2
C1225 100P_0402_50V8JC1225 100P_0402_50V8J
1 2
C1226 100P_0402_50V8JC1226 100P_0402_50V8J
1 2
C1227 100P_0402_50V8JC1227 100P_0402_50V8J
1 2
C1228 100P_0402_50V8JC1228 100P_0402_50V8J
1 2
C1229 100P_0402_50V8JC1229 100P_0402_50V8J
1 2
C1230 100P_0402_50V8JC1230 100P_0402_50V8J
1 2
C1231 100P_0402_50V8JC1231 100P_0402_50V8J
1 2
C1232 100P_0402_50V8JC1232 100P_0402_50V8J
1 2
C1233 100P_0402_50V8JC1233 100P_0402_50V8J
1 2
C1234 100P_0402_50V8JC1234 100P_0402_50V8J
Lid SW
+3VALW
U54
U54 APX9132ATI-TRL_SOT23-3
APX9132ATI-TRL_SOT23-3
VDD2VOUT
1
C1202
C1202
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
GND
1
10P_0402_50V8J
10P_0402_50V8J
3
C1203
C1203
LPC Debug Port
LID_SW# <28>
1
2
SERIRQ<18,28>
LPC_AD3<18,28>
LPC_AD1<18,28>
LPC_FRAME#<18,28>
Please place the PAD under DDR DIMM.
+3VS
H7
56
7
8
9
10
DEBUG_PAD@H7DEBUG_PAD@
4
3
2
1
R876
R876 22_0402_5%
22_0402_5% @
@
1 2 2
C1204
C1204 22P_0402_50V8J
22P_0402_50V8J
1
@
@
PLT_RST# <12,15,18,23,24,28>
LPC_AD2 <18,28>
LPC_AD0 <18,28>
CLK_PCI_SIO <18,22>
reserve for EMI
Security Classification
Security Classification
Security Classification
2010-08-25 2010-08-25
2010-08-25 2010-08-25
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2010-08-25 2010-08-25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
401982
401982
Wednesday, September 01, 2010
Wednesday, September 01, 2010
Wednesday, September 01, 2010
of
29 40
of
29 40
of
29 40
B
B
B
5
Power Button
debug phase using
SW6
DEBUG@SW6
DEBUG@
BTM side
D D
1 2
SMT1-05-A_4P
SMT1-05-A_4P
5
6
+3VL
R883
R883 100K_0402_5%
100K_0402_5%
1 2
3 4
ON/OFFBTN#
1
C1235
C1235
0.1U_0402_25V6
0.1U_0402_25V6 @
@
2
EC_ON<28,31,35>
10K_0402_5%
10K_0402_5%
For EMI request
R884
R884
4
61
2
1 2
51_ON# <32>
Q163A
Q163A 2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
3
2
< Touch / B Connector >
< Power / B Connector > Right Switch
SW4
SW4
1 2
SW1
SW1
1 2
ON/OFFBTN#<28>
D12
D12 @
@
AZ5125-02S.R7G
AZ5125-02S.R7G
ON/OFFBTN#
2
JPOWER
JPOWER
1
1
2
2
3
1
3
3
4
4
5
G1
6
G2
ACES_85201-0405N
ACES_85201-0405N
CONN@
CONN@
TP_SWR
Left Switch
TP_SWL
SMT1-05-A_4P
SMT1-05-A_4P
5
6
SMT1-05-A_4P
SMT1-05-A_4P
5
6
1
3 4
TP_CLK<28> TP_DATA<28>
3 4
+5VS
2
1
3
AZ5125-02S.R7G
AZ5125-02S.R7G D11
D11
TP_SWL TP_SWR
JTOUCH
JTOUCH
1
1
2
2
3
3
4
4
5
P-TWO_161021-06021_6P-T
P-TWO_161021-06021_6P-T
5 66G8
CONN@
CONN@
7
G7
8
7/13 For ESD request
Screw Hole
POWER/SUSPEND LED
Vf=1.9V(typ),2.4V(max)
C C
If=20mA(max)
R768 510_0402_5%R768 510_0402_5%
+5VALW
1 2
D67
D67
2 1
YG
YG
HT-110UYG5_YELLOW GREEN
HT-110UYG5_YELLOW GREEN
3
PWR_LED# <28>
7/6 For Power LED PWM function 7/15 Change D67/D70 to 5mA type 7/23 Change R773 from 120 to 510 ohm 7/23 Change Net name from+3VALW to +5VALW
DC IN/ BATT CHARGE
D70
D70
+5VALW
7/23 Change R773 from 120 to 510 ohm 7/23 Change Net name from+3VALW to +5VALW 8/6 Add R774 link to BATT_CHG_LOW_LED# 8/6 Change R773 link to BATT_FULL_LED#
1
HT-210UD5-UYG5_AMBER-YEL GRN
HT-210UD5-UYG5_AMBER-YEL GRN
Vf=1.8V(typ),2.0V(max) for amber Vf=1.8V(typ),2.0V(max) for green If=20mA(max)
R774 510_0402_5%R774 510_0402_5%
2
1 2
A
A
R773 510_0402_5%R773 510_0402_5%
3
YG
YG
1 2
BATT_CHG_LOW_LED# <28>
BATT_FULL_LED# <28>
H5
H5
1
H1
H1
1
H_3P0
H_3P0 @
@
H_2P7x3P2N
H_2P7x3P2N @
@
CPU
H20
H20
H_4P2
H_4P2 @
@
1
H12
H6
H6
H8
H8
H_3P0
H_3P0
H_3P0
H_3P0
@
@
@
H2
H2
H21
H21
1
H_2P7N
H_2P7N @
@
1
H_4P2x4P7
H_4P2x4P7 @
@
@
1
H3
H3
H22
H22
1
1
H9
H9
1
H_1P0N
H_1P0N @
@
1
H_4P2x4P7
H_4P2x4P7 @
@
H_3P0
H_3P0 @
@
H10
H10
H_3P0
H_3P0 @
@
1
H15
H15
H_5P0N
H_5P0N @
@
1
H23
H23
H_4P9
H_4P9 @
@
1
H11
H11
H_3P0
H_3P0 @
@
1
H16
H16
H_5P0N
H_5P0N @
@
1
H12
H_3P0
H_3P0 @
@
1
MINI CARD -- WLAN
H18
H18
H_3P3
H_3P3 @
@
1
H14
H14
H13
H13
1
H_3P0
H_3P0 @
@
H19
H19
H_3P0
H_3P0 @
@
1
H_3P3
H_3P3 @
@
1
PCB Fedical Mark PAD
FD2@FD2
FD1@FD1
@
@
B B
1
FD4@FD4
FD3@FD3
@
@
1
1
1
ESD reserved
7/13 Change P/N to DC30100A400
PJP1
PJP1
DC-IN
PJP1
PJP1 45@
45@
U8
U8
SB820M_FCBGA605_A13
SB820M_FCBGA605_A13 R3@
R3@
7/21 Change P/N to SA00003IWB0
Title
Title
Title
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
401982
401982
401982
Wednesday, September 01, 2010
Wednesday, September 01, 2010
Wednesday, September 01, 2010
of
30 40
of
30 40
of
1
30 40
B
B
B
1
2
@
@
C1263
C1263
0.1U_0402_16V7K
0.1U_0402_16V7K
+5VS
1
2
@
@
C1262
C1262
0.1U_0402_16V7K
0.1U_0402_16V7K
+1.1VS
1
2
C1258
C1258
@
@
Near R972
Compal Secret Data
Compal Secret Data
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
Compal Secret Data
+3VS +3VS
1
2
C1257
C1257
@
@
0.1U_0402_16V7K
0.1U_0402_16V7K
A A
Near H5 Near H11 Near H12 Near H8 Near H13
5
4
B+
1
2
@
@
C1259
C1259
0.1U_0402_16V7K
0.1U_0402_16V7K
C1260
C1260
@
@
0.1U_0402_16V7K
0.1U_0402_16V7K
1
2
C1261
C1261
@
@
0.1U_0402_16V7K
0.1U_0402_16V7K
1
2
Near H14
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
0.1U_0402_16V7K
0.1U_0402_16V7K
Deciphered Date
Deciphered Date
Deciphered Date
ISPD
ZZZ
ZZZ
PCB
NB R3 SB R3
2
PCB SKU LA-6843P Rev10
PCB SKU LA-6843P Rev10
U3
U3
RS880M
RS880M R3@
R3@
Compal Electronics, Inc.
A
< +5VALW TO +5VS >
+5VALW
Q2
Q2
S
D
S
D
S
D
G
D
SI4800BDY_SO8
SI4800BDY_SO8
1 2 3
RUNON
4
8 7 6 5
1
C452
4.7U_0805_10V4Z
4.7U_0805_10V4Z
C452
2
1 1
+5VS
Inrush current = 0A
1
C449
C449 1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
1
C450
C450
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
B
SUSP
+5VS
R250
R250 470_0805_5%
470_0805_5%
1 2 3
5
4
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6 Q34B
Q34B
C
< +1.5V TO +1.5VS >
+1.5V
1
C464
C464
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
7/8 Change Q5 from FDS6676AS to SI4800DBY
Q5
Q5
8
D
7
D
6
D
5
D
SI4800BDY_SO8
SI4800BDY_SO8
S S S G
1 2 3 4
12
1.5VS_ENABLE
R286
R286 10M_0402_5%
10M_0402_5%
D
+1.5VS
Inrush current = 0A
1
C462
C462 1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
1
C466
C466
0.01U_0402_25V7K
0.01U_0402_25V7K
2
2
C463
C463 10U_0805_10V4Z
10U_0805_10V4Z
1
1 2
61
2
Q11A
Q11A 2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
R285
R285 750K_0402_1%
750K_0402_1%
SUSP
+VSB
E
R305
R305 470_0805_5%
470_0805_5%
1 2 3
Q11B
Q11B 2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
5
4
< +1.1VALW TO +1.1VS >< +3VALW TO +3VS >
+3VALW +3VS
Q3
Q3
8
S
D
7
S
D
6
S
D
5
G
D
1
C470
C470
SI4800BDY_SO8
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2 2
< +1.1VALW TO +NB_CORE >
+1.1VALW
1
2
3 3
2
Q7
Q7
IRF8113PBF_SO8
IRF8113PBF_SO8
8 7
5
C480
C480
4.7U_0805_10V4Z
4.7U_0805_10V4Z
SI4800BDY_SO8
4
12
R293
R293 10M_0402_5%
10M_0402_5%
1 2 3 4
1
2
1 2 36
1
2
RUNON
C474
C474
0.01U_0402_25V7K
0.01U_0402_25V7K
Inrush current = 0A
1
C469
C468
C468 1U_0402_6.3V4Z
1U_0402_6.3V4Z
+NB_CORE
C469
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
Inrush current = 0A
1
C479
C479 1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
1
C481
C481
0.01U_0402_25V7K
0.01U_0402_25V7K
2
61
2
Q14A
Q14A 2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
1
C478
C478
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
61
Q13A
Q13A 2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
2
R287
R287 750K_0402_1%
750K_0402_1%
12
12
BOOT_ON
SUSP
R292
R292 330K_0402_5%
330K_0402_5%
+VSB
+VSB
5
R251
R251 470_0805_5%
470_0805_5%
1 2
3
Q14B
Q14B 2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
5
4
R306
R306 470_0805_5%
470_0805_5%
1 2 3
Q13B
Q13B 2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
4
< Inversion of SYSON, SUSP#, VLDT_EN, EC_ON >
+1.1VALW
Q6
Q6
IRF8113PBF_SO8
IRF8113PBF_SO8
8 7
5
1
C475
C475
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
R814
R814
100K_0402_5%
100K_0402_5%
SYSON# SUSP
Q15B
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
Q15B
5
4
12
R291
R291 10M_0402_5%
10M_0402_5%
12
3
4
+1.1VS
1 2 36
+5VALW+5VALW
12
R245
R245 100K_0402_5%
100K_0402_5%
61
Q15A
Q15A 2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
2
Inrush current = 0A
1
C471
C471 1U_0402_6.3V4Z
1U_0402_6.3V4Z
2
1
C476
C476
0.01U_0402_25V7K
0.01U_0402_25V7K
2
SUSP <37>
1
C472
C472
4.7U_0805_10V4Z
4.7U_0805_10V4Z
2
61
1
+
+
C158
C158 @
@ 390U_2.5V_M_R10
390U_2.5V_M_R10
2
R290
R290 330K_0402_5%
330K_0402_5%
12
BOOT_ON
2
Q12A
Q12A 2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
100K_0402_5%
100K_0402_5%
VLDT_EN#
VLDT_EN<28>SUSP# <23,28,37>SYSON<28,36> EC_ON <28,30,35>
VLDT_EN
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
+VSB
Q16A
Q16A
2
R816
R816
5
+5VALW
R300
R300 470_0805_5%
470_0805_5%
1 2
3
Q12B
Q12B 2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
4
12
61
BOOT_ON
+5VALW
12
R815
R815 @
@ 100K_0402_5%
100K_0402_5%
EC_ON#
3
Q16B
Q16B
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
4
R45 0_0402_5%@R45 0_0402_5%@ R46 0_0402_5%R46 0_0402_5% R47 0_0402_5%@R47 0_0402_5%@
5
12 12 12
SUSPBOOT_ON VLDT_EN# VGATE#BOOT_ON
< Discharge circuit >
+1.5V
12
12
R802
R802
100K_0402_5%
100K_0402_5%
VGATE# VR_ON#
3
Q35B
2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
VGATE<28,38>
4 4
Q35B
5
4
A
R803
R803 100K_0402_5%
100K_0402_5%
61
Q35A
Q35A 2N7002DW-T/R7_SOT363-6
2N7002DW-T/R7_SOT363-6
2
VR_ON# <37>
VR_ON <28,38>
R257
R257 470_0805_5%
470_0805_5%
1 2 13
D
SYSON#
B
D
Q17
Q17
2
G
G
2N7002_SOT23-3
2N7002_SOT23-3
S
S
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
SUSP
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
+0.75VS
R258
R258 470_0805_5%
470_0805_5%
1 2 13
D
D
Q10
Q10
2
G
G
2N7002_SOT23-3
2N7002_SOT23-3
S
S
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
+1.8VS +1.1VALW+5VALW +5VALW
R253
R253 470_0805_5%
470_0805_5%
1 2
13
D
2
G
G
D
D
Q23
Q23
2N7002_SOT23-3
2N7002_SOT23-3
S
S
Custom
Custom
Custom
SUSP EC_ON#
R254
R254 @
@ 470_0805_5%
470_0805_5%
1 2 13
D
D
Q22
Q22
2
@
@
G
G
2N7002_SOT23-3
2N7002_SOT23-3
S
S
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
401982
401982
E
31 40Wednesday, September 01, 2010
31 40Wednesday, September 01, 2010
31 40Wednesday, September 01, 2010
B
B
B
A
B
C
D
VIN
PF1
DC301001M80
PJP1
PJP1
1
1 1
2 2
+
2
+
3
-
4
-
@SINGA_2DW-0005-B03
@SINGA_2DW-0005-B03
BATT+
51_ON#<29>
DC_IN_S1 DC_IN_S2
PD3
PD3
RLS4148_LL34-2
RLS4148_LL34-2
100K_0402_1%
100K_0402_1%
1 2
PR15
PR15
22K_0402_1%
22K_0402_1%
PF1
7A_24VDC_429007.WRML
7A_24VDC_429007.WRML
12
PR12
PR12
21
12
1000P_0402_50V7K
1000P_0402_50V7K
12
PC1
PC1
N1
12
PC7
PC7
0.22U_0603_25V7K
0.22U_0603_25V7K
680P_0402_50V7K
680P_0402_50V7K
12
PC17
PC17
PQ1
PQ1 BSS84_SOT23-3
BSS84_SOT23-3
1 2
SMB3025500YA_2P
SMB3025500YA_2P
12
PC2
PC2 100P_0402_50V8J
100P_0402_50V8J
68_1206_5%
68_1206_5%
2
PL1
PL1
PR9
PR9
13
VIN
PD2
PD2 RLS4148_LL34-2
RLS4148_LL34-2
1 2
12
12
PC8
PC8
0.1U_0603_25V7K
0.1U_0603_25V7K
12
PC3
PC3 1000P_0402_50V7K
1000P_0402_50V7K
12
PR10
PR10 68_1206_5%
68_1206_5%
VS
12
PC4
PC4 100P_0402_50V8J
100P_0402_50V8J
VIN
1 2 0_1206_5%
0_1206_5%
@
@ 1 2 1K_1206_5%
1K_1206_5%
@
@ 1 2 1K_1206_5%
1K_1206_5%
@
@ 1 2
1K_1206_5%
1K_1206_5%
@
@ 1 2
1K_1206_5%
1K_1206_5%
ACOFF<28,34>
+5VALWP<35>
PreCHG
PR1
PR1
PR2
PR2
PR5
PR5
PR6
PR6
PR8
PR8
PD4
@ PD4
@
2 3
RB715F_SOT323-3
RB715F_SOT323-3
1
PD1
@ PD1
@
RLS4148_LL34-2
RLS4148_LL34-2
PR3
PR3
100K_0402_5%
100K_0402_5%
2
12
12
@
@
13
DTC115EUA_SC70-3
DTC115EUA_SC70-3
PQ5
12
PR4
PR4
100K_0402_5%
100K_0402_5%
@
@
2
@PQ5
@
PQ2
@PQ2
@
BSS84_SOT23-3
BSS84_SOT23-3
2
12
PR7
PR7
100K_0402_5%
100K_0402_5%
13
DTC115EUA_SC70-3
DTC115EUA_SC70-3
PQ3
PQ3
13
@
@
@
@
B+
PJ1
@ PJ1
@
+3VALWP +3VALW
3 3
+5VALWP
2
112
JUMP_43X118
JUMP_43X118
(5A,200mils, Via NO.= 10) OCP(min) = 8.33A
PJ5
@ PJ5
@
2
112
JUMP_43X118
JUMP_43X118
(5A,200mils, Via NO.= 10)
+5VALW
+1.1VALWP +1.1VALW
(16A,640mils, Via NO.= 32) OCP(min) = 18.7A
OCP(min) = 8.33A
PJ8
@ PJ8
@
+VSBP +VSB
(120mA,40mils, Via NO.= 1)
4 4
2
112
JUMP_43X39
JUMP_43X39
PJ11
@ PJ11
@
2
112
JUMP_43X79
JUMP_43X79
(1.5A,60mils, Via NO.= 3)
+0.75VS+0.75VSP
(9.5A,380mils ,Via NO.= 20) OCP(min) = 8.7A
+1.8VSP +1.8VS
(2.5A,100mils, Via NO.= 5)
PJ2
@ PJ2
@
2
JUMP_43X118
JUMP_43X118
PJ4
@ PJ4
@
2
JUMP_43X118
JUMP_43X118
PJ7
@ PJ7
@
2
JUMP_43X118
JUMP_43X118
PJ10
@ PJ10
@
2
JUMP_43X79
JUMP_43X79
112
112
112
+1.5V+1.5VP
+3VLP +3VL
(100mA,40mils ,Via NO.= 2)
+2.5VSP +2.5VS
(1A,40mils ,Via NO.= 2)
+VDDNBP +VDDNB
(4A,160mils ,Via NO.= 8)
112
+1.05VSP +1.05VS
(1.75A,80mils, Via NO.= 4)
PJ3
@ PJ3
@
2
JUMP_43X39
JUMP_43X39
PJ9
@ PJ9
@
2
JUMP_43X39
JUMP_43X39
PJ12
@ PJ12
@
2
JUMP_43X79
JUMP_43X79
PJ13
@ PJ13
@
2
JUMP_43X79
JUMP_43X79
112
112
112
112
Precharge detector
15.97V/14.84V FOR ADAPTOR
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
C
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
2010-08-252010-08-25
2010-08-252010-08-25
2010-08-252010-08-25
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
D
32 40Wednesday, September 01, 2010
32 40Wednesday, September 01, 2010
32 40Wednesday, September 01, 2010
B
B
B
of
of
of
A
B
C
D
PH1 under CPU botten side :
CPU thermal protection at 95 degree C Recovery at 56 degree C
VMB
PL2
PF2
1 1
2 2
3 3
PJP2
@ PJP2
@
1
1
2
2
3
3
4
4
5
5 GND GND GND GND
6
7
8
9
POK<35,36>
6 7 8 9
100K_0402_1%
100K_0402_1%
10 11 12 13
SUYIN_200045MR009G171ZR
SUYIN_200045MR009G171ZR
BATT_S1 BATT_P3
BATT_P4 BATT_P5 EC_SMDA EC_SMCA
PJSOT24C_SOT23-3
PJSOT24C_SOT23-3
PR38
PR38
100_0402_1%
100_0402_1%
VL
PR47
PR47
1 2
1 2
PD6
PD6
100_0402_1%
100_0402_1%
1 2
PR48
PR48
0_0402_5%
0_0402_5%
1
2
3
2 3
PJSOT24C_SOT23-3
PJSOT24C_SOT23-3
PR39
PR39
12
1 2
PR40
PR40 1K_0402_1%
1K_0402_1%
B+
PR45
PR45
1 2
22K_0402_1%
22K_0402_1%
13
D
D
PQ7
PQ7
2
SSM3K7002FU_SC70-3
SSM3K7002FU_SC70-3
G
G
S
S
12
PC22
PC22
@
@
.1U_0402_16V7K
.1U_0402_16V7K
PF2
10A_125V_451010MRL
10A_125V_451010MRL
12
PR32
PR32 1K_0402_1%
1K_0402_1%
PD8
PD8
1
PR37
PR37
6.49K_0402_1%
6.49K_0402_1%
12
PR43
PR43
100K_0402_1%
100K_0402_1%
21
12
12
PC19 @ PC19
@
+3VLP
+3VLP
BATT_TEMPA <28>
EC_SMB_DA1 <28>
EC_SMB_CK1 <28>
PQ6
PQ6 BSS84_SOT23-3
BSS84_SOT23-3
2
0.22U_0603_25V7K
0.22U_0603_25V7K
PL2
SMB3025500YA_2P
SMB3025500YA_2P
1 2
12
PC14
PC14 1000P_0402_50V7K
1000P_0402_50V7K
13
12
PC20
PC20
@
@
0.1U_0603_25V7K
0.1U_0603_25V7K
12
PC15
PC15
0.01U_0402_25V7K
0.01U_0402_25V7K
+VSBP
BATT+
Rset = 3 * Rtmh Rhyst = (Rset* Rtml) / (3*Rtml - Rset)
Rtmh at 95C = 6.64K, Rtml at 57C = 25.1K Rset = 3 * 6.64K = 19.92K ==> 20K Rhyst = (20K * 25.1K) / (3 * 25.1K - 20K) = 9.078K ==> 9.09K
VL
12
PC16
PC16
0.1U_0402_16V4Z
0.1U_0402_16V4Z
VS_ON<35>
PU3
PU3
1
VCC
TMSNS1
2
GND
RHYST1
3
OT1
TMSNS2
4
RHYST2
OT2
G718TM1U_SOT23-8
G718TM1U_SOT23-8
8 7 6 5
12
PR31
PR31
23.2K_0402_1%
23.2K_0402_1%
PR33
PR33
10.7K_0402_1%
10.7K_0402_1%
1 2
12
PH1
PH1
100K_0402_1%_NCP15WF104F03RC
100K_0402_1%_NCP15WF104F03RC
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
C
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
2010-08-252010-08-25
2010-08-252010-08-25
2010-08-252010-08-25
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
D
33 40Wednesday, September 01, 2010
33 40Wednesday, September 01, 2010
33 40Wednesday, September 01, 2010
B
B
B
A
PQ20B
PQ20B
12
PC26
PC26
5
G
G
P2
12
PR50
PR50 200K_0402_1%
200K_0402_1%
0.1U_0603_25V7K
0.1U_0603_25V7K
12
PR59
PR59 150K_0402_1%
150K_0402_1%
34
D
D
S
S
IREF<28>
PQ10
PQ10
SI4483ADY-T1-GE3_SO8
SI4483ADY-T1-GE3_SO8 1 2 3 6
4
FSTCHG<28>
PR71
PR71
154K_0402_1%
154K_0402_1%
12
PR73
PR73
120K_0402_1%
120K_0402_1%
8 7
5
PC25
PC25 5600P_0402_25V7K
5600P_0402_25V7K
1 2
PR57
PR57
10K_0402_1%
10K_0402_1%
100K_0402_1%
100K_0402_1%
PC35
PC35
1 2
0.01U_0402_25V7K
0.01U_0402_25V7K
ADP_I<28>
12
6251VREF
12
PC42
PC42
0.01U_0402_25V7K
0.01U_0402_25V7K
P3
12
12
PR60
PR60
PC33 6800P_0402_25V7KPC33 6800P_0402_25V7K PR64
PR64
1 2
6.81K_0402_1%
6.81K_0402_1%
1 2
PC37
PC37
.1U_0402_16V7K
.1U_0402_16V7K
PR72
PR72
24K_0402_1%
24K_0402_1%
1 2
PQ9
PQ9
AO4435_SO8
AO4435_SO8 8 7
VIN
1 1
PR52
PR52
200K_0402_1%
200K_0402_1%
BATT_ON
2
G
G
2 2
PACIN
ACOFF<28,32>
6 5
PQ13
PQ13
DTA144EUA_SC70-3
DTA144EUA_SC70-3
12
61
D
D
S
S
2
13
2
PQ20A
PQ20A DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
PR68
PR68
47K_0402_5%
47K_0402_5%
1 2
ACOFF
PQ22
PQ22
DTC115EUA_SC70-3
DTC115EUA_SC70-3
1 2 3
4
1 3
PQ15
PQ15 DTC115EUA_SC70-3
DTC115EUA_SC70-3
13
2
75W_65W<28>
SSM3K7002FU_SC70-3
SSM3K7002FU_SC70-3
3 3
CHGVADJ<28>
15.4K_0402_1%
15.4K_0402_1% 1 2
31.6K_0402_1%
31.6K_0402_1%
CHGVADJ=(Vcell-4)*9.445
Vcell CHGVADJ 4V
4.2V
4.35V
0V
1.882V
3.2935V
CC=0.25A~3.6A IREF=0.9133*Icharge IREF=0.228V~3.29V VCHLIM need over 95mV
(UMA) Iin = 2.512 ADP_I
Vin = 7.57 ADP_V
B
12
12
PC31
PC31
PC130
PR49
PR49
0.02_1206_1%
0.02_1206_1%
PQ39
PQ39
PR76
PR76
2
G
G
1 2
1 2
4 3
6251VDD
ACSETIN
6251_EN CSON
PR66
PR66
47K_0402_1%
47K_0402_1% 1 2
6251VREF
6251aclim
12
12
PR193
PR193
PR75
PR75
12.4K_0402_1%
12.4K_0402_1%
13
D
D
S
S
VADJ
12
PR77
PR77
10U_1206_25V6M
10U_1206_25V6M
12
PC27
PC27
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
20K_0402_1%
20K_0402_1%
47K_0402_1%
47K_0402_1%
ACPRN
DTC115EUA_SC70-3
DTC115EUA_SC70-3
PC130
10U_1206_25V6M
10U_1206_25V6M
RB751V-40_SOD323-2
RB751V-40_SOD323-2
PU4
PU4
1
VDD
2
ACSET
3
EN
4
CELLS
5
ICOMP
6
VCOMP
7
ICM
8
VREF
9
CHLIM
10
ACLIM
11
VADJ
12
GND
ISL6251AHAZ-T_QSOP24
ISL6251AHAZ-T_QSOP24
12
PR240
PR240
2
PQ214
PQ214
B+
10_1206_5%
10_1206_5%
DCIN
ACPRN
CSON
CSOP
CSIN
CSIP
PHASE
UGATE
BOOT
VDDP
LGATE
PGND
12
PC132
PC132
10U_1206_25V6M
10U_1206_25V6M
PD201
PD201
PR227
PR227
24
23
22
21
20
19
18
17
16
15
14
13
6251VDD
12
PR242
PR242
10K_0402_1%
10K_0402_1%
13
VIN
1 2 12
PC217
PC217
1000P_0402_25V8J
1000P_0402_25V8J
PC29
PC29
DCIN
0.1U_0603_25V7K
0.1U_0603_25V7K
PC30
PC30
0.047U_0603_16V7K
0.047U_0603_16V7K 1 2
1 2
PR62 20_0603_5%PR62 20_0603_5%
PC34
PC34
0.1U_0603_25V7K
0.1U_0603_25V7K
1 2
LX_CHG
DH_CHG
PR70
PR70
2.2_0603_5%
2.2_0603_5%
BST_CHG
1 2
6251VDDP
DL_CHG
PR241
PR241
10K_0402_1%
10K_0402_1%
1 2
12
PR243
PR243
14.3K_0402_1%
14.3K_0402_1%
PJ22
@ PJ22
@
2
112
JUMP_43X79
JUMP_43X79
CSIN
CSIP
PreCHG
12
PR226
PR226
191K_0402_1%
191K_0402_1%
ACSETIN
12
12
PR228
PR228
14.3K_0402_1%
14.3K_0402_1%
12
ACPRN<35>
PR61
PR61 20_0603_5%
20_0603_5%
1 2
12
PR63
PR63 20_0603_5%
20_0603_5%
1 2
PR65 2.2_0603_5%PR65 2.2_0603_5%
PC38
PC38
0.1U_0603_25V7K
0.1U_0603_25V7K
BST_CHGA 12
PD14
PD14 RB751V-40_SOD323-2
RB751V-40_SOD323-2
1 2
PR74
PR74
4.7_0603_5%
4.7_0603_5%
PC43
PC43
1 2
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
PACIN
C
12
PC23
PC23
4.7U_0805_25V6-K
4.7U_0805_25V6-K
CSOP
12
6251VDD
ACIN <20,28,29>
Vin Detector
High Low
12
PC24
PC24
4.7U_0805_25V6-K
4.7U_0805_25V6-K
18.089V
17.44V
CHG_B+
12
PC28
PC28
4.7U_0805_25V6-K
4.7U_0805_25V6-K
6
578
4
6
578
4
PQ16
PQ16
DTC115EUA_SC70-3
DTC115EUA_SC70-3
PQ19
PQ19 AO4466L_SO8
AO4466L_SO8
10UH_MSCDRI-104A-100M-E_4.6A_20%
10UH_MSCDRI-104A-100M-E_4.6A_20%
123
12
PR69
PR69
4.7_1206_5%
4.7_1206_5%
12
PC41
PC41
680P_0603_50V7K
PR78
@ PR78
@ 309K_0402_1%
309K_0402_1%
PR80
@ PR80
@ 47K_0402_1%
47K_0402_1%
680P_0603_50V7K
PQ21
PQ21
123
AO4466L_SO8
AO4466L_SO8
1 2
VIN
12
12
PR56
PR56 10K_0402_1%
10K_0402_1%
1 2 13
PL4
PL4
12
AO4435_SO8
AO4435_SO8 1 2 3
2
PR238
PR238
100K_0402_1%
100K_0402_1%
BATT_ON
0.02_1206_1%
0.02_1206_1%
CHG
1 2
@
@
10K_0402_1%
10K_0402_1%
1 2
PC44
PC44
@
@
.1U_0402_16V7K
.1U_0402_16V7K
PQ8
PQ8
4
1 2
47K_0402_1%
47K_0402_1%
12
SSM3K7002FU_SC70-3
SSM3K7002FU_SC70-3
PR67
PR67
PR79
PR79
D
8 7 6 5
PR54
PR54
4 3
12
ACPRN
PC32
PC32
PC39
PC39
VIN
2200P_0402_25V7K
2200P_0402_25V7K
13
D
D
2
G
G
S
S
PQ18
PQ18
12
12
PC40
PC40
@
@
10U_1206_25V6M
10U_1206_25V6M
10U_1206_25V6M
10U_1206_25V6M
ADP_V <28>
BATT+
12
PC48
PC48
10U_1206_25V6M
10U_1206_25V6M
UMA
4 4
Iada=0~3.947A(75W) CP=3.63A
PR49=0.02, PR72=24k, PR75=20k, PR35=11.5K, 75W_65W=highIada=0~3.421A(65W) CP=3.15A
PR49=0.02, PR72=24k, PR75=20k, PR35=11.5K, 75W_65W=low
CP= 92%*Iada
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
C
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843 401982
401982
401982
D
34 40Wednesday, September 01, 2010
34 40Wednesday, September 01, 2010
34 40Wednesday, September 01, 2010
B
B
B
5
4
3
2
1
2VREF_6182
12
PC45
PC45
1U_0603_10V6K
1U_0603_10V6K
D D
PR81
PR81
13K_0402_1%
13K_0402_1%
1 2
PR83
150K_0402_1%
150K_0402_1%
BST_3V UG_3V LX_3V LG_3V
2VREF_6182
PR83
20K_0402_1%
20K_0402_1%
1 2
PR85
PR85
1 2
PU5
PU5
25
P PAD
7
VO2
8
VREG3
9
VBST2
10
DRVH2
11
LL2
12
DRVL2
ENTRIP2
6
5
VFB2
ENTRIP2
SKIPSEL
EN0
14
13
UP6182_B+
4
TONSEL
15
UP6182_B+
PL3
PL3
HCB2012KF-121T50_0805
HCB2012KF-121T50_0805
B+
C C
Ipeak = 7.65A Imax = 5.36A F = 305K
Total capacitor 220uF
12
12
PC50
PC50
PC49
PC49
10U_1206_25V6M
10U_1206_25V6M
2200P_0402_50V7K
2200P_0402_50V7K
+3VALWP
330U_6.3V_M
330U_6.3V_M
12
12
PC51
PC51
10U_1206_25V6M
10U_1206_25V6M
4.7UH_SIL1045R-4R7PF_6.3A_30%
4.7UH_SIL1045R-4R7PF_6.3A_30%
1
+
+
PC55
PC55
2
PL6
PL6
1 2
PR89
PR89
4.7_1206_5%
4.7_1206_5%
PC57
PC57
680P_0603_50V7K
680P_0603_50V7K
6
578
PC52
PC52
4.7U_0805_10V6K
4.7U_0805_10V6K
4
PQ24
PQ24
123
AO4466L_SO8
AO4466L_SO8
786
123
5
4
PQ25
PQ25 AO4712L_SO8
AO4712L_SO8
12
12
0.1U_0603_25V7K
0.1U_0603_25V7K
499K_0402_1%
499K_0402_1%
B+
1 2
ESR = 15mohm
ENTRIP2ENTRIP1
B B
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
PQ27A
PQ27A
61
D
D
2
G
G
S
S
34
D
D
PQ27B
5
G
G
PQ27B DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
S
S
PC53
PC53
1 2
PR91
PR91
12
PR92
PR92
+3VLP
PR87
PR87
1 2
0_0603_5%
0_0603_5%
12
100K_0402_1%
100K_0402_1%
12
PC59
PC59
1U_0402_6.3V6K
1U_0402_6.3V6K
PR82
PR82
30K_0402_1%
30K_0402_1%
1 2
PR84
PR84
19.1K_0402_1%
19.1K_0402_1%
1 2
ENTRIP1
1 2
1
3
2
VFB1
VREF
ENTRIP1
VO1
PGOOD
VBST1 DRVH1
LL1
DRVL1
VCLK18VREG5
VIN16GND
TPS51125ARGER_QFN24_4X4
TPS51125ARGER_QFN24_4X4
17
12
PC60
PC60
4.7U_0805_10V6K
4.7U_0805_10V6K
12
PC61
PC61
0.1U_0603_25V7K
0.1U_0603_25V7K
PR86
PR86
150K_0402_1%
150K_0402_1%
24 23 22 21 20 19
VL
BST_5V UG_5V LX_5V LG_5V
PR88
PR88
1 2
0_0603_5%
0_0603_5%
UP6182_B+
12
PC47
PC47
PC46
PC46
10U_1206_25V6M
10U_1206_25V6M
2200P_0402_50V7K
2200P_0402_50V7K
POK <33,36>
PC54
PC54
0.1U_0603_25V7K
0.1U_0603_25V7K
1 2
12
PQ26
PQ26
AO4712L_SO8
AO4712L_SO8
6
578
4
4
5
PQ23
PQ23 AO4466L_SO8
AO4466L_SO8
123
4.7UH_SIL1045R-4R7PF_6.3A_30%
4.7UH_SIL1045R-4R7PF_6.3A_30%
1 2
786
12
PR90
PR90
4.7_1206_5%
4.7_1206_5%
12
PC58
PC58
680P_0603_50V7K
680P_0603_50V7K
123
PL7
PL7
Ipeak=8.61A Imax=6.03A F=245K
+5VALWP
1
+
+
PC56
PC56 330U_6.3V_M
330U_6.3V_M
2
Total capacitor 220uF ESR = 15mohm
VL
VS_ON<33>
PR373
PR373
1 2
2
5
1 2
PR95
PR95
100K_0402_1%
100K_0402_1%
13
13
D
D
2
G
G
S
S
PQ363
PQ363
DTC115EUA_SC70-3
DTC115EUA_SC70-3
12
PQ362
PQ362
SSM3K7002FU_SC70-3
SSM3K7002FU_SC70-3
VS
ACPRN<34>
A A
EC_ON<28,29,31>
200K_0402_1%
200K_0402_1%
PR94
PR94
100K_0402_1%
100K_0402_1%
12
PR96
PR96
42.2K_0402_1%
42.2K_0402_1%
12
2
PC370
PC370
13
2.2U_0603_10V6K
2.2U_0603_10V6K
PQ29
PQ29 DTC115EUA_SC70-3
DTC115EUA_SC70-3
4
Security Classification
Security Classification
Security Classification
2010-08-25 2010-08-25
2010-08-25 2010-08-25
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2010-08-25 2010-08-25
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
Wednesday, September 01, 2010
Wednesday, September 01, 2010
Wednesday, September 01, 2010
401982
1
35 40
35 40
35 40
B
B
B
5
D D
PR98
PR98
0_0402_5%
0_0402_5%
POK<33,35>
+5VALW
C C
1 2
PR101
PR101
100_0603_1%
100_0603_1%
1 2
PC67
PC67
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
12
PC64
@PC64
@
.1U_0402_16V7K
.1U_0402_16V7K
12
PR103
PR103
4.75K_0402_1%
4.75K_0402_1% 1 2
12
PR104
PR104 10K_0402_1%
10K_0402_1%
4
PR97
PR97
255K_0402_1%
255K_0402_1%
1 2
1 2
PR99
PR99
0_0603_5%
15
1
PU6
PU6
2
TON
EN_SKIP
3
OUT
4
VCC
5
FB
6
PGOOD
AGND7PGND
0_0603_5%
14
TP
BST
13
DH
12
LX
11
ILIM
10
VDD
9
DL
G5603RU1U_TQFN14_3P5X3P5
G5603RU1U_TQFN14_3P5X3P5
8
DH_1.1V LX_1.1V
1 2
PR102
PR102
9.1K_0402_1%
9.1K_0402_1% DL_1.1V
BST_1.1V
0.1U_0603_25V7K
0.1U_0603_25V7K
+5VALW
PC65
PC65 1 2
12
PC69
PC69
4.7U_0805_10V6K
4.7U_0805_10V6K
3
1.1V_B+
12
12
12
PC62
PC62
PC63
4.7U_0805_25V6-K
4.7U_0805_25V6-K
1 2
12
PR100
PR100
12
PC68
PC68
1.5V_B+
PC63
4.7U_0805_25V6-K
4.7U_0805_25V6-K
PL9
PL9
4.7_1206_5%
4.7_1206_5%
680P_0603_50V7K
680P_0603_50V7K
5
4
PQ30
PQ30 TPCA8030-H_SOP-ADV8-5
TPCA8030-H_SOP-ADV8-5
123
1UH_FDUE1040D-1R0M-P3_21.3A_20%
1UH_FDUE1040D-1R0M-P3_21.3A_20%
PQ31
PQ31
3 5
241
MDU2653RH_POWERDFN56-8-5
MDU2653RH_POWERDFN56-8-5
12
PC133
PC133
10U_1206_25V6M
10U_1206_25V6M
HCB2012KF-121T50_0805
HCB2012KF-121T50_0805
2
PL151
PL151
HCB2012KF-121T50_0805
HCB2012KF-121T50_0805
1 2
PC91
PC91
2200P_0402_50V7K
2200P_0402_50V7K
(+1.1VALW, +1.1VS, NB_CORE)
1
+
+
PC66
PC66 330U_6.3V_M
330U_6.3V_M
2
PL152
PL152
1 2
B+
1
+
+
PC127
PC127
2
68U_25V_M_R0.36
68U_25V_M_R0.36
Ipeak = 16.1A Imax = 11.3A F = 315K
+1.1VALWP
Total capacitor 550uF ESR = 7.5mohm
B+
1
12
6
578
PR105
PR105
255K_0402_1%
255K_0402_1%
1
EN_SKIP
AGND7PGND
15
TP
8
1 2
1 2
PR107
PR107
0_0603_5%
0_0603_5%
14
BST
G5603RU1U_TQFN14_3P5X3P5
G5603RU1U_TQFN14_3P5X3P5
ILIM VDD
DH_1.5V
13
DH
LX_1.5V
12
LX
11
1 2
PR110
PR110
20K_0402_1%
20K_0402_1%
10
DL_1.5V
9
DL
PC74
PC74
BST_1.5V
1 2
0.1U_0603_25V7K
0.1U_0603_25V7K
+5VALW
12
PC78
PC78
4.7U_0805_10V6K
4.7U_0805_10V6K
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PR106
PR106
0_0402_5%
0_0402_5%
5
1 2
PR109
PR109
100_0603_1%
100_0603_1%
1 2
PC76
PC76
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
12
PC73
@PC73
@
.1U_0402_16V7K
.1U_0402_16V7K
12
PR111
PR111
10K_0402_1%
10K_0402_1%
1 2
12
PR112
PR112 10K_0402_1%
10K_0402_1%
PU7
PU7
2
TON
3
OUT
4
VCC
5
FB
6
PGOOD
4
SYSON<28,31>
B B
+5VALW
A A
4
123
786
5
4
123
3
12
PC71
PC71
4.7U_0805_25V6-K
4.7U_0805_25V6-K
PQ32
PQ32 AO4466L_SO8
AO4466L_SO8
1.8UH_SIL104R-1R8PF_9.5A_30%
1.8UH_SIL104R-1R8PF_9.5A_30% 1 2
12
PR108
PR108
4.7_1206_5%
4.7_1206_5%
12
PC77
PQ33
PQ33 AO4712L_SO8
AO4712L_SO8
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
PC77
680P_0603_50V7K
680P_0603_50V7K
12
PC72
PC72
PC79
PC79
4.7U_0805_25V6-K
4.7U_0805_25V6-K
2200P_0402_50V7K
2200P_0402_50V7K
PL11
PL11
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
1
+
+
2
PC75
PC75 330U_6.3V_M
330U_6.3V_M
2
+1.5VP
Ipeak = 9.5A Imax = 6.65A F = 315K
Total capacitor 220uF ESR = 15mohm
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
B
B
36 40Wednesday, September 01, 2010
36 40Wednesday, September 01, 2010
36 40Wednesday, September 01, 2010
1
B
5
4
3
2
1
+1.5V
D D
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
VDDR_SW<34>
C C
B B
+3VS
VR_ON#<31>
PC84
PC84
@ PJ14
@
112
JUMP_43X39
JUMP_43X39
1
PJ15
PJ15
1
JUMP_43X79@
JUMP_43X79@
2
2
12
PR115
PR115
0_0402_5%
0_0402_5%
1 2
@ PC90
@
.1U_0402_16V7K
.1U_0402_16V7K
PJ14
2
PC80
PC80
1U_0603_10V6K
1U_0603_10V6K
+5VALW
PC90
12
@PR167
@
10K_0402_1%
10K_0402_1%
12
@PR153
@
10K_0402_1%
10K_0402_1%
12
12
PR148
@ PR148
@
12.4K_0402_1%
PR167
PR153
12
12.4K_0402_1%
13
D
D
@
@
2
PQ11
PQ11
G
G
S
S
13
D
D
2
PQ4
PQ4
G
G
S
S
PU8
PU8
APL5508-25DC-TRL_SOT89-3
APL5508-25DC-TRL_SOT89-3
2
IN
OUT
GND
1
SSM3K7002FU_SC70-3
SSM3K7002FU_SC70-3
SSM3K7002FU_SC70-3
SSM3K7002FU_SC70-3
3
12
PR113
PR113
6.98K_0402_1%
6.98K_0402_1%
12
PR117
PR117
10.5K_0402_1%
10.5K_0402_1%
VDDR_SW VDDR
HIGH LOW
2 3 4
12
PC86
PC86
12
PC87
PC87 10U_0805_6.3V6M
10U_0805_6.3V6M
.1U_0402_16V7K
.1U_0402_16V7K
+2.5VSP
12
PC81
PC81
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
PU9
PU9 APL5331KAC-TRL_SO8~N
APL5331KAC-TRL_SO8~N
VIN1VCNTL GND VREF VOUT
+1.05VSP
6 5
NC
7
NC
8
NC
9
TP
1.05V
0.9V
+5VALW+3VS
1
PJ16
PJ16
1
JUMP_43X79@
JUMP_43X79@
2
2 12
PC85
PC85
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
+5VALW
12
PC82
PC82
1U_0603_6.3V6M
1U_0603_6.3V6M
SUSP<31>
SUSP#
PR121
PR121
0_0402_5%
0_0402_5%
1 2
PC96
@ PC96
@
.1U_0402_16V7K
.1U_0402_16V7K
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
12
0.01U_0402_25V7K
0.01U_0402_25V7K
+1.5V
PC92
PC92
2
G
G
PR195
PR195
0_0402_5%
0_0402_5%
1 2
PC83
@ PC83
@
1
PJ17
@ PJ17
@
1
JUMP_43X79
JUMP_43X79
2
2
12
PR119
PR119
1K_0402_1%
1K_0402_1%
13
D
D
PR120
PR120
1K_0402_1%
1K_0402_1%
S
S
PQ34
PQ34 SSM3K7002FU_SC70-3
SSM3K7002FU_SC70-3
12
PC181
PC181 1U_0603_6.3V6M
1U_0603_6.3V6M
6
VCNTL
5
VIN
9
VIN
8
EN
7
POK
12
12
12
12
3
VOUT
4
VOUT
2
FB
GND
1
PU10
PU10 APL5930KAI-TRG_SO8
APL5930KAI-TRG_SO8
PU11
PU11 APL5331KAC-TRL_SO8~N
APL5331KAC-TRL_SO8~N
VIN1VCNTL
2
GND
3
VREF
4
VOUT
12
PC94
PC94
PC95
PC95 10U_0805_6.3V6M
10U_0805_6.3V6M
.1U_0402_16V7K
.1U_0402_16V7K
3K_0402_1%
3K_0402_1%
2.4K_0402_1%
2.4K_0402_1%
+0.75VSP
PR165
PR165
PR166
PR166
PC89
PC89
22U_0805_6.3V6M
22U_0805_6.3V6M
+3VALW
+1.8VSP
12
12
6 5
NC
7
NC
8
NC
9
TP
12
PC88
PC88
0.01U_0402_25V7K
0.01U_0402_25V7K
12
12
PC93
PC93 1U_0603_6.3V6M
1U_0603_6.3V6M
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
1
B
B
37 40Wednesday, September 01, 2010
37 40Wednesday, September 01, 2010
37 40Wednesday, September 01, 2010
B
A
B
C
D
E
CPU_B+
PC97
PC97
33P_0402_50V8J
33P_0402_50V8J
12
12
PR122
PR122
44.2K_0402_1%
PR123
1 1
12
PR134
@PR134
@
10K_0402_1%
10K_0402_1%
PR144
PR144
95.3K_0402_1%
95.3K_0402_1%
+CPU_CORE
COMP0
12
PC125
PC125
1200P_0402_50V7K
1200P_0402_50V7K
+5VS +3VS
12
12
+3VS
12
PR132
PR132
105K_0402_1%
105K_0402_1%
DIFF_0
PR155
PR155
12
PC119
PC119
4700P_0402_25V7K
4700P_0402_25V7K
PR157
PR157
1K_0402_5%
1K_0402_5%
VGATE<28,31>
CPU_SVD<7> CPU_SVC<7>
VR_ON<28,31>
PR143
PR143
21.5K_0402_1%
21.5K_0402_1%
12
12
A
1 2
PR136 0_0402_5%@ PR136 0_0402_5%@
1 2
PR138 0_0402_5%PR138 0_0402_5%
12
FB_0
54.9K_0402_1%
54.9K_0402_1%
12
PR163
@ PR163
@
36.5K_0402_1%
36.5K_0402_1%
CPU_VDD0_RUN_FB_H<7>
CPU_VDD0_RUN_FB_L<7>
VW0
PC120
PC120
180P_0402_50V8J
180P_0402_50V8J
PR158
PR158
12
2 2
H_PWRGD<7,18>
H_PWRGD_L<18>
3 3
255_0402_1%
255_0402_1%
4 4
CPU_B+
12
PR130
PR130 0_0402_5%
0_0402_5%
ISL6265_PWROK
PR140
PR140
0_0402_5%
0_0402_5%
PR189
PR189
10_0402_1%
10_0402_1%
PR190
PR190
10_0402_1%
10_0402_1%
PC121
PC121
1000P_0402_50V7K
1000P_0402_50V7K
PR159
PR159
6.81K_0402_1%
6.81K_0402_1%
+5VALW
12
12
12
0_0402_5%
0_0402_5%
12
12
12
12
PR123
2_0603_5%
2_0603_5%
1 2
0.1U_0603_16V7K
0.1U_0603_16V7K
1 2
PR127
PR127
2_0603_5%
2_0603_5%
0.1U_0603_25V7K
0.1U_0603_25V7K
PR131
@PR131
@ 105K_0402_1%
105K_0402_1%
PR135
@PR135
@ 105K_0402_1%
105K_0402_1%
12
PR142
PR142
10 11 12
PC371
PC371
1 2
330P_0402_25V8J
330P_0402_25V8J
PR146
PR146
0_0402_5%
0_0402_5%
PR147
PR147
0_0402_5%
0_0402_5%
PC219
PC219
1000P_0402_50V7K
1000P_0402_50V7K
PC107
PC107
1 2 3 4 5 6 7 8 9
12
12
PU12
PU12
ISP0 ISN0
PC103
PC103
12
OFS/VFIXEN PGOOD PWROK SVD SVC ENABLE RBIAS OCSET VDIFF0 FB0 COMP0 VW0
VSEN0VSEN0
RTN0
12
PR156
@PR156
@
255_0402_1%
255_0402_1%
B
44.2K_0402_1%
12
48
45
47
46
VIN
VCC
FB_NB
ISL6265CHRTZ-T_TQFN48_6X6
ISL6265CHRTZ-T_TQFN48_6X6
VSEN0
ISN0
ISP0
15
16
14
13
12
PC218
PC218
2200P_0402_25V7K
2200P_0402_25V7K
PR150
PR150
1K_0402_1%
1K_0402_1%
+1.5V
12
12
PC122
PC122
@
@
4700P_0402_25V7K
4700P_0402_25V7K
12
PR160
@PR160
@
1K_0402_5%
1K_0402_5%
1000P_0402_50V7K
1000P_0402_50V7K
22K_0402_1%
22K_0402_1%
44
43
FSET_NB
COMP_NB
RTN1
RTN0
17
18
1 2
VSEN0
DIFF_1
54.9K_0402_1%
54.9K_0402_1% 12
PC102
PC102
PR126
PR126
VSEN_NB
VSEN1
@ PR164
@
36.5K_0402_1%
36.5K_0402_1%
PC100
PC100
1000P_0402_50V7K
1000P_0402_50V7K
12
12
PR128
PR128
0_0402_5%
0_0402_5%
12
11K_0402_1%
11K_0402_1%
40
42
41
RTN_NB
PGND_NB
OCSET_NB
VDIFF1
COMP121ISP1
FB1
19
20
PC123
PC123
@
@
180P_0402_50V8J
180P_0402_50V8J
PR161
PR161
@
@
12
1200P_0402_50V7K
1200P_0402_50V7K
PR164
12
UGATE_NB
PHASE_NB
PR124
PR124
2.2_0603_1%
2.2_0603_1%
PR191
PR191
10_0402_1%
10_0402_1%
1 2
PR129
PR129
12
0_0402_5%
0_0402_5%
39
38
37
BOOT_NB
LGATE_NB
PHASE_NB
UGATE_NB
BOOT0 UGATE0 PHASE0
PGND0 LGATE0
PVCC
LGATE1
PGND1 PHASE1 UGATE1
BOOT1
VW1
ISN1
22
23
24
ISN1
ISP1
VW1
COMP1FB_1
12
1000P_0402_50V7K
1000P_0402_50V7K
PC126
PC126
@
@
12
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BOOT_NB
+VDDNB
LGATE_NB
CPU_VDDNB_RUN_FB_H <7>
PHASE_NB LGATE_NB PHASE_NB UGATE_NB
12
PR133
PR133
36 35 34 33 32 31 30 29 28 27 26 25
TP
49
12
PC124
PC124
@
@
PR162
PR162
@
@
6.81K_0402_1%
6.81K_0402_1% 12
C
BOOT_NB BOOT0 UGATE0 PHASE0
LGATE0
LGATE1
PHASE1 UGATE1 BOOT1
10_0402_1%
10_0402_1%
1 2
1 2
1 2
PC104
PC104
0.22U_0603_10V7K
0.22U_0603_10V7K
PR192
PR192
CPU_VDDNB_RUN_FB_L <7>
UGATE0
PHASE0
BOOT0
+5VALW
12
PC113
PC113 1U_0603_10V6K
1U_0603_10V6K
UGATE1
PHASE1
BOOT1
LGATE1
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
6
578
4
5
4
PR137
PR137
0_0603_5%
0_0603_5%
1 2
PC110
PC110
0.22U_0603_10V7K
0.22U_0603_10V7K
LGATE0
PR149
PR149
0_0603_5%
0_0603_5%
1 2
0.22U_0603_10V7K
0.22U_0603_10V7K
Compal Secret Data
Compal Secret Data
Compal Secret Data
PQ35
PQ35 AO4466L_SO8
AO4466L_SO8
123
786
PQ36
PQ36 AO4712L_SO8
AO4712L_SO8
123
4
1 2
4
1 2
PC116
PC116
Deciphered Date
Deciphered Date
Deciphered Date
PC101
PC101
5
3 5
241
5
3 5
241
1
12
+
+
PC98
PC98
PC99
PC99
2
10U_1206_25V6M
10U_1206_25V6M
68U_25V_M_R0.36
68U_25V_M_R0.36
68U_25V_M_R0.36
68U_25V_M_R0.36
PL13
PL13
4.7UH_SIL1045R-4R7PF_6.3A_30%
4.7UH_SIL1045R-4R7PF_6.3A_30% 1 2
12
PR125
PR125
4.7_1206_5%
4.7_1206_5%
12
PC106
PC106
680P_0603_50V7K
680P_0603_50V7K
PC108
PC108
4.7U_0805_25V6-K
PQ38
PQ38
PQ41
PQ41
4.7U_0805_25V6-K
PC114
PC114
4.7U_0805_25V6-K
4.7U_0805_25V6-K
D
PQ37
PQ37 TPCA8030-H_SOP-ADV8-5
TPCA8030-H_SOP-ADV8-5
123
MDU2653RH_POWERDFN56-8-5
MDU2653RH_POWERDFN56-8-5
PQ40
PQ40 TPCA8030-H_SOP-ADV8-5
TPCA8030-H_SOP-ADV8-5
123
MDU2653RH_POWERDFN56-8-5
MDU2653RH_POWERDFN56-8-5
1
1
+
+
+
+
PC128
PC128
2
2
68U_25V_M_R0.36
68U_25V_M_R0.36
1
+
+
PC105
PC105 330U_6.3V_M
330U_6.3V_M
2
CPU_B+
12
12
12
12
PC109
PC109
PC129
PC129
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
12
PR139
PR139
4.7_1206_5%
4.7_1206_5%
12
PC111
PC111
680P_0603_50V7K
680P_0603_50V7K
CPU_B+
12
12
PC131
PC131
PC115
PC115
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
12
PR151
PR151
4.7_1206_5%
4.7_1206_5%
12
PC117
PC117
680P_0603_50V7K
680P_0603_50V7K
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom Date: Sheet of
Date: Sheet of
Date: Sheet of
PL12
PL12
HCB4532KF-800T90_1812
HCB4532KF-800T90_1812
1 2
+VDDNBP
B+
Ipeak = 36A Imax = 25.2A F = 300K
Total capacitor 1320uF ESR = 1.5mohm
PL14
0.36UH_PCMC104T-R36MN1R17_30A_20%
0.36UH_PCMC104T-R36MN1R17_30A_20%
0.36UH_PCMC104T-R36MN1R17_30A_20%
0.36UH_PCMC104T-R36MN1R17_30A_20%
PL14
1 2
PR141
PR141
16.5K_0402_1%
16.5K_0402_1%
1 2
0.1U_0603_16V7K
0.1U_0603_16V7K
4.02K_0402_1%
4.02K_0402_1%
ISP0
1 2
PR152
PR152
16.5K_0402_1%
16.5K_0402_1%
1 2
0.1U_0603_16V7K
0.1U_0603_16V7K
ISP1
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
4 3
PC112
PC112
12
12
PR145
PR145
PL15
PL15
PC118
PC118
PR154
PR154
4.02K_0402_1%
4.02K_0402_1%
ISN0
4 3
12
12
ISN1
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
E
+CPU_CORE
+CPU_CORE
38 40Wednesday, September 01, 2010
38 40Wednesday, September 01, 2010
38 40Wednesday, September 01, 2010
B
B
B
5
PIR (Product Improve Record)
PWWAE LA-6843P SCHEMATIC CHANGE LIST REVISION CHANGE: 0.1 TO 0.2
NO DATE PAGE MODIFICATION LIST PURPOSE
--------------------------------------------------------------------------------------------------------------------------------------------------------------------­1 2010/07/20 28 Reserve C1199,Y5,C1200 For design change 2 2010/07/20 28 Reserve R436 for only KB926E0 For design change 2010/07/20 29 Del R875 For SERIRQ direct connect to H7.7 2010/07/20 29 Del C588/C589/Y4/R368 For design change 3 2010/07/21 11~15 Change U8 R1 P/N from A12(SA000032WI40) to A13(SA000032WA0) For SB820 A13 version 2010/07/21 30 Change U8 R3 P/N from A12(SA000032WI50) to A13(SA000032WB0) For SB820 A13 version 4 2010/07/23 18 Change D8 from DAN202U to CHN202UPT For design change 5 2010/07/23 24 Chagne UL4 from LF-H1201P-2 to LFE8456E-R for use 5mA type For design change
D D
6 2010/07/23 30 Change R768/R773 from 120 to 510 ohm for use 5mA type For design change Change R768.1 pull up from +3VALW to +5VALW for use 5mA type For design change Change R773.1 pull up from +3VALW to +5VALW for use 5mA type For design change 7 2010/07/23 27 Change JLINE/JEXMIC to FOX_JA6331-B39S4-7F For DFX request 8 2010/07/26 23 Reserve DM2 For +3V_WLAN is +3VS 9 2010/07/26 Add R50 For Intel Rainbow Peak module 2010/07/26 24 Reserve CL39 For EMI request 10 2010/07/27 28 Change R867 pull up from +3VALW to +3VL For design change
4
3
2
1
REVISION CHANGE: 0.2 TO 1.0
NO DATE PAGE MODIFICATION LIST PURPOSE
--------------------------------------------------------------------------------------------------------------------------------------------------------------------­1 2010/08/06 29 Change U13 footprint to M25P10-AVMN6T-SOP For design change 2 2010/08/06 25 Change Net name form V1_8 to +V1_8 For customer request 2010/08/06 29 Add R774 link to BATT_CHG_LOW_LED# For customer request 2010/08/06 29 Change R773 link to BATT_FULL_LED# For customer request 3 2010/08/06 30 Reserve SW6 Del SW5 For debug phase 2010/08/09 30 Chagne UL4 from NS681680 to NS681610 For design change 4 2010/08/09 08 Mount C26/C89,Reserve C24,C90 For design change 5 2010/08/16 18 Del R42/C94 For EMI request 2010/08/16 18 Reserve CC9/RC7 For EMI request 6 2010/08/16 24 Add CL3/CL7 link to +3V_LAN For EMI request Reserve CL38 For EMI request Change CL37 from 0.1uF to 120 pF For EMI request Add D13 link to LANGND For EMI request
C C
B B
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
401982
401982
401982
1
B
B
B
of
39 40Wednesday, September 01, 2010
of
39 40Wednesday, September 01, 2010
of
39 40Wednesday, September 01, 2010
A
B
Version Change List ( P. I. R. List ) for Power Circuit
C
D
E
NO DATE PAGE MODIFICATION LIST PURPOSE
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
2010 . 06 . 21 Release
1 1
Rev.
2010 . 07.25 modification list
P 33 P 38 P 33 Remove PD6 , PD8 @ ESD test fail P 34 Add PC132 , remove PC130 , PC131 , PR69 , PC41 @ For EMI fail P 35 Add PC51 , remove PC49 , PC46 , PC57 , PC58 , PR89 , PR90 @ P 36 Add PC79 , PC91 , PC133 , remove PR100 , PR108 , PC68 , PC77 @
PC16 change to SE070104Z80 Defore material EOL PU12 change to SA000022M80 Before material MP schedule will impact PWWAE MP schedule
For EMI fail For EMI fail
PVT PVT PVT PVT PVT PVT
For EMI fail PVTP 38 Remove PR125 , PR139 , PR151 , PC106 , PC111 , PC117 @
2010 . 08.10 modification list
2 2
Pre-MPP 37 Change PU9 , PU11 to SA053310110 UP7711 stop using from now on Pre-MPP 38 Add PC218 , PC219 , PC371 For VCORE Ripple Pre-MPP 32 Add PR8 For Precharge rising current Pre-MPP 32 , P 33 PQ1 , PQ2 , PQ6 change to SB900840003 SB906100210 material delivery had problem
2010 . 08.16 modification list
Pre-MPP 35 Change PU5 to SA000020C80 UPI product stop using
2010 . 08.17 modification list
Pre-MPP 34 Change PU4 to SA00001EP80 SA00003TK00 stop using
3 3
2010 . 08.23 modification list
Pre-MPP 38 Remove PR127 @ To solve +1.1VALW noise
Pre-MPP 34 Remove PR193 , PQ39 @ For PWWAE MP use 25W CPU
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2010-08-25 2010-08-25
2010-08-25 2010-08-25
2010-08-25 2010-08-25
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
SCHEMATICS,MB A6843
401982
401982
401982
40 40Wednesday, September 01, 2010
40 40Wednesday, September 01, 2010
40 40Wednesday, September 01, 2010
E
B
B
B
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