Quanta Computer LA-1931 DBL10 Sapporo X, Satellite A30, Satellite A35 Schematic

A
B
COMPAL CONFIDENTIAL
C
D
E
1 1
MODEL NAME :
COMPAL P/N :
PCB NO :
Revision :
2 2
LA-1931
0.2
DBL10 -- Sapporo X
DA8BL10L000
DBL10 -- Sapporo X Schematics Document
uFCBGA/uFCPGA NorthWood MT
2003-06-09 0.2 Gerber Out Version
3 3
4 4
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, IN C. NEIT HER TH IS SHEE T NOR T HE INF ORMATION IT CONTAIN S
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CON SENT OF COMPAL ELE CTRONICS , INC.
C
D
Size Document Number Rev
Date: Sheet
Compal Electronics, In c.
LA-1931
Cover Sheet
E
of
147Monday, June 09, 2003
A
Compal confidential
Model : DBL10 -- Sapporo X
B
C
D
E
Block Diagram
Fan Control 1
+12VALW
1 1
+5VALW
+12VALW +5VALW
TV OUT Connector
+3VS
CRT Connector
+5VS +3VS
LVDS Connector
2 2
B+
page 33
Fan Control 2
page 33
page 15
page 16
page 16
TV Encoder
CH7011A
+3VS
page 15
CPU Bypass
page 6
TV-OUT Signal by DVOC
CRT Signal
LVDS Signal
+1.2VP
+CPU_CORE
+1.5VS
+2.5V
+3VS
+CPU_CORE
Prescott-MT -- 533 Celeron-MT -- 400
400/533 MHz
478pin
page 4,5
HD#(0..63)HA#(3.. 31)
uFCPGA CPU
System Bus
INTEL
Montara-GT 852GME
732 BGA
page 7,8,9,10
Thermal Sensor
ADM1032AR
+5VS +3VS
page 5
Memory BUS(DDR)
+2.5V 200/266/333MHz
Clock Generator
ICS950810CG
page 14
DDR-DIMM X2
BANK 0, 1, 2, 3
+2.5V
+1.25VS
page 11,12,13
HUB LINK 1.5
+1.5VS 66MHz
NorthWood-MT -- 533
USB Ports X2 ( X1 reserve )
+5V
+5VS
+3VS
+3V
page 28
MIC Phone
+5VDDA
LINE IN
+5VDDA
Compal Electronics , Inc .
Block Diagram
E
page 27
MDC
page 28
RJ11
Cable
Cable
page 29
of
247Monday, June 09, 2003
0.2
Super I/O
page 30
FIR
page 30
page 30
+3VS
+3VALW
+1.5VS
+1.5VALW
+CPU_CORE
VCC5REF
VCC5REFSUS
LPC BUS
page 30
48MHz
24.576MHz
page 26
USB 2.0/1.1
AC-LINK
ATA100
IDE ODD
+5VCD
page 26
PIDE IRQ15SIDE IRQ14
INT. Speaker
page 29
D
+5VALW
INTEL
ICH4-M
421 BGA
page 17,18,19
+3VS 33MHz
IDE HDD
+5VS
Embedded Controller
NS PC87591L
+3VS +3VALW
EC DEBUG & Int. KB
+5VALW
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY ORDISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC .
C
page 31
+3VALW
page 31
BIOS & Ext. IO
+3VALW +5VALW
page 32
LID SW & Kill SW
+3VALW
page 33
Touch Pad
+5VS
page 33
LID Hibernation
+RTC_VREF
page 35
AC97 Codec
ALC202
+5VALW -> +VDDA
+3VS
EQ
+5VCD
page 29
AMP TPA6011A4
page 29
HeadPhone
+AUD_VREF
page 29
Title
Size Document Number Re v
LA-1931
Date: Sheet
IEEE 1394
VT6301S
+3V +3VS
1394 Conn.
B
PCI BUS
IDSEL:AD16 PIRQE#
page 20
page 20
+5VS
+5VS
Debug COM Port
+5V
SMs FDC47N227
+3VS
Paralle l
+3VS 33MHz
LAN RTL8101L
+3V +2.5VLAN
RJ45
page 33
IDSEL:AD17 PIRQF#
page 23
page 24
SW Board Conn
+5VALW
RTC Batt.
DC/DC Interface Suspend
IDSEL:AD18 PIRQG#
Minipci CONN
WIRELESS & Dubug
+3V +3VS +5VS
page 25
3 3
On/Off BTN & User Keys
+3VALW
Power Circuit DC/DC
4 4
A
IDSEL:AD20 PIRQA#
CardBus
CB1410
+3V +3VS
page 21
PWR Controller & Slot
+12VALW +5VALW +3VALW
page 22
page 33
page 33
page 36
5
4
3
2
1
Voltage Rails
Power Plane Description
D D
C C
VIN
B+
+CPU_CORE
+1.2V
+1.25VS 1.25V switched power rail
+1.5VALW 1.5V always on power rail
+1.5V
+1.5VS
+2.5V 2.5V power rail
+3VALW
+3V
+3VS
+5VALW
+5V
+5VS
+12VALW
+RTCBATT
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
1.2V switched power rail for CPU A GTL Bus
1.5V power rail
1.5V switched power rail
3.3V always on power rail
3.3V power rail
3.3V switched power rail
5V always on power rail
5V power rail
5V switched power rail
12V always on power rail
RTC power ONON
S1 S3 S5
N/A N/A N/A
ON OFF
ON
ON OFF OFF
ON
ON OFF
ON OFF OFF
ON
ON ON
ON
ON
ON
ON
ON
ON
ON
ON
ON ON
ON
ON
ON
OFF OF F
ON
ON
OFF OF F
ON
N/AN/AN/A
OFF
OFF
OFF
ON
OFF
ON
OFF
ON
Power Managment table
Signal
State
S0
S1
S3
S5 S4/AC
S5 S4/AC don't exist
+1.5VALW
+3VALW
+5VALW
+12VALW
ON
+5V
+3V
+2.5V
+1.2V
ON ON
ON ON ON
ON ON
ON OFF
OFF OFF OFF
+5VS
+3VS
+1.5VS
+CPU_CORE
+1.25VS
OFF
OFF
Board ID Table for AD channel
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
External PCI Devices ( follow PCI IRQ routing plannig ver0.2.04 )
Device IDSEL# REQ#/GNT# Interrupts - (ICH4-M)
CardB us (ENE-CB1410)
IEEE 1394 (VIA -VT6301S)
LAN (Realtek-RTL8101L)
B B
Mini-PCI
AD20
AD16 0
AD17
AD18
2
3PIRQF#
1/1
PIRQA#
PIRQE#
PIRQG#
Vcc 3.3V +/- 5%
Board ID
0 1 2 3 4 5 6
100K +/- 5%Ra
Rb V min
0
8.2K +/- 1%0V0.216 V 0.250 V 0.289 V 18K +/- 1% 33K +/- 1% 56K +/- 1% 100K +/- 1% 200K +/- 1%
7 NC
AD_BID
Vtyp
AD_BID
V
AD_BID
max
0V 0V
0.436 V
0.712 V
1.036 V
0.503 V
0.819 V
0.538 V
0.875 V
1.185 V 1.264 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
2.200 V
3.300 V
2.341 V
3.300 V
EC SM Bus1 address
Device
Smart B attery
EEPROM(24C16)
EC SM Bus2 address
Addres s Addres s
1010 000X b
Devic e
ADM1032
1001 100X b0001 011X b
Board ID
0 1 2 3 4
PCB Revision
0.1
5 6 7
A A
ICH4 SM Bus address
Device
CLK GEN ( ICS-950810)
5
Address
1101 001X
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, IN C. NEIT HER TH IS SHEE T NOR T HE INF ORMATION IT CONTAIN S
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CON SENT OF COMPAL ELE CTRONICS , INC.
3
2
Note & Revision
Size Document Number Rev
LA-1931
Date: Sheet
1
of
347Monday, June 09, 2003
5
D D
A10
A12
A14
A16
VCC_0
VCC_1
VCC_2
HOST ADDR
CONTROL
CLK
CON TROL
VSS_0H1VSS_1H4VSS_2
A18
VCC_3
H23
JCPU1A
HA#[3..31]<7> HD#[0..63] <7>
C C
H_R EQ#[0..4]<7>
+CPU_CORE
B B
H_R EQ#[0..4]
H_ADS#<7>
R15 56_0402_1%
1 2
H_BREQ0#<7>
H_BPRI#<7> H_BNR#<7> H_LOCK#<7>
CLK_CPU_BCLK<14> CLK_CPU_BCLK#<14>
H_HIT#<7 > H_HITM#<7>
H_DEFER#<7>
HA#3
K2
HA#4
K4
HA#5
L6
HA#6
K1
HA#7
L3
HA#8
M6
HA#9
L2
HA#10
M3
HA#11
M4
HA#12
N1
HA#13
M1
HA#14
N2
HA#15
N4
HA#16
N5
HA#17
T1
HA#18
R2
HA#19
P3
HA#20
P4
HA#21
R3
HA#22
T2
HA#23
U1
HA#24
P6
HA#25
U3
HA#26
T4
HA#27
V2
HA#28
R6
HA#29
W1
HA#30
T5
HA#31
U4 V3
W2
Y1
AB1
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_ADS#
CLK_CPU_BCLK CLK_CPU_BCLK#
FOX_PZ47803-274A-42_Prescott
AF22 AF23
J1 K5 J4 J3 H3 G1
AC1
V5 AA3 AC3
H6
D2
G2
G4
F3
E3
E2
A#3 A#4 A#5 A#6 A#7 A#8 A#9 A#10 A#11 A#12 A#13 A#14 A#15 A#16 A#17 A#18 A#19 A#20 A#21 A#22 A#23 A#24 A#25 A#26 A#27 A#28 A#29 A#30 A#31 A#32 A#33 A#34 A#35
REQ#0 REQ#1 REQ#2 REQ#3 REQ#4 ADS#
AP#0 AP#1 BINIT# IERR#
BR0# BPRI# BNR# LOCK#
BCLK0 BCLK1
HIT# HITM# DEFER#
A20
VCC_4
H26
VCC_5
VSS_3
A11
AA10
AA12
VCC_6A8VCC_7
VSS_4
VSS_5
A13
A15
AA14
VCC_8
VSS_6
A17
AA16
VCC_9
VSS_7
A19
VCC_10
VSS_8
4
AA18
AA8
AB11
AB13
AB15
AB17
AB19
AB7
AB9
AC10
AC12
AC14
AC16
AC18
AC8
AD11
AD13
AD15
AD17
AD19
AD7
AD9
AE10
AE12
AE14
AE16
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
POWER
Northwood-MT Prescott-MT
GND
VSS_9
VSS_10
VSS_11
VSS_12A3VSS_13A9VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
A21
A24
A26
AA1
AA11
AA4
AA7
AA13
AA15
AA9
AA17
AA19
AA23
AA26
AB10
AB12
AB3
AB14
AB6
AB16
AB18
AB20
AB21
AB24
AE18
VCC_36
VSS_34
AB8
AE20
VCC_37
VSS_35
AC11
AE6
VCC_38
VSS_36
AC13
AE8
VCC_39
VSS_37
AC15
AF11
VCC_40
VCC_41
VSS_38
VSS_39
AC17
AF13
VCC_42
VSS_40
AC19
3
AF15
AC2
AF17
VCC_43
VCC_44
VSS_41
VSS_42
AC22
AF19
VCC_45
VSS_43
AC25
AF2
VCC_46
VSS_44
AC5
AF21
VCC_47
VSS_45
AC7
AF5
VCC_48
VSS_46
AC9
AF7
AD10
AF9
VCC_49
VCC_50
VSS_47
VSS_48
AD12
B11
VCC_51
VSS_49
AD14
B13
AD16
B15
VCC_52
VCC_53
VSS_50
VSS_51
AD18
B17
AD21
B19
VCC_54
VSS_52
AD23
VCC_55
VSS_53
AD4
VCC_56B7VCC_57B9VCC_58
VSS_54
VSS_55
AD8
C10
C12
C14
VCC_59
VCC_61
BOOTSELECT
AD1
C16
C18
C20
VCC_62
VCC_63
VCC_64
VCC_65C8VCC_66
POWER
VCC_81
VCC_82
VCC_83
VCC_84
F13
F15
F17
F19
D11
VCC_85
F9
D13
VCC_67
F11
D15
D17
VCC_68
VCC_79E8VCC_80
E20
D19
D9
VCC_69
VCC_70
VCC_71D7VCC_72
HOST ADDR
VCC_76
VCC_77
VCC_78
E14
E16
E18
+CPU_CORE
E10
VCC_73
VCC_74
VCC_75
E12
+CPU_CORE
2
HD#[0..63]HA#[3..31]
D#10 D#11 D#12 D#13 D#14 D#15 D#16 D#17 D#18 D#19 D#20 D#21 D#22 D#23 D#24 D#25 D#26 D#27 D#28 D#29 D#30 D#31 D#32 D#33 D#34 D#35 D#36 D#37 D#38 D#39 D#40 D#41 D#42 D#43 D#44 D#45 D#46 D#47 D#48 D#49 D#50 D#51 D#52 D#53 D#54 D#55 D#56 D#57 D#58 D#59 D#60 D#61 D#62 D#63
D#0 D#1 D#2 D#3 D#4 D#5 D#6 D#7 D#8 D#9
B22 A23 A25 C21 D22 B24 C23 C24 B25 G22 H21 C26 D23 J21 D25 H22 E24 G23 F23 F24 E25 F26 D26 L21 G26 H24 M21 L22 J24 K23 H25 M23 N22 P21 M24 N23 M26 N26 N25 R21 P24 R25 R24 T26 T25 T22 T23 U26 U24 U23 V25 U21 V22 V24 W26 Y26 W25 Y23 Y24 Y21 AA25 AA22 AA24
HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63
HD#0
B21
1
BOOTSEL
A A
Pop: Northwood Depop: Prescott
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, IN C. NEIT HER TH IS SHEE T NOR T HE INF ORMATION IT CONTAIN S
5
4
3
R8
@0_0402_5%
12
R_C
BOOTSELECT <44>
2
Compal Electronics, Inc.
Title
Prescott / P4 uFCPGA (1/2)
Size Document Number Rev
LA-1931
Custom Date: Sheet
1
of
447Monday, June 09, 2003
5
+CPU_CORE
H_RS#[0..2]<7>
ITP_BPM#0
1 2
R49 51_0402_5%
D D
+CPU_CORE
C C
+IOPLL
B B
ITP_BPM#1
1 2
R44 51_0402_5%
ITP_BPM#2
1 2
R14 51_0402_5%
ITP_BPM#3
1 2
R38 51_0402_5%
ITP_BPM#4
1 2
R41 51_0402_5%
ITP_BPM#5
1 2
R13 51_0402_5%
H_PWRGD
1 2
R84 300_0402_5%
ITP_TDI
12
R9 150_ 0402_5%
ITP_T MS
12
R1 39.2_0603_1%
ITP_TRST#
12
R21 680_0402_5 %
ITP_TCK
12
R19 27.4_ 0603_1%
0_0603_5%
R325
1 2
@0_0805_5%
R324
1 2
L26
1 2
LQG21F4R7N00_0805
1 2
LQG21F4R7N00_0805
L27
C331
@33U_D2_16VM
+CPU_CORE
1
+
2
CLK_CPU_ITP<14> CLK_CPU_ITP#<14>
+1.2V
1
+
C332 33U_D2_16VM
2
H_RS#[0..2]
H_TRDY#<7>
H_A20M#<17>
H_FERR#<17> H_IGNNE#<17> H_SMI#<17> H_PWRGD<17> H_STPCLK#<17>
H_INTR<17> H_NMI<17> H_INIT#<17> H_RESET#<7>
H_DBSY#<7>
H_DRDY#<7>
H_BSEL0<14>
H_THERMTRIP#<18>
VCCIOPLL
VCCA
VCCSENSE<44> VSSSENSE<44>
+1.2V
1 2
R82 61.9_0603_1 %
1 2
R20 61.9_0603_1 %
Comp0/1 need keep 25 mils trace width
H_RS#0 H_RS#1 H_RS#2
H_TRDY#
H_A20M# H_FERR# H_IGNNE# H_SMI# H_PWRGD H_STPCLK#
H_INTR H_NMI H_INIT# H_RESET#
H_DBSY# H_DRDY# H_BSEL0
H_THERMDA H_THERMDC
H_THERMTRIP#
ITP_BPM#0 ITP_BPM#1 ITP_BPM#2 ITP_BPM#3 ITP_BPM#4 ITP_BPM#5
ITP_TCK ITP_TDI
ITP_T MS ITP_TRST#
VCCSENSE VSSSENSE
VSSA
FOX_PZ47803-274A-42_Prescott
+3VS
AB23
AB25
AD6 AD5
AC6
AC4
AD20 AE23
AD22
AC26 AD26
F1
G5
F4
AB2
J6
C6
B6 B2 B5
Y4
D1
E5
W5
H5 H2
B3
C4
A2
AB5
Y6 AA5 AB4
D4 C1 D5
F7
E6
A5
A4 AF3
L24
P1
CPU Temperature Sensor
1 2
H_THERMDA
1
A A
5
C24
2200P_0603_50V7K
H_THERMDC
EC_SMC2<32>
EC_SMD2<32>
2
200_0402_5%
GND
JCPU1B
RS#0 RS#1 RS#2 RSP# TRDY#
CON TROL
A20M# FERR# IGNNE# SMI# PWRGOOD STPCLK#
LINT0
LEGACY
LINT1 INIT# RESET#
DBSY# DRDY# BSEL0 BSEL1
THERMDA THERMDC
THERMTRIP#
BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5
TCK TDI TDO TMS TRST#
VCCIOPLL VCCA
VCCSENSE VSSSENSE VCCVIDLB
VSSA
ITP_CLK0 ITP_CLK1
COMP0 COMP1
R61
U6
2
D+
3
D-
8
SCLK
7
SDATA
ADM1032ARM_RM8
4
AE11
AE13
AE15
VSS_57
VSS_58
MISC
THER MAL
MISC
MISC
ITP CLK
VSS_129F8VSS_130
G21
G24
1
2
VDD1
ALERT#
THERM#
4
AE17
AE19
AE22
AE24
AE7
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
ITP
VSS_131
VSS_132G3VSS_133G6VSS_134J2VSS_135
J22
J25
C27 1U_0402_6.3V4Z
1
6
4
5
GND
VSS_65
VSS_136
3
AE9
AF1
AF10
AF12
AF14
AF16
AF18
AF20
AF6
AF8
B10
B12
B14
B16
B18
B20
B23
B26
C11
C13
C15
C17
C19
C22
C25
D10
D12
D14
D16
D18
D20
D21
D24
E11
E13
E15
E17
E19
E23
E26
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85B4VSS_86B8VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92C2VSS_93
VSS_94
VSS_95C5VSS_96C7VSS_97C9VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106D3VSS_107D6VSS_108D8VSS_109E1VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
GROUND
Northwood-MT Prescott-MT
GROUND MISC
VID0
VSS_137J5VSS_138
VSS_139
VSS_140K3VSS_141K6VSS_142L1VSS_143
VSS_144
VSS_145L4VSS_146M2VSS_147
VSS_148
VSS_149M5VSS_150
VSS_151
VSS_152N3VSS_153N6VSS_154P2VSS_155
VSS_156
VSS_157P5VSS_158R1VSS_159
VSS_160
VSS_161R4VSS_162
VSS_163
VSS_164T3VSS_165T6VSS_166U2VSS_167
VSS_168
VSS_169U5VSS_170V1VSS_171
VSS_172
VSS_173V4VSS_174
VSS_175
VSS_176W3VSS_177W6VSS_178Y2VSS_179
L23
L26
K21
K24
12
R48 10K_0402_5%
M22
M25
P22
N21
N24
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, IN C. NEIT HER TH IS SHEE T NOR T HE INF ORMATION IT CONTAIN S
T21
P25
T24
R23
R26
3
V23
V26
U22
U25
W21
W24
+3VS
R270 1K_0402_5%
1 2
R271 1K_0402_5%
1 2
R272 1K_0402_5%
1 2
R267 1K_0402_5%
1 2
R266 1K_0402_5%
1 2
R16 1K_0402_5%
1 2
CPU_VID[0..5]<44>
Y22
VID1
VSS_180
VSS_181
Y5
Y25
AE5
AE4
AE3
CPU_VID2
CPU_VID0
CPU_VID1
VSS_117E4VSS_118E7VSS_119E9VSS_120
VID2
VID3
AE2
AE1
CPU_VID3
CPU_VID4
F10
F12
F14
VSS_121
VID4
VID5
AD3
CPU_VID5
2
F16
F18
F22
F25
F5
VSS_122
VSS_123
VSS_124
VSS_125F2VSS_126
VSS_127
REF
OPTIMIZED/COM PAT#
ITP
DATA
ADDR
DATA
MISC
VIDPWRGD
AF4
AD2
Pop: Prescott Depop: Northwood
2
AF26
VSS_128
SKTOCC#
GTLREF0 GTLREF1 GTLREF2 GTLREF3
TESTHI10 TESTHI11 TESTHI12
DSTBN#0 DSTBN#1 DSTBN#2 DSTBN#3
DSTBP#0 DSTBP#1 DSTBP#2 DSTBP#3
ADSTB#0 ADSTB#1
PROCHOT#
VCCVID
R12 @2.43 K_0603_1%
1
H_SKTOCC#
R320 @33_0402_5%
TESTHI0 TESTHI1 TESTHI2 TESTHI3 TESTHI4 TESTHI5 TESTHI6 TESTHI7 TESTHI8 TESTHI9
MCERR#
12
H_DPSLPR#
H_GHI#
+H_GTLREF
J26
DP#0
K25
DP#1
K26
DP#2
L25
DP#3
DBI#0 DBI#1 DBI#2 DBI#3
DBR#
SLP#
NC1 NC2 NC3 NC4 NC5
12
Title
Size Document Number Rev
Custom Date: Sheet
220P_0603_50V8J
AA21 AA6 F20 F6
AE26
AD24 AA2 AC21 AC20 AC24 AC23 AA20 AB22 U6 W4 Y3
H_GHI#
A6
H_DPSLPR#
AD25
H_DSTBN#0
E22
H_DSTBN#1
K22
H_DSTBN#2
R22
H_DSTBN#3
W22
H_DSTBP#0
F21
H_DSTBP#1
J23
H_DSTBP#2
P23
H_DSTBP#3
W23
H_ADSTB#0
L5
H_ADSTB#1
R5
H_DBI#0
E21
H_DBI#1
G25
H_DBI#2
P26
H_DBI#3
V21
AE25
H_PROCHOT#
C3 V6
H_SLP#
AB26
A22 A7 AF25 AF24 AE21
+1.2V
1
C276
0.1U_0402_16V7K
2
+1.2V
H_VID_PWRGD <35>
Compal Electronics, Inc.
Prescott / P4 uFCPGA & Thermal sensor (2/2)
LA-1931
R321 0_0402_5%
1 2
1 2
R55
0_0402_5%
C33
1 2
R_G
R326 @0_0402_5%
1 2
1 2
R80 56_0402_5%
1 2
R79 56_0402_5%
1 2 1 2 1 2 1 2 1 2 1 2 1 2
H_DS TBN#[0..3]
H_DSTBP# [0..3]
H_D BI#[0..3]
12
R323 150_0402_5%
1 2
R10 100K_0402_1%
GTL Reference Voltage
Layout note :
H_DPSLP# <8,17>
PM_CPUPERF# <18>
+CPU_CORE
R52 56_0402_5% R78 56_0402_5% R37 56_0402_5% R40 56_0402_5% R43 56_0402_5% R57 300_0402_5 % R322 @56_0402_5%
H_DS TBN#[0..3] <7>
H_DSTBP #[0..3] <7>
H_ADSTB#0 <7>
H_ADSTB#1 <7>
H_D BI#[0..3] <7>
+3VALW
+CPU_CORE
H_PROCHOT# <43>
H_SLP# <17>
1. Place R_A and R_B near CPU (Within 1.5").
+CPU_CORE
R56
51.1_0603_1%
12
R59
86.6_0603_1%
1
C34 1U_0603_6.3V6M
2
of
547Monday, June 09, 2003
1
+H_GTLREF
A
Layout note :
1 1
+CPU_CORE
2 2
+CPU_CORE
Place close to CPU, Use 2~3 vias per PA D. Place 22uF caps x31 pcs, populated 14pcs.
1
C308 22U_1206_6.3V6M
2
1
C306 22U_1206_6.3V6M
2
B
1
C313 22U_1206_6.3V6M
2
1
C297 22U_1206_6.3V6M
2
C
Place on CPU inside
1
C321 22U_1206_6.3V6M
2
1
C323 22U_1206_6.3V6M
2
1
C315 22U_1206_6.3V6M
2
1
C298 22U_1206_6.3V6M
2
1
C307 22U_1206_6.3V6M
2
1
C322 22U_1206_6.3V6M
2
D
1
C314 22U_1206_6.3V6M
2
1
C299 22U_1206_6.3V6M
2
E
Layout note :
Place close to CPU power and ground pin as possible (<1inch)
For Desktop's CPU:
470uFx15/12mOhm H=1.8 each Total 0.923m ohm
F
+CPU_CORE
+CPU_CORE
+CPU_CORE
1
+
C20 470U_D4_2.5VM
2
1
+
C18 @470U_D4_2.5VM
2
1
+
C319 470U_D4_2.5VM
2
G
1
+
C30 470U_D2_2.5VM
2
1
+
C45 470U_D4_2.5VM
2
1
+
C325 470U_D4_2.5VM
2
H
1
+
2
1
+
2
1
+
2
C11 @470U_D4_2.5VM
C53 470U_D4_2.5VM
C329 470U_D4_2.5VM
1
+
2
1
+
2
I
C40 470U_D4_2.5VM
C304 470U_D4_2.5VM
1
+
2
1
+
2
C26 470U_D4_2.5VM
C291 470U_D4_2.5VM
J
3 3
+CPU_CORE
1
2
4 4
+CPU_CORE
1
C343 @22U_1206_6.3V6M
2
Please place these cap on the socket north side
C338 @22U_1206_6.3V6M
1
C344 @22U_1206_6.3V6M
2
1
C335 @22U_1206_6.3V6M
2
1
2
1
C339 @22U_1206_6.3V6M
2
C336 @22U_1206_6.3V6M
1
2
1
C340 @22U_1206_6.3V6M
2
C345 @22U_1206_6.3V6M
1
C341 @22U_1206_6.3V6M
2
1
C337 @22U_1206_6.3V6M
2
1
C342 @22U_1206_6.3V6M
2
5 5
6 6
7 7
8 8
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
C
D
E
F
G
H
Compal Electronics, Inc.
Title
CPUDecoupling CAP.
Size Document Number Re v
LA-1931
Custom Date: Sheet
I
of
647Monday, June 09, 2003
J
0.2
5
4
3
2
1
HA#[3..31]
H_R EQ#[0..4]
HD#[0..63]
D D
C C
H_ADSTB#0<5> H_ADSTB#1<5>
CLK_MCH_BCLK#<14> CLK_MCH_BCLK<14>
R331 27 .4_0402_1%
1 2 1 2
R367 27 .4_0402_1%
+1.5VS
HUB_PSTRB<17>
HUB_PSTRB#<17>
H_D STBN#[0..3]
H_DSTBP# [0..3]
H_D BI#[0..3]
H_RESET#<5>
H_PD[0..10]
1 2
48.7_0603_1%
B B
A A
H_DST BN#[0..3]<5>
H_DSTBP# [0..3]<5>
H_DBI#[0..3]<5>
H_PD[0..10]<17>
R492
HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
CLK_MCH_BCLK# CLK_MCH_BCLK
+HYSWING
+HXSWING +HYRCOMP +HXRCOMP
+HVREF +HCCVREF +HAVREF
H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 H_DBI#0 H_DBI#1 H_DBI#2 H_DBI#3
H_PD0 H_PD1 H_PD2 H_PD3 H_PD4 H_PD5 H_PD6 H_PD7 H_PD8 H_PD9 H_PD10
HLRCOMP +HUB_PSWING +HUB_VREF
W25
AA27
W24 W23 W27
AA28
W28
AB27
AB28
AA26
AD29 AE29
HA#[3..31] <4>
H_R EQ#[0..4] <4>
HD#[0..63] <4>
U26A
Montara-GT
P23
HA#3
T25
HA#4
T28
HA#5
R27
HA#6
U23
HA7#
U24
HA#8
R24
HA#9
U28
HA#10
V28
HA#11
U27
HA#12
T27
HA#13
V27
HA#14
U25
HA#15
V26
HA#16
Y24
HA#17
V25
HA#18
V23
HA#19 HA#20
Y25
HA#21 HA#22 HA#23 HA#24 HA#25
Y27
HA#26 HA#27 HA#28 HA#29
Y26
HA#30 HA#31
R28
HREQ#0
P25
HREQ#1
R23
HREQ#2
R25
HREQ#3
T23
HREQ#4 HADSTB#0 HADSTB#1
BCLK# BCLK HYSWING HXSWING HYRCOMP HXRCOMP
HDVREF0 HDVREF1 HDVREF2 HCCVREF HAVREF
HDSTBN#0 HDSTBN#1 HDSTBN#2 HDSTBN#3 HDSTBP#0 HDSTBP#1 HDSTBP#2 HDSTBP#3 DINV0# DINV1# DINV2# DINV3#
CPURST#
HL_0 HL_1 HL_2 HL_3 HL_4 HL_5 HL_6 HL_7 HL_8 HL_9 HL_10 HLSTB HLSTB# HLRCOMP PSWING HLVREF
HOST
HUB I/F
T26
K28 B18 H28 B20
K21 J21 J17 Y28 Y22
J28 C27 E22 D18 K27 D26 E21 E18 J25 E25 B25 G19
F15
U7 U4 U3
V3 W2 W6
V6 W7
T3
V5
V4 W3
V2
T2
U2 W1
RG82G4350MA1_uFCBGA732_MONTARA-GT
HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8
HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63
ADS#
HTRDY#
DRDY#
DEFER#
HITM#
HIT# HLOCK# BREQ0#
BNR#
BPRI#
DBSY#
RS#0 RS#1 RS#2
K22 H27 K25 L24 J27 G28 L27 L23 L25 J24 H25 K23 G27 K26 J23 H26 F25 F26 B27 H23 E27 G25 F28 D27 G24 C28 B26 G22 C26 E26 G23 B28 B21 G21 C24 C23 D22 C25 E24 D24 G20 E23 B22 B23 F23 F21 C20 C21 G18 E19 E20 G17 D20 F19 C19 C17 F17 B19 G16 E16 C16 E17 D16 C18
L28 M25 N24 M28 N28 N27 P27 M23 N25 P28 M26 N23 P26 M27
HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63
H_BREQ0#
H_RS#0 H_RS#1 H_RS#2
HXSWING and HYSWING Ref. Voltage
12
R337 301_0402_1 %
+HYSWING +HXSWING
1
12
R338
150_0402_1%
C387
0.1U_0402_10V6K
2
Host data Ref. Voltage
+CPU_CORE
12
R385
49.9_0603_1%
12
R376
100_0603_1%
1
C423 1U_0402_6.3V4Z
2
1
C456
0.1U_0402_10V6K
2
Host Address Ref. Voltage
+CPU_CORE
12
R384
49.9_0603_1%
+HAVREF
1
1
C418
C427
2
0.1U_0402_10V6K
2
HUBLink reference Voltage
+HUB_PSWING
C588
0.01U_0402_25V7Z
+HUB_VREF
C592
0.01U_0402_25V7Z
Placed by GMCH
H_BREQ0#
H_ADS# <4> H_TRDY# <5> H_DRDY# <5> H_DEFER# <4> H_HITM# <4> H_HIT# <4> H_LOCK# <4> H_BREQ0# <4> H_BNR# <4>
H_BPRI# <4>
H_DBSY# <5>
H_RS#[0..2]
R383
100_0603_1 %
H_RS#[0..2] <5>
12
1U_0402_6.3V4Z
+CPU_CORE
12
R35220_0402_5%
+CPU_CORE+CPU_CORE
R392
150_0402_1 %
1.Place R385 and R376 within 0.5" of U77 pin K21 J21 J17
2.Place C423 C456 C424 C457 in order from U77 to divider
3.+HVREF 10mil trace, 20mil space.
100_0603_1 %
1.Place R337 and R338 within 0.5" of U77 pin K28
2.Place R387 and R392 within 0.5" of U77 pin B18
3.+HYSWING, +HXSWING 10mil trace, 20mil space.
12
R387 301_0402_1 %
12
1
C447
0.1U_0402_10V6K
2
+HVREF
1
2
C389
R455
80.6_0402_1%
1
2
1
2
1
C457 @0.1U_0402_10V6K
2
+HCCVREF
1
C390
2
0.1U_0402_10V6K
C593
0.1U_0402_10V6K
C591
0.1U_0402_10V6K
1
2
+CPU_CORE
R335
1
2
1
2
C424 @0.1U_0402_10V6K
12
R334
49.9_0603_1%
12
1U_0402_6.3V4Z
+1.5VS
12
12
R491
51.1_0603_1%
12
R490
40.2_0603_1%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, IN C. NEIT HER TH IS SHEE T NOR T HE INF ORMATION IT CONTAIN S
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CON SENT OF COMPAL ELE CTRONICS , INC.
3
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, In c.
Montara-GT (1/4)
LA-1931
of
747Monday, June 09, 2003
1
5
4
3
2
1
I2C BUS PULL UP
+1.5VS
RP65
18 27
D D
+1.5VS_DVO
DVOBC_CLKINT
12
C C
RTCCLK<18>
B B
A A
36 45
2.2K_0804_8P4R_5%
1 2
R470 100 K_0402_5%
R465
@22_0402_5%
C578
@10P_0402_50V8K
CLK_MCH_66M
12
R464 @33_0402_5%
1
C577 @10P_0402_25V8K
2
+1.5VS
12
1
5
MI2CCLK
R4282.2K_0402_5%
MI2CDATA
R4272.2K_0402_5%
MDDCCLK MDDCDATA MDVICLK MDVIDATA
DVOBCINTR#
W/O TV-OUT R465 = 50K; C578 = 50K.
W/ TV-OUT De-Pop
R468
1K_0402_5%
D
S
3G2
DVOC_TV_D[0..11]<15>
DPMS
Q34 BSS138_SOT23
1K_0402_1%
R489
40.2_0603_1%
+1.5VS
R471
12
+1.5VS
R477100K_0402_5%
R451100K_0402_5%
R4481K_0402_5%
DVOBC_CLKINT<15>
TV_CLK<15>
TV_CLK#<15> TV_HSYNC<15> TV_VSYNC<15>
MI2CCLK<15> MI2CDATA<15>
DVOC_TV_D[0..11]
R486 1K_0402_1%
+GVREF
Close to Ball F1
C601
0.1U_0402_16V4Z
AGP_BUSY#<18>
CLK_MCH_66M<14>
1 2
R484 @1K_0402_5%
1 2
R496 @1K_0402_5%
1 2
R495 @1K_0402_5%
1 2
R497 @1K_0402_5%
1 2
R533 1K_0402_5%
DVOB_FLDSTL
12
DVOC_FLDSTL
12
ADDID7
12
DVODETECT
4
DVOB_FLDSTL
DVOBCINTR# DVOBC_CLKINT
DVOC_FLDSTL
MI2CCLK MI2CDATA MDVICLK MDVIDATA MDDCCLK MDDCDATA
DVOC_TV_D0 DVOC_TV_D1 DVOC_TV_D2 DVOC_TV_D3 DVOC_TV_D4 DVOC_TV_D5 DVOC_TV_D6 DVOC_TV_D7 DVOC_TV_D8 DVOC_TV_D9 DVOC_TV_D10 DVOC_TV_D11
ADDID7
DVODETECT DPMS +GVREF
CLK_MCH_66M
GST2 GST1 GST0
GST2
GST1
GST0
W/O TV-OUT De-Pop
W/ TV-OUT Pop
U26B
Montara-GT
R3
DVOBD0/GAD3
R5
DVOBD1/GAD2
R6
DVOBD2/GAD5
R4
DVOBD3/GAD4
P6
DVOBD4/GAD7
P5
DVOBD5/GAD6
N5
DVOBD6/GAD8
P2
DVOBD7/GCBE0#
N2
DVOBD8/GAD10
N3
DVOBD9/GAD9
M1
DVOBD10/GAD12
M5
DVOBD11/GAD11
P3
DVOBCLK/GADSTB0
P4
DVOBCLK#/GADSTB0#
T6
DVOBHSYNC/GAD0
T5
DVOBVSYNC/GAD1
L2
DVOBBLANK#/GCBE1#
M2
DVOBFLDSTL/GAD14
G2
DVOBCINTR#/GAD30
M3
DVOBCCLKINT/GAD13
J3
DVOCCLK/GADSTB1
J2
DVOCCLK#/GADSTB1#
K6
DVOCHSYNC/GAD17
L5
DVOCVSYNC/GAD16
L3
DVOCBLANK#/GAD18
H5
DVOCFLDSTL/GAD31
K7
MI2CCLK/GIRDY#
N6
MI2CDATA/GDEVS EL#
N7
MDVICLK/GTRDY#
M6
MDVIDATA/GFRAME#
P7
MDDCCLK/GSTOP#
T7
MDDCDATA/GAD15
K5
DVOCD0/GAD19
K1
DVOCD1/GAD20
K3
DVOCD2/GAD21
K2
DVOCD3/GAD22
J6
DVOCD4/GAD23
J5
DVOCD5/GCBE3#
H2
DVOCD6/GAD25
H1
DVOCD7/GAD24
H3
DVOCD8/GAD27
H4
DVOCD9/GAD26
H6
DVOCD10/GAD29
G3
DVOCD11/GAD28
E5
ADDID0/GSBA0
F5
ADDID1/GSBA1
E3
ADDID2/GSBA2
E2
ADDID3/GSBA3
G5
ADDID4/GSBA4
F4
ADDID5/GSBA5
G6
ADDID6/GSBA6
F6
ADDID7/GSBA7
L7
DVODETECT/GPAR
D5
DPMS/GPIPE#
F1
GVREF
F7
AGPBUSY#
D1
DVO_GRCOMP
Y3
GCLKIN
F2
GSBSTB
F3
GSBSTB#
B2
GGNT#
B3
GREQ#
C2
GST2
C3
GST1
C4
GST0
D2
GWBF#
D3
GRBF#
L4
GCBE#2
D7
RSVD1
AA5
RSVD2
RG82G435 0MA1_uFCBGA732_MONTARA-GT
PANELBKLTCTL
PANELBKLTEN
PANELVDDEN
DVO
BLUE#
GREEN
GREEN#
HSYNC VSYNC
DAC
REFSET
DDCACLK
DDCADATA
IYAM0 IYAM1 IYAM2 IYAM3
IYBM0 IYBM1 IYBM2 IYBM3
LVDS
ICLKAM
ICLKAP
ICLKBM
ICLKBP
DDCPCLK
DDCPDATA
RSVD3 RSVD4 RSVD5
DREFCLK
DREFSSCLK
LCLKCTLA LCLKCTLB
CLKS
DPWR# DPSLP#
RSTIN#
PWROK
MISCNC
EXTTS0
BLUE
RED
RED#
IYAP0 IYAP1 IYAP2 IYAP3
IYBP0 IYBP1 IYBP2 IYBP3
LIBG
NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8
NC9 NC10 NC11
3
C9 D9 C8 D8 A7 A8 H10 J9 E8 B6 G9
G14 E15 C15 C13 F14 E14 C14 B13 H12 E12 C12 G11 G12 E11 C11 G10 D14 E13 E10 F10
R483 2.2K_0402_5%
B4
R476 2.2K_0402_5%
C5
G8
PANEL_BKEN
F8 A5
A10
D12 F12 B12
CLK_MCH_DISPLAY
B7 B17 H9
LCLKCTLB
C6
AA22
H_DPSLP#
Y23 AD28
J11
D6
B1 AH1 A2 AJ2 A28 AJ28 A29 B29 AH29 AJ29 AA9 AJ4
INTCRT_B <16>
INTCRT_G <16>
INTCRT_R <16>
INTCRT_HSYNC <16> INTCRT_VSYNC <16>
INTDDCCK <16> INTDDCDA <16>
LCD_A0- <16> LCD_A1- <16> LCD_A2- <16>
LCD_A0+ <16> LCD_A1+ <16> LCD_A2+ <16>
LCD_B0- <16> LCD_B1- <16> LCD_B2- <16>
LCD_B0+ <16> LCD_B1+ <16> LCD_B2+ <16>
LCD_ACLK- <16> LCD_ACLK+ <16> LCD_BCLK- <16>
1 2 1 2
R485 0_0402_5%
R444 1.5K_0603_1%
LCD_BCLK+ <16>
1 2
1 2
CLK_MCH_DISPLAY <14> CLK_VCH <14>
1 2
R456 1K_0402_5%
H_DPSLP# <5,17> PCIRST# <15,17,20,21,22,23,25,26,31,32>
SYS_PWROK <18,35>
1 2
R466 10K_0603_1%
R450
127_0603_1%
1 2
+3VS
ENBKL <32> ENVDD <16>
+3VS
LCLKCTLB H:1.2V
PSB Voltage Select
+3VS
Title
Size Document Number Rev
2
Date: Sheet
CLK_MCH_DISPLAY
R443
@33_0402_5%
C552
@10P_0402_25V8K
LA-1931
CLK_VCH
12
1
2
Compal Electronics, In c.
Montara-GT (2/4)
1
12
R405 @33_0402_5%
1
C470 @10P_0402_25V8K
2
847Monday, June 09, 2003
of
5
4
3
2
1
D D
DDR_SDQS[0..7]<11>
+2.5V
12
R487
R366
R365
R395
R396
60.4_0603_1%
1
C598
0.1U_0402_10V6K
2
+2.5V
12
12
+2.5V
12
12
+SMRCOMP
12
R488
60.4_0603_1%
+SMVSWINGL
1
C459
0.1U_0402_10V6K
2
+SMVSWINGH
1
C541
0.1U_0402_10V6K
2
DDR_SDM[0..7]<11>
C C
604_0603_1 %
150_0603_1 %
B B
150_0603_1 %
604_0603_1 %
A A
DDR_SMA[0..12]
DDR_SDQS[0..7]
DDR_SWE#<11> DDR_SRAS#<11> DDR_SCAS#<11>
DDR_CLK0<11> DDR_CLK0#<11> DDR_CLK1<11> DDR_CLK1#<11>
DDR_CLK3<12> DDR_CLK3#<12> DDR_CLK4<12> DDR_CLK4#<12>
DDR_CKE0<11> DDR_CKE1<11> DDR_CKE2<12> DDR_CKE3<12> DDR_SCS#0<11> DDR_SCS#1<11> DDR_SCS#2<12> DDR_SCS#3<12>
DDR_SBS0<11> DDR_SBS1<11>
DDR_SDM[0..7]
DDR_SMAB1<12> DDR_SMAB2<12> DDR_SMAB4<12> DDR_SMAB5<12>
Need place Via as closed as pin.
+SMRCOMP
+SMVSWINGL +SMVSWINGH
DDR_SDQS0 DDR_SDQS1 DDR_SDQS2 DDR_SDQS3 DDR_SDQS4 DDR_SDQS5 DDR_SDQS6 DDR_SDQS7
DDR_SDM0 DDR_SDM1 DDR_SDM2 DDR_SDM3 DDR_SDM4 DDR_SDM5 DDR_SDM6 DDR_SDM7
DDR_SMAB1 DDR_SMAB2 DDR_SMAB4 DDR_SMAB5
DDR_SMA0 DDR_SMA1 DDR_SMA2 DDR_SMA3 DDR_SMA4 DDR_SMA5 DDR_SMA6 DDR_SMA7 DDR_SMA8 DDR_SMA9 DDR_SMA10 DDR_SMA11 DDR_SMA12
DDR_SWE# DDR_SRAS# DDR_SCAS#
DDR_CLK0 DDR_CLK0# DDR_CLK1 DDR_CLK1#
DDR_CLK3 DDR_CLK3# DDR_CLK4 DDR_CLK4#
DDR_CKE0 DDR_CKE1 DDR_CKE2 DDR_CKE3 DDR_SCS#0 DDR_SCS#1 DDR_SCS#2 DDR_SCS#3
DDR_SBS0 DDR_SBS1
U26C
AC18 AD14 AD13 AD17 AD11 AC13
AD8 AD7 AC6 AC5
AC19
AD5 AB5
AG2 AH5
AH8 AE12 AH17 AE21 AH24 AH27 AD15
AD25 AC21 AC24
AB2
AA2 AC26 AB25
AC3
AD4
AC2
AD2 AB23 AB24
AA3
AB4
AC7
AB7
AC9 AC10 AD23 AD26 AC22 AC25
AD22 AD20
AE5
AE6
AE9 AH12 AD19 AD21 AD24 AH28 AH15
AD16 AC12 AF11 AD10
AC15 AC16
AB1
AJ22 AJ19
Montara-GT
SMA0 SMA1 SMA2 SMA3 SMA4 SMA5 SMA6 SMA7 SMA8 SMA9 SMA10 SMA11 SMA12
SDQS0
MEMORY
SDQS1 SDQS2 SDQS3 SDQS4 SDQS5 SDQS6 SDQS7 SDQS8
SWE# SRAS# SCAS#
SCK0 SCK0# SCK1 SCK1# SCK2 SCK2# SCK3 SCK3# SCK4 SCK4# SCK5 SCK5#
SCKE0 SCKE1 SCKE2 SCKE3 SCS#0 SCS#1 SCS#2 SCS#3
SBA0 SBA1
SDM0 SDM1 SDM2 SDM3 SDM4 SDM5 SDM6 SDM7 SDM8
SMAB1 SMAB2 SMAB4 SMAB5
RCVENOUT# RCVENIN#
SMRCOMP
SMVSWINGL SMVSWINGH
RG82G435 0MA1_uFCBGA732_MONTARA-GT
SDQ0 SDQ1 SDQ2 SDQ3 SDQ4 SDQ5 SDQ6 SDQ7 SDQ8
SDQ9 SDQ10 SDQ11 SDQ12 SDQ13 SDQ14 SDQ15 SDQ16 SDQ17 SDQ18 SDQ19 SDQ20 SDQ21 SDQ22 SDQ23 SDQ24 SDQ25 SDQ26 SDQ27 SDQ28 SDQ29 SDQ30 SDQ31 SDQ32 SDQ33 SDQ34 SDQ35 SDQ36 SDQ37 SDQ38 SDQ39 SDQ40 SDQ41 SDQ42 SDQ43 SDQ44 SDQ45 SDQ46 SDQ47 SDQ48 SDQ49 SDQ50 SDQ51 SDQ52 SDQ53 SDQ54 SDQ55 SDQ56 SDQ57 SDQ58 SDQ59 SDQ60 SDQ61 SDQ62 SDQ63
SDQ64 SDQ65 SDQ66 SDQ67 SDQ68 SDQ69 SDQ70 SDQ71
SMVREF0
DDR_SDQ0
AF2
DDR_SDQ1
AE3
DDR_SDQ2
AF4
DDR_SDQ3
AH2
DDR_SDQ4
AD3
DDR_SDQ5
AE2
DDR_SDQ6
AG4
DDR_SDQ7
AH3
DDR_SDQ8
AD6
DDR_SDQ9
AG5
DDR_SDQ10
AG7
DDR_SDQ11
AE8
DDR_SDQ12
AF5
DDR_SDQ13
AH4
DDR_SDQ14
AF7
DDR_SDQ15
AH6
DDR_SDQ16
AF8
DDR_SDQ17
AG8
DDR_SDQ18
AH9
DDR_SDQ19
AG10
DDR_SDQ20
AH7
DDR_SDQ21
AD9
DDR_SDQ22
AF10
DDR_SDQ23
AE11
DDR_SDQ24
AH10
DDR_SDQ25
AH11
DDR_SDQ26
AG13
DDR_SDQ27
AF14
DDR_SDQ28
AG11
DDR_SDQ29
AD12
DDR_SDQ30
AF13
DDR_SDQ31
AH13
DDR_SDQ32
AH16
DDR_SDQ33
AG17
DDR_SDQ34
AF19
DDR_SDQ35
AE20
DDR_SDQ36
AD18
DDR_SDQ37
AE18
DDR_SDQ38
AH18
DDR_SDQ39
AG19
DDR_SDQ40
AH20
DDR_SDQ41
AG20
DDR_SDQ42
AF22
DDR_SDQ43
AH22
DDR_SDQ44
AF20
DDR_SDQ45
AH19
DDR_SDQ46
AH21
DDR_SDQ47
AG22
DDR_SDQ48
AE23
DDR_SDQ49
AH23
DDR_SDQ50
AE24
DDR_SDQ51
AH25
DDR_SDQ52
AG23
DDR_SDQ53
AF23
DDR_SDQ54
AF25
DDR_SDQ55
AG25
DDR_SDQ56
AH26
DDR_SDQ57
AE26
DDR_SDQ58
AG28
DDR_SDQ59
AF28
DDR_SDQ60
AG26
DDR_SDQ61
AF26
DDR_SDQ62
AE27
DDR_SDQ63
AD27
AG14 AE14 AE17 AG16 AH14 AE15 AF16 AF17
SMVREF0
AJ24
C408
0.1U_0402_10V6K
1
2
DDR_SDQ[0..63]
+SDREF
DDR_SDQ[0..63] <11>DDR_SMA[0..12]<11,12>
TOPOLOGY 1 FOR DDR
SMAA[12:6,3,0], SBA[1:0], SRAS#, SCAS#, SWE#
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, IN C. NEIT HER TH IS SHEE T NOR T HE INF ORMATION IT CONTAIN S
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CON SENT OF COMPAL ELE CTRONICS , INC.
3
2
Size Document Number Rev
Date: Sheet
Compal Electronics, In c.
Montara-GT (3/4)
LA-1931
of
947Monday, June 09, 2003
1
5
U26D
C1
VSS0
G1
VSS1
L1
VSS2
U1
VSS3
AA1
VSS4
AE1
VSS5
R2
VSS6
D D
C C
B B
A A
AG3
VSS7
AJ3
VSS8
D4
VSS9
G4
VSS10
K4
VSS11
N4
VSS12
T4
VSS13
W4
VSS14
AA4
VSS15
AC4
VSS16
AE4
VSS17
B5
VSS18
U5
VSS19
Y5
VSS20
Y6
VSS21
AG6
VSS22
C7
VSS23
E7
VSS24
G7
VSS25
J7
VSS26
M7
VSS27
R7
VSS28
AA7
VSS29
AE7
VSS30
AJ7
VSS31
H8
VSS32
K8
VSS33
P8
VSS34
T8
VSS35
V8
VSS36
Y8
VSS37
AC8
VSS38
E9
VSS39
L9
VSS40
N9
VSS41
R9
VSS42
U9
VSS43
W9
VSS44
AB9
VSS45
AG9
VSS46
C10
VSS47
J10
VSS48
AA10
VSS49
AE10
VSS50
D11
VSS51
F11
VSS52
H11
VSS53
AB11
VSS54
AC11
VSS55
AJ11
VSS56
J12
VSS57
AA12
VSS58
AG12
VSS59
A13
VSS60
D13
VSS61
F13
VSS62
H13
VSS63
N13
VSS64
R13
VSS65
U13
VSS66
AB13
VSS67
AE13
VSS68
J14
VSS69
P14
VSS70
T14
VSS71
AA14
VSS72
AC14
VSS73
D15
VSS74
H15
VSS75
N15
VSS76
R15
VSS77
U15
VSS78
AB15
VSS79
AG15
VSS80
F16
VSS81
J16
VSS82
P16
VSS83
T16
VSS84
AA16
VSS85
AE16
VSS86
A17
VSS87
D17
VSS88
H17
VSS89
N17
VSS90
RG82G435 0MA1_uFCBGA732_MONTARA-GT
Montara-GT
VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98
VSS99 VSS100 VSS101 VSS102 VSS103 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182
R17 U17 AB17 AC17 F18 J18 AA18 AG18 A19 D19 H19 AB19 AE19 F20 J20 AA20 AC20 A21 D21 H21 M21 P21 T21 V21 Y21 AA21 AB21 AG21 B24 F22 J22 L22 N22 R22 U22 W22 AE22 A23 D23 AA23 AC23 AJ23 F24 H24 K24 M24 P24 T24 V24 AA24 AG24 A25 D25 AA25 AE25 G26 J26 L26 N26 R26 U26 W26 AB26 A27 F27 AC27 AG27 AJ27 AC28 AE28 C29 E29 G29 J29 L29 N29 U29 W29 AA29 AJ10 AJ12 AJ18 AJ20 C22 D28 E28 L6 T9 AJ26 AJ1
4
+1.5VS
L37
KC FBM-L11-201209-221LMAT_0805
1 2
CLOSE TO PIN
C525 220U_D2_4VM
1 2
L28
KC FBM-L11-201209-221LMAT_0805
+1.5VS
C501
@220U_D2_4VM
47U_1210_6.3V4Z
1 2
FLM1608081R8K_0603
47U_1210_6.3V4Z
220U_D2_4VM
12
L35
FLM1608081R8K_0603
1
0.01U_04 02_25V7Z
1
+
2
2
C535
0.1U_0402_10V6K
+1.5VS_DLVDS
1
C468
2
L32
C512
0.1U_0402_10V6K
L33
1 2
FLM1608081R8K_0603
C465
C400
1
150U_D2_6.3VM
+
2
C358 150U_D2_6.3VM
+VCCADPLLA
1
+
0.1U_0402_10V6K
2
+VCCADPLLB
1
+
C478
2
C432
0.1U_0402_10V6K
+1.5VS_DAC
C534
1
2
1
C491 22U_1210_6.3V6M
2
1
0.01U_04 02_25V7Z
2
C484
22U_1206_16V4Z_V1
1
1
2
2
0.1U_0402_10V6K
1
+
2
C461
10U_1206_6.3V7K
1
C562
2
1
2
0.1U_0402_10V6K
+1.5VS
L31
BLM21A601SPT_0805
1 2
C579
0.1U_0402_10V6K
C580
0.1U_0402_10V6K
1
C521
2
1
2
C505
CLOSE TO VCC
C442
0.1U_0402_10V6K
1
1
2
2
+1.5VS
C480
10U_1206_6.3V7K
C599
1
0.1U_0402_10V6K
2
1
C618 150U_D 2_6.3VM
2
1
C546
2
0.1U_0402_10V6K
L29
1 2
FLM1608081R8K_0603
C520
0.1U_0402_10V6K
1
1
2
2
C530
0.1U_0402_10V6K
C500
0.1U_0402_10V6K
+2.5V_TXLVDS+2.5V
3
C479
0.1U_0402_10V6K
1
1
2
2
C540
0.1U_0402_10V6K
CLOSE TO VCCHL
C561
0.1U_0402_10V6K
1
1
2
2
+1.5VS
1
C369
2
1
1
+
2
2
C513
10U_1206_6.3V7K
1
1
C545
2
2
0.1U_0402_10V6K
+1.5VS_DLVDS+1.5VS+1.5VS_ALVDS+1.5VS
+3VS
10U_1206_6.3V7K
1
C428
2
0.1U_0402_10V6K
C572
0.1U_0402_10V6K
1
2
C600
0.1U_0402_10V6K
+1.5VS_DVO
C544
1
0.1U_0402_10V6K
2
0.1U_0402_10V6K
+1.5VS_DAC
+1.5VS_ALVDS
+1.5VS_DLVDS
1
2
+2.5V_TXLVDS
R493
0_0603_5%
1 2
C609
+1.5VS
1
2
+VCCADPLLA +VCCADPLLB
1
2
C543
+VCC_GPIO
1
0.1U_0402_10V6K
2
U26E
Montara-GT
J15
VCC0
P13
VCC1
T13
VCC2
N14
VCC3
R14
VCC4
U14
VCC5
P15
VCC6
T15
VCC7
AA15
VCC8
N16
VCC9
R16
VCC10
U16
VCC11
P17
VCC12
T17
VCC13
AA17
VCC14
AA19
VCC15
W21
VCC16
H14
VCC17
V1
VCCHL0
Y1
VCCHL1
W5
VCCHL2
U6
VCCHL3
U8
VCCHL4
W8
VCCHL5
V7
VCCHL6
V9
VCCHL7
D29
VCCAHPLL
Y2
VCCAGPLL
A6
VCCADPLLA
B16
VCCADPLLB
E1
VCCDVO_0
J1
VCCDVO_1
N1
VCCDVO_2
E4
VCCDVO_3
J4
VCCDVO_4
M4
VCCDVO_5
E6
VCCDVO_6
H7
VCCDVO_7
J8
VCCDVO_8
L8
VCCDVO_9
M8
VCCDVO_10
N8
VCCDVO_11
R8
VCCDVO_12
K9
VCCDVO_13
M9
VCCDVO_14
P9
VCCDVO_15
A9
VCCADAC0
B9
VCCADAC1
B8
VSSADAC
A11
VCCALVDS
B11
VSSALVDS
G13
VCCDLVDS0
B14
VCCDLVDS1
J13
VCCDLVDS2
B15
VCCDLVDS3
F9
VCCTXLVDS0
B10
VCCTXLVDS1
D10
VCCTXLVDS2
A12
VCCTXLVDS3
A3
VCCGPIO_0
A4
VCCGPIO_1
1
RG82G435 0MA1_uFCBGA732_MONTARA-GT
C585
2
POWER
2
VTTLF0 VTTLF1 VTTLF2 VTTLF3 VTTLF4 VTTLF5 VTTLF6 VTTLF7 VTTLF8
VTTLF9 VTTLF10 VTTLF11 VTTLF12 VTTLF13 VTTLF14 VTTLF15 VTTLF16 VTTLF17 VTTLF18 VTTLF19 VTTLF20
VTTHF0
VTTHF1
VTTHF2
VTTHF3
VTTHF4
VCCSM0 VCCSM1 VCCSM2 VCCSM3 VCCSM4 VCCSM5 VCCSM6 VCCSM7 VCCSM8 VCCSM9
VCCSM10 VCCSM11 VCCSM12 VCCSM13 VCCSM14 VCCSM15 VCCSM16 VCCSM17 VCCSM18 VCCSM19 VCCSM20 VCCSM21 VCCSM22 VCCSM23 VCCSM24 VCCSM25 VCCSM26 VCCSM27 VCCSM28 VCCSM29 VCCSM30 VCCSM31 VCCSM32 VCCSM33 VCCSM34 VCCSM35 VCCSM36
VCCQSM0 VCCQSM1
VCCASM0 VCCASM1
G15 H16 H18 J19 H20 L21 N21 R21 U21 H22 M22 P22 T22 V22 Y29 K29 F29 AB29 A26 A20 A18
A22 A24 H29 M29 V29
AC1 AG1 AB3 AF3 Y4 AJ5 AA6 AB6 AF6 Y7 AA8 AB8 Y9 AF9 AJ9 AB10 AA11 AB12 AF12 AA13 AJ13 AB14 AF15 AB16 AJ17 AB18 AF18 AB20 AF21 AJ21 AB22 AF24 AJ25 AF27 AC29 AF29 AG29
0.1U_0402_10V6K
AJ6 AJ8
VCC_ASM
AD1 AF1
C597
0.1U_0402_10V6K
+CPU_CORE
1
2
C420
0.1U_0402_10V6K
+2.5V
C502
0.1U_0402_10V6K
1
2
C394
0.1U_0402_10V6K
C529
0.1U_0402_10V6K
1
2
C455
0.1U_0402_10V6K
C771 & C772 change to 100u next Reversion
1
C506
+
150U_D2_4VM
2
C547
1
1
2
2
1
1
+
2
2
C419
0.1U_0402_10V6K
0.1U_0402_10V6K
C417 0.1U_0402_10V6K
C406 0.1U_0402_10V6K
C380 0.1U_0402_10V6K
C379 0.1U_0402_10V6K
C378 0.1U_0402_10V6K
1
2
1
2
150U_D2_4VM
C560
4.7U_1206_10V7K
C612 100U_D_16VM
1
1
2
2
KC FBM-L11-201209-221LMAT_0805
C429
10U_1206_6.3V7K
0.1U_0402_10V6K
1
1
C368
C443
2
2
1 2
1 2
1 2
1 2
1 2
C439
0.1U_0402_10V6K
1
1
2
2
C528
0.1U_0402_10V6K
C477
0.1U_0402_10V6K
1
1
2
1
C587
2
0.1U_0402_10V6K
2
C499
0.1U_0402_10V6K
1
C388
+
0.1U_0402_10V6K
2
L39
1 2
L40
1 2
KC FB M-L11-201209-221LMAT_0805
1
1
+
C357 150U_D2_4VM
2
0.1U_0402_10V6K
1
C469
2
0.1U_0402_10V6K
1
C381
2
0.1U_0402_10V6K
1
C519
2
0_0805_5%
1 2
1
C403
2
0.1U_0402_10V6K
1
C426
2
0.1U_0402_10V6K
1
C558
2
0.1U_0402_10V6K
R429
+1.5VS
1
C542
2
+2.5V+2.5V_QSM
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEE T NOR THE IN FORMATION IT C ONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN C ONSENT OF COMPAL EL ECTRONICS , INC.
3
2
Size Document Number Rev
Date: Sheet
Compal Electronics, In c.
Montara-GT(4/4)
LA-1931
of
10 47Monday, June 09, 2003
1
A
RP100 10_0404_4P2R_5%
DDR_SDQ0 DDR_DQ0 DDR_SDQ1 DDR_DQ1
DDR_SDQ4 DDR_DQ4 DDR_SDQ5
DDR_SDQ2 DDR_DQ2
1 1
DDR_SDQ6 DDR_DQ6
DDR_SDQ8 DDR_DQ8 DDR_SDQ13 DDR_DQ13
DDR_SDQ12 DDR_SDQ9 DDR_DQ9
DDR_SDQ15 DDR_DQ15 DDR_SDQ14 DDR_DQ14
DDR_SDQ10 DDR_DQ10 DDR_SDQ11 DDR_DQ11
DDR_SDQ18 DDR_DQ18 DDR_SDQ16 DDR_DQ16
2 2
DDR_SDQ20 DDR_DQ20
DDR_SDQ21 DDR_DQ21 DDR_SDQ23 DDR_DQ23
DDR_SDQ25 DDR_DQ25 DDR_SDQ31 DDR_DQ31
DDR_SDQ24 DDR_DQ24 DDR_SDQ28 DDR_DQ28
DDR_SDQ60 DDR_DQ60 DDR_SDQ61
DDR_SDQ57 DDR_DQ57 DDR_SDQ56 DDR_DQ56
3 3
4 4
1 4 2 3
RP101 10_0404_4P2R_5%
1 4 2 3
RP97 10_0404_4P2R_5%
1 4 2 3
RP95 10_0404_4P2R_5%
1 4 2 3
RP94 10_0404_4P2R_5%
1 4 2 3
RP92 10_0404_4P2R_5%
1 4 2 3
RP88 10_0404_4P2R_5%
1 4 2 3
RP86 10_0404_4P2R_5%
1 4 2 3
RP80 10_0404_4P2R_5%
1 4 2 3
RP84 10_0404_4P2R_5%
1 4 2 3
RP75 10_0404_4P2R_5%
1 4 2 3
RP82 10_0404_4P2R_5%
1 4 2 3
RP73 10_0404_4P2R_5%
1 4 2 3
RP78 10_0404_4P2R_5%
1 4 2 3
RP24 10_0404_4P2R_5%
1 4 2 3
RP26 10_0404_4P2R_5%
1 4 2 3
DDR_SDQS0
R507 10_0402_5%
DDR_SDQS1
R500 10_0402_5%
DDR_SDQS2
R459 10_0402_5%
DDR_SDQS3 DDR_DQS3
R440 10_0402_5%
DDR_SDQS4
R361 10_0402_5%
DDR_SDQS5
R343 10_0402_5%
DDR_SDQS6
R333 10_0402_5%
DDR_SDQS7
R330 10_0402_5%
A
12
12
12
12
12
12
12
12
DDR_DQ5
DDR_DQ3DDR_SDQ3
DDR_DQ7DDR_SDQ7
DDR_DQ12
DDR_DQ17DDR_SDQ17
DDR_DQ19DDR_SDQ19 DDR_DQ22DDR_SDQ22
DDR_DQ61
DDR_DQS0
DDR_DQS1
DDR_DQS2
DDR_DQS4
DDR_DQS5
DDR_DQS6
DDR_DQS7
B
RP68 10_0404_4P2R_5%
DDR_SDQ27 DDR_DQ27 DDR_SDQ29 DDR_DQ29
DDR_SDQ30 DDR_DQ30 DDR_SDQ26 DDR_DQ26
DDR_SDQ37 DDR_DQ37 DDR_SDQ33
DDR_SDQ32 DDR_SDQ36
DDR_SDQ39
DDR_SDQ35
DDR_SDQ38 DDR_SDQ34
DDR_SDQ40 DDR_DQ40 DDR_SDQ44
DDR_SDQ41
DDR_SDQ45
DDR_SDQ43 DDR_SDQ47 DDR_DQ47
DDR_SDQ46 DDR_DQ46 DDR_SDQ42
DDR_SDQ52 DDR_SDQ50 DDR_DQ50
DDR_SDQ48 DDR_SDQ53
DDR_SDQ51 DDR_SDQ54 DDR_DQ54
DDR_SDQ49
DDR_SDQ62 DDR_DQ62 DDR_SDQ63 DDR_DQ63
DDR_SDQ58 DDR_DQ58 DDR_SDQ59 DDR_DQ59
1 4 2 3
RP70 10_0404_4P2R_5%
1 4 2 3
RP56 10_0404_4P2R_5%
1 4 2 3
RP54 10_0404_4P2R_5%
1 4 2 3
RP47 10_0404_4P2R_5%
1 4 2 3
RP49 10_0404_4P2R_5%
1 4 2 3
RP43 10_0404_4P2R_5%
1 4 2 3
RP45 10_0404_4P2R_5%
1 4 2 3
RP38 10_0404_4P2R_5%
1 4 2 3
RP40 10_0404_4P2R_5%
1 4 2 3
RP34 10_0404_4P2R_5%
1 4 2 3
RP36 10_0404_4P2R_5%
1 4 2 3
RP30 10_0404_4P2R_5%
1 4 2 3
RP28 10_0404_4P2R_5%
1 4 2 3
RP21 10_0404_4P2R_5%
1 4 2 3
RP19 10_0404_4P2R_5%
1 4 2 3
DDR_SDM0
R506 10_0402_5%
DDR_SDM1
R498 10_0402_5%
DDR_SDM2 DDR_DM2
R475 10_0402_5%
DDR_SDM3
R449 10_0402_5%
DDR_SDM4 DDR_DM4
R363 10_0402_5%
DDR_SDM5 DDR_DM5
R345 10_0402_5%
DDR_SDM6 DDR_DM6
R332 10_0402_5%
DDR_SDM7
R329 10_0402_5%
DDR_SDQ[0..63]
DDR_SDQS[0..7]
DDR_SDM[0 ..7]
DDR_SMA[1..2]
DDR_SMA[4..5]
DDR_SMA[6..12]
DDR_SMA0
DDR_SMA3
B
DDR_DQ33
DDR_DQ32 DDR_DQ36
DDR_DQ39 DDR_DQ35
DDR_DQ38 DDR_DQ34
DDR_DQ44
DDR_DQ41 DDR_DQ45
DDR_DQ43
DDR_DQ42
DDR_DQ52
DDR_DQ48 DDR_DQ53
DDR_DQ51
DDR_DQ49 DDR_DQ55DDR_SDQ55
DDR_DM0
12
DDR_DM1
12
12
DDR_DM3
12
12
12
12
DDR_DM7
12
DDR_SDQ[0..6 3] <9>
DDR_SDQS[0..7] <9>
DDR_SDM[0..7 ] <9>
DDR_SMA[1..2] <9,12>
DDR_SMA[4..5] <9,12>
DDR_SMA[6..12] <9>
DDR_SMA0 <9>
DDR_SMA3 <9>
C
DDR_CLK0<9> DDR_CLK0#<9>
DDR_CKE1<9>
DDR_SCS#0<9>
Layout note Place these resistors
close to DIMM0, all trace length<500 mil
DDR TOPOLOGY 1 FOR SMAA[0, 3, 6:12], SBA[1, 0], SRAS#, SCAS#, SWE#
C
D
+2.5V
JP21
1
VREF
3
DDR_DQ4 DDR_DQ5
DDR_DQS0 DDR_DQ3
DDR_DQ2 DDR_DQ8
DDR_DQ13 DDR_DQS1
DDR_DQ15
DDR_DQ18 DDR_DQ16
DDR_DQS2 DDR_DQ21
DDR_DQ23 DDR_DQ25
DDR_DQ31 DDR_DQS3
DDR_DQ27 DDR_DQ29
DDR_CKE1
DDR_SMA12 DDR_SMA9
DDR_SMA7 DDR_SMA5 DDR_SMA3 DDR_SMA1
DDR_SMA10 DDR_SBS0 DDR_SWE# DDR_ SCS#0
DDR_DQ32 DDR_DQ36
DDR_DQS4 DDR_DQ39
DDR_DQ35 DDR_DQ40
DDR_DQ44 DDR_DQS5
DDR_DQ43 DDR_DQ47
DDR_DQ52 DDR_DQ50
DDR_DQ51
DDR_DQ54 DDR_DQ57
DDR_DQ56 DDR_DQS7
DDR_DQ62 DDR_DQ58 DDR_DQ63
SMDATA<12,14,17>
SMCLK<12,14,17>
+3VS
D
VSS
5
DQ0
7
DQ1
9
VDD
11
DQS0
13
DQ2
15
VSS
17
DQ3
19
DQ8
21
VDD
23
DQ9
25
DQS1
27
VSS
29
DQ10
31
DQ11
33
VDD
35
CK0
37
CK0#
39
VSS
41
DQ16
43
DQ17
45
VDD
47
DQS2
49
DQ18
51
VSS
53
DQ19
55
DQ24
57
VDD
59
DQ25
61
DQS3
63
VSS
65
DQ26
67
DQ27
69
VDD
71
CB0
73
CB1
75
VSS
77
DQS8
79
CB2
81
VDD
83
CB3
85
DU
87
VSS
89
CK2
91
CK2#
93
VDD
95
CKE1
97
DU/A13
99
A12
101
A9
103
VSS
105
A7
107
A5
109
A3
111
A1
113
VDD
115
A10/AP
117
BA0
119
WE#
121
S0#
123
DU
125
VSS
127
DQ32
129
DQ33
131
VDD
133
DQS4
135
DQ34
137
VSS
139
DQ35
141
DQ40
143
VDD
145
DQ41
147
DQS5
149
VSS
151
DQ42
153
DQ43
155
VDD
157
VDD
159
VSS
161
VSS
163
DQ48
165
DQ49
167
VDD
169
DQS6
171
DQ50
173
VSS
175
DQ51
177
DQ56
179
VDD
181
DQ57
183
DQS7
185
VSS
187
DQ58
189
DQ59
191
VDD
193
SDA
195
SCL
197
VDD_SPD
199
VDD_ID
KLINK_5746-2-111
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY ORDISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC .
E
2
VREF
4
VSS
6
DQ4
8
DQ5
10
VDD
12
DM0
14
DQ6
16
VSS
18
DQ7
20
DQ12
22
VDD
24
DQ13
26
DM1
28
VSS
30
DQ14
32
DQ15
34
VDD
36
VDD
38
VSS
40
VSS
42
DQ20
44
DQ21
46
VDD
48
DM2
50
DQ22
52
VSS
54
DQ23
56
DQ28
58
VDD
60
DQ29
62
DM3
64
VSS
66
DQ30
68
DQ31
70
VDD
72
CB4
74
CB5
76
VSS
78
DM8
80
CB6
82
VDD
84
CB7
86
DU/RESET#
88
VSS
90
VSS
92
VDD
94
VDD
96
CKE0
98
DU/BA2
100
A11
102
A8
104
VSS
106
A6
108
A4
110
A2
112
A0
114
VDD
116
BA1
118
RAS#
120
CAS#
122
S1#
124
DU
126
VSS
128
DQ36
130
DQ37
132
VDD
134
DM4
136
DQ38
138
VSS
140
DQ39
142
DQ44
144
VDD
146
DQ45
148
DM5
150
VSS
152
DQ46
154
DQ47
156
VDD
158
CK1#
160
CK1
162
VSS
164
DQ52
166
DQ53
168
VDD
170
DM6
172
DQ54
174
VSS
176
DQ55
178
DQ60
180
VDD
182
DQ61
184
DM7
186
VSS
188
DQ62
190
DQ63
192
VDD
194
SA0
196
SA1
198
SA2
200
DU
E
+2.5V
DDR_DQ0 DDR_DQ1
DDR_DM0 DDR_DQ7
DDR_DQ6 DDR_DQ12
DDR_DQ9 DDR_DM1
DDR_DQ10 DDR_DQ11DDR_DQ14
DDR_DQ20 DDR_DQ17
DDR_DM2 DDR_DQ22
DDR_DQ19 DDR_DQ24
DDR_DQ28 DDR_DM3
DDR_DQ30 DDR_DQ26
DDR_CKE0
DDR_SMA11 DDR_SMA8
DDR_SMA6 DDR_SMA4 DDR_SMA2 DDR_SMA0
DDR_SBS1 DDR_SRAS# DDR_SCAS# DDR_ SCS#1
DDR_DQ37 DDR_DQ33
DDR_DM4 DDR_DQ38
DDR_DQ34 DDR_DQ41
DDR_DQ45 DDR_DM5
DDR_DQ46 DDR_DQ42
DDR_DQ48 DDR_DQ53
DDR_DM6DDR_DQS6 DDR_DQ49
DDR_DQ55 DDR_DQ60
DDR_DQ61 DDR_DM7
DDR_DQ59
F
F
1
C637
2
0.1U_0402_10V6K
+SDREF_DIMM0
DDR_CKE0 <9>
DDR_SCS# 1 <9>
DDR_CLK1# <9> DDR_CLK1 <9>
DDR_SBS0<9>
DDR_SBS1<9>
DDR_SRAS#<9>
DDR_SCAS#<9>
DDR_SWE#<9>
R523
R524
G
12
0_0402_5%
12
@0_0402_5%
+2.5V
12
12
+SDREF_DIMM
R525 @10K_0603_1%
R526 @10K_0603_1%
+SDREF
+SDREF_DIMM0
DDR_DQ[0..63]
DDR_DQS[0..7]
DDR_DM[0..7]
DDR_SMAA[6..12]
DDR_SMAA0
DDR_SMAA3
R168 10_0402_5%
R170 10_0402_5%
R171 10_0402_5%
R176 10_0402_5%
R177 10_0402_5%
R183 10_0402_5%
R160 10_0402_5%
R184 10_0402_5%
R188 10_0402_5%
12
12
12
12
12
12
12
12
12
Layout note
Place these resistor close by DIMM0, all trace length Max=1.4"
+1.25VS
DDR_CKE0 DDR_CKE1
DDR_SCS#1 DDR_SCS#0
DDR_SBS0
R158 10_0402_5%
DDR_SBS1
R159 10_0402_5%
DDR_SRAS#
R157 10_0402_5%
DDR_SCAS#
R152 10_0402_5%
DDR_SWE#
R153 10_0402_5%
Title
Size Document Number Re v
LA-1931
Date: Sheet
G
RP15
1 4 2 3
56_040 4_4P2R_5%
RP9
1 4 2 3
56_040 4_4P2R_5%
12
12
12
12
12
Compal Electronics , Inc .
DDR-SODIMM SLOT0
H
DDR_DQ[0..63] <12>
DDR_DQS[0..7] <12>
DDR_DM[0..7] <12>
DDR_SMAA[6..12] <12>
DDR_SMAA0 <12>
DDR_SMAA3 <12>
DDR_SMAA0DDR_SMA0
DDR_SMAA3DDR_SMA3
DDR_SMAA6DDR_SMA6
DDR_SMAA7DDR_SMA7
DDR_SMAA8DDR_SMA8
DDR_SMAA9DDR_SMA9
DDR_SMAA10DDR_SMA10
DDR_SMAA11DDR_SMA11
DDR_SMAA12DDR_SMA12
DDR_BS0 <12>
DDR_BS1 <12>
DDR_RAS# <12>
DDR_CAS# <12>
DDR_WE# <12>
of
11 47Monday, June 09, 2003
H
0.2
A
+1.25VS +1.25VS
RP98
DDR_DQ0
1 4
DDR_DQ1
2 3
56_0404_4P2R_5% RP99
DDR_DQ4
1 4
DDR_DQ5
2 3
56_0404_4P2R_5%
DDR_DM0 DDR_DQ7
DDR_DQS0 DDR_DQ3
DDR_DQ6 DDR_DQ12
DDR_DQ2 DDR_DQ8
DDR_DQ9 DDR_DM1
DDR_DQ13 DDR_DQS1
DDR_DQ15 DDR_DQ14
DDR_DQ10 DDR_DQ11
DDR_DQ18 DDR_DQ16
DDR_DQ20 DDR_DQ17
DDR_DQS2 DDR_DQ21
DDR_DM2 DDR_DQ22
DDR_DQ23 DDR_DQ25
DDR_DQ19 DDR_DQ24
RP93
1 4 2 3
56_0404_4P2R_5%
RP96
1 4 2 3
56_0404_4P2R_5%
RP90
1 4 2 3
56_0404_4P2R_5%
RP91
1 4 2 3
56_0404_4P2R_5%
RP87
1 4 2 3
56_0404_4P2R_5%
RP89
1 4 2 3
56_0404_4P2R_5%
RP85
1 4 2 3
56_0404_4P2R_5%
RP83
1 4 2 3
56_0404_4P2R_5%
RP79
1 4 2 3
56_0404_4P2R_5%
RP81
1 4 2 3
56_0404_4P2R_5%
RP76
1 4 2 3
56_0404_4P2R_5%
RP77
1 4 2 3
56_0404_4P2R_5%
RP72
1 4 2 3
56_0404_4P2R_5%
RP74
1 4 2 3
56_0404_4P2R_5%
1 1
2 2
3 3
Layout note
Place these resistor closely DIMM1, all trace length<=800mil
4 4
RP69
DDR_DQ31
14
DDR_DQS3
23
56_0404_4P2R_5%
RP71
DDR_DQ28
14
DDR_DM3
23
56_0404_4P2R_5%
RP66
DDR_DQ27
14
DDR_DQ29
23
56_0404_4P2R_5%
RP67
DDR_DQ30
14
DDR_DQ26
23
56_0404_4P2R_5%
RP57
DDR_DQ32
14
DDR_DQ36
23
56_0404_4P2R_5%
RP53
DDR_DQ37
14
DDR_DQ33
23
56_0404_4P2R_5%
RP48
DDR_DQS4
14
DDR_DQ39
23
56_0404_4P2R_5%
RP51
DDR_DM4
14
DDR_DQ38
23
56_0404_4P2R_5%
RP44
DDR_DQ35
14
DDR_DQ40
23
56_0404_4P2R_5%
RP46
DDR_DQ34
14
DDR_DQ41
23
56_0404_4P2R_5%
RP41
DDR_DQ44
14
DDR_DQS5 DDR_SMAB1
23
56_0404_4P2R_5%
RP42
DDR_DQ45
14
DDR_DM5
23
56_0404_4P2R_5%
RP37
DDR_DQ43
14
DDR_DQ47
23
56_0404_4P2R_5%
RP39
DDR_DQ46
14
DDR_DQ42
23
56_0404_4P2R_5%
RP33
DDR_DQ52
14
DDR_DQ50
23
56_0404_4P2R_5%
RP35
DDR_DQ48
14
DDR_DQ53
23
56_0404_4P2R_5%
RP31
DDR_DQS6
14
DDR_DQ51
23
56_0404_4P2R_5%
RP32
DDR_DM6
14
DDR_DQ49
23
56_0404_4P2R_5%
RP27
DDR_DQ54
14
DDR_DQ57
23
56_0404_4P2R_5%
RP29
DDR_DQ55
14
DDR_DQ60
23
56_0404_4P2R_5%
RP23
DDR_DQ56
14
DDR_DQS7
23
56_0404_4P2R_5%
RP20
DDR_DQ62
14
DDR_DQ63
23
56_0404_4P2R_5%
RP25
DDR_DQ61
14
DDR_DM7
23
56_0404_4P2R_5%
RP22
DDR_DQ58
14
DDR_DQ59
23
56_0404_4P2R_5%
DDR_DQS[0..7]
DDR_DQ[0..63]
DDR_DM[0..7]
DDR_SMA[1..2]
DDR_SMA[4..5]
DDR_SMAA[6..12]
DDR_SMAA0
DDR_SMAA3
DDR_SMAB1<9>
DDR_SMAB2<9>
DDR_SMAB4<9>
DDR_SMAB5<9>
B
DDR_DQS[0..7] <11>
DDR_DQ[0..63] <11>
DDR_DM[0..7] <11>
DDR_SMA[1..2] <9,11>
DDR_SMA[4..5] <9,11>
DDR_SMAA[6..12] <11>
DDR_SMAA0 <11>
DDR_SMAA3 <11>
DDR_SMAB1
DDR_SMAB2
DDR_SMAB4
DDR_SMAB5
C
+2.5V
DDR_DQ4 DDR_DQ5
DDR_DQS0 DDR_DQ3
DDR_DQ2 DDR_DQ8
DDR_DQ13 DDR_DQS1
DDR_DQ15 DDR_DQ14
DDR_CLK3<9> DDR_CLK3#<9>
DDR_DQ18 DDR_DQ16
DDR_DQS2 DDR_DQ21
DDR_DQ23 DDR_DQ25
DDR_DQ31 DDR_DQS3
DDR_DQ27 DDR_DQ29
DDR_CKE3 DDR_CKE2
DDR_SMAA12 DDR_SMAA9
DDR_SMAA7 DDR_SMAB5 DDR_SMAA3 DDR_SMAB1
DDR_SMAA10
DDR_BS0<11> DDR_WE#<11>
SMDATA<11,14,17>
SMCLK<11,14,17>
DDR_BS0 DDR_RAS#
DDR_SC S#2 DDR_CS#3
DDR_DQ32 DDR_DQ36
DDR_DQS4 DDR_DQ39
DDR_DQ35 DDR_DQ40
DDR_DQ44 DDR_DQS5
DDR_DQ43 DDR_DQ47
DDR_DQ52 DDR_DQ50
DDR_DQS6 DDR_DQ51
DDR_DQ54 DDR_DQ57
DDR_DQ56 DDR_DQS7
DDR_DQ62 DDR_DQ63
+3VS
JP20
1
VREF
3
VSS
5
DQ0
7
DQ1
9
VDD
11
DQS0
13
DQ2
15
VSS
17
DQ3
19
DQ8
21
VDD
23
DQ9
25
DQS1
27
VSS
29
DQ10
31
DQ11
33
VDD
35
CK0
37
CK0#
39
VSS
41
DQ16
43
DQ17
45
VDD
47
DQS2
49
DQ18
51
VSS
53
DQ19
55
DQ24
57
VDD
59
DQ25
61
DQS3
63
VSS
65
DQ26
67
DQ27
69
VDD
71
CB0
73
CB1
75
VSS
77
DQS8
79
CB2
81
VDD
83
CB3
85
DU
87
VSS
89
CK2
91
CK2#
93
VDD
95
CKE1
97
DU/A13
99
A12
101
A9
103
VSS
105
A7
107
A5
109
A3
111
A1
113
VDD
115
A10/AP
117
BA0
119
WE#
121
S0#
123
DU
125
VSS
127
DQ32
129
DQ33
131
VDD
133
DQS4
135
DQ34
137
VSS
139
DQ35
141
DQ40
143
VDD
145
DQ41
147
DQS5
149
VSS
151
DQ42
153
DQ43
155
VDD
157
VDD
159
VSS
161
VSS
163
DQ48
165
DQ49
167
VDD
169
DQS6
171
DQ50
173
VSS
175
DQ51
177
DQ56
179
VDD
181
DQ57
183
DQS7
185
VSS
187
DQ58
189
DQ59
191
VDD
193
SDA
195
SCL
197
VDD_SPD
199
VDD_ID
DU/RESET#
DDR-SODIMM_200_STD_H4.0
VREF
DQ12
DQ13
DQ14 DQ15
DQ20 DQ21
DQ22
DQ23 DQ28
DQ29
DQ30 DQ31
CKE0
DU/BA2
RAS# CAS#
DQ36 DQ37
DQ38
DQ39 DQ44
DQ45
DQ46 DQ47
CK1#
DQ52 DQ53
DQ54
DQ55 DQ60
DQ61
DQ62 DQ63
D
+2.5V
2 4
VSS
6
DQ4
8
DQ5
10
VDD
12
DM0
14
DQ6
16
VSS
18
DQ7
20 22
VDD
24 26
DM1
28
VSS
30 32 34
VDD
36
VDD
38
VSS
40
VSS
42 44 46
VDD
48
DM2
50 52
VSS
54 56 58
VDD
60 62
DM3
64
VSS
66 68 70
VDD
72
CB4
74
CB5
76
VSS
78
DM8
80
CB6
82
VDD
84
CB7
86 88
VSS
90
VSS
92
VDD
94
VDD
96 98 100
A11
102
A8
104
VSS
106
A6
108
A4
110
A2
112
A0
114
VDD
116
BA1
118 120 122
S1#
124
DU
126
VSS
128 130 132
VDD
134
DM4
136 138
VSS
140 142 144
VDD
146 148
DM5
150
VSS
152 154 156
VDD
158 160
CK1
162
VSS
164 166 168
VDD
170
DM6
172 174
VSS
176 178 180
VDD
182 184
DM7
186
VSS
188 190 192
VDD
194
SA0
196
SA1
198
SA2
200
DU
DDR_DQ0 DDR_DQ1
DDR_DM0 DDR_DQ7
DDR_DQ6 DDR_DQ12
DDR_DQ9 DDR_DM1
DDR_DQ10 DDR_DQ11
DDR_DQ20 DDR_DQ17
DDR_DM2 DDR_DQ22
DDR_DQ19 DDR_DQ24
DDR_DQ28 DDR_DM3
DDR_DQ30 DDR_DQ26
DDR_SMAA11 DDR_SMAA8
DDR_SMAA6 DDR_SMAB4 DDR_SMAB2 DDR_SMAA0
DDR_BS1
DDR_CAS#DDR_WE#
DDR_DQ37 DDR_DQ33
DDR_DM4 DDR_DQ38
DDR_DQ34 DDR_DQ41
DDR_DQ45 DDR_DM5
DDR_DQ46 DDR_DQ42
DDR_DQ48 DDR_DQ53
DDR_DM6 DDR_DQ49
DDR_DQ55 DDR_DQ60
DDR_DQ61 DDR_DM7
DDR_DQ58 DDR_DQ59
+3VS
1
2
DDR_CKE2 <9>DDR_CKE3<9>
DDR_BS1 <11> DDR_RAS# <11> DDR_CAS# <11> DDR_SCS# 3 <9>DDR_SCS# 2<9>
DDR_CLK4# <9> DDR_CLK4 <9>
12
R527 0_0402_5%
12
R528 @0_0402_5%
C227
0.1U_0402_10V6K
E
+SDREF_DIMM
+SDREF_DIMM0
+SDREF_DIMM0
+1.25VS
DDR_SMAA12
1 2
R182 56_0402_5%
RP64 56_0404_4P2R_5%
RP63 56_0404_4P2R_5%
RP60 56_0404_4P2R_5%
RP58 56_0404_4P2R_5%
R169 56_0402_5%
R167 56_0402_5%
RP59 56_0404_4P2R_5%
RP13 56_0404_4P2R_5%
RP61 56_0404_4P2R_5%
RP12 56_0404_4P2R_5%
RP55 56_0404_4P2R_5%
R389 56_0402_5%
1 2
DDR_CKE3 DDR_CKE2
DDR_SCS#2 DDR_SCS#3
DDR_SMAA11
14
DDR_SMAA9
23
DDR_SMAA7
14
DDR_SMAA8
23
DDR_SMAA6
14
DDR_SMAA3
23
DDR_SMAA10
14
DDR_SMAA0
23
12
12
14
DDR_SMAB2
23
DDR_SMA4
14
DDR_SMA5
23
DDR_SMAB4
14
DDR_SMAB5
23
DDR_WE#
14
DDR_BS0
23
DDR_RAS#
14
DDR_CAS#
23
DDR_BS1
1 4 2 3
56_040 4_4P2R_5%
1 4 2 3
56_040 4_4P2R_5%
Layout note
Place these resistor close by DIMM1, all trace length Max=0.8"
+2.5V
12
12
DDR_SMA1
DDR_SMA2
RP62
RP10
R529 @10K_0603_1%
R530 @10K_0603_1%
+1.25VS
DDR TOPOLOGY 1 FOR SMAA[0, 3, 6:12], SBA[1, 0], SRAS#, SCAS#, SWE#
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY ORDISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC .
C
D
Size Document Number Re v
Date: Sheet of
Compal Electronics , Inc .
DDR-SODIMM SLOT1
LA-1931
12 47Monday, June 09, 2003
E
0.2
A
Layout note :
Distribute as close as possible to DDR-SODIMM0.
+2.5V
B
C
Layout note :
Distribute as close as possible to DDR-SODIMM1.
+2.5V
D
E
C333 150U_D2_6.3VM
1
C82
0.1U_0402_10V6K
2
1
C193
0.1U_0402_10V6K
2
1 1
2 2
3 3
C334 150U_D2_6.3VM
2
1
C162
0.1U_0402_10V6K
2
1
+
150U_D2_6.3VM
2
+1.25VS
1
C431
0.1U_0402_10V6K
2
+1.25VS
1
C440
0.1U_0402_10V6K
2
+1.25VS
1
C617
0.1U_0402_10V6K
2
1
+
1
C135
0.1U_0402_10V6K
2
1
C151
0.1U_0402_10V6K
2
1
C228
+
C643 150U_D2_6.3VM
2
Layout note :
Place one cap close to every 2 pull up resistors termination to +1.25VS
1
C421
0.1U_0402_10V6K
2
1
C444
0.1U_0402_10V6K
2
1
C619
0.1U_0402_10V6K
2
1
C97
0.1U_0402_10V6K
2
1
C178
0.1U_0402_10V6K
2
1
C413
0.1U_0402_10V6K
2
1
C450
0.1U_0402_10V6K
2
1
C622
0.1U_0402_10V6K
2
1
C80
0.1U_0402_10V6K
2
1
C167
0.1U_0402_10V6K
2
1
C409
0.1U_0402_10V6K
2
1
C476
0.1U_0402_10V6K
2
1
C625
0.1U_0402_10V6K
2
1
C70
0.1U_0402_10V6K
2
1
C72
0.1U_0402_10V6K
2
1
C405
0.1U_0402_10V6K
2
1
C483
0.1U_0402_10V6K
2
1
C628
0.1U_0402_10V6K
2
1
C196
0.1U_0402_10V6K
2
1
C179
0.1U_0402_10V6K
2
1
C402
0.1U_0402_10V6K
2
1
C503
0.1U_0402_10V6K
2
1
C629
0.1U_0402_10V6K
2
1
C164
0.1U_0402_10V6K
2
1
C134
0.1U_0402_10V6K
2
1
C398
0.1U_0402_10V6K
2
1
C539
0.1U_0402_10V6K
2
1
C195
0.1U_0402_10V6K
2
1
C86
0.1U_0402_10V6K
2
1
C392
0.1U_0402_10V6K
2
1
C550
0.1U_0402_10V6K
2
1
C98
0.1U_0402_10V6K
2
1
C117
0.1U_0402_10V6K
2
1
C384
0.1U_0402_10V6K
2
1
C557
0.1U_0402_10V6K
2
+
1
C377
0.1U_0402_10V6K
2
1
C511
0.1U_0402_10V6K
2
1
2
1
C194
0.1U_0402_10V6K
2
1
C88
0.1U_ 0402_10V6K
2
1
C183
0.1U_ 0402_10V6K
2
1
C107
0.1U_0402_10V6K
2
1
C175
0.1U_0402_10V6K
2
1
C94
0.1U_ 0402_10V6K
2
1
C115
0.1U_ 0402_10V6K
2
1
C156
0.1U_0402_10V6K
2
1
C81
0.1U_0402_10V6K
2
1
C73
0.1U_0402_10V6K
2
1
C170
0.1U_0402_10V6K
2
1
C139
0.1U_0402_10V6K
2
1
C181
0.1U_0402_10V6K
2
1
C166
0.1U_0402_10V6K
2
1
C74
0.1U_0402_10V6K
2
+1.25VS
1
C141
0.1U_0402_10V6K
2
+1.25VS
1
C517
0.1U_0402_10V6K
2
+1.25VS
4 4
1
C590
0.1U_0402_10V6K
2
1
C160
0.1U_0402_10V6K
2
1
C350
0.1U_0402_10V6K
2
1
C354
0.1U_0402_10V6K
2
A
1
C142
0.1U_0402_10V6K
2
1
C360
0.1U_0402_10V6K
2
1
C603
0.1U_0402_10V6K
2
1
C155
0.1U_0402_10V6K
2
1
C526
0.1U_0402_10V6K
2
1
C596
0.1U_0402_10V6K
2
1
C464
0.1U_0402_10V6K
2
1
C576
0.1U_0402_10V6K
2
1
C352
0.1U_0402_10V6K
2
1
C566
0.1U_0402_10V6K
2
1
C356
0.1U_0402_10V6K
2
1
C607
0.1U_0402_10V6K
2
B
1
C367
0.1U_0402_10V6K
2
1
C615
0.1U_0402_10V6K
2
1
C498
0.1U_0402_10V6K
2
1
C584
0.1U_0402_10V6K
2
1
C627
0.1U_0402_10V6K
2
1
C355
0.1U_0402_10V6K
2
1
C366
0.1U_0402_10V6K
2
1
C616
0.1U_0402_10V6K
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY ORDISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC .
C
D
Title
Size Document Number Re v
Date: Sheet
Compal Electronics , Inc .
DDR SODIMMD ecoupling
LA-1931
of
13 47Monday, June 09, 2003
E
0.2
A
B
C
D
E
F
G
H
1 1
CPU Frequency Select Table (Based on H_BSEL0)
*
SEL[2:0] CK-408 Speed
001
011
PM_SLP_S3#<18,32>
PM_SLP_S1#<18,32>
2 2
VGATE<18,44>
+CPU_CORE +3VS
3 3
1
IN1
2
IN2
1 2
R445 10K_0402_5%
1 2
R463 @56_0402_5%
100 MHZ
133 MHZ
+3V
5
U21
P
4
1 2
O
R128 0_0402_5%
G
SN74AHC1G08HDCK_TSSOP5
3
1 2
R129 @0_0402_5%
Q13
2
B
3
E
2SC2411K_SC59
CLK_PWD#
1
C
R437 10K_0402_5%
CLK_VCH<8>
CLK_ICH_48M<18>
CLK_MCH_DISPLAY<8>
CLK_ICH_14M<18>
CLK_SIO_14M<31>
H_BSEL0<5>
12
VTT_PWRGD#
R83
20K_0402_5%
1
C57 @10P_0402_50V8K
2
+3VS
+3VS
+3VS
12
12
R95 0_0402_5%
L7 BLM21A601SPT_0805
1 2
4.7U_0805_10V4Z
R94 20K_0402_5%
12
PM_STPPCI#<18>
PM_STPCPU#<18,44>
+3VS
SMDATA<11,12,17>
SMCLK<11,12,17>
R93 33_0402_5%
R75 475 _0402_1%
R102 33_0402_5%
R103 33_0402_5%
R105 33_0402_5%
R106 33_0402_5%
1
C58 @10P_0402_50V8K
2
H_SEL0
R76 @1K_0603_1%
1 2
1 2
1 2
1 2
1 2
1 2
+3VS
+3V_48M
1
C76
2
C96 @10P_0402_50V8K
1 2
1 2
C101
1 2
R85 1K_0402_5%
1 2
@10P_0402_50V8K
VTT_PWRGD#
R74
10K_0402_5%
12
XTALIN
12
14.3 1818MHZ_20P
XTALOUT
CLK_PWD#
CLK_VCH66
ICH_48M
MCH _DISPLAY
ICH_14M
L6
KC FBM-L11-201209-221LMAT_0805
1 2
1
C68
0.1U_ 0402_16V4Z
2
U17
2
X2
XTAL_IN
3
XTAL_OUT
54
SEL0
55
SEL1
40
SEL2
25
PWR_DWN#
34
PCI_STOP#
53
CPU_STOP#
28
VTT_PWRGD#
43
MULT0
29
SDATA
30
SCLK
33
3V66_0
35
3V66_1/VCH_CLK
42
IREF
39
48MHZ_USB
38
48MHZ_DOT
56
REF
+3V_CLK
1
37
14
32
VDD_REF
VDD_PCI_08VDD_PCI_1
VDD_48MHZ
VDD_3V66_019VDD_3V66_1
GND_REF4GND_PCI_09GND_PCI_115GND_3V66_020GND_3V66_131GND_48MHZ36GND_IREF41GND_CPU
1
C65 10U_1206_10V4Z
2
50
VDDA
VDD_CPU_046VDD_CPU_1
VSSA
CPUCLKT2
CPU_CLKC2
CPUCLKT1
CPUCLKC1
CPUCLKT0
CPUCLKC0
3V66_5
3V66_4 3V66_3 3V66_2
PCICLK_F2 PCICLK_F1 PCICLK_F0
PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0
ICS950 810CG_TSSOP56
47
1
C362
0.1U_0402_16V4Z
2
26
0.1U_0402_16V4Z
27
CPU_BCLK
45
CPU_BCLK#
44
MCH_BCLK
49
MCH_BCLK#
48
CPU_ITP
52
CPU_ITP#
51
24
23
MCH_66M
22
ICH_66M
21
PCI_ICH
7 6 5
18
PCI_1394
17
PCI_LAN
16
PCI_PCM
13
PCI_MINI
12
PCI_SIO
11
PCI_LPC
10
1
C361
0.1U_0402_16V4Z
2
+3V_VDD
1
1
C90
C363
2
2
0.1U_0402_16V4Z
1 2
R100 33_0402_1%
1 2
R101 33_0402_1%
1 2
R98 33_0402_1%
1 2
R99 33_0402_1%
1 2
R96 33_0402_1%
1 2
R97 33_0402_1%
R125 33_040 2_5% R124 33_040 2_5%
R117 33_0402_5%
R123 33_040 2_5% R122 33_040 2_5% R121 33_040 2_5% R120 33_040 2_5% R119 33_040 2_5% R118 33_040 2_5%
1
C63
2
0.1U_0402_16V4Z
1 2 1 2
1 2
1 2 1 2 1 2 1 2 1 2 1 2
@10P_0402_50V8K
1
C364
0.1U_0402_16V4Z
2
BLM21A601SPT_0805 L8
1 2
1
C91 10U_1 206_10V4Z
2
R90 49.9_0402_1%
1 2 1 2
R91 49.9_0402_1%
R88 49.9_0402_1%
1 2 1 2
R89 49.9_0402_1%
R86 49.9_0402_1%
1 2 1 2
R87 49.9_0402_1%
1
C372
2
1
C62
0.1U_0402_16V4Z
2
+3VS
CLK_CPU_BCLK <4>
CLK_CPU_BCLK# <4>
CLK_MCH_BCLK <7>
CLK_M CH_BCLK# <7>
CLK_CPU_ITP <5>
CLK_CPU_ITP# <5>
1
C371 @10P_0402_50V8K
2
1
C60
0.1U_ 0402_16V4Z
2
CLK_MCH_66M <8> CLK_ICH_66M <17>
CLK_PCI_ICH <17>
CLK_PCI_1394 <20> CLK_PCI_LAN <23> CLK_PCI_CB <21> CLK_PCI_M INI <25> CLK_PCI_SIO <31> CLK_LPC_EC <32>
4 4
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
C
D
MAY BE USED BY ORDISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC .
E
F
Size Document Number Re v
Date: Sheet of
Compal Electronics , Inc .
LA-1931
G
Clock Gener ator
14 47Monday, June 09, 2003
H
0.2
A
B
C
D
E
F
G
H
CH-7011A
DVOC_TV_D[0..11]<8>
1 1
2N7002_SOT23
Q29
D
S
+3VS
12
R282
2N7002_SOT23
G
2
12
13
D
S
13
G
12
Q27
2
12
R36
10K_0402_5%
R34
10K_0402_5%
+3VS
+3VS
@10K_0402_5%
I2C Address = 1110110X
MI2CDATA<8>
MI2CCLK<8>
R309
1.5K_0603_5%
2 2
4.7K_0402_5%
R47
DVOC_TV_D[0..11]
DVOBC_CLKINT<8>
12
R45
330_0402_5%
1 2
TV_CLK#<8>
TV_CLK<8>
TV_HSYN C<8>
TV_VSYNC<8>
PCIRST#<8,17,20,21,22,23,25,26,31,32>
0.1U_0402_16V4Z
R306 0_0603_5%
1 2
With Wide & Short Trace
R289
140_0402_5%
1 2
+1.5VS
R51
10K_0402_1%
1
C28
2
DVOC_TV_D11 DVOC_TV_D10 DVOC_TV_D9 DVOC_TV_D8 DVOC_TV_D7 DVOC_TV_D6 DVOC_TV_D5 DVOC_TV_D4 DVOC_TV_D3 DVOC_TV_D2 DVOC_TV_D1 DVOC_TV_D0
12
12
R54
10K_0402_1%
GPIO1 GPIO0
U5
50
D11
51
D10
52
D9
53
D8
54
D7
55
D6
58
D5
59
D4
60
D3
61
D2
62
D1
63
D0
56
XCLK*
57
XCLK
2
NC
46
Pout/DET#
4
H
5
V
13
RESET*
14
SD
15
SC
7
GPIO1
8
GPIO0
10
AS
35
ISET
19
NC
3
VREF
CH7011A
C22
22P_0402_5 0V8J
NC21NC22NC24NC25NC27NC28NC30NC
XI/FIN
42
Y1
1 2
14.318MHZ
1
2
31
C/H Sync
CVBS
C/R/V
CVBS/B/U
DVDD0 DVDD1 DVDD2
DGND0 DGND1 DGND2
DVDDV
AVDD0
AVDD1 AGND0 AGND1 AGND2
GND0 GND1
XO
43
1
C38
22P_0402_5 0V8J
2
BCO
VDD
9
NC
47
48
36
LUMA
37
Y/G
CRMA
38
COMPS
39
1 12 49
6 11 64
45
+1.5VS
23
NC
29
NC
20
NC
26
NC
32
NC
18 44 16 17 41 33 34 40
R293 75_0402_5%
1 2
1
C35
0.1U_0402_16V4Z
2
1
C311
0.1U_0402_16V4Z
2
1
C293
0.1U_0402_16V4Z
2
1
C29
0.1U_0402_16V4Z
2
1
C288
0.1U_0402_16V4Z
2
+3VS_ 7011_VDD
1
C295 22U_1206_16V4Z_V1
2
+3VS_ 7011_AVDD
R299
0_0603_5%
GPIO1
1
C305
0.1U_0402_16V4Z
2
+3VS_7011_DVDD
1
C23
0.1U_0402_16V4Z
2
1 2
1
C294
22U_1206_16V4Z_V1
2
+3VS
1
C36
22U_1 206_16V4Z_V1
2
R298 0_0603_5%
+3VS
12
R300
@10K_0402_5%
GPIO0
12
R303
330_0402_5%
R63 0_0603_5%
1 2
+3VS
Pull High: Default PAL Pull Low: Default NTSC ( For Power on default )
+3VS
TV-OUT CONN.
3 3
V-PORT-0603-220 M-V05_0603
C8 @33P_0402_50V8J
1 2
LUMA
CRMA COMPS
R305 75_0402_1%
12
R25 75_0402_1%
12
R24 75_0402_1%
D
1
C13
100P_0402_50V8K
2
12
4 4
A
B
C
L3 FBM-11-160808-121-T_0603
1 2
C9 @33P_0402_50V8J
1 2
L4 FBM-11-160808-121-T_0603
1 2
1
C12
100P_0402_50V8K
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY ORDISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC .
D7
2 1
1
C7
270P_0402_25V8K
2
1
C10
270P_0402_25V8K
2
E
D6
V-PORT-0603-220 M-V05_0603
2 1
JP14
1
1
2
2
3
3
4
4
SUYIN_030008FR004T100ZL
F
Compal Electronics, Ltd.
Title
CH-7011& TV-CO NN.
Size Document Number Re v
Custom
LA-1931
Date: Sheet
G
15 47Monday, June 09, 2003
of
H
0.2
A
1 1
3.3P_0402_50V8C
INTCRT_R<8>
INTCRT_G<8>
INTCRT_B<8>
+5VS
1
5
P
4
INTCRT_HSYNC<8>
2 2
INTCR T_VSYNC<8>
OE#
A2Y
G
U1
3
SN74AH CT1G125GW_SOT353-5
R28
1K_0402_5%
1 2
5
1
P
4
OE#
A2Y
G
U2
3
SN74AH CT1G125GW_SOT353-5
C277
R276
75_0402_1%
B
1
3.3P_0402_50V8C
2
12
75_0402_1%
C278
R277
HSYNC
VSYNC
V-PORT-0603-220 M-V05_0603
1
1
C279
3.3P_0402_50V8C
2
2
1 2
1 2
1 2
12
12
R278
75_0402_1%
V-PORT-0603-220 M-V05_0603
L22 FCM2012C-800_0805
L21 FCM2012C-800_0805
L20 FCM2012C-800_0805
D24
CRT_R
CRT_G
CRT_B
1
C262 8P_0402_50V8K
2
CHB1608B121_0603
CHB1608B121_0603
+5VS
D23
2 1
V-PORT-0603-220 M-V05_0603
1
2
1 2
1 2
27P_0402_5 0V8J
C
2 1
C261 8P_0402_50V8K
L1
L2
D9
2 1
CH491D_SOT23
1
C3
2
+R_CRT_VCC
1A_6VDC_MINISMDC110
0.1U_0402_16V4Z
D22
2 1
1
C260 8P_0402_50V8K
2
CRT_HSYNC
CRT_VSYNC
1
C4 27P_0402_50V8J
2
100P_0402_5 0V8J
F1
R11
2.2K_0402_5%
21
1
C6
2
1
C259
2
100P_0402_5 0V8J
+CRT_VCC
12
1
C2
2
12
R17
2.2K_0402_5%
+CRT_VCC
2N7002_SOT23
DDC_DATA
DDC_CLK
1
C5 100P_0402_50V8J
2
D
+3VS
12
R29
2.2K_0402_5%
Q1
2
G
1 3
D
S
2
G
Q2
1 3
D
JP12
6
11
1 7
12
2 8
13
CRT Conn ector
3 9
14
4 10 15
5
SUYIN_070549MR015S200ZU
+3VS
R18 10K_0402_5%
1 2
S
2N7002_SOT23
R27 10K_0402_5%
1 2
E
INTDDCDA <8>
INTDDCCK <8>
D
Protect for EC
DAC_BRIG<32>
INVT_PWM<32>
Title
Size Document Number Re v
Custom
Date: Sheet
+3VALW
D42 RB751V
R519
1 2
1K_0402_5%
R520
1 2
1K_0402_5%
R521
1 2
1K_0402_5%
BRIG
PWM
DISP_OFF#DI SPOFF#
D43
2 1
RB751V
2 1
Compal Electronics, Ltd.
CRT& LVDS CONN.
LA-1931
16 47Monday, June 09, 2003
E
D44 RB751V
2 1
0.2
of
+3VS
12
R290
4.7K_0402_5%
+LCDVDD
R304
Q30
12
10K_0402_5%
13
D
S
ENVDD
A
R312
2
G
D30
RB751V
+5V
2
1 2
1
O
21
DTC124EK_SC59
R314
1 2
47K_0603_5%
Q31 DTC124EK_SC59
G3I
Q32
DISPOF F#
+12VALW
R317
100K_0603_5%
1 2
1
O
G
3I2
2
C296
1000P_0402_50V7K
1
12
R310
200K_0603_5%
1
C318
1000P_0603_50V7K
2
2
B
+3V
1
D
Q28 SI2302DS_SOT23
S3G
1
C302
0.1U_0402_16V7K
2
1
C301
4.7U_1206_16V6K
2
+LCDVDD
1
C303
4.7U_1206_16V6K
2
3 3
4 4
BKOFF#<3 2>
100_0603_5%
2N7002_SOT23
ENVDD<8>
C290
0.1U_0603_50V4Z
B+
1
1
C282
10U_1210_35V4Z
2
2
R301
@0_0402_5%
+3VS
RP18
PID0 PID1
18 27
PID2 PID3
36
PID3
45
10K_1206_ 8P4R_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY ORDISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC .
C
B+
L24 CH B2012U170_0805
1 2
1 2
L23
CHB2012U170_0805
+LCDVDD
LCD_B0+<8>
LCD_B0-<8>
LCD_B1+<8>
LCD_B1-<8>
LCD_B2+<8>
LCD_B2-<8>
LCD_BCLK+<8>
LCD_BCLK-<8>
PID0<31> PID1<31> PID2<31> PID3<31>
LCD_A0+<8>
LCD_A0-<8>
LCD_A1+<8>
LCD_A1-<8>
LCD_A2+<8>
LCD_A2-<8>
LCD_ACLK+<8>
LCD_ACLK-<8>
BRIG PWM DISP_OFF#
PID0
PID2PID1
IB+
JP1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
IPEX_20143-030E
A
+3VS +3VS
PCI_FRAME# PCI_TRDY# PCI_STOP# PCI_ SERR#
1 1
PCI_REQ#3 PCI_REQB# PCI_REQ#4 PCI_REQ# 1 PCI_REQA# PCI_REQ#0
PIRQD# PIRQC# PIRQB# PIRQA#
+3VS
R436 8.2 K_0402_5%
2 2
3 3
R461 8.2 K_0402_5%
R407 @ 8.2K_0402_5%
R372 @ 100_0402_5%
Note: In ICH4, PCI_GNT[0..4] don't need external pullup
1 2 3 4 5
+3VS +3VS
1 2 3 4 5
+3VS
1 2 3 4 5
12
12
12
12
CLK_PCI_ICH<14>
HUB I/F REF VOLTAGE
C216
0.1U_0402_16V4Z
4 4
C218
0.1U_0402_16V4Z
RP8
10 9 8 7
CLK_ PCI_ICH
@22_0402_5%
@10P_0402_25V8K
80.6_0402_1%
1
51.1_0603_1%
2
1
40.2_0603_1%
2
RP14
RP50
6
10 9 8 7 6
10 9 8 7 6
8.2K_ 1206_10P8R_5%
8.2K_ 1206_10P8R_5%
8.2K_ 1206_10P8R_5%
+3VS
INT_IRQ14
INT_IRQ15
PCIRST#
PCI_PAR
R406
C451
+1.5VS
R213
R217
R219
PCI_LOCK#
PCI_DEVSEL#
PCI_ PERR# PCI_IRDY#
PCI_REQ#2
SERIRQ
PIRQE#
PIRQF# PIRQH# PIRQG#
12
1
2
1 2
1 2
1 2
Between divider and ICH
+ICH_HI_ VSWING
1
C215
0.01U_0402_25V7Z
2
+IC H_HI_VREF
1
C217
0.01U_0402_25V7Z
2
PCI_AD[0..31]<20,21,23,25>
PCI_AD[0..31]
PCI_C/BE#0<2 0,21,23,25> PCI_C/BE#1<2 0,21,23,25> PCI_C/BE#2<2 0,21,23,25> PCI_C/BE#3<2 0,21,23,25>
PCI_REQ#0<20> PCI_REQ#1<25> PCI_REQ#2<21> PCI_REQ#3<23>
PCI_GNT#0<20> PCI_GNT#1<25> PCI_GNT#2<21> PCI_GNT#3<23>
PCI_FRAME#<20,21,23,25>
PCI_DEVSEL#<20,21,23,25>
PCI_IRDY#<20,21,23,25>
PCI_PERR #<20,21,23,25>
ICH_WAKE _UP#<32>
PCI_SERR#<21,23,25>
PCI_STOP#<20,21,23,25> PCI_TRDY#<20,21,23,25>
PIDERST#<26> SIDERST#<26>
PCI_PAR<2 0,21,23,25>
PCIRST#<8,15,20,21,22,23,25,26,31,32>
Place this schematic close to ICH
A
B
PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31
C/BE#0 C/BE#1 C/BE#2 C/BE#3
PCI_REQ#0 PCI_REQ#1 PCI_REQ#2 PCI_REQ#3 PCI_REQ#4
PCI_GNT#0 PCI_GNT#1 PCI_GNT#2 PCI_GNT#3
FRAME# DEVSEL# IRDY#
PERR# PCI_LOCK#
PCIRST# SERR# STOP# TRDY#
PCI_REQA# PCI_REQB# GNTA#
B
U25A
H5
AD0
J3
AD1
H3
AD2
K1
AD3
G5
AD4
J4
AD5
H4
AD6
J5
AD7
K2
AD8
G2
AD9
L1
AD10
G4
AD11
L2
AD12
H2
AD13
L3
AD14
F5
AD15
F4
AD16
N1
AD17
E5
AD18
N2
AD19
E3
AD20
N3
AD21
E4
AD22
M5
AD23
E2
AD24
P1
AD25
E1
AD26
P2
AD27
D3
AD28
R1
AD29
D2
AD30
P4
AD31
J2
C/BE#0
K4
C/BE#1
M4
C/BE#2
N4
C/BE#3
B1
REQ#0
A2
REQ#1
B3
REQ#2
C7
REQ#3
B6
REQ#4
C1
GNT#0
E6
GNT#1
A7
GNT#2
B7
GNT#3
D6
GNT#4
P5
PCICLK
F1
FRAME#
M3
DEVSEL#
L5
IRDY#
G1
PAR
L4
PERR#
M2
LOCK#
W2
PME#
U5
PCIRST#
K5
SERR#
F3
STOP#
F2
TRDY#
B5
REQA#/GPI0
A6
REQB#/GPI1/REQ5#
E8
GNTA#/GPO16
C5
GNTB#/GPO17/GNT5#
ICH4-M
PIRQA# PIRQB# PIRQC# PIRQD#
PIRQH# PIRQG# PIRQF# PIRQE#
C
+RTCVCC
R1494.7K_0402_5% R1454.7K_0402_5%
Place R481 close to pinAA21
H_PD[0..10] <7>
R218
48.7_06 03_1%
+3VALW
R481 56_0402_1%
R378
ICH4-M
PCI I/F
R393 0_0402_5%
1 2
RP11
1 8 2 7 3 6 4 5
@0_1206_8 P4R_5%
RP52
1 8 2 7 3 6 4 5
0_1206_8P4R_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY ORDISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC .
SM I/F
SMB_ALERT#/GPI11
CPU I/F
CPU_PWRGOOD
HUB I/F
HUB_VSWING
PIRQE#/GPI2 PIRQF#/GPI3
PIRQG#/GPI4
PIRQH#/GPI5
Interrupt I/F
EEPROM I/F
LAN I/F
LAN_RSTSYNC
INTRUDER#
SMLINK0 SMLINK1
SMB_CLK
SMB_DATA
A20GATE
A20M#
DPSLP#
FERR#
IGNNE#
STPCLK#
CLK66
HI_STB
HI_STB#
HICOMP
HUB_VREF
APICCLK
APICD0 APICD1 PIRQA# PIRQB# PIRQC# PIRQD#
IRQ14 IRQ15
SERIRQ
EE_CS
EE_IN
EE_OUT
EE_SHCLK
LAN_RXD0 LAN_RXD1 LAN_RXD2 LAN_TXD0 LAN_TXD1 LAN_TXD2
LAN_CLK
LAN_RST#
INIT# INTR
NMI
RCIN#
SLP# SMI#
HI0 HI1 HI2 HI3 HI4 HI5 HI6 HI7 HI8
HI9 HI10 HI11
PIRQA#_PCM
PIRQA#/E# PIRQB#/F#/ D# PIRQC#/G# PIRQD#/H#
PIRQD#/H# PIRQC#/G#
PIRQB#/F# /D#
PIRQA#/E#
W6 AC3 AB1 AC4 AB4 AA5
Y22 AB23 U23 AA21 W21 V22 AB22 V21 Y23 U22 U21 W23 V23
L19 L20 M19 M21 P19 R19 T20 R20 P23 L22 N22 K21
T21
P21 N20
R23 M23 R22
J19 H19 K20 D5 C2 B4 A3 C8 D7 C3 C4 AC13 AA19 J22
D10 D11 A8 C12
A10 A9 A11 B10 C10 A12 C11 B11 Y5
CLK_ICH_66M
HUB_PSTRB HUB_PSTRB#
SM_INTRUDER# SMLINK0 SMLINK1 SMB_CLK SMB_DATA ICH_ACIN
H_PD0 H_PD1 H_PD2 H_PD3 H_PD4 H_PD5 H_PD6 H_PD7 H_PD8 H_PD9 H_PD10
HUB_RCOM P_ICH +IC H_HI_VREF +ICH_HI_ VSWING
APICCLK APICD0 APICD1 PIRQA# PIRQB# PIRQC# PIRQD# PIRQE# PIRQF# PIRQG# PIRQH# IRQ14 IRQ15 SERIRQ
1 2
@1K_0402_5%
1 2
10K_0402_5%
100K_0402_5%
1 2
H_FERR#
H_PD[0..10]
R480 56_ 0402_1%
1 2
HUB_PSTRB <7> HUB_PSTRB# <7>
Place R218 within 0.5" of ICH4 ball R23, use thick trace
INT_IRQ14 <26> INT_IRQ15 <26> SERIRQ <21,31,32>
R185
R408
PIRQA#_PCM <21>
PIRQH#_MI NI_2 <25> PIRQG#_MINI <25> PIRQF#_LAN <23> PIRQE#_1394 <20>
C
1 2 1 2
GATEA20 <32> H_A20M# <5> H_DPSLP# <5,8>
H_IGNNE# <5> H_INIT# <5> H_INTR <5> H_NMI <5> H_PWRGD <5> KBRST# <32> H_SLP# <5> H_SMI# <5> H_STPCLK# <5>
1 2
1 2
+1.5VS
APICCLK APICD0 APICD1
1394
CardBus
LAN
MINIPCI
D
+3VALW
12
R154 100K_0402_5%
ACI N <32,34,38>
+CPU_CORE
H_FERR# <5>
R478
@22_0402_5%
C595
@10P_0402_25V8K
R474 10K_0402_5%
1 2
Topology 1:
Pop : RP52 and R393
Depop : RP11
Trace: PIRQE#_1394 Use IRQE
Trace:PIRQA# Use IRQA
Trace:PIRQF#_LAN Use IRQF
Trace:PIRQG# Use IRQG
Title
Size Document Number Re v
Custom
Date: Sheet
SMB_CLK
1 2
R398 4.7K_0402_5%
SMB_DATA
1 2
R397 4.7K_0402_5%
SMCLK
1 2
R517 4.7K_0402_5%
SMDATA
1 2
R518 4.7K_0402_5%
+3VS
G
2
SMCLK
SMCLK<11,12,14>
SMDATA<11,12,14>
R473 10K_0402_5%
1 2
12
1
2
S
Q40 2N7002_SOT23
G
SMDATA
S
2N7002_SOT23
CLK_ICH_66M <14>
R467 0_0402_5%
1 2
2
Q41
Compal Electronics, Ltd.
ICH4-M(1/2)
LA-1931
D
13
D
13
D
SMB_CLK
SMB_DATA
17 47Monday, June 09, 2003
+3VALW
+3VS
0.2
of
A
+3VALW
1 2
R146 10K_0402_5%
1 2
R138 10K_0402_5%
1 2
R172 100K_0402_5%
R179 100K_0402_5%
R482 100K_0402_5%
PM_SLP_S5#<32>
EC_THERM#<32>
@22_0402_5%
@10P_0402_25V8K
R139 10K_0402_5%
74AHC 1G08
RB751V_SOD323
+3V
R200 10K_0402_5%
R439 10K_0402_5%
R447 10K_0402_5%
R191
C165
1 1
2 2
3 3
4 4
PM_BATLOW#
EC_SWI#
SYSRST#
SYS_PW ROK
12
EC_RSMRST#
12
PM_DPRSLPVR
12
+3VALW
5
1
4
2
U23
3
D16
21
BTO Base on USB JP28
1 2
R198 @10K_0402_5%
1 2
1 2
1 2
12
@22_0402_5%
1
@10P_0402_25V8K
2
SLP_S4#
SLP_S5#
+3VS
R140 10K_0402_5%
12
ATF_INT#
OVCUR#3
OVCUR#0
OVCUR#1
OVCUR#5
CLK_ICH_14M CLK_ICH_48MIAC_BITCLK
12
R214
1
C220
2
1 2
R147 10K_0402_5%
1 2
R142 10K_0402_5%
R462 10K_0402_5%
+3VS
R469
@22_0402_5%
C602
@10P_0402_25V8K
CLKRUN#
AGP_BUSY#
V_GATE
12
R placed within 500 mils of the ICH4-M. Trace Avoid routing next to clock pin.
12
1
2
AGP_BUSY#<8>
PM_CLKRUN#<21, 23,25,31,32>
PM_DPRSLPVR<44>
PBTN_OUT#<32>
SYS_PW ROK<8,35>
EC_SWI#<32>
EC_RSMRST#<32>
PM_SLP_S1#<14,32>
PM_SLP_S3#<14,32>
PM_STPCPU#<14,44>
PM_STPPCI#<14>
RTCCLK<8>
PM_CPUPERF#<5>
VGATE<14,44>
IAC_BITCLK<28>
IAC_RST#<28> IAC_SDATAI0<28> IAC_SDATAI1<28>
IAC_SDATAO<28> IAC_SYNC<28>
LPC_AD0<31,32> LPC_AD1<31,32>
LPC_AD2<31,32> LPC_AD3<31,32>
LPC_DRQ#0<32>
LPC_DRQ#1<31>
LPC_F RAME#<31,32>
USBP2+<27>
USBP2-<27>
USBP3+<27>
USBP3-<27>
USBP4+<27>
USBP4-<27>
OVCUR#2<2 7> OVCUR#3<2 7> OVCUR#4<2 7>
B
AGP_BUSY# SYSRST# PM_BATLOW#
CLKRUN# PM_DPRSLPVR
SYS_PW ROK EC_SWI# EC_RSMRST#
SLP_S4# SLP_S5#
RTCCLK
ATF_INT#
R472 0_0402_5%
R457 0_0402_5%
IAC_BITCLK
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_DRQ#0 LPC_DRQ#1
OVCUR#0 OVCUR#1 OVCUR#2 OVCUR#3 OVCUR#4 OVCUR#5
USB_RBIAS
R226
22.6_0603_1%
1 2
CPUPERF#
12
V_GATE
12
U25B
R2
AGPBUSY#
Y3
SYSRST#
AB2
BATLOW#
T3
C3_STAT#
AC2
CLKRUN#
V20
DPRSLPVR
AA1
PWRBTN#
AB6
PWROK
Y1
RI#
AA6
RSMRST#
W18
SLP_S1#
Y4
SLP_S3#
Y2
SLP_S4#
AA2
SLP_S5#
W19
STP_CPU#
Y21
STP_PCI#
AA4
SUS_CLK
AB3
SUS_STAT#/LPCPD#
V1
THRM#
J21
SSMUXSEL
Y20
CPUPERF#
V19
VGATE/VRMPWRGD
B8
AC_BITCLK
C13
AC_RST#
D13
AC_SDATAIN0
A13
AC_SDATAIN1
B13
AC_SDATAIN2
D9
AC_SDATAOUT
C9
AC_SYNC
T2
LPC_AD0
R4
LPC_AD1
T4
LPC_AD2
U2
LPC_AD3
U3
LPC_DRQ#0
U4
LPC_DRQ#1
T5
LPC_FRAME#
C20
USBP0+
D20
USBP0-
A21
USBP1+
B21
USBP1-
C18
USBP2+
D18
USBP2-
A19
USBP3+
B19
USBP3-
C16
USBP4+
D16
USBP4-
A17
USBP5+
B17
USBP5-
B15
OC#0
C14
OC#1
A15
OC#2
B14
OC#3
A14
OC#4
D14
OC#5
A23
USB_RBIAS
B23
USB_RBIAS#
J20
GPIO32
G22
GPIO33
F20
GPIO34
G20
GPIO35
F21
GPIO36
H20
GPIO37
F23
GPIO38
H22
GPIO39
G23
GPIO40
H21
GPIO41
F22
GPIO42
E23
GPIO43
ICH4-M
ICH4-M
PM
IST
AC97 I/F
LPC I/F
USB I/F
GPIO
GPIO
IDE I/F
CLOCK
MISC
THRMTRIP#
GPI7
GPI8 GPI12 GPI13
GPIO25 GPIO27 GPIO28
PDA0 PDA1
PDA2 PDCS1# PDCS3#
PDDREQ
PDDACK#
PDIOR#
PDIOW#
PIORDY
PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 PDD8
PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15
SDA0 SDA1
SDA2 SDCS1# SDCS3#
SDDREQ
SDDACK#
SDIOR#
SDIOW#
SIORDY
SDD0 SDD1 SDD2 SDD3 SDD4 SDD5 SDD6 SDD7 SDD8
SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15
CLK14 CLK48
RTCRST#
VBIAS
RTCX1
RTCX2
SPKR
C
+3VS
12
R143
10K_0402_5%
R3 V4
SCI#
V5 W3 V2 W1 W4
PDA0
AA13
PDA1
AB13
PDA2
W13
PDCS1#
Y13
PDCS3#
AB14
PDDREQ
AA11
PDDACK#
Y12
PDIOR#
AC12
PDIOW#
W12
PDIORDY
AB12
IDE_PDD0
AB11
IDE_PDD1
AC11
IDE_PDD2
Y10
IDE_PDD3
AA10
IDE_PDD4
AA7
IDE_PDD5
AB8
IDE_PDD6
Y8
IDE_PDD7
AA8
IDE_PDD8
AB9
IDE_PDD9
Y9
IDE_ PDD10
AC9
IDE_ PDD11
W9
IDE_ PDD12
AB10
IDE_ PDD13
W10
IDE_ PDD14
W11
IDE_ PDD15
Y11
SDA0
AA20
SDA1
AC20
SDA2
AC21
SDCS1#
AB21
SDCS3#
AC22
SDDREQ
AB18
SDDACK#
AB19
SDIOR#
Y18
SDIOW#
AA18
SDIORDY
AC19
IDE_SDD0
W17
IDE_SDD1
AB17
IDE_SDD2
W16
IDE_SDD3
AC16
IDE_SDD4
W15
IDE_SDD5
AB15
IDE_SDD6
W14
IDE_SDD7
AA14
IDE_SDD8
Y14
IDE_SDD9
AC15
IDE_ SDD10
AA15
IDE_ SDD11
Y15
IDE_ SDD12
AB16
IDE_ SDD13
Y16
IDE_ SDD14
AA17
IDE_ SDD15
Y17
J23 F19
RTC_RST#
W7
+VBIAS +R_VBIAS
Y6
RTCX1
AC7
RTCX2
AC6
SPKR
H23
W20
Place R502 near to U12 pinW20
THRMTRIP#
EC_SMI# <32> EC_SCI# <32> EC_LID_OUT# <32> FLASH# <33>
IDE_PDA0 <26> IDE_PDA1 <26> IDE_PDA2 <26> IDE_PDCS1 # <26> IDE_PDCS3 # <26>
IDE_PDDREQ <26> IDE_PDDACK# <26> IDE_PDIOR# <26> IDE_PDIOW # <26> IDE_PDIORDY <26>
IDE_PDD[0..1 5]
IDE_SDA0 <26> IDE_SDA1 <26> IDE_SDA2 <26> IDE_SDCS1 # <26> IDE_SDCS3 # <26>
IDE_SDDREQ <26> IDE_SDDACK# <26> IDE_SDIOR# <26> IDE_SDIOW # <26> IDE_SDIORDY <26>
IDE_SDD[0..1 5]
CLK_ICH_14M <14> CLK_ICH_48M <14>
ICH_SPKR <30>
R220 @1K_0402_5%
12
R502
1 2
56_0402_5%
IDE_PDD[0..1 5] <26>
IDE_SDD[0..15 ] <26>
Place J1 close to DDR-SODIMM
12
J7 JOPEN
1 2
10M_0603_5%
32.768KHZ
+3VS
1
C485 12P_0603_50V8K
2
+CPU_CORE
H_THERMTRIP# <5>
R186
X3
R422
1 2
1K_0603_5%
R421
1 2
10M_0603_5%
1
C518 12P_0603_50V8K
2
D
1
C425
0.1U_0402_16V7K
2
C475
1 2
0.047U_0603_16V7K
@22M_0603_5% R418 @2.4M_0603_1%
1 2
R394 180K_0402_5%
1 2
1 2
1K_0603_5%
R401
12
+RTCVCC
R386
Compal Electronics, Ltd.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY ORDISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC .
C
ICH4-M(2/2)
Size Document Number Re v
Custom
LA-1931
Date: Sheet
D
18 47Monday, June 09, 2003
of
0.2
A
B
C
D
E
F
G
H
U25C
VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101
ICH4-M
ICH4-M
POWERGND
VCC5REFSUS1
VCC_CPU_IO_0 VCC_CPU_IO_1 VCC_CPU_IO_2
B
VCC3.3_0 VCC3.3_1 VCC3.3_2 VCC3.3_3 VCC3.3_4 VCC3.3_5 VCC3.3_6 VCC3.3_7 VCC3.3_8
VCC3.3_9 VCC3.3_10 VCC3.3_11 VCC3.3_12 VCC3.3_13 VCC3.3_14 VCC3.3_15
VCCSUS3.3_0 VCCSUS3.3_1 VCCSUS3.3_2 VCCSUS3.3_3 VCCSUS3.3_4 VCCSUS3.3_5 VCCSUS3.3_6 VCCSUS3.3_7 VCCSUS3.3_8 VCCSUS3.3_9
VCC1.5_0
VCC1.5_1
VCC1.5_2
VCC1.5_3
VCC1.5_4
VCC1.5_5
VCC1.5_6
VCC1.5_7
VCCSUS1.5_0 VCCSUS1.5_1 VCCSUS1.5_2 VCCSUS1.5_3 VCCSUS1.5_4 VCCSUS1.5_5 VCCSUS1.5_6 VCCSUS1.5_7
VCC5REF1 VCC5REF2
VCCHI_0 VCCHI_1 VCCHI_2 VCCHI_3
VCCPLL
VCCRTC
VCCLAN3.3_0 VCCLAN3.3_1
VCCLAN1.5_0 VCCLAN1.5_1
D22 E10 E14 E16
W22
AA12 AA16 AA22
AB20
AC10 AC14 AC18 AC23
E17 E18 E19 E21 E22
F8 G19 G21
G3 G6
H1
J6 K11 K13 K19 K23
K3 L10 L11 L12 L13 L14 L21
M1 M11 M12 M13 M20 M22 N10 N11 N12 N13 N14 N19 N21 N23
N5 P11 P13 P20 P22
P3 R18 R21
R5
T1
T19
T23 U20 V15 V17
V3
W5
W8 Y19
Y7 A16 A18 A20 A22
A4
AA3 AA9
AB7 AC1
AC5 B12 B16 B18 B20 B22
B9 C15 C17 C19 C21 C23
C6
D1 D12 D15 D17 D19 D21 D23
D4
D8
A1
1 1
2 2
3 3
4 4
A
A5 AC17 AC8 B2 H18 H6 J1 J18 K6 M10 P12 P6 U1 V10 V16 V18
E11 F10 F15 F16 F17 F18 K14 V7 V8 V9
K10 K12 K18 K22 P10 T18 U19 V14
E12 E13 E20 F14 G18 R6 T6 U6
E7 V6
E15
L23 M14 P18 T22
AA23 P14 U18
C22
AB5
E9 F9
F6 F7
+3VS
+3VALW
+1.5VS
+1.5VALW
+VCC5REF
+VCC5REFSUS
+1.5VS
+CPU_CORE
+RTCVCC
R225 0_0805_5%
1 2
R423 0_0805_5%
1 2
R420 0_0805_5%
1 2
C
+3VALW
22U_1 206_16V4Z_V1
1
1
C109
C199
2
2
22U_1 206_16V4Z_V1
+3VS
0.1U_0402_16V4Z
1
1
C122
C497
2
+1.5VALW
1
C207
2
+1.5VS
1
C623
2
1
C473
0.1U_0402_16V4Z
2
+RTCVCC
+VCC5REF
0.1U_0402_16V4Z
E
2
0.1U_0402_16V4Z
10U_1206_16V4Z
1
C202
2
0.1U_0402_16V4Z
1
C605
2
2
1
1
C462
0.1U_0402_16V4Z
2
D36
1SS355
C494
22U_1 206_16V4Z_V1
22U_1 206_16V4Z_V1
22U_1 206_16V4Z_V1
+1.5VS+1.5VS_PLL
+3V+3V_LAN
+1.5V+ 1.5V_LAN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
D
MAY BE USED BY ORDISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC .
1
C565
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
C571
2
2
1
C523
2
0.1U_0402_16V4Z
1
C509
2
0.1U_0402_16V4Z
C492
0.01U_0402_25V4Z
21
12
1
1
C495
1U_0603_1 0V6K
2
2
0.1U_0402_16V4Z
1
C582
2
1
C474
C434
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C481
2
0.1U_0402_16V4Z
1
C524
2
1
2
R424 1K_0603_5%
1
C508
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C433
2
0.1U_0402_16V4Z
1
2
0.1U_0402_16V4Z
1
2
0.1U_0402_16V4Z
C504
0.1U_0402_16V4Z
F
0.1U_0402_16V4Z
1
C460
2
0.1U_0402_16V4Z
C583
22U_1206_16V4Z_V1
C606
2
C493
0.01U_0402_25V4Z
1
+CPU_CORE
1
C549
0.1U_0402_16V4Z
2
1
C573
2
0.1U_0402_16V4Z
1
2
1
C536
2
1
C210
2
+VCC5REFSUS
0.1U_0402_16V4Z
1
1
2
0.1U_0402_16V4Z
C510
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
0.1U_0402_16V4Z
Title
Size Document Number Re v
Date: Sheet
C516
C507
2
0.1U_0402_16V4Z
1
1
C522
C575
2
2
1
1
C471
C594
C553
+1.5VS_PLL+1.5V_LAN +3V_LAN
1
C604
0.1U_0402_16V4Z
2
+3VALW +5VALW+3VS +5VS
D37
1SS355
C569
2
1
2
21
1
2
0.1U_0402_16V4Z
C589
0.1U_0402_16V4Z
2
1
2
C611
0.1U_0402_16V4Z
Compal Electronics, Ltd.
ICH4-M Pullups & Decoupling
Custom
LA-1931
G
1
2
0.1U_0402_16V4Z
2
C613
0.01U_0402_25V4Z
1
1
C567
1U_0603_1 0V6K
2
12
R431 1K_0603_5%
1
C568
1U_0603_1 0V6K
2
0.1U_0402_16V4Z
C537
1
C496
2
1
C482
2
0.1U_0402_16V4Z
19 47Monday, June 09, 2003
of
H
0.2
5
,
PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31
1 2
CLK_PCI_1394
12
1
2
PCI_AD[0..31]
R216
100_0402_1%
R232 @33_0402_5%
C226 @22P_0402_50V8J
U29
25
AD0
24
AD1
20
AD2
19
AD3
18
AD4
16
AD5
15
AD6
14
AD7
11
AD8
10
AD9
9
AD10
8
AD11
7
AD12
4
AD13
3
AD14
2
AD15
117
AD16
116
AD17
115
AD18
114
AD19
113
AD20
109
AD21
107
AD22
106
AD23
103
AD24
102
AD25
101
AD26
98
AD27
97
AD28
96
AD29
95
AD30
94
AD31
12
CBE0#
1
CBE1#
119
CBE2#
104
CBE3#
105
IDSEL
120
FRAME#
121
IRDY#
123
TRDY#
124
DEVSEL#
125
STOP#
127
PERR#
128
PAR
93
REQ#
92
GNT#
88
INTA#
89
PCIRST#
90
PCICLK
NC45NC48NC49NC50NC37NC51NC52NC53NC54NC40NC39NC35NC74NC75NC76NC77NC78NC64NC81NC82NC83NC84NC85I2CEN43CARDEN
NC41NC
42
PCI_AD[0..31]<17,21,23,25>
D D
C C
PCI_C/BE#0<17,21,23,25> PCI_C/BE#1<17,21,23,25> PCI_C/BE#2<17,21,23,25> PCI_C/BE#3<17,21,23,25>
PCI_AD16
PCI_FRAME#<17,21,23,25>
PCI_IRDY#<17,21,23,25>
PCI_TRDY#<17,21,23,25>
PCI_DEVSEL#<17,21,23,25>
PCI_STOP#<17,21,23,25>
PCI_PERR #< 17,21,23,25>
PCI_PAR<1 7,21,23,25> PCI_REQ#0<17> PCI_GNT#0<17>
PIRQE#_1394<17>
17,21,22,23,25,26,31,32>
B B
CLK_PCI_1394<14>
PCIRST#
+3VS
46
Power
IEEE 1394
VT6301S
PCI Bus
+3VS
PVD36PVD
110
122
VCC99VCC
4
111
VCC
VCC5VCC17VCC32VCC
R210
4.7K_0402_5%
3
0.1U_0402_16V4Z
1
1
2
+3VS
21
30
VCC
VCC
12
NC
31
GND47GND
44
100
108
118
126
GND91GND
GND
GND
GND
EEPROM I/F
PM & Test
OSC
XI
57
C221 10P_0402_25V8K
112
38
GND6GND13GND23GND33GND
GND22GND
PVA PVA PVA PVA PVA PVA
GND GND GND GND GND GND
EECS EEDO
EEDI/SDA
EECK/SCL
PME#
XCPS
XREXT
TPB0M
TPB0P
TPA0M
TPA0P
TPBIAS0
PHYRESET#
XO
VT6301S-CD_LQFP128
58
1394 Differential Pairs
XO
XI
X4
XI
1 2
24.576MHz_16P_3XG-24 576-43E1
1 2
2
R227
1M_0402_5%
1
59 62 72 73 86 87
61 65 66 79 80 56
26 27 28 29
34
60
63
67 68 69 70 71
55
XO
1 2
EEDI_1394 EECK_1394
XCPS
XREXT
XTPB0­XTPB0+ XTPA0­XTPA0+ XTPBIAS0
2
C624
0.1U_0402_16V4Z
1
2
C225 10P_0402_25V8K
1
L41
FCM2012C-800_0805
+3V_1394
2
C633
1
0.1U_0402_16V4Z
1394_PME# <32>
0.1U_0402_16V4Z
2
C626
1
54.9_0402_1%
0.1U_0402_16V4Z
2
C635
1
0.1U_0402_16V4Z
12
R230
54.9_0402_1%
C632
0.33U_0603_10V7K
Note:These co mponents need t o close to chip pins.
C191
2
C634
0.1U_0402_16V4Z
1
6.34K_0402 _1%
12
R231
1
2
C190
2
XREXT
12
R505
54.9_0402 _1%
4.99K_0603 _1%
1
C189
2
0.1U_0402_16V4Z
2
C630 47P_0402_5 0V8J
1
12
R228
12
R238
2
0.1U_0402_16V4Z
1
C208
2
U28
1
A0
2
A1
3
A2
4
GND
AT24C02N-10SI-2.7_SO8
12
54.9_0402_1%
1
270P_0402_25V8K
2
1
C214
2
0.1U_0402_16V4Z
+3VS
8
VCC
7
WP
EECK_1394
6
SCL
EEDI_1394
5
SDA
+3VS
XCPS
R229
C229
0.1U_0402_16V4Z
1
C223
2
1 2
R224
1K_0402_5%
1 2
R222
1K_0402_5%
1 2
JP23
1
1
2
2
3
3
4
4
1
C188
2
0.1U_0402_16V4Z
R446 560_0402_5%
SANTA_360302
+3VS
0.1U_0402_16V4Z
1
C209
2
1
1
C204
0.1U_0402_16V4Z
2
A A
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY ORDISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC .
3
2
IEEE-1394 VT6306
Size Document Number Re v
LA-1931
Custom Date: Sheet
20 47Monday, June 09, 2003
1
of
0.2
5
4
3
2
1
D D
+S1_VCC
+3V
1
1
C365
4.7U_0805_10V4Z
VPPD0<22>
VPPD1<22> VCCD0#<22> VCCD1#<22>
+3V
12
10K_0402_5% R438
21
R328 @33_0402_5%
C353 @10P_0402_50V8K
PCI_AD[0..31]
PCI_C/BE#3<1 7,20,23,25> PCI_C/BE#2<1 7,20,23,25> PCI_C/BE#1<1 7,20,23,25> PCI_C/BE#0<1 7,20,23,25>
PCIRST#<8,15,17,20,22,23,25,26,31,32>
PCI_FRAME#<17,20,23,25>
PCI_IRDY#<17,20,23,25>
PCI_TRDY#<17,20,23,25>
PCI_DEVSEL#<17,20,23,25>
PCI_STOP#<17,20,23,25>
PCI_PERR #< 17,20,23,25>
PCI_SERR #<17,23,25>
PCI_PAR<1 7,20,23,25> PCI_REQ#2<17> PCI_GNT#2<17>
CLK_PCI_ CB<14>
PCM_PME#<32>
PCI_AD20
1 2
R327 100_0402_1%
PIRQA#_PCM<17>
SERIRQ<17,31,32>
PM_CLKRUN#<18, 23,25,31,32>
CBRST#<22,25>
PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0
CLK_PCI_PCM
PCM_ID
PM_CLKRUN#
3 4 5 7 8
9 10 11 15 16 17 19 23 24 25 26 38 39 40 41 43 45 46 47 49 51 52 53 54 55 56 57
12 27 37 48
20 28 29 31 32 33 34 35 36
1
2 21
59 70
13
60 61 64 65 67 68 69
66
PCI_AD[0..31]<17,20,23,25>
C C
B B
SUSP#<28,3 2,33,37,43>
D19 RB751V_SOD323
CLK_PCI_PCM
A A
12
1
2
2
74
U11
AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
C/BE3# C/BE2# C/BE1# C/BE0#
RST# FRAME# IRDY# TRDY# DEVSEL# STOP# PERR# SERR# PAR REQ# GNT# PCLK
RI_OUT#/PME# SUSPEND#
IDSEL
MFUNC0 MFUNC1 MFUNC2 MFUNC3 MFUNC4 MFUNC5 MFUNC6
VCC/GRST#
C349
0.1U_0402_16V4Z
2
18
44
72
VPPD071VPPD1
VCCP1
VCCP0
VCCD0#73VCCD1#
PQFP 144
22.2 X 22.2 X 1.60
GND1
GND2
GND3
GND4
GND5
GND6
6
22
42
58
78
94
1
C69
0.1U_0402_16V4Z
2
90
126
138
VCC1
VCCSK1
VCCSK0
GND7
GND8
114
130
102
122
VCC3
VCC2
RSVD/D14
RSVD/A18
84
100
1
C347
0.1U_ 0402_16V4Z
2
+3V
+3V
14
30
50
86
VCC7
VCC6
VCC5
VCC4
CAD31/D10
CAD19/A25
CAD17/A24 CAD16/A17
CAD15/IOWR#
CAD13/IORD#
CAD12/A11
CAD11/OE#
CAD10/CE2#
CC/BE3#/REG#
CC/BE2#/A12
CC/BE1#/A8
CC/BE0#/CE1#
CRST#/RESET CFRAME#/A23
CIRDY#/A15
CTRDY#/A22
CDEVSEL#/A21
CSTOP#/A20 CPERR#/A14
CSERR#/WAIT#
CREQ#/INPACK#
CGNT#/WE#
CSTSCHG/BVD1
CCLKRUN#/WP
CBLOCK#/A19
CINT#/READY
CAUDIO/BVD2
CCD2#/CD2# CCD1#/CD1#
CVS2/VS2# CVS1/VS1#
RSVD/D2
CB1410_LQFP144
143
1 2
C359
0.1U_0402_16V4Z
63
VCCI
CAD30/D9 CAD29/D1 CAD28/D8 CAD27/D0 CAD26/A0 CAD25/A1 CAD24/A2 CAD23/A3 CAD22/A4 CAD21/A5 CAD20/A6
CAD18/A7
CAD14/A9
CAD9/A10 CAD8/D15
CAD7/D7
CAD6/D13
CAD5/D6
CAD4/D12
CAD3/D5
CAD2/D11
CAD1/D4 CAD0/D3
CPAR/A13
CCLK/A16
SPKOUT
+3V
C374
S1_A16
1 2
C348 0.1U_0402_16V4Z
1 2
C84 0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C373
2
S1_A[0..25]
S1_D[0..15]
1
2
0.1U_0402_16V4Z
S1_CD2# <22> S1_CD1# <22>
0.1U_0402_16V4Z
1
1
C351
2
2
0.1U_0402_16V4Z
S1_D10
144
S1_D9
142
S1_D1
141
S1_D8
140
S1_D0
139
S1_A0
129
S1_A1
128
S1_A2
127
S1_A3
124
S1_A4
121
S1_A5
120
S1_A6
118
S1_A25
116
S1_A7
115
S1_A24
113
S1_A17
98
S1_IOWR#
96
S1_A9
97
S1_IORD#
93
S1_A11
95
S1_OE#
92
S1_CE2#
91
S1_A10
89
S1_D15
87
S1_D7
85
S1_D13
82
S1_D6
83
S1_D12
80
S1_D5
81
S1_D11
77
S1_D4
79
S1_D3
76
S1_REG#
125
S1_A12
112
S1_A8
99
S1_CE1#
88
S1_RST
119
S1_A23
111
S1_A15
110
S1_A22
109
S1_A21
107
S1_A20
105
S1_A14
104
S1_WAIT#
133
S1_A13
101
S1_INPACK#
123
S1_WE#
106
A16_CLK
108
135 136
103
132
62 134
137 75 117 131
R81 33_0402_5%
S1_BVD1 S1_WP
S1_A19
S1_RDY#
PCM_SPK# S1_BVD2
S1_VS2 S1_VS1
S1_D2 S1_A18 S1_D14
1 2
C375
S1_IOWR# <22>
S1_IORD# <22>
S1_OE# <22> S1_CE2# <22>
S1_REG# <22>
S1_CE1# <22>
S1_RST <22>
S1_WAIT# <22>
S1_INPACK# <22> S1_WE# <2 2>
S1_BVD1 <22> S1_WP <2 2>
S1_RDY# <22>
PCM_SPK# <30> S1_BVD2 <22>
S1_VS2 <22> S1_VS1 <22>
1
2
0.1U_0402_16V4Z
C77
0.1U_0402_16V4Z
1
C56
2
S1_A[0..2 5] <22>
S1_D[0..15] <22>
1
C346
0.1U_0402_16V4Z
2
Compal Electronics, Ltd.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY ORDISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC .
3
2
CardBus Controller<ENE CB1410>
Size Document Number Re v
Custom
LA-1931
Date: Sheet
21 47Monday, June 09, 2003
1
of
0.2
PCMCIA Powe r Controller
C78 1U_0805_25V4Z
C66
0.1U_0402_16V4Z
C64
0.1U_0402_16V4Z
13 12 11
10
1 2 15 14
8
+5VALW
1
C75 10U_1206_16V4Z
2
+3V
14
1
P
OE#
I2O
G
U16A
7
SN74L VC125APWLE_TSSOP14
+3V POWER
+S1_VCC
1
C67
0.1U_0402_16V4Z
2
CBRST#
3
+S1_VPP
VCCD0# <21> VCCD1# <21> VPPD0 <21> VPPD1 <21>
PCMRST# <32>
+3V
+12VALW
1
2
1
2
1
2
U12
9
12V
+5VALW
5
5V_1
6
5V_2
+3VALW
3
3.3V_1
4
3.3V_2
+3VALW
1
C61 10U_1206_16V4Z
2
PCIRST#<8,15,17,20,21,23,25,26,31,32> CBRST# <21,25>
AVCC1 AVCC2 AVCC3
AVPP
VCCD0# VCCD1#
VPPD0 VPPD1
GND
SHDN#
7
TPS2211IDBR_SSOP16
16
CBRST#
OC#
1
C79 1U_08 05_25V4Z
2
12
R116 10K_0402_5%
C145
0.01U_0402_25V4Z
C147
0.1U_0402_16V4Z
+S1_VPP
+S1_VCC
S1_A23
S1_WP
S1_OE#
1
1
2
1
2
C146
4.7U_ 1206_16V4Z
2
1
C150 10U_1206_16V4Z
2
S1_A[0..25]<21>
S1_D[0..15]<21>
S1_A[0..25]
S1_D[0..15]
CardBus Socket
JP18
1 2
R150 22K_0402_5%
1 2
R113 22K_0402_5%
1 2
R194 43K_0402_5%
S1_D3 S1_D4 S1_D5 S1_D6 S1_D7
S1_CE1#<21>
S1_OE#<21>
S1_WE#<21> S1_RDY#<21>
S1_WP<21>
+S1_VCC
+S1_VCC
+S1_VCC
S1_CE1# S1_A10 S1_OE# S1_A11 S1_A9 S1_A8 S1_A13 S1_A14 S1_WE# S1_RDY#
+S1_VPP +S1_VPP
S1_A16 S1_A15 S1_A12 S1_A7 S1_A6 S1_A5 S1_A4 S1_A3 S1_A2 S1_A1 S1_A0 S1_D0 S1_D1 S1_D2 S1_WP
1 3 5 7
9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83
FOXCO NN_1CA415M1-TA_68P
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 GND GND GND GND GND GND GND GND
(APL11)
GND GND GND GND GND GND GND GND
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
54
56
56
58
58
60
60
62
62
64
64
66
66
68
68
70 72 74 76 78 80 82 84
S1_CD1# S1_D11 S1_D12 S1_D13 S1_D14 S1_D15 S1_CE2# S1_VS1 S1_IORD# S1_IOWR# S1_A17 S1_A18 S1_A19 S1_A20 S1_A21
S1_A22 S1_A23 S1_A24 S1_A25 S1_VS2 S1_RST S1_WAIT# S1_INPACK# S1_REG# S1_BVD2 S1_BVD1 S1_D8 S1_D9 S1_D10 S1_CD2#
S1_CD1# <21>
S1_CE2# <21> S1_VS1 <21> S1_IORD# <21> S1_IOWR# <21>
+S1_VCC+S1_VCC
S1_VS2 <21> S1_RST <21> S1_WAIT# <21> S1_INPACK# <21> S1_REG# <21> S1_BVD2 <21> S1_BVD1 <21>
S1_CD2# <21>
S1_CE1#
1 2
R197 43K_0402_5%
S1_CE2#
1 2
R195 43K_0402_5%
S1_RST
1 2
R135 43K_0402_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY ORDISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.
+S1_VCC
+S1_VCC
+S1_VCC
Compal Electronics, Ltd.
Title
PCMCIA SOCKET
Size Document Number R ev
Custom
LA-1931
Date: Sheet
22 47Monday, June 09, 2003
of
0.2
5
4
3
2
1
GND
VCC
R382
12
+3V
C171
0.1U_0402_16V4Z
R193
Place as close to U4(LAN Chip)
+2.5V_LAN
1 2
C161 22U_1206_16V4Z_V1
1 2
C441
1 2
C452
1 2
C454
1 2
C453
12
12
R192
49.9_0603_1%
1
C169
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
LAN_TD+ <24> LAN_TD- <24>
1 2
L30LQG21N4R7K10_0805
Place closed to RTL8101L pin58
RTL8101L has internal +2.5V generator at pin58
+2.5V_LAN
+3V
TRACE=30mil
+3V
1
C410
0.1U_0402_16V4Z
2
+3V
1
C382
0.1U_0402_16V4Z
2
1
C446
0.1U_0402_16V4Z
2
1
C114
0.1U_0402_16V4Z
2
1
C127
0.1U_0402_16V4Z
2
1
C383
0.1U_0402_16V4Z
2
0_0805_5%
+3V
5 6
NC
7
NC
8
1
2
49.9_0603_1%
1
C173 27P_0402_50V8J
2
+2.5V_LAN_1
2
D D
PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31
PCI_C/BE#0 PCI_C/BE#1 PCI_C/BE#2 PCI_C/BE#3
1 2
R130 100_0402 _5%
CLK_PCI_LAN
+3V
CLK_PCI_LAN
PCI_ AD[0..31]
PCI_C/BE#0<17,20,21,25> PCI_C/BE#1<17,20,21,25> PCI_C/BE#2<17,20,21,25> PCI_C/BE#3<17,20,21,25>
PCI_AD17 LAN_IDSEL
PCI_PAR<17,20,21,25>
PCI_FRAME#<17,20,21,25>
PCI_IR DY#<17,20,21,25>
PCI_TRDY#<17,20,21,25>
PCI_DEVSEL#<17,20,21,25>
PCI_STOP#<17,20,21,25>
PCI_PERR#<17,20,21,25> PCI_SERR#<17,21,25>
PCI_REQ#3<17>
PCI_GNT#3<17>
PIRQF#_LAN<17>
LAN_PME#<32>
PCIRST#<8,15,17,20,21,22,25,26,31,32>
CLK_PCI_LAN<14>
PM_CLK RUN#<18,21,25,31,32>
PCI_AD[0..31]<17,20,21,25>
C C
B B
12
R133
@10_0402_5%
1
C99 @10P_0402_50V8K
2
U18
47
AD0
46
AD1
45
AD2
43
AD3
42
AD4
41
AD5
40
AD6
39
AD7
36
AD8
35
AD9
34
AD10
33
AD11
32
AD12
30
AD13
29
AD14
28
AD15
15
AD16
14
AD17
13
AD18
12
AD19
11
AD20
10
AD21
9
AD22
8
AD23
96
AD24
93
AD25
92
AD26
91
AD27
89
AD28
87
AD29
86
AD30
85
AD31
38
C/BE#0
27
C/BE#1
17
C/BE#2
84
C/BE#3
98
IDSEL
24
PAR
18
FRAME#
19
IRDY#
20
TRDY#
21
DEVSEL#
23
STOP#
25
PERR#
26
SERR#
83
REQ#
82
GNT#
80
INTA#
79
INTB#
57
PME#
81
RST#
97
PCICLK
50
CLKRUN#
6
VDD
22
VDD
37
VDD
Power
49
VDD
90
VDD
95
VDD
RTL8101L_LQFP100
PCI I/F
ROMCS/OEB
Power
ISOLATE#
AC_RST# AC_SYNC AC_DOUT
AC-Link
VDD25 VDD25
AVDD25
AVDD
AVDD
AVDD
EEDO
EEDI EESK EECS
LED0 LED1 LED2
TXD+
TXD-
RXIN+
RXIN-
LAN I/F
LWAKE
RTSET
RTT3
VCTRL
AC_DIN
AC_BCK
GPIO0 GPIO1
DGND1 DGND2 DGND3 DGND4 DGND5 AGND1 AGND2 AGND3
48 94
58
59
70
75
52 53 54 55
78 77 76
72 71
68 67
61
X1
60
X2
64
74
65
63
56
1 3 4 5 7
100 99
51 69
NC
2 16 31 44 88 62 66 73
C123
0.1U_040 2_16V4Z
1
+2.5V_LAN
+3V_LAN_VDD1
+3V_LAN_VDD2
+3V_LAN_VDD3
LAN_EEDO LAN_EEDI LAN_EECLK LAN_EECS
ACTIVITY# LINK10_100#
LAN_TD+ LAN_TD­LAN_RD+ LAN_RD-
LAN_X1
LAN_X2
1 2
R189 1K_0402_5%
1 2
R190 15K _0402_5%
1 2
R374
5.6K_0603_1%
TRACE=20mil
TRACE=20mil
TRACE=20mil
TRACE=20mil
1 2
LAN_X1 LAN_X2
1
2
TRACE=20mil
2
C437
0.1U_040 2_16V4Z
1
R178 5.6K_0402_5%
U27
4
DO
3
DI
2
SK
1
CS
AT93C46-10SI-2.7_SO8
ACTIVITY# <24> LINK10_100# <24>
LAN_RD+ <24> LAN_RD- <24>
+3VS
Y2
12
25MHZ_20P_1BX25000CK1A
C174 27P_0402_50V8J
A A
Compal Electronics, Inc.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, IN C. NEIT HER TH IS SHEE T NOR T HE INF ORMATION IT CONTAIN S
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CON SENT OF COMPAL ELE CTRONICS , INC.
3
2
LAN REALTEK RTL8101L
Size Document Number Rev
LA-1931
Date: Sheet
1
of
23 47Monday, June 09, 2003
5
4
3
2
1
Keep Out 40mil
Layout Note H0013 pls close to
LAN_TD+<23> LAN_TD-<23>
R307
49.9_0603_1%
conn.
O
1
+3V
3I2
G
+3V
LAN_RD+ LAN_RD-
LAN_TD+
LAN_TD-
DTA114YKA_SC59 Q26
1 2
300_0402_5%
1 2 3 4 5 6
8
1
C316
0.1U_0402_16V4Z
2
R285
U4
RD+ RD­CT NC NC CT TD+7TX+ TD-
H0013
RX+
RX-
CT NC NC CT
TX-
16 15 14 13 12 11 10 9
R287
75_0402_5%
RJ45_RX+ RJ45_RX-
RJ45_TX+ RJ45_TX-
12
12
R288 75_0402_5%
RJ45_GND
LAYOUT NOTICE: This area do not connect to power plan include Vcc and GND in any layer
+Amber_LED
+Amber_LED
+Green_LED
RJ45_GND
RJ45_RX-
RJ45_RX+
RJ45_TX-
RJ45_TX+
R283
75_0402_5%
T=10mil
T=10mil
1 2
1 2
1000P_1206_2KV7K
JP15
12
Amber LED+
11
Amber LED-
8
PR4-
7
PR4+
6
PR2-
5
PR3-
4
PR3+
3
PR2+
2
PR1-
1
PR1+
10
Green LED-
9
Green LED+
R284 75_0402_5%
C285
1 2
Termination plane should be copled to chassis ground and also depends on safety concern
1
C15
@0.1U _0402_16V4Z
2
SHLD4
SHLD3
SHLD2
SHLD1
SANTA_130401- 1
16
15
14
13
LANGND
1
2
C16
4.7U_ 0805_10V4Z
D D
LAN_RD+<23> LAN_RD-<23>
12
R308
49.9_0603_1%
C C
B B
Place as close to Magnetic ( U3)
ACTIVITY#<23>
12
1
C312
0.1U_0402_16V4Z
2
ACTIVITY#
LINK10_100#<23>
A A
5
LINK10_100#
2
3
I
G
DTA114YKA_SC59 Q25
O
1
R281
1 2
300_0402_5%
+Green_LED
Compal Electronics, Ltd.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY ORDISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC .
3
2
RJ11/RJ45 Connector
Size Document Number Re v
Custom
LA-1931
Date: Sheet
24 47Monday, June 09, 2003
1
of
0.2
1
C85
2
1000P_0402_25V8K
1
C187
0.1U_0402_16V4Z
2
1
C182
0.1U_0402_16V4Z
2
+3VS_MINIPCI
+5VS_MINIPCI
1
2
1 2
+3V
CHB1608B121_0603
0.1U_0402_16V4Z
C200 10U_0805_10V4Z
12
1
2
WL_OFF#<3 2>
KILL_SW#<32,34>
L11
C105
CLK_PCI_MI NI
R144 33_0402_5%
C130 10P_0402_50V8K
2
1
+3V
5
U22
1
P
B
2
A
G
TC7SH0 8FU_SSOP5
3
W=40mils
CLK_PCI_M INI<14>
2
C108
0.1U_0402_16V4Z
1
PM_CLKRUN#<18, 21,23,31,32>
+5VS_MINIPCI
+5VS_MINIPCI
Y
PIRQG#_MINI<17>
PCI_REQ#1<17>
PCI_C/BE#3<17,20,21,23>
PCI_C/BE#2<1 7,20,21,23> PCI_IRDY#<17,20,21,23>
PCI_SERR #<17,21,23>
PCI_C/BE#1<1 7,20,21,23>
C104
1 2
0.1U_0402_16V4Z
4
1 2
L18 0_0603_5%
MINI_PCI SOCKET
JP19
TIP RING
LAN RESERVED
RB751V_SOD323
D15
21
PIRQG#_MINI
PCI_AD31 PCI_AD29
PCI_AD27 PCI_AD25
PCI_AD21 PCI_AD19
PCI_AD17
PCI_AD12 PCI_AD10
PCI_AD8 PCI_AD7
PCI_AD5
PCI_AD3
W=30mils
PCI_AD1
W=30mils W =20mils
0603
112
KEY KEY
334 556 778 9910 111112 131314 151516 171718 191920 212122 232324 252526 272728 292930 313132 333334 353536 373738 393940 414142 434344 454546 474748 494950 515152 535354 555556 575758 595960 616162 636364 656566 676768 696970 717172 737374 757576 777778 797980 818182 838384 858586 878788 898990 919192 939394 959596 979798 9999100
101
101
102
103
103
104
105
105
106
107
107
108
109
109
110
111
111
112
113
113
114
115
115
116
117
117
118
119
119
120
121
121
122
123
123
124
KEYLIN K_5305-4-21 1
PCI_AD[0..31]
2
4 6 8
LAN RESERVED
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124
PIRQH#_MINI_2
W=40mils
MINI_RST#
PCI_AD30
PCI_AD28 PCI_AD26 PCI_AD24
MINI_IDSELPCI_AD23
PCI_AD22 PCI_AD20
PCI_AD18 PCI_AD16
PCI_AD15PCI_AD14 PCI_AD13 PCI_AD11
PCI_AD9
PCI_AD6 PCI_AD4 PCI_AD2 PCI_AD0
2
C177
0.1U_0402_16V4Z
1
W=30mils
+3V+5VS
1 2
R174
+5VS_MINIPCI PIRQH#_MINI_2 <17>
+3V
PCI_GNT#1 <17>
WLANPME# <32>
PCI_AD18
100_0402_5%
PCI_PAR <17,20,21,23>
PCI_FRAME# <17,20,21,23> PCI_ TRDY# <17,20,21,23> PCI_STOP# <17,20,21,23>
PCI_DEVSEL# <17,20,21,23>PCI_PERR #< 17,20,21,23>
PCI_C/BE# 0 <17,20,21,23>
MINI_RST#
R127
R126
W=40mils
1 2
1 2
PCI_AD[0..31] < 17,20,21,23>
PCIRST#
0_0402_5%
@0_0402_5%
0.1U_0402_16V4Z
PCIRST# <8,15,17,20,21,22,23,26,31,32>
CBRST# <21,22>
+3VS_MINIPCI
L12
1 2
CHB1608B121_0603
2
2
C93
C144
0.1U_0402_16V4Z
1
1
+3V
C138
0.1U_0402_16V4Z
+3VS_MINIPCI
1
2
1
C143 10U_0805_10V4Z
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY ORDISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.
Compal Electronics, Ltd.
Title
Mini PCI Slot
Size Document Number R ev
Custom
LA-1931
Date: Sheet
25 47Monday, June 09, 2003
of
0.2
IDE Module CONN.
IDE_PDDREQ<18>
IDE_PDIOW #<18>
IDE_PDIOR#<18> IDE_PDIORDY<1 8> IDE_PDDACK#<18>
INT_IRQ14<17>
IDE_PDA1<18>
IDE_PDA0<18>
IDE_PDCS1#<18> IDE_PDCS3 # <18>
PHDD_LED#<32>
+5VS
1 2
R254 100K_0402_5%
IDE_PDD[0..1 5]<18>
PIDE_RST# IDE_PDD7 IDE_PDD6 IDE_PDD5
IDE_PDD2 IDE_PDD1 IDE_PDD0
IDE_ PDDREQ
IDE_PDIORDY
INT_IRQ14
+5VS
IDE_ PDD[0..15]
JP10
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
SUYIN_200138FR044G242ZL
IDE_PDD8 IDE_PDD9 IDE_PDD 10 IDE_PDD 11IDE_PDD4 IDE_PDD 12IDE_PDD3 IDE_PDD 13 IDE_PDD 14 IDE_PDD 15
PCSEL
1 2
R265 470_0402_5%
1 2
R256 0_0402_5%
+5VS
IDE_PDA2 <18>
+3VS
1 2
R262 4. 7K_0402_5%
1 2
R264 @10K_0402_1%
1 2
R263 @5.6K_0402 _5%
+5VS
1
C257 1000P_0402_25V8K
2
Place component's closely IDE CONN.
IDE_PDIORDY
IDE_PDD7
IDE_PD DREQ
1
C255 10U_0805_10V4Z
2
1
C256 1U_0603_10V4Z
2
1
C258
0.1U_0402_16V4Z
2
+5VS
C254
0.1U_0402_16V4Z
12
5
1
B
2
A
U37
P
4
Y
G
TC7SH0 8FU_SSOP5
3
PIDE_RST#
PCIRST#<8,15,1 7,20,21,22,23,25,31,32>
PIDERST#<17>
PCIRST#
CD-ROM Module CONN.
IDE_SDD[0..1 5]<18>
INT_CD_L<28>
+5VS
1
CD_AGND<28>
C248 @12P_0402_50V8J
2
IDE_SDIOW #<18>
IDE_SDIORDY<18>
INT_IRQ15<17>
IDE_SDA1<18>
IDE_SDA0<18> IDE_SDCS1#<18> SHDD_LED#<32>
SHDD_LED#
1 2
R248 100K_0402_5%
SIDE_RST#
IDE_SDIORDY
+5VS
470_0402_5%
IDE_SDD[0..1 5]
IDE_SDD7 IDE_SDD6 IDE_SDD5 IDE_SDD4 IDE_SDD3 IDE_SDD2 IDE_SDD1 IDE_SDD0
12
R243
JP25
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
SUYIN_800189MB050S105ZL
1 2
@12P_0402_50V8J
IDE_SDD8
IDE_SDD9 IDE_SDD 10 IDE_SDD 11 IDE_SDD 12 IDE_SDD 13 IDE_SDD 14 IDE_SDD 15
IDE_ SDDREQ
1 2
R240 100K_0402_5%
2
C234
0.1U_ 0402_16V4Z
1
C235
+5VS
+5VS
INT_CD_R <28>
IDE_SDDREQ <18>
IDE_SDIOR# <18>
IDE_SDDACK# <18>
IDE_SDA2 <18> IDE_SDCS3# <18>
1 2
R250 4.7K_0402_5%
1 2
R247 @10K_0402_1%
1 2
R242 @5.6K_0402 _5%
+5VS
1
C238 1000P_0402_25V8K
2
Place component's closely CD-ROM CONN.
W=80mils
1
C247 10U_0805_10V4Z
2
IDE_SDIORDY
IDE_SDD7
IDE_SD DREQ
1
C236 1U_0603_10V4Z
2
1
C237
0.1U_0402_16V4Z
2
+5VS+3VS
C253
0.1U_0402_16V4Z
12
5
1
B
2
A
U36
P
4
Y
G
TC7SH0 8FU_SSOP5
3
SIDE_RST#
PCIRST#
SIDERST#<17>
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY ORDISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.
Compal Electronics, Ltd.
Title
IDE & CD-ROM Connec tor
Size Document Number R ev
Custom
LA-1931
Date: Sheet
26 47Monday, June 09, 2003
of
0.2
1
C283 10U_0805_10V4Z
2
C17
0.1U_0402_16V4Z
+USB_VCCA
R33 100K_0402_5%
+3V
12
100K_0402_5% R32
1 2
R31 47_0402_5%
1 2
R22 47_0402_5%
C19
0.1U_0402_16V4Z
1
2
1
C14
0.1U_0402_16V4Z
2
OVCUR#2 <18>
OVCUR#4 <18> USBP2+<18>
Keep 20 mils minimum spacing
1
+
C273
150U_D2_6.3VM
USBP2-<18>
USBP4-<18>
USBP4+<18>
R273 0_0402_5%
R274 0_0402_5%
R268 0_0402_5%
R269 0_0402_5%
150U_D2_6.3VM
1 2
1 2
1 2
1 2
C284
2
+USB_VCCB
1
+
2
USB_CGND
USB_BGND
USB2­USB2+
USB4-
USB4+
1
C275 470P_0603_50V8J
2
1
C274 470P_0603_50V8J
2
USB CONNE CTOR
JP13
1 2 3 4 5 6 7 8
TYCO_1470713-1
+USB_VCCB
+USB_VCCA
+5V
1
2
U3
1
GND
2
IN
3
EN1#
4
EN2#
TPS2042ADR_SO8
OC1# OUT1 OUT2
OC2#
8 7 6 5
12
0.1U_0402_16V4Z
1
C645 10U_0805_10V4Z
2
C231
+3V+USB_VCCC
R261 100K_0402_5%
12
R260 100K_0402_5%
1 2
R259 47_0402_5%
0.1U_0402_16V4Z
C250
OVCUR#3 <18>
1
2
USB2- USB2+ USB4+USB4-
1
C271
@10P_0402_50V8K
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY ORDISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.
2
C272
@10P_0402_50V8K
1
@10P_0402_50V8K
2
USBP3-<18>
USBP3+<18>
1
C269
@10P_0402_50V8K
2
C270
12
+5V
1
2
U32
1
GND
2
IN
3
EN1#
4
EN2#
TPS2042ADR_SO8
OC1# OUT1 OUT2
OC2#
8 7 6 5
+USB_VCCC
1
+
C646
150U_D2_6.3VM
R255 0_0402_5%
R253 0_0402_5%
1 2
1 2
1
2
2
USB_AGN D
C251
@10P_0402_50V8K
Title
Size Document Number R ev
Custom
Date: Sheet
1
C647 470P_0603_50V8J
2
USB3­USB3+
USB3- USB3+
1
@10P_0402_50V8K
2
C241
USB CONNE CTOR
JP26
1
1
2
2
3
3
4
4
TYCO_1470712-1
1
2
Compal Electronics, Ltd.
USB & Bluetoot h
LA-1931
27 47Monday, June 09, 2003
0.2
of
5
AC97 Codec
12
R344 @68K_0402_5%
12
12
R379
20K_0402_5%
1
2
12
12
LINEIN_L
LINEIN_R
12
R340 @68K_0402_5%
12
C_MD_SPK
12
R413
2.4K_0402_5%
CD_GNA
R358
20K_0402_5%
CD_L
CD_R
12
R349 20K_0402_5%
+VDDA
MONO_IN<30>
IAC_RST#<18>
IAC_SYNC<18>
IAC_SDATAO<18>
MD_SPK
C467
1 2
R342 0_0402_5%
1 2
R336 0_0402_5%
INT_CD_L
R380 20K_0402_5%
INT_CD_R
R351 20K_0402_5%
R411
1 2
10K_0402_5%
1
2
@0.01U_0402_25V4Z
12
R370 0_0402_5%
C458
R362
20K_0402_5%
LINE_IN_L<30>
LINE_IN_R<30>
D D
INT_CD_L<26>
INT_CD_R<26>
C C
0.01U_0402_25V4Z
CD_AGND<26>
B B
CHB2012U170_0805
MIC<3 0>
EAPD<30>
4
L9
1 2
0.1U_0402_16V4Z
LINEIN_L
LINEIN_R
CD_L
CD_R
CD_GNA
C_MD_SPK
IAC_RST#
IAC_SYNC
IAC_SDATAO
DGND
1
1
C111
C399 1U_0603_10V4Z
C386 1U_0603_10V4Z
C438 1U_0603_10V4Z
C411 1U_0603_10V4Z
C422 1U_0603_10V4Z
C404 1U_0603_10V4Z
C125 0.1U_0402_16V4Z
C445 1U_0603_10V4Z
1 2
R410 100_0402_5%
R155 @0_0402_5%
2
12
12
12
12
12
12
12
12
C102 10U_0805_10V4Z
2
C_MICMIC
12
3
+AVDD_AC97
U45
14
AUX_L
15
AUX_R
16
VIDEO_L
17
VIDEO_R
23
LINE_IN_L
24
LINE_IN_R
18
CD_L
20
CD_R
19
CD_GND
21
MIC1
22
MIC2
13
PHONE
12
PC_BEEP
11
RESET#
10
SYNC
5
SDATA_OUT
45
NC
46
XTLSEL
47
EAPD
48
SPDIFO
4
DVSS1
7
DVSS2
ALC202 E_LQFP48
38
AVDD125AVDD2
1 2
L36 0_0805_5%
1 2
L19 0_0805_5%
1 2
L10 0_0805_5%
1 2
L42 0_0805_5%
0.1U_0402_16V4Z
DVDD11DVDD2
LINE_OUT_L
LINE_OUT_R
MONO_OUT
TRUE_LOUT_L
TRUE_LOUT_R
BIT_CLK
SDATA_IN
XTL_IN
XTL_OUT
AFILT1
AFILT2
VREFOUT
VREF
VRDA
VRAD
DCVOL
VAUX GPIO0 GPIO1
AVSS1 AVSS2
+3VS
C152
9
35
36
37
39
41
6
8
2
3
29
30
28
27
32
31 33 34 43 44
40
NC
26 42
DGND AGND
1
2
LINEL
C131 4.7U_0805_10V4Z
LINER
C132 4.7U_0805_10V4Z
C129 1U_0 603_10V4Z
R402 22_0402_5%
R403 22_0402_5%
XTL_IN
XTL_OUT
C118 1000P_0402_25V8K
C119 1000P_0402_25V8K
1 2
R161@0_0402_5%
AGND
AGND
1
C448 10U_0805_10V4Z
2
1 2
1 2
1 2
1 2
1 2
R404 @1M_0402_5%
1 2
1 2
1 2
+AVDD_AC97
4.7U_0805_10V4Z
12
R339
@1K_0402_5%
SUSP#<21 ,32,33,37,43>
@0.01 U_0402_25V4Z
1
C385 1U_0603_10V4Z
2
+5VALW
C140
LINE_OUT_L
LINE_OUT_R
MD_MIC
IAC_BITCLK
IAC_SDATAI0
0.1U_0402_16V4Z
1
2
SUSP#
+AUD_VREF
1
C113
2
2
1
C128
2
LINE_O UT_L <29>
LINE_OUT_R <29>
IAC_BITCLK <18>
IAC_SDATAI0 <18>
22P_0402_5 0V8J
0.1U_0402_16V4Z
1
C95 1U_06 03_10V4Z
2
Adjustable Ou tput
U20
4
VIN
2
SENSE or ADJ
DELAY
ERROR7CNOISE
8
SD
SI918 2DH-AD_MSOP8
LINEL
LINER
IAC_BITCLK
IAC_SDATAI0
1
C489
2
1
C112
2
5
VOUT
6
1
3
GND
XTL_IN
24.576MHz_16P_3XG-24 576-43E1
1
C391
4.7U_0805_10V4Z
2
1
C100
0.1U_0402_16V4Z
2
1 2
C120 1000P_0402_25V8K
1 2
C121 1000P_0402_25V8K
1 2
C466 @22P_0402_50V8J
1 2
@10K_0402_5%
R409
X5
12
0.1U_0402_16V4Z
XTL_OUT
C376
12
12
1
C490 22P_0402_5 0V8J
2
1
2
1
+VDDA
R151
69.8K_0603 _1%
R137 24K_0402_1%
+AUD_VREF
1
C370
4.7U_0805_10V4Z
2
+VDDA
1
C133
4.7U_0805_10V4Z
2
+5VALW TO +5VCD
+5VCD
U30
1
+5VALW
+5VALW
C203
10U_1206_16V4Z
A A
1 2
5
C206
1U_0805_25V4Z
1 2
1 2
R208
240K_0402_5%
C205
12
1U_0805_25V4Z
R207 10K_0402_5%
SUSP#
S
2
S
3
S G4D
SI4425DY-T1_SO8
2
8
D
7
D
6
D
5
1
O
Q15 DTC124EK_SC59
G3I
4
C198
10U_1206_16V4Z
1 2
1
C197
0.1U_0402_16V4Z
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY ORDISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC .
3
MDC Connector
1 2
+3V
R66 0_0402_5%
1 2
+3VS
L5 CH B1608B121_0603
IAC_SDATAO IAC_RST#
+3V_MDC
+3VS_MDC
JP17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
AMP 3-1565120-0 30P H:9MM
2
MD_SPK
+5VS_MDC
+3VS_MDC_R
1 2
L25 CHB1 608B121_0603
1 2
R313 10K_0402_5%
1 2
R316 0_0402_5% R318 22_0402_5%
1 2
R319 22_0402_5%
12
R315 10K_0402_5%
Compal Electronics, Ltd.
Title
AC97 Codec ALC202
Size Document Number Re v
Custom
LA-1931
Date: Sheet
IAC_SYNC
IAC_BITCLK
1
+5VS
+3VS
IAC_SDATAI1 <18>
28 47Monday, June 09, 2003
of
0.2
5
BY-PASS EQ CIRCUIT == W/O EQ
LINE_OUT_L<28>
LINE_OUT_R<28>
D D
LINE_OUT_L
LINE_OUT_R
R164 0_0402_5%
R165 0_0402_5%
12
12
AMP_LEFT
AMP_RIGHT
4
C556
@0.1U_0402_16V4Z
@100K_0603_1%
2
@100K_0603_1%
1
R426
R435
+5VCD
3
12
+5VCD
4
9
-
V+
O
10
+
V-
+5VCD
13
-
12
+
U48C
11
@LMV824MTX_TSSOP14
4
V+
O
V-
U48D
11
@LMV824MTX_TSSOP14
12
+2.5VOP_REF
8
14
2
1
+5VCD+5VCD
1
C154 @4.7U_0805_10V4Z
2
C C
LINE_OUT_L
@0.01 8U_0603_16V7K
C153
1 2
12
R180 @54 .9K_0603_1%
C157
@0.01 8U_0603_16V7K
+2.5VOP_REF
EQ_L_IN1
12
@0.1U_0402_16V4Z
EQ_L_IN1#
12
AUDIO LEFT CHANNEL
+5VCD
1
1
2
2
C149
@0.01 8U_0603_16V7K
C116 @4.7U_0805_10V4Z
12
R156 @54 .9K_0603_1%
C137
@0.01 8U_0603_16V7K
+2.5VOP_REF
1 2
@0.1U_0402_16V4Z
EQ_R_IN1#
EQ_R_IN1
12
B B
C103
@4.7U_0805_10V4Z
LINE_OUT_R
AUDIO RIGHT CHANNEL
A A
2
C158
1
4
2
-
V+
EQ_L_OUT1
1
O
3
+
V-
U46A
11
R173 @143K_0603_1%
@3300P_0402_50V7K
12
R148 @143K_0603_1%
@3300P_0402_50V7K
@LMV824MTX_TSSOP14
1 2
R181
2
C488
1
EQ_L_IN2
12
R166 @100K_0603_1%
+2.5VOP_REF +2.5VOP_REF
+5VCD
2
C126
1
4
2
-
V+
1
O
3
+
V-
U44A
11
@LMV824MTX_TSSOP14
1 2
R346
2
C407
1
EQ_R_IN2
12
R357 @100K_0603_1%
+2.5VOP_REF
1 2
R425 @4.3 2K_0603_1%
C487 @0.056U_0402_16V4Z
@5.62K _0603_1%
6
5
EQ_R_OUT1
@5.62K_0 603_1%
1 2
R368 @4.3 2K_0603_1%
+5VCD
4
-
V+
7
O
+
V-
U46B
11
@LMV824MTX_TSSOP14
C397 @0 .056U_0402_16V4Z
+5VCD
4
6
-
V+
7
O
5
+
V-
U44B
11
@LMV824MTX_TSSOP14
EQ_L_OUT2
EQ_R_OUT2
R175 @2.87K_0603 _1%
2
C163
1
2
1
+2.5VOP_REF
@0.1U _0402_16V4Z
C486
@1000P_0402_50V7K
12
1 2
@2700P_0603_50V7K
EQ_L_IN3 EQ_L_IN4
12
R187 @162K_0603_1%
C393 @1000P_0402_50V7K
1 2
R341 @2.87K_0603 _1%
C396
@2700P_0603_50V7K
EQ_R_IN3 EQ_R_IN 4
12
R347 @162K_0603_1%
+5VCD
4
9
-
V+
O
10
+
V-
U46C
11
@LMV824MTX_TSSOP14
12
+5VCD
4
9
-
V+
O
10
+
V-
11
EQ_L_IN5
R433 @1.05K_0603 _1%
2
C531
EQ_L_OUT3 EQ_L_OUT4
8
EQ_R_IN5
EQ_R_OUT3
8
U44C @LMV824MTX_TSSOP14
1
+2.5VOP_REF
2
1
+2.5VOP_REF
C555
C548
12
@1800P_0402_50V7K
1 2
@1200P_0603_50V7K
12
R432
@162K_0603_1%
C436
@1800P_0402_50V7K
1 2
R360 @1.05K_0603 _1%
C435
@1200P_0603_50V7K
12
R352
2
1
12
@162K_0603_1%
+5VCD
2
-
3
+
+5VCD
13
-
12
+
6
5
13
12
C574 @100P_0402_50V8K
1 2
R452 @2.2 6K_0603_1%
4
V+
1
O
V-
U48A
11
@LMV824MTX_TSSOP14
4
V+
14
O
V-
U46D
11
@LMV824MTX_TSSOP14
C430 @100P_0402_50V8K
1 2
R373 @2.2 6K_0603_1%
+5VCD
4
-
V+
7
O
+
V-
U48B
11
@LMV824MTX_TSSOP14
+5VCD
4
-
V+
EQ_R_OUT4
14
O
+
V-
U44D
11
@LMV824MTX_TSSOP14
12
AMP_LEFT
OUTPUT TO AMPLIFIER LEFT CHANNEL
12
AMP_RIGHT
OUTPUT TO AMPLIFIER RIGHT CHANNEL
AMP_LEFT <30>
AMP_RIGHT <30>
Compal Electronics, Ltd.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY ORDISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC .
3
2
H/W EQ
Size Document Number Re v
Custom
LA-1641
Date: Sheet
29 47Monday, June 09, 2003
1
of
0.2
A
Audio AMP
12
R4411.3K_0603_5%
12
4 4
AMP_LEFT<29>
AMP_RIGHT<29>
R1961.3K_0603_5%
12
C1720.1U_0402_16V4Z
AMP_LEFT
AMP_RIGHT
AMP_LEFT
AMP_RIGHT
VOL_AMP
W/EQ Depop R385 & R386
W/O EQ R385=R386= 1.3K Ohm
R = R385, R386 C = C537, C539
OUT_L
fo=1/(2*3.14*R*C)=260Hz
OUT_R
R=1.3K / C=0.47U
HIGH
Pin 22
LOW PIN 9,5 ACTIVE
INTSPK_L1 INTSPK_R1 OUT_L
1 2
C570 0.47U_0603_16V4Z
C514 0.47U_0603_16V4Z
1 2
OUT_R
C581 0.47U_0603_16V4Z
C515 0.47U_0603_16V4Z
C537=C539=0
C537=C539= 0.47U
PIN 10,4 ACTIVE
NBA_PLUG VOL_AMP
1 2
C564 0.47U_0603_16V4Z
1 2
C532 0.47U_0603_16V4Z
1 2
1 2
HP_L
HP_R
B
W=40Mil
C180
0.1U_0402_16V4Z
3
11
7
22 21 14 24
9
10
4
16
+5VCD
1
1
2
2
U47
PVDD
SHUTDOWN#
PVDD
SE/BTL#
VDD
BYPASS
LOUT-
HP/LINE#
ROUT­VOLUME LOUT+ ROUT+ LLINEIN
SEMAX RLINEIN5SEDIFF LHPIN RHPIN
PGND PGND AGND
FADE#
TPA6011A4_TSSOP24
C185
4.7U_ 0805_10V4Z
15 23 17 12 2 8
LIN
6
RIN
19 20
1 13 18
SHUTDOWN#
2
C563
1
0.47U_0603_16V4Z
1U_0603_10V6K
(0.47U~1U)
INTSPK_L2 INTSPK_R2
1
C533
2
+5VCD
12
R454 100K_0402_5%
Q33
13
D
2N7002_SOT23
2
G
S
R430
100K_0402_5%
NBA_PLUG
10K_0402_5%
1
@10K_0402_5%
C551
2
0.47U_0603_16V4Z
+5VCD
1 2
R202
R199
C
EAPD <28>
+5VCD
12
12
R434 @0_0402_5%
12
12
R442 0_0402_5%
100K_0402_5%
NBA_PLUG
2N7002_SOT23
2
R512
G
Q36
+5VCD
D
+5VCD
R513
3.9K_0402_5%
1 2
VR1
3
10K_A TYPE
VOL_AMP
R503
2
G
1 2
2.2K_0402_5%
13
D
Q38
S
2N7002_SOT23
1 2
13
D
S
6
VR - A-Type
2
1
1 2
5
1
R504 3K_0402_5%
+AUD_VREF
E
R162
12
3 3
Speaker Connector
INTSPK_L1 INTSPK_L2 INTSPK_R1 INTSPK_R2
V-PORT-0603-220 M-V05_0603
2 2
System Sound
I5O
A
4
U16B
OE#
+3V
12
R206 100K_0402_5%
R209
1 2
6
8.2K_0402_5%
0.22U_0603_16V4Z
U31B
3
BEEP#<32>
SN74L VC125APWLE_TSSOP14
PCM_SPK#<21>
1 1
ICH_SPKR<18>
SN74L VC14APWLE_TSSOP14
C211
+3V
14
7
1
1
2
+3V POWER
P
O4I
G
+3V
C192
1 2
0.1U_0402_16V4Z
14
U31A
P
O2I
G
SN74L VC14APWLE_TSSOP14
7
+3V POWER
C219
1 2
1U_0603_10V6K
C213
1 2
1U_0603_10V6K
C212
1 2
1U_0603_10V6K
1 2
560_0402_5%
R221
1 2
560_0402_5%
R212
1 2
560_0402_5%
10K_0402_5%
B
R215
R211
D35
2 1
V-PORT-0603-220 M-V05_0603
MONO_IN_I
12
D34
V-PORT-0603-220 M-V05_0603
V-PORT-0603-220 M-V05_0603
D20 RB751V_SOD323
2 1
+VDDA
2
2 1
D33
12
R203 10K_0402_5%
12
R204 10K_0402_5%
1
C
E3B
2 1
D32
MONO_IN_O
Q16 2SC2411K_SC59
JP4
1 2 3 4
ACES_85204-0400
2 1
1
C201 10U_1206_16V4Z
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY ORDISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC .
1U_0603_10V 6K
R205
2.4K_0402_5%
1 2
C
C184
12
MONO_IN <28>
INTSPK_R1
INTSPK_L1
MIC<28>
LINE_IN_R<28>
LINE_IN_L<28>
1 2
C148
1 2
C168
+
150U_D2_6.3VM
+
150U_D2_6.3VM
MIC
L15
1 2
FBM-11-160808-700T_0603
L13
1 2
FBM-11-160808-700T_0603
1 2
L14
FBM-11-160808-700T_0603
330P_0402_50V7K
L16
FBM-11-160808- 700T_0603
L17 FBM-11-160808- 700T_0603
D
1 2
1 2
330P_0402_50V7K
MIC-1
220P_0402_50V8K
C136
Title
Size Document Number Re v
Custom
Date: Sheet
12
2.2K_0402_5%
R163
@2.2K_0402 _5%
1
C159
2
LINE_IN_R-1
LINE_IN_L-1
1
1
C110
330P_0402_50V7K
2
2
NBA_PLUG
1
1
C186
2
C176 330P_0402_50V7K
2
Compal Electronics, Ltd.
Audio AMP & JACK
LA-1931
MICROPHONE IN JACK
JP3
5
4
3 6 2 1
FOX_JA6033L-5 S1-TR
LINE IN JACK
JP2
5
4
3 6 2 1
FOX_JA6033L-5 S1-TR
HEADPHONE OUT JACK
JP5
5
4
3 6 2 1
FOX_JA6033L-5 S1-TR
E
30 47Monday, June 09, 2003
0.2
of
A
SUPER I/O SMsC FDC47N227
1 1
14.3M_SIO
R70
@10K_0402_5%
@15P_0402_50V8J
@33_0402_5%
2 2
@22P_0402_50V8J
1 2 1
C49
2
PCLK_SIO
R60
1 2
1
C31
2
PID[0..3]<16>
LPC_AD[0..3]<18,32>
PID[0 ..3]
B
LPC_AD[0..3]
LPC_F RAME#<18,32>
LPC_DRQ#1<18>
PCIRST#<8,15,17,20,21,22,23,25,26,32>
PM_CLKRUN#<18,21,2 3,25,32>
CLK_PCI_SIO<14>
CLK_SIO_14M<14>
+3VS
R294
R297
+3VS
C326
4.7U_0805_10V4Z
+3VS
SERIRQ<17,21,32>
R302 100K_0402_ 5%
1 2
10K_0402_5%
10K_0402_5%
1
2
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
1 2
R64 10K_0 402_5% R39 10K_0 402_5% R69 10K_0 402_5%
PCLK_SIO
14.3M_SIO
FIR_EN#
12
12
1
C289
0.1U_0402_16V4Z
2
12 12
1
C320
0.1U_0402_16V4Z
2
0.1U_0402_16V4Z
PID0 PID1 PID2 PID3
C
U7
20
LAD0
21
LAD1
22
LAD2
23
LAD3
24
LFRAME#
25
LDRQ#
26
PCIRST#
27
LPCPD#
50
GPIO12/IO_SMI#
17
IO_PME#
30
SIRQ
28
CLKRUN#
29
PCICLK
19
CLK14
48
GPIO10
54
GPIO15
55
GPIO16
56
GPIO17
57
GPIO20
58
GPIO21
59
GPIO22
6
GPIO24
32
GPIO30
33
GPIO31
34
GPIO32
35
GPIO33
36
GPIO34
37
GPIO35
38
GPIO36
39
GPIO37
40
GPIO40
41
GPIO41
42
GPIO42
43
GPIO43
44
GPIO44
45
GPIO45
46
GPIO46
47
GPIO47
51
GPIO13/IRQIN1
52
GPIO14/IRQIN2
64
GPIO23/FDC_PP
18
VTR
53
VCC
65
VCC
93
VCC
7
VSS
31
VSS
60
1
C328
2
VSS
76
VSS
LPC47N227 B_TQFP100
PD0/INDEX#
PD1/TRK0
PD2/WRTPRT#
PD3/RDATA#
PD4/DSKCHG#
PD6/MTR0#
BUSY/MTR1#
PE/WDATA#
SLCT/WGATE#
ERROR#/HDSEL#
ACK#/DS1#
INIT#/DIR#
AUTOFD#/DRVDEN0#
STROBE#/DS0# SLCTIN#/STEP#
DTR2# CTS2# RTS2#
DSR2#
TXD2 RXD2
DCD2#
DTR1# CTS1# RTS1#
DSR1#
TXD1 RXD1
DCD1#
IRMODE/IRRX3
IRRX2 IRTX2
RDATA# WDATA# WGATE#
HDSEL#
DIR#
STEP#
DS0#
INDEX# DSKCHG# WRTPRT#
TRK0#
MTR0#
DRVDEN0
DRVDEN1
GPIO11/SYSOPT
PD5
PD7
RI2#
RI1#
LPD0
68
LPD1
69
LPD2
70
LPD3
71
LPD4
72
LPD5
73
LPD6
74
LPD7
75
LPTBUSY
79
LPTPE
78
LPTSLCT
77
LPTERR#
81
LPTACK#
80
INIT#
66
LPTAFD#
82
LPTSTB#
83
SLCTIN#
67
100
CTS#2
99 98
DSR#2
97 96 95
DCD#2
94
RI#2
92
DTR#1
89
CTS#1
88
RTS#1
87
DSR#1
86
TXD1
85
RXD1
84
DCD#1
91
RI#1
90
IRMODE
63
IRRX
61
IRTX
62
RDATA#
16
WDATA#
10
WGATE#
11
HDSEL#
12
FDDIR#
8
STEP#
9
DRV0#
5
INDEX#
13
DSKCHG#
4
WP#
15
TRACK0#
14
MTR0#
3 1
2
49
D
DCD#1
1 8
RI#1
2 7
CTS#1
3 6
DSR#1
4 5
1 2
R311 1K_0402_5%
1 2
R50 1K_0402_5%
1 2
R296 1K_0402_5%
+3VS
R42 @10K_0402_5%
1 2
*
Base I/O Address
R46 1K_0402_5%
1 2
RP5
4.7K_ 1206_8P4R_5%
+5VS
0 = 02Eh 1 = 04Eh
CTS#2 DSR#2 DCD#2 RI#2
MTR0# DRV0# STEP# WGATE#
+3VS+3VS
RP6
1 8 2 7 3 6 4 5
4.7K_1206_8P4R_5%
6 7 8 9
10
RP16
5 4 3 2 1
1K_1206_1 0P8R_5%
Serial Port for Debug
+5V
RXD1 TXD1 DSR#1 RTS#1 CTS#1 DTR#1 RI#1 DCD#1
E
INDEX# TRACK0# WP# RDATA#
DSKCHG#
FDDIR# WDATA# HDSEL#
RP17
1 8 2 7 3 6 4 5
1K_1206_8P4R_5%
+5VS
JP16
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
@E&T_96212-1011S
+5VS
RP1
FD0 FD1
68_1206_8P4R_5%
RP2
FD7 FD6 FD5
68_1206_8P4R_5%
RP3
5
AFD#/3M#LPTBUSY
4
LPTERR#
3
LPTINIT#
2
LPTSLCTIN#
1
2.7K_1206_10P8R_5%
RP4
5
FD0
4
FD1
3
FD2
2
FD3
1
2.7K_1206_10P8R_5%
+5V_PRN
+5V_PRN
B
LPTSTB#
AFD#/3M#
LPTAFD# FD0 LPTERR# FD1 INIT# FD2 SLCTIN# FD3
FD4
FD5
FD6
FD7
LPTACK#
LPTBUSY
LPTPE
LPTSLCT
2 1
+5VS
RB420D_SOT23
R3
1 2
47_0402_5%
1 2
R4 33_0402_5%
1 2
33_0402_5%
R5
1 2
33_0402_5%
R6
D1
+5V_PRN
LPTINIT#
LPTSLCTIN#
12
R2
2.2K_0402_5%
1 2
JP11
1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9 22 10 23 11 24 12 25 13
SUYIN_070536FR025S204ZU
FIR Module
+3VS
C1
220P_0402_50V8K
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY ORDISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC .
C
FIR_EN# Low FIR poped High FIR un-poped
FIR_EN#
+3VS
R65 47_ 1206_5%
1 2
1
C25
4.7U_0805_10V4Z
2
1 2
R295
1
C37
100P_0805_50V8K
2
0_0402_5%
D
IRRX
+IR_VCC
1
C32
0.1U_0402_16V4Z
2
+IR_GND
SD/MODE: SHUTDOWN MODE, HIGH ACTIVE MODE: HIGH/LOW SPEED SELECT
3.3_1206_5%
@3.3_1206_5%
1 3
TXD
5 7
MODE
+IR_ANODE
+
IRTX IRMODE
60mil
1
C310 @150U_D2_6.3VM
2
E
1 2
R53
1 2
R58
1
C21
22U_1206_16V4Z
2
U40
2 4 6 8
IR_VISHAY_TFDU6101E-TR4_8P
IRED_A
IRED_C
SD/MODE
RXD VCC GND
Compal Electronics, Ltd.
Title
LPC-Super I/O
Size Document Number Re v
Custom
LA-1931
Date: Sheet
31 47Monday, June 09, 2003
0.2
of
Parallel Port
3 3
CP7
2 3 4 5
220P_1206_8P4C_50V8K
CP10
8 1 7 6
220P_1206_8P4C_50V8K
CP9
8 1 7 6
220P_1206_8P4C_50V8K
CP8
2 3 4 5
4 4
220P_1206_8P4C_50V8K
LPTSLCTIN#
81
LPTINIT#
7
LPTERR#
6
AFD#/3M#
LPTACK#
LPTBUSY
2
LPTPE
3
LPTSLCT
45
FD0 FD1
2
FD2
3
FD3
45
FD4
81
FD5
7
FD6
6
FD7
A
+5V_PRN
+5V_PRN
LPTACK#
6 7
LPTPE
8
LPTSLCT
9
10
FD7
6
FD6
7
FD5
8
FD4
9
10
LPD0
1 8
LPD1
2 7
LPD2 FD2
3 6
LPD3 FD3
4 5
LPD7
1 8
LPD6
2 7
LPD5
3 6
LPD4 FD4
4 5
5
0.1U_0402_16V4Z
1
C416
2
0.1U_0402_16V4Z
D D
10K_0402_5%
GATEA20<17>
KBRST#<17>
C C
1394_PME#<20>
WLANPME#<25>
ICH_WAKE _UP#<17>
PCM_PME#<21>
LAN_PME#<23>
ECAGND
B B
+5VALW
1 2
4.7K_040 2_5%
R355
1 2
4.7K_040 2_5%
R356
+3VALW
R458 100K_0402_5%
Ra
1 2
A A
R453 0_0402_5%
Rb
1 2
Analog Board ID definition, Please see page 3.
0.1U_0402_16V4Z
1
1
C538
C449
2
2
0.1U_0402_16V4Z
+EC_AVCC
L38
1 2
CHB1608U800_0603
1
C554
0.1U_0402_16V4Z
2
ECAGND
+3VS
R381
1 2
C527 0.01U_0402_25V4Z
+3VALW
RP7
1 8 2 7 3 6 4 5
10K_12 06_8P4R_5%
EC_SMC2
EC_SMD2
AD_BID0
1
C559
0.1U_0402_16V4Z
2
1
C414
2
1000P_0402_50V7K
+3VALW
CLK_LPC_EC<14>
R371 10K_0402_5%
D18
1 2
2 1
RB751V
D17
2 1
RB751V
1 2
R412 0_0402_5%
1 2
R399 0_0402_5%
1 2
R377 @0_0402_5%
1 2
R369 0_0402_5%
1 2
R390 0_0402_5%
BATT_TEMP
12
MODE# FRD# SELIO# FSEL#
47K_0402_5%
10K_0402_5%
10K_0402_5%
Board ID
5
2
C586
1
EC_GA20
EC_KBRST#
R353
12
R531
12
R532
12
3 4 5 6
+3VALW
2
C412
1000P_0402_50V7K
1
+3VALW
+3VALW
R415 10K_0402_5%
1 2
VR_ON
SYSON
SUSP#
Rb
33K+-1%
56K+-1%
100K+-1%
200K+-1%
+3VS
LPC_AD[0..3]<18,31>
12
R416 @33_0402_5%
1
C472 @22P_0402_25V8K
2
12
R419 4. 7K_0402_5%
EC_PME#
R400 0_0402_5%
SERIRQ<17,21,31>
LPC_DRQ#0<18>
LPC_F RAME#<18,31>
EC_RST#
+RTCVCC
CRY1
1
2
4
1 2
R391 @0_0402_5%
LPC_AD[0..3]
EC_SCI#<18>
EC_PLAYBTN#<34> EC_STOPBTN#<34> EC_REVBTN#<34> EC_FRDBTN#<34> TV_OUT_EN#<34>
1
C415
0.1U_0402_16V4Z
2
pin110 reserve for KSO16
KSO17<34>
PM_SLP_S1#<14,18>
TP_CLK<34>
TP_DATA<34>
LID_SW#<34,36>
HDD_LED#<34>
EC_SMI#<18>
S4_DATA<36>
WL_OFF#<25>
EC_SWI#<18>
S4_LATCH<36>
SYSON<36,37,42> SUSP#<21,2 8,33,37,43>
VR_ON<44>
PCMRST#<22> EC_RSMRST#<18> SHDD_LED#<26>
ENBKL<8> BKOFF#<16>
FSEL#<33>
R136
CRY2
1 2
20M_0603_5%
X1
32.768KHZ_12.5PF_CM155
C124
10P_0402_50V8K
4
1
C463
0.1U_0402_16V4Z
2
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
EC_RST#
EC_SCI#
EC_GA20 EC_KBRST#
EC_TINT# EC_TCK EC_TDO EC_TDI EC_TMS
TP_CLK TP_DATA
EC_SMI#
SYSON SUSP# VR_ON
BKOFF#
FSEL#
R134 120K_0402_5%
1 2
1
C106
12P_0402_5 0V8J
2
+EC_VDD
U24
7
SERIRQ
8
LDRQ#
9
LFRAME#
15
LAD0
14
LAD1
13
LAD2
10
LAD3
18
LCLK
19
RESET1#
22
SMI#
23
PWUREQ#
31
IOPD3/ECSCI#
5
GA20/IOPB5
6
KBRST/IOPB6
KSI0
71
KBSIN0
KSI1
72
KBSIN1
KSI2
73
KBSIN2
KSI3
74
KBSIN3
KSI4
77
KBSIN4
KSI5
78
KBSIN5
KSI6
79
KBSIN6
KSI7
80
KBSIN7
KSO0
49
KBSOUT0
KSO1
50
KBSOUT1
KSO2
51
KBSOUT2
KSO3
52
KBSOUT3
KSO4
53
KBSOUT4
KSO5
56
KBSOUT5
KSO6
57
KBSOUT6
KSO7
58
KBSOUT7
KSO8
59
KBSOUT8
KSO9
60
KBSOUT9
KSO10
61
KBSOUT10
KSO11
64
KBSOUT11
KSO12
65
KBSOUT12
KSO13
66
KBSOUT13
KSO14
67
KBSOUT14
KSO15
68
KBSOUT15
105
TINT#
106
TCK
107
TDO
108
TDI
109
TMS
110
PSCLK1/IOPF0
111
PSDAT1/IOPF1
114
PSCLK2/IOPF2
115
PSDAT2/IOPF3
116
PSCLK3/IOPF4
117
PSDAT3/IOPF5
118
PSCLK4/IOPF6
119
PSDAT4/IOPF7
CRY1
158
32KX1/32KCLKIN
CRY2
160
32KX2
62
IOPJ2/BST0
63
IOPJ3/BST1
69
IOPJ4/BST2
70
IOPJ5/PFS
75
IOPJ6/PLI
76
IOPJ7/BRKL_RSTO
148
IOPM0/D8
149
IOPM1/D9
155
IOPM2/D10
156
IOPM3/D11
3
IOPM4/D12
4
IOPM5/D13
27
IOPM6/D14
28
IOPM7/D15
173
SEL0#
174
SEL1#
47
CLK
PC875 91L-V PCN01 A2_LQFP176
16
VDD
Host interface
Key matrix scan
JTAG debug port
PS2 interface
PORTM
GND117GND235GND346GND4
PROPRIETARY NOTE
3
KBA[0..18]
ADB[0..7]
BATT_TEMPA <39> ADP_I <40,43> BATT_OVP <40>
ALI/M H# <39,43> EMAIL# <34> MODE# <34> INTERNET# <34>
DAC_BRIG <16> EN_DFAN2 <34> IREF <40> EN_DFAN1 <34>
INVT_PWM <16> BEEP# <30> PWR_SUSP_ LED <34> ACOFF <40> KILL_SW# <25,34> EC_ON <34> EC_LID_OUT# <18>
EC_SMC1 <33,39> EC_SMD1 <33,39> PCIRST# <8,15,17,20,21,22,23,25,26,31>
PBTN_OUT# <18> EC_SMC2 <5> EC_SMD2 <5> FAN_SPEED1 <34>
EC_THERM# <18> FAN_SPEED2 <34>
ACIN <17,34,38> CD_PLAY PM_SLP_S3# <14,18>
ON/OFF <34> PM_SLP_S5# <18>
PM_CLKRUN# <18,21,23,25,31>
FRD# <33> FWR# <33>
SELIO# <33>
PHDD_LED# <26>
FSTCHG <40>
AD0 AD1 AD2 AD3
DA0 DA1 DA2 DA3
IOPC0
IOPD4 IOPD5 IOPD6 IOPD7
98
1 2
KBA[0..18]<33>
ADB[0..7]<33>
BATT_TEMPB
BATT_TEMP
81
VBATTA
82 83
VBATTB
84 87 88 89 90
AD_BID0
93 94
99 100 101 102
INVT_PWM
32 33 36 37 38 39 40 43
EC_URXD
153
EC_UTXD
154
EC_USCLK
162
EC_SMC1
163
EC_SMD1
164 165
168
EC_SMC2
169
EC_SMD2
170 171
EC_PME#
172
EC_THERM#
175 176 1
ACIN
26 29 30
2 44 24 25
KBA0
124
KBA1
125
KBA2
126
KBA3
127
KBA4
128
KBA5
131
KBA6
132
KBA7
133
ADB0
138
ADB1
139
ADB2
140
ADB3
141
ADB4
144
ADB5
145
ADB6
146
ADB7
147
FRD#
150 151
SELIO#
152
41
NUM_LED#
42
CAPS_LED#
54
PADS_LED#
55
KBA8
143
KBA9
142
KBA10
135
KBA11
134
KBA12
130
KBA13
129
KBA14
121
KBA15
120
KBA16
113
KBA17
112
KBA18
104
KBA19
103 48
L34
CHB160 8U800_0603
+RTCVCC
+EC_AVCC+3VALW
123
136
95
157
166
VCC134VCC245VCC3
VCC4
VCC5
VCC6
AD Input
DA output
PWM or PORTA
PORTB
PORTC
PORTD-1
PORTE
PORTH
PORTJ-1
PORTJ-2
PORTD-2
PORTK
PORTL
AGND
GND5
GND6
GND7
96
122
159
167
137
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY ORDISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC .
161
VBAT
AVCC
IOPE0AD4 IOPE1/AD5 IOPE2/AD6 IOPE3/AD7
DP/AD8 DN/AD9
IOPA0/PWM0 IOPA1/PWM1 IOPA2/PWM2 IOPA3/PWM3 IOPA4/PWM4 IOPA5/PWM5 IOPA6/PWM6 IOPA7/PWM7
IOPB0/URXD
IOPB1/UTXD
IOPB2/USCLK
IOPB3/SCL1
IOPB4/SDA1
IOPB7/RING/PFAIL/RESET2
IOPC1/SCL2
IOPC2/SDA2
IOPC3/TA1
IOPC4/TB1/EXWINT22
IOPC5/TA2
IOPC6/TB2/EXWINT23
IOPC7/CLKOUT
IOPD0/RI1/EXWINT20 IOPD1/RI2/EXWINT21
IOPD2/EXWINT24/RESET2
IOPE4/SWIN
IOPE5/EXWINT40
IOPE6/LPCPD/EXWIN45
IOPE7/CLKRUN/EXWINT46
IOPH0/A0/ENV0
IOPH1/A1/ENV1 IOPH2/A2/BADDR0 IOPH3/A3/BADDR1
IOPH4/A4/TRIS
IOPH5/A5/SHBM
IOPH6/A6 IOPH7/A7
IOPI0/D0 IOPI1/D1 IOPI2/D2
IOPK5/A13_BE0
IOPK6/A14_BE1
IOPK7/A15_CBRD
NC212NC320NC421NC585NC686NC791NC892NC997NC10
NC1
11
3
IOPI3/D3 IOPI4/D4 IOPI5/D5 IOPI6/D6 IOPI7/D7
IOPJ0/RD
IOPJ1/WR0
SELIO#
IOPK0/A8
IOPK1/A9 IOPK2/A10 IOPK3/A11 IOPK4/A12
IOPL0/A16 IOPL1/A17 IOPL2/A18 IOPL3/A19
IOPL4/WR1#
PORTI
ECAGND
2
KEYBOARD CONN.
JP9
NUM_LED#
34
PADS_LED#
33
CAPS_LED#
32 31
KSO15
30
KSO14
29
KSO10
28
KSO11
27
KSO8
26
KSO9
25
KSO13
24
KSI7
23
KSO3
22
KSO7
21
KSO12
20
KSI4
19
KSI6
18
KSI5
17
KSO6
16
KSO5
15
KSI3
14
KSI0
13
KSO0
12
KSO1
11
KSI1
10
KSI2
9
KSO2
8
KSO4
7 6 5 4 3 2 1
ACES_88170-3400
BADDR1(KBA3) BADDR0(KBA2)
0
0
*
11
TP_CLK
TP_DATA KBA5
2
0
1
01
IRE
*
OBD 0 DEV 0 PROG
SHBM(KBA5)=1: Enable shared memory with host BIOS TRIS(KBA4)=1: While in IRE and OBD, float all the
signals for clip-on ISE use
1 2
4.7K_0 402_5%
R417
1 2
4.7K_0 402_5%
R414
Title
Size Document Number Re v
Custom
Date: Sheet
1
For EC Tools
JP7
1
1
EC_TINT#
2
2
EC_TCK
3
3
EC_TDO
4
4
EC_TDI
5
5
EC_TMS
6
6
7
7
EC_URXD
8
8
EC_UTXD
9
9
EC_USCLK
10
10
@E&T_96212-1011S
CP6
KSO15 KSO14
6
KSO10
7
KSO11
8 1
R235
1 2
300_0402_5%
R234
1 2
300_0402_5%
R233
1 2
300_0402_5%
+3VS
+3VS
+3VS
100P_1206_8P4C_50V8
CP5
KSO8 KSO9
6
KSO13
7
KSI7
8 1
100P_1206_8P4C_50V8
CP4
KSO3 KSO7
6
KSO12
7
KSI4
8 1
100P_1206_8P4C_50V8
CP3
KSI6 KSI5
6
KSO6
7
KSO5
8 1
100P_1206_8P4C_50V8
CP2
KSI3 KSI0
6
KSO0
7
KSO1
8 1
100P_1206_8P4C_50V8
CP1
KSI1 KSI2
6
KSO2
7
KSO4
8 1
100P_1206_8P4C_50V8
I/O Address
Index
Data
2E 2F
4E
4F
(HCFGBAH, HCFGBAL) (HCFGBAH, HCFGBAL)+1
Reserved
+5VS
ENV1 (KBA1)
0
1 1
KBA1
KBA2
KBA3
0 1
1
0
0
0
0
1 2
R388 1K_0402_5%
1 2
R375 @1K_0402_5%
1 2
R364 1K_0402_5%
1 2
R359 1K_0402_5%
ENV0 (KBA0) TRIS (KBA4)
Compal Electronics, Ltd.
LPC- PC87591
LA-1931
32 47Monday, June 09, 2003
1
+3VALW
45 3 2
45 3 2
45 3 2
45 3 2
45 3 2
45 3 2
+3VALW
0.2
of
+5VALW
C51
1 2
0.1U_0402_16V4Z U9
+3VALW
ADB0
1 2
ADB1 ADB2 ADB3 ADB4 ADB5 ADB6 ADB7
AA LARST#SELIO#
C52
1 2
1U_0805_25V4Z
+3VALW
C395
1 2
0.1U_0402_16V4Z
KBA2
SELIO#<32>
14
U15A
1
P
A
O
2
B
G
SN74L VC32APWLE_TSSOP14
7
100K_0402_5%
3
+5VALW
R350
1 2
R73
20K_0402_5%
3
11
1
20
D0
VCC
D14Q1 D27Q2 D38Q3 D413Q4 D514Q5 D617Q6 D718Q7
CP MR
GND
10
2
Q0
5 6 9 12 15 16 19
SN74HC T273PW_TSSOP20
CDON_LED# <34> MP3_LED# <34> E-MAIL_LED # <34> PWR_LED# <34> WL_B T_LED# <34> BATT_LOW_LE D# <34> BATT_CHGI_LED# <34> CD_FDD_LED# <34>
System BIOS SMBus EEPROM
C44
C401
1 2
0.1U_0402_16V4Z
U15B
FWE#
6
SN74L VC32APWLE_TSSOP14
C48
0.1U_0402_16V4Z
1 2
KBA[0..18]<32>
ADB[0..7]<32>
O
+3VALW
14
7
KBA11 KBA9 KBA8 KBA13 KBA14 KBA17 FWE#
KBA18 KBA16 KBA15 KBA12 KBA7 KBA6 KBA5 KBA4
P
G
A
B
+3VALW+3VALW
4
5
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16
KBA[0..18]
ADB[0..7]
R141 100K_0402_5%
1
1 2
U43
A11 A9 A8 A13 A14 A17 WE# VCC A18 A16 A15 A12 A7 A6 A5 A4
@SST39VF040_TSOP
Q12
D
OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0
2N7002_SOT23
2
G
3
S
32 31 30 29 28 27 26 25 24 23 22 21 20
A0
19
A1
18
A2
17
A3
FWR# <32>
FRD# KBA10 FSEL# ADB7 ADB6 ADB5 ADB4 ADB3
ADB2 ADB1 ADB0 KBA0 KBA1 KBA2 KBA3
SUSP# <21 ,28,32,37,43>
FLASH# <18>
FRD# <32>
FSEL# <32>
+3VALW
U42
KBA18
1
A18
KBA16
2
A16
KBA15 KBA17
3
A15
KBA12 KBA14
4
A12
KBA7 KBA13
5
A7
KBA6 KBA8
6
A6
KBA5 KBA9
7
A5
KBA4 KBA11
8
A4
KBA3 FRD#
9
A3
KBA2 KBA10
10
A2
KBA1 FSEL#
11
A1
KBA0
12
A0
ADB0 ADB6
13
DQ0
ADB1
14
DQ1
ADB2 ADB4
15
DQ2
16
VSS
512K8-90_PLCC32
U41
KBA11
1
A11
KBA9
2
A9
KBA8
3
A8
KBA13
4
A13
KBA14
5
A14
KBA17
6
A17
FWE#
7
WE#
8
VCC
KBA18
9
A18
KBA16
10
A16
KBA15
11
A15
KBA12
12
A12
KBA7
13
A7
KBA6
14
A6
KBA5
15
A5
KBA4
16
A4
@29F040_TSOP
VDD WE#
A17 A14 A13
A8
A9 A11 OE# A10 CE#
DQ7 DQ6 DQ5 DQ4 DQ3
OE# A10 CE#
DQ7 DQ6 DQ5 DQ4 DQ3
VSS
DQ2 DQ1 DQ0
A0
A1
A2
A3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY ORDISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
1 2
0.1U_0402_16V4Z
+3VALW
FWE#
ADB7
ADB5
ADB3
FRD# KBA10 FSEL# ADB7 ADB6 ADB5 ADB4 ADB3
ADB2 ADB1 ADB0 KBA0 KBA1 KBA2 KBA3
EC_SMC1<32,39> EC_SMD1<32,39>
4.7K_0402_5%
GND
+5VALW
R244
U34
A0 A1 A2
100K_0402_5%
1 2 1 2 3 4
R241 100K_0402_5%
1 2
33 47Monday, June 09, 2003
+5VALW +5VALW
R236
1 2
+5VALW
C230
1 2
R237
0.1U_0402_16V4Z
4.7K_0402_5%
8
VCC
1 2
Compal Electronics, Ltd.
Title
BIOS & Ext.I/O
Size Document Number R ev
Custom
LA-1931
Date: Sheet
7
WP
6
SCL
5
SDA
AT24C16N-10SI-2.7_SO8
0.2
of
5
SW BOARD Connector
(Top contact)
+5VALW
12
R522 10K_0402_5%
D D
R494
1K_0402_5%
Q35
2
G
+3VS
1 2
2
3 1
MMBT3904_SOT23
PWR_SUSP_ LED<32>
+5VALW
1
C614
1U_0603_10V6K
2
HDD_LED#<32>
C C
FAN CONN
1
1
C642
0.1U_0402_16V4Z
EN_DFAN1<32>
B B
2
2
R510
10K_0402_5%
C640
0.1U_0402_16V4Z
EN_DFAN1
12
+12VALW
3
2
R514
13
D
Q43 2N7002_SOT23
S
+5VALW
8
U49A
P
+IN
OUT
-IN G
LM358A_SO8
4
1 2
FAN_SPEED1<32>
SUSP_LED#
R499
10K_0402_5%
1 2
1
8.2K_040 2_5%
MODE#<32>
51ON#<38>
EC_REVBTN#<32>
EC_FRDBTN#<32> EC_PLAYBTN#<32> EC_STOPBTN#<32>
PWR_LED#<33>
BATT_LOW_LED#<33> BATT_CHGI_LED#<33>
CD_FDD_LED#<33>
CDON_LED#<33>
MP3_LED#<33>
E-MAIL_LED #<33>
R501
1 2
100_0402_5%
C620
0.1U_0402_16V4Z
+3VS
1 2
+5VALW +5VALW
KSO17<32>
ACIN<17,32,38>
FMMT619_SOT23
2
1
1N4148_SOT23
R516 10K_0402_5%
FAN CONN. 2
5
+IN
6
-IN
1 2
R511
U49B
OUT
LM358A_SO8
8.2K_040 2_5%
FAN_SPEED2<32>
7
EN_DFAN2<32>
A A
EN_DFAN2
R509
10K_0402_5%
5
12
R508
1 2
100_0402_5%
0.1U_0402_16V4Z
R354
10K_0402_5%
FMMT619_SOT23
2
C631
1
+3VS
1 2
4
Touch Pad Connector
TP_CLK
TP_CLK<32>
51ON#
1
C
E3B
1
1000P_0402_50V7K
3
1000P_0402_50V7K
1
C
E3B
1
1000P_0402_50V7K
3
1000P_0402_50V7K
4
+5VS
2
2
TP_DATA
D38
1SS355
C636
C639
1SS355
C641
C644
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
D40
TP_DATA<32>
KSO17 EC_REVBTN# EC_FRDBTN# EC_PLAYBTN# EC_STOPBTN#
SUSP_LED#
FAN CONN. 1
+5VALW
Q37
2
D39
+5VALW
Q39
2
1N4148_SOT23
D41
1
C608
1U_0603_10V6K
2
JP8
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
E&T_6901-26
2 1
1
2
1
2
2 1
1
2
1
2
KSO17
SUSP_LED#
C648
100P_0402_5 0V8J
For EMI
1
C621
10U_1206_16V4Z
2
1 2 3 4
1
C638
10U_1206_16V4Z
2
1 2 3 4
JP6
1 2 3 4 5 6
ACES_85201-0602
1
2
JP22
1 2 3 4
ACES_85205-0400
JP24
1 2 3 4
ACES_85205-0400
3
LID_SW#
LID_SW#<32,36>
100K_0402_5%
LID_SW#
V-PORT-0603-220 M-V05_0603
D8
R23
+3VALW
12
2 1
SW1
2 5
ESE24MV1T_6P
2
1 6
3 4
TV-OUT BUTTON
SMT1-05_4P
SW5
3
1
KSO17
2
1
C649
100P_0402_5 0V8J
2
4
5
6
V-PORT-0603-220 M-V05_0603
Internet Button User Button & E-MAIL SW
3
2
Q22
S
G
SMT1-05_4P
SW3
1
2
D
1
3
4
5
6
NDS35 2AP_SOT23
D2
51ON#
12
R275
0_0603_5%
D28 1N4148_SOT23
2
3
1
3
2 1
1
TV_OUT_EN# <32>
3
1
2
PSOT24C_SOT23 D26
+3VALW
R7 100K_0402_ 5%
R280 10 0K_0402_5%
INTERNET#
2
D25 1N4148_SOT23
Power Button
3
2
D27
PSOT24C_SOT23
1
SW2
3
1
2
SMT1-05_4P
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY ORDISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC .
4
5
6
EC_ON<32>
2N7002_SOT23
3
EC_ON
Q23
+3VALW
D
S
D29 DAN202U_SC70
1
R291
4.7K_0402_5%
R292
1 2
1 2
33K_0402_5%
13
2
G
+3VALW
2
1 2
3
1
O
DTC124EK_SC59
R286 100K_0402_5%
51ON#
Q24
C292
G
3I2
1000P_0402_50V7K
2
1
2
Kill SWITCH
SW6
1
1
2
2
3
3
DS-1208_3P
V-PORT-0603-220 M-V05_0603
WIRELESS ACTIVE AMB LED
HP HSMG-C170 AMB 0805
WL_BT_LED#<33>
12
12
INTERNET# <32>
SMT1-05_4P
ON/OFF# <36>
WL_ BT_LED#
SW4
1
2
5
6
2
EMAIL#
INTERNET#
2
3
3
4
RTC BATT
BATT1
-
ON/OFF <32>
ML1220T13RE
12
D31 RLZ20A_LL34
Title
Size Document Number Re v
Custom
Date: Sheet
+RTCVCC
C222
0.1U_0402_16V4Z
Compal Electronics, Ltd.
System Connectors
LA-1931
D10
31
47K
B
10K
C
1N4148_SOT23 D3
1
3
+
+RTCBATT
12
1
2
1
+3VALW
R68 100K_0402_5%
1 2
2 1
D11
E
Q4 DTA114YKA_SOT23
3
1
2
1
+RTCBATT
3
1
KILL_SW# <25,32>
R109
21
120_0402_5%
EMAIL#
2
D4 1N4148_SOT23
D5 PSOT24C_SOT23
C224
0.1U_0402_16V4Z
1 2
1
D21 BAS40-04_SOT23
2
+CHGRTC
34 47Monday, June 09, 2003
12
+3VALW
EMAIL# <32>
of
0.2
A
Power Good Circuit
+3VS
1 1
R479
180K_0402_5%
12
2
C610 1U_08 05_25V4Z
1
+3V +3V
14
U31C
P
5
O6I
G
SN74L VC14APWLE_TSSOP14
7
14
U31D
P
9
O8I
G
SN74L VC14APWLE_TSSOP14
7
B
12
R460
100K_0402_5%
SYS_PW ROK <8,18>
C
FD1 FIDUCAL
1
FD5 FIDUCAL
1
CF2 SMD40M80
1
CF8 SMD40M80
1
CF5 SMD40M80
1
FD3 FIDUCAL
1
FD6 FIDUCAL
1
CF14 SMD40M80
CF21 SMD40M80
1
1
FD2 FIDUCAL
1
FD4 FIDUCAL
1
CF1 SMD40M80
1
CF16 SMD40M80
1
CF6 SMD40M80
1
CF17 SMD40M80
1
CF7 SMD40M80
1
D
CF18 SMD40M80
1
CF11 SMD40M80
1
CF20 SMD40M80
1
CF9 SMD40M80
1
CF12 SMD40M80
1
CF4 SMD40M80
1
E
VID_PWRGD
+3V
12
10
OE#
I9O
R132 10K_0402_5%
1 2
R131 0_0402_5%
VID_PWRGD <44>
ENLL <44>
2 2
U16C
H_VID_PW RGD<5>
8
SN74L VC125APWLE_TSSOP14
+3V POWER
H1
H_S315D110
1
H29
H_S315D110
1
H4
H_C315D142
1
H_S315D110
H_S315D110
H_C315D142
H3
H10
H2
H_S315D110
H_S315D110
1
1
H33
H30
1
H9
1
H_S315D110
1
H5
H_C315D142
1
H_S315D110
H_C315D142
H14
H_S315D110
1
1
H34
H35
H_S315D110
1
1
H8
1
H41
H_C118D118N
1
H6
3 3
+3V
13
U16D
11
OE#
4 4
I12O
SN74L VC125APWLE_TSSOP14
A
+3V +3V
14
U31E
P
11
O10I
G
SN74L VC14APWLE_TSSOP14
7
14
U31F
P
13
O12I
G
SN74L VC14APWLE_TSSOP14
7
B
+3VALW +3VALW
14
U15C
9
P
A
8
O
10
B
G
SN74L VC32APWLE_TSSOP14
7
14
U15D
12
P
A
O
13
B
G
SN74L VC32APWLE_TSSOP14
7
11
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY ORDISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC .
C
H_S315D181
H_C121D98
H_C335D91
H_O85X118D85X118N
H23
H_S315D181
1
1
H13
H27
H_C121D98
1
1
H18
1
H16
1
H25
H_C335D91
1
H21
H_C63D63N
1
H_O63X102D63X102N
H7
1
H15
1
H19
1
H_C85D85N
H12
H_C276D142
1
H24
1
H28
H_O201X162D201X162N
1
Title
Size Document Number Re v
Custom
Date: Sheet
H_C276D142
H_S315D118
H_C335D142
H20
1
D
H11
H_C197D91
H_C276D91
H31
H_C181D161
1
H_O315X236D315X236N
H26
H_C197D91
1
1
H32
1
H22
H_C276D91
1
H17
1
Compal Electronics, Ltd.
PowerGood
LA-1931
35 47Monday, June 09, 2003
E
0.2
of
A
1 1
B
C
D
E
+RTCVCC
2 2
3 3
LID_SW#<32,34>
J2
@JOPEN
12
J5
12
@JOPEN
R110
100K_0402_5%
D12
RB751V
S4_LATCH<32>
+RTC_VREF
12
100K_0402_5%
21
+3VALW
1 2
R114 10K_0402_5%
S4_DATA<32>
+RTC_VREF +RTC_VREF +RTC_VREF
12
R107
620K_0402_5%
1 2
C71 1U_0805_25V4Z
13
D
Q7
2
2N7002_SOT23
G
S
R115
12
1
D13 1N4148_SOT23
3
2
+RTC_VREF
1 2
R111 10K_0402_5%
+RTC_VREF
J3
12
@JOPEN
J4 @JOPEN
D14
2 1
RB751V
C83
1 2
1U_0805_16V7K
12
C59 0.1U_0402_16V4Z
1 2
5
2
4
U13 NC7SZ14M5X
3
SYSON<32,37,42>
U14
1
CD1#
VCC
2
D1
CD2#
3
CP1
D2
4
SD1#
CP2
5
Q1
SD2#
6
Q1#
Q2
7
GND
Q2#
74LCX74
D_SET_S4
1 2
R112 10K_0402_5%
J1
@JOPEN
+RTC_VREF
14 13 12 11 10 09 08
J6
12
@JOPEN
13
D
Q10
2
2N7002_SOT23
G
S
13
D
12
Q8
2
2N7002_SOT23
G
S
13
D
Q11
2
2N7002_SOT23
G
S
ON/OFF# <34>
4 4
Compal Electronics, Ltd.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY ORDISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC .
C
D
AC-IN-Mode-Hibern ation
Size Document Number Re v
Custom
LA-1931
Date: Sheet
36 47Monday, June 09, 2003
E
of
0.2
A
+1.5VALW To + 1.5V Transfer
+1.5V+1.5VALW
U38
1
8
S
D
2
7
S
D
3
6
S
D
5
D
1
C280
1 1
SI4800DY_SO8
4.7U_0805_10V4Z
2
ON_GATE
4
G
1
C263 1U_06 03_10V4Z
2
4.7U_0805_10V4Z
1
C266
2
1
C265
4.7U_0805_10V4Z
2
B
+1.5VALW To +1 .5VS Tran sfer
+1.5VS+1.5VALW
U39
1
8
S
D
2
7
S
D
3
6
S
D
5
D
1
SI4800DY_SO8
C286
4.7U_0805_10V4Z
2
+5VS_GATE
4
G
C
4.7U_0805_10V4Z
1
C264
1U_0603_10V4Z
2
D
+1.5V & +1.5VS Discharge
1
2
C268
1
C267
4.7U_0805_10V4Z
2
+1.5V +1.5VS
12
R252 470_0402_5%
13
SYSON# SUSP
D
2
Q20
G
2N7002_SOT23
S
E
12
R223 1K_0402_5%
13
D
2
Q17
G
2N7002_SOT23
S
+3VALW To +3V Transfer +3VALW To +3VS Transfer +3V & +3VS Discharge
+3VALW +3V
1
C89
4.7U_0805_10V4Z
2 2
2
U19
8
D
7
D
6
D
5
D
SI4800DY_SO8
S S S
G
ON_GATE
1 2 3 4
C92
4.7U_0805_10V4Z
1
2
1
C87 1U_08 05_25V4Z
2
+3VALW
1
C55
4.7U_0805_10V4Z
2
U10
8
D
7
D
6
D
5
D
SI4800DY_SO8
+5VS_GATE
C54
10U_1206_16V4Z
1
2
1
S
2
S
3
S
4
G
1U_0603_10V4Z
1
2
10U_1206_16V4Z
C46
1
2
10U_120 6_16V4Z
C50
+3VS
1
2
1
C41
C43
10U_1206_16V4Z
2
+3V +3VS
SYSON#
2
G
12
R201 470_0402_5%
13
D
Q14 2N7002_SOT23
S
SUSP
12
R77 1K_0402_5%
13
D
2
Q3
G
2N7002_SOT23
S
+5VALW To +5V Transfer +5V & +5VS Discharge+5VALW To +5VS Transfer
U35
1
8
S
D
2
7
S
D
3
6
S
D
4
5
G
R251 100K
2
G
D
SI4800DY_SO8
1 2
1M_0402_5%
12
R108 10K_0402_5%
13
D
Q6 2N7002_SOT23
S
R249
12
1
C233
4.7U_0805_10V4Z
3 3
4 4
2
+12VALW
SYSON<32,36,42>
1
C245
4.7U_0805_10V4Z
2
ON_GATE +5VS_GATE
1
C242
2
0.1U_0402_16V4Z
13
D
S
SUSP#<21 ,28,32,33,43>
1
2
SYSON#
2
G
Q19 2N7002_SOT23
C244
1U_0805_25V4Z
SUSP#
2
G
+5VALW+5VALW
12
13
4.7U_0805_10V4Z
R104
4.7K_0402_5%
D
Q9 2N7002_SOT23
S
+5VALW
1
C232
SUSPSYSON#
+12VALW
2
U33
8
D
7
D
6
D
5
D
SI4800DY_SO8
R246 100K
1M_0402_5%
12
R245
S S S G
1 2 3 4
12
+5VS+5V+5VALW
1
C243
4.7U_0805_10V4Z
2
1
C240
2
0.1U_0402_16V4Z
0.1U_ 0402_10V6K
13
D
2
G
Q21
S
2N7002_SOT23
1
1
C252
C239
4.7U_1206_25VFZ
2
2
SUSP
1
C249
4.7U_1206_25VFZ
2
1
C246
4.7U_1206_25VFZ
2
12
R239 470_0402_5%
13
SYSON# SUSP
D
2
Q18
G
2N7002_SOT23
S
+5VS+5V
12
R92 1K_0402_5%
13
D
2
Q5
G
2N7002_SOT23
S
Compal Electronics, Ltd.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY ORDISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC .
C
D
DC/DC Interf ace
Size Document Number Re v
Custom
LA-1931
Date: Sheet
37 47Monday, June 09, 2003
E
of
0.2
A
PL14
1 2
C8B BPH 853025_2P
12
PC113
100P_0603_50V8J
PCN1
1
6
G
5
G
4
G
2
3
G
1 1
SINGA_2 DC-S113L200
1
2
PF2 12 A_65VDC_451012
21
12
EC10QS0 4_SOD106
PD28
12
PC112
1000P_0603_50V7K
VIN
B
12
PC114
1000P_0603_50V7K
VIN
12
PC115
100P_0603_50V8J
12
PC116
1000P_0603_50V7K
VIN
12
PR130
84.5K_0603_1%
12
PR133
20K_0603_1%
1 2
PR132 22K_0603_5%
12
PC117
0.1U_0603_50V4Z
C
PR135 10K_0603_1%
1 2
PR128 1M_0603_1%
VS
8
PU14A
3
P
+
2
-
G
LM393M_SO8
4
12
1
O
RTCVREF
3.3V
VS
12
PR129
5.6K_0603_5%
12
PD1
RLZ4.3B_ LL34
1 2
PR131 1K_0603_5%
PACIN
12
PR134 10K_0603_1%
D
ACIN <17,32,34>
PACIN <40,41,43>
Vin Detector
High 18.764 17.901 17.063 Low 17.745 16.903 16.038
PZD2
BATT+
2 2
CHGRTCP N3N1
51ON#<34>
3 3
+CHGRTC
+2.5VP +2.5V
+1.5VALWP
4 4
+12VALWP
+5VALWP
+3VALWP
PR152
1 2
200_0603_5%
PJP2
1 2
PAD-OPEN 3x3m
2 1
PAD-OPEN 3x3m
2 1
PAD-OPEN 2x2m PJP9
1 2
PAD-OPEN 3x3m PJP10
1 2
PAD-OPEN 3x3m
PJP6
RB751V_SOD323
PR151
1 2
200_0603_5%
PR141 22K_0603_5%
PR149
1 2
200_0603_5 %
PJP7
12
1 2
+1.5VALW
+12VALW
+5VALW
+3VALW
A
12
PC118
0.22U_1 206_25V7K
PU15 S-81233SGUP-T1_SOT89
3
3
1
1
1U_0805_25V4Z
RTCVREF
12
12
PR139 100K_0603_5%
3.3V
PC124 10U_1206_10V4Z
(8.5A,340mils ,Via NO.= 142)
(4A,160mils ,Via NO.= 8)
(300mA,20mils ,Via NO.= 1)
(8A,320mils ,Via NO.= 16)
(5A,200mils ,Via NO.= 10)
2
3
2
2
PC123
PQ46 TP0610T_SOT23
S
D
G
12
PR145 200_0603_5%
12
1
PD29
1N4148_SOD80
1 2
12
PR137 33_1206_5%
VS
12
PC119
0.1U_0603_50V4Z
PD4
RLZ16B_LL34
2 1
PJP3
+1.25VSP
1 2
PAD-OPEN 2x2m
(900mA,40mils ,Via NO.= 2)
PJP5
+1.2VP
2 1
PAD-OPEN 2x2m
(30mA,40mils ,Via NO.= 2)
B
1 2
PR1361K_1206_5%
PD31
VIN
VL
MAINPWON<39,41>
ACON<40>
12
1N4148_SOD80
1 2
PR142 10K_0603_1%
RB715F_SOT3 23
2
3
PD32
1
1 2
PR1381K_1206_5%
1 2
PR140 1K_1206_5%
6.0V
7
O
12
PC121 1000P_0603_50V7K
12
PR143 1M_0603_1%
8
PU14B
5
P
+
6
-
G
LM393M_SO8
4
12
PC122
0.1U_0603_50V4Z
Precharge detector
15.34 15.90 16.48
+1.25VS
+1.2V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEE T NOR THE IN FORMATION IT C ONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN C ONSENT OF COMPAL EL ECTRONICS , INC.
13.13 13.71 14.20
C
B+
12
PR144 499K_0603_ 1%
12
2
1
G3I
PQ47 2N7002_SOT23
O
PR146 499K_0603_ 1%
PR150 47K_0603_5%
2
D
12
PR147 10K_0603_1%
1 2
RTCVREF
3.3V
Title
Size Document Number Re v
B
Date: Sheet
PR148 215K_0603_1%
1
D
S3G
Compal Electronics, Ltd.
DCIN/DECTOR
LA-1931
12
PACIN
12
PQ48 DTC115EKA_SC59
+5VALWP
PC120 1000P_0603_50V7K
of
38 47Monday, June 09, 2003
0.2
A
B
C
D
PH1 under CPU botten side :
CPU thermal protection at 84 degree C Recovery at 44(45) degree C
1 1
PCN2
BATT+ BATT+
ID B/I TS
SMD
10 11
SMC
GND
GND­GND-
GND
SUYIN_200275MR009G116ZL
1 2
BLI/NIM H#
3
BB/I
4
TS
5
EC_SMDA
6
EC_SMCA
7 8 9
100_0603_5%
PR113
12
PR114
100_0603_5 %
12
PR110 1K_0603_5%
12
PR116 1K_0603_5%
12
1
PF1
12A_65V DC_451012
1 2
PR11147K_0603_5%
3
PD22
2
21
BAS40-04_SOT23@
1 2
PR119 25.5K_0603_1%
2 2
12
PR121 1K_0603_5%
1
3
2
PD24
BAS40-04_SOT23@
+3VALWP
+3VALWP
VMB
C8B BPH 853025_2P
12
PC106 1000P_0603_50V7K
PL13
1 2
ALI/MH# <32,43>
12
PC107
0.01U_0 603_50V7K
BATT+
0.22U_1 206_25V7K
VL VS
10K_TSM1A-103(F4D3R)_0603_1%
12
PH1
1 2
PR115 16.9K_0603_1%
12
PR117
12
PC108
3.32K_0603_1%
PC109
1000P_0603_50V7K
12
PC105
0.1U_0603_50V4Z
TM_REF1
12
1 2
3
+
2
-
PR118 100K_0603_1%
12
PR120 100K_0603_1%
PR112 47K_0603_1%
8
PU13A
P
O
G
LM393M_SO8
4
12
1
VL
VL
PR109 47K_0603_1%
1 2
1SS355_SOD323
PD23
PQ45 DTC115EKA_SC59
G
MAINPWON <38,41>
1
O
I
3
2
12
BATT_TEMPA <32 >
EC_SMD1 <32,33>
EC_SMC1 <32,33>
1
PD25
BAS40-04_SOT23@
3 3
+5VALWP
4 4
3
A
1
PD26
BAS40-04_SOT23@
2
3
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEE T NOR THE IN FORMATION IT C ONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN C ONSENT OF COMPAL EL ECTRONICS , INC.
PH2 near main Battery CONN :
BAT. thermal protection at 78 degree C Recovery at 39(40) degree C
VL
12
PH2
PC110
0.22U_1206_25V7K
3.92K_0603_0.5%
12
10K_TSM 1A-103(F4D3R)_0603_1%
1 2
PR124
12
PR126
1000P_0603_50V7K
C
16.9K_0603_1%
TM_REF2
12
PC111
1 2
PR123 47K_0603_1%
5
6
12
PR127 100K_0603_1%
8
PU13B
P
+
7
O
-
G
LM393M_SO8
4
12
PR125 10 0K_0603_1%
VL
PR122 47K_0603_1%
1 2
PD27
12
1SS355_SOD323
VL
Compal Electronics, Ltd.
Title
BATTERY CONN / OTP
Size Document Number Re v
B
LA-1931
Date: Sheet
D
of
39 47Monday, June 09, 2003
0.2
A
3
B
C
D
PC90
1 2
4700P_0603_50V7K
PC93
1 2
1000P_0603_50V7K
PC96
0.1U_0603_50V4Z
VMB
12
12
12
Iadp=0~4.2A
PR79
12
0.01_2512_1%
12
PR86 100K _0603_1%
PR90 10K_0603_5%
1 2
PR91 1K_0603_5%
1 2
PR95
12
10K_0603_1%
PR102 340K_0603_1%
PR103 499K_0603_1%
PR153 105K_ 0603_0.5%
PU11
1
-INC2
2
OUTC2
3
+INE2
4
-INE2
5
FB2
6
VREF
7
FB1
8
-INE1
9
+INE1
10
OUTC1
11
OUTD
12
-INC1
MB3887_SSOP24
PR100
1 2
95.3K_0603_1%
PR2
1 2
95.3K_0603_1%
12
PC104
0.01U_0603_50V7K
C8B BPH 853025_2P
+INC2
GND
CS
VCC(o)
OUT
VH
VCC
RT
-INE3
FB3
CTL
+INC1
PL11
1 2
24
23
22
21
20
PC91
1 2
19
0.1U_0603_50V4Z
18
1 2
17
68K_0603_5%
16
1 2
15
47K_0603_5%
14
13
CS
PR92
PR96
ACON
12
PC84
4.7U_1210_25V6K
12
PR85 0_0603_5%
1 2
0.022U_0603_25V7K
1 2
PC88 0.1U_060 3_50V4Z
PC94
1 2
0.1U_060 3_50V4Z
PC95
1 2
1500P_0603_50V7K
4.2V
PC87
12
PC85
4.7U_1210_25V6K
12
PC86
4.7U_1210_25V6K
N18
PD21
RB051L-40_SOD106~D
12
PR101 14 3K_0603_1%
B++
ACOFF#
36
241
PQ40 SI4835DY_SO8
578
LXCHRG
CC=0.5~2.52A CV=16.84V(12 CELLS LI-ION)IREF=0.73~3.3V
PL12
1 2
22UH_SPC-1205P-220A_2.8A_20%
2 1
1 2
0.02_2512_1%
PR94
1 2 3
SI7447DP_SO8
1 2
10K_0603_1%
1
O
G3I
PQ39
4
PR82
PQ41 DTC115EKA_SC59
2
4.7U_1210_25V6K
5
12
PC97
PR83
1 2
47K_0603_5%
12
PC98
4.7U_1210_25V6K
VIN
ACOFF <32>
12
PC99
4.7U_1210_25V6K
BATT+
P2
PQ37
1
S
D
2
S
D
3
S
D
4
G
D
SI4825DY_SO8
PD19
PR87
IREF=1.31*Icharge
IREF<32>
+3VALWP
12
PR99 47K_0603_5%
12
PR81
200K_0603_ 1%
12
PR84 150K_0603_1%
1
PQ42 2N7002_SOT23
D
S
3G2
1 2
1
I
2
12
8 7 6 5
PR80 10K_0603_1%
ACOFF#
1 2
1SS355_SOD323
PACIN
1 2
3K_0603_5%
ACON
VIN
1 1
PACIN
8,41,43>
ACON<38>
2 2
PQ38
4
G
3
S
2
S
1
S
SI4825DY_SO8
PC89
0.1U_060 3_50V4Z
PR93 226K_0603_1%
CS
O
PQ43 DTC115EKA_SC59
G
3
5
D
6
D
7
D
8
D
12
100K_0603_ 1%
ADP_I<32,43>
12
PR89 10K_0603_1%
PR97
P3 B+
12
PR88
33.2K_0603_1%
12
PC92
0.1U_060 3_50V4Z
12
12
1
O
PQ44 DTC115EKA_SC59
G
3 3
FSTCHG<32>
OVP voltage : LI
4S3P : 18V--> BATT_OVP= 2.0V
3S4P/3S3P : 13.5V--> BATT_OVP= 1.5V
(BAT_OVP=0.1111 *VMB)
4 4
I
3
2
VS
12
PC100
0.1U_0603_50V4Z
8
PU12A
3
P
+
1
BATT_OVP<32>
12
12
PC103
0.1U_060 3_16V4Z@
PR107
2.2K_0603_5%
0
2
-
G
4
LM358A_SO8
Compal Electronics, Ltd.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEE T NOR THE IN FORMATION IT C ONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN C ONSENT OF COMPAL EL ECTRONICS , INC.
C
CHARGER
Size Document Number Re v
B
LA-1931
Date: Sheet
D
of
40 47Monday, June 09, 2003
0.2
A
B
C
D
1 1
PC63
G1
8 7 6 5
1 2
0.1U_060 3_50V4Z
PDH31
PDL3
B+++
PL9
1 2
B+
HCB4532K-800T90_1812
4.7U_1210_25V6K
2 2
PC64
12
4.7U_1210_25V6K
12
PC65
12
PL10
12
PC72 47P_0603_50V8J
PQ35
1
D1
2
D1
S1/D2
3
G2
S1/D2
4
S1/D2
S2
SI4814DY_SO8
PR65
1 2
0_0603_5%
PLX3
BST31
PDH3
PD16
1SS355_SOD323
12
PC70
0.1U_060 3_50V4Z
3
2
VS
VL
1 2
1
12
PC69
4.7U_1206_16V4Z
DAP202U_SOT323 PD15
10UH_S PC-1205P-100_4.5A_20%
22
V+
12
21
12OUT
VL
VDD
BST5
DH5 LX5 DL5
PGND
CSH5 CSL5
FB5
SEQ
REF
SYNC
RST#
GND
MAX1632_ SSOP28
8
VL
MAINPW ON <38,39>
4 5 18 16 17 19 20 14 13 12 15 9 6 11
PU10
25
BST3
12
PR68
1
2
0.012_2512_1%
1
+
PC75
2
150U_D2_6.3VM
2 1
+3VALWP
+
PC74
150U_D 2_6.3VM
3 3
PD17
EP10QY03
PR67 1M_0603_1%
1 2
1 2
1 2
12
PR72
3.57K_0603_1%
100P_0603_50V8J
PR74 10K_0603_1%
PC76
PACIN<38,40,43>
CSH3
1 2
PR71 10K_0603_ 1%
VS
12
PR75 47K_0603_5%
27
26 24
1 2
3 10 23
7
28
12
PC125 680P_0603_50V8J
DH3
LX3 DL3
CSH3 CSL3 FB3 SKIP# SHDN#
TIME/ON5
RUN/ON3
PR78
+3.3V Ipeak = 6.66A ~ 10A
12
PC82
0.047U_0603_16V7K
47K_0603_1%
12
PC83
0.047U_0603_16V7K
BST51
+12VALWP
12
POK <42>
PC71
4.7U_120 6_16V4Z
12
1 2
0.1U_0603_50V4Z
2.5VREF
PC77
4.7U_120 6_16V4Z
PC66
4.7U_1210_25V6K
PDH5
PLX5
PR73
10.5K_0603_1%
PC67
12
1 2
PR66 0_0603_5%
PDL5
12
12
PR77
10K_0603_1%
N4
B+++
PC68
12
4.7U_1210_25V6K
12
PC81
100P_0603_50V8J
PC62 470P_0805_100V7K
1 2
PR64
FLYBACKSNB
12
22_1206_5%
PQ36
G1
D1 D1
S1/D2
G2
S1/D2 S1/D2
S2
SI4814DY_SO8
8 7 6 5
12
PDH51
1 2 3 4
12
1
+
PC79
2
150U_D2_6.3VM
+5V Ipeak = 6.66A ~ 10A
PC61
1 2
12
4.7U_1210_25V6K
PD14
EC11FS2_SOD106
PT1
1 4
3 2
10U_SD T-1205P-100-132A_5A_30%
PC73 47P_0603_50V8J
CSH5
PR69 2M_0603_5%
1
+
150U_D2_6.3VM
2
PC80
12
PR70
0.012 _2512_1%
PD18 EP10QY03
2 1
+5VALWP
4 4
Compal Electronics, Ltd.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEE T NOR THE IN FORMATION IT C ONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN C ONSENT OF COMPAL EL ECTRONICS , INC.
C
5V/3V/12V
Size Document Number Re v
B
LA-1931
Date: Sheet
D
of
41 47Monday, June 09, 2003
0.2
A
B
C
D
1 1
12
PC126
4.7U_1210_25V6K
1
PC131
2
0_0603_5%
1U_0805_25V4Z
3
PR157
1 2
0_0603_5%
MAX1845EEI_QSOP28
1U_0603_10V6K
25
26
27 24
28
1
2
11
DAP202U_SOT323
PD33
PQ50
G1
D1 D1
S1/D2
G2
S1/D2 S1/D2
S2
SI4814DY_SO8
POK<41>
8 7 6 5
PC134
12
0.1U_0603_25V7K
1 2
PR161
1
2 2
+1.5V
+1.5VALWP
2 1
2200P_0402_50V7K
1
+
220U_D_2.5VM
2
PD36
EP10QY03
3 3
PC140
4700P_0603_50V7K
12
PC139
12
PC142
PL17 5UH_SPC-06704-5R0_2.9A_30%
PR158
1 2
5.1K_0603_1%
12
PR160 10K_0603_1%
2 3 4
12
12
PC132
PU17
BST1
DH1
LX1 DL1
CS1 OUT1
FB1
ON1
OVP
8
0.22U_0805_16V7K
PR154 0_0603_5%
1 2
4
V+
GND
23
12
6
PC144
SKIP
22
VCC
PR155
20_0603_5%
9
VDD
UVP
BST2
DH2
LX2 DL2
CS2
OUT2
FB2
ON2
PGOOD
TON
ILIM2 ILIM1
REF
10
12
+5VALWP
12
21
19 18 17 20 16
15 14 12
7 5
13 3
PR164
12
42.2K_0603_1%
PR165
12
75K_0603_1%
12
4.7U_120 6_16V4Z
PR156
1 2
0_0603_5%
12
PR166
100K_0603_ 1%
PC127
PC133 0.1U_0603_25V7K
12
12
PR167 100K_0603_ 1%
PQ49
IRF7811A_SO8
PR162
5
4
578
SYSON
12
0_0603_5%
S
2
3 6
241
+2.5V/+1.5V
12
PC128
D8D7D6D
4.7U_1210_25V6K
S1S3G
PL16
2.2H_SPC-1205P-2R2B_+40-20%
1 2
12
PD34
EC31QS04
PQ51 FDS6672A_SO8
SYSON <32,36,37>
10K_0603_1%
PL15
1 2
HCB4532K-800T90_1812
PR163
12
PC129
4.7U_1210_25V6K
PR159
15K_0603_1%
1 2
12
PC135
1
220U_D2_4VM
+
2
12
1
+
2
12
12
2.5V OCP > 13A
PC130
4.7U_1210_25V6K
+2.5V
1
+
PC136
2
220U_D2_4VM
220U_D2_4VM
PC141
4700P_0603_50V7K
PC143
2200P_0402_50V7K
B+
PC137
+2.5VP
1
+
PC138
2
220U_D2_4VM
PD35
EP10QY03
2 1
4 4
Compal Electronics, Ltd.
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEE T NOR THE IN FORMATION IT C ONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN C ONSENT OF COMPAL EL ECTRONICS , INC.
C
+2.5VP/1.5VALWP
Size Document Number Re v
Custom
LA-1931
Date: Sheet
D
of
42 47Monday, June 09, 2003
0.2
5
4
3
2
1
+3VALWP+3VALW P
PR168
12
PR169
D D
22K_0603_5%
0.1U_0603_16V7K
PC146
PR170
1 2
5.1_0603_5%
12
0_1206_5%
1 2
12
PC145
4.7U_120 6_16V4Z
PU18
VIN1PVIN
2
PR171
+2.5VP
C C
B B
A A
105K_0603_1%
SUSP#<21,28,32,33,37>
+SDREF
12
1U_0603_10V6K
12
PR174
105K_ 0603_0.5%
R67 0_0603_5%
10U_1206_10V4Z
5
PR176
1 2
0_0603_5%
C39
PC148
1
LM358A_SO8
2
LM358A_SO8
12
U8A
1
R348
1 2
@0_0603_5%
U8B
7
1
PQ52
D
S
2N7002_SOT23
3G2
1
D
PQ53 2N7002_SOT23
S
G
3
2
VS
1
C42
0.1U_060 3_50V4Z
2
8
P
3
+IN
OUT
2
-IN G
4
5
+IN
OUT
6
-IN
PR175 100K_0603_5%
1 2
+2.5V
12
12
R72 10K_0603_1%
R71 10K_0603_1%
4
GND
3
SD VREF4VFB
CM3718_PSOP8
1
C47
0.1U_0603_16V7K
2
PGND
8 7
LX
6 5
PL18
1 2
5UH_SPC-06704-5R0_2.9A_30%
PR172
1 2
100K_0603_5%
PC149
PR173
ADP_I<32,40>
VL
1 2
470P_0603_50V8J
PR229
1 2
@
200K_0603_ 1%
PR227
1 2
@
84.5K_0603_1%
PR228
100K_0603_1%@
12
1 2
1K_0603_5%
1
G
ALI/MH#<32,39>
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, IN C. NEIT HER TH IS SHEE T NOR T HE INF ORMATION IT CONTAIN S MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITTEN CON SENT OF COMPAL ELE CTRONICS , INC.
2
3
+1.25VSP
1
+
PC147 220U_D2_4VM
2
PR226
1 2
1M_0603_1%@
VS
12
PC2
8
3
+
2
-
4
12
PC3
1000P_0603_50V7K@
0.1U_0603_25V7K@
PU6A
P
1
O
G
LM393M_SO8@
VL
12
12
PR223
47K_0603_1%@
PD7
1SS355_SOD323@
PC1
10P_0603_50V8J
1
D
PQ1
S
G
3
2
12
H_PROCHOT# <5>
2N7002_SOT23@
VL
12
PR232
200K_0603_ 1%@
8
PU6B
5
+
12
6
PQ2
D
S
2N7002_SOT23
@
3
PACIN<38,40,41>
PR233
100K_0603_ 1%@
-
2
PD8
P
O
G
4
LM393M_SO8@
12
7
1SS355_SOD323@
Compal Electronics, Ltd.
Title
+1.25VSP
Size Document Number Rev
Custom
LA-1931
Date: Sheet
43 47Monday, June 09, 2003
1
of
A
Different Pin Definition for ISL6561 in PU9
B
C
D
#7 GND
#9 TCOMP
PR207
0_0603_5%
#10 DAC
PM_DPRSLPV R<18>
PM_STPCPU#<14,18>
VID_PWRGD<35>
12
12
VR_ON<32>
1 1
2 2
3 3
+3VALWP
4 4
#11
#14
#18 RGND
PR183 0_0603_5%@
PR184 0_0603_5%@
100P_0603_50V8J
PC159
4.7U_120 6_16V4Z
PR211 0_060 3_5%
A
REF
IDROOP
PR181
1 2
0_0603_5%@
1 2
12
PR185
0_0603_5%@
12
PC154
12
PR212 100K_0603_1%
1 2
BOOTSELECT=1
BOOTSELECT=0
#33
#35 GND
#37 GND
PR179 0_0603_5%
1 2
1 2
PU5
1
IN
4
PG
3
EN
MIC5258_SOT23-5
12
12
EN #38 OVP
#40 GND
12
PR182 0_0603_5%
ENLL<35>
12
PR186
475_0603_1 %
PR190
27.4K_0603_1%
PR198
45.3K_0603_1%
1 2
OUT
GND
PR187
69.8K_0603_1%
1 2
12
5
2
PRESCOTT
NORTHWOOD
CPU_VID4<5> CPU_VID3<5> CPU_VID2<5> CPU_VID1<5> CPU_VID0<5>
CPU_VID5<5>
Frequency Select
PU12B
5
+
7
0
6
-
LM358A_SO8
PR194 10K_0603_1%
PR199
32.4K_0603_1%
100K_0603_ 1%
12
PR193
S3G
+1.2VP
12
PC160
4.7U_120 6_16V4Z
1. When mode control signal is high/ low, the VR will operate to Northwood/ Prescott load line.
2. VID5(12.5) should be pulled high, when the VR operates to Nothwood load line.
B
+5VALWP
12
PC150
1U_0603_10V6K
PC151
12
0.033U_0603_25V7M
PR191
1 2
+3VALWP
1
0_0603_5%
220P_0603_50V8J@
12
PC156
PR196
10K_0603_1%
1 2
Panasonic ERTJ0EV334J (0402) Locate this NTC resistor on PCB between phase 2 and 3 for thermal compensation.
D
PQ56 2N7002_SOT23
2
PH3
330KB_0 402_5%_ERTJ0EV334J@
1 2
BOOTSELECT<4>
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEE T NOR THE IN FORMATION IT C ONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN C ONSENT OF COMPAL EL ECTRONICS , INC.
12
PR177
0_0603_5%
32
1 2 3 4 5 6
34
33
35
10
11
9
36
37
38
40
12
19
PU2
VCC
VID4 VID3 VID2 VID1 VID0 VID12.5
ENLL
DRSEN
DSEN#
OCSET
SOFT
DSV
FS
DRSV
VR-TT#
NTC
GND
GND
ISL6247_MLFP40
PR209
22K_0603_5%
12
PR210 100K_0603_ 5%
2
G
1
PQ55
D
3
12
RAMPS
PGOOD
PWM1
ISEN1+
ISEN1-
PWM2
ISEN2+
ISEN2-
PWM3
ISEN3+
ISEN3-
PWM4
ISEN4+
ISEN4-
COMP
FB
NC
VDIFF VSEN VRTN
OFS
PR197
1.2M_0603_5%
340K_0603_ 1%
S
TP0610T_SOT23
2
B
7
39
25
24 23
26
27 28
20
21 22
31
30 29
15
13
14
16 17 18
8
PR202
1
C
12
C
Battery Feed
B+
Forward
PR178
80.6K_0603_1%
1 2
PR180
PR188 0_0603_5%
+5VALWP
1 2
E
PQ58 MMBT3904_SOT23
3
12
10K_0603_1%
12
Place close to IC
PC157
0.1U_0603_16V7K
PR201
5.1K_0603_1%
1 2
PR203
27K_0603_5%
1 2
1
PQ57
D
S
G
3
2
+5VALWP
1000P_0603_50V7K
1000P_0603_50V7K@
1 2
1U_0603_10V6K
2N7002_SOT23
VGATE <14,18>
PWM1 <45>
ISEN1+ <45>
ISEN1- <45>
PWM2 <45>
ISEN2+ <45>
ISEN2- <45>
PWM3 <45>
ISEN3+ <45>
ISEN3- <45>
PR189
PC152
1 2
12
20K_0603_1%
PC153
12
PR192 0_0603_ 5%@
PQ54 2N7002_SOT23
1
PR200 16.2K_0603_1%
+CPU_CORE
VSSSENSE <5>
12
12
Remote Sensing
VCCSENSE <5>
D
12
PC155 1000P _0603_50V7K@
PR195 2.26K_0603_1%
1 2
3
12
PC158
S
D
2
G
PR204
12
0_0603_5%@
12
PR205 0_0603_5%@
PR206
0_0603_5%@
0_0603_5%@
Title
Size Document Number Re v
B
Date: Sheet
Place near +VCC_CORE output capacitor
12
PR208
12
Compal Electronics, Ltd.
CPU_CORE_Controller
LA-1931
0.2
of
44 47Monday, June 09, 2003
A
+5VALWP
PC161
12
0.22U_0805_16V7K
PU1
6
1 1
PWM1<44>
12
PR214 0_060 3_5%
PR215 499K_0603_1%
1 2
PC166
0.1U_0603_16V7K
1 2
3
7
4
PC167 1U_0805_25V4Z
1 2
VCC
PWM
EN
GND
ISL6207CB-T_SO8
BOOT
UGATE
PHASE
LGATE
2
1
8
5
PR213
1 2
SI4362DY_SO8
PQ59
IRF7811A_SO8
2.2_0603_1%
PQ61
B
5
S
4
2
5
S
4
2
5
4
5
4
D8D7D6D
S1S3G
S
2
IRF7811A_SO8
PQ62
D8D7D6D
SI4362DY_SO8
S1S3G
S
2
PQ60
D8D7D6D
S1S3G
D8D7D6D
S1S3G
PC162
4.7U_1210_25V6K
1 2
12
PD2 EC31QS04
CPU_B+
12
PC165
4.7U_1210_25V6K
12
PC163
4.7U_1210_25V6K
C
1 2
PL1 C8B BPH 853025_2P
1
+
PC164
100U_25V_M@
2
PL2
1 2
0.6U_HK_AE26A0R6_26A_25%
12
32.4K_0603_1%
PR217
B+
PC168
12
0.01U_0603_16V7K
D
CPU_DRIVE_EN
ISEN1-<44>
ISEN1+<44>
PC170
1 2
2 2
PWM2<44>
PC174
PR220 499K_0603_1%
1U_0805_25V4Z
1 2
0.22U_0805_16V7K
PU3
6
VCC
3
PWM
7
EN
4
GND
ISL6207CB-T_SO8
BOOT
UGATE
PHASE
LGATE
2
1 2
1
8
5
PR218
SI4362DY_SO8
1 2
2.2_0603_1%
PQ65
5
4
5
4
S
IRF7811A_SO8
2
S
2
5
4
5
4
PQ64
D8D7D6D
S1S3G
S
IRF7811A_SO8
2
PQ66
D8D7D6D
SI4362DY_SO8
S1S3G
S
2
PQ63
D8D7D6D
S1S3G
D8D7D6D
S1S3G
CPU_B+
12
PC171
4.7U_1210_25V6K
12
PD3 EC31QS04
12
PC172
4.7U_1210_25V6K
12
PC173
4.7U_1210_25V6K
1 2
0.6U_HK_AE26A0R6_26A_25%
12
32.4K_0603_1%
PR221
Local Transistor Swtich Decoupling
PL3
12
PH4 820B_0603_5%_ERAV33J821V
PC175
12
0.01U_0603_16V7K
12
PD6 EC31QS04
+CPU_CORE
ISEN2-<44>
ISEN2+<44>
PC178
CPU_B+
12
PC179
4.7U_1210_25V6K
0.6U_HK_AE26A0R6_26A_25%
PR225 32.4K_0603_1%
C
12
PC180
4.7U_1210_25V6K
12
Local Transistor Swtich Decoupling
3 3
PWM3<44>
PR224 499K_0603_1%
1 2
4 4
ISEN3-<44> ISEN3+<44>
A
PC182
1U_0805_25V4Z
1 2
PC177
1 2
0.22U_0805_16V7K
PU4
6
VCC
3
PWM
7
EN
4
GND
ISL6207CB-T_SO8
BOOT
UGATE
PHASE
LGATE
2
1
8
5
PR222
1 2
2.2_0603_1%
SI4362DY_SO8
PQ69
5
4
5
4
B
D8D7D6D
S1S3G
S
2
D8D7D6D
S1S3G
S
2
5
PQ67 IRF7811A_SO8
PQ68
D8D7D6D
IRF7811A_SO8
S1S3G
S
4
2
5
PQ70
D8D7D6D
SI4362DY_SO8
S1S3G
S
4
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEE T NOR THE IN FORMATION IT C ONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN C ONSENT OF COMPAL EL ECTRONICS , INC.
12
4.7U_1210_25V6K
12
PD5 EC31QS04
PH5 820B_0 603_5%_ERAV33J821V
PL4
12
PC181
0.01U_0 603_16V7K
PH6 820B_0603_5%_ERAV33J821V
12
12
12
Compal Electronics, Ltd.
Title
CPU_CORE_Power stage
Size Document Number Re v
Custom
LA-1931
Date: Sheet
D
0.2
of
45 47Monday, June 09, 2003
REV 0.1
DescriptionDate Page Delet e Pow er in terface short line.04/10 21 Chang e Card Bus controller as one slote CB141004/13 21, 22 Swap RAM data signals.11, 12 Add EQ circuit04/16 29 Add throutoling circuit.43 Add FIR and Remove SW DJ cicuit26, 31 Add R569 and R570 for Layout Request. Move Signal IRQE#~H# from RP92 to RP91 and del RP92.04/24 17 CLK- GEN. pin 1(V DD_REF) and pin 46(VDD_CPU_0) change power plan as +3V_VDD. Suggestion from ICS14 C249 and C251 change power plane as +3VDD PL4 swap pin1 and pin2.04/25 45 Change CPU Decoupling CAP. from 22U_1210_6.3V6M to 22U_1206_6.3V6M ( H=1.6 )6
1. EC GPIO signal HDD_LED# move from pin114 to pin119.32
2. Add signal PM_SLP_S1# on EC GPIO pin115. Q44 for +5VCD change part name as U5528 Del R73, cause it duplicate pull high.04/28 8 Change C478 and C488 from 150U to 10U27 Change R480 from 560K to 620K Ohm36 Add R571 for BOOTSELECT4 Add R573 for OPTIMIZED/COMPAT#5 Add R572 for signal PM_DPRSLPVR18 Rename from Layout04/29 R73 0402 -> 0603 and C52 0805 -> 06033304/3 0 C2, C5, C259, C3, C4, C6, C260, C261 and C262 Link CIS.16 Therm al Sen sor : Del R62, R61 8.2K-->200Ohm and power +5VS -> +3VS, C27 value 0.1U -> 1U, Sensor power rout direction : +3VS -> R61 -> C27.1 -> U6.15 Add Q40 and Q41, R517 and R518 for SMBus isolate solution.17 Change CRT_HSYNC -> INTCRT_HSYNC and CRT_VSYNC -> INTCRT_VSYNC on MGCH terminal.805/01 Remove dummy net on SUSP#.3305/02 R28, C277, C278 and C279 modify P/N for CIS link16 C215 and C217 modify P/N for CIS link17 C145 modify P/N for CIS link22 Remove dummy net on XI20 R83 and R94 modify P/N for CIS link14 CP4 pi n2 add connected to GND3205/0 3 PR151 pin1 SYSON signal --> MAINPWON4205/0 5 Swap U26.B6 (INTDDCDA) and U26.G9 (INTDDCCK) --> U26.B6 (INTDDCCK) and U26.G9 (INTDDCDA)8 +SDRE F cir cuit move to page 449 Modify Cap.s location same with Layout6 Change R129 net from PM_SLP_S3# to PM_SLP_S1#14 Add R519 and R520 for EC protect16 EEDI_ LAN --> EEDI_1394; EECK_LAN --> EECK_13942005/06 Remove R26. Delete USBEN# and U3.3, U3.4, U32.3 and U32.4 connect to GND.27 Delet e R30, R279, R258 and R257. Chang e C273, C284 and C646 220U -->150U. PR151 pin1 SYSON signal --> POK; PU10 pin 11 output POK.42 R324 size 0603 -> 08055 U24.175 ATF_INT# --> EC_THERM#32 Add L4 2 between GND and AGND by EMI request.2805/0 7 R408, remove @ for Intel comment.17 R56 60.4_0603_1% --> 51 .1_0603_1%; R59 102_0603_1% -> 86.6_0603_1%5 H19 GNDA -> GND; H31 GND -> GNDA3505/08 C242 0.01U -> 0.1U.37 JP21 DDR-SO-DIMM link with CIS.11 De-pop EQ components, add @ symbol on components.29
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY ORDISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.
Compal Electronics, Ltd.
Title
PIR
Size Document Number R ev
Custom
LA-1931
Date: Sheet
46 47Monday, June 09, 2003
of
0.2
REV 0.2
DescriptionDate Page Change H31 GND - -> AGND and H19 AGND --> GND05/12 35 R104 and R108 power plane changed, +3VALW --> +5VALW37
05/29 40 Change PR100 47.5K-->95.3K
PR100 47.5K-->95.3K;PQ37,PQ38,PQ39 SI4835DY-->SI4825DY PR79 0.015-->0.01; PR86 10K-->100K ;PR90 4.7K-->10K; PR88 29.4K-->33.2K
Add PR2 95.3K 38 Change PCN1 90W-->120W 20 U29 Pin 37 pull up with 4.7K Ohm --> U29 Pin 43
change X4 footprint same as X2 16 Add Protect circuit for EC (Add D42, D43 ,D44 and R521) 32 PWR_SUSP_LED# --> PWR_SUSP_LED 34 Add reverse circuit for PWR_SUSP_LED (Add Q43 and R522). 23 change Y2 footprint same as X2 36 chang e J1 ~ J6 footprint from JUMP_2MM to 2MM 35 Add H41 and change H13 H27 size.05/30 38 Change PL14 value06/02 39 Change PL13 value 45 Change PL1 value 40 Change PQ39 and PL11 value 11 Add R523, R524, R525 and R526, Del R515 12 Add R527, R528, R529 and R530
6 D elete C281, C287, C300, C309, C317, C324, C327 and C330.06/03 34 Add C648 and C649 for EMI request06/05 32 Add R531 and R532 for EC floating issue
8 Add R533 for DVO device detect
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC . NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY ORDISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, I NC.
Compal Electronics, Ltd.
Title
PIR
Size Document Number R ev
Custom
LA-1931
Date: Sheet
47 47Monday, June 09, 2003
of
0.2
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