QUANTA ZN1 Schematics

5

4

3

2

1

Amazon LCD PC Block Diagram

V

D D

DDRII X2

page:8

18.

5" panel

page:19

CHA

/B

AMD AM2

uP

GA940

CORE:+1.196 ~ +0.748

V
VCCP:+1.1V
VCCA:+1.8V or +1.5V

page:4-7

+/- CP

+/- HCLK

U_CLK

HT-LINK

LV

ID[0:6]

DS

LV

C C

MXM
MODULE
(MXM3.0)

page:20

10/100
Et

RJ-45

page:25

B B

6 in 1

page:27

SPK

page:29

LINE OUT

page:23

A A

H/P OUT

page:29

Int

. Mic

page:29

5

hernet

TL8103EL

R

page:24

ard Reader

C

JR385

page:27

HDA CODEC

ALC269

page:29

B X2

US

side USB

page:26

4

DS

PCIEX1

PCI­PCI-

A

zalia

US

6

E
E

RS780MN

ST

HO
LVDS, DMI, DDR CLK
POWER
GND

page:10-13

A_

LINK

PCI

SA

-E/USB

TA

SB700

RTC, AC97, S
PCI-E, USB, DMI, PCI
SMB, GPIO, CLK

B

ATA, IDE, LPC, CPU

page:14-18

EC

ITE8512

page:32

3

LP

C BUS

US

B

USB

Camera Conn.

USB PORT X4
Rear

SPI
Fl

page:32

CPU VCORE

page:34

Clock Gengerator

page:3

INI CARD

M

page:30

HDD, ODD

page:28

page:22

page:26

ash

2

W

LAN

Module

Bluetooth

USB

Camera
M

odule

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Block Diagr

Block Diagr

Block Diagr

Date: Sheet

Date: Sheet

Date: Sheet

RESERVE

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

am

am

am

ZN1

ZN1

ZN1

1

1

B

B

14

14

14

B

1Friday, May 08, 2009

1Friday, May 08, 2009

1Friday, May 08, 2009

of

of

of

5

4

3

2

1

2

3&%67$&.83

LAYER 1 :
LAYER 2 : VCC
LAYER 3 : IN1

D D

LAYER 4 : IN2
LAYER 5 :
LAYER 6 : BOT

C C

B B

TOP

GND

Pow

er S0~S2

5VPCU

1
5

VPCU

3VPCU

CC3

RV

5VSUS

1.8VSUS
CC5

V
VCC3

CC1.8 1.8V

V
VCC1.5

CC1.2 1.2V

V
CP

U_VDDA
NB_CORE
SMDDR_VTERM
CP

U_CORE

36B216/3B66/3B6

Volta

15V
5V
3V

3V

5V

1.
5V
3V

1.5V

2.

1.2V

0.9V
By CP

9$/:

560567

999

9'50B3:5*'

9&&B1%B3:5*'

950B3:5*'

1%B3:5*'

6%B3:5*'

&38B3:5*'

3&,B567

&38B567

8V SUSON

5V

Voltage Rails

ge

U

%21(),6+32:(5836(48(1&(

VV
V
VV

V

VV
V
V
V
V
V
V
V
V
V

T

1>= 70 ms

VV

VV
VV

VV

1m
1ms < T3 < 5ms

T2

T3T1

s < T2 < 10ms

S4

V

V

S5

V
V
V

V
V

Ctl Sign

VI

N

VIN

CC_ON

RV
RVCC_ONRVCC1.2 1.2V V

SUSD

MAIND
MA

IND
MAIND
MAINON
MAINON
V

CC3

ON

VR
SU

SON

VR_ON

alS3

Power On Sequence

From AC IN

5VPCU 3VPCU

From PWM

From Power Button

From EC

SYS_HWPG(PCU)

NBSWON#

RVCC_ON

RVCC5

RVCC3

From EC
From EC
From SB

From SB to EC

From EC

RVCC1.2

RSMRST#

DNBSWON#

PCIE_WAKE#

SUSB#,SUSC#

SUSON

>10ms

>100ms

SUSON

3VSUS 1.8VSUS SMDDR_VREF SMDDR_VTERM

From PWM
From EC

HWPG_1.8V (SUS)

MAINON

MAINON

VCC5 VCC3 VCC2.5 VCC1.8 VCC1.5 NB_CORE 1.1V_NB

From PWM
From EC

HWPG_1.5V,HWPG_2.5V,GFXPG(MAIN) HWPG_1.2_NB

VRON

CPU_CORE0, CPU_CORE1, CPU VDDNB_CORE, VCC1.2

From PWM

VRM_PWRGD (CPU)

HWPG

From EC

From SB
From SB
From SB
From SB

ECPWROK

SB_PWRGD

NB_PWRGD

CPU_PWRGD/LDT_PG

PLTRST# PCIRST#

CPU_LDT_RST#

CPU_LDT_STOP#

0ns~30ns

99ms~108ms

A A

Qu

Qu

Qu

anta Computer Inc.

anta Computer Inc.

anta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

SYST

SYST

SYST

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

PROJECT :

EM INFORMATION

EM INFORMATION

EM INFORMATION

ZN1

ZN1

ZN1

24

24

1

24

B

B

B

1Friday, May 08, 2009

1Friday, May 08, 2009

1Friday, May 08, 2009

of

of

of

5

4

3

2

1

CLK_

D D

C C

B B

GEN_SLG8SP628

V

CC3

B

B

K1608HS600

K1608HS600

C

LK_VDD

R

R

315 8.2K_4

315 8.2K_4

LK_PD#

C

V

CC3

L27

L27

L26

L26

B

B

K1608HS600

K1608HS600

CL

K_VDD_USB

266 33P

266 33P

C

C

264 33P

264 33P

C

C

C

63

63

C2

C2

0.1u/10V_4

0.1u/10V_4

LK_VDD

52

52

C2

C2

22U/6.3V_8

22U/6.3V_8

255

255

C

C

2.2U_0805

2.2U_0805

21

Y2

Y2

14.

14.

318MHZ/20P

318MHZ/20P

C2

C2
10uF_0805

10uF_0805

_XIN

CG

_XOUT

CG

LK_SMB8,15,19,30

PC
PD

AT_SMB8,15,19,30

56

56

260

260

C

C

0.1u/10V_4

0.1u/10V_4

1 2

C2

C2

0.1u/10V_4

0.1u/10V_4

CL

K_VDDIO

58

58

C

LK_VDD

T80T8
T85T8

T84T8

22U/6.3V_8

22U/6.3V_8

CG
CG

C

0
5

4

C2

C2

0.1u/10V_4

0.1u/10V_4

50

50

C2

C2

_XIN
_XOUT

LK_PD#

70

70

LKREQ2#

C

69

69

75

75

C2

C2

C2

C2

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

,&6/356

6/*63

5701

U1

U1

2

2

4

VDDDOT

16

VDDSRC

26

VDDAT

IG

35

VDDSB_

SRC

40

VDDSAT

A

48

VDDCPU

55

VDDHT

T

56

VDDREF

63

8

VDD4

11

VDDSRC_

17

VDDSRC_

25

VDDAT

IG_IO

34

VDDSB_

SRC_IO

47

VDDCPU_

1

GND48

7

GNDDOT

10

GNDSRC0

18

GNDSRC1

24

IG

GNDAT

33

GNDSB_

SRC

43

GNDSAT

46

GNDCPU

52

T

GNDHT

60

GNDREF

61

X1

62

X2

2

BCLK

SM

3

BDAT

SM

51

PD#

23

CL

KREQ0#

45

KREQ1#

CL

44

KREQ2#

CL

39

KREQ3#

CL

38

KREQ4#

CL

SLG8SP628

SLG8SP628

68

68

C2

C2

0.1u/10V_4

0.1u/10V_4

31$/356

31$/63

31$/

IO0
IO1

IO

QFN64

QFN64

A

GND0

GND1

T

T

65

66

C

GND2
T

67

68

LK_VDD

GND3
T

GND4
T

69

76

76

C2

C2

0.1u/10V_4

0.1u/10V_4

SRC6

SRC6

RC7T/27M_SS

S
SRC7

REF

REF1

GND5

GND6

GND7

T

T

T

70

71

72

C2

C2

0.1u/10V_4

0.1u/10V_4

PUK8_0T

C

CPUK8

A

TIG0T

A

TIG0C

A

TIG1T

A

TIG1C

SRC0T

SB_

SRC0C

SB_

SRC1T

SB_
SB_

SRC1C

SRC0
SRC0
SRC1T
SRC1
SRC2
SRC2
SRC3
SRC3
SRC4
SRC4

T/SATAT
C/SATAC

C/27M_NS

TT0T/66M

H

T0C/66M

HT

48M

Hz_0

0/SEL_HTT66

/SEL_SATA
EF2/SEL_27

R

GND8

GND9

T

T

73

74

CL

L28

CC1.2

CP

UCLKP_R

CP

UCLKN_R

BGFX_CLKP_R

N
NB

GFX_CLKN_R

INK_CLKP_R

SBL

INK_CLKN_R

SBL
SBSR
S

BSRC_CLKN_R

CL

K_PCIE_MINI_R

CL

K_PCIE_MINI#_R

LK_PCIE_MXM_R

C

LK_PCIE_MXM#_R

C

LK_PCIE_LAN_R

C
C

LK_PCIE_LAN#_R

LK_PCIE_JM385_R

C

LK_PCIE_JM385#_R

C

NB

HT_REFCLKP_R
HT_REFCLKN_R

NB

C

LK_48M_USB_R

SEL
SEL
SEL

C2

C2

65

65

*10p/50V_4

*10p/50V_4

V

T83T8
T82T8

C_CLKP_R

T81T8
T77T7
T79T7
T78T7

T76T7
T75T7

_HTT66
_SATA
_27

3
2

1
7
9
8

6
5

C2

C2
*10p/50V_4

*10p/50V_4

59

59

73

73

50
49

_0C

30
29
28
27

37
36
32
31

22

T

21

C

20
19

C

15

T

14

C

13

T

12

C

9

T

8

C

42
41
6
5

54
53

64

59
58
57

L28

B

B

K1608HS600

K1608HS600

lock chip has internal serial terminations

C
for differencial pairs, external resistors are
reserved for debug purpose.

lace within 0.5"

P
of CLKGEN

RP

RP

7 0X2

7 0X2

4 0X2

4 0X2

RP

RP

9 0X2

9 0X2

RP

RP

RP

RP

6

6

RP

RP

3 0X2

3 0X2

RP

RP

2 0X2

2 0X2
1 0X2

1 0X2

RP

RP

RP

RP

8 0X2

8 0X2

RP

RP

5 0X2

5 0X2

177 33_4

177 33_4

R

R

180 158/F_4

180 158/F_4

R

R

181 90.9/F_4

181 90.9/F_4

R

R

2

1

4

3

2

1

4

3

2

1

4

3
1
3

1
3
1
3
1
3

1
3

1
3

0X2

0X2

2
4

2
4
2
4
2
4

2
4

2
4

Ra

Rb

K_VDDIO

*261/F_4

*261/F_4

GFX_CLKP

NB
NB

GFX_CLKN

INK_CLKPSBLINK_CLKP

SBL

INK_CLKNSBLINK_CLKN

SBL
S

BSRC_CLKPSBSRC_CLKP

S

BSRC_CLKNSBSRC_CLKN

C

LK_PCIE_WLANCLK_PCIE_WLAN

C

LK_PCIE_WLAN#CLK_PCIE_WLAN#

K_MXM

CL

LK_MXM#

C

LK_PCIE_LANCLK_PCIE_LAN

C
C

LK_PCIE_LAN#CLK_PCIE_LAN#

LK_PCIE_JM385CLK_PCIE_JM385

C

LK_PCIE_JM385#CLK_PCIE_JM385#

C

NB

HT_REFCLKPNBHT_REFCLKP
HT_REFCLKNNBHT_REFCLKN

NB

C

LK_48M_USB

_NB_OSC

EXT

22U/6.3V_8

22U/6.3V_8

182

182

R

R

72

72

C2

C2

74

74

C2

C2

0.1u/10V_4

0.1u/10V_4

CP

UCLKP

CP

UCLKN

SBL

INK_CLKP 12

SBL

INK_CLKN 12

S

BSRC_CLKP 14
BSRC_CLKN 14

S

LK_PCIE_WLAN 30

C

LK_PCIE_WLAN# 30

C

K_MXM 20

CL
C

LK_MXM# 20

C

LK_PCIE_LAN 24

C

LK_PCIE_LAN# 24

LK_PCIE_JM385 27

C
C

LK_PCIE_JM385# 27

HT_REFCLKP 12

NB

HT_REFCLKN 12

NB

CL

K_48M_USB 15

EXT

_NB_OSC 12

262

262

C

C

0.1u/10V_4

0.1u/10V_4

CP
CP

NB
NB

278

278

C

C

C

C

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

0.1u/10V_4

UCLKP 6
UCLKN 6

GFX_CLKP 12
GFX_CLKN 12

To NB

100 Mhz

To SB

To Mini PCIE Slot(WLAN)
To MXM MODULE
To LAN Controller

o 6 in 1 Controller

T

To NB HT BUS

To SB USB

NB

To

257

257

C2

C2

0.1u/10V_4

0.1u/10V_4

CPU

To

To NB

RS780 for VGA

100 Mhz

100 Mhz

48 Mhz

C

LOCK INPUT TABLE

CLOCKS
HT_REFCLKP
HT_REFCLKN
REFCLK_P
REFCLK_N
GFX_REFCLK
GPP_REFCLK
GPPSB_REFCLK

77

77

267

267

C

C

0.1u/10V_4

0.1u/10V_4

200 Mhz

RS780

100M D

IFF
100M DIFF
14M SE (1.1V)
vref

100M DIFF(IN/OUT)*

r 100M DIFF OUTPUT

NC o

100M DIFF

R3

R3

27

27

*8.2K_4

*8.2K_4

A A

26

26

R3

R3

8.2K_4

8.2K_4

5

4

R3

R3

8.2K_4

8.2K_4

SEL_SATA
SEL_HTT66
S

EL_27

316

316

28

28

R

R

8.2K_4

8.2K_4

3

SEL_HTT66

SEL_SATA

_27

SEL

6

1

6 MHz 3.3V single ended HTT clock

*0

z differential HTT clock

100 MH
100 MHz non-spreading differential SRC clock

1*
0

100 MHz spreading differential SRC clock
27MHz and 27M SS outputs

1

Hz SRC clock

0*

100 M

* default

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

ize Document Number Rev

ize Document Number Rev

S

S

Cl

Cl

Cl

Date: Sheet

Date: Sheet

2

Date: Sheet

PROJECT :

ock Generator

ock Generator

ock Generator

ZN1

ZN1

ZN1

1A

1A

1A

of

of

of

341Friday, May 08, 2009

341Friday, May 08, 2009

341Friday, May 08, 2009

1

5

4

3

2

1

4

CPU Hy

D D

.2

VCC1

98 *short0805

98 *short0805

R

R
R

R

100 *short0805

100 *short0805

C C

B B

DT_RUN

VL

VDDLDTRUNCPU is connected to the VDD_LDT_RUN power
supply through the package or on the die. It is only connected

VL

H

T_CADIN15_P10

H

T_CADIN15_N10
T_CADIN14_P10

H
H

T_CADIN14_N10
T_CADIN13_P10

H
H

T_CADIN13_N10
T_CADIN12_P10

H
H

T_CADIN12_N10

H

T_CADIN11_P10

H

T_CADIN11_N10
T_CADIN10_P10

H

T_CADIN10_N10

H
H

T_CADIN9_P10
T_CADIN9_N10

H
H

T_CADIN8_P10
T_CADIN8_N10

H
H

T_CADIN7_P10
T_CADIN7_N10

H

T_CADIN6_P10

H
H

T_CADIN6_N10

H

T_CADIN5_P10

H

T_CADIN5_N10
T_CADIN4_P10

H
H

T_CADIN4_N10
T_CADIN3_P10

H
H

T_CADIN3_N10
T_CADIN2_P10

H
H

T_CADIN2_N10
T_CADIN1_P10

H
H

T_CADIN1_N10
T_CADIN0_P10

H

T_CADIN0_N10

H

T_CLKIN1_P10

H
H

T_CLKIN1_N10

H

T_CLKIN0_P10
T_CLKIN0_N10

H

T_CTLIN1_P10

H
H

T_CTLIN1_N10

H

T_CTLIN0_P10

H

T_CTLIN0_N10

perTransport Interface

on the boar

DT_RUN

d to decoupling near the CPU package.

A

A

U9

U9

AJ4

LDT_06

V

AJ3

LDT_05

V

AJ2

V

LDT_02

AJ1

LDT_01

V

U6

L0_C

ADIN_H15

V6

ADIN_L15

L0_C

T4

L0_C

ADIN_H14

T5

ADIN_L14

L0_C

R6

L0_C

ADIN_H13

T6

ADIN_L13

L0_C

P4

ADIN_H12

L0_C

P5

L0_C

ADIN_L12

M4

L0_C

ADIN_H11

M5

L0_C

ADIN_L11

L6

ADIN_H10

L0_C

M6

L0_C

ADIN_L10

K4

ADIN_H9

L0_C

K5

L0_C

ADIN_L9

J6

L0_C

ADIN_H8

K6

L0_C

ADIN_L8

U3

L0_C

ADIN_H7

U2

ADIN_L7

L0_C

R1

L0_C

ADIN_H6

T1

ADIN_L6

L0_C

R3

L0_C

ADIN_H5

R2

ADIN_L5

L0_C

N1

L0_C

ADIN_H4

P1

ADIN_L4

L0_C

L1

L0_C

ADIN_H3

M1

ADIN_L3

L0_C

L3

ADIN_H2

L0_C

L2

ADIN_L2

L0_C

J1

L0_C

ADIN_H1

K1

L0_C

ADIN_L1

J3

ADIN_H0

L0_C

J2

L0_C

ADIN_L0

N6

L0_C

LKIN_H1

P6

LKIN_L1

L0_C

N3

L0_C

LKIN_H0

N2

L0_C

LKIN_L0

V4

0_CTLIN_H1

L

V5

L0_C

TLIN_L1

U1

L

0_CTLIN_H0

V1

TLIN_L0

L0_C

At

hlon 64 M2

rocessor Socket

P

L0_C

0_CADOUT_L15

L

L0_C

0_CADOUT_L14

L

L0_C

0_CADOUT_L13

L

L0_C

L

0_CADOUT_L12

L0_C

L

0_CADOUT_L11

L0_C

L

0_CADOUT_L10

L0_C

L

0_CADOUT_L9

L0_C

L

0_CADOUT_L8

L0_C

LINK

LINK

0_CADOUT_L7

L

L0_C

HT

HT

0_CADOUT_L6

L

L0_C

0_CADOUT_L5

L

L0_C

0_CADOUT_L4

L

L0_C

0_CADOUT_L3

L

L0_C

0_CADOUT_L2

L

L0_C

L

0_CADOUT_L1

L0_C

L

0_CADOUT_L0

L0_C

L0_C

L0_C

L0_C

0_CTLOUT_H1

L

L0_C

L

0_CTLOUT_H0

L0_C

DT_08

VL

DT_07

VL
VL

DT_04
DT_03

VL

ADOUT_H15
ADOUT_H14
ADOUT_H13
ADOUT_H12
ADOUT_H11
ADOUT_H10

ADOUT_H9
ADOUT_H8
ADOUT_H7
ADOUT_H6
ADOUT_H5
ADOUT_H4
ADOUT_H3
ADOUT_H2
ADOUT_H1
ADOUT_H0

LKOUT_H1

LKOUT_L1

LKOUT_H0

LKOUT_L0

TLOUT_L1

TLOUT_L0

H6
H5
H2
H1

Y5
Y4
AB6
AA6
AB5
AB4
AD6
AC6
AF6
AE6
AF5
AF4
AH6
AG6
AH5
AH4
Y1
W1
AA2
AA3
AB1
AA1
AC2
AC3
AE2
AE3
AF1
AE1
AG2
AG3
AH1
AG1

AD5
AD4

AD1
AC1

Y6
W6

W2
W3

49

49

C1

C1

4.7U_0603

4.7U_0603

HT

_CADOUT15_P 10
_CADOUT15_N 10

HT
HT

_CADOUT14_P 10
_CADOUT14_N 10

HT
HT

_CADOUT13_P 10
_CADOUT13_N 10

HT

_CADOUT12_P 10

HT
HT

_CADOUT12_N 10

HT

_CADOUT11_P 10

HT

_CADOUT11_N 10
_CADOUT10_P 10

HT
HT

_CADOUT10_N 10

T_CADOUT9_P 10

H
H

T_CADOUT9_N 10

H

T_CADOUT8_P 10

H

T_CADOUT8_N 10

H

T_CADOUT7_P 10
T_CADOUT7_N 10

H
H

T_CADOUT6_P 10
T_CADOUT6_N 10

H
H

T_CADOUT5_P 10
T_CADOUT5_N 10

H
H

T_CADOUT4_P 10
T_CADOUT4_N 10

H
H

T_CADOUT3_P 10
T_CADOUT3_N 10

H

T_CADOUT2_P 10

H

T_CADOUT2_N 10

H
H

T_CADOUT1_P 10

H

T_CADOUT1_N 10
T_CADOUT0_P 10

H
H

T_CADOUT0_N 10

H

T_CLKOUT1_P 10
T_CLKOUT1_N 10

H
H

T_CLKOUT0_P 10

H

T_CLKOUT0_N 10
T_CTLOUT1_P 10

H
H

T_CTLOUT1_N 10

H

T_CTLOUT0_P 10
T_CTLOUT0_N 10

H

VL

DT_RUN

C1

C1
180P

180P

12

C1

C1

50

47

47

180P

180P

50

uanta Computer Inc.

uanta Computer Inc.

uanta Computer Inc.

Q

Q

Q

PROJECT :

PROJECT :

ze Document Number Rev

ze Document Number Rev

Si

Si

Size Document Num b er Rev

Date: Sheet

Date: Sheet

2

Date: Sheet of

D AM2 HT I/F

D AM2 HT I/F

D AM2 HT I/F

AM

AM

AM

PROJECT :

ZN1

ZN1

ZN1

44

44

44

1

1A

1A

1A

1Friday, May 08, 2009

of

1Friday, May 08, 2009

of

1Friday, May 08, 2009

C1

C1

46

46

4.7U_0603

4.7U_0603

A A

5

4

C1

C1

45

45

4.7U_0603

4.7U_0603

C1

C1

0.22U

0.22U

C1

C1

51

51

0.22U

0.22U

12

48

48

3

5

U9

U9

C

M_

M

_B_DQS0

M

_B_DQS1

M_B_DQS2

_B_DQS3

M
M

_B_DQS4
_B_DQS5

M
M

_B_DQS6
_B_DQS7

M

_B_DQS#0

M

_B_DQS#1

M
M

_B_DQS#2
_B_DQS#3

M

_B_DQS#4

M

_B_DQS#5

M

_B_DQS#6

M
M_B_DQS#7

M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_

M_
M_
M_
M_
M_
M_
M_
M_

B_DQ63
B_DQ62
B_DQ61
B_DQ60
B_DQ59
B_DQ58
B_DQ57
B_DQ56
B_DQ55
B_DQ54
B_DQ53
B_DQ52
B_DQ51
B_DQ50
B_DQ49
B_DQ48
B_DQ47
B_DQ46
B_DQ45
B_DQ44
B_DQ43
B_DQ42
B_DQ41
B_DQ40
B_DQ39
B_DQ38
B_DQ37
B_DQ36
B_DQ35
B_DQ34
B_DQ33
B_DQ32
B_DQ31
B_DQ30
B_DQ29
B_DQ28
B_DQ27
B_DQ26
B_DQ25
B_DQ24
B_DQ23
B_DQ22
B_DQ21
B_DQ20
B_DQ19
B_DQ18
B_DQ17
B_DQ16
B_DQ15
B_DQ14
B_DQ13
B_DQ12
B_DQ11
B_DQ10
B_DQ9
B_DQ8
B_DQ7
B_DQ6
B_DQ5
B_DQ4
B_DQ3
B_DQ2
B_DQ1
B_DQ0

B_DM7
B_DM6
B_DM5
B_DM4
B_DM3
B_DM2
B_DM1
B_DM0

M

_B_DQS7

M

_B_DQS#7

M_B_DQS6

_B_DQS#6

M
M

_B_DQS5
_B_DQS#5

M
M

_B_DQS4
_B_DQS#4

M

_B_DQS3

M

_B_DQS#3

M

_B_DQS2

M
M

_B_DQS#2
_B_DQS1

M

_B_DQS#1

M

_B_DQS0

M

_B_DQS#0

M

M

_B_DQ[0..63]8

D D

C C

B B

M

_B_DM[0..7]8

A A

_B_DQS[0..7]8

M

M

_B_DQS#[0..7]8

5

AH13

AL13
AL15

AJ15

AF13

AG13

AL14
AK15
AL16
AL17
AK21
AL21

AH15

AJ16

AH19

AL20

AJ22
AL22
AL24
AK25

AJ21

AH21
AH23

AJ24
AL27
AK27

AH31
AG30

AL25
AL26

AJ30

AJ31

E31
E30
B27
A27

A29
A28
A25
A24
C22
D21
A26
B25
B23
A22
B21
A20
C16
D15
C21
A21
A17
A16
B15
A14
E13

C15
A15
A13
D13

G30
G29

H31
G31

AJ14

AH17

AJ23
AK29

C30
A23
B17
B13

AK13

AJ13
AK17

AJ17
AK23
AL23
AL28
AL29

D31
C31
C24
C23
D17
C17
C14
C13

F29
F31

F13

K29
K31

L29
L28

J29

J31
J30

C

B_DATA63

M
M

B_DATA62

M

B_DATA61

M

B_DATA60
B_DATA59

M

B_DATA58

M
M

B_DATA57
B_DATA56

M
M

B_DATA55
B_DATA54

M
M

B_DATA53
B_DATA52

M

B_DATA51

M

B_DATA50

M
M

B_DATA49
B_DATA48

M

B_DATA47

M
M

B_DATA46
B_DATA45

M

B_DATA44

M

B_DATA43

M
M

B_DATA42
B_DATA41

M
M

B_DATA40
B_DATA39

M
M

B_DATA38
B_DATA37

M

B_DATA36

M
M

B_DATA35

M

B_DATA34

M

B_DATA33
B_DATA32

M
M

B_DATA31
B_DATA30

M
M

B_DATA29

M

B_DATA28

M

B_DATA27

M

B_DATA26
B_DATA25

M
M

B_DATA24
B_DATA23

M
M

B_DATA22
B_DATA21

M
M

B_DATA20
B_DATA19

M
M

B_DATA18
B_DATA17

M

B_DATA16

M

B_DATA15

M
M

B_DATA14

M

B_DATA13
B_DATA12

M
M

B_DATA11
B_DATA10

M
M

B_DATA9
B_DATA8

M
M

B_DATA7

M

B_DATA6

M

B_DATA5
B_DATA4

M

B_DATA3

M
M

B_DATA2
B_DATA1

M
M

B_DATA0

B_CHECK7

M

B_CHECK6

M
M

B_CHECK5

M

B_CHECK4

M

B_CHECK3
B_CHECK2

M
M

B_CHECK1
B_CHECK0

M

_DM8

MB
MB

_DM7
_DM6

MB
MB

_DM5
_DM4

MB

_DM3

MB

_DM2

MB

_DM1

MB

_DM0

MB
MB_DQS_H8

B_DQS_L8

M
M

B_DQS_H7
B_DQS_L7

M
MB_DQS_H6
MB_DQS_L6
M

B_DQS_H5

M

B_DQS_L5
B_DQS_H4

M
MB_DQS_L4
MB_DQS_H3
M

B_DQS_L3

M

B_DQS_H2

M

B_DQS_L2
MB_DQS_H1
MB_DQS_L1
M

B_DQS_H0
M

B_DQS_L0

hlon 64 M2

At
P

rocessor Socket

4

M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M

DDRII: DATA

DDRII: DATA

M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M

M
M
M
M
M
M
M
M

MA_DQS_H8

M

M

M

MA_DQS_H6

MA_DQS_L6

M

M

M

MA_DQS_L4

MA_DQS_H3

M

M

M

MA_DQS_H1

MA_DQS_L1

M

M

4

Processor DDR2 M

M_

A_DQ63

AE14

A_DATA63
A_DATA62
A_DATA61
A_DATA60
A_DATA59
A_DATA58
A_DATA57
A_DATA56
A_DATA55
A_DATA54
A_DATA53
A_DATA52
A_DATA51
A_DATA50
A_DATA49
A_DATA48
A_DATA47
A_DATA46
A_DATA45
A_DATA44
A_DATA43
A_DATA42
A_DATA41
A_DATA40
A_DATA39
A_DATA38
A_DATA37
A_DATA36
A_DATA35
A_DATA34
A_DATA33
A_DATA32
A_DATA31
A_DATA30
A_DATA29
A_DATA28
A_DATA27
A_DATA26
A_DATA25
A_DATA24
A_DATA23
A_DATA22
A_DATA21
A_DATA20
A_DATA19
A_DATA18
A_DATA17
A_DATA16
A_DATA15
A_DATA14
A_DATA13
A_DATA12
A_DATA11
A_DATA10

M

A_DATA9
A_DATA8

M
M

A_DATA7

M

A_DATA6

M

A_DATA5
A_DATA4

M

A_DATA3

M
M

A_DATA2
A_DATA1

M
M

A_DATA0

A_CHECK7
A_CHECK6
A_CHECK5
A_CHECK4
A_CHECK3
A_CHECK2
A_CHECK1
A_CHECK0

_DM8

MA
MA

_DM7
_DM6

MA
MA

_DM5
_DM4

MA

_DM3

MA

_DM2

MA

_DM1

MA

_DM0

MA

A_DQS_L8

A_DQS_H7

A_DQS_L7

A_DQS_H5

A_DQS_L5

A_DQS_H4

A_DQS_L3

A_DQS_H2

A_DQS_L2

A_DQS_H0

A_DQS_L0

AG14
AG16
AD17
AD13
AE13
AG15
AE16
AG17
AE18
AD21
AG22
AE17
AF17
AF21
AE21
AF23
AE23
AJ26
AG26
AE22
AG23
AH25
AF25
AJ28
AJ29
AF29
AE26
AJ27
AH27
AG29
AF27
E29
E28
D27
C27
G26
F27
C28
E27
F25
E25
E23
D23
E26
C26
G23
F23
E22
E21
F17
G17
G22
F21
G18
E17
G16
E15
G13
H13
H17
E16
E14
G14

K25
J26
G28
G27
L24
K27
H29
H27

J25
AF15
AF19
AJ25
AH29
B29
E24
E18
H15

J28
J27
AD15
AE15
AG18
AG19
AG24
AG25
AG27
AG28
D29
C29
C25
D25
E19
F19
F15
G15

M_

A_DQ62

M_

A_DQ61
A_DQ60

M_

A_DQ59

M_

A_DQ58

M_
M_

A_DQ57
A_DQ56

M_
M_

A_DQ55
A_DQ54

M_

A_DQ53

M_

A_DQ52

M_

A_DQ51

M_
M_

A_DQ50
A_DQ49

M_
M_

A_DQ48
A_DQ47

M_
M_

A_DQ46
A_DQ45

M_
M_

A_DQ44

M_

A_DQ43

M_

A_DQ42

M_

A_DQ41
A_DQ40

M_
M_

A_DQ39
A_DQ38

M_
M_

A_DQ37
A_DQ36

M_
M_

A_DQ35
A_DQ34

M_
M_

A_DQ33
A_DQ32

M_

A_DQ31

M_

A_DQ30

M_
M_

A_DQ29

M_

A_DQ28
A_DQ27

M_
M_

A_DQ26
A_DQ25

M_
M_

A_DQ24
A_DQ23

M_
M_

A_DQ22

M_

A_DQ21

M_

A_DQ20
A_DQ19

M_

A_DQ18

M_
M_

A_DQ17
A_DQ16

M_
M_

A_DQ15
A_DQ14

M_
M_

A_DQ13
A_DQ12

M_

A_DQ11

M_
M_

A_DQ10

M_

A_DQ9

M_

A_DQ8
A_DQ7

M_
M_

A_DQ6
A_DQ5

M_
M_

A_DQ4
A_DQ3

M_
M_

A_DQ2
A_DQ1

M_
M_

A_DQ0

M_

A_DM7

M_

A_DM6
A_DM5

M_
M_

A_DM4
A_DM3

M_
M_

A_DM2

M_

A_DM1

M_

A_DM0

M

_A_DQS7

M

_A_DQS#7

M_A_DQS6

_A_DQS#6

M
M

_A_DQS5
_A_DQS#5

M
M

_A_DQS4
_A_DQS#4

M

_A_DQS3

M

_A_DQS#3

M

_A_DQS2

M
M

_A_DQS#2
_A_DQS1

M

_A_DQS#1

M

_A_DQS0

M

_A_DQS#0

M

M
M
M_A_DQS2
M
M
M
M
M

M
M
M
M
M
M
M
M_A_DQS#7

o SODIMM socket A (near)To SODIMM socket B (Far)

T

_A_DQS0
_A_DQS1

_A_DQS3
_A_DQS4
_A_DQS5
_A_DQS6
_A_DQS7

_A_DQS#0
_A_DQS#1
_A_DQS#2
_A_DQS#3
_A_DQS#4
_A_DQS#5
_A_DQS#6

3

emory Interface

M

_A_DQ[0..63] 8

M

_A_DM[0..7] 8

_A_DQS[0..7] 8

M

M_A_DQS#[0..7] 8

3

PL

ACE THEM CLOSE TO

U WITHIN 1"

CP

8VSUS

1.

R3

R3

58

58

39.2F

39.2F

1 2

63

63

R3

R3

39.2F

39.2F

1 2

A_CS#38,9

M_
M_

A_CS#28,9

M_

A_CS#18,9

M_

A_CS#08,9
B_CS#38,9

M_
M_

B_CS#28,9
B_CS#18,9

M_
M_

B_CS#08,9

M

_CKE38,9
_CKE28,9

M
M

_CKE18,9
_CKE08,9

M

_A_A[0..15]8,9

M

M

_A_BS#28,9
_A_BS#18,9

M

_A_BS#08,9

M
M

_A_RAS#8,9

M

_A_CAS#8,9

A_WE#8,9

M_

0.9V

DDR_VTERM

SM

T122T122

M_

ZN
ZP

M_

499

499

C

C

4.7U_0603

4.7U_0603

C

C

186

186

1000P

1000P

2

0.9V

CPU_

CPU_

M_VREF

VTT_SEN

M

_A_A15
_A_A14

M
M

_A_A13
_A_A12

M

_A_A11

M
M

_A_A10

M

_A_A9

M

_A_A8
_A_A7

M
M

_A_A6
_A_A5

M
M

_A_A4
_A_A3

M
M

_A_A2
_A_A1

M
M

_A_A0

2

M_VREF

SE

15

15

C5

C5

4.7U_0603

4.7U_0603

C1

C1

77

77

1000P

1000P

D1
C1
B1
A1

AK1

AJ
AH1
AG

L12

A

F12
E1

AH11

AJ11
AD27

AA25
AC25
AA24

AE29
AB31
AE30
AC31

M31
M29

L27

M25
M27

N24

AC26

N26

P25

Y25
N27
R24

P27
R25
R26
R27

T25
U25

T27

W24

N25

Y27

AA27
AA26

AB25
AB27

C

C

0.1U

0.1U

12
12

517

517

2
2
2
2
2

2

2

1

1.

8VSUS

R

R

351

351

2K/F

2K/F

C

C

R

R

518

518

352

352

1000P

1000P

2K/F

2K/F

B

B

U9

VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9

ME
VTT_SENSE
ME

ME
M

M
M
M

M
M
M
M

M
M
M
M

M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M

M
M
M

M
M
MA

U9

M

A1_CLK_H2

A1_CLK_L2

M

A1_CLK_H1

M

A1_CLK_L1

M
M

A1_CLK_H0

A1_CLK_L0

M
M

A0_CLK_H2

A0_CLK_L2

M
M

MVREF

MZN
MZP

A1_CS_L1
A1_CS_L0
A0_CS_L1
A0_CS_L0

B1_CS_L1
B1_CS_L0
B0_CS_L1
B0_CS_L0

B_CKE1
B_CKE0
A_CKE1
A_CKE0

A_ADD15
A_ADD14
A_ADD13
A_ADD12
A_ADD11
A_ADD10
A_ADD9
A_ADD8
A_ADD7
A_ADD6
A_ADD5
A_ADD4
A_ADD3
A_ADD2
A_ADD1
A_ADD0

A_BANK2
A_BANK1
A_BANK0

A_RAS_L
A_CAS_L

_WE_L

A

thlon 64 M2

Processor Socket

491

491

C

C

4.7U_0603

4.7U_0603

C

C

188

188

1000P

1000P

Si

Si

Si

Date: Sheet

Date: Sheet

Date: Sheet

A0_CLK_H1

A0_CLK_L1

M

A0_CLK_H0

M
M

A0_CLK_L0

M

B1_CLK_H2

B1_CLK_L2

M
M

B1_CLK_H1

B1_CLK_L1

M
M

B1_CLK_H0

M

B1_CLK_L0

M

B0_CLK_H2

M

B0_CLK_L2

B0_CLK_H1

M
M

B0_CLK_L1

B0_CLK_H0

M
M

B0_CLK_L0

DDR II: CMD/CTRL/CLK

DDR II: CMD/CTRL/CLK

M
M
M
M

M
M

M

509

509

C

C

4.7U_0603

4.7U_0603

C

C

179

179

1000P

1000P

ze Document Number Rev

ze Document Number Rev

ze Document Number Rev

AM

AM

AM

AE20
AE19
G20
G21
V27
W27
AG21
AG20
G19
H19
U27
U26

AL19
AL18
C19
D19
W29
W28
AJ19
AK19
A18
A19
U31
U30

AD31

B1_ODT0

AD29

B0_ODT0

AC27

A1_ODT0

AC28

A0_ODT0
B_ADD15

B_ADD14

M

B_ADD13
B_ADD12

M
M

B_ADD11
B_ADD10

M

M

B_ADD9
B_ADD8

M
M

B_ADD7

M

B_ADD6

M

B_ADD5
B_ADD4

M

B_ADD3

M
M

B_ADD2
B_ADD1

M
M

B_ADD0

B_BANK2
B_BANK1

M

B_BANK0

M
M

B_RAS_L

M

B_CAS_L

_WE_L

MB

526

526

C

C

0.22U

0.22U

C

C

190

190

180P

180P

D AM2 DDR II Memory I/F

D AM2 DDR II Memory I/F

D AM2 DDR II Memory I/F

M

_B_A15

N28

_B_A14

M

N29

M

_B_A13

AE31

_B_A12

M

N30

_B_A11

M

P29

M

_B_A10

AA29

M

_B_A9

P31

M

_B_A8

R29

_B_A7

M

R28

M

_B_A6

R31

_B_A5

M

R30

M

_B_A4

T31

_B_A3

M

T29

M

_B_A2

U29

_B_A1

M

U28

M

_B_A0

AA30
N31

AA31
AA28

AB29
AC29
AC30

521

521

24

24

C

C5

C5

0.22U

0.22U

C1

C1
180P

180P

Q

Q

Q

PROJECT :

PROJECT :

PROJECT :

C

0.22U

0.22U

C

C

82

82

191

191

180P

180P

uanta Computer Inc.

uanta Computer Inc.

uanta Computer Inc.

1

M

_CLKOUT1 8
_CLKOUT1# 8

M
M

_CLKOUT0 8
_CLKOUT0# 8

M

M

_CLKOUT4 8

M

_CLKOUT4# 8
_CLKOUT3 8

M
M

_CLKOUT3# 8

M_

ODT3 8,9
ODT2 8,9

M_
M_

ODT1 8,9
ODT0 8,9

M_

_B_A[0..15] 8,9

M

M

_B_BS#2 8,9
_B_BS#1 8,9

M

_B_BS#0 8,9

M
M

_B_RAS# 8,9

M

_B_CAS# 8,9

B_WE# 8,9

M_

DDR_VTERM

SM

25

25

C5

C5

0.22U

0.22U

C1

C1

84

84

180P

180P

ZN1

ZN1

ZN1

of

of

of

54

54

54

5

1Friday, May 08, 2009

1Friday, May 08, 2009

1Friday, May 08, 2009

1A

1A

1A

5

V

CC3

D D

Vout =1.25(1+R1/R2)
= 1.25 (1+20K/20K)
= 2.5V

If AMD SI is not used, the SID pin can be left unconnected and SIC
should have a 300-ȍ (±5%) pulldown to VSS.

1

.8VSUS

CP

U_SIC15

CP

U_SID15

C C

CP

UCLKP3

CP

UCLKN3

R105

R105

300_4

R103

R103
R102

R102

300_4
300_4

300_4
300_4

300_4

H_PROCHOT#

R93

R93

R95

R95

5

.8VSUS

1

U_PWRGD14

CP

CP

U_LDT_STOP#12,14

CP

U_LDT_RST#12,14

B B

V

CC3

V

CC3

A A

V

CC3

PU

PU

10

10

1

S

VO

HDN

2

D

GN

3

N

VI

SET

G923-330T1UF

G923-330T1UF

PC

PC

139

139

10U_0805

10U_0805

R114

R114

*300

*300

R137

R137

*300

*300

*0

R130*0R130

*0

R115*0R115

3900P

3900P

C166

C166

R134

R134
169_0603F

169_0603F

3900P

3900P

C163

C163

R104

R104

R107

R107

*

*

*6

*6

680

680

80

80

1.8VSUS

1.8VSUS

R361

R361
*1

*1

R362

R362

0K

0K

300

300

2

1 3

*

*

MMBT3904

MMBT3904

Q27

Q27

R372 0R372 0

R960R96

*10K

*10K

TH

MDAT

1

2
2

*10K

*10K

THMCLK

1

R3840R384

4

5

U_SIC_R

CP
CP

U_SID_R

R1100R110

R1110R111

R1090R109

R106

R106
*6

*6

80

80

V

0
Q29

Q29

2N7002E-LF

2N7002E-LF

*

*

3

3

Q30

Q30

2N7002E-LF

2N7002E-LF

*

*
0

CC3

CP

CP

R370

R370
*4

*4

MB

MBCLK

0.2A

R150

R150

P

P
20K_0603F

20K_0603F

P

P

R149

R149

20K_0603F

20K_0603F

R135300 R135300

U_CLKIN_SC_P

U_CLKIN_SC_N

0

0

0

.7K

.7K

DATA

2.5V

149

149

PC

PC
100U/6.3V/3528

100U/6.3V/3528

CP

U_ALL_PWROK

CP

U_LDTSTOP#

C

PU_HT_RESET#

U_PROCHOT# 14

CP

MBDATA 12,32

CLK 12, 32

MB

CP

U_VDDA

4

CP

U_TEST27_SINGLECHAIN

CP

U_TEST26_BURNIN#

PU_PRESENT#

C

PU_TEST25_H_BYPASSCLK_H

C
CP

U_TEST21_SCANEN

CP

U_TEST20_SCANCLK2

CP

U_TEST24_SCANCLK1

CP

U_TEST22_SCANSHIFTEN

CP

U_TEST12_SCANSHI FTENB

PU_TEST15_BP1

C

PU_TEST14_BP0

C

PU_TEST25_L_BYPASSCLK_L

C

PU_TEST19_PLLTEST0

C
C

PU_TEST18_PLLTEST1

1

.8VSUS

R97

R97
300_4

300_4

U_DBREQ#

CP

CP

T127T1
T136T1
T129T1
T128T128
T123T1

T66T6

U_DBRDY

6

27

U_TCK

CP

CP

U_TMS

36

CP

U_TDI

29

CP

U_TRST#

CP

U_TDO

23

C144

C144

CPU Thermal
Senser

0.1U

0.1U

C567

C567

2200P_0603

2200P_0603

C128

C128

R88

R88

_4

_4

*0

*0

4

R381

R381
R113

R113
R112

R112
R140

R140
R142

R142
R139

R139
R141

R141
R144

R144
R143

R143
R375

R375
R108

R108
R371

R371
R369

R369
R374

R374

CP

CO

REFB+V34

CO

REFB-34

Connector

HDT

1.

8VSUS

*0.1U/10V_4

*0.1U/10V_4

R385

R385

H_T

HERMDA

HERMDC

H_T

SHDN#1

SYS_

U_CORE

1 2
3 4
5 6
7 8

9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24

KEY

KEY

CN10

CN10
*HDT CONN

*HDT CONN

200_6

200_6

U6

U6

1

VCC

2

P

DX

3

DX

N

4

-OVT

G781-1

G781-1

SOP8-4_9-65

SOP8-4_9-65

M

M

.8VSUS

1

*300

*300
300

300
1K/F

1K/F
510/F

510/F
300

300
*300

*300
*300

*300
*300

*300
*300

*300
*300

*300
*300

*300
510/F

510/F
300

300
300

300

close to CPU

.8VSUS

1

25

CC3

V

sub-address:9Ah

SMCLK

SM

PR

PR

PR

PR

DATA

-A
GND

C564

C564

*0.1U

*0.1U

CP

LT

3110/F

3110/F

3010/F

3010/F

U_VDDA

CC3

V

8
7
6
5

3

L51

L51

V

LDT_RUN

R145*0R145

CC3

V

THMCLKTHERM_VCC
TH

MDAT

HERM_ALERT#

T

3

R82

R82
*4

*4

.7K

.7K

40ohm_600mA

40ohm_600mA

*0

1

.8VSUS

*

*

MMBT3904

MMBT3904

Q15

Q15

1K

1K

R448

R448

C541

C541

7U_0603

7U_0603

4.

4.

7

T67T6

30

T130T1
T135T1

35

R379

R379
R380

R380

place them to CPU within 1"

25

T125T1
T124T1

24

T61T6

1
33

T133T1

T65T6

5

T142T1

42

T132T1

32
37

T137T1

38

T138T1

40

T140T1
T107T1

07

T101T1

01

T94T9

4
7

T97T9

00

T100T1
T103T1

03

T98T9

8

T99T9

9

T108T1

08

R81

R81
*

*

10K

10K

2

C

PU_HT_RESET#

13

/F_4

/F_4

A

DDA_RUN

V

C

PU_HT_RESET#
CP
CP

CP
CP

CP

CP
CP

CP
CP

CP
CP

CP
CP
CP

C

PU_TEST25_H_BYPASSCLK_H
CP
C

PU_TEST19_PLLTEST0
C

PU_TEST18_PLLTEST1

PU_TEST17_BP3

C
C

PU_TEST16_BP2
C

PU_TEST15_BP1
C

PU_TEST14_BP0
CP

CP
CP
H_T
H_T
CP
CP

CP
CP

CP
CP

THLON Control and Debug

12

C543

C543

C544

C544

0.

0.

22U

22U

3300pF

3300pF

U_ALL_PWROK
U_LDTSTOP#

U_SIC_R
U_SID_R

CP
CP

_SHDN#112

CP

SYS_

M_THERM#20,32

MX

HERM_ALERT# 15

U_HTREF1
U_HTREF0

U_THERMTRIP#

44.2F

44.2F

44.2F

44.2F

U_VDDIO_SUS_FB_H

U_VDDIO_SUS_FB_H
U_VDDIO_SUS_FB_L

U_CLKIN_SC_P
U_CLKIN_SC_N

U_DBRDY
U_TMS

U_TCK
U_TRST#
U_TDI

U_TEST25_L_BYPASSCLK_L

U_TEST12_SCANSHIFTENB
U_TEST07_ANALOG_T

U_TEST6_DIECRACKMON

HERMDC

HERMDA
U_TEST3_GATE0
U_TEST2_DRAIN0

U_RSVD_MA0_CLK3_P
U_RSVD_MA0_CLK3_N

U_RSVD_MB0_CLK3_P
U_RSVD_MB0_CLK3_N

NB

T

R790R79

SHDN#1

2

C10

VD

D10

VD

C7

R

C9

PW

D8

LD

AL6

SI

AK6

SI

V8

HT

V7

HT

G2

VD

G1

VD

AK11

V

AL11

V

A8

CL

B8

CL

B6

DB

AL9

TM

AH10

TC

AJ10

TR

AL10

TD

A10

T

B10

T

F10

T

E9

T

AJ7

T

F6

T

D6

T

E7

T

F8

T

C5

T

AH9

T

E5

T

AJ5

T

AG9

T

AG8

T

AH7

T

AJ6

T

L25

R

L26

R

L31

R

L30

R

W26

R

W25

R

AE27

R

U24

R

V24

R

AE28

R

AD25

R

AE24

R

AE25

R

AJ18

R

AJ20

R

C18

R

C20

R

G24

R

G25

RSVD18

H25

R

V29

R

W30

R

AM
Processor Socket

CC3

V

0

R780R78

0

R3870R387

0

R80*0R80

*0

SMBUS SLAVE ADDRESS

G781

2

U9D

U9D

DA2
DA1

ESET_L

ROK

TSTOP_L

C
D

_REF1
_REF0

C
D_FB_H
D_FB_L

DDIO_FB_H
DDIO_FB_L

KIN_H
KIN_L

RDY

S
K
ST_L
I

EST25_H
EST25_L
EST19
EST18
EST13
EST9
EST17
EST16
EST15
EST14
EST12

EST7
EST6
EST5
EST4
EST3
EST2

SVD0
SVD1
SVD2
SVD3

SVD4
SVD5
SVD6
SVD7
SVD8
SVD9

SVD10
SVD11
SVD12
SVD13
SVD14
SVD15
SVD16
SVD17

SVD19
SVD20
SVD21

D NPT M2 SOCKET

VCC3

R390

R390
10K

10K

2

1 3

T3904

T3904

MMB

MMB

Q14

Q14

98 (CPU)

HERMTRIP_L

T

P

ROCHOT_L

PU_PRESENT_L

PSI

NC#
NC#
NC#
NC#

DB

REQ_L

T

EST29_H

EST29_L

T

NC#
NC#
NC#
NC#

T

EST24

T

EST23
EST22

T

EST21

T

EST20

T

T

EST28_H

T

EST28_L

T

EST27
EST26

T

EST10

T

EST8

T

R

SVD22

R

SVD23
SVD24

R

SVD25

R

SVD26

R

MISC

MISC

R

SVD27

R

SVD28
SVD29

R

SVD30

R
R

SVD31

R

SVD32
SVD33

R

SVD34

R

SVD35

R
R

SVD36

RSVD37

R77

R77
300

300

D5

VI

D4

VI
VI

D3

VI

D2

VI

D1
D0

VI

_L

1
2
3
4

O

TD

5
6
7
8

SYS_

1

Add component to BOM

Vender suggest

.8VSUS

1

HERMTRIP#

H_T

AK7

ROCHOT#

H_P

AL7

D2
D1
C1
E3
E2
E1

PU_PRESENT#

C

AL3
F1
H3

H4
H20
H21

CP

U_DBREQ#

A5

CP

U_TDO

AK10

CP

U_TEST29_H_FBCLKOUT_P

C11

CP

U_TEST29_L_FBCLKOUT_N

D11
AE7
AD19
AE8
AD18

U_TEST24_SCANCLK1

CP

AK8

CP

U_TEST23_TSTUPD

AH8

CP

U_TEST22_SCANSHIFTEN

AJ9

CP

U_TEST21_SCANEN

AL8

CP

U_TEST20_SCANCLK2

AJ8

U_TEST28_H_PLLCHRZ_P

CP

J10

U_TEST28_L_PLLCHRZ_N

CP

H9

CP

U_TEST27_SINGLECHAIN

AK9

CP

U_TEST26_BURNIN#

AK5

C

PU_TEST10_ANALOGOUT

G7

CP

U_TEST08_DIG_T

D4

PU_MA_RESET#

C

E20

PU_MB_RESET#

C

B19
AL4

AK4
AK3

CP

U_RSVD_VIDSTRB1

F2

U_RSVD_VIDSTRB0

CP

F3

CP

U_VDDNB_FB_H

G4

CP

U_VDDNB_FB_L

G3

CP

U_CORE_TYPE

G5

Y31
Y30
AG31
V31
W31
AF31

SHDN# 38

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Shee t

Date: Shee t

.8VSUS1.8VSUS

1

R376

R376
10K

R373

R373
300

300

PSI#

9

T59T5

PLACE IT CLOSE TO CPU WITHIN 1"
ROUTE AS 80 Ohm DIFFERENTIAL PAIR

AM

AM

AM

D AM2 CTRL & DEBUG

D AM2 CTRL & DEBUG

D AM2 CTRL & DEBUG

10K

R101

R101
300

300

2

1 3

T3904

T3904

MMB

MMB

Q28

Q28

34

PSI_L is a Power Status Indicator
signal. This signal is asserted when
the processor is in a low powerstate.
PSI_L should be connected to the power
supply controller, if the controller
supports “skipmode, or diode emulation
mode”. PSI_L is asserted by the
processor during the C3 and S1 states.

R368

R368

80.6F

80.6F

139T139

T

T

126T126

T

131T131

134T134

T

4

T64T6
T

115T115

T

119T119

T

143T143
144T144

T
T58T5

8

T57T5

7

T62T6

2

T63T6

3
0

T60T6

T92T9

2

T96T9

6

T91T9

1

T90T9

0

T95T9

5

T93T9

3

uanta Computer Inc.

uanta Computer Inc.

uanta Computer Inc.

Q

Q

Q

PROJECT :

PROJECT :

PROJECT :

1

CP

U_THERMTRIP# 15

VID

5 34

VID

4 34
3 34

VID
VID

2 34
1 34

VID

0 34

VID

141T141

T

R3830R383
0

ZN1

ZN1

ZN1

64

64

64

6

1A

1A

1A

1Friday, May 08, 2009

1Friday, May 08, 2009

1Friday, May 08, 2009

of

of

of

5

4

3

2

1

PROCESSOR POWER AND GROUND

H

H

U9

G

G

U9

U9

A3

VSS1

A7

CPU_

CORE

8VSUS

O28
O27
O26
O25
O24
O23
O22
O21
O20
O19
O18
O17
O16
O15
O14
O13
O12
O11
O10

1.

Y29
Y28
Y26
Y24
V30
V28
V26
V25
T30
T28
T26
T24
P30
P28
P26
P24
M30
M28
M26
M24

O9

AF30

O

AD30

O8

AD28

O7

AD26

O6

AC24

O5

AB30

O4

AB28

O3

AB26

O2

AB24

O1

Y23
W22
V23
U22
T23
R22
P23
P21
N22
N20
M23
M21
L22
L20
AF11
AE12
AD23
AD11
AC22
AC20
AC18
AC16
AC14
AC12

51

51

C5

C5
10U_0603

10U_0603

52

52

C5

C5
10U_0603

10U_0603

CORE

U9

U9

E

E10

G10
G12

AA8
AA1
AA1
AA1
AA1
AA1

AB7

AB9
AB11

AC4
AC5
AC8

AC10

AD2
AD3
AD7
AD9

AE10

AF7

AF9

AG4
AG5
AG7
AH2
AH3

H11

H23

C5

C5

0.01U

0.01U

E

A4

VDD1

A6

VDD2

B5

9

VDD2

B7

0

VDD3

C6

3

VDD3

C8

VDD3

4

D7

7

VDD3

D9

8

VDD3

E8

VDD4

1
2

VDD4

F9

5

VDD4

F11

6

VDD4
VDD4

9
0

VDD5
VDD3

0

VDD4

2

VDD5

4

VDD6

6

VDD7

8

VDD8
VDD9
VDD1

0
1

VDD1
VDD1

2

ER1

ER1

3

VDD1
VDD1

4

POW

5
6
7
8
9
0
1
2
3
4
5
6
7
8
1
2
5
6
9
0
3
4
7
8
1
2
3

At

hlon 64 M2

rocessor Socket

P

60

60

C5

C5
180P

180P

C4

C4

0.22U

0.22U

POW

32

32

VDD1
VDD1
VDD1
VDD1
VDD1
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2
VDD2

B3

VDD2

C2

VDD3

C4

VDD3

D3

VDD3

D5

VDD3

E4

VDD3

E6

VDD4

F5

VDD4

F7

VDD4

G6

VDD4

G8

VDD4

H7

VDD5
VDD5
VDD5

57

57

C

C

459

459

0.22U

0.22U

D D

C C

B B

CORE

CPU_

61

1.

C5

C5

0.22U

0.22U

8VSUS

61

22U/6.3V_8

22U/6.3V_8

556

556

559

559

C

C

C

C

0.22U

0.22U

0.22U

0.22U

C

C

C

C

426

426

427

427

22U/6.3V_8

22U/6.3V_8

VDD1
VDD1
VDD1
VDD1
VDD1
VDD1
VDD1

VDD9
VDD9
VDD9
VDD9
VDD9
VDD9
VDD9
VDD9
VDD9
VDD9
VDD8
VDD8
VDD8
VDD8
VDD8
VDD8
VDD8
VDD8
VDD8
VDD8
VDD7
VDD7
VDD7
VDD7
VDD7
VDD7
VDD7
VDD7
VDD7
VDD7
VDD6
VDD6
VDD6
VDD6
VDD6
VDD6
VDD6
VDD6
VDD6
VDD6
VDD5
VDD5
VDD5
VDD5
VDD5
VDD5

CPU_

06
05
04
03
02
01
00

9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4

CORE

CPU_

R10
R8
R5
R4
P19
P17
P15
P13
P11
P9
P7
N18
N16
N14
N12
N10
N8
M19
M17
M15
M13
M11
M9
M7
M3
M2
L18
L16
L14
Y19
Y17
L12
L10
L8
L5
L4
K23
K21
K19
K17
K15
K13
K11
K9
K7
J24
J22
J20
J18
J16
J14
J12
J8

47

47

C5

C5
10U_0603

10U_0603

CORE

CPU_

R12

07

VDD1

R14

VDD1

08

R16

09

VDD1

R18

10

VDD1

R20

11

VDD1

T2

VDD1

12

T3

13

VDD1

T7

14

VDD1

T9

VDD1

15

T11

16

VDD1

T13

17

VDD1

T15

18

VDD1

T17

VDD1

19

T19

20

VDD1

T21

VDD1

21

U8

22

VDD1

U10

VDD1

23

U12

24

VDD1

U14

25

VDD1

U16

VDD1

26

U18

VDD1

27

U20

VDD1

28

V9

29

VDD1

V11

VDD1

30

V13

31

VDD1

V15

VDD1

32

V17

VDD1

33

V19

VDD1

34

V21

VDD1

35

W4

36

VDD1

W5

VDD1

37

W8

38

VDD1

W10

VDD1

39

W12

40

VDD1

W14

VDD1

41

W16

42

VDD1

W18

VDD1

43

W20

44

VDD1

Y2

45

VDD1

Y3

46

VDD1

Y7

VDD1

47

Y9

VDD1

48

Y11

49

VDD1

Y13

VDD1

50

Y15

51

VDD1

Y21

VDD1

52

AA20

53

VDD1

AA22

VDD1

54

AB13

VDD1

55

AB15

VDD1

56

AB17

57

VDD1

AB19

58

VDD1

AB21

VDD1

59

AB23

60

VDD1

BOT

TOMSIDE DECOUPLING

46

548

548

C

C
10U_0603

10U_0603

46

C5

C5
10U_0603

10U_0603

549

549

C

C
10U_0603

10U_0603

U9

U9

F

F

VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI
VDDI

VDDI

VDDI

VDDI

ER2

ER2

VDDI
VDDI

POW

POW

VDDI
VDDI
VDDI
VDDI
VDDI

V

DD184
DD183

V
V

DD182
DD181

V
V

DD180
DD179

V
V

DD178
DD177

V

DD176

V

DD175

V
V

DD174

V

DD173
DD172

V
V

DD171
DD170

V
V

DD169
DD168

V
V

DD167

V

DD166

V

DD165
DD164

V

DD163

V
V

DD162
DD161

V

50

50

C5

C5
10U_0603

10U_0603

A9

A1
AA4
AA5
AA7
AA9

AA1
AA13
AA15
AA17
AA19
AA21
AA23

AB2
AB3
AB8

AB10
AB12
AB14
AB16
AB18
AB20
AB22

AC7
AC9

AC11
AC13
AC15
AC17
AC19
AC21
AC23

AD8

AD10
AD12
AD14
AD16
AD20
AD22
AD24

AE4
AE5
AE9

AE11

AF2

AF3

AF8

AF10
AF12
AF14
AF16
AF18
AF20
AF22
AF24
AF26
AF28

AG10

54

54

C5

C5
10U_0603

10U_0603

VSS2
VSS3

1

VSS4
VSS5
VSS6
VSS7
VSS8

1

VSS9
VSS1
VSS1
VSS1
VSS1
VSS1
VSS1
VSS1
VSS1
VSS1
VSS1
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS3
VSS3
VSS3
VSS3
VSS3
VSS3
VSS3
VSS3
VSS3
VSS3
VSS4
VSS4
VSS4
VSS4
VSS4
VSS4
VSS4
VSS4
VSS4
VSS4
VSS5
VSS5
VSS5
VSS5
VSS5
VSS5
VSS5
VSS5
VSS5
VSS5
VSS6

At

hlon 64 M2

rocessor Socket

P

6090022000_4

6090022000_4

0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
1

CPU_

53

53

C5

C5
10U_0603

10U_0603

GND1

GND1

CORE

VSS1

21
20

VSS1

19

VSS1
VSS1

18
17

VSS1
VSS1

16
15

VSS1
VSS1

14
13

VSS1

12

VSS1

11

VSS1
VSS1

10
09

VSS1

08

VSS1
VSS1

07
06

VSS1

05

VSS1

04

VSS1
VSS1

03
02

VSS1
VSS1

01
00

VSS1

VSS9

9
8

VSS9

7

VSS9
VSS9

6

VSS9

5

VSS9

4
3

VSS9
VSS9

2
1

VSS9
VSS9

0

VSS8

9

VSS8

8

VSS8

7
6

VSS8
VSS8

5
4

VSS8
VSS8

3
2

VSS8
VSS8

1
0

VSS8
VSS7

9
8

VSS7

7

VSS7

6

VSS7
VSS7

5

VSS7

4
3

VSS7
VSS7

2
1

VSS7
VSS7

0
9

VSS6
VSS6

8

VSS6

7

VSS6

6
5

VSS6

4

VSS6
VSS6

3
2

VSS6

154

154

C

C

*22U/6.3V_8

*22U/6.3V_8

H10
H8
G11
G9
F30
F28
F26
F24
F22
F20
F18
F16
F14
F4
E11
D30
D28
D26
D24
D22
D20
D18
D16
D14
C3
B30
B28
B26
B24
B22
B20
B18
B16
B14
B11
B9
B4
AL5
AK30
AK28
AK26
AK24
AK22
AK20
Y16
Y14
AK18
AK16
AK14
AK2
AH30
AH28
AH26
AH24
AH22
AH20
AH18
AH16
AH14
AG11

53

53

C1

C1

*22U/6.3V_8

*22U/6.3V_8

52

52

C1

C1

*22U/6.3V_8

*22U/6.3V_8

1

.8VSUS

.8VSUS

1

U9

T22

VSS1

83

T20

VSS1

82

T18

81

VSS1

T16

80

VSS1

T14

VSS1

79

T12

78

VSS1

T10

VSS1

77

T8

76

VSS1

R23

VSS1

75

R21

74

VSS1

R19

73

VSS1

R17

72

VSS1

R15

VSS1

71

R13

70

VSS1

R11

69

VSS1

R9

VSS1

68

R7

67

VSS1

P22

66

VSS1

P20

65

VSS1

P18

VSS1

64

P16

63

VSS1

P14

VSS1

62

P12

61

VSS1

P10

VSS1

60

P8

59

VSS1

P3

58

VSS1

P2

VSS1

57

N23

VSS1

56

N21

VSS1

55

N19

54

VSS1

N17

VSS1

53

Y18

52

VSS1

K22

VSS1

51

K20

VSS1

50

K18

VSS1

49

K16

VSS1

48

K14

47

VSS1

K12

VSS1

46

K10

45

VSS1

K8

VSS1

44

K3

43

VSS1

K2

VSS1

42

J23

41

VSS1

J21

VSS1

40

J19

39

VSS1

J17

38

VSS1

J15

37

VSS1

J13

VSS1

36

J11

VSS1

35

J9

34

VSS1

J7

VSS1

33

J5

32

VSS1

J4

VSS1

31

H30

30

VSS1

H28

VSS1

29

H26

VSS1

28

H24

VSS1

27

H22

26

VSS1

H18

25

VSS1

H16

VSS1

24

H14

23

VSS1

H12

VSS1

22

6090022000_4

6090022000_4

DECOUPLI

GND2

GND2

NG BETWEEN PROCESSOR AND DIMMs

VSS1
VSS1
VSS1
VSS1
VSS1
VSS1
VSS1
VSS1
VSS1
VSS1
VSS1
VSS1
VSS1
VSS1
VSS1
VSS1
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2
VSS2

U4

84

U5

85

U7

86

U9

87

U11

88

U13

89

U15

90

U17

91

U19

92

U21

93

U23

94

V2

95

V3

96

V10

97

V12

98

V14

99

V16

00

V18

01

V20

02

V22

03

W9

04

W11

05

W13

06

W15

07

W17

08

W19

09

W21

10

W23

11

Y8

12

Y10

13

Y12

14

W7

15

Y20

16

Y22

17

K24

18

K26

19

K28

20

K30

21

L7

22

L9

23

L11

24

L13

25

L15

26

L17

27

L19

28

L21

29

L23

30

M8

31

M10

32

M12

33

M14

34

M16

35

M18

36

M20

37

M22

38

N4

39

N5

40

N7

41

N9

42

N11

43

N13

44

N15

45

PLACE CLOSE TO PROCESSOR AS POSSIBLE

29

28

28

C4

C4

4.7U_0603

4.7U_0603

31

31

C4

C4

4.7U_0603

4.7U_0603

30

30

C4

C4

4.7U_0603

4.7U_0603

29

C4

C4

4.7U_0603

4.7U_0603

C4

C4

0.22U

0.22U

C

C

C

453

453

0.22U

0.22U

C

460

460

0.22U

0.22U

C

C

462

462

0.22U

0.22U

C

C

34

34

456

456

0.22U

0.22U

C

C

438

438

0.22U

0.22U

C

C

442

442

0.01U

0.01U

7

C4

C4
180P

180P

50

50

CPU_

CORE

C4

C

C

C

C

C

C

C

531

531

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

A A

C

527

527

528

528

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

5

C

C5

C5

506

506

32

32

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

C

C

C

507

507

504

504

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

C4

C4

C5

C5

08

08

79

79

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

4

C4

C4

C4

C4

80

80

22U/6.3V_8

22U/6.3V_8

81

81

C4

82

82

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

22U/6.3V_8

C5

C5

C4

C4

85

85

22U/6.3V_8

22U/6.3V_8

30

30

C5

C5

03

03

22U/6.3V_8

22U/6.3V_8

3

C4

C4

0.01U

0.01U

C4

C4

43

43

39

39

180P

180P

C

C

454

454

180P

180P

uanta Computer Inc.

uanta Computer Inc.

uanta Computer Inc.

Q

Q

Q

PROJECT :

PROJECT :

Size Document Number Rev

ze Do cument Number Rev

ze Do cument Number Rev

Si

Si

Date: Sheet

Date: Sheet

2

Date: Sheet

D AM2 PWR & GND

D AM2 PWR & GND

D AM2 PWR & GND

AM

AM

AM

PROJECT :

ZN1

ZN1

ZN1

74

74

74

1

1A

1A

1A

of

1Friday, May 08, 2009

of

1Friday, May 08, 2009

of

1Friday, May 08, 2009

5

1.

8VSUS

4

3

.8VSUS

1

2

1

8

103

111

104

112

117

_B_A[0..15]5,9

313 4.7K

313 4.7K

09 *4.7K

09 *4.7K

M

_B_DM[0..7]5

_B_DQS[0..7]5

M

M

_B_DQS#[0..7]5

C

C

411 0.1U

411 0.1U

2.2U_0805

2.2U_0805

3080R3080
R

M

12

M
M
M
M

M
M

M
M
M_
M_
M_

M_
M_

PDAT_
PCL

C

C

C435

C435

1.5P

1.5P

C

C

1.5P

1.5P

SA0

SA1

12

312*0R312*0
R

M
M
M

_CLKOUT35
_CLKOUT3#5
_CLKOUT45
_CLKOUT4#5

_CKE25,9
_CKE35,9

_B_RAS#5,9
_B_CAS#5,9

B_WE#5,9
B_CS#05,9
B_CS#15,9

ODT25,9
ODT35,9

SMB3,15,19,30

K_SMB3,15,19,30

395

395

M

_CLKOUT3

M

_CLKOUT3#

M

_CLKOUT4

441

441

M

_CLKOUT4#

_B_BS#05,9
_B_BS#15,9
_B_BS#25,9

_B

_B

1 2

3

_CLKOUT3

M

_CLKOUT3#

M
M

_CLKOUT4

M

_CLKOUT4#

S

A0_B
A1_B

S

394 0.1U

394 0.1U

C

C

M

VREF_DIM

C

C

402

402

0.1U

0.1U

M

_B_A0
_B_A1

M

_B_A2

M

_B_A3

M
M

_B_A4
_B_A5

M
M

_B_A6
_B_A7

M

_B_A8

M

_B_A9

M

_B_A10

M
M

_B_A11
_B_A12

M
M

_B_A13
_B_A14

M
M

_B_A15

B_DM0

M_
M_

B_DM1
B_DM2

M_
M_

B_DM3
B_DM4

M_
M_

B_DM5
B_DM6

M_
M_

B_DM7

_B_DQS0

M

_B_DQS1

M
M

_B_DQS2

M

_B_DQS3
_B_DQS4

M
M

_B_DQS5
_B_DQS6

M
M

_B_DQS7

M

_B_DQS#0

M

_B_DQS#1

M

_B_DQS#2
_B_DQS#3

M

_B_DQS#4

M
M

_B_DQS#5
_B_DQS#6

M
M

_B_DQS#7

102

A0

101

A1
A2
A3
A4
A5
A6
A7
A8
A9

0

A1

1

A1
A1

2
3

A1

4

A1
A1

5

BA0
BA1
BA2

DM
DM
DM
DM
DM
DM
DM
DM

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

CK0
CK0
CK1
CK1

CKE0
CKE1

RAS
CAS
WE
S0
S1

OD
OD

SA0
SA1

SDA
SCL

VDDs

1

VREF

2

VSS0

3

VSS1

8

VSS2

9

VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS1
VSS11
VSS12
VSS1
VSS1
VSS1
VSS16
VSS17
VSS1
VSS1
VSS2

VDD081VDD182VDD287VDD388VDD495VDD596VDD6

0
1
2
3
4
5
6
7

S0
S1
S2
S3
S4
S5
S6
S7

S0
S1
S2
S3
S4
S5
S6
S7

T0
T1

pd

(H=11)

0

3
4
5

4

3

1

8
9
0

VSS2

VSS2

VSS2260VSS2

66

65

59

71

5

VSS2

72

100

99
98
97
94
92
93
91

105

90
89

116

86
84

107
106

85
10

26
52

67
130
147
170
185

13

31

51

70
131
148
169
188

11

29

49

68
129
146
167
186

30

32
164
166

79

80
108

113
109
110
115

114
119

198
200

195
197

199

12

15

18

21

24

27

28

33

34

39

40

41

42

47

48

53

54

117

118

103

111

104

M

_A_A[0..15]5,9

720R2720
R2

M
M
M
M

M
M

M
M
M_
M_
M_

M_
M_

PDAT_
PCL

C3

C3

2.2U_0805

2.2U_0805

M

C4

C4

1.5P

1.5P

M
M

C4

C4

1.5P

1.5P

M

_A

SA0

A1_A

S

12

12

810R2810
R2

_A_BS#05,9

M
M

_A_BS#15,9

M

_A_BS#25,9

_CLKOUT05
_CLKOUT0#5
_CLKOUT15
_CLKOUT1#5

_CKE05,9
_CKE15,9

_A_RAS#5,9
_A_CAS#5,9

A_WE#5,9
A_CS#05,9
A_CS#15,9

ODT05,9
ODT15,9

SMB3,15,19,30

K_SMB3,15,19,30

67

67

1 2

_CLKOUT0

36

36

_CLKOUT0#
_CLKOUT1

37

37

_CLKOUT1#

5

273 *4.7K

273 *4.7K

R

R

VCC3

R

R

259 *4.7K

259 *4.7K

D D

_A : 00

SA

_A_DM[0..7]5

M

C C

M

_A_DQS[0..7]5

_A_DQS#[0..7]5

M

B B

VCC3

383 0.1U

383 0.1U

C

C

8VSUS

1.

A A

_CLKOUT0

M
M

_CLKOUT0#

M

_CLKOUT1

M

_CLKOUT1#

A0_A

S
S

A1_A

361 0.1U

361 0.1U

C

C

M

VREF_DIM

C

C

370

370

0.1U

0.1U

_A_A0

M

_A_A1

M

_A_A2

M
M

_A_A3
_A_A4

M
M

_A_A5
_A_A6

M

_A_A7

M

_A_A8

M

_A_A9

M
M

_A_A10
_A_A11

M
M

_A_A12
_A_A13

M
M

_A_A14
_A_A15

M

M_

A_DM0
A_DM1

M_
M_

A_DM2
A_DM3

M_
M_

A_DM4
A_DM5

M_
M_

A_DM6
A_DM7

M_

_A_DQS0

M
M

_A_DQS1

M

_A_DQS2
_A_DQS3

M
M

_A_DQS4
_A_DQS5

M
M

_A_DQS6
_A_DQS7

M
M

_A_DQS#0

M

_A_DQS#1
_A_DQS#2

M

_A_DQS#3

M
M

_A_DQS#4
_A_DQS#5

M
M

_A_DQS#6
_A_DQS#7

M

102

A0

101

A1

1
2

3
8
9

VDD081VDD182VDD287VDD388VDD495VDD596VDD6

A2
A3
A4
A5
A6
A7
A8
A9

0

A1
A1

1
2

A1

3

A1
A1

4
5

A1
BA0

BA1
BA2

0

DM
DM

1
2

DM

3

DM
DM

4

DM

5

DM

6
7

DM

S0

DQ
DQ

S1

DQ

S2

DQ

S3

DQ

S4
S5

DQ
DQ

S6
S7

DQ

S0

DQ
DQ

S1
S2

DQ
DQ

S3
S4

DQ

S5

DQ

S6

DQ
DQ

S7

CK0
CK0
CK1
CK1

CKE0
CKE1

RAS
CAS
WE
S0
S1

T0

OD

T1

OD
SA0

SA1
SDA

SCL

pd

VDDs
VREF
VSS0

VSS1

(H=6.5)

VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11

2

VSS1
VSS1

3
4

VSS1
VSS15
VSS16
VSS1

7

2

1

VSS1

8

VSS1

9

VSS20

VSS2

VSS2

60

59

3

VSS2

65

100

99
98
97
94
92
93
91

105

90
89

116

86
84

107
106

85
10

26
52

67
130
147
170
185

13

31

51

70
131
148
169
188

11

29

49

68
129
146
167
186

30

32
164
166

79

80
108

113
109
110
115

114
119

198
200

195
197

199

12

15

18

21

24

27

28

33

34

39

40

41

42

47

48

53

54

112

VDD8

VDD7

VDD9

SO-DIMM

SO-DIMM

0

9

8

7

6

5

4

VSS3

VSS2

VSS2

VSS2

VSS2

VSS2

VSS2

78

77

72

71

66

122

121

CN2

CN2

0

1

DQ
DQ
DQ

VDD1

VDD1

DQ
DQ
DQ
DQ
DQ
DQ
DQ

10

DQ
DQ

11
12

DQ

13

DQ
DQ

14
15

DQ

16

DQ

17

DQ
DQ

18
19

DQ
DQ

20
21

DQ
DQ

22
23

DQ

24

DQ
DQ

25

DQ

26

DQ

27
28

DQ
DQ

29
30

DQ
DQ

31

DQ

32

DQ

33

DQ

34
35

DQ
DQ

36
37

DQ
DQ

38
39

DQ
DQ

40
41

DQ
DQ

42
43

DQ

44

DQ

45

DQ
DQ

46

DQ

47
48

DQ
DQ

49
50

DQ
DQ

51
52

DQ
DQ

53

DQ

54

DQ

55
56

DQ

57

DQ
DQ

58
59

DQ
DQ

60
61

DQ
DQ

62
63

DQ

NC1
NC2
NC3
NC4

NC/

TEST

G

uidePin
uidePin

G

VSS5
VSS5
VSS5
VSS5
VSS5
VSS5
VSS5
VSS4
VSS48
VSS4
VSS4
VSS4
VSS44
VSS43
VSS4
VSS4
VSS4
VSS39
VSS38
VSS3

3

2

1

VSS3
VSS3
VSS34

VSS3

VSS3

VSS3

132

128

127

DDRII_SODIMM_H_6.5

DDRII_SODIMM_H_6.5

4

2

2

A_DQ0

M_

5

0
1
2
3
4
5
6
7
8
9

6
5
4
3
2
1
0
9

7
6
5

2
1
0

7
6
5

A_DQ1

M_

7

A_DQ2

M_

17

M_

A_DQ3

19

A_DQ5

M_

4

M_

A_DQ4

6

A_DQ7

M_

14

A_DQ6

M_

16

A_DQ12

M_

23

A_DQ8

M_

25

M_

A_DQ10

35

A_DQ14

M_

37

M_

A_DQ13

20

A_DQ9

M_

22

M_

A_DQ15

36

A_DQ11

M_

38

M_

A_DQ21

43

M_

A_DQ17

45

M_

A_DQ19

55

M_

A_DQ18

57

A_DQ20

M_

44

M_

A_DQ16

46

A_DQ22

M_

56

M_

A_DQ23

58

A_DQ29

M_

61

M_

A_DQ28

63

A_DQ31

M_

73

M_

A_DQ30

75

A_DQ25

M_

62

A_DQ24

M_

64

A_DQ27

M_

74

M_

A_DQ26

76

M_

A_DQ36

123

A_DQ32

M_

125

M_

A_DQ38

135

A_DQ35

M_

137

M_

A_DQ33

124

A_DQ37

M_

126

M_

A_DQ34

134

M_

A_DQ39

136

M_

A_DQ40

141

A_DQ41

M_

143

A_DQ42

M_

151

M_

A_DQ46

153

A_DQ44

M_

140

M_

A_DQ45

142

A_DQ43

M_

152

M_

A_DQ47

154

A_DQ49

M_

157

A_DQ53

M_

159

M_

A_DQ55

173

M_

A_DQ51

175

M_

A_DQ52

158

A_DQ48

M_

160

M_

A_DQ50

174

A_DQ54

M_

176

M_

A_DQ56

179

A_DQ61

M_

181

M_

A_DQ58

189

A_DQ59

M_

191

M_

A_DQ57

180

A_DQ60

M_

182

A_DQ62

M_

192

A_DQ63

M_

194
50

69
83
120
163

201
202

196
193
190
187
184
183
178
177
172
171
168
165
162
161
156
155
150
149
145
144
139
138
133

M

_A_DQ[0..63] 5

VCC3

_B : 10

SA

M

_A_CS#2 5,9
_A_CS#3 5,9

M

.8VSUS

1

R

R
R3

R3

VCC3

118

CN2

CN2

0

DQ
DQ

VDD8

VDD7

VDD9

VDD1

VDD11

DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

NC1

NC2

NC3

NC4
TEST

NC/

uidePin

G

SO-DIMM

SO-DIMM

G

uidePin

VSS5
VSS5
VSS5
VSS5
VSS5
VSS5
VSS5
VSS4
VSS4
VSS47
VSS4
VSS4
VSS4
VSS43
VSS42
VSS4
VSS4
VSS3
VSS38
VSS37

3

1

0

9

8

6

VSS2777VSS2

78

VSS2

121

VSS2

122

VSS3

VSS3
VSS3
VSS3

VSS3

VSS32

VSS3

132

128

127

DDRII_SODIMM_H_11

DDRII_SODIMM_H_11

2

1

1

M_

B_DQ4

5

0
1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

6

5

4

3

2

1

0

9

8

6

5

4

1

0

9

6

5

4

B_DQ1

M_

7

B_DQ2

M_

17

B_DQ3

M_

19

M_

B_DQ5

4

B_DQ0

M_

6

M_

B_DQ6

14

B_DQ7

M_

16

B_DQ8

M_

23

B_DQ9

M_

25

B_DQ10

M_

35

M_

B_DQ15

37

B_DQ12

M_

20

M_

B_DQ13

22

B_DQ14

M_

36

M_

B_DQ11

38

B_DQ20

M_

43

M_

B_DQ16

45

M_

B_DQ19

55

M_

B_DQ23

57

M_

B_DQ21

44

B_DQ17

M_

46

M_

B_DQ18

56

B_DQ22

M_

58

M_

B_DQ29

61

B_DQ28

M_

63

M_

B_DQ26

73

B_DQ27

M_

75

M_

B_DQ24

62

B_DQ25

M_

64

B_DQ30

M_

74

B_DQ31

M_

76

M_

B_DQ33

123

M_

B_DQ36

125

B_DQ39

M_

135

M_

B_DQ35

137

B_DQ32

M_

124

M_

B_DQ37

126

B_DQ34

M_

134

M_

B_DQ38

136

M_

B_DQ40

141

M_

B_DQ41

143

B_DQ46

M_

151

B_DQ43

M_

153

M_

B_DQ44

140

B_DQ45

M_

142

M_

B_DQ47

152

B_DQ42

M_

154

M_

B_DQ53

157

B_DQ49

M_

159

B_DQ55

M_

173

M_

B_DQ54

175

M_

B_DQ48

158

M_

B_DQ52

160

B_DQ50

M_

174

M_

B_DQ51

176

B_DQ60

M_

179

M_

B_DQ57

181

B_DQ62

M_

189

M_

B_DQ59

191

B_DQ61

M_

180

M_

B_DQ56

182

B_DQ63

M_

192

B_DQ58

M_

194
50

69
83
120
163

201
202

196
193
190
187
184
183
178
177
172
171
168
165
162
161
156
155
150
149
145
144
139
138
133

Si

Si

Si

Date: Sheet

Date: Sheet

Date: Sheet

M

_B_DQ[0..63] 5

.8VSUS

1

*

10U_0805C415*10U_0805C415

*

10U_0805C371*10U_0805C371

_0805C321

_0805C321

10U

10U

_0805C373

_0805C373

10U

10U

0.

1UC4160.1UC416

0.

1UC3760.1UC376
1UC3770.1UC377

0.

0.

1UC4170.1UC417
1UC3780.1UC378

0.
1UC4210.1UC421

0.
1UC4230.1UC423

0.
1UC4180.1UC418

0.
1UC3800.1UC380

0.
1UC4190.1UC419

0.

0.

1UC3740.1UC374

0.

1UC3750.1UC375

0.

1UC3790.1UC379

0.

1UC3810.1UC381

0.

1UC3820.1UC382
1UC3270.1UC327

0.
1UC3280.1UC328

0.

0.

1UC3220.1UC322
1UC3230.1UC323

0.

0.

1UC3250.1UC325

1.

8VSUS

*0

.1UC422*0.1UC422

*0

.1UC420*0.1UC420
.1UC324*0.1UC324

M_

B_CS#2 5,9

M_

B_CS#3 5,9

*0

.1UC326*0.1UC326

*0

For EMI

DDR_

ze Do cument Number Rev

ze Do cument Number Rev

ze Do cument Number Rev

DDRII S

DDRII S

DDRII S

ODIMM x2

ODIMM x2

ODIMM x2

1

VREF

.8VSUS

R256

R261*0R261
*0

M

VREF_DIM

C352

C352
*1

*1

U

U

Q

Q

Q

PROJECT :

PROJECT :

PROJECT :

R256
1K/F

1K/F

0.9V

R

R

274

274

1K/F

1K/F

uanta Computer Inc.

uanta Computer Inc.

uanta Computer Inc.

ZN1

ZN1

ZN1

84

84

84

1

of

1Friday, May 08, 2009

of

1Friday, May 08, 2009

of

1Friday, May 08, 2009

1A

1A

1A

5

4

3

2

1

9

SM

DDR_VTERM

288 47_4

288 47_4

R

M

D D

0.9V

1.

DDR_VTERM

SM

_0805C372

_0805C372

10U

10U

10U_0805C414*10U_0805C414

*

1UC3990.1UC399

0.

0.

1UC3980.1UC398
1UC3970.1UC397

0.
1UC3890.1UC389

C C

0.
1UC3860.1UC386

0.
1UC3960.1UC396

0.

0.

1UC3850.1UC385
1UC3460.1UC346

0.

0.

1UC3620.1UC362
.1UC390*0.1UC390

*0
*0

.1UC401*0.1UC401
1UC4000.1UC400

0.

0.

1UC3910.1UC391

0.

1UC3880.1UC388

0.

1UC4120.1UC412

0.

1UC3510.1UC351
.1UC413*0.1UC413

*0

0.

1UC3870.1UC387
1UC3630.1UC363

0.

0.

1UC3640.1UC364

*0

.1UC365*0.1UC365

0.

1UC3660.1UC366
1UC3470.1UC347

0.
1UC3480.1UC348

0.

*0

.1UC349*0.1UC349
1UC3500.1UC350

0.

8VSUS

0.9V

DDR_VTERM

SM

1UC4040.1UC404

0.

0.

1UC4030.1UC403
1UC3320.1UC332

0.
1UC3370.1UC337

0.
1UC4100.1UC410

0.
1UC4050.1UC405

0.

0.

1UC4060.1UC406
1UC4070.1UC407

0.

0.

1UC4080.1UC408
1UC4090.1UC409

0.

0.

1UC3310.1UC331
1UC3380.1UC338

0.

0.

1UC3330.1UC333

0.

1UC3340.1UC334

0.

1UC3350.1UC335

0.

1UC3360.1UC336

_CKE05,8

M

_CKE15,8

M

_CKE25,8
_CKE35,8

M

ODT05,8

M_
M_

ODT15,8
ODT25,8

M_
M_

ODT35,8

_A_BS#05,8

M

_A_BS#15,8

M

_A_BS#25,8

M
M_

A_WE#5,8

M

_A_CAS#5,8
_A_RAS#5,8

M

_B_BS#05,8

M
M

_B_BS#15,8
_B_BS#25,8

M
M_

B_WE#5,8

M

_B_CAS#5,8
_B_RAS#5,8

M
M_

A_CS#05,8
A_CS#15,8

M_
M_

A_CS#25,8
A_CS#35,8

M_

B_CS#05,8

M_

B_CS#15,8

M_
M_

B_CS#25,8

M_

B_CS#35,8

M

_A_A[0..15]5,8

_A_A13

M
M

_A_A10
_A_A0

M
M

_A_A2
_A_A4

M
M

_A_A6
_A_A7

M

_A_A11

M
M

_A_A12

M

_A_A9

M

_A_A3
_A_A1

M
M

_A_A8
_A_A5

M
M

_A_A14
_A_A15

M

R
R

R

265 47_4

265 47_4
317 47_4

317 47_4

R

R
R

R

310 47_4

310 47_4

R

R

268 47_4

268 47_4

R

R

296 47_4

296 47_4
304 47_4

304 47_4

R

R

325 47_4

325 47_4

R

R
R

R

293 47_4

293 47_4
266 47_4

266 47_4

R

R
R

R

290 47_4

290 47_4

R

R

292 47_4

292 47_4
295 47_4

295 47_4

R

R

267 47_4

267 47_4

R

R
R

R

322 47_4

322 47_4

R

R

302 47_4

302 47_4
319 47_4

319 47_4

R

R

321 47_4

321 47_4

R

R
R

R

323 47_4

323 47_4
303 47_4

303 47_4

R

R

269 47_4

269 47_4

R

R
R

R

294 47_4

294 47_4
289 47_4

289 47_4

R

R

271 47_4

271 47_4

R

R

305 47_4

305 47_4

R

R
R

R

324 47_4

324 47_4
318 47_4

318 47_4

R

R
R

R

307 47_4

307 47_4

R

R

270 47_4

270 47_4

R

R

291 47_4

291 47_4

R

R

P16 0404-47X2

P16 0404-47X2

1 2
3 4

P15 0404-47X2

P15 0404-47X2

R

R

1 2
3 4

P14 0404-47X2

P14 0404-47X2

R

R

1 2
3 4

R

R

P17 0404-47X2

P17 0404-47X2

1 2
3 4

P19 0404-47X2

P19 0404-47X2

R

R

1 2
3 4

R

R

P18 0404-47X2

P18 0404-47X2

1 2
3 4

R

R

P13 0404-47X2

P13 0404-47X2

1 2
3 4

M

B B

A A

5

4

_B_A[0..15]5,8

3

_B_A2

M

_B_A0

M

_B_A6

M
M

_B_A4
_B_A11

M
M

_B_A7
_B_A3

M
M

_B_A1
_B_A8

M
M

_B_A5

M

_B_A12

M

_B_A9

M

_B_A10
_B_A13

M
M

_B_A15
_B_A14

M

R

R

P23 0404-47X2

P23 0404-47X2

1 2
3 4

R

R

P22 0404-47X2

P22 0404-47X2

1 2
3 4

P21 0404-47X2

P21 0404-47X2

R

R

1 2
3 4

P26 0404-47X2

P26 0404-47X2

R

R

1 2
3 4

P25 0404-47X2

P25 0404-47X2

R

R

1 2
3 4

P24 0404-47X2

P24 0404-47X2

R

R

1 2
3 4

320 47_4

320 47_4

R

R

306 47_4

306 47_4

R

R

R

R

P20 0404-47X2

P20 0404-47X2

1 2
3 4

2

uanta Computer Inc.

uanta Computer Inc.

uanta Computer Inc.

Q

Q

Q

PROJECT :

PROJECT :

ze Do cument Number Rev

ze Do cument Number Rev

ze Do cument Number Rev

Si

Si

Si

DDRII TE

DDRII TE

DDRII TE

Date: Sheet

Date: Sheet

Date: Sheet

PROJECT :

RMINATION

RMINATION

RMINATION

ZN1

ZN1

ZN1

94

94

94

1

of

of

of

1A

1A

1A

1Friday, May 08, 2009

1Friday, May 08, 2009

1Friday, May 08, 2009

5

_CADOUT0_P4

HT

_CADOUT0_N4

HT

_CADOUT1_P4

HT

_CADOUT1_N4

HT

_CADOUT2_P4

HT
HT

_CADOUT2_N4

HT

_CADOUT3_P4

HT

_CADOUT3_N4

HT

_CADOUT4_P4

HT

_CADOUT4_N4

HT

_CADOUT5_P4

HT

_CADOUT5_N4
_CADOUT6_P4

R151

R151

HT
HT

_CADOUT6_N4
_CADOUT7_P4

HT

_CADOUT7_N4

HT

_CADOUT8_P4

HT

_CADOUT8_N4

HT

_CADOUT9_P4

HT
HT

_CADOUT9_N4

HT

_CADOUT10_P4

HT

_CADOUT10_N4

HT

_CADOUT11_P4

HT

_CADOUT11_N4

HT

_CADOUT12_P4

HT

_CADOUT12_N4

HT

_CADOUT13_P4

HT

_CADOUT13_N4

HT

_CADOUT14_P4
_CADOUT14_N4

HT

_CADOUT15_P4

HT

_CADOUT15_N4

HT

_CLKOUT0_P4

HT
HT

_CLKOUT0_N4

HT

_CLKOUT1_P4

HT

_CLKOUT1_N4

HT

_CTLOUT0_P4

HT

_CTLOUT0_N4

HT

_CTLOUT1_P4

HT

_CTLOUT1_N4

300/F_4

300/F_4

D D

C C

H

T_RXCALP

H

T_RXCALN

4

Y2

Y2
V22
V23
V25
V24
U24
U25

T25

T24
P22
P23
P25
P24
N24
N25

AC24
AC25
AB25
AB24
AA24
AA25

Y2

Y2

W2
W2

V21
V20
U20
U21
U19
U18

T22

T23

AB23
AA22

M22
M23
R21
R20

C23
A24

5
4

2
3
1
0

U10A

U10A

HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N

HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N

HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N

HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N

HT_RXCALP
HT_RXCALN

RS780

RS780

PART

HT_TXCAD0N

HT_TXCAD1P

HT_TXCAD1N

HT_TXCAD2P

HT_TXCAD2N

HT_TXCAD3P

HT_TXCAD3N

HT_TXCAD4P

HT_TXCAD4N

HT_TXCAD5P

HT_TXCAD5N

/F

/F

HT_TXCAD6P

HT_TXCAD6N

HT_TXCAD7P

HT_TXCAD7N

HT_TXCAD8P

HT_TXCAD8N

HT_TXCAD9P

HT_TXCAD9N

HT_TXCAD10P

HT_TXCAD10N

HT_TXCAD11P

HT_TXCAD11N

HT_TXCAD12P

HT_TXCAD12N

HT_TXCAD13P

HT_TXCAD13N

HT_TXCAD14P

HT_TXCAD14N

HT_TXCAD15P

HT_TXCAD15N

HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N

HYPER TRANSPORT CPU I

HYPER TRANSPORT CPU I

HT_TXCTL0P

HT_TXCTL0N

HT_TXCTL1P

HT_TXCTL1N

HT_TXCALP
HT_TXCALN

s block is for UMA RS780 only

Thi

HT_TXCAD0P

1 OF 6

1 OF 6

PART

D24
D25
E24
E25
F24
F25
F23
F22
H23
H22
J25
J24
K24
K25
K23
K22

F21
G21
G20
H21
J20
J21
J18
K17
L19
J19
M19
L18
M21
P21
P18
M18

H24
H25
L21
L20

M24
M25
P19
R18

B24
B25

HT
HT

3

_TXCALP
_TXCALN

_CADIN0_P 4

HT

_CADIN0_N 4

HT

_CADIN1_P 4

HT

_CADIN1_N 4

HT

_CADIN2_P 4

HT

_CADIN2_N 4

HT
HT

_CADIN3_P 4

HT

_CADIN3_N 4

HT

_CADIN4_P 4

HT

_CADIN4_N 4

HT

_CADIN5_P 4

HT

_CADIN5_N 4

HT

_CADIN6_P 4

HT

_CADIN6_N 4

HT

_CADIN7_P 4
_CADIN7_N 4

HT

_CADIN8_P 4

HT

_CADIN8_N 4

HT

_CADIN9_P 4

HT

_CADIN9_N 4

HT
HT

_CADIN10_P 4

HT

_CADIN10_N 4

HT

_CADIN11_P 4

HT

_CADIN11_N 4

HT

_CADIN12_P 4

HT

_CADIN12_N 4

HT

_CADIN13_P 4

HT

_CADIN13_N 4

HT

_CADIN14_P 4

HT

_CADIN14_N 4
_CADIN15_P 4

HT

_CADIN15_N 4

HT

_CLKIN0_P 4

HT

_CLKIN0_N 4

HT
HT

_CLKIN1_P 4

HT

_CLKIN1_N 4

HT

_CTLIN0_P 4

HT

_CTLIN0_N 4

HT

_CTLIN1_P 4

HT

_CTLIN1_N 4

R149

R149

300/F_4

300/F_4

2

1

10

U10D

U10D

AB12

MEM_A0(

AE16

MEM_A1(

V11

MEM_A2(

AE15

MEM_A3(

AA12

MEM_A4(

AB16

MEM_A5(

AB14

MEM_A6(

AD14

MEM_A7(

B B

A A

5

AD13

MEM_A8(

AD15

MEM_A9(NC)

AC16

MEM_A10(

AE13

MEM_A11(

AC14

MEM_A12(

Y14

MEM_A13(

AD16

MEM_BA0(

AE17

MEM_BA1(

AD17

MEM_BA2(

W12

MEM_RASb(

Y12

MEM_CASb(

AD18

MEM_W

AB13

MEM_CSb(

AB18

MEM_CKE(

V14

MEM_ODT(

V15

MEM_CKP(

W14

MEM_CKN(

AE12

MEM_COMPP(

AD12

MEM_COMPN(

RS780

RS780

4

P

P

AR 4 OF 6

AR 4 OF 6

NC)

MEM_DQ0/

NC)

MEM_DQ1/
NC)
NC)
NC)
NC)
NC)
NC)
NC)

NC)
NC)
NC)
NC)

NC)
NC)
NC)

Eb(NC)

NC)
NC)
NC)

NC)
NC)

NC)
NC)

MEM_DQ2/
MEM_DQ3/

MEM_DQ5/
MEM_DQ6/
MEM_DQ7/
MEM_DQ8/

MEM_DQ9/DVO_D5(NC)
MEM_DQ10/
MEM_DQ11/

MEM_DQ13/

MEM_DQ14/
MEM_DQ15/

MEM_DQS0P/

MEM_DQS0N/

MEM_DM1/

SBD_MEM/DVO_I/F

SBD_MEM/DVO_I/F

NC)
NC)

DVO_VSYNC(NC)
DVO_HSYNC(NC)

DVO_DE(NC)
DVO_D0(NC)

MEM_DQ4(

DVO_D1(NC)
DVO_D2(NC)
DVO_D4(NC)
DVO_D3(NC)

DVO_D6(NC)
DVO_D7(NC)

MEM_DQ12(

DVO_D9(NC)
DVO_D10(NC)
DVO_D11(NC)

DVO_IDCKP(NC)

DVO_IDCKN(NC)
MEM_DQS1P(
MEM_DQS1N(

MEM_DM0(

DVO_D8(NC)

OPLLVDD18(NC)

I

OPLLVDD(NC)

I

I

OPLLVSS(NC)

MEM_VREF(

NC)

NC)

NC)
NC)

NC)

NC)

AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21

Y17
W18
AD20
AE21

W17
AE19

AE23
AE24

AD23
AE18

+1.8_I

OPLLVDD18_NB

+1.1V_IOPLLVDD

3

R133

R133

*0_6

*0_6

R129 *0_6R129 *0_6

VCC1.8

1.1V_NB

Qu

Qu

Qu

anta Computer Inc.

anta Computer Inc.

anta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

RS7

RS7

RS7

Date: Sheet

Date: Sheet

2

Date: Sheet

PROJECT :

80M HT LINK I/F 1/4

80M HT LINK I/F 1/4

80M HT LINK I/F 1/4

ZN1

ZN1

ZN1

1A

1A

1A

of

of

of

41Friday, May 08, 2009

41Friday, May 08, 2009

41Friday, May 08, 2009

10

10

10

1

5

PC

IE_RXP020
IE_RXN020

PC

IE_RXP120

PC
PC

IE_RXN120

PC

IE_RXP220

PC

IE_RXN220
IE_RXP320

PC

IE_RXN320

PC
PC

D D

PC

PCIE_RXP[15..0]20
PC

IE_RXN[15..0]20

IE_TXP[15..0]20

PC
PC

IE_TXN[15..0]20

C C

B B

IE_RXP[15..0]
IE_RXN[15..0]

PC
PC

IE_TXP[15..0]
IE_TXN[15..0]

PC

IE_RXP420

PC

IE_RXN420

PC

IE_RXP520
IE_RXN520

PC
PCIE_RXP620
PC

IE_RXN620

PC

IE_RXP720

PC

IE_RXN720
IE_RXP820

PC
PC

IE_RXN820

PC

IE_RXP920

PC

IE_RXN920
IE_RXP1020

PC
PCIE_RXN1020
PC

IE_RXP1120

PC

IE_RXN1120

PC

IE_RXP1220

PC

IE_RXN1220

PC

IE_RXP1320
IE_RXN1320

PC
PC

IE_RXP1420

PC

IE_RXN1420
IE_RXP1520

PC
PC

IE_RXN1520

GP

P_RX0P_WLAN30

GP

P_RX0N_WLAN30

GP

P_RX2P_LAN24

GP

P_RX2N_LAN24

G

PP_RX4P_CARD27

G

PP_RX4N_CARD27

PC

IE_SB_NB_RX0P14

PC

IE_SB_NB_RX0N14
IE_SB_NB_RX1P14

PC

IE_SB_NB_RX1N14

PC

IE_SB_NB_RX2P14

PC

PC

IE_SB_NB_RX2N14

PC

IE_SB_NB_RX3P14
IE_SB_NB_RX3N14

PC

4

U

U

10B

10B

D4

GFX

_RX0P

C4

GFX

_RX0N

A3

GFX

_RX1P

B3

_RX1N

GFX

C2

_RX2P

GFX

C1

GFX

_RX2N

E5

GFX

_RX3P

F5

GFX

_RX3N

G5

_RX4P

GFX

G6

_RX4N

GFX

H5

GFX

_RX5P

H6

GFX

_RX5N

J6

GFX

_RX6P

J5

_RX6N

GFX

J7

_RX7P

GFX

J8

GFX

_RX7N

L5

GFX

_RX8P

L6

GFX

_RX8N

M8

_RX9P

GFX

L8

_RX9N

GFX

P7

GFX

_RX10P

M7

GFX

_RX10N

P5

GFX

_RX11P

M5

_RX11N

GFX

R8

_RX12P

GFX

P8

GFX

_RX12N

R6

GFX

_RX13P

R5

GFX

_RX13N

P4

_RX14P

GFX

P3

GFX_RX14N

T4

GFX

_RX15P

T3

GFX

_RX15N

AE3

PP_RX0P

G

AD4

G

PP_RX0N

0

T70T7

21

T121T1

04

T104T1

17

T117T1

AE2
AD3
AD1
AD2

AA8

AA7

AA5

AA6

V5

W6

U5
U6
U8
U7

Y8
Y7

W5

Y5

G

PP_RX1P

G

PP_RX1N

G

PP_RX2P
GPP_RX2N
G

PP_RX3P
G

PP_RX3N
G

PP_RX4P
G

PP_RX4N
G

PP_RX5P

PP_RX5N

G
SB_

RX0P
RX0N

SB_
SB_

RX1P

SB_

RX1N

SB_

RX2P

SB_

RX2N
RX3P

SB_

RX3N

SB_

RS780

RS780

2 OF 6

2 OF 6

PART

PART

PCIE I/F GFX

PCIE I/F GFX

GPP

GPP

PCIE I/F

PCIE I/F

PCIE I/F SB

PCIE I/F SB

PC

E_CALRP(PCE_BCALRP)

E_CALRN(PCE_BCALRN)

PC

GFX
GFX
GFX
GFX
GFX
GFX
GFX
GFX
GFX
GFX_TX14N
GFX
GFX

GFX

_TX0P

GFX

_TX0N

GFX

_TX1P
_TX1N

GFX

_TX2P

GFX

GFX

_TX2N

GFX

_TX3P

GFX

_TX3N
_TX4P

GFX

_TX4N

GFX

GFX

_TX5P

GFX

_TX5N

GFX

_TX6P
_TX6N

GFX

_TX7P

GFX

GFX

_TX7N

GFX

_TX8P

GFX

_TX8N
_TX9P

GFX

_TX9N

GFX

_TX10P

_TX10N

_TX11P

_TX11N

_TX12P

_TX12N

_TX13P

_TX13N

_TX14P
_TX15P

_TX15N

PP_TX0P

G

G

PP_TX0N

G

PP_TX1P

G

PP_TX1N

G

PP_TX2P

GPP_TX2N

G

PP_TX3P

G

PP_TX3N

G

PP_TX4P

G

PP_TX4N

G

PP_TX5P
PP_TX5N

G

SB_

TX0P
TX0N

SB_
SB_

TX1P

SB_

TX1N

SB_

TX2P

SB_

TX2N
TX3P

SB_

TX3N

SB_

3

G

A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2

AC1
AC2
AB4
AB3
AA2
AA1
Y1
Y2
Y4
Y3
V1
V2

AD7
AE7
AE6
AD6
AB6
AC6
AD5
AE5

AC8
AB8

FX_TXP0

GFX

_TXN0

G

FX_TXP1

_TXN1

GFX

FX_TXP2

G
GFX

_TXN2

G

FX_TXP3

GFX

_TXN3

FX_TXP4

G

_TXN4

GFX
G

FX_TXP5

GFX

_TXN5

G

FX_TXP6

_TXN6

GFX

FX_TXP7

G
GFX

_TXN7

G

FX_TXP8

GFX

_TXN8

FX_TXP9

G

_TXN9

GFX
G

FX_TXP10

GFX

_TXN10

G

FX_TXP11

_TXN11

GFX

FX_TXP12

G
GFX

_TXN12

G

FX_TXP13

GFX

_TXN13

FX_TXP14

G

_TXN14

GFX
G

FX_TXP15

GFX

_TXN15

IE_TXP0_C

PC

IE_TXN0_C

PC

PC

IE_TXP2_C
IE_TXN2_C

PC

PC

IE_TXP4_C

PC

IE_TXN4_C

A
A_
A
A_
A
A_
A
A_TX3N_C

NB
NB

_TX0P_CA_TX0P_C

TX0N_CA_TX0N_C

_TX1P_CA_TX1P_C

TX1N_CA_TX1N_C

_TX2P_C

TX2N_C

_TX3P_C

_PCIECALRP
_PCIECALRN

C

C

243 0.1U/10V/4

243 0.1U/10V/4
245 0.1U/10V/4

245 0.1U/10V/4

C

C

238 0.1U/10V/4

238 0.1U/10V/4

C

C

240 0.1U/10V/4

240 0.1U/10V/4

C

C
C

C

239 0.1U/10V/4

239 0.1U/10V/4

C

C

241 0.1U/10V/4

241 0.1U/10V/4
234 0.1U/10V/4

234 0.1U/10V/4

C

C

236 0.1U/10V/4

236 0.1U/10V/4

C

C
C237 0.1U/10V/4C237 0.1U/10V/4
C

C

235 0.1U/10V/4

235 0.1U/10V/4

C

C

232 0.1U/10V/4

232 0.1U/10V/4
229 0.1U/10V/4

229 0.1U/10V/4

C

C

233 0.1U/10V/4

233 0.1U/10V/4

C

C
C

C

231 0.1U/10V/4

231 0.1U/10V/4

C

C

226 0.1U/10V/4

226 0.1U/10V/4

C

C

228 0.1U/10V/4

228 0.1U/10V/4
225 0.1U/10V/4

225 0.1U/10V/4

C

C
C227 0.1U/10V/4C227 0.1U/10V/4
C

C

218 0.1U/10V/4

218 0.1U/10V/4

C

C

222 0.1U/10V/4

222 0.1U/10V/4

C

C

213 0.1U/10V/4

213 0.1U/10V/4
216 0.1U/10V/4

216 0.1U/10V/4

C

C
C

C

221 0.1U/10V/4

221 0.1U/10V/4
224 0.1U/10V/4

224 0.1U/10V/4

C

C
C

C

217 0.1U/10V/4

217 0.1U/10V/4

C

C

215 0.1U/10V/4

215 0.1U/10V/4
C209 0.1U/10V/4C209 0.1U/10V/4
C

C

206 0.1U/10V/4

206 0.1U/10V/4
C

C

208 0.1U/10V/4

208 0.1U/10V/4
C

C

211 0.1U/10V/4

211 0.1U/10V/4
C

C

199 0.1U/10V/4

199 0.1U/10V/4
C

C

202 0.1U/10V/4

202 0.1U/10V/4

C

C

496 0.1u/10V_4

496 0.1u/10V_4

C

C

502 0.1u/10V_4

502 0.1u/10V_4

120T120

T

116T116

T

C

C

193 0.1u/10V_4

193 0.1u/10V_4

C

C

195 0.1u/10V_4

195 0.1u/10V_4

111T111

T

112T112

T

201 0.1u/10V_4

201 0.1u/10V_4

C

C
C

C

204 0.1u/10V_4

204 0.1u/10V_4

C

C

175 0.1u/10V_4

175 0.1u/10V_4

C

C

174 0.1u/10V_4

174 0.1u/10V_4

C

C

178 0.1u/10V_4

178 0.1u/10V_4
176 0.1u/10V_4

176 0.1u/10V_4

C

C

180 0.1u/10V_4

180 0.1u/10V_4

C

C
C

C

181 0.1u/10V_4

181 0.1u/10V_4

C

C

185 0.1u/10V_4

185 0.1u/10V_4

C

C

183 0.1u/10V_4

183 0.1u/10V_4

353 1.27K/F_4

353 1.27K/F_4

R

R
R

R

349 2K/F_4

349 2K/F_4

GP
GP

GP
GP

G
G

PC

IE_NB_SB_TX0P 14
IE_NB_SB_TX0N 14

PC

IE_NB_SB_TX1P 14

PC

IE_NB_SB_TX1N 14

PC
PC

IE_NB_SB_TX2P 14

PC

IE_NB_SB_TX2N 14
IE_NB_SB_TX3P 14

PC

IE_NB_SB_TX3N 14

PC

2

IE_TXP0 20

PC

IE_TXN0 20

PC
PC

IE_TXP1 20

PC

IE_TXN1 20

PC

IE_TXP2 20
IE_TXN2 20

PC

IE_TXP3 20

PC
PC

IE_TXN3 20

PC

IE_TXP4 20

PC

IE_TXN4 20
IE_TXP5 20

PC
PCIE_TXN5 20
PC

IE_TXP6 20

PC

IE_TXN6 20

PC

IE_TXP7 20
IE_TXN7 20

PC
PC

IE_TXP8 20

PC

IE_TXN8 20

PC

IE_TXP9 20
IE_TXN9 20

PC
PCIE_TXP10 20
PC

IE_TXN10 20

PC

IE_TXP11 20

PC

IE_TXN11 20

PC

IE_TXP12 20

PC

IE_TXN12 20
IE_TXP13 20

PC
PC

IE_TXN13 20

PC

IE_TXP14 20
IE_TXN14 20

PC
PC

IE_TXP15 20

PC

IE_TXN15 20

P_TX0P_WLAN 30
P_TX0N_WLAN 30

P_TX2P_LAN 24
P_TX2N_LAN 24

PP_TX4P_CARD 27
PP_TX4N_CARD 27

1V_NB

1.

1

11

TO MXM MODULE

TO WLAN

TO LAN

TO CARD READER

To A-Link

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

S

S

Size Document Number Rev

ize Document Number Rev

ize Document Number Rev

RS780M-

RS780M-

RS780M-

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

PROJECT :

PCIE I/F 2/4

PCIE I/F 2/4

PCIE I/F 2/4

ZN1

ZN1

ZN1

1A

1A

1A

41Friday, May 08, 2009

41Friday, May 08, 2009

41Friday, May 08, 2009

of

11

of

11

of

11

1

5

V

Thermal

R128

U7

U7

VC

C

DX

P

DX

N

-OV

T

781

781

G

G

MSOP8-4_9-65

MSOP8-4_9-65

*0_4

*0_4

0_4

0_4

CRT

R128

C162

C162

SMBUS Add. : 98h

SMBUS Add. : 98h

_RST#_IN

NB

V

CC3

_RED

_GRN

CRT
CRT

_BLU

SM

SM

DATA

Senser

C165

C165

0.1U_4

0.1U_4

1

2200P_0603

2200P_0603

C171

C171

D D

NB

_SHDN#16

R

X780

CP

U_LDT_RST#6,14

RS780

_PLTRST#14

NB

+NB

C C

_CORE_ON

_THRMDA

R_NB

_THRMDC

R_NB

R337

R337

R336

R336

orth Bridge RESET

N

R162

R162

R164

R164

2
3
4

*10K/F_4

*10K/F_4

2.2K_4

2.2K_4

CC3

0R_6

0R_6

*0.

*0.

1U

1U

8

CLK

7
6

-A

LT

5

GN

D

CC3

V

/F_4

/F_4

1K

1K

R449

R449

4

SMBUS SLAVE ADDRESS

G

781

98 (NB)

G

781-1

9A (CPU)

BCLK 6,32

M
M

BDATA 6,32
N

B_TALERT# 15

Change BOM value

NB

_PWRGD_IN18

LLOW_LDTSTOP14

A

NB

HT_REFCLKP3

NB

HT_REFCLKN3

EXT

_NB_OSC3

1.

1V_NB

R330

R330

4.

4.

NB

GFX_CLKP3
GFX_CLKN3

NB

INK_CLKP3

SBL

INK_CLKN3

SBL

7K_4

7K_4

RS7

3

U10C

+3V

_AVDD_NB

+1.8V

_AVDDDI_NB

+

1.8V_AVDDQ_NB

I

NT_TV_C/R

09

T109T1

CRT

_RED21
_GRN21

CRT
CRT

_BLU21

CRT
C

RT_VSYNC21
CRT
CRT

IV@715/F_6

IV@715/F_6

R346

R346

R331

R331

RS7

80

80

4.

4.

7K_4

7K_4

DS_DAT19,20

LV

DS_CLK19,20

LV

_HSYNC21
_DDCDAT21

_DDCCLK21

T110T1
T113T1

+NB

R332

R332
R333

R333

10
13

T73T7
T74T7

_CORE_ON

T118T1
T114T1

R343

R343
R344

R344
R345

R345

DA

1.1V_PLLVDD

+

1.8V_PLLVDD18

+

+1.

1.8V_VDDA18PCIEPLL

+

NB
NB
NB
NB

NB
NB

0_4

0_4
0_4

0_4

NB
NB

SBL
SBL

3
4

T72T7

2

18
14

0_4

0_4
0_4

0_4
0_4

0_4

C_RSET_NBDAC_RSET_NB

8V_VDDA18HTPLL

_RST#_IN
_PWRGD_IN
_LDT_STOP#
_ALLOW_LDTSTOP

HT_REFCLKP
HT_REFCLKN

NB

_REFCLK_PNB_REFCLK_P
_REFCLK_NNB_REFCLK_N

NB

GFX_CLKP
GFX_CLKN

N

BGPP_CLKP

N

BGPP_CLKN

INK_CLKP
INK_CLKN

RS

740_DFT_GPIO1

780_AUX_CAL

RS

U10C

F12

VDD1(NC)

A

E12

VDD2(NC)

A

F14

VDDDI(NC)

A

G15

I(NC)

AVSSD

H15

VDDQ(NC)

A

H14

(NC)

AVSSQ

E17

C

_Pr(DFT_GPIO5)

F17

DFT_GPIO2)

Y(

F15

OMP_Pb(DFT_GPIO4)

C

G18

RE

D(DFT_GPIO0)

G17

RE

Db(NC)

E18

EEN(DFT_GPIO1)

GR

F18

G

REENb(NC)

E19

BL

UE(DFT_GPIO3)

F19

B

LUEb(NC)

A11

DA

C_HSYNC(PWM_GPIO4)

B11

DA

C_VSYNC(PWM_GPIO6)

E8

D

AC_SDA(PCE_TCALRN)

F8

DA

C_SCL(PCE_RCALRN)

G14

DA

C_RSET(PWM_GPIO1)

A12

P

LLVDD(NC)

D14

P

LLVDD18(NC)

B12

PL

LVSS(NC)

H17

V

DDA18HTPLL

D7

VD

DA18PCIEPLL1

E7

VD

DA18PCIEPLL2

D8

SYSR

ESETb

A10

OWERGOOD

P

C10

DTSTOPb

L

C12

LLOW_LDTSTOP

A

C25

HT

_REFCLKP

C24

_REFCLKN

HT

E11

EFCLK_P/OSCIN(OSCIN)

R

F11

EFCLK_N(PWM_GPIO3)

R

T2

X_REFCLKP

GF

T1

X_REFCLKN

GF

U1

PP_REFCLKP

G

U2

PP_REFCLKN

G

V4

PPSB_REFCLKP(SB_REFCL KP)

G

V3

PPSB_REFCLKN(SB_REFCLKN)

G

A9

2C_DATA

I

B9

I

2C_CLK

B8

DDC_

DATA/AUX0N(NC)

A8

CLK/AUX0P(NC)

DDC_

B7

X1P(NC)

AU

A7

UX1N(NC)

A

B10

ST

RP_DATA

G11

R

SVD

C8

A

UX_CAL(NC)

RS

RS

780

780

I

I/O

I/O

PART 3 OF 6

PART 3 OF 6

T

XOUT_U1P(PCIE_RESET_GPIO3)

T

XOUT_U1N(PCIE_RESET_GPIO2)

/TVOUT

/TVOUT

T

XOUT_U3P(PCIE_RESET_GPIO5)

CRT

CRT

T

XCLK_UP(PCIE_RESET_GPIO4)

T

XCLK_UN(PCIE_RESET_GPIO1)

LVTM

LVTM

PM

PM

I

CLOCKs PLL PWR

CLOCKs PLL PWR

MIS.

MIS.

T
T
T
T
T

OUT_L2N(DBG_GPIO0)

TX

T

TX

OUT_L3N(DBG_GPIO2)

T

T

T
T

T

T

XCLK_LP(DBG_GPIO1)

T

XCLK_LN(DBG_GPIO 3)

VDS_DIGON(PCE_TCALRP)

L

VDS_BLON(PCE_RCALRP)

L

DS_ENA_BL(PWM_GPIO2)

LV

VCLKIN(PW M_GPIO5)

T

TH

ERMALDIODE_P

T

HERMALDIODE_N

XOUT_L0P(NC)

XOUT_L0N(NC)

XOUT_L1P(NC)

XOUT_L1N(NC)

XOUT_L2P(NC)
XOUT_L3P(NC)

XOUT_U0P(NC)
XOUT_U0N(NC)

XOUT_U2P(NC)
XOUT_U2N(NC)

XOUT_U3N(NC)

V

DDLTP18(NC)

VSSL

TP18(NC)

V

DDLT18_1(NC)

V

DDLT18_2(NC)

V

DDLT33_1(NC)

V

DDLT33_2(NC)

VSSL

T1(VSS)

VSSL

T2(VSS)

VSSL

T3(VSS)
T4(VSS)

VSSL

T5(VSS)

VSSL

T6(VSS)

VSSL
VSSL

T7(VSS)

T

MDS_HPD(NC)

HP

D(NC)

T

ESTMODE

2

A22
B22
A21
B21
B20
A20
A19
B19

B18
A18
A17
B17
D20
D21
D18
D19

B16
A16
D16
D17

A13
B13

A15
B15
A14
B14

C14
D15
C16
C18
C20
E20
C22

E9
F7
G12

D9
D10

D12
AE8

AD8
D13

8V_VDDLTP18_NB

+1.

1.8V_VDDLT_18_NB

+

TM

DS_HPD0

TM

DS_HPD1

SU

S_STAT#_NB

R_NB

_THRMDA

R_NB

_THRMDC

T

EST_EN

XLOUT0+ 19

T

XLOUT0- 19

T

XLOUT1+ 19

T

XLOUT1- 19

T

XLOUT2+ 19

T

XLOUT2- 19

T
T

XLOUT3+ 19

T

XLOUT3- 19
XUOUT0+ 19

T
T

XUOUT0- 19

T

XUOUT1+ 19

T

XUOUT1- 19
XUOUT2+ 19

T
T

XUOUT2- 19

T

XUOUT3+ 19

T

XUOUT3- 19

TX

LCLKOUT+ 19

T

XLCLKOUT- 19

T

XUCLKOUT+ 19

T

XUCLKOUT- 19

3V_VDLT33_NB

+

IGON 19

D

T

ON 19

BL

R334

R334

1.

1.

82K/F_4

82K/F_4

105T105

02

T102T1

06

T106T1

T68T6
T69T6

To LVDS panel

LVDS POWER

R329

R329

D48

D48

*1SS355

8
9

*1SS355

1

*0_4

*0_4

S_STAT# 15

SU

LTRST# 14,16,20,24,27,30

P

12

LM18PG201SN1D(200_1.4A)_6

LM18PG201SN1D(200_1.4A)_6

B

R197140/FR197140/

R205150/FR205150/

R202150/F R202150/F

F

F

B B

RS

780_AUX_CAL

C

RT_VSYNC

_HSYNC

CRT

A A

R166

R166

*3K_4

*3K_4

R160

R160

3K_4

3K_4

V

CC3

*3K_4

*3K_4

R161

R161

R159

R159

3K_4

3K_4

V

*3K_4

*3K_4

CC3

4

R158

R158

5

L48

L48

V

CC3

LM18PG201SN1D(200_1.4A)_6

LM18PG201SN1D(200_1.4A)_6

B

B

CC1.8

V

L25

L25

BLM18PG201SN1D(200_1.4A)_6

BLM18PG201SN1D(200_1.4A)_6

C230

C230

6.3V_8

6.3V_8

10u/

10u/

V

CC1.8

VDDA18PCIEPLL -PCIE PLL

L46

L46

LM18PG221SN1D(220_1.4A)_6

LM18PG221SN1D(220_1.4A)_6

B

B

VDDA18HTPLL -HT LINK PLL

L24

L24

BLM18PG201SN1D(200_1.4A)_6

BLM18PG201SN1D(200_1.4A)_6

+3V

C474

C474

2.

2.

2u/6.3V_6

2u/6.3V_6

20mils width

+

1.8V_VDDA18PCIEPLL

20mils width

+1.8V_VDDA18HTPLL

_AVDD_NB

C461

C461

.2u/6.3V_6

.2u/6.3V_6

2

2

+1.8V_PLLVDD18

C440

C440

2u/6.3V_6

2u/6.3V_6

2.

2.

C223

C223

2u/6.3V_6

2u/6.3V_6

2.

2.

U_LDT_STOP#6,14

CP

B

1.

1V_NB

CC1.8

V

BLM18PG201SN1D(200_1.4A)_6

BLM18PG201SN1D(200_1.4A)_6

L43

L43

3

R339

R339

L22

L22

VCC1.8

*short0603

*short0603

C466

C466

1u/10V_4

1u/10V_4

0.

0.

R169

R169
*300_4

*300_4

*BSS138_NL/SOT23

*BSS138_NL/SOT23

+1.8V

_AVDDDI_NB

+

1.8V_AVDDQ_NB

C433

C433
2

2

.2u/6.3V_6

.2u/6.3V_6

7

7

Q1

Q1

1

R167

R167

RS780

1.1V_PLLVDD

1.1V_PLLVDD

+

+

C219

C219

2u/6.3V_6

2u/6.3V_6

2.

2.

CC1.8

V

2

CC1.8

V

LM18PG201SN1D(200_1.4A)_6

LM18PG201SN1D(200_1.4A)_6

B

B

L21

L21

L20

L20

DDG_NB

+V

R165

R165

7K_4

7K_4

*4.

*4.

NB

3

0_4

0_4

_LDT_STOP#

2

C455

C455

.2u/6.3V_6

.2u/6.3V_6

2

2

B

B

LM21PG201SN1D(200_100M_2A)_8

LM21PG201SN1D(200_100M_2A)_8

C210

C210

4

4

.7u/6.3V_6

.7u/6.3V_6

8V_VDDLTP18_NB

+1.

8V_VDDLT_18_NB

+1.

C207

C207

0.

0.

1u/10V_4

1u/10V_4

R163

R163

0_6

VC

C3

CC3

V

LM21PG221SN1D(220_100M_2A)_8

LM21PG221SN1D(220_100M_2A)_8

*B

*B

Size Document Number Rev

ize Document Number Rev

ize Document Number Rev

S

S

Date: Sheet

Date: Sheet

Date: Sheet

0_6

L47

L47

80M-SYSTEM I/F 3/4

80M-SYSTEM I/F 3/4

80M-SYSTEM I/F 3/4

RS7

RS7

RS7

+V

DDG_NB

3V_VDLT33_NB

+

C444

C444

*

*

2.2u/6.3V_6

2.2u/6.3V_6

Q

Q

Q

uanta Computer Inc.

uanta Computer Inc.

uanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

ZN1

ZN1

ZN1

12

12

12

1

of

of

of

1A

1A

1A

41Friday, May 08, 2009

41Friday, May 08, 2009

41Friday, May 08, 2009

5

4

3

2

1

C470

C470
*0.1u

*0.1u

/10V_4

/10V_4

13

NB_CORE

C483

C483

10u

10u

/6.3V_8

/6.3V_8

ER DIFFERENCE TABLE

R

S780

+1.1V
+1.1V
+1.2V
+1.8V
+1.8V
+1.8V
+1.1V
+1.1V

+1.8V/1.5V

+3.3V
+1.8V

E

C468

C468

C476

C476

0.1u

0.1u

0.1u

0.1u

/10V_4

/10V_4

C487

C487

C513

C513

0.1u

0.1u

0.1u

0.1u

/10V_4

/10V_4

C512

C512

0.1u

0.1u

/10V_4

/10V_4

EM

+1.8V_VDD_M

+3V_VDDG33

C469

C469

0.1u

0.1u

/10V_4

/10V_4

C477

C477

0.1u

0.1u

PIN NAME
IOPLLVDD

DD
AVDDDI
A

VDDQ
PLLVDD
PLLVDD18
VDDA18PCIEPLL
VDDA18HTPLL
VDDLTP18
VDDLT18
VDDLT33

C489

C489
1u

1u

/10V_4

/10V_4

C519

C519

0.1u

0.1u

/10V_4

/10V_4

C493

C493

0.1u

0.1u

/10V_4

/10V_4

R335

R335

/10V_4

/10V_4

RS

780

+1.1V
+3.3VAV
+1.8V
+1.8V
+1.1V

+1.8V
+1.8V
+1.8V
+1.8V
NC

VDDPCIE - PCIE-E Main power

R348

R348

C497

C497

C445

C445

4.7U/6.3V_6

4.7U/6.3V_6

1u

1u

/10V_4

/10V_4

/10V_4

/10V_4

C449

C449

C501

C501

10u

10u

0.1u

0.1u

/10V_4

/10V_4

C523

C523

0.1u

0.1u

*BLM

*BLM

21PG221SN1D(220_100M_2A)_8

21PG221SN1D(220_100M_2A)_8

L50

L50
R356

R356

RS780

*short0603

*short0603

/10V_4

/10V_4

/10V_4

/10V_4

/6.3V_8

/6.3V_8

0_6

0_6

10u

10u

VDD33 - 3.3V I/O

*short0805

*short0805

1.1V_NB

VDDC - Core Logic power

C533

C533

C467

C467

0.1u

0.1u

0.1u

0.1u

/10V_4

/10V_4

/10V_4

/10V_4

C457

C457

/6.3V_8

/6.3V_8

VDD_MEM For UMA RS780

VCC1.8

VCC3

C473

C473

0.1u

0.1u

/10V_4

/10V_4

RX

A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9

K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16

AE10
AA11
Y11
AD10
AB10
AC10

H11
H12

RS780 POW

+1.1V_VDD_PCI

A2

D3

G1

H7

J4

R7

L1

L2

L4

L7

M6

N4

P6

R1

R2

R4

V7

U4

V8

V6

W1

W2

W4

W7

W8

Y6

AA4

AB5

AB1

AB7

AC3

U10F

U10F

VSSAPCIE1

VSSAPCIE2B1VSSAPCIE3

VSSAPCIE4D5VSSAPCIE5E4VSSAPCIE6

VSSAPCIE7G2VSSAPCIE8G4VSSAPCIE9

VSSAPCIE10

VSSAPCIE11

VSSAPCIE12

VSSAPCIE13

VSSAPCIE14

VSSAPCIE15

VSSAPCIE16

VSSAPCIE17

VSSAPCIE18

VSSAPCIE19

VSSAPCIE20

VSSAPCIE21

VSSAPCIE22

VSSAPCIE23

VSSAPCIE24

VSSAPCIE25

VSSAPCIE26

VSSAPCIE27

VSSAPCIE28

VSSAPCIE29

VSSAHT24

VSSAHT25

VSSAHT26

VSSAHT27

Y21

W25

AD25

C514

C514

0.1u

0.1u

C486

C486

4.7U/6.3V_6

4.7U/6.3V_6

R338

R338

R136

R136

VSSAPCIE30

VSS11

VSS12

L12

M14

C538

C538

4.7U/6.3V_6

4.7U/6.3V_6

C205

C205

4.7U/6.3V_6

4.7U/6.3V_6

/10V_4

/10V_4

N13

C516

C516

0.1u

0.1u

D D

C C

B B

VDDA18PCIE ­PCIE TX stage
I/O for
RS780

6/6

6/6

PART

PART

VSSAHT1

VSSAHT2

VSSAHT3

VSSAHT4

VSSAHT5

VSSAHT6

VSSAHT7

VSSAHT8

VSSAHT9

VSSAHT10

VSSAHT11

VSSAHT12

VSSAHT13

VSSAHT14

J22

L17

L22

L24

H19

L25

M20

1.1V_NB

N22

P20

A25

E22

D23

G22

G24

G25

VDDHT - HT
LINK digital
I/O for
RS780

VDDHTRX - HT
LINK RX I/O for
RS780

2V 2A for RS780M+SB700

+1.

L17

VCC1.2

L17

BLM

BLM

21PG221SN1D(220_100M_2A)_8

21PG221SN1D(220_100M_2A)_8

VDDHTTX - HT
LINK TX I/O for
RS780

+1.8V 1A for RS780M+SB700

L52

VCC1.8

BLM

BLM

21PG221SN1D(220_100M_2A)_8

21PG221SN1D(220_100M_2A)_8

L52

VDD18 - RS780 I/O
transform

VSSAHT15

VSSAHT16

VSSAHT17

VSSAHT18

VSSAHT19

VSSAHT21

VSSAHT20

R19

R22

R24

R25

U22

H20

+1.1V 2A

L53

L53
BLM

BLM

21PG221SN1D(220_100M_2A)_8

21PG221SN1D(220_100M_2A)_8

L23

L23

21PG221SN1D(220_100M_2A)_8

21PG221SN1D(220_100M_2A)_8

BLM

BLM

C161

C161

4.7U/6.3V_6

4.7U/6.3V_6

C522

C522

4.7U/6.3V_6

4.7U/6.3V_6

VCC1.8

VCC1.8

VSSAHT22

VSSAHT23

V19

W22

W24

for RS780M

AC4

VSSAPCIE31

VSSAPCIE32

VSSAPCIE33

VSSAPCIE34

VSSAPCIE35

VSSAPCIE36

VSSAPCIE37

GROUND

GROUND

VSS13

VSS14

VSS15

VSS16

VSS17

VSS18

VSS19

T12

P12

P15

R11

R14

U14

C495

C495

0.1u

0.1u

C490

C490

0.1u

0.1u

C535

C535

0.1u

0.1u

/10V_4

/10V_4

C500

C500

0.1u

0.1u

/10V_4

/10V_4

*short0603

*short0603

C458

C458
1u/10V_4

1u/10V_4

*short0603

*short0603

VDD18_MEM For UMA RS780

AE1

AE4

AB2

VSSAPCIE38

VSSAPCIE39

VSSAPCIE40

VSS20

VSS21

VSS22

V12

U11

U15

W11

/10V_4

/10V_4

/10V_4

/10V_4

/10V_4

/10V_4

C170

C170
1u/10V_4

1u/10V_4

AE14

VSS1

VSS23

VSS24

VSS25

W15

AC12

C510

C510

0.1u

0.1u

C203

C203

0.1u

0.1u

C529

C529

0.1u

0.1u

+1.8V_VDDA

C472

C472

0.1u

0.1u

D11

AA14

+1.1V_VDDHT

+1.1V_VDDHT

+1.2V_VDDHT

/10V_4

/10V_4

VSS2

VSS3G8VSS4

VSS26

VSS27

Y18

/10V_4

/10V_4

/10V_4

/10V_4

/10V_4

/10V_4

+1.8V_VDDG18_NB

+1.8V_VDD18_M

E14

VSS28

AB11

E15

VSS5

VSS29

AB15

J12

J15

VSS6

VSS30

AB17

AB19

C505

C505

0.1u

0.1u

C200

C200

0.1u

0.1u

C555

C555

0.1u

0.1u

18PCIE

C492

C492

0.1u

0.1u

K14

VSS7

VSS8

VSS31

VSS32

AE20

RX

TX

M11

VSS9

VSS33

AB21

/10V_4

/10V_4

/10V_4

/10V_4

/10V_4

/10V_4

/10V_4

/10V_4

L15

VSS10

VSS34

K11

EM

M16

AE25
AD24
AC23
AB22
AA21

W1

M17

M10

AD9

AE11
AD11

J17
K16
L16

P16
R16
T16

H18
G19
F20
E21
D22
B23
A23

Y2
V18

U17
T17
R17
P17

J10
P10
K10

L10

T10
R10

AA9
AB9

AE9
U10

W9

H9

Y9

F9

G9

U10E

U10E

VDDHT_1
VDDHT_2
VDDHT_3
VDDHT_4
VDDHT_5
VDDHT_6
VDDHT_7

VDDHTRX_1
VDDHTRX_2
VDDHTRX_3
VDDHTRX_4
VDDHTRX_5
VDDHTRX_6
VDDHTRX_7

VDDHTTX_1
VDDHTTX_2
VDDHTTX_3
VDDHTTX_4
VDDHTTX_5

0

VDDHTTX_6

9

VDDHTTX_7
VDDHTTX_8
VDDHTTX_9
VDDHTTX_10
VDDHTTX_11
VDDHTTX_12
VDDHTTX_13

VDDA18PCI
VDDA18PCI
VDDA18PCI
VDDA18PCI
VDDA18PCI
VDDA18PCI
VDDA18PCI
VDDA18PCI
VDDA18PCI
VDDA18PCI
VDDA18PCI
VDDA18PCI
VDDA18PCI
VDDA18PCI
VDDA18PCI

VDDG18_1(
VDDG18_2(
VDD18_MEM1(
VDD18_MEM2(

RS780

RS780

PART

PART

E_1
E_2
E_3
E_4
E_5
E_6
E_7
E_8
E_9
E_10
E_11
E_12
E_13
E_14
E_15

VDD18_1)
VDD18_2)

NC)
NC)

VDDPCI

5/6

5/6

VDDPCI
VDDPCI
VDDPCI
VDDPCI
VDDPCI
VDDPCI
VDDPCI

VDDPCI
VDDPCI
VDDPCI
VDDPCI
VDDPCI
VDDPCI
VDDPCI
VDDPCI
VDDPCI

POWER

POWER

VDD_MEM1(
VDD_MEM2(
VDD_MEM3(
VDD_MEM4(
VDD_MEM5(
VDD_MEM6(

VDDG33_1(
VDDG33_2(

PIN NAME
VDDHT
VDDHT
VDDHTTX
VDDA18PCIE
VDDG18
VDD18_MEM +1.8V
VDDPCIE
VDDC
VDD_MEM
VDDG33

OPLLVDD18

I

E_1
E_2
E_3
E_4
E_5
E_6
E_7
E_8

E_9
E_10
E_11
E_12
E_13
E_14
E_15
E_16
E_17

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8

VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22

NC)
NC)
NC)
NC)
NC)
NC)

NC)
NC)

A A

Qu

Qu

Qu

anta Computer Inc.

anta Computer Inc.

anta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

R

R

R

S780M-POWER4/4

S780M-POWER4/4

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

S780M-POWER4/4

PROJECT :

ZN1

ZN1

ZN1

1A

1A

1A

of

of

of

41Friday, May 08, 2009

41Friday, May 08, 2009

41Friday, May 08, 2009

13

13

13

1