Quanta ZL2 DA0ZL2MB8F8, Aspire 1690, Aspire 3510, TravelMate 4100, TravelMate 4600 Schematic

1

5VPCU

5V / 3.3V / 12V

Page : 35

A A

2.5V / 1.25V

Page : 36

1.5V / 1.05V / 1.8V

B B

Page : 37

3V_ALWAYS
+12V
+5V
3V_S5

3VSUS
5VSUS

2.5VSUS
+2.5V
+1.8V
MVREF_DM
SMDDR_VTERM

1.5V_S5
+1.5V
AGP_VCC (+1.5V)

1.2VCCT
VTT

2

CLOCK GEN

ICS
ICS954201

Page : 2

DDR-SODIMM1

Page:9~10

DDR-SODIMM2

Page:9~10

3

CLK_SDRAM0~5,
CLK_SDRAM0~5#

333MHZ DDR

4

Centrino

DORTHAN
CELEROM-M

INTEL Mobile_479 CPU

ALVISO

1257 BGA
915GM/PM

Page : 5 ~ 8

Page : 3 , 4

HOST BUS 400MHz

5

6

CRANE ( ZL2 )

PCIE

LVDS

RGB

TVOUT

ATI

M24P/M26P

64M /
128M

Page : 11 ~ 14

EXT_LVDS

EXT_CRT

EXT_TV-OUT

INT_LVDS

INT_CRT

INT_TV-OUT

7

ED@ INT. VGA WITH DOCK
ID@ INT. VGA WITH DOCK
ND@ W/O DOCKING

要打

SWITCH
CIRCUIT

BOM MARK
E@ EXT VGA
I@ INTVGA
SA@ SATA
F@ FIXED ODD
SW@ SWAPPABLE ODD
3@ 3in1 n
N@ NEW CARD
4@ 4401 n
5@ 5705M
D@ DOCKING

8

要打

要打

要打

要打

打

要打

打

要打

要打

CRT

Page:17

LVDS

Page:16

TV-OUT

Page:16

要打

DVI
CH7307

DOCKING/DVI

SATA - HDD

Page:21

Page:15

Page: 33

IDE - HDD

CPU CORE

Page : 34

+1.2V

Page : 38

BATTERY

C C

CHARGER

Page : 39

VCC_CORE

VGA_CORE

2.5V_VGA

BATTERY
SELECT

Page : 40

Page:21

IDE-ODD

Page:21

MEDIA BAY

Page:21

AUDIO CODEC

CONEXANT
20468-31

Page:27

AMP

MAX9750

Page:28

CONEXANT

MODEM

20493-21

Page:27

SATA

ATA 66/100

AC97

DMI I/F

ICH6-M

609 BGA

Page : 18 ~ 20

LPC

NS

KBC(97551)

Page : 29

PCIE

PCI BUS

USB 2.0

NEW CARD

Page : 32

NS

SIO (87383)

Page : 31

TI

PCMCIA+1394

+3 IN 1

PCI7411

Page: 23

MINI-PCI

Wireless LAN
Modem/LAN

Page : 22

BROADCOM

10/100/1G LAN

4401 / 5705M

Page:25

BOTHHAND

TRANSFORMER

Page:26

3 IN 1

Page: 24

PCMCIA

Page: 24

1394

Page: 23

RJ45

Page:26

MIC IN

D D

PM :

紀明進

EE Laerer :
ME Leader : M

Sunyu Jih

劉鳴豹

林哲敏

1

Page:27

Selmon Liu

LINE
IN

ill Lin

2

SPEKER

Page:28Page:27

LINE
OUT

Page:28

RJ11

Page:27

3

DOCKING
PS2

Page:33

Touchpad

PCI ROUTING TABLE

REQ0# / GNT0#
REQ2# / GNT2#
REQ1# / GNT1#

4

IDSEL

AD24
AD19
AD17

Keyboard

Page:30Page:30

IrDA

Page:31

INTERUPT

INTA#
INTB# , INTD#
INTC#,INTD#,INTA#

DOCKING
Print Port

Page:33

DOCKING
COM Port

Page:33

DEVICE

BROADCOM LAN
MINI-PCI
TI 7411

5

SYSTEM 3
USB PORT

Page : 22

USB2,3,5

6

DOCKING 2
USB PORT

Page : 22

USB0,1

Size Document Number Re v

Date: Sheet

MINI-USB

Page: 22

Quanta Computer Inc.

BLOCK DIAGRAM

7

USB4

REV.E

PROJECT : ZL2

141Wednesday, December 22, 2004

8

F

of

1

2

3

4

5

6

7

8

REVB: POP R203 R468 AND DEPOP R204, R470 FOR DOTHAN B

IREF

R205

2.2

U35

50

XTAL_IN

49

XTAL_OUT

10

VTT_PWRGD#/PD

55

PCI/SRC_STOP#

54

CPU_STOP#

46

SCLK

47

SDATA

12

FSA/USB_48

16

FSB/TEST_MODE

53

FSC/TEST_SEL

48

VDD_REF

1

VDD_PCI_1

7

VDD_PCI_2

42

VDD_CPU

21

VDD_SRC0

28

VDD_SRC1

34

VDD_SRC2

11

VDD_48

39

IREF

*Internal Pull-Down Resistor

14

DOT96

15

DOT96#

12

C722

10U/10V_8

1 2

1 2

R463

1

R212

2.2

VDD_CKG_CPU

R468
1K_4

R470
*0_4

12

C366

12

C373

12

C368
.047U_4

10U/10V_8

10U/10V_8

C369
.047U_4

CLK48_USB<19>

12

C372
.047U_4

12

C707
.047U_4

12

1 2

1 2

12

C361
.047U_4

R489
10K_4

R488
*10K_4

SELPSB1_CLK<4,6>
SELPSB2_CLK<4,6>

VDD_CKGREF

CLKVDD

12

C371
.047U_4

12

C370
.047U_4

B: DEPOP COMPONENTS FOR
DIFFERENT SKUS

C718
33P_4

C709
33P_4

R482 33_4

1 2

12

C706

.047U_4

Iref=5mA,
Ioh=4*Iref

DOT96<6>
DOT96#<6>

12

12

CLK_EN#<34>

STP_PCI#<19>

STP_CPU#<19,34>

CG_XIN

12

Y4

14.318MHZ/20PF

CG_XOUT R_HCLK_CPU

CLK_EN#

SMbus address D2

SMBCK

SMBDT

SELPSB0_CLK
SELPSB1_CLK
SELPSB2_CLK

VDD_CKG_CPU

VDD_CKG_48

R465 475/F_4

1 2

I@4P2R-S-33

4
2

RP15

3
1

R_DOT96
R_DOT96#

SMBUS ADDRESS: D2, D3

+3V

A A

+3V

B B

1 2

L50 ACB2012L-120

+VCCP +3V+VCCP

R203
1K_4

1 2

SELPSB2_CLK SELPSB0_CLKSELPSB1_CLK

R204
*0_4

1 2

1 2

L51 ACB2012L-120

B: DEPOP SSC COMPONENTS

C C

R109

R106

+3V

2

4

2

,32,33>

D D

PCLK_SMB

,32,33> SMBCK <9>

3

Q40
2N7002

+3V

2

3

Q41
2N7002

1

1

3

1

1

*10K_4

RP9
4P2R-S-10K

SMBDT

SMBCK

2

*10K_4

1 2

SMBDT <9>PDAT_SMB

R111
*10K_4

1 2

1 2

SMBUS ADDRESS: D4, D5

SSCD_VDD

DOTHAN-A 400
DOTHAN-A 533

3

CLK_SSC_IN

SMBCK
SMBDT

CLK_EN#

1 2

R117 *10K_4

U9

1

SSC_S3
SSC_S2
SSC_S1

CLKIN

2

S3

3

S2

4

S1

7

SCLK

8

SDATA

5

PWRDWN

6

REFOUT/SEL

*MK1493-05GT

FSC FSB FSA CPU SRC PCI
1 0 1 100 100 33
0 0 1 133 100 33
0 1 1 166 100 33
0 1 0 200 100 33
0 0 0 266 100 33
1 0 0 333 100 33
1 1 0 400 100 33
1 1 1 RSVD 100 33

4

37

VDDA

CK-410M

GND_REF

GND_PCI_26GND_SRC29GND_CPU

GND_PCI_1

GND_48

2

51

13

VDDA

CLKOUT

CLKOUT#

IREF

VSSIREF

VSSA

VDDA_CKG

38

VSSA

CPU2_ITP/SRC5

CPU2#_ITP/SRC5#

*PERREQ1#
*PERREQ2#

PCIF0/ITP_EN

45

ICS954217

250mA ( MAX. )

16
9

VDD

12
11

14
13

10

VSS

15

12

C708
.047U_4

REF

CPU0

CPU0#

CPU1

CPU1#

SRC4

SRC4#

SATACLK

SATACLK#

SRC3

SRC3#

SRC2

SRC2#

SRC1

SRC1#

SRC0

SRC0#

PCI5
PCI4
PCI3
PCI2

PCIF1

SSCD_VDD

R_DREFSSCLK
R_DREFSSCLK#

5

12

C355

10U/10V_8

14M_REF

52
44

R_HCLK_CPU#

43

R_HCLK_MCH

41

R_HCLK_MCH#

40

R_MCH_3GPLL

36

R_MCH_3GPLL#

35
33

32

R_PCIE_VGA

31

R_PCIE_VGA#

30

R_PCIE_SATA

26

R_PCIE_SATA#

27

R_PCIE_EZ1

24

R_PCIE_EZ1#

25

R_PCIE_ICH

22

R_PCIE_I CH#

23

R_PCIE_EZ2

19

R_PCIE_EZ2#

20

R_PCIE_NEWC

17

R_PCIE_NEWC#

18

R_PCLK_591

5

R_PCLK_PCM

4

R_PCLK_LAN

3

R_PCLK_SIO

56

R_PCLK_MINI

9

R_PCLK_ICH

8

PULL HIGH TO SET PIN35,36 TO HOST CLK

*BLM21B331SB

12

12

*.1U_4

C241

4
2

R108
*475/F_4

1 2

C229
*10U/10V_8

RP2

*4P2R-S-33

Place these termination
to close CK410M.

R199 49.9/F_4

1 2

R198 49.9/F_4

1 2

R197 49.9/F_4

1 2

R196 49.9/F_4

1 2

R195 49.9/F_4

1 2

R194 49.9/F_4

1 2

4
2

4
2

4
2

4
2

2
4

2
4

2
4

2
4

2
4

L23

1 2

3
1

R110
*49.9/F_4

CLK_SSC_IN

RP10

3
1

4P2R-S-33
RP11

3
1

4P2R-S-33
RP12

3
1

4P2R-S-33

RP13

3
1

E@4P2R-S-33
RP20

1
3

SA@4P2R-S-33
RP19

1
3

D@4P2R-S-33
RP18

1
3

4P2R-S-33
RP17

1
3

D@4P2R-S-33
RP16

1
3

N@4P2R-S-33
R478 33_4
R477 33_4
R476 33_4
R464 33_4
R481 33_4
R479 33_4

R480 10K_4

1 2

+3V

1 2

1 2

6

R114
*49.9/F_4

12

R104
*33_4

12

C230
*10P_4

1 2
1 2
1 2
1 2
1 2
1 2

DREFSSCLK <6>
DREFSSCLK# <6>

B: DEPOP SSC COMPONENTS

E: R200/202 CHANGE TO 12ohm for EA pass

R201 *24_4

1 2

R200 12_4

1 2

R202 12_4

1 2

HCLK_CPU <3>
HCLK_CPU# <3>

HCLK_MCH <5>
HCLK_MCH# <5>

CLK_MCH_3GPLL <6>
CLK_MCH_3GPLL# <6>

NEW_CLKREQ# <32>
EZ_CLKREQ# <33>

CLK_PCIE_VGA <11>
CLK_PCIE_VGA# <11>

CLK_PCIE_SATA <18>
CLK_PCIE_SATA# <18>

CLK_PCIE_EZ1 <33>
CLK_PCIE_EZ1# <33>

CLK_PCIE_ICH <19>
CLK_PCIE_ICH# <19>

CLK_PCIE_EZ2 <33>
CLK_PCIE_EZ2# <33>

CLK_PCIE_NEWC <32>
CLK_PCIE_NEWC# <32>

PCLK_591 <29>
PCLK_PCM <23>
PCLK_LAN <25>
PCLK_SIO <31>
PCLK_MINI <22>
PCLK_ICH <18>

CLK_SSC_IN

14M_SIO

14M_SIO

D: ADD EMI SOLUTION

E: CHANGE TO 10p

PEREQ1# - SRC0, 2, SATA
PEREQ2# - SRC1, 3, 4

14M_SIO <31>

14M_ICH <19>

DEFALT OFF

DEFALT OFF

B: DEPOP COMPONENTS FOR
DIFFERENT SKUS

EZ_CLKREQ#
NEW_CLKREQ#

C: ADD PULLUPS
D: DEPOP R615

+3V

R615
*1K_4

1 2

1 2

12

R616
1K_4

C915
10P_4

B: DEPOP COMPONENTS FOR DIFFERENT SKUS

DOT96
DOT96#

CLK_PCIE_VGA
CLK_PCIE_VGA#

CLK_PCIE_SATA
CLK_PCIE_SATA#

CLK_PCIE_EZ2
CLK_PCIE_EZ2#

CLK_PCIE_ICH
CLK_PCIE_ICH#

CLK_PCIE_EZ1
CLK_PCIE_EZ1#

CLK_PCIE_NEWC

CLK_PCIE_NEWC#

R490 I@49.9/F_4

1 2

R491 I@49.9/F_4

1 2

R193 E@49.9/F_4

1 2

R192 E@49.9/F_4

1 2

R486 SA@49.9/F_4

1 2

R487 SA@49.9/F_4

1 2

R492 D@49.9/F_4

1 2

R493 D@49.9/F_4

1 2

R209 49.9/F_4

1 2

R208 49.9/F_4

1 2

R207 D@49.9/F_4

1 2

R206 D@49.9/F_4

1 2

R211 N@49.9/F_4

1 2

R210 N@49.9/F_4

1 2

Place these termination
to close CK410M.

QUANTA

Title

Size Document Number Rev

Date: Sheet

COMPUTER

CLOCK GENERATOR

ZL2 F

of

7

241Tuesday, December 21, 2004

8

1

2

3

4

5

6

7

8

1

1

+3V

T171

T157

T155
T156
T158
T160
T163
T161

+3V

2

+3V

2

R448
10K_4

Q38
2N7002

Q37
2N7002

3

3

+VCCP

MBDATA

MBCLK

1 2

BPM0#
BPM1#
BPM2#
BPM3#
PRDY#
PREQ#

MBDATA <29,40>

MBCLK <29,40>

MAX6648_AL# <29>

MAX6648_OV# <30>

+3V_S5

C640
*.1U_4

DBR#

of

341Tuesday, December 21, 2004

8

R409
150_4

+3V

HD#[0..63]

HDSTBN0# <5>
HDSTBP0# <5>
HDSTBN1# <5>
HDSTBP1# <5>
HDSTBN2# <5>
HDSTBP2# <5>
HDSTBN3# <5>
HDSTBP3# <5>

HDBI0# <5>
HDBI1# <5>
HDBI2# <5>
HDBI3# <5>

DBSY# <5>
DRDY# <5>

HCLK_CPU# <2>
HCLK_CPU <2>

CPUINIT# <18>
CPURST# <5>
DPWR# <5>

AA3
AA2

AF4
AC4
AC7
AC3
AD3
AE4
AD2
AB4
AC6
AD5
AE2
AD6
AF3
AE1
AF1

AE5

A13
A12
C12
C11
B13
A16
A15
B10
A10

B18
A18

C17
B17

P4
U4
V3
R3
V2

W1

T4

W2

Y4
Y1
U1

Y3

U3

R2
P3
T2
P1
T1

N2

A4
N4

J3

L1

J2
K3

K4

L4
C8

B8
A9
C9

M3

H1
K1

L2
C2

D3
A3
E4
B4

A7
D1

D4
C6
A6
B7

G1

U31A

A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#

ADSTB0#
ADSTB1#

REQ0#
REQ1#
REQ2#
REQ3#
REQ4#

ADS#

IERR#
BREQ0#

BPRI#
BNR#
LOCK#

HIT#
HITM#
DEFER#

BPM0#
BPM1#
BPM2#
BPM3#
TRDY#
RS0#
RS1#
RS2#

A20M#
FERR#
IGNNE#
PWRGOOD
SMI#

TCK
TDO
TDI
TMS
TRST#
ITP_CLK0
ITP_CLK1
PREQ#
PRDY#
DBR#

LINT0
LINT1
STPCLK#
SLP#
DPSLP#
DPRSTP#

THERMDA
THERMDC

THERMTRIP#
PROCHOT#

Dothan Processor

Dothan

REQUEST
PHASE
SIGNALS

ERROR
SIGNALS

ARBITRATION
PHASE
SIGNALS

SNOOP PHASE
SIGNALS

RESPONSE
PHASE
SIGNALS

PC
COMPATIBILITY
SIGNALS

DIAGNOSTIC
& TEST
SIGNALS

EXECUTION
CONTROL
SIGNALS

THERMAL DIODE

3

1 OF 3

DATA
PHASE
SIGNALS

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#

D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

DSTBN0#
DSTBP0#
DSTBN1#
DSTBP1#
DSTBN2#
DSTBP2#
DSTBN3#
DSTBP3#

DINV0#
DINV1#
DINV2#
DINV3#

DBSY#
DRDY#

BCLK1
BCLK0

INIT#

RESET#

DPWR#

HD#0

A19

HD#1

A25

HD#2

A22

HD#3

B21

HD#4

A24

HD#5

B26

HD#6

A21

HD#7

B20

HD#8

C20

HD#9

B24

HD#10

D24

HD#11

E24

HD#12

C26

HD#13

B23

HD#14

E23

HD#15

C25

HD#16

H23

HD#17

G25

HD#18

L23

HD#19

M26

HD#20

H24

HD#21

F25

HD#22

G24

HD#23

J23

HD#24

M23

HD#25

J25

HD#26

L26

HD#27

N24

HD#28

M25

HD#29

H26

HD#30

N25

HD#31

K25

HD#32

Y26

HD#33

AA24

HD#34

T25

HD#35

U23

HD#36

V23

HD#37

R24

HD#38

R26

HD#39

R23

HD#40

AA23

HD#41

U26

HD#42

V24

HD#43

U25

HD#44

V26

HD#45

Y23

HD#46

AA26

HD#47

Y25

HD#48

AB25

HD#49

AC23

HD#50

AB24

HD#51

AC20

HD#52

AC22

HD#53

AC25

HD#54

AD23

HD#55

AE22

HD#56

AF23

HD#57

AD24

HD#58

AF20

HD#59

AE21

HD#60

AD21

HD#61

AF25

HD#62

AF22

HD#63

AF26

C23
C22
K24
L24
W25
W24
AE24
AE25

D25
J26
T24
AD20

M2
H2

B14
B15

CPUINIT#

B5

CPURST#

B11
C19

4

HA#[3..31]<5>

A A

B B

C C

+VCCP

R429
150_4

TDI

G1: NC for Dothan and
DPRSTP# for Yonah

D D

THERMTRIP#<6,18>

+VCCP

1

CPUPWRGD<18>

C: UNINSTALL

R441 *0_4

R436 56_4

HA#[3..31]

HADSTB0#<5>
HADSTB1#<5>

HREQ#0<5>
HREQ#1<5>
HREQ#2<5>
HREQ#3<5>
HREQ#4<5>

ADS#<5>

HBREQ0#<5>

BPRI#<5>

BNR#<5>

HLOCK#<5>

HIT#<5>

HITM#<5>

DEFER#<5>

HTRDY#<5>

RS#0<5>
RS#1<5>
RS#2<5>

A20M#<18>

FERR#<18>

IGNNE#<18>

SMI#<18>

T180
T179

DBR#<19>

INTR<18>
NMI<18>
STPCLK#<18>

CPUSLP#<5,18>

DPSLP#<18>

DPRSLP#<18>

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

IERR#

BPM0#
BPM1#
BPM2#
BPM3#

A20M#
FERR#
IGNNE#
CPUPWRGD
SMI#

TCK
TDO
TDI
TMS
TRST#

PREQ#
PRDY#
DBR#

STPCLK#
CPUSLP#
DPSLP#

THERMDA
THERMDC

THERMTRIP#_PWR

CPU_PROCHOT#

2

+3V

THERMDC

THERMDA

HD#[0..63] <5>

R439 47

10 mil trace /
10 mil space

5

15 MIL

3V_THM

C661
.1U_4

C674
2200P

THERMTRIP#_PWR

TDI

TMS
TDO

TRST#

CPURST#

TCK

TCK NO STUB

close to ITP conn

TCK
TRST#

close to CPU

IERR#
CPUPWRGD

R618
56_4

R619

330_4

B: DEPOP R425, R426, R421, C640 WHEN NO JITP

+VCCP +VCCP

R422

54.9/F_4

R425 *22.6/F_4

R421 *22.6/F_4

R430 27.4/F_4
R427 680_4

R393 56_4
R402 200/F_4

6

U33

1

VCC

3

DXN

2

DXP

-OVT4GND

MAX6657

+VCCP+VCCP

1 3

Q53 MMBT3904

R426
*54.9/F_4

+VCCP

R442
10K_4

+3V

R435
10K_4

KBSMDAT

7

SMDATA

KBSMCLK

8

SMCLK

6

-ALT

5

R449
*10K_4

+3V

B: DEPOP R449
D: POP R449

R617
330_4

2

E: DEPOP R449

1999_SHT# <35>

C: ADD SHUTDOWN CIRCUITS

R428

39.2/F_4

T177
T173

T166
T176

T162

T178

JITP CONN

QUANTA

Title

Size Document Number Rev

Date: Sheet

COMPUTER

Dothan Processor (HOST)

ZL2 F

7

1

2

3

4

5

6

7

8

+VCCP

T152
T153

T181

CPU_VCCA

*0_8
0_8

COMP0
COMP1
COMP2
COMP3

GTLREF0

TEST1
TEST2

VCC_CORE

COMP0
COMP1
COMP2
COMP3

A A

27.4/F_4

B B

12

C262

10U_6.3V

12

C325

10U_6.3V

C C

12

C672

10U_6.3V

C660

10U_6.3V

1 2

R457

R458

54.9/F_4

27.4/F_4

Place pulldown resistors within

0.5" of COMP pins

.01U/16V_4

VCC_CORE

12

12

12

C250
10U_6.3V

VCC_CORE

12

C320

10U_6.3V

12

C301

10U_6.3V

VCC_CORE

C292

10U_6.3V

1 2

C328

10U_6.3V

12

C281

10U_6.3V

12

C309

10U_6.3V

C666

10U_6.3V

1 2

C286

10U_6.3V

12

C294

10U_6.3V

12

C671

10U_6.3V

C279

10U_6.3V

1 2

R132

R124

54.9/F_4

C704

12

C298

10U_6.3V

12

C300

10U_6.3V

12

C653

10U_6.3V

C299

10U_6.3V

1 2

1 2

12

C702

10U_6.3V

12

C255

10U_6.3V

12

C313

10U_6.3V

C663

10U_6.3V

1 2

1K/F

2K/F_4

CPU_VCCA

12

C649

10U_6.3V

12

C322

10U_6.3V

10U_6.3V

1 2

R455

R456

VCC_CORE

VCC_CORE

VCC_COREVCC_CORE

C668

Place voltage
divider within

0.5" of GTLREF
pin

R407

*1K_4

T182
T128
T151

+1.8V
+1.5V

12

12

C310

C656

10U_6.3V

10U_6.3V

12

12

C329

C321

10U_6.3V

10U_6.3V

C305

C659

10U_6.3V

10U_6.3V

1 2

1 2

R459
*1K_4

R461
R462

12

C683
10U_6.3V

12

C684

10U_6.3V

C657

10U_6.3V

1 2

Total caps = 2633 uF
ESR = 15m oh m/5 // 5m ohm / 25 // 5m ohm /15

D D

+VCCP

12

C351

+

150U/4V

<Type>
CC3528

12

C304

.1U_4

1

12

C681
.1U_4

12

.1U_4

C327

12

C652

.1U_4

2

12

C651

.1U_4

+VCCP

C285
.1U_4

3

C307

.1U_4

C650
.1U_4

C678

.1U_4

C682

.1U_4

4

P25
P26
AB2
AB1

AD26

AF7
AC1
E26

AC26

D18
D20
D22

E17
E19
E21

G21
H22

K22

V22

W21

Y22
AA5
AA7

AA9
AA11
AA13
AA15
AA17
AA19
AA21

AB6

AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22

AC9
AC11
AC13
AC15
AC17
AC19

AD8
AD10
AD12
AD14
AD16
AD18

AE9
AE11
AE13
AE15
AE17
AE19

AF8
AF10
AF12
AF14
AF16
AF18

C5

F23

B2
C3

N1
B1

F26

D6
D8

E5
E7
E9

F6

F8
F18
F20
F22

G5
H6

J5

J21

U5
V6

W5

Y6

U31B

COMP0
COMP1
COMP2
COMP3

GTLREF0

TEST1
TEST2

NC1
RSVD2

RSVD3
RSVD4
RSVD5

VCCA3
VCCA2
VCCA1
VCCA0

VCC00
VCC01
VCC02
VCC03
VCC04
VCC05
VCC06
VCC07
VCC08
VCC09
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71

Dothan Processor

Dothan

2 OF 3

POWER,
GROUND,
RESERVED
SIGNALS

A2

VSS00

A5

VSS01

A8

VSS02

A11

VSS03

A14

VSS04

A17

VSS05

A20

VSS06

A23

VSS07

A26

VSS08

B3

VSS09

B6

VSS10

B9

VSS11

B12

VSS12

B16

VSS13

B19

VSS14

B22

VSS15

B25

VSS16

C1

VSS17

C4

VSS18

C7

VSS19

C10

VSS20

C13

VSS21

C15

VSS22

C18

VSS23

C21

VSS24

C24

VSS25

D2

VSS26

D5

VSS27

D7

VSS28

D9

VSS29

D11

VSS30

D13

VSS31

D15

VSS32

D17

VSS33

D19

VSS34

D21

VSS35

D23

VSS36

D26

VSS37

E3

VSS38

E6

VSS39

E8

VSS40

E10

VSS41

E12

VSS42

E14

VSS43

E16

VSS44

E18

VSS45

E20

VSS46

E22

VSS47

E25

VSS48

F1

VSS49

F4

VSS50

F5

VSS51

F7

VSS52

F9

VSS53

F11

VSS54

F13

VSS55

F15

VSS56

F17

VSS57

F19

VSS58

F21

VSS59

F24

VSS60

G2

VSS61

G6

VSS62

G22

VSS63

G23

VSS64

G26

VSS65

H3

VSS66

H5

VSS67

H21

VSS68

H25

VSS69

J1

VSS70

J4

VSS71

J6

VSS72

J22

VSS73

J24

VSS74

K2

VSS75

K5

VSS76

K21

VSS77

K23

VSS78

K26

VSS79

L3

VSS80

L6

VSS81

L22

VSS82

L25

VSS83

M1

VSS84

M4

VSS85

M5

VSS86

M21

VSS87

M24

VSS88

N3

VSS89

N6

VSS90

N22

VSS91

N23

VSS92

N26

VSS93

P2

VSS94

P5

VSS95

P21

VSS96

P24

VSS97

R1

VSS98

R4

VSS99

5

CPU_VID0<34>
CPU_VID1<34>
CPU_VID2<34>
CPU_VID3<34>
CPU_VID4<34>
CPU_VID5<34>

T159

T154

SELPSB2_CLK<2,6>
SELPSB1_CLK<2,6>

SELPSB2_CLK
SELPSB1_CLK

DOTHAN-A NC
DOTHAN-B POP

6

1 2
1 2

T146

+VCCP

Z0501
Z0502

0_4

BSEL0

R433

BSEL1

R432

0_4

Title

Size Document Number Rev

Date: Sheet

U31C

W23

D10

VCCP0

D12

VCCP1

D14

VCCP2

D16

VCCP3

E11

VCCP4

E13

VCCP5

E15

VCCP6

F10

VCCP7

F12

VCCP8

F14

VCCP9

F16

VCCP10

K6

VCCP11

L5

VCCP12

L21

VCCP13

M6

VCCP14

M22

VCCP15

N5

VCCP16

N21

VCCP17

P6

VCCP18

P22

VCCP19

R5

VCCP20

R21

VCCP21

T6

VCCP22

T22

VCCP23

U21

VCCP24

P23

VCCQ0

W4

VCCQ1

E2

VID0

F2

VID1

F3

VID2

G3

VID3

G4

VID4

H4

VID5

AE7

VCCSENSE

AF6

VSSSENSE

C16

BSEL0

C14

BSEL1

E1

PSI

R6

VSS100

R22

VSS101

R25

VSS102

T3

VSS103

T5

VSS104

T21

VSS105

T23

VSS106

T26

VSS107

U2

VSS108

U6

VSS109

U22

VSS110

U24

VSS111

V1

VSS112

V4

VSS113

V5

VSS114

V21

VSS115

V25

VSS116

W3

VSS117

W6

VSS118

W22

VSS119

Dothan Processor

Dothan

3 OF 3

POWER, GROUND AND NC

VID

VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191

W26
Y2
Y5
Y21
Y24
AA1
AA4
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB3
AB5
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26
AC2
AC5
AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24
AD1
AD4
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD22
AD25
AE3
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF2
AF5
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF24

QUANTA
COMPUTER

Dothan Processor (POWER)

ZL2 F

of

7

441Tuesday, December 21, 2004

8

1

2

3

4

5

6

7

8

U34E

AF23

VSS136

H23

VSS137

AL22

VSS138

AH22

VSS139

J22

VSS140

E22

VSS141

D22

VSS142

A22

VSS143

AN21

VSS144

AF21

VSS145

F21

VSS146

C21

VSS147

A A

B B

C C

D D

1

AK20

AN19
AG19

AL18

AN17
AF17

AL16

AN14
AL14

AG14

AN11
AL11

AG11
AF11
AA11

AA10

AN24
AL24

VSS148

V20

VSS149

G20

VSS150

F20

VSS151

E20

VSS152

D20

VSS153

A20

VSS154
VSS155
VSS156

W19

VSS157

T19

VSS158

J19

VSS159

H19

VSS160

C19

VSS161
VSS162

U18

VSS163

B18

VSS164

A18

VSS165
VSS166

AJ17

VSS167
VSS168

G17

VSS169

C17

VSS170
VSS171

K16

VSS172

H16

VSS173

D16

VSS174

A16

VSS175

K15

VSS176

C15

VSS177
VSS178
VSS179

AJ14

VSS180
VSS181

K14

VSS182

J14

VSS183

F14

VSS184

B14

VSS185

A14

VSS186

J12

VSS187

D12

VSS188

B12

VSS189
VSS190
VSS191

AJ11

VSS192
VSS193
VSS194
VSS195

Y11

VSS196

H11

VSS197

F11

VSS198
VSS199

Y10

VSS200

L10

VSS201

D10

VSS202

AN9

VSS203

AH9

VSS204

AE9

VSS205

AC9

VSS206

AA9

VSS207

V9

VSS208

T9

VSS209

K9

VSS210

H9

VSS211

A9

VSS212

AL8

VSS213

Y8

VSS214

P8

VSS215

L8

VSS216

E8

VSS217

C8

VSS218

AN7

VSS219

AK7

VSS220

AG7

VSS221

AA7

VSS222

V7

VSS223

G7

VSS224

AJ6

VSS225

AE6

VSS226

AC6

VSS227

AA6

VSS228

T6

VSS229

P6

VSS230

L6

VSS231

J6

VSS232

B6

VSS233

AP5

VSS234

AL5

VSS235

W5

VSS236

E5

VSS237

AN4

VSS238

AF4

VSS239

Y4

VSS240

U4

VSS241

P4

VSS242

L4

VSS243

H4

VSS244

C4

VSS245

AJ3

VSS246

AC3

VSS247

AB3

VSS248

AA3

VSS249

C3

VSS250

A3

VSS251

AN2

VSS252

AL2

VSS253

AH2

VSS254

AE2

VSS255

AD2

VSS256

V2

VSS257

T2

VSS258

P2

VSS259

L2

VSS260

B27

VSS261

J26

VSS262

G26

VSS263

E26

VSS264

A26

VSS265
VSS266
VSS267

J2

VSS268

G2

VSS269

D2

VSS270

Y1

VSS271

B36

VSSALVDS

VSS

2

AG37

VSS0

Y37

VSS1

V37

VSS2

T37

VSS3

P37

VSS4

M37

VSS5

K37

VSS6

H37

VSS7

E37

VSS8

AN36

VSS9

AL36

VSS10

AJ36

VSS11

AF36

VSS12

AE36

VSS13

AD36

VSS14

AC36

VSS15

AB36

VSS16

AA36

VSS17

C36

VSS18

AE35

VSS19

Y35

VSS20

W35

VSS21

V35

VSS22

U35

VSS23

T35

VSS24

R35

VSS25

P35

VSS26

N35

VSS27

M35

VSS28

L35

VSS29

K35

VSS30

J35

VSS31

H35

VSS32

G35

VSS33

F35

VSS34

E35

VSS35

D35

VSS36

B35

VSS37

AN34

VSS38

AH34

VSS39

AD34

VSS40

AC34

VSS41

AB34

VSS42

AA34

VSS43

C34

VSS44

AL33

VSS45

AF33

VSS46

AD33

VSS47

W33

VSS48

V33

VSS49

U33

VSS50

T33

VSS51

R33

VSS52

P33

VSS53

N33

VSS54

M33

VSS55

L33

VSS56

K33

VSS57

J33

VSS58

H33

VSS59

G33

VSS60

F33

VSS61

E33

VSS62

D33

VSS63

AN32

VSS64

AJ32

VSS65

AD32

VSS66

AC32

VSS67

AB32

VSS68

AA32

VSS69

Y32

VSS70

C32

VSS71

A32

VSS72

AL31

VSS73

AG31

VSS74

AD31

VSS75

W31

VSS76

V31

VSS77

U31

VSS78

T31

VSS79

R31

VSS80

P31

VSS81

N31

VSS82

M31

VSS83

L31

VSS84

K31

VSS85

J31

VSS86

H31

VSS87

G31

VSS88

F31

VSS89

E31

VSS90

D31

VSS91

AP30

VSS92

AE30

VSS93

AC30

VSS94

AB30

VSS95

AA30

VSS96

Y30

VSS97

C30

VSS98

AM29

VSS99

AJ29

VSS100

AG29

VSS101

AD29

VSS102

AA29

VSS103

W29

VSS104

V29

VSS105

U29

VSS106

P29

VSS107

L29

VSS108

H29

VSS109

G29

VSS110

F29

VSS111

E29

VSS112

D29

VSS113

A29

VSS114

AC28

VSS115

AB28

VSS116

AA28

VSS117

W28

VSS118

E28

VSS119

AN27

VSS120

AL27

VSS121

AJ27

VSS122

AG27

VSS123

AF27

VSS124

AB27

VSS125

AA27

VSS126

W27

VSS127

G27

VSS128

E27

VSS129

AJ24

VSS130

AG24

VSS131

J24

VSS132

F24

VSS133

D24

VSS134

B24

VSS135

@ALVISO_GM/GML

221/F_4

100/F_4

24.9/F_4

R453
221/F_4

R452
100/F_4

R438

R437

R454

+VCCP

+VCCP

+VCCP

+VCCP

HXRCOMP

R434

24.9/F_4

R150

54.9/F_4

HXSCOMP

HYRCOMP

R451

54.9/F_4

HYSCOMP

HXSWING

C665

.1U_4

1 2

HYSWING

C690

.1U_4

1 2

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8

HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

U34A

E4

HD0#

E1

HD1#

F4

HD2#

H7

HD3#

E2

HD4#

F1

HD5#

E3

HD6#

D3

HD7#

K7

HD8#

F2

HD9#

J7

HD10#

J8

HD11#

H6

HD12#

F3

HD13#

K8

HD14#

H5

HD15#

H1

HD16#

H2

HD17#

K5

HD18#

K6

HD19#

J4

HD20#

G3

HD21#

H3

HD22#

J1

HD23#

L5

HD24#

K4

HD25#

J5

HD26#

P7

HD27#

L7

HD28#

J3

HD29#

P5

HD30#

L3

HD31#

U7

HD32#

V6

HD33#

R6

HD34#

R5

HD35#

P3

HD36#

T8

HD37#

R7

HD38#

R8

HD39#

U8

HD40#

R4

HD41#

T4

HD42#

T5

HD43#

R1

HD44#

T3

HD45#

V8

HD46#

U6

HD47#

W6

HD48#

U3

HD49#

V5

HD50#

W8

HD51#

W7

HD52#

U2

HD53#

U1

HD54#

Y5

HD55#

Y2

HD56#

V4

HD57#

Y7

HD58#

W1

HD59#

W3

HD60#

Y3

HD61#

Y6

HD62#

W2

HD63#

C1

HXRCOMP

C2

HXSCOMP

D1

HXSWING

T1

HYRCOMP

L1

HYSCOMP

P1

HYSWING

@ALVISO_GM/GML

HOST

HA3#
HA4#
HA5#
HA6#
HA7#
HA8#

HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#

HADS#

HADSTB0#
HADSTB1#

HVREF
HBNR#

HBPRI#

BREQ0#

HCPURST#

HCLKINN
HCLKINP

HDBSY#

HDEFER#

HDINV#0
HDINV#1
HDINV#2
HDINV#3
HDPWR#

HDRDY#
HDSTBN0#
HDSTBN1#
HDSTBN2#
HDSTBN3#

HDSTBP0#
HDSTBP1#
HDSTBP2#
HDSTBP3#

HEDRDY#

HHIT#

HHITM#

HLOCK#

HPCREQ#

HREQ0#

HREQ1#

HREQ2#

HREQ3#

HREQ4#

HRS0#
HRS1#
HRS2#

HCPUSLP#

HTRDY#

G9
C9
E9
B7
A10
F9
D8
B10
E10
G10
D9
E11
F10
G11
G13
C10
C11
D11
C12
B13
A12
F12
G12
E12
C13
B11
D13
A13
F13

F8
B9
E13
J11
A5
D5
E7
H10

AB1
AB2

C6
E6
H8
K3
T7
U5
G6
F7
G4
K1
R3
V3
G5
K2
R2
W4
F6
D4
D6
B3
A11
A7
D7
B8
C7
A8
A4
C5
B4
G8
B5

HD#[0..63]<3>

HD#[0..63]

HXRCOMP
HXSCOMP
HXSWING
HYRCOMP
HYSCOMP
HYSWING

HA#[3.. 31]
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

HCPUSLP#_GMC H

HA#[3..31] <3>

ADS# <3>
HADSTB0# <3>
HADSTB1# <3>

BNR # <3>
BPRI# <3>
HBREQ0# <3>
CPURS T# <3>

HCLK_MCH# <2>
HCLK_MCH <2>

DBSY# <3>
DEFER# <3>
HDBI0# <3>
HDBI1# <3>
HDBI2# <3>
HDBI3# <3>

DPWR# <3>

DRDY# <3>
HDSTBN0# <3>
HDSTBN1# <3>
HDSTBN2# <3>
HDSTBN3# <3>
HDSTBP0# <3>
HDSTBP1# <3>
HDSTBP2# <3>
HDSTBP3# <3>

HIT# <3>
HITM# <3>
HLOCK# <3>

HREQ#0 <3>
HREQ#1 <3>
HREQ#2 <3>
HREQ#3 <3>
HREQ#4 <3>
RS#0 <3>
RS#1 <3>
RS#2 <3>

HTRDY# <3>

+VCCP

R178
100/F_4

HVREF

R173
200/F_4

T60
*PAD

T170
*PAD

B: POP FOR DOTHAN B

R162

1 2

0_4

CPUSLP # <3,18>

DO NOT INSTALL FOR DOTHAN-A AND INSTALL FOR DOTHAN-B

C331

.1U_4

1 2

QUANTA

Title

Size Doc u m en t N u m be r Re v

3

4

5

6

Date: Sheet

7

COMPUTER

Alviso (Host)

ZL2 F

C

541Tuesday, De ce mber 21, 2004

8

of

1

DMI_TXN0<19>
DMI_TXN1<19>

12

R184
*40.2/F_4

R190

80.6/F_4

M_RCOMPN
M_RCOMPP

R188

80.6/F_4

DREFSSCLK_R
DREFSSCLK#_R

DREFSSCLK#_R
DREFSSCLK_R

DMI_TXN2<19>
DMI_TXN3<19>

DMI_TXP0<19>
DMI_TXP1<19>
DMI_TXP2<19>
DMI_TXP3<19>

DMI_RXN0<19>
DMI_RXN1<19>
DMI_RXN2<19>
DMI_RXN3<19>

DMI_RXP0<19>
DMI_RXP1<19>
DMI_RXP2<19>
DMI_RXP3<19>

CLK_SDRAM0<9>
CLK_SDRAM1<9>

T79 T54

CLK_SDRAM3<9>
CLK_SDRAM4<9>

T74

CLK_SDRAM0#<9>
CLK_SDRAM1#<9>

T78

CLK_SDRAM3#<9>
CLK_SDRAM4#<9>

T73

CKE0<9,10>
CKE1<9,10>
CKE2<9,10>
CKE3<9,10>

SM_CS0#<9,10>
SM_CS1#<9,10>
SM_CS2#<9,10>
SM_CS3#<9,10>

CLK_SDRAM2

CLK_SDRAM5

CLK_SDRAM2#

CLK_SDRAM5#

CKE0
CKE1
CKE2
CKE3

SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#

M_OCDCOMP0
M_OCDCOMP1

E: DEPOP

M_RCOMPN

+2.5V

R606

1 2
1 2

R607

RP7

4
2

*4P2R-S-0

M_RCOMPP

SMXSLEW
SMYSLEW

R171 10K_4

1 2

R170 10K_4

1 2

*0
*0

3
1

+1.25VSUS

It's point to point,
55ohm trace, keep as
short as possible.

A A

B B

12

R186
*40.2/F_4

Route as short
as possible.

C C

+2.5VSUS

12

12

D D

D: DEPOP RP7

1

2

CFG[0:2]=100 FOR FSB 533
CFG[0:2]=101 FOR FSB 400

U34C

AA31

DMIRXN0

AB35

DMIRXN1

AC31

DMIRXN2

AD35

DMIRXN3

Y31

DMIRXP0

AA35

DMIRXP1

AB31

DMIRXP2

AC35

DMIRXP3

AA33

DMITXN0

AB37

DMITXN1

AC33

DMITXN2

AD37

DMITXN3

Y33

DMITXP0

AA37

DMITXP1

AB33

DMITXP2

AC37

DMITXP3

AM33

SM_CK0

AL1

SM_CK1

AE11

SM_CK2

AJ34

SM_CK3

AF6

SM_CK4

AC10

SM_CK5

AN33

SM_CK0#

AK1

SM_CK1#

AE10

SM_CK2#

AJ33

SM_CK3#

AF5

SM_CK4#

AD10

SM_CK5#

AP21

SM_CKE0

AM21

SM_CKE1

AH21

SM_CKE2

AK21

SM_CKE3

AN16

SM_CS0#

AM14

SM_CS1#

AH15

SM_CS2#

AG16

SM_CS3#

AF22

SM_OCDCOMP0

AF16

SM_OCDCOMP1

AP14

SM_ODT0

AL15

SM_ODT1

AM11

SM_ODT2

AN10

SM_ODT3

AK10

SMRCOMPN

AK11

SMRCOMPP

AF37

SMVREF0

AD1

SMVREF1

AE27

SMXSLEWIN

AE28

SMXSLEWOUT

AF9

SMYSLEWIN

AF10

SMYSLEWOUT

@ALVISO_GM/GML

PM_EXTTS#0

PM_EXTTS#1

DREFSSCLK <2>
DREFSSCLK# <2>

DOT96# <2>
DOT96 <2>

2

DMIDDR MUXING

CFG/RSVDPMLCKNC

THRMTRIP#

DREF_CLKN

DREF_CLKP
DREF_SSCLKN
DREF_SSCLKP

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8

CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27

BM_BUSY#

EXT_TS0#
EXT_TS1#

PWROK

RSTIN#

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8

NC9
NC10
NC11

3

CFG3

R168

*1K_4

R174 4.7K_4

CFG0

G16
H13
G14
F16
F15
G15
E16
D17
J16
D15
E15
D14
E14
H12
C14
H15
J15
H14
G22
G23
D23
G25
G24
J17
A31
A30
D26
D25

J23
J21
H22
F5
AD30
AE29

A24
A23
C37
D37

AP37
AN37
AP36
AP2
AP1
AN1
B1
A2
B37
A36
A37

3

1 2

R164 1K_4
R167 1K_4

CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

CFG[17:3] have internal pullup resistors.
CFG[19:18] have internal pulldown resistors

PM_EXTTS#0
PM_EXTTS#1

DOT96#
DOT96
DREFSSCLK#_R
DREFSSCLK_R

TP_NC1
TP_NC2
TP_NC3
TP_NC4
TP_NC5
TP_NC6
TP_NC7
TP_NC8

TP_NC9
TP_NC10
TP_NC11

T56

R177 0_4

1 2

R460 100

T187
T183
T186
T185
T184
T188
T175
T167
T172
T165
T164

TXLCLKOUT-<11,16>
TXLCLKOUT+<11,16>
TXUCLKOUT-<11,16>
TXUCLKOUT+<11,16>

TXLOUT0-<11,16>
TXLOUT0+<11,16>
TXLOUT1-<11,16>
TXLOUT1+<11,16>
TXLOUT2-<11,16>
TXLOUT2+<11,16>

TXUOUT0-<11,16>
TXUOUT0+<11,16>
TXUOUT1-<11,16>
TXUOUT1+<11,16>
TXUOUT2-<11,16>
TXUOUT2+<11,16>

DISP_ON<11,16>
BLON<11,16>

R166 *1K_4
R157

*1K_4

T50
T70

R153

T58

R161

T52
T63
T49
T72
T69
T67
T66
T59
T55
T64
T68
T71
T169
T168

T51

PM_BMBUSY# <19>

IMVP_PWRGD <19,34>
PLTRST# <11,15,18,21,29,31,32,33>

4

FOR DDR533

+VCCP

SELPSB1_CLK <2,4>
SELPSB2_CLK <2,4>

*1K_4
1K_4

THERMTRIP# <3,18>

B: POP ALWAYS

R147 150/F_4

1 2

R148 150/F_4

1 2

R151 150/F_4

1 2

R143 150/F_4

1 2

R152 150/F_4

1 2

R159 150/F_4

1 2

TXLCLKOUT+
TXUCLKOUT­TXUCLKOUT+

TXLOUT0­TXLOUT1-

TXLOUT1+
TXLOUT2­TXLOUT2+

TXUOUT0­TXUOUT0+
TXUOUT1­TXUOUT1+
TXUOUT2­TXUOUT2+

DISP_ON
BLON

4

CFG5 Low=DMIx2
High=DMIx4
CFG6 Low=DDR2
High=DDR

CFG9 Low=REVERSE LANE
High=NORMAL

CFG11 FOR CPU533

INT_DDCCLK<17>
INT_DDCDAT<17>

INT_VGA_BLU<17>
INT_VGA_GRN<17>
INT_VGA_RED<17>

INT_VSYNC<17>

INT_HSYNC<17>

INT_TV_C/R
INT_TV_COMP
INT_TV_Y/G

INT_VGA_RED
INT_VGA_GRN
INT_VGA_BLU

241
241

241
241
241

241
241
241

R134I@0_4
R139I@0_4

I_EDIDCLK<16>
I_EDIDDATA<16>

RN110I@4P2R-S-0

3

RN9I@4P2R-S-0

3

RN107I@4P2R-S-0

3

RN108I@4P2R-S-0

3

RN109I@4P2R-S-0

3

RN12I@4P2R-S-0

3

RN11I@4P2R-S-0

3

RN10I@4P2R-S-0

3

5

SDVO_CTRLDATA<15>

SDVO_CTRLCLK<15>
CLK_MCH_3GPLL#<2>
CLK_MCH_3GPLL<2>

INT_TV_COMP<16>

INT_TV_Y/G<16>
INT_TV_C/R<16>

R156 1.5K/F

INT_TXLCLKOUT-TXLCLKOUT­INT_TXLCLKOUT+
INT_TXUCLKOUT­INT_TXUCLKOUT+

INT_TXLOUT0-

INT_TXLOUT0+TXLOUT0+

INT_TXLOUT1-

INT_TXLOUT1+

INT_TXLOUT2-

INT_TXLOUT2+

INT_TXUOUT0-

INT_TXUOUT0+

INT_TXUOUT1-

INT_TXUOUT1+

INT_TXUOUT2-

INT_TXUOUT2+

INT_DISP_ON
INT_BLON

5

R169 4.99K/F

R176 255/F_4

INT_BLON

T47
T48

INT_DISP_ON

T53
T62
T61

INT_TXLCLKOUT­INT_TXLCLKOUT+
INT_TXUCLKOUT­INT_TXUCLKOUT+

INT_TXLOUT0­INT_TXLOUT1­INT_TXLOUT2-

INT_TXLOUT0+
INT_TXLOUT1+
INT_TXLOUT2+

INT_TXUOUT0­INT_TXUOUT1­INT_TXUOUT2-

INT_TXUOUT0+
INT_TXUOUT1+
INT_TXUOUT2+

6

GMCHEXP_TXP[0..15]<11>
GMCHEXP_TXN[0..15]<11>
GMCHEXP_RXP[0..15]<11,15>

GMCHEXP_RXN[0..15]<11,15>

U34F

H24

SDVOCTRL_DATA

H25

SDVOCTRL_CLK

AB29

GCLKN

AC29

GCLKP

INT_TV_COMP
INT_TV_Y/G
INT_TV_C/R
TV_REFSET

REFSET

A15

TVDAC_A

C16

TVDAC_B

A17

TVDAC_C

J18

TV_REFSET

B15

TV_IRTNA

B16

TV_IRTNB

B17

TV_IRTNC

E24

DDCCLK

E23

DDCDATA

E21

BLUE

D21

BLUE#

C20

GREEN

B20

GREEN#

A19

RED

B19

RED#

H21

VSYNC

G21

HSYNC

J20

REFSET

T57

E25

LBKLT_CTRL

F25

LBKLT_EN

C23

LCTLA_CLK

C22

LCTLB_DATA

F23

LDDC_CLK

F22

LDDC_DATA

F26

LVDD_EN

C33

LIBG

C31

LVBG

F28

LVREFH

F27

LVREFL

B30

LACLKN

B29

LACLKP

C25

LBCLKN

C24

LBCLKP

B34

LADATAN0

B33

LADATAN1

B32

LADATAN2

A34

LADATAP0

A33

LADATAP1

B31

LADATAP2

C29

LBDATAN0

D28

LBDATAN1

C27

LBDATAN2

C28

LBDATAP0

D27

LBDATAP1

C26

LBDATAP2

@ALVISO_GM/GML

B: NO STUFF WHEN NO DOCKING

6

7

GMCHEXP_TXP[0..15]
GMCHEXP_TXN[0..15]

GMCHEXP_RXP[0..15]
GMCHEXP_RXN[0..15]

R158 24.9/F_4

MISC

TV VGA LVDS

PCI-EXPRESS GRAPHICS

CGMCHEXP_TXP0
CGMCHEXP_TXN0

CGMCHEXP_TXP1
CGMCHEXP_TXN1

CGMCHEXP_TXP2
CGMCHEXP_TXN2

CGMCHEXP_TXP3
CGMCHEXP_TXN3

EXP_COMPI

EXP_ICOMPO

EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8

EXP_RXN9
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

EXP_RXP0

EXP_RXP1

EXP_RXP2

EXP_RXP3

EXP_RXP4

EXP_RXP5

EXP_RXP6

EXP_RXP7

EXP_RXP8

EXP_RXP9

EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

EXP_TXN0

EXP_TXN1

EXP_TXN2

EXP_TXN3

EXP_TXN4

EXP_TXN5

EXP_TXN6

EXP_TXN7

EXP_TXN8

EXP_TXN9

EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

EXP_TXP0

EXP_TXP1

EXP_TXP2

EXP_TXP3

EXP_TXP4

EXP_TXP5

EXP_TXP6

EXP_TXP7

EXP_TXP8

EXP_TXP9

EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

D36
D34

GMCHEXP_RXN0

E30

GMCHEXP_RXN1

F34

GMCHEXP_RXN2

G30

GMCHEXP_RXN3

H34

GMCHEXP_RXN4

J30

GMCHEXP_RXN5

K34

GMCHEXP_RXN6

L30

GMCHEXP_RXN7

M34

GMCHEXP_RXN8

N30

GMCHEXP_RXN9

P34

GMCHEXP_RXN10

R30

GMCHEXP_RXN11

T34

GMCHEXP_RXN12

U30

GMCHEXP_RXN13

V34

GMCHEXP_RXN14

W30

GMCHEXP_RXN15

Y34

GMCHEXP_RXP0

D30

GMCHEXP_RXP1

E34

GMCHEXP_RXP2

F30

GMCHEXP_RXP3

G34

GMCHEXP_RXP4

H30

GMCHEXP_RXP5

J34

GMCHEXP_RXP6

K30

GMCHEXP_RXP7

L34

GMCHEXP_RXP8

M30

GMCHEXP_RXP9

N34

GMCHEXP_RXP10

P30

GMCHEXP_RXP11

R34

GMCHEXP_RXP12

T30

GMCHEXP_RXP13

U34

GMCHEXP_RXP14

V30

GMCHEXP_RXP15

W34

CGMCHEXP_TXN0

E32

CGMCHEXP_TXN1

F36

CGMCHEXP_TXN2

G32

CGMCHEXP_TXN3

H36

CGMCHEXP_TXN4

J32

CGMCHEXP_TXN5

K36

CGMCHEXP_TXN6

L32

CGMCHEXP_TXN7

M36

CGMCHEXP_TXN8

N32

CGMCHEXP_TXN9

P36

CGMCHEXP_TXN10

R32

CGMCHEXP_TXN11

T36

CGMCHEXP_TXN12

U32

CGMCHEXP_TXN13

V36

CGMCHEXP_TXN14

W32

CGMCHEXP_TXN15

Y36

CGMCHEXP_TXP0

D32

CGMCHEXP_TXP1

E36

CGMCHEXP_TXP2

F32

CGMCHEXP_TXP3

G36

CGMCHEXP_TXP4

H32

CGMCHEXP_TXP5

J36

CGMCHEXP_TXP6

K32

CGMCHEXP_TXP7

L36

CGMCHEXP_TXP8

M32

CGMCHEXP_TXP9

N36

CGMCHEXP_TXP10

P32

CGMCHEXP_TXP11

R36

CGMCHEXP_TXP12

T32

CGMCHEXP_TXP13

U36

CGMCHEXP_TXP14

V32

CGMCHEXP_TXP15

W36

C629ID@.1U_4

12

C627ID@.1U_4

12

C308ID@.1U_4

12

C312ID@.1U_4

12

C625ID@.1U_4

12

C620ID@.1U_4

12

C318ID@.1U_4

12

C323ID@.1U_4

12

1 2

SDVOB_R+
SDVOB_R-

SDVOB_G+
SDVOB_G-

SDVOB_B+

SDVOB_B-

SDVOB_CLK+

SDVOB_CLK-

QUANTA

Title

Size Document Number Rev

Custom

Date: Sheet

COMPUTER

Alviso (VGA,DMI)

ZL2 F

7

8

VCC3G_PCIE

GMCHEXP_TXN0

C626E@.1U_4

GMCHEXP_TXN1

C667E@.1U_4

GMCHEXP_TXN2

C619E@.1U_4

GMCHEXP_TXN3

C673E@.1U_4

GMCHEXP_TXN4

C613E@.1U_4

GMCHEXP_TXN5

C685E@.1U_4

GMCHEXP_TXN6

C605E@.1U_4

GMCHEXP_TXN7

C689E@.1U_4

GMCHEXP_TXN8

C599E@.1U_4

GMCHEXP_TXN9

C692E@.1U_4

GMCHEXP_TXN10

C594E@.1U_4

GMCHEXP_TXN11

C695E@.1U_4

GMCHEXP_TXN12

C592E@.1U_4

GMCHEXP_TXN13

C698E@.1U_4

GMCHEXP_TXN14

C590E@.1U_4

GMCHEXP_TXN15

C587E@.1U_4

GMCHEXP_TXP0

C628E@.1U_4

GMCHEXP_TXP1

C664E@.1U_4

GMCHEXP_TXP2

C624E@.1U_4

GMCHEXP_TXP3

C669E@.1U_4

GMCHEXP_TXP4

C616E@.1U_4

GMCHEXP_TXP5

C679E@.1U_4

GMCHEXP_TXP6

C608E@.1U_4

GMCHEXP_TXP7

C686E@.1U_4

GMCHEXP_TXP8

C601E@.1U_4

GMCHEXP_TXP9

C691E@.1U_4

GMCHEXP_TXP10

C595E@.1U_4

GMCHEXP_TXP11

C693E@.1U_4

GMCHEXP_TXP12

C593E@.1U_4

GMCHEXP_TXP13

C697E@.1U_4

GMCHEXP_TXP14

C591E@.1U_4

GMCHEXP_TXP15

C588E@.1U_4

SDVOB_R+ <15>
SDVOB_R- <15>

SDVOB_G+ <15>
SDVOB_G- <15>

SDVOB_B+ <15>
SDVOB_B- <15>

SDVOB_CLK+ <15>
SDVOB_CLK- <15>

641Tuesday, December 21, 2004

8

of

1

2

3

4

5

6

7

8

MD[0..63]
SM_DQS[0..7]
SDM[0..7]

RN26

A A

4P2R-S-10
RN43

4P2R-S-10

RN25
4P2R-S-10
RN42
4P2R-S-10

RN24
4P2R-S-10
RN41
4P2R-S-10

RN40
4P2R-S-10

RN23
4P2R-S-10

RN32
4P2R-S-10
RN44
4P2R-S-10

B B

RN35
4P2R-S-10

RN31
4P2R-S-10

RN30
4P2R-S-10

RN50
4P2R-S-10

RN29
4P2R-S-10

RN49
4P2R-S-10

RN28
4P2R-S-10
RN48
4P2R-S-10

RN27
4P2R-S-10

RN47
4P2R-S-10

C C

RN34
4P2R-S-10
RN46
4P2R-S-10

RN45
4P2R-S-10

RN33
4P2R-S-10

RN22
4P2R-S-10
RN39
4P2R-S-10

RN21
4P2R-S-10
RN38
4P2R-S-10

RN37
4P2R-S-10

RN20
4P2R-S-10

D D

RN19
4P2R-S-10
RN36
4P2R-S-10

MD31 R_MD31
MD26 R_MD26
MD30
MD27

MD25 R_MD25
MD24 R_MD24
MD28 R_MD28
MD29 R_MD29

MD18 R_MD18
MD22 R_MD22
MD23

MD21
MD20
MD16
MD17

MD35 R_MD35
MD34 R_MD34
MD39 R_MD39
MD38 R_MD38

MD36
MD37
MD33
MD32

MD59
MD58
MD62
MD63

MD56
MD60
MD61
MD57

MD51 R_MD51
MD50 R_MD50
MD55 R_MD55
MD54 R_MD54

MD48
MD49

MD52

MD47 R_MD47
MD46 R_MD46
MD42 R_MD42
MD43 R_MD43

MD44
MD45
MD40
MD41

MD14 R_MD14

MD13
MD9

MD12 R_MD12

MD6
MD3
MD2
MD7

MD5 R_MD5

1

2

1

4

3
3
1

1
3
1
3

1
3
1
3

3
1
3
1

1
3
1
3

3
1
1
3

3
1
3
1

3
1
1
3

1
3
1
3

3
1
3
1

1
3
1
3

3
1
3
1

1
3
1
3

1
3
1
3

3
1
1
3

1
3
1
3

R_MD30

4

R_MD27

2

2
4
2
4

R_MD19MD19

2
4
2

R_MD23

4

R_MD21

4

R_MD20

2

R_MD16

4

R_MD17

2

2
4
2
4

R_MD36

4

R_MD37

2

R_MD33

2

R_MD32

4

R_MD59

4

R_MD58

2

R_MD62

4

R_MD63

2

R_MD56

4

R_MD60

2

R_MD61

2

R_MD57

4

2
4
2
4

R_MD48

4

R_MD53MD53

2

R_MD49

4

R_MD52

2

2
4
2
4

R_MD44

4

R_MD45

2

R_MD40

4

R_MD41

2

R_MD10MD10

2

R_MD11MD11

4

R_MD15MD15

2
4

R_MD13

2

R_MD8MD8

4

R_MD9

2
4

R_MD6

4

R_MD3

2

R_MD2

2

R_MD7

4

R_MD1MD1

2

R_MD0MD0

4

R_MD4MD4

2
4

R_SDM0
R_SDM1

R_SDM6 R_SM_DQS6
R_SDM7

2

R_MD0
R_MD1
R_MD2
R_MD3
R_MD4
R_MD5
R_MD6
R_MD7
R_MD8
R_MD9
R_MD10
R_MD11
R_MD12
R_MD13
R_MD14
R_MD15
R_MD16
R_MD17
R_MD18
R_MD19
R_MD20
R_MD21
R_MD22
R_MD23
R_MD24
R_MD25
R_MD26
R_MD27
R_MD28
R_MD29
R_MD30
R_MD31
R_MD32
R_MD33
R_MD34
R_MD35
R_MD36
R_MD37
R_MD38
R_MD39
R_MD40
R_MD41
R_MD42
R_MD43
R_MD44
R_MD45
R_MD46
R_MD47
R_MD48
R_MD49
R_MD50
R_MD51
R_MD52
R_MD53
R_MD54
R_MD55
R_MD56
R_MD57
R_MD58
R_MD59
R_MD60
R_MD61
R_MD62
R_MD63

1 2

R236 10_4

1 2

R241 10_4

1 2

R242 10_4

1 2

R237 10_4

1 2

R235 10_4

1 2

R238 10_4

1 2

R239 10_4

1 2

R240 10_4

U34B

AG35

SADQ0

AH35

SADQ1

AL35

SADQ2

AL37

SADQ3

AH36

SADQ4

AJ35

SADQ5

AK37

SADQ6

AL34

SADQ7

AM36

SADQ8

AN35

SADQ9

AP32

SADQ10

AM31

SADQ11

AM34

SADQ12

AM35

SADQ13

AL32

SADQ14

AM32

SADQ15

AN31

SADQ16

AP31

SADQ17

AN28

SADQ18

AP28

SADQ19

AL30

SADQ20

AM30

SADQ21

AM28

SADQ22

AL28

SADQ23

AP27

SADQ24

AM27

SADQ25

AM23

SADQ26

AM22

SADQ27

AL23

SADQ28

AM24

SADQ29

AN22

SADQ30

AP22

SADQ31

AM9

SADQ32

AL9

SADQ33

AL6

SADQ34

AP7

SADQ35

AP11

SADQ36

AP10

SADQ37

AL7

SADQ38

AM7

SADQ39

AN5

SADQ40

AN6

SADQ41

AN3

SADQ42

AP3

SADQ43

AP6

SADQ44

AM6

SADQ45

AL4

SADQ46

AM3

SADQ47

AK2

SADQ48

AK3

SADQ49

AG2

SADQ50

AG1

SADQ51

AL3

SADQ52

AM2

SADQ53

AH3

SADQ54

AG3

SADQ55

AF3

SADQ56

AE3

SADQ57

AD6

SADQ58

AC4

SADQ59

AF2

SADQ60

AF1

SADQ61

AD4

SADQ62

AD5

SADQ63

SDM0 SM_DQS0
SDM1 SM_DQS1

SDM6 SM_DQS6
SDM7 R_SM_DQS7

3

MD[0..63] <9,10>
SM_DQS[0..7] <9,10>
SDM[0..7] <9,10>

SA_BS0#
SA_BS1#
SA_BS2#

SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8

SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13

DDR SYSTEM MEMORY A

SA_CAS#
SA_RAS#

SA_RCVENIN#

SA_RCVENOUT#

SA_WE#

@ALVISO_GM/GML

R_SM_DQS0
R_SM_DQS1
R_SM_DQS2R_SDM2
R_SM_DQS3R_SDM3

R_SM_DQS4R_SDM4

R_SM_DQS5R_SDM5 SDM5

M_A_BA0

AK15

M_A_BA1

AK16
AL21

R_SDM0

AJ37

R_SDM1

AP35

R_SDM2

AL29

R_SDM3

AP24

R_SDM4

AP9

R_SDM5

AP4

R_SDM6

AJ2

R_SDM7

AD3

R_SM_DQS0

AK36

R_SM_DQS1

AP33

R_SM_DQS2

AN29

R_SM_DQS3

AP23

R_SM_DQS4

AM8

R_SM_DQS5

AM4

R_SM_DQS6

AJ1

R_SM_DQS7

AE5
AK35

AP34
AN30
AN23
AN8
AM5
AH1
AE4

M_A_MA0

AL17

M_A_MA1

AP17

M_A_MA2

AP18

M_A_MA3

AM17

M_A_MA4

AN18

M_A_MA5

AM18

M_A_MA6

AL19

M_A_MA7

AP20

M_A_MA8

AM19

M_A_MA9

AL20

M_A_MA10

AM16

M_A_MA11

AN20

M_A_MA12

AM20

M_A_MA13

AM15

M_A_SCASA#

AN15

M_A_SRASA#

AP16

SA_RCVENIN#

AF29

SA_RCVENOUT#

AF28

M_A_BMWEA#

AP15

1 2

R214 10_4

1 2

R215 10_4

1 2

R216 10_4

1 2

R217 10_4

1 2

R220 10_4

1 2

R221 10_4

1 2

R218 10_4

1 2

R219 10_4

4

SM_DQS2SDM2
SM_DQS3SDM3
SM_DQS4SDM4
SM_DQS5

SM_DQS7

M_A_BA0 <9,10>
M_A_BA1 <9,10>

M_A_MA[0..13] <9,10>

M_A_SCASA# <9,10>
M_A_SRASA# <9,10>

T77
T80

M_A_BMWEA# <9,10>

5

AE31
AE32
AG32
AG36
AE34
AE33

AF31

AF30
AH33
AH32
AK31
AG30
AG34
AG33
AH31

AJ31
AK30

AJ30
AH29
AH28
AK29
AH30
AH27
AG28

AF24
AG23

AJ22
AK22
AH24
AH23
AG22

AJ21
AG10

AG9
AG8

AH8
AH11
AH10

AK9

AK6

AH5

AK8

AK4

AG5

AG4

AD8

AD9

AH4

AG6

AE8

AD7

AC5

AB8

AB6

AA8

AC8

AC7

AA4

AA5

U34G

SBDQ0
SBDQ1
SBDQ2
SBDQ3
SBDQ4
SBDQ5
SBDQ6
SBDQ7
SBDQ8
SBDQ9
SBDQ10
SBDQ11
SBDQ12
SBDQ13
SBDQ14
SBDQ15
SBDQ16
SBDQ17
SBDQ18
SBDQ19
SBDQ20
SBDQ21
SBDQ22
SBDQ23
SBDQ24
SBDQ25
SBDQ26
SBDQ27
SBDQ28
SBDQ29
SBDQ30
SBDQ31
SBDQ32
SBDQ33
SBDQ34
SBDQ35
SBDQ36
SBDQ37

AJ9

SBDQ38
SBDQ39

AJ7

SBDQ40
SBDQ41

AJ4

SBDQ42
SBDQ43
SBDQ44

AJ8

SBDQ45

AJ5

SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63

SB_BS0#
SB_BS1#
SB_BS2#

SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7

SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8

SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13

DDR SYSTEM MEMORY B

SB_CAS#
SB_RAS#

SB_RCVENIN#

SB_RCVENOUT#

SB_WE#

@ALVISO_GM/GML

AJ15
AG17
AG21

AF32
AK34
AK27
AK24
AJ10
AK5
AE7
AB7

AF34
AK32
AJ28
AK23
AM10
AH6
AF8
AB4

AF35
AK33
AK28
AJ23
AL10
AH7
AF7
AB5

AH17
AK17
AH18
AJ18
AK18
AJ19
AK19
AH19
AJ20
AH20
AJ16
AG18
AG20
AG15

AH14
AK14
AF15
AF14
AH16

M_B_BA0
M_B_BA1

M_B_MA0
M_B_MA1
M_B_MA2
M_B_MA3
M_B_MA4
M_B_MA5
M_B_MA6
M_B_MA7
M_B_MA8
M_B_MA9
M_B_MA10
M_B_MA11
M_B_MA12
M_B_MA13

M_B_SCASA#
M_B_SRASA#
SB_RCVENIN#
SB_RCVENOUT#
M_B_BMWEA#

M_B_BA0 <9,10>
M_B_BA1 <9,10>

M_B_MA[0..13] <9,10>

M_B_SCASA# <9,10>
M_B_SRASA# <9,10>

T75
T76

M_B_BMWEA# <9,10>

QUANTA

Title

Size Document Number Rev

Custom

6

Date: Sheet

COMPUTER

Alviso (DDR)

ZL2 F

of

7

741Tuesday, December 21, 2004

8

5

+VCCP

3900mA

12

12

C687

C340

.1U_4

.1U_4

D D

12

12

12

C334

C332

10U_6.3V

.1U_4

C330
10U_6.3V

12

C336
10U_6.3V

B: DEPOP C259, C248, C306, C303 WHEN NO EXT.VGA

L31

VCCA_DPLLA

+1.5V

60mA

+1.5V

C C

+1.5V

60mA

+1.5V

60mA

10UH

10UH

1UH

L69

1UH

12

L28

12

L70

12

12

12

12

C306
I@.1U_4

VCCA_DPLLB

12

C303
I@.1U_4

12

C701
.1U_4

C696
.1U_4

C259

+

I@470U/2.5V

C248

+

I@470U/2.5V

C699

+

470U/2.5V

C688

+

470U/2.5V

.1U_4

+2.5V

C319

+1.5V

12

VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL

VCCA_CRTDAC

12

C291
10U_6.3V

B: CHANGE FROM RB751

R142

VCCGFOLLOW

10

B B

+2.5V

68mA

+VCCP

12

@BLM18PG181S N 1/ 0_6

12

C341

2.2U_6.3V

L39

C333

4.7U/10V_8

12

C293
I@.022U_4

D11

CH551

VCCA_CRTDAC

12

C287
I@.1U_4

21

+VCCP

C646 .47 U /25V

1 2

C658 .47 U /25V

1 2

C694 .22U

C670 .22U

+VCCP

810mA

VCCP_GMCH_CAP1

VCCP_GMCH_CAP2
VCCP_GMCH_CAP3

VCCP_GMCH_CAP4

T29
R29

N29
M29
K29

J29
V28
U28
T28
R28
P28
N28
M28

L28
K28

J28
H28
G28
V27
U27
T27
R27
P27
N27
M27

L27
K27

J27
H27
K26
H26
K25

J25
K24
K23
K22
K21
W20
U20
T20
K20
V19
U19
K19
W18
V18
T18
K18
K17

AC2
AC1
B23
C35
AA1
AA2

F19
E19
G19

H20
K13

J13
K12
W11
V11
U11
T11
R11
P11
N11
M11

L11
K11
W10
V10
U10
T10
R10
P10
N10
M10
K10

J10

Y9

W9

U9
R9
P9
N9
M9

L9

J9
N8
M8
N7
M7
N6
M6
A6
N5
M5
N4
M4
N3
M3
N2
M2
B2
V1
N1
M1
G1

U34H

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48

VCCH_MPLL1
VCCH_MPLL0
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL

VCCA_CRTDAC0
VCCA_CRTDAC1
VVSSA_CRTDAC

VCC_SYNC
VTT0

VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
VTT32
VTT33
VTT34
VTT35
VTT36
VTT37
VTT38
VTT39
VTT40
VTT41
VTT42
VTT43
VTT44
VTT45
VTT46
VTT47
VTT48
VTT49
VTT50
VTT51

@ALVISO_GM/GML

4

POWER

VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCA_TVBG
VSSA_TVBG

VCCD_TVDAC

VCCDQ_TVDAC

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCA_LVDS

VCCHV0
VCCHV1
VCCHV2

VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8

VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCSM52
VCCSM53
VCCSM54
VCCSM55
VCCSM56
VCCSM57
VCCSM58
VCCSM59
VCCSM60
VCCSM61
VCCSM62
VCCSM63
VCCSM64

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2

VCCA_SM0
VCCA_SM1
VCCA_SM2
VCCA_SM3

VCC3G0

VCC3G1

VCC3G2

VCC3G3

VCC3G4

VCC3G5

VCC3G6

VCCA_3GPLL0
VCCA_3GPLL1
VCCA_3GPLL2

VCCA_3GBG
VSSA_3GBG

F17
E17
D18
C18
F18
E18

H18
G18

D19
H17

B26
B25
A25

A35
B22

B21
A21

AM37
AH37
AP29
AD28
AD27
AC27
AP26
AN26
AM26
AL26
AK26
AJ26
AH26
AG26
AF26
AE26
AP25
AN25
AM25
AL25
AK25
AJ25
AH25
AG25
AF25
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AE17
AE16
AE15
AE14
AP13
AN13
AM13
AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AP12
AN12
AM12
AL12
AK12
AJ12
AH12
AG12
AF12
AE12
AD11
AC11
AB11
AB10
AB9
AP8
AM1
AE1

B28
A28
A27

AF20
AP19
AF19
AF18

AE37
W37
U37
R37
N37
L37
J37

Y29
Y28
Y27

F37
G37

VCC_TVBG

+1.5V

VCC_QTVDAC

V1.8_DDR_CAP6
V1.8_DDR_CAP3
V1.8_DDR_CAP4

B: NO FILTER WHEN EXT. VGA

12

C273
I@.1U_4

C296
.1U_4

Note: All VCCSM
pins shorted
internally.

+2.5VSUS

12

C346

10U_6.3V

C358 .1U_4

1 2

C354 .1U_4

1 2

C348 .1U_4

1 2

12

C315
.1U_4

L32
@BLM18PG181S N 1/ 0_6

+2.5V

12

2mA

C280
10U_6.3V

C356 .1U_4

1 2

C705 .1U_4

1 2

C357 .1U_4

1 2

12

C344
10U_6.3V

+

C339

220U/2.5V

12

+2.5V

150mA

VCC_TVDACC

C264
I@.022U_4

V1.8_DDR_CAP1

V1.8_DDR_CAP2

V1.8_DDR_CAP5

+2.5V

60mA

VCC_DDRDLL

VCC3G_PCIE

12

12

Note: All VCCSM
pins shorted
internally.

3

C274

I@.022U_4

+3V

12

12

C290
.1U_4

C272

I@.022U_4

C260

.022U_4

C360

VCC_QTVDAC

C271

I@.022U_4

+

330U/6.3V-7343

B: NO FILTER WHEN EXT. VGA

12

12

C703

C345

10U_6.3V

10U_6.3V

12

C343

C342
.1U_4

10U_6.3V

VCC_TVDACA

12

C265
I@.1U_4

10mA

+2.5V

12

C302
.01U/16V_4

VCC_TVBG

12

C266
I@.1U_4

12

C261
.1U_4

12

C263
I@.1U_4

+

C359

100U/10V

VCC3G_PCIE

12

+3V

L33

12

@BLM18PG1 81SN1/0_6

120mA

VCC_TVDACB

12

C275

C267

I@.022U_4

I@.1U_4

+1.5V

60mA

12

12

C918
I@10U_6.3V

12

C295
.1U_4

L34

12

@BLM18PG1 81SN1/0_6

C277
10U_6.3V

+3V

E: Add bulk cap. for acer TV

+1.5V

close to PIN D19

L30

@BLM18PG181SN1/0_6

L49

BLM18PG181SN1

12

C349
.1U_4

L71

BLM18PG181SN1
C700
.1U_4

R182

1 2

0.5/F

24mA

12

+1.5V

12

12

+1.5V

+1.5V

30mA

1A

VCCA_3GPLL_1VCCA_3GPLL

L46

BLM18PG181SN1

R133

V1_5VFOLLOW

10

L35

12

@BLM18PG181SN1/0_6

+VCCP

12

+1.5V

2

B: CHANGE FROM RB751

D10

21

+1.5V

CH551

+3V

W13

V13
U13
T13
R13
P13
N13

M13

L13

W12

V12
U12
T12
R12
P12
N12

M12

L12

AB26
AA26

Y26
AB25
AA25

Y25
AB24
AA24

Y24
AB23
AA23

Y23
AB22
AA22

Y22
AB21
AA21

Y21

R21
AB20
AA20
AB19
AA19
AB18
AA18
AB17
AA17

Y17

R17
AB16
AA16

Y16

W16

V16

U16

T16

R16

P16

N16

M16

L16
AB15
AA15

Y15

W15

V15

U15

T15

R15

P15

N15

M15

L15
AB14
AA14

Y14

W14

V14

U14

T14

R14

P14

N14

M14

L14
AA13

Y13
AA12

Y12

U34D

VTT_NCTF0
VTT_NCTF1
VTT_NCTF2
VTT_NCTF3
VTT_NCTF4
VTT_NCTF5
VTT_NCTF6
VTT_NCTF7
VTT_NCTF8
VTT_NCTF9
VTT_NCTF10
VTT_NCTF11
VTT_NCTF12
VTT_NCTF13
VTT_NCTF14
VTT_NCTF15
VTT_NCTF16
VTT_NCTF17

VSS_NCTF0
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12
VSS_NCTF13
VSS_NCTF14
VSS_NCTF15
VSS_NCTF16
VSS_NCTF17
VSS_NCTF18
VSS_NCTF19
VSS_NCTF20
VSS_NCTF21
VSS_NCTF22
VSS_NCTF23
VSS_NCTF24
VSS_NCTF25
VSS_NCTF26
VSS_NCTF27
VSS_NCTF28
VSS_NCTF29
VSS_NCTF30
VSS_NCTF31
VSS_NCTF32
VSS_NCTF33
VSS_NCTF34
VSS_NCTF35
VSS_NCTF36
VSS_NCTF37
VSS_NCTF38
VSS_NCTF39
VSS_NCTF40
VSS_NCTF41
VSS_NCTF42
VSS_NCTF43
VSS_NCTF44
VSS_NCTF45
VSS_NCTF46
VSS_NCTF47
VSS_NCTF48
VSS_NCTF49
VSS_NCTF50
VSS_NCTF51
VSS_NCTF52
VSS_NCTF53
VSS_NCTF54
VSS_NCTF55
VSS_NCTF56
VSS_NCTF57
VSS_NCTF58
VSS_NCTF59
VSS_NCTF60
VSS_NCTF61
VSS_NCTF62
VSS_NCTF63
VSS_NCTF64
VSS_NCTF65
VSS_NCTF66
VSS_NCTF67
VSS_NCTF68

NCTF

VCCSM_NCTF0
VCCSM_NCTF1
VCCSM_NCTF2
VCCSM_NCTF3
VCCSM_NCTF4
VCCSM_NCTF5
VCCSM_NCTF6
VCCSM_NCTF7
VCCSM_NCTF8

VCCSM_NCTF9
VCCSM_NCTF10
VCCSM_NCTF11
VCCSM_NCTF12
VCCSM_NCTF13
VCCSM_NCTF14
VCCSM_NCTF15
VCCSM_NCTF16
VCCSM_NCTF17
VCCSM_NCTF18
VCCSM_NCTF19
VCCSM_NCTF20
VCCSM_NCTF21
VCCSM_NCTF22
VCCSM_NCTF23
VCCSM_NCTF24
VCCSM_NCTF25
VCCSM_NCTF26
VCCSM_NCTF27
VCCSM_NCTF28
VCCSM_NCTF29
VCCSM_NCTF30
VCCSM_NCTF31

VCC_NCTF0
VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF8

VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VCC_NCTF47
VCC_NCTF48
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
VCC_NCTF65
VCC_NCTF66
VCC_NCTF67
VCC_NCTF68
VCC_NCTF69
VCC_NCTF70
VCC_NCTF71
VCC_NCTF72
VCC_NCTF73
VCC_NCTF74
VCC_NCTF75
VCC_NCTF76
VCC_NCTF77
VCC_NCTF78

@ALVISO_GM/GML

AD26
AC26
AD25
AC25
AD24
AC24
AD23
AC23
AD22
AC22
AD21
AC21
AD20
AC20
AD19
AC19
AD18
AC18
AD17
AC17
AD16
AC16
AD15
AC15
AD14
AC14
AD13
AC13
AB13
AD12
AC12
AB12

W26
V26
U26
T26
R26
P26
N26
M26
L26
W25
V25
U25
T25
R25
P25
N25
M25
L25
W24
V24
U24
T24
R24
P24
N24
M24
L24
W23
V23
U23
T23
R23
P23
N23
M23
L23
W22
V22
U22
T22
R22
P22
N22
M22
L22
W21
V21
U21
T21
P21
N21
M21
L21
Y20
R20
P20
N20
M20
L20
Y19
R19
P19
N19
M19
L19
Y18
R18
P18
N18
M18
L18
W17
V17
U17
T17
P17
N17
M17
L17

1

+2.5VSUS

+VCCP

A A

12

C289
.1U_4

12

C288

4.7U/10V_8

+2.5V

close to PIN B28,A28,A27

QUANTA

Title

Size Doc u m en t N u m be r Re v

5

4

3

2

Date: Sheet

COMPUTER

Alviso (Power)

ZL2 F

C

1

841Tuesday, De ce mber 21, 2004

of

1

+1.25VSUS

1

MD1
MD0 MD4 MD0

A A

CLK_SDRAM0<6>

CLK_SDRAM0#<6>

B B

R224 200
R228 200

C C

D D

+3V +3V

SM_DQS0
MD7

MD2
MD8 MD9

SM_DQS1
MD11 MD14

MD10 MD15

CLK_SDRAM0
CLK_SDRAM0#

MD16
MD17

SM_DQS2
MD19

MD18 MD22
MD24 MD28

MD25
SM_DQS3

MD26 MD30
MD31 MD27

CKE1 CKE3 CKE2
M_A_MA12 M_A_MA11

M_A_MA9 M_B_MA9 M_B_MA8
M_A_MA7
M_A_MA3

M_A_MA10
M_A_BA0

M_A_BMWEA#

SM_CS0#
M_A_MA13

MD33
MD32

SM_DQS4
MD34 MD38

MD35
MD40

MD41
SM_DQS5

MD46 MD43
MD47

MD53
MD48 MD52

SM_DQS6
MD50 MD54

MD51
MD56

MD60
SM_DQS7

MD59
MD58

SMBDT
SMBCK

R225 *10K_4
C408
.1U_4

1

3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99

101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

2

+1.25VSUS +1.25VSUS+1.25VSUS

SODIMM0 SODIMM1

CN27

VREF
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
CK0
VSS

DQ16
DQ17
VDD
DQS2
DQ18
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
DQ27
VDD
CB0
CB1
VSS
DQS8
CB2
VDD
CB3
DU
VSS
CK2
CK2
VDD
CKE1
DU
A12
A9
VSS
A7
A5
A3
A1
VDD
A10/AP
BA0
WE
S0
DU(A13)
VSS
DQ32
DQ33
VDD
DQS4
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ42
DQ43
VDD
VDD
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
VSS
DQ58
DQ59
VDD
SDA
SCL
VDD(SPD)
VDD(ID)

QTC_DDR_SODIMM_H4.0

CLOCK 0,1,2 CLOCK 3,4,5

VREF

VSS
DQ4

DQ5
VDD
DM0

DQ6

VSS

DQ7

DQ12

VDD

DQ13

DM1

VSS

DQ14
DQ15

VDD
VDD

VSS

VSS

DQ20
DQ21

VDD
DM2

DQ22

VSS

DQ23
DQ28

VDD

DQ29

DM3

VSS

DQ30
DQ31

VDD

CB4

CB5

VSS
DM8

CB6
VDD

CB7

DU/RESET

VSS

VSS
VDD
VDD

CKE0

DU/BA2

A11

A8

VSS

A6
A4
A2
A0

VDD

BA1

RAS

CAS

S1

DU

VSS

DQ36
DQ37

VDD
DM4

DQ38

VSS

DQ39
DQ44

VDD

DQ45

DM5

VSS

DQ46
DQ47

VDD

CK1

CK1

VSS

DQ52
DQ53

VDD
DM6

DQ54

VSS

DQ55
DQ60

VDD

PC2100 DDR SDRAM SO-DIMM (200P)

DQ61

DM7

VSS

DQ62
DQ63

VDD

SA0

SA1

SA2

DU

2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

MD5

SDM0
MD6

MD3

MD12MD13
SDM1

MD20
MD21

SDM2

MD29
SDM3

CKE0

M_A_MA8
M_A_MA6

M_A_MA4M_A_MA5
M_A_MA2
M_A_MA0 M_B_MA1

M_A_BA1
M_A_SRASA#
M_A_SCASA#
SM_CS1#

MD37
MD36

SDM4

MD39
MD45

MD44
SDM5

MD42
CLK_SDRAM1#

CLK_SDRAM1
MD49

SDM6

MD55
MD61

MD57
SDM7

MD62
MD63

SMbus address A0

3

CLK_SDRAM3<6>

CLK_SDRAM3#<6>

+2.5VSUS+2.5VSUS

CLK_SDRAM1# <6>

3

R252 200
R263 200

SMBDT<2>
SMBCK<2>

MD1

SM_DQS0
MD7

MD2
MD8

MD13
SM_DQS1

MD11
MD10

CLK_SDRAM3
CLK_SDRAM3#

MD16
MD17

SM_DQS2
MD19

MD18
MD24

MD25
SM_DQS3

MD26
MD31

M_B_MA12

M_B_MA7
M_B_MA3

M_B_MA10
M_B_BA0
M_B_BMWEA#

M_B_MA13

MD33
MD32

SM_DQS4
MD34

MD35
MD40

MD41
SM_DQS5

MD46
MD47

MD53
MD48

SM_DQS6
MD50

MD51
MD56

MD60
SM_DQS7

MD59
MD58

SMBDT

SMBCK

R251 *10K_4
C499
.1U_4

4

+2.5VSUS +2.5VSUS+2.5VSUS+2.5VSUS

CN29

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VDD

11

DQS0

13

DQ2

15

VSS

17

DQ3

19

DQ8

21

VDD

23

DQ9

25

DQS1

27

VSS

29

DQ10

31

DQ11

33

VDD

35

CK0

37

CK0

39

VSS

41

DQ16

43

DQ17

45

VDD

47

DQS2

49

DQ18

51

VSS

53

DQ19

55

DQ24

57

VDD

59

DQ25

61

DQS3

63

VSS

65

DQ26

67

DQ27

69

VDD

71

CB0

73

CB1

75

VSS

77

DQS8

79

CB2

81

VDD

83

CB3

85

DU

87

VSS

89

CK2

91

CK2

93

VDD

95

CKE1

97

DU

99

A12

101

A9

103

VSS

105

A7

107

A5

109

A3

111

A1

113

VDD

115

A10/AP

117

BA0

119

WE

121

S0

123

DU(A13)

125

VSS

127

DQ32

129

DQ33

131

VDD

133

DQS4

135

DQ34

137

VSS

139

DQ35

141

DQ40

143

VDD

145

DQ41

147

DQS5

149

VSS

151

DQ42

153

DQ43

155

VDD

157

VDD

159

VSS

161

VSS

163

DQ48

165

DQ49

167

VDD

169

DQS6

171

DQ50

173

VSS

175

DQ51

177

DQ56

179

VDD

181

DQ57

183

DQS7

185

VSS

187

DQ58

189

DQ59

191

VDD

193

SDA

195

SCL

197

VDD(SPD)

199

VDD(ID)

QTC_DDR_SODIMM_H9.2

CKE 2,3CKE 0,1

4

VREF

VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7

DQ12

VDD

DQ13

DM1

VSS
DQ14
DQ15

VDD

VDD

VSS

VSS
DQ20

DQ21

VDD

DM2
DQ22

VSS
DQ23
DQ28

VDD
DQ29

DM3

VSS
DQ30
DQ31

VDD

CB4

CB5

VSS

DM8

CB6

VDD

CB7

DU/RESET

VSS

VSS

VDD

VDD
CKE0

DU/BA2

A11

A8

VSS

A6
A4
A2

A0
VDD
BA1
RAS
CAS

S1

DU

VSS

DQ36
DQ37

VDD
DM4

DQ38

VSS

DQ39
DQ44

VDD

DQ45

DM5
VSS

DQ46
DQ47

VDD
CK1
CK1
VSS

DQ52
DQ53

VDD
DM6

DQ54

VSS

DQ55
DQ60

VDD

PC2100 DDR SDRAM SO-DIMM (200P)

DQ61

DM7
VSS

DQ62
DQ63

VDD
SA0
SA1
SA2

DU

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

SMbus address A1

5

MD5
MD4

SDM0
MD6

MD3
MD9

MD12
SDM1

MD14
MD15

MD20
MD21

SDM2
MD23MD23

MD22
MD28

MD29
SDM3

MD30
MD27

M_B_MA11

M_B_MA6
M_B_MA4M_B_MA5
M_B_MA2
M_B_MA0M_A_MA1

M_B_BA1
M_B_SRASA#
M_B_SCASA#
SM_CS3#SM_CS2#

MD37
MD36

SDM4
MD38

MD39
MD45

MD44
SDM5

MD43
MD42

CLK_SDRAM4#
CLK_SDRAM4

MD49
MD52

SDM6
MD54

MD55
MD61

MD57
SDM7

MD62
MD63

+3V

5

+2.5VSUS

C833
.1U_4

+2.5VSUS

C821
.1U_4

+2.5VSUS

C438
.1U_4

+2.5VSUS

C447
.1U_4

+2.5VSUS

C440
.1U_4

+1.25VSUS

C834
.1U_4

CLK_SDRAM4# <6>
CLK_SDRAM4 <6>CLK_SDRAM1 <6>

6

C823
.1U_4

C827
.1U_4

C441
.1U_4

C443
.1U_4

C819
.1U_4

C395
.1U_4

C822
.1U_4

C407
.1U_4

C432
.1U_4

C404
.1U_4

C820
.1U_4

C434
.1U_4

C830
.1U_4

C405
.1U_4

C439
.1U_4

C448
.1U_4

C442
.1U_4

C456
.1U_4

6

7

C825
.1U_4

C832
.1U_4

C435
.1U_4

C396
.1U_4

C402
.1U_4

+2.5VSUS

C424
150U/6.3V_7

M_A_MA[0..13]
M_A_BA0
M_A_BA1
M_A_SRASA#
M_A_SCASA#
M_A_BMWEA#

M_B_MA[0..13]
M_B_BA0
M_B_BA1
M_B_SRASA#
M_B_SCASA#
M_B_BMWEA#

MD[0..63]
SM_DQS[0..7]
SDM[0..7]

SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#

CKE0
CKE1
CKE2
CKE3

Size Document Number Re v

DDR SO-DIMM ( 200P )

Date: Sheet

7

C828

C829
.1U_4

C818
.1U_4

C436
.1U_4

C398
.1U_4

C412
.1U_4

C835
150U/6.3V_7

C826

.1U_4

.1U_4

C831

C433

.1U_4

.1U_4

C444

C437

.1U_4

.1U_4

C400

C399

.1U_4

.1U_4

C410

C411

.1U_4

.1U_4

M_A_MA[0..13] <7,10>

M_A_BA0 <7,10>

M_A_BA1 <7,10>
M_A_SRASA# <7,10>
M_A_SCASA# <7,10>

M_A_BMWEA# <7,10>

M_B_MA[0..13] <7,10>
M_B_BA0 <7,10>
M_B_BA1 <7,10>
M_B_SRASA# <7,10>
M_B_SCASA# <7,10>
M_B_BMWEA# <7,10>

MD[0..63] <7,10>
SM_DQS[0..7] <7,10>
SDM[0..7] <7,10>

SM_CS0# <6,10>
SM_CS1# <6,10>
SM_CS2# <6,10>
SM_CS3# <6,10>

CKE0 <6,10>
CKE1 <6,10>
CKE2 <6,10>
CKE3 <6,10>

PROJECT : ZL2

Quanta Computer Inc.

C406
.1U_4

C824
.1U_4

C445
.1U_4

C401
.1U_4

C403
.1U_4

8

941Tuesday, December 21, 2004

of

8

C397
.1U_4

C449
.1U_4

C446
.1U_4

C394
.1U_4

F

1

2

3

4

5

6

7

8

+1.25V

C385

C425

.1U_4

.1U_4

A A

B B

+1.25V

C384
.1U_4

C487
.1U_4

C486
.1U_4

C458
.1U_4

C377
.1U_4

C388
.1U_4

For terminal R-pack.

C416

C459

.1U_4

.1U_4

C417

C490

.1U_4

.1U_4

C468
.1U_4

C427
.1U_4

C485
.1U_4

C426
.1U_4

C383
.1U_4

C472
.1U_4

C461
.1U_4

C492
.1U_4

C467
.1U_4

C489
.1U_4

C462
.1U_4

C483
.1U_4

C479
.1U_4

C460
.1U_4

C478
.1U_4

C457
.1U_4

C415
.1U_4

C481
.1U_4

C378
.1U_4

C482
.1U_4

C466
.1U_4

C480
.1U_4

C484
.1U_4

C477
.1U_4

C463
.1U_4

C476
.1U_4

19 PCS

19 PCS

+1.25V

C491
.1U_4

C464
.1U_4

C465
.1U_4

C488
.1U_4

C494
150U/6.3V_7

+1.25V+1.25V +1.25V

R264 56_4
RN78
4P2R-S-56
RN77
4P2R-S-56

RN75
4P2R-S-56
RN74
4P2R-S-56

RN73
4P2R-S-56
RN72
4P2R-S-56

RN64
4P2R-S-56
RN86
4P2R-S-56

C C

RN63
4P2R-S-56
RN62
4P2R-S-56

RN61
4P2R-S-56
RN60
4P2R-S-56

RN81
4P2R-S-56
RN59
4P2R-S-56

RN58
4P2R-S-56
RN57
4P2R-S-56

MD58 MD62
MD59

MD56

MD53 MD55 M_B_MA8
MD47
MD46 MD50

MD41
MD34 MD44

MD26 MD39
MD31
MD27
MD30

MD24 MD28 M_A_MA9
MD19
MD18

MD17
MD16
MD11 MD5
MD10

MD9
MD12
MD8
MD13

MD2
MD7
MD0
MD1

2

1

4

3

2

1

4

3

2

1

4

3

2

1

4

3

2

1

4

3

2

1

4

3

2

1

4

3

2

1

4

3

2

1

4

3

2

1

4

3

2

1

4

3

2

1

4

3

2

1

4

3

2

1

4

3

2

1

4

3

2

1

4

3

2

1

4

3

2

1

4

3

2

1

4

3

2

1

4

3

2

1

4

3

2

1

4

3

2

1

4

3

2

1

4

3

2

1

4

3

2

1

4

3

2

1

4

3

2

1

4

3

2

1

4

3

2

1

4

3

2

1

4

3

2

1

4

3

RN100
4P2R-S-56

MD63
MD57

RN99

MD61

4P2R-S-56

MD54

RN98
4P2R-S-56

MD51

RN76
4P2R-S-56

RN71
4P2R-S-56

MD32 M_B_MA1
MD45

RN95
4P2R-S-56

RN94

MD38

4P2R-S-56

MD37

RN93
4P2R-S-56

MD36

MD29

RN85
4P2R-S-56

MD23

RN84
4P2R-S-56

MD22

MD3

RN80

MD6

4P2R-S-56
RN79
4P2R-S-56

MD4

MD20

RN83
4P2R-S-56

MD21
MD14

RN82

MD15

4P2R-S-56

MD43

RN96
4P2R-S-56

MD42

MD49

RN97

MD52

4P2R-S-56

SDM0

SDM1

SDM2

SDM3

SM_DQS0

SM_DQS1

SM_DQS2

SM_DQS3

MD[0..63]
SM_DQS[0..7]
SDM[0..7]
M_A_MA[0..13]

M_A_BA0
M_A_BA1
M_A_SRASA#
M_A_SCASA#
M_A_BMWEA#

SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#

CKE[0..3]

1 2

R265 56_4

1 2

R266 56_4

1 2

R267 56_4

1 2

R254 56_4

1 2

R255 56_4

1 2

R256 56_4

1 2

R257 56_4

1 2

R268 56_4

1 2

R269 56_4

1 2

R270 56_4

1 2

R271 56_4

1 2

R258 56_4

1 2

R259 56_4

1 2

R260 56_4

1 2

R261 56_4

1 2

MD[0..63] <7,9>
SM_DQS[0..7] <7,9>
SDM[0..7] <7,9>
M_A_MA[0..13] <7,9>

M_A_BA0 <7,9>

M_A_BA1 <7,9>
M_A_SRASA# <7,9>
M_A_SCASA# <7,9>

M_A_BMWEA# <7,9>

SM_CS0# <6,9>
SM_CS1# <6,9>
SM_CS2# <6,9>
SM_CS3# <6,9>

CKE[0..3] <6,9>

SDM4

SDM5

SDM6

SDM7

SM_DQS4

SM_DQS5

SM_DQS6

SM_DQS7

M_B_MA[0..13]
M_B_BA0
M_B_BA1
M_B_SRASA#
M_B_SCASA#
M_B_BMWEA#

M_B_MA[0..13] <7,9>
M_B_BA0 <7,9>
M_B_BA1 <7,9>
M_B_SRASA# <7,9>
M_B_SCASA# <7,9>
M_B_BMWEA# <7,9>

RN92
4P2R-S-56
RN69
4P2R-S-56

RN65
4P2R-S-56
RN88
4P2R-S-56

RN68
4P2R-S-56
RN67
4P2R-S-56

RN55
4P2R-S-56
RN18
4P2R-S-56

RN13
4P2R-S-56
RN15
4P2R-S-56

RN51
4P2R-S-56

RN87
4P2R-S-56

2

M_B_SCASA#
M_B_BA0
M_B_BMWEA#

M_B_MA12
CKE3 M_B_MA0MD48

M_B_MA6

M_B_MA10
M_B_MA3

M_B_MA9 M_A_MA10MD35

M_A_MA0
M_A_SCASA#
M_A_BA0
M_A_BMWEA#

CKE1
M_A_MA12
M_A_MA1
M_A_MA5

M_A_MA11
CKE0

CKE2
M_B_MA11 M_B_MA13

1
3
1
3

1
3
1
3

1
3
1
3

1
3
3
1

1
3
1
3

1
3

1
3

1

4

3

2

1

4

3

1

2

3

4

1

2

3

4

2

1

4

3
1

2

3

4

1

2

3

4

4

1

2

3

2

1

4

3
1

2

3

4

2

1

4

3

2

1

4

3

2
4
2
4

2
4
2
4

2
4
2
4

2
4
2
4

2
4
2
4

2
4

2
4

SM_CS3#
M_B_SRASA#
M_B_BA1
M_B_MA4MD60

M_B_MA2
M_B_MA5

M_B_MA7

M_A_SRASA#
SM_CS1#MD40 MD33
M_A_MA3

M_A_BA1
M_A_MA4
M_A_MA2

M_A_MA8
M_A_MA6MD25

M_A_MA7

SM_CS0#
M_A_MA13

SM_CS2#

RN91
4P2R-S-56
RN90
4P2R-S-56

RN89
4P2R-S-56
RN66
4P2R-S-56

RN56
4P2R-S-56
RN16
4P2R-S-56

RN54
4P2R-S-56
RN53
4P2R-S-56

RN52
4P2R-S-56
RN14
4P2R-S-56

RN17
4P2R-S-56

RN70
4P2R-S-56

D D

Size Document Number Re v

DDR TERMINATION

1

2

3

4

5

6

Date: Sheet

7

PROJECT : ZL2

Quanta Computer Inc.

10 41Tuesday, December 21, 2004

of

8

F

5

GMCHEXP_TXP[0..15]<6>

GMCHEXP_TXN[0..15]<6>

GMCHEXP_RXP[0..15]<6,15>
GMCHEXP_RXN[0..15]<6,15>

D D

GMCHEXP_RXP0
GMCHEXP_RXN0
GMCHEXP_RXP1
GMCHEXP_RXN1
GMCHEXP_RXP2
GMCHEXP_RXN2
GMCHEXP_RXP3

VGA1.2V

+3V

+3V

R74 *10K_4

GMCHEXP_RXN3
GMCHEXP_RXP4
GMCHEXP_RXN4
GMCHEXP_RXP5
GMCHEXP_RXN5
GMCHEXP_RXP6
GMCHEXP_RXN6
GMCHEXP_RXP7
GMCHEXP_RXN7
GMCHEXP_RXP8
GMCHEXP_RXN8
GMCHEXP_RXP9
GMCHEXP_RXN9
GMCHEXP_RXP10
GMCHEXP_RXN10
GMCHEXP_RXP11
GMCHEXP_RXN11
GMCHEXP_RXP12
GMCHEXP_RXN12
GMCHEXP_RXP13
GMCHEXP_RXN13
GMCHEXP_RXP14
GMCHEXP_RXN14
GMCHEXP_RXP15
GMCHEXP_RXN15

CLK_PCIE_VGA<2>
CLK_PCIE_VGA#<2>

C C

B B

C231 E@.1U_4
C234 E@.1U_4
C227 E@.1U_4
C224 E@.1U_4
C211 E@.1U_4
C205 E@.1U_4
C212 E@.1U_4
C207 E@.1U_4
C194 E@.1U_4
C188 E@.1U_4
C195 E@.1U_4
C191 E@.1U_4
C178 E@.1U_4
C171 E@.1U_4
C160 E@.1U_4
C154 E@.1U_4
C159 E@.1U_4
C151 E@.1U_4
C182 E@.1U_4
C172 E@.1U_4
C140 E@.1U_4
C131 E@.1U_4
C141 E@.1U_4
C135 E@.1U_4
C116 E@.1U_4
C112 E@.1U_4
C117 E@.1U_4
C113 E@.1U_4
C96 E@.1U_4

C98 E@.1U_4
C95 E@.1U_4

R101 E@150/F_4
R90 E@100/F_4
R89 E@10K/F
R77 *10K_4
R76 E@10K_4

PLTRST#<6,15,18,21,29,31,32,33>

R72
E@1K_4

F: NEW ADD 1K PULLDOWN

R120
*1M_4

XT_IN

XT_OUT

+3V

5

C258 E@22P_4

A A

E@TXC=27MHz

Y2

C242 E@22P_4

GMCHEXP_TXP0
GMCHEXP_TXN0
GMCHEXP_TXP1
GMCHEXP_TXN1
GMCHEXP_TXP2
GMCHEXP_TXN2
GMCHEXP_TXP3
GMCHEXP_TXN3
GMCHEXP_TXP4
GMCHEXP_TXN4
GMCHEXP_TXP5
GMCHEXP_TXN5
GMCHEXP_TXP6
GMCHEXP_TXN6
GMCHEXP_TXP7
GMCHEXP_TXN7
GMCHEXP_TXP8
GMCHEXP_TXN8
GMCHEXP_TXP9
GMCHEXP_TXN9
GMCHEXP_TXP10
GMCHEXP_TXN10
GMCHEXP_TXP11
GMCHEXP_TXN11
GMCHEXP_TXP12
GMCHEXP_TXN12
GMCHEXP_TXP13
GMCHEXP_TXN13
GMCHEXP_TXP14
GMCHEXP_TXN14
GMCHEXP_TXP15
GMCHEXP_TXN15

V_GMCHEXP_RXP0
V_GMCHEXP_RXN0
V_GMCHEXP_RXP1
V_GMCHEXP_RXN1
V_GMCHEXP_RXP2
V_GMCHEXP_RXN2
V_GMCHEXP_RXP3
V_GMCHEXP_RXN3
V_GMCHEXP_RXP4
V_GMCHEXP_RXN4
V_GMCHEXP_RXP5
V_GMCHEXP_RXN5
V_GMCHEXP_RXP6
V_GMCHEXP_RXN6
V_GMCHEXP_RXP7
V_GMCHEXP_RXN7
V_GMCHEXP_RXP8
V_GMCHEXP_RXN8
V_GMCHEXP_RXP9
V_GMCHEXP_RXN9
V_GMCHEXP_RXP10
V_GMCHEXP_RXN10
V_GMCHEXP_RXP11
V_GMCHEXP_RXN11
V_GMCHEXP_RXP12
V_GMCHEXP_RXN12
V_GMCHEXP_RXP13
V_GMCHEXP_RXN13
V_GMCHEXP_RXP14
V_GMCHEXP_RXN14
V_GMCHEXP_RXP15
V_GMCHEXP_RXN15

VPCIE_CR+
VPCIE_CR­VPCIE_CAL
VPCIE_TIN

B: POP R76

R127
E@715/F

T134
T142

R648

E@1K_4

T145

R121 *33_4
R119 *33_4

R122 E@1K_4
R57 E@0_4

R347 E@0_4

T39

R126
E@10K_4

R125 *10K_4

-VPCIE_RSTM
V_R2SET
EXT_TV_Y/G

EXT_TV_C/R
EXT_TV_COMP

VTHM_CLK
VTHM_DAT

27M_IN
27M_O

Z_V0101
Z_V0102
Z_V0103

Z_V0104

AH30
AG30
AG29
AF29
AE29
AE30
AD30
AD29
AC29
AB29
AB30
AA30
AA29

W29
W30

U29

R30
R29

N29
N30
M30
M29

AF26
AE26
AC25
AB25
AC27
AB27
AC26
AB26

W25
W27
W26

U25
U27
U26

N25
N27
N26

AF27
AE27

AC23
AB24
AB23

AE25
AD25

AD24
AH21
AK21

AJ22

AK22

AJ24

AK24
AG22

AG23

AJ23

AH24

AH28

AJ29

AH27

AF25
AH25

Y29

V30
V29

T29
T30

P29

L29
K29
K30

J30

Y25
Y27
Y26

T25
T27
T26

P25
P27
P26
L25

K25
L27
K27
L26
K26

E8
B6

U29A

PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N
PCIE_RX4P
PCIE_RX4N
PCIE_RX5P
PCIE_RX5N
PCIE_RX6P
PCIE_RX6N
PCIE_RX7P
PCIE_RX7N
PCIE_RX8P
PCIE_RX8N
PCIE_RX9P
PCIE_RX9N
PCIE_RX10P
PCIE_RX10N
PCIE_RX11P
PCIE_RX11N
PCIE_RX12P
PCIE_RX12N
PCIE_RX13P
PCIE_RX13N
PCIE_RX14P
PCIE_RX14N
PCIE_RX15P
PCIE_RX15N

PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N
PCIE_TX4P
PCIE_TX4N
PCIE_TX5P
PCIE_TX5N
PCIE_TX6P
PCIE_TX6N
PCIE_TX7P
PCIE_TX7N
PCIE_TX8P
PCIE_TX8N
PCIE_TX9P
PCIE_TX9N
PCIE_TX10P
PCIE_TX10N
PCIE_TX11P
PCIE_TX11N
PCIE_TX12P
PCIE_TX12N
PCIE_TX13P
PCIE_TX13N
PCIE_TX14P
PCIE_TX14N
PCIE_TX15P
PCIE_TX15N

PCIE_REFCLKP
PCIE_REFCLKN

PCIE_CALRP
PCIE_CALRN
PCIE_CALI

PCIE_TESTIN
PERSTb

PERSTb_MASK
R2SET
Y_G

C_R_PR
COMP_B_PB

H2SYNC
V2SYNC

DDC3CLK
DDC3DATA

SSIN
SSOUT

XTALIN
XTALOUT

TESTEN
TEST_YCLK
TEST_MCLK
PLLTEST

STEREOSYNC

E@M24/M22/M26

DAC2

SS PCI EXPRESSCLK

4

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14

GPIO_PWRCNTL

GPIO_MEMSSIN

DVOMODE

DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8

DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DPVDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

DVPCNTL_0

DVPCNTL_1

DVPCNTL_2

DVPCNTL_3

VREFG

TXOUT_L0N

TXOUT_L0P

TXOUT_L1N

TXOUT_L1P

TXOUT_L2N

TXOUT_L2P

TXOUT_L3N

TXOUT_L3P

TXCLK_LN

TXCLK_LP
TXOUT_U0N
TXOUT_U0P
TXOUT_U1N
TXOUT_U1P

LVDS DVO / EXT TMDS / GPIOTHERM TMDSDAC1

TXOUT_U2N
TXOUT_U2P
TXOUT_U3N
TXOUT_U3P

TXCLK_UN
TXCLK_UP

DIGON

BLON

TXCM

DDC2CLK

DDC2DATA

HSYNC
VSYNC

DDC1DATA

DDC1CLK

GPIO_AUXWIN

DPLUS

DMINUS

4

TX0M
TX0P
TX1M
TX1P
TX2M
TX2P

TXCP

HPD1

RSET

R
G
B

AJ5
AH5
AJ4
AK4
AH4
AF4
AJ3
AK3
AH3
AJ2
AH2
AH1
AG3
AG1
AG2
AF3
AF2

AE10
AH6

AJ6
AK6
AH7
AK7
AJ7
AH8
AJ8
AH9
AJ9
AK9
AH10
AE6
AG6
AF6
AE7
AF7
AE8
AG8
AF8
AE9
AF9
AG10
AF10

AJ10
AK10
AJ11
AH11

AG4

AH15
AH16
AJ16
AJ17
AJ18
AK18
AJ20
AJ21
AK19
AJ19
AG16
AG17
AF16
AF17
AE18
AE19
AF19
AF20
AG19
AG20

AE12
AG12

AK13
AJ13
AJ14
AJ15
AK15
AK16
AJ12
AK12

AE13
AE14

AF12
AK27

AJ27
AJ26

AJ25
AK25

AH26
AG25

AF24
AG24

AF11
AE11

T148
T143
T141
T33
T130
T136
T127
T129
T132

T37
T123
T126

DVOMODE

DVPDATA_16
DVPDATA_17

DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

DVPCNTL0

R374 E@10K_4

DVPCNTL1

R389 E@10K_4

DVPCNTL2

R401 E@10K_4

DVPCNTL3

R392 E@10K_4
R116 E@1K_4

VREFG

R115 E@1K_4
C236 E@.1U_4

EXT_TXLOUT0­EXT_TXLOUT0+
EXT_TXLOUT1­EXT_TXLOUT1+
EXT_TXLOUT2­EXT_TXLOUT2+

EXT_TXLCLKOUT­EXT_TXLCLKOUT+
EXT_TXUOUT0­EXT_TXUOUT0+
EXT_TXUOUT1­EXT_TXUOUT1+
EXT_TXUOUT2­EXT_TXUOUT2+

EXT_TXUCLKOUT­EXT_TXUCLKOUT+

DISP_ON
BLON

TMDS_TX0M
TMDS_TX0P
TMDS_TX1M
TMDS_TX1P
TMDS_TX2M
TMDS_TX2P
TMDS_TXCM
TMDS_TXCP

TMDS_DDCCLK
TMDS_DDCDATA

EXT_VGA_RED
EXT_VGA_GRN
EXT_VGA_BLU

EXT_HSYNC
EXT_VSYNC

V_RST

R112 E@499/F

EXT_DDCDAT
EXT_DDCCLK

VGATHRM+
VGATHRM-

B: POP R369

R369 E@10K_4
R367 *10K_4

ROMIDCFG0 <13>

VGA_PWR_SW

V_MEMSSIN

C245 E@10P_4

R102 E@0_4
T139

T150
T147
T138
T149
T137
T140
T131
T43
T42
T45
T41
T31
T40
T44
T36

DVPDATA_16 <13>
DVPDATA_17 <13>

EDIDDATA <16>

EDIDCLK <16>

DVPDATA_21 <13>
DVPDATA_22 <13>
DVPDATA_23 <13>

241
241
241

T135
T144

241

241
241
241

T38
T35

241

EXT_DDCDAT <17>
EXT_DDCCLK <17>

-VGA_ALERT

R113
*10K_4

3

+3V

R128 E@33_4

+3V

+3V

TXLOUT0-

RN101E@4P2R-S-0

TXLOUT0+

3

TXLOUT1-

RN102E@4P2R-S-0

TXLOUT1+

3

TXLOUT2-

RN103E@4P2R-S-0

TXLOUT2+

3

RN104E@4P2R-S-0

TXLCLKOUT­TXLCLKOUT+

3

TXUOUT0-

RN8E@4P2R-S-0

3

TXUOUT0+
TXUOUT1-

RN7E@4P2R-S-0

3

TXUOUT1+
TXUOUT2-

RN6E@4P2R-S-0

3

TXUOUT2+

TXUCLKOUT-

TXUCLKOUT+

3

RN5E@4P2R-S-0

DISP_ON <6,16>
BLON <6,16>

TMDS_DDCCLK <15,33>
TMDS_DDCDATA <15,33>

TMDS_HPD <15,33>
EXT_VGA_RED <17>

EXT_VGA_GRN <17>
EXT_VGA_BLU <17>

EXT_HSYNC <17>
EXT_VSYNC <17>

Close to pin ASIC

TMDS_TX0M
TMDS_TX0P

TMDS_TX1M
TMDS_TX1P

TMDS_TX2M
TMDS_TX2P

TMDS_TXCM
TMDS_TXCP

3

MEMORY CLOCK SPREAD
SPECTRUM

F: NEW ADD PWR PLAY

VGA_PWR_SW <38>

+3V

R440 E@47

VGATHRM-

10 mil trace /
10 mil space

VGATHRM+

R381 ED@330_4

R382 ED@330_4

R383 ED@330_4

R380 ED@330_4

Hi: 1.0V
Lo: 1.2V

XT_IN
1726_S0

1726_CKO

TXLOUT0- <6,16>
TXLOUT0+ <6,16>
TXLOUT1- <6,16>
TXLOUT1+ <6,16>
TXLOUT2- <6,16>
TXLOUT2+ <6,16>

TXLCLKOUT- <6,16>
TXLCLKOUT+ <6,16>
TXUOUT0- <6,16>
TXUOUT0+ <6,16>
TXUOUT1- <6,16>
TXUOUT1+ <6,16>
TXUOUT2- <6,16>
TXUOUT2+ <6,16>

TXUCLKOUT- <6,16>
TXUCLKOUT+ <6,16>

1
2
3

R93 ED@0_4

1 2

R94 ED@0_4

1 2

R95 ED@0_4

1 2

R96 ED@0_4

1 2

R97 ED@0_4

1 2

R98 ED@0_4

1 2

R91 ED@0_4

1 2

R92 ED@0_4

1 2

U13

XIN
VSS
SRS
SSCLK4REF

E@CY25819

MK1726-8

15 MIL

3V_THM1

C662
E@.1U_4

C638
E@2200P_4

2

+3V

R123
*10K_4

R131
*10K_4

XT_OUT

8

XOUT

VDD

MK1726_VDD

7

MK_PD

6

PD

MK_27M

5

R144 E@33_4

C297
E@10P_4

B: CHANGE FROM 27M_O TO 27M_IN

27M_IN

27M_O

R378E@0_4

R379*0_4

VGA27M

R398
E@71.5/F

PLACE CLOSE TO ASIC

EXT_TV_Y/G<16>

EXT_TV_C/R<16>

EXT_TV_COMP<16>

2

U32

VCC1/ALERT

3

DXN

2

DXP
GND5/THERM

E@MAX6657

TX0- <15,33>

TX0+ <15,33>

TX1- <15,33>

TX1+ <15,33>

TX2- <15,33>

TX2+ <15,33>
CLK- <15,33>

CLK+ <15,33>

6
7

SDA

8

SCLK

4

B: DEPOP WHEN NO DOCKING

Size Document Number Rev
Custom

Date: Sheet

MK_PD1726_S0

R146

*10K_4

1

SRS= 1 DOWN -2.5%
0 DOWN -1.8%
M DOWN -0.6%

27MOUT

VTHM_DAT
VTHM_CLK

R397E@121/F

VTHM_CLK
VTHM_DAT
DVPDATA_20

EXT_VGA_RED
EXT_VGA_GRN
EXT_VGA_BLU

EXT_TV_Y/G
EXT_TV_C/R
EXT_TV_COMP

+3V

R424 *0_4

C278
E@.1U_4

R385 E@150/F_4
R386 E@150/F_4
R384 E@150/F_4

+3V

R420
E@10K_4

2

PROJECT : ZL2

Quanta Computer Inc.

VGA HOST(ATI M24)

1

L38

+3V

E@0
C270
E@22U/10V_8

+3V

R88 E@6.8K/F
R86 E@6.8K/F
R100 E@10K_4

PLACE CLOSE TO ASIC

R375 E@150/F_4
R376 E@150/F_4
R377 E@150/F_4C94 E@.1U_4

R423
E@10K_4

Q36
E@2N7002

-VGA_ALERT

MEMVMODE0 <13>

3

1

R419
E@0_4

M26

of

11 41Tuesday, December 2 1, 2004

F

5

4

3

2

1

VDD1

C204

4

U29D

VDD15_AC11
VDD15_AC20

VDDR3_AD19
VDDR3_AD21
VDDR3_AC22

VDDR3_AC21
VDDR3_AC19

VDDR4_AC10
VDDR4_AD10

PCIE_VDDR_12_AG26

PCIE_VDDR_12_AK29

PCIE_VDDR_12_AJ30
PCIE_VDDR_12_AG28
PCIE_VDDR_12_AG27

PCIE_PVDD_12_N24
PCIE_PVDD_12_N23
PCIE_PVDD_12_P23

PCIE_PVDD_18_U23
PCIE_PVDD_18_T23
PCIE_PVDD_18_V23

PCIE_PVDD_18_W23

LVSSR_AF18
LVSSR_AH17
LVSSR_AG15
LVSSR_AG18

TXVSSR_AH14
TXVSSR_AG13
TXVSSR_AG14

I/O POWER

A2VSSN_AH20

A2VSSN_AG21

E@M24/M22/M26

C222
E@.1U_4

VDDC_AC13
VDDC_AD13
VDDC_AD15
VDDC_AC15
VDDC_AC17

VDD15_H20
VDD15_H11
VDD15_M23
VDD15_Y23

VDDR3_AD7

VDDR3_AC8

VDDR4_AG7
VDDR4_AD9
VDDR4_AC9

V_AVDD

VDD1

PVDD

MPVDD

AA1
AA4
AA7
AA8

A15
A21
A28

B30
D26
D23
D20
D17
D14
D11

E27

G10
G13
G15
G19
G22
G27
H22
H19
AD4

AE16
AE17
AF15
AE15

AH19
AH13

AF13
AF14

AF21
AE20

AF23
AH23

AE23
AE22

AK28

K23
K24

H10
H13
H15
H17

L23

F18

T7
R4
R1
N8
N7
M4

L8

N4

J8

J7

J4

J1

T8
V4
V7
V8

A3
A9

B1

D8
D5

F4
G7

N6

A7

VDDR1_T7
VDDR1_R4
VDDR1_R1
VDDR1_N8
VDDR1_N7
VDDR1_M4
VDDR1_L8
VDDR1_K23
VDDR1_K24
VDDR1_N4
VDDR1_J8
VDDR1_J7
VDDR1_J4
VDDR1_J1
VDDR1_H10
VDDR1_H13
VDDR1_H15
VDDR1_H17
VDDR1_T8
VDDR1_V4
VDDR1_V7
VDDR1_V8
VDDR1_AA1
VDDR1_AA4
VDDR1_AA7
VDDR1_AA8
VDDR1_A3
VDDR1_A9
VDDR1_A15
VDDR1_A21
VDDR1_A28
VDDR1_B1
VDDR1_B30
VDDR1_D26
VDDR1_D23
VDDR1_D20
VDDR1_D17
VDDR1_D14
VDDR1_D11
VDDR1_D8
VDDR1_D5
VDDR1_E27
VDDR1_F4
VDDR1_G7
VDDR1_G10
VDDR1_G13
VDDR1_G15
VDDR1_G19
VDDR1_G22
VDDR1_G27
VDDR1_H22
VDDR1_H19
VDDR1_AD4
VDDR1_L23

LVDDR_25_AE16
LVDDR_25_AE17
LVDDR_18_AF15
LVDDR_18_AE15

LPVDD
TPVDD

TXVDDR_AF13
TXVDDR_AF14

VDDRH0
VDDRH1

A2VDD_AF21
A2VDD_AE20

A2VDDQ
AVDD

VDD1DI
VDD2DI

PVDD
MPVDD

E@10U/10V_8

VGA_MEM_IO

C580

E@10U/10V_8

C581

E@1000P_4

C578

E@1000P_4

C589

E@1000P_4

C597

E@1000P_4

(350mA)

D D

VGA_MEM_IO

VGA_MEM_IO

(125mA)

C C

(30mA)

+1.8V

B B

+2.5V

L27

E@BLM18PG181SN1/0_6

E@10U/10V_8

+2.5V
+3V

E@10U/10V_8

+1.8V

L20 E@0_8
C161
E@10U/10V_8

12

C244

E@.1U_4

(80mA)

(28mA)

A A

(5.8mA)

C225

+1.8V

(6mA)

C220
E@.1U_4

C243

C585

E@10U/10V_8

C105
E@.1U_4

L22 E@0_8

E@10U/10V_8

L66 E@0_8

E@10U/10V_8

C219

VGA_MEM_IO

E@.1U_4

C214

+1.8V

E@.1U_4

+1.8V

+1.8V

5

C164

C119

E@.1U_4

E@.1U_4

C177

C156

E@.1U_4

E@.1U_4

L24 *0_8

D9

2 1

C202

E@RB500

E@.1U_4

C203
E@10U/10V_8

C186

C217
E@.1U_4

C233

C632

E@.1U_4

L16 E@0_8

C100
C142 E@.1U_4

L25 E@BLM18PG181SN1/0_6

(67mA)

+1.8V
+1.8V

(7mA)

C240 E@.1U_4

E@BLM18PG181SN1/0_6

L21 E@0_8

L68 E@0_8

C642

E@10U/10V_8

L13 E@0_8

C70

E@10U/10V_8

C110

C109

E@.1U_4

E@.1U_4

C106

C99

E@.1U_4

E@.1U_4

LVDR25

C216
E@.1U_4

LVDDR18

C218
E@.1U_4

LPVDD

C228
E@.1U_4

TXVDDR18

E@.1U_4

VDDRH

A2VDD25

V_A2VDDQ

12

C637 E@.1U_4

L67

12

C641
E@.1U_4

C71
E@.1U_4

VDD15_P8
VDD15_Y8

NC_D9
NC_D13
NC_D19
NC_D25

NC_E4

NC_T4
NC_AB4

AVSSQ

LPVSS

TPVSS

VSSRH0
VSSRH1

A2VSSQ

AVSSN

VSS1DI
VSS2DI

PVSS

MPVSS

C213
E@.1U_4

AC13
AD13
AD15
AC15
AC17

P8
Y8
AC11
AC20
H20
H11
M23
Y23

AD7
AD19
AD21
AC22
AC8
AC21
AC19

AG7
AD9
AC9
AC10
AD10

AG26
AK29
AJ30
AG28
AG27

N24
N23
P23

U23
T23
V23
W23

D9
D13
D19
D25
E4
T4
AB4

AD22

AF18
AH17
AG15
AG18

AH18
AH12

AH14
AG13
AG14

F19
M6

AH20
AG21

AF22
AH22

AE24
AE21

AJ28
A6

C173

C183

E@1000P_4

E@1000P_4

C107

C111
E@1000P_4

E@1000P_4

C215

C192

E@.1U_4

E@.1U_4

C206

C199

E@.1U_4

E@.1U_4

C635 E@.1U_4
C209 E@.1U_4
C634 E@.1U_4

VGA_PCIE12

C143 E@.1U_4
C157 E@.1U_4
C158 E@.1U_4

C168 E@.1U_4
C174 E@.1U_4
C185 E@.1U_4

T14
T19
T16
T18
T17
T25
T29

E@10U/10V_8

C121

E@1U/10V

E@1U/10V

C176
E@.1U_4

C187

C118

E@1000P_4

E@10U/10V_8

C189

C190

E@1000P_4

E@1000P_4

C201

C208

E@.1U_4

E@.1U_4

C200

C198

E@.1U_4

E@.1U_4

C636 E@10U/10V_8
C633 E@.1U_4

L18 E@0_8

C123

C122
E@1000P_4

+1.5V

C148
E@10U/10V_8

C196

(IO.POWER)

E@10U/10V_8

+3V

C197

(EXT.TMDS)

E@10U/10V_8

VGA1.2V

E@1000P_4

VGA1.2V

(PCIE 1.2V)

(40mA)

(2.7mA)

(2mA)

(1034mA)

(85mA)

(QUIET PCIE 1.2V)

(PCIE PLL/IO 1.8V)

+1.8V

(350mA)

B: ADD 220UF

VGA1.2V

+

VGA_MEM_IO

R118 E@0_1206

+2.5V

+1.8V

C919

R45 *0_1206

V_AVDD V_A2VDDQ

C920

E@10U/10V_8

E: Add bulk cap. for acer CRT

C129

C179
E@.1U_4

3

C221
E@1000P_4

C175
E@.1U_4

C146

E@1000P_4

C169
E@.1U_4

C126
E@1000P_4

C153
E@.1U_4

C124

E@1000P_4

C152
E@.1U_4

C166
E@1000P_4

C139
E@.1U_4

C914

E@220U/2.5V

C162

E@1000P_4

C138
E@.1U_4

+1.2V

+3V

(VGA CORE=1.2 OR 1.0V)

(6.2A)

+1.2V

+1.2V

C193

C127
E@1U/10V

E@1U/10V

+1.2V

C149

C155

E@.1U_4

E@.1U_4

A2

VSS_A2

A10

VSS_A10

A16

VSS_A16

A22

VSS_A22

A29

VSS_A29

C1

VSS_C1

C3

VSS_C3

C28

VSS_C28

C30

VSS_C30

D27

VSS_D27

D24

VSS_D24

D21

VSS_D21

D18

VSS_D18

D15

VSS_D15

D12

VSS_D12

D10

VSS_D10

D6

VSS_D6

D4

VSS_D4

F27

VSS_F27

G9

VSS_G9

G12

VSS_G12

G16

VSS_G16

G18

VSS_G18

G21

VSS_G21

G24

VSS_G24

H27

VSS_H27

H23

VSS_H23

H21

VSS_H21

H18

VSS_H18

H16

VSS_H16

H14

VSS_H14

H12

VSS_H12

H9

VSS_H9

H8

VSS_H8

H4

VSS_H4

J23

VSS_J23

J24

VSS_J24

AD12

VSS_AD12

AG5

VSS_AG5

AG9

VSS_AG9

AG11

VSS_AG11

R7

VSS_R7

P4

VSS_P4

M7

VSS_M7

M8

VSS_M8

L4

VSS_L4

K1

VSS_K1

K7

VSS_K7

K8

VSS_K8

R8

VSS_R8

T1

VSS_T1

P17

VDDC_P17

P18

VDDC_P18

P19

VDDC_P19

U12

VDDC_U12

U13

VDDC_U13

U14

VDDC_U14

U17

VDDC_U17

U18

VDDC_U18

U19

VDDC_U19

V19

VDDC_V19

V18

VDDC_V18

V17

VDDC_V17

V14

VDDC_V14

V13

VDDC_V13

V12

VDDC_V12

N18

VDDC_N18

N17

VDDC_N17

N14

VDDC_N14

W17

VDDC_W17

W18

VDDC_W18

W12

VDDC_W12

W13

VDDC_W13

W14

VDDC_W14

N13

VDDC_N13

N19

VDDC_N19

M19

VDDC_M19

M18

VDDC_M18

M12

VDDC_M12

N12

VDDC_N12

M13

VDDC_M13

M14

VDDC_M14

P12

VDDC_P12

P13

VDDC_P13

P14

VDDC_P14

M17

VDDC_M17

W19

VDDC_W19

Size Document Number Rev
Custom

2

Date: Sheet

U29E

PCIE_VSS_K28

PCIE_VSS_L28
PCIE_VSS_M27
PCIE_VSS_M26
PCIE_VSS_M24

CORE GND

PCIE_VSS_M25
PCIE_VSS_M28

PCIE_VSS_P28
PCIE_VSS_N28
PCIE_VSS_R25
PCIE_VSS_R23
PCIE_VSS_R24
PCIE_VSS_R26
PCIE_VSS_R27
PCIE_VSS_R28

PCIE_VSS_T28

PCIE_VSS_T24

PCIE_VSS_U28
PCIE_VSS_V24
PCIE_VSS_V26
PCIE_VSS_V27
PCIE_VSS_V25
PCIE_VSS_V28

PCIE_VSS_Y28
PCIE_VSS_W24
PCIE_VSS_W28

PCIE_VSS_AA26
PCIE_VSS_AA27

PCIE_VSS_A23

PCIE_VSS_AA24
PCIE_VSS_AA25
PCIE_VSS_AA28

PCIE_VSS_AB28
PCIE_VSS_AC28
PCIE_VSS_AD28
PCIE_VSS_AD26
PCIE_VSS_AD27

PCIE_VSS_AE28

PCIE_VSS_AF28
PCIE_VSS_AH29

CENTER ARRAY

VDDC1_W16
VDDC1_M15

VDDC1_R19
VDDC1_T12

E@M24/M22/M26

VSS_U4

VSS_U8
VSS_W7
VSS_W8

VSS_Y4

VSS_AB8
VSS_AB7
VSS_AB1

VSS_ AC4
VSS_AC12
VSS_AC14
VSS_AD16
VSS_AC16
VSS_AC18
VSS_AD18

VSS_AK2

VSS_AJ1

VSS_M16

VSS_N16
VSS_N15
VSS_P15
VSS_P16
VSS_R18
VSS_R17
VSS_R16
VSS_R15
VSS_R14
VSS_R13
VSS_R12
VSS_T13
VSS_T14
VSS_T15

VSS_W15

VSS_V16
VSS_V15
VSS_U15
VSS_U16
VSS_T19
VSS_T18
VSS_T17
VSS_T16

U4
U8
W7
W8
Y4
AB8
AB7
AB1
AC4
AC12
AC14
AD16
AC16
AC18
AD18
AK2
AJ1

K28
L28
M27
M26
M24
M25
M28
P28
N28
R25
R23
R24
R26
R27
R28
T28
T24
U28
V24
V26
V27
V25
V28
Y28
W24
W28
AA26
AA27
AA23
AA24
AA25
AA28
AB28
AC28
AD28
AD26
AD27
AE28
AF28
AH29

M16
N16
N15
P15
P16
R18
R17
R16
R15
R14
R13
R12
T13
T14
T15
W15
V16
V15
U15
U16
T19
T18
T17
T16

W16
M15
R19
T12

VGA_VDDC

PROJECT : ZL2

Quanta Computer Inc.

ATI M24(POWER)

1

L19 E@0_8

+1.2V

C163 E@1U/10V
C165 E@1U/10V
C145 E@1U/10V
C125 E@1U/10V

of

12 41Tuesday, December 2 1, 2004

F

5

4

3

2

1

R54
E@100

MDB[0..63]<14>

C570
E@.1U_4

R342

E@100

R341
E@100

MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8

MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63

AA2
AA6
AA5
AB6

AB5
AD6
AD5

AE5

AE4

AB2

AB3
AC2
AC3
AD3

AE1

AE2

AE3

VDDR1

1.8V

2.5V

D7

F7

E7
G6
G5

F5

E5
C4

B5
C5

A4

B4
C2
D3
D1
D2
G4
H6
H5

J6
K5
K4
L6
L5

G2

F3

H2

E2
F2

J3
F1

H3
U6
U5
U3

V6

W5
W4

Y6
Y5

U2

V2
V1
V3

W3

Y2
Y3

U29C

DQB0
DQB1
DQB2
DQB3
DQB4
DQB5
DQB6
DQB7
DQB8
DQB9
DQB10
DQB11
DQB12
DQB13
DQB14
DQB15
DQB16
DQB17
DQB18
DQB19
DQB20
DQB21
DQB22
DQB23
DQB24
DQB25
DQB26
DQB27
DQB28
DQB29
DQB30
DQB31
DQB32
DQB33
DQB34
DQB35
DQB36
DQB37
DQB38
DQB39
DQB40
DQB41
DQB42
DQB43
DQB44
DQB45
DQB46
DQB47
DQB48
DQB49
DQB50
DQB51
DQB52
DQB53
DQB54
DQB55
DQB56
DQB57
DQB58
DQB59
DQB60
DQB61
DQB62
DQB63

E@M24/M22/M26

MEMVMODE_0

GND

+VDDC_CT

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8

MAB9
MAB10
MAB11
MAB12
MAB13
MAB14

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

QSB0

QSB1

QSB2

QSB3

QSB4

QSB5

QSB6

QSB7
RASB#
CASB#

WEB#
CSB0#
CSB1#

MEMORY INTERFACE B

CLKB0#

CLKB1#

DIMB_0
DIMB_1

ROMCS#

MEMVMODE_0
MEMVMODE_1

MEMTEST

MEMVMODE_1

+VDDC_CT

CKEB
CLKB0

CLKB1

M1
M3
L3
L2
M2
M5
P6
N3
K2
K3
J2
P5
P3
P2

E6
B2
J5
G3
W6
W2
AC6
AD2

F6
B3
K6
G1
V5
W1
AC5
AD1

R2
T5
T6
R5
R6
R3
N1

N2
T2

T3

E3
AA3

AF5
C6

C7
C8

R53
E@47

MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13

-DQMB0

-DQMB1

-DQMB2

-DQMB3

-DQMB4

-DQMB5

-DQMB6

-DQMB7
QSB0

QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7

-RASB

-CASB

-WEB

-CSB0

-CSB1

CKEB

CLKB0

-CLKB0
CLKB1

-CLKB1

MEMVMODE0
MEMVMODE1

MBMTEST

MAB0

N5

GND

R355 E@10K_4

R353 E@10
R354 E@10

R356 E@10
R357 E@10

DIMB0
DIMB1

R349
E@4.7K_4

MDA[0..63]<14>

MDA0

H28

G26
G30
D29
D28
E28
E29
G29
G28

G25
E26
E24
E23

D22
B29
C29
C25
C27
B28
B25
C26
B26

E17
D16

E15
E14
C17

B18
B17
B15
C13
B14
C14
C16
A13
A12
C12
B12
C10

B10
E13
E12
E10

H29
J28
J29
J26
H25
H26

F28
F26
F25
F23

F17

F16
F14
F13

F12
F11

DQA0
DQA1
DQA2
DQA3
DQA4
DQA5
DQA6
DQA7
DQA8
DQA9
DQA10
DQA11
DQA12
DQA13
DQA14
DQA15
DQA16
DQA17
DQA18
DQA19
DQA20
DQA21
DQA22
DQA23
DQA24
DQA25
DQA26
DQA27
DQA28
DQA29
DQA30
DQA31
DQA32
DQA33
DQA34
DQA35
DQA36
DQA37
DQA38
DQA39
DQA40
DQA41
DQA42
DQA43
DQA44
DQA45
DQA46
DQA47
DQA48
DQA49
DQA50
DQA51
DQA52

C9

DQA53

B9

DQA54
DQA55
DQA56
DQA57
DQA58
DQA59
DQA60

E9

DQA61

F9

DQA62

F8

DQA63

MDA1
MDA2
MDA3
MDA4
MDA5
MDA6

D D

C C

B B

MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16

MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46

MDA47

MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

U29B

MEMORY INTERFACE A

E@M24/M22/M26

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8

MAA9
MAA10
MAA11
MAA12
MAA13
MAA14

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

QSA0

QSA1

QSA2

QSA3

QSA4

QSA5

QSA6

QSA7
RASA#
CASA#

WEA#
CSA0#
CSA1#

CKEA

CLKA0

CLKA0#

CLKA1

CLKA1#

MVREFD
MVREFS

DIMA_0
DIMA_1

E22
B22
B23
B24
C23
C22
F22
F21
C21
A24
C24
A25
E21
B20
C19

J25
F29
E25
A27
F15
C15
C11
E11

J27
F30
F24
B27
E16
B16
B11
F10

A19
E18
E19
E20
F20
B19

B21
C20

C18
A18

B7
B8

D30
B13

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

-DQMA0

-DQMA1MDA17

-DQMA2

-DQMA3

-DQMA4

-DQMA5

-DQMA6

-DQMA7
QSA0

QSA1
QSA2
QSA3
QSA4
QSA5
QSA6
QSA7

-RASA

-CASA

-WEA

-CSA0

-CSA1
CKEA

R348 E@10K_4

CLKA0

R346 E@10

-CLKA0

R345 E@10

CLKA1

R343 E@10

-CLKA1

R344 E@10

DIMA0
DIMA1

MVREFD

MVREFS

-RASA <14>

-CASA <14>

-WEA <14>

-CSA0 <14>

-CSA1 <14>

MAA[0..13] <14>

-DQMA[0..7] <14>

QSA[0..7] <14>

CKEA <14>

M_CLKA0 <14>

-M_CLKA0 <14>
M_CLKA1 <14>

-M_CLKA1 <14>

T112

C72

T13

E@.1U_4

VGA_MEM_IO VGA_MEM_IO

R51
E@100

Place close to ASIC

MAB[0..13] <14>

-DQMB[0..7] <14>

QSB[0..7] <14>

-RASB <14>

-CASB <14>

-WEB <14>

-CSB0 <14>

-CSB1 <14>

M_CLKB0 <14>

-M_CLKB0 <14>
M_CLKB1 <14>

-M_CLKB1 <14>

T21

T27

R351 E@4.7K_4

R350 *4.7K_4

R352
*4.7K_4

CKEB <14>

MEMVMODE0 <11>

+1.8V

DVPDATA_16
DVPDATA_17
DVPDATA_21
DVPDATA_22
DVPDATA_23

R391
*10K_4

R400
E@10K_4

R107
*10K_4

R105
E@10K_4

ROMIDCFG0

2

STRAPS PIN

STRAPS PIN

GPIO_0

0: use reference voltage from Bandgap

GPIO_6

1: use refer e n c e v o l t a g e f ro m resistor divider

PCI-Express Current Calibration Bandgap Backup

GPIO_1

PCI-Express PLL Calibration force enable

0: Disable PLL force calibration

GPIO_8

1: Enable PLL force calibration

00: PCI Expr es s 1.0 mode

GPIO_(3,2)

A A

01: RESERVED
10: PCI Express 1.0 mode

GPIO(9,13:11)

INT P/D

11: RESERVED
Turn off PCI- Express impedance / strength calibration

GPIO_4

GPIO_5

0: enable

1: disable
Bypass PCI-Express PLL

5

DVPDATA_21~23

MEM TYPE

4

PCI-Express transmitter current compensation

0: Normal

1: Inject extra current for output buffer switching
Strap to set t h e d e b u g m u x es to bting out DEBUG signals

even if regis t e r s a r e i n a c cessible
ROMIDCFG

0x0x: No ROM, CHG_ID=0

0x1x: No Rom, CHG_ID=1
1000: Parallel ROM, Chip ID'S from ROM
1000: Parallel ROM, Chip ID'S from ROM

DVPDATA_21: 0=4Mx32 1=8Mx32
DVPDATA_22: 0=128M 1=64M
DVPDATA_23: 0=Hynix 1=Samsung

3

FOR M26P ONLY
0: 128M
1: 256M

ROMIDCFG0 <11>

+3V

R406
*10K_4

DVPDATA_23

R410
E@10K_4

R390
E@10K_4

DVPDATA_22 DVPDATA_21 DVPDATA_17 DVPDATA_16ROMIDCFG0

R399
*10K_4

C: FOR HYNIX MEMORY

Size Document Number Rev
Custom

Date: Sheet

DVPDATA_16 <11>
DVPDATA_17 <11>
DVPDATA_21 <11>
DVPDATA_22 <11>
DVPDATA_23 <11>

R372
*10K_4

R387
E@10K_4

R373
*10K_4

R388
E@10K_4

PROJECT :ZL2

Quanta Computer Inc.

ATI M24 MEM/STRAPS PIN

1

of

13 41Tuesday, December 2 1, 2004

F