Quanta ZK2 DA0ZK2MB6E0 Schematic
5
4
3
2
1
BOM MARK
I@: INT VGA
E@: STUFF FOR EXT VGA
ND@: STUFF FOR NON-DOCK
D@: DOCK
SP@: SPECIAL FOR EXT/INT VGA
D D
CLOCK GENERATOR
ICS: ICS9LPRS365BGLFT
SELGO: SLG8SP512K05
ZK2 SYSTEM BLOCK DIAGRAM
X'TAL
14.318MHz
Penryn 479
uFCPGA
P2
P3, P4
Thermal Sensor
(NS LM95245) (G991)
P3
Fan Driver
P30
DDR PWR
TPS5116
THERMAL
PROTECTION
2.5V/ 1.5V PWR
DISCHARGER
POWER TREE
CHARGER
P36
3/5V SYS PWR
P37
CPU CORE PWR
P38
+1.05V
P39
ISL6251
ISL6237
ISL6262A
RT8202
P32
P33
P34
P35
FSB
667/800/1067 Mhz
PCIE
MXM (n-Vidia)
NB9M-GS
VRAM 512MB
DDRII
SO-DIMM 0
SO-DIMM 1
C C
P16
MP-Stage
31ZK2MB0000: ZK2 MB ASSY(GM/UMA)ASSY W/O CPU
31ZK2MB0010: ZK2 MB ASSY(PM/MXM)ASSY W/O CPU
31ZK2MB0020: ZK2 MB ASSY(PM/MXM) W/O CPU/E-SATA
eSATA Conn.
USB1
USB Port x 3
B B
A A
USB0, 4, 7
Bluetooth
USB5
CCD
USB11
FingerPrint
USB9
Wire Docking
USB10
Audio Amplifier
Speaker
P25
S/PDIF
5
P29
P29
P21
P18
P30
P30
P24,P25
P25
eSATA Buffer
(PI2EQX3021)
Sub-Amplifier
(MAX9736B)
SUBWOOFER
HDD (SATA) *2
ODD (SATA)
P29
Audio CODEC
(ALC888S)
P25
Line in
P25
Dual Channel DDR2
667/800 MHz
P23
P23
P24
MIC Jack
P25
4
MDC 1.5
P25
SATA0
SATA4
SATA1
SATA5
USB 2.0
Azalia
HDCP ROM
(Option)
P24
Int. D-MIC
P18, P24
(GM45/ PM45/ GL40)
NB
Cantiga
P5, P6, P7, P8, P9, P10, P11
X4 DMI interface
SB
ICH9M
P12,P13,P14,P15
SPI
P13
RJ11
WIRE CONN.
EC (WPC775LDG)
SPI ROM
Touch Pad
K/B COON.
LPC
P31
P30
P30
3
P31
X'TAL
32.768KHz
LVDS
RGB
PCI-Express
USB8
USB2
X'TAL
32.768KHz
MMB
P28
CIR
P31
Media
Cardreader
(RTS5158E)
Card Reader
Connector
P17
P27
P27
EXT_LVDS
EXT_CRT
EXT_DVI
INT_LVDS
INT_CRT
PCIE-6
ATHEROS
Giga-LAN
(AR8121)
LAN SWITCH
(PI3L500)
Transformer
RJ45
2
CRT
P18
SWITCH
CIRCUIT
LVDS
P18
HDMI switch
(PS8122)
P19
PCIE-1
PCIE-2&4
X'TAL
25MHz
P20
P21 P30
P21
P21
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
New Card
USB6
Mini Card
WLAN / TV
USB2 & 3
HDMI
DOCKING/DVI
USB6
P26
P22
USB2 & 3
DOCK/LAN
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
Block Diagram
Block Diagram
Block Diagram
DA0ZK2MB6D0
DA0ZK2MB6C0
DA0ZK2MB6B0
DA0ZK2MB6A0
ZK2
ZK2
ZK2
1
P18
P19
P19
3B
3B
139Friday, June 27, 2008
139Friday, June 27, 2008
139Friday, June 27, 2008
3B
of
of
of
5
4
3
2
1
Clock Generator
U30
FSA
U30
2
VDD_PCI
9
VDD_48
16
VDD_PLL3
39
VDD_SRC
55
VDD_CPU
61
VDD_REF
60
XTAL_IN
59
XTAL_OUT
1
PCI_0/CLKREQ_A#
3
PCI_1/CLKREQ_B#
4
PCI_2
5
PCI_3
6
^PCI_4/LCDCLK_SEL
7
PCIF_5/ITP_EN
10
USB_48MHz/FS_A
57
FS_B/TEST_MODE
62
REF/FS_C/TEST_SEL
13
SRC_0/DOT_96
14
SRC_0#/DOT_96#
64
SCL
63
SDA
8
VSS_PCI
11
VSS_48
15
VSS_I/O
19
VSS_PLL3
23
VSS_SRC_1
29
VSS_SRC_2
42
VSS_SRC_3
52
VSS_CPU
58
VSS_REF
SLG8SP512
SLG8SP512
VDD_I/O
VDD_PLL3_I/O
VDD_SRC_I/O_1
VDD_SRC_I/O_2
VDD_SRC_I/O_3
VDD_CPU_I/O
CPU_STOP#
PCI_STOP#
CKPWRGD/PD#
CPU_0
CPU_0#
CPU_1_MCH
CPU_1_MCH#
SRC_8/CPU_ITP
SRC_8#/CPU_ITP#
LCDCLK/27M
LCDCLK#/27M_SS
SRC_2
SRC_2#
SRC_3/CLKREQ_C#
SRC_3#/CLKREQ_D#
SRC_7/CLKREQ_F#
SRC_7#/CLKREQ_E#
SRC_11/CLKREQ_H#
SRC_11#/CLKREQ_G#
SRC_4
SRC_4#
SRC_6
SRC_6#
SRC_9
SRC_9#
SRC_10
SRC_10#
12
20
26
36
45
49
37
38
56
54
53
51
50
47
46
48
NC
17
18
21
22
24
25
27
28
41
40
44
43
30
31
34
35
33
32
C486
C486
10u_6
10u_6
+1V05_CLK
C470
C470
.1u_4
.1u_4
C499
C499
.1u_4
.1u_4
PM_STPCPU# (14)
PM_STPPCI# (14)
CK_PWRGD (14)
CLK_CPU_BCLK (3)
CLK_CPU_BCLK# (3)
CLK_MCH_BCLK (5)
CLK_MCH_BCLK# (5)
CLK_DREFSSCLK (6)
CLK_DREFSSCLK# (6)
CLK_PCIE_SATA (12)
CLK_PCIE_SATA# (12)
CLK_PCIE_LAN (20)
CLK_PCIE_LAN# (20)
CLK_PCIE_NEW_C (26)
CLK_PCIE_NEW_C# (26)
CLK_PCIE_ICH (13)
CLK_PCIE_ICH# (13)
CLK_MXM (17)
CLK_MXM# (17)
CLK_PCIE_MINI1 (22)
CLK_PCIE_MINI1# (22)
CLK_PCIE_3GPLL (6)
CLK_PCIE_3GPLL# (6)
CLK_PCIE_TV (22)
CLK_PCIE_TV# (22)
C471
C471
*.1u_4
*.1u_4
L39 BKP1608HS181-TL39 BKP1608HS181-T
+3V
C472
C474
C474
.1u_4
.1u_4
D D
PCLK_DEBUG(22)
PCLK_591(31)
PCLK_ICH(13)
C C
R511 33_4R511 33_4
R523 33_4R523 33_4
R519 33_4R519 33_4
PDAT_SMB(14,16,19,20,22,26)
PCLK_SMB(14,16,19,20,22,26)
Q35
Q35
RHU002N06
RHU002N06
Q33
Q33
RHU002N06
RHU002N06
C475
C475
*.1u_4
*.1u_4
C501
C501
*10p_4
*10p_4
+3V
2
3
+3V
2
3
C472
.1u_4
.1u_4
PCLK_MINI_R
PCLK_591_R
PCLK_ICH_R
C504
C504
C505
C505
*10p_4
*10p_4
*10p_4
*10p_4
R483
R483
10K_4
10K_4
1
1
C492
C492
*.1u_4
*.1u_4
C484 33p/50V_4C484 33p/50V_4
C488 33p/50V_4C488 33p/50V_4
SATACLKREQ#(14)
NEW_CLKREQ#(26)
CLKUSB_48(14)
CLK_Card48(27)
14M_ICH(14)
CLK_DREFCLK(6)
CLK_DREFCLK#(6)
R484
R484
10K_4
10K_4
CGDAT_SMB
CGCLK_SMB
+3V_CLK
C498
C498
.1u_4
.1u_4
Y5
Y5
14.318MHz
14.318MHz
R489 475/F_4R489 475/F_4
R496 475/F_4R496 475/F_4
CPU_BSEL0
MCH_BSEL1
CPU_BSEL2
C496
C496
.1u_4
.1u_4
T85T85
R521 2.2K_4R521 2.2K_4
R520 22_4R520 22_4
R522 22_4R522 22_4
R478 10K_4R478 10K_4
R479 33_4R479 33_4
C473 *30p/50V_4C473 *30p/50V_4
C491
C491
10u_6
10u_6
CG_XIN
CG_XOUT
SATACLKREQ#_R
NEW_CLKREQ#_R
PCLK_MINI_R
PCLK_591_R
PCLK_PCM_R
PCLK_ICH_R
CGCLK_SMB
CGDAT_SMB
FSC
CLK VDD power range 1.05V~3.3V
L38 BKP1608HS181-TL38 BKP1608HS181-T
C500
C469
C469
.1u_4
.1u_4
C497
C497
.1u_4
.1u_4
C500
.1u_4
.1u_4
Pin 56 : It acts as a
level sensitive strobe
to latch the FS pins
and other multiplexed
inputs.
+1.05V
CPU Clock select
B B
BSEL Frequency Select Table
Pin 10/57/62 : For Pin CPU frequency selection
CPU_BSEL0(3)
CPU_BSEL1(3)
CPU_BSEL2(3)
A A
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
R524 0_4R524 0_4
R480 0_4R480 0_4
R476 0_4R476 0_4
MCH_BSEL0 (6)
MCH_BSEL1 (6)
MCH_BSEL2 (6)
FSC FSB FSA Frequency
0
0
0
1
0
1
0
1
1
1
1
0
1
0
0
1
1
0
01
1
1
0
266Mhz0
133Mhz
166Mhz
200Mhz
400Mhz
Reserved
100Mhz
333Mhz
CLOCK GENERATOR
5
4
3
Strap table
+3V
R490 10K_4R490 10K_4
R497 10K_4R497 10K_4
R512 10K_4R512 10K_4
PCLK_PCM_R
SATACLKREQ#_R
NEW_CLKREQ#_R
PCLK_MINI_R
R508 10K_4R508 10K_4
Pin 6 : For Pin 13/14 and 17/18 selection
0 = LCDCLK & DOT96 for internal graphic controller support
1 = 27M & 27M_SS &SRC_0 for external graphic controller support
PCLK_ICH_R
R518 10K_4R518 10K_4
Pin 7 : For Pin 46/47 selection
1 = CPU_ITP
0 = SRC_8
2
Control CPU_0 & SRC_2
Control CPU_1 & SRC_4
R513 *10K_4R513 *10K_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Reserve overclocking
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
CLOCK GENERATOR
CLOCK GENERATOR
CLOCK GENERATOR
ZK2
ZK2
ZK2
239Wednesday, July 09, 2008
239Wednesday, July 09, 2008
239Wednesday, July 09, 2008
of
of
1
of
3B
3B
3B
5
4
3
2
1
H_A#[3..16](5)
D D
H_ADSTB#0(5)
H_REQ#[0..4](5)
H_A#[17..35](5)
C C
H_ADSTB#1(5)
H_A20M#(12)
H_FERR#(12)
H_IGNNE#(12)
H_STPCLK#(12)
H_INTR(12)
H_NMI(12)
H_SMI#(12)
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
AA4
AB2
AA3
D22
W6
W2
W5
W3
J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1
K3
H2
K2
J3
L1
Y2
U5
R3
U4
Y5
U1
R4
T5
T3
Y4
U2
V4
V1
A6
A5
C4
D5
C6
B4
A3
M4
N5
T2
V3
B2
D2
D3
F6
U25A
U25A
A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#
A20M#
FERR#
IGNNE#
STPCLK#
LINT0
LINT1
SMI#
RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]
ADDR GROUP_0
ADDR GROUP_0
ADDR GROUP_1
ADDR GROUP_1
ICH
ICH
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
CONTROL
CONTROL
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
HIT#
HITM#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDO
TMS
TRST#
DBR#
XDP/ITP SIGNALS
XDP/ITP SIGNALS
THERMAL
THERMAL
PROCHOT#
THERMDA
THERMDC
THERMTRIP#
H CLK
H CLK
BCLK[0]
BCLK[1]
RESERVED
RESERVED
H1
E2
G5
H5
F21
E1
F1
H_IERR#
D20
B3
H4
C1
F3
F4
G3
G2
G6
E4
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
TDI
AB3
AB5
AB6
C20
D21
A24
B25
C7
A22
A21
R180 56_4R180 56_4
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
SYS_RST#
H_PROCHOT#_D
H_THERMDA
H_THERMDC
PM_THRMTRIP#
T11T11
T14T14
T13T13
T10T10
T12T12
H_ADS# (5)
H_BNR# (5)
H_BPRI# (5)
H_DEFER# (5)
H_DRDY# (5)
H_DBSY# (5)
H_BREQ# (5)
+1.05V
H_INIT# (12)
H_LOCK# (5)
H_CPURST# (5)
H_RS#0 (5)
H_RS#1 (5)
H_RS#2 (5)
H_TRDY# (5)
H_HIT# (5)
H_HITM# (5)
Connect it to CPU DBR# is for ITP debug port
or CPU interposer (like ICE) to reset the system
SYS_RST# (14)
CLK_CPU_BCLK (2)
CLK_CPU_BCLK# (2)
+1.05V
R214
R214
1K/F_4
1K/F_4
R217
R217
2K/F_4
2K/F_4
Layout note:
H_GTLREF: Zo=55 ohm
L<0.5", 2/3*VCCP+-2%
H_D#[0..15](5)
H_DSTBN#0(5)
H_DSTBP#0(5)
H_DINV#0(5)
H_D#[16..31](5)
H_DSTBN#1(5)
H_DSTBP#1(5)
H_DINV#1(5)
CPU_BSEL0(2)
CPU_BSEL1(2)
CPU_BSEL2(2)
H_D#[0..15]
H_D#[16..31]
T51T51
T52T52
T55T55
T41T41
T15T15
T82T82
T17T17
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_GTLREF
CPU_TEST1
CPU_TEST2
CPU_TEST3
CPU_TEST4
CPU_TEST5
CPU_TEST6
CPU_TEST7
AD26
AF26
E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
H22
F26
K22
H23
H26
H25
N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24
C23
D25
C24
AF1
A26
B22
B23
C21
J24
J23
J26
C3
U25B
U25B
D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL[0]
BSEL[1]
BSEL[2]
Penryn
Penryn
DATA GRP 0
DATA GRP 0
DATA GRP 1
DATA GRP 1
MISC
MISC
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
DATA GRP 2DATA GRP 3
DATA GRP 2DATA GRP 3
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
COMP[0]
COMP[1]
COMP[2]
COMP[3]
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
R26
U26
AA1
Y1
E5
B5
D24
D6
D7
AE6
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
COMP0
COMP1
COMP2
COMP3
H_D#[32..47]
H_D#[48..63]
R229 27.4/F_6R229 27.4/F_6
R226 54.9/F_4R226 54.9/F_4
R75 27.4/F_6R75 27.4/F_6
R82 54.9/F_4R82 54.9/F_4
H_D#[32..47] (5)
H_DSTBN#2 (5)
H_DSTBP#2 (5)
H_DINV#2 (5)
H_D#[48..63] (5)
Layout note:
comp0,2: Zo=27.4ohm, L<0.5"
comp1,3: Zo=55ohm, L<0.5"
Layout note:
DPRSTP# , Daisy Chain
(SB>Power>NB>CPU)
H_DSTBN#3 (5)
H_DSTBP#3 (5)
H_DINV#3 (5)
ICH_DPRSTP# (6,12,34)
H_DPSLP# (12)
H_DPWR# (5)
H_PWRGD (12)
H_CPUSLP# (5)
PSI# (34)
Penryn
Penryn
B B
Thermal Trip
DELAY_VR_PWRGOOD(6,14,31,34)
PM_THRMTRIP#
Processor hot
A A
H_PROCHOT#_D
+1.05V
R227
R227
56_4
56_4
R228 *0_4R228 *0_4
CPU 1/2
5
+1.05V
3
Q28
Q28
2
FDV301N
+1.05V
R391
R391
56_4
56_4
No use Thermal trip CPU side still PU 56ohm.
Use Thermal trip can share PU at SB side
No use PROCHOT CPU side still PU 56ohm.
Use PROCHOT to optional receiver CPU side PU
68ohm and through isolat 2.2K ohm to receiver
side
1
2
1 3
FDV301N
Q27
Q27
MMBT3904
MMBT3904
SYS_SHDN# (33,37)PM_THRMTRIP#(6,12)
H_PROCHOT# (34)
4
CPU Thermal monitor
ABCLK(31)
ABDATA(31)
THERM_ALERT#(14,17)
CPUFAN#_ON(30)
3
3
+3V
+5V
+3V
2
1
Q30
Q30
RHU002N06
RHU002N06
+3V
2
1
Q31
Q31
RHU002N06
RHU002N06
R469 10K_4R469 10K_4
R468 *0_4R468 *0_4
R462 *10K_4R462 *10K_4
3
R471
R471
10K_4
10K_4
R470
R470
10K_4
10K_4
U28
U28
8
SCLK
7
SDA
6
ALERT#
4
OVERT#
LM95245
LM95245
ADDRESS: 98H
WINDBOND AL83L771000
VCC
DXP
DXN
GND
+3V
R460
R460
200_6
200_6
VCC_TH
1
2
3
5
C450
C450
.1u_4
.1u_4
H_THERMDA
C452
C452
100p/50V_4
100p/50V_4
H_THERMDC
AL095245000NS
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
XDP PU/PD
SYS_RST#
XDP_TDO
XDP_TDI
XDP_TMS
XDP_BPM#5
XDP_TCK
XDP_TRST#
XDP_DBRESET# and XDP_TDO
reserve for XDP
R454 *1K_4R454 *1K_4
R92 *54.9/F_4R92 *54.9/F_4
R108 54.9/F_4R108 54.9/F_4
R96 54.9/F_4R96 54.9/F_4
R386 54.9/F_4R386 54.9/F_4
R97 54.9/F_4R97 54.9/F_4
R100 54.9/F_4R100 54.9/F_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
CPU Host Bus
CPU Host Bus
CPU Host Bus
ZK2
ZK2
ZK2
1
+3V
+1.05V
3B
3B
339Wednesday, July 09, 2008
339Wednesday, July 09, 2008
339Wednesday, July 09, 2008
3B
of
of
of
5
4
3
2
1
U25D
U25D
A4
VSS[001]
A8
VSS[002]
A11
VSS[003]
A14
VSS[004]
A16
VSS[005]
A19
VSS[006]
A23
D D
C C
B B
A A
VSS[007]
AF2
VSS[008]
B6
VSS[009]
B8
VSS[010]
B11
VSS[011]
B13
VSS[012]
B16
VSS[013]
B19
VSS[014]
B21
VSS[015]
B24
VSS[016]
C5
VSS[017]
C8
VSS[018]
C11
VSS[019]
C14
VSS[020]
C16
VSS[021]
C19
VSS[022]
C2
VSS[023]
C22
VSS[024]
C25
VSS[025]
D1
VSS[026]
D4
VSS[027]
D8
VSS[028]
D11
VSS[029]
D13
VSS[030]
D16
VSS[031]
D19
VSS[032]
D23
VSS[033]
D26
VSS[034]
E3
VSS[035]
E6
VSS[036]
E8
VSS[037]
E11
VSS[038]
E14
VSS[039]
E16
VSS[040]
E19
VSS[041]
E21
VSS[042]
E24
VSS[043]
F5
VSS[044]
F8
VSS[045]
F11
VSS[046]
F13
VSS[047]
F16
VSS[048]
F19
VSS[049]
F2
VSS[050]
F22
VSS[051]
F25
VSS[052]
G4
VSS[053]
G1
VSS[054]
G23
VSS[055]
G26
VSS[056]
H3
VSS[057]
H6
VSS[058]
H21
VSS[059]
H24
VSS[060]
J2
VSS[061]
J5
VSS[062]
J22
VSS[063]
J25
VSS[064]
K1
VSS[065]
K4
VSS[066]
K23
VSS[067]
K26
VSS[068]
L3
VSS[069]
L6
VSS[070]
L21
VSS[071]
L24
VSS[072]
M2
VSS[073]
M5
VSS[074]
M22
VSS[075]
M25
VSS[076]
N1
VSS[077]
N4
VSS[078]
N23
VSS[079]
N26
VSS[080]
VSS[081]P3VSS[162]
Penryn
Penryn
CPU 2/2
5
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[163]
.
.
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
C146
C146
*10u_8
*10u_8
C408
C408
10u_8
10u_8
C119
C136
C136
10u_8
10u_8
C421
C421
*10u_8
*10u_8
C119
10u_8
10u_8
C414
C414
10u_8
10u_8
C97
C97
*10u_8
*10u_8
Layout Note:
Place these parts
reference to Intel demo
board.
C144
C144
*10u_8
*10u_8
C401
C401
10u_8
10u_8
4
C413
C127
C127
*10u_8
*10u_8
C409
C409
*10u_8
*10u_8
C109
C109
*10u_8
*10u_8
C433
C433
10u_8
10u_8
C110
C110
*10u_8
*10u_8
C428
C428
+
+
*330u_7343
*330u_7343
C157
C157
10u_8
10u_8
C131
C131
*10u_8
*10u_8
C118
C118
10u_8
10u_8
C405
C405
10u_8
10u_8
C368
C368
*10u_8
*10u_8
C145
C145
*10u_8
*10u_8
C125
C125
*10u_8
*10u_8
C412
C412
+
+
330u_7343
330u_7343
C432
C432
*10u_8
*10u_8
C443
C443
10u_8
10u_8
C402
C402
*10u_8
*10u_8
C413
*10u_8
*10u_8
C98
C98
*10u_8
*10u_8
C424
C424
10u_8
10u_8
C104
C104
*10u_8
*10u_8
C420
C420
10u_8
10u_8
C140
C140
10u_8
10u_8
C124
C124
+
+
330u_7343
330u_7343
+
+
Montevina platform : Early Reference Board Schematics Feb 2007. Rev 1.0
stuff 22U*34, NC 22U*2
stuff 330U*2, NC330U*2
3
VCC_CORE VCC_CORE
U25C
U25C
A7
C135
C135
*10u_8
*10u_8
C419
C419
*10u_8
*10u_8
C96
C96
10u_8
10u_8
C103
C103
10u_8
10u_8
C404
C404
*10u_8
*10u_8
C438
C438
*10u_8
*10u_8
C407
C407
*330u_7343
*330u_7343
A10
A12
A13
A15
A17
A18
A20
B10
B12
B14
B15
B17
B18
B20
C10
C12
C13
C15
C17
C18
D10
D12
D14
D15
D17
D18
E10
E12
E13
E15
E17
E18
E20
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18
A9
B7
B9
C9
D9
E7
E9
F7
F9
VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]
Penryn
Penryn
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
VCCA[01]
VCCA[02]
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VCCSENSE
VSSSENSE
2
.
.
VCC:38A (Low power type)
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
B26
C26
AD6
AF5
AE5
AF4
AE3
AF3
AE2
AF7
AE7
VCC:47A (Standard type)
Layout Note:
Inside CPU center cavity in 2 rows
VCCP : 2.5A(Supply after VCC Stable)
4.5A(Supply before VCC Stable)
C85
C85
.1u/16V_6
.1u/16V_6
C153
C153
*.1u/16V_6
*.1u/16V_6
C91
C91
.1u/16V_6
.1u/16V_6
C154
C154
.1u/16V_6
.1u/16V_6
C86
C86
.1u/16V_6
.1u/16V_6
C156
C156
.1u/16V_6
.1u/16V_6
+
+
VCCA:130mA
C456
H_VID0 (34)
H_VID1 (34)
H_VID2 (34)
H_VID3 (34)
H_VID4 (34)
H_VID5 (34)
H_VID6 (34)
C456
.01u/25V_4
.01u/25V_4
R118 100/F_6R118 100/F_6
R111
R111
100/F_6
100/F_6
C455
C455
10u_8
10u_8
VCC_CORE
VCCSENSE (34)
VSSSENSE (34)
Layout Note:
Z0=27.4,PU/PD L<1"
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
PROJECT :
CPU Power
CPU Power
CPU Power
ZK2
ZK2
ZK2
1
of
of
of
439Friday, June 27, 2008
439Friday, June 27, 2008
439Friday, June 27, 2008
+1.05V
C377
C377
330u_7343
330u_7343
+1.5V
3B
3B
3B
5
4
3
2
1
U26A
M11
N12
P13
N10
AD14
Y10
Y12
Y14
W2
AA8
AA13
AA9
AA11
AD11
AD10
AD13
AE12
AE9
AA2
AD8
AA3
AD3
AD7
AE14
AF3
AC1
AE3
AC3
AE11
AE8
AG2
AD6
C12
E11
A11
B11
F2
G8
F8
E6
G2
H6
H2
F6
D4
H3
M9
J1
J2
J6
P2
L2
R2
N9
L6
M5
J3
N2
R1
N5
N6
N8
L7
M3
Y3
Y6
Y7
Y9
C5
E3
U26A
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
H_SWING
H_RCOMP
H_CPURST#
H_CPUSLP#
H_AVREF
H_DVREF
CANTIGA_PM
CANTIGA_PM
H_ADSTB#_0
H_ADSTB#_1
HOST
HOST
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
H_ADS#
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
H_RS#_0
H_RS#_1
H_RS#_2
A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20
H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9
J8
L3
Y13
Y1
L10
M7
AA5
AE6
L9
M8
AA6
AE5
B15
K13
F13
B13
B14
B6
F12
C8
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
H_D#[0..63](3)
QCI P/N
D D
C C
Intel Cantiga (G)M
Intel Cantiga (P)M
+1.05V
AJSLB940T04
AJSLB970T06
0.3125*VCCP
R110
R110
221/F_4
221/F_4
R109
R109
100/F_4
100/F_4
B B
R425
R425
24.9/F_4
24.9/F_4
WIDE(10):SPACING(20) ,
L<0.5"
H_SWING
C77
C77
.1u_4
.1u_4
H_RCOMP
Layout Note:
WIDE(10):SPACING(20) ,
L<0.5"
+1.05V
R418
2/3*VCCP
WIDE(10):SPACING(20),
A A
L<0.5"
R418
1K/F_4
1K/F_4
R419
R419
2K/F_4
2K/F_4
H_CPURST#(3)
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_SWING
H_RCOMP
H_AVREF
C394
C394
*.1u_4
*.1u_4
GMCH (CANTIGA)
5
4
3
2
H_A#[3..35] (3)
H_ADS# (3)
H_ADSTB#0 (3)
H_ADSTB#1 (3)
H_BNR# (3)
H_BPRI# (3)
H_BREQ# (3)
H_DEFER# (3)
H_DBSY# (3)
CLK_MCH_BCLK (2)
CLK_MCH_BCLK# (2)
H_DPWR# (3)
H_DRDY# (3)
H_HIT# (3)
H_HITM# (3)
H_LOCK# (3)
H_TRDY# (3)
H_DINV#[3..0] (3)
H_DSTBN#[3..0] (3)
H_DSTBP#[3..0] (3)
H_REQ#[0..4] (3)
H_RS#[0..2] (3)H_CPUSLP#(3)
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
PROJECT :
GMCH HOST
GMCH HOST
GMCH HOST
ZK2
ZK2
ZK2
1
of
of
of
539Friday, June 27, 2008
539Friday, June 27, 2008
539Friday, June 27, 2008
3B
3B
3B
5
4
3
2
1
IV@
EV@
U26B
AH10
AH12
AH13
AY21
BG23
BF23
BH18
BF18
AL34
AK34
AN35
AM35
AT40
AT11
BG48
BF48
BD48
BC48
BH47
BG47
BE47
BH46
BF46
BG45
BH44
BH43
M36
N36
R33
T33
AH9
K12
T24
B31
M1
B2
T25
R25
P25
P20
P24
C25
N24
M24
E21
C23
C24
N21
P21
T21
R20
M20
L21
H21
P29
R28
T28
R29
N33
P32
T20
R32
BH6
BH5
BG4
BH3
BF3
BH2
BG2
BE2
BG1
BF1
BD1
BC1
U26B
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD14
RSVD15
RSVD17
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
ME_JTAG_TCK
ME_JTAG_TDI
ME_JTAG_TDO
ME_JTAG_TMS
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
PM_SYNC#
B7
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
F1
NC_25
CANTIGA_PM
CANTIGA_PM
3
CFG
CFG
PM
PM
AP24
SA_CK_0
AT21
SA_CK_1
AV24
SB_CK_0
AU20
SB_CK_1
AR24
SA_CK#_0
AR21
SA_CK#_1
AU24
SB_CK#_0
AV20
SB_CK#_1
BC28
SA_CKE_0
AY28
SA_CKE_1
AY36
SB_CKE_0
RSVD
RSVD
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_DRAMRST#
DPLL_REF_CLK
DDR CLK/ CONTROL/COMPENSATION
DDR CLK/ CONTROL/COMPENSATION
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
ME JTAG
ME JTAG
CLK
CLK
DMI
DMI
GRAPHICS VID
GRAPHICS VID
MEHDA
MEHDA
DDPC_CTRLCLK
DDPC_CTRLDATA
NC
NC
SDVO_CTRLCLK
SDVO_CTRLDATA
MISC
MISC
SB_CKE_1
SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1
SA_ODT_0
SA_ODT_1
SB_ODT_0
SB_ODT_1
SM_RCOMP
SM_RCOMP#
SM_VREF
SM_PWROK
SM_REXT
PEG_CLK
PEG_CLK#
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4
GFX_VR_EN
CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF
CLKREQ#
ICH_SYNC#
TSATN#
HDA_BCLK
HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC
BB36
BA17
AY16
AV16
AR13
BD17
AY17
BF15
AY13
BG22
BH21
BF28
BH28
AV42
AR36
BF17
BC36
B38
A38
E41
F41
F43
E43
AE41
AE37
AE47
AH39
AE40
AE38
AE48
AH40
AE35
AE43
AE46
AH42
AD35
AE44
AF46
AH43
B33
B32
G33
F33
E33
C34
AH37
AH36
AN36
AJ35
AH34
N28
M28
G36
E36
K36
H36
B12
B28
B30
B29
C29
A28
M_RCOMP
M_RCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_VREF
R223 10K/F_4R223 10K/F_4
SM_POK
SM_REXT
R237 499/F_4R237 499/F_4
CLK_DREFCLK
CLK_DREFCLK#
CLK_DREFSSCLK
CLK_DREFSSCLK#
CLK_PCIE_3GPLL
CLK_PCIE_3GPLL#
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
MCH_CLVREF_R
DDPC_CTRLCLK
DDPC_DDCDATA
CLK_MCH_OE#
TSATN#
R114 56_4R114 56_4
HDA_BIT_CLK_HDMI
HDA_RST#_HDMI
HDA_SDIN_HDMI
HDA_SDOUT_HDMI
HDA_SYNC_HDMI
Impact ICH9M VCCHDA and VCCSUSHDA supply 1.5V/3.3V
NOTE:
If (G)MCH's HD Audio signals are connected to ICH9M for
iHDMI, VCCHDA and VCCSUSHDA on ICH9M should be
only on 1.5V. These power pins on ICH9M can be supplied
with 3.3V if and only if (G)MCH's HDA is not connected to
ICH9M. Consequently, only 1.5V audio/modem codecs can
be used on the platform.
M_CLK0 (16)
M_CLK1 (16)
M_CLK2 (16)
M_CLK3 (16)
M_CLK#0 (16)
M_CLK#1 (16)
M_CLK#2 (16)
M_CLK#3 (16)
M_CKE0 (16)
M_CKE1 (16)
M_CKE2 (16)
M_CKE3 (16)
M_CS#0 (16)
M_CS#1 (16)
M_CS#2 (16)
M_CS#3 (16)
M_ODT0 (16)
M_ODT1 (16)
M_ODT2 (16)
M_ODT3 (16)
SM_VREF=0.5*VCC_SM
SM_PWROK only for
DDR3.(DDR2 PD only)
SM_DRAMRST# only
for DDR3.(DDR2:NC)
CLK_DREFCLK (2)
CLK_DREFCLK# (2)
CLK_DREFSSCLK (2)
CLK_DREFSSCLK# (2)
CLK_PCIE_3GPLL (2)
CLK_PCIE_3GPLL# (2)
DMI_TXN[3:0] (13)
DMI_TXP[3:0] (13)
DMI_RXN[3:0] (13)
DMI_RXP[3:0] (13)
CL_CLK0 (14)
CL_DATA0 (14)
MPWROK (14,31)
CL_RST#0 (14)
SDVO_CTRLCLK (19)
SDVO_CTRLDATA (19)
MCH_ICH_SYNC# (14)
+1.05V
HDA_BIT_CLK_HDMI (12)
HDA_RST#_HDMI (12)
HDA_SDIN_HDMI (12)
HDA_SDOUT_HDMI (12)
HDA_SYNC_HDMI (12)
2
+1.05V
R173
R173
1K/F_4
1K/F_4
C139
C139
.1u_4
.1u_4
If HDMI not support
HDA --> NC
VCC_HDA-->GND
Differential signal-->NC
Check list note : CL_VREF=0.35V
R179
R179
511/F_4
511/F_4
M_RCOMP
R475 80.6/F_4R475 80.6/F_4
M_RCOMP#
R474 80.6/F_4R474 80.6/F_4
SM_VREF
SM_VREF.Default use voltage divider for
poor layout cause +SMDDR_VREF not
meet spec.And Intel circuit PU/PD is
1K,But Check list PU/PD is 10K.
+VDR_SUS
R233 10K/F_4R233 10K/F_4
R230 10K/F_4R230 10K/F_4
+VDR_SUS
INTEL FAE Suggest PD for Ext graphics
CLK_DREFCLK#
CLK_DREFCLK
CLK_DREFSSCLK#
CLK_DREFSSCLK
SM_RCOMP_VOH
C479
C479
2.2u_6
2.2u_6
SM_RCOMP_VOL
C478
C478
2.2u_6
2.2u_6
NB Thermaltrip
TSATN#
DDPC_CTRL for HDMI port C
SDVO_CTRL for HDMI port B
<Checklist ver0.8>
If TSATN# is not used, then it must be terminated
with a 56-Ω pull-up resistor to VCCP.
<Pin out check issue>
Cantiga EDS 0.7 change Ball B12 to TSATN# from TSATN
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
R412 *E@0_4R412 *E@0_4
R413 *E@0_4R413 *E@0_4
R124 *E@0_4R124 *E@0_4
R120 *E@0_4R120 *E@0_4
C462
C462
R477
R477
.01u_4
.01u_4
3.01K/F_4
3.01K/F_4
R481
R481
C461
C461
1K/F_4
1K/F_4
.01u_4
.01u_4
+1.05V
R84
R84
*10K_4
*10K_4
2
Q11
Q11
*MMBT3904
*MMBT3904
1 3
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
GMCH DMI
GMCH DMI
GMCH DMI
1
+VDR_SUS
R4821K/F_4 R4821K/F_4
TSATN_EC# (31)
ZK2
ZK2
ZK2
639Friday, June 27, 2008
639Friday, June 27, 2008
639Friday, June 27, 2008
3B
3B
3B
Strap table
Pin Name Strap description
CFG[2:0]
D D
CFG[4:3]
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
FSB Frequency Select
Reserved
DMI X2 Select
iTPM Host Interface
ME TLS Confidentiality
Reserved
PCIE Graphics Lane Reversal
PCIE Loopback enable
ReservedCFG11
CFG12
CFG13
CFG[15:14]
C C
CFG16
CFG[18:17]
CFG19
CFG20
ALLZ
XOR
Reserved
FSB Dynamic ODT
Reserved
DMI Lane Reversal
Digital Display Port
(SDVO/DP/iHDMI)
Concurrent with PCIE
SDVO_CTRLDATA SDVO Present
DDPC_CTRLDATA Digital Display Present
Strap pin
+3V
B B
A A
R395 *4.02K/F_4R395 *4.02K/F_4
R392 *4.02K/F_4R392 *4.02K/F_4
R400 *2.21K/F_4R400 *2.21K/F_4
R158 *2.21K/F_4R158 *2.21K/F_4
R145 *2.21K/F_4R145 *2.21K/F_4
R399 *2.21K/F_4R399 *2.21K/F_4
R394 *2.21K/F_4R394 *2.21K/F_4
R171 *2.21K/F_4R171 *2.21K/F_4
R166 *2.21K/F_4R166 *2.21K/F_4
R147 *2.21K/F_4R147 *2.21K/F_4
+3V
R132 I@2.21K/F_4R132 I@2.21K/F_4
R131 I@2.21K/F_4R131 I@2.21K/F_4
R157 *2.21K/F_4R157 *2.21K/F_4
R168 *2.21K/F_4R168 *2.21K/F_4
R155 10K_4R155 10K_4
R396 10K_4R396 10K_4
R161 10K_4R161 10K_4
Configuration
000= FSB 1066MHz
010 = FSB 800MHz
011 = FSB 667MHz
0 = DMI X2
1 = DMI X4(Default)
0 = iTPM Host Interface is enabled
1 = iTPM Host Interface is disabled(Default)
0 = AMT Firmware will use TLS cipher suite
with no confidentiality
1 = AMT Firmware will use TLS cipher suite
with confidentiality(Default)
0 = Reverse Lanes
1 = Normal operation(Default)
0 = Enabled
1 = Disabled (Default)
0 = ALLZ mode enable
1 = disable(Default)
0 = XOR mode enable
1 = disable(Default)
0 = Dynamic ODT disable
1 = Dynamic ODT Enable(Default)
0 = Normal (Default)
1 = Lanes Reversed
0 = Only Digital Display port (SDVO/DP/iHDMI)
or PCIE is operational (Default)
1 = Digital Display port (SDVO/DP/iHDMI) and
PCIE are operating simultaneously via PEG
port
0 = No SDVO/HDMI Device Present(Default)
1 = SDVO/HDMI Device present
0 = Digital display(HDMI/DP) device
absent(Default)
1 = Digital display(HDMI/DP) device present
MCH_CFG_19
MCH_CFG_20
MCH_CFG_5
TPM Disable
MCH_CFG_6
MCH_CFG_7
MCH_CFG_9
MCH_CFG_10
MCH_CFG_12
MCH_CFG_13
MCH_CFG_16
SDVO_CTRLDATA
SDVO_CTRLCLK
DDPC_DDCDATA
DDPC_CTRLCLK
CLK_MCH_OE#
PM_EXTTS#0
PM_EXTTS#1
PM_SYNC#(14)
ICH_DPRSTP#(3,12,34)
PM_EXTTS#0(16)
PM_EXTTS#1(16)
DELAY_VR_PWRGOOD(3,14,31,34)
PLT_RST#(13)
PM_THRMTRIP#(3,12)
PM_DPRSLPVR(14,34)
NB Thermal trip pin
No use Thermal trip NB side can
NC.(NB has ODT)
PM_DPRSTP#
The Daisy chain topology should
be routed from ICH9M to IMVP ,
then to (G)MCH and CPU, in that
order.
R220 100/F_4R220 100/F_4
R170 *0_4R170 *0_4
JTAG_TCK
T38T38
JTAG_TDI
T29T29
JTAG_TDO
T46T46
JTAG_TMS
T40T40
MCH_BSEL0(2)
MCH_BSEL1(2)
MCH_BSEL2(2)
MCH_CFG_3
T23T23
MCH_CFG_4
T24T24
MCH_CFG_5
MCH_CFG_6
MCH_CFG_7
MCH_CFG_8
T19T19
MCH_CFG_9
MCH_CFG_10
MCH_CFG_11
T22T22
MCH_CFG_12
MCH_CFG_13
MCH_CFG_14
T25T25
MCH_CFG_15
T18T18
MCH_CFG_16
MCH_CFG_17
T20T20
MCH_CFG_18
T21T21
MCH_CFG_19
MCH_CFG_20
RST_IN#_MCH
THRMTRIP#_R
GMCH (CANTIGA)
5
4
5
4
3
2
1
IV@
U26C
EV@
SP@
D D
C C
B B
IV&EV Dis/Enable setting
If LVDS no use,all signal can NC
L_BKLT_CTRL(18)
INT_LVDS_BLON(18)
+3V
INT_LVDS_EDIDCLK(18)
INT_LVDS_EDIDDATA(18)
INT_LVDS_DIGON(18)
INT_TXLCLKOUT-(17)
INT_TXLCLKOUT+(17)
INT_TXUCLKOUT-(17)
INT_TXUCLKOUT+(17)
INT_TXLOUT0-(17)
INT_TXLOUT1-(17)
INT_TXLOUT2-(17)
INT_TXLOUT0+(17)
INT_TXLOUT1+(17)
INT_TXLOUT2+(17)
INT_TXUOUT0-(17)
INT_TXUOUT1-(17)
INT_TXUOUT2-(17)
INT_TXUOUT0+(17)
INT_TXUOUT1+(17)
INT_TXUOUT2+(17)
INT_CRT_DDCCLK(17)
INT_CRT_DDCDAT(17)
INT_HSYNC(17)
INT_VSYNC(17)
R154 I@10K_4R154 I@10K_4
R401 I@10K_4R401 I@10K_4
R137 75_4R137 75_4
R143 75_4R143 75_4
R156 75_4R156 75_4
INT_CRT_BLU(17)
INT_CRT_GRN(17)
INT_CRT_RED(17)
R416 I@30.1_4R416 I@30.1_4
R415 I@30.1_4R415 I@30.1_4
L_CTRL_CLK
L_CTRL_DATA
R121 I@2.37K/F_4R121 I@2.37K/F_4
INT_TXLCLKOUTÂINT_TXLCLKOUT+
INT_TXUCLKOUTÂINT_TXUCLKOUT+
INT_TXLOUT0ÂINT_TXLOUT1ÂINT_TXLOUT2-
INT_TXLOUT0+
INT_TXLOUT1+
INT_TXLOUT2+
INT_TXUOUT0ÂINT_TXUOUT1ÂINT_TXUOUT2-
INT_TXUOUT0+
INT_TXUOUT1+
INT_TXUOUT2+
INT_TV_COMP
INT_TV_Y/G
INT_TV_C/R
INT_CRT_BLU
INT_CRT_GRN
INT_CRT_RED
HSYNC_G
CRTIREF
VSYNC_G
HSYNC/VSYNC serial R place close to NB
MXM STUFFED.
A A
HSYNC_G
VSYNC_G
CRTIREF pull down
for IV cantiga 1.02k ohm/F
U26C
L32
L_BKLT_CTRL
G32
L_BKLT_EN
M32
L_CTRL_CLK
M33
L_CTRL_DATA
K33
L_DDC_CLK
J33
L_DDC_DATA
M29
L_VDD_EN
C44
LVDS_IBG
B43
LVDS_VBG
E37
LVDS_VREFH
E38
LVDS_VREFL
C41
LVDSA_CLK#
C40
LVDSA_CLK
B37
LVDSB_CLK#
A37
LVDSB_CLK
H47
LVDSA_DATA#_0
E46
LVDSA_DATA#_1
G40
LVDSA_DATA#_2
A40
LVDSA_DATA#_3
H48
LVDSA_DATA_0
D45
LVDSA_DATA_1
F40
LVDSA_DATA_2
B40
LVDSA_DATA_3
A41
LVDSB_DATA#_0
H38
LVDSB_DATA#_1
G37
LVDSB_DATA#_2
J37
LVDSB_DATA#_3
B42
LVDSB_DATA_0
G38
LVDSB_DATA_1
F37
LVDSB_DATA_2
K37
LVDSB_DATA_3
F25
TVA_DAC
H25
TVB_DAC
K25
TVC_DAC
H24
TV_RTN
C31
TV_DCONSEL_0
E32
TV_DCONSEL_1
E28
CRT_BLUE
G28
CRT_GREEN
J28
CRT_RED
G29
CRT_IRTN
H32
CRT_DDC_CLK
J32
CRT_DDC_DATA
J29
CRT_HSYNC
E29
CRT_TVO_IREF
L29
CRT_VSYNC
CANTIGA_PM
CANTIGA_PM
PEG_COMPI
PEG_COMPO
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
LVDS
LVDS
TV
TV
VGA
VGA
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PCI-EXPRESS GRAPHICS
PCI-EXPRESS GRAPHICS
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
L<0.5" , If PCIE not support
still connect to +VCC_PEG
EXP_A_COMPX
T37
T36
H44
J46
L44
L40
N41
P48
N44
T43
U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39
H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40
J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46
J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46
PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15
PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15
C_PEG_TXN0
C_PEG_TXN1
C_PEG_TXN2
C_PEG_TXN3
C_PEG_TXN4
C_PEG_TXN5
C_PEG_TXN6
C_PEG_TXN7
C_PEG_TXN8
C_PEG_TXN9
C_PEG_TXN10
C_PEG_TXN11
C_PEG_TXN12
C_PEG_TXN13
C_PEG_TXN14
C_PEG_TXN15
C_PEG_TXP0
C_PEG_TXP1
C_PEG_TXP2
C_PEG_TXP3
C_PEG_TXP4
C_PEG_TXP5
C_PEG_TXP6
C_PEG_TXP7
C_PEG_TXP8
C_PEG_TXP9
C_PEG_TXP10
C_PEG_TXP11
C_PEG_TXP12
C_PEG_TXP13
C_PEG_TXP14
C_PEG_TXP15
R165 49.9/F_4R165 49.9/F_4
Can support reversal routing.If CFG9=1, PCI Express
is normal operation. If CFG9=0, then PEG_TXP0
becomes PEG_TXP15, PEG_TXP1 becomes
PEG_TXP14, PEG_TXP2 becomes PEG_TXP13, etc.
similarly for PEG_RXP[15:0] and PEG_RXN[15:0]
C88 .1u_4C88 .1u_4
C80 .1u_4C80 .1u_4
C90 .1u_4C90 .1u_4
C100 .1u_4C100 .1u_4
C102 *E@.1u_4C102 *E@.1u_4
C107 *E@.1u_4C107 *E@.1u_4
C111 *E@.1u_4C111 *E@.1u_4
C122 *E@.1u_4C122 *E@.1u_4
C123 *E@.1u_4C123 *E@.1u_4
C142 *E@.1u_4C142 *E@.1u_4
C152 *E@.1u_4C152 *E@.1u_4
C134 *E@.1u_4C134 *E@.1u_4
C155 *E@.1u_4C155 *E@.1u_4
C176 *E@.1u_4C176 *E@.1u_4
C216 *E@.1u_4C216 *E@.1u_4
C172 *E@.1u_4C172 *E@.1u_4
C89 .1u_4C89 .1u_4
C75 .1u_4C75 .1u_4
C82 .1u_4C82 .1u_4
C94 .1u_4C94 .1u_4
C101 *E@.1u_4C101 *E@.1u_4
C105 *E@.1u_4C105 *E@.1u_4
C108 *E@.1u_4C108 *E@.1u_4
C115 *E@.1u_4C115 *E@.1u_4
C120 *E@.1u_4C120 *E@.1u_4
C138 *E@.1u_4C138 *E@.1u_4
C151 *E@.1u_4C151 *E@.1u_4
C128 *E@.1u_4C128 *E@.1u_4
C148 *E@.1u_4C148 *E@.1u_4
C175 *E@.1u_4C175 *E@.1u_4
C219 *E@.1u_4C219 *E@.1u_4
C171 *E@.1u_4C171 *E@.1u_4
+1.05V
PEG_RXN[15:0] (17)
PEG_RXP[15:0] (17)
PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15
PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15
PEG_TXN[15:0] (17)
PEG_TXP[15:0] (17)
IV&EV Dis/Enable setting
<5/31>Montevina_Schematics_Checklist_Rev0_8
a)For TVOUT Disabled, TV_DCONSEL[1:0] Connect to GND. But
design guide Rev0.7 show NC.What is correct.
b)For CRT DAC Disable, CRT_DDC_CLK, CRT_DDC_DATA .
CRT_HSYNC, CRT_VSYNCThese signals should be connected to
GND. But design guide Rev0.7 show NC, Intel suggest follow
Design guide.
<check list>
For EV@
CRT R/G/B 0ohm to GND
CRTIREF 0ohm to GND
<check list>
For IV@
CRT R/G/B 150ohm to GND
CRTIREF 1.02Kohm to GND
CRTIREF
For IV: 1.02Kohm
For EV:0ohm
R115 SP@1.02K/F_4R115 SP@1.02K/F_4
CRTIREF
SP@
CRT_R/G/B
For IV: 150ohm
For EV:0ohm
R127 SP@150_4R127 SP@150_4
R138 SP@150_4R138 SP@150_4
R146 SP@150_4R146 SP@150_4
INT_CRT_BLU
INT_CRT_GRN
INT_CRT_RED
R417
R417
*E@0_4
*E@0_4
R414
R414
*E@0_4
*E@0_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
PROJECT :
GMCH VGA
GMCH VGA
GMCH VGA
ZK2
ZK2
ZK2
3B
3B
3B
of
of
of
739Wednesday, July 09, 2008
739Wednesday, July 09, 2008
739Wednesday, July 09, 2008
1
5
4
3
2
1
M_A_DQ[63:0](16)
D D
C C
B B
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
AJ38
AJ41
AN38
AM38
AJ36
AJ40
AM44
AM42
AN43
AN44
AU40
AT38
AN41
AN39
AU44
AU42
AV39
AY44
BA40
BD43
AV41
AY43
BB41
BC40
AY37
BD38
AV37
AT36
AY38
BB38
AV36
AW36
BD13
AU11
BC11
BA12
AU13
AV13
BD12
BC12
BB9
BA9
AU10
AV9
BA11
BD9
AY8
BA6
AV5
AV7
AT9
AN8
AU5
AU6
AT5
AN10
AM11
AM5
AJ9
AJ8
AN12
AM13
AJ11
AJ12
U26D
U26D
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
CANTIGA_PM
CANTIGA_PM
BD21
SA_BS_0
BG18
SA_BS_1
AT25
SA_BS_2
BB20
SA_RAS#
BD20
SA_CAS#
AY20
SA_WE#
AM37
SA_DM_0
AT41
SA_DM_1
AY41
SA_DM_2
AU39
SA_DM_3
BB12
SA_DM_4
AY6
SA_DM_5
AT7
SA_DM_6
AJ5
SA_DM_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7
AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8
BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_BS0 (16)
M_A_BS1 (16)
M_A_BS2 (16)
M_A_RAS# (16)
M_A_CAS# (16)
M_A_WE# (16)
M_A_DM[7:0] (16)
M_A_DQS[7:0] (16)
M_A_DQS#[7:0] (16)
M_A_A[14:0] (16)
M_B_DQ[63:0](16)
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
AK47
AH46
AP47
AP46
AJ46
AJ48
AM48
AP48
AU47
AU46
BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44
BG43
BF43
BE45
BC41
BF40
BF41
BG38
BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11
BG8
BH12
BF11
BF8
BG7
BC5
BC6
AY3
AY1
BF6
BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1
AL1
AL2
AJ1
AH1
AM2
AM3
AH3
AJ3
U26E
U26E
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
CANTIGA_PM
CANTIGA_PM
BC16
SB_BS_0
BB17
SB_BS_1
BB33
SB_BS_2
AU17
SB_RAS#
BG16
SB_CAS#
BF14
SB_WE#
AM47
SB_DM_0
AY47
SB_DM_1
BD40
SB_DM_2
BF35
SB_DM_3
BG11
SB_DM_4
BA3
SB_DM_5
AP1
SB_DM_6
AK2
SB_DM_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6
AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5
AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_BS0 (16)
M_B_BS1 (16)
M_B_BS2 (16)
M_B_RAS# (16)
M_B_CAS# (16)
M_B_WE# (16)
M_B_DM[7:0] (16)
M_B_DQS[7:0] (16)
M_B_DQS#[7:0] (16)
M_B_A[14:0] (16)
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
GMCH (CANTIGA)
5
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
4
3
2
Date: Sheet
PROJECT :
GMCH DDRII
GMCH DDRII
GMCH DDRII
ZK2
ZK2
ZK2
3B
3B
3B
839Friday, June 27, 2008
839Friday, June 27, 2008
839Friday, June 27, 2008
of
of
1
of
5
4
3
2
1
IV@
SP@
Power consumption reference to Intel
644135 Cantiga chipset EDS Volume1.
Section 10
GM TDP 10.5~12W
GS TDP 7~8W
D D
C C
B B
PM TDP 7W
+VDR_SUS
+
+
C191
C191
C465
C465
C464
C464
22u_8
22u_8
22u_8
22u_8
VCC_SM(1.8V)
DDR2(800M)
3000mA_S0 , 1mA_S3
DDR2(667M) : 2600mA_S0
DDR3(1067M) : 4140mA_S0
1.05V
Graphics core
VCC_AXG
VCC_AXG_NCTF
6326.84mA
Voltage regulator is shared between
the Graphics Core Rail,
VCCA_HPLL,VCCA_MPLL,VCCA_PEG_PLLVCCD_PEG_PLL,
VCCA_SM_CK, VCCA_DPLLA, VCCA_DPLLB, VCCD_HPLL,
VCCA_SM, VCC_AXF
.1u_4
.1u_4
IV@
C477
C477
330u_7343
330u_7343
+1.05V_AXG
R197 I@10/F_4R197 I@10/F_4
R191 I@10/F_4R191 I@10/F_4
+1.05V_AXG
AP33
AN33
BH32
BG32
BF32
BD32
BC32
BB32
BA32
AY32
AW32
AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31
BF31
BG30
BH29
BG29
BF29
BD29
BC29
BB29
BA29
AY29
AW29
AV29
AU29
AT29
AR29
AP29
BA36
BB24
BD16
BB21
AW16
AW13
AT13
AE25
AB25
AA25
AE24
AC24
AA24
AE23
AC23
AB23
AA23
AJ21
AG21
AE21
AC21
AA21
AH20
AF20
AE20
AC20
AB20
AA20
AM15
AL15
AE15
AJ15
AH15
AG15
AF15
AB15
AA15
AN14
AM14
AJ14
AH14
Y26
Y24
Y21
T17
T16
Y15
V15
U15
U14
T14
U26G
U26G
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36/NC
VCC_SM_37/NC
VCC_SM_38/NC
VCC_SM_39/NC
VCC_SM_40/NC
VCC_SM_41/NC
VCC_SM_42/NC
VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC_AXG_35
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_42
VCC_AXG_SENSE
VSS_AXG_SENSE
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
POWER
POWER
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC SMVCC GFX
VCC SMVCC GFX
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC GFX NCTF
VCC GFX NCTF
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
VCC SM LF
VCC SM LF
W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16
AV44
BA37
AM40
AV21
AY5
AM10
BB13
+1.05V_AXG
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
IV@
+1.05V_AXG
+
+
C444
C444
I@330u_7343
I@330u_7343
Place close to the GMCH Cavity Capacitors
Intel check list(Rev 0.8)
220U*2 near to NB(ESR=15m ohm)
Intel CRB(Rev 0.7)
270U*4 near to power(+V1.05S).
330U*2 near to NB
1.8V
Internal connect to power
C185
C185
C227
C227
.1u_4
.1u_4
.1u_4
.1u_4
+1.05V +1.05V_AXG
IV&EV Dis/Enable setting
Design guide(Table 72)
For INT VGA diasble.VCC_AXG power can connect to GND
Intel check list(Rev 0.8)
No description for VCC_SM bulk CAP
Intel CRB(Rev 0.7)
330U*1 Reserve near to power
330U*1 near to NB
R172 I@0_8R172 I@0_8
R435 I@0_8R435 I@0_8
R449 I@0_8R449 I@0_8
+
+
C454
C211
C211
.22u_4
.22u_4
C454
I@330u_7343
I@330u_7343
C204
C204
.22u_4
.22u_4
C159
C159
I@.47u_4
I@.47u_4
SP@:IV Sutff 1uf
EVstuff 0 ohm
C184
C184
.47u_4
.47u_4
C218
C218
1u_4
1u_4
C186
C186
SP@1u_6
SP@1u_6
Intel check list(Rev 0.8)
270U*1 near to power(+V1.05M).
270U*2 near to NB
Intel CRB(Rev 0.7)
270U*3 near to power(+V1.05M).
270U*1 near to NB
ESR=12m ohm
+1.05V
C177
C177
.1u_4
.1u_4
SP@
C141
C141
I@10u_8
I@10u_8
C208
C208
1u_4
1u_4
C166
C166
.22u_4
.22u_4
C133
C133
I@22u_8
I@22u_8
C167
C167
.22u_4
.22u_4
C137
C137
I@.1u_4
I@.1u_4
C143
C143
22u_8
22u_8
Place close to
the GMCH
+
+
C193
C193
I@.1u_4
I@.1u_4
C418
C418
330u_7343
330u_7343
C130
C130
I@.1u_4
I@.1u_4
AG34
AC34
AB34
AA34
AM33
AK33
AG33
AF33
AE33
AC33
AA33
AH28
AF28
AC28
AA28
AG26
AE26
AC26
AH25
AG25
AF25
AG24
AH23
AF23
Y34
V34
U34
AJ33
Y33
W33
V33
U33
AJ26
AJ23
T32
U26F
U26F
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
CANTIGA_PM
CANTIGA_PM
VCC CORE
VCC CORE
POWER
POWER
VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC NCTF
VCC NCTF
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
+1.05V
AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23
VCC
VCC_NCTF
1210.34mA_EV
1930.4mA_IV
ME Engine
508.12mA
Total Max=2438.52mA
CANTIGA_PM
A A
1. Route VCC_AXG_SENSE and VSS_AXG_SENSE differentially
2. VCC_AXG_SENSE PU to +VGFX_CORE_INT with 10ohm
and VSS_AXG_SENSE PD with 10ohm for Intel suggest
GMCH (CANTIGA)
5
CANTIGA_PM
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
4
3
2
Date: Sheet
PROJECT :
GMCH VCC,NCTF
GMCH VCC,NCTF
GMCH VCC,NCTF
ZK2
ZK2
ZK2
939Friday, June 27, 2008
939Friday, June 27, 2008
1
939Friday, June 27, 2008
3B
3B
3B
of
of
of
5
Power consumption reference to Intel
Cantiga chipset EDS Volume1. Section 10
+3V_CRT_TV_DAC
R397 I@0_6R397 I@0_6
IV@
EV@
SP@
D D
C C
3.3V
24.15mA for VCCA_TVA_DAC
39.48mA for VCCA_TVB_DAC
24.15mA for VCCA_TVC_DAC
Total 87.78mA
B B
A A
1210 10UH, 10%
0.45A DCR_max = 0.39
+1.05V
+1.05V
+1.05V
1210 0.1uH, 20%, 1A,
DCR_max=0.078Ω
FB 180@100 MHz, 25% 1.5A
DCR_max=90 m
CRB no 10U
Check list need min 10U~100U for VCCA_TV_DAC
+1.5V
L28 I@10uh_8L28 I@10uh_8
1.05V
64.8mA for DPLL_A/B
1210 10UH, 10%
0.45A DCR_max = 0.39
L33 I@10uh_8L33 I@10uh_8
R202 0_6R202 0_6
L16 BLM18PG181SN1D_6L16 BLM18PG181SN1D_6
+1.05VM_MPLL_RC
C168
C168
22u_8
22u_8
L32 I@BLM18PG181SN1D_6L32 I@BLM18PG181SN1D_6
+3V
C384
C384
I@10u_8
I@10u_8
R389 I@0_6R389 I@0_6
VCCD_TVDAC always keep 0.1U/0.022U/10U to +1.5V
+1.5V
1.5V
48.363mA for CRT
5mA for TV
R112 0_6R112 0_6
FB 180@100 MHz, 25% 1.5A
DCR_max=90 m
L27 I@BLM18PG181SN1D_6L27 I@BLM18PG181SN1D_6
C380
C380
10u_8
10u_8
CRB no 10U
Check list need min 10U~100U
for VCCA_QDAC
FB 220 @100 MHz, 25%, 2A
+1.05V
L34 BLM18PG181SN1D_6L34 BLM18PG181SN1D_6
+1.05VM_PEGPLL_RC
C431
C431
10u_6
10u_6
ESR=60m ohm
IV&EV Dis/Enable setting
+
+
C378
C378
I@220u_7343
I@220u_7343
ESR=15 m
+
+
ESR=15 m
C169
C169
4.7u_6
4.7u_6
R182 0.5/F_6R182 0.5/F_6
3.3V
79mA
1.5V
50mA
1.5V
35mA
R430 1/F_4R430 1/F_4
SP@:INT use 0.1U
EXT use 0 ohm
C382
C382
SP@.1u_4
SP@.1u_4
C399
C399
I@220u_7343
I@220u_7343
C164
C164
.1u_4
.1u_4
C160
C160
.1u_4
.1u_4
+1.05V
C391
C391
I@.1u_4
I@.1u_4
SP@:INT use 0.1U
EXT use 0 ohm
C99
C99
.1u_4
.1u_4
1.5V
0.5mA
C92
C92
I@.1u_4
I@.1u_4
1.05V
50mA
R403 I@0_6R403 I@0_6
VCCA_DPLLA/B always keep to +1.05V
(If no use IV dynamic core power)
C403
C403
SP@.1u_4
SP@.1u_4
1.05V
24mA
1.05V
139.2mA
R193 0_6R193 0_6
IV&EV Dis/Enable setting
C397
C397
SP@.01u_4
SP@.01u_4
C76
C76
SP@.1u_4
SP@.1u_4
C93
C93
.01u/25V_4
.01u/25V_4
C84
C84
SP@.01u_4
SP@.01u_4
IV&EV Dis/Enable setting
GMCH (CANTIGA)
5
4
+3V_A_DAC_BG
+1.5V
3.9 nH, 0.2 nH, 1A
, DCR_max=32 m
+1.05V
SP@:INT use 0.01U
EXT use 0 ohm
SP@:INT use 0.01U
EXT use 0 ohm
C415
C415
.1u_4
.1u_4
C434
C434
.1u_4
.1u_4
+VDR_SUS
4
IV&EV Dis/Enable setting
+3V_VCCA_CRT_DAC
C386
C386
I@.1u_4
I@.1u_4
SP@:INT use 0.01U
EXT use 0 ohm
C398
C398
I@.1u_4
I@.1u_4
C387
C387
SP@.01u_4
SP@.01u_4
C392
C392
SP@.01u_4
SP@.01u_4
C665
C665
I@10u_8
I@10u_8
USE same GND plane
1.8V
13.2mA
R453 0_8R453 0_8
1.05V
DDR2-800
720mA
R192 0_6R192 0_6
1.05V
DDR2-800
26mA
CRB : 0 ohm
Check list : 2.2nH
+1.05VM_A_SM
C390
C390
I@1000p/50V_4
I@1000p/50V_4
C442
C442
.1u_4
.1u_4
VCCA_PEG_PLL
+1.25V for Teenah use(100mA)
C195
C195
22u_8
22u_8
+1.05VM_A_SM_CK
C188
C188
*2.2u_6
*2.2u_6
C194
C194
4.7u_6
4.7u_6
C182
C182
22u_8
22u_8
VCCD_QDAC share to TV and CRT
R212 0_6R212 0_6
+1.05V
1.05V
157.2mA
R162 I@0_6R162 I@0_6
1.8V
60.31mA
C181
C181
.1u_4
.1u_4
IV&EV Dis/Enable setting
+1.8VSUS_DLVDS
SP@:INT use 1 U
EXT use 0 ohm
3.3V
5mA
+1.05VM_DPLLA
+1.05VM_DPLLB
+1.05VM_HPLL
+1.05VM_MPLL
+1.8VSUS_TXLVDS
1.5V
414uA
+VCCA_PEG_BG
+1.05VM_PEGPLL
C187
C187
1u_4
1u_4
C189
C189
.1u_4
.1u_4
+3V_CRT_TV_DAC
+VCC_HDA
+1.5V_TVDAC
+1.5V_QDAC
+1.05VM_MCH_PLL2
+1.05VM_PEGPLL
C393
C393
I@10u_8
I@10u_8
3.3V
73mA
1.05V
50mA
C114
C114
SP@1u_4
SP@1u_4
3
U26H
U26H
B27
VCCA_CRT_DAC_1
A26
VCCA_CRT_DAC_2
A25
VCCA_DAC_BG
B25
VSSA_DAC_BG
F47
VCCA_DPLLA
L48
VCCA_DPLLB
AD1
VCCA_HPLL
AE1
VCCA_MPLL
J48
VCCA_LVDS
J47
VSSA_LVDS
AD48
VCCA_PEG_BG
AA48
VCCA_PEG_PLL
AR20
VCCA_SM_1
AP20
VCCA_SM_2
AN20
VCCA_SM_3
AR17
VCCA_SM_4
AP17
VCCA_SM_5
AN17
VCCA_SM_6
AT16
VCCA_SM_7
AR16
VCCA_SM_8
AP16
VCCA_SM_9
AP28
VCCA_SM_CK_1
AN28
VCCA_SM_CK_2
AP25
VCCA_SM_CK_3
AN25
VCCA_SM_CK_4
AN24
VCCA_SM_CK_5
AM28
VCCA_SM_CK_NCTF_1
AM26
VCCA_SM_CK_NCTF_2
AM25
VCCA_SM_CK_NCTF_3
AL25
VCCA_SM_CK_NCTF_4
AM24
VCCA_SM_CK_NCTF_5
AL24
VCCA_SM_CK_NCTF_6
AM23
VCCA_SM_CK_NCTF_7
AL23
VCCA_SM_CK_NCTF_8
B24
VCCA_TV_DAC_1
A24
VCCA_TV_DAC_2
A32
VCC_HDA
M25
VCCD_TVDAC
L28
VCCD_QDAC
AF1
VCCD_HPLL
AA47
VCCD_PEG_PLL
M38
VCCD_LVDS_1
L37
VCCD_LVDS_2
CANTIGA_PM
CANTIGA_PM
3
Power Net Name
VCC_AXG_#
VCC_AXG_NCTF_#
VCCA_PEG_BG
VCCA_DPLLA
VCCA_DPLLB
VCCA_SM_#
VCCA_HPLL
VCCA_MPLL
VCCA_SM_CK_#
VCCA_PEG_PLL
VCC_AXF_#
VCCD_HPLL
VCCD_PEG_PLL
CRTPLLA PEGA SM
CRTPLLA PEGA SM
A LVDS
A LVDS
POWER
POWER
A CK
A CK
TV
TV
HDA
HDA
D TV/CRT
D TV/CRT
LVDS
LVDS
Cantiga(V)
1.05V
1.5V
1.05V
1.05V
1.05V
1.05V
1.05V
1.05V
1.05V
1.05V
1.05V
1.05V
AXF
AXF
VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4
SM CK
SM CK
VCC_TX_LVDS
HV
HV
PEG
PEG
DMI
DMI
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT
VTT
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25
VCC_AXF_1
VCC_AXF_2
VCC_AXF_3
VCC_HV_1
VCC_HV_2
VCC_HV_3
VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5
VCC_DMI_1
VCC_DMI_2
VCC_DMI_3
VCC_DMI_4
VTTLF1
VTTLF2
VTTLF3
VTTLF
VTTLF
U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1
B22
B21
A21
BF21
BH20
BG20
BF20
K47
C35
B35
A35
V48
U48
V47
U47
U46
AH48
AF48
AH47
AG47
A8
L1
AB2
2
C149
C149
C132
C132
.47u_4
.47u_4
2.2u_6
2.2u_6
1.05V
321.35mA
+1.05VM_AXF
+1.8VSUS_VCC_SM_CK
C463
C463
.1u_4
.1u_4
C396
C396
1u_4
1u_4
IV&EV Dis/Enable setting
+1.8VSUS_TXLVDS
SP@:INT use 1000pf
EXT use 0 ohm
3.3V
105.3mA
1.05V
1782mA
1.05V
456mA
C406
C406
C429
C429
.47u_4
.47u_4
.47u_4
.47u_4
2
C447
C447
.1u_4
.1u_4
1.05V
FSB-1067
852mA
C126
C126
C129
C129
4.7u_6
4.7u_6
4.7u_6
4.7u_6
Check list : 0.1UH
CRB : 0 ohm
1210 0.1 ?H, 20% 1A
DCR max = 78 m
C389
C389
*10u_8
*10u_8
ESR = 60 m
+1.8VSUS_SMCK_RC
R4731/F_4 R4731/F_4
C385
C385
SP@1000p/50V_4
SP@1000p/50V_4
+3V
R384 10_4R384 10_4
C83
C83
.1u_4
.1u_4
C449
C449
4.7u_6
4.7u_6
1.05V
Internal connect to power
C395
C395
.47u_4
.47u_4
1
External Graphics
(GMCH Integrated Graphics Disable)
VCCSYNC_CRT
VCCA_CRT_DAC
VCCD_LVDS
VCC_TX_LVDS
VCCA_LVDS
VCCA_TVDAC
VCCD_QDAC
VCCA_DAC_BG
VCC_AXG
VCC_AXG_NCTF
+
+
C383
C383
330u_7343
330u_7343
+1.05V
ESR= 12m ohm
L31 0.1uh_8L31 0.1uh_8
1.8V
DDR2-800
124mA
L37 1uh_8L37 1uh_8
1.8V
118.8mA
L30 I@0.1uh_6L30 I@0.1uh_6
C388
C388
I@22u_8
I@22u_8
+1.05V
0805 1UH , Rdc = 0.14 - 0.26.
Max rated current = 220 mA
+VDR_SUS
C466 10u_6C466 10u_6
0805 100 nH, DCR=160 m
+VDR_SUS
+1.05V_SD
D22 CH751D22 CH751
+1.05V
+
+
C453
C453
C374
C374
22u_8
22u_8
220u_7343
220u_7343
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
21
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
GMCH POWER
GMCH POWER
GMCH POWER
1
+1.05V
ZK2
ZK2
ZK2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
3B
3B
10 39Friday, June 27, 2008
10 39Friday, June 27, 2008
10 39Friday, June 27, 2008
3B
of
of
of
5
U26I
U26I
AU48
VSS_1
AR48
VSS_2
AL48
VSS_3
BB47
VSS_4
AW47
VSS_5
AN47
VSS_6
AJ47
VSS_7
AF47
VSS_8
D D
C C
B B
A A
AD47
AB47
BD46
BA46
AY46
AV46
AR46
AM46
BF44
AH44
AD44
AA44
BC43
AV43
AU43
AM43
BG42
AY42
AT42
AN42
AJ42
AE42
BD41
AU41
AM41
AH41
AD41
AA41
BG40
BB40
AV40
AN40
AT39
AM39
AJ39
AE39
BH38
BC38
BA38
AU38
AH38
AD38
AA38
BF37
BB37
AW37
AT37
AN37
AJ37
BG36
BD36
AK15
AU36
M44
C43
N42
U41
M41
G41
H40
N39
U38
C38
H37
C37
Y47
T47
N47
L47
G47
V46
R46
P46
H46
F46
Y44
U44
T44
F44
L42
Y41
T41
B41
E40
L39
B39
Y38
T38
F38
J43
J38
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
CANTIGA_PM
CANTIGA_PM
VSS
VSS
GMCH (CANTIGA)
5
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
4
AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
4
3
U26J
U26J
BG21
VSS_199
L12
VSS_200
AW21
VSS_201
AU21
VSS_202
AP21
VSS_203
AN21
VSS_204
AH21
VSS_205
AF21
VSS_206
AB21
VSS_207
R21
VSS_208
M21
VSS_209
J21
VSS_210
G21
VSS_211
BC20
VSS_212
BA20
VSS_213
AW20
VSS_214
AT20
VSS_215
AJ20
VSS_216
AG20
VSS_217
Y20
VSS_218
N20
VSS_219
K20
VSS_220
F20
VSS_221
C20
VSS_222
A20
VSS_223
BG19
VSS_224
A18
VSS_225
BG17
VSS_226
BC17
VSS_227
AW17
VSS_228
AT17
VSS_229
R17
M17
H17
C17
BA16
AU16
AN16
N16
K16
G16
E16
BG15
AC15
W15
A15
BG14
AA14
C14
BG13
BC13
BA13
AN13
AJ13
AE13
N13
L13
G13
E13
BF12
AV12
AT12
AM12
AA12
J12
A12
BD11
BB11
AY11
AN11
AH11
Y11
N11
G11
C11
BG10
AV10
AT10
AJ10
AE10
AA10
M10
BF9
BC9
AN9
AM9
AD9
G9
B9
BH8
BB8
AV8
AT8
3
VSS_230
VSS_231
VSS_232
VSS_233
VSS_235
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
CANTIGA_PM
CANTIGA_PM
VSS
VSS
VSS NCTF
VSS NCTF
VSS SCB
VSS SCB
NC
NC
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_6
NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42
NC_43
2
AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4
BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1
U24
U28
U25
U29
AJ6
AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17
BH48
BH1
A48
C1
A3
E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48
A47
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
PROJECT :
GMCH VSS
GMCH VSS
GMCH VSS
1
ZK2
ZK2
ZK2
3B
3B
3B
of
of
of
11 39Friday, June 27, 2008
11 39Friday, June 27, 2008
11 39Friday, June 27, 2008
1
5
ICH9M
IV@
EV@
D D
24.9 Ohm pull up to 1.5V
for GLAN_COMPI/O is
required, no matter intel
LAN is used or not.
C C
SATA HDD
ODD (SATA)
C163 15p/50V_4C163 15p/50V_4
C162 15p/50V_4C162 15p/50V_4
+VCCRTC
Internal pull-down
resistors that are
always enabled
23
Y2
Y2
32.768KHZ
32.768KHZ
4 1
R434 1M/F_6R434 1M/F_6
R429 332K/F_4R429 332K/F_4
Internal VRM enabled for
VccSus1_05, VccSus1_5,
VccCL1_5, VccLAN1_05 and
VccCL1_05.
+3V_S5
R441 10K_4R441 10K_4
R461 24.9/F_4R461 24.9/F_4
+1.5V
ACZ_SDIN0(24)
ACZ_SDIN1(24)
SATA_LED#(28)
SATA_RXN1(23)
SATA_RXP1(23)
SATA_TXN1(23)
SATA_TXP1(23)
SATA_RXN4(23)
SATA_RXP4(23)
SATA_TXN4(23)
SATA_TXP4(23)
R181
R181
10M_6
10M_6
CLK_32KX1
CLK_32KX2
RTC_RST#
SRTC_RST#
SM_INTRUDER#
ICH_INTVRMEN
ICH_GPIO56
HDA_BIT_CLK_R
HDA_SYNC_R
HDA_RST#_R
HDA_SDIN2
HDA_SDIN3
HDA_SDOUT_R
T66T66
T60T60
4
U29A
U29A
C23
RTCX1
C24
RTCX2
A25
RTCRST#
F20
SRTCRST#
C22
INTRUDER#
B22
INTVRMEN
A22
LAN100_SLP
E25
GLAN_CLK
C13
LAN_RSTSYNC
F14
LAN_RXD0
G13
LAN_RXD1
D14
LAN_RXD2
D13
LAN_TXD0
D12
LAN_TXD1
E13
LAN_TXD2
B10
GLAN_DOCK#/GPIO56
B28
GLAN_COMPI
B27
GLAN_COMPO
AF6
HDA_BIT_CLK
AH4
HDA_SYNC
AE7
HDA_RST#
AF4
HDA_SDIN0
AG4
HDA_SDIN1
AH3
HDA_SDIN2
AE5
HDA_SDIN3
AG5
HDA_SDOUT
AG7
HDA_DOCK_EN#/GPIO33
AE8
HDA_DOCK_RST#/GPIO34
AG8
SATALED#
AJ16
SATA0RXN
AH16
SATA0RXP
AF17
SATA0TXN
AG17
SATA0TXP
AH13
SATA1RXN
AJ13
SATA1RXP
AG14
SATA1TXN
AF14
SATA1TXP
ICH9M REV 1.0
ICH9M REV 1.0
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
FWH4/LFRAME#
RTCLAN / GLAN
LPCCPU
RTCLAN / GLAN
LPCCPU
LDRQ0#
LDRQ1#/GPIO23
A20GATE
A20M#
DPRSTP#
DPSLP#
FERR#
CPUPWRGD
IGNNE#
INIT#
RCIN#
STPCLK#
THRMTRIP#
SATA4RXN
IHDA
IHDA
SATA4RXP
SATA4TXN
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATA_CLKN
SATA_CLKP
SATA
SATA
SATARBIAS#
SATARBIAS
INTR
SMI#
TP8
NMI
K5
K4
L6
K2
K3
J3
J1
N7
AJ27
AJ25
AE23
H_FERR#_R
AJ26
AD22
AF25
AE22
AG25
L3
AF23
AF24
AH27
H_THERMTRIP_R
AG26
AG27
AH11
AJ11
AG12
AF12
AH9
AJ9
AE10
AF10
AH18
AJ18
SATA_RBIAS_PN
AJ7
AH7
SATABIAS L<0.5"
3
LDRQ0/1# : Internal PU
T81T81
T80T80
R222 8.2K_4R222 8.2K_4
R492 56_4R492 56_4
R219 10K_4R219 10K_4
T62T62
R501
R501
24.9/F_4
24.9/F_4
+3V
+3V
SATA_RXN0 (23)
SATA_RXP0 (23)
SATA_TXN0 (23)
SATA_TXP0 (23)
SATA_RXN5 (29)
SATA_RXP5 (29)
SATA_TXN5 (29)
SATA_TXP5 (29)
CLK_PCIE_SATA# (2)
CLK_PCIE_SATA (2)
LAD0 (22,31)
LAD1 (22,31)
LAD2 (22,31)
LAD3 (22,31)
LFRAME# (22,31)
GATEA20 (31)
H_A20M# (3)
H_PWRGD (3)
H_IGNNE# (3)
H_INIT# (3)
H_INTR (3)
RCIN# (31)
H_NMI (3)
H_SMI# (3)
H_STPCLK# (3)
2ND SATA HDD
eSATA
2
Intel ICH9M
+1.05V
R499
*56_4
*56_4
R491 56_4R491 56_4
R488 *0_4R488 *0_4
No use Thermal trip SB side still PU 56ohm.(Serial R use 0ohm)
Use Thermal trip can share PU for CPU and SB side(And Serial R use 54.9 ohm)
PU L<2"
DPRSTP# , Daisy Chain
*56_4
*56_4
(SB>Power>NB>CPU)
ICH_DPRSTP# (3,6,34)
H_DPSLP# (3)
+1.05V
PM_THRMTRIP# (3,6)
Layout note:
R248
R248
R499
+1.05V
R493
R493
56_4
56_4
1
AJSLB8Q0T03
H_FERR# (3)
HD Audio
B B
HDA_SDOUT_R
Weak integrated PD on the HDA_SDOUT pin.
HDA_SYNC_R
Weak integrated PD on the HDA_SYNC pins
R274 *E@33_4R274 *E@33_4
R275 I@33_4R275 I@33_4
R272 33_4R272 33_4
R269 *E@33_4R269 *E@33_4
R258 I@33_4R258 I@33_4
R270 33_4R270 33_4
R268 33_4R268 33_4
MXM_SDOUT_HDMI (17)
HDA_SDOUT_HDMI (6)
ACZ_SDOUT_MDC (24)
ACZ_SDOUT_AUDIO (24)
C256
C256
*10p/50V_4
*10p/50V_4
MXM_SYNC_HDMI (17)
HDA_SYNC_HDMI (6)
ACZ_SYNC_MDC (24)
ACZ_SYNC_AUDIO (24) ACZ_RST#_AUDIO (24)
C255
C255
*10p/50V_4
*10p/50V_4
HDA_BIT_CLK_R
24.000 MHz is output from the ICH9M.
R265 *E@33_4R265 *E@33_4
R266 I@33_4R266 I@33_4
R267 33_4R267 33_4
R264 33_4R264 33_4R276 33_4R276 33_4
HDA_RST#_R
HDA_SDIN3
HDA_SDIN2
C252
C252
*10p/50V_4
*10p/50V_4
C254
C254
*10p/50V_4
*10p/50V_4
R254 *E@33_4R254 *E@33_4
R255 I@33_4R255 I@33_4
R256 33_4R256 33_4
R253 33_4R253 33_4
R259 *E@0_4R259 *E@0_4
R257 I@0_4R257 I@0_4
MXM_BIT_CLK_HDMI (17)
HDA_BIT_CLK_HDMI (6)
BIT_CLK_MDC (24)
BIT_CLK_AUDIO (24)
C253
C253
*10p/50V_4
*10p/50V_4
MXM_RST#_HDMI (17)
HDA_RST#_HDMI (6)
ACZ_RST#_MDC (24)
MXM_SDIN_HDMI (17)
HDA_SDIN_HDMI (6)
South Bridge Strap Pin (1/3)
Pin Name
HDA_DOCK_EN/
GPIO33
A A
SATALED#
TP3
HDA_SDOUT
Strap description
Flash Descriptor Security
Override Strap
PCI Express Lane Reversal
(Lanes 1-4)
XOR Chain Entrance
XOR Chain Entrance /PCI Express*
Port Config 1 bit 1(Port 1-4)
5
Sampled
PWROK
PWROK
PWROK
PWROK
Configuration PU/PD
0 = The Flash Descriptor Security will be overridden.
1 = The security measures defined
in the Flash Descriptor will be in effect
Internal PU
ICH_TP3
HDA_SDOUT
0
0
0
11
4
RSVD
Enter XOR Chain
1
Normal opration(Default)
01
Set PCIE port config bit 1
Description
This strap should only be enabled in manufacturing
environments using an external pull-up resistor.
ICH_TP3(14)
HDA_SDOUT_R
ICH_TP3
3
R451 *1K_4R451 *1K_4
R273 *1K_4R273 *1K_4
+3V
RTC
Pjt: BCBAT54CZ04
Ons: BCBAT54CZ70
+3VPCU
VCCRTC_1
20MIL
R424
R424
1K_4
1K_4
1 3
VCCRTC_2
20MIL
RTC_BAT
RTC_BAT
2
2
1
1
CN34
CN34
Pitch: 1,25mm; Height: 1.95mm
Change type
2
D23
D23
BAT54C
BAT54C
2
RTC_N01
Q18
Q18
MMBT3904
MMBT3904
RTC_N03
+VCCRTC
20MIL
R427 20K_6R427 20K_6
C417
C417
1u_4
1u_4
R428 20K_6R428 20K_6
R341 16K_6R341 16K_6
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
R338
R338
68.1K/F_4
68.1K/F_4
R336
R336
150K/F_6
150K/F_6
+5VPCU
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
ICH9M HOST
ICH9M HOST
ICH9M HOST
SRTC_RST#
12
C410
C410
1u_4
1u_4
RTC_RST#
12
C416
C416
1u_4
1u_4
ZK2
ZK2
ZK2
12 39Wednesday, July 09, 2008
12 39Wednesday, July 09, 2008
12 39Wednesday, July 09, 2008
1
G1
G1
*SHORT_ PAD
*SHORT_ PAD
G2
G2
*SHORT_ PAD
*SHORT_ PAD
of
of
of
3B
3B
3B
Loading...