Quanta ZHVA Schematic

5

4

3

2

1

ZHVA Virgo_GL UMA(11.6")

01

D D

C C

B B

3.3V EC code
SPI ROM(8Mb)

PAGE 13

Thermal senser

PAGE 16

Keyboard

A A

PAGE 15

Intel Gemini Lake Platform Block Diagram

DDR4 2333
Memory down
2 Channel 1Rx16

PAGE 10,11

SATA - 1st HDD
Package : 9.5 (mm)
Power :

PAGE 17

SATA SSD
M.2 NGFF

PAGE 17

1.8V BIOS+TXE
SPI ROM(64Mb)

PAGE 5

Touch Pad

PAGE 15

PS2

Embedded Controller

IT8987

Power :

Package : LQPF128

Size : 14 x 14 (mm)

Speaker

Combo Jack
Headphone + MIC

Digital -MIC

SATA0 6GB/s

SATA0 6GB/s

SPI Interface

PAGE 13

PAGE 19

PAGE 19

PAGE 19

DDR4

LPC Interface

Port0

Port1

I2C

32.768KHz
PAGE 6

Intel Gemini Lake

Package : FCBG 1170
Size : 24 x 31 (mm)

PAGE 2~9

Audio Codec

ALC255

Power :

Package : QFN

Size : 6 x 6 (mm)

Azalia

PAGE 19

PCIE2

19.2MHz
PAGE 4

DDI 0

x8

SMBus

USB 2.0 Interface

USB 3.0

Port0

USB3.0 Port

PAGE 18

PCIE3

PCIE Gen 2 x 1 Lane

M.2 NGFF
WLAN / BT Combo

PAGE 21

LAN sub board
RTL8111H

PAGE 22

EMMC 5.0

SDIN7DP4

32GB/64GB

Port0

Port4

HDMI Conn

eDP

P17

G sensor/sensor HUB

Port2

USB2.0 Port

PAGE 17

USB Board

DDR4 1.2V(RT8231BGQW)

PAGE 14

PAGE 14

Touch Screen

PAGE 20

Port5 Port6

Charger(BQ24737RGRR)

PAGE 26

SYSTEM 3V/5V
(SY8286B&8288)

+1.05V (M5671RE1U)

Camera

PAGE 14PAGE 14

PAGE 23

PAGE 24

PAGE 25

Card reader

RTS5170

USB Board

Port7

PAGE 18

+VCCGI (RT3601EAGQW)

PAGE 26

+VNN (RT3601EAGQW)

PAGE 27

Thermal / Discharge

PAGE 30

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Thursday, August 09, 2018

Date: Sheet of

Thursday, August 09, 2018

Date: Sheet of

Thursday, August 09, 2018

5

4

3

2

Date: Sheet of

PROJECT :

Intel Block Diagram

Intel Block Diagram

Intel Block Diagram

ZHVA

ZHVA

ZHVA

1A

1A

1A

341

341

1

341

5

4

GLK ULT (DDR4)

3

2

+1.2VSUS_ Q[7]

1

02

M_A_DQ[63:0][10]

D D

C C

B B

M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31

BJ36
BK37
BJ35
BL36
BJ39
BL40
BJ40
BK41
BA35
AY33
BA33
AY35
BA37
AY37
AY39
BA39
BL34
BL30
BJ29
BK29
BJ33
BK33
BJ34
BJ30

BD29

BF29

BH29

BF33
BC29
BD33

BF35
BH35

AR53

AP55

AP53
AN54
AU54

AV53

AV55
AW53
AU51
AU48
AU49

BA46

BA48

BA49

BA51
AR51

AY55

BA54

BA53

AY53
BC53
BD55

BE54
BD53
AN43
AN44
AR48
AU41
AU43
AN41
AN39
AU44

U23A

MEM_CH0_DQ 40
MEM_CH0_DQ 41
MEM_CH0_DQ 42
MEM_CH0_DQ 43
MEM_CH0_DQ 44
MEM_CH0_DQ 45
MEM_CH0_DQ 46
MEM_CH0_DQ 47
MEM_CH0_DQ 32
MEM_CH0_DQ 33
MEM_CH0_DQ 34
MEM_CH0_DQ 35
MEM_CH0_DQ 36
MEM_CH0_DQ 37
MEM_CH0_DQ 38
MEM_CH0_DQ 39
MEM_CH0_DQ 56
MEM_CH0_DQ 57
MEM_CH0_DQ 58
MEM_CH0_DQ 59
MEM_CH0_DQ 60
MEM_CH0_DQ 61
MEM_CH0_DQ 62
MEM_CH0_DQ 63
MEM_CH0_DQ 48
MEM_CH0_DQ 49
MEM_CH0_DQ 50
MEM_CH0_DQ 51
MEM_CH0_DQ 52
MEM_CH0_DQ 53
MEM_CH0_DQ 54
MEM_CH0_DQ 55

MEM_CH0_DQ 0
MEM_CH0_DQ 1
MEM_CH0_DQ 2
MEM_CH0_DQ 3
MEM_CH0_DQ 4
MEM_CH0_DQ 5
MEM_CH0_DQ 6
MEM_CH0_DQ 7
MEM_CH0_DQ 8
MEM_CH0_DQ 9
MEM_CH0_DQ 10
MEM_CH0_DQ 11
MEM_CH0_DQ 12
MEM_CH0_DQ 13
MEM_CH0_DQ 14
MEM_CH0_DQ 15
MEM_CH0_DQ 16
MEM_CH0_DQ 17
MEM_CH0_DQ 18
MEM_CH0_DQ 19
MEM_CH0_DQ 20
MEM_CH0_DQ 21
MEM_CH0_DQ 22
MEM_CH0_DQ 23
MEM_CH0_DQ 24
MEM_CH0_DQ 25
MEM_CH0_DQ 26
MEM_CH0_DQ 27
MEM_CH0_DQ 28
MEM_CH0_DQ 29
MEM_CH0_DQ 30
MEM_CH0_DQ 31

DDR4_LP3_LP4DDR4_LP3_LP4

MEM_CH0_DQ S0_P

MEM_CH0_DQ S0

MEM_CH0_DQ S1_P

MEM_CH0_DQ S1

MEM_CH0_DQ S2_P

MEM_CH0_DQ S2

MEM_CH0_DQ S3_P

MEM_CH0_DQ S3

MEM_CH0_DQ S4_P

MEM_CH0_DQ S4

MEM_CH0_DQ S5_P

MEM_CH0_DQ S5

MEM_CH0_DQ S6_P

MEM_CH0_DQ S6

MEM_CH0_DQ S7_P

MEM_CH0_DQ S7

DDR0

1 OF 13

NCTF1
NCTF2
NCTF3

MEM_CH0_O DT1

MEM_CH0_CS 1

NCTF4

MEM_CH0_O DT0

MEM_CH0_CS 0
MEM_CH0_CK E1
MEM_CH0_CK E0

MEM_CH0_CL K0_P

MEM_CH0_CL K0

MEM_CH0_CL K1_P

MEM_CH0_CL K1

MEM_CH0_MA 0

MEM_CH0_MA 1

MEM_CH0_MA 2
MEM_CH0_MA 10
MEM_CH0_MA 13
MEM_CH0_MA 16

MEM_CH0_B A1

MEM_CH0_B A0

MEM_CH0_B G1

MEM_CH0_A CT

MEM_CH0_MA 3

MEM_CH0_MA 4

MEM_CH0_MA 5

MEM_CH0_MA 6

MEM_CH0_MA 7

MEM_CH0_MA 8

MEM_CH0_MA 9
MEM_CH0_MA 11
MEM_CH0_MA 12
MEM_CH0_MA 14
MEM_CH0_MA 15

MEM_CH0_B G0

MEM_CH0_V REFDQ
MEM_CH0_V REFCA

M_A_DQSP 0

AT53

M_A_DQSN0

AT55

M_A_DQSP 1

AW49

M_A_DQSN1

AW48

M_A_DQSP 2

BC54

M_A_DQSN2

BB53

M_A_DQSP 3

AR41

M_A_DQSN3

AR43

M_A_DQSP 4

AV37

M_A_DQSN4

AV35

M_A_DQSP 5

BL38

M_A_DQSN5

BJ38

M_A_DQSP 6

BF31

M_A_DQSN6

BD31

M_A_DQSP 7

BJ32

M_A_DQSN7

BK31
BG54

BH54
BJ42
BF39
BK43

BL44

M_A_ODT0

BD39

M_A_CS#0

BJ43
BF54

M_A_CKE0

BF55

M_A_CLK0

BE49

M_A_CLK0 #

BE51
BC49

BC48

M_A_A0

BD45

M_A_A1

BH50

M_A_A2

BH47

M_A_A10

BF45

M_A_A13

BH43

M_A_A16

BD41

M_A_BA#1

BH51

M_A_BA#0

BD43

M_A_BG#1

BF43

M_A_ACT#

BF41

M_A_A3

BG52

M_A_A4

BK45

M_A_A5

BJ46

M_A_A6

BJ44

M_A_A7

BJ47

M_A_A8

BJ45

M_A_A9

BK47

M_A_A11

BJ51

M_A_A12

BJ52

M_A_A14

BJ48

M_A_A15

BJ50

M_A_BG#0

BL50

M0_VREF_DQ

AY31
AV29

R142 *0_5%_4

Default no stuff

M_B_DQ[63:0][11]

M_A_DQSP 0 [10]
M_A_DQSN0 [10]

M_A_DQSP 1 [10]
M_A_DQSN1 [10]

M_A_DQSP 2 [10]
M_A_DQSN2 [10]

M_A_DQSP 3 [10]
M_A_DQSN3 [10]

M_A_DQSP 4 [10]
M_A_DQSN4 [10]

M_A_DQSP 5 [10]
M_A_DQSN5 [10]

M_A_DQSP 6 [10]
M_A_DQSN6 [10]

M_A_DQSP 7 [10]
M_A_DQSN7 [10]

M_A_CS#0 [10]
M_A_CKE0 [10]
M_A_CLK0 [10]

M_A_CLK0 # [10]

M_A_A0 [10]
M_A_A1 [10]
M_A_A2 [10]
M_A_A10 [10]
M_A_A13 [10]
M_A_A16 [10]
M_A_BA#1 [10]
M_A_BA#0 [10]
M_A_BG#1 [10]
M_A_ACT# [10]
M_A_A3 [10]

M_A_A4 [10]
M_A_A5 [10]
M_A_A6 [10]
M_A_A7 [10]
M_A_A8 [10]
M_A_A9 [10]
M_A_A11 [10]
M_A_A12 [10]
M_A_A14 [10]
M_A_A15 [10]
M_A_BG#0 [10]

TP5

+VREF_CA_CPU [10]

VREF trace must be at least
20 mils wide and space

M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31

AN15
AN17
AU12
AN12
AN13
AU13
AU15

BA10
BJ26

BL26
BJ27
BK27
BJ23
BK23
BJ22
BL22
BD27
BF27
BH27
BC27
BH21
BF23
BD23
BF21
BK19
BJ20
BL20
BJ21
BJ17
BJ16
BK15
BL16
BA21
AY23
BA23
BA17
AY21
AY17
AY19
BA19

AY3
BD3
BD1
BC3
AY1
BA3
BA2
BE2
AR8

AP3
AU2
AV3

AW3

AN2
AP1
AR3
AV1
AR5
BA8
AU7
AU5
BA5
BA7
AU8

U23B

MEM_CH1_DQ 40
MEM_CH1_DQ 41
MEM_CH1_DQ 42
MEM_CH1_DQ 43
MEM_CH1_DQ 44
MEM_CH1_DQ 45
MEM_CH1_DQ 46
MEM_CH1_DQ 47
MEM_CH1_DQ 32
MEM_CH1_DQ 33
MEM_CH1_DQ 34
MEM_CH1_DQ 35
MEM_CH1_DQ 36
MEM_CH1_DQ 37
MEM_CH1_DQ 38
MEM_CH1_DQ 39
MEM_CH1_DQ 56
MEM_CH1_DQ 57
MEM_CH1_DQ 58
MEM_CH1_DQ 59
MEM_CH1_DQ 60
MEM_CH1_DQ 61
MEM_CH1_DQ 62
MEM_CH1_DQ 63
MEM_CH1_DQ 48
MEM_CH1_DQ 49
MEM_CH1_DQ 50
MEM_CH1_DQ 51
MEM_CH1_DQ 52
MEM_CH1_DQ 53
MEM_CH1_DQ 54
MEM_CH1_DQ 55

MEM_CH1_DQ 0
MEM_CH1_DQ 1
MEM_CH1_DQ 2
MEM_CH1_DQ 3
MEM_CH1_DQ 4
MEM_CH1_DQ 5
MEM_CH1_DQ 6
MEM_CH1_DQ 7
MEM_CH1_DQ 8
MEM_CH1_DQ 9
MEM_CH1_DQ 10
MEM_CH1_DQ 11
MEM_CH1_DQ 12
MEM_CH1_DQ 13
MEM_CH1_DQ 14
MEM_CH1_DQ 15
MEM_CH1_DQ 16
MEM_CH1_DQ 17
MEM_CH1_DQ 18
MEM_CH1_DQ 19
MEM_CH1_DQ 20
MEM_CH1_DQ 21
MEM_CH1_DQ 22
MEM_CH1_DQ 23
MEM_CH1_DQ 24
MEM_CH1_DQ 25
MEM_CH1_DQ 26
MEM_CH1_DQ 27
MEM_CH1_DQ 28
MEM_CH1_DQ 29
MEM_CH1_DQ 30
MEM_CH1_DQ 31

R156 *0_5%_4

DDR4_LP3_LP4DDR4_LP3_LP4

MEM_CH1_DQ S0_P

MEM_CH1_DQ S0

MEM_CH1_DQ S1_P

MEM_CH1_DQ S1

MEM_CH1_DQ S2_P

MEM_CH1_DQ S2

MEM_CH1_DQ S3_P

MEM_CH1_DQ S3

MEM_CH1_DQ S4_P

MEM_CH1_DQ S4

MEM_CH1_DQ S5_P

MEM_CH1_DQ S5

MEM_CH1_DQ S6_P

MEM_CH1_DQ S6

MEM_CH1_DQ S7_P

MEM_CH1_DQ S7

DDR1

2 OF 13

M_A_ODT0_MDM_A_ODT0

M_A_ODT0_MD [10]

MEM_CH1_MA 0
MEM_CH1_MA 1
MEM_CH1_MA 2

MEM_CH1_MA 3
MEM_CH1_MA 10
MEM_CH1_MA 13
MEM_CH1_MA 16

MEM_CH1_B A0

MEM_CH1_B A1

MEM_CH1_B G1

MEM_CH1_A CT
MEM_CH1_MA 11

MEM_CH1_MA 12
MEM_CH1_MA 14
MEM_CH1_MA 15

MEM_CH1_B G0

MEM_CH1_MA 4

MEM_CH1_MA 5

MEM_CH1_MA 6

MEM_CH1_MA 7

MEM_CH1_MA 8

MEM_CH1_MA 9

MEM_CH1_CL K0_P

MEM_CH1_CL K0

MEM_CH1_CL K1_P

MEM_CH1_CL K1

NCTF3
NCTF4
NCTF1

MEM_CH1_CS 1
MEM_CH1_O DT1

MEM_CH1_CS 0
MEM_CH1_O DT0

NCTF2
MEM_CH1_CK E0
MEM_CH1_CK E1

MEM_CH0_RCOMP

MEM_CH1_RE SET

MEM_CH1_RCOMP

MEM_CH1_V REFCA
MEM_CH1_V REFDQ

MEM_CH0_RE SET

MA_DRAMRST# MB_DRAMRST#

M_B_DQSP 0

BJ24

M_B_DQSN0

BK25

M_B_DQSP 1

BD25

M_B_DQSN1

BF25

M_B_DQSP 2

BL18

M_B_DQSN2

BJ18

M_B_DQSP 3

AV19

M_B_DQSN3

AV21

M_B_DQSP 4

AR13

M_B_DQSN4

AR15

M_B_DQSP 5

BB3

M_B_DQSN5

BC2

M_B_DQSP 6

AW7

M_B_DQSN6

AW8

M_B_DQSP 7

AT1

M_B_DQSN7

AT3

M_B_A0

BH9

M_B_A1

BC13

M_B_A2

BD11

M_B_A3

BD13

M_B_A10

BF11

M_B_A13

BE5

M_B_A16

BH5

M_B_BA#0

BH6

M_B_BA#1

BF13

M_B_BG#1

BG4

M_B_ACT#

BE7

M_B_A11

BK11

M_B_A12

BJ12

M_B_A14

BK9

M_B_A15

BJ11

M_B_BG#0

BJ10

M_B_A4

BJ4

M_B_A5

BL6

M_B_A6

BJ5

M_B_A7

BJ9

M_B_A8

BJ6

M_B_A9

BJ8

M_B_CLK0

BF17

M_B_CLK0 #

BD17
BF15

BH15
BJ13

BL12
BF1
BF2
BC7

M_B_CS#0

BH2

M_B_ODT0

BC8

R154 *0_5%_4

BG2

M_B_CKE0

BK13
BJ14

MEM_CH0_RCOMP

AY29

MB_DRAMRST#

BC15

MEM_CH1_RCOMP

AY27

M1_VREF_CA

AV27
AY25

BC43

M1_VREF_DQ

MA_DRAMRST#

R141 *0_5%_4

TP4

Default no stuff

colsed to CPU pin within 100 mils

C125
*1000p/5 0V_4

R137
*10_5%_4

M_B_DQSP 0 [11]
M_B_DQSN0 [11]

M_B_DQSP 1 [11]
M_B_DQSN1 [11]

M_B_DQSP 2 [11]
M_B_DQSN2 [11]

M_B_DQSP 3 [11]
M_B_DQSN3 [11]

M_B_DQSP 4 [11]
M_B_DQSN4 [11]

M_B_DQSP 5 [11]
M_B_DQSN5 [11]

M_B_DQSP 6 [11]
M_B_DQSN6 [11]

M_B_DQSP 7 [11]
M_B_DQSN7 [11]

M_B_A0 [11]
M_B_A1 [11]
M_B_A2 [11]
M_B_A3 [11]
M_B_A10 [11]
M_B_A13 [11]
M_B_A16 [11]
M_B_BA#0 [11]
M_B_BA#1 [11]
M_B_BG#1 [11]
M_B_ACT# [11]

M_B_A11 [11]
M_B_A12 [11]
M_B_A14 [11]
M_B_A15 [11]
M_B_BG#0 [11]
M_B_A4 [11]
M_B_A5 [11]
M_B_A6 [11]
M_B_A7 [11]
M_B_A8 [11]
M_B_A9 [11]

M_B_CLK0 [11]
M_B_CLK0 # [11]

R151 110_1%_ 4

R150 110_1%_ 4

VREF trace must be at least
20 mils wide and space

C129
*1000p/5 0V_4

R148
*10_5%_4

M_B_CS#0 [11]
M_B_ODT0_MD [11]

M_B_CKE0 [11]

R179 , R183 close to CPU

Trace length < 500 mils
Trace width=15 mils
Trace spacing = 20mils

+VREFDQ_SB_M3 [11]

DRAMRST-MEMORY DOWN

+1.2VSUS_ Q +1.2VSUS_ Q

A A

5

CPU

MA_DRAMRST# MB_DRAMRST#

Trace length < 4500 mils, 50 ohm impendence
Trace spacing = 15mils

R144
1K_1%_4

R152 *S_4

4

C132
*0.1u/16V_4

MEMORY DOWN

M_A_DRAMRS T# [10]

Trace length < 4500 mils, 50 ohm impendence
Trace spacing = 15mils

CPU

3

R153
1K_1%_4

R149 *S_4

C134
*0.1u/16V_4

MEMORY DOWN

M_B_DRAMRS T# [11]

2

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Nu mber Rev

Size Document Nu mber Rev

Size Document Nu mber Rev

Date: Sheet of

Thursday, Augu st 09, 2018

Date: Sheet of

Thursday, Augu st 09, 2018

Date: Sheet of

Thursday, Augu st 09, 2018

PROJECT :

GLK(MEMORY)

GLK(MEMORY)

GLK(MEMORY)

ZHVA

ZHVA

ZHVA

2 34

2 34

1

2 34

1A

1A

1A

5

Gemini lake (SATA , ODD, CLK ,USB,PCIE)

U23D

<1000mil

PCIE_CLK_RCOMP

PCIE_TXP2_LAN_C
PCIE_TXN2_LAN_C

L10

PCIE_REF_CLK_RCOMP

R12

PCIE_CLKOUT0P

R10

PCIE_CLKOUT0N

N7

PCIE_CLKOUT1P

N5

PCIE_CLKOUT1N

R7

PCIE_CLKOUT2P

R5

PCIE_CLKOUT2N

N8

PCIE_CLKOUT3P

N10

PCIE_CLKOUT3N

E2

PCIE_P0_TXP

F2

PCIE_P0_TXN

G7

PCIE_P0_RXP

H6

PCIE_P0_RXN

A7

PCIE_P1_TXP

C7

PCIE_P1_TXN

D4

PCIE_P1_RXP

E5

PCIE_P1_RXN

C9

PCIE_P2_TXP

B9

PCIE_P2_TXN

E7

PCIE_P2_RXP

F6

PCIE_P2_RXN

A46

PCIE_CLKREQ0

C45

PCIE_CLKREQ1

B45

PCIE_CLKREQ2

C44

PCIE_CLKREQ3

F47

PCIE_WAKE0

D47

PCIE_WAKE1

F45

PCIE_WAKE2

D50

PCIE_WAKE3

J3

SATA_P0_TXP

J2

SATA_P0_TXN

J7

SATA_P0_RXP

J5

SATA_P0_RXN

SATA/USB3

PCIe

USB3

PCIe/USB3

SSIC

SATA

USB2

4 OF 13

R225 56_1%_4

D D

LAN

2.5~12 inch(Gen1)

C C

LAN

WLAN4~12 inch

PCIE_TXP2_LAN[22]
PCIE_TXN2_LAN[22]

PCIE_RXP2_LAN[22]
PCIE_RXN2_LAN[22]

CLK_PCIE_LAN_REQ#[22]

PCIE_CLKREQ_WLAN#[21]

SATA HDD

CLK_PCIE_LANP[22]
CLK_PCIE_LANN[22]

CLK_PCIE_WLANP[21]
CLK_PCIE_WLANN[21]

C421 0.1u/16V_4
C422 0.1u/16V_4

SATA_TXP0[17]
SATA_TXN0[17]

SATA_RXP0[17]
SATA_RXN0[17]

CLK_PCIE_SSD_REQ#
PCIE_CLKREQ1
CLK_PCIE_LAN_REQ#
PCIE_CLKREQ_WLAN#

PCIE_LAN_WAKE#
PCIE_WLAN_WAKE#

4

SATA_P1_USB3_P5_TXP
SATA_P1_USB3_P5_TXN

SATA_P1_USB3_P5_RXP
SATA_P1_USB3_P5_RXN

USB3_P0_TXP
USB3_P0_TXN

USB3_P0_RXP
USB3_P0_RXN

USB3_P1_TXP
USB3_P1_TXN

USB3_P1_RXP
USB3_P1_RXN

PCIE_P3_USB3_P4_TXP

PCIE_P3_USB3_P4_TXN
PCIE_P3_USB3_P4_RXP

PCIE_P3_USB3_P4_RXN

PCIE_P4_USB3_P3_TXP

PCIE_P4_USB3_P3_TXN
PCIE_P4_USB3_P3_RXP

PCIE_P4_USB3_P3_RXN

PCIE_P5_USB3_P2_TXP

PCIE_P5_USB3_P2_TXN
PCIE_P5_USB3_P2_RXP

PCIE_P5_USB3_P2_RXN

PCIE2_USB3_SATA3_RCOMP

PCIE2_USB3_SATA3_RCOMP_P

USB2_DP0
USB2_DN0

USB2_DP1
USB2_DN1

USB2_DP2
USB2_DN2

USB2_DP3
USB2_DN3

USB2_DP4
USB2_DN4

USB2_DP5
USB2_DN5

USB2_DP6
USB2_DN6

USB2_DP7
USB2_DN7

USB2_RCOMP

USB2_DUALROLE
USB2_VBUS_SNS

USB2_OC0
USB2_OC1

NC1
NC2

NC5
NC4

NC3

H1
H2

H4
G5

B15
C15

F15
D15

C14
A14

J11
H11

PCIE_TXP3_WLAN_C

C10

PCIE_TXN3_WLAN_C

A10
H9

F9
C11

B11
D11

F11
B13

C13
F13

D13

PCIE_RCOMPN

C5

PCIE_RCOMPP

C6

AA10
AA8

W13
W12

U15

U7
U5

N2
N3

L2
L3

R13
R15

M1
M3

R2
R3

P1
P3

U8
U10

U12

USBCOMP
USB_OTG_ID

V1

USB_VBUS_SNS

V3

USB_OC0#

U54

USB_OC1#

U53

SATA_TXP1 [17]
SATA_TXN1 [17]

SATA_RXP1 [ 17]

SATA_RXN1 [17]

USB30_TX0+ [18]

USB30_TX0- [18]

USB30_RX0+ [18]

USB30_RX0- [18]

C426 0.1u/16V_4
C428 0.1u/16V_4

R245 100_1%_4

USBP0+ [ 18]
USBP0- [ 18]

USBP2+ [ 18]
USBP2- [ 18]

USBP4+ [ 21]
USBP4- [ 21]

USBP_TOUCH+ [14]
USBP_TOUCH- [14]

USBP6_CCD+ [14]
USBP6_CCD- [14]

USB_CAR7+ [18]
USB_CAR7- [18]

R196 113_1%_4

R205 *10K_5%_4
R206 *10K_5%_4

M.2 SATA SSD

SB3.0

U

USB2 .0

BT

Touch Panel

CCD

Cardreader

R223 *0_5%_4
R270 *0_5%_4

PCIE_TXP3_WLAN [21]
PCIE_TXN3_WLAN [21]

PCIE_RXP3_WLAN [21]
PCIE_RXN3_WLAN [21]

USB_OC0# [9]

USB_OC1# [18]

3

+1.8V_S5

Near CPU

I2C4_SDA

R2212K_1%_4

I2C4_SCL

R2182K_1%_4

I2C5_SDA

R4722K_1%_4

I2C5_SCL

R4672K_1%_4

I2C6_SDA

R2902K_1%_4

I2C6_SCL

R2912K_1%_4

I2C standard/fast mode
I2C total lenght is about 4500 mils = 4.5inchs
Cb = 4.5*5pF +7pF = 29.5pF
PU resistor = 2K ohm

：

2~8 inchUSB3.0

I2C4_SCL[15]
I2C4_SDA[15]

I2C5_SCL[20]
I2C5_SDA[20]

I2C6_SCL[20]
I2C6_SDA[20]

SMB_SOC_CLK[9]

TP18

R246 33_5%_4

TP17

R248 150_1%_4

33 ohm resistor must be placed at a distance <2000mi
Minimum Length forBRI/RGI signals is3000 mils /76.2 mm

WLAN

2.5~12 inch(Gen1)

CNVI_BRI_DT[9]

3~12 inch

+1.8V_S5
+1.8V

Touch PAD

Sensor HUB

R

eseve for Gsensor

I2C4_SCL
I2C4_SDA

I2C5_SCL
I2C5_SDA

I2C6_SCL
I2C6_SDA

SMB1ALERT#
SMB_SOC_CLK
SMB_SOC_DAT

CNVI_BRI_DT_CCNVI_BRI_DT

CNVI_RF_RESET#

CNVI_WT_RCOMP

U49
U51

U46
U48

AA39
AA41

R44
R43

R49

R51

C50

A50

C48

C47

B47

C46

A26

B27

C27

H29

H31

M31
P31

D29

F29
F35

D35

J35

H35

L31
J31

J29
F19

H17

J17
D19
D17
F17

F33

U23I

SIO_I2C0_SCL
SIO_I2C0_SDA

SIO_I2C1_SCL
SIO_I2C1_SDA

SIO_I2C2_SCL
SIO_I2C2_SDA

SIO_I2C3_SCL
SIO_I2C3_SDA

SIO_I2C4_SCL
SIO_I2C4_SDA

SIO_I2C5_SCL
SIO_I2C5_SDA

SIO_I2C6_SCL
SIO_I2C6_SDA

SIO_I2C7_SCL
SIO_I2C7_SDA

SMB_ALERT
SMB_CLK
SMB_DATA

CNV_WGR_CLK_P
CNV_WGR_CLK

CNV_WGR_D0_P
CNV_WGR_D0

CNV_WGR_D1_P
CNV_WGR_D1

CNV_WT_CLK_P
CNV_WT_CLK

CNV_WT_D0_P
CNV_WT_D0

CNV_WT_D1_P
CNV_WT_D1

CLKIN_XTAL_LCP
XTAL_CLKREQ

CNV_BRI_DT
CNV_BRI_RSP
CNV_RGI_DT
CNV_RGI_RSP
CNV_RF_RESET

CNV_WT_RCOMP

ls/50.8 mm from SoC

SMBUS set 3.3V

2

LPSS_I2C

LPSS SMBus

CNVI

LPSS_SPI

LPSS_UART

6 OF 13

+1.8V_S5[4,5,6,7,9,12,15,21,22,23,27,29]
+1.8V[4,14,17,20,22,29,30]
+3V_S5[6,7,12,13,15,22,24,26,29]
+3V[4,5,12,13,14,16,17,18,19,20,21,22,24,25,26,27,28,29,30]

SIO_UART0_TXD
SIO_UART0_RXD
SIO_UART0_RTS
SIO_UART0_CTS

SIO_UART2_TXD
SIO_UART2_RXD
SIO_UART2_RTS
SIO_UART2_CTS

1

SIO_SPI_0_CLK
SIO_SPI_0_TXD

SIO_SPI_0_RXD
SIO_SPI_0_FS0
SIO_SPI_0_FS1

SIO_SPI_2_CLK
SIO_SPI_2_TXD

SIO_SPI_2_RXD
SIO_SPI_2_FS0
SIO_SPI_2_FS1
SIO_SPI_2_FS2

03

M39
J37

L39
L37
J39

M37
M33

P35
P33
P37
L35

N54
P53
N53
M55

L54
M53
K53
L53

GPIO_65
GPIO_64

GPIO_65
GPIO_64

GPIO_79 [9]
GPIO_83 [9]
GPIO_80 [9]

GPIO_81 [9,21]
GPIO_84 [9]
GPIO_89 [9]
GPIO_85 [9]

GPIO_86 [9]
GPIO_87 [9]

GPIO_61 [9]

TP49

GPIO_62 [9]

TP51

GPIO_65 [9]
GPIO_66 [9]

GPIO_67 [21]

TP53

TP50

B B

USB_VBUS_SNS

3

+1.8V_S5

R457
*10K_5%_4

R452
*S_4

SoC

+1.8V_S5

R299 *1K_1%_4
R298 *1K_1%_4
R287 *1K_1%_4

+1.8V_S5

R519 10K_5%_4
R280 *10K_5%_4
R273 *10K_5%_4
R520 10K_5%_4

+3V_S5

USB_OTG_ID

R461 *0_5%_4

4

R261
*10K_5%_4

PCIE_LAN_WAKE#

PCIE_WLAN_WAKE#

A A

+1.8V_S5

R512
*10K_5%_4

5

PCIE_LAN_WAKE# [22]

PCIE_WLAN_WAKE# [12]

PCIE_CLKREQ1
PCIE_CLKREQ_WLAN#
CLK_PCIE_LAN_REQ#
CLK_PCIE_SSD_REQ#

level shift already PU

SMBus

SMB_SOC_CLK
SMB_SOC_DAT

2

+3V_S5

R297
1K_1%_4

GML S5

SMB_SOC_DAT
SMB_SOC_CLK
SMB1ALERT#

R296
1K_1%_4

+3V_S5

R286 *1K_1%_4

SMB1ALERT#

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

ZHVA

PROJECT :

ZHVA

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

GLK(PCIE/USB/SATA/CNVI)

GLK(PCIE/USB/SATA/CNVI)

GLK(PCIE/USB/SATA/CNVI)

Date: Sheet of

Thursday, August 09, 2018

Date: Sheet of

Thursday, August 09, 2018

Date: Sheet of

Thursday, August 09, 2018

1

ZHVA

3 34

3 34

3 34

1A

1A

1A

5

4

3

2

1

Gemini lake (DISPLAY,eDP)

U23C

AC12
AC10

AE12
AE13

AC15
AC17

AE10

AH1
AH3

AE2
AE3

AJ2
AJ3

AG2
AG3

C39
B43

C43

AA2
AA3

Y3
Y1

AD1
AD3

AC2
AC3

AC7
AC5

C42
A42
C38

AE8
AE5

AE7

W17
W15

B39
B41

C40
C41

AA5
AA7

DDI0_TXP_0
DDI0_TXN_0

DDI0_TXP_1
DDI0_TXN_1

DDI0_TXP_2
DDI0_TXN_2

DDI0_TXP_3
DDI0_TXN_3

DDI0_AUXP
DDI0_AUXN

DDI0_HPD
DDI0_DDC_SCL

DDI0_DDC_SDA

DDI1_TXP_0
DDI1_TXN_0

DDI1_TXP_1
DDI1_TXN_1

DDI1_TXP_2
DDI1_TXN_2

DDI1_TXP_3
DDI1_TXN_3

DDI1_AUXP
DDI1_AUXN

DDI1_DDC_SCL
DDI1_DDC_SDA
DDI1_HPD

EDP_TXP_0
EDP_TXN_0

EDP_TXP_1
EDP_TXN_1

EDP_TXP_2
EDP_TXN_2

EDP_TXP_3
EDP_TXN_3

EDP_AUXP
EDP_AUXN

EDP_HPD
PNL0_BKLCTL

PNL0_BKLTEN
PNL0_VDDEN

EDP_RCOMP_P
EDP_RCOMP

DDI0/DDI_B

MDSI

DDI1/DDI_C

eDP/DDI_A

3 OF 13

INT_HDMITX2P[14]
INT_HDMITX2N[14]

INT_HDMITX1P[14]

D D

Max 7.5 inch

HDMI

HDMI_HPD

+3V

TypeC_HPD#
INT_EDP_HPD#

C C

HDMI HPD

B B

R568 *10K_5%_4
R7 10K_5%_4

INT_HDMI_HPD#

RUC002N05GZT116

eDP Panel

<10000 mil

+1.8V

change to 3.3V

R284
10K_5%_4

3

Q13

HDMI_HPD_R

2

1

R309 *S_4

R300
100K_1%_4

INT_HDMITX1N[14]
INT_HDMITX0P[14]

INT_HDMITX0N[14]

INT_HDMICLK+[14]
INT_HDMICLK-[14]

INT_HDMI_HPD#

HDMI_DDCCLK_SW[14]

HDMI_DDCDATA_SW[14]

TypeC_HPD#

EDP_TXP0[14]
EDP_TXN0[14]

EDP_TXP1[14]
EDP_TXN1[14]

EDP_AUXP[14]
EDP_AUXN[14]

INT_EDP_HPD#[14]

R453 100_1%_4

HDMI_HPD_C [14]

INT_EDP_HPD#
PCH_BKLTCTL

PCH_BKLTEN
PCH_VDDEN

EDP_RCOMP_P
EDP_RCOMP_N

MDSI_A_CLKP

MDSI_A_CLKN
MDSI_C_CLKP

MDSI_C_CLKN

MDSI_A_DP_0
MDSI_A_DN_0

MDSI_A_DP_1
MDSI_A_DN_1

MDSI_A_DP_2
MDSI_A_DN_2

MDSI_A_DP_3
MDSI_A_DN_3

MDSI_C_DP_0
MDSI_C_DN_0

MDSI_C_DP_1
MDSI_C_DN_1

MDSI_C_DP_2
MDSI_C_DN_2

MDSI_C_DP_3
MDSI_C_DN_3

MIPI_I2C_SCL

MIPI_I2C_SDA

MDSI_C_TE
MDSI_A_TE

MDSI_RCOMP

AL2
AM3

AG13
AG12

AN5
AN7

AJ15
AJ17

AJ7
AJ5

AJ10
AJ12

AG15
AG17

AG8
AG10

AG7
AG5

AE15
AE17

R53
R54

T53

SOC_OVRIDE

T55

GPIO_42 HW Strap

MDSI_RCOMP

AL5

GPIO_43 [9]

R167 150_1%_4

+1.8V_S5[3,5,6,7,9,12,15,21,22,23,27,29]
+1.8V[3,14,17,20,22,29,30]
+3V[5,12,13,14,16,17,18,19,20,21,22,24,25,26,27,28,29,30]

04

+3V +3V +3V

R202

*10K_5%_4

PCH_VDDEN PCH_BKLTEN PCH_BKLTCTL

A A

5

Q8A

R208 *S_4

R192
*10K_5%_4

61

34

2

*SSM6N43FU

Q8B

5

EDP_VDD_EN [14] PCH_BLON [14] PCH_BRIGHT [14]

R295

*10K_5%_4

5

Q15A

R294 *S_4

R306
*10K_5%_4

61

34

2

*SSM6N43FU

Q15B

4

R212

*10K_5%_4

5

Q9A

R224 *S_4

R203
*10K_5%_4

34

61

2

*SSM6N43FU

Q9B

3

Override

Flash Descriptor Override (SOC_OVRIDE)

0 = Normal Override(Normal operation)

1 = Override

3

2

ME_WR#[13]

2

1

Q34

2N7002K

+1.8V_S5

R488

2.2K_5%_4

SOC_OVRIDE

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Thursday, August 09, 2018

Date: Sheet of

Thursday, August 09, 2018

Date: Sheet of

Thursday, August 09, 2018

Date: Sheet

PROJECT :

GLK (HDMI/eDP)

GLK (HDMI/eDP)

GLK (HDMI/eDP)

ZHVA

ZHVA

ZHVA

of

4 34

4 34

1

4 34

1A

1A

1A

5

?
?

U23J

C26

AVS_I2S0_MCLK

B25

AVS_I2S0_BCLK

C25

AVS_I2S0_WS_SYNC

HDA_BCLK_R
HDA_SYNC_R

HDA_SDO_R
HDA_RST#_R

EMMC_RCOMP

CLK_PCI_LPC

C432

*18P/50V_4

C24

AVS_I2S0_SDI

B23

AVS_I2S0_SDO

M23

AVS_I2S1_MCLK

L21

AVS_I2S1_BCLK

J21

AVS_I2S1_WS_SYNC

M21

AVS_I2S1_SDI

P23

AVS_I2S1_SDO

A22

AVS_HDA_BCLK

C23

AVS_HDA_WS_SYNC

B21

AVS_HDA_SDI

C22

AVS_HDA_SDO

C21

AVS_HDA_RST

B19

AVS_DMIC_CLK_A1

C20

AVS_DMIC_CLK_B1

C19

AVS_DMIC_DATA_1

C18

AVS_DMIC_CLK_AB2

A18

AVS_DMIC_DATA_2

J13

EMMC_CLK

L15

EMMC_RCLK

M19

EMMC_D0

H19

EMMC_D1

J19

EMMC_D2

P17

EMMC_D3

P19

EMMC_D4

J15

EMMC_D5

L17

EMMC_D6

M17

EMMC_D7

M13

EMMC_CMD

U44

EMMC_RST

G51

EMMC_PWR_EN

L13

EMMC_RCOMP

GLK_SOC_RVP1

?

AUDIO-AVS

eMMC

EMMC_CLK[17]
EMMC_RCLK[17]

EMMC_DATA_0[17]
EMMC_DATA_1[17]
EMMC_DATA_2[17]
EMMC_DATA_3[17]
EMMC_DATA_4[17]
EMMC_DATA_5[17]
EMMC_DATA_6[17]
EMMC_DATA_7[17]
EMMC_CMD[17]

EMMC_RST[17]

C431
*33p/50V_4

GPIO_159[9]

GPIO_163[9]
GPIO_164[9]

R513 33_5%_4
R530 33_5%_4

R549 33_5%_4
R548 33_5%_4

GPIO_172[9]
GPIO_174[9]

GPIO_175[9]

R226 200_1%_4

D D

HDA

AZ_CODEC_BITCLK[19]

AZ_CODEC_SYNC[19]

AZ_CODEC_SDIN0[9,19]

AZ_CODEC_SDOUT[19]

AZ_CODEC_RST#[19]

C C

AZ_CODEC_BITCLK

4

Gemini lake (EMMC/LPC/I2C/GPIO/HDA)

L29

SDCARD

LPC/eSPI

LPC set 3.3V

FAST_SPI

7 OF 13

XDP_TCK
XDP_TRST#

XDP_PREQ#
XDP_PRDY#
XDP_TMS
XDP_TDO
XDP_TDI

R425 51_5%_4
R433 51_5%_4

R444 51_5%_4
R445 169_1%_4
R426 51_5%_4
R428 169_1%_4
R446 51_5%_4

SPI is 1.8V

+1.8V_S5

SDCARD_CLK

SDCARD_D0
SDCARD_D1
SDCARD_D2
SDCARD_D3

SDCARD_CMD

SDCARD_CD

SDCARD_LVL_W P

SDCARD_PWR_D WN

SDCARD_RCOMP

LPC_CLKOUT0
LPC_CLKOUT1

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_CLKRUN

LPC_FRAME

LPC_SERIRQ

FST_SPI_CLK

FST_SPI_MOSI_IO0
FST_SPI_MISO_IO1

FST_SPI_IO2
FST_SPI_IO3

FST_SPI_CS0
FST_SPI_CS1

M29
P29
M27
P27
L27
L25
P25
L23

J25

C37
A38

A34
C34
B35
C35

C33
B33
B37

B29
B31

C30
A30
C29

C31
C32

LPC_CLKOUT0
LPC_CLKOUT1

LPC_LAD0_R
LPC_LAD1_R
LPC_LAD2_R
LPC_LAD3_R

LPC_CLKRUN#_R
LPC_LFRAME#_R
SOC_SERIRQ_R

PCH_SPI_CLK
PCH_SPI_SI

PCH_SPI_SO
PCH_SPI_IO2
PCH_SPI_IO3

PCH_SPI_CS0#
PCH_SPI_CS1#

3

R532 22_5%_4
R516 DBG@22_5%_4

R538 22_5%_4
R551 22_5%_4
R531 22_5%_4
R514 22_5%_4

R521 22_5%_4
R537 22_5%_4
R515 22_5%_4

PCH_SPI_CLK [2 1]
PCH_SPI_SI [21 ]

PCH_SPI_SO [21]

TP20

TP44
TP48
TP46
TP45

XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#

XDP_PRDY#
XDP_PREQ#

CLK_PCI_EC [13]

CLK_PCI_LPC [21]

LPC_LAD0 [13,21]
LPC_LAD1 [13,21]
LPC_LAD2 [13,21]
LPC_LAD3 [13,21]

CLKRUN# [13]
LPC_LFRAME# [13,21]

SOC_SERIRQ [12]

2

+1.8V_S5[3,4,6,7,9,12,15,21,22,23,27,29]
+1.8V[3,4,14,17,20,22,29,30]

U23H

AH53

JTAGX

AM53

JTAG_TCK

AJ54

JTAG_TDI

AL53

JTAG_TDO

AL54

JTAG_TMS

AK53

JTAG_TRST

AH55

JTAG_PRDY

AJ53

JTAG_PREQ

JTAG

ITP

GPIO

5 OF 13

+3V_S5[3,6,7,12,13,15,22,24,26,29]

GPIO_8

GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_15
GPIO_16

GPIO_17
GPIO_18
GPIO_19
GPIO_20
GPIO_21
GPIO_22
GPIO_23
GPIO_24
GPIO_25

GPIO_26
GPIO_27
GPIO_28
GPIO_29
GPIO_30
GPIO_31
GPIO_32
GPIO_33
GPIO_34

GPIO_35
GPIO_36
GPIO_37
GPIO_38
GPIO_39
GPIO_40
GPIO_41

GPIO_105
GPIO_134
GPIO_135
GPIO_136
GPIO_137
GPIO_138
GPIO_139
GPIO_140
GPIO_141
GPIO_142
GPIO_143
GPIO_144
GPIO_145
GPIO_146
GPIO_210
GPIO_212
GPIO_213
GPIO_214

AG53
AG54
AE54
AE53
AD55
AD53
AC54
AC53
AB53

AA49
AC48
AC46
AE51
AE49
AC51
AC49
AA51
AA46

AE41
AE39
AE46
AE44
AC41
AC39
AC44

RF_KILL#_R

AC43
AA44

AA54
AA53
Y55

R491 *S_4

Y53
W54
W53

IERR

V53

GPIO_105

L46
H45
H47

R194 *0_5%_4

L43

R193 *0_5%_4

M43

SATA_GP0

H37

PCH_PCIERST#

H43

GPIO_140

J43

GPIO_141

D43

GPIO_142

F43
H41
F39
L41

AC_PRESENT

F41
H27
U43
U41
U39

Board_ID0
Board_ID1
Board_ID2
Board_ID3
Board_ID4
Board_ID5
Board_ID6
Board_ID7
Board_ID8

RAM_ID0

RAM_ID1
RAM_ID2

RAM_ID3

RAM_ID4
RAM_ID5
eMMC_ID0
eMMC_ID1

eMMC_ID2

1

05

TP6
TP8
TP7

SPKR [19]

R492 *S_4

GPIO_27 [9]
GPIO_28 [9]

TP14
TP21

TP10

PIRQ# [21]

PCH_TPD_INT# [15]
SENSOR_HUB_INT1# [20]

SIO_EXT_SCI# [13]

SOC_PCI_SERR#

GSENSOR_INT [12]
ISH_MODE1 [20]
ISH_MODE2 [20]

set to 3.3V

HW strap ID
Board_ID0

B B

Board_ID1

Board_ID2

Board_ID3

Board_ID4

Board_ID5

Board_ID6

Board_ID7

B

oard_ID8

RAM_ID0

RAM_ID1

RAM_ID2

RAM_ID5

0

A A

0
0
0

eMMC_ID1eMMC_ID2

0
0

0 1
1 1

Strap pin Description

0 = Non Touch Screen
1 = Touch Screen

0 = with EMMC

1 = without EMMC <HDD only>

0 = M.2 SATA SSD

1 = M.2 PCIE SSD

0 = none G sensor

1 = G sensor

0 = none TPM

1 = TPM

0 = With SATA Port 0 Connector

1 = Without SATA Port 0 Connector

0 = With SATA Port 1 Connector

1 = Without SATA Port 1 Connector

0 = Convertible model (360’)

1 = Clamshell model

Reserve

0 = Single chanel (A)

1 = Dual chanel(A&B)

0 = Channel A On board RAM 2GB

1 = Channel A On board RAM 4GB

0 = Channel B On board RAM 2GB

1 = Channel B On board RAM 4GB

Vender

RAM_ID3RAM_ID4

0

0

Miron

0

1

Hynix

01

Samsung

1 1

eMMC_ID0

0
1
0
1

Sandisk 32G/64G/128GB

1

Vender

Samsung 32/64GB

Hynix 32/64GB

Kingston 32/64GB

Toshiba 128GB

0
0
10

BOARD ID SETTING

R455 *10K_5%_4
R442 10K_5%_4
R470 10K_5%_4
R459 *10K_5%_4
R468 *10K_5%_4
R476 10K_5%_4
R484 10K_5%_4
R475 10K_5%_4
R489 10K_5%_4

R437 *10K_5%_4
R479 *10K_5%_4
R480 *10K_5%_4
R434 10K_5%_4
R436 10K_5%_4
R478 10K_5%_4

R435 *10K_5%_4
R438 *10K_5%_4
R481 10K_5%_4

5

Board_ID0
Board_ID1
Board_ID2
Board_ID3
Board_ID4
Board_ID5
Board_ID6
Board_ID7
Board_ID8

RAM_ID0
RAM_ID1
RAM_ID2
RAM_ID3
RAM_ID4
RAM_ID5

eMMC_ID0
eMMC_ID1
eMMC_ID2

R456 10K_5%_4
R443 *10K_5%_4
R471 *10K_5%_4
R460 10K_5%_4
R469 10K_5%_4
R477 *10K_5%_4
R485 *10K_5%_4
R482 *10K_5%_4
R490 *10K_5%_4

R450 10K_5%_4
R464 10K_5%_4
R465 10K_5%_4
R447 *10K_5%_4
R449 *10K_5%_4
R463 *10K_5%_4

R448 10K_5%_4
R451 10K_5%_4
R466 *10K_5%_4

+1.8V_S5

Board ID

RAM ID

eMMC ID

4

R552

R567 33_5%_4
R539 33_5%_4
R556 33_5%_4

R546 33_5%_4

3.3K_5%_4

SPI_CLK_A

PCH_SPI_CS0#
PCH_SPI_CLK
PCH_SPI_SI
PCH_SPI_SO

PCH_SPI_IO2

Series resistance 33R is recommended
for signalsasper PDG Table 27-2

+1.8V_S5

R569
*3.3K_5%_4

U28

1

CE#

6

SCLK

5

SI

2

SO

3

IO2

GD25LB64CSIGR

+1.8V_S5

C440

R565

0.1u/16V_4

3.3K_5%_4

8

VCC

7

IO3

4

VSS

3

R566 33_5%_4

PCH_SPI_IO3

GPIO_142

GPIO_140

Q36A

*10K_5%_4

R557

*10K_5%_4

34

5

R555 *S_4

BOARD ID SETTING

R172

34

5

Q7A

R184 *0_5%_4

+3V

61

2

Q36B

*2N7002KDW

2

R571
10K_5%_4

+3V

61

R176
*10K_5%_4

Q7B

*SSM6N43FU

2

NGFF_SATA_DET# [17 ]

SATA_DEVSLP0 [17]

GPIO_141

R293

*10K_5%_4

5

Q14A

R292 *S_4

SOC_PCI_SERR#
PCH_TPD_INT#
SIO_EXT_SCI#
SENSOR_HUB_INT1#

RF_KILL#_R

GPIO_105

R487 *10K_5%_4
R175 10K_5%_4
R486 10K_5%_4
R191 *GS@10K_5%_4

R190 *10K_5%_4

R220 *10K_5%_4

+3V

R301
10K_5%_4

34

61

2

Q14B

*SSM6N43FU

SATA_DEVSLP1 [17]

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number R

Date: Sheet of

Date: Sheet of

Date: Sheet of

PROJECT :

GLK (GPIO/LPC/I2C/HDA)

GLK (GPIO/LPC/I2C/HDA)

GLK (GPIO/LPC/I2C/HDA)

Thursday, August 09, 2018

Thursday, August 09, 2018

Thursday, August 09, 2018

1

set to PU

ZHVA

ZHVA

ZHVA

+1.8V_S5

+1.8V_S5

5 34

5 34

5 34

ev

1A

1A

1A

5

PMU set to 3.3V

+3V_S5 +1.8V_S5

R274

R233

0_5%_4

*0_5%_4

D D

R239 *10K_5%_4

R232 100K_1%_4
R262 10K_5%_4
R535 *1K_1%_4
R281 *10K_5%_4
R278 *20K_1%_4
R285 20K_1%_4

R250 *10K_5%_4
R180 *1K_1%_4

+1.8V_S5

check list use 20k

R517 1K_1%_4

C C

R260 *1K_1%_4

R247 *100K_1%_4

R534 100K_1%_4

C248 *0.1u/16V_4
C234 *0.1u/16V_4
C240 *0.1u/16V_4
C244 0.1u/16V_4
C199 *0.1u/16V_4

PCH_SUSPWRDNACK

PCH_BATLOW#
PMU_RSTBTN#

PLTRST#
PMU_SLP_S0#
SOC_RSMRST#
CORE_PWROK

PCH_SUS_STAT#
DNBSWON#

H_PROCHOT#

THRMTRIP#_R

CORE_PWROK

PLTRST#

CORE_PWROK
PCH_BATLOW#
SOC_RSMRST#
PMU_RSTBTN#
DNBSWON#

PLTRST#[13,17,21,22]
DNBSWON#[13]

PMU_SLP_S0#[21]

SUSB#[13]
SUSC#[13]

PCH_SUSPWRDNACK[13]

TP22
TP16

H_CPU_SVIDCLK[27,28]

H_CPU_SVIDDAT[27,28]

VR_SVID_ALERT#_VCORE[27,28]

TP23
TP19

4

TP12
TP13

PLTRST#
DNBSWON#
PMU_SLP_S0#
SUSB#
SUSC#
PCH_SUSPWRDNACK
PCH_BATLOW#
PMU_RSTBTN#
PMU_SUSCLK

PCH_SUS_STAT#

R523 *S_4
R525 *S_4
R524 220_5%_4

H_CPU_SVIDDAT
VR_SVID_ALERT#_VCORE
H_CPU_SVIDCLK

SVID_CLK#_R
SVID_DAT#_R
SVID_ALERT#_R

3

Gemini lake (PMU/PMIC/RTC)

U23E

R46

PMC_I2C_SCL

R48

PMC_I2C_SDA

L48

PMC_SPI_CLK

N48

PMC_SPI_FS0

N44

PMC_SPI_FS1

L49

PMC_SPI_FS2

L51

PMC_SPI_RXD

N49

PMC_SPI_TXD

D54

PMU_PLTRST

E54

PMU_PWRBTN

C52

PMU_SLP_S0

D51

PMU_SLP_S3

J49

PMU_SLP_S4

F54

SUSPWRDNACK

J48

PMU_BATLOW

C51

PMU_RSTBTN

G49

PMU_SUSCLK

E52

SUS_STAT

F55

SVID0_CLK

G53

SVID0_DATA

G54

SVID0_ALERT_B

D1

DEBUG_PORT_A0

D2

DEBUG_PORT_A1

A54

NC2

C54

NC11

+1.05V

R543
240_1%_4

PMU set 3.3V

R542
68_5%_4

R541
*160_1%_4

PMC

PMU

SVID

Misc

C437
1000p/50V_4

iCLK

RTC

Thermal

Spare

8 OF 13

THRMTRIP#_R

RTC is 3.3V

2

OSC_CLK_OUT_0
OSC_CLK_OUT_1

OSCIN

OSCOUT

RTC_X1
RTC_X2

VCC_RTC_EXTPAD

INTRUDER

SOC_PWROK

RSM_RST

RTC_TEST

RTC_RST

THERMTRIP

1.8V

PROCHOT

NC15
NC16

SKTOCC

NC14

NC10
NC17

R231
*10K_5%_4

61

Q10B
*PJT138K

GND

NC3
NC4

NC1
NC5

NC6
NC7
NC8
NC9

5

B17
C17

XTAL192_IN

U2

XTAL192_OUT

T1

RTC_X1

D23

RTC_X2

F23

BVCCRTC_EXTPAD

J23
H25

INTRUDER#
CORE_PWROK

D25

SOC_RSMRST#

F27

RTC_TEST#

F25

RTC_RST#

D27

THRMTRIP#_R

J53

H_PROCHOT#

J54
AG43
H53
AG44
H55

A4
BH1
A53
F37
BL2
BL3
BL53
C2
C3
R41

+3VPCU

R243
*10K_5%_4

34

Q10A
*PJT138K

THERMTRIP#

C216 0.1u/16V_4
R266 330K_5%_4
R277 *S_4

R242 *S_4

RTC_RST#

2

+1.8V_S5[3,4,5,7,9,12,15,21,22,23,27,29]
+1.05V[7,25,27,28]
+3V_S5[3,7,12,13,15,22,24,26,29]
+3VPCU[13,14,15,16,19,21,22,23,24,29]
+3V_RTC[7,13]

+3V_RTC

EC_PWROK [13]

THERMTRIP# [13]
H_PROCHOT# [13,23,27,28]

colsed to CPU pin within 100 mils

C271
1000p/50V_4

R303
10_5%_4

EC reset RTC

CLR_CMOS[13]

SOC_RSMRST# [12]

colsed to CPU pin within 100 mils

C188
1000p/50V_4

R174
10_5%_4

CORE_PWROK

Q11

3

1

2

PMZ370UNE

1

colsed to CPU pin within 100 mils

C266
1000p/50V_4

R288
10_5%_4

RTC_TEST#
RTC_RST#

Q16

3

1

2

PMZ370UNE

06

B B

RTC Circuitry (RTC)

R2 1K_1%_4

Trace width = 20 mils

12

CN1

+ -

AAA-BAT-046-K03

A A

5

4

34

ML1220 Coin type

HL03001031 [VDE] 17mAH

A
AHL03001057 [DBV] 17mAH

+3VPCU

+3V_RTC_1

1 3

Q1 EJ@PMST3904

20MIL

2

+3V_RTC

D1

2
1

R3 EJ@4.7K_5%_4

BAT54CW

R302

3

20K_1%_4

R1

20K_1%_4

VCCRTC_4VCCRTC_3VCCRTC_2

3

+3V_RTC
Trace width = 20 mils

C270
1u/6.3V_4

C1
1u/6.3V_4

R4 EJ@4.7K_5%_4

EJ@68.1K_1%_4

EJ@150K_1%_4

RTC_RST#

RTC_TEST#

+5V_S5

R5

R6

19.2MHZ/20ppm

RTC Clock 32.768KHz (CPU)

Trace length < 1000 mils

2

C404 15p/50V_4

Y2

C402 15p/50V_4

C430 18p/50V_4

C429 18p/50V_4

XTAL192_OUT

4

3

R483
200K_1%_4

1

2

XTAL192_IN

CH01006JB08 -> 10p
CH01506JB06 -> 15p
CH-6806TB01 -> 6.8p

12

Y3

32.768KHZ/20ppm

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

RTC_X1

R518
10M_5%_4

RTC_X2

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

GLK (PMU/PMIC/SMB/RTC)

GLK (PMU/PMIC/SMB/RTC)

GLK (PMU/PMIC/SMB/RTC)

Thursday, August 09, 2018

Thursday, August 09, 2018

Thursday, August 09, 2018

ZHVA

ZHVA

ZHVA

6 34

6 34

1

6 34

1A

1A

1A

5

EDGE DECAPS
FOR EXPOSED POWER PLANES

BACK side cap

4

Gemini (POWER)

3

2

+3V_S5[3,6,12,13,15,22,24,26,29]
+1.24V_S5[29]
+1.8V_S5[3,4,5,6,9,12,15,21,22,23,27,29]
+3V_RTC[6,13]
+1.2VSUS_Q[2]

+VNN[28]
+VCC_VCCGI[27]
+1.05V[6,25,27,28]

1

07

VNN1
VNN2
VNN3
VNN4
VNN5
VNN6
VNN7
VNN8

VNN9
VNN10
VNN11
VNN12
VNN13
VNN14
VNN15
VNN16

NC1

NC2
NC3

NC4

AF35
AG27
AG28
AG36
AG46
AG48
AJ27
AJ28
AJ46
AJ48
AL27
AL28
AL48
AL49
AM27
AM28

AJ49

AW44
BH55
AG41

AG39
AJ41

AJ43
BL54

AC33
AC35
AE33
AE35
AE36
AE38
AF27
AF28
AF36
AF38

+VCCRAM_1P05_FHV0

AG51

+VCCRAM_1P05_FHV1

AG49

+VCCRAM_1P05_FUSE

AJ51
AA36

AA38
AC36
AC38
Y36
Y38

P15

AJ21
U17

AG21
T18
T20
V18
V20
Y18
Y20

+VNN+VCC_VCCGI

+VCCRAM_1P05

VRTC_3P3

C231

*1u/6.3V_4

C220

*1u/6.3V_4

C162

1u/6.3V_4

C148

*1u/6.3V_4

R230 *S_6

C230

1u/6.3V_4

C211

*1u/6.3V_4

R418 *S_6

C172

1u/6.3V_4

C150

*1u/6.3V_4

VCCGI_SENSE [27]
VCCGISS_SENSE [27]

VNN_SENSE [28]
VNNSS_SENSE [28]

+1.05V

R171 *S_6
R166 *S_6

R164 *S_6

+3V_RTC

C205

1u/6.3V_4C191 1u/6.3V_4

C153

1u/6.3V_4

C171

*22u/6.3V_6

C180

1u/6.3V_4

*47u/10V_8

C390

22u/6.3V_6

C147

1u/6.3V_4

C143

C389

*1u/6.3V_4

R217 *S_6

C217

22u/6.3V_6

2

22u/6.3V_6

C127
*47u/10V_8

+VCCRAM_1P05+VCCRAM_1P05

C185

*1u/6.3V_4

C159

1u/6.3V_4

C388

*1u/6.3V_4

+3V_S5

C140

22u/6.3V_6

C133

*47u/10V_8

C193

C178

1u/6.3V_4

C186

1u/6.3V_4

C164

22u/6.3V_6

C154
*47u/10V_8

C137
*47u/10V_8

C391

22u/6.3V_6

C170

*22u/6.3V_6

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Thursday, August 09, 2018

Date: Sheet of

Thursday, August 09, 2018

Date: Sheet of

Thursday, August 09, 2018

PROJECT :

GLK (POWER)

GLK (POWER)

GLK (POWER)

ZHVA

ZHVA

ZHVA

1

7 34

7 34

7 34

1A

1A

1A

U23F

AA28

VCC_VCG1

AA29

VCC_VCG2

AA31

D D

C229

0.1u/16V_4

C169

22u/6.3V_6

22u/6.3V_6

C419

*22u/6.3V_6

C246

C C

+1.2VSUS

R139 *S_8
R132 *S_8

B B

+1.24V_S5

A A

*47u/10V_8

+1.2VSUS_Q

+1.2VSUS_Q

C126

22u/6.3V_6

R183 *S_6
R189 *S_6
R161 *S_6
R424 *S_6
R169 *S_6
R187 *S_6
R170 *S_6

C215 *47u/10V_8
C212 1u/6.3V_4

C146 22u/6.3V_6

5

22u/6.3V_6

C206

0.1u/16V_4

C410

C399

*22u/6.3V_6

C263

*47u/10V_8

*47u/10V_8

C131

22u/6.3V_6

+1.05V

R155 *S_8

+1.8V_S5

+VDD2_1P24_MPHY
+VDD2_1P24_AUD_ISH
+VDD2_1P24_DSI_CSI
+VDD2_1P24_GLML
+VDD2_1P24_PLL
+VDD2_1P24_VNNAON
+VDD2_1P24_USB2

+VDD2_1P24_AUD_ISH

+VDD2_1P24_DSI_CSI

C201

1u/6.3V_4

C237

1u/6.3V_4

C198

22u/6.3V_6

C249

*22u/6.3V_6

C416
*47u/10V_8

C418

C128

R251 *S_6

C214

1u/6.3V_4

C173

1u/6.3V_4

C423

22u/6.3V_6

C397

*22u/6.3V_6

C245
*47u/10V_8

C265

*47u/10V_8

C130

22u/6.3V_6

C221

C204

1u/6.3V_4

1u/6.3V_4

C181

C175

1u/6.3V_4

1u/6.3V_4

C401

C182

22u/6.3V_6

22u/6.3V_6

C398

C396

*22u/6.3V_6

*22u/6.3V_6

C232

C241

*1u/6.3V_4

*1u/6.3V_4

C247

C264

*47u/10V_8

*47u/10V_8

C156

C151

1u/6.3V_4

1u/6.3V_4

C157

C155

1u/6.3V_4

1u/6.3V_4

C251

C252

*1u/6.3V_4

*1u/6.3V_4

C194 47u/6.3V_6
C196 47u/6.3V_6
C195 22u/6.3V_6

C190 1u/6.3V_4
C184 1u/6.3V_4

C394 22u/6.3V_6
C395 22u/6.3V_6
C152 1u/6.3V_4

C163 22u/6.3V_6
C166 1u/6.3V_4
C167 1u/6.3V_4

C179 1u/6.3V_4
C177 *22u/6.3V_6

22u/6.3V_6

+VCCIOA

+VDD2_1P24_MPHY

+VDD2_1P24_PLL

+VDD2_1P24_USB2

C213

1u/6.3V_4

C209

1u/6.3V_4

C222

C168

*22u/6.3V_6

C161

*1u/6.3V_4

C417
*47u/10V_8

C139

0.1u/16V_4

C158

1u/6.3V_4

C253

1u/6.3V_4

C202

1u/6.3V_4

C210

1u/6.3V_4

C192

22u/6.3V_6

C411

*22u/6.3V_6

C233

*1u/6.3V_4

C223
*47u/10V_8

C142

0.1u/16V_4

C141

22u/6.3V_6

C208

1u/6.3V_4

4

VCC_VCG3

AA33

VCC_VCG4

AC28

VCC_VCG5

AC31

VCC_VCG6

AE28

VCC_VCG7

AE29

VCC_VCG8

AE31

VCC_VCG9

AF31

VCC_VCG10

AF33

VCC_VCG11

AG31

VCC_VCG12

AG33

VCC_VCG13

AJ31

VCC_VCG14

AJ33

VCC_VCG15

AJ35

VCC_VCG16

AL31

VCC_VCG17

AL33

VCC_VCG18

AL35

VCC_VCG19

AM33

VCC_VCG20

AM35

VCC_VCG21

AM36

VCC_VCG22

D31

VCC_VCG23

D33

VCC_VCG24

D37

VCC_VCG25

D39

VCC_VCG26

P39

VCC_VCG27

P41

VCC_VCG28

T28

VCC_VCG29

T29

VCC_VCG30

T31

VCC_VCG31

T33

VCC_VCG32

T35

VCC_VCG33

T36

VCC_VCG34

V28

VCC_VCG35

V29

VCC_VCG36

V31

VCC_VCG37

V33

VCC_VCG38

V35

VCC_VCG39

V36

VCC_VCG40

Y28

VCC_VCG41

Y29

VCC_VCG42

Y33

VCC_VCG43

Y35

VCC_VCG44

C138

0.1u/16V_4

C136

22u/6.3V_6

C174

22u/6.3V_6

1u/6.3V_4

+VDD2_1P24_MPHY

+VDD2_1P24_AUD_ISH

+VDD2_1P24_DSI_CSI
+VDD2_1P24_GLML+VDD2_1P24_GLML

+VDD2_1P24_PLL

+VDD2_1P24_VNNAON

+VDD2_1P24_USB2

C135

0.1u/16V_4

C145

2.2u/10V_4

C250

25A

AW12

AP18
AP21
AP36
AP38
AT18
AT20
AT21
AT35
AT36
AT38
BA13
BA15
BA25
BA31
BA41
BA43

AP25
AP31
AT25
AT27
AT28
AT29
AT31

AJ23

AG23

AC21
AE20
AE21
AF20
AF21

AC18
AC20

AL36
AL38
AP20

AM20
AL18

AM18
AA18

AA20
AG18

AJ20

T21
T23
T25
V21
V23
V25

U23G

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7

3A

VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16

VCCIOA1
VCCIOA2
VCCIOA3
VCCIOA4
VCCIOA5
VCCIOA6
VCCIOA7

VCC_1P8V_A3
VCC_1P8V_A4

VDD1(1.8V)

VCC_1P8V_A5
VCC_1P8V_A6
VCC_1P8V_A7
VCC_1P8V_A8

VCC_1P8V_A2
VCC_1P8V_A1

VDD2_1P2_MPHY1
VDD2_1P2_MPHY2
VDD2_1P2_MPHY3
VDD2_1P2_MPHY4
VDD2_1P2_MPHY5

VDD2_1P2_AUD1
VDD2_1P2_AUD2

VDD2_1P2_DSI_CSI
VDD2_1P2_GLM1

VDD2_1P2_GLM2
VDD2_1P2_GLM4

VDD2_1P2_GLM3
VDD2_1P2_PLL1

VDD2_1P2_PLL2
VDD2_1P2_VNNAON1

VDD2_1P2_VNNAON2
VDD2_1P2_USB2

VDD2_1P2_USB3

VDD2(1.2V)

9 OF 13

0.4A

3A

10 OF 13

4.5A

VCCRAM(1.05V)

RTC

0.15A

VDD3(3.3V)

3

A

4

VCC_VCG_SENSE
VSS_VCG_SENSE

VNN_SENSE

VNN_VSS_SENSE

VCCRAM_1P053
VCCRAM_1P054
VCCRAM_1P057
VCCRAM_1P058

VCCRAM_1P059
VCCRAM_1P0510
VCCRAM_1P0511
VCCRAM_1P0512
VCCRAM_1P0513
VCCRAM_1P0514

VCC_1P05_INT2

VCC_1P05_INT1

VCC_1P05_INT3

VCCRAM_1P051

VCCRAM_1P052

VCCRAM_1P055

VCCRAM_1P056
VCCRAM_1P0515
VCCRAM_1P0516

VCCRTC_3P3V

VCC_3P3V_A2
VCC_3P3V_A5

VCC_3P3V_A1
VCC_3P3V_A3
VCC_3P3V_A4
VCC_3P3V_A6
VCC_3P3V_A7
VCC_3P3V_A8
VCC_3P3V_A9

5

4

3

2

1

GLK ULT (GND)

08

D D

C C

B B

A12
A16
A20
A24
A28
A32
A36
A40
A44
A48

A51
AA12
AA13
AA15
AA17
AA21
AA23
AA25
AA27
AA35
AA43
AA48

AB1
AB3

AB55

AC8
AC13
AC23
AC25
AC27
AC29
AE18
AE23
AE25
AE27
AE43
AE48

AF1
AF3
AF4
AF6
AF8

AF9
AF11
AF12
AF14
AF16
AF18
AF23
AF25
AF29
AF40
AF42

U23K

A3

VSS6

A6

VSS13
VSS1
VSS2
VSS3
VSS4
VSS5
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS33
VSS28
VSS29
VSS30
VSS31
VSS32
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS49
VSS50
VSS61
VSS62
VSS63
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS51
VSS52

11 OF 13

VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS64
VSS87
VSS65
VSS66
VSS67
VSS68
VSS77
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS78
VSS79
VSS80
VSS90
VSS97
VSS98
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS88
VSS89
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS108
VSS110
VSS107
VSS109

AF44
AF45
AF47
AF48
AF50
AF52
AF53
AF55
AG20
AL21
AG25
AG29
AG35
AG38
AJ8
AJ13
AJ18
AJ25
AJ29
AJ36
AJ38
AJ39
AJ44
AK1
AK3
AK55
AL3
AL7
AL8
AL10
AL12
AL13
AL15
AL17
AL20
AL25
AL29
AL39
AL41
AL43
AL44
AL46
AL51
AM1
AM21
AM23
AM25
AM29
AM31
AM38
AM55
AN3
AN8
AN10
AN46

AN48
AN49
AN51
AN53
AP23
AP27
AP28
AP29
AP33
AP35

AR2

AR7
AR10
AR12
AR17
AR39
AR44
AR46
AR49
AR54

AT23
AT33

AU3
AU10
AU28
AU46
AU53
AV15
AV17
AV23
AV25
AV31
AV33
AV39
AV41

AW2

AW5
AW10
AW28
AW46
AW51
AW54

AY13

AY15

AY28

AY41

AY43

B55
BA27
BA29

BB1
BB28
BB55

BC5

U23M

BC11

VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_124
VSS_130
VSS_121
VSS_122
VSS_123
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_131
VSS_132
VSS_135
VSS_133
VSS_134
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_147
VSS_150
VSS_146
VSS_148
VSS_149
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157

B2

VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_178

12 OF 13

VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_179
VSS_187
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_189
VSS_188
VSS_190
VSS_194
VSS_191
VSS_192
VSS_193
VSS_195
VSS_199
VSS_196
VSS_197
VSS_198
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_215
VSS_213
VSS_214
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220

BC17
BC19
BC21
BC23
BC25
BC31
BC33
BC35
BC37
BC39
BC41
BC45
BC51
BD9
BD15
BD19
BD21
BD28
BD35
BD37
BD47
BE3
BE28
BE53
BF9
BF19
BF37
BF47
BG1
BG6
BG28
BG50
BG55
BH11
BH13
BH17
BH19
BH23
BH25
BH28
BH31
BH33
BH37
BH39
BH41
BH45
BJ2
BJ15
BJ19
BJ25
BJ28
BJ31
BJ37
BJ41

AL23
BJ54

BK1
BK17
BK21
BK35
BK39
BK55

BL10
BL14
BL24
BL28
BL32
BL42
BL46
BL48
BL51

C12

C16

C28

C36

D21

D28

D41

D45

D55

G28

H13

H15

H21

H23

H28

H33

H39

BL5
BL8

E28
E50
E55

F21
F31

J27
J33
J41
J45

U23L

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS17
VSS19
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS18

C1

VSS20
VSS21
VSS22
VSS23
VSS24

D6

VSS30

D9

VSS31
VSS25
VSS26
VSS27
VSS28
VSS29
VSS32
VSS33
VSS34

F1

VSS35

F4

VSS38
VSS36
VSS37
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46

J8

VSS52
VSS47
VSS48
VSS49
VSS50

13 OF 13

VSS51
VSS53
VSS55
VSS54
VSS56
VSS59
VSS60
VSS61
VSS57
VSS58
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS74
VSS73
VSS75
VSS77
VSS78
VSS80
VSS81
VSS82
VSS84
VSS85
VSS93
VSS95
VSS96
VSS83
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS94
VSS97
VSS98

VSS99
VSS100
VSS101

VSS76

VSS79

J51
K1
K3
K28
K55
L5
L7
L8
L19
L33
M15
M25
M28
M35
M41
N12
N28
N46
N51
P21
P55
R8
R28
T27
T38
U13
V27
V38
V55
W2
W3
W5
W7
W8
W10
W39
W41
W43
W44
W46
W48
W49
W51
Y21
Y23
Y25
Y27
Y31
T3
U3

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Thursday, August 09, 2018

Date: Sheet of

Thursday, August 09, 2018

Date: Sheet of

5

4

3

2

Thursday, August 09, 2018

PROJECT :

GLK (GND)

GLK (GND)

GLK (GND)

ZHVA

ZHVA

ZHVA

1

8 34

8 34

8 34

1A

1A

1A

5

4

3

2

1

HARDWARE STRAPS

09

+1.8V_S5

Note: If platform is using eMMC as boot device, then
provide a pull down for this strap to disable

R500

R544
*4.7K_1%_4

R527
10K_5%_4

*4.7K_1%_4

R498
10K_5%_4

D D

C C

B B

R179
*4.7K_1%_4

R178

4.7K_1%_4

R186

4.7K_1%_4

R185
*10K_5%_4

R505
*4.7K_1%_4

R504
10K_5%_4

R234
*10K_5%_4

R219

4.7K_1%_4

R547
*10K_5%_4

R529

4.7K_1%_4

R510
*4.7K_1%_4

R503
10K_5%_4

USB_OC0#[3]

SMB_SOC_CLK[3]

GPIO_43[4]
GPIO_81[3,21]

GPIO_62[3]
GPIO_79[3]
GPIO_80[3]
GPIO_85[3]
GPIO_86[3]
GPIO_87[3]
GPIO_89[3]
GPIO_159[5]
GPIO_164[5]

R267
*4.7K_1%_4

R249

4.7K_1%_4

R554
*4.7K_1%_4

R553

4.7K_1%_4

R240

R545

*4.7K_1%_4

*4.7K_1%_4

R528

R241

4.7K_1%_4

*4.7K_1%_4

R496 10K_5%_4
R268 4.7K_1%_4

R198 *10K_5%_4
R497 10K_5%_4
R201 4.7K_1%_4
R269 10K_5%_4
R200 10K_5%_4
R213 10K_5%_4
R216 10K_5%_4
R204 10K_5%_4
R211 4.7K_1%_4
R197 4.7K_1%_4
R289 *10K_5%_4

+1.8V_S5

R215
*4.7K_1%_4

R214

4.7K_1%_4

GPIO_174 [5]
GPIO_61 [3]
GPIO_27 [5]
GPIO_28 [5]
GPIO_65 [3]
GPIO_163 [5]
AZ_CODEC_SDIN0 [5,19]
GPIO_66 [3]
GPIO_83 [3]
GPIO_172 [5]
GPIO_175 [5]
CNVI_BRI_DT [3]
GPIO_84 [3]

SPI.

Note: The default for A0 will be eSPI
due to a bug on LPC.

Hardware Strap Strap Description

PIO_174

GPIO_61

GPIO_27

GPIO_28

PIO_65

G

PIO_163

G

AZ_CODEC_SDIN0

GPIO_66

GPIO_83

GPIO_172 0 = Disable (default)

GPIO_42

GPIO_175

CNVI_BRI_DT

GPIO_84

VDD2 1.24V vs.1.20V select
0 = 1.2V(default)G

1 = 1.24V

Enable CSE(TXE3.0) ROM Bypass

0 = Disable bypass

1 = Enable Bypass
Allow eMMC as a boot source

0 = Disable

1 = Enable
Allow SPI as a boot source

0 = Disable

1 = Enable

Force DNX FW Load

0 = Do not force

1 = Force
SMBus 1.8V/3.3V mode select

0=buffers set to 3.3V

1=buffers set to 1.8V
PMU 1.8V/3.3V mode select

0=buffers set to 3.3V mode

1=buffers set to 1.8V mode
LPC No Re-Boot

0 = Disable (default)

1 = Enable
LPC 1.8V/3.3V mode select

0=buffers set to 3.3V mode

1=buffers set to 1.8V mode

SMbus No Re-Boot
1 = Enable
Top swap override

0 = Disable

1 = Enable
eSPI vs. LPC

0 = LPC mode (default)

1 = eSPI mode
eSPI Flash Sharing Mode:

0 = master attached flash sharing
(MAFS; default)

1 = slave attached flash sharing

(SAFS)

Allow SPI as a boot source

0 = Enable (default)

1 = Disable

Value

1

0

0

1

0

0

0

0

0

0

0

0

0

0

0

+1.8V_S5[3,4,5,6,7,12,15,21,22,23,27,29]

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Thursday, August 09, 2018

Date: Sheet of

Thursday, August 09, 2018

Date: Sheet of

5

4

3

2

Thursday, August 09, 2018

PROJECT :

HW STRAPS/XDP

HW STRAPS/XDP

HW STRAPS/XDP

ZHVA

ZHVA

ZHVA

9 34

9 34

1

9 34

1A

1A

1A

5

U3

M1

VREFCA

B1

VPP#B1

R9

VPP#R9

M_A_A0

P3

M_A_A1
M_A_A2
M_A_A3
M_A_A4 M_A_DQ62 M_A_DQ7
M_A_A5 M_A_DQ59 M_A_DQ0
M_A_A6 M_A_DQ61 M_A_DQ6
M_A_A7 M_A_DQ63 M_A_DQ1
M_A_A8 M_A_DQ56 M_A_DQ5
M_A_A9 M_A_DQ57 M_A_DQ2
M_A_A10 M_A_DQ60 M_A_DQ4
M_A_A11 M_A_DQ58 M_A_DQ3
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_A16

M_A_CLK0
M_A_CLK0#
M_A_CKE0

M_A_ODT0_MD
M_A_CS#0

M_A1_ZQ0 M_A2_ZQ0 M_A3_ZQ0 M_A4_ZQ0

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC

T8

A13

L2

WE_n/A14

M8

CAS_n/A15

L8

RAS_n/A16

M_A_BA#0

N2

BA0

M_A_BA#1

N8

BA1

M_A_BG#0

M2

BG0

K7

CK_t

K8

CK_c

K2

CKE

K3

ODT

L7

CS

G3

DQSL_t

B7

DQSU_t

F3

DQSL_c

A7

DQSU_c

E7

DML_n/DBIL_n

E2

DMU_n/DBIU_n

P1

RESET_n

F9

ZQ

N9

TEN

P9

ALERT_n

L3

ACT_n

T3

PAR

T7

NC

96-BALL
DDR4

R

AM@DDR4_96P

AKD5QGSTW00

M_A_CLK0

R106 *36_1%_4

M_A_CLK0#

R114 *36_1%_4

R68 5 1_1%_4

M_A_CLK0

In the middle of CPU and Double-T

M_A_CLK0#

C363 0.01u/50V_4

+1.2VSUS

C77 0.01u/ 50V_4
C358 0.01u/50V_4
C71 0.01u/ 50V_4
C87 0.01u/ 50V_4

C369 RAM@1u/6.3V_4

+2.5V_SUS

C104 RAM@1u/6.3V_4
C56 RA M@1u/6.3V_4
C59 RA M@1u/6.3V_4
C31 RA M@1u/6.3V_4
C95 RA M@1u/6.3V_4
C340 RAM@1u/6.3V_4
C115 RAM@1u/6.3V_4
C373 RAM@10u/6.3V_4
C374 RAM@10u/6.3V_4
C63 RA M@68p/50V_4

DB1 12/11, close memory

68p/50V_4

C30

+SMDDR_VREF_DQ1_M11

M_A_A[16:0][2]

+2.5V_SUS +2.5V_SUS

SI1, 0427 RF

D D

M_A_BA#0[2]
M_A_BA#1[2]
M_A_BG#0[2]

M_A_CLK0[2]
M_A_CLK0#[2]
M_A_CKE0[2]

M_A_ODT0_MD[2]

M_A_CS#0[2]

M_A_DQSP7[2] M_A_DQSP5[2] M_A_DQSP0[2]

M_A_DQSN7[2] M_A_DQSN5[2] M_A_DQSN0[2]

C C

M_A_DRAMRST#[2]

M_A_ACT#[2]

B B

M_A_BA#0
M_A_BA#1
M_A_BG#0 M_A_ALERT#
M_A_CKE0
M_A_CS#0
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_A16
M_A_ODT0_MD
M_A_ACT#
M_A_PARITY
M_A_BG#1

M_A_ODT0_MD M_A_PARITY

A A

R52 RA M@36_1%_4
R131 RAM@36_1%_4
R74 RA M@36_1%_4
R117 RAM@36_1%_4
R83 RA M@36_1%_4
R46 RA M@36_1%_4
R45 RA M@36_1%_4
R38 RA M@36_1%_4 C41 RA M@10u/6.3V_4
R71 RA M@36_1%_4
R75 RA M@36_1%_4
R398 RAM@36_1%_4
R396 RAM@36_1%_4
R400 RAM@36_1%_4
R397 RAM@36_1%_4
R399 RAM@36_1%_4
R120 RAM@36_1%_4
R401 RAM@36_1%_4
R78 RA M@36_1%_4
R29 RA M@36_1%_4
R116 RAM@36_1%_4
R88 RA M@36_1%_4
R110 RAM@36_1%_4
R136 *36_1%_4
R92 RA M@36_1%_4
R39 RA M@36_1%_4
R64 RA M@36_1%_4

R135
0_5%_4

R40
*0_5%_4

+VDDQ_VTT [11,26]
+1.2VSUS [7,11,26]
+2.5V_SUS [11,26]

M_A_DQSP7 M_A_DQSP5 M_A_DQSP0

M_A_DQSN7 M_A_DQSN5 M_A_DQSN0

+1.2VSUS +1.2VSUS +1.2VSUS +1.2VSUS

M_A_DRAMRST# M_A_DRAMRST# M_A_DRAMRST# M_A_DRAMRST#

R82 2 40_1%_4

M_A_ALERT#
M_A_ACT#
M_A_PARITY

DB1 12/11, close memory

+VDDQ_VTT

5

BYTE4_32-39
BYTE7_56-63

M_A_DQ36

G2

DQL0

M_A_DQ35

F7

DQL1

M_A_DQ37

H3

DQL2

M_A_DQ32

H7

DQL3

M_A_DQ39

H2

DQL4

M_A_DQ34

H8

DQL5

M_A_DQ38

J3

DQL6

M_A_DQ33

J7

DQL7

A3

DQU0

B8

DQU1

C3

DQU2

C7

DQU3

C2

DQU4

C8

DQU5

D3

DQU6

D7

DQU7

B3

VDD#B3

B9

VDD#B9

D1

VDD#D1

G7

VDD#G7

J1

VDD#J1

J9

VDD#J9

L1

VDD#L1

L9

VDD#L9

R1

VDD#R1

T9

VDD#T9

A1

VDDQ#A1

A9

VDDQ#A9

C1

VDDQ#C1

D9

VDDQ#D9

F2

VDDQ#F2

F8

VDDQ#F8

G1

VDDQ#G1

G9

VDDQ#G9

J2

VDDQ#J2

J8

VDDQ#J8

DB1 Option for 16Gbx16 die

B2

VSS#B2

E1

VSS#E1

E9

R89 0_5%_4

VSS#E9

G8

VSS#G8

K1

VSS#K1

K9

VSS#K9

M_A_BG#1_1 M_A_BG#1_2 M_A_BG#1 M_A_BG#1_3 M_A_BG#1 M_A_BG#1_4 M_A_BG#1

M9

VSS#M9

N1

VSS#N1

T1

VSS#T1

A2

VSSQ#A2

A8

VSSQ#A8

C9

VSSQ#C9

D2

VSSQ#D2

D8

VSSQ#D8

E3

VSSQ#E3

E8

VSSQ#E8

F1

VSSQ#F1

H1

VSSQ#H1

H9

VSSQ#H9

+VDDQ_VTT

+1.2VSUS

R111
75_1%_4

4

DB1 change

M_A_DQ36 [2]
M_A_DQ35 [2]
M_A_DQ37 [2]
M_A_DQ32 [2]
M_A_DQ39 [2]
M_A_DQ34 [2]
M_A_DQ38 [2]
M_A_DQ33 [2]

SI1, 0427 RF

M_A_DQ62 [2] M_A_DQ7 [2]
M_A_DQ59 [2] M_A_DQ0 [2]
M_A_DQ61 [2] M_A_DQ6 [2]
M_A_DQ63 [2] M_A_DQ1 [2]
M_A_DQ56 [2] M_A_DQ5 [2]
M_A_DQ57 [2] M_A_DQ2 [2]
M_A_DQ60 [2] M_A_DQ4 [2]
M_A_DQ58 [2] M_A_DQ3 [2]

+1.2VSUS +1.2VSUS +1.2VSUS +1.2VSUS

R62 *0_5%_4

+SMDDR_VREF_DQ1_M11 +SMDDR_VREF_DQ1_M11 +SMDDR_VREF_DQ1_M11

C114

M_A_BG#1 [2]

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_A16

M_A_BA#0
M_A_BA#1
M_A_BG#0

M_A_CLK0
M_A_CLK0#
M_A_CKE0

M_A_ODT0_MD
M_A_CS#0

M_A_DQSP6M_A_DQSP4

M_A_DQSN6M_A_DQSN4

68p/50V_4

M_A_DQSP6[2]M_A_DQSP4[2]

M_A_DQSN6[2]M_A_DQSN4[2]

SI1C, 0615

R90 2 40_1%_4 R81 240_1%_4

M_A_ALERT#
M_A_ACT#
M_A_PARITY

M_A_BG#1_1
M_A_BG#1_2
M_A_BG#1_3
M_A_BG#1_4

DB1 Option for 16Gbx16 die
Close DDR ball

Memory 8G & Memory 16G TABLE

R278
R279
R280
R281
R282
R283
R284
R285
R290
R291
R292
R293

4

R54 0 _5%_4
R55 0 _5%_4
R63 0 _5%_4
R409 0_5%_4

Memory 8G
0Ω CS00002JB38
0Ω CS00002JB38
0Ω CS00002JB38
0Ω CS00002JB38

UNINSTAL

UNINSTAL

UNINSTAL

UNINSTAL

INSTAL

INSTAL

INSTAL

INSTAL

U21

M1

VREFCA

B1

VPP#B1

R9

VPP#R9

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC

T8

A13

L2

WE_n/A14

M8

CAS_n/A15

L8

RAS_n/A16

N2

BA0

N8

BA1

M2

BG0

K7

CK_t

K8

CK_c

K2

CKE

K3

ODT

L7

CS

G3

DQSL_t

B7

DQSU_t

F3

DQSL_c

A7

DQSU_c

E7

DML_n/DBIL_n

E2

DMU_n/DBIU_n

P1

RESET_n

F9

ZQ

N9

TEN

P9

ALERT_n

L3

ACT_n

T3

PAR

T7

NC

96-BALL
DDR4

R

AM@DDR4_96P

240Ω CS12402FB03
240Ω CS12402FB03
240Ω CS12402FB03
240Ω CS12402FB03
INSTAL
INSTAL
INSTAL
INSTAL
UNINSTAL
UNINSTAL
UNINSTAL
UNINSTAL

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B3
VDD#B9
VDD#D1

VDD#G7

VDD#J1
VDD#J9
VDD#L1
VDD#L9
VDD#R1
VDD#T9

VDDQ#A1

VDDQ#A9
VDDQ#C1
VDDQ#D9
VDDQ#F2
VDDQ#F8
VDDQ#G1
VDDQ#G9

VDDQ#J2

VDDQ#J8

VSS#B2
VSS#E1

VSS#E9
VSS#G8
VSS#K1
VSS#K9
VSS#M9
VSS#N1
VSS#T1

VSSQ#A2
VSSQ#A8

VSSQ#C9
VSSQ#D2
VSSQ#D8

VSSQ#E3

VSSQ#E8

VSSQ#F1
VSSQ#H1
VSSQ#H9

Memory 16G

BYTE6_48-55
BYTE5_40-47

M_A_DQ50

G2

M_A_DQ51

F7

M_A_DQ48

H3

M_A_DQ55

H7

M_A_DQ49

H2

M_A_DQ54

H8

M_A_DQ52

J3

M_A_DQ53

J7

M_A_DQ42

A3

M_A_DQ44

B8

M_A_DQ40

C3

M_A_DQ45

C7

M_A_DQ43

C2

M_A_DQ47

C8

M_A_DQ41

D3

M_A_DQ46

D7

B3
B9
D1
G7
J1
J9
L1
L9
R1
T9

A1
A9
C1
D9
F2
F8
G1
G9
J2
J8

DB1 Option for 16Gbx16 die

B2
E1
E9

R96 0 _5%_4

G8
K1
K9
M9
N1
T1

A2
A8
C9
D2
D8
E3
E8
F1
H1
H9

3

+2.5V_SUS

68p/50V_4

C62

DB1 change

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_A16

M_A_BA#0
M_A_BA#1
M_A_BG#0

M_A_CLK0
M_A_CLK0#
M_A_CKE0

M_A_ODT0_MD
M_A_CS#0

M_A_DQSP3
M_A_DQSP2

M_A_DQSN3
M_A_DQSN2

M_A_DQ50 [2]
M_A_DQ51 [2]
M_A_DQ48 [2]
M_A_DQ55 [2]
M_A_DQ49 [2]
M_A_DQ54 [2]
M_A_DQ52 [2]
M_A_DQ53 [2]

SI1, 0427 RF

M_A_DQ42 [2]
M_A_DQ44 [2]
M_A_DQ40 [2]
M_A_DQ45 [2]
M_A_DQ43 [2]
M_A_DQ47 [2]
M_A_DQ41 [2]
M_A_DQ46 [2]

R60 *0_5%_4

M_A_DQSP3[2]
M_A_DQSP2[2]

M_A_DQSN3[2]
M_A_DQSN2[2]

SI1C, 0615

M_A_ALERT#
M_A_ACT#
M_A_PARITY

Place these Caps near Channel A

1uF/10uF 4pcs on each side of connector

+1.2VSUS

C72 RA M@1u/6.3V_4
C366 RAM@1u/6.3V_4
C362 RAM@1u/6.3V_4
C91 RA M@1u/6.3V_4
C75 RA M@1u/6.3V_4
C99 RA M@1u/6.3V_4
C109 RAM@1u/6.3V_4
C81 RA M@1u/6.3V_4
C38 RA M@1u/6.3V_4
C23 RA M@1u/6.3V_4
C80 RA M@1u/6.3V_4

C386 RAM@10u/6.3V_4
C336 RAM@10u/6.3V_4
C36 RA M@10u/6.3V_4
C355 RAM@10u/6.3V_4

C113 RAM@1u/6.3V_4
C382 RAM@1u/6.3V_4
C342 RAM@1u/6.3V_4
C337 RAM@1u/6.3V_4
C43 RA M@1u/6.3V_4

SI1, 0421 add

+VDDQ_VTT

DB1 Intel

+SMDDR_VREF_DQ1_M11

DB1 Intel

+SMDDR_VREF_DQ1_M1 +1.2VSUS

C25

C26

68p/50V_4

3.3p/50V_4

U4

M1

VREFCA

B1

VPP#B1

R9

VPP#R9

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC

T8

A13

L2

WE_n/A14

M8

CAS_n/A15

L8

RAS_n/A16

N2

BA0

N8

BA1

M2

BG0

K7

CK_t

K8

CK_c

K2

CKE

K3

ODT

L7

CS

G3

DQSL_t

B7

DQSU_t

F3

DQSL_c

A7

DQSU_c

E7

DML_n/DBIL_n

E2

DMU_n/DBIU_n

P1

RESET_n

F9

ZQ

N9

TEN

P9

ALERT_n

L3

ACT_n

T3

PAR

T7

NC

96-BALL
DDR4

R

AM@DDR4_96P

C94 1 u/6.3V_4
C46 1 u/6.3V_4
C338 1u/6.3V_4
C82 1 u/6.3V_4
C121 1u/6.3V_4
C76 1 u/6.3V_4
C339 1u/6.3V_4
C122 1u/6.3V_4

C29 RA M@10u/6.3V_4
C52 RA M@10u/6.3V_4

C350 0.1u/16V_4
C69 2 .2u/6.3V_4
C64 0 .047u/25V_4
C352 0.047u/25V_4
C66 0 .047u/25V_4
C42 0 .047u/25V_4

SI1B, 0603

SI1, 0417 RF

C65
2200p/50V_4

DB1 RF

3

BYTE3_24-31
BYTE2_16-23

G2

DQL0

F7

DQL1

H3

DQL2

H7

DQL3

H2

DQL4

H8

DQL5

J3

DQL6

J7

DQL7

A3

DQU0

B8

DQU1

C3

DQU2

C7

DQU3

C2

DQU4

C8

DQU5

D3

DQU6

D7

DQU7

B3

VDD#B3

B9

VDD#B9

D1

VDD#D1

G7

VDD#G7

J1

VDD#J1

J9

VDD#J9

L1

VDD#L1

L9

VDD#L9

R1

VDD#R1

T9

VDD#T9

A1

VDDQ#A1

A9

VDDQ#A9

C1

VDDQ#C1

D9

VDDQ#D9

F2

VDDQ#F2

F8

VDDQ#F8

G1

VDDQ#G1

G9

VDDQ#G9

J2

VDDQ#J2

J8

VDDQ#J8

DB1 Option for 16Gbx16 die

B2

VSS#B2

E1

VSS#E1

E9

VSS#E9

G8

VSS#G8

K1

VSS#K1

K9

VSS#K9

M9

VSS#M9

N1

VSS#N1

T1

VSS#T1

A2

VSSQ#A2

A8

VSSQ#A8

C9

VSSQ#C9

D2

VSSQ#D2

D8

VSSQ#D8

E3

VSSQ#E3

E8

VSSQ#E8

F1

VSSQ#F1

H1

VSSQ#H1

H9

VSSQ#H9

M_A_DQ29
M_A_DQ26
M_A_DQ25
M_A_DQ31
M_A_DQ24
M_A_DQ27
M_A_DQ30
M_A_DQ28

M_A_DQ19
M_A_DQ21
M_A_DQ17
M_A_DQ20
M_A_DQ16
M_A_DQ23
M_A_DQ18
M_A_DQ22

R95 0 _5%_4

R61 *0_5%_4

+VREF_CA_CPU[2]

C40
68p/50V_4

2

2

+2.5V_SUS

68p/50V_4

M_A_DQSP1[2]

M_A_DQSN1[2]

DB1 changeDB1 change

C365

M_A_DQ29 [2]
M_A_DQ26 [2]
M_A_DQ25 [2]
M_A_DQ31 [2]
M_A_DQ24 [2]
M_A_DQ27 [2]
M_A_DQ30 [2]
M_A_DQ28 [2]

SI1, 0427 RF

M_A_DQ19 [2]
M_A_DQ21 [2]
M_A_DQ17 [2]
M_A_DQ20 [2]
M_A_DQ16 [2]
M_A_DQ23 [2]
M_A_DQ18 [2]
M_A_DQ22 [2]

SI1C, 0615

R414 240_1%_4

M_A_ALERT#
M_A_ACT#
M_A_PARITY

VREF DQ1 M1 Solution

+VREF_CA_CPU +SMDDR_ VREF_DQ1_M11

R133 24.9_1%_4

R140

C118

0.022u/25V_4

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_A16

M_A_BA#0
M_A_BA#1
M_A_BG#0

M_A_CLK0
M_A_CLK0#
M_A_CKE0

M_A_ODT0_MD
M_A_CS#0

M_A_DQSP1

M_A_DQSN1

RAM@2_1%_6

+1.2VSUS

M1
B1
R9

P3
P7
R3
N7
N3
P8
P2
R8
R2
R7
M3

M7

M8

N2
N8
M2

K7
K8
K2

K3

G3
B7

A7

E7
E2

P1
N9

P9

R146

3.65K_1%_4

R145

3.65K_1%_4

SI1, 0417 RF

C344

0.1u/16V_4

C37

3.3p/50V_4

C39
2200p/50V_4

DB1 RF

U22

T2
T8

L2
L8

L7

F3

F9

L3
T3

T7

R

VREFCA
VPP#B1
VPP#R9

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
WE_n/A14
CAS_n/A15
RAS_n/A16

BA0
BA1
BG0

CK_t
CK_c
CKE

ODT
CS

DQSL_t
DQSU_t

DQSL_c
DQSU_c

DML_n/DBIL_n
DMU_n/DBIU_n

RESET_n
ZQ
TEN

ALERT_n
ACT_n
PAR

NC

96-BALL
DDR4

AM@DDR4_96P

1

BYTE1_8-15
BYTE0_0-7

M_A_DQ12

G2

DQL0

M_A_DQ8

F7

DQL1

M_A_DQ11

H3

DQL2

M_A_DQ10

H7

DQL3

M_A_DQ14

H2

DQL4

M_A_DQ9

H8

DQL5

M_A_DQ13

J3

DQL6

M_A_DQ15

J7

DQL7

A3

DQU0

B8

DQU1

C3

DQU2

C7

DQU3

C2

DQU4

C8

DQU5

D3

DQU6

D7

DQU7

B3

VDD#B3

B9

VDD#B9

D1

VDD#D1

G7

VDD#G7

J1

VDD#J1

J9

VDD#J9

L1

VDD#L1

L9

VDD#L9

R1

VDD#R1

T9

VDD#T9

A1

VDDQ#A1

A9

VDDQ#A9

C1

VDDQ#C1

D9

VDDQ#D9

F2

VDDQ#F2

F8

VDDQ#F8

G1

VDDQ#G1

G9

VDDQ#G9

J2

VDDQ#J2

J8

VDDQ#J8

DB1 Option for 16Gbx16 die

B2

VSS#B2

E1

VSS#E1

E9

VSS#E9
VSS#G8
VSS#K1

VSS#K9
VSS#M9
VSS#N1

VSS#T1

VSSQ#A2
VSSQ#A8
VSSQ#C9
VSSQ#D2
VSSQ#D8
VSSQ#E3
VSSQ#E8
VSSQ#F1
VSSQ#H1
VSSQ#H9

R415 0_5%_4

G8
K1
K9
M9

R411 *0_5%_4

N1
T1

A2
A8
C9
D2
D8
E3
E8
F1
H1
H9

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev

DDR4 Memory Down (CH. A)

DDR4 Memory Down (CH. A)

DDR4 Memory Down (CH. A)

Date: Sheet of

Thursday, August 09, 2018

Date: Sheet of

Thursday, August 09, 2018

Date: Sheet of

Thursday, August 09, 2018

1

M_A_DQ12 [2]
M_A_DQ8 [2]
M_A_DQ11 [2]
M_A_DQ10 [2]
M_A_DQ14 [2]
M_A_DQ9 [2]
M_A_DQ13 [2]
M_A_DQ15 [2]

10

SI1C, 0615

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

ZHVA

ZHVA

ZHVA

10 34

10 34

10 34

1A

1A

1A

5

BYTE4_32-39

DB1 change DB1 change DB1 change DB1 change

+SMDDR_VREF_DQ1_M1

C331

M_B_A[16:0][2]

OBM@68p/50V_4

SI1, 0427 RF

D D

M_B_BA#0[2]
M_B_BA#1[2]
M_B_BG#0[2]

M_B_CLK0[2]
M_B_CLK0#[2]
M_B_CKE0[2]

M_B_ODT0_MD[2]

M_B_CS#0[2]

M_B_DQSP4[2]
M_B_DQSP7[2]

M_B_DQSN4[2]
M_B_DQSN7[2]

C C

M_B_DRAMRST#[2]

B B

M_B_BA#0
M_B_BA#1
M_B_BG#0
M_B_CKE0
M_B_CS#0
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_A16
M_B_ODT0_MD
M_B_ACT#
M_B_PARITY
M_B_BG#1

A A

M_B_ODT0_MD

R118 OBM@0_5%_4

R93 OBM@240_1%_4

M_B_ACT#[2]

R51 OBM@36_1%_4
R128 OBM@36_1%_4
R79 OBM@36_1%_4
R126 OBM@36_1%_4
R84 OBM@36_1%_4
R50 OBM@36_1%_4
R44 OBM@36_1%_4
R43 OBM@36_1%_4
R69 OBM@36_1%_4
R76 OBM@36_1%_4
R37 OBM@36_1%_4
R404 OBM@36_1%_4
R36 OBM@36_1%_4
R35 OBM@36_1%_4
R405 OBM@36_1%_4
R119 OBM@36_1%_4
R395 OBM@36_1%_4
R73 OBM@36_1%_4
R31 OBM@36_1%_4
R102 OBM@36_1%_4
R86 OBM@36_1%_4
R105 OBM@36_1%_4
R122 *OBM@36_1%_4
R100 OBM@36_1%_4
R42 OBM@36_1%_4
R57 OBM@36_1%_4

+VDDQ_VTT [10,26]
+1.2VSUS [7,10,26]
+2.5V_SUS [10,26]

5

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_A16

M_B_DQSP4
M_B_DQSP7

M_B_DQSN4
M_B_DQSN7

M_B1_ZQ0

M_B_ALERT# M_B_ALERT# M_B_ALERT# M_B_ALERT#

+VDDQ_VTT

DG 0.5 7/12, close T routing

U19

M1

VREFCA

B1

VPP#B1

R9

VPP#R9

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC

T8

A13

L2

WE_n/A14

M8

CAS_n/A15

L8

RAS_n/A16

N2

BA0

N8

BA1

M2

BG0

K7

CK_t

K8

CK_c

K2

CKE

K3

ODT

L7

CS

G3

DQSL_t

B7

DQSU_t

F3

DQSL_c

A7

DQSU_c

E7

DML_n/DBIL_n

E2

DMU_n/DBIU_n

P1

RESET_n

F9

ZQ

N9

TEN

P9

ALERT_n

L3

ACT_n

T3

PAR

T7

NC

96-BALL
DDR4

O

BM@DDR4_96P

Hynix AKD5JGETW00--H5TC4G63AFR-PBA

DB1 12/11, close memory

M_B_CLK0
M_B_CLK0#

M_B_ALERT#

R70 OBM@51_1%_4

M_B_CLK0

M_B_CLK0#

+1.2VSUS

+2.5V_SUS

C45 OBM@0.01u/50V_4
C97 OBM@0.01u/50V_4
C90 OBM@0.01u/50V_4
C101 OBM@0.01u/50V_4
C74 OBM@0.01u/50V_4

C34 OBM@1u/6.3V_4
C330 OBM@1u/6.3V_4
C103 OBM@1u/6.3V_4
C106 OBM@1u/6.3V_4
C379 OBM@1u/6.3V_4
C61 OBM@1u/6.3V_4
C53 OBM@1u/6.3V_4
C88 OBM@1u/6.3V_4
C48 OBM@10u/6.3V_4
C334 OBM@10u/6.3V_4
C92 OBM@68p/50V_4

DB1 12/11, close memory

BYTE7_56-63

G2

DQL0

F7

DQL1

H3

DQL2

H7

DQL3

H2

DQL4

H8

DQL5

J3

DQL6

J7

DQL7

A3

DQU0

B8

DQU1

C3

DQU2

C7

DQU3

C2

DQU4

C8

DQU5

D3

DQU6

D7

DQU7

B3

VDD#B3

B9

VDD#B9

D1

VDD#D1

G7

VDD#G7

J1

VDD#J1

J9

VDD#J9

L1

VDD#L1

L9

VDD#L9

R1

VDD#R1

T9

VDD#T9

A1

VDDQ#A1

A9

VDDQ#A9

C1

VDDQ#C1

D9

VDDQ#D9

F2

VDDQ#F2

F8

VDDQ#F8

G1

VDDQ#G1

G9

VDDQ#G9

J2

VDDQ#J2

J8

VDDQ#J8

B2

VSS#B2

E1

VSS#E1

E9

R99 OBM@0_5%_4

VSS#E9

G8

VSS#G8

K1

VSS#K1

K9

VSS#K9

M_B_BG#1_1

M9

VSS#M9

N1

VSS#N1

T1

VSS#T1

A2

VSSQ#A2

A8

VSSQ#A8

C9

VSSQ#C9

D2

VSSQ#D2

D8

VSSQ#D8

E3

VSSQ#E3

E8

VSSQ#E8

F1

VSSQ#F1

H1

VSSQ#H1

H9

VSSQ#H9

R108 *OBM@36_1%_4
R115 *OBM@36_1%_4

+1.2VSUS

R113
OBM@75_1%_4

M_B_DQ36
M_B_DQ35
M_B_DQ33
M_B_DQ32
M_B_DQ37
M_B_DQ38
M_B_DQ34
M_B_DQ39

M_B_DQ60
M_B_DQ58
M_B_DQ61
M_B_DQ57
M_B_DQ56
M_B_DQ63
M_B_DQ62
M_B_DQ59

+VDDQ_VTT

4

BYTE6_48-55

U1

M1

VREFCA

B1

VPP#B1

R9

VPP#R9

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC

T8

A13

L2

WE_n/A14

M8

CAS_n/A15

L8

RAS_n/A16

N2

BA0

N8

BA1

M2

BG0

K7

CK_t

K8

CK_c

K2

CKE

K3

ODT

L7

CS

G3

DQSL_t

B7

DQSU_t

F3

DQSL_c

A7

DQSU_c

E7

DML_n/DBIL_n

E2

DMU_n/DBIU_n

P1

RESET_n

F9

ZQ

N9

TEN

P9

ALERT_n

L3

ACT_n

T3

PAR

T7

NC

96-BALL
DDR4

O

BM@DDR4_96P

240Ω CS12402FB03
240Ω CS12402FB03
240Ω CS12402FB03
240Ω CS12402FB03
INSTAL
INSTAL
INSTAL
INSTAL
UNINSTAL
UNINSTAL
UNINSTAL
UNINSTAL

+2.5V_SUS+2.5V_SUS

M_B_DQSP6[2]
M_B_DQSP5[2]

M_B_DQSN6[2]
M_B_DQSN5[2]

C58

OBM@68p/50V_4

M_B_BG#1 [2]

+SMDDR_VREF_DQ1_M1

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_A16

M_B_BA#0
M_B_BA#1
M_B_BG#0

M_B_CLK0
M_B_CLK0#
M_B_CKE0

M_B_CS#0
M_B_DQSP6

M_B_DQSP5
M_B_DQSN6

M_B_DQSN5

M_B_DQ36 [2]
M_B_DQ35 [2]
M_B_DQ33 [2]
M_B_DQ32 [2]
M_B_DQ37 [2]
M_B_DQ38 [2]
M_B_DQ34 [2]
M_B_DQ39 [2]

SI1, 0427 RF

M_B_DQ60 [2]
M_B_DQ58 [2]
M_B_DQ61 [2]
M_B_DQ57 [2]
M_B_DQ56 [2]
M_B_DQ63 [2]
M_B_DQ62 [2]
M_B_DQ59 [2]

+1.2VSUS +1.2VSUS +1.2VSUS +1.2VSUS

R66 *OBM@0_5%_4

SI1C, 0615 SI1C, 0615 SI1C, 0615 SI1C, 0615

M_B_DRAMRST#M_B_DRAMRST# M_B_DRAMRST#

R80 OBM@240_1%_4

M_B_BG#1_1
M_B_BG#1_2
M_B_BG#1_3
M_B_BG#1_4

DB1 Option for 16Gbx16 die
Close DDR ball

Memory 8G & Memory 16G TABLE

R278
R279
R280
R281
R282
R283
R284
R285
R290
R291
R292
R293

4

0Ω CS00002JB38
0Ω CS00002JB38
0Ω CS00002JB38
0Ω CS00002JB38

M_B2_ZQ0

M_B_ACT#M_B_ACT# M_B_ACT# M_B_ACT#
M_B_PARITY M_B_PARITYM_B_PARITY

R65 OBM@0_5%_4
R56 OBM@0_5%_4
R408 OBM@0_5%_4
R59 OBM@0_5%_4

Memory 8G Memory 16G

UNINSTAL
UNINSTAL
UNINSTAL
UNINSTAL
INSTAL
INSTAL
INSTAL
INSTAL

BYTE5_40-47

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B3

VDD#B9
VDD#D1
VDD#G7

VDD#J1

VDD#J9

VDD#L1

VDD#L9
VDD#R1

VDD#T9

VDDQ#A1

VDDQ#A9
VDDQ#C1
VDDQ#D9

VDDQ#F2

VDDQ#F8
VDDQ#G1
VDDQ#G9

VDDQ#J2

VDDQ#J8

VSS#B2
VSS#E1
VSS#E9
VSS#G8
VSS#K1
VSS#K9

VSS#M9

VSS#N1
VSS#T1

VSSQ#A2

VSSQ#A8

VSSQ#C9

VSSQ#D2

VSSQ#D8

VSSQ#E3

VSSQ#E8

VSSQ#F1

VSSQ#H1

VSSQ#H9

G2
F7
H3
H7
H2
H8
J3
J7

A3
B8
C3
C7
C2
C8
D3
D7

B3
B9
D1
G7
J1
J9
L1
L9
R1
T9

A1
A9
C1
D9
F2
F8
G1
G9
J2
J8

B2
E1
E9
G8
K1
K9
M9
N1
T1

A2
A8
C9
D2
D8
E3
E8
F1
H1
H9

3

M_B_DQ53

M_B_DQ53 [2]

M_B_DQ50

M_B_DQ50 [2]

M_B_DQ55

M_B_DQ55 [2]

M_B_DQ51

M_B_DQ51 [2]

M_B_DQ49

M_B_DQ49 [2]

M_B_DQ48

M_B_DQ48 [2]

M_B_DQ52

M_B_DQ52 [2]

M_B_DQ54

M_B_DQ54 [2]

M_B_DQ41
M_B_DQ44
M_B_DQ42
M_B_DQ45
M_B_DQ47
M_B_DQ40
M_B_DQ43
M_B_DQ46

R87 OBM@0_5%_4

M_B_BG#1_2 M_B_BG#1

+1.2VSUS

SI1, 0427 RF

M_B_DQ41 [2]
M_B_DQ44 [2]
M_B_DQ42 [2]
M_B_DQ45 [2]
M_B_DQ47 [2]
M_B_DQ40 [2]
M_B_DQ43 [2]
M_B_DQ46 [2]

R67 *OBM@0_5%_4

Place these Caps near Channel B

1uF/10uF 4pcs on each side of connector

C356 OBM@1u/6.3V_4
C341 OBM@1u/6.3V_4
C333 OBM@1u/6.3V_4
C44 OBM@1u/6.3V_4
C375 OBM@1u/6.3V_4
C359 OBM@1u/6.3V_4
C96 OBM@1u/6.3V_4
C371 OBM@1u/6.3V_4
C73 OBM@1u/6.3V_4
C78 OBM@1u/6.3V_4
C367 OBM@1u/6.3V_4
C372 OBM@10u/6.3V_4

C55 OBM@10u/6.3V_4
C79 OBM@10u/6.3V_4
C60 OBM@10u/6.3V_4
C68 OBM@10u/6.3V_4

C354 OBM@1u/6.3V_4
C360 OBM@1u/6.3V_4
C84 OBM@1u/6.3V_4
C27 OBM@1u/6.3V_4
C357 OBM@1u/6.3V_4

SI1, 0421 add

+SMDDR_VREF_DQ1_M1 +SMDDR_VREF_DQ1_M1

+2.5V_SUS

C335

OBM@68p/50V_4

M_B_DQSP3[2]
M_B_DQSP0[2]

M_B_DQSN3[2]
M_B_DQSN0[2]

R412 OBM@240_1%_4

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_A16

M_B_BA#0
M_B_BA#1
M_B_BG#0

M_B_CLK0
M_B_CLK0#
M_B_CKE0 M_B_CKE0

M_B_ODT0_MD M_B_ODT0_MDM_B_ODT0_MD
M_B_CS#0

M_B_DQSP3
M_B_DQSP0

M_B_DQSN3
M_B_DQSN0

M_B_DRAMRST#

M_B3_ZQ0

M_B_PARITY

+VDDQ_VTT

C19 OBM@1u/6.3V_4
C111 OBM@1u/6.3V_4
C67 OBM@1u/6.3V_4
C28 OBM@1u/6.3V_4
C17 OBM@1u/6.3V_4
C21 OBM@1u/6.3V_4
C20 OBM@1u/6.3V_4
C18 OBM@1u/6.3V_4

C15 OBM@10u/6.3V_4
C16 OBM@10u/6.3V_4

DB1 Intel

+SMDDR_VREF_DQ1_M1

C33 OBM@0.1u/16V_4
C353 OBM@2.2u/6.3V_4
C32 OBM@0.047u/25V_4
C349 OBM@0.047u/25V_4
C348 OBM@0.047u/25V_4
C24 OBM@0.047u/25V_4

DB1 Intel

+SMDDR_VREF_DQ1_M1

C351
OBM@3.3p/50V_4

SI1, 0417 RF

C47
OBM@68p/50V_4

DB1 RF

3

U20

M1

VREFCA

B1

VPP#B1

R9

VPP#R9

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC

T8

A13

L2

WE_n/A14

M8

CAS_n/A15

L8

RAS_n/A16

N2

BA0

N8

BA1

M2

BG0

K7

CK_t

K8

CK_c

K2

CKE

K3

ODT

L7

CS

G3

DQSL_t

B7

DQSU_t

F3

DQSL_c

A7

DQSU_c

E7

DML_n/DBIL_n

E2

DMU_n/DBIU_n

P1

RESET_n

F9

ZQ

N9

TEN

P9

ALERT_n

L3

ACT_n

T3

PAR

T7

NC

96-BALL
DDR4

O

BM@DDR4_96P

SI1B, 0603

C347
OBM@2200p/50V_4

2

BYTE3_24-31

BYTE0_0-7

M_B_DQ30

G2

DQL0

F7

DQL1

H3

DQL2

H7

DQL3

H2

DQL4

H8

DQL5

J3

DQL6

J7

DQL7

A3

DQU0

B8

DQU1

C3

DQU2

C7

DQU3

C2

DQU4

C8

DQU5

D3

DQU6

D7

DQU7

B3

VDD#B3

B9

VDD#B9

D1

VDD#D1

G7

VDD#G7

J1

VDD#J1

J9

VDD#J9

L1

VDD#L1

L9

VDD#L9

R1

VDD#R1

T9

VDD#T9

A1

VDDQ#A1

A9

VDDQ#A9

C1

VDDQ#C1

D9

VDDQ#D9

F2

VDDQ#F2

F8

VDDQ#F8

G1

VDDQ#G1

G9

VDDQ#G9

J2

VDDQ#J2

J8

VDDQ#J8

B2

VSS#B2

E1

VSS#E1

E9

R413 OBM@0_5%_4

VSS#E9

G8

VSS#G8

K1

VSS#K1

K9

VSS#K9

M_B_BG#1_3 M_B_BG#1 M_B_BG#1_4 M_B_BG#1

M9

VSS#M9

N1

VSS#N1

T1

VSS#T1

A2

VSSQ#A2

A8

VSSQ#A8

C9

VSSQ#C9

D2

VSSQ#D2

D8

VSSQ#D8

E3

VSSQ#E3

E8

VSSQ#E8

F1

VSSQ#F1

H1

VSSQ#H1

H9

VSSQ#H9

+VREFDQ_SB_M3[2]

+1.2VSUS

M_B_DQ28
M_B_DQ31
M_B_DQ24
M_B_DQ27
M_B_DQ25
M_B_DQ29
M_B_DQ26

M_B_DQ7
M_B_DQ1
M_B_DQ5
M_B_DQ0
M_B_DQ6
M_B_DQ2
M_B_DQ4
M_B_DQ3

R410 *OBM@0_5%_4

C100
OBM@68p/50V_4

M_B_DQ30 [2]
M_B_DQ28 [2]

+2.5V_SUS
M_B_DQ31 [2]
M_B_DQ24 [2]
M_B_DQ27 [2]
M_B_DQ25 [2]
M_B_DQ29 [2]
M_B_DQ26 [2]

M_B_DQ7 [2]
M_B_DQ1 [2]
M_B_DQ5 [2]
M_B_DQ0 [2]
M_B_DQ6 [2]
M_B_DQ2 [2]
M_B_DQ4 [2]
M_B_DQ3 [2]

C35

OBM@68p/50V_4

SI1, 0427 RF

M_B_DQSP1[2]
M_B_DQSP2[2]

M_B_DQSN1[2]
M_B_DQSN2[2]

+1.2VSUS+1.2VSUS+1.2VSUS+1.2VSUS

R77 OBM@240_1%_4

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_A16

M_B_BA#0
M_B_BA#1
M_B_BG#0

M_B_CLK0
M_B_CLK0#

M_B_CS#0
M_B_DQSP1

M_B_DQSP2
M_B_DQSN1

M_B_DQSN2

VREF DQ1 M1 Solution

+VREFDQ_SB_M3 +SMDDR_VREF_DQ1_M1

R143 OBM@24.9_1%_4

R134 OBM@2_1%_6

C123
OBM@0.022u/25V_4

SI1, 0417 RF

C83

C364

C70
OBM@2200p/50V_4

OBM@0.1u/16V_4

OBM@3.3p/50V_4

M_B4_ZQ0

+1.2VSUS

U2

M1

VREFCA

B1

VPP#B1

R9

VPP#R9

P3

A0

P7

A1

R3

A2

N7

A3

N3

A4

P8

A5

P2

A6

R8

A7

R2

A8

R7

A9

M3

A10/AP

T2

A11

M7

A12/BC

T8

A13

L2

WE_n/A14

M8

CAS_n/A15

L8

RAS_n/A16

N2

BA0

N8

BA1

M2

BG0

K7

CK_t

K8

CK_c

K2

CKE

K3

ODT

L7

CS

G3

DQSL_t

B7

DQSU_t

F3

DQSL_c

A7

DQSU_c

E7

DML_n/DBIL_n

E2

DMU_n/DBIU_n

P1

RESET_n

F9

ZQ

N9

TEN

P9

ALERT_n

L3

ACT_n

T3

PAR

T7

NC

96-BALL
DDR4

O

BM@DDR4_96P

R406
OBM@3.65K_1%_4

R138
OBM@3.65K_1%_4

DB1 RF

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Thursday, August 09, 2018

Date: Sheet of

Thursday, August 09, 2018

Date: Sheet of

2

Thursday, August 09, 2018

1

BYTE1_8-15
BYTE2_16-23

M_B_DQ10

G2

DQL0

M_B_DQ12

F7

DQL1

M_B_DQ8

H3

DQL2

M_B_DQ15

H7

DQL3

M_B_DQ9

H2

DQL4

M_B_DQ14

H8

DQL5

M_B_DQ11

J3

DQL6

M_B_DQ13

J7

DQL7

M_B_DQ16

A3

DQU0

M_B_DQ20

B8

DQU1

M_B_DQ17

C3

DQU2

M_B_DQ23

C7

DQU3

M_B_DQ19

C2

DQU4

M_B_DQ22

C8

DQU5

M_B_DQ18

D3

DQU6

M_B_DQ21

D7

DQU7

B3

VDD#B3

B9

VDD#B9

D1

VDD#D1

G7

VDD#G7

J1

VDD#J1

J9

VDD#J9

L1

VDD#L1

L9

VDD#L9

R1

VDD#R1

T9

VDD#T9

A1

VDDQ#A1

A9

VDDQ#A9

C1

VDDQ#C1

D9

VDDQ#D9

F2

VDDQ#F2

F8

VDDQ#F8

G1

VDDQ#G1

G9

VDDQ#G9

J2

VDDQ#J2

J8

VDDQ#J8

DB1 Option for 16Gbx16 dieDB1 Option for 16Gbx16 dieDB1 Option for 16Gbx16 dieDB1 Option for 16Gbx16 die

B2

VSS#B2

E1

VSS#E1

E9

VSS#E9

VSS#G8

VSS#K1

VSS#K9
VSS#M9
VSS#N1

VSS#T1

VSSQ#A2
VSSQ#A8
VSSQ#C9
VSSQ#D2
VSSQ#D8
VSSQ#E3
VSSQ#E8
VSSQ#F1
VSSQ#H1
VSSQ#H9

R91 OBM@0_5%_4

G8
K1
K9
M9
N1
T1

A2
A8
C9
D2
D8
E3
E8
F1
H1
H9

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

DDR4 Memory Down (CH. B)

DDR4 Memory Down (CH. B)

DDR4 Memory Down (CH. B)

1

R58 *OBM@0_5%_4

ZHVA

ZHVA

ZHVA

M_B_DQ10 [2]
M_B_DQ12 [2]
M_B_DQ8 [2]
M_B_DQ15 [2]
M_B_DQ9 [2]
M_B_DQ14 [2]
M_B_DQ11 [2]
M_B_DQ13 [2]

M_B_DQ16 [2]
M_B_DQ20 [2]
M_B_DQ17 [2]
M_B_DQ23 [2]
M_B_DQ19 [2]
M_B_DQ22 [2]
M_B_DQ18 [2]
M_B_DQ21 [2]

11 34

11 34

11 34

11

1A

1A

1A

5

SERIRQ is 1.8V_S5 at EC side but

SERIRQ is 1.8V_S5 at EC side but

SERIRQ

D D

C C

IRQ_SERIRQ[13] SOC_SERIRQ [5]

+3V_S5 [3,6,7,13,15,22,24,26,29]
+3V [4,5,13,14,16,17,18,19,20,21,22,24,25,26,27,28,29,30]
+1.8V_S5 [3,4,5,6,7,9,15,21,22,23,27,29]

WAKE_SRC_WLAN[21]

SERIRQ is 1.8V_S5 at EC side butSERIRQ is 1.8V_S5 at EC side but

3V_S5 at CPU/TPM side

3V_S5 at CPU/TPM side

3V_S5 at CPU/TPM side3V_S5 at CPU/TPM side

+1.8V_S5 +3V_S5

*NTS0101GW

6

5

4

B

1 2

R163 *10K_5%_4

R522
*10K_5%_4

VCCA1VCCB

321

Q37
*PJA138K

GND2EO

3

A

R162 *S_4

IRQ_SERIRQ SOC_SERIRQ

+3V_S5 +1.8V_S5 +1.8V_S5

R550
*10K_5%_4

1 2

10/30 Add WLAN WAKE follow Intel

PCIE_WLAN_WAKE# [3]

11/02 modify

SOC_SERIRQ

+1.8V_S5

4

+3V_S5

R158 10K_5%_4U7

RSMRST#[13]

3

PMU Set to 3.3V

R177 *S_4

GND

1 2

R168
*100K_1%_4

SOC_RSMRST# [6]

2

1

12

G Sensor INT

ACCEL_INTA_SUB[20]

c

heck it if need pull up

R282 *0_5%_4

12

+3V

Q12
*2N7002K

GSENSOR_INT [5]

R310
*10K_5%_4

1 2

3

2

1

GND

Q20
*2N7002K

3

2

1

HOLE13

HOLE14

*O-ZHV-10

*O-ZHV-10

B B

A A

1

HOLE7

HOLE12

*spad-ZHV-30

*O-ZHV-20

1

HOLE4
*H-O159X114D159X114N

1

HOLE15

HOLE9

*O-ZHV-15

*SPAD-C315

1

HOLE1
*H-TBC197I130D110P2

1

1

1

HOLE6
*h-o138x118d138x118n

1

HOLE8
*SPAD-C315

1

5

HOLE10
*H-TC276IC154BC315D134P2

1

HOLE5
*h-tc276ic134bc266d134p2

1

HOLE3
*h-o130x118d130x118n

HOLE16
*SPAD-ZHV-17

1

1

HOLE2
*H-TBC315I130D110P2

1

1

HOLE11
*SPAD-RE260X774NP

1

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Thursday, August 09, 2018

Date: Sheet of

Thursday, August 09, 2018

Date: Sheet of

4

3

2

Thursday, August 09, 2018

PROJECT :

Level Shift/Hole

Level Shift/Hole

Level Shift/Hole

ZHVA

ZHVA

ZHVA

1

1A

1A

1A

3412

3412

3412

5

CLK_PCI_EC[5]

LPC_LFRAME#[5,21]

C288

0.1u/16V _4

PLTRST#[6 ,17,21,22]

PCH_SUSPWRDNACK[6]

IOAC_WLAN_WAKE#[21]

TPD_INT#[15]

SYS_SHDN#[24,30]

1 2

L6 BLM15AG121SN1D

12 mils

C255

0.1u/16V _4

0.1u/16V _4

R275 2.2_5%_ 6

+3V_S5

LPC_LAD0[5,21]
LPC_LAD1[5,21]
LPC_LAD2[5,21]
LPC_LAD3[5,21]

C277 180p/50 V_4

DDR4_SUSO N_2V5[26]

IRQ_SERIRQ[12]

SIO_EXT_S CI#[5]

TP55

TP15

DNBSWON#[6]

EC_FPBACK#[14]

IOAC_RST#[21,22]
PCH_BLON_EC[14]
LAN_WA KE#[22]

TPCLK[15]

SUSB#[6]

EC_PWROK[6]

ME_WR#[4]
AMP_MUTE#[19]

PTP_PWR_EN#[15]

MY0[15]
MY1[15]
MY2[15]
MY3[15]
MY4[15]
MY5[15]
MY6[15]
MY7[15]
MY8[15]

MY9[15]
MY10[15]
MY11[15]
MY12[15]
MY13[15]
MY14[15]
MY15[15]

MX0[1 5]
MX1[1 5]
MX2[1 5]
MX3[1 5]
MX4[1 5]
MX5[1 5]
MX6[1 5]
MX7[1 5]

TPD_INT#_R

C254

180p/50V_4

0.1u/16V _4

ECAGND

C427

EC_PWROK

C279

C268

0.1u/16V _4

PROCHOT_EC

WRST#
IOAC_WLAN_WAKE#

DNBSWON#

SUSB#

PTP_PWR_EN#

PCH_SPI_CLK_EC
PCH_SPI_SO_EC

PCH_SPI_SI_EC
SPI_CS0# _UR_ME
GPG2

TPD_INT#_R

R23533_5%_4

SYS_SHDN#_ R

R253*S_4

EC(KBC)

+3VPCU_EC and +3V_RTC
minimum trace width 12mils.

+3V_LDO_EC

D D

CLK_PCI_EC

R305

C C

B B

*22_5%_4

C272
*10p/50V _4

TP9
TP11
TP54

TS_EN[14]

Prevent ESD/EOS Layout near EC

+3V_LDO_EC

DNBSWON#
SUSB#
SUSC#

C294 180p/50 V_4

R346 2.2_5%_ 6

R506
100K_5% _4

C425
1u/6.3V_ 4

R339 33_5%_ 4

0.1u/16V _4

1

D18
RB500V-40

2

C438

TS_EN_C

Prevent ESD/EOS Layout near device

VSTBY_FSPI

0.1u/16V _4

+3V_EC

+A3VPCU

+3VPCU_EC

C302

C267

0.1u/16V _4

10

22
13

17

126

15
23
14

16

113
123

86
85
88
87
90
89

119

33

108
109

125
105

103
102
101
100

36
37
38
39
40
41
42
43
44
45
46
51
52
53
54
55
58
59
60
61
62
63
64
65

128

4

R227 2.2_5%_ 6

9
8
7

6

5

4

2

VSTBY_FSPI_ R

C236

0.1u/16V _4

114

121

11

VCC

LAD0
LAD1

VSTBY_126VSTBY_250VSTBY_392VSTBY_4

LAD2
LAD3
LPCRST#/GP D2
LPCCLK/GPM4
LFRAME#/G PM5

LPCPD#/GPE6
GA20/GPB5

SERIRQ/GP M6
ECSMI#/GP D4
ECSCI#/GP D3
WRST#
KBRST#/GPB6
PWUREQ#/BBO/GPC7

CRX0/GPC0
CTX0/TMA0/GPB2

IT8987

PS2DAT0/TMB1 /GPF1
PS2CLK0/TMB0/CEC/GPF0
PS2DAT1/RTS0 #/GPF3
PS2CLK1/DTR0#/GPF2
PS2DAT2/GPF5
PS2CLK2/GPF4

DSR0#/GPG6
GINT/CTS0#/GP D5

RXD/SIN0/G PB0
TXD/SOUT0/GPB1

SSCE1#/G PG0
FSCK/GPG7

FMISO/GPG 5
FMOSI/GPG 4
FSCE#/GPG3
SSCE0#/G PG2

KSO0/PD0
KSO1/PD1
KSO2/PD2
KSO3/PD3
KSO4/PD4
KSO5/PD5
KSO6/PD6
KSO7/PD7
KSO8/ACK #
KSO9/BUS Y
KSO10/PE
KSO11/ERR#
KSO12/SLCT
KSO13
KSO14
KSO15
KSI0/STB#
KSI1/AFD#
KSI2/INIT#
KSI3/SLIN#
KSI4
KSI5
KSI6
KSI7

GPJ6
GPJ7

1

+3VPCU_ECPLL

C258

0.1u/16V _4

106

74

127

EGCLK/GP E3

AVCC

VSTBY_6

VSTBY_FSPI

LPC

CTX1/SOUT1/SMDAT3/GPH2/ID2

PS/2

UART

FLASH

KBMX

RING#/PW RFAIL#/CK32KOUT/LPCRST#/GPB7

EGCS#/GP E2

VSTBY(PLL)

KSO16/SMOSI/GPC3
KSO17/SMISO/GPC5

L80HLAT/BAO/GPE0

L80LLAT/G PE7

GPIO

DTR1/SBUSY/GPG1/ID7

CRX1/SIN1/SMCLK3/GPH1/ID1

CLKRUN#/GPH0/ID0

SMCLK2/PECI/GPF6

SMDAT2/PECIRQT#/GPF7

SMCLK0/GPB3
SMDAT0/GPB 4

SM_BUS

SMCLK1/GPC1
SMDAT1/GPC2

PWM0/GPA0
PWM1/GPA1
PWM2/GPA2
PWM3/GPA3
PWM4/GPA4

PWM5/GPA5
PWM6/SSCK/GPA6
PWM7/RIG1#/GPA7

PWM

TACH0A/GPD6

TACH1A/TMA1/G PD7

TACH2/GPJ0

PWRSW /GPE4

WAKE UP

RTS1#/GPE5

A/D D/A

ADC5/DCD1# /GPI5
ADC6/DSR1#/GPI6
ADC7/CTS1#/ GPI7

12

AVSS

75

ECAGND

DAC5/RIG0#/GPJ5

DAC4/DCD0# /GPJ4

DAC3/TACH1B/GPJ3
DAC2/TACH0B/GPJ2

VCORE

12

C269

0.1u/16V _4

CLOCK

VSS_1

VSS_2

VSS_327VSS_4

VSS_5

49

91

104

L5 BLM15AG121SN1D

1 2

L1 BLM15AG121SN1D

U11
IT8987E/BX

84
83

82

EGAD/GPE 1

56
57

19
20

122
99

GPH6/ID6

98

GPH5/ID5

97

GPH4/ID4

96

GPH3/ID3

95
94
93

3

GPH7

117
118
110
111
115
116

24
25
28
29
30
31
32
34

47
48

77

GPJ1

76
120

TMR0/GPC4

124

TMR1/GPC6

107
18

RI1#/GPD0

21

RI2#/GPD1

35
112

66

ADC0/GPI0

67

ADC1/GPI1

68

ADC2/GPI2

69

ADC3/GPI3

70

ADC4/GPI4

71
72
73

81
80
79
78

3

SLP_S0IX#

TP26

TP25

R222 10_5%_ 4

C292 10u/6.3V_4

TP28

+3VPCU_EC

KL_NO_EC [24]

MY16 [15]
MY17 [15]

EXT_LED_1 # [14]
EXT_LED_2 # [14]

THERMTRIP# [6]

USBON# [18 ]
EXT_LED_3 # [14]

EXT_LED_4 # [14]

CLKRUN# [5]

TP24

MBCLK [23]
MBDATA [23]TPDATA[15]
2ND_MBCLK [16]
2ND_MBDATA [16 ]

BATLED0# [16]

TP29

BATLED1# [16]

TP31

MAINON [24 ,25,26,29,30]

PCBEEP_EC [19]

TP33

MODE1 [20]

SYS_HWP G [24]

VNN_ON [27,28]
SUSON [26]

NBSWON# [15,18]

SUSC# [6]

WLANPW R# [2 1]

RSMRST# [12]

ICMNT

TP30

ACIN [23]

TEMP_MBAT# [23]

MODE2 [20]
CLR_CMOS [6]

Prevent ESD/EOS Layout near EC

C8
180p/50V_4

Prevent ESD/EOS Layout near EC

C256
180p/50V_4

R181 33_5%_ 4

C200 180p/50 V_4

D3 VARISTOR

Prevent ESD/EOS Layout near EC

ECAGND

ICMNT [23]
VRON [27]
S5_ON [24,28 ,29]
LANPWR# [22]

C299
180p/50V_4

Output for type-c Apling ridge
reset timming"Low " Active

SM BUS ARRANGEMENT TABLE

SM Bus 1

SM Bus 2

R14 33_5%_4

R272 33_5%_ 4

R338 33_5%_ 4

Battery

Thermal sensor

(For PLL Power)

VccDSW

MBCLK
MBDATA
2ND_MBCLK
2ND_MBDATA

TS_EN_C

GPC6

Pin124 is a board ID for Cloud book (PD) , EC has internal PU for EJ series

NBSWON#
SUSC#

HWPG

C228 0.1u/16V_4

colsed to EC pin within 100 mils

SM Bus 3

SM Bus 4

2

BT_EN [2 1]

TPD_EN [15]

LID# [14,16]

Prevent ESD/EOS Layout near EC

RF_EN [21]

PU/PD (KBC)

GPG2
NBSWON#

MBCLK
MBDATA
GPC6

2ND_MBCLK
2ND_MBDATA

PROCHOT_EC

MAINON
SUSON
RSMRST#
EC_PWROK
CLR_CMOS
S5_ON

R244 10K_5% _4
R259 10K_5% _4

R258 4.7K_5%_4
R257 4.7K_5%_4
R236 *CLA@10K _5%_4

R254 CON@10K_ 5%_4
R334 100K_5 %_4
R237 100K_5 %_4
R238 100K_5 %_4
R345 100K_5 %_4
R320 100K_5 %_4
R328 10K_5% _4

R256 4.7K_5%_4
R255 4.7K_5%_4

3

2

1

R316
100K_5% _4

Battery Disable (FSW)

BI#[23]

1

2

SW3

PJA138K

6

*JTE1CQR

5

+3V_RTC

3

4

R558

2

C441

*0.1u/16V_4

100K_5% _4

SW2

TME-532W-Q-T/R

3

2

3

Q38

1

R578
0_5%_4

Q24
2N7002K

BI_GATE

4

1

5

6

1

+3V_LDO_EC

+3V

+3V_RTC +3VPCU

R494

*0_5%_4

C424 *0.1u/16 V_4

5

Q35A

13

H_PROCHOT# [6,23,27,28]

R495
*0_5%_4

R502
*10K_5%_4

WRST#

61

34

2

Q35B
*SSM6N43FU

Reserve power on switch for test
(MP remove)

SW1

2

3

NBSWON#

A A

*TME-532W -Q-T/R

1

4

5

6

5

SPI ROM(KBC)

3.3K_5%_4

SPI_CS0# _UR_ME
PCH_SPI_CLK_EC
PCH_SPI_SI_EC
PCH_SPI_SO_EC

R473

VSTBY_FSPI

SPI_WP#

R458

3.3K_5%_4
U25

1

CS

6

CLK

5

DI

2

DO

3

WP

W25X1 0CLSNIG

4

HOLD

VSTBY_FSPI

R440

3.3K_5%_4

8

VCC

SPI_HOLD#

7
4

GND

C400

0.1u/16V _4

Power_Auto_Recovery

+3V_LDO_EC

15 mils

680_LDO

3

R199 *S_4

+3V_LDO_EC

20 mils

R207 *S_4

VSTBY_FSPI

2

HWPG(KBC)

HWPG_1 .8V_S5[29]

HWPG_1 .2VSUS[26]

IMVP_PW RGD[27]

HWPG_1 .24V_S5[29]

IMVP_PW RGD_VNN[28]

HWPG_1 .5V[29]

HWPG_1 .05V[25]

HWPG_2 .5V[26]

Size Document Num ber Rev

Size Document Num ber Rev

Size Document Num ber Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

D22 RB500V-40

1

D13 *RB 500V-40

1

D21 *RB 500V-40

1

D16 *RB 500V-40

1

D17 *RB 500V-40

1

D19 *RB 500V-40

1

D14 *RB 500V-40

1

D23 *RB 500V-40

+3V

R499
10K_5%_ 4

2

HWPG

2
2
2
2
2
2
2

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

KBC IT8987E_BX

KBC IT8987E_BX

KBC IT8987E_BX

ZHVA

ZHVA

ZHVA

13 34Thursday, Augu st 09, 2018

13 34Thursday, Augu st 09, 2018

1

13 34Thursday, Augu st 09, 2018

1A

1A

1A

5

+VIN [23,24,25,26,27,28,30]
+5V [17,19,24,30]

EDP Conn.

+3V

1 2

5
4
3

R379
100K_1%_4

R402

100K_1%_4

U15

IN#2
IN#1
EN

G5245AT11U

PCH_BLON_R

1 2

C317

D D

C C

EDP_VDD_EN[4]

PCH_BLON[4]

PCH_BLON_EC[13]

1u/6.3V_4

R393 *S_4
R394 *S_4

+3V [4,5,12,13,16,17,18,19,20,21,22,24,25,26,27,28,29,30]
+1.8V [3,4,17,20,22,29,30]
+1.8V_S5 [3,4,5,6,7,9,12,15,21,22,23,27,29]
+3VPCU [6,13,15,16,19,21,22,23,24,29]

60mil 60mil

1

OUT

2

GND

INT

+3V

10K_5%_4

PQ17A
PJ4N3KDW

R407

5

R403
10K_5%_4

1 2

1 2

61

34

2

PQ17B
PJ4N3KDW

C318

0.01u/50V_4

BL_ON

1 3

HDMI Conn.

HDMI SMBus Isolation

1 2

R157 *2.2K_5%_4

+1.8V

HDMI_DDCCLK_SW[4]

HDMI_DDCDATA_SW[4]

+1.8V

1 2

R160 *2.2K_5%_4

Q6B
SSM6N43FU

2

5

Q6A

SSM6N43FU

61

34

+1.8V

HDMI_SCLK

HDMI_SDATA

+3VPCU

1 2

2 1

4

C5

0.1u/16V_4

R382
*100K_1%_4

D9
1N4148WS

Q29
DDTC144EUA-7-F

2

LID591#,EC intrnal PU

C6
33p/50V_4

LCDVCC

C4
22u/6.3V_6

LID# [13,16]

EC_FPBACK# [13]

3

CCD_PWR TOUCH_SCREEN_PWR

C11

C10

*10p/50V_4

1000p/50V_4

PCH_BRIGHT[4]

C13

*10p/50V_4

+3V

+1.8V

R8
*10K_5%_4

INT_EDP_HPD#[4]

1 2

Q2
PJA138K

321

GND GND

C12
1000p/50V_4

R16 *S_4
R11 *S_4

1 2
1 2

EDP_HPD_R

R13
100K_1%_4

1 2

2

CCD

CCD

TS

TS

R25 *S_8

EDP_AUXP[4]
EDP_AUXN[4]

EDP_TXP1[4]

EDP_TXN1[4]

EDP_TXP0[4]
EDP_TXN0[4]

USBP6_CCD+[3]
USBP6_CCD-[3]

USBP_TOUCH+[3]
USBP_TOUCH-[3]

TS_EN[13]

PR10

100K_1%_4

0.1u/50V_6

DMIC_CLK[19]
DMIC_DAT[19]

12

C326

12

+5V

PR9
100K_1%_4

+3VPCU

EDP_HPD_R

+3V

Modify TPS Power 10/30

+3V

R21 *S_6

EDP_AUXN
EDP_TXP1

EDP_TXP0

USBP_TOUCH+
USBP_TOUCH-

EXT_LED_1#_R
EXT_LED_2#_R
TS_EN
EXT_LED_3#_R
EXT_LED_4#_R

PQ15A

5

2N7002KDW

+VIN

BL_EnableBL_ON

BL_PWM_DIMPCH_BRIGHT

EDP_AUXN_C

R392*100K_1%_4

EDP_AUXP_C

R385*100K_1%_4

EXT_LED_1#[13]
EXT_LED_2#[13] EXT_LED_3#[13]

1

40mil40mil20mil10mil

+VIN_BLIGHT

C325 *4.7u/25V_8
C327 0.1u/50V_6
C328 100p/50V_4

TOUCH_SCREEN_PWR

USB_CCD6_P_R
USB_CCD6_N_R

USB_TS5_P_R
USB_TS5_N_R

EXT_LED_4#[13]

+VIN_BLIGHT

LCDVCC

LED_PWR
CCD_PWR

BL_PWM_DIM
BL_Enable

EDP_HPD_R_C

EDP_AUXP_CEDP_AUXP
EDP_AUXN_C

EDP_TXP1_C
EDP_TXN1_CEDP_TXN1

EDP_TXP0_C
EDP_TXN0_CEDP_TXN0

DFHS40FS036
DFHS40FS150 12/27 SMT request

12

PR8

100K_1%_4

R24 *S_4
R23 *0_5%_4

R18 *S_6
R20 *0_5%_4

C7180p/50V_4

1 2

R12 33_5%_4

C319 0.1u/16V_4
C329 0.1u/16V_4

C321 0.1u/16V_4
C322 0.1u/16V_4

C323 0.1u/16V_4
C324 0.1u/16V_4

R387 *S_4
R388 *S_4

R389 *S_4
R390 *S_4

EXT_LED_1#_R
EXT_LED_2#_R EXT_LED_3#_R

PQ15B

61

34

2

2N7002KDW

12

CN4

PR7
100K_1%_4

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

46

45

PQ14A

5

2N7002KDW

115B40-020000-G4-R

42

44

43

41

PQ14B

34

2

2N7002KDW

14

EXT_LED_4#_R

61

Intel Requesrt Rds_ON <3.5ohm

B B

HDMI-Level shift (HDM)

+3V

2/24 Add C506 for EMI request

C412 1000p/50V_4

1 2

R493 *100K_1%_4
C413

0.1u/16V_4

Close to Q51

2

DGPU_CL_HDMIP

3

1

Close to HDMI connector

15 mils

Q33
2N7002K

1 2

R454 470_1%_4

1 2

R441 470_1%_4

1 2

R439 470_1%_4

1 2

R432 470_1%_4

1 2

R474 470_1%_4

1 2

R462 470_1%_4

1 2

R429 470_1%_4

1 2

R427 470_1%_4

C_TX2_HDMI+
C_TX2_HDMI-

C_TX1_HDMI+
C_TX1_HDMI-

C_TX0_HDMI+
C_TX0_HDMI-

C_TXC_HDMI+
C_TXC_HDMI-

20 mils

+5V

C_TX2_HDMI+
C_TX2_HDMI-

C_TX1_HDMI+
C_TX1_HDMI-

C_TX0_HDMI+
C_TX0_HDMI-

C_TXC_HDMI+
C_TXC_HDMI-

HDMI_SCLK
HDMI_SDATA

HDMI_5V

D12RB500V-40

1

D11RB500V-40

1

C197 0.1u/16V_4
C189 0.1u/16V_4

C183 0.1u/16V_4
C176 0.1u/16V_4

C207 0.1u/16V_4
C203 0.1u/16V_4

C165 0.1u/16V_4
C160 0.1u/16V_4

5V_HSMBCK
5V_HSMBDT

R431 10K_5%_4
R430 10K_5%_4

C149 *10p/50V_4
C144 *10p/50V_4

INT_HDMITX2P[4]
INT_HDMITX2N[4]

INT_HDMITX1P[4]
INT_HDMITX1N[4]

INT_HDMITX0P[4]

HDMI_5V

INT_HDMITX0N[4]
INT_HDMICLK+[4]

INT_HDMICLK-[4]

2
2

Q32

1

VOUT

3

VIN

GND

AP2331SA-7

C393

2

1000p/50V_4

20 mils

HDMI_5V

D10
EGA10402V05AH_0.2p

EMI (EMC)

C_TX0_HDMI+

A A

5

C_TX1_HDMI+

C_TX2_HDMI+

C_TXC_HDMI+

12

R188 *100_1%_4

R173 *100_1%_4

R182 *100_1%_4

R165 *100_1%_4

12

12

12

C_TXC_HDMI-

C_TX0_HDMI-

C_TX1_HDMI-

C_TX2_HDMI-

C_TX0_HDMI+

C_TX2_HDMI+ C_TX2_HDMI+
C_TX2_HDMI- C_TX2_HDMI-

C_TX1_HDMI+ C_TX1_HDMI+
C_TX1_HDMI-

C_TXC_HDMI+

For ESD Layout note:Place close to HDMI Conn

4

U9

NC46IN4

7

NC3

8

GND2

9

NC2

10

NC1

*AZ1045-04F.R7G

U8

NC46IN4

7

NC3

8

GND2

9

NC2

10

NC1

*AZ1045-04F.R7G

GND1

GND1

C_TX0_HDMI+

5

C_TX0_HDMI-C_TX0_HDMI-

4

IN3

3
2

IN2

1

IN1

HDMI_HPD_C[4]

5

C_TX1_HDMI-

4

IN3

3

C_TXC_HDMI+

2

IN2

C_TXC_HDMI-C_TXC_HDMI-

1

IN1

3

VC1

TVM0G5R5M220R_22p

2

2021

1

D2+

2
3

D2-

4
5

D1_shield

6
7

D0+

8
9

D0-

10
11

CLK_shield

12
13

CEC

14
15

DDC CLK

16
17

GND

18
19

HP DET

Change footprint to hdmi-80103-1121-19p-ldv-smt
Change PN to 2nd DFHS19FR072 due to DFHS19FR079 SDA test fail

C392
220p/50V_4

CN8
59056-01902-001

D2_shield

D1+

D1-

D0_shield

CLK+

CLK-

NC

DDC DATA

+5V

23 22

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Thursday, August 09, 2018

Date: Sheet of

Thursday, August 09, 2018

Date: Sheet of

Thursday, August 09, 2018

PROJECT :

eDP/HDMI/Camera

eDP/HDMI/Camera

eDP/HDMI/Camera

ZHVA

ZHVA

ZHVA

1

1A

1A

1A

3414

3414

3414

5

TOUCHPAD BOARD CONN (TPD
I2C/PS2 co-lay)

+5V [14,17,19,24,30]
+3VPCU [6,13,14,16,19,21,22,23,24,29]
+1.8V [3,4,14,17,20,22,29,30]
+3V_S5 [3,6,7,12,13,22,24,26,29]
+1.8V_S5 [3,4,5,6,7,9,12,21,22,23,27,29]

D D

PTP_PWR_EN#[13]

+1.8V_S5

+3V_S5

50mil

R329 *0_5%_4

+TPVDD_1

4

R333 *S_6

3

1

Q21

*AO3413

2

C290 *1000p/50V_4

1 2

C280

0.1u/16V_4

Un-stuff R324 10/30

C450

0.22u/25V_6

+TPVDD_1

C453

0.1u/16V_4

TPCLK[13]

TPDATA[13]

3

R587

10K_5%_4

1 2

*0.1u/16V_4

R586
10K_5%_4

1 2

C452

C451

*0.1u/16V_4

50mil

2

+TPVDD_1

1

15

C455

0.1u/16V_4

+TPVDD_1

I2C_TP_SDA_R

TP_INT#_R

TPD_EN[13]

TPD_EN

I2C_TP_SCL_R

910

1
2
3
4
5
6
7
8

CN13
196047-08021-3_FFC/FPC

R350

2

Q26B

I2C4_SDA[3]

Q26A

I2C4_SCL[3]

C C

1/13 Add

TPD_INT#[13]

PJ4N3KDW

5

PJ4N3KDW

+3V_S5

R331
*10K_5%_4

1 2

61

34

2.2K_5%_4

+TPVDD_1

Q22

321

*2N7002K

R330 0_5%_4

R351

2.2K_5%_4

1 2

1 2

I2C_TP_SDA_R

+1.8V_S5

I2C_TP_SCL_R

TP_INT#_R

pull high at SOC side

PCH_TPD_INT#[5]

1 2

3

1

R349
*10K_5%_4

Q25
2N7002K

2

+TPVDD_1

1 2

3

1

R340
10K_5%_4

Q23
2N7002K

2

R336
10K_5%_4

1 2

TP_INT#_R

check the ESD

reserve for auto wake up from S3 issue.

3/19 Modify & Add it

TP_INT#_R

C297
*10p/50V_4

use for Acer request to change design.

KEYBOARD (KBC)

+3VPCU

Swap RP1 nets 11/19

RP1

B B

A A

MX2
MX1
MX0

8
7 4

10

9

MX3

10K_6_10P8R

1

MX4

2

MX5

3

MX6
MX7

56

NBSWON#[13,18]

NBSWON#

C439

*180p/50V_4

MX0[13]
MX1[13]
MX2[13]
MX3[13]
MX4[13]
MX5[13]
MX6[13]
MX7[13]
MY17[13]
MY16[13]
MY15[13]
MY14[13]
MY13[13]
MY12[13]
MY11[13]
MY10[13]
MY9[13]
MY8[13]
MY7[13]
MY6[13]
MY5[13]
MY4[13]
MY3[13]
MY2[13]
MY1[13]
MY0[13]

R559

12

*33_5%_4

12

D24

MX0
MX1
MX2
MX3
MX4
MX5
MX6
MX7

MY17
MY16
MY15
MY14
MY13
MY12
MY11
MY10
MY9
MY8
MY7
MY6
MY5
MY4
MY3
MY2
MY1
MY0

CN11

29

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

*AZ5725-01F.R7G

1 2

R570
*0_5%_4

30

196153-28021-35

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet

KB/TP

KB/TP

KB/TP

PROJECT :

ZHVA

ZHVA

ZHVA

1A

1A

1A

of

15 34Thursday, August 09, 2018

15 34Thursday, August 09, 2018

15 34Thursday, August 09, 2018

1

5

4

3

2

1

CPU Thermal sensor(THS) / MB Local
TEMP (THM)

+3V

U24

ALERT#

G753T11U

C370
CB@0.01u/50V_4

3

ALERT#

TP47

D D

4

+Vs

2ND_MBDATA[13]
2ND_MBCLK[13]

C C

2ND_MBDATA
2ND_MBCLK

5

SMBDATA

1

SMBCLK

GND

2

Lid

+3VPCU

+3VPCU

LED(UIF)

+3VPCU

LED1

Blue

1

12-12/S2BHC-A30/2C

2

Blu

1

3

Ora R347 680_1%_4

Amber

Del option Power SW

GMR(option)

Del option GMR

Adjust for ME

1 2

R344 470_1%_4

FULL LED

BATLED0# [13]
BATLED1# [13]

CHG LED

16

B B

A A

C49

1u/6.3V_4

R33

2.2_5%_6

1 2

C50

0.1u/25V_4

5

LID#_MR1

1

2

VCC

YB8251ST23

S

N

OUTPUT

GND

MR1

3

R381 *S_4

*LCP0G050M0R2R_0.2p

D8

4

LID#

R386
*47K_5%_4

1 2

180p/50V_4

C320

LID# [13,14]

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Thursday, August 09, 2018

Date: Sheet of

Thursday, August 09, 2018

Date: Sheet of

3

2

Thursday, August 09, 2018

PROJECT :

Thm/Lid/LED

Thm/Lid/LED

Thm/Lid/LED

ZHVA

ZHVA

ZHVA

1

1A

1A

1A

3416

3416

3416

5

4

3

2

1

SATA HDD Conn

+5V [14,19,24,30]
+1.8V [3,4,14,20,22,29,30]

1 2

R147*S_8

+3V

CN7*M2_SSD@NASB0-S6701-TSH4

7677

1
34
56
78
910

11

2120
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75

C124
M2_SSD@0.01u/50V_4

SATA_RXP1_NGFF
SATA_RXN1_NGFF

SATA_TXN1_NGFF
SATA_TXP1_NGFF

SATA_TXP1_NGFF
SATA_TXN1_NGFF
SATA_RXN1_NGFF
SATA_RXP1_NGFF

20mil

+1.8V

R229 *S_4

20mil

+3V

R279 *S_4

C407 M2_SSD@0.01u/50V_4
C408 M2_SSD@0.01u/50V_4
C406 M2_SSD@0.01u/50V_4
C405 M2_SSD@0.01u/50V_4

C224
EM@1u/6.3V_4

C262
EM@0.1u/16V_4

+1.8V_EMMC

C225
EM@0.1u/16V_4

+3V_EMMC

C261
EM@1u/6.3V_4

SATA_TXP1 [3]
SATA_TXN1 [3]
SATA_RXN1 [3]
SATA_RXP1 [3]

C226
EM@1u/6.3V_4

C260
EM@1u/6.3V_4

Hynix EMMC 1U, others 0.1u,
For HS400

C120

M2_SSD@0.1u/25V_4

D D

SATA_DEVSLP1[5]

C C

SATA_DEVSLP1

2

22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74

C187

M2_SSD@10u/6.3V_6

7879

SATA HDD

CN9
HD@CVS520EM1RB-NH

22

24

20
19
18
17
16
15
14
13
12
11

B B

10

9
8
7
6
5
4
3
2
1

23

25 26

NGFF_SATA_DET#
SATA_DEVSLP0

SATA_RXP0_CN
SATA_RXN0_CN

SATA_TXN0_CN
SATA_TXP0_CN

21

C403
HD@100u/6.3V_12

NGFF_SATA_DET# [5]
SATA_DEVSLP0 [5]

C436 HD@0.01u/50V_4
C435 HD@0.01u/50V_4

C434 HD@0.01u/50V_4
C433 HD@0.01u/50V_4

R536
w/o GS@0_5%_4

1 2

C218

HD@10u/6.3V_6

HDD_INTA_C

+5V_HDD

C227

HD@0.1u/16V_4

SATA_RXP0
SATA_RXN0

SATA_TXN0
SATA_TXP0

R596 *0_5%_4

100mil

1 2

C235

HD@0.1u/16V_4

SMT suggest 2nd DFHS20FS095

12

HDD_INTA

R195*S_8

SATA_RXP0 [3]
SATA_RXN0 [3]

SATA_TXN0 [3]
SATA_TXP0 [3]

HDD_INTA [20]

+5V

+3V [4,5,12,13,14,16,18,19,20,21,22,24,25,26,27,28,29,30]

20mil

K6

VDDI_DSC

AA5

W4

Y4

AA3
T10

U9
M6
N5

K2

R10

U8
M7

P5

L4
A4
A6
A9

A11

B2

B13

D1

D14

H1
H2
H6
H7
H8

H9
H10
H11
H12
H13
H14

J1
J7
J8

J9
J10
J11
J12
J13
J14

K1

K3

K5

K7

K8

K9

K10
K11
K12
K13
K14

L1

L2

L3

L12
L13
L14

M1
M2
M3
M5
M8
M9

M10
M12
M13
M14

N1
N2
N3

N10
N12
N13
N14

P1

P2

P3

P10
P12
P13
P14

C243
EM@0.1u/16V_4

20mil

C257
EM@0.1u/16V_4

C219

EM@0.1u/16V_4

1 2

R265 0_5%_4

C242
EM@0.1u/16V_4

C259
EM@0.1u/16V_4

U27

VCCQ_1
VCCQ_2
VCCQ_3
VCCQ_4
VCCQ_5

VCC_1
VCC_2
VCC_3
VCC_4

VDDI

VSS_1
VSS_2
VSS_3
VSS_4

A1_Index
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42
NC_43
NC_44
NC_45
NC_46
NC_47
NC_48
NC_49
NC_50
NC_51
NC_52
NC_53
NC_54
NC_55
NC_56
NC_57
NC_58
NC_59
NC_60
NC_61
NC_62
NC_63
NC_64
NC_65
NC_66
NC_67
NC_68
NC_69

EM@THGBMHT0C8LBAIG

eMMC

Power Signals

GND

NC

RST_n

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5

NC_70
NC_71
NC_72
NC_73
NC_74
NC_75
NC_76
NC_77
NC_78
NC_79
NC_80
NC_81
NC_82
NC_83
NC_84
NC_85
NC_86

NC_87
NC_88
NC_89
NC_90
NC_91
NC_92
NC_93
NC_94
NC_95
NC_96
NC_97
NC_98

NC_99
NC_100
NC_101
NC_102
NC_103
NC_104
NC_105
NC_106
NC_107
NC_108
NC_109
NC_110
NC_111
NC_112
NC_113
NC_114
NC_115
NC_116
NC_117
NC_118
NC_119
NC_120
NC_121
NC_122
NC_123
NC_124
NC_125
NC_126
NC_127
NC_128
NC_129
NC_130
NC_131
NC_132
NC_133
NC_134
NC_135
NC_136
NC_137
NC_138

EM@10K_5%_4

CLK

CMD

D0
D1
D2
D3
D4
D5
D6
D7

W6
W5

H3
H4
H5
J2
J3
J4
J5
J6

U5
AA6

Y5
K4
AA4
Y2

R1
R2
R3
R5
R12
R13
R14
T1
T2
T3
T5
T12
T13
T14
U1
U2
U3

U6
U7
U10
U12
U13
U14
V1
V2
V3
V12
V13
V14
W1
W2
W3
W7
W8
W9
W10
W11
W12
W13
W14
Y1
Y3
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
AA1
AA2
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AE1
AE14
AG2
AG13
AH4
AH6
AH9
AH11

+1.8V +1.8V

12

R562

12

R209 *EM@0_5%_4

EMMC_RCLK_R

R228 0_5%_4

EM@0_5%_4

12

R210
EM@10K_5%_4

R564 EM@10_1%_4
R563 EM@10_1%_4

R509 EM@10_1%_4
R533 EM@10_1%_4
R560 EM@10_1%_4
R501 EM@10_1%_4
R507 EM@10_1%_4
R526 EM@10_1%_4
R540 EM@10_1%_4
R561 EM@10_1%_4

12

D2

2

1

EM@RB500V-40

1 2

R252

12

R264
EM@100K_5%_4

17

EMMC_CLK [5]
EMMC_CMD [5]

EMMC_DATA_0 [5]
EMMC_DATA_1 [5]
EMMC_DATA_2 [5]
EMMC_DATA_3 [5]
EMMC_DATA_4 [5]
EMMC_DATA_5 [5]
EMMC_DATA_6 [5]
EMMC_DATA_7 [5]

EMMC_RST [5]

PLTRST# [6,13,21,22]

EMMC_RCLK [5]

Follow Apollo CRB

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number R

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

PROJECT :

SATA HDD/eMMC

SATA HDD/eMMC

SATA HDD/eMMC

ZHVA

ZHVA

ZHVA

17 34Thursday, August 09, 2018

17 34Thursday, August 09, 2018

1

17 34Thursday, August 09, 2018

ev

1A

1A

1A

5

USB 3.0 Connector

D D

+5V_S5

Enable: Low Active /2A

C420

4.7u/10V_6

USBON#[13]

USBON#

AP2822HKETR-G1

5

IN

4

EN

U26

VOUT

GND

FLAG

5VUSB_0

1
2
3

USB_OC1#

4

USB30_RX0-[3]
USB30_RX0+[3]

USBP0+[3]
USBP0-[3]

USB30_TX0-[3]
USB30_TX0+[3]

C239 0.1u/25V_4
C238 0.1u/25V_4

USB30_RX0­USB30_RX0+

USB30_TX0-_C
USB30_TX0+_C

3

R283 0_5%_4

R276 0_5%_4
R511 0_5%_4

R508 0_5%_4
R271 0_5%_4

R263 0_5%_4

2

2/26 add

1110

Shield

USB30_RX1-_R

GND
USB30_RX1+_R
USBP0+_R

GND
USBP0-_R
USB30_TX1-_R
5VUSB_0
USB30_TX1+_R

5
4
6
3
7
2
8
1
9

StdA_SSRX-

GND

StdA_SSRX+

D+

GND_Drain

D-

StdA_SSTX-

VBUS

StdA_SSTX+

Shield

Shield Shield

13 12

7/16 change to 0 ohm for ESD data pin issue.

CN10
53065-00902-001

1

18

Close USB3.0

C C

5VUSB_0

AZ5725-01F.R7G

D15

12

C415

470p/50V_4

C414

0.1u/25V_4

C409
100u/6.3V_12

USBP0+_R
USBP0-_R

2

3

1

D20
PESD5V0X2UM

USB30_RX1-_R
USB30_RX1+_R USB30_RX1+_R

USB30_TX1-_R
USB30_TX1+_R

U10

1

Line-1

2

Line-2

3

GND#1

4

Line-3
Line-45NC#1

AZ1043-04F.R7G

NC#4
NC#3

NC#2

USB30_RX1-_R

10
9

USB30_TX1-_R

7

USB30_TX1+_R

6

D/B PortUSB 2.0 X 1

<Layout note>

B B

+5V_S5

5VUSB_1

Enable: Low Active /2A

2

USB_CAR7-[3]

USB_CAR7+[3]

1

3

100u/6.3V_12

NBSWON#[13,15]

C361

4.7u/10V_6

USBON#

AP2822HKETR-G1

5

IN

4

EN

U17

VOUT

GND

FLAG

1
2
3

5VUSB_1

USB_OC1# [3]

Close to CN6

7/16 rreserve 0 ohm for ESD data pin issue.

USBP2+[3]
USBP2-[3]

A A

5

+3V_S5 [3,6,7,12,13,15,22,24,26,29]
+3V [4,5,12,13,14,16,17,19,20,21,22,24,25,26,27,28,29,30]
+5V_S5 [6,24,26,27,28]

4

R597 0_5%_4
R598 0_5%_4

USB2.0_CONN2+
USB2.0_CONN2-

3

Close to CONN

C345

D28
*PESD5V0X2UM

USB2.0_CONN2+
USB2.0_CONN2-

C346

0.1u/16V_4

NBSWON#

C381

+3V

CN6

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

C368

*100u/6.3V_12

0.1u/16V_4

2

USB 2.0

1718

51619-01601-V05

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Thursday, August 09, 2018

Date: Sheet of

Thursday, August 09, 2018

Date: Sheet of

Thursday, August 09, 2018

PROJECT :

USB CONN

USB CONN

USB CONN

ZHVA

ZHVA

ZHVA

1

1A

1A

1A

3418

3418

3418

5

Codec(ADO)

C289

10u/6.3V_4

ear Codec

n

Low is power down
amplifier output

C296

0.1u/16V_4

+3V

placed close to codec

ADOGND

C459 10u/6.3V_4

+5V_PVDD

L_SPK+
L_SPK-

C456

0.1u/16V_4

R_SPK­R_SPK+

PD#

T4

R323 *S_6

Place next to pin 1

0.1u/16V_4

C282 10p/50V_4

1 2

R327 22_1%_4

C284

10p/50V_4

C306
1u/25V_4

40mil40mil

C449

+AZA_VDD

37
38
39
40
41
42
43
44
45
46
47
48

49

C46110u/6.3V_4

36

CPVDD
CBP
AVSS2
LDO2-CAP
AVDD2
PVDD1
SPK-L+
SPK-L­SPK-R­SPK-R+
PVDD2
PDB
SPDIF-OUT

DGND

DVDD1GPIO0/DMIC-DATA2GPIO1/DMIC-CLK3DC DET4SDATA-OUT5BCLK6LDO3-CAP7SDATA-IN8DVDD-IO9SYNC10RESETB11PCBEEP

+AZA_VDD

C286
10u/6.3V_4

DMIC_DAT

DMIC_CLK_R

D D

Place next to pin 40

+1.5VA

C303

C305

0.1u/16V_4

10u/6.3V_4

ADOGND

Analog

Digital

+5V

L8

1 2

PBY160808T-600Y-N

40mil

C C

Tied at one point only under
the codec or near the codec

R589 *S_4
R326 *S_4
R593 *S_4
R581 *S_4
R590 *S_4
R588 *S_4

C442 *1000p/50V_4
C460 *1000p/50V_4

B B

ADOGND

Cap need near AVDD1
and AVDD2
power source input

C291

10u/6.3V_4

near Codec

DMIC_DAT[14]

DMIC_CLK[14]

4

C3071u/25V_4

30

31

35

34

CBN

CPVEE

(Include Thermal pad)

QFN48 (6x6)

T3

29

33

32

HP-OUT-L

HP-OUT-R

MIC2-VREFO

LINE1-VREFO-L

LINE1-VREFO-R

SPDIFO/FRO NT JD/GPIO3

Close

C275

10u/6.3V_4

ACZ_SDIN

BITCLK

C285 *22p/50V_4

HP-R2
HP-L2
LINE1-VREFO-L
LINE1-VREFO-R
MIC2-VREFO

20mil

CODEC_VREF

INT_AMIC-VREFO

27

28

25

26

VREF

AVSS1

AVDD1

LDO1-CAP

LINE2-L

LINE2-R

LINE1-L

LINE1-R

VD33 STB

MIC-CAP

MIC2-R/SLEEVE

MIC2-L/RING2

MONO-OUT

MIC2/LIN2 JD

HP/LINE1 JD

12

PCBEEP

AZ_CODEC_RST#

1 2

R321 33_5%_4

1 2

R322 *short_0402

C311 2.2u/6.3V_4
C310 10u/6.3V_4

R352

U13
ALC255-CG

24
23
22
21
20
19
18
17
16
15
14
13

1.6Vrms

C283

0.1u/16V_4

+1.5V [29]
+5V [14,17,24,30]
+3V [4,5,12,13,14,16,17,18,20,21,22,24,25,26,27,28,29,30]
+3VPCU [6,13,14,15,16,21,22,23,24,29]

ADOGND
ADOGND

12

100K_1%_4

C308

0.1u/16V_4

+5VA

Place next to pin 26

ADOGND

LINE1-L
LINE1-R

SLEEVE
RING2

SENSEA

1 2

C30410u/6.3V_4

trace width of SLEEVE & RING2
a

re required at least 40mil and

its length should be asshort as possible

12

R580 100K_1%_4

1 2

R579 200K_5%_4

Placement near Audio Codec

2/24 Modify to 10K

BEEP_1

C443
100p/50V_4

1 2

R577

4.7K_5%_4

1 2

AZ_CODEC_RST# [5]
AZ_CODEC_SYNC [5]

DVDD_IO

AZ_CODEC_SDIN0 [5,9]

AZ_CODEC_BITCLK [5]

AZ_CODEC_SDOUT [5]

3

for discharge

C309
10u/6.3V_4

R348*short_0402

+3VPCU

ADOGND

+3V

HP_JD#

Analog

Digital

D25

1

3

R57610K_1%_4

2

BAT54CW

APL only support 1.5V on ISH

1 2

10mil

1 2

R318 *short_0402

C281

C278

0.1u/16V_4

10u/6.3V_4

Place next to pin 9

SPKR [5]
PCBEEP_EC [13]

+3V +1.5V

R315* 0_5%_4

2

Grounding circuit(ADO)

If IC pin20 connect to always power,
G

rounding circuit can be remove

Mute(ADO)

+AZA_VDD

12

Stuff R384 for AMP_MUTE#

R325
1K_5%_4

PD#

12

R324

*10K_5%_4

D5 *RB500V-40

D4 RB500V-4021

1

PCH_AZ_CODEC_RST_R#

AMP_MUTE# [13]

2

Power (ADO)

HEADPHONE/MIC/LINE combo (ADO)

MIC2-VREFO

L19/L21 change to 0 ohm 11/4

RING2
HP-L2

HP-R2
SLEEVE

LINE1-L
LINE1-VREFO-L
LINE1-VREFO-R
LINE1-R

1 2

R337 2.2K_5%_4

1 2

R594 2.2K_5%_4

1 2

L12

*short_0402

1 2

L11

*short_0402

C458 4.7u/6.3V_6

12

R592 4.7K_5%_4

12

R585 4.7K_5%_4

C457 4.7u/6.3V_6

SLEEVE
RING2

FB1/FB2(SLEEVE/RING2) should choose DC
resistance (Rdc) < 30m-ohm
to get the best audio performance for HP crosstalk

HP-L3

HP-R3

12

R591 62_1%_4

12

R583 62_1%_4

C300

100p/50V_4

C462

C463

C447

100p/50V_4

100p/50V_4

L7

100p/50V_4

Layout note:

1.SLEEVE/Ring2 trace width at least 40mils

2.HP/Line trace width at least 10mils

3.At least 10mils are required between L/R.

L13

1 2

BLM15AG121SN1D

1 2

BLM15AG121SN1D

12

12

12

D6

D26

D27

AZ5725-01F.R7G

AZ5725-01F.R7G

AZ5725-01F.R7G

ADOGND

ADOGND

1

For A-MIC LDO

Combo Jack

CN12

RING2_R
HP-L4

HP_JD#
HP-R4

SLEEVE_R

G/M

3
1

L

5
6

R

2

M/G

4

2SJ3080-088111F

ADOGNDADOGND

19

7

ADOGND

Codec PWR 5V(ADO)

+5V

20mil

1 2

DIGITAL

A A

5

L9

20mil

HCB2012KF-220T60

ANALOG

+5VA

Codec PWR 1.5V(ADO)

20mil 20mil

+1.5V

C274
1u/6.3V_4

ANALOG DIGITAL

L4 *S_6

Internal Speaker

R_SPK+

R575 *short_0805

R_SPK-

R574 *short_0805

L_SPK- L_SPK-_CN

R573 *short_0805

L_SPK+

R572 *short_0805

4

40mil for each signal

12
12
12
12

C448

C446

1000p/50V_4

1000p/50V_4

Place these EMI components next to codec 2016/01/19
SMT requestchange to CH21006JB10

+1.5VA

R_SPK+_CN
R_SPK-_CN

L_SPK+_CN

C445
1000p/50V_4

C444
1000p/50V_4

3

CN14

56

1
2
3
4

3806K-F04M-03L

ADOGND

change on Ramp stage

A-Mic

Level shift

+3V

12

R312
10K_5%_4

PCH_AZ_CODEC_RST_R#

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Codec ALC225

Codec ALC225

Codec ALC225

Thursday, August 09, 2018

Thursday, August 09, 2018

Thursday, August 09, 2018

12

R304
10K_5%_4

Q19

3

PJA138K

2

1

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

1

3

1

Q18
PJA138K

AZ_CODEC_RST#

2

ZHVA

ZHVA

ZHVA

3419

3419

3419

1A

1A

1A

5

4

3

2

1

G-sensor

+SENSOR_POWER

R308 GS@0_5%_6

D D

C C

+3V

R307 *0_5%_6

ACCEL_INTA INT_HUB_TO_CPU

Sensor hub

I2C5_SDA[3]

B B

A A

I2C5_SCL[3]

SENSOR_HUB_INT1#[5]

MODE1_HUB
MODE2_HUB

ISH_MODE1[5]
ISH_MODE2[5]

clamshell/tent/stand/tablet

5

+SENSOR_POWER

R319 *S_6

GS@0.1u/16V_4

C273
*0.1u/25V_4

Reserve

R332

*GS@0_5%_4

+SENSOR_POWER

Q27A

5

34

*GS@ME2N7002DKW-G

R366 *S_4

+SENSOR_POWER

Q27B

2

61

*GS@ME2N7002DKW-G

R371 *S_4

+SENSOR_POWER

Q28

2

3

1

*GS@2N7002K

R368 *S_4

R359 *S_4

R364 *S_4

R354 *GS@0_5%_4
R362 *GS@0_5%_4

C276

SDA_SENSOR_HUB

SCL_SENSOR_HUB

INT_HUB_TO_CPU

+G_SEN_PW

C287
GS@10u/6.3V_6

Address: I2C mode,SDO pin

+SENSOR_POWER

12

R365
*4.7K_1%_4

+SENSOR_POWER

12

R376
*4.7K_1%_4

+SENSOR_POWER

12

R370
*4.7K_1%_4

7

VDD

3

VDDIO

11

PS

8

GNDIO

9

GND

GS@BMA253

PD:0X18
PU:0X19

+SENSOR_POWER

+1.8V

+SENSOR_POWER

12

EC

MODE1 [13]
MODE2 [13]

4

+SENSOR_POWER+1.8V

U12

SDO

SDX

SCX
INT1
INT2

NC

CSB

4

10

C3 GS@0.1u/16V_4
C2 GS@0.1u/16V_4

C316 GS@0.1u/16V_4

R341 *GS@0_5%_4

1

SDA_GSENSOR

2

SCL_GSENSOR

12

ACCEL_INTA

5

HDD_INTA

6

SDA_GSENSOR
SCL_GSENSOR

close to Pin C1

1

R360
GS@100K_1%_4

C313
GS@1u/6.3V_4

R358 *GS@100K_1%_4
R356 *GS@100K_1%_4
R363 *GS@100K_1%_4
R367 *GS@100K_1%_4
R369 *GS@100K_1%_4

R353 *GS@100K_1%_4
R361 *GS@100K_1%_4

D7
GS@RB500V-40

2

WRST#_8350

12
12
12
12
12

12
12

12

R342 0_5%_4
R343 *GS@0_5%_4
R335 *GS@0_5%_4

C301 *GS@33p/50V_4

C293 *GS@33p/50V_4

ACCEL_INTA_R
ACCEL_INTA_SUB_R
I2CINT13
INT_HUB_TO_CPU
INT6_SENSOR_HUB

MODE1
MODE2

3

12
12

HDD_INTA [17]

C312 GS@0.1u/16V_4

+SENSOR_POWER

TP43
TP42

TP34

ACCEL_INTA_R
ACCEL_INTA_SUB_R

+SENSOR_POWER

Reserve

I2C6_SDA [3]

U14

+1.8V

GS@IT8353VG-128/BX

C1

VCCA

C2

VCCIO

B3

VCCK

E2

SIN0/JTMSC/ADC2/GPB0

E3

SOUT0/JTCKC/ADC3/GPB1

A4

I2CINT11/FMOSI/SSCE2#/PWM4/I2SWS

A5

I2CINT10/FMISO//SSCE1#/PWM5/TACH0

B4

I2CINT12/FSCE#/PWM3/I2SDAT/MICDAT

I2CINT13
WRST#_8350

B5

I2CINT13/FSCK/PWM7/I2SBCLK/MICCLK

A2

WRST#

1 2

R374 GS@4.7K_1%_4

1 2

R373 GS@4.7K_1%_4

G-sensor sub

ACCEL_INTA_SUB[12]I2C6_SCL [3]

I2CDAT3/PWM2/TACH1/GPB5

I2CINT4/SMISO/GPC5D2I2CINT5/SMOSI/GPC3D3I2CINT6/SSCE0#/GPD2D4I2CINT7/SSCK/GPA6

SDA_GSENSOR_R
SCL_GSENSOR_R SCL_GSENSOR

ACCEL_INTA_R

ACCEL_INTA_SUB_R ACCEL_INTA_SUB

R375 *S_4
R372 *S_4
R357 *S_4
R355 *S_4

+SENSOR_POWER

TP40

I2CDAT0/GPB3
I2CDAT1/GPB4

I2CDAT2/SOUT1/GPC7

I2CDAT5/RTS1#/GPA5

I2CCLK0/GPB3
I2CCLK1/GPB4

I2CCLK2/SIN1/GPC6

I2CCLK3/PWM1/GPB2

I2CCLK5/CTS1#/GPA4

D5

TP41

INT6_SENSOR_HUB
INT_HUB_TO_CPU

ACCEL_INTA_SUB

SDA_GSENSOR
SCL_GSENSOR

GND

TP39

SDA_GSENSOR

ACCEL_INTA

C5
A3
A1
E4
D1

C4
B2
B1
E5
E1

C3

Reserve

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Thursday, August 09, 2018

Date: Sheet of

Thursday, August 09, 2018

Date: Sheet of

Thursday, August 09, 2018

2

Date: Sheet

PROJECT :

SENSOR HUB

SENSOR HUB

SENSOR HUB

20

CN3

78

GS@50208-00601-V02

1
2
3
4
5
6

DFHS06FR039

SDA_SENSOR_HUB
MODE1_HUB

TP35

SDA_GSENSOR_R

TP37

SCL_SENSOR_HUB
MODE2_HUB

TP36

SCL_GSENSOR_R

TP38

ZHVA

ZHVA

ZHVA

1

1A

1A

1A

of

3420

3420

3420

5

1 2

R28 NAC@0_5%_8

WLAN

WLANPWR#[13]

D D

WAKE_SRC_WLAN[12]
IOAC_WLAN_WAKE#[13]

PCIE_CLKREQ_WLAN#[3]

C C

+3V

+3VPCU

*AC@1u/6.3V_4

R49

12

*AC@10K_5%_4

C51

R47
R48

*AC@0_5%_4

1 2
1 2

*0_5%_4

+1.8V_S5

+1.8V[3,4,14,17,20,22,29,30]
+3V[4,5,12,13,14,16,17,18,19,20,22,24,25,26,27,28,29,30]
+3V_S5[3,6,7,12,13,15,22,24,26,29]

12

R32
*100K_1%_4

1

VCCA
A13B1

2

GND

Q3

1

Q4

321

*AC@PJA138K

U16

VCCB

G2129BTL1U

*AC@AO3413

2

+WL_VDD

6
4
5

EO

3

1 2

4

C54
10u/6.3V_6

R380
*AC@4.7K_1%_4

PCIE_WAKE#_R

+WL_VDD

12

R378
*10K_5%_4

PCIE_CLKREQ3_WLAN#_R

1 2

R383 10K_5%_4

+WL_VDD

C22

0.1u/16V_4

CLK_PCI_LPC[5]

LPC_LFRAME#[5,13]

+1.8V_S5

C315

0.1u/25V_4

+WL_VDD

USBP4+[3]

C314

0.1u/25V_4

PCIE_TXP3_WLAN[3]
PCIE_TXN3_WLAN[3]

PCIE_RXP3_WLAN[3]
PCIE_RXN3_WLAN[3]

CLK_PCIE_WLANP[3]
CLK_PCIE_WLANN[3]

1 2

R384 *DBG@0_5%_4

1 2

R391 *DBG@0_5%_4

3

USBP4-[3]

PCIE_CLKREQ3_WLAN#_R
PCIE_WAKE#_R

CLK_24M_DEBUG_C

LFRAME#_C

2

76

CN2

51747-07502-005

76

1

1

3

3

5

5

7

7

9

9

11

11

13

13

15

15

17

17

19

19

21

21

23

23

33

33

35

35

37

37

39

39

41

41

43

43

45

45

47

47

49

49

51

51

53

53

55

55

57

57

59

59

61

61

63

63

65

65

67

67

69

69

71

71

73

73

75

75

77

77

+WL_VDD

78

78

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

54

56

56

58

58

60

60

62

62

64

64

66

66

68

68

70

70

72

72

74

74

79

79

Modify footprint for SMT request

WIFI_SUSCLK

PLTRST#_2

LAD0_C
LAD1_C
LAD2_C
LAD3_C

+WL_VDD

T1

1 2

R9 *AC@0_5%_4

1 2

R10 NAC@0_5%_4

1 2

R19 *S_4

1 2
1 2
1 2

*S_4
*S_4

R22
R26
R27 *S_4

1

BT_EN [13]

RF_EN [13]

LPC_LAD0 [5,13]
LPC_LAD1 [5,13]
LPC_LAD2 [5,13]
LPC_LAD3 [5,13]

21

IOAC_RST# [13,22]
PLTRST# [6,13,17,22]

TPM (TPM)

C105

PCH_SPI_SO

PIRQ#_C

TPM_VDD

C110

TPM@0.1u/16V_4

TPM_VDD

22

8

30

PMU_SLP_S0#[6]
PIRQ#[5]
GPIO_67[3]

PCH_SPI_CLK[5]
PCH_SPI_SI[5]
PCH_SPI_SO[5]

GPIO_81[3,9]

PMU_SLP_S0#
PIRQ#

GPIO_67
PCH_SPI_CLK

PCH_SPI_SI
PCH_SPI_SO
GPIO_81 TPM_SCS#TPM_SCS#

3

R124 *0_5%_4
R98 *0_5%_4
R595 0_5%_4

R104 33_5%_4
R107 33_5%_4
R121 33_5%_4
R109 0_5%_4

T2

PIRQ#_C

PP

PLTRST#

29
18

19
21
24
20

6

13

4

17

SCL/GPIO1
SDA/GPIO0
PIRQ/GPIO2

SCLK
MOSI/GPIO7
MISO
SCS/GPIO5

GPIO3
GPIO4
PP/GPIO6

PLTRST

VHIO#2

VHIO#1

U5

TPM@NPCT750AAAYX

33

R112

1 2

TPM@0_5%_4

1

VSB

NC#1
NC#2
NC#3
NC#4
NC#5
NC#6
NC#7
NC#8

NC#9
NC#11
NC#12
NC#13
NC#14
NC#15
NC#16
NC#17

GND#1

GND#2

EPAD

16

23

2

TPM_VDD

2
3
5
7
9
10
11
12
14
15
25
26
27
28
31
32

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Thursday, August 09, 2018

Date: Sheet of

Thursday, August 09, 2018

Date: Sheet of

Thursday, August 09, 2018

PROJECT :

NGFF/BT/TPM

NGFF/BT/TPM

NGFF/BT/TPM

ZHVA

ZHVA

ZHVA

1

1A

1A

1A

3421

3421

3421

B B

A A

+1.8V_S5

R127

TPM@2.2_5%_6

TPM@10u/6.3V_6

5

10mil

C119

+1.8V_S5

NOTE:

- Place 0.1 uF capacitors as close as possible to the device power pins.

- VHIO can be either +3.3V or +1.8V.

- It is recommended to connect VHIO to V_RUN.

- VALW can be either +3.3V or +1.8V.

- VALW power rail should be powered whenever the system is powered
by any power source.

- For details regarding the TPM power sequence, see the NPCT75x
Datasheet and Board Design Guidelines.

C89

TPM@0.1u/16V_4

R123 10K_5%_4
R103 10K_5%_4
R97 10K_5%_4

Layout Note:
R3641 close to TPM IC

TPM@0.1u/16V_4

1 2
1 2
1 2

C93

TPM@0.1u/16V_4

4

5

(1.5A) 60 mils

1

C377

0.1u/16V_4

C85

0.1u/16V_4

Q30

321

PJA138K

12

12

Q5

3

*AC@AO3413

2

60 mils

C380

0.1u/16V_4

C387
*4.7u/6.3V_6

IOAC circuit (MPC)

+LAN_POWER

R422
10K_5%_4

2

PCIE_LAN_WAKE#_R

3

1

2N7002K

R313
10K_5%_4

PCIE_REQ_LAN#_R

+LAN_POWER

C378

0.1u/16V_4

C86
*4.7u/6.3V_6

+3V_S5

+3VPCU

C57

*AC@1u/6.3V_4

12

LANPWR#[13]

D D

REGOUT

60 mils

R125 *S_8

R30

*AC@10K_1%_4

C376

0.1u/16V_4

+LAN_POWER

For RTL8111H
* Place 0.1uF CAP close to each
VDD10 pin-- 3, 8, 22, 30

R94 0_5%_8

R34

*AC@100K_1%_4

1 2

C384

0.1u/16V_4

40 mils

C C

C98

0.1u/16V_4

For RTL8111H
* Place 0.1uF/4.7uF CAP close to each
VDD33 pin-- 11, 32

+1.8V_S5

R419
10K_5%_4

+1.8V

R420 0_5%_4

R421 *0_5%_4

R311 0_5%_4

R317 *0_5%_4

12

12

12

Q17

R314 *0_5%_4

PCIE_LAN_WAKE#[3]

B B

LAN_WAKE#[13]

+1.8V_S5

CLK_PCIE_LAN_REQ#[3]

4

+3V [4,5,12,13,14,16,17,18,19,20,21,24,25,26,27,28,29,30]
+3VPCU [6,13,14,15,16,19,21,23,24,29]

For RTL8111H
* Place 1uF CAP close to each VDD10 pin-- 22 (reserve)

VDD10

C385
1u/6.3V_4

C383

0.1u/16V_4

C343

0.01u/50V_4

MDI_0+
MDI_0-

MDI_1+
MDI_1-

MDI_2+
MDI_2-

MDI_3+
MDI_3-

S0

Tramsformer

3

VDD10

VDD10

+LAN_POWER

U18

1

TCT1

2

TD1+

3

TD1-

4

TC2

5

TD2+

6

TD2-

7

TC3

8

TD3+

9

TD3-

10

TC4

11

TD4+

12

TD4-

+LAN_POWER

MDI_0+
MDI_0-

MDI_1+
MDI_1­MDI_2+
MDI_2-

MDI_3+
MDI_3-

NC#4
MX1+

MX1-

NC#3
MX2+

MX2-

NC#2
MX3+

MX3-

NC#1
MX4+

MX4-

GND

A-8300G

25

R101

2.49K_1%_4

24
23
22

21
20
19

18
17
16

15
14
13

33

1
2
3
4
5
6
7
8

LAN_MCT0
LAN_MX0+
LAN_MX0-

LAN_MCT1
LAN_MX1+
LAN_MX1-

LAN_MCT2
LAN_MX2+
LAN_MX2-

LAN_MCT3
LAN_MX3+
LAN_MX3-

VDD10

GND

MDIP0
MDIN0
AVDD10#1
MDIP1
MDIN1
MDIP2
MDIN2
AVDD10#2

RSET

10 mils

32

AVDD33#2

MDIP39MDIN3

R41 75_1%_12

R53 75_1%_12

R72 75_1%_12

R85 75_1%_12

31

10

30

RSET

AVDD10#3

AVDD33#1

11

12

28

CKXTAL229CKXTAL1

CLKREQB

27

HSIP13HSIN14REFCLK_P15REFCLK_N

C117 *10p/50V_4

C116 *10p/50V_4

26

25

LED2

LED0

LED1/GPO

REGOUT
VDDREG

DVDD10

LANWAKEB

ISOLATEB

PERSTB

16

PCIE_REQ_LAN#_R

LANCT3

2

TP2
TP3
TP1

U6
RTL8111H-CG

24
23
22
21
20
19
18

HSON

17

HSOP

CLK_PCIE_LANN
CLK_PCIE_LANP
PCIE_TXN2_LAN
PCIE_TXP2_LAN

10p/3KV_1808

C332

XTAL2

XTAL1

REGOUT
+LAN_POWER
VDD10

ISOLATEB
PERSTB

C112 0.1u/16V_4
C107 0.1u/16V_4

2/6 Change from 10pF to 12pF

C102

4

3

12p/50V_4

Y1
25MHZ/30ppm

1

2

C108

12p/50V_4

PERSTB

default Non-IOAC 11/6

PCIE_LAN_WAKE#_R

PCIE_RXN2_LAN
PCIE_RXP2_LAN

CLK_PCIE_LANN [3]
CLK_PCIE_LANP [3]

PCIE_TXN2_LAN [3]
PCIE_TXP2_LAN [3]

RJ45 Connector

LAN_MX0+
LAN_MX0­LAN_MX1+
LAN_MX2+
LAN_MX2­LAN_MX1­LAN_MX3+
LAN_MX3-

1
2
3
4
5
6
7
8

1

R130 *AC@0_4
R129 NAC@0/J_4

PCIE_RXN2_LAN [3]
PCIE_RXP2_LAN [3]

Consider VCC33 may be connected to Main
P

ower or chipset/bios's GPO, the pull-low
resistor R14 can be NC only when Main Power
or chipset/bios's GPO can ensure to drive the
ISOLATEB pin to a voltage level < 0.8V at the
system state S1~S5.

If the ISOLATEB pin can not be well-controlled to
a voltage level < 0.8V at S1~S5, the pull-low
resistor R14 is needed to make sure the LAN
chip is well isolated.

910

CN5

60404-08GAX

IOAC_RST# [13,21]
PLTRST# [6,13,17,21]

+3V

22

R416
1K_5%_4

R417
15K_5%_4

GST5009B LF H=4.0mm

Layout:All termination

ignal should have 30

A A

s
mil trace

SYMBOL AOP,PN YMI

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Thursday, August 09, 2018

Date: Sheet of

Thursday, August 09, 2018

Date: Sheet of

5

4

3

2

Thursday, August 09, 2018

PROJECT :

LAN(RTL8111H-CG)

LAN(RTL8111H-CG)

LAN(RTL8111H-CG)

ZHVA

ZHVA

ZHVA

1A

1A

1A

3422

3422

1

3422

5

4

3

2

1

PJ5

4

2

D D

4

-

3

+

5

5

30706-00042-001

3

1

PC96

PC97

2200p/50V_4

0.1u/50V_6

VA VA1

PD4
SV1040

2
1

PD1

2 1

P4SMAFJ20A

PQ13
AON6414AL

3

D

3

PC98

0.1u/50V_6

5

PC117
1000p/50V_4

G

4

S

2
1

4.02K_1%_4

PR153

(1) Double Check ADP-IN Connector with ME

PR116
20_5%_12

C C

REGN6V

ACDET=16.4V

PR112
100K_1%_4

ACIN[13]

CS31542FB14 15.4K 1/16W +-1% (0402) For 78W
CS31272FB17 12.7K 1/16W +-1% (0402) For 95W
CS31002FB26 10K 1/16W +-1% (0402) For 116W

PC232

PC78

*47p/50V_4

0.1u/50V_6

PC233

*100p/50V_4

5

PR111 *0_5%_4

PR104 100_5%_4

PR106
100_5%_4

2 1

PD3
PDZ5.6B

B B

PJ16
50458-00801-V02

8
7
6
5
4
3
2
1

9 10

Double Check BATT Connector
with ME

A A

2 1

PD2
PDZ5.6B

PR103
100_5%_4

PR113
100K_1%_4

PMON[27,28]

BAT-V

TEMP_MBAT#

PR115
1M_5%_4

PC77
*47p/50V_4

PMON

PR102

*SP@15.4K_1%_4

+3VPCU

MBCLK [13]

MBDATA [13]

BI# [13]

TEMP_MBAT# [13]

PR114
137K_1%_4

ICMNT[13]

TP32

+3VPCU

MBDATA
MBCLK
ICMNT
D/C#

PR107
866K_1%_4

PC72

*100p/50V_4

PR89 10K_5%_4
PR84 *10K_5%_4

PR83
316K_1%_4

4

PC73

0.47u/50V_6

PR109 *S_4
PR96 *S_4
PR95 *S_4
PR105 *S_4
PR101 *S_4
PR100 *0_5%_4

Set Floating for PMON unusing

PC74

PC71

100p/50V_4

100p/50V_4

PR85

100K_1%_4

0.01u/50V_4

PC67

VA2

PC118

0.047u/50V_6

24780_CMSRC

24780_ACDRV
24780_VCC

24780_ACDET

24780_BM#
24780_CMPOUT
24780_ILIM
24780_CMPIN

PR93
100K_5%_4

0.1u/16V_4

PR108

4.02K_1%_4

C295

3

4

28

6

5
11
12

7

8

9

16
14
21
13

PC81

0.1u/50V_6

PU3

CMSRC

ACDRV
VCC

ACDET
ACOK
SDA
SCL
IADP
IDCHG
PMON

TB_STAT
CMPOUT
ILIM

CMPIN

GND#835GND#936GND#1037GND#11

10

38

+1.8V_S5

PC75

0.1u/50V_6

2

ACP

PROCHOT

BATPRES

15

TEMP_MBAT#

PR98
*100K_5%_4

GND#1

22

*S_4

PR90

3

24780_ACP

24780_ACN

1

BATDRV

ACN

BATSRC

GND#229GND#330GND#431GND#532GND#633GND#7

PR91

PR97
*S_4

PR137

0.01_1%_0612

PC80

0.1u/50V_6

REGN

BTST

HIDRV

PHASE

LODRV

SRP

SRN

BQ24780SRUYR

34

*0_5%_4

24780_BATDRV

18

24780_BATSRC

17

24

24780_BST

25

24780_DH

26

24780_LX

27

24780_DL

23

20

19

H_PROCHOT#

PR86
*S_6

PR87
*S_6

PR145
*S_4

PR144
*S_4

REGN6V

PR99
*S_6

24780_ACN

24780_ACP

PC68

2.2u/10V_6

PC69

0.047u/50V_6

PC63

0.1u/25V_4

24780_SRP

PC64

0.1u/25V_4

24780_SRN

PC65

0.1u/25V_4

H_PROCHOT# [6,13,27,28]

PQ23
AON7410

4

PQ22
AON7410

4

PC79
2200p/50V_4

PR88
10_1%_6

PC235
2200p/50V_4

PR92
*4.7_5%_6

PC66
*680p/50V_6

PQ11
AON6414AL

5

1 2

D

S

G

4

PR110
*S_6

+VIN

PL10

6.8uH_7x7x3

3
2
1

PC234
10u/25V_8

PC70

*0.01u/50V_4

PR256

0.01_1%_0612

PR254

PR253

*S_4

*S_4

24780_SRP
24780_SRN

REGN MAX voltage 6.5V
V_ILIM=20*(VSRP-VSRN)=20*Ichg*Rsr
=0.793V for 3.965A current limit

ILIM=0.793V
Rsr = 0.01ohm

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Charger (BQ24780S)

Charger (BQ24780S)

Charger (BQ24780S)

Date: Sheet of

Date: Sheet of

Date: Sheet of

BAT-V

PC227

PC225

22u/25V_8

2200p/50V_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

1

BAT-V

PC230
22u/25V_8

ZHVA

ZHVA

ZHVA

23 34Thursday, August 09, 2018

23 34Thursday, August 09, 2018

23 34Thursday, August 09, 2018

23

1A

1A

1A

+VIN

PC76

0.1u/50V_6

D

G

S

2

153

D

G

S

2

153

2

5

+VIN

PJ6
*S_3720

D D

PR18
*S_4

SYS_SHDN#[13,30]

C C

SYS_SHDN#

KL_NO_EC[13]

PR260

*100K_1%_6

PR17

10K_1%_4

3

2

PQ24

1

2N7002K

PC19

0.1u/16V_4

SYS_SHDN#

To Thermal Protection

High frequency noise eliminate circuit

+VIN

PR26
*S_4

SYS_SHDN#

KL_NO_EC

PR261

*100K_1%_6

PR29

10K_1%_4

PC21

0.1u/16V_4

3

2

PQ25
2N7002K

1

VL

LDO=5V/100mA

5

B B

A A

SYS_HWPG[13]

PR24
10K_1%_4

Power Auto Recovery

680_LDO

680_LDO V3A_VBYP

680_LDO[13]

PJ10
*S_3720

SYS_HWPG

PR162 *S_4

PR163 *S_6

VL

PC113

0.1u/25V_4

V3A_VBYP

PC154

0.1u/25V_4

+3VPCU

SYS_HWPG

PR19 10K_1%_4
PR22 *S_4
PR20 100K_1%_4

PC131

4.7u/6.3V_4

PR209
*S_6

PC152

0.1u/25V_4

PC143

4.7u/10V_6

V5P5A_VOUT

PC124

PC119

2200p/50V_4

V3A_EN

V3A_VOUT

PR161

1K_1%_4

PC135

10p/50V_4

+V5P5A_VIN

PC145

PC148

10u/25V_8

10u/25V_8

(1) USM : 0.8V-1.7V
(2) Normal Mode : >2.3V

V5P5A_EN

V5P5A_PWRGD

PR28

1K_1%_4

PC22

10p/50V_4

0.1u/25V_4

(1) USM : 0.8V-1.7V
(2) Normal Mode : >2.3V

PR157
*S_4

LDO=3.3V/100mA

6

7

12

8

PR164
*1K_1%_4

PR27
*10K_1%_4

4

+V3A_VIN

PC112

PC120

10u/25V_8

10u/25V_8

6

EN

V3A_PWRGD

7

PGOOD

11

LDO3

8

AGND

PR160
*1K_1%_4

PR159
*10K_1%_4

PC150

2200p/50V_4

V5P5A_BOOT

1

5

VIN

BOOT

EN

PGOOD

LDO5

AGND

FF

9

11

+VCC_V5P5A

VCC=5V
(DON'T Connect to External Load)

4

PR158
10_1%_6

V3A_BOOT

PU7

1

5

RT6256BGQUF

VIN

2

BOOT

LX#1

3

LX#2

10

VOUT

4

PGND

VCC

FF

9

12

+VCC_V3A

PC127
1u/10V_4

VCC=5V
(DON'T Connect to External Load)

V5P5A_BOOT_R

PU8

2
3

10

4

V5P5A_VOUT

PC147

0.1u/25V_4

PR166
10_1%_6

RT6258CGQUF

LX#1
LX#2

VOUT

PGND

VCC

PC139
1u/10V_4

PC138

0.1u/16V_4

V3A_BOOT_R

V3A_VOUT

PC134

0.1u/25V_4

PR25
*S_4

PC128

0.1u/16V_4

1uH/11A_7x7x3

1 2

PR173
*S_4

PR30
*4.7_5%_6

+V5P5A_LX_R

PC23
*680p/50V_6

PL5

+V3A_LX

PR23
*4.7_5%_6

+V3A_LX_R

PC18
*680p/50V_6

PL3

1uH/11A_7x7x3

1 2

3

+3VPCU
3

.3 Volt +/- 5%
TDC : 6A
Width : 240mil
FSW : 500KHZ

+3VPCU

PJ9

+V3A_OUT

PC115

PC114

22u/6.3V_6

PC129

PC125

22u/6.3V_6

22u/6.3V_6

PC126

PC122

22u/6.3V_6

*22u/6.3V_6

*S_3720

PC132

0.1u/16V_4

*22u/6.3V_6

2

TDC : 1A
PEAK : 1.33A
Width : 40mil

+5VPCU

S5_ON[13,28,29]

S5_ON

PC2
10u/6.3V_6

PR129 *S_4

+VIN [14,23,25,26,27,28,30]
+3VPCU [6,13,14,15,16,19,21,22,23,29]
+5VPCU [25,29]

VL [30]

+5V [14,17,19,30]

+5V_S5 [6,18,26,27 ,28]

+3V [4,5,12,13,14,16 ,17,18,19,20,21,22,25,26,27,28,29,30]

+3V_S5 [3,6,7,12,13,15 ,22,26,29]

PC3
1u/25V_4

1

13

VOUT1#1

14

PC1

VOUT1#2

0.1u/16V_4

4

VBIAS

PC9

0.1u/16V_4

3

PC6
*0.1u/16V_4

1000p/50V_4

ON1

PC8

PR128
*S_4

VIN1#22VIN1#1

PU1

AOZ1331DI

CT1

12

VIN2#16VIN2#2

CT2

10

7

OUT2#1
OUT2#2

GND#1
GND#2

ON2

PC10
1000p/50V_4

1

24

+3VPCU+3VPCU

TDC : 3.66A
P

EAK : 4.89A

MAINON

PC15
10u/6.3V_6

Width : 160mil

+3V+3V_S5

MAINON [13,25,26,29,30]

PC13
1u/25V_4

8

PC16

9

0.1u/16V_4

11
15

PR136
*S_4

5

PC11
*0.1u/16V_4

Soft-Start

+5VPCU +5VPCU

MAINON

PC176
10u/6.3V_6

TDC : 4A
PEAK : 5.3A
Width : 160mil

TDC : 5.25A

EAK : 7A

+5VPCU
5 Volt +/- 5%
TDC : 8A
Width : 320mil
FSW : 750KHZ

+5VPCU

PJ14

+V5P5A_OUT+V5P5A_LX

PC165

PC162

PC160

PC172

22u/6.3V_6

22u/6.3V_6

PC169

22u/6.3V_6

22u/6.3V_6

*22u/6.3V_6

*S_3720

PC157

PC173

0.1u/16V_4

*22u/6.3V_6

P
Width : 240mil

+5V_S5 +5V

PC195
10u/6.3V_6

PR44

+5VPCU

*S_4

S5_ON

PC193
1u/25V_4

1

VIN1#22VIN1#1

13

VOUT1#1

14

PC196

VOUT1#2

0.1u/16V_4

PC185

0.1u/16V_4

PR45
*S_4

4

3

PC192
*0.1u/16V_4

1000p/50V_4

PU11

AOZ1331DI

VBIAS

ON1

CT1

12

PC190

VIN2#16VIN2#2

10

7

OUT2#1
OUT2#2

GND#1
GND#2

CT2

PC184

1000p/50V_4

PC181
1u/25V_4

8

PC177

9

0.1u/16V_4

11
15

PR41
*S_4

5

ON2

PC183
*0.1u/16V_4

Soft-Start

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

ZHVA

PROJECT :

ZHVA

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

SYSTEM 5V/3V (RT6256B/RT6258C)

SYSTEM 5V/3V (RT6256B/RT6258C)

SYSTEM 5V/3V (RT6256B/RT6258C)

Date: Sheet of

Date: Sheet of

3

2

Date: Sheet of

1

ZHVA

1A

1A

1A

24 34Thursday, August 09, 2018

24 34Thursday, August 09, 2018

24 34Thursday, August 09, 2018

5

D D

4

3

2

+VIN [14,23,24,26,27,28,30]
+1.05V [6,7,27,28]
+5VPCU [24,29]
+3V [4,5,12,13,14,16,17,18,19,20,21,22,24,26,27,28,29,30]

1

25

G5335-AGND-1

PC104
*0.01u/50V_4

PR156

2.2_5%_6

PC110

0.1u/25V_4

PR21
*4.7_5%_6

PC20
*680p/50V_6

PL4

0.68uH_7x7x3

1 2

PJ4
*S_3720

PC105

*0.1u/25V_4

PC141

22u/6.3V_6

PC107

PC101

10u/25V_8

2200p/50V_4

PC130

PC144

22u/6.3V_6

22u/6.3V_6

VFB=0.8V

+VIN

+1.05V

1.05 Volt +/- 5%
TDC : 3.38A
PEAK : 4.5A
Width : 160mil

PJ11
*S_3720

PC133

PC142

PC137

22u/6.3V_6

22u/6.3V_6

PC136

PC140

*22u/6.3V_6

0.1u/16V_4

*22u/6.3V_6

PR12

6.34K_1%_4

PR138
20K_1%_4

G5335-AGND-1

R1

PC14
*1000p/50V_4

R2

Vo=0.8*(R1+R2)/R2

=1.0536V

+1.05V

Fsw=550KHz

PR134

73.2K_1%_4

G5335-TON-1

6

PU6

7

+5VPCU

Double check PU high with HW

C C

HWPG_1.05V[13]

G5335-AGND-1

+5VPCU

PR154

100K_1%_4

Pulse-Skipping mode

MAINON[13,24,26,29,30]

B B

PR146
*S_4

+3V

PR15
*0_5%_4

PR142
*S_4

PR155
10_5%_6

PC111

*0.047u/16V_4

G5335-AGND-1

PR152
*S_4

PC123
10u/6.3V_6

G5335-VCC-1

G5335-PWRGD-1

G5335-PFM-1

G5335-EN-1

G5335-SS-1

PC121

0.047u/16V_4

G5335-AGND-1

NC

21

VCC

1

PGOOD

3

PFM

2

EN

23

SS

G5335QT2U

G5335-AGND-1

PR16
*S_4

TON

V+#1
V+#2
V+#3
V+#4

LX#1
LX#2
LX#3
LX#4
LX#5
LX#6

PGND#1
PGND#2
PGND#3
PGND#4
PGND#5

AGND

BST

8
9
22
24

20

G5335-BST-1

25
10
11
16

G5335-LX-1

17
18

12
13
14
15
19
4

5

G5335-FB-1

FB

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

+1.05V (G5335QT2U)

+1.05V (G5335QT2U)

+1.05V (G5335QT2U)

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet

PROJECT :

ZHVA

ZHVA

ZHVA

1A

1A

1A

of

25 34Thursday, August 09, 2018

25 34Thursday, August 09, 2018

1

25 34Thursday, August 09, 2018

1

+3V

PR151
100K_1%_4

HWPG_1.2VSUS[13]

A A

TDC : 0.375A
PEAK : 0.5A
Width : 20mil

B B

SUSON[13]

MAINON[13,24,25,29,30]

TDC : 0.375A
PEAK : 0.5A
Width : 20mil

+VDDQ

PC93

0.1u/16V_4

PR140
*0_5%_4

PR124
100_1%_4

PR135
*S_4

1P35V_S51P35V_S3

PR143
*S_4

PR139
*S_4

+VDDQ_VTT

PC92

0.033u/16V_4

+1.2VSUS

PC102
*0.1u/16V_4

PC95
10u/6.3V_6

VID

+5V_S5

PC106
*0.1u/16V_4

20

VTT

2

VTTSNS

1

VTTGND

4

VTTREF

19

VLDOIN

PC94

22u/6.3V_6

PR123
*S_4

PR150 *S_4

PR149 *0_5%_4

Ref. Voltage

1P35V_S5

1P35V_S3

7

RT8231BGQW

GND

3

11

1P35V_PGOOD

10

S58S3

PU5

VID

14

1P35V_VID

R2

High 0.675V

Low

OCP=10A
L ripple current
=(19-1.2)*1.2/(2.2u*500k*19)
=1.022A
Vtrip=10-(1.022/2)*14.5mohm
=137.59mV
Rlimit=137.59mV/5uA*10=275.18Kohm

0.75V

DDR=1.2V
R1=7.87K/F_4
R2=10K/F_4

PGOOD

PR147
274K_1%_4

1P35V_CS

13

CS

FB

6

1P35V_FB

R1

PR130
10K_1%_4

OCP=10A

1P35V_TON

9

TON

PAD

VDDQ5PGND

21

1P35V_VDDQ

PR131

7.87K_1%_4

2

1P35V_UGATE

17

UGATE

1P35V_BOOT

18

BOOT

1P35V_PHASE

16

PHASE

1P35V_LGATE

15

LGATE

1P35V_VDD

12

VDD

Vo=Vref x (R1/R2+1)
=1.206V

Fsw=500KHz

PR141
499K_1%_4

PC108

PR133

0.1u/50V_6

2.2_5%_6

+5V_S5

PR148
*S_4

PC116
1u/6.3V_4

S3

S0

S3 (mainon off) 1

1

0

S4/S5

+VIN [14,23,24,25,27,28,30]
+1.2VSUS [7,10,11]
+1.2V [30]
+VDDQ_VTT [10,11]
+5V_S5 [6,18,24,27,28]
+3V [4,5,12,13,14,16,17,18,19,20,21,22,24,25,27,28,29,30]

PQ12
AON7410

PQ16
AON7752

D

G

4

S

2

153

5

D

G

4

S

213

Rds(on)=14.5mohm

VDDQ

ON

1

ON ON

OFF

0

3

PC5

0.1u/25V_4

PR14
*4.7_5%_6

PC17
*680p/50V_6

PC86

10u/25V_8

ON

OFF

PC85

10u/25V_8

PL2

1uH_7x7x3

1 2

Isat=14A

VTTVTTREFS5

ON

OFF

OFF0

4

5

26

+1.2VSUS

PC12

0.1u/16V_4

1.2 Volt +/- 5%
TDC : 5.91A
PEAK : 7.88A
OCP : 10A
Width : 240mil

+1.2VSUS

PJ8
*S_3720

PC89

PC87

22u/6.3V_8

22u/6.3V_8

for HDMI re-timer IC

+1.2VSUS

3

2

MAIND[29,30]

PC90

PC88

PC100

22u/6.3V_8

22u/6.3V_8

PC91

22u/6.3V_8

22u/6.3V_8

MAIND

PQ5
*AO3404

1

+1.2V

TDC : 0.261A
PEAK : 0.348A
Width : 20mil

+VIN

PJ3
*S_3720

PC4

2200p/50V_4

PR127
*S_4

PC83

0.1u/25V_4

C C

+2.5VSUS Power Rail For DDR4

+3V_S5 [3,6,7,12,13,15,22,24,29]

PR120

+3V

+3V_S5

HWPG_2.5V[13]

PR126 *0_5%_4

PR122 *S_4

PR118
100K_1%_4

PR117
*S_4

PR125
10K_5%_4

Double Check PU high with HW

SUSON

DDR4_SUSON_2V5[13]

D D

1

*S_6

PC82

4.7u/6.3V_6

4

PU4

VIN

VFB

6

LX

GND

PR119
15K_1%_4

3

G5719LX2.5V

2

PR121

47.5K_1%_4

R1

5

PG

G5719CTB1U

1

EN

PC84

0.47u/6.3V_4

R2

2

+2.5V_SUS [10,11]

PL1

2.2uH_2.5x2.0x1.2

1 2

PR132
*S_4

PC99

Vo=(0.6(R1+R2)/R2)
=2.5V

PC109

PC103

10u/6.3V_6

0.1u/16V_4

*10u/6.3V_6

3

PJ7
*S_3720

+2.5V_SUS

2.5Volt +/- 5%
TDC : 0.91A
PEAK : 1.2A
Width : 40mil

+2.5V_SUS

Reserve +2.5V for DDR4 VDDSPD

+2.5V_SUS

3

2

MAIND

4

PQ4
*AO3404

1

TDC : 0.156A
PEAK : 0.21A
Width : 20mil

Double Check with HW if Reserve

+2.5V

+2.5V [30]

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

DDR4 (RT8231BGQW)

DDR4 (RT8231BGQW)

DDR4 (RT8231BGQW)

Date: Sheet of

Date: Sheet of

Date: Sheet

PROJECT :

ZHVA

ZHVA

ZHVA

of

26 34Thursday, August 09, 2018

26 34Thursday, August 09, 2018

5

26 34Thursday, August 09, 2018

1A

1A

1A

5

SVID_CLK : UP:160 ohm Series:95 ohm
SVID_ALERT : UP:68 ohm Series:220 ohm
SVID_DATA : UP:240 ohm Series:20 ohm

+1.05V

4

3

2

+VIN [14,23,24,25,26,28,30]
+VCC_VCCGI [7]
+3V [4,5,12,13,14,16,17,18,19,20,21,22,24,25,26,28,29,30]
+5V_S5 [6,18,24,26,28]
+1.8V_S5 [3,4,5,6,7,9,12,15,21,22,23,29]
+1.05V [6,7,25,28]

1

27

D D

PR211
240_1%_4

PR212
*200_1%_4

Check SVID PU UP R/Series R with HW

IMVP_PWRGD[13]

PR217 *10K_1%_4

+3V

H_CPU_SVIDCLK[6,28]

VR_SVID_ALERT#_VCORE[6,28]

+VREF_VCGI

1425mV
901mV

PR215 *S_4
PR216 *0_5%_4

H_PROCHOT#[6,13,23,28]

H_CPU_SVIDDAT[6,28]

+VREF_VCGI

PR246

57.6K_1%_4

VNN_ON[13,28]

C C

CheckENSequencewithHW

B B

VRON[13]

Vset1
Delta Vset1

675mVVset2
Delta Vset2 49.8mV
Vset3

A A

Delta Vset3
VTsen

974mV

950mV

448mV

5

PC206

PR213

1000p/50V_4

160_1%_4

H_CPU_SVIDDAT
VR_SVID_ALERT#_VCORE
H_CPU_SVIDCLK

+3V

+1.8V_S5

Imax=26A

PR226

24.9K_1%_4

FSW=550KHZ

PR228

2.94K_1%_4

PR230

38.3K_1%_4

PC214
1000p/50V_4

PR247
1K_1%_4

PR238

9.53K_1%_4

PR239
*S_4

PR214
10K_1%_4

PR210
*20K_1%_4

PR222 95.3_1%_4
PR221 *S_4
PR220 20_1%_4

PR227
365_1%_4

PR229
20_1%_4

PR231
681_1%_4

PR236
121K_1%_4

PR237
100K_NTC_4_1%

B=4250

PUT COLSE
TO VCCGI
HOT SPOT

PR223
*S_4

PR67
20K_1%_4

PR69
680_1%_4

PR72

16.9K_1%_4

12

+5V_S5 +5V_S5

VR_READY_VCGI

PC207
*0.1u/16V_4

VRON_VCGI

PR219 *S_4

VCLK_VCGI
ALERT#_VCGI
VDIO_VCGI

SET1_VCGI

PR66
280_1%_4

SET2_VCGI

PR68
110_1%_4

SET3_VCGI

PR71
182_1%_4

TSEN_VCGI

4

PR224
22_5%_6

PMON[23,28]

PC213

2.2u/10V_4

7

VR_READY

2

EN

3

VRHOT

6

VCLK

5

ALERT

4

VDIO

28

SET1

27

SET2

26

SET3

16

TSEN

VCC_VCCGI

DRVEN15PSYS

PMON

1

VCC

RT3601EAGQW

19

PU12

PR242
*S_4

PVCC2

12

PVCC

PC218

2.2u/10V_4

UGATE

BOOT

PHASE

LGATE

PWM

ISEN1P
ISEN1N

IMON

VREF

VSEN

COMP

RGND

GND

29

PR75

2.2_5%_6

FB

VIN

13

PC217

0.1u/25V_4

9
8

10
11

14

20
21

18

17

25

23

24
22

PR73

3.3_5%_6

PQ20
AON6414AL

PR218
*S_6

UGATE_VCGI
BOOT_VCGI

PHASE_VCGI
LGATE_VCGI

ISEN1P_VCGI
ISEN1N_VCGI

Vref=0.6V

COMP_VCGI

FB_VCGI
GND_VCGI

PC59

0.1u/50V_6

PR76

16.2K_1%_4

PR243 3.9_1%_4

PR74 *S_4

PC215 100p/50V_4

PR233 37.4K_1%_4 PR232 10K_1%_4

LL~6m

+VIN_VCC_VCGI

3

G

4

PQ21
AON6792

G

4

PC222

0.1u/16V_4

PR78

40.2K_1%_4

Imax=26A

PC223 0.47u/6.3V_4

PC216 330p/50V_4

153

2

5

213

D

S

D

S

+VIN_VCC_VCGI

PC55

2200p/50V_4

PHASE_VCGI

PR70
*2.2_5%_6

PC60
*2200p/50V_4

+VREF_VCGI

PC54

0.1u/25V_4

PC204

PR240
*S_4

PC219
*0.1u/25V_4

PR241
*S_4

PC197

10u/25V_8

10u/25V_8

Isat=45A
DCR=0.66m ohm

PL9

0.15uH/36A_7x7x4

1 2

PR62
*S_4

PR77
365_1%_4

PR245
604_1%_4

PC61
*100p/50V_4

PC62
*100p/50V_4

2

PC56

0.1u/25V_4

PR63
*S_4

PC221

1u/6.3V_4

PR248
10K_1%_4

1 2

PR225

1K_NTC_4_3%

+VCC_VCCGI

PJ2
*S_3720

Place close
with VCORE
Inductor
B=3650

PR64
100_1%_4

PR65
100_1%_4

+VIN

+VCC_VCCGI

PC50

PC51

PC202

22u/6.3V_6

22u/6.3V_6

PC47

PC198

22u/6.3V_6

22u/6.3V_6

PC52

22u/6.3V_6

PC201

22u/6.3V_6

22u/6.3V_6

PC212

PC209

22u/6.3V_6

22u/6.3V_6

PC200

PC199

22u/6.3V_6

22u/6.3V_6

PC58

PC210

22u/6.3V_6

PC208

22u/6.3V_6

PC211

22u/6.3V_6

PC48

22u/6.3V_6

PC49

PC194

22u/6.3V_6

PC46

PC57

*10u/6.3V_4

Total 20pcs 22u_0603 (with HW)

VCCGI_SENSE [7]
VCCGISS_SENSE [7]

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

+VCC_VCCGI (RT3601EAGQW)

+VCC_VCCGI (RT3601EAGQW)

+VCC_VCCGI (RT3601EAGQW)

Date: Sheet of

Date: Sheet of

Date: Sheet of

+VCCGI

Icc Max：25A
Icc TDC：18A
Vboot：0V
OCP：35A
Fsw：550KHZ

VCCGI L/L：

R_DC_LL：6mV/A
R_AC_LL：6mV/A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

1

ZHVA

ZHVA

ZHVA

27 34Thursday, August 09, 2018

27 34Thursday, August 09, 2018

27 34Thursday, August 09, 2018

：

：：

22u/6.3V_6

22u/6.3V_6

*10u/6.3V_4

1A

1A

1A

5

SVID_CLK : UP:160 ohm Series:95 ohm
SVID_ALERT : UP:68 ohm Series:220 ohm
SVID_DATA : UP:240 ohm Series:20 ohm

+1.05V

D D

PR59
*240_1%_4

PR60
*200_1%_4

PR61
*160_1%_4

PC205
1000p/50V_4

H_CPU_SVIDDAT
VR_SVID_ALERT#_VCORE
H_CPU_SVIDCLK

Check SVID PU UP R/Series R with HW

PR199 10K_1%_4

VNN_ON[13,27]

S5_ON[13,24,29]

+VREF_VNN

+3V

PC30

1000p/50V_4

PR36

47.5K_1%_4

PR208 *S_4

PR206 *1K_1%_4

H_PROCHOT#[6,13,23,27]

PR52
221K_1%_4

PR49
100K_1%_4

PR196
215K_1%_4

PR37
324_1%_4

PR191

6.04K_1%_4

PR186

3.83K_1%_4

IMVP_PWRGD_VNN[13]

CheckENSequencewithHW

C C

H_CPU_SVIDCLK[6,27]

VR_SVID_ALERT#_VCORE[6,27]

H_CPU_SVIDDAT[6,27]

B B

Vset1
Delta Vset1

+VREF_VNN

124.9mV
899mV

PR204
*S_4

PR57 95.3_1%_4
PR56 *S_4
PR207 20_1%_4

PR51
68K_1%_4

PR47

22.6K_1%_4

PR197

2.15K_1%_4

PR190
121K_1%_4

PR176
100K_NTC_4_1%

B=4250

PUT COLSE
TO VNN
HOT SPOT

PR55 *S_4

373.4mVVset2

Delta Vset2 1.14V

A A

Vset3
Delta Vset3
VTsen

176mV
950mV
548mV

5

PR54

11.5K_1%_4

PR198

12.4K_1%_4

PR200

3.48K_1%_4

12

4

VR_READY_VNN

PC203

0.1u/16V_4

VRON_VNN

VCLK_VNN
ALERT#_VNN
VDIO_VNN

PR53
210_1%_4

PR203

3.83K_1%_4

PR202

9.09K_1%_4

TSEN_VNN

4

PR58
22_5%_6

SET1_VNN

SET2_VNN

SET3_VNN

3

VCC_VNN

VNN_PVCC1

PC53

2.2u/10V_4

1

VCC

7

VR_READY

2

EN

3

VRHOT

6

VCLK

5

ALERT

4

VDIO

DRVEN15PSYS

PMON

PU2

RT3601EAGQW

19

28

SET1

27

SET2

26

SET3

16

TSEN

PMON[23,27]

PC39

2.2u/10V_4

12

PVCC

UGATE

BOOT

PHASE
LGATE

PWM

ISEN1P

ISEN1N

IMON

VREF

VSEN

COMP

FB

RGND

VIN

GND

13

29

PC38

0.1u/25V_4

PR42

2.2_5%_6

9
8

10
11

14

20
21

18

17

25

23

24
22

UGATE_VNN
BOOT_VNN

PHASE_VNN
LGATE_VNN

ISEN1P_VNN
ISEN1N_VNN

COMP_VNN

FB_VNN
GND_VNN

PR193

3.3_5%_6

+5V_S5+5V_S5

PC45

0.1u/50V_6

PR188

30.1K_1%_4

PR35 3.9_1%_4

PR195 *S_4

PC40 82p/50V_4

PR43 57.6K_1%_4

+VIN_VNN

PQ19
AON7410

PR48
*S_6

4

4

PQ18
AON7752

PC32

0.1u/16V_4

PR189

20.5K_1%_4

PC31 0.47u/6.3V_4

D

G

S

2

153

5

D

G

S

213

PC41 470p/50V_4

PR194 10K_1%_4

PC36

2200p/50V_4

PHASE_VNN

PR38
*2.2_5%_6

PC33
*2200p/50V_4

PC37

0.1u/25V_4

+VREF_VNN

PC34
*0.1u/25V_4

PC180

PR40
*S_4

PR39
*S_4

10u/25V_8

2

+VIN [14,23,24,25,26,27,30]
+VNN [7]
+5V_S5 [6,18,24,26,27]
+1.05V [6,7,25,27]
+3V [4,5,12,13,14,16,17,18,19,20,21,22,24,25,26,27,29,30]

PC35

PC179

10u/25V_8

0.1u/25V_4

Isat=26A
DCR(MAX)= 4.2m ohm

PL8

0.47uH/17.5A_7X7X3

1 2

PR181
*S_4

PR187
402_1%_4

PR33
402_1%_4

PC186
*100p/50V_4

PC182
*100p/50V_4

PR178
*S_4

PC178

0.47u/10V_4
PR32

1K_1%_4
PR177

1 2

1K_NTC_4_3%

+VNN

PJ15
*S_3720

B=3650

Place close
with VCORE
Inductor

PR46
100_1%_4

PR50
100_1%_4

+VIN+VIN_VNN

+VNN

PC42

PC167

PC175

22u/6.3V_6

22u/6.3V_6

PC26

PC166

22u/6.3V_6

PC25

22u/6.3V_6

22u/6.3V_6

PC44

PC28

22u/6.3V_6

22u/6.3V_6

PC174

22u/6.3V_6

PC27

PC43

22u/6.3V_6

PC188

PC189

22u/6.3V_6

Total 6pcs 22u_0603 (with HW)

VNN_SENSE [7]
VNNSS_SENSE [7]

+VNN

Icc Max：5.6A

1

28

PC168

22u/6.3V_6

22u/6.3V_6

PC187

22u/6.3V_6

22u/6.3V_6

PC29

22u/6.3V_6

PC191

*10u/6.3V_4

*10u/6.3V_4

Icc TDC：N/A

PR34
*S_4

Vboot：1.05V
OCP：10A
Fsw：600KHZ

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

+VNN (RT3601EAGQW)

+VNN (RT3601EAGQW)

+VNN (RT3601EAGQW)

Date: Sheet of

Date: Sheet of

3

2

Date: Sheet of

PROJECT :

ZHVA

ZHVA

ZHVA

1A

1A

28 34Thursday, August 09, 2018

28 34Thursday, August 09, 2018

1

28 34Thursday, August 09, 2018

1A

5

D D

H cha _  pull up to 3_

HWPG_1.8V_S5[13]

S5_ON[13,24,28]

C C

PR184
100K_1%_4

PJ12
*S_3720

+3V_S5

hc  Hih uc with HW

HWPG_1.24V_S5[13]

+3VPCU

+3V_S5

PR165
100K_1%_4

Check RC delay time with HW
(follow ZHP RC dealy time)

PR182
*S_4

PC156

0.01u/50V_4

5671PG_1.24V

PR172
10_5%_6

PC159
10u/6.3V_6

4

+3VPCU[6,13,14,15,16,19,21,22,23,24]
+1.8V_S5[3,4,5,6,7,9,12,15,21,22,23,27]
+1.24V_S5[7]
+1.8V[3,4,14,17,20,22,30]
+1.5V[19]

+3VPCU

PR169
*S_4

PR171
120K_1%_4

5671SVIN_1.24V

PC163
1u/6.3V_4

PR168
*S_6

PC153

0.1u/16V_4

4
9

10

8

11

5

PG

1

EN

PU10

POK
VIN#1
VIN#2

VCC
GND

M5671RE1U

4

VIN

PU9

G5719CTB1U

VFB

6

R2

PC24

*2200p/50V_4

LX

GND

PR170
15K_1%_4

NC#1
SW#1
SW#2

NC#2

PC146

4.7u/6.3V_4

3

G5719LX1.8V

2

R1

PR167
30K_1%_4

PR31

*2.2_5%_6

1
2
3
7
6

FB

5

EN

3

PL6

1 2

2.2uH_2.5x2.0x1.2

PR174
*S_4

Vo=(0.6(R1+R2)/R2)
=1.8V

PL7

1uH_7x7x3

5671LX_1.24V

1 2

PC170

PC164
*68p/50V_4

PC171
*0.1u/16V_4

*22p/50V_4

PR183
*S_4

5671NC_1.24V
5671FB_1.24V
5671EN_1.24V

+3V_S5[3,6,7,12,13,15,22,24,26]
+5VPCU[24,25]
+3V[4,5,12,13,14,16,17,18,19,20,21,22,24,25,26,27,28,30]

PC151

10u/6.3V_6

5671FB_1.24V_S

PR179

R1

10K_1%_4

PR180

R2

10K_1%_4

PJ13
*S_3720

PC149

PC155

0.1u/16V_4

*10u/6.3V_6

PR175
*S_4

Vo=0.6*(R1+R2)/R2
=1.24V

2

+1.8V_S5

1.8Volt +/- 5%
TDC : 0.85A
PEAK : 1.13A
Width : 40mil

+1.8V_S5

+1.24V_S5

1.24Volt +/- 5%
TDC : 1.875A
PEAK : 2.5A
Width : 80mil

+1.24V_S5

PJ1
*S_3720

PC158

PC161

0.1u/25V_4

22u/6.3V_6

1

29

+1.8V_S5

3

2

MAIND[26,30]

MAIND

PQ7
AO3404

1

+1.8V

TDC : 0.173A

EAK : 0.23A

P
Width : 20mil

PR258
*S_8

HWPG_1.8V_S5

+1.5V

1.5Volt +/- 5%
TDC : 0.39A
PEAK : 0.52A
Width : 20mil

+1.5V

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

+1.8V_S5 / +1.24V_S5 / +1.5V

+1.8V_S5 / +1.24V_S5 / +1.5V

+1.8V_S5 / +1.24V_S5 / +1.5V

Date: Sheet of

Date: Sheet of

Date: Sheet

2

PROJECT :

1

ZHVA

ZHVA

ZHVA

29 34Thursday, August 09, 2018

29 34Thursday, August 09, 2018

29 34Thursday, August 09, 2018

1A

1A

1A

of

B B

+3VPCU

MAINON[13,24,25,26,30]

+5VPCU

A A

5

MAINON

PR257
*S_4

PR259
*S_8

PR251
*S_4

PC231
1u/25V_4

PC226

PC229

10u/6.3V_6

0.1u/50V_6

PC224

PR250

100K_5%_4

*0.1u/50V_6

HWPG_1.5V[13]

+3V

PR249
100K_5%_4

4

PU14
G9661MF11U

3

VIN

2

VEN
VPP4GND#1

1

POK

5

NC

6

VO

8
9

GND#2

ADJ

7

R1

PR255
30K_1%_4

Vref=0.8V Vo =0.8(1+R1/R2)

PR252
34K_1%_4

2

R

3

PC228
10u/6.3V_6

=1.506V

5

4

VL[24]
+VIN[14,23,24,25,26,27,28]
+3V[4,5,12,13,14,16,17,18,19,20,21,22,24,25,26,27,28,29]
+5V[14,17,19,24]
+1.8V[3,4,14,17,20,22,29]
+2.5V[26]

3

2

1

30

D D

Thermal Protection

(1) Need fine tune

for thermal protect point

PR235

VL

C C

Rset(Kohm)=0.0012T*T-0.9308T+96.147
=29.363 K ohm

B B

MAINON_ON_G

150_1%_4

PR244

30.1K_1%_4

+VIN

PR79
1M_5%_6

PC220

0.1u/16V_4

PR82
22_5%_8

5

OT

VCC

PU13

TMP708AIDBVR

1

SET

GND

HYST

2

4

+5V PU High R= 220 ohm for
Bo-Bo sound issue.

+5V+3V +1.8V

PR94
*220_5%_8

(2) Note placement position

TEMP=80C

3

PR234
*S_4

HYST=VCC for 10
degree Hys.
HYST=GND for 30
degree Hys.

PR2
22_5%_8

SYS_SHDN#

+2.5V +1.2V

PR1
*22_5%_8

SYS_SHDN# [13,24]

PR5
*22_5%_8

+VIN

PR6
1M_5%_6

MAIND

MAIND [26,29]

MAINON[13,24,25,26,29]

PR81

*100K_1%_6

A A

5

2

PQ8

DDTC144EUA-7-F

1 3

PR80
1M_5%_6

3

2

PQ9
2N7002K

1

4

3

2

PQ10
*2N7002K

1

3

2

PQ2
2N7002K

1

3

3

2

PQ1
*2N7002K

1

3

2

PQ6
*2N7002K

1

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

2

3

2

PQ3
2N7002K

1

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

Thermal / Discharge

Thermal / Discharge

Thermal / Discharge

PC7
*2200p/50V_4

ZHVA

ZHVA

ZHVA

30 34Thursday, August 09, 2018

30 34Thursday, August 09, 2018

30 34Thursday, August 09, 2018

1

1A

1A

1A

5

4

3

2

1

Gemini lake Power Tree

110mil

D D

25mil

+VCC_VCCGI

840 mil

+VNN

200 mil

PU4

PU3

31

LAN RTL8411B-CG

55mil

+1.35VSUS

420 mil

PU15

RTC

20mil

CN13

40mil

U13

TPM

5mil

105mil

+3VPCU

310mil

PU5

LED

10mil

+3V_S5

70mil

C C

PU7

U14

Touch Pad

10mil

EC

12mil

U16

Audio codec

10mil

CN15

U15

WIFI

30mil

CN9

+3V

190mil

PU7

CRD RTL8411B-CG

35mil

U13

VIN

600mil

LCDVCC

60mil

U19

M.2 SSD

20mil

CN5

eMMC

B B

+1.8V_S5

40mil

+1.8V

20mil

PQ4PU12

15mil

U2

+1.05V

110mil

PU8

+1.24V_S5

55mil

PU10

+1.5V

20mil

305mil

A A

+5VPCU

590mil

PU11

+5V

240mil

+5V_S5

350mil

5

4

PU14

PU13

PU13

3

Codec

40mil

USBPWR1

100mil

U15

U7

panel boost

40mil

USBPWR2

100mil

+5V_FAN1

20mil

PU1 CN10 CN12 CN16 CN3

HDD+M2_PWR

60mil

+5V_ODD

60mil

TP_PWR

10mil

+TYPEC_VBUS_C

150mil

U18 U3

Size Do cument Number Rev

Size Do cument Number Rev

Size Do cument Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

ZHVA

ZHVA

POWER TREE

POWER TREE

POWER TREE

1

ZHVA

31 34Thursday, August 09, 201 8

31 34Thursday, August 09, 201 8

31 34Thursday, August 09, 201 8

1A

1A

1A

5

4

3

2

1

VCCRTC
R

TC_RST#

32

VCC_RTC_3P3V power to RTC_TEST# > 9 ms

D D

Adaptor in

From PWM to EC

POWER BUTTON

RTC_TEST#

+3VPCU/+5VPCU

SYS_HWPG

NBSWON#

S5_ON

+5V_S5/+3V_S5

From EC to PWM

VNN_ON

+VNN

Delay S5_ON (6.34ms)

C C

HWPG_1.8V_S5

From EC to SOC
From EC to SOC

From SOC to EC
From EC to PWM

B B

+1.8V_S5

1.24V_S5

+

RSMRST#

DNBSWON#

SUSB#/SUSC#

SUSON

+1.35VSUS

MAINON

30ms

120ms

10ms

10ms

+1.05V/+1.5V

HWPG_1.5V

From PW to MOS

HWPG

MAIND

>100ms

+1.8V

From EC to SOC

C_PWROK

E

boot up by SVID

+VCC_VCCGI

PLTRST#

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Power on Sequence

Power on Sequence

Power on Sequence

PROJECT :

1

ZHVA

ZHVA

ZHVA

32 34Thursday, August 09, 2018

32 34Thursday, August 09, 2018

32 34Thursday, August 09, 2018

1A

1A

1A

1

2

3

4

5

6

7

8

34

A A

B B

C C

D D

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

1

2

3

4

5

6

Date: Sheet

7

PROJECT :

Power status table

Power status table

Power status table

ZHVA

ZHVA

ZHVA

34 34Thursday, August 09, 2018

34 34Thursday, August 09, 2018

34 34Thursday, August 09, 2018

8

1A

1A

1A

of