Quanta ZHVA Schematic
5
4
3
2
1
ZHVA Virgo_GL UMA(11.6")
01
D D
C C
B B
3.3V EC code
SPI ROM(8Mb)
PAGE 13
Thermal senser
PAGE 16
Keyboard
A A
PAGE 15
Intel Gemini Lake Platform Block Diagram
DDR4 2333
Memory down
2 Channel 1Rx16
PAGE 10,11
SATA - 1st HDD
Package : 9.5 (mm)
Power :
PAGE 17
SATA SSD
M.2 NGFF
PAGE 17
1.8V BIOS+TXE
SPI ROM(64Mb)
PAGE 5
Touch Pad
PAGE 15
PS2
Embedded Controller
IT8987
Power :
Package : LQPF128
Size : 14 x 14 (mm)
Speaker
Combo Jack
Headphone + MIC
Digital -MIC
SATA0 6GB/s
SATA0 6GB/s
SPI Interface
PAGE 13
PAGE 19
PAGE 19
PAGE 19
DDR4
LPC Interface
Port0
Port1
I2C
32.768KHz
PAGE 6
Intel Gemini Lake
Package : FCBG 1170
Size : 24 x 31 (mm)
PAGE 2~9
Audio Codec
ALC255
Power :
Package : QFN
Size : 6 x 6 (mm)
Azalia
PAGE 19
PCIE2
19.2MHz
PAGE 4
DDI 0
x8
SMBus
USB 2.0 Interface
USB 3.0
Port0
USB3.0 Port
PAGE 18
PCIE3
PCIE Gen 2 x 1 Lane
M.2 NGFF
WLAN / BT Combo
PAGE 21
LAN sub board
RTL8111H
PAGE 22
EMMC 5.0
SDIN7DP4
32GB/64GB
Port0
Port4
HDMI Conn
eDP
P17
G sensor/sensor HUB
Port2
USB2.0 Port
PAGE 17
USB Board
DDR4 1.2V(RT8231BGQW)
PAGE 14
PAGE 14
Touch Screen
PAGE 20
Port5 Port6
Charger(BQ24737RGRR)
PAGE 26
SYSTEM 3V/5V
(SY8286B&8288)
+1.05V (M5671RE1U)
Camera
PAGE 14PAGE 14
PAGE 23
PAGE 24
PAGE 25
Card reader
RTS5170
USB Board
Port7
PAGE 18
+VCCGI (RT3601EAGQW)
PAGE 26
+VNN (RT3601EAGQW)
PAGE 27
Thermal / Discharge
PAGE 30
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Thursday, August 09, 2018
Date: Sheet of
Thursday, August 09, 2018
Date: Sheet of
Thursday, August 09, 2018
5
4
3
2
Date: Sheet of
PROJECT :
Intel Block Diagram
Intel Block Diagram
Intel Block Diagram
ZHVA
ZHVA
ZHVA
1A
1A
1A
341
341
1
341
5
4
GLK ULT (DDR4)
3
2
+1.2VSUS_ Q[7]
1
02
M_A_DQ[63:0][10]
D D
C C
B B
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
BJ36
BK37
BJ35
BL36
BJ39
BL40
BJ40
BK41
BA35
AY33
BA33
AY35
BA37
AY37
AY39
BA39
BL34
BL30
BJ29
BK29
BJ33
BK33
BJ34
BJ30
BD29
BF29
BH29
BF33
BC29
BD33
BF35
BH35
AR53
AP55
AP53
AN54
AU54
AV53
AV55
AW53
AU51
AU48
AU49
BA46
BA48
BA49
BA51
AR51
AY55
BA54
BA53
AY53
BC53
BD55
BE54
BD53
AN43
AN44
AR48
AU41
AU43
AN41
AN39
AU44
U23A
MEM_CH0_DQ 40
MEM_CH0_DQ 41
MEM_CH0_DQ 42
MEM_CH0_DQ 43
MEM_CH0_DQ 44
MEM_CH0_DQ 45
MEM_CH0_DQ 46
MEM_CH0_DQ 47
MEM_CH0_DQ 32
MEM_CH0_DQ 33
MEM_CH0_DQ 34
MEM_CH0_DQ 35
MEM_CH0_DQ 36
MEM_CH0_DQ 37
MEM_CH0_DQ 38
MEM_CH0_DQ 39
MEM_CH0_DQ 56
MEM_CH0_DQ 57
MEM_CH0_DQ 58
MEM_CH0_DQ 59
MEM_CH0_DQ 60
MEM_CH0_DQ 61
MEM_CH0_DQ 62
MEM_CH0_DQ 63
MEM_CH0_DQ 48
MEM_CH0_DQ 49
MEM_CH0_DQ 50
MEM_CH0_DQ 51
MEM_CH0_DQ 52
MEM_CH0_DQ 53
MEM_CH0_DQ 54
MEM_CH0_DQ 55
MEM_CH0_DQ 0
MEM_CH0_DQ 1
MEM_CH0_DQ 2
MEM_CH0_DQ 3
MEM_CH0_DQ 4
MEM_CH0_DQ 5
MEM_CH0_DQ 6
MEM_CH0_DQ 7
MEM_CH0_DQ 8
MEM_CH0_DQ 9
MEM_CH0_DQ 10
MEM_CH0_DQ 11
MEM_CH0_DQ 12
MEM_CH0_DQ 13
MEM_CH0_DQ 14
MEM_CH0_DQ 15
MEM_CH0_DQ 16
MEM_CH0_DQ 17
MEM_CH0_DQ 18
MEM_CH0_DQ 19
MEM_CH0_DQ 20
MEM_CH0_DQ 21
MEM_CH0_DQ 22
MEM_CH0_DQ 23
MEM_CH0_DQ 24
MEM_CH0_DQ 25
MEM_CH0_DQ 26
MEM_CH0_DQ 27
MEM_CH0_DQ 28
MEM_CH0_DQ 29
MEM_CH0_DQ 30
MEM_CH0_DQ 31
DDR4_LP3_LP4DDR4_LP3_LP4
MEM_CH0_DQ S0_P
MEM_CH0_DQ S0
MEM_CH0_DQ S1_P
MEM_CH0_DQ S1
MEM_CH0_DQ S2_P
MEM_CH0_DQ S2
MEM_CH0_DQ S3_P
MEM_CH0_DQ S3
MEM_CH0_DQ S4_P
MEM_CH0_DQ S4
MEM_CH0_DQ S5_P
MEM_CH0_DQ S5
MEM_CH0_DQ S6_P
MEM_CH0_DQ S6
MEM_CH0_DQ S7_P
MEM_CH0_DQ S7
DDR0
1 OF 13
NCTF1
NCTF2
NCTF3
MEM_CH0_O DT1
MEM_CH0_CS 1
NCTF4
MEM_CH0_O DT0
MEM_CH0_CS 0
MEM_CH0_CK E1
MEM_CH0_CK E0
MEM_CH0_CL K0_P
MEM_CH0_CL K0
MEM_CH0_CL K1_P
MEM_CH0_CL K1
MEM_CH0_MA 0
MEM_CH0_MA 1
MEM_CH0_MA 2
MEM_CH0_MA 10
MEM_CH0_MA 13
MEM_CH0_MA 16
MEM_CH0_B A1
MEM_CH0_B A0
MEM_CH0_B G1
MEM_CH0_A CT
MEM_CH0_MA 3
MEM_CH0_MA 4
MEM_CH0_MA 5
MEM_CH0_MA 6
MEM_CH0_MA 7
MEM_CH0_MA 8
MEM_CH0_MA 9
MEM_CH0_MA 11
MEM_CH0_MA 12
MEM_CH0_MA 14
MEM_CH0_MA 15
MEM_CH0_B G0
MEM_CH0_V REFDQ
MEM_CH0_V REFCA
M_A_DQSP 0
AT53
M_A_DQSN0
AT55
M_A_DQSP 1
AW49
M_A_DQSN1
AW48
M_A_DQSP 2
BC54
M_A_DQSN2
BB53
M_A_DQSP 3
AR41
M_A_DQSN3
AR43
M_A_DQSP 4
AV37
M_A_DQSN4
AV35
M_A_DQSP 5
BL38
M_A_DQSN5
BJ38
M_A_DQSP 6
BF31
M_A_DQSN6
BD31
M_A_DQSP 7
BJ32
M_A_DQSN7
BK31
BG54
BH54
BJ42
BF39
BK43
BL44
M_A_ODT0
BD39
M_A_CS#0
BJ43
BF54
M_A_CKE0
BF55
M_A_CLK0
BE49
M_A_CLK0 #
BE51
BC49
BC48
M_A_A0
BD45
M_A_A1
BH50
M_A_A2
BH47
M_A_A10
BF45
M_A_A13
BH43
M_A_A16
BD41
M_A_BA#1
BH51
M_A_BA#0
BD43
M_A_BG#1
BF43
M_A_ACT#
BF41
M_A_A3
BG52
M_A_A4
BK45
M_A_A5
BJ46
M_A_A6
BJ44
M_A_A7
BJ47
M_A_A8
BJ45
M_A_A9
BK47
M_A_A11
BJ51
M_A_A12
BJ52
M_A_A14
BJ48
M_A_A15
BJ50
M_A_BG#0
BL50
M0_VREF_DQ
AY31
AV29
R142 *0_5%_4
Default no stuff
M_B_DQ[63:0][11]
M_A_DQSP 0 [10]
M_A_DQSN0 [10]
M_A_DQSP 1 [10]
M_A_DQSN1 [10]
M_A_DQSP 2 [10]
M_A_DQSN2 [10]
M_A_DQSP 3 [10]
M_A_DQSN3 [10]
M_A_DQSP 4 [10]
M_A_DQSN4 [10]
M_A_DQSP 5 [10]
M_A_DQSN5 [10]
M_A_DQSP 6 [10]
M_A_DQSN6 [10]
M_A_DQSP 7 [10]
M_A_DQSN7 [10]
M_A_CS#0 [10]
M_A_CKE0 [10]
M_A_CLK0 [10]
M_A_CLK0 # [10]
M_A_A0 [10]
M_A_A1 [10]
M_A_A2 [10]
M_A_A10 [10]
M_A_A13 [10]
M_A_A16 [10]
M_A_BA#1 [10]
M_A_BA#0 [10]
M_A_BG#1 [10]
M_A_ACT# [10]
M_A_A3 [10]
M_A_A4 [10]
M_A_A5 [10]
M_A_A6 [10]
M_A_A7 [10]
M_A_A8 [10]
M_A_A9 [10]
M_A_A11 [10]
M_A_A12 [10]
M_A_A14 [10]
M_A_A15 [10]
M_A_BG#0 [10]
TP5
+VREF_CA_CPU [10]
VREF trace must be at least
20 mils wide and space
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
AN15
AN17
AU12
AN12
AN13
AU13
AU15
BA10
BJ26
BL26
BJ27
BK27
BJ23
BK23
BJ22
BL22
BD27
BF27
BH27
BC27
BH21
BF23
BD23
BF21
BK19
BJ20
BL20
BJ21
BJ17
BJ16
BK15
BL16
BA21
AY23
BA23
BA17
AY21
AY17
AY19
BA19
AY3
BD3
BD1
BC3
AY1
BA3
BA2
BE2
AR8
AP3
AU2
AV3
AW3
AN2
AP1
AR3
AV1
AR5
BA8
AU7
AU5
BA5
BA7
AU8
U23B
MEM_CH1_DQ 40
MEM_CH1_DQ 41
MEM_CH1_DQ 42
MEM_CH1_DQ 43
MEM_CH1_DQ 44
MEM_CH1_DQ 45
MEM_CH1_DQ 46
MEM_CH1_DQ 47
MEM_CH1_DQ 32
MEM_CH1_DQ 33
MEM_CH1_DQ 34
MEM_CH1_DQ 35
MEM_CH1_DQ 36
MEM_CH1_DQ 37
MEM_CH1_DQ 38
MEM_CH1_DQ 39
MEM_CH1_DQ 56
MEM_CH1_DQ 57
MEM_CH1_DQ 58
MEM_CH1_DQ 59
MEM_CH1_DQ 60
MEM_CH1_DQ 61
MEM_CH1_DQ 62
MEM_CH1_DQ 63
MEM_CH1_DQ 48
MEM_CH1_DQ 49
MEM_CH1_DQ 50
MEM_CH1_DQ 51
MEM_CH1_DQ 52
MEM_CH1_DQ 53
MEM_CH1_DQ 54
MEM_CH1_DQ 55
MEM_CH1_DQ 0
MEM_CH1_DQ 1
MEM_CH1_DQ 2
MEM_CH1_DQ 3
MEM_CH1_DQ 4
MEM_CH1_DQ 5
MEM_CH1_DQ 6
MEM_CH1_DQ 7
MEM_CH1_DQ 8
MEM_CH1_DQ 9
MEM_CH1_DQ 10
MEM_CH1_DQ 11
MEM_CH1_DQ 12
MEM_CH1_DQ 13
MEM_CH1_DQ 14
MEM_CH1_DQ 15
MEM_CH1_DQ 16
MEM_CH1_DQ 17
MEM_CH1_DQ 18
MEM_CH1_DQ 19
MEM_CH1_DQ 20
MEM_CH1_DQ 21
MEM_CH1_DQ 22
MEM_CH1_DQ 23
MEM_CH1_DQ 24
MEM_CH1_DQ 25
MEM_CH1_DQ 26
MEM_CH1_DQ 27
MEM_CH1_DQ 28
MEM_CH1_DQ 29
MEM_CH1_DQ 30
MEM_CH1_DQ 31
R156 *0_5%_4
DDR4_LP3_LP4DDR4_LP3_LP4
MEM_CH1_DQ S0_P
MEM_CH1_DQ S0
MEM_CH1_DQ S1_P
MEM_CH1_DQ S1
MEM_CH1_DQ S2_P
MEM_CH1_DQ S2
MEM_CH1_DQ S3_P
MEM_CH1_DQ S3
MEM_CH1_DQ S4_P
MEM_CH1_DQ S4
MEM_CH1_DQ S5_P
MEM_CH1_DQ S5
MEM_CH1_DQ S6_P
MEM_CH1_DQ S6
MEM_CH1_DQ S7_P
MEM_CH1_DQ S7
DDR1
2 OF 13
M_A_ODT0_MDM_A_ODT0
M_A_ODT0_MD [10]
MEM_CH1_MA 0
MEM_CH1_MA 1
MEM_CH1_MA 2
MEM_CH1_MA 3
MEM_CH1_MA 10
MEM_CH1_MA 13
MEM_CH1_MA 16
MEM_CH1_B A0
MEM_CH1_B A1
MEM_CH1_B G1
MEM_CH1_A CT
MEM_CH1_MA 11
MEM_CH1_MA 12
MEM_CH1_MA 14
MEM_CH1_MA 15
MEM_CH1_B G0
MEM_CH1_MA 4
MEM_CH1_MA 5
MEM_CH1_MA 6
MEM_CH1_MA 7
MEM_CH1_MA 8
MEM_CH1_MA 9
MEM_CH1_CL K0_P
MEM_CH1_CL K0
MEM_CH1_CL K1_P
MEM_CH1_CL K1
NCTF3
NCTF4
NCTF1
MEM_CH1_CS 1
MEM_CH1_O DT1
MEM_CH1_CS 0
MEM_CH1_O DT0
NCTF2
MEM_CH1_CK E0
MEM_CH1_CK E1
MEM_CH0_RCOMP
MEM_CH1_RE SET
MEM_CH1_RCOMP
MEM_CH1_V REFCA
MEM_CH1_V REFDQ
MEM_CH0_RE SET
MA_DRAMRST# MB_DRAMRST#
M_B_DQSP 0
BJ24
M_B_DQSN0
BK25
M_B_DQSP 1
BD25
M_B_DQSN1
BF25
M_B_DQSP 2
BL18
M_B_DQSN2
BJ18
M_B_DQSP 3
AV19
M_B_DQSN3
AV21
M_B_DQSP 4
AR13
M_B_DQSN4
AR15
M_B_DQSP 5
BB3
M_B_DQSN5
BC2
M_B_DQSP 6
AW7
M_B_DQSN6
AW8
M_B_DQSP 7
AT1
M_B_DQSN7
AT3
M_B_A0
BH9
M_B_A1
BC13
M_B_A2
BD11
M_B_A3
BD13
M_B_A10
BF11
M_B_A13
BE5
M_B_A16
BH5
M_B_BA#0
BH6
M_B_BA#1
BF13
M_B_BG#1
BG4
M_B_ACT#
BE7
M_B_A11
BK11
M_B_A12
BJ12
M_B_A14
BK9
M_B_A15
BJ11
M_B_BG#0
BJ10
M_B_A4
BJ4
M_B_A5
BL6
M_B_A6
BJ5
M_B_A7
BJ9
M_B_A8
BJ6
M_B_A9
BJ8
M_B_CLK0
BF17
M_B_CLK0 #
BD17
BF15
BH15
BJ13
BL12
BF1
BF2
BC7
M_B_CS#0
BH2
M_B_ODT0
BC8
R154 *0_5%_4
BG2
M_B_CKE0
BK13
BJ14
MEM_CH0_RCOMP
AY29
MB_DRAMRST#
BC15
MEM_CH1_RCOMP
AY27
M1_VREF_CA
AV27
AY25
BC43
M1_VREF_DQ
MA_DRAMRST#
R141 *0_5%_4
TP4
Default no stuff
colsed to CPU pin within 100 mils
C125
*1000p/5 0V_4
R137
*10_5%_4
M_B_DQSP 0 [11]
M_B_DQSN0 [11]
M_B_DQSP 1 [11]
M_B_DQSN1 [11]
M_B_DQSP 2 [11]
M_B_DQSN2 [11]
M_B_DQSP 3 [11]
M_B_DQSN3 [11]
M_B_DQSP 4 [11]
M_B_DQSN4 [11]
M_B_DQSP 5 [11]
M_B_DQSN5 [11]
M_B_DQSP 6 [11]
M_B_DQSN6 [11]
M_B_DQSP 7 [11]
M_B_DQSN7 [11]
M_B_A0 [11]
M_B_A1 [11]
M_B_A2 [11]
M_B_A3 [11]
M_B_A10 [11]
M_B_A13 [11]
M_B_A16 [11]
M_B_BA#0 [11]
M_B_BA#1 [11]
M_B_BG#1 [11]
M_B_ACT# [11]
M_B_A11 [11]
M_B_A12 [11]
M_B_A14 [11]
M_B_A15 [11]
M_B_BG#0 [11]
M_B_A4 [11]
M_B_A5 [11]
M_B_A6 [11]
M_B_A7 [11]
M_B_A8 [11]
M_B_A9 [11]
M_B_CLK0 [11]
M_B_CLK0 # [11]
R151 110_1%_ 4
R150 110_1%_ 4
VREF trace must be at least
20 mils wide and space
C129
*1000p/5 0V_4
R148
*10_5%_4
M_B_CS#0 [11]
M_B_ODT0_MD [11]
M_B_CKE0 [11]
R179 , R183 close to CPU
Trace length < 500 mils
Trace width=15 mils
Trace spacing = 20mils
+VREFDQ_SB_M3 [11]
DRAMRST-MEMORY DOWN
+1.2VSUS_ Q +1.2VSUS_ Q
A A
5
CPU
MA_DRAMRST# MB_DRAMRST#
Trace length < 4500 mils, 50 ohm impendence
Trace spacing = 15mils
R144
1K_1%_4
R152 *S_4
4
C132
*0.1u/16V_4
MEMORY DOWN
M_A_DRAMRS T# [10]
Trace length < 4500 mils, 50 ohm impendence
Trace spacing = 15mils
CPU
3
R153
1K_1%_4
R149 *S_4
C134
*0.1u/16V_4
MEMORY DOWN
M_B_DRAMRS T# [11]
2
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Nu mber Rev
Size Document Nu mber Rev
Size Document Nu mber Rev
Date: Sheet of
Thursday, Augu st 09, 2018
Date: Sheet of
Thursday, Augu st 09, 2018
Date: Sheet of
Thursday, Augu st 09, 2018
PROJECT :
GLK(MEMORY)
GLK(MEMORY)
GLK(MEMORY)
ZHVA
ZHVA
ZHVA
2 34
2 34
1
2 34
1A
1A
1A
5
Gemini lake (SATA , ODD, CLK ,USB,PCIE)
U23D
<1000mil
PCIE_CLK_RCOMP
PCIE_TXP2_LAN_C
PCIE_TXN2_LAN_C
L10
PCIE_REF_CLK_RCOMP
R12
PCIE_CLKOUT0P
R10
PCIE_CLKOUT0N
N7
PCIE_CLKOUT1P
N5
PCIE_CLKOUT1N
R7
PCIE_CLKOUT2P
R5
PCIE_CLKOUT2N
N8
PCIE_CLKOUT3P
N10
PCIE_CLKOUT3N
E2
PCIE_P0_TXP
F2
PCIE_P0_TXN
G7
PCIE_P0_RXP
H6
PCIE_P0_RXN
A7
PCIE_P1_TXP
C7
PCIE_P1_TXN
D4
PCIE_P1_RXP
E5
PCIE_P1_RXN
C9
PCIE_P2_TXP
B9
PCIE_P2_TXN
E7
PCIE_P2_RXP
F6
PCIE_P2_RXN
A46
PCIE_CLKREQ0
C45
PCIE_CLKREQ1
B45
PCIE_CLKREQ2
C44
PCIE_CLKREQ3
F47
PCIE_WAKE0
D47
PCIE_WAKE1
F45
PCIE_WAKE2
D50
PCIE_WAKE3
J3
SATA_P0_TXP
J2
SATA_P0_TXN
J7
SATA_P0_RXP
J5
SATA_P0_RXN
SATA/USB3
PCIe
USB3
PCIe/USB3
SSIC
SATA
USB2
4 OF 13
R225 56_1%_4
D D
LAN
2.5~12 inch(Gen1)
C C
LAN
WLAN4~12 inch
PCIE_TXP2_LAN[22]
PCIE_TXN2_LAN[22]
PCIE_RXP2_LAN[22]
PCIE_RXN2_LAN[22]
CLK_PCIE_LAN_REQ#[22]
PCIE_CLKREQ_WLAN#[21]
SATA HDD
CLK_PCIE_LANP[22]
CLK_PCIE_LANN[22]
CLK_PCIE_WLANP[21]
CLK_PCIE_WLANN[21]
C421 0.1u/16V_4
C422 0.1u/16V_4
SATA_TXP0[17]
SATA_TXN0[17]
SATA_RXP0[17]
SATA_RXN0[17]
CLK_PCIE_SSD_REQ#
PCIE_CLKREQ1
CLK_PCIE_LAN_REQ#
PCIE_CLKREQ_WLAN#
PCIE_LAN_WAKE#
PCIE_WLAN_WAKE#
4
SATA_P1_USB3_P5_TXP
SATA_P1_USB3_P5_TXN
SATA_P1_USB3_P5_RXP
SATA_P1_USB3_P5_RXN
USB3_P0_TXP
USB3_P0_TXN
USB3_P0_RXP
USB3_P0_RXN
USB3_P1_TXP
USB3_P1_TXN
USB3_P1_RXP
USB3_P1_RXN
PCIE_P3_USB3_P4_TXP
PCIE_P3_USB3_P4_TXN
PCIE_P3_USB3_P4_RXP
PCIE_P3_USB3_P4_RXN
PCIE_P4_USB3_P3_TXP
PCIE_P4_USB3_P3_TXN
PCIE_P4_USB3_P3_RXP
PCIE_P4_USB3_P3_RXN
PCIE_P5_USB3_P2_TXP
PCIE_P5_USB3_P2_TXN
PCIE_P5_USB3_P2_RXP
PCIE_P5_USB3_P2_RXN
PCIE2_USB3_SATA3_RCOMP
PCIE2_USB3_SATA3_RCOMP_P
USB2_DP0
USB2_DN0
USB2_DP1
USB2_DN1
USB2_DP2
USB2_DN2
USB2_DP3
USB2_DN3
USB2_DP4
USB2_DN4
USB2_DP5
USB2_DN5
USB2_DP6
USB2_DN6
USB2_DP7
USB2_DN7
USB2_RCOMP
USB2_DUALROLE
USB2_VBUS_SNS
USB2_OC0
USB2_OC1
NC1
NC2
NC5
NC4
NC3
H1
H2
H4
G5
B15
C15
F15
D15
C14
A14
J11
H11
PCIE_TXP3_WLAN_C
C10
PCIE_TXN3_WLAN_C
A10
H9
F9
C11
B11
D11
F11
B13
C13
F13
D13
PCIE_RCOMPN
C5
PCIE_RCOMPP
C6
AA10
AA8
W13
W12
U15
U7
U5
N2
N3
L2
L3
R13
R15
M1
M3
R2
R3
P1
P3
U8
U10
U12
USBCOMP
USB_OTG_ID
V1
USB_VBUS_SNS
V3
USB_OC0#
U54
USB_OC1#
U53
SATA_TXP1 [17]
SATA_TXN1 [17]
SATA_RXP1 [ 17]
SATA_RXN1 [17]
USB30_TX0+ [18]
USB30_TX0- [18]
USB30_RX0+ [18]
USB30_RX0- [18]
C426 0.1u/16V_4
C428 0.1u/16V_4
R245 100_1%_4
USBP0+ [ 18]
USBP0- [ 18]
USBP2+ [ 18]
USBP2- [ 18]
USBP4+ [ 21]
USBP4- [ 21]
USBP_TOUCH+ [14]
USBP_TOUCH- [14]
USBP6_CCD+ [14]
USBP6_CCD- [14]
USB_CAR7+ [18]
USB_CAR7- [18]
R196 113_1%_4
R205 *10K_5%_4
R206 *10K_5%_4
M.2 SATA SSD
SB3.0
U
USB2 .0
BT
Touch Panel
CCD
Cardreader
R223 *0_5%_4
R270 *0_5%_4
PCIE_TXP3_WLAN [21]
PCIE_TXN3_WLAN [21]
PCIE_RXP3_WLAN [21]
PCIE_RXN3_WLAN [21]
USB_OC0# [9]
USB_OC1# [18]
3
+1.8V_S5
Near CPU
I2C4_SDA
R2212K_1%_4
I2C4_SCL
R2182K_1%_4
I2C5_SDA
R4722K_1%_4
I2C5_SCL
R4672K_1%_4
I2C6_SDA
R2902K_1%_4
I2C6_SCL
R2912K_1%_4
I2C standard/fast mode
I2C total lenght is about 4500 mils = 4.5inchs
Cb = 4.5*5pF +7pF = 29.5pF
PU resistor = 2K ohm
：
2~8 inchUSB3.0
I2C4_SCL[15]
I2C4_SDA[15]
I2C5_SCL[20]
I2C5_SDA[20]
I2C6_SCL[20]
I2C6_SDA[20]
SMB_SOC_CLK[9]
TP18
R246 33_5%_4
TP17
R248 150_1%_4
33 ohm resistor must be placed at a distance <2000mi
Minimum Length forBRI/RGI signals is3000 mils /76.2 mm
WLAN
2.5~12 inch(Gen1)
CNVI_BRI_DT[9]
3~12 inch
+1.8V_S5
+1.8V
Touch PAD
Sensor HUB
R
eseve for Gsensor
I2C4_SCL
I2C4_SDA
I2C5_SCL
I2C5_SDA
I2C6_SCL
I2C6_SDA
SMB1ALERT#
SMB_SOC_CLK
SMB_SOC_DAT
CNVI_BRI_DT_CCNVI_BRI_DT
CNVI_RF_RESET#
CNVI_WT_RCOMP
U49
U51
U46
U48
AA39
AA41
R44
R43
R49
R51
C50
A50
C48
C47
B47
C46
A26
B27
C27
H29
H31
M31
P31
D29
F29
F35
D35
J35
H35
L31
J31
J29
F19
H17
J17
D19
D17
F17
F33
U23I
SIO_I2C0_SCL
SIO_I2C0_SDA
SIO_I2C1_SCL
SIO_I2C1_SDA
SIO_I2C2_SCL
SIO_I2C2_SDA
SIO_I2C3_SCL
SIO_I2C3_SDA
SIO_I2C4_SCL
SIO_I2C4_SDA
SIO_I2C5_SCL
SIO_I2C5_SDA
SIO_I2C6_SCL
SIO_I2C6_SDA
SIO_I2C7_SCL
SIO_I2C7_SDA
SMB_ALERT
SMB_CLK
SMB_DATA
CNV_WGR_CLK_P
CNV_WGR_CLK
CNV_WGR_D0_P
CNV_WGR_D0
CNV_WGR_D1_P
CNV_WGR_D1
CNV_WT_CLK_P
CNV_WT_CLK
CNV_WT_D0_P
CNV_WT_D0
CNV_WT_D1_P
CNV_WT_D1
CLKIN_XTAL_LCP
XTAL_CLKREQ
CNV_BRI_DT
CNV_BRI_RSP
CNV_RGI_DT
CNV_RGI_RSP
CNV_RF_RESET
CNV_WT_RCOMP
ls/50.8 mm from SoC
SMBUS set 3.3V
2
LPSS_I2C
LPSS SMBus
CNVI
LPSS_SPI
LPSS_UART
6 OF 13
+1.8V_S5[4,5,6,7,9,12,15,21,22,23,27,29]
+1.8V[4,14,17,20,22,29,30]
+3V_S5[6,7,12,13,15,22,24,26,29]
+3V[4,5,12,13,14,16,17,18,19,20,21,22,24,25,26,27,28,29,30]
SIO_UART0_TXD
SIO_UART0_RXD
SIO_UART0_RTS
SIO_UART0_CTS
SIO_UART2_TXD
SIO_UART2_RXD
SIO_UART2_RTS
SIO_UART2_CTS
1
SIO_SPI_0_CLK
SIO_SPI_0_TXD
SIO_SPI_0_RXD
SIO_SPI_0_FS0
SIO_SPI_0_FS1
SIO_SPI_2_CLK
SIO_SPI_2_TXD
SIO_SPI_2_RXD
SIO_SPI_2_FS0
SIO_SPI_2_FS1
SIO_SPI_2_FS2
03
M39
J37
L39
L37
J39
M37
M33
P35
P33
P37
L35
N54
P53
N53
M55
L54
M53
K53
L53
GPIO_65
GPIO_64
GPIO_65
GPIO_64
GPIO_79 [9]
GPIO_83 [9]
GPIO_80 [9]
GPIO_81 [9,21]
GPIO_84 [9]
GPIO_89 [9]
GPIO_85 [9]
GPIO_86 [9]
GPIO_87 [9]
GPIO_61 [9]
TP49
GPIO_62 [9]
TP51
GPIO_65 [9]
GPIO_66 [9]
GPIO_67 [21]
TP53
TP50
B B
USB_VBUS_SNS
3
+1.8V_S5
R457
*10K_5%_4
R452
*S_4
SoC
+1.8V_S5
R299 *1K_1%_4
R298 *1K_1%_4
R287 *1K_1%_4
+1.8V_S5
R519 10K_5%_4
R280 *10K_5%_4
R273 *10K_5%_4
R520 10K_5%_4
+3V_S5
USB_OTG_ID
R461 *0_5%_4
4
R261
*10K_5%_4
PCIE_LAN_WAKE#
PCIE_WLAN_WAKE#
A A
+1.8V_S5
R512
*10K_5%_4
5
PCIE_LAN_WAKE# [22]
PCIE_WLAN_WAKE# [12]
PCIE_CLKREQ1
PCIE_CLKREQ_WLAN#
CLK_PCIE_LAN_REQ#
CLK_PCIE_SSD_REQ#
level shift already PU
SMBus
SMB_SOC_CLK
SMB_SOC_DAT
2
+3V_S5
R297
1K_1%_4
GML S5
SMB_SOC_DAT
SMB_SOC_CLK
SMB1ALERT#
R296
1K_1%_4
+3V_S5
R286 *1K_1%_4
SMB1ALERT#
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
ZHVA
PROJECT :
ZHVA
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
GLK(PCIE/USB/SATA/CNVI)
GLK(PCIE/USB/SATA/CNVI)
GLK(PCIE/USB/SATA/CNVI)
Date: Sheet of
Thursday, August 09, 2018
Date: Sheet of
Thursday, August 09, 2018
Date: Sheet of
Thursday, August 09, 2018
1
ZHVA
3 34
3 34
3 34
1A
1A
1A
5
4
3
2
1
Gemini lake (DISPLAY,eDP)
U23C
AC12
AC10
AE12
AE13
AC15
AC17
AE10
AH1
AH3
AE2
AE3
AJ2
AJ3
AG2
AG3
C39
B43
C43
AA2
AA3
Y3
Y1
AD1
AD3
AC2
AC3
AC7
AC5
C42
A42
C38
AE8
AE5
AE7
W17
W15
B39
B41
C40
C41
AA5
AA7
DDI0_TXP_0
DDI0_TXN_0
DDI0_TXP_1
DDI0_TXN_1
DDI0_TXP_2
DDI0_TXN_2
DDI0_TXP_3
DDI0_TXN_3
DDI0_AUXP
DDI0_AUXN
DDI0_HPD
DDI0_DDC_SCL
DDI0_DDC_SDA
DDI1_TXP_0
DDI1_TXN_0
DDI1_TXP_1
DDI1_TXN_1
DDI1_TXP_2
DDI1_TXN_2
DDI1_TXP_3
DDI1_TXN_3
DDI1_AUXP
DDI1_AUXN
DDI1_DDC_SCL
DDI1_DDC_SDA
DDI1_HPD
EDP_TXP_0
EDP_TXN_0
EDP_TXP_1
EDP_TXN_1
EDP_TXP_2
EDP_TXN_2
EDP_TXP_3
EDP_TXN_3
EDP_AUXP
EDP_AUXN
EDP_HPD
PNL0_BKLCTL
PNL0_BKLTEN
PNL0_VDDEN
EDP_RCOMP_P
EDP_RCOMP
DDI0/DDI_B
MDSI
DDI1/DDI_C
eDP/DDI_A
3 OF 13
INT_HDMITX2P[14]
INT_HDMITX2N[14]
INT_HDMITX1P[14]
D D
Max 7.5 inch
HDMI
HDMI_HPD
+3V
TypeC_HPD#
INT_EDP_HPD#
C C
HDMI HPD
B B
R568 *10K_5%_4
R7 10K_5%_4
INT_HDMI_HPD#
RUC002N05GZT116
eDP Panel
<10000 mil
+1.8V
change to 3.3V
R284
10K_5%_4
3
Q13
HDMI_HPD_R
2
1
R309 *S_4
R300
100K_1%_4
INT_HDMITX1N[14]
INT_HDMITX0P[14]
INT_HDMITX0N[14]
INT_HDMICLK+[14]
INT_HDMICLK-[14]
INT_HDMI_HPD#
HDMI_DDCCLK_SW[14]
HDMI_DDCDATA_SW[14]
TypeC_HPD#
EDP_TXP0[14]
EDP_TXN0[14]
EDP_TXP1[14]
EDP_TXN1[14]
EDP_AUXP[14]
EDP_AUXN[14]
INT_EDP_HPD#[14]
R453 100_1%_4
HDMI_HPD_C [14]
INT_EDP_HPD#
PCH_BKLTCTL
PCH_BKLTEN
PCH_VDDEN
EDP_RCOMP_P
EDP_RCOMP_N
MDSI_A_CLKP
MDSI_A_CLKN
MDSI_C_CLKP
MDSI_C_CLKN
MDSI_A_DP_0
MDSI_A_DN_0
MDSI_A_DP_1
MDSI_A_DN_1
MDSI_A_DP_2
MDSI_A_DN_2
MDSI_A_DP_3
MDSI_A_DN_3
MDSI_C_DP_0
MDSI_C_DN_0
MDSI_C_DP_1
MDSI_C_DN_1
MDSI_C_DP_2
MDSI_C_DN_2
MDSI_C_DP_3
MDSI_C_DN_3
MIPI_I2C_SCL
MIPI_I2C_SDA
MDSI_C_TE
MDSI_A_TE
MDSI_RCOMP
AL2
AM3
AG13
AG12
AN5
AN7
AJ15
AJ17
AJ7
AJ5
AJ10
AJ12
AG15
AG17
AG8
AG10
AG7
AG5
AE15
AE17
R53
R54
T53
SOC_OVRIDE
T55
GPIO_42 HW Strap
MDSI_RCOMP
AL5
GPIO_43 [9]
R167 150_1%_4
+1.8V_S5[3,5,6,7,9,12,15,21,22,23,27,29]
+1.8V[3,14,17,20,22,29,30]
+3V[5,12,13,14,16,17,18,19,20,21,22,24,25,26,27,28,29,30]
04
+3V +3V +3V
R202
*10K_5%_4
PCH_VDDEN PCH_BKLTEN PCH_BKLTCTL
A A
5
Q8A
R208 *S_4
R192
*10K_5%_4
61
34
2
*SSM6N43FU
Q8B
5
EDP_VDD_EN [14] PCH_BLON [14] PCH_BRIGHT [14]
R295
*10K_5%_4
5
Q15A
R294 *S_4
R306
*10K_5%_4
61
34
2
*SSM6N43FU
Q15B
4
R212
*10K_5%_4
5
Q9A
R224 *S_4
R203
*10K_5%_4
34
61
2
*SSM6N43FU
Q9B
3
Override
Flash Descriptor Override (SOC_OVRIDE)
0 = Normal Override(Normal operation)
1 = Override
3
2
ME_WR#[13]
2
1
Q34
2N7002K
+1.8V_S5
R488
2.2K_5%_4
SOC_OVRIDE
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Thursday, August 09, 2018
Date: Sheet of
Thursday, August 09, 2018
Date: Sheet of
Thursday, August 09, 2018
Date: Sheet
PROJECT :
GLK (HDMI/eDP)
GLK (HDMI/eDP)
GLK (HDMI/eDP)
ZHVA
ZHVA
ZHVA
of
4 34
4 34
1
4 34
1A
1A
1A
5
?
?
U23J
C26
AVS_I2S0_MCLK
B25
AVS_I2S0_BCLK
C25
AVS_I2S0_WS_SYNC
HDA_BCLK_R
HDA_SYNC_R
HDA_SDO_R
HDA_RST#_R
EMMC_RCOMP
CLK_PCI_LPC
C432
*18P/50V_4
C24
AVS_I2S0_SDI
B23
AVS_I2S0_SDO
M23
AVS_I2S1_MCLK
L21
AVS_I2S1_BCLK
J21
AVS_I2S1_WS_SYNC
M21
AVS_I2S1_SDI
P23
AVS_I2S1_SDO
A22
AVS_HDA_BCLK
C23
AVS_HDA_WS_SYNC
B21
AVS_HDA_SDI
C22
AVS_HDA_SDO
C21
AVS_HDA_RST
B19
AVS_DMIC_CLK_A1
C20
AVS_DMIC_CLK_B1
C19
AVS_DMIC_DATA_1
C18
AVS_DMIC_CLK_AB2
A18
AVS_DMIC_DATA_2
J13
EMMC_CLK
L15
EMMC_RCLK
M19
EMMC_D0
H19
EMMC_D1
J19
EMMC_D2
P17
EMMC_D3
P19
EMMC_D4
J15
EMMC_D5
L17
EMMC_D6
M17
EMMC_D7
M13
EMMC_CMD
U44
EMMC_RST
G51
EMMC_PWR_EN
L13
EMMC_RCOMP
GLK_SOC_RVP1
?
AUDIO-AVS
eMMC
EMMC_CLK[17]
EMMC_RCLK[17]
EMMC_DATA_0[17]
EMMC_DATA_1[17]
EMMC_DATA_2[17]
EMMC_DATA_3[17]
EMMC_DATA_4[17]
EMMC_DATA_5[17]
EMMC_DATA_6[17]
EMMC_DATA_7[17]
EMMC_CMD[17]
EMMC_RST[17]
C431
*33p/50V_4
GPIO_159[9]
GPIO_163[9]
GPIO_164[9]
R513 33_5%_4
R530 33_5%_4
R549 33_5%_4
R548 33_5%_4
GPIO_172[9]
GPIO_174[9]
GPIO_175[9]
R226 200_1%_4
D D
HDA
AZ_CODEC_BITCLK[19]
AZ_CODEC_SYNC[19]
AZ_CODEC_SDIN0[9,19]
AZ_CODEC_SDOUT[19]
AZ_CODEC_RST#[19]
C C
AZ_CODEC_BITCLK
4
Gemini lake (EMMC/LPC/I2C/GPIO/HDA)
L29
SDCARD
LPC/eSPI
LPC set 3.3V
FAST_SPI
7 OF 13
XDP_TCK
XDP_TRST#
XDP_PREQ#
XDP_PRDY#
XDP_TMS
XDP_TDO
XDP_TDI
R425 51_5%_4
R433 51_5%_4
R444 51_5%_4
R445 169_1%_4
R426 51_5%_4
R428 169_1%_4
R446 51_5%_4
SPI is 1.8V
+1.8V_S5
SDCARD_CLK
SDCARD_D0
SDCARD_D1
SDCARD_D2
SDCARD_D3
SDCARD_CMD
SDCARD_CD
SDCARD_LVL_W P
SDCARD_PWR_D WN
SDCARD_RCOMP
LPC_CLKOUT0
LPC_CLKOUT1
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_CLKRUN
LPC_FRAME
LPC_SERIRQ
FST_SPI_CLK
FST_SPI_MOSI_IO0
FST_SPI_MISO_IO1
FST_SPI_IO2
FST_SPI_IO3
FST_SPI_CS0
FST_SPI_CS1
M29
P29
M27
P27
L27
L25
P25
L23
J25
C37
A38
A34
C34
B35
C35
C33
B33
B37
B29
B31
C30
A30
C29
C31
C32
LPC_CLKOUT0
LPC_CLKOUT1
LPC_LAD0_R
LPC_LAD1_R
LPC_LAD2_R
LPC_LAD3_R
LPC_CLKRUN#_R
LPC_LFRAME#_R
SOC_SERIRQ_R
PCH_SPI_CLK
PCH_SPI_SI
PCH_SPI_SO
PCH_SPI_IO2
PCH_SPI_IO3
PCH_SPI_CS0#
PCH_SPI_CS1#
3
R532 22_5%_4
R516 DBG@22_5%_4
R538 22_5%_4
R551 22_5%_4
R531 22_5%_4
R514 22_5%_4
R521 22_5%_4
R537 22_5%_4
R515 22_5%_4
PCH_SPI_CLK [2 1]
PCH_SPI_SI [21 ]
PCH_SPI_SO [21]
TP20
TP44
TP48
TP46
TP45
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_PRDY#
XDP_PREQ#
CLK_PCI_EC [13]
CLK_PCI_LPC [21]
LPC_LAD0 [13,21]
LPC_LAD1 [13,21]
LPC_LAD2 [13,21]
LPC_LAD3 [13,21]
CLKRUN# [13]
LPC_LFRAME# [13,21]
SOC_SERIRQ [12]
2
+1.8V_S5[3,4,6,7,9,12,15,21,22,23,27,29]
+1.8V[3,4,14,17,20,22,29,30]
U23H
AH53
JTAGX
AM53
JTAG_TCK
AJ54
JTAG_TDI
AL53
JTAG_TDO
AL54
JTAG_TMS
AK53
JTAG_TRST
AH55
JTAG_PRDY
AJ53
JTAG_PREQ
JTAG
ITP
GPIO
5 OF 13
+3V_S5[3,6,7,12,13,15,22,24,26,29]
GPIO_8
GPIO_9
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_15
GPIO_16
GPIO_17
GPIO_18
GPIO_19
GPIO_20
GPIO_21
GPIO_22
GPIO_23
GPIO_24
GPIO_25
GPIO_26
GPIO_27
GPIO_28
GPIO_29
GPIO_30
GPIO_31
GPIO_32
GPIO_33
GPIO_34
GPIO_35
GPIO_36
GPIO_37
GPIO_38
GPIO_39
GPIO_40
GPIO_41
GPIO_105
GPIO_134
GPIO_135
GPIO_136
GPIO_137
GPIO_138
GPIO_139
GPIO_140
GPIO_141
GPIO_142
GPIO_143
GPIO_144
GPIO_145
GPIO_146
GPIO_210
GPIO_212
GPIO_213
GPIO_214
AG53
AG54
AE54
AE53
AD55
AD53
AC54
AC53
AB53
AA49
AC48
AC46
AE51
AE49
AC51
AC49
AA51
AA46
AE41
AE39
AE46
AE44
AC41
AC39
AC44
RF_KILL#_R
AC43
AA44
AA54
AA53
Y55
R491 *S_4
Y53
W54
W53
IERR
V53
GPIO_105
L46
H45
H47
R194 *0_5%_4
L43
R193 *0_5%_4
M43
SATA_GP0
H37
PCH_PCIERST#
H43
GPIO_140
J43
GPIO_141
D43
GPIO_142
F43
H41
F39
L41
AC_PRESENT
F41
H27
U43
U41
U39
Board_ID0
Board_ID1
Board_ID2
Board_ID3
Board_ID4
Board_ID5
Board_ID6
Board_ID7
Board_ID8
RAM_ID0
RAM_ID1
RAM_ID2
RAM_ID3
RAM_ID4
RAM_ID5
eMMC_ID0
eMMC_ID1
eMMC_ID2
1
05
TP6
TP8
TP7
SPKR [19]
R492 *S_4
GPIO_27 [9]
GPIO_28 [9]
TP14
TP21
TP10
PIRQ# [21]
PCH_TPD_INT# [15]
SENSOR_HUB_INT1# [20]
SIO_EXT_SCI# [13]
SOC_PCI_SERR#
GSENSOR_INT [12]
ISH_MODE1 [20]
ISH_MODE2 [20]
set to 3.3V
HW strap ID
Board_ID0
B B
Board_ID1
Board_ID2
Board_ID3
Board_ID4
Board_ID5
Board_ID6
Board_ID7
B
oard_ID8
RAM_ID0
RAM_ID1
RAM_ID2
RAM_ID5
0
A A
0
0
0
eMMC_ID1eMMC_ID2
0
0
0 1
1 1
Strap pin Description
0 = Non Touch Screen
1 = Touch Screen
0 = with EMMC
1 = without EMMC <HDD only>
0 = M.2 SATA SSD
1 = M.2 PCIE SSD
0 = none G sensor
1 = G sensor
0 = none TPM
1 = TPM
0 = With SATA Port 0 Connector
1 = Without SATA Port 0 Connector
0 = With SATA Port 1 Connector
1 = Without SATA Port 1 Connector
0 = Convertible model (360’)
1 = Clamshell model
Reserve
0 = Single chanel (A)
1 = Dual chanel(A&B)
0 = Channel A On board RAM 2GB
1 = Channel A On board RAM 4GB
0 = Channel B On board RAM 2GB
1 = Channel B On board RAM 4GB
Vender
RAM_ID3RAM_ID4
0
0
Miron
0
1
Hynix
01
Samsung
1 1
eMMC_ID0
0
1
0
1
Sandisk 32G/64G/128GB
1
Vender
Samsung 32/64GB
Hynix 32/64GB
Kingston 32/64GB
Toshiba 128GB
0
0
10
BOARD ID SETTING
R455 *10K_5%_4
R442 10K_5%_4
R470 10K_5%_4
R459 *10K_5%_4
R468 *10K_5%_4
R476 10K_5%_4
R484 10K_5%_4
R475 10K_5%_4
R489 10K_5%_4
R437 *10K_5%_4
R479 *10K_5%_4
R480 *10K_5%_4
R434 10K_5%_4
R436 10K_5%_4
R478 10K_5%_4
R435 *10K_5%_4
R438 *10K_5%_4
R481 10K_5%_4
5
Board_ID0
Board_ID1
Board_ID2
Board_ID3
Board_ID4
Board_ID5
Board_ID6
Board_ID7
Board_ID8
RAM_ID0
RAM_ID1
RAM_ID2
RAM_ID3
RAM_ID4
RAM_ID5
eMMC_ID0
eMMC_ID1
eMMC_ID2
R456 10K_5%_4
R443 *10K_5%_4
R471 *10K_5%_4
R460 10K_5%_4
R469 10K_5%_4
R477 *10K_5%_4
R485 *10K_5%_4
R482 *10K_5%_4
R490 *10K_5%_4
R450 10K_5%_4
R464 10K_5%_4
R465 10K_5%_4
R447 *10K_5%_4
R449 *10K_5%_4
R463 *10K_5%_4
R448 10K_5%_4
R451 10K_5%_4
R466 *10K_5%_4
+1.8V_S5
Board ID
RAM ID
eMMC ID
4
R552
R567 33_5%_4
R539 33_5%_4
R556 33_5%_4
R546 33_5%_4
3.3K_5%_4
SPI_CLK_A
PCH_SPI_CS0#
PCH_SPI_CLK
PCH_SPI_SI
PCH_SPI_SO
PCH_SPI_IO2
Series resistance 33R is recommended
for signalsasper PDG Table 27-2
+1.8V_S5
R569
*3.3K_5%_4
U28
1
CE#
6
SCLK
5
SI
2
SO
3
IO2
GD25LB64CSIGR
+1.8V_S5
C440
R565
0.1u/16V_4
3.3K_5%_4
8
VCC
7
IO3
4
VSS
3
R566 33_5%_4
PCH_SPI_IO3
GPIO_142
GPIO_140
Q36A
*10K_5%_4
R557
*10K_5%_4
34
5
R555 *S_4
BOARD ID SETTING
R172
34
5
Q7A
R184 *0_5%_4
+3V
61
2
Q36B
*2N7002KDW
2
R571
10K_5%_4
+3V
61
R176
*10K_5%_4
Q7B
*SSM6N43FU
2
NGFF_SATA_DET# [17 ]
SATA_DEVSLP0 [17]
GPIO_141
R293
*10K_5%_4
5
Q14A
R292 *S_4
SOC_PCI_SERR#
PCH_TPD_INT#
SIO_EXT_SCI#
SENSOR_HUB_INT1#
RF_KILL#_R
GPIO_105
R487 *10K_5%_4
R175 10K_5%_4
R486 10K_5%_4
R191 *GS@10K_5%_4
R190 *10K_5%_4
R220 *10K_5%_4
+3V
R301
10K_5%_4
34
61
2
Q14B
*SSM6N43FU
SATA_DEVSLP1 [17]
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number R
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROJECT :
GLK (GPIO/LPC/I2C/HDA)
GLK (GPIO/LPC/I2C/HDA)
GLK (GPIO/LPC/I2C/HDA)
Thursday, August 09, 2018
Thursday, August 09, 2018
Thursday, August 09, 2018
1
set to PU
ZHVA
ZHVA
ZHVA
+1.8V_S5
+1.8V_S5
5 34
5 34
5 34
ev
1A
1A
1A
5
PMU set to 3.3V
+3V_S5 +1.8V_S5
R274
R233
0_5%_4
*0_5%_4
D D
R239 *10K_5%_4
R232 100K_1%_4
R262 10K_5%_4
R535 *1K_1%_4
R281 *10K_5%_4
R278 *20K_1%_4
R285 20K_1%_4
R250 *10K_5%_4
R180 *1K_1%_4
+1.8V_S5
check list use 20k
R517 1K_1%_4
C C
R260 *1K_1%_4
R247 *100K_1%_4
R534 100K_1%_4
C248 *0.1u/16V_4
C234 *0.1u/16V_4
C240 *0.1u/16V_4
C244 0.1u/16V_4
C199 *0.1u/16V_4
PCH_SUSPWRDNACK
PCH_BATLOW#
PMU_RSTBTN#
PLTRST#
PMU_SLP_S0#
SOC_RSMRST#
CORE_PWROK
PCH_SUS_STAT#
DNBSWON#
H_PROCHOT#
THRMTRIP#_R
CORE_PWROK
PLTRST#
CORE_PWROK
PCH_BATLOW#
SOC_RSMRST#
PMU_RSTBTN#
DNBSWON#
PLTRST#[13,17,21,22]
DNBSWON#[13]
PMU_SLP_S0#[21]
SUSB#[13]
SUSC#[13]
PCH_SUSPWRDNACK[13]
TP22
TP16
H_CPU_SVIDCLK[27,28]
H_CPU_SVIDDAT[27,28]
VR_SVID_ALERT#_VCORE[27,28]
TP23
TP19
4
TP12
TP13
PLTRST#
DNBSWON#
PMU_SLP_S0#
SUSB#
SUSC#
PCH_SUSPWRDNACK
PCH_BATLOW#
PMU_RSTBTN#
PMU_SUSCLK
PCH_SUS_STAT#
R523 *S_4
R525 *S_4
R524 220_5%_4
H_CPU_SVIDDAT
VR_SVID_ALERT#_VCORE
H_CPU_SVIDCLK
SVID_CLK#_R
SVID_DAT#_R
SVID_ALERT#_R
3
Gemini lake (PMU/PMIC/RTC)
U23E
R46
PMC_I2C_SCL
R48
PMC_I2C_SDA
L48
PMC_SPI_CLK
N48
PMC_SPI_FS0
N44
PMC_SPI_FS1
L49
PMC_SPI_FS2
L51
PMC_SPI_RXD
N49
PMC_SPI_TXD
D54
PMU_PLTRST
E54
PMU_PWRBTN
C52
PMU_SLP_S0
D51
PMU_SLP_S3
J49
PMU_SLP_S4
F54
SUSPWRDNACK
J48
PMU_BATLOW
C51
PMU_RSTBTN
G49
PMU_SUSCLK
E52
SUS_STAT
F55
SVID0_CLK
G53
SVID0_DATA
G54
SVID0_ALERT_B
D1
DEBUG_PORT_A0
D2
DEBUG_PORT_A1
A54
NC2
C54
NC11
+1.05V
R543
240_1%_4
PMU set 3.3V
R542
68_5%_4
R541
*160_1%_4
PMC
PMU
SVID
Misc
C437
1000p/50V_4
iCLK
RTC
Thermal
Spare
8 OF 13
THRMTRIP#_R
RTC is 3.3V
2
OSC_CLK_OUT_0
OSC_CLK_OUT_1
OSCIN
OSCOUT
RTC_X1
RTC_X2
VCC_RTC_EXTPAD
INTRUDER
SOC_PWROK
RSM_RST
RTC_TEST
RTC_RST
THERMTRIP
1.8V
PROCHOT
NC15
NC16
SKTOCC
NC14
NC10
NC17
R231
*10K_5%_4
61
Q10B
*PJT138K
GND
NC3
NC4
NC1
NC5
NC6
NC7
NC8
NC9
5
B17
C17
XTAL192_IN
U2
XTAL192_OUT
T1
RTC_X1
D23
RTC_X2
F23
BVCCRTC_EXTPAD
J23
H25
INTRUDER#
CORE_PWROK
D25
SOC_RSMRST#
F27
RTC_TEST#
F25
RTC_RST#
D27
THRMTRIP#_R
J53
H_PROCHOT#
J54
AG43
H53
AG44
H55
A4
BH1
A53
F37
BL2
BL3
BL53
C2
C3
R41
+3VPCU
R243
*10K_5%_4
34
Q10A
*PJT138K
THERMTRIP#
C216 0.1u/16V_4
R266 330K_5%_4
R277 *S_4
R242 *S_4
RTC_RST#
2
+1.8V_S5[3,4,5,7,9,12,15,21,22,23,27,29]
+1.05V[7,25,27,28]
+3V_S5[3,7,12,13,15,22,24,26,29]
+3VPCU[13,14,15,16,19,21,22,23,24,29]
+3V_RTC[7,13]
+3V_RTC
EC_PWROK [13]
THERMTRIP# [13]
H_PROCHOT# [13,23,27,28]
colsed to CPU pin within 100 mils
C271
1000p/50V_4
R303
10_5%_4
EC reset RTC
CLR_CMOS[13]
SOC_RSMRST# [12]
colsed to CPU pin within 100 mils
C188
1000p/50V_4
R174
10_5%_4
CORE_PWROK
Q11
3
1
2
PMZ370UNE
1
colsed to CPU pin within 100 mils
C266
1000p/50V_4
R288
10_5%_4
RTC_TEST#
RTC_RST#
Q16
3
1
2
PMZ370UNE
06
B B
RTC Circuitry (RTC)
R2 1K_1%_4
Trace width = 20 mils
12
CN1
+ -
AAA-BAT-046-K03
A A
5
4
34
ML1220 Coin type
HL03001031 [VDE] 17mAH
A
AHL03001057 [DBV] 17mAH
+3VPCU
+3V_RTC_1
1 3
Q1 EJ@PMST3904
20MIL
2
+3V_RTC
D1
2
1
R3 EJ@4.7K_5%_4
BAT54CW
R302
3
20K_1%_4
R1
20K_1%_4
VCCRTC_4VCCRTC_3VCCRTC_2
3
+3V_RTC
Trace width = 20 mils
C270
1u/6.3V_4
C1
1u/6.3V_4
R4 EJ@4.7K_5%_4
EJ@68.1K_1%_4
EJ@150K_1%_4
RTC_RST#
RTC_TEST#
+5V_S5
R5
R6
19.2MHZ/20ppm
RTC Clock 32.768KHz (CPU)
Trace length < 1000 mils
2
C404 15p/50V_4
Y2
C402 15p/50V_4
C430 18p/50V_4
C429 18p/50V_4
XTAL192_OUT
4
3
R483
200K_1%_4
1
2
XTAL192_IN
CH01006JB08 -> 10p
CH01506JB06 -> 15p
CH-6806TB01 -> 6.8p
12
Y3
32.768KHZ/20ppm
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
RTC_X1
R518
10M_5%_4
RTC_X2
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
GLK (PMU/PMIC/SMB/RTC)
GLK (PMU/PMIC/SMB/RTC)
GLK (PMU/PMIC/SMB/RTC)
Thursday, August 09, 2018
Thursday, August 09, 2018
Thursday, August 09, 2018
ZHVA
ZHVA
ZHVA
6 34
6 34
1
6 34
1A
1A
1A
5
EDGE DECAPS
FOR EXPOSED POWER PLANES
BACK side cap
4
Gemini (POWER)
3
2
+3V_S5[3,6,12,13,15,22,24,26,29]
+1.24V_S5[29]
+1.8V_S5[3,4,5,6,9,12,15,21,22,23,27,29]
+3V_RTC[6,13]
+1.2VSUS_Q[2]
+VNN[28]
+VCC_VCCGI[27]
+1.05V[6,25,27,28]
1
07
VNN1
VNN2
VNN3
VNN4
VNN5
VNN6
VNN7
VNN8
VNN9
VNN10
VNN11
VNN12
VNN13
VNN14
VNN15
VNN16
NC1
NC2
NC3
NC4
AF35
AG27
AG28
AG36
AG46
AG48
AJ27
AJ28
AJ46
AJ48
AL27
AL28
AL48
AL49
AM27
AM28
AJ49
AW44
BH55
AG41
AG39
AJ41
AJ43
BL54
AC33
AC35
AE33
AE35
AE36
AE38
AF27
AF28
AF36
AF38
+VCCRAM_1P05_FHV0
AG51
+VCCRAM_1P05_FHV1
AG49
+VCCRAM_1P05_FUSE
AJ51
AA36
AA38
AC36
AC38
Y36
Y38
P15
AJ21
U17
AG21
T18
T20
V18
V20
Y18
Y20
+VNN+VCC_VCCGI
+VCCRAM_1P05
VRTC_3P3
C231
*1u/6.3V_4
C220
*1u/6.3V_4
C162
1u/6.3V_4
C148
*1u/6.3V_4
R230 *S_6
C230
1u/6.3V_4
C211
*1u/6.3V_4
R418 *S_6
C172
1u/6.3V_4
C150
*1u/6.3V_4
VCCGI_SENSE [27]
VCCGISS_SENSE [27]
VNN_SENSE [28]
VNNSS_SENSE [28]
+1.05V
R171 *S_6
R166 *S_6
R164 *S_6
+3V_RTC
C205
1u/6.3V_4C191 1u/6.3V_4
C153
1u/6.3V_4
C171
*22u/6.3V_6
C180
1u/6.3V_4
*47u/10V_8
C390
22u/6.3V_6
C147
1u/6.3V_4
C143
C389
*1u/6.3V_4
R217 *S_6
C217
22u/6.3V_6
2
22u/6.3V_6
C127
*47u/10V_8
+VCCRAM_1P05+VCCRAM_1P05
C185
*1u/6.3V_4
C159
1u/6.3V_4
C388
*1u/6.3V_4
+3V_S5
C140
22u/6.3V_6
C133
*47u/10V_8
C193
C178
1u/6.3V_4
C186
1u/6.3V_4
C164
22u/6.3V_6
C154
*47u/10V_8
C137
*47u/10V_8
C391
22u/6.3V_6
C170
*22u/6.3V_6
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Thursday, August 09, 2018
Date: Sheet of
Thursday, August 09, 2018
Date: Sheet of
Thursday, August 09, 2018
PROJECT :
GLK (POWER)
GLK (POWER)
GLK (POWER)
ZHVA
ZHVA
ZHVA
1
7 34
7 34
7 34
1A
1A
1A
U23F
AA28
VCC_VCG1
AA29
VCC_VCG2
AA31
D D
C229
0.1u/16V_4
C169
22u/6.3V_6
22u/6.3V_6
C419
*22u/6.3V_6
C246
C C
+1.2VSUS
R139 *S_8
R132 *S_8
B B
+1.24V_S5
A A
*47u/10V_8
+1.2VSUS_Q
+1.2VSUS_Q
C126
22u/6.3V_6
R183 *S_6
R189 *S_6
R161 *S_6
R424 *S_6
R169 *S_6
R187 *S_6
R170 *S_6
C215 *47u/10V_8
C212 1u/6.3V_4
C146 22u/6.3V_6
5
22u/6.3V_6
C206
0.1u/16V_4
C410
C399
*22u/6.3V_6
C263
*47u/10V_8
*47u/10V_8
C131
22u/6.3V_6
+1.05V
R155 *S_8
+1.8V_S5
+VDD2_1P24_MPHY
+VDD2_1P24_AUD_ISH
+VDD2_1P24_DSI_CSI
+VDD2_1P24_GLML
+VDD2_1P24_PLL
+VDD2_1P24_VNNAON
+VDD2_1P24_USB2
+VDD2_1P24_AUD_ISH
+VDD2_1P24_DSI_CSI
C201
1u/6.3V_4
C237
1u/6.3V_4
C198
22u/6.3V_6
C249
*22u/6.3V_6
C416
*47u/10V_8
C418
C128
R251 *S_6
C214
1u/6.3V_4
C173
1u/6.3V_4
C423
22u/6.3V_6
C397
*22u/6.3V_6
C245
*47u/10V_8
C265
*47u/10V_8
C130
22u/6.3V_6
C221
C204
1u/6.3V_4
1u/6.3V_4
C181
C175
1u/6.3V_4
1u/6.3V_4
C401
C182
22u/6.3V_6
22u/6.3V_6
C398
C396
*22u/6.3V_6
*22u/6.3V_6
C232
C241
*1u/6.3V_4
*1u/6.3V_4
C247
C264
*47u/10V_8
*47u/10V_8
C156
C151
1u/6.3V_4
1u/6.3V_4
C157
C155
1u/6.3V_4
1u/6.3V_4
C251
C252
*1u/6.3V_4
*1u/6.3V_4
C194 47u/6.3V_6
C196 47u/6.3V_6
C195 22u/6.3V_6
C190 1u/6.3V_4
C184 1u/6.3V_4
C394 22u/6.3V_6
C395 22u/6.3V_6
C152 1u/6.3V_4
C163 22u/6.3V_6
C166 1u/6.3V_4
C167 1u/6.3V_4
C179 1u/6.3V_4
C177 *22u/6.3V_6
22u/6.3V_6
+VCCIOA
+VDD2_1P24_MPHY
+VDD2_1P24_PLL
+VDD2_1P24_USB2
C213
1u/6.3V_4
C209
1u/6.3V_4
C222
C168
*22u/6.3V_6
C161
*1u/6.3V_4
C417
*47u/10V_8
C139
0.1u/16V_4
C158
1u/6.3V_4
C253
1u/6.3V_4
C202
1u/6.3V_4
C210
1u/6.3V_4
C192
22u/6.3V_6
C411
*22u/6.3V_6
C233
*1u/6.3V_4
C223
*47u/10V_8
C142
0.1u/16V_4
C141
22u/6.3V_6
C208
1u/6.3V_4
4
VCC_VCG3
AA33
VCC_VCG4
AC28
VCC_VCG5
AC31
VCC_VCG6
AE28
VCC_VCG7
AE29
VCC_VCG8
AE31
VCC_VCG9
AF31
VCC_VCG10
AF33
VCC_VCG11
AG31
VCC_VCG12
AG33
VCC_VCG13
AJ31
VCC_VCG14
AJ33
VCC_VCG15
AJ35
VCC_VCG16
AL31
VCC_VCG17
AL33
VCC_VCG18
AL35
VCC_VCG19
AM33
VCC_VCG20
AM35
VCC_VCG21
AM36
VCC_VCG22
D31
VCC_VCG23
D33
VCC_VCG24
D37
VCC_VCG25
D39
VCC_VCG26
P39
VCC_VCG27
P41
VCC_VCG28
T28
VCC_VCG29
T29
VCC_VCG30
T31
VCC_VCG31
T33
VCC_VCG32
T35
VCC_VCG33
T36
VCC_VCG34
V28
VCC_VCG35
V29
VCC_VCG36
V31
VCC_VCG37
V33
VCC_VCG38
V35
VCC_VCG39
V36
VCC_VCG40
Y28
VCC_VCG41
Y29
VCC_VCG42
Y33
VCC_VCG43
Y35
VCC_VCG44
C138
0.1u/16V_4
C136
22u/6.3V_6
C174
22u/6.3V_6
1u/6.3V_4
+VDD2_1P24_MPHY
+VDD2_1P24_AUD_ISH
+VDD2_1P24_DSI_CSI
+VDD2_1P24_GLML+VDD2_1P24_GLML
+VDD2_1P24_PLL
+VDD2_1P24_VNNAON
+VDD2_1P24_USB2
C135
0.1u/16V_4
C145
2.2u/10V_4
C250
25A
AW12
AP18
AP21
AP36
AP38
AT18
AT20
AT21
AT35
AT36
AT38
BA13
BA15
BA25
BA31
BA41
BA43
AP25
AP31
AT25
AT27
AT28
AT29
AT31
AJ23
AG23
AC21
AE20
AE21
AF20
AF21
AC18
AC20
AL36
AL38
AP20
AM20
AL18
AM18
AA18
AA20
AG18
AJ20
T21
T23
T25
V21
V23
V25
U23G
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
3A
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VCCIOA1
VCCIOA2
VCCIOA3
VCCIOA4
VCCIOA5
VCCIOA6
VCCIOA7
VCC_1P8V_A3
VCC_1P8V_A4
VDD1(1.8V)
VCC_1P8V_A5
VCC_1P8V_A6
VCC_1P8V_A7
VCC_1P8V_A8
VCC_1P8V_A2
VCC_1P8V_A1
VDD2_1P2_MPHY1
VDD2_1P2_MPHY2
VDD2_1P2_MPHY3
VDD2_1P2_MPHY4
VDD2_1P2_MPHY5
VDD2_1P2_AUD1
VDD2_1P2_AUD2
VDD2_1P2_DSI_CSI
VDD2_1P2_GLM1
VDD2_1P2_GLM2
VDD2_1P2_GLM4
VDD2_1P2_GLM3
VDD2_1P2_PLL1
VDD2_1P2_PLL2
VDD2_1P2_VNNAON1
VDD2_1P2_VNNAON2
VDD2_1P2_USB2
VDD2_1P2_USB3
VDD2(1.2V)
9 OF 13
0.4A
3A
10 OF 13
4.5A
VCCRAM(1.05V)
RTC
0.15A
VDD3(3.3V)
3
A
4
VCC_VCG_SENSE
VSS_VCG_SENSE
VNN_SENSE
VNN_VSS_SENSE
VCCRAM_1P053
VCCRAM_1P054
VCCRAM_1P057
VCCRAM_1P058
VCCRAM_1P059
VCCRAM_1P0510
VCCRAM_1P0511
VCCRAM_1P0512
VCCRAM_1P0513
VCCRAM_1P0514
VCC_1P05_INT2
VCC_1P05_INT1
VCC_1P05_INT3
VCCRAM_1P051
VCCRAM_1P052
VCCRAM_1P055
VCCRAM_1P056
VCCRAM_1P0515
VCCRAM_1P0516
VCCRTC_3P3V
VCC_3P3V_A2
VCC_3P3V_A5
VCC_3P3V_A1
VCC_3P3V_A3
VCC_3P3V_A4
VCC_3P3V_A6
VCC_3P3V_A7
VCC_3P3V_A8
VCC_3P3V_A9
5
4
3
2
1
GLK ULT (GND)
08
D D
C C
B B
A12
A16
A20
A24
A28
A32
A36
A40
A44
A48
A51
AA12
AA13
AA15
AA17
AA21
AA23
AA25
AA27
AA35
AA43
AA48
AB1
AB3
AB55
AC8
AC13
AC23
AC25
AC27
AC29
AE18
AE23
AE25
AE27
AE43
AE48
AF1
AF3
AF4
AF6
AF8
AF9
AF11
AF12
AF14
AF16
AF18
AF23
AF25
AF29
AF40
AF42
U23K
A3
VSS6
A6
VSS13
VSS1
VSS2
VSS3
VSS4
VSS5
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS33
VSS28
VSS29
VSS30
VSS31
VSS32
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS49
VSS50
VSS61
VSS62
VSS63
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS51
VSS52
11 OF 13
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS64
VSS87
VSS65
VSS66
VSS67
VSS68
VSS77
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS78
VSS79
VSS80
VSS90
VSS97
VSS98
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS88
VSS89
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS108
VSS110
VSS107
VSS109
AF44
AF45
AF47
AF48
AF50
AF52
AF53
AF55
AG20
AL21
AG25
AG29
AG35
AG38
AJ8
AJ13
AJ18
AJ25
AJ29
AJ36
AJ38
AJ39
AJ44
AK1
AK3
AK55
AL3
AL7
AL8
AL10
AL12
AL13
AL15
AL17
AL20
AL25
AL29
AL39
AL41
AL43
AL44
AL46
AL51
AM1
AM21
AM23
AM25
AM29
AM31
AM38
AM55
AN3
AN8
AN10
AN46
AN48
AN49
AN51
AN53
AP23
AP27
AP28
AP29
AP33
AP35
AR2
AR7
AR10
AR12
AR17
AR39
AR44
AR46
AR49
AR54
AT23
AT33
AU3
AU10
AU28
AU46
AU53
AV15
AV17
AV23
AV25
AV31
AV33
AV39
AV41
AW2
AW5
AW10
AW28
AW46
AW51
AW54
AY13
AY15
AY28
AY41
AY43
B55
BA27
BA29
BB1
BB28
BB55
BC5
U23M
BC11
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_124
VSS_130
VSS_121
VSS_122
VSS_123
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_131
VSS_132
VSS_135
VSS_133
VSS_134
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_147
VSS_150
VSS_146
VSS_148
VSS_149
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
B2
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_178
12 OF 13
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_179
VSS_187
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_189
VSS_188
VSS_190
VSS_194
VSS_191
VSS_192
VSS_193
VSS_195
VSS_199
VSS_196
VSS_197
VSS_198
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_215
VSS_213
VSS_214
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
BC17
BC19
BC21
BC23
BC25
BC31
BC33
BC35
BC37
BC39
BC41
BC45
BC51
BD9
BD15
BD19
BD21
BD28
BD35
BD37
BD47
BE3
BE28
BE53
BF9
BF19
BF37
BF47
BG1
BG6
BG28
BG50
BG55
BH11
BH13
BH17
BH19
BH23
BH25
BH28
BH31
BH33
BH37
BH39
BH41
BH45
BJ2
BJ15
BJ19
BJ25
BJ28
BJ31
BJ37
BJ41
AL23
BJ54
BK1
BK17
BK21
BK35
BK39
BK55
BL10
BL14
BL24
BL28
BL32
BL42
BL46
BL48
BL51
C12
C16
C28
C36
D21
D28
D41
D45
D55
G28
H13
H15
H21
H23
H28
H33
H39
BL5
BL8
E28
E50
E55
F21
F31
J27
J33
J41
J45
U23L
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS17
VSS19
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS18
C1
VSS20
VSS21
VSS22
VSS23
VSS24
D6
VSS30
D9
VSS31
VSS25
VSS26
VSS27
VSS28
VSS29
VSS32
VSS33
VSS34
F1
VSS35
F4
VSS38
VSS36
VSS37
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
J8
VSS52
VSS47
VSS48
VSS49
VSS50
13 OF 13
VSS51
VSS53
VSS55
VSS54
VSS56
VSS59
VSS60
VSS61
VSS57
VSS58
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS74
VSS73
VSS75
VSS77
VSS78
VSS80
VSS81
VSS82
VSS84
VSS85
VSS93
VSS95
VSS96
VSS83
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS94
VSS97
VSS98
VSS99
VSS100
VSS101
VSS76
VSS79
J51
K1
K3
K28
K55
L5
L7
L8
L19
L33
M15
M25
M28
M35
M41
N12
N28
N46
N51
P21
P55
R8
R28
T27
T38
U13
V27
V38
V55
W2
W3
W5
W7
W8
W10
W39
W41
W43
W44
W46
W48
W49
W51
Y21
Y23
Y25
Y27
Y31
T3
U3
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Thursday, August 09, 2018
Date: Sheet of
Thursday, August 09, 2018
Date: Sheet of
5
4
3
2
Thursday, August 09, 2018
PROJECT :
GLK (GND)
GLK (GND)
GLK (GND)
ZHVA
ZHVA
ZHVA
1
8 34
8 34
8 34
1A
1A
1A
5
4
3
2
1
HARDWARE STRAPS
09
+1.8V_S5
Note: If platform is using eMMC as boot device, then
provide a pull down for this strap to disable
R500
R544
*4.7K_1%_4
R527
10K_5%_4
*4.7K_1%_4
R498
10K_5%_4
D D
C C
B B
R179
*4.7K_1%_4
R178
4.7K_1%_4
R186
4.7K_1%_4
R185
*10K_5%_4
R505
*4.7K_1%_4
R504
10K_5%_4
R234
*10K_5%_4
R219
4.7K_1%_4
R547
*10K_5%_4
R529
4.7K_1%_4
R510
*4.7K_1%_4
R503
10K_5%_4
USB_OC0#[3]
SMB_SOC_CLK[3]
GPIO_43[4]
GPIO_81[3,21]
GPIO_62[3]
GPIO_79[3]
GPIO_80[3]
GPIO_85[3]
GPIO_86[3]
GPIO_87[3]
GPIO_89[3]
GPIO_159[5]
GPIO_164[5]
R267
*4.7K_1%_4
R249
4.7K_1%_4
R554
*4.7K_1%_4
R553
4.7K_1%_4
R240
R545
*4.7K_1%_4
*4.7K_1%_4
R528
R241
4.7K_1%_4
*4.7K_1%_4
R496 10K_5%_4
R268 4.7K_1%_4
R198 *10K_5%_4
R497 10K_5%_4
R201 4.7K_1%_4
R269 10K_5%_4
R200 10K_5%_4
R213 10K_5%_4
R216 10K_5%_4
R204 10K_5%_4
R211 4.7K_1%_4
R197 4.7K_1%_4
R289 *10K_5%_4
+1.8V_S5
R215
*4.7K_1%_4
R214
4.7K_1%_4
GPIO_174 [5]
GPIO_61 [3]
GPIO_27 [5]
GPIO_28 [5]
GPIO_65 [3]
GPIO_163 [5]
AZ_CODEC_SDIN0 [5,19]
GPIO_66 [3]
GPIO_83 [3]
GPIO_172 [5]
GPIO_175 [5]
CNVI_BRI_DT [3]
GPIO_84 [3]
SPI.
Note: The default for A0 will be eSPI
due to a bug on LPC.
Hardware Strap Strap Description
PIO_174
GPIO_61
GPIO_27
GPIO_28
PIO_65
G
PIO_163
G
AZ_CODEC_SDIN0
GPIO_66
GPIO_83
GPIO_172 0 = Disable (default)
GPIO_42
GPIO_175
CNVI_BRI_DT
GPIO_84
VDD2 1.24V vs.1.20V select
0 = 1.2V(default)G
1 = 1.24V
Enable CSE(TXE3.0) ROM Bypass
0 = Disable bypass
1 = Enable Bypass
Allow eMMC as a boot source
0 = Disable
1 = Enable
Allow SPI as a boot source
0 = Disable
1 = Enable
Force DNX FW Load
0 = Do not force
1 = Force
SMBus 1.8V/3.3V mode select
0=buffers set to 3.3V
1=buffers set to 1.8V
PMU 1.8V/3.3V mode select
0=buffers set to 3.3V mode
1=buffers set to 1.8V mode
LPC No Re-Boot
0 = Disable (default)
1 = Enable
LPC 1.8V/3.3V mode select
0=buffers set to 3.3V mode
1=buffers set to 1.8V mode
SMbus No Re-Boot
1 = Enable
Top swap override
0 = Disable
1 = Enable
eSPI vs. LPC
0 = LPC mode (default)
1 = eSPI mode
eSPI Flash Sharing Mode:
0 = master attached flash sharing
(MAFS; default)
1 = slave attached flash sharing
(SAFS)
Allow SPI as a boot source
0 = Enable (default)
1 = Disable
Value
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
+1.8V_S5[3,4,5,6,7,12,15,21,22,23,27,29]
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Thursday, August 09, 2018
Date: Sheet of
Thursday, August 09, 2018
Date: Sheet of
5
4
3
2
Thursday, August 09, 2018
PROJECT :
HW STRAPS/XDP
HW STRAPS/XDP
HW STRAPS/XDP
ZHVA
ZHVA
ZHVA
9 34
9 34
1
9 34
1A
1A
1A
5
U3
M1
VREFCA
B1
VPP#B1
R9
VPP#R9
M_A_A0
P3
M_A_A1
M_A_A2
M_A_A3
M_A_A4 M_A_DQ62 M_A_DQ7
M_A_A5 M_A_DQ59 M_A_DQ0
M_A_A6 M_A_DQ61 M_A_DQ6
M_A_A7 M_A_DQ63 M_A_DQ1
M_A_A8 M_A_DQ56 M_A_DQ5
M_A_A9 M_A_DQ57 M_A_DQ2
M_A_A10 M_A_DQ60 M_A_DQ4
M_A_A11 M_A_DQ58 M_A_DQ3
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_A16
M_A_CLK0
M_A_CLK0#
M_A_CKE0
M_A_ODT0_MD
M_A_CS#0
M_A1_ZQ0 M_A2_ZQ0 M_A3_ZQ0 M_A4_ZQ0
A0
P7
A1
R3
A2
N7
A3
N3
A4
P8
A5
P2
A6
R8
A7
R2
A8
R7
A9
M3
A10/AP
T2
A11
M7
A12/BC
T8
A13
L2
WE_n/A14
M8
CAS_n/A15
L8
RAS_n/A16
M_A_BA#0
N2
BA0
M_A_BA#1
N8
BA1
M_A_BG#0
M2
BG0
K7
CK_t
K8
CK_c
K2
CKE
K3
ODT
L7
CS
G3
DQSL_t
B7
DQSU_t
F3
DQSL_c
A7
DQSU_c
E7
DML_n/DBIL_n
E2
DMU_n/DBIU_n
P1
RESET_n
F9
ZQ
N9
TEN
P9
ALERT_n
L3
ACT_n
T3
PAR
T7
NC
96-BALL
DDR4
R
AM@DDR4_96P
AKD5QGSTW00
M_A_CLK0
R106 *36_1%_4
M_A_CLK0#
R114 *36_1%_4
R68 5 1_1%_4
M_A_CLK0
In the middle of CPU and Double-T
M_A_CLK0#
C363 0.01u/50V_4
+1.2VSUS
C77 0.01u/ 50V_4
C358 0.01u/50V_4
C71 0.01u/ 50V_4
C87 0.01u/ 50V_4
C369 RAM@1u/6.3V_4
+2.5V_SUS
C104 RAM@1u/6.3V_4
C56 RA M@1u/6.3V_4
C59 RA M@1u/6.3V_4
C31 RA M@1u/6.3V_4
C95 RA M@1u/6.3V_4
C340 RAM@1u/6.3V_4
C115 RAM@1u/6.3V_4
C373 RAM@10u/6.3V_4
C374 RAM@10u/6.3V_4
C63 RA M@68p/50V_4
DB1 12/11, close memory
68p/50V_4
C30
+SMDDR_VREF_DQ1_M11
M_A_A[16:0][2]
+2.5V_SUS +2.5V_SUS
SI1, 0427 RF
D D
M_A_BA#0[2]
M_A_BA#1[2]
M_A_BG#0[2]
M_A_CLK0[2]
M_A_CLK0#[2]
M_A_CKE0[2]
M_A_ODT0_MD[2]
M_A_CS#0[2]
M_A_DQSP7[2] M_A_DQSP5[2] M_A_DQSP0[2]
M_A_DQSN7[2] M_A_DQSN5[2] M_A_DQSN0[2]
C C
M_A_DRAMRST#[2]
M_A_ACT#[2]
B B
M_A_BA#0
M_A_BA#1
M_A_BG#0 M_A_ALERT#
M_A_CKE0
M_A_CS#0
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_A16
M_A_ODT0_MD
M_A_ACT#
M_A_PARITY
M_A_BG#1
M_A_ODT0_MD M_A_PARITY
A A
R52 RA M@36_1%_4
R131 RAM@36_1%_4
R74 RA M@36_1%_4
R117 RAM@36_1%_4
R83 RA M@36_1%_4
R46 RA M@36_1%_4
R45 RA M@36_1%_4
R38 RA M@36_1%_4 C41 RA M@10u/6.3V_4
R71 RA M@36_1%_4
R75 RA M@36_1%_4
R398 RAM@36_1%_4
R396 RAM@36_1%_4
R400 RAM@36_1%_4
R397 RAM@36_1%_4
R399 RAM@36_1%_4
R120 RAM@36_1%_4
R401 RAM@36_1%_4
R78 RA M@36_1%_4
R29 RA M@36_1%_4
R116 RAM@36_1%_4
R88 RA M@36_1%_4
R110 RAM@36_1%_4
R136 *36_1%_4
R92 RA M@36_1%_4
R39 RA M@36_1%_4
R64 RA M@36_1%_4
R135
0_5%_4
R40
*0_5%_4
+VDDQ_VTT [11,26]
+1.2VSUS [7,11,26]
+2.5V_SUS [11,26]
M_A_DQSP7 M_A_DQSP5 M_A_DQSP0
M_A_DQSN7 M_A_DQSN5 M_A_DQSN0
+1.2VSUS +1.2VSUS +1.2VSUS +1.2VSUS
M_A_DRAMRST# M_A_DRAMRST# M_A_DRAMRST# M_A_DRAMRST#
R82 2 40_1%_4
M_A_ALERT#
M_A_ACT#
M_A_PARITY
DB1 12/11, close memory
+VDDQ_VTT
5
BYTE4_32-39
BYTE7_56-63
M_A_DQ36
G2
DQL0
M_A_DQ35
F7
DQL1
M_A_DQ37
H3
DQL2
M_A_DQ32
H7
DQL3
M_A_DQ39
H2
DQL4
M_A_DQ34
H8
DQL5
M_A_DQ38
J3
DQL6
M_A_DQ33
J7
DQL7
A3
DQU0
B8
DQU1
C3
DQU2
C7
DQU3
C2
DQU4
C8
DQU5
D3
DQU6
D7
DQU7
B3
VDD#B3
B9
VDD#B9
D1
VDD#D1
G7
VDD#G7
J1
VDD#J1
J9
VDD#J9
L1
VDD#L1
L9
VDD#L9
R1
VDD#R1
T9
VDD#T9
A1
VDDQ#A1
A9
VDDQ#A9
C1
VDDQ#C1
D9
VDDQ#D9
F2
VDDQ#F2
F8
VDDQ#F8
G1
VDDQ#G1
G9
VDDQ#G9
J2
VDDQ#J2
J8
VDDQ#J8
DB1 Option for 16Gbx16 die
B2
VSS#B2
E1
VSS#E1
E9
R89 0_5%_4
VSS#E9
G8
VSS#G8
K1
VSS#K1
K9
VSS#K9
M_A_BG#1_1 M_A_BG#1_2 M_A_BG#1 M_A_BG#1_3 M_A_BG#1 M_A_BG#1_4 M_A_BG#1
M9
VSS#M9
N1
VSS#N1
T1
VSS#T1
A2
VSSQ#A2
A8
VSSQ#A8
C9
VSSQ#C9
D2
VSSQ#D2
D8
VSSQ#D8
E3
VSSQ#E3
E8
VSSQ#E8
F1
VSSQ#F1
H1
VSSQ#H1
H9
VSSQ#H9
+VDDQ_VTT
+1.2VSUS
R111
75_1%_4
4
DB1 change
M_A_DQ36 [2]
M_A_DQ35 [2]
M_A_DQ37 [2]
M_A_DQ32 [2]
M_A_DQ39 [2]
M_A_DQ34 [2]
M_A_DQ38 [2]
M_A_DQ33 [2]
SI1, 0427 RF
M_A_DQ62 [2] M_A_DQ7 [2]
M_A_DQ59 [2] M_A_DQ0 [2]
M_A_DQ61 [2] M_A_DQ6 [2]
M_A_DQ63 [2] M_A_DQ1 [2]
M_A_DQ56 [2] M_A_DQ5 [2]
M_A_DQ57 [2] M_A_DQ2 [2]
M_A_DQ60 [2] M_A_DQ4 [2]
M_A_DQ58 [2] M_A_DQ3 [2]
+1.2VSUS +1.2VSUS +1.2VSUS +1.2VSUS
R62 *0_5%_4
+SMDDR_VREF_DQ1_M11 +SMDDR_VREF_DQ1_M11 +SMDDR_VREF_DQ1_M11
C114
M_A_BG#1 [2]
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_A16
M_A_BA#0
M_A_BA#1
M_A_BG#0
M_A_CLK0
M_A_CLK0#
M_A_CKE0
M_A_ODT0_MD
M_A_CS#0
M_A_DQSP6M_A_DQSP4
M_A_DQSN6M_A_DQSN4
68p/50V_4
M_A_DQSP6[2]M_A_DQSP4[2]
M_A_DQSN6[2]M_A_DQSN4[2]
SI1C, 0615
R90 2 40_1%_4 R81 240_1%_4
M_A_ALERT#
M_A_ACT#
M_A_PARITY
M_A_BG#1_1
M_A_BG#1_2
M_A_BG#1_3
M_A_BG#1_4
DB1 Option for 16Gbx16 die
Close DDR ball
Memory 8G & Memory 16G TABLE
R278
R279
R280
R281
R282
R283
R284
R285
R290
R291
R292
R293
4
R54 0 _5%_4
R55 0 _5%_4
R63 0 _5%_4
R409 0_5%_4
Memory 8G
0Ω CS00002JB38
0Ω CS00002JB38
0Ω CS00002JB38
0Ω CS00002JB38
UNINSTAL
UNINSTAL
UNINSTAL
UNINSTAL
INSTAL
INSTAL
INSTAL
INSTAL
U21
M1
VREFCA
B1
VPP#B1
R9
VPP#R9
P3
A0
P7
A1
R3
A2
N7
A3
N3
A4
P8
A5
P2
A6
R8
A7
R2
A8
R7
A9
M3
A10/AP
T2
A11
M7
A12/BC
T8
A13
L2
WE_n/A14
M8
CAS_n/A15
L8
RAS_n/A16
N2
BA0
N8
BA1
M2
BG0
K7
CK_t
K8
CK_c
K2
CKE
K3
ODT
L7
CS
G3
DQSL_t
B7
DQSU_t
F3
DQSL_c
A7
DQSU_c
E7
DML_n/DBIL_n
E2
DMU_n/DBIU_n
P1
RESET_n
F9
ZQ
N9
TEN
P9
ALERT_n
L3
ACT_n
T3
PAR
T7
NC
96-BALL
DDR4
R
AM@DDR4_96P
240Ω CS12402FB03
240Ω CS12402FB03
240Ω CS12402FB03
240Ω CS12402FB03
INSTAL
INSTAL
INSTAL
INSTAL
UNINSTAL
UNINSTAL
UNINSTAL
UNINSTAL
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDD#B3
VDD#B9
VDD#D1
VDD#G7
VDD#J1
VDD#J9
VDD#L1
VDD#L9
VDD#R1
VDD#T9
VDDQ#A1
VDDQ#A9
VDDQ#C1
VDDQ#D9
VDDQ#F2
VDDQ#F8
VDDQ#G1
VDDQ#G9
VDDQ#J2
VDDQ#J8
VSS#B2
VSS#E1
VSS#E9
VSS#G8
VSS#K1
VSS#K9
VSS#M9
VSS#N1
VSS#T1
VSSQ#A2
VSSQ#A8
VSSQ#C9
VSSQ#D2
VSSQ#D8
VSSQ#E3
VSSQ#E8
VSSQ#F1
VSSQ#H1
VSSQ#H9
Memory 16G
BYTE6_48-55
BYTE5_40-47
M_A_DQ50
G2
M_A_DQ51
F7
M_A_DQ48
H3
M_A_DQ55
H7
M_A_DQ49
H2
M_A_DQ54
H8
M_A_DQ52
J3
M_A_DQ53
J7
M_A_DQ42
A3
M_A_DQ44
B8
M_A_DQ40
C3
M_A_DQ45
C7
M_A_DQ43
C2
M_A_DQ47
C8
M_A_DQ41
D3
M_A_DQ46
D7
B3
B9
D1
G7
J1
J9
L1
L9
R1
T9
A1
A9
C1
D9
F2
F8
G1
G9
J2
J8
DB1 Option for 16Gbx16 die
B2
E1
E9
R96 0 _5%_4
G8
K1
K9
M9
N1
T1
A2
A8
C9
D2
D8
E3
E8
F1
H1
H9
3
+2.5V_SUS
68p/50V_4
C62
DB1 change
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_A16
M_A_BA#0
M_A_BA#1
M_A_BG#0
M_A_CLK0
M_A_CLK0#
M_A_CKE0
M_A_ODT0_MD
M_A_CS#0
M_A_DQSP3
M_A_DQSP2
M_A_DQSN3
M_A_DQSN2
M_A_DQ50 [2]
M_A_DQ51 [2]
M_A_DQ48 [2]
M_A_DQ55 [2]
M_A_DQ49 [2]
M_A_DQ54 [2]
M_A_DQ52 [2]
M_A_DQ53 [2]
SI1, 0427 RF
M_A_DQ42 [2]
M_A_DQ44 [2]
M_A_DQ40 [2]
M_A_DQ45 [2]
M_A_DQ43 [2]
M_A_DQ47 [2]
M_A_DQ41 [2]
M_A_DQ46 [2]
R60 *0_5%_4
M_A_DQSP3[2]
M_A_DQSP2[2]
M_A_DQSN3[2]
M_A_DQSN2[2]
SI1C, 0615
M_A_ALERT#
M_A_ACT#
M_A_PARITY
Place these Caps near Channel A
1uF/10uF 4pcs on each side of connector
+1.2VSUS
C72 RA M@1u/6.3V_4
C366 RAM@1u/6.3V_4
C362 RAM@1u/6.3V_4
C91 RA M@1u/6.3V_4
C75 RA M@1u/6.3V_4
C99 RA M@1u/6.3V_4
C109 RAM@1u/6.3V_4
C81 RA M@1u/6.3V_4
C38 RA M@1u/6.3V_4
C23 RA M@1u/6.3V_4
C80 RA M@1u/6.3V_4
C386 RAM@10u/6.3V_4
C336 RAM@10u/6.3V_4
C36 RA M@10u/6.3V_4
C355 RAM@10u/6.3V_4
C113 RAM@1u/6.3V_4
C382 RAM@1u/6.3V_4
C342 RAM@1u/6.3V_4
C337 RAM@1u/6.3V_4
C43 RA M@1u/6.3V_4
SI1, 0421 add
+VDDQ_VTT
DB1 Intel
+SMDDR_VREF_DQ1_M11
DB1 Intel
+SMDDR_VREF_DQ1_M1 +1.2VSUS
C25
C26
68p/50V_4
3.3p/50V_4
U4
M1
VREFCA
B1
VPP#B1
R9
VPP#R9
P3
A0
P7
A1
R3
A2
N7
A3
N3
A4
P8
A5
P2
A6
R8
A7
R2
A8
R7
A9
M3
A10/AP
T2
A11
M7
A12/BC
T8
A13
L2
WE_n/A14
M8
CAS_n/A15
L8
RAS_n/A16
N2
BA0
N8
BA1
M2
BG0
K7
CK_t
K8
CK_c
K2
CKE
K3
ODT
L7
CS
G3
DQSL_t
B7
DQSU_t
F3
DQSL_c
A7
DQSU_c
E7
DML_n/DBIL_n
E2
DMU_n/DBIU_n
P1
RESET_n
F9
ZQ
N9
TEN
P9
ALERT_n
L3
ACT_n
T3
PAR
T7
NC
96-BALL
DDR4
R
AM@DDR4_96P
C94 1 u/6.3V_4
C46 1 u/6.3V_4
C338 1u/6.3V_4
C82 1 u/6.3V_4
C121 1u/6.3V_4
C76 1 u/6.3V_4
C339 1u/6.3V_4
C122 1u/6.3V_4
C29 RA M@10u/6.3V_4
C52 RA M@10u/6.3V_4
C350 0.1u/16V_4
C69 2 .2u/6.3V_4
C64 0 .047u/25V_4
C352 0.047u/25V_4
C66 0 .047u/25V_4
C42 0 .047u/25V_4
SI1B, 0603
SI1, 0417 RF
C65
2200p/50V_4
DB1 RF
3
BYTE3_24-31
BYTE2_16-23
G2
DQL0
F7
DQL1
H3
DQL2
H7
DQL3
H2
DQL4
H8
DQL5
J3
DQL6
J7
DQL7
A3
DQU0
B8
DQU1
C3
DQU2
C7
DQU3
C2
DQU4
C8
DQU5
D3
DQU6
D7
DQU7
B3
VDD#B3
B9
VDD#B9
D1
VDD#D1
G7
VDD#G7
J1
VDD#J1
J9
VDD#J9
L1
VDD#L1
L9
VDD#L9
R1
VDD#R1
T9
VDD#T9
A1
VDDQ#A1
A9
VDDQ#A9
C1
VDDQ#C1
D9
VDDQ#D9
F2
VDDQ#F2
F8
VDDQ#F8
G1
VDDQ#G1
G9
VDDQ#G9
J2
VDDQ#J2
J8
VDDQ#J8
DB1 Option for 16Gbx16 die
B2
VSS#B2
E1
VSS#E1
E9
VSS#E9
G8
VSS#G8
K1
VSS#K1
K9
VSS#K9
M9
VSS#M9
N1
VSS#N1
T1
VSS#T1
A2
VSSQ#A2
A8
VSSQ#A8
C9
VSSQ#C9
D2
VSSQ#D2
D8
VSSQ#D8
E3
VSSQ#E3
E8
VSSQ#E8
F1
VSSQ#F1
H1
VSSQ#H1
H9
VSSQ#H9
M_A_DQ29
M_A_DQ26
M_A_DQ25
M_A_DQ31
M_A_DQ24
M_A_DQ27
M_A_DQ30
M_A_DQ28
M_A_DQ19
M_A_DQ21
M_A_DQ17
M_A_DQ20
M_A_DQ16
M_A_DQ23
M_A_DQ18
M_A_DQ22
R95 0 _5%_4
R61 *0_5%_4
+VREF_CA_CPU[2]
C40
68p/50V_4
2
2
+2.5V_SUS
68p/50V_4
M_A_DQSP1[2]
M_A_DQSN1[2]
DB1 changeDB1 change
C365
M_A_DQ29 [2]
M_A_DQ26 [2]
M_A_DQ25 [2]
M_A_DQ31 [2]
M_A_DQ24 [2]
M_A_DQ27 [2]
M_A_DQ30 [2]
M_A_DQ28 [2]
SI1, 0427 RF
M_A_DQ19 [2]
M_A_DQ21 [2]
M_A_DQ17 [2]
M_A_DQ20 [2]
M_A_DQ16 [2]
M_A_DQ23 [2]
M_A_DQ18 [2]
M_A_DQ22 [2]
SI1C, 0615
R414 240_1%_4
M_A_ALERT#
M_A_ACT#
M_A_PARITY
VREF DQ1 M1 Solution
+VREF_CA_CPU +SMDDR_ VREF_DQ1_M11
R133 24.9_1%_4
R140
C118
0.022u/25V_4
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_A16
M_A_BA#0
M_A_BA#1
M_A_BG#0
M_A_CLK0
M_A_CLK0#
M_A_CKE0
M_A_ODT0_MD
M_A_CS#0
M_A_DQSP1
M_A_DQSN1
RAM@2_1%_6
+1.2VSUS
M1
B1
R9
P3
P7
R3
N7
N3
P8
P2
R8
R2
R7
M3
M7
M8
N2
N8
M2
K7
K8
K2
K3
G3
B7
A7
E7
E2
P1
N9
P9
R146
3.65K_1%_4
R145
3.65K_1%_4
SI1, 0417 RF
C344
0.1u/16V_4
C37
3.3p/50V_4
C39
2200p/50V_4
DB1 RF
U22
T2
T8
L2
L8
L7
F3
F9
L3
T3
T7
R
VREFCA
VPP#B1
VPP#R9
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
WE_n/A14
CAS_n/A15
RAS_n/A16
BA0
BA1
BG0
CK_t
CK_c
CKE
ODT
CS
DQSL_t
DQSU_t
DQSL_c
DQSU_c
DML_n/DBIL_n
DMU_n/DBIU_n
RESET_n
ZQ
TEN
ALERT_n
ACT_n
PAR
NC
96-BALL
DDR4
AM@DDR4_96P
1
BYTE1_8-15
BYTE0_0-7
M_A_DQ12
G2
DQL0
M_A_DQ8
F7
DQL1
M_A_DQ11
H3
DQL2
M_A_DQ10
H7
DQL3
M_A_DQ14
H2
DQL4
M_A_DQ9
H8
DQL5
M_A_DQ13
J3
DQL6
M_A_DQ15
J7
DQL7
A3
DQU0
B8
DQU1
C3
DQU2
C7
DQU3
C2
DQU4
C8
DQU5
D3
DQU6
D7
DQU7
B3
VDD#B3
B9
VDD#B9
D1
VDD#D1
G7
VDD#G7
J1
VDD#J1
J9
VDD#J9
L1
VDD#L1
L9
VDD#L9
R1
VDD#R1
T9
VDD#T9
A1
VDDQ#A1
A9
VDDQ#A9
C1
VDDQ#C1
D9
VDDQ#D9
F2
VDDQ#F2
F8
VDDQ#F8
G1
VDDQ#G1
G9
VDDQ#G9
J2
VDDQ#J2
J8
VDDQ#J8
DB1 Option for 16Gbx16 die
B2
VSS#B2
E1
VSS#E1
E9
VSS#E9
VSS#G8
VSS#K1
VSS#K9
VSS#M9
VSS#N1
VSS#T1
VSSQ#A2
VSSQ#A8
VSSQ#C9
VSSQ#D2
VSSQ#D8
VSSQ#E3
VSSQ#E8
VSSQ#F1
VSSQ#H1
VSSQ#H9
R415 0_5%_4
G8
K1
K9
M9
R411 *0_5%_4
N1
T1
A2
A8
C9
D2
D8
E3
E8
F1
H1
H9
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
DDR4 Memory Down (CH. A)
DDR4 Memory Down (CH. A)
DDR4 Memory Down (CH. A)
Date: Sheet of
Thursday, August 09, 2018
Date: Sheet of
Thursday, August 09, 2018
Date: Sheet of
Thursday, August 09, 2018
1
M_A_DQ12 [2]
M_A_DQ8 [2]
M_A_DQ11 [2]
M_A_DQ10 [2]
M_A_DQ14 [2]
M_A_DQ9 [2]
M_A_DQ13 [2]
M_A_DQ15 [2]
10
SI1C, 0615
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
ZHVA
ZHVA
ZHVA
10 34
10 34
10 34
1A
1A
1A
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