1
A A
DDRII-SODIMM1
DDRII-SODIMM2
PG 7,8
Mini Card (WLAN)
PCI Express Mini Card
Express Card
B B
NEW CARD
PCIE3 & USB4
PG 19
PCIE2 & USB5
PG 31
2
BOM MARK
SA@ SATA
PA@ PATA
3@ 3G
要打
要打
要打
533/ 667 MHZ DDR II PG 7,8
USB 2.0 * 1(USB5)
PCI-E, 1X
PCI-E, 1X
3
ZH3
AMD S1
Turion 64 Rev.F Dual-Core/
Sempron Rev.F Single-Core
Dual-Core 35W / Single-Core 25W
(638 S1g1 socket)
PG 3,4,5,6
HT_LINK
RS485
465 FCBGA
4
CPU THERMAL
SENSOR
Page 5
DVI
TI TFP513PAP
DVO
TVOUT
RGB
LVDS
Page : 29
5
ZH3 ASSY P/N :31ZH3MB0008
ZH3 MB C/S ASSY P/N: 41ZH3CS0001
ZH3 MB S/S ASSY P/N: 51ZH3SS0003
CRT Switch
SN74CBTLV3257PWR
Page : 16
6
DVI
EXT_CRT
INT_CRT
Docking
Page : 30
CRT
Page : 16
LVDS
Page : 16
7
VCC_CORE
+1.2V
+VCCP
+1.8VSUS
+1.8V
SMDDR_VTERM
+3VPCU
+3V_S5
+3VSUS
+5VSUS
+5V
+12V
VIN
8
CPU VR
PG 30
+1.2V
+VCCP
PG 31
+1.8VSUS
SMDDR
VTERM
PG 32
3V/5V
PG 33
CHARGER
PG 34
PG 9,10,11,12
A_LINK
USB2.0 (P0~P7)
SATA - HDD
PG 23
PATA - HDD
SATA0
PATA 100
SB460
549 BGA
PG 23
C C
PCI Bus 33MHz
Bluetooth
USB7
USB2.0 I/O Port X3
USB0 & USB1& USB2
DSC USB I/F
USB6
PG 20
PG 20
PG 16
Azalia
PG 14,15,16,17
Azalia Audio
PG 24
Amplifier
MAX4411
PG 25
Amplifier
MAX9755A
PG 25
Azalia MDC
PG 24
G-SENSOR
KXP84-0200
D D
MIC.
PG 25
H.P/SPDIF
PG 25
1
INT.
S.P.
PG 25
2
MODEM
RJ 11
PG 18
Page : 23
3
LPC
K/B
CONN.
PG 28
4
PCI7412 REQ0# / GNT0#
5788M INT G#
KBC
NS97551
Touch
Pad
PG 28
IDSEL#
AD25
AD20 REQ2# / GNT2#
PG 27
X-Bus
Flash
ROM
PG 27
SIO (87383)
Page : 26
Page : 26
5
NS
FIR
Interrupts PCI DEVICE REQ# / GNT#
INT E/F/G#
AD25
REQ0# / GNT0#
INT E/F/G#
OSC
48MHZ
1394
Page: 21
6
HOST 133/166MHz
PCIE 100MHz
VGA 96MHz
USB 48MHz
REF 14MHz
TI
PCMCIA+1394
+6 IN 1
PCI7412
Page :21~22
5 IN 1
Page: 22
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
BROADCOM
10/100/1G LAN
BOTHHAND
TRANSFORMER
PCMCIA
Page: 22
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
7
CLOCK GENERATOR
ICS951462
PG 2
PG 17
5788M
RJ45
PG 18
PROJECT :ZH3
PROJECT :ZH3
Quanta Computer Inc.
Quanta Computer Inc.
PG 18
13 6 Tuesday, June 27, 2006
13 6 Tuesday, June 27, 2006
13 6 Tuesday, June 27, 2006
8
of
of
of
D
D
D
5
4
3
2
1
+3V
L68
L68
SBK160808T-301Y-S
SBK160808T-301Y-S
D D
1- PLACE ALL SERIAL TERMINATION
RESISTORS CLOSE TO U800
2- PUT DECOUPLING CAPS CLOSE TO
Clock Gen.POWER PIN
C C
B B
CLK_VDD
C102
C102
C118
C118
C112
C112
C128
C128
C558
C558
C560
C560
22U/10V_8
22U/10V_8
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
.1U_4
+3V
.1U_4
.1U_4
.1U_4
.1U_4
L64
L64
SBK160808T-301Y-S
SBK160808T-301Y-S
300ohm/200mA
+3V
L63
L63
SBK160808T-301Y-S
SBK160808T-301Y-S
300ohm/200mA
SYS_RST# 13
C528
C528
1U/10V_4
1U/10V_4
R351 *0_4 R351 *0_4
CLK_VDD
EXT CLK FREQUENCY SELECT TABLE(MHZ)
FS1
FS0
FS2
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 1
CPU
Hi-Z
X
180.00
220.00
100.00
133.33
200.00
SRCCLK
[2:1]
100.00
100.00
100.00
100.00
100.00
100.00
100.00
PCI
HTT
Hi-Z
Hi-Z
X/3 X/6
30.00
60.00
73.12
36.56
66.66
33.33
66.66
33.33
66.66
33.33 48.00
C534
C534
C554
C554
.1U_4
.1U_4
C86
C86
1U/10V_4
1U/10V_4
CLK_VDD_REF
C529
C529
.1U_4
.1U_4
Parallel Resonance Crystal
R352
R352
10K_4
10K_4
USB
48.00
48.00
48.00
48.00
48.00
48.00
C542
C542
.1U_4
.1U_4
.1U_4
.1U_4
CLK_VDD_USB
C530
C530
.1U_4
.1U_4
C531 33P_4 C531 33P_4
C536 33P_4 C536 33P_4
PCLK_SMB 7,13,17,19,30
PDAT_SMB 7,13,17,19,30
Ioh = 5 * Iref
(2.32mA)
Voh = 0.71V @ 60 ohm
COMMENT
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Y4
Y4
14.318MHz
14.318MHz
Normal ATHLON64 operation
CLK_VDD
CLK_XOUT
CLK_XIN
R355
R355
475/F_4
475/F_4
U19
U19
54
VDDCPU
14
VDD_SRC1
23
VDD_SRC2
28
VDD_SRC3
44
VDD_SRC4
5
VDD_48
39
VDD_ATIG
2
VDD_REF
60
VDDHTT
53
GND_CPU
15
GND_SRC1
22
GND_SRC2
29
GND_SRC3
45
GND_SRC4
8
GND_48
38
GND_ATIG
1
GND_REF
58
GNDHTT
3
XIN
4
XOUT
11
RESET_IN#
61
NC
9
SMBCLK
10
SMBDAT
48
IREF
ICS951462
ICS951462
CLKREQA# Controls SRC5,6,7
CLKREQB# Controls SRC2,3,4,ATIG3
CLKREQC# Controls SRC0,1,ATIG0,1,2
CLKREQB#
EZ_CLKREQ#
B1A R342 not stuff for New card
VDDA
GNDA
CPUCLK8T0
CPUCLK8C0
CPUCLK8T1
CPUCLK8C1
ATIGCLKT0
ATIGCLKC0
ATIGCLKT1
ATIGCLKC1
ATIGCLKT2
ATIGCLKC2
ATIGCLKT3
ATIGCLKC3
SRCCLKT0
SRCCLKC0
SRCCLKT1
SRCCLKC1
SRCCLKT2
SRCCLKC2
SRCCLKT3
SRCCLKC3
SRCCLKT4
SRCCLKC4
SRCCLKT5
SRCCLKC5
SRCCLKT6
SRCCLKC6
SRCCLKT7
SRCCLKC7
CLKREQA#
CLKREQB#
CLKREQC#
48MHz_1
48MHz_0
FS1/REF1
FS0/REF0
FS2/REF2
HTTCLK0
R394 *10K_4 R394 *10K_4
R395 10K_4 R395 10K_4
50
49
56
55
52
51
41
40
37
36
35
34
30
31
47
46
43
42
26
27
24
25
20
21
18
19
16
17
12
13
57
32
33
7
6
63
64
62
59
+3V
CLK_VDDA
CPUCLK_EXT_R
CPUCLK#_EXT_R
NBSRC_CLKP_R
NBSRC_CLKN_R
GPP_CLK2P_R
GPP_CLK2N_R
GPP_CLK3P_R
GPP_CLK3N_R
SBLINK_CLKP_R
SBLINK_CLKN_R
SBSRC_CLKP_R
SBSRC_CLKN_R
GPP_CLK0P_R
GPP_CLK0N_R
R396 0_4 R396 0_4
CLK_48M_1_R
CLK_48M_2_R
CLK_VDDA
C544
C544
.1U_4
.1U_4
R337 47/F_4 R337 47/F_4
R346 47/F_4 R346 47/F_4
R384 33/F_4 R384 33/F_4
R388 33/F_4 R388 33/F_4
R359 33/F_4 R359 33/F_4
R363 33/F_4 R363 33/F_4
R372 33/F_4 R372 33/F_4
R377 33/F_4 R377 33/F_4
R387 33/F_4 R387 33/F_4
R392 33/F_4 R392 33/F_4
R375 33/F_4 R375 33/F_4
R380 33/F_4 R380 33/F_4
R366 33/F_4 R366 33/F_4
R370 33/F_4 R370 33/F_4
CLKREQB#
EZ_CLKREQ#
T92T92
R315 33/F_4 R315 33/F_4
SB_OSCIN_R
NB_OSCIN_R
HTREFCLK_R
C547
C547
22U/10V_8
22U/10V_8
R340 261/F_4 R340 261/F_4
T93T93
EZ_CLKREQ# 27,30
L66
L66
SBK160808T-301Y-S
SBK160808T-301Y-S
USBCLK 13
R324 8.2K_4 R324 8.2K_4
R319 8.2K_4 R319 8.2K_4
R328 8.2K_4 R328 8.2K_4
R325 33/F_4 R325 33/F_4
R316 33/F_4 R316 33/F_4
R329 33/F_4 R329 33/F_4
R333 33/F_4 R333 33/F_4
Check AMD clock
+3V
R369 49.9/F_4 R369 49.9/F_4
CLK_VDD
R334
R334
49.9/F_4
49.9/F_4
CPUCLK 5
CPUCLK# 5
R379 49.9/F_4 R379 49.9/F_4
R365 49.9/F_4 R365 49.9/F_4
R313
R313
2.2K_4
2.2K_4
R391 49.9/F_4 R391 49.9/F_4
R374 49.9/F_4 R374 49.9/F_4
R386 49.9/F_4 R386 49.9/F_4
R314
R314
2.2K_4
2.2K_4
SB_OSCIN 13
SIO_14M 26
NB_OSC 10
HTREFCLK 10
R373 49.9/F_4 R373 49.9/F_4
R378 49.9/F_4 R378 49.9/F_4
R326
R326
2.2K_4
2.2K_4
R320 *0_4 R320 *0_4
R310 *0_4 R310 *0_4
R330 *0_4 R330 *0_4
R364 49.9/F_4 R364 49.9/F_4
R360 49.9/F_4 R360 49.9/F_4
R389 49.9/F_4 R389 49.9/F_4
R385 49.9/F_4 R385 49.9/F_4
NBSRC_CLKP 10
NBSRC_CLKN 10
CLK_PCIE_EZ1 30
CLK_PCIE_EZ1# 30
CLK_PCIE_EZ2 30
CLK_PCIE_EZ2# 30
SBLINK_CLKP 10
SBLINK_CLKN 10
SBSRCCLK 12
SBSRCCLK# 12
CLK_PCIE_MINI_A 19
CLK_PCIE_MINI_A# 19
NB
DOCKING
SB
MINI
A A
<OrgName>
<OrgName>
<OrgName>
<OrgAd dr1>
<OrgAd dr1>
<OrgAd dr1>
<OrgA ddr2>
<OrgA ddr2>
<OrgA ddr2>
<OrgAd dr3>
<OrgAd dr3>
<OrgAd dr3>
<OrgAddr4>
<OrgAddr4>
<OrgAddr4>
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
CLOCK GENERATOR
CLOCK GENERATOR
CLOCK GENERATOR
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
PROJECT :ZH3
PROJECT :ZH3
Quanta Computer Inc.
Quanta Computer Inc.
23 6 Tuesday, June 27, 2006
23 6 Tuesday, June 27, 2006
23 6 Tuesday, June 27, 2006
of
of
1
of
D
D
D
5
4
3
2
1
PROCESSOR HYPERTRANSPORT INTERFACE
D D
VLDT_Ax AND VLDT_Bx ARE CONNECTED TO THE LDT_RUN POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE
VLDT_RUN
HT_CADIN15_P 8
HT_CADIN15_N 8
HT_CADIN14_P 8
HT_CADIN14_N 8
HT_CADIN13_P 8
HT_CADIN13_N 8
HT_CADIN12_P 8
HT_CADIN12_N 8
HT_CADIN11_P 8
HT_CADIN11_N 8
HT_CADIN10_P 8
HT_CADIN10_N 8
HT_CADIN9_P 8
HT_CADIN9_N 8
HT_CADIN8_P 8
C C
VLDT_RUN
B B
HT_CADIN8_N 8
HT_CADIN7_P 8
HT_CADIN7_N 8
HT_CADIN6_P 8
HT_CADIN6_N 8
HT_CADIN5_P 8
HT_CADIN5_N 8
HT_CADIN4_P 8
HT_CADIN4_N 8
HT_CADIN3_P 8
HT_CADIN3_N 8
HT_CADIN2_P 8
HT_CADIN2_N 8
HT_CADIN1_P 8
HT_CADIN1_N 8
HT_CADIN0_P 8
HT_CADIN0_N 8
HT_CLKIN1_P 8
HT_CLKIN1_N 8
HT_CLKIN0_P 8
HT_CLKIN0_N 8
R48 49.9/F_4 R48 49.9/F_4
49.9/F_4
49.9/F_4
R49
R49
HT_CTLIN0_P 8
HT_CTLIN0_N 8
+1.2V
VLDT_RUN
U20A U20A
D4
D3
D2
D1
N5
P5
M3
M4
L5
M5
K3
K4
H3
H4
G5
H5
F3
F4
E5
F5
N3
N2
L1
M1
L3
L2
J1
K1
G1
H1
G3
G2
E1
F1
E3
E2
J5
K5
J3
J2
P3
P4
N1
P1
VLDT_A3
VLDT_A2
VLDT_A1
VLDT_A0
L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0
L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKIN_H0
L0_CLKIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
L0_CTLIN_H0
L0_CTLIN_L0
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
Athlon 64 S1
Processor Socket
VLDT_B3
VLDT_B2
VLDT_B1
VLDT_B0
AE5
AE4
AE3
AE2
T4
T3
V5
U5
V4
V3
Y5
W5
AB5
AA5
AB4
AB3
AD5
AC5
AD4
AD3
T1
R1
U2
U3
V1
U1
W2
W3
AA2
AA3
AB1
AA1
AC2
AC3
AD1
AC1
Y4
Y3
Y1
W1
T5
R5
R2
R3
HT_CPU_CTLOUT1_P HT_CTLIN1_P
HT_CPU_CTLOUT1_N HT_CTLIN1_N
C69 4.7U/6.3V_6 C69 4.7U/6.3V_6
HT_CADOUT15_P 8
HT_CADOUT15_N 8
HT_CADOUT14_P 8
HT_CADOUT14_N 8
HT_CADOUT13_P 8
HT_CADOUT13_N 8
HT_CADOUT12_P 8
HT_CADOUT12_N 8
HT_CADOUT11_P 8
HT_CADOUT11_N 8
HT_CADOUT10_P 8
HT_CADOUT10_N 8
HT_CADOUT9_P 8
HT_CADOUT9_N 8
HT_CADOUT8_P 8
HT_CADOUT8_N 8
HT_CADOUT7_P 8
HT_CADOUT7_N 8
HT_CADOUT6_P 8
HT_CADOUT6_N 8
HT_CADOUT5_P 8
HT_CADOUT5_N 8
HT_CADOUT4_P 8
HT_CADOUT4_N 8
HT_CADOUT3_P 8
HT_CADOUT3_N 8
HT_CADOUT2_P 8
HT_CADOUT2_N 8
HT_CADOUT1_P 8
HT_CADOUT1_N 8
HT_CADOUT0_P 8
HT_CADOUT0_N 8
HT_CLKOUT1_P 8
HT_CLKOUT1_N 8
HT_CLKOUT0_P 8
HT_CLKOUT0_N 8
HT_CTLOUT0_P 8
HT_CTLOUT0_N 8
T29T29
T34T34
L57
L57
FBJ3216HS800
FBJ3216HS800
L56
L56
FBJ3216HS800
FBJ3216HS800
80 ohm(4A)
A A
C67
C67
4.7U/6.3V_6
4.7U/6.3V_6
C66
C66
4.7U/6.3V_6
4.7U/6.3V_6
LAYOUT: Place bypass cap on topside of board
5
C70
C70
.22U/6V_4
.22U/6V_4
NEAR HT POWER PINS THAT ARE NOT CONNECTED DIRECTLY
TO DOWNSTREAM HT DEVICE, BUT CONNECTED INTERNALLY
TO OTHER HT POWER PINS
PLACE CLOSE TO VLDT0 POWER PINS
C63
C63
.22U/6V_4
.22U/6V_4
1 2
C71
C71
10P_4
10P_4
1 2
C64
C64
10P_4
10P_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
ATHLON64 HT I/F
ATHLON64 HT I/F
ATHLON64 HT I/F
Date: Sheet
Date: Sheet
4
3
2
Date: Sheet
PROJECT :ZH3
PROJECT :ZH3
Quanta Computer Inc.
Quanta Computer Inc.
of
of
of
33 6 Tuesday, June 27, 2006
33 6 Tuesday, June 27, 2006
1
33 6 Tuesday, June 27, 2006
D
D
D
A
B
C
D
E
C133
C133
1000p/50V_4
1000p/50V_4
U20B
U20B
MEMVREF
VTT_SENSE
MEMZN
MEMZP
MA0_CS_L3
MA0_CS_L2
MA0_CS_L1
MA0_CS_L0
MB0_CS_L3
MB0_CS_L2
MB0_CS_L1
MB0_CS_L0
MB_CKE1
MB_CKE0
MA_CKE1
MA_CKE0
MA_ADD15
MA_ADD14
MA_ADD13
MA_ADD12
MA_ADD11
MA_ADD10
MA_ADD9
MA_ADD8
MA_ADD7
MA_ADD6
MA_ADD5
MA_ADD4
MA_ADD3
MA_ADD2
MA_ADD1
MA_ADD0
MA_BANK2
MA_BANK1
MA_BANK0
MA_RAS_L
MA_CAS_L
MA_WE_L
C82
C82
.22U/6V_4
.22U/6V_4
+1.8VSUS
R74
R74
1K/F_4
1K/F_4
R75
R75
1K/F_4
1K/F_4
MA0_CLK_H2
MA0_CLK_L2
MA0_CLK_H1
MA0_CLK_L1
MB0_CLK_H2
MB0_CLK_L2
MB0_CLK_H1
MB0_CLK_L1
MB0_ODT1
MB0_ODT0
MA0_ODT1
MA0_ODT0
MB_ADD15
MB_ADD14
MB_ADD13
MB_ADD12
MB_ADD11
MB_ADD10
MB_ADD9
MB_ADD8
MB_ADD7
MB_ADD6
MB_ADD5
MB_ADD4
MB_ADD3
MB_ADD2
MB_ADD1
MB_ADD0
MB_BANK2
MB_BANK1
MB_BANK0
MB_RAS_L
MB_CAS_L
MB_WE_L
DDR II: CMD/CTRL/CLK
DDR II: CMD/CTRL/CLK
Athlon 64 S1
Processor Socket
C94
C94
1000p/50V_4
1000p/50V_4
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
C93
C93
1000p/50V_4
1000p/50V_4
D10
C10
B10
AD10
W10
AC10
AB10
AA10
A10
Y16
AA16
E16
F16
AF18
AF17
A17
A18
W23
W26
V20
U19
J25
J26
W25
L23
L25
U25
L24
M26
L26
N23
N24
N25
N26
P24
P26
T24
K26
T26
U26
U24
V26
U22
1000p/50V_4
1000p/50V_4
C92
C92
+0.9V_VTER
M_B_A15
M_B_A14
M_B_A13
M_B_A12
M_B_A11
M_B_A10
M_B_A9
M_B_A8
M_B_A7
M_B_A6
M_B_A5
M_B_A4
M_B_A3
M_B_A2
M_B_A1
M_B_A0
C91
C91
1000p/50V_4
1000p/50V_4
M_ODT3 7
M_ODT2 7
M_ODT1 7
M_ODT0 7
M_B_BS#2 7
M_B_BS#1 7
M_B_BS#0 7
M_B_RAS# 7
M_B_CAS# 7
M_B_WE# 7
180P_4
180P_4
M_CLKOUT1 7
M_CLKOUT1# 7
M_CLKOUT0 7
M_CLKOUT0# 7
M_CLKOUT4 7
M_CLKOUT4# 7
M_CLKOUT3 7
M_CLKOUT3# 7
M_B_A[0..15] 7
C326
C326
C302
C302
180P_4
180P_4
180P_4
180P_4
C340
C340
C284
C284
180P_4
180P_4
Processor DDR2 Memory Interface
U20C
AD11
AF11
AF14
AE14
AB11
AC12
AF13
AF15
AF16
AC18
AF19
AD14
AC14
AE18
AD18
AD20
AC20
AF23
AF24
AF20
AE20
AD22
AC22
AE25
AD26
AA25
AA26
AE24
AD24
AA23
AA24
AD12
AC16
AE22
AB26
AF12
AE12
AE16
AD16
AF21
AF22
AC25
AC26
Y11
G24
G23
D26
C26
G26
G25
E24
E23
C24
B24
C20
B20
C25
D24
A21
D20
D18
C18
D14
C14
A20
A19
A16
A15
A13
D12
E11
G11
B14
A14
A11
C11
E25
A22
B16
A12
F26
E26
A24
A23
D16
C16
C12
B12
U20C
MB_DATA63
MB_DATA62
MB_DATA61
MB_DATA60
MB_DATA59
MB_DATA58
MB_DATA57
MB_DATA56
MB_DATA55
MB_DATA54
MB_DATA53
MB_DATA52
MB_DATA51
MB_DATA50
MB_DATA49
MB_DATA48
MB_DATA47
MB_DATA46
MB_DATA45
MB_DATA44
MB_DATA43
MB_DATA42
MB_DATA41
MB_DATA40
MB_DATA39
MB_DATA38
MB_DATA37
MB_DATA36
MB_DATA35
MB_DATA34
MB_DATA33
MB_DATA32
MB_DATA31
MB_DATA30
MB_DATA29
MB_DATA28
MB_DATA27
MB_DATA26
MB_DATA25
MB_DATA24
MB_DATA23
MB_DATA22
MB_DATA21
MB_DATA20
MB_DATA19
MB_DATA18
MB_DATA17
MB_DATA16
MB_DATA15
MB_DATA14
MB_DATA13
MB_DATA12
MB_DATA11
MB_DATA10
MB_DATA9
MB_DATA8
MB_DATA7
MB_DATA6
MB_DATA5
MB_DATA4
MB_DATA3
MB_DATA2
MB_DATA1
MB_DATA0
MB_DM7
MB_DM6
MB_DM5
MB_DM4
MB_DM3
MB_DM2
MB_DM1
MB_DM0
MB_DQS_H7
MB_DQS_L7
MB_DQS_H6
MB_DQS_L6
MB_DQS_H5
MB_DQS_L5
MB_DQS_H4
MB_DQS_L4
MB_DQS_H3
MB_DQS_L3
MB_DQS_H2
MB_DQS_L2
MB_DQS_H1
MB_DQS_L1
MB_DQS_H0
MB_DQS_L0
DDR: DATA
DDR: DATA
Athlon 64 S1
Processor Socket
MA_DATA63
MA_DATA62
MA_DATA61
MA_DATA60
MA_DATA59
MA_DATA58
MA_DATA57
MA_DATA56
MA_DATA55
MA_DATA54
MA_DATA53
MA_DATA52
MA_DATA51
MA_DATA50
MA_DATA49
MA_DATA48
MA_DATA47
MA_DATA46
MA_DATA45
MA_DATA44
MA_DATA43
MA_DATA42
MA_DATA41
MA_DATA40
MA_DATA39
MA_DATA38
MA_DATA37
MA_DATA36
MA_DATA35
MA_DATA34
MA_DATA33
MA_DATA32
MA_DATA31
MA_DATA30
MA_DATA29
MA_DATA28
MA_DATA27
MA_DATA26
MA_DATA25
MA_DATA24
MA_DATA23
MA_DATA22
MA_DATA21
MA_DATA20
MA_DATA19
MA_DATA18
MA_DATA17
MA_DATA16
MA_DATA15
MA_DATA14
MA_DATA13
MA_DATA12
MA_DATA11
MA_DATA10
MA_DATA9
MA_DATA8
MA_DATA7
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MA_DATA2
MA_DATA1
MA_DATA0
MA_DM7
MA_DM6
MA_DM5
MA_DM4
MA_DM3
MA_DM2
MA_DM1
MA_DM0
MA_DQS_H7
MA_DQS_L7
MA_DQS_H6
MA_DQS_L6
MA_DQS_H5
MA_DQS_L5
MA_DQS_H4
MA_DQS_L4
MA_DQS_H3
MA_DQS_L3
MA_DQS_H2
MA_DQS_L2
MA_DQS_H1
MA_DQS_L1
MA_DQS_H0
MA_DQS_L0
M_B_DQ[0..63] 7
To SODIMM socket B (Far)
M_B_DM[0..7] 7 M_A_DM[0..7] 7
M_B_DQS[0..7] 7
M_B_DQS#[0..7] 7
M_B_DQ63
M_B_DQ62
M_B_DQ61
M_B_DQ60
M_B_DQ59
M_B_DQ58
M_B_DQ57
M_B_DQ56
M_B_DQ55
M_B_DQ54
M_B_DQ53
M_B_DQ52
M_B_DQ51
M_B_DQ50
M_B_DQ49
M_B_DQ48
M_B_DQ47
M_B_DQ46
M_B_DQ45
M_B_DQ44
M_B_DQ43
M_B_DQ42
M_B_DQ41
M_B_DQ40
M_B_DQ39
M_B_DQ38
M_B_DQ37
M_B_DQ36
M_B_DQ35
M_B_DQ34
M_B_DQ33
M_B_DQ32
M_B_DQ31
M_B_DQ30
M_B_DQ29
M_B_DQ28
M_B_DQ27
M_B_DQ26
M_B_DQ25
M_B_DQ24
M_B_DQ23
M_B_DQ22
M_B_DQ21
M_B_DQ20
M_B_DQ19
M_B_DQ18
M_B_DQ17
M_B_DQ16
M_B_DQ15
M_B_DQ14
M_B_DQ13
M_B_DQ12
M_B_DQ11
M_B_DQ10
M_B_DQ9
M_B_DQ8
M_B_DQ7
M_B_DQ6
M_B_DQ5
M_B_DQ4
M_B_DQ3
M_B_DQ2
M_B_DQ1
M_B_DQ0
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_DM7
M_B_DM6
M_B_DM5
M_B_DM4
M_B_DM3
M_B_DM2
M_B_DM1
M_B_DM0
M_B_DQS7
M_B_DQS#7
M_B_DQS6
M_B_DQS#6
M_B_DQS5
M_B_DQS#5
M_B_DQS4
M_B_DQS#4
M_B_DQS3
M_B_DQS#3
M_B_DQS2
M_B_DQS#2
M_B_DQS1
M_B_DQS#1
M_B_DQS0
M_B_DQS#0
AA12
AB12
AA14
AB14
W11
Y12
AD13
AB13
AD15
AB15
AB17
Y17
Y14
W14
W16
AD17
Y18
AD19
AD21
AB21
AB18
AA18
AA20
Y20
AA22
Y22
W21
W22
AA21
AB22
AB24
Y24
H22
H20
E22
E21
J19
H24
F22
F20
C23
B22
F18
E18
E20
D22
C19
G18
G17
C17
F14
E14
H17
E17
E15
H15
E13
C13
H12
H11
G14
H14
F12
G12
Y13
AB16
Y19
AC24
F24
E19
C15
E12
W12
W13
Y15
W15
AB19
AB20
AD23
AC23
G22
G21
C22
C21
G16
G15
G13
H13
M_A_DQ63
M_A_DQ62
M_A_DQ61
M_A_DQ60
M_A_DQ59
M_A_DQ58
M_A_DQ57
M_A_DQ56
M_A_DQ55
M_A_DQ54
M_A_DQ53
M_A_DQ52
M_A_DQ51
M_A_DQ50
M_A_DQ49
M_A_DQ48
M_A_DQ47
M_A_DQ46
M_A_DQ45
M_A_DQ44
M_A_DQ43
M_A_DQ42
M_A_DQ41
M_A_DQ40
M_A_DQ39
M_A_DQ38
M_A_DQ37
M_A_DQ36
M_A_DQ35
M_A_DQ34
M_A_DQ33
M_A_DQ32
M_A_DQ31
M_A_DQ30
M_A_DQ29
M_A_DQ28
M_A_DQ27
M_A_DQ26
M_A_DQ25
M_A_DQ24
M_A_DQ23
M_A_DQ22
M_A_DQ21
M_A_DQ20
M_A_DQ19
M_A_DQ18
M_A_DQ17
M_A_DQ16
M_A_DQ15
M_A_DQ14
M_A_DQ13
M_A_DQ12
M_A_DQ11
M_A_DQ10
M_A_DQ9
M_A_DQ8
M_A_DQ7
M_A_DQ6
M_A_DQ5
M_A_DQ4
M_A_DQ3
M_A_DQ2
M_A_DQ1
M_A_DQ0
M_A_DM7
M_A_DM6
M_A_DM5
M_A_DM4
M_A_DM3
M_A_DM2
M_A_DM1
M_A_DM0
M_A_DQS7
M_A_DQS#7
M_A_DQS6
M_A_DQS#6
M_A_DQS5
M_A_DQS#5
M_A_DQS4
M_A_DQS#4
M_A_DQS3
M_A_DQS#3
M_A_DQS2
M_A_DQS#2
M_A_DQS1
M_A_DQS#1
M_A_DQS0
M_A_DQS#0
M_A_DQS[0..7] 7
M_A_DQS#[0..7] 7
M_A_DQ[0..63] 7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
To SODIMM socket A (near)
VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE
CPU_M_VREF
4 4
+1.8VSUS
R344
R344
39.2F_4
39.2F_4
1 2
R350
R350
39.2F_4
39.2F_4
1 2
PLACE THEM CLOSE TO
CPU WITHIN 1"
3 3
2 2
C100
C100
C80
C80
4.7U/6.3V_6
4.7U/6.3V_6
4.7U/6.3V_6
4.7U/6.3V_6
+0.9V_VTER
C90
C90
4.7U/6.3V_6
4.7U/6.3V_6
T35T35
M_A_CS#3 7
M_A_CS#2 7
M_A_CS#1 7
M_A_CS#0 7
M_B_CS#3 7
M_B_CS#2 7
M_B_CS#1 7
M_B_CS#0 7
M_A_A[0..15] 7
4.7U/6.3V_6
4.7U/6.3V_6
C101
C101
M_ZN
M_ZP
M_CKE3 7
M_CKE2 7
M_CKE1 7
M_CKE0 7
M_A_BS#2 7
M_A_BS#1 7
M_A_BS#0 7
M_A_RAS# 7
M_A_CAS# 7
M_A_WE# 7
C81
C81
.22U/6V_4
.22U/6V_4
VTT_SENSE
M_A_A15
M_A_A14
M_A_A13
M_A_A12
M_A_A11
M_A_A10
M_A_A9
M_A_A8
M_A_A7
M_A_A6
M_A_A5
M_A_A4
M_A_A3
M_A_A2
M_A_A1
M_A_A0
C83
C83
.22U/6V_4
.22U/6V_4
C132
C132
.1U_4
.1U_4
W17
Y10
AE10
AF10
V19
J22
V22
T19
Y26
J24
W24
U23
H26
J23
J20
J21
K19
K20
V24
K24
L20
R19
L19
L22
L21
M19
M20
M24
M22
N22
N21
R21
K22
R20
T22
T20
U20
U21
C99
C99
.22U/6V_4
.22U/6V_4
1 1
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
ATHLON64 DDRII MEMORY I/F
ATHLON64 DDRII MEMORY I/F
ATHLON64 DDRII MEMORY I/F
Date: Sheet
Date: Sheet
A
B
C
D
Date: Sheet
PROJECT :ZH3
PROJECT :ZH3
Quanta Computer Inc.
Quanta Computer Inc.
43 6 Tuesday, June 27, 2006
43 6 Tuesday, June 27, 2006
43 6 Tuesday, June 27, 2006
of
of
E
of
D
D
D
5
LAYOUT: ROUTE VDDA TRACE APPROX.
50 mils WIDE (USE 2x25 mil TRACES TO
EXIT BALL FIELD) AND 500 mils LONG.
CPU_VDDA_RUN
R345
R345
169F
169F
C522 .1U_4 C522 .1U_4
4
U17
U17
NC7SZ08P5X_NL
NC7SZ08P5X_NL
C75 .1U_4 C75 .1U_4
4
U3
U3
NC7SZ08P5X_NL
NC7SZ08P5X_NL
C519 .1U_4 C519 .1U_4
4
U15
U15
NC7SZ08P5X_NL
NC7SZ08P5X_NL
6
KBSMDAT CPU_TEST5_THERMDC
7
KBSMCLK
8
5
+2.5V
C533
C533
100U/6.3V_3528
100U/6.3V_3528
CPU_CLKIN_SC_P
CPU_CLKIN_SC_N
CPU_ALL_PWROK
CPU_LDTSTOP#
CPU_HT_RESET#
+3V
R306
R306
10K_4
10K_4
1
Q26 2N7002E-LF Q26 2N7002E-LF
+3V
R347
R347
2
10K_4
10K_4
To SB GPIO
3
To FAN
CPU_VDDA_RUN
C532
MMBT3904Q3MMBT3904
R42 *0_4 R42 *0_4
CPUCLK 2
CPUCLK# 2
+1.8V
Q3
C532
4.7U/6.3V_6
4.7U/6.3V_6
R307
R307
300_4
300_4
R51
R51
300_4
300_4
+1.8V
R302
R302
300_4
300_4
R299 0_4 R299 0_4
R298 *0_4 R298 *0_4
R39
R39
330_4
330_4
2
1 3
D D
B2A:ATI suggestion
to avoid hynix ram
s3 issue
stuff R303,R299
del R298
CPU_PWRGD 12,13
C C
LDT_STOP# 10,12,13
LDT_RST# 12
EC_PWRGD 12,13,27
NB_PWRGD 10,27
B B
+1.8VSUS
R41
R41
300_4
300_4
H_PROCHOT#
L65
L65
BLM18PG330SN1D
BLM18PG330SN1D
C98
C98
C88
C88
.22U/6V_4
.22U/6V_4
3900p/25V_4
3900p/25V_4
C541 3900p/25V_4 C541 3900p/25V_4
C537 3900p/25V_4 C537 3900p/25V_4
+1.8V +3V
+1.8VSUS
R303
R303
4.7K/F_4
4.7K/F_4
5
1
2
+1.8VSUS
1
2
+1.8VSUS
1
2
3
5
3
5
3
+1.8V
B1A :Change P/N for ROHS
CPU_EC_PROCHOT# 27
CPU_PROCHOT# 13
CPU H/W MONITOR
+3V
A A
R348 47/F_6 R348 47/F_6
CPU_TEST4_THERMDA
10 mil trace /
10 mil space
15 MIL
3V_THM
C535
C535
.1U_4
.1U_4
C539
C539
2200P/50V_4
2200P/50V_4
5
Address 98H
U18 G781 U18 G781
1
VCC
3
DXN
SMDATA
2
DXP
-OVT4GND
SMCLK
-ALT
+1.8VSUS
MAX6648_AL# 13
MAX6648_OV# 28
4
If AMD SI is not used, the SID pin can be left unconnected and SIC
should have a 300-Ω (±5%) pulldown to VSS.
R308 *300 R308 *300
+1.8V
R309 *300 R309 *300
R311 300_4 R311 300_4
CPU_SIC_R
CPU_SID_R
place them to CPU within 1"
+1.8VSUS +3V
R587
R587
10K_4
10K_4
PSI# PSI_L
2
1 3
R586
R586
10K_4
10K_4
Q41
Q41
MMBT3904
MMBT3904
B1A :Change P/N for ROHS
SB_THERMTRIP# 13
separated input voltage
0104
+1.8V
R40 300_4 R40 300_4
4
R45 *330_4 R45 *330_4
H_THERMTRIP#
+3V
R327
R327
10K_4
10K_4
1
+3V
R317
R317
10K_4
10K_4
2
Q28
Q28
2
2N7002E-LF
2N7002E-LF
2
1
Q4
*MMBT3904Q4*MMBT3904
1 3
2
1 3
4.7K/F_4
4.7K/F_4
Q5
MMBT3904Q5MMBT3904
B1A :Change P/N for ROHS
3
MBDATA 27,35
Q27
Q27
2N7002E-LF
2N7002E-LF
3
MBCLK 27,35
To Power
R44
R44
PSI# 31
R43 4.7K/F_4 R43 4.7K/F_4
THERM_SYS_PWR 34
3
ATHLON Control and Debug
CPU_VDDA_RUN
CPU_HT_RESET#
T88T88
CPU_ALL_PWROK
T89T89
CPU_LDTSTOP#
R47 44.2F_4 R47 44.2F_4
R46 44.2F_4 R46 44.2F_4
CPU_VDDIO_SUS_FB_H
CPU_VDDIO_SUS_FB_L
T12T12
T19T19
T17T17
T32T32
T44T44
T41T41
T45T45
T42T42
T38T38
T20T20
T11T11
CPU_CLKIN_SC_P
CPU_CLKIN_SC_N
CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI
CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1
CPU_TEST17_BP3
CPU_TEST16_BP2
CPU_TEST15_BP1
CPU_TEST14_BP0
CPU_TEST12_SCANSHIFTENB
CPU_TEST07_ANALOG_T
CPU_TEST6_DIECRACKMON
CPU_TEST5_THERMDC
CPU_TEST4_THERMDA
CPU_TEST3_GATE0
CPU_TEST2_DRAIN0
CPU_RSVD_MA0_CLK3_P
CPU_RSVD_MA0_CLK3_N
CPU_RSVD_MA0_CLK0_P
CPU_RSVD_MA0_CLK0_N
CPU_RSVD_MB0_CLK3_P
CPU_RSVD_MB0_CLK3_N
CPU_RSVD_MB0_CLK0_P
CPU_RSVD_MB0_CLK0_N
R336 *300_4 R336 *300_4
R312 300_4 R312 300_4
R322 1K/F_4 R322 1K/F_4
R56 510/F_4 R56 510/F_4
R331 300_4 R331 300_4
R318 300_4 R318 300_4
R323 300_4 R323 300_4
R332 300_4 R332 300_4
R335 300_4 R335 300_4
R50 300_4 R50 300_4
R57 300_4 R57 300_4
R53 510/F_4 R53 510/F_4
R62 300_4 R62 300_4
R60 300_4 R60 300_4
COREFB+V 31
COREFB- 31
EC_PWRGD
3
VLDT_RUN
T36T36
T28T28
T14T14
T13T13
T96T96
T50T50
T46T46
T47T47
CPU_TEST27_SINGLECHAIN
CPU_TEST26_BURNIN#
CPU_PRESENT#
CPU_TEST25_H_BYPASSCLK_H
CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST24_SCANCLK1
CPU_TEST22_SCANSHIFTEN
CPU_TEST12_SCANSHIFTENB
CPU_TEST15_BP1
CPU_TEST14_BP0
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1
U20D
U20D
F8
VDDA2
F9
VDDA1
B7
RESET_L
A7
PWROK
F10
CPU_SIC_R
CPU_SID_R
CPU_HTREF1
CPU_HTREF0
LDTSTOP_L
AF4
SIC
AF5
SID
P6
HT_REF1
R6
HT_REF0
F6
VDD_FB_H
E6
VDD_FB_L
W9
VDDIO_FB_H
Y9
VDDIO_FB_L
A9
CLKIN_H
A8
CLKIN_L
G10
DBRDY
AA9
TMS
AC9
TCK
AD9
TRST_L
AF9
TDI
E9
TEST25_H
E8
TEST25_L
G9
TEST19
H10
TEST18
AA7
TEST13
C2
TEST9
D7
TEST17
E7
TEST16
F7
TEST15
C7
TEST14
AC8
TEST12
C3
TEST7
AA6
TEST6
W7
TEST5
W8
TEST4
Y6
TEST3
AB6
TEST2
P20
RSVD0
P19
RSVD1
N20
RSVD2
N19
RSVD3
R26
RSVD4
R25
RSVD5
P22
RSVD6
R22
RSVD7
+1.8VSUS
IF no use which Net
need pull-up or down
2
THERMTRIP_L
PROCHOT_L
VID5
VID4
VID3
VID2
VID1
VID0
CPU_PRESENT_L
PSI_L
DBREQ_L
TDO
TEST29_H
TEST29_L
TEST24
TEST23
TEST22
TEST21
TEST20
TEST28_H
TEST28_L
TEST27
TEST26
TEST10
TEST8
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
MISC
MISC
2
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
AMD NPT S1 SOCKET
Processor Socket
NOTE: HDT TERMINATION IS REQUIRED
FOR REV. Ax SILICON ONLY.
1
+1.8VSUS
R52
R52
300_4
300_4
H_THERMTRIP#
AF6
H_PROCHOT#
AC7
A5
C6
A6
A4
C5
B5
CPU_PRESENT#
AC6
A3
E10
AE9
C9
C8
AE7
AD7
AE8
AB8
AF7
J7
H8
AF8
AE6
K8
C4
H16
B18
B3
C1
H6
G6
D5
R24
W18
R23
AA8
H18
H19
PSI_L
T22T22
PSI_L is a Power Status Indicator signal. This signal is asserted
when the processor is in a low powerstate. PSI_L should be
connected to the power supply controller, if the controller
supports “skipmode, or diode emulation mode”. PSI_L is asserted by
the processor during the C3 and S1 states.
CPU_DBREQ#
CPU_TDO
CPU_TEST29_H_FBCLKOUT_P
CPU_TEST29_L_FBCLKOUT_N
+1.8VSUS
R349 220_4 R349 220_4
CPU_TRST#
CPU_TDO
ROUTE AS 80 Ohm DIFFERENTIAL PAIR
PLACE IT CLOSE TO CPU WITHIN 1"
CPU_TEST24_SCANCLK1
CPU_TEST23_TSTUPD
CPU_TEST22_SCANSHIFTEN
CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST28_H_PLLCHRZ_P
CPU_TEST28_L_PLLCHRZ_N
CPU_TEST27_SINGLECHAIN
CPU_TEST26_BURNIN#
CPU_TEST10_ANALOGOUT
CPU_TEST08_DIG_T
CPU_MA_RESET#
CPU_MB_RESET#
CPU_RSVD_VIDSTRB1
CPU_RSVD_VIDSTRB0
CPU_RSVD_VDDNB_FB_P
CPU_RSVD_VDDNB_FB_N
CPU_RSVD_CORE_TYPE
R339 220_4 R339 220_4
R54 220_4 R54 220_4
R338 220_4 R338 220_4
R343 220_4 R343 220_4
CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
LDT_RST#
VID5 31
VID4 31
VID3 31
VID2 31
VID1 31
VID0 31
R59 80.6F R59 80.6F
T90T90
T16T16
T30T30
T31T31
T18T18
T40T40
T43T43
T21T21
T15T15
T9T9
T10T10
T24T24
HDT CONNECTOR
T39T39
T37T37
T25T25
T33T33
T91T91
T27T27
T26T26
T87T87
PUT CLOSE ON LAYOUT
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
PROJECT :ZH3
PROJECT :ZH3
Quanta Computer Inc.
Quanta Computer Inc.
ATHLON64 CTRL & DEBUG
ATHLON64 CTRL & DEBUG
ATHLON64 CTRL & DEBUG
1
D
D
D
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of
of
53 6 Tuesday, June 27, 2006
53 6 Tuesday, June 27, 2006
53 6 Tuesday, June 27, 2006
5
D D
VCC_CORE VCC_CORE
C C
B B
U20E
U20E
AC4
VDD1
AD2
VDD2
G4
VDD3
H2
VDD4
J9
VDD5
J11
VDD6
J13
VDD7
K6
VDD8
K10
VDD9
K12
VDD10
K14
VDD11
L4
VDD12
L7
VDD13
L9
VDD14
L11
VDD15
L13
VDD16
M2
VDD17
M6
VDD18
M8
VDD19
M10
VDD20
N7
VDD21
N9
VDD22
N11
VDD23
P8
VDD24
P10
VDD25
R4
VDD26
R7
VDD27
R9
VDD28
R11
VDD29
T2
VDD30
T6
VDD31
T8
VDD32
T10
VDD33
T12
VDD34
T14
VDD35
U7
VDD36
U9
VDD37
U11
VDD38
U13
VDD39
V6
VDD40
V8
VDD41
V10
VDD42
Athlon 64 S1
Processor Socket
POWER
POWER
VDD43
VDD44
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51
VDD52
VDD53
VDD54
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27
V12
V14
W4
Y2
J15
K16
L15
M16
P16
T16
U15
V16
+1.8VSUS
H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17
P18
P21
P23
P25
R17
T18
T21
T23
T25
U17
V18
V21
V23
V25
Y25
4
U20F
U20F
AA11
AA13
AA15
AA17
AA19
AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21
AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23
AA4
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
AB2
VSS7
AB7
VSS8
AB9
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
AD6
VSS18
AD8
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
B4
VSS28
B6
VSS29
B8
VSS30
B9
VSS31
B11
VSS32
B13
VSS33
B15
VSS34
B17
VSS35
B19
VSS36
B21
VSS37
B23
VSS38
B25
VSS39
D6
VSS40
D8
VSS41
D9
VSS42
D11
VSS43
D13
VSS44
D15
VSS45
D17
VSS46
D19
VSS47
D21
VSS48
D23
VSS49
D25
VSS50
E4
VSS51
F2
VSS52
F11
VSS53
F13
VSS54
F15
VSS55
F17
VSS56
F19
VSS57
F21
VSS58
F23
VSS59
F25
VSS60
H7
VSS61
H9
VSS62
H21
VSS63
H23
VSS64
J4
VSS65
GROUND
GROUND
Athlon 64 S1
Processor Socket
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
M11
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6
3
2
1
BOTTOMSIDE DECOUPLING
VCC_CORE
C551
C79
C79
22U/10V_8
22U/10V_8
C107
C107
.22U/6V_4
.22U/6V_4
C152
C152
22U/10V_8
22U/10V_8
C551
22U/10V_8
22U/10V_8
C111
C111
.01U_4
.01U_4
C546
C546
22U/10V_8
22U/10V_8
C95
C95
180P_4
180P_4
C105
C105
22U/10V_8
22U/10V_8
3/6 AMD recommendation.
C117
C117
.22U/6V_4
.22U/6V_4
C124
C124
.22U/6V_4
.22U/6V_4
C275
C275
180P_4
180P_4
C85
C85
22U/10V_8
22U/10V_8
C274
C274
180P_4
180P_4
C104
C104
22U/10V_8
22U/10V_8
C149
C149
180P_4
180P_4
C108
C108
22U/10V_8
22U/10V_8
C158
C158
180P_4
180P_4
C109
C109
22U/10V_8
22U/10V_8
VCC_CORE
+1.8VSUS
C77
C77
22U/10V_8
22U/10V_8
C89
C89
.22U/6V_4
.22U/6V_4
C153
C153
22U/10V_8
22U/10V_8
DECOUPLING BETWEEN PROCESSOR AND DIMMs
PLACE CLOSE TO PROCESSOR AS POSSIBLE
+1.8VSUS
C120
C154
C154
4.7U/6.3V_6
4.7U/6.3V_6
C156
C156
4.7U/6.3V_6
4.7U/6.3V_6
C155
C155
4.7U/6.3V_6
4.7U/6.3V_6
C157
C157
4.7U/6.3V_6
4.7U/6.3V_6
C115
C115
.22U/6V_4
.22U/6V_4
C123
C123
.22U/6V_4
.22U/6V_4
C116
C116
.22U/6V_4
.22U/6V_4
C121
C121
.22U/6V_4
.22U/6V_4
C122
C122
.01U_4
.01U_4
C114
C114
.01U_4
.01U_4
C119
C119
10P_4
10P_4
C120
180P_4
180P_4
PROCESSOR POWER AND GROUND
A1
+5V
+1.2V
C9
.1U_4C9.1U_4
+5V
C375
C375
C78
C78
.1U_4
.1U_4
.1U_4
.1U_4
+3V
+5V
+5V
C637
C637
C368
C368
.1U_4
.1U_4
.1U_4
.1U_4
+3V
+3V +3V
+5V +3V
C487
C487
.1U_4
.1U_4
Athlon 64 S1g1
uPGA638
Top View
AF1
4
3
VLDT_RUN +3V
A A
VLDT_RUN
C59
C59
.1U_4
.1U_4
VIN +1.2V
C65
C65
.1U_4
.1U_4
+3V VLDT_RUN
C3
C74
C74
.1U_4C3.1U_4
.1U_4
.1U_4
VIN +3V
+3V
+1.2V
C8
.1U_4C8.1U_4
3/6 :ADD 0.1U CAPACITOR TO CROSS POWER PLANE.
5
A26
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
ATHLON64 PWR & GND
ATHLON64 PWR & GND
ATHLON64 PWR & GND
Date: Sheet
Date: Sheet
2
Date: Sheet
PROJECT :ZH3
PROJECT :ZH3
Quanta Computer Inc.
Quanta Computer Inc.
63 6 Tuesday, June 27, 2006
63 6 Tuesday, June 27, 2006
63 6 Tuesday, June 27, 2006
of
of
1
of
D
D
D
A
TERMINATOR DECOUPLING CAPACITOR DDR2 TERMINATOR
+0.9V_VTER
C293
C293
C335
C335
C339
C339
C312
C312
C281
.1U-16V_4
.1U-16V_4
10U/6.3V/X5R
10U/6.3V/X5R
4 4
+1.8VSUS
C350
C350
.1U-16V_4
.1U-16V_4
.1U-16V_4
.1U-16V_4
C309
C309
.1U-16V_4
.1U-16V_4
.1U-16V_4
.1U-16V_4
.1U-16V_4
.1U-16V_4
C336
C336
.1U-16V_4
.1U-16V_4
C264
C264
.1U-16V_4
.1U-16V_4
C281
.1U-16V_4
.1U-16V_4
.1U-16V_4
.1U-16V_4
C283
C283
C304
C304
.1U-16V_4
.1U-16V_4
C328
C328
.1U-16V_4
.1U-16V_4
C333
C333
.1U-16V_4
.1U-16V_4
C265
C265
.1U-16V_4
.1U-16V_4
C280
C280
.1U-16V_4
.1U-16V_4
C267
C267
.1U-16V_4
.1U-16V_4
C313
C313
.1U-16V_4
.1U-16V_4
.1U-16V_4
.1U-16V_4
C262
C262
C342
C342
.1U-16V_4
.1U-16V_4
C344
C344
.1U-16V_4
.1U-16V_4
B
C334
C334
.1U-16V_4
.1U-16V_4
C266
C266
.1U-16V_4
.1U-16V_4
C343
C343
.1U-16V_4
.1U-16V_4
C292
C292
.1U-16V_4
.1U-16V_4
C303
C303
.1U-16V_4
.1U-16V_4
C269
C269
.1U-16V_4
.1U-16V_4
C325
C325
.1U-16V_4
.1U-16V_4
C314
C314
.1U-16V_4
.1U-16V_4
C285
C285
.1U-16V_4
.1U-16V_4
C268
C268
.1U-16V_4
.1U-16V_4
C338
C338
+0.9V_VTER
C263
C263
.1U-16V_4
.1U-16V_4
C311
C311
.1U-16V_4
.1U-16V_4
C
+0.9V_VTER
M_A_CS#3
RN12 47_4P2R_S RN12 47_4P2R_S
1 2
M_A_A13
M_A_CAS#
M_ODT0
M_CKE0
M_CKE1
M_CKE2
M_CKE3
M_ODT3
M_B_WE#
M_B_A13
M_B_CS#3
M_A_CS#1
M_ODT1
M_B_CAS#
M_B_CS#1
4 3
RN9 47_4P2R_S RN9 47_4P2R_S
1 2
4 3
R175 47_4 R175 47_4
R176 47_4 R176 47_4
R195 47_4 R195 47_4
R197 47_4 R197 47_4
RN19 47_4P2R_S RN19 47_4P2R_S
1 2
4 3
RN32 47_4P2R_S RN32 47_4P2R_S
1 2
4 3
RN10 47_4P2R_S RN10 47_4P2R_S
1 2
4 3
RN20 47_4P2R_S RN20 47_4P2R_S
1 2
4 3
D
M_A_A2
M_A_A4
M_A_A3
M_A_A5
M_A_BS#1
M_A_A0
M_A_A7
M_A_A6
M_A_A1
M_A_A10
M_A_WE#
M_A_BS#0
M_A_A12
M_A_BS#2
M_A_A8
M_A_A11
M_A_CS#2
M_A_A9
M_A_RAS#
M_A_CS#0
M_A_A14
M_A_A15
RN15 47_4P2R_S RN15 47_4P2R_S
1 2
4 3
RN8 47_4P2R_S RN8 47_4P2R_S
1 2
4 3
RN14 47_4P2R_S RN14 47_4P2R_S
1 2
4 3
RN16 47_4P2R_S RN16 47_4P2R_S
1 2
4 3
RN7 47_4P2R_S RN7 47_4P2R_S
1 2
4 3
RN11 47_4P2R_S RN11 47_4P2R_S
1 2
4 3
RN5 47_4P2R_S RN5 47_4P2R_S
1 2
4 3
RN17 47_4P2R_S RN17 47_4P2R_S
1 2
4 3
RN6 47_4P2R_S RN6 47_4P2R_S
1 2
4 3
RN13 47_4P2R_S RN13 47_4P2R_S
1 2
4 3
RN18 47_4P2R_S RN18 47_4P2R_S
1 2
4 3
M_B_A10
M_B_BS#0
M_B_A4
M_B_A2
M_B_A5
M_B_A1
M_B_A6
M_B_A0
M_B_A3
M_B_A8
M_B_A11
M_B_A7
M_B_BS#2
M_B_CS#2
M_B_RAS#
M_B_BS#1
M_ODT2
M_B_CS#0
M_B_A12
M_B_A9
M_B_A15
M_B_A14
E
RN21 47_4P2R_S RN21 47_4P2R_S
1 2
4 3
RN29 47_4P2R_S RN29 47_4P2R_S
1 2
4 3
RN22 47_4P2R_S RN22 47_4P2R_S
1 2
4 3
RN30 47_4P2R_S RN30 47_4P2R_S
1 2
4 3
RN24 47_4P2R_S RN24 47_4P2R_S
1 2
4 3
RN31 47_4P2R_S RN31 47_4P2R_S
1 2
4 3
RN25 47_4P2R_S RN25 47_4P2R_S
1 2
4 3
RN28 47_4P2R_S RN28 47_4P2R_S
1 2
4 3
RN27 47_4P2R_S RN27 47_4P2R_S
1 2
4 3
RN23 47_4P2R_S RN23 47_4P2R_S
1 2
4 3
RN26 47_4P2R_S RN26 47_4P2R_S
1 2
4 3
+0.9V_VTER +0.9V_VTER
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
BA0
BA1
BA2
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
CK0
CK0
CK1
CK1
CKE0
CKE1
RAS
CAS
WE
S0
S1
ODT0
ODT1
SA0
SA1
SDA
SCL
VDDspd
VREF
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
+1.8VSUS
VDD081VDD182VDD287VDD388VDD495VDD596VDD6
CN22
CN22
REVERSE
(H=8)
59
103
111
104
112
117
118
DQ0
DQ1
VDD8
VDD7
VDD9
DQ2
VDD10
VDD11
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
NC1
NC2
NC3
NC4
NC/TEST
SO-DIMM
SO-DIMM
VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
VSS29
VSS2878VSS2777VSS2672VSS2571VSS2466VSS2365VSS2260VSS21
132
128
127
122
121
DDRII_SODIMM_R
DDRII_SODIMM_R
M_B_DQ4
5
M_B_DQ1
7
M_B_DQ7
17
M_B_DQ3
19
M_B_DQ5
4
M_B_DQ0
6
M_B_DQ6
14
M_B_DQ2
16
M_B_DQ8
23
M_B_DQ9
25
M_B_DQ15
35
M_B_DQ11
37
M_B_DQ13
20
M_B_DQ12
22
M_B_DQ14
36
M_B_DQ10
38
M_B_DQ16
43
M_B_DQ17
45
M_B_DQ18
55
M_B_DQ19
57
M_B_DQ20
44
M_B_DQ21
46
M_B_DQ22
56
M_B_DQ23
58
M_B_DQ25
61
M_B_DQ29
63
M_B_DQ27
73
M_B_DQ26
75
M_B_DQ28
62
M_B_DQ24
64
M_B_DQ30
74
M_B_DQ31
76
M_B_DQ32
123
M_B_DQ36
125
M_B_DQ34
135
M_B_DQ38
137
M_B_DQ33
124
M_B_DQ37
126
M_B_DQ39
134
M_B_DQ35
136
M_B_DQ41
141
M_B_DQ40
143
M_B_DQ42
151
M_B_DQ43
153
M_B_DQ45
140
M_B_DQ44
142
M_B_DQ46
152
M_B_DQ47
154
M_B_DQ48
157
M_B_DQ49
159
M_B_DQ50
173
M_B_DQ51
175
M_B_DQ52
158
M_B_DQ53
160
M_B_DQ55
174
M_B_DQ54
176
M_B_DQ61
179
M_B_DQ57
181
M_B_DQ58
189
M_B_DQ62
191
M_B_DQ56
180
M_B_DQ60
182
M_B_DQ59
192
M_B_DQ63
194
50
69
83
120
163
196
193
190
187
184
183
178
177
172
171
168
165
162
161
156
155
150
149
145
144
139
138
133
D
M_B_DQ[0..63] 4
M_B_CS#2 4
M_B_CS#3 4
+1.8VSUS
*10U/6.3V/X5R C301 *10U/6.3V/X5R C301
*10U/6.3V/X5R C324 *10U/6.3V/X5R C324
10U/10V/X5R_8 C345 10U/10V/X5R_8 C345
10U/10V/X5R_8 C282 10U/10V/X5R_8 C282
.1U_4 C279 .1U_4 C279
.1U_4 C310 .1U_4 C310
.1U_4 C286 .1U_4 C286
.1U_4 C287 .1U_4 C287
.1U_4 C341 .1U_4 C341
.1U_4 C327 .1U_4 C327
.1U_4 C305 .1U_4 C305
.1U_4 C349 .1U_4 C349
.1U_4 C329 .1U_4 C329
.1U_4 C347 .1U_4 C347
.1U_4 C346 .1U_4 C346
.1U_4 C332 .1U_4 C332
.1U_4 C307 .1U_4 C307
.1U_4 C289 .1U_4 C289
.1U_4 C288 .1U_4 C288
.1U_4 C306 .1U_4 C306
.1U_4 C348 .1U_4 C348
.1U_4 C330 .1U_4 C330
.1U_4 C308 .1U_4 C308
.1U_4 C331 .1U_4 C331
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
DDR2 SO-DIMM
DDR2 SO-DIMM
DDR2 SO-DIMM
Date: Sheet
Date: Sheet of
Date: Sheet of
PROJECT :ZH3
PROJECT :ZH3
Quanta Computer Inc.
Quanta Computer Inc.
of
73 6 Tuesday, June 27, 2006
73 6 Tuesday, June 27, 2006
73 6 Tuesday, June 27, 2006
E
D
D
D
+1.8VSUS
103
111
104
112
117
M_A_A[0..15] 4
3 3
M_A_BS#0 4
M_A_BS#1 4
M_A_BS#2 4
M_A_DM[0..7] 4
M_A_DQS[0..7] 4
M_A_DQS#[0..7] 4
+1.8VSUS
M_CLKOUT0 4
M_CLKOUT0# 4
M_CLKOUT1 4
M_CLKOUT1# 4
M_CLKOUT0
C130
C130
1.5P_4
1.5P_4
M_CLKOUT0#
M_CLKOUT1
C113
C113
1.5P_4
1.5P_4
M_CLKOUT1#
+3V
PDAT_SMB 2,13,17,19,30
PCLK_SMB 2,13,17,19,30
C290 .1U_4 C290 .1U_4
A
MVREF_DIM
C295
C295
2.2U/10V/X5R
2.2U/10V/X5R
1 2
2 2
1 1
M_CKE0 4
M_CKE1 4
M_A_RAS# 4
M_A_CAS# 4
M_A_WE# 4
M_A_CS#0 4
M_A_CS#1 4
M_ODT0 4
M_ODT1 4
C294 .1U_4 C294 .1U_4
C291
C291
.1U_4
.1U_4
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
102
A0
101
A1
VDD081VDD182VDD287VDD388VDD495VDD596VDD6
100
A2
99
A3
98
A4
97
A5
94
A6
92
A7
CN19
A8
A9
A10
A11
A12
A13
A14
A15
BA0
BA1
BA2
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
CK0
CK0
CK1
CK1
CKE0
CKE1
RAS
CAS
WE
S0
S1
ODT0
ODT1
SA0
SA1
SDA
SCL
VDDspd
VREF
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
CN19
REVERSE
(H=4)
59
93
91
105
90
89
116
86
84
107
106
85
10
26
52
67
130
147
170
185
13
31
51
70
131
148
169
188
11
29
49
68
129
146
167
186
30
32
164
166
79
80
108
113
109
110
115
114
119
198
200
195
197
199
1
2
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
118
5
DQ0
7
DQ1
VDD8
VDD7
VDD9
17
DQ2
VDD10
VDD11
19
DQ3
4
DQ4
6
DQ5
14
DQ6
16
DQ7
23
DQ8
25
DQ9
35
DQ10
37
DQ11
20
DQ12
22
DQ13
36
DQ14
38
DQ15
43
DQ16
45
DQ17
55
DQ18
57
DQ19
44
DQ20
46
DQ21
56
DQ22
58
DQ23
61
DQ24
63
DQ25
73
DQ26
75
DQ27
62
DQ28
64
DQ29
74
DQ30
76
DQ31
123
DQ32
125
DQ33
135
DQ34
137
DQ35
124
DQ36
126
DQ37
134
DQ38
136
DQ39
141
DQ40
143
DQ41
151
DQ42
153
DQ43
140
DQ44
142
DQ45
152
DQ46
154
DQ47
157
DQ48
159
DQ49
173
DQ50
175
DQ51
158
DQ52
160
DQ53
174
DQ54
176
DQ55
179
DQ56
181
DQ57
189
DQ58
191
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
50
NC1
69
NC2
83
NC3
120
NC4
163
NC/TEST
SO-DIMM
SO-DIMM
VSS29
VSS2878VSS2777VSS2672VSS2571VSS2466VSS2365VSS2260VSS21
121
VSS31
VSS30
127
122
VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
VSS33
VSS32
132
128
DDRII_SODIMM_R
DDRII_SODIMM_R
B
196
193
190
187
184
183
178
177
172
171
168
165
162
161
156
155
150
149
145
144
139
138
133
M_A_DQ1
M_A_DQ0
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ7
M_A_DQ6
M_A_DQ12
M_A_DQ8
M_A_DQ10
M_A_DQ11
M_A_DQ9
M_A_DQ13
M_A_DQ15
M_A_DQ14
M_A_DQ17
M_A_DQ21
M_A_DQ23
M_A_DQ18
M_A_DQ20
M_A_DQ19
M_A_DQ22
M_A_DQ16
M_A_DQ29
M_A_DQ28
M_A_DQ31
M_A_DQ30
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ32
M_A_DQ36
M_A_DQ37
M_A_DQ35
M_A_DQ33
M_A_DQ38
M_A_DQ34
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ46
M_A_DQ44
M_A_DQ45
M_A_DQ43
M_A_DQ47
M_A_DQ49
M_A_DQ52
M_A_DQ50
M_A_DQ51
M_A_DQ53
M_A_DQ48
M_A_DQ55
M_A_DQ54
M_A_DQ60
M_A_DQ56
M_A_DQ58
M_A_DQ63
M_A_DQ57
M_A_DQ61
M_A_DQ59
M_A_DQ62
M_A_CS#2 4
M_A_CS#3 4
+0.9V_REF
R194
R194
+1.8VSUS
*0_4
*0_4
C323
C323
1U/10V_4
1U/10V_4
M_A_DQ[0..63] 4
M_CLKOUT3
C125
C125
1.5P_4
1.5P_4
M_CLKOUT3#
M_CLKOUT4
C127
C127
1.5P_4
1.5P_4
M_CLKOUT4#
MVREF_DIM
M_B_A[0..15] 4
M_B_BS#0 4
M_B_BS#1 4
M_B_BS#2 4
M_B_DM[0..7] 4
M_B_DQS[0..7] 4
M_B_DQS#[0..7] 4
M_CLKOUT3 4
M_CLKOUT3# 4
M_CLKOUT4 4
M_CLKOUT4# 4
R196 0_4 R196 0_4
R198 10K_4 R198 10K_4
+3V
+3V
C321 .1U_4 C321 .1U_4
C337
C337
2.2U/10V/X5R
2.2U/10V/X5R
1 2
+1.8VSUS
R177
R177
1K/F_4
1K/F_4
R178
R178
1K/F_4
1K/F_4
1.This part should not contain any substances which are specified in SS-00259-1
2.Purchase ink, paint, wire rods and molding resins only from the business partners that Sony approves as Green Partners.
M_CLKOUT3
M_CLKOUT3#
M_CLKOUT4
M_CLKOUT4#
M_CKE2 4
M_CKE3 4
M_B_RAS# 4
M_B_CAS# 4
M_B_WE# 4
M_B_CS#0 4
M_B_CS#1 4
M_ODT2 4
M_ODT3 4
PDAT_SMB
PCLK_SMB
C320 .1U_4 C320 .1U_4
MVREF_DIM
C322
C322
.1U_4
.1U_4
C
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
102
101
100
99
98
97
94
92
93
91
105
90
89
116
86
84
107
106
85
10
26
52
67
130
147
170
185
13
31
51
70
131
148
169
188
11
29
49
68
129
146
167
186
30
32
164
166
79
80
108
113
109
110
115
114
119
198
200
195
197
199
1
2
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
5
D D
U12A
U12A
R19
AC21
AB22
AB20
AA20
AA19
AA25
AA24
AB23
AA23
AB24
AB25
AC24
AC25
R18
R21
R22
U22
U21
U18
U19
W19
W20
Y19
T24
R25
U25
U24
V23
U23
V24
V25
W21
W22
Y24
W25
P24
P25
A24
C24
HT_RXCAD15P
HT_RXCAD15N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD7P
HT_RXCAD7N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD0P
HT_RXCAD0N
HT_RXCLK1P
HT_RXCLK1N
HT_RXCLK0P
HT_RXCLK0N
HT_RXCTLP
HT_RXCTLN
HT_RXCALP
HT_RXCALN
RS485M A11 HT
RS485M A11 HT
PART 1 OF 5
PART 1 OF 5
HYPER TRANSPORT CPU I/F
HYPER TRANSPORT CPU I/F
HT_CADOUT15_P 3
HT_CADOUT15_N 3
HT_CADOUT14_P 3
HT_CADOUT14_N 3
HT_CADOUT13_P 3
HT_CADOUT13_N 3
HT_CADOUT12_P 3
HT_CADOUT12_N 3
HT_CADOUT11_P 3
HT_CADOUT11_N 3
HT_CADOUT10_P 3
HT_CADOUT10_N 3
HT_CADOUT9_P 3
HT_CADOUT9_N 3
HT_CADOUT8_P 3
HT_CADOUT8_N 3
HT_CADOUT7_P 3
C C
VDDHT_PKG
B B
HT_CADOUT7_N 3
HT_CADOUT6_P 3
HT_CADOUT6_N 3
HT_CADOUT5_P 3
HT_CADOUT5_N 3
HT_CADOUT4_P 3
HT_CADOUT4_N 3
HT_CADOUT3_P 3
HT_CADOUT3_N 3
HT_CADOUT2_P 3
HT_CADOUT2_N 3
HT_CADOUT1_P 3
HT_CADOUT1_N 3
HT_CADOUT0_P 3
HT_CADOUT0_N 3
HT_CLKOUT1_P 3
HT_CLKOUT1_N 3
HT_CLKOUT0_P 3
HT_CLKOUT0_N 3
HT_CTLOUT0_P 3
HT_CTLOUT0_N 3
R295 49.9/F_4 R295 49.9/F_4 R33 100/F_4 R33 100/F_4
R294
R294
49.9/F_4
49.9/F_4
HT_RXCALP
HT_RXCALN
4
HT_TXCAD15P
HT_TXCAD15N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD0P
HT_TXCAD0N
HT_TXCLK1P
HT_TXCLK1N
HT_TXCLK0P
HT_TXCLK0N
HT_TXCTLP
HT_TXCTLN
HT_TXCALP
HT_TXCALN
P21
P22
P18
P19
M22
M21
M18
M19
L18
L19
G22
G21
J20
J21
F21
F22
N24
N25
L25
M24
K25
K24
J23
K23
G25
H24
F25
F24
E23
F23
E24
E25
L21
L22
J24
J25
N23
P23
C25
D24
HT_TXCALP
HT_TXCALN
HT_CADIN15_P 3
HT_CADIN15_N 3
HT_CADIN14_P 3
HT_CADIN14_N 3
HT_CADIN13_P 3
HT_CADIN13_N 3
HT_CADIN12_P 3
HT_CADIN12_N 3
HT_CADIN11_P 3
HT_CADIN11_N 3
HT_CADIN10_P 3
HT_CADIN10_N 3
HT_CADIN9_P 3
HT_CADIN9_N 3
HT_CADIN8_P 3
HT_CADIN8_N 3
HT_CADIN7_P 3
HT_CADIN7_N 3
HT_CADIN6_P 3
HT_CADIN6_N 3
HT_CADIN5_P 3
HT_CADIN5_N 3
HT_CADIN4_P 3
HT_CADIN4_N 3
HT_CADIN3_P 3
HT_CADIN3_N 3
HT_CADIN2_P 3
HT_CADIN2_N 3
HT_CADIN1_P 3
HT_CADIN1_N 3
HT_CADIN0_P 3
HT_CADIN0_N 3
HT_CLKIN1_P 3
HT_CLKIN1_N 3
HT_CLKIN0_P 3
HT_CLKIN0_N 3
HT_CTLIN0_P 3
HT_CTLIN0_N 3
3
2
1
A A
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
RS485-HT LINK0 I/F
RS485-HT LINK0 I/F
RS485-HT LINK0 I/F
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
PROJECT :ZH3
PROJECT :ZH3
Quanta Computer Inc.
Quanta Computer Inc.
of
of
of
83 6 Tuesday, June 27, 2006
83 6 Tuesday, June 27, 2006
1
83 6 Tuesday, June 27, 2006
D
D
D
5
D D
C C
B B
4
EZ4
EZ4
WLAN
10KOhm FOR RS485
R27:
1.47KOhm FOR
RS690
8.25KOhm FOR RS485
R29:
DNI FOR RS690
PCIE_RXP0 30
PCIE_RXN0 30
PCIE_RXP1 30
PCIE_RXN1 30
PCIE_RXP3 19
PCIE_RXN3 19
A_RX0P 12
A_RX0N 12
A_RX1P 12
A_RX1N 12
3
R27 10K_4 R27 10K_4
R29 8.25K/F_6 R29 8.25K/F_6
U12B
U12B
G5
GFX_RX0P
G4
GFX_RX0N
J8
GFX_RX1P
J7
GFX_RX1N
J4
GFX_RX2P
J5
GFX_RX2N
L8
GFX_RX3P
L7
GFX_RX3N
L4
GFX_RX4P
L5
GFX_RX4N
M8
GFX_RX5P
M7
GFX_RX5N
M4
GFX_RX6P
M5
GFX_RX6N
P8
GFX_RX7P
P7
GFX_RX7N
P4
GFX_RX8P
P5
GFX_RX8N
R4
GFX_RX9P
R5
GFX_RX9N
R7
GFX_RX10P
R8
GFX_RX10N
U4
GFX_RX11P
U5
GFX_RX11N
W4
GFX_RX12P
W5
GFX_RX12N
Y4
GFX_RX13P
Y5
GFX_RX13N
V9
GFX_RX14P
W9
GFX_RX14N
AB7
GFX_RX15P
AB6
GFX_RX15N
W11
GPP_RX0P
W12
GPP_RX0N
AA11
GPP_RX1P
AB11
GPP_RX1N
Y7
GPP_RX2P
AA7
GPP_RX2N
AB9
GPP_RX3P
AA9
GPP_RX3N
W14
SB_RX0P
W15
SB_RX0N
AB12
SB_RX1P
AA12
SB_RX1N
AA14
PCE_ISET(PCE_CALI)
AB14
PCE_TXISET(NC)
RS485M A11 HT
RS485M A11 HT
PART 2 OF 5
PART 2 OF 5
PCIE I/F GFX
PCIE I/F GFX
PCIE I/F GPP
PCIE I/F GPP
PCIE I/F SB
PCIE I/F SB
PCE_PCAL(PCE_CALRP)
PCE_NCAL(PCE_CALRN)
GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
2
J1
H2
K2
K1
K3
L3
L1
L2
N2
N1
P2
P1
P3
R3
R1
R2
T2
U1
V2
V1
V3
W3
W1
W2
Y2
AA1
AA2
AB2
AB1
AC1
AE3
AE4
AD8
AE8
AD7
AE7
AD4
AE5
AD5
AD6
AE9
AD10
AC8
AD9
AD11
AE11
GPP_TX0P_C
GPP_TX0N_C
GPP_TX1P_C
GPP_TX1N_C
GPP_TX3P_C
GPP_TX3N_C
A_TX0P_C
A_TX0N_C
A_TX1P_C
A_TX1N_C
R28 150/F_4 R28 150/F_4
R26 100/F_4 R26 100/F_4
C35 .1U_4 C35 .1U_4
C34 .1U_4 C34 .1U_4
C20 .1U_4 C20 .1U_4
C25 .1U_4 C25 .1U_4
C16 .1U_4 C16 .1U_4
C17 .1U_4 C17 .1U_4
C31 .1U_4 C31 .1U_4
C36 .1U_4 C36 .1U_4
C22 .1U_4 C22 .1U_4
C27 .1U_4 C27 .1U_4
VDDA12_PKG2
Place these caps
close to connector
PCIE_TXP3 19
PCIE_TXN3 19
A_TX0P 12
A_TX0N 12
A_TX1P 12
A_TX1N 12
150 Ohm FOR RS485
R28:
562 Ohm FOR RS690
R26:
Ward update to 100 Ohm FOR RS485
2KOhm FOR RS690
1
PCIE_TXP0 30
PCIE_TXN0 30
PCIE_TXP1 30
PCIE_TXN1 30
EZ4
EZ4
WLAN
A A
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
RS485-PCIE LINK I/F
RS485-PCIE LINK I/F
RS485-PCIE LINK I/F
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
PROJECT :ZH3
PROJECT :ZH3
Quanta Computer Inc.
Quanta Computer Inc.
of
of
of
93 6 Tuesday, June 27, 2006
93 6 Tuesday, June 27, 2006
1
93 6 Tuesday, June 27, 2006
D
D
D
+1.8V
L7
L7
BK1608HS330
BK1608HS330
5
HTPVDD
C504
C504
10U/10V/X5R_8
10U/10V/X5R_8
C60
C60
4.7U/6.3V_6
4.7U/6.3V_6
L55
L55
BK1608HS330
BK1608HS330
AVDDQ +1.8V
C498
C498
10U/10V/X5R_8
10U/10V/X5R_8
4
C499
C499
2.2U/10V/X5R
2.2U/10V/X5R
1 2
+3V
L6
L6
BK1608HS330
BK1608HS330
AVDD_NB
C57
C57
4.7U/6.3V_6
4.7U/6.3V_6
3
+1.8V AVDD1
R290 0/F_6 R290 0/F_6
C495
C55
C55
.1U_4
.1U_4
C495
2.2U/10V/X5R
2.2U/10V/X5R
1 2
2
1
+1.8V PLLVDD
L52
D D
C C
L52
BK1608HS330
BK1608HS330
LDT_STOP# 5,12,13
C492
C492
10U/10V/X5R_8
10U/10V/X5R_8
C491
C491
4.7U/6.3V_6
4.7U/6.3V_6
+1.8V +3V
R14
R14
10K_4
10K_4
2
1 3
Q1
Q1
MMBT3904
MMBT3904
TV_C/R_SYS 30
TV_Y/G_SYS 30
TV_COMP_SYS 30
R16
R16
1K/F_4
1K/F_4
LDT_STOP#_NB
VGA_RED 16
VGA_GRN 16
VGA_BLU 16
B1A :Change P/N for ROHS
+3V
R17 2K/F R17 2K/F
B B
A A
R15 10K_4 R15 10K_4
STRP_DATA
TV_SWITCH
5
LOAD_ROM#: LOAD ROM STRAP ENABLE
High, LOAD ROM STRAP DISABLE
Low, LOAD ROM STRAP ENABLE
R36
R36
150/F_6
150/F_6
150/F_6
150/F_6
close to NB
R30
R30
150/F_6
150/F_6
close to NB
R37
R37
150/F_6
150/F_6
R31
R31
150/F_6
150/F_6
4
R38
R38
R32
R32
150/F_6
150/F_6
NB_PWRGD 5,27
NBSRC_CLKP 2
NBSRC_CLKN 2
SBLINK_CLKP 2
SBLINK_CLKN 2
R22 3K/F_4 R22 3K/F_4
BMREQ# 12
U12C
AVDD_NB
AVDDQ
CRTDCLK 16
CRTDDAT 16
ALINK_RST# 12,19,23,26,30
NB_OSC 2
D14 RB751 D14 RB751
2 1
R282 0_4 R282 0_4
LOAD_ROM#
ALLOW_LDTSTOP 12
PHL_CLK 16,29,30
PHL_DATA 16,29
TMDS_HPD 29
DDC_DATA 29,30
R18
R18
4.7K/F_4
4.7K/F_4
AVDD1
C497
C497
.1U_4
.1U_4
VSYNC 16
HSYNC 16
R20 0_4 R20 0_4
R19 0_4 R19 0_4
PLLVDD
HTPVDD
R286 0_4 R286 0_4
HTREFCLK 2
T79T79
R23 *2.7K_4 R23 *2.7K_4
R24 *2.7K_4 R24 *2.7K_4
R283 *2.7K_4 R283 *2.7K_4
R284 *2.7K_4 R284 *2.7K_4
R285 *2.7K_4 R285 *2.7K_4
T4T4
T5T5
TV_C/R_SYS
TV_Y/G_SYS
TV_COMP_SYS
R291 715/F R291 715/F
NB_RST#
LDT_STOP#_NB
R34 10K_4 R34 10K_4
TV_SWITCH
PLLVDD12
DFT_GPIO0
DFT_GPIO2
DFT_GPIO3
DFT_GPIO4
DFT_GPIO5
3
STRP_DATA
U12C
B22
AVDD1
C22
AVDD2
G17
AVSSN1
H17
AVSSN2
A20
AVDDDI
B20
AVSSDI
A21
AVDDQ
A22
AVSSQ
C21
C_R
C20
Y_G
D19
COMP_B
E19
RED
F19
GREEN
G19
BLUE
C6
DACVSYNC
A5
DACHSYNC
B21
RSET
B6
DACSCL
A6
DACSDA
A10
PLLVDD(PLLVDD18)
B10
PLLVSS
B24
HTPVDD
B25
HTPVSS
C10
SYSRESET#
C11
POWERGOOD
C5
LDTSTOP#
B5
ALLOW_LDTSTOP
C23
HTTSTCLK
B23
HTREFCLK
C2
TVCLKIN
B11
OSCIN
A11
OSCOUT(PLLVDD12)
F2
GFX_CLKP
E1
GFX_CLKN
G1
SB_CLKP
G2
SB_CLKN
D6
DFT_GPIO0
D7
DFT_GPIO1
C8
DFT_GPIO2
C7
DFT_GPIO3
B8
DFT_GPIO4
A8
DFT_GPIO5
B2
BMREQb
A2
I2C_CLK
B4
I2C_DATA
AA15
THERMALDIODE_P
AB15
THERMALDIODE_N
C14
TMDS_HPD
B3
DDC_DATA
C3
TESTMODE
A3
STRP_DATA
RS485M A11 HT
RS485M A11 HT
PART 3 OF 5
PART 3 OF 5
CRT/TVOUT
CRT/TVOUT
LVDS
LVDS
PLL PWR
PLL PWR
PM
PM
CLOCKs
CLOCKs
DVO_D0(GPP_TX4P)
DVO_D1(GPP_TX4N)
DVO_D3(GPP_RX4P)
DVO_D4(GPP_RX4N)
DVO_D7(GPP_TX5N)
DVO_D8(GPP_TX5P)
DVO_D9(GPP_RX5N)
DVO
DVO
MIS.
MIS.
DVO_D10(GPP_RX5P)
DVO_VSYNC(NC)
DVO_HSYNC(NC)
DVO_IDCKP(NC)
DVO_IDCKN(NC)
RS485
OSCOUT(A11)
DVO_D0(AD14)
DVO_D1(AD15) DVO_D1
DVO_D3(AD16)
DVO_D7(AE19)
DVO_D8(AD19)
DVO_D9(AE20)
DVO_D10(AD20)
OSCOUT
DVO_D0
DVO_D3
DVO_D4
DVO_D7
DVO_D8
DVO_D9
DVO_D10
TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N
TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N
TXCLK_LP
TXCLK_LN
TXCLK_UP
TXCLK_UN
LPVDD
LPVSS
LVDDR18D_1
LVDDR18D_2
LVDDR18A_1
LVDDR18A_2
LVSSR1
LVSSR3
LVSSR5
LVSSR6
LVSSR7
LVSSR8
LVSSR12
LVSSR13
LVDS_DIGON
LVDS_BLON
LVDS_BLEN
DVO_D2(NC)
DVO_D5(NC)
DVO_D6(NC)
DVO_D11(NC)
DVO_DE(NC)
RS690
PLLVDD12
GPP_TX4P
GPP_TX4N
GPP_RX4P
GPP_RX4N DVO_D4(AE16)
GPP_TX5N
GPP_TX5P
GPP_RX5N
GPP_RX5P
2
B14
B15
B13
A13
H14
G14
D17
E17
A15
B16
C17
C18
B17
A17
A18
B18
E15
D15
H15
G15
D14
E14
A12
B12
C12
C13
A16
A14
D12
C19
C15
C16
F14
F15
E12
G12
F12
AD14
AD15
AE15
AD16
AE16
AC17
AD18
AE19
AD19
AE20
AD20
AE21
AD13
AC13
AE13
AE17
AD17
TXLOUT0+ 16
TXLOUT0- 16
TXLOUT1+ 16
TXLOUT1- 16
TXLOUT2+ 16
TXLOUT2- 16
T80T80
T81T81
T7T7
T86T86
T82T82
T85T85
T84T84
T83T83
TXLCLKOUT+ 16
TXLCLKOUT- 16
T1T1
T3T3
C40
C40
.1U_4
.1U_4
C493
C493
.1U_4
.1U_4
LCD_PON
R289 0_4 R289 0_4
LVDS_BLON
T2T2
LVDS_BLON
NB_PWRGD
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
RS485-SYSTEM I/F & DVO
RS485-SYSTEM I/F & DVO
RS485-SYSTEM I/F & DVO
Date: Sheet
Date: Sheet
Date: Sheet
L5 BK1608HS330 L5 BK1608HS330
C51
C51
4.7U/6.3V_6
4.7U/6.3V_6
DVO_D0 29
DVO_D1 29
DVO_D2 29
DVO_D3 29
DVO_D4 29
DVO_D5 29
DVO_D6 29
DVO_D7 29
DVO_D8 29
DVO_D9 29
DVO_D10 29
DVO_D11 29
DVO_VSYNC 29
DVO_DE 29
DVO_HSYNC 29
DVO_IDCKP 29
DVO_IDCKN 29
Quanta Computer Inc.
Quanta Computer Inc.
L53
L53
BK1608HS330
BK1608HS330
C494
C494
4.7U/6.3V_6
4.7U/6.3V_6
LCD_POWER_ON 16
LCD_PON
LVDS_BLON
+3V
5 3
1
R287 0_4 R287 0_4
4
2
U11
U11
NC7SZ08P5X_NL
NC7SZ08P5X_NL
PROJECT :ZH3
PROJECT :ZH3
1
RS485: LVDDR18A=1.8V
+1.8V
+1.8V
L54
L54
BK1608HS330
BK1608HS330
C44
C44
C46
C46
.1U_4
.1U_4
4.7U/6.3V_6
4.7U/6.3V_6
R288 2K/F_4 R288 2K/F_4
R25 2.7K/F_4 R25 2.7K/F_4
BLON 16
of
of
of
10 36 Tuesday, June 27, 2006
10 36 Tuesday, June 27, 2006
10 36 Tuesday, June 27, 2006
D
D
D
5
V12
M3
VSSA2
D D
VLDT_RUN
80 ohm(4A)
VSSA1
VSS1
A25
PAR 5 OF 5
PAR 5 OF 5
F11
VSS2
V11
VSSA3
VSS3
D23
V14
VSSA4
VSS4E9VSS5
G11
4
VSS17
L23
M11
VSS18
VSS19
M20
VSS20
M23
VSS21
M25
P9
VSS22
N12
N14
VSSA23
VSS23
VSS24
B7
L24
AE6
AE10
V15
G3
VSSA5F3VSSA6
VSSA7A1VSSA8H1VSSA9
VSSA10J2VSSA11H3VSSA13J6VSSA15F1VSSA16L6VSSA17M2VSSA18M6VSSA19J3VSSA20P6VSSA21T1VSSA22N3VSSA24R6VSSA25U2VSSA26T3VSSA27U3VSSA28U6VSSA30Y1VSSA32W6VSSA33
VSSA14
VSSA12
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
J22
J12
L12
L14
M15
L20
G23
Y23
P11
R24
AE18
VSS25
VSS26
P13
VSS27
P20
P15
AC4
VSS28
R12
VSSA29
VSS29
R14
AC2
Y11
Y15
VSSA34Y3VSSA35Y9VSSA36
VSSA31
GROUND
GROUND
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
Y25
R20
U20
H25
W23
W24
AD25
AD1
AC5
AC6
VSSA37R9VSSA38
VSSA39
VSS37
VSS38
VSS39
Y22
D25
AC23
AC7
AD3
VSSA40
VSSA41
VSS40
VSS41
G24
AC14
3
AC9
AC10
VSSA42
VSSA43
VSS42
VSS43
H12
AC22
G6
Y12
VSSA44
VSSA45
VSS44
VSS45
R23
Y14
AA3
VSSA46
VSSA47
VSSA48
VSS46C4VSS47
VSS48
T23
AE22
VSS49
T25
VSS50
AE14
VSS51
R17
VSS52
H23
VSS53
M17
VSS54
A23
VSS55
AC15
VSS56
VSS57D4VSS59
F17
VSS58
AC16
M13
U12E
U12E
RS485M A11 HT
RS485M A11 HT
2
1
+1.2V
80 ohm(4A)
L51
L51
FBJ3216HS800
C482
C482
10U/10V/X5R_8
10U/10V/X5R_8
C32
C32
1U/10V_4
1U/10V_4
C33
C33
1U/10V_4
1U/10V_4
FBJ3216HS800
C483
C483
100U/6.3V_3528
100U/6.3V_3528
C38
C38
1U/10V_4
1U/10V_4
C484
C484
100U/6.3V_3528
100U/6.3V_3528
+1.2V
NB RS485 POWER STATES
Power Signal
VDDHT
VDDR
VDD18
VDDC
VDDA18
VDDA12
S0
ON
ON
ON
ON
ON
ON
ON
AVDDDI
PLLVDD
HTPVDD
VDDR3
LPVDD
LVDDR18D
ON
ON
ON
ON
ON
ON
LVDDR18A OFF ON ON OFF OFF
S3
S1
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF AVDD
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
S4/S5
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
G3
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
VDDA12
U12D
C61
C61
C62
C62
10U/10V/X5R_8
10U/10V/X5R_8
10U/10V/X5R_8
C C
+3V
+1.8V VDD18
+1.8V VDDA18
L50 BLM18PG330SN1D L50 BLM18PG330SN1D
33 ohm (3000mA)
+3V VDDR3
L2 TI201209G121 L2 TI201209G121
B B
VDDA12
10U/10V/X5R_8
D16
D16
D17
D17
2 1
2 1
SW1010C
SW1010C
L3 TI201209G121 L3 TI201209G121
SW1010C
SW1010C
RS485: VDDA18=1.8V
C489
C489
10U/10V/X5R_8
10U/10V/X5R_8
+1.8V
L4 TI201209G121 L4 TI201209G121
R21 0/F_6 R21 0/F_6
RS485: 0 Ohm RESISTOR
A A
C56
C56
1U/10V_4
1U/10V_4
D15
D15
2 1
SW1010C
SW1010C
C45
C45
1U/6.3V_6
1U/6.3V_6
C486
C486
100U/6.3V_3528
100U/6.3V_3528
C30
C30
4.7U/6.3V_6
4.7U/6.3V_6
VDDDVO
C43
C43
1U/10V_4
1U/10V_4
C19
C19
4.7U/6.3V_6
4.7U/6.3V_6
C29
C29
1U/6.3V_6
1U/6.3V_6
VDDPLL
C54
C54
1U/10V_4
1U/10V_4
C37
C37
C18
C18
1U/10V_4
1U/10V_4
C42
C42
1U/10V_4
1U/10V_4
1U/6.3V_6
1U/6.3V_6
C52
C49
C49
1U/10V_4
1U/10V_4
C52
1U/10V_4
1U/10V_4
C58
C58
1U/10V_4
1U/10V_4
20mil trace width
C39
C39
1U/6.3V_6
1U/6.3V_6
C10
C10
C21
C21
1U/10V_4
1U/10V_4
1U/10V_4
1U/10V_4
20mil trace width
20mil trace width
20mil trace width
C48
C48
1U/10V_4
1U/10V_4
VDDA12_PKG1
C28
C28
1U/10V_4
1U/10V_4
C14
C14
1U/10V_4
1U/10V_4
1U/10V_4
1U/10V_4
VDDHT_PKG
VDDA12_PKG1
VDDA12_PKG2
C488
C488
10U/10V/X5R_8
10U/10V/X5R_8
C26
C26
C490
C490
1U/10V_4
1U/10V_4
?
U12D
AE24
VDD_HT1
AD24
VDD_HT2
AD22
VDD_HT3
AB17
VDD_HT4
AE23
VDD_HT5
Y17
VDD_HT6
W17
VDD_HT7
AC18
VDD_HT8
AD21
VDD_HT9
AC19
VDD_HT10
AC20
VDD_HT11
AB19
VDD_HT12
AD23
VDD_HT13
AA17
VDD_HT14
AE25
VDD_HT15
J14
VDD18_1
J15
VDD18_2
AE2
VDDA18_1(VDDA12_13)
AB3
VDDA18_2(VDDA12_14)
U7
VDDA18_3(VDDA12_15)
W7
VDDA18_4(VDDA12_16)
AB4
VDDA18_5(VDDA12_17)
AC3
VDDA18_6(VDDA12_18)
AD2
VDDA18_7(VDDA12_19)
AE1
VDDA18_8(VDDA12_20)
E11
VDDR3_1
D11
VDDR3_2
AC12
VDD_DVO1(VDDR_1)
AD12
VDD_DVO2(VDDR_2)
AE12
VDD_DVO3(VDDR_3)
E7
VDDA12_13(VDDPLL_1)
F7
VDDA12_14(VDDPLL_2)
F9
VSSA49(VSSPLL_1)
G9
VSSA50(VSSPLL_2)
D22
VDDHT_PKG
M1
VDDA12_PKG1
AC11
VDDA12_PKG2
RS485M A11 HT
RS485M A11 HT
PART 4 OF 5
PART 4 OF 5
VDDA12_1
VDDA12_2
VDDA12_3
VDDA12_4
VDDA12_5
VDDA12_6
VDDA12_7
VDDA12_8
VDDA12_9
VDDA12_10
VDDA12_11
VDDA12_12
VDDC_1
VDDC_2
VDDC_3
POWER
POWER
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDDC_23
VDDC_24
VDDC_25
VDDC_26
VDDC_27
VDDC_28
VDDC_29
VDDC_30
VDDC_31
VDDC_32
D1
G7
E2
C1
E3
D2
M9
F4
B1
D3
L9
E6
L11
L13
L15
M12
R15
M14
N11
N13
N15
J11
H11
P12
P14
R11
R13
A19
B19
U11
U14
P17
L17
J19
D20
G20
A9
B9
C9
D9
A7
A4
U12
U15
C11
C11
1U/10V_4
1U/10V_4
C24
C24
1U/10V_4
1U/10V_4
10U/10V/X5R_8
10U/10V/X5R_8
C477
C477
C23
C23
1U/10V_4
1U/10V_4
C15
C15
1U/10V_4
1U/10V_4
C480
C480
10U/10V/X5R_8
10U/10V/X5R_8
C481
C481
10U/10V/X5R_8
10U/10V/X5R_8
C53
C53
1U/10V_4
1U/10V_4
C50
C50
1U/10V_4
1U/10V_4
C41
C41
1U/10V_4
1U/10V_4
C47
C47
1U/10V_4
1U/10V_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
RS485-POWER
RS485-POWER
RS485-POWER
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
PROJECT :ZH3
PROJECT :ZH3
Quanta Computer Inc.
Quanta Computer Inc.
of
of
of
11 36 Tuesday, June 27, 2006
11 36 Tuesday, June 27, 2006
1
11 36 Tuesday, June 27, 2006
D
D
D
5
ALINK_RST# 10,19,23,26,30
D D
R173
R172
R174
SB CALIBRATION RESISITOR VALUE
SB600
562 OHM 1%
2.05K 1%
0 ohm
SB460
150 OHM 1%
150 OHM 1%
4.12K 1%
+1.8V
L35
L35
SBK160808T-301Y-S
SBK160808T-301Y-S
PCIE Power
+1.8V
C C
L32
L32
TI201209G121
TI201209G121
C249
C249
22U/10V_8
22U/10V_8
C234
C234
.1U_4
.1U_4
C237
C237
.1U_4
.1U_4
+3VSUS
U5
U5
NC7SZ08P5X_NL
NC7SZ08P5X_NL
5 3
4
R119 *0_4 R119 *0_4
C246
C246
C229
C229
.1U_4
.1U_4
.1U_4
.1U_4
C147 .1U_4 C147 .1U_4
EC_PWRGD
1
2
C257
C257
10U/10V/X5R_8
10U/10V/X5R_8
C228
C228
.1U_4
.1U_4
SBSRCCLK 2
SBSRCCLK# 2
A_RX0P 9
A_RX0N 9
A_RX1P 9
A_RX1N 9
A_TX0P 9
A_TX0N 9
A_TX1P 9
A_TX1N 9
PCIE_VDDR
C254
C254
1U/10V_4
1U/10V_4
C240
C240
.1U_4
.1U_4
RTC
D23 RB751 D23 RB751
+3VPCU
B B
R493 1K/F_4 R493 1K/F_4
3VRTC
C688
C688
A A
.1U_4
.1U_4
Q24
Q24
MMBT3904
MMBT3904
1 3
2
RTC_N02
2 1
D24 RB751 D24 RB751
2 1
C605
C605
1U/10V_4
1U/10V_4
RTC_N01 RTC_N04
R502 1.5K/F_6 R502 1.5K/F_6
RTC_N03
CN18
CN18
1
1
2
2
RTC CONN
RTC CONN
D3A:Due to remove bridge battery,Add RTC circuit ,
VCCRTC
C606
C606
.1U_4
.1U_4
R507 1.5K/F_6 R507 1.5K/F_6
1 2
R470
R470
1K/F_4
1K/F_4
R497
R497
4.7K/F_6
4.7K/F_6
R506
R506
15K/F_6
15K/F_6
JP3
JP3
*Clear PAD
*Clear PAD
+5VPCU
SB-1
5
4
R123 8.2K_4 R123 8.2K_4
16mA
C271 .01U_4 C271 .01U_4
C270 .01U_4 C270 .01U_4
C272 .01U_4 C272 .01U_4
T114T114
T117T117
T118T118
T115T115
T67T67
T71T71
T64T64
T66T66
C253
C253
.1U_4
.1U_4
PCIE_VDDR
C243
C243
.1U_4
.1U_4
R89
R89
20M_4
20M_4
CPU_PWRGD 5,13
LDT_STOP# 5,10,13
ALLOW_LDTSTOP 10
LDT_RST# 5
CPU_PWR_SB
C273 .01U_4 C273 .01U_4
R173 150/F_6 R173 150/F_6
R172 150/F_6 R172 150/F_6
R174 4.12K/F_6 R174 4.12K/F_6
C242
C242
C241
C241
.1U_4
.1U_4
.1U_4
.1U_4
ATi Recommend
Vendor: NSK
Part Number: NXG 32.768KAE12FUD 16 PPM.
Y1 32.768KHZ Y1 32.768KHZ
4 1
2 3
R113 20M_4 R113 20M_4
C135
C135
18P_4
18P_4
ATI recommand have internal pull-up
CPU_PWR_SB
R153
R153
*10K_4
*10K_4
R155 *0_4 R155 *0_4
R480 0_4 R480 0_4
FOR SB460, THIS BALL
IS LDT_RST# ONLY
H_DPSLP# 13
R159
R159
10K_4
10K_4
R139
R139
*10K_4
*10K_4
4
T73T73
T70T70
T69T69
T68T68
T63T63
T72T72
T116T116
T98T98
T65T65
H_DPSLP#
3
U25A
U25A
AG10
A_RST#
J24
PCIE_RCLKP
J25
A_RX0P_C
A_RX0N_C
A_RX1P_C
A_RX1N_C
PCIE_CALRP
PCIE_CALRN
PCIE_CALI
PCIE_PVDD
32K_X1
32K_X2 32K_X2 32K_X2 32K_X2
C144
C144
18P_4
18P_4
32K_X1
32K_X2
H_INTR
H_NMI
H_INIT#
H_IGNNE# BMREQ#
H_A20M#
H_FERR#
STP_CPU#
DPRSLPVR
PCIE_RCLKN
P29
PCIE_TX0P
P28
PCIE_TX0N
M29
PCIE_TX1P
M28
PCIE_TX1N
K29
PCIE_TX2P
K28
PCIE_TX2N
H29
PCIE_TX3P
H28
PCIE_TX3N
T25
PCIE_RX0P
T26
PCIE_RX0N
T22
PCIE_RX1P
T23
PCIE_RX1N
M25
PCIE_RX2P
M26
PCIE_RX2N
M22
PCIE_RX3P
M23
PCIE_RX3N
E29
PCIE_CALRP
E28
PCIE_CALRN
E27
PCIE_CALI
U29
PCIE_PVDD
U28
PCIE_PVSS
F27
PCIE_VDDR_1
F28
PCIE_VDDR_2
F29
PCIE_VDDR_3
G26
PCIE_VDDR_4
G27
PCIE_VDDR_5
G28
PCIE_VDDR_6
G29
PCIE_VDDR_7
J27
PCIE_VDDR_8
J29
PCIE_VDDR_9
L25
PCIE_VDDR_10
L26
PCIE_VDDR_11
L29
PCIE_VDDR_12
N29
PCIE_VDDR_13
D2
X1
C1
X2
AC26
CPU_PG/LDT_PG
W26
INTR/LINT0
W24
NMI/LINT1
W25
INIT#
AA24
SMI#
AA23
SLP#/LDT_STP#
AA22
IGNNE#/SIC
AA26
A20M#/SID
Y27
FERR#
AA25
STPCLK#/ALLOW_LDTSTP
AH9
CPU_STP#/DPSLP_3V#
B24
DPSLP_OD#/GPIO37
W23
DPRSLPVR
AC25
LDT_RST#/DPRSTP#/PROCHOT#
SB460
SB460
SB460 SB 27x27mm
SB460 SB 27x27mm
Part 1 of 4
Part 1 of 4
PCI CLKS
PCI CLKS
SPDIF_OUT/PCICLK7/GPIO41
AD0/ROMA18
AD1/ROMA17
AD2/ROMA16
AD3/ROMA15
AD4/ROMA14
AD5/ROMA13
AD6/ROMA12
AD7/ROMA11
AD10/ROMA7
AD11/ROMA6
AD12/ROMA5
AD13/ROMA4
AD14/ROMA3
AD15/ROMA2
AD16/ROMD0
AD17/ROMD1
AD18/ROMD2
AD19/ROMD3
PCI EXPRESS INTERFACE
PCI EXPRESS INTERFACE
XTAL
XTAL
CPU
CPU
3
AD20/ROMD4
AD21/ROMD5
AD22/ROMD6
AD23/ROMD7
CBE0#/ROMA10
CBE1#/ROMA1
CBE2#/ROMWE#
PCI INTERFACE
PCI INTERFACE
DEVSEL#/ROMA0
TRDY#/ROMOE#
PAR/ROMA19
REQ3#/GPIO70
REQ4#/GPIO71
GNT3#/GPIO72
GNT4#/GPIO73
INTE#/GPIO33
INTF#/GPIO34
INTG#/GPIO35
INTH#/GPIO36
LPC
LPC
LDRQ1#/GNT5#/GPIO68
BMREQ#/REQ5#/GPIO65
RTC_IRQ#/GPIO69
RTC
RTC
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
PCIRST#
AD8/ROMA9
AD9/ROMA8
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
CBE3#
FRAME#
IRDY#
STOP#
PERR#
SERR#
REQ0#
REQ1#
REQ2#
GNT0#
GNT1#
GNT2#
CLKRUN#
LOCK#
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
SERIRQ
RTCCLK
VBAT
RTC_GND
U2
T2
U1
V2
W3
U3
V1
T1
AJ9
W7
Y1
W8
W5
AA5
Y3
AA6
AC5
AA7
AC3
AC7
AJ7
AD4
AB11
AE6
AC9
AA3
AJ4
AB1
AH4
AB2
AJ3
AB3
AH3
AC1
AH2
AC2
AH1
AD2
AG2
AD1
AG1
AB9
AF9
AJ5
AG3
AA2
AH6
AG5
AA1
AF7
Y2
AG8
AC11
AJ8
AE2
AG9
AH8
AH5
AD11
AF2
AH7
AB12
AG4
AG7
AF6
AD3
AF1
AF4
AF3
AG24
AG25
AH24
AH25
AF24
AJ24
AH26
W22
AF23
D3
F5
E1
D1
PCI_MINI
PCI_591
PCI_PCM
PCI_SIO
PCI_CLK4
PCI_LAN
PCI_CLK6
SPDIF_RR
PCIRST#_C
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
GNT0#
GNT1#
GNT2#
GNT3#
GNT4#
CLKRUN#
PCI_LOCK#
INTE#
INTF#
INTG#
INTH#
LAD0/FWH0
LAD1/FWH1
LAD2/FWH2
LAD3/FWH3
LFRAME#/FWH4
LDRQ#0
LDRQ#1
SERIRQ
R434 22_4 R434 22_4
R439 22_4 R439 22_4
R433 22_4 R433 22_4
R432 22_4 R432 22_4
R430 22_4 R430 22_4
R438 22_4 R438 22_4
R431 22_4 R431 22_4
R436 0_4 R436 0_4
AD[0..31]
T124T124
VCCRTC
C571
C571
1U/10V_4
1U/10V_4
2
PCLK_MINI
PCLK_591
PCLK_PCM
PCLK_SIO
PCICLK4
PCLK_LAN
PCICLK6
CBE0# 17,21
CBE1# 17,21
CBE2# 17,21
CBE3# 17,21
FRAME# 17,21
DEVSEL# 17,21
IRDY# 17,21
TRDY# 17,21
PAR 17,21
STOP# 17,21
PERR# 17,21
SERR# 17,21
REQ0# 21
REQ2# 17
GNT0# 21
GNT2# 17
CLKRUN# 17,21,26,27
INTE# 21
INTF# 21
INTG# 17,21
T52T52
2
PCLK_MINI 15,19
PCLK_591 15,27
PCLK_PCM 15,21
PCLK_SIO 15,26
PCICLK4 15
PCLK_LAN 15,17
PCICLK6 15
SB_SPDIF_OUT 15
AD[0..31] 15,17,21
EC_PWRGD 5,13,27
PCIRST#_C
C575
C575
*82P_4
*82P_4
LAD0/FWH0 19,26,27
LAD1/FWH1 19,26,27
LAD2/FWH2 19,26,27
LAD3/FWH3 19,26,27
LFRAME#/FWH4 15,19,26,27
LDRQ#0 26
LDRQ#1 19
BMREQ# 10
SERIRQ 19,21,26,27
RTC_CLK 15
AUTO_ON# 15
1
Reserved For EMI
PCLK_MINI
PCLK_591
PCLK_PCM
PCLK_SIO
PCICLK4
PCLK_LAN
PCICLK6
+3V
C579 .1U_4 C579 .1U_4
U22
U22
NC7SZ08P5X_NL
NC7SZ08P5X_NL
5 3
1
4
2
R419
R419
8.2K_4
8.2K_4
R417 *0_4 R417 *0_4
PCI_LOCK#
SERIRQ
PERR#
FRAME#
TRDY#
STOP#
REQ4#
DEVSEL#
REQ0#
REQ2#
GNT0#
GNT2#
GNT3#
GNT1#
REQ3#
SERR#
REQ1#
IRDY#
B1A R149 stuff
C221
C221
18P_4
18P_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
R94 8.2K_4 R94 8.2K_4
INTE#
R96 8.2K_4 R96 8.2K_4
INTF#
R125 8.2K_4 R125 8.2K_4
INTG#
R81 8.2K_4 R81 8.2K_4
INTH#
R95 8.2K_4 R95 8.2K_4
GNT4#
PAR
LAD3/FWH3
LAD2/FWH2
LAD1/FWH1
LAD0/FWH0
BMREQ#
CLKRUN#
LDRQ#1
LDRQ#0
PROJECT :ZH3
PROJECT :ZH3
Quanta Computer Inc.
Quanta Computer Inc.
SB460M PCIE/PCI/CPU/LPC I/F
SB460M PCIE/PCI/CPU/LPC I/F
SB460M PCIE/PCI/CPU/LPC I/F
C569 *33P_4 C569 *33P_4
C572 *33P_4 C572 *33P_4
C568 *33P_4 C568 *33P_4
C567 *33P_4 C567 *33P_4
C565 *33P_4 C565 *33P_4
C570 *33P_4 C570 *33P_4
C566 *33P_4 C566 *33P_4
PCIRST#
C564
C564
82P_4
82P_4
+3V
R157 10K_4 R157 10K_4
RN34 8.2KX4_4 RN34 8.2KX4_4
1
2
3
4
5
6
7 8
RN33 8.2KX4_4 RN33 8.2KX4_4
1
2
3
4
5
6
7 8
RN2 *8.2KX4_4 RN2 *8.2KX4_4
1
2
3
4
5
6
7 8
RN1 8.2KX4_4 RN1 8.2KX4_4
1
2
3
4
5
6
7 8
R80 *8.2K_4 R80 *8.2K_4
R93 *8.2K_4 R93 *8.2K_4
R156 100K/F_4 R156 100K/F_4
R483 100K/F_4 R483 100K/F_4
R151 100K/F_4 R151 100K/F_4
R147 100K/F_4 R147 100K/F_4
R149 10K_4 R149 10K_4
RN4 10KX4_4 RN4 10KX4_4
1
2
3
4
5
6
7 8
1
PCIRST# 17,19,21,22,27,29
C136
C136
.1U_4
.1U_4
+3V
C238
C238
.1U_4
.1U_4
C576
C576
.1U_4
.1U_4
of
of
of
12 36 Tuesday, June 27, 2006
12 36 Tuesday, June 27, 2006
12 36 Tuesday, June 27, 2006
D
D
D