QUANTA ZE8 Schematics

http://goo.gl/lOFD2

ZE8 BLOCK DIAGRAM

PCB STACK UP

POWER6L HDI

LAYER 1 : TOP LAYER 2 : GND LAYER 3 : IN1 LAYER 4 : IN2 LAYER 5 : VCC LAYER 6 : BOT

CPU

CLOCK

CK505 (QFN-64)

PG 3

FAN & THERMAL

P 4

Penryn SFF ULV DC/SC

Micro-FCBGA956/10W

P4,5

SYSTEM 5V/3V RT8206B

P24

CPU Core ISL6261A P25

DDR Power RT8207A P26

VCCP 1.05V RT8202A

P27

1.5V

800/1066 MHz FSB

DDR2-SODIMM

P16

cahnge A

667/800MHZ DDR II

cahnge B

P17

NORTH BRIDGE

Cantiga SFF GS45

TMDS HDMI Level Shifter

PG 6,7,8,9,10,11

LVDS LED Panel

Connector

VGA

CRT Connector

HDMI

P23

Connector

P23

P22

P23

G9334/AO4466

1.5V_S5 RT9025

Discharge

GFX ISL6263A

P28

P29

DMI x 4

2.5HDD

Touch Screen

P21

P23

On Board USB0

P21

MINI CARD 1

SATA0

Port 8

Port 6

Port 4

SOUTH BRIDGE

ICH9-M SFF

P20

MINI CARD 2

Port 2

USB

P20

CCD

Port 7

P23

Bule Tooth

P22

On Board USB2

On Board USB3

Card Reader Alcor AU6433

Connector

P22

Port 5

Port 0

Port 1

Port 3

Winbond WPCE775LA0DG

SPI

FLASH 2Mbytes

P19

PG 12,13,14,15

LPC

8x16

P19

PS/2

TouchPAD Connector

P22

PCIE4 MINI CARD 1

Connector

PCIE5PCIE

MINI CARD 2 Connector

PCIE1

Connector

P22

GLAN Atheros AR8131L

Line Out/MIC

CODEC

Realtek ALC269X

Speaker

Digital MIC LED Panel

P18

Keyboard Connector

P22

P20

SIM CARD

P20

Connector

ConnectorIHDA

P20

P22

Speaker Connector

P19

Connector

Size Document Number Rev

Schematic Block Diagram

Date: Sheet of

P23

Quanta Computer Inc.

PROJECT :

ZE8

1 32Tuesday, September 29, 2009

http://goo.gl/lOFD2

ZE8 Power On Sequence

From AC,Battery VIN

From PWM

From Power Button

From EC

+5VPCU +3VPCU

SYS_HWPG(PCU)

NBSWON#

S5_ON

+3V_S5,1.5V_S5

+5V_S5

From EC to SB

From EC

RSMRST#

SUSB#,SUSC#From SB to EC

SUSON

Items Function Name Description

With HDMI

Without HDMI

3G Module 3G@

BOM naming rule

HD@

NHD@

+3VSUS +1.8VSUS +SMDDR_VREF +SMDDR_VTERM

From PWM

From EC

HWPG_1.8V (SUS)

MAINON

+5V +3V +1.5V +1.05V

From PWM

From EC

HWPG_1.5V HWPG_1.05V

HWPG(MPWROK)

PWROK_EC

VRON

>5ms

MAINON

VRON

>5ms

>10ms

(SMB_DATA) / (SMB_CLK) (+3V_S5)

Power Plane

MOS CKT

ICH9M SFF SMBUS Table

CLK GEN RAM Mini Card (WLAN/WMAX)

+3V +3V

Stuff Stuff Stuff Stuff

+3V

Mini Card (3G)

+3VSUS

G sensor

+3V

Stuff

+VCC_CORE

From PWM to U5

From U5 to SB

From SB to CLK GEN

From PWM to U7

From U7 to SB

From SB to CPU

From SB to NB

From NB to CPU

VR_PWRGD_CK410#

VR_PWRGD_CLKEN

VR_PWRGD_CK410

DELAY_VR_PWRGOOD(CPU PWRGD)

ICH_PWRGD

H_PWRGOOD

PLTRST#,PCIRST#

CPURST#

EC SMBUS Table

EC775 SDATA1/SCLK1(+3VPCU)

EC775 SDATA2/SCLK2(+3V)

EC775 SDATA3/SCLK3(+3VPCU)

Power Plane

MOS CKT

Battery CPU thermal Sensor EC EEPROM

+3VPCU +3V +3VPCU

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

Date: Sheet of

PROJECT :

Power Sequence/ BOM Rule

ZE8

2 32Tuesday, September 29, 2009

http://goo.gl/lOFD2

+3V+3V

Clock Generator (CLK)

R157

R152

+1.05V +1.05V_VDD_CLK

L16 PBY160808T-301Y-N/2A/300ohm_6L16 PBY160808T-301Y-N/2A/300ohm_6

C239

C237

+3V +3V_VDD_CLK

L17 PBY160808T-301Y-N/2A/300ohm_6L17 PBY160808T-301Y-N/2A/300ohm_6

0603 : card reader use external crystal

C237

10u/10V_8

C240

10u/10V_8

C230

C223

0.1u/10V_4

CLKREQ#_SATA(14)

CLKREQ#_LAN(21)

PCICLK_EC(18)

PCLK_ICH(13)

CLK48_CARD(21)

CLK48_ICH(14)

CLK14_ICH(14)

C230

0.1u/10V_4

C234

0.1u/10V_4

C227

0.1u/10V_4

PCICLK_EC

PCLK_ICH

CLK48_CARD

CLK48_ICH

CLK14_ICH

Layout notice: placed within 500-mils of CK505M

C226 27p/50V_4C226 27p/50V_4

C225 33p/50V_4C225 33p/50V_4

C238

0.1u/10V_4

C228

0.1u/10V_4

PCLK_DEBUG(19)

If XDP is not implemented the 1-k ±10% resistor is not required.

REF (MHz)

CLK48_ICH_R

MCH_BSEL0

FSB

MCH_BSEL1

CLK14_ICH_R

MCH_BSEL2

R135 2.2K_4R135 2.2K_4 R127 1K_4R127 1K_4

R141 Short_4R141 Short_4 R140 10K_4R140 10K_4 R137 1K_4R137 1K_4

R134 10K_4R134 10K_4 R119 1K_4R119 1K_4

SRC

PCI

(MHz)

100.0 33.3 14.318 96.0 48.0

Reserved

1 0 1 0 1 0 1

CPU_BSEL0

CPU_BSEL1

CPU_BSEL2

(MHz)

133.3

200.0

166.6

333.3

100.0

400.0

CPU_BSEL0(4)

CPU_BSEL1(4)

CPU_BSEL2(4)

FSC

FSB FSA CPU

000 266.6 0

C239

0.1u/10V_4

C232

*0.1u/10V_4

R121 475/F_4R121 475/F_4

R138 475/F_4R138 475/F_4

R117 33_4R117 33_4

R118 33_4R118 33_4

R133 *22_4R133 *22_4

R124 22_4R124 22_4

R126 33_4R126 33_4

CG_XIN

14.318MHZ

CG_XOUT

DOT96

USB

(MHz)

96.0 48.0100.0 33.3 14.318

C236

0.1u/10V_4

+1.05V_VDD_CLK

C231

0.1u/10V_4

CR#_ACLKREQ#_SATA

CR#_BCLKREQ#_LAN

PCLK_DEBUG

PCICLK_EC_R

PCLK_ICH_R

CG_XIN

CG_XOUT

CLK48_ICH_R

FSB

CLK14_ICH_R

MCH_BSEL0 (7)

MCH_BSEL1 (7)

MCH_BSEL2 (7)

+3V_VDD_CLK

VDD_PCI

VDD_48

VDD_PLL3

VDD_REF

VDD_SRC

VDD_CPU

VDD_96_IO

VDD_PLL3_IO

VDD_SRC_IO_1

VDD_SRC_IO_3

VDD_SRC_IO_2

VDD_CPU_IO

PCI0/CR#_A

PCI1/CR#_B

PCI2/TME

PCI3

PCI4/LCDCLK_SEL

PCIF5/ITP_EN

XTAL_IN

XTAL_OUT

USB_48/FSA

FSB/TEST/MODE

REF0/FSC/TESTSEL

VSS_BODY

VSS_PCI

VSS_48

VSS_IO

VSS_PLL3

VSS_CPU

VSS_SRC1

VSS_SRC2

VSS_SRC3

VSS_REF

SLG8SP513VTR ,ICS9LPRS365BKLFT

+3V

ITP_EN Pin 53/54

0 1

R139 10K_4R139 10K_4

LCDCLK_SEL Pin 20/21 Pin 24/25

0 1

SMbus address D2

R12210K_4 R12210K_4

SRC_8/SRC_8#

ITP/ITP#

DOT_96/DOT96# LCDCLK/LCDCLK# SRC_0/SRC_0# 27M/27M_SS

4.7K_4

R153 *0_4R153 *0_4

CK505

QFN

CKPWRGD/PWRDW N#

PCLK_DEBUG

PCLK_ICH_R

PCICLK_EC_R

2N7002Q52N7002

SCLK

SDA

SRC5/PCI_STOP#

SRC5#/CPU_STOP#

CPU0

CPU0#

CPU1

CPU1#

SRC8/ITP

SRC8#/ITP#

SRC10

SRC10#

SRC11/CR#_H

SRC11#/CR#_G

SRC9

SRC9#

SRC7/CR#_F

SRC7#/CR#_E

SRC6

SRC6#

SRC4

SRC4#

SRC3/CR#_C

SRC3#/CR#_D

SRC2/SATA

SRC2#/SATA#

SRC1/SE1

SRC1#/SE2

SRC0/DOT96

SRC0#/DOT96#

SLG8SP513

FAE suggest: place Cap before Resistor

7 6

45 44

61 60

58 57

54 53

41 42

40 39

37 38

51 50

48 47

34 35

31 32

28 29

24 25

20 21

PCLK_ICH_R PCICLK_EC_R CLK48_ICH_R CLK14_ICH_R

SMBCK1(16,19,21) PCLK_SMB (14,19)SMBDT1(16,19,21) PDAT_SMB (14,19)

SMBCK1 SMBDT1

PM_STPPCI# PM_STPCPU#

CLK_CPU_BCLK CLK_CPU_BCLK#

CLK_MCH_BCLK CLK_MCH_BCLK#

PECLK_MINI2 PECLK_MINI2#

CR#_H CR#_G CLKREQ#_MINI1

PECLK_MINI1 PECLK_MINI1#

CR#_E

PECLK_3GPLL PECLK_3GPLL#

PECLK_LAN PECLK_LAN#

PECLK_ICH PECLK_ICH#

PECLK_SATA PECLK_SATA#

DREFSSCLK DREFSSCLK#

DREFCLK DREFCLK#

VR_PWRGD_CK410

Pin 11

Pin 13

Pin 14

C220 *33p/50V_4C220 *33p/50V_4 C219 *33p/50V_4C219 *33p/50V_4 C229 *33p/50V_4C229 *33p/50V_4 C224 *33p/50V_4C224 *33p/50V_4

PM_STPPCI# (14) PM_STPCPU# (14)

CLK_CPU_BCLK (4) CLK_CPU_BCLK# (4)

CLK_MCH_BCLK (6) CLK_MCH_BCLK# (6)

PECLK_MINI2 (19) PECLK_MINI2# (19)

R147 3G@475/F_4R147 3G@475/F_4 R146 475/F_4R146 475/F_4

PECLK_MINI1 (19) PECLK_MINI1# (19)

R143 475/F_4R143 475/F_4

PECLK_3GPLL (7) PECLK_3GPLL# (7)

PECLK_LAN (21) PECLK_LAN# (21)

PECLK_ICH (13) PECLK_ICH# (13)

PECLK_SATA (12) PECLK_SATA# (12)

DREFSSCLK (7) DREFSSCLK# (7)

DREFCLK (7) DREFCLK# (7)

VR_PWRGD_CK410 (14)

SLG8SP513VTR (AL8SP513000)

PCI2/TME

PCI4/ 27_Select

PCIF-5/ITP_EN

ICS9LPRS365 (ALPRS365000)

PCIF-5/ITP_EN

Size Document Number Rev

Date: Sheet of

CLKREQ#_MCH

PCI2/TME

PCI_4/ SEL_LCDCLK#

<MAIN> : SLG8SP513VTR(AL8SP513000) <SECOND> : ICS9LPRS365BKLFT(ALPRS365000)

R157

4.7K_4

NO OVERCLOCKING NORMAL RUN

PIN 24/25 IS 27MHz PIN 24/25

PIN 53/54 IS CPUITP PIN 53/54 IS SRC8

CLOCK GENERATOR CK505

PCLK_SMBPDAT_SMB

R158 *0_4R158 *0_4

PULL HIGH PULL DOWN

2N7002Q62N7002

PM_STPPCI# PM_STPCPU#

CLKREQ#_MINI2 (19) CLKREQ#_MINI1 (19)

CLKREQ#_MCH (7)

Quanta Computer Inc.

PROJECT :

R149 2.2K_4R149 2.2K_4 R148 2.2K_4R148 2.2K_4

CR#_A

R131 10K_4R131 10K_4

CR#_B

R132 10K_4R132 10K_4

CR#_E

R142 10K_4R142 10K_4

CR#_G

R145 10K_4R145 10K_4

CR#_H

R144 3G@10K_4R144 3G@10K_4

Clock Request Table CLKREQ#

CR#_A CR#_B CR#_C CR#_D CR#_E CR#_F CR#_G CR#_H

(default)

+3V

MAPPING Control 01 SRC0 SRC2

SRC0 SRC2

SRC6 SRC8 SRC9 SRC10

IS SRC/DOT

ZE8

3 32Tuesday, September 29, 2009

SRC4LCDCLK

SATA LAN N/A N/A MCH N/A MINI1 MINI2

(default)

+3V

http://goo.gl/lOFD2

Penryn SFF - Host Bus (CPU)

H_A#[3..16](6)

Celeron 743

SU2300

SU4100

SU7300

AJSLGEVVT03

AJSLGYWVT03

AJSLGS4VT03

AJSLGYVVT06

H_ADSTB#0(6) H_REQ#[0..4](6)

H_A#[17..35](6)

H_ADSTB#1(6)

H_A20M#(12) H_FERR#(12) H_IGNNE#(12)

H_STPCLK#(12) H_INTR(12) H_NMI(12) H_SMI#(12)

H_A#[3..16]

H_REQ#[0..4]

H_A#[17..35]

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

P2 V4

T4 AA1 AB4

T2 AC5 AD2 AD4 AA5 AE5 AB2 AC1

AN1 AK4 AG1 AT4 AK2 AT2 AH2 AF4

AJ5 AH4 AM4 AP4 AR5

AJ1 AL1 AM2 AU5 AP2 AR1 AN5

C7 D4

F10

F8 C9 C5 E5

Y2 AG5 AL5

U17A

A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]#

REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]#

A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]#

A20M#

ICH

FERR# IGNNE#

STPCLK# LINT0 LINT1 SMI#

RSVD01 RSVD02 RSVD03 RSVD04 RSVD05 RSVD06 RSVD07

Penryn_SFF_1p0

ADDR GROUP 0 ADDR GROUP 1

DEFER#

CONTROL

RESET#

BPM[0]# BPM[1]# BPM[2]# BPM[3]#

XDP/ITP SIGNALS

THERMAL

PROCHOT#

THERMDA THERMDC

THERMTRIP#

H CLK

BCLK[0] BCLK[1]

ADS# BNR#

BPRI#

DRDY# DBSY#

BR0#

IERR#

INIT#

LOCK#

RS[0]# RS[1]# RS[2]# TRDY#

HIT#

HITM#

PRDY# PREQ#

TDO TMS

TRST#

DBR#

C214

*0.1u/10V_4

H_D#[0..15](6)

H_DSTBN#0(6) H_DSTBP#0(6) H_DINV#0(6)

H_D#[16..31](6)

H_DSTBN#1(6) H_DSTBP#1(6) H_DINV#1(6)

CPU_BSEL0(3) CPU_BSEL1(3) CPU_BSEL2(3)

M4 J5 L5

N5 F38 J1

H_IERR#

B40 D8

G5 K2 H4 K4 L1

H2 F2

AY8 BA7 BA5 AY2 AV10

ITP_BPM5#

AV2

ITP_TCK

AV4

TCK

ITP_TDI

AW7

TDI

AU1

ITP_TMS

AW5

ITP_TRST#

AV8

SYS_RST#

H_PROCHOT#_D

D38

H_THERMDA

BB34

H_THERMDC

BD34

H_PM_THRMTRIP#

B10

CLK_CPU_BCLK

A35

CLK_CPU_BCLK#

C35

RESERVED

H_ADS# (6) H_BNR# (6) H_BPRI# (6)

H_DEFER# (6) H_DRDY# (6) H_DBSY# (6)

H_BR0# (6)

H_INIT# (12)

H_LOCK# (6)

H_RESET# (6)

H_RS#0 (6)

H_RS#1 (6)

H_RS#2 (6)

H_TRDY# (6)

H_HIT# (6) H_HITM# (6)

SYS_RST# (14)

CLK_CPU_BCLK (3) CLK_CPU_BCLK# (3)

+1.05V

R123

1K/F_4

R116

2K/F_4

Layout Note: Place voltage divider within 0.5" of GTLREF pin

H_D#[0..15] H_D#[32..47]

H_D#[16..31]

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31

V_CPU_GTLREF

AB44

AA41 AB40 AD40 AC41 AA43

AW43

AE41 AY10 AC43

F40

G43

E43 J43 H40 H44

G39

E41 L41 K44 N41

T40 M40 G41 M44

L43

K40

J41

P40

P44

V40

V44

R41 W41

N43

U41

Y40

Y44

T44

U43 W43

R43

E37

D40

C43

A37

C37

B38

U17B

D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]#

D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]#

GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6

BSEL[0] BSEL[1] BSEL[2]

Penryn_SFF_1p0

DATA GROUP 0 DATA GROUP 1

MISC

D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]#

DATA GROUP 2DATA GROUP 3

D[45]# D[46]#

D[47]# DSTBN[2]# DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]# DSTBN[3]# DSTBP[3]#

DINV[3]#

COMP[0] COMP[1] COMP[2] COMP[3]

DPRSTP#

DPSLP# DPWR#

PWRGOOD

SLP#

H_D#32

AP44

H_D#33

AR43

H_D#34

AH40

H_D#35

AF40

H_D#36

AJ43

H_D#37

AG41

H_D#38

AF44

H_D#39

AH44

H_D#40

AM44

H_D#41

AN43

H_D#42

AM40

H_D#43

AK40

H_D#44

AG43

H_D#45

AP40

H_D#46

AN41

H_D#47

AL41 AK44 AL43 AJ41

AV38 AT44 AV40 AU41 AW41 AR41 BA37 BB38 AY36 AT40 BC35 BC39 BA41 BB40 BA35 AU43 AY40 AY38 BC37

AE43 AD44 AE1 AF2

G7 B8 C41 E7 D10 BD10

PSI#

H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

COMP0

R275 27.4/F_4R275 27.4/F_4

COMP1

R130 54.9/F_4R130 54.9/F_4

COMP2

R287 27.4/F_4R287 27.4/F_4

COMP3

R288 54.9/F_4R288 54.9/F_4

H_D#[48..63]

H_D#[32..47] (6)

H_DSTBN#2 (6) H_DSTBP#2 (6) H_DINV#2 (6)

H_D#[48..63] (6)

H_DSTBN#3 (6) H_DSTBP#3 (6) H_DINV#3 (6)

Layout note: comp0,2: Zo=27.4ohm, L<0.5" comp1,3: Zo=55ohm, L<0.5"

H_DPRSTP# (7,12,25) H_DPSLP# (12) H_DPWR# (6) H_PWRGOOD (12) H_CPUSLP# (6)

+1.05V

R309

56.2/F_4

ME2N7002EQ4ME2N7002E

R84

1K_4

MMBT3904-7-F

1 3

R83 *0_4R83 *0_4

Voltage Level shift

No use Thermal trip CPU side still PU 56ohm. Use Thermal trip can share PU at SB side

SYS_SHDN# (24)

PM_THRMTRIP# (7,12)

DELAY_VR_PWRGOOD(7,14,25)

+1.05V

H_PM_THRMTRIP#

CPU FAN CTRL(THM)

8/11 B-test : for EMI

FANSIGFAN_PWM_CN

C244

C244 *220p/50V_6

*220p/50V_6

FAN_ON#

R344 10K_4R344 10K_4

CPUFAN#(18)

CPUFAN#

C245

C245 *220p/50V_6

*220p/50V_6

FAN_PWM_B

+3V

R345

10K_4

1 3

Q24

Q24 MMBT3904

MMBT3904

+3V

1 3

R346

10K_4

Q25

MMBT3904

+3V

+5V

R343

10K_4

FAN_PWM_CNFAN_PWM_E

R341

10K_4

FANSIG

+5V

FANSIG (18)

CN15

6 345 2 1

FAN

+1.05V

R120 56_4R120 56_4

+1.05V

R286 51/F_4R286 51/F_4 R284 51/F_4R284 51/F_4 R285 51/F_4R285 51/F_4

R101 51/F_4R101 51/F_4 R103 51/F_4R103 51/F_4

Layout Note: Place Resistor close to CPU with Stub length <200mils.

H_IERR#

ITP_BPM5# ITP_TDI ITP_TMS

ITP_TCK ITP_TRST#

CPU Thermal Monitor(THM)

+3V +3V

ALERT#:pull up at SB side

R128

R125

*10K_4

10K_4

2ND_MBCLK(18)

2ND_MBDATA(18)

THERM_ALERT#(14)

FAN_ON#

IC OTHER(8P) G780P81U(MSOP-8)

GMT ADDRESS: 4CH EC ADDRESS: 98H

SCLK

SDA

ALERT#

OVERT#

VCC

DXP

DXN

GND

H_PROCHOT#_D

+1.05V

R274

56_4

R273 *0_4R273 *0_4

C222 0.1u/10V_4C222 0.1u/10V_4

30mA(20mils)

H_THERMDA

C221

2200p/50V_6

2200p/50V_6R129 *0_4R129 *0_4

H_THERMDC

H_PROCHOT# (25)

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

Penryn SFF (Host Bus)/FAN/Thermal

Date: Sheet of

PROJECT :

ZE8

4 32Tuesday, September 29, 2009

http://goo.gl/lOFD2

Penryn SFF - Power (CPU)

VCORE

U17F

BD28

VCC_101 VCC_102 VCC_103 VCC_104 VCC_105 VCC_106 VCC_107 VCC_108 VCC_109 VCC_110 VCC_111 VCC_112 VCC_113 VCC_114 VCC_115 VCC_116 VCC_117 VCC_118 VCC_119 VCC_120 VCC_121 VCC_122 VCC_123 VCC_124 VCC_125 VCC_126 VCC_127 VCC_128 VCC_129 VCC_130 VCC_131 VCC_132 VCC_133 VCC_134 VCC_135 VCC_136 VCC_137 VCC_138 VCC_139 VCC_140 VCC_141 VCC_142 VCC_143 VCC_144 VCC_145 VCC_146 VCC_147 VCC_148 VCC_149 VCC_150 VCC_151 VCC_152 VCC_153 VCC_154 VCC_155 VCC_156 VCC_157 VCC_158 VCC_159 VCC_160 VCC_161 VCC_162 VCC_163 VCC_164 VCC_165 VCC_166 VCC_167 VCC_168 VCC_169 VCC_170 VCC_171 VCC_172 VCC_173 VCC_174 VCC_175 VCC_176 VCC_177 VCC_178 VCC_179 VCC_180 VCC_181 VCC_182 VCC_183 VCC_184 VCC_185 VCC_186 VCC_187 VCC_188 VCC_189 VCC_190 VCC_191 VCC_192 VCC_193 VCC_194 VCC_195 VCC_196 VCC_197 VCC_198 VCC_199 VCC_200 VCC_201 VCC_202 VCC_203 VCC_204 VCC_205 VCC_206 VCC_207 VCC_208 VCC_209 VCC_210 VCC_211 VCC_212 VCC_213 VCC_214 VCC_215 VCC_216 VCC_217 VCC_218 VCC_219 VCC_220

VCCP_017 VCCP_018 VCCP_019 VCCP_020

Penryn_SFF_1p0

VCCP_021 VCCP_022 VCCP_023 VCCP_024 VCCP_025 VCCP_026 VCCP_027 VCCP_028 VCCP_029 VCCP_030 VCCP_031 VCCP_032 VCCP_033 VCCP_034 VCCP_035 VCCP_036 VCCP_037 VCCP_038 VCCP_039 VCCP_040 VCCP_041 VCCP_042 VCCP_043 VCCP_044 VCCP_045 VCCP_046 VCCP_047 VCCP_048 VCCP_049 VCCP_050 VCCP_051 VCCP_052 VCCP_053 VCCP_054 VCCP_055 VCCP_056 VCCP_057 VCCP_058 VCCP_059 VCCP_060 VCCP_061 VCCP_062 VCCP_063 VCCP_064 VCCP_065 VCCP_066 VCCP_067 VCCP_068 VCCP_069 VCCP_070 VCCP_071 VCCP_072 VCCP_073 VCCP_074 VCCP_075 VCCP_076 VCCP_077 VCCP_078 VCCP_079 VCCP_080 VCCP_081 VCCP_082 VCCP_083 VCCP_084 VCCP_085 VCCP_086 VCCP_087 VCCP_088 VCCP_089 VCCP_090 VCCP_091 VCCP_092 VCCP_093 VCCP_094 VCCP_095 VCCP_096 VCCP_097 VCCP_098 VCCP_099 VCCP_100 VCCP_101 VCCP_102 VCCP_103 VCCP_104 VCCP_105 VCCP_106 VCCP_107 VCCP_108 VCCP_109 VCCP_110 VCCP_111 VCCP_112 VCCP_113 VCCP_114 VCCP_115 VCCP_116 VCCP_117 VCCP_118 VCCP_119 VCCP_120 VCCP_121 VCCP_122 VCCP_123 VCCP_124 VCCP_125 VCCP_126 VCCP_127 VCCP_128 VCCP_129 VCCP_130 VCCP_131 VCCP_132 VCCP_133 VCCP_134 VCCP_135 VCCP_136 VCCP_137 VCCP_138 VCCP_139 VCCP_140 VCCP_141 VCCP_142 VCCP_143 VCCP_144 VCCP_145

BB26 BD26

B22 B24 D22 D24 F24 F22 H24 H22 K24 K22 M24 M22 P24 P22 T24 T22 V24 V22 Y24

Y22 AB24 AB22 AD24 AD22 AF24 AF22 AH24 AH22 AK24 AK22 AM24 AM22 AP24 AP22 AT24 AT22 AV24 AV22 AY24 AY22 BB24 BB22 BD24 BD22

B16

B18

B20

D16

D18

F18

F16

H18

H16

D20

F20

H20

K18

K16

M18

M16

K20

M20

P18

P16

T18

T16

V18

V16

P20

T20

V20

Y18

Y16 AB18 AB16 AD18 AD16

Y20 AB20 AD20 AF18 AF16 AH18 AH16 AF20 AH20 AK18 AK16 AM18 AM16 AP18 AP16 AK20 AM20 AP20 AT18 AT16 AV18 AV16 AY18 AY16 AT20 AV20 AY20 BB18 BB16 BD18 BD16 BB20 BD20 AM14 AP14 AT14 AV14 AY14 BB14 BD14

AF38 AG37

AJ37

AK38

C172

10u/6.3V_6

C140

1u/6.3V_4

AB28 AD30 AD28 Y26 AB26 AD26 AF30 AF28 AH30 AH28 AF26 AH26 AK30 AK28 AM30 AM28 AP30 AP28 AK26 AM26 AP26 AT30 AT28 AV30 AV28 AY30 AY28 AT26 AV26 AY26 BB30 BB28 BD30

J11 E11 G11 J37 K38 L37 N37 P38 R37 U37 V38 W37 AA37 AB38 AC37 AE37

B34 D34

BD8 BC7 BB10 BB8 BC5 BB4 AY4

BD12

BC13

C175

10u/6.3V_6

C121

*1u/6.3V_4

VCORE

C134

1u/6.3V_4

+1.05V

C178

10u/6.3V_6

VCORE

C122

1u/6.3V_4

C82

220u/2.5V_3528

VID0 (25) VID1 (25) VID2 (25) VID3 (25) VID4 (25) VID5 (25) VID6 (25)

C138

1u/6.3V_4

C136

1u/6.3V_4

C118

1u/6.3V_4

C179

10u/6.3V_6

C144

1u/6.3V_4

C139

1u/6.3V_4

C117

*1u/6.3V_4

VCORE

C174

10u/6.3V_6

R276

100/F_4

R277

100/F_4

C137

1u/6.3V_4

C194

1u/6.3V_4

C426

0.01u/25V_4

C143

1u/6.3V_4

C191

1u/6.3V_4

+1.5V

C427

10u/6.3V_6

C192

*1u/6.3V_4

VCC_SENSE (25)

VSS_SENSE (25)

+1.05V

VCORE

+1.05V

C162

330u/2.5V_7343

C173

10u/6.3V_6

C141

1u/6.3V_4

C190

*1u/6.3V_4

C180

10u/6.3V_6

C135

1u/6.3V_4

C193

1u/6.3V_4

C154

10u/6.3V_6

AA33 AB32 AC33 AD32 AE33 AF32 AG33 AH32

AK32

AM32 AN33 AP32 AR33 AT34 AT32 AU33 AV32 AY32 BB32 BD32

AB30

C168

10u/6.3V_6

C142

1u/6.3V_4

C120

1u/6.3V_4

F32 G33 H32 J33 K32 L33 M32 N33 P32 R33 T32 U33 V32

W33

Y32

AJ33

AL33

B28 B30 B26 D28 D30 F30 F28 H30 H28 D26 F26 H26 K30 K28 M30 M28 K26 M26 P30 P28 T30 T28 V30 V28 P26 T26 V26 Y30 Y28

C176

10u/6.3V_6

U17C

VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067]

Penryn_SFF_1p0

C177

10u/6.3V_6

C181

10u/6.3V_6

C145

1u/6.3V_4

C119

*1u/6.3V_4

VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]

VCCP_001 VCCP_002 VCCP_003 VCCP_004 VCCP_005 VCCP_006 VCCP_007 VCCP_008 VCCP_009 VCCP_010 VCCP_011 VCCP_012 VCCP_013 VCCP_014 VCCP_015 VCCP_016

VCCA[01] VCCA[02]

VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]

VCCSENSE

VSSSENSE

C116

1u/6.3V_4

AL37 AN37 AP38 B32 C33 D32 E35 E33 F34 G35 F36 H36 J35 L35 N35 K36 R35 U35 P36 V36 W35 AA35 AC35 AB36 AE35 AG35 AJ35 AF36 AL35 AN35 AK36 AP36 B12 B14 C13 D12 D14 E13 F14 F12 G13 H14 H12 J13 K14 K12 L13 L11 M14 N13 N11 K10 P14 P12 R13 R11 T14 U13 U11 V14 V12 W13 W11 P10 V10 Y14 AA13 AA11 AB14 AB12 AC13 AC11 AD14 AB10 AE13 AE11 AF14 AF12 AG13 AG11 AH14 AJ13 AJ11 AF10 AK14 AK12 AL13 AL11 AN13 AN11 AP12 AR13 AR11 AK10 AP10 AU13 AU11 L9 L7 N9 N7 R9 R7 U9 U7 W9 W7 AA9 AA7 AC9 AC7 AE9 AE7 AG9 AG7 AJ9 AJ7 AL9 AL7 AN9 AN7 AR9 AR7 A33 A13

+1.05V

U17E

G25

VSS_164

G23

VSS_165

G21

VSS_166

J25

VSS_167

J23

VSS_168

J21

VSS_169

L25

VSS_170

L23

VSS_171

L21

VSS_172

N25

VSS_173

N23

VSS_174

N21

VSS_175

R25

VSS_176

R23

VSS_177

R21

VSS_178

U25

VSS_179

U23

VSS_180

U21

VSS_181

W25

VSS_182

W23

VSS_183

W21

VSS_184

AA25

VSS_185

AA23

VSS_186

AA21

VSS_187

AC25

VSS_188

AC23

VSS_189

AC21

VSS_190

AE25

VSS_191

AE23

VSS_192

AE21

VSS_193

AG25

VSS_194

AG23

VSS_195

AG21

VSS_196

AJ25

VSS_197

AJ23

VSS_198

AJ21

VSS_199

AL25

VSS_200

AL23

VSS_201

AL21

VSS_202

AN25

VSS_203

AN23

VSS_204

AN21

VSS_205

AR25

VSS_206

AR23

VSS_207

AR21

VSS_208

AU25

VSS_209

AU23

VSS_210

AU21

VSS_211

AW25

VSS_212

AW23

VSS_213

AW21

VSS_214

BA25

VSS_215

BA23

VSS_216

BA21

VSS_217

BC25

VSS_218

BC23

VSS_219

BC21

VSS_220

C17

VSS_221

C19

VSS_222

E19

VSS_223

E17

VSS_224

G19

VSS_225

G17

VSS_226

J19

VSS_227

J17

VSS_228

L19

VSS_229

L17

VSS_230

N19

VSS_231

N17

VSS_232

R19

VSS_233

R17

VSS_234

U19

VSS_235

U17

VSS_236

W19

VSS_237

W17

VSS_238

AA19

VSS_239

AA17

VSS_240

AC19

VSS_241

AC17

VSS_242

AE19

VSS_243

AE17

VSS_244

AG19

VSS_245

AG17

VSS_246

AJ19

VSS_247

AJ17

VSS_248

AL19

VSS_249

AL17

VSS_250

AN19

VSS_251

AN17

VSS_252

AR19

VSS_253

AR17

VSS_254

AU19

VSS_255

AU17

VSS_256

AW19

VSS_257

AW17

VSS_258

BA19

VSS_259

BA17

VSS_260

BC19

VSS_261

BC17

VSS_262

C11

VSS_263

C15

VSS_264

E15

VSS_265

G15

VSS_266

H10

VSS_267

M12

VSS_268

J15

VSS_269

L15

VSS_270

N15

VSS_271

M10

VSS_272

T12

VSS_273

R15

VSS_274

U15

VSS_275

W15

VSS_276

T10

VSS_277

Y12

VSS_278

AD12

VSS_279

Penryn_SFF_1p0

VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358 VSS_359 VSS_360 VSS_361 VSS_362 VSS_363 VSS_364 VSS_365 VSS_366 VSS_367 VSS_368 VSS_369 VSS_370 VSS_371 VSS_372 VSS_373 VSS_374 VSS_375 VSS_376 VSS_377 VSS_378 VSS_379 VSS_380 VSS_381 VSS_382 VSS_383 VSS_384 VSS_385 VSS_386 VSS_387 VSS_388 VSS_389 VSS_390 VSS_391 VSS_392 VSS_393 VSS_394 VSS_395

AA15 AC15 Y10 AD10 AH12 AE15 AG15 AJ15 AH10 AM12 AL15 AN15 AR15 AM10 AT12 AV12 AW13 AW11 AY12 AU15 AW15 AT10 BA13 BA11 BB12 BC11 BA15 BC15 B6 D6 E9 F6 G9 H6 K8 K6 M8 M6 P8 P6 T8 T6 V8 V6 U5 Y8 Y6 AB8 AB6 AD8 AD6 AF8 AF6 AH8 AH6 AK8 AK6 AM8 AM6 AP8 AP6 AT8 AT6 AU9 AV6 AU7 AW9 AY6 BA9 BB6 BC9 BD6 B4 C3 E3 G3 J3 L3 N3 R3 U3 W3 AA3 AC3 AE3 AG3 AJ3 AL3 AN3 AR3 AU3 AW3 BA3 BC3 D2 E1 G1 AW1 BA1 BB2 A41 A39 A29 A27 A31 A25 A23 A21 A19 A17 A11 A15 A7 A5 A9 BD4

Size Document Number Rev

Penryn SFF (Power)

Date: Sheet of

U17D

B42

VSS[001]

F44

VSS[002]

D44

VSS[003]

D42

VSS[004]

F42

VSS[005]

H42

VSS[006]

K42

VSS[007]

M42

VSS[008]

P42

VSS[009]

T42

VSS[010]

V42

VSS[011]

Y42

VSS[012]

AB42

VSS[013]

AD42

VSS[014]

AF42

VSS[015]

AH42

VSS[016]

AK42

VSS[017]

AM42

VSS[018]

AP42

VSS[019]

AY44

VSS[020]

AV44

VSS[021]

AT42

VSS[022]

AV42

VSS[023]

AY42

VSS[024]

BA43

VSS[025]

BB42

VSS[026]

C39

VSS[027]

E39

VSS[028]

G37

VSS[029]

H38

VSS[030]

J39

VSS[031]

L39

VSS[032]

M38

VSS[033]

N39

VSS[034]

R39

VSS[035]

T38

VSS[036]

U39

VSS[037]

W39

VSS[038]

Y38

VSS[039]

AA39

VSS[040]

AC39

VSS[041]

AD38

VSS[042]

AE39

VSS[043]

AG39

VSS[044]

AH38

VSS[045]

AJ39

VSS[046]

AL39

VSS[047]

AM38

VSS[048]

AN39

VSS[049]

AR39

VSS[050]

AR37

VSS[051]

AT38

VSS[052]

AU39

VSS[053]

AU37

VSS[054]

AW39

VSS[055]

AW37

VSS[056]

BA39

VSS[057]

BC41

VSS[058]

BD40

VSS[059]

BD38

VSS[060]

B36

VSS[061]

H34

VSS[062]

D36

VSS[063]

K34

VSS[064]

M34

VSS[065]

M36

VSS[066]

P34

VSS[067]

T34

VSS[068]

V34

VSS[069]

T36

VSS[070]

Y34

VSS[071]

AB34

VSS[072]

AD34

VSS[073]

Y36

VSS[074]

AD36

VSS[075]

AF34

VSS[076]

AH34

VSS[077]

AH36

VSS[078]

AK34

VSS[079]

AM34

VSS[080]

AP34

VSS[081]

Penryn_SFF_1p0

Quanta Computer Inc.

PROJECT :

VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163]

ZE8

AM36 AR35 AU35 AV34 AW35 AW33 AY34 AT36 AV36 BA33 BC33 BB36 BD36 C27 C29 C31 E29 E27 G29 G27 E31 G31 J29 J27 L29 L27 N29 N27 J31 L31 N31 R29 R27 U29 U27 R31 U31 W29 W27 W31 AA29 AA27 AC29 AC27 AA31 AC31 AE29 AE27 AG29 AG27 AJ29 AJ27 AE31 AG31 AJ31 AL29 AL27 AN29 AN27 AL31 AN31 AR29 AR27 AR31 AU29 AU27 AW29 AW27 AU31 AW31 BA29 BA27 BC29 BC27 BA31 BC31 C21 C23 C25 E25 E23 E21

5 32Tuesday, September 29, 2009

http://goo.gl/lOFD2

Cantiga SFF - Host Bus (CLG)

H_D#[0..63](4)

+1.05V

R87

221/F_4

H_SWING

R92

100/F_4

C93

0.1u/10V_4

Layout Note: H_RCOMP trace should be 10-mil wide with 20-mil spacing.

H_RCOMP

R289

24.9/F_4

+1.05V

R96

1K/F_4

R91

2K/F_4

H_D#[0..63]

H_RESET#(4)

H_CPUSLP#(4)

C104

*0.1u/10V_4

H_AVREF

H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_SWING H_RCOMP

U18A

L11

J3 H4 G3

K10 K12

M10

N11

L7 K6 M4 K4 P6

V6 V2

P10

N9 P4 U9 V4 U1

V10

W11

U11

AC11

AC9

Y10 AB6 AA9

AB10

AA1 AC3 AC7

AD12

AB4

AD10

AA11

AB2 AD4 AE7 AD2 AD6

AE3 AG9 AG7

AE11

AK6

AF6

AJ9 AH6

AF12

AH4

AJ7 AE9

B6 D4

J11

L17

K18

CANTIGASFF_1p0

H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63

H_SWING H_RCOMP

H_CPURST# H_CPUSLP#

H_AVREF H_DVREF

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8

H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35

H_ADS# H_ADSTB#_0 H_ADSTB#_1

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HOST

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HIT#

H_HITM# H_LOCK# H_TRDY#

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3

H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4

H_RS#_0

H_RS#_1

H_RS#_2

B14 C15 D12 F14 G17 B12 J15 D16 C17 D14 K16 F16 B16 C21 D18 J19 J21 B18 D22 G19 J17 L21 L19 G21 D20 K22 F18 K20 F20 F22 B20 A19

F10 A15 C19 C9 B8 C11 E5 D6 AH10 AJ11 G11 H2 C7 F8 A11 D8

L9 N7 AA7 AG3

K2 N3 AA3 AF4

L3 M2 Y2 AF2

J13 L13 C13 G13 G15

F4 F2 G7

H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

H_A#3

L15

H_A#[3..35]

H_ADS# (4) H_ADSTB#0 (4) H_ADSTB#1 (4) H_BNR# (4) H_BPRI# (4) H_BR0# (4) H_DEFER# (4) H_DBSY# (4) CLK_MCH_BCLK (3) CLK_MCH_BCLK# (3) H_DPWR# (4) H_DRDY# (4) H_HIT# (4) H_HITM# (4) H_LOCK# (4) H_TRDY# (4)

H_DINV#0 (4) H_DINV#1 (4) H_DINV#2 (4) H_DINV#3 (4)

H_DSTBN#0 (4) H_DSTBN#1 (4) H_DSTBN#2 (4) H_DSTBN#3 (4)

H_DSTBP#0 (4) H_DSTBP#1 (4) H_DSTBP#2 (4) H_DSTBP#3 (4)

H_REQ#0 (4) H_REQ#1 (4) H_REQ#2 (4) H_REQ#3 (4) H_REQ#4 (4)

H_RS#0 (4) H_RS#1 (4) H_RS#2 (4)

H_A#[3..35] (4)

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

Cantiga SFF (Host Bus)

Date: Sheet of

PROJECT :

ZE8

6 32Tuesday, September 29, 2009

http://goo.gl/lOFD2

Cantiga SFF - DMI/VGA (CLG)

Intel GS40/GS45 Strapping Signals and Configuration Pin Name Strap Description Configuration

CFG2:0 FSB Frequency

CFG4:3 CFG5

CFG6

CFG7 Intel Management

CFG8 CFG9

CFG10

CFG11 Reserved CFG12 ALLZ 1 = Disabled

CFG13 XOR 1 = Disabled

CFG14 Reserved CFG15 Reserved CFG16 FSB Dynamic ODT

CFG17 Reserved CFG18 Reserved CFG19 DMI Lane Reversal 1 = Reverse Lanes

CFG20

SDVO_CTRLDATA

L_DDC_DATA

DDPC_CTRLDATA

The recommended pull-up resistor value is 4.02 k Ω ±1%

•

The recommended pull-down resistor value is 2.21 k Ω ±1%.

•

DMI x2 Select

ITPM Host Interface

Engine Crypto Strap

PCIE Graphics Lane

PCIE Loopback enable

Digital DisplayPort (SDVO/DP/iHDMI) Concurrent with PCIE

SDVO Present

Local Flat Panel (LFP) Present Digital Display Present

DDR3 PWROK

SUSON(18,26,28)

HWPG_+1.5V_SUS(18,26)

Check list note : CL_REF=0.35V

(15mils)

MCH_CLVREF

C170

0.1u/10V_4

000 = FSB1066 010 = FSB800 011 = FSB667 Other = Reserved

Reserved

1 = DMI x 4 0 = DMI x2 1 = ITPM disabled 0 = ITPM enabled 1 = Intel Management Engine Crypto TLS cipher suite with confidentiality 0 = Intel Management Engine Crypto Transport Layer Security (TLS) cipher suite with no confidentiality

Reserved

1 = Normal operation : Lane Numbered in Order 0 = Reverse Lanes 1 = Disabled 0 = Enabled

0 = ALLZ mode enabled

0 = XOR mode enabled

1 = Dynamic ODT enabled 0 = Dynamic ODT disabled

0 = Normal operation : Lane Numbered in Order 1 = Digital DisplayPort (SDVO/DP/iHDMI) and PCIE are operating simultaneously via the PEG port 0 = Digital DisplayPort (SDVO/DP/iHDMI) or PCIE are operational 1 = SDVO/HDMI/DP interface enabled 0 = No SDVO/HDMI/DP interface disabled 1 = LFP Card Present; PCIE disabled 0 = LFP Disable 1 = Digital display (iHDMI/DP) devide present 0 = Digital display (iHDMI/DP) interface absent

MCH_BSEL0(3) MCH_BSEL1(3) MCH_BSEL2(3)

PM_SYNC#(14) H_DPRSTP#(4,12,25) PM_EXTTS#0(16) PM_EXTTS#1(16)

DELAY_VR_PWRGOOD(4,14,25)

PLTRST#(13,18,19,21)

PM_THRMTRIP#(4,12)

DPRSLPVR(14,25)

+3V_S5

At 11/19 change U21 power supply from +3VSUS to +3V_S5

U21

U21 TC7SH08FU

TC7SH08FU

+1.05V

R112

1K/F_4

R111

511/F_6

R347

12.1K/F_4

R348

10K_4

J43

L43

J41

L41 AN11 AM10 AK10

AL11

F12

C27

D30

AW42

BB20 BE19

BF20 BF18

AN45 AP44

AT44

AN47

K26

G23 G25

J25

L25

MCH_CFG5

MCH_CFG7

MCH_CFG12 MCH_CFG13

MCH_CFG16

MCH_CFG19 MCH_CFG20

PM_EXTTS#0 PM_EXTTS#1

RSTIN#_MCH

AY39 BB18

BE55 BH55 BK55 BK54

L27

F24

D24

D26

J23 B26 A23 C23 B24 B22 K24 C25 L23 L33 K32 K34

J35

J39 L39

K28 K36

A7 A49 A52 A54 B54 D55

G55

BL54 BL52 BL49

BL7 BL4 BL2

BK2 BK1 BH1 BE1

T10T10

T17T17

T16T16 T15T15

T14T14

T8T8 T9T9

R136 100_4R136 100_4 R98 *0_4R98 *0_4

SM_PWROK

(20mils)

+SMDDR_VREF_NB

+SMDDR_VREF_NB.Default use voltage divider for poor layout cause +SMDDR_VREF not meet spec.And Intel circuit PU/PD is 1K,But Check list PU/PD is 10K.

R113

U18B

RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9

RSVD14 RSVD15

RSVD17

RSVD20

RSVD22 RSVD23 RSVD24 RSVD25

ME_JTAG_TCK ME_JTAG_TDI ME_JTAG_TDO ME_JTAG_TMS

CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20

PM_SYNC# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR

NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20 NC_21 NC_22

CANTIGASFF_1p0

+SMDDR_VREF

BLM18BA750SN1D_6

+1.5V_SUS

R350 *10K/F_4R350 *10K/F_4 R349 *10K/F_4R349 *10K/F_4

CFGRSVD

SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1

SA_CK#_0 SA_CK#_1 SB_CK#_0 SB_CK#_1

SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1

SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1

SA_ODT_0 SA_ODT_1 SB_ODT_0 SB_ODT_1

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH SM_RCOMP_VOL

SM_VREF

SM_PWROK

SM_REXT

SM_DRAMRST#

DPLL_REF_CLK

DDR CLK/ CONTROL/COMPENSATION

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK

PEG_CLK#

CLK

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

DMI

GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4

GFX_VR_EN

GRAPHICS VID

CL_CLK

CL_DATA

CL_PWROK

CL_RST# CL_VREF

DDPC_CTRLCLK

DDPC_CTRLDATA

SDVO_CTRLCLK

SDVO_CTRLDATA

CLKREQ#

ICH_SYNC#

TSATN#

MISC

HDA_BCLK HDA_RST#

HDA_SDI

HDA_SDO

HDA_SYNC

HDA

<Checklist ver0.8> If TSATN# is not used, then it must be terminated with a 56-Ω pull-up resistor to VCCP.

PM_EXTTS#0 PM_EXTTS#1

SM_REXT

BB32 BA25 BA33 BA23

BA31 BC25 BC33 BB24

BC35 BE33 BE37 BC37

BK18 BK16 BE23 BC19

BJ17 BJ19 BC17 BE17

BL25 BK26

BK32 BL31

BC51 AY37 BH20 BA37

B42 D42 B50 D50

R49 P50

AG55 AL49 AH54 AL47

AG53 AK50 AH52 AL45

AG49 AJ49 AJ47 AG47

AF50 AH50 AJ45 AG45

G33 G37 F38 F36 G35

G39

AK52 AK54 AW40 AL53 AL55

F34 F32 B38 A37 C31 K42

D10

C29 B30 D28 A27 B28

TSATN#

SMRCOMPP SMRCOMPN

SM_RCOMP_VOH SM_RCOMP_VOL

+SMDDR_VREF_NB SM_PWROK SM_REXT

DREFCLK DREFCLK# DREFSSCLK DREFSSCLK#

PECLK_3GPLL PECLK_3GPLL#

MCH_CLVREF

DDPC_CTRLCLK DDPC_CTRLDATA SDVO_CTRLCLK SDVO_CTRLDATA

CLKREQ#_MCH

TSATN#

HDA_BIT_CLK_HDMI HDA_RST#_HDMI HDA_SDIN_HDMI HDA_SDOUT_HDMI HDA_SYNC_HDMI

R296 56_4R296 56_4

R100 10K_4R100 10K_4 R97 10K_4R97 10K_4

R271 499/F_4R271 499/F_4

M_CLK_DDR0 (16) M_CLK_DDR1 (16) M_CLK_DDR2 (16) M_CLK_DDR3 (16)

M_CLK_DDR#0 (16) M_CLK_DDR#1 (16) M_CLK_DDR#2 (16) M_CLK_DDR#3 (16)

M_CKE0 (16) M_CKE1 (16) M_CKE2 (16) M_CKE3 (16)

M_CS#0 (16) M_CS#1 (16) M_CS#2 (16) M_CS#3 (16)

M_ODT0 (16) M_ODT1 (16) M_ODT2 (16) M_ODT3 (16)

DDR3_RST# (16)

DREFCLK (3) DREFCLK# (3) DREFSSCLK (3) DREFSSCLK# (3)

PECLK_3GPLL (3) PECLK_3GPLL# (3)

DMI_MRX_ITX_N0 (13) DMI_MRX_ITX_N1 (13) DMI_MRX_ITX_N2 (13) DMI_MRX_ITX_N3 (13)

DMI_MRX_ITX_P0 (13) DMI_MRX_ITX_P1 (13) DMI_MRX_ITX_P2 (13) DMI_MRX_ITX_P3 (13)

DMI_MTX_IRX_N0 (13) DMI_MTX_IRX_N1 (13) DMI_MTX_IRX_N2 (13) DMI_MTX_IRX_N3 (13)

DMI_MTX_IRX_P0 (13) DMI_MTX_IRX_P1 (13) DMI_MTX_IRX_P2 (13) DMI_MTX_IRX_P3 (13)

GPU_VID0 (29) GPU_VID1 (29) GPU_VID2 (29) GPU_VID3 (29) GPU_VID4 (29)

GFX_VR_EN (29)

CL_CLK0 (14) CL_DATA0 (14) MPWROK (14,18)

ICH_CL_RST0# (14)

SDVO_CTRLCLK (22)

SDVO_CTRLDATA (22) CLKREQ#_MCH (3) MCH_ICH_SYNC# (14)

HDA_BIT_CLK_HDMI (12) HDA_RST#_HDMI (12) HDA_SDIN_HDMI (12) HDA_SDOUT_HDMI (12) HDA_SYNC_HDMI (12)

+1.05V

+3V

SM_VREF=0.5*VCC_SM

SM_PWROK only for DDR3.(DDR2 PD only) SM_DRAMRST# only for DDR3.(DDR2:NC)

DDCCLK(21) DDCDATA(21)

DDR3 RCOMP DDR3 RCOMP_VOH/VOLDDR3 VREF

SMRCOMPP

R270 80.6/F_4R270 80.6/F_4

SMRCOMPN

R272 80.6/F_4R272 80.6/F_4

INT_LVDS_PWM(22) INT_LVDS_BLON(22)

PHL_CLK(22) PHL_DATA(22)

INT_LVDS_DIGON(22)

TXLCLKOUT-(22) TXLCLKOUT+(22)

TXLOUT0-(22) TXLOUT1-(22) TXLOUT2-(22)

TXLOUT0+(22) TXLOUT1+(22) TXLOUT2+(22)

CRT_B(21)

CRT_G(21)

CRT_R(21)

VGAHSYNC(21)

VGAVSYNC(21)

R81 30.1/F_4R81 30.1/F_4

R80 30.1/F_4R80 30.1/F_4

CRT setting LVDS setting

R82 150/F_4R82 150/F_4 R78 150/F_4R78 150/F_4 R79 150/F_4R79 150/F_4

+1.5V_SUS

L_CTRL_CLK

L_CTRL_DATA PHL_CLK PHL_DATA

LVDS_IBG

TXLCLKOUTTXLCLKOUT+

TXLOUT0TXLOUT1TXLOUT2-

TXLOUT0+ TXLOUT1+ TXLOUT2+

INT_TV_COMP INT_TV_Y/G INT_TV_C/R

CRT_B

CRT_G

CRT_R

R84: if the total motherboard route length is less than 12", the recommended reference resistor value is 1 K Ω ±1% For longer route lengths between 12" - 15.3" , the recommended reference resistor value is 976 Ω ±1%

+1.5V_SUS

CRT_B CRT_G CRT_R

HSYNC

CRT_IREF

VSYNC

D38 C37 K38

L37 J37 L35

B36 F50 H46 P44 K46 D46 B46 D44 B44

G45 F46 G41 C45

F44 G47 F40 A45

B40 A41 F42 D48

D40 C41 G43 B48

J27 E27 G27

F26

B34 D34

J29

G29

F30

E29

D36 C35 J33 D32 G31

U18C

L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK

L_CTRL_DATA L_DDC_CLK L_DDC_DATA

L_VDD_EN LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK

LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3

LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3

LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3

LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3

TVA_DAC TVB_DAC TVC_DAC

TVA_RTN

TV_DCONSEL_0 TV_DCONSEL_1

CRT_BLUE

CRT_GREEN

CRT_RED

CRT_IRTN

CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC

CANTIGASFF_1p0

R93 1.02K/F_4R93 1.02K/F_4

R102 75/F_4R102 75/F_4 R291 75/F_4R291 75/F_4 R292 75/F_4R292 75/F_4

SM_RCOMP_VOH

R269

C423

3.01K/F_4

0.01u/25V_4

SM_RCOMP_VOL

R266

C422

1K/F_4

0.01u/25V_4

LVDS

VGA

CRT_IREF

INT_TV_COMP

INT_TV_Y/G INT_TV_C/R

C421

2.2u/6.3V_6

C418

2.2u/6.3V_6

PCI-EXPRESS GRAPHICS

Layout notice: Place the resistor within 500 mils (1.27 mm) of the (G)MCH.

U45

PEG_COMPI

T44

PEG_COMPO

D52

PEG_RX#_0

G49

PEG_RX#_1

K54

PEG_RX#_2

H50

PEG_RX#_3

M52

PEG_RX#_4

N49

PEG_RX#_5

P54

PEG_RX#_6

V46

PEG_RX#_7

Y50

PEG_RX#_8

V52

PEG_RX#_9

W49

PEG_RX#_10

AB54

PEG_RX#_11

AD46

PEG_RX#_12

AC55

PEG_RX#_13

AE49

PEG_RX#_14

AF54

PEG_RX#_15

E51

PEG_RX_0

F48

PEG_RX_1

J55

PEG_RX_2

J49

PEG_RX_3

M54

PEG_RX_4

M50

PEG_RX_5

P52

PEG_RX_6

U47

PEG_RX_7

AA49

PEG_RX_8

V54

PEG_RX_9

V50

PEG_RX_10

AB52

PEG_RX_11

AC47

PEG_RX_12

AC53

PEG_RX_13

AD50

PEG_RX_14

AF52

PEG_RX_15

L47

PEG_TX#_0

F52

PEG_TX#_1

P46

PEG_TX#_2

H54

PEG_TX#_3

L55

PEG_TX#_4

T46

PEG_TX#_5

R53

PEG_TX#_6

U49

PEG_TX#_7

T54

PEG_TX#_8

Y46

PEG_TX#_9

AB46

PEG_TX#_10

W53

PEG_TX#_11

Y54

PEG_TX#_12

AC49

PEG_TX#_13

AF46

PEG_TX#_14

AD54

PEG_TX#_15

J47

PEG_TX_0

F54

PEG_TX_1

N47

PEG_TX_2

H52

PEG_TX_3

L53

PEG_TX_4

R47

PEG_TX_5

R55

PEG_TX_6

T50

PEG_TX_7

T52

PEG_TX_8

W47

PEG_TX_9

AA47

PEG_TX_10

W55

PEG_TX_11

Y52

PEG_TX_12

AB50

PEG_TX_13

AE47

PEG_TX_14

AD52

PEG_TX_15

(7/7) intel check list 360543 rev 2.0 CLKREQ# need to 10K pull high to 3.3V

Size Document Number Rev

Date: Sheet of

R104 49.9/F_4R104 49.9/F_4

PEG_COMP

PEG_TXN0

C73 0.1u/10V_4C73 0.1u/10V_4

PEG_TXN1

C74 0.1u/10V_4C74 0.1u/10V_4

PEG_TXN2

C71 0.1u/10V_4C71 0.1u/10V_4

PEG_TXN3

C92 0.1u/10V_4C92 0.1u/10V_4

PEG_TXP0

C72 0.1u/10V_4C72 0.1u/10V_4

PEG_TXP1

C75 0.1u/10V_4C75 0.1u/10V_4

PEG_TXP2

C70 0.1u/10V_4C70 0.1u/10V_4

PEG_TXP3

C99 0.1u/10V_4C99 0.1u/10V_4

+3V

R95 10K_4R95 10K_4

R94 10K_4R94 10K_4 R300 2.2K_4R300 2.2K_4 R301 2.2K_4R301 2.2K_4

R290 2.4K/F_4R290 2.4K/F_4

DDPC_CTRLCLK DDPC_CTRLDATA SDVO_CTRLCLK SDVO_CTRLDATA CLKREQ#_MCH

Cantiga SFF (DMI/VGA)

+1.05V

R294 2.2K_4R294 2.2K_4 R295 2.2K_4R295 2.2K_4 R297 4.7K_4R297 4.7K_4 R299 4.7K_4R299 4.7K_4R264 1K/F_4R264 1K/F_4 R293 10K_4R293 10K_4

Quanta Computer Inc.

PROJECT :

HDMI_HP_IV# (22)

HDMI Port B

HDMITX2N (22) HDMITX1N (22) HDMITX0N (22) HDMICLKN (22)

HDMITX2P (22) HDMITX1P (22) HDMITX0P (22) HDMICLKP (22)

L_CTRL_CLK

L_CTRL_DATA

PHL_DATA

PHL_CLK

LVDS_IBG

ZE8

7 32Tuesday, September 29, 2009

+3V

http://goo.gl/lOFD2

Cantiga SFF - DDRII (CLG)

M_A_DQ[63:0](16) M_B_DQ[63:0](16)

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

AP46 AU47 AT46 AU49 AR45 AN49 AV50 AP50

AW47

BD50

AW49

BA49 BC49 AV46 BA47 AY50 BF46 BC47 BF50 BF48 BC43 BE49 BA43 BE47 BF42 BC39 BF44 BF40 BB40 BE43 BF38 BE41 BA15 BE11 BE15 BF14 BB14 BC15 BE13 BF16 BF10 BC11

BF8 BG7 BC7 BC9 BD6

BF12

AV6

BB6

AW7

AY6

AT10

AW11

AU11

AW9

AR11

AT6

AP6

AL7 AR7

AT12

AM6 AU7

U18D

SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63

CANTIGASFF_1p0

DDR SYSTEM MEMORY A

SA_BS_0 SA_BS_1 SA_BS_2

SA_RAS# SA_CAS#

SA_WE#

SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6

SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14

BC21 BJ21 BJ41

BH22 BK20 BL15

AT50 BB50 BB46 BE39 BB12 BE7 AV10 AR9

AR47 BA45 BE45 BC41 BC13 BB10 BA7 AN7 AR49 AW45 BC45 BA41 BA13 BA11 BA9 AN9

BC23 BF22 BE31 BC31 BH26 BJ35 BB34 BH32 BB26 BF32 BA21 BG25 BH34 BH18 BE25

M_A_BS#0 M_A_BS#1 M_A_BS#2

M_A_RAS# M_A_CAS# M_A_WE#

M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14

M_A_BS#0 (16) M_A_BS#1 (16) M_A_BS#2 (16)

M_A_RAS# (16) M_A_CAS# (16) M_A_WE# (16)

M_A_DM[7:0] (16)

M_A_DQS[7:0] (16)

M_A_DQS#[7:0] (16)

M_A_A[14:0] (16)

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

AP54 AM52 AR55

AV54 AM54 AN53

AT52 AU53

AW53

AY52

BB52 BC53

AV52

AW55

BD52 BC55

BF54

BE51 BH48

BK48

BE53 BH52

BK46

BJ47

BL45

BJ45

BL41 BH44 BH46

BK44

BK40

BJ39

BK10 BH10

BK6 BH6

BL11

BG5

BG3 BF4 BD4 BA3 BE5 BF2 BB4 AY4 BA1 AP2 AU1 AT2 AT4 AV4 AU3 AR3 AN1 AP4 AL3

AK4

AM4

AH2 AK2

BJ9

BJ5

AJ1

U18E

SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

CANTIGASFF_1p0

DDR SYSTEM MEMORY B

SB_BS_0 SB_BS_1 SB_BS_2

SB_RAS# SB_CAS#

SB_WE#

SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6

SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14

BJ13 BK12 BK38

BE21 BH14 BK14

AP52 AY54 BJ49 BJ43 BH12 BD2 AY2 AJ3

AR53 BA53 BH50 BK42 BH8 BB2 AV2 AM2 AT54 BB54 BJ51 BH42 BK8 BC3 AW3 AN3

BJ15 BJ33 BH24 BA17 BF36 BH36 BF34 BK34 BJ37 BH40 BH16 BK36 BH38 BJ11 BL37

M_B_BS#0 M_B_BS#1 M_B_BS#2

M_B_RAS# M_B_CAS# M_B_WE#

M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14

M_B_BS#0 (16) M_B_BS#1 (16) M_B_BS#2 (16)

M_B_RAS# (16) M_B_CAS# (16) M_B_WE# (16)

M_B_DM[7:0] (16)

M_B_DQS[7:0] (16)

M_B_DQS#[7:0] (16)

M_B_A[14:0] (16)

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

Cantiga SFF (DDRII)

Date: Sheet of

PROJECT :

ZE8

8 32Tuesday, September 29, 2009

http://goo.gl/lOFD2

Cantiga SFF - VCC/NCTF (CLG)

Ivcc internal VGA 2.4A (Shape or 140mils)

VCC 2200mA

+1.05V

AT41 AR41 AN41 AJ41 AH41 AD41 AC41

AT40

AM40

AL40

AJ40 AH40 AG40 AE40 AD40 AC40

AA40

AN35 AM35

AJ35 AH35 AD35 AC35

AM34

AL34

AJ34 AH34 AG34 AE34 AD34

AC34

AA34

AM32

AL32

AJ32 AH32 AE32 AD32

AA32 AM31

AL31

AJ31 AH31 AM29

AL29 AM28

AL28

AJ28 AM27

AL27 AM25

AL25

AJ25 AM24

Y41

W41

Y40

W35

Y34

W34

N36

U18F

VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12

VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34

VCC_35 VCC_36

VCC_37 VCC_38 VCC_39 VCC_40 VCC_41 VCC_42 VCC_43 VCC_44 VCC_45 VCC_46 VCC_47 VCC_48 VCC_49 VCC_50 VCC_51 VCC_52 VCC_53 VCC_54 VCC_55 VCC_56 VCC_57 VCC_58 VCC_59 VCC_60 VCC_61

CANTIGASFF_1p0

VCC CORE

+1.05V

AT38

VCC_NCTF_1

AR38

VCC_NCTF_2

AN38

VCC_NCTF_3

AM38

VCC_NCTF_4

AL38

VCC_NCTF_5

AG38

VCC_NCTF_6

AE38

VCC_NCTF_7

AA38

VCC_NCTF_8

POWER

VCC NCTF

VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38

Y38 W38 U38 T38 R38 AT37 AR37 AN37 AM37 AL37 AJ37 AH37 AG37 AE37 AD37 AC37 AA37 Y37 W37 U37 T37 R37 AT35 AR35 U35 AT34 AR34 U34 T34 R34

Differential routing

GFX_VCCSENSE(29) GFX_VSSSENSE(29)

VCC_SM(+1.5V_SUS) DDR3(800M) : 3162.5mA DDR3(1067M) : 4140mA

+1.5V_SUS

+VCC_SM_BB36 +VCC_SM_BE35

C217

C216

0.1u/10V_4

VCC_SM :3000mA

+VCC_SM_BC29

C213

0.1u/10V_4

+VCC_SM_BF24 +VCC_SM_BL19 +VCC_SM_BB16

C209

0.1u/10V_4

C424

0.1u/10V_4

C206

0.1u/10V_4

+VGFX

VCC_AXG 7700mA

+VGFX

R108

10/F_4

R107

10/F_4

1. Route VCC_AXG_SENSE and VSS_AXG_SENSE differentially

2. VCC_AXG_SENSE PU to +VGFX_CORE_INT with 10ohm and VSS_AXG_SENSE PD with 10ohm for Intel suggest

BB36

BE35 AW34 AW32

BK30

BH30

BF30

BD30

BB30 AW30

BL29

BJ29

BG29

BE29

BC29

BA29

AY29

BK28

BH28

BF28

BD28

BB28

BL27

BJ27

BG27

BE27

BC27

BA27

AY27 AW26

BF24

BL19

BB16

AG31

AE31

AD31

AC31

AA31

AH29

AG29

AE29

AD29

AC29

AA29

AH28

AG28

AE28

AA28

AH27

AG27

AE27

AD27

AC27

AA27

AH25

AD25

AC25

AJ24

AH24

AG24

AE24

AD24

AC24

AA24

AM22

AL22

AJ22

AH22

AG22

AE22

AD22

AC22

AA22 AM21

AL21

AJ21

AH21

AD21

AC21

AA21

AM16

AL16

AG13

AE13

W32

Y31

W31

Y29

W29

Y27

W27

W25

Y24

W24

Y21

W21

U18G

VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33

VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34 VCC_AXG_35 VCC_AXG_36 VCC_AXG_37 VCC_AXG_38 VCC_AXG_39 VCC_AXG_40 VCC_AXG_41 VCC_AXG_42 VCC_AXG_43 VCC_AXG_44 VCC_AXG_45 VCC_AXG_46 VCC_AXG_47 VCC_AXG_48 VCC_AXG_49 VCC_AXG_50 VCC_AXG_51 VCC_AXG_52 VCC_AXG_53 VCC_AXG_54 VCC_AXG_55 VCC_AXG_56 VCC_AXG_57 VCC_AXG_58 VCC_AXG_59 VCC_AXG_60 VCC_AXG_61

VCC_AXG_SENSE VSS_AXG_SENSE

CANTIGASFF_1p0

VCC SMVCC GFX

POWER

VCC GFX NCTF

VCC GFX

VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8

VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21 VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30 VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44

VCC_AXG_62 VCC_AXG_63 VCC_AXG_64 VCC_AXG_65 VCC_AXG_66 VCC_AXG_67 VCC_AXG_68 VCC_AXG_69 VCC_AXG_70 VCC_AXG_71 VCC_AXG_72 VCC_AXG_73 VCC_AXG_74 VCC_AXG_75 VCC_AXG_76 VCC_AXG_77 VCC_AXG_78 VCC_AXG_79 VCC_AXG_80

VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7

VCC SM LF

UMA 9.6A(GM45) (Plane or shape)

+VGFX

T32 U31 T31 R31 U29 T29 R29 U28 U27 T27 R27 U25 T25 R25 U24 U22 T22 R22 U21 T21 R21 AM19 AL19 AH19 AG19 AE19 AD19 AC19 W19 U19 AM18 AL18 AJ18 AH18 AG18 AE18 AD18 AC18 AA18 Y18 W18 U18 T18 R18

AJ16 AH16 AD16 AC16 AA16 U16 T16 R16 AM15 AL15 AJ15 AH15 AG15 AE15 AA15 Y15 W15 U15 T15

VCCSM_LF1

AU45

VCCSM_LF2

BF52

VCCSM_LF3

BB38

VCCSM_LF4

BA19

VCCSM_LF5

BE9

VCCSM_LF6

AU9

VCCSM_LF7

AL9

+1.05V+VGFX

R64 *0_8R64 *0_8

R65 *0_8R65 *0_8

Celeron 723,743 not support graphics render standby mode, so add R64 , R65, del GFX power (Page 29) SU type cpu support it, so del R64, R65 and add GFX power (Page 29)

R183 *0_8R183 *0_8

9/28: add R183 for voltage low issue

+1.05V

C156

*10u/6.3V_8

+1.5V_SUS

C211

10u/6.3V_8

C115

10u/6.3V_8

8/13 : add for EMI

C83

*220u/2.5V_3528

C212

*10u/6.3V_8

C124

0.1u/10V_4

+VGFX

C246

C246 *220p/50V_6

*220p/50V_6

C132

0.1u/10V_4

+VGFX

C203

0.1u/10V_4

C133

0.47u/6.3V_4

C108

*220u/2.5V_3528

C182

0.22u/10V_4

Layout Note: Inside GMCH cavity.

C200

0.1u/10V_4

C128

C107

220u/2.5V_3528

C128

10u/6.3V_6

C127

*1u/16V_6

C201

0.22u/10V_4

C215

10u/6.3V_8

Close to GMCH

Layout Note: 370 mils from edge.

10mil

C205

C163

0.1u/10V_4

C205

0.1u/10V_4

C204

0.22u/10V_4

C207

0.22u/10V_4

C218

0.47u/6.3V_4

Size Document Number Rev

Cantiga SFF (VCC/NCTF)

Date: Sheet of

C197

C210

1u/10V_6

Quanta Computer Inc.

PROJECT :

C247

C247 *220p/50V_6

*220p/50V_6

ZE8

9 32Tuesday, September 29, 2009

http://goo.gl/lOFD2

Cantiga SFF - Power (CLG)

+3V

L9 BLM18PG181SN1D_6L9 BLM18PG181SN1D_6

+1.05V

L27 10uH_8L27 10uH_8

+1.05V

L28 10uH_8L28 10uH_8

+1.05V

R110 Short_6R110 Short_6

L15 BLM18PG181SN1D_6L15 BLM18PG181SN1D_6

C152

+1.05VM_MPLL_RC

10u/6.3V_8

+1.05V

L14 BLM18PG181SN1D_6L14 BLM18PG181SN1D_6

L13 BLM18PG221SN1D_6L13 BLM18PG221SN1D_6

C161

+1.05VM_PEGPLL_RC

10u/6.3V_8

C436

220U/2.5V_3528

C437

220U/2.5V_3528

C155

4.7u/6.3V_6

R106

0.5/F_4

+3V_A_CRT_BG

+1.05VM_DPLLA

C105

0.1u/10V_4

+1.05VM_DPLLB

C110

0.1u/10V_4

+1.05VM_HPLL

C157

0.1u/10V_4

+1.05VM_MPLL

C149

0.1u/10V_4

R109

1/F_4

+1.05V

C198

100u/6.3V_3528

+1.05V

C183

10u/6.3V_8

+1.05VM_MCH_PLL2

+1.05VM_PEGPLL

C158

0.1u/10V_4

+3V

+3V_A_CRT_DAC

C101

0.1u/10V_4

C85

10u/6.3V_8

C126 1000p/50V_4C126 1000p/50V_4

+1.5V

C169

0.1u/10V_4

C188

10u/6.3V_8

C185

*2.2u/6.3V_6

L10

L10 BLM18PG181SN1D_6

BLM18PG181SN1D_6

73mA(20mils)

5mA(10mils)

C94

0.1u/10V_4

64mA(20mils)

24mA(20mils)

139.2mA(20mils)

10mA(20mils)

414uA(10mils)

50mA(10mils)

720mA(40mils)

C184

4.7u/6.3V_6

26mA(20mils)

C186

0.1u/10V_4

157.2mA(20mils)

C164

0.1u/10V_4

50mA(20mils)

30mA(20mils)

C102

0.01u/25V_4

C95

0.01u/25V_4

+1.05VM_PEGPLL

C189

1u/6.3V_4

+1.8V

C111

1u/6.3V_4

U18H

J31

VCCA_CRT_DAC

L31

VCCA_DAC_BG

M33

VSSA_DAC_BG

J45

VCCA_DPLLA

L49

VCCA_DPLLB

AF10

VCCA_HPLL

AE1

VCCA_MPLL

U43

VCCA_LVDS1

U41

VCCA_LVDS2

V44

VSSA_LVDS

AJ43

VCCA_PEG_BG

AG43

VCCA_PEG_PLL

AW24

VCCA_SM_1

AU24

VCCA_SM_2

AW22

VCCA_SM_3

AU22

VCCA_SM_4

AU21

VCCA_SM_5

AW20

VCCA_SM_6

AU19

VCCA_SM_7

AW18

VCCA_SM_8

AU18

VCCA_SM_9

AW16

VCCA_SM_10

AU16

VCCA_SM_11

AT16

VCCA_SM_12

AR16

VCCA_SM_13

AU15

VCCA_SM_14

AT15

VCCA_SM_15

AR15

VCCA_SM_16

AW14

VCCA_SM_17

AT24

VCCA_SM_NCTF_1

AR24

VCCA_SM_NCTF_2

AT22

VCCA_SM_NCTF_3

AR22

VCCA_SM_NCTF_4

AT21

VCCA_SM_NCTF_5

AR21

VCCA_SM_NCTF_6

AT19

VCCA_SM_NCTF_7

AR19

VCCA_SM_NCTF_8

AT18

VCCA_SM_NCTF_9

AR18

VCCA_SM_NCTF_10

AU27

VCCA_SM_CK_4

AU28

VCCA_SM_CK_3

AU29

VCCA_SM_CK_2

AU31

VCCA_SM_CK_1

AT31

VCCA_SM_CK_NCTF_1

AR31

VCCA_SM_CK_NCTF_2

AT29

VCCA_SM_CK_NCTF_3

AR29

VCCA_SM_CK_NCTF_4

AT28

VCCA_SM_CK_NCTF_5

AR28

VCCA_SM_CK_NCTF_6

AT27

VCCA_SM_CK_NCTF_7

AR27

VCCA_SM_CK_NCTF_8

AH12

VCCD_HPLL

AE43

VCCD_PEG_PLL

M46

VCCD_LVDS_1

L45

VCCD_LVDS_2

CANTIGASFF_1p0

CRTPLLA PEGA SM

A LVDS

POWER

LVDS

VCCA_TV_DAC

TVD TV/CRT

HDA

VCCD_QDAC

VCCD_TVDAC

VCC_AXF_1 VCC_AXF_2 VCC_AXF_3

AXF

VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4

SM CK

VCC_TX_LVDS

VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4

PEG

VCC_DMI_1 VCC_DMI_2 VCC_DMI_3

DMI

VTTLF

VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8

VTT_9 VTT_10 VTT_11 VTT_12 VTT_13

VTT

VCC_HDA

VCC_HV_1 VCC_HV_2

VTTLF1 VTTLF2 VTTLF3

R13 T12 R11 T10 R9 T8 R7 T6 R5 T4 R3 T2 R1

K30

A31

N34

N32

M25 N24 M23

BK24 BL23 BJ23 BK22

T41

C33 A33

AB44 Y44 AC43 AA43

AM44 AN43 AL43

K14 Y12 P2

C146

0.47u/6.3V_4

456mA(30mils)

+VTTLF_CAP1 +VTTLF_CAP2 +VTTLF_CAP3

10mil

852mA(50mils)

C131

2.2u/6.3V_6

79mA(20mils)

C97

0.01u/25V_4

50mA(15mils)

2.7mA(15mils)

C103

0.01u/25V_4

35mA(15mils)

440mA(30mils)

C106

1u/6.3V_4

DDR3-800 124mA (20mils)

80mA(20mils)

105.3mA(20mils)

1.782A(100mils)

C202

0.1u/10V_4

C430

0.47u/6.3V_4

C148

C130

4.7u/6.3V_6

C96

0.1u/10V_4

C112

0.1u/10V_4

+1.05V

Check list 2.2 DDR3=>0 ohm DDR2=>0.1uH, DCR<160 mohm

C147

0.47u/6.3V_4

C148

4.7u/6.3V_6

+3V_TV_DAC

+1.5V_VCC_HDA

C438

HD@NHD@0.1u/10V_4

+1.5V_QDAC

+1.5V_TVDAC+1.8V_TXLVDS

C151

10u/6.3V_6

+1.5VSUS_VCC_SM_CK

C420

0.1u/10V_4

+1.8V_TXLVDS

C125

1000p/50V_4

+1.05V

C98

0.47u/6.3V_4

C199

4.7u/6.3V_6

+1.05V

C160

*10u/6.3V_6

R89 Short_6R89 Short_6

R298 HD@0_6R298 HD@0_6

+3V

+1.5V

Enable HDMI C394= 0.1uF

Disable HDMI C394= 0Ω

+1.5V

L11

BLM18PG181SN1D_6

R88 Short_6R88 Short_6

C86

C114

0.01u/25V_4

Clock supply(1.5V) DDR3(1066):149.5mA

R265

1/F_4

+1.5VSUS_SMCK_RC

LVDS Transmitter(1.8V)

118.8mA

C129

10u/6.3V_6

C91

0.1u/10V_4

C196

10u/6.3V_8

Size Document Number Rev

Date: Sheet of

C86

0.1u/10V_4

+1.5V_SUS

L26

1uH/300MA_8

C417

10u/6.3V_6

R114 Short_6R114 Short_6

R86 10_4R86 10_4

Cantiga SFF (Power)

+1.8V

+1.05V_SD

+1.05V

C171

*10u/6.3V_6

Quanta Computer Inc.

PROJECT :

+1.05V

D11

CH751H-40PT

+3V

ZE8

10 32Tuesday, September 29, 2009

http://goo.gl/lOFD2

Cantiga SFF - GND (CLG)

BA55 AU55 AN55

AJ55 AE55 AA55

U55

N55 BD54 BG53

AJ53 AE53 AA53

U53 N53 J53

G53

E53

K52 BG51 BA51 AW51 AU51 AR51 AN51

AL51

AJ51 AG51 AE51 AC51 AA51

W51

U51 R51 N51 L51 J51

G51

C51 BK50 AM50

K50 BG49

E49

C49 BD48 BB48 AY48 AV48

AT48 AP48 AM48 AK48 AH48

AF48 AD48 AB48

Y48 V48 T48 P48

M48

K48 H48

BL47 BG47

E47 C47

A47 BD46 AY46 AM46 AK46 AH46 BG45 AE45 AC45 AA45

W45

R45

N45

E45 BD44 BB44 AV44 AK44 AH44

AF44

AD44

K44

H44

BL43 BG43 AY43 AR43

W43

R43

M43

E43

U18I

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99

CANTIGASFF_1p0

VSS

VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198

C43 A43 BD42 H42 BG41 AY41 AU41 AM41 AL41 AG41 AE41 AA41 R41 M41 E41 BD40 AU40 AR40 AN40 W40 U40 T40 R40 K40 H40 BL39 BG39 BA39 E39 C39 A39 BD38 AU38 H38 BG37 AU37 M37 E37 BD36 AW36 H36 BL35 BG35 AY35 AU35 AL35 AG35 AE35 AA35 Y35 M35 E35 A35 BD34 AU34 AN34 H34 BL33 BG33 AY33 E33 BD32 AU32 AN32 AG32 AC32 Y32 H32 B32 BJ31 BG31 AY31 AN31 M31 E31 N30 H30 AN29 AJ29 M29 A29 AW28 AN28 AD28 AC28 Y28 W28 H28 F28 AN27 AJ27 M27 BF26 BD26 N26 H26 BJ25 AY25 AU25

U18J

AN25

VSS_199

AG25

VSS_200

AE25

VSS_201

AA25

VSS_202

Y25

VSS_203

E25

VSS_204

A25

VSS_205

BD24

VSS_206

AN24

VSS_207

AL24

VSS_208

H24

VSS_209

BG23

VSS_210

AY23

VSS_211

E23

VSS_212

BD22

VSS_213

BB22

VSS_214

AN22

VSS_215

Y22

VSS_216

W22

VSS_217

H22

VSS_218

BL21

VSS_219

BG21

VSS_220

AY21

VSS_221

AN21

VSS_222

AG21

VSS_223

AE21

VSS_224

M21

VSS_225

E21

VSS_226

A21

VSS_227

BD20

VSS_228

H20

VSS_229

BG19

AY19

M19 E19

BD18

N18 H18

BL17

BG17

AY17

M17 E17

A17 BD16 AN16 AG16

AE16

Y16

W16

N16

H16 BG15

AY15 AN15 AD15 AC15

R15 M15 E15

BD14

H14

BL13 BG13

AY13 AU13 AR13

AJ13 AC13

AA13

W13

U13 M13 E13 A13

BD12

AV12

AP12 AM12

AK12

AB12

V12 P12

H12 BG11 AG11

E11 BD10

AY10 AP10

H10

BL9

BG9

A9 BD8 BB8 AY8 AV8 AT8 AP8

VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299

CANTIGASFF_1p0

VSS

VSS NCTF

VSS SCB

VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358

VSS_359 VSS_360 VSS_361 VSS_362

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8

VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23

VSS_SCB_1 VSS_SCB_2 VSS_SCB_3 VSS_SCB_4 VSS_SCB_5 VSS_SCB_6 VSS_SCB_7

AM8 AK8 AH8 AF8 AD8 AB8 Y8 V8 P8 M8 K8 H8 BJ7 E7 BF6 BC5 BA5 AW5 AU5 AR5 AN5 AL5 AJ5 AG5 AE5 AC5 AA5 W5 U5 N5 L5 J5 G5 C5 BH4 BE3 U3 E3 BC1 AW1 AR1 AL1 AG1 AC1 W1 N1 J1 AU43 BB42 AW38 BA35 L29 N28 N22 N20 N14 AL13 B10 AN13

N42 N40 N38 M39

AJ38 AH38 AD38 AC38 T35 R35 AT32 AR32 U32 R32 T28 R28 AT25 AR25 T24 R24 AN19 AJ19 AA19 Y19 T19 R19 AN18

BL55 BL1 A55 D1 B55 B2 A4

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

Cantiga SFF (GND)

Date: Sheet of

PROJECT :

ZE8

11 32Tuesday, September 29, 2009

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