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ZE7 DA0ZE7MB6D0
Schematic
41 pgs861.94 Kb18

Quanta ZE7 DA0ZE7MB6D0, Aspire One AOD270 Schematic

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1
ZE7 Block Diagram (Intel Cedar Trail-M Platform)
2
3
4
5
6
7
8
01
DDI0
P17
LVDS 18bit,SC
1366x768
1920x1200
4
P18
HDMI 1.3a
DDI1
1366x768
DAC
PCIE Gen1
USB 2.0
A A
HDMI CONN
LVDS/eDP CONN
VGA CONN
B B
RTL8105TA-VC-CG
RJ45 CONN
P22
P22
0
2
RTS5209-GR CARDREADER
C C
USB PORT
Left
5 IN1 CARDREADER
SD3.0, MS, MS PRO, xD, MMC
3
P21
0 21
USB PORT
Right Down Right Up
P26
P21
P18
P18
3
1
P26
USB PORT
Mini card2
Mini card1
MM-SIM CARD
USB interface module
P21
P25
P25
P19
0ohm
5
7
P25
6
CCD
Cedarview-M
400 / 640MHz
DC(3.5W) & DC(6.5W)
(32nm)
Micro-FCBGA8
(22x22mm)
P5~9
x2 DMI Gen1
Tigerpoint (NM10)
1.5W
vFBGA
(360 balls,17x17mm)
P10~15
DDR III,800/1066 MT/s
Channel A
HD AUDIO I/F
SATA II I/F
0
Mobile 2.5" HDD
CLK Gen. SLG8LV631V
UNBUFFERED DDRIII SODIMM
RC-B/F CLK2/3, H=4
Audio CODEC Realtek 271X
P24
P20
P2
P4
MIC In Jack Analog MIC Speaker Header (2W)
P20
EC
BATTERY CHAGER
D D
SYSTEM 5V/3V PCU
P29
P30
DDR 1.5VSUS
+1.05V
CPU Core Gfx Core
P31
1
2
Discharge/+1.8V/
P32
+3.3V_PRIME Thermal Protection
P33
P34
P35
3
Keyboard
4
Touch Pad
P19 P19 P29
Nuvoton NPCE791L
SPI Flash
5
Charger
P27
PWM FAN
6
P27
P6
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
7
PROJECT :
Block Diagram
Block Diagram
Block Diagram
ZE7
ZE7
ZE7
1 40Wednesday, November 02, 2011
1 40Wednesday, November 02, 2011
1 40Wednesday, November 02, 2011
8
5
CLK GEN (CLK)
+3V
L32
PBY160808T-301Y-N/2A/300ohm_6
D D
PBY160808T-301Y-N/2A/300ohm_6
L32
Place close to L32
VDD_IO can be ranging from 1.05V to 3.3V.
+1.05V
L28
L28 PBY160808T-301Y-N/2A/300ohm_6
R311
R311 *20K/J_4
*20K/J_4
R310
R310 *100K_4
*100K_4
C238
C238 33P/50V_4
33P/50V_4
C236
C236 33P/50V_4
33P/50V_4
PBY160808T-301Y-N/2A/300ohm_6
CG_XIN
21
Y2 14.318MHZY2 14.318MHZ
Load Capacitance=20p
CG_XOUT
<20110110> CFG input hardware strapping to allocate PLL assignment. LOW = Both CPU and SRC clock drive from PLL3 HIGH = CPU clock drive from PLL1, SRC clock drive from PLL3. Contains 100kΩ pull-down resistor.
R221 *0/short_6R221 *0/short_6
Place close to L28
C C
<Layout note> Crystal place within 500mil of CK505
+3V
B B
VDD_CLK_3.3V
C228
C228 10U/10V_8
10U/10V_8
C285
C285 10U/10V_8
10U/10V_8
C278
C278
C254
C254
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
0.1uF near every power pin
VDD_CLKIO_1.05V
C229
C229
C249
C249
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
0.1uF near every power pin
CLKUSB_48[10]
14M_ICH[13]
PCLK_ICH[12] LCLK_EC[27]
PCLK_DEBUG[25]
SMBDT1[4,13,25] SMBCK1[4,13,25]
C253
C253 .1U/10V_4
.1U/10V_4
C242
C242 .1U/10V_4
.1U/10V_4
R312 33/J_4R312 33/J_4
R293 33/J_4R293 33/J_4
R296 22/J_4R296 22/J_4 R304 22/J_4R304 22/J_4 R291 33/J_4R291 33/J_4
4
CG_XOUT CG_XIN
SMBDT1 SMBCK1
FSB USB_48M
FSC
ITP_EN 33M_SEL
U12
U12
5
VDD_REF_3.3
9
VDD_PCI_3.3
14
VDD_48M_3.3
30
VDD_SRC_IO_1.05
35
VDD_SRC_IO_1.05
48
VDD_CPU_IO_1.05
1
NC
2
NC
13
NC
54
NC
3
XTAL_OUT
4
XTAL_IN
7
SDA
8
SCL
15
USB48_1/FSB
17
USB48_2
6
REF/FSC
10
PCIF/ITP_EN
11
25MHz/PCI_2/SEL_33MHz
12
VSS_PCI
16
VSS_48M
22
VSS_LCD
24
VSS_SATA
39
VSS_SRC
51
VSS_CPU
56
VSS_REF
57
Thermal Pad
SLG8LV631V
SLG8LV631V
VDD_CORE_1.5 VDD_CORE_1.5
PCI_STOP#
CPU_STOP#
CPU_0
CPU_0#
CPU_1
CPU_1#
SRC_1/CPU_ITP
SRC_1/CPU_ITP#
SRC_2
SRC_2#
SRC_3
SRC_3#
SRC_4
SRC_4#
SRC_5
SRC_5#
SRC_6
SRC_6#
DOT96/SRC7
DOT96#/SRC7#
LCD_CLK
LCD_CLK#
SATA
SATA#
CLKREQ_A# CLKREQ_B# CLKREQ_C#
CKPWRGD/PD#
23 45
36 42
53 52
50 49
44 43
41 40
38 37
34 33
32 31
28 27
18 19
20 21
26 25
CLKREQ_LAN#_R
47
CLKREQ_MPC#_R
46
CLKREQ_MMC#_R
29
HWPG
55
PM_STPPCI#_R PM_STPCPU#_R
DREFCLK_R DREFCLK#_R
3
VDD_CLK_1.5V
C277
C277
C225
C225
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
0.1uF near every power pin
R251 *0/J_4R251 *0/J_4 R229 *0/J_4R229 *0/J_4
R299 *0/J_4R299 *0/J_4 R300 *0/J_4R300 *0/J_4
R204 475/F_4R204 475/F_4 R199 475/F_4R199 475/F_4 R284 475/F_4R284 475/F_4
C357
C357 *0.1U/10V_4
*0.1U/10V_4
2
R219 2.2/J_6R219 2.2/J_6
1 2
C224
C224 10U/10V_8
10U/10V_8
PBY160808T-301Y-N/2A/300ohm_6
PBY160808T-301Y-N/2A/300ohm_6
<20100819_FAE Poyueh> Add 2.2ohm resistor for noise suppress
+1.5V
L27
L27
Place close to L27
<20100803_Sam> Reserve 0ohm to connect to CK505, 10Kohm pull up is required.
PM_STPPCI# [13] PM_STPCPU# [13]
CLK_MCH_BCLK [6] CLK_MCH_BCLK# [6]
CLK_DDR3_REFCLK [8] CLK_DDR3_REFCLK# [8]
CLK_PCIE_LANP [22] CLK_PCIE_LANN [22]
CLK_PCIE_MNC_P [25] CLK_PCIE_MNC_N [25]
CLK_PCIE_MPC_P [25] CLK_PCIE_MPC_N [25]
CLK_PCIE_DMIP [5] CLK_PCIE_DMIN [5]
CLK_PCIE_MMC_P [26] CLK_PCIE_MMC_N [26]
CLK_PCIE_ICH [10] CLK_PCIE_ICH# [10]
DREFCLK [5] DREFCLK# [5]
DREFSSCLK [5] DREFSSCLK# [5]
CLK_PCIE_SATA [11] CLK_PCIE_SATA# [11]
<20100819> Add 475ohm resistors to prevent current leakage
CLKREQ_LAN# [22] CLKREQ_MPC# [25] CLKREQ_MMC# [26]
HWPG [13,16,27]
<20110221> Reserve 0.1F cap to solve that PCICLK (EC 33MHz) sometimes will change to 25MHz after flash BIOS and restart in first time issue.
From SB
To CPU (Host CLK) 100 MHz
To CPU (DDR3 IO CLK)
To Mini Card 2 (3G/Wimax) 100 MHz
To CPU (DMI CLK) 100 MHz
To SB (DMI CLK) 100 MHz
To CPU (DPLSS CLK) 100 MHz
Control SRC_1
Register B5b6 for CLKREQ_A# 0 = SRC1, 1=SRC2 Register B5b4 for CLKREQ_B#
Control SRC_3
0 = SRC3, 1=SRC4
Control SRC_5 Register B5b3 for CLKREQ_C#
0 = SRC5, 1=SRC6
100 MHz
100 MHzTo LAN (LAN)
<20101109> Place R235/ R241/ R248/ R254 close to U13
100 MHzTo Mini Card 1 (WLAN)
100 MHzTo Card Reader (MMC)
96 MHzTo CPU (PLL CLK)
<20110110> DPL_REFSSCCLK is used to drive internal registers and logics of the display interface and therefore needs to be present at all times.
100 MHzTo SB (SATA CLK)
1
02
FSC FSB Frequency 0 0 133MHz 0 1 166MHz
R313 *10K/J_4R313 *10K/J_4
+3V
A A
R306 10K/J_4R306 10K/J_4
R301 10K/J_4R301 10K/J_4
+3V +3V +3V
R295 *10K/J_4R295 *10K/J_4
1 = Pin 43/44 as CPU_ITP
ITP_EN
0 = Pin 43/44 as SRC_1
33M_SEL FSC
1 = Pin 11 as 33MHz
0= Pin 11 as 25MHz
5
1 1 200MHz
1 0 100MHz
R289 10K/J_4R289 10K/J_4
R259 *10K/J_4R259 *10K/J_4
<20100720_Sam> Keep 100MHz as default.
R317 *10K/J_4R317 *10K/J_4
FSB
R318 10K/J_4R318 10K/J_4
4
<EMI>
USB_48M
ITP_EN
FSB
FSC
33M_SEL
C280 *10P/50V_4C280 *10P/50V_4
C259 *10P/50V_4C259 *10P/50V_4
C279 *10P/50V_4C279 *10P/50V_4
C245 *10P/50V_4C245 *10P/50V_4
C266 *10P/50V_4C266 *10P/50V_4
3
PM_STPPCI#_R
PM_STPCPU#_R
CLKREQ_MPC#_R
CLKREQ_MMC#_R
CLKREQ_LAN#_R
R250 10K/J_4R250 10K/J_4
R230 10K/J_4R230 10K/J_4
R213 10K/J_4R213 10K/J_4
R279 10K/J_4R279 10K/J_4
R212 10K/J_4R212 10K/J_4
2
+3V
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROJECT :
CLOCK GENERATOR
CLOCK GENERATOR
CLOCK GENERATOR
ZE7
ZE7
ZE7
2 40Wednesday, November 02, 2011
2 40Wednesday, November 02, 2011
1
2 40Wednesday, November 02, 2011
1B
1B
1B
5
4
3
2
1
03
D D
C C
B B
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
PROJECT :
Reserved
Reserved
Reserved
ZE7
ZE7
ZE7
1B
1B
1B
3 40Wednesday, November 02, 2011
3 40Wednesday, November 02, 2011
3 40Wednesday, November 02, 2011
1
5
DDR_STD(DDR)
M_A_A[15:0][8]
D D
C C
B B
Populate rules: populate SODIMM1 first Strictly follow the mapping between clock/control signal groups and SODIMMs, as well as SMB address. Other configurations/mappings will not be supported by MRC
DESIGN NOTE:
+3V
ADDRESS-(A2)H
R150
R150 10K/J_4
10K/J_4
R170
R170
R151
R151 *10K/J_4
*10K/J_4
10K/J_4
10K/J_4
M_A_BS0[8] M_A_BS1[8] M_A_BS2[8] M_CS#2[8] M_CS#3[8] M_CLK2[8] M_CLK2#[8] M_CLK3[8] M_CLK3#[8] M_CKE2[8] M_CKE3[8] M_A_CAS#[8] M_A_RAS#[8] M_A_WE#[8]
SMBCK1[2,13,25] SMBDT1[2,13,25]
M_ODT2[8] M_ODT3[8] M_A_DM[7:0][8]
M_A_DQS[7:0][8]
M_A_DQS#[7:0][8]
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15
DIMM1_SA0 DIMM1_SA1 SMBCK1 SMBDT1
M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7
M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7
98 97 96 95 92 91 90 86 89 85
107
84 83
119
80 78
109 108
79 114 121 101 103 102 104
73
74 115 110 113 197 201 202 200
116 120
11
28
46
63 136 153 170 187
12
29
47
64 137 154 171 188
10
27
45
62 135 152 169 186
4
DIMM0 H=4mm
JDIM1A
JDIM1A
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC# A13 A14 A15
BA0 BA1 BA2 S0# S1# CK0 CK0# CK1 CK1# CKE0 CKE1 CAS# RAS# WE# SA0 SA1 SCL SDA
ODT0 ODT1
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS#0 DQS#1 DQS#2 DQS#3 DQS#4 DQS#5 DQS#6 DQS#7
DDR3-DIMM0_H=4_STD
DDR3-DIMM0_H=4_STD
PC2100 DDR3 SDRAM SO-DIMM
PC2100 DDR3 SDRAM SO-DIMM
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8
DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46
(204P)
(204P)
DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
3
+1.5VSUS
+3V
C179
C179
DDR3_DRAMRST#[8]
2.48A
C178
C178
.1U/10V_4
.1U/10V_4
+SMDDR_VREF_DQ0 +SMDDR_VREF_DIMM
5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194
M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63
M_A_DQ[63:0] [8]
.1U/10V_4
.1U/10V_4
2
JDIM1B
JDIM1B
75
VDD1
76
VDD2
81
VDD3
82
VDD4
87
VDD5
88
VDD6
93
VDD7
94
VDD8
99
VDD9
100
VDD10
105
VDD11
106
VDD12
111
VDD13
112
VDD14
117
VDD15
118
VDD16
123
VDD17
124
VDD18
199
VDDSPD
77
NC1
122
NC2
125
NCTEST
198
EVENT#
30
RESET#
1
VREF_DQ
126
VREF_CA
2
VSS1
3
VSS2
8
VSS3
9
VSS4
13
VSS5
14
VSS6
19
VSS7
20
VSS8
PC2100 DDR3 SDRAM SO-DIMM
VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15
R191 1K/F_4R191 1K/F_4
PC2100 DDR3 SDRAM SO-DIMM
25 26 31 32 37 38 43
DDR3-DIMM0_H=4_STD
DDR3-DIMM0_H=4_STD
<Layout note> PLACE TWO 1K RESISTORS CLOSE TO CPU DIMM ON DDR_VREF_CA
+1.5VSUS
C194
C194
.1U/10V_4
.1U/10V_4
44
VSS16
48
VSS17
49
VSS18
54
VSS19
55
VSS20
60
VSS21
61
VSS22
65
VSS23
66
VSS24
71
VSS25
72
VSS26
127
VSS27
128
VSS28
133
VSS29
134
VSS30
138
VSS31
139
VSS32
144
VSS33
145
VSS34
150
VSS35
151
VSS36
155
VSS37
156
VSS38
161
VSS39
162
VSS40
167
VSS41
168
VSS42
172
VSS43
173
VSS44
178
VSS45
179
VSS46
184
VSS47
185
VSS48
189
VSS49
190
VSS50
195
VSS51
196
VSS52
(204P)
(204P)
203
VTT1
204
VTT2
205
GND
206
GND
R198 *0/J_4R198 *0/J_4
+SMDDR_VREF_DIMM_R
R208
R208 1K/F_4
1K/F_4
+0.75V_DDR_VTT
+SMDDR_VREF
R205 0/J_4R205 0/J_4
1
+SMDDR_VREF
+SMDDR_VREF_DIMM
C205
C205
0.1U/50V_6
0.1U/50V_6
04
<Layout note> PLACE TWO 1K RESISTORS CLOSE TO CPU DIMM ON DDR_VREF_DQ
Place these Caps near DIMM0
+1.5VSUS
+
C199
C198
C198 10U/6.3V_6
10U/6.3V_6
C192
C192 1U/6.3V_4
1U/6.3V_4
C199 10U/6.3V_6
10U/6.3V_6
C189
C189 1U/6.3V_4
1U/6.3V_4
C197
C197 10U/6.3V_6
10U/6.3V_6
C196
C196 10U/6.3V_6
10U/6.3V_6
C168
C169
C169
C193
.1U/10V_4
.1U/10V_4
C162
C162 1U/6.3V_4
1U/6.3V_4
C193 .1U/10V_4
.1U/10V_4
C173
C173 1U/6.3V_4
1U/6.3V_4
C164
C164 1U/6.3V_4
1U/6.3V_4
5
C171
C171 .1U/10V_4
.1U/10V_4
A A
+1.5VSUS
C191
C191 1U/6.3V_4
1U/6.3V_4
C163
C163 10U/6.3V_6
10U/6.3V_6
C165
C165 1U/6.3V_4
1U/6.3V_4
C168 10U/6.3V_6
10U/6.3V_6
C161
C161 1U/6.3V_4
1U/6.3V_4
+
C203
C203
*330U/2V_7343
*330U/2V_7343
4
<20100827> Add by DG request
+0.75V_DDR_VTT
C190
C190
C200
C200
C172
C172
10U/6.3V_6
10U/6.3V_6
LAYOUT NOTE: PLACE CAPS NEAR DIMM-0
+SMDDR_VREF_DQ0
C170
C170
.1U/10V_4
.1U/10V_4
*10U/6.3V_6
*10U/6.3V_6
C167
2.2U/6.3V_6
2.2U/6.3V_6
*10U/6.3V_6
*10U/6.3V_6
.1U/10V_4
.1U/10V_4
C216
C216
3
C185
C185
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
+SMDDR_VREF_DIMM
C214
C214
2.2U/6.3V_6
2.2U/6.3V_6
C176
C176
+1.5VSUS
C160
C160
.1U/10V_4
.1U/10V_4
+0.75V_DDR_VTT
C175
C175
1U/6.3V_4
1U/6.3V_4
R148 1K/F_4R148 1K/F_4
C184
C184
1U/6.3V_4
1U/6.3V_4C167
2
R149 *0/J_4R149 *0/J_4
+SMDDR_VREF_DQ0_R
R147
R147 1K/F_4
1K/F_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
+SMDDR_VREF
R146 0/J_4R146 0/J_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
DDRIII SO-DIMM-0
DDRIII SO-DIMM-0
DDRIII SO-DIMM-0
+SMDDR_VREF
+SMDDR_VREF_DQ0
C166
C166
0.1U/50V_6
0.1U/50V_6
1
ZE7
ZE7
ZE7
1B
1B
4 40Wednesday, November 02, 2011
4 40Wednesday, November 02, 2011
4 40Wednesday, November 02, 2011
1B
5
Cedar View (CPU)
HDMI: 7.5", 4 via, 1.65 Gbps
Level Shifter For HDMI
D D
TX2_HDMI+[17] TX2_HDMI-[17] TX1_HDMI+[17] TX1_HDMI-[17] TX0_HDMI+[17] TX0_HDMI-[17] TX3_HDMI+[17] TX3_HDMI-[17]
eDP: 7", 3 via, 2.7Gbps
+1.5V
R32
R32
C55 1U/6.3V_4C55 1U/6.3V_4
0/J_6
0/J_6
<20101125_Colt> Please follow PDG, we will
C C
doing BOM stuff changing in next version CRB
+3V
ACZ_BITCLK_CPU[13] ACZ_SYNC_CPU[13]
ACZ_SDINO[13] ACZ_SDOUT_CPU[13]
ACZ_RST#_CPU[13]
DDI0_HDMI_SCL[17] DDI0_HDMI_SDA[17]
T33T33 T31T31
HDMI_DDI0_HPD#[17]
TX2_HDMI+
C66 .1U/10V_4C66 .1U/10V_4
TX2_HDMI-
C67 .1U/10V_4C67 .1U/10V_4
TX1_HDMI+
C61 .1U/10V_4C61 .1U/10V_4
TX1_HDMI-
C68 .1U/10V_4C68 .1U/10V_4
TX0_HDMI+
C43 .1U/10V_4C43 .1U/10V_4
TX0_HDMI-
C44 .1U/10V_4C44 .1U/10V_4
TX3_HDMI+
C41 .1U/10V_4C41 .1U/10V_4
TX3_HDMI-
C42 .1U/10V_4C42 .1U/10V_4
T3T3 T9T9
R68 *2.2K/J_4R68 *2.2K/J_4 R62 *eDP@2.2K/J_4R62 *eDP@2.2K/J_4
DDI1_AUX_DP[18] DDI1_AUX_DN[18]
DDI1_HPD#[18]
DDI1_TX0_DP[18] DDI1_TX0_DN[18] DDI1_TX1_DP[18] DDI1_TX1_DN[18] DDI1_TX2_DP[18] DDI1_TX2_DN[18] DDI1_TX3_DP[18] DDI1_TX3_DN[18]
T11T11 T7T7
R45 7.5K/F_4R45 7.5K/F_4
R42 33/J_4R42 33/J_4
H_RSVD_TP_H15
DDI0_AUXP DDI0_AUXN
HDMI_DDI0_HPD# DDI0_TX2_DP
DDI0_TX2_DN DDI0_TX1_DP DDI0_TX1_DN DDI0_TX0_DP DDI0_TX0_DN DDI0_TX3_DP DDI0_TX3_DN
H_RSVD_TP_J15 DDI1_DDC_SCL
DDI1_DDC_SDA DDI1_AUX_DP
DDI1_AUX_DN DDI1_HPD# DDI1_TX0_DP
DDI1_TX0_DN DDI1_TX1_DP DDI1_TX1_DN DDI1_TX2_DP DDI1_TX2_DN DDI1_TX3_DP DDI1_TX3_DN
H_RSVD_TP_H17 H_RSVD_TP_J17
BREF1.8V EXT_BANDGAP
ACZ_SDINO_R
4
U24C
U24C
H25
DDI0_DDC_SCL
J22
DDI0_DDC_SDA
C8
DDI0_AUXP
B8
DDI0_AUXN
H22
DDI0_HPD
G2
DDI0_TXP0
G3
DDI0_TXN0
F3
DDI0_TXP1
F2
DDI0_TXN1
D4
DDI0_TXP2
C3
DDI0_TXN2
B7
DDI0_TXP3
A7
DDI0_TXN3
H15
RSVD_TP_H15
J15
RSVD_TP_J15
F25
DDI1_DDC_SCL
G27
DDI1_DDC_SDA
D10
DDI1_AUXP
C10
DDI1_AUXN
D26
DDI1_HPD
E11
DDI1_TXP0
F11
DDI1_TXN0
J11
DDI1_TXP1
H11
DDI1_TXN1
F13
DDI1_TXP2
E13
DDI1_TXN2
J13
DDI1_TXP3
K13
DDI1_TXN3
J17
RSVD_TP_J17
H17
RSVD_TP_H17
E15
BREF18V
F15
BREFREXT
H21
AZIL_BCLK
F22
AZIL_SYNC
E22
AZIL_SDI
F21
AZIL_SDO
E21
AZIL_RST#
CDV_22MM_REV1P10
CDV_22MM_REV1P10
CEDARVIEW
CEDARVIEW
DDI
DDI
IHDA
IHDA
REV = 1.10
REV = 1.10
LVDS VGA
LVDS VGA
DPL_REFSSCCLKP DPL_REFSSCCLKN
LVDS_CTRL_CLK
LVDS_CTRL_DATA
LVDS_DDC_DATA
3 OF 6
3 OF 6
CRT_HSYNC CRT_VSYNC
CRT_RED
CRT_GREEN
CRT_BLUE
CRT_IRTN CRT_IREF
CRT_DDC_DATA
CRT_DDC_CLK
DPL_REFCLKP DPL_REFCLKN
LVDS_DDC_CLK
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDS_TXP0
LVDS_TXN0
LVDS_TXP1
LVDS_TXN1
LVDS_TXP2
LVDS_TXN2
LVDS_TXP3
LVDS_TXN3 LVDS_CLKP
LVDS_CLKN
PANEL_BKLTCTL
PANEL_BKLTEN
PANEL_VDDEN
3
D14 C14
B12 B11 C11
D12 A13
E29 E27
F17 E17
B9 A9
F28 E24
G24 H24
LIBG
E10 F10
H2 H3
G10 H10 F8 E8 H7 H8 G5 G6
H4 J4
G22 E25 F29
CRT_IREF
R408 681/F_6R408 681/F_6
CRT_DDC_SDA [18] CRT_DDC_SCL [18]
DREFCLK_R1 DREFCLK#_R1
R426 *0/short_6R426 *0/short_6 R428 *0/short_6R428 *0/short_6
LBKLT_EN INT_LVDS_DIGON_Q
R406 *0/J_4R406 *0/J_4 R405 *0/J_4R405 *0/J_4
R52 *2.2K/J_4R52 *2.2K/J_4 R48 *2.2K/J_4R48 *2.2K/J_4
LCD_CLK [18] LCD_DATA [18]
R612.37K/F_4 R612.37K/F_4
TXLOUT0+ [18] TXLOUT0- [18] TXLOUT1+ [18] TXLOUT1- [18] TXLOUT2+ [18] TXLOUT2- [18]
TXLCLKOUT+ [18] TXLCLKOUT- [18]
R414
R414 150/F_4
150/F_4
R65
R65 *10K/J_4
*10K/J_4
R397 *1K/J_4R397 *1K/J_4 R398 *1K/J_4R398 *1K/J_4
CRT_HSYNC [18] CRT_VSYNC [18]
R415
R415
R413
R413
150/F_4
150/F_4
150/F_4
150/F_4
+3V
T51T51 T52T52
INT_LVDS_PWM [18]
2
+3V
CRT_R [18] CRT_G [18] CRT_B [18]
LAYOUT NOTE: PLACE THESE 3 RESISTORS CLOSE TO PIN
<20110110> DPL_REFSSCCLK is used to drive internal
DREFSSCLK [2] DREFSSCLK# [2]
DREFCLK [2] DREFCLK# [2]
registers and logics of the display interface and therefore needs to be present at all times.
<20100818_Jerry> If you implement XDP, you need the PU 2.2K
<20110610> Remove PU resistor for Intel update. <20110630> Stuff R38/ R39 PU resistor. Intel will fixed EDID issue by VGA driver and vbios
+3V
+3V
R39 2.2K/J_4R39 2.2K/J_4 R38 2.2K/J_4R38 2.2K/J_4
<EMI>
*220P/50V_4
*220P/50V_4
R58 2.2K/J_4R58 2.2K/J_4 R56 2.2K/J_4R56 2.2K/J_4
<EMI>
C58
C58
*220P/50V_4
*220P/50V_4
C50
C50
LCD_CLK LCD_DATA
*220P/50V_4
*220P/50V_4
CRT_DDC_SDA CRT_DDC_SCL
*220P/50V_4
*220P/50V_4
1
05
C51
C51
C65
C65
LCD Panel Power (LDS)
+1.5V
R409
R409 0/J_4
0/J_4
27MHz/+-20PPM_20PF
27MHz/+-20PPM_20PF
C334
C334
DMI_TXP0[10] DMI_TXN0[10] DMI_TXP1[10] DMI_TXN1[10] DMI_TXP2[10] DMI_TXN2[10] DMI_TXP3[10] DMI_TXN3[10]
CLK_PCIE_DMIP[2] CLK_PCIE_DMIN[2]
R450 *0/short_4R450 *0/short_4
Y3
Y3
R385 1M/J_4R385 1M/J_4
33P/50V_4
33P/50V_4
C354
C354
1U/10V_4
1U/10V_4
R410
R410 0/J_4
0/J_4
2nd source: BG627000289 (ZYG)
C335
C335
+3V
C329 .1U/10V_4C329 .1U/10V_4
U20
R360
R360 100K_4
100K_4
U20
2 1
3 5
R355 *0/J_4R355 *0/J_4
TC7SH08FU
TC7SH08FU
4
INT_LVDS_DIGON [18]
DMI_REF1.5V
For HDMI deep color mode support
ECPWROK
INT_LVDS_DIGON_Q
B B
LCD Panel Backlight (LDS)
(HDM)
+3V
C48 .1U/10V_4C48 .1U/10V_4
U2
R53
R53 100K_4
100K_4
5
U2
2 1
3 5
R51 *0/J_4R51 *0/J_4
TC7SH08FU
TC7SH08FU
4
INT_LVDS_BLON [18]
ECPWROK[8,13,16,27]
A A
ECPWROK LBKLT_EN
<20100727_Sam> Customer must to use 27MHz due to accuracy concerns(<1000ppm) from Intel silicon perspective.
LAYOUT NOTE: PLACE CLOSE TO PIN
DREFCLK_R1 DREFCLK#_R1
33P/50V_4
33P/50V_4
4
U24A
U24A
L3
DMI_RXP0
L2
DMI_RXN0
M3
DMI_RXP1
M2
DMI_RXN1
N2
DMI_RXP2
N1
DMI_RXN2
P2
DMI_RXP3
P3
DMI_RXN3
N9
DMI_REFCLKP
N8
DMI_REFCLKN
T2
DMI_REF1P5
CDV_22MM_REV1P10
CDV_22MM_REV1P10
CEDARVIEW
CEDARVIEW
REV = 1.10
REV = 1.10
DMI
DMI
1 OF 6
1 OF 6
<20101109> Add C354 to follow CRB v0.7
THERMAL SENSOR (THM)
<20110414> Unstuff Thermal Sensor and related circuit.
THERM_ALERT#[6,13,27]
3
K6
DMI_TXP0
K5
DMI_TXN0
L5
DMI_TXP1
L6
DMI_TXN1
L9
DMI_TXP2
L8
DMI_TXN2
N5
DMI_TXP3
N6
DMI_TXN3
R8
RSVD_TP_R8
R7
RSVD_TP_R7
T1
DMI_RCOMP
ALERT# Pull Up Value
2K ohm
7.5K ohm
10.5K ohm 14K ohm
18.7K ohm
DMI_REF1.5V_R
+3V
R115
R115
*
*2K/F_4
*2K/F_4
R111 *0/J_4R111 *0/J_4
*
Alert temperature point
75 degree
90 degree 100 degree 105 degree 110 degree
DMI_RXP0 [10] DMI_RXN0 [10] DMI_RXP1 [10] DMI_RXN1 [10] DMI_RXP2 [10] DMI_RXN2 [10] DMI_RXP3 [10] DMI_RXN3 [10]
7.5K/F_4
7.5K/F_4
R445
R445
THERMAL_SCL THERMAL_SDA
THERM_ALERT#_1
DMI_REF1.5V
<20101109> Add DMI_REF1.5V to follow CRB v0.7
U5
*
1
SCL
2
GND
3
ALERT#
*NCT7717UU5*NCT7717U
2
*
R119 *0/J_4R119 *0/J_4
C155
C155 *0.1U/16V_4
*0.1U/16V_4
*
**
+3V
C156
C156 *4.7U/6.3V_6
*4.7U/6.3V_6
C148
C148
*0.1U/16V_4
*0.1U/16V_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Cedarview DMI/Display
Cedarview DMI/Display
Cedarview DMI/Display
Wednesday, November 02, 2011
Wednesday, November 02, 2011
Wednesday, November 02, 2011
5
SDA
4
VDD
2ND_MBCLK [27]
2ND_MBDATA [27]
C154
C154
*0.1U/16V_4
*0.1U/16V_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
ZE7
ZE7
ZE7
1
1B
1B
1B
405
405
405
R114 *0/J_4R114 *0/J_4
<20110414> Pull up at EC side
5
Cedar View (CPU)
R74 2.2K/J_4R74 2.2K/J_4 R71 2.2K/J_4R71 2.2K/J_4
D D
<20100811_Jerry>can be NC but please reserve 2.2K pull low as CRB. can be removed later depends on CRB validation status.
<20101019>Stuff R74 R71 for using 0xFFFE_0000 as Punit microbase address
HV_GPIO_RCOMP MV_GPIO_RCOMP
R72
R72
R69
R69
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
C C
XDP_TCLK
T45T45
XDP_TDI
T46T46
XDP_TDO
T47T47
XDP_TMS
T48T48
XDP_TRST#
T49T49
+1.05V
XDP_TDI
R449 51/J_4R449 51/J_4
XDP_TDO
R459 51/J_4R459 51/J_4
XDP_TMS
R470 51/J_4R470 51/J_4
XDP_TCLK
R446 51/J_4R446 51/J_4
XDP_TRST#
R448 51/J_4R448 51/J_4
L26
RSVD_L26
L27
RSVD_L27
K28
RSVD_K28
K25
RSVD_K25
J28
RSVD_J28
K26
RSVD_K26
K27
RSVD_K27
H27
RSVD_H27
K30
RSVD_K30
L29
RSVD_L29
L30
RSVD_L30
K29
RSVD_K29
J31
RSVD_J31
H30
RSVD_H30
K24
HV_GPIO_RCOMP
K23
MV_GPIO_RCOMP
C25
TCLK
C24
TDI
B25
TDO
D24
TMS
B24
TRST#
R5
RSVD_R5
R6
RSVD_R6
W25
RSVD_W25
W26
RSVD_W26
N24
RSVD_N24
N25
RSVD_N25
U24D
U24D
4
3
2
1
06
CEDARVIEW
CEDARVIEW
REV = 1.10
REV = 1.10
B18
SMI#
C22
NMI/LINT1
RSVD_C18
ICH
ICH
CPU
CPU
STPCLK#
DPRSTP#
DPLSLP# CPUSLP#
INIT#
INTR/LINT0
THERMTRIP#
RSVD_L11
PBE#
PROCHOT# PWRGOOD
RESET#
DBR#
PRDY# PREQ#
HPLL_REFCLK_P
HPLL_REFCLK
RSVD_E19 RSVD_F19
SVID_ALERT#
SVID_CLK
SVID_DATA
RSVD_K21
RSVD_L22 RSVD_L24
R386 *0/short_4R386 *0/short_4
C18 D22
C21 B21 B22
A23 D20
H_THRMTRIP#
B20 L11
H_FERR#_R
C20
H_PROCHOT_R#
A19
H_PWRGD
D23
PLTRST#
G30 E30
XDP_DBRESET_N_CDV
H_BPM4_PRDY#
H29
H_BPM5_PREQ#
G29
CLK_MCH_BCLK
J19
CLK_MCH_BCLK#
K19 E19
F19
B16 D18 C16
K21 L22 L24
R400 *0/short_4R400 *0/short_4
R399
R399 75/J_4
75/J_4
H_SMI# [11] H_NMI [11] H_A20M# [11] H_STPCLK# [11]
ICH_DPRSTP# [13] H_DPSLP# [13] CPUSLP# [11]
H_INIT# [11] H_INTR [11]
H_PWRGD [13,16] PLTRST# [13,16,22,25,26,27]
R33 1K/J_4R33 1K/J_4
T43T43 T44T44
CLK_MCH_BCLK [2] CLK_MCH_BCLK# [2]
VR_SVID_ALERT# [31] VR_SVID_CLK [31]
H_FERR# [11]
+3V
R416
R416 110/F_4
110/F_4
+1.05V
<20100811_Jerry>please use 100+/-5% as in PDG.
R381
R381 100/J_4
100/J_4
R377 *0/short_4R377 *0/short_4
Host CLK 100/133 MHz
+1.05V
VR_SVID_DATA [31]
H_PROCHOT# [31]
H_BPM4_PRDY# H_BPM5_PREQ#
.1U/10V_4
.1U/10V_4
R442 *51/J_4R442 *51/J_4
R443 51/J_4R443 51/J_4
C268
C268
+1.8V
CDV_22MM_REV1P10
CDV_22MM_REV1P10
B B
125 Degree Protection(CPU)
+1.05V
3
Q2 2N7002KQ22N7002K
2
1
2
Shutdown System Power Immediately
Q1
Q1
1 3
METR3904-G
METR3904-G
SYS_SHDN# [30,35]
To System Power
PM_THRMTRIP# [11]
To Tiger Point
H_THRMTRIP#
5
IMVP_PWRGD
R16 *0/short_4R16 *0/short_4
R17
R17 1K/J_4
1K/J_4
IMVP_PWRGD[27,31]
From CPU
A A
4 OF 6
4 OF 6
CPU FAN CTRL(THM)
+5V
+3V
R512
R512
R505 *0/short_6R505 *0/short_6
10K/J_4
10K/J_4
FANSIG [27]
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Wednesday, November 02, 2011
Date: Sheet of
Wednesday, November 02, 2011
Date: Sheet of
2
Wednesday, November 02, 2011
C365 0.1U/16V_4C365 0.1U/16V_4
CN18
+5V_FANVCC
FANSIG FAN_PWM_CNCPUFAN#
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
Cedarview Miscellaneous
Cedarview Miscellaneous
Cedarview Miscellaneous
CN18
345 2 1
FAN CONN
FAN CONN
1
6
ZE7
ZE7
ZE7
1B
1B
1B
406
406
406
THERM_ALERT#[5,13,27]
CPUFAN#[27]
EC PWM SIGNAL
R514 *0/J_4R514 *0/J_4
+3V
1 3
Q43 METR3904-GQ43 METR3904-G
2
R509
R509 10K/J_4
10K/J_4
+5V
R507
R507 10K/J_4
10K/J_4
For EMI
FAN_PWM_CN
4
3
FANSIG
C368
C368 *220P/50V_6
*220P/50V_6
C372
C372 *220P/50V_6
*220P/50V_6
1
Cedar View (CPU)
LAYOUT NOTE: place close to VCCADDR pin
C352
C352 *22U/6.3V_8
C129
C129
C149
C149
2.2U/6.3V_6
2.2U/6.3V_6
R77 *0/short_6R77 *0/short_6
+1.8V
*22U/6.3V_8
C128
C128
C130
C130
1U/10V_4
1U/10V_4
1U/10V_4
1U/10V_4
C153
C153
2.2U/6.3V_6
2.2U/6.3V_6
2.2U/6.3V_6
2.2U/6.3V_6
+1.05V
C83
C83
1U/10V_4
1U/10V_4
+3.3V_PRIME
R384 0.2A/600ohm_6R384 0.2A/600ohm_6
R47 *0/short_6R47 *0/short_6
R94 *0/short_6R94 *0/ short_6
A A
<20101126_Colt> Please follow PDG to placehold the 0805 capacitor
VCCDDRAON_1.5[8]
R134 *0/short_8R134 *0/short_8
+1.5VSUS
*1U/10V_4
*1U/10V_4
For Deep Standby
B B
R31 *0/short_6R 31 *0/short_6
+1.5V
R46 *0/short_6R 46 *0/short_6
+1.8V
<20100830> Add Farrite bead for VCCDAC low pass filter
<20101125_Colt> Please follow PDG, we will doing BOM stuff changing in next version CRB
C C
+1.05V
C82 *0.1U/10V_4C82 *0.1U/10V_4
C93 1U/10V_4C93 1U/10V_4
+3.3V_PRIME
V_1.05_CORE_RSENSE VCCDMPL_1.05
C120
C120 1U/10V_4
1U/10V_4
C92 *1U/10V_4C92 *1U/10V_4 C116 1U/10V_4C 116 1U/10V_4
VCCDDRAON_1.5
C152
C152
C146
C146
2.2U/6.3V_6
2.2U/6.3V_6
R419 *0/short_6R419 *0/short_6
R55 *0/short_6R55 *0/short_6
C336 22U/6.3V_8C336 22U/6.3V_8 C337 *47U/6.3V_8C337 *47U/6.3V_8
C54 2.2U/6.3V_6C54 2.2U/6.3V_6
*2.2U/6.3V_4
*2.2U/6.3V_4
2
C141
C141 *1U/10V_4
*1U/10V_4
R54 *0/J_6R54 *0/J_6
C59 2.2U/6.3V_6C59 2.2U/6.3V_6
C91 1U/10V_4C91 1U/10V_4
C139
C139
V_1.05_CORE_RSENSE
V_1.05_CORE_EAST
V_1.05_CORE_RSENSE V_1.05_VCCDDR
V_1.05_VCCDDR
VCCCKDDR_VSM
VCCADP_1.05
C56 1U/10V_4C56 1U/10V_4
VCCADP0_1.5 VCCADP1_1.5
V_1.05_CORE_EAST VCCAGPIO_1.5 VCCAGPIO_1.8
VCCAGPIO_3.3
VCCADAC_1.8 VCCALVDS_1.8
VCCDLVDS_1.8
V_1.05_CORE_EAST
VCCSFRMPL_1.5
VCCPLLCPU0_1.05 VCCPLLCPU1_1.05
VCCAHPLL_1.05
AA14 AA16
AH14 AH19 AK23
AG31
W16 W18
N30 N31
V4
W8 W9
W11 W13
AJ6
AK6
AK5 AL11 AL16 AL21
B5 C6 D6
K17
L18 L19
L16
N18
D30
D31
B13
H5
J1
L21
B29
A30 AA18
AA11
B27
C29
B30
B26
U24E
U24E
VCCADDR_1 VCCADDR_2 VCCADDR_3 VCCADDR_4
VCCRAMXXX_1 VCCRAMXXX_2 VCCRAMXXX_3
VCCACKDDR_1 VCCACKDDR_2
VCCADLLDDR_1 VCCADLLDDR_2
VCCCKDDR_1 VCCCKDDR_2
V_SM_1 V_SM_2 V_SM_3 V_SM_4 V_SM_5 V_SM_6 V_SM_7 V_SM_8
VCCADP_1 VCCADP_2 VCCADP_3
VCCADP0_SFR VCCADP1_SFR
VCCAGPIO_LV VCCAGPIO_REF VCCAGPIO_DIO
VCCAGPIO_1 VCCAGPIO_2
VCCADAC VCCALVDS
VCCDLVDS
VCCDIO VCCAZILAON_1
VCCAZILAON_2 VCCSFRMPL
VCCDMPL VCCPLLCPU0
VCCPLLCPU1_1 VCCPLLCPU1_2
VCCAHPLL
3
CEDARVIEW
CEDARVIEW
REV = 1.10
REV = 1.10
DDR
DDR
CPU
CPU
POWER
POWER
DMI
DMI
PLL
PLL
4
VCC_CPU_01 VCC_CPU_02 VCC_CPU_03 VCC_CPU_04 VCC_CPU_05 VCC_CPU_06 VCC_CPU_07 VCC_CPU_08 VCC_CPU_09 VCC_CPU_10 VCC_CPU_11 VCC_CPU_12 VCC_CPU_13 VCC_CPU_14 VCC_CPU_15 VCC_CPU_16 VCC_CPU_17 VCC_CPU_18 VCC_CPU_19 VCC_CPU_20 VCC_CPU_21 VCC_CPU_22 VCC_CPU_23 VCC_CPU_24 VCC_CPU_25 VCC_CPU_26 VCC_CPU_27 VCC_CPU_28 VCC_CPU_29
VCC_GFX_01 VCC_GFX_02 VCC_GFX_03 VCC_GFX_04 VCC_GFX_05 VCC_GFX_06 VCC_GFX_07 VCC_GFX_08 VCC_GFX_09 VCC_GFX_10 VCC_GFX_11
VCCADMI_1 VCCADMI_2 VCCADMI_3
VCCADMI_PLLSFR
VCCFHV_1 VCCFHV_2
VCCFHV_3
VCC_CPUSENSE VSS_CPUSENSE
VCC_GFXSENSE
VSS_GFXSENSE
VCCTHRM_1 VCCTHRM_2
1.1V (0.75V~1.18V)
5.95A
+VCC_CORE
P18
1U/10V_4
1U/10V_4
P19 P21 P28 P29 P30 R22 R23 R24 R25 R26 R27 T19 T21 T29 T30 T31 U22 U23 U24 U25 U26 U27 V18 V19 V21 V28 V29 V30
N11 N13 P11 P13 R10 R9 T11 T13 U10 V11 V13
B4 C5 A4 K4
V16 T16
V14 M28
M30 U8
U7 N16
K2
C100
C100
C126
C126
*1U/10V_4
*1U/10V_4
1U/10V_4
1U/10V_4
1.05V (0.76V~1.05V)
1.98A
VCCGFX
C95
C95
C98
C98
1U/10V_4
1U/10V_4
1U/10V_4
1U/10V_4
C60 1U/10V_4C60 1U/10V_4
VCCADMI_1.05
C88 1U/10V_4C88 1U/10V_4
VCCADMI_1.5 V_1.05_CORE_RSENSEVCCAZILAON_3.3
CPUVCC_SENSE [31] CPUVSS_SENSE [31]
GTVCC_SENSE [31] GTVSS_SENSE [31]
V_1.8_RSENSE
C350
C350 *1U/10V_4
*1U/10V_4
5
22U/6.3V_8
22U/6.3V_8
*1U/10V_4
*1U/10V_4
C125
C125
C118
C118
C105
C105
C101
C101
C106
C106
*1U/10V_4
*1U/10V_4
22U/6.3V_8
22U/6.3V_8
LAYOUT NOTE: PLACE ONE 1U CAP ON BOT LAYER
LAYOUT NOTE: PLACE TWO CAPS ON BOT LAYER
C117
C117
C94
C94
1U/10V_4
1U/10V_4
1U/10V_4
1U/10V_4
R437 *0/short_6R437 *0/short_6
+1.8V
22U/6.3V_8
22U/6.3V_8
C112
C112
C103
C103
22U/6.3V_8
22U/6.3V_8
C115
C115 22U/6.3V_8
22U/6.3V_8
R423 *0/short_6R423 *0/short_6
R456 *0/short_6R456 *0/short_6
+1.05V
+1.5V
VCCPLLCPU0_1.05 VCCPLLCPU1_1.05
R40 *0/J_6R40 *0/J_6
6
Cedar View PLL Power
Default stuff 1.5VPLL, Intel verify whether
1.05VPLL is ok or not
VCCSFRMPL_1.5
VCCADP0_1.5
VCCADP1_1.5
7
C134
C134 1U/10V_4
1U/10V_4
C52
C52 1U/10V_4
1U/10V_4
C53
C53 1U/10V_4
1U/10V_4
R112 *1.5VPLL@0/short_6R112 *1.5VPLL@0/short_6
L18
L18 *1.05VPLL@10uH/100mA_8
*1.05VPLL@10uH/100mA_8 C142
C142 *10U/6.3V_8
*10U/6.3V_8
R29 *1.5VPLL@0/short_6R29 *1.5VPLL@0/short_6
L3
L3 *1.05VPLL@10uH/100mA_8
*1.05VPLL@10uH/100mA_8 C28
C28 *10U/6.3V_8
*10U/6.3V_8
R36 *1.5VPLL@0/short_6R36 *1.5VPLL@0/short_6
L4
L4 *1.05VPLL@10uH/100mA_8
*1.05VPLL@10uH/100mA_8 C29
C29 *10U/6.3V_8
*10U/6.3V_8
8
07
+1.5V
+1.05V
+1.5V
+1.05V
+1.5V
+1.05V
Cedar View LVDS Power
BOM structure
w/LVDS: stuff R436/ C345/ L38/ C75 w/EDP: unstuff R436/ C75 change L38/ C345 to 0ohm
VCCDLVDS_1.8
VCCALVDS_1.8
C75
C75
LVDS@4.7u/6.3V_6
LVDS@4.7u/6.3V_6
L38BOM@0.1uH/300mA_6 L38BOM@0.1uH/300mA_6
C345
C345
BOM@1U/10V_4
BOM@1U/10V_4
R436 LVDS@0/J_6R436 LVDS@0/J_6
+1.8V
LAYOUT NOTE: OVERLAP RESISTOR AND INDUCTOR
2nd source: CV01001MN32
VCCPLLCPU0_1.05
C31
C31
C40
4.7u/6.3V_6
5 OF 6
CDV_22MM_REV1P10
CDV_22MM_REV1P10
D D
1
2
3
5 OF 6
<20101125_Colt> Please follow PDG, we will doing BOM stuff changing in next version CRB
4
5
4.7u/6.3V_6
VCCPLLCPU1_1.05
4.7u/6.3V_6
4.7u/6.3V_6
VCCAHPLL_1.05
4.7u/6.3V_6
4.7u/6.3V_6
C40
1U/10V_4
1U/10V_4
C45
C45
C46
C46
1U/10V_4
1U/10V_4
C32
C32
C49
C49
1U/10V_4
1U/10V_4
6
+1.05V
L610uH/100mA_8 L610uH/100mA_8
+1.05V
L1110uH/100mA_8 L1110uH/100mA_8
+1.05V
L1010uH/100mA_8 L1010uH/100mA_8
VCCCKDDR_VSM
C359
C359
C362
10U/6.3V_8
10U/6.3V_8
V_1.05_VCCDDR
V_1.05_CORE_RSENSE
C362
<2010/9/27>Reserve 0805 footprint for farrite bead CV01001MN16 due to co-layout issue.
R89 *0/short_6R89 *0/short_6
R440 *0/short_6R440 *0/short_6
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Wednesday, November 02, 2011
Date: Sheet of
Wednesday, November 02, 2011
Date: Sheet of
7
Wednesday, November 02, 2011
1U/6.3V_4
1U/6.3V_4
<20101125_Colt> Please follow PDG, we will doing BOM stuff changing in next version CRB
R489 *0/short_8R489 *0/short_8
+1.05V
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
CedarView Power
CedarView Power
CedarView Power
+1.5VSUS
ZE7
ZE7
ZE7
8
407
407
407
5
Cedar View (CPU)
D D
<Layout note> PLACE RESISTORS AND CAP CLOSE TO CPU DDR_VREF PIN
VCCDDRAON_1.5[7]
+SMDDR_VREF
C C
<20100810_Jerry> Please refer to Cedar Trail CPET HW section(#454349), it is to implement Deep Standby. And please waiting the whitepaper for implementation detail.
<20100817_Jerry>DELAY_VR_PWRGOOD on CDV should be connected to the XDP_PWRGOOD because the SV folks expressed a preference on using PWROK over PWRGOOD for CDV. This has changed from PNV to CDV.
B B
R482 1K/F_4R482 1K/F_4
R492 *0/J_4R492 *0/J_4
<20110520>Change 12.1K to 121ohm to follow CRBv1.5
R483 *0/short_4R483 *0/short_4
R493
R493 1K/F_4
1K/F_4
ECPWROK[5,13,16,27]
<20110520>Change 10K to 100ohm to follow CRBv1.5
<20100811_Jerry> R485 please follow CRB schematic. (274ohm)
C360
C360
0.1U/16V_4
0.1U/16V_4
R99 121/F_4R99 121/F_4
DRAM Reset (CPU)
4
M_A_A[15:0][4]
M_A_WE#[4] M_A_CAS#[4] M_A_RAS#[4]
M_A_BS0[4] M_A_BS1[4] M_A_BS2[4]
M_CS#2[4] M_CS#3[4]
M_CKE2[4] M_CKE3[4]
M_ODT2[4] M_ODT3[4]
M_CLK2[4] M_CLK2#[4] M_CLK3[4] M_CLK3#[4]
*
CLK_DDR3_REFCLK[2] CLK_DDR3_REFCLK#[2]
T53T53
R98
R98 100/F_4
100/F_4
274/F_4
274/F_4
R485
R485
R488
R488
22.6/F_4
22.6/F_4
M_A_DM[7:0][4]
3
DDR3_DRAMRST#_R
DDRAM_PWROK
DELAY_VR_PWRGD_CDV
C361
C361
*0.01U/25V_4
*0.01U/25V_4
M_A_WE# M_A_CAS# M_A_RAS#
M_A_BS0 M_A_BS1 M_A_BS2
M_CS#2 M_CS#3
M_CKE2 M_CKE3
M_ODT2 M_ODT3
M_CLK2 M_CLK2# M_CLK3 M_CLK3#
DDR_VREF
M_ODTPU M_CMDPU M_DQPU
R484
R484
33.2/F_4
33.2/F_4
M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15
U24B
U24B
AK14
DDR3_MA0
AK16
DDR3_MA1
AJ14
DDR3_MA2
AJ16
DDR3_MA3
AK18
DDR3_MA4
AH18
DDR3_MA5
AJ18
DDR3_MA6
AK20
DDR3_MA7
AJ20
DDR3_MA8
AH20
DDR3_MA9
AJ12
DDR3_MA10
AK21
DDR3_MA11
AJ21
DDR3_MA12
AJ8
DDR3_MA13
AH22
DDR3_MA14
AJ22
DDR3_MA15
AH10
DDR3_W E#
AJ10
DDR3_CAS#
AJ11
DDR3_RAS#
AK12
DDR3_BS0
AH13
DDR3_BS1
AK22
DDR3_BS2
AH12
DDR3_CS#0
AH8
DDR3_CS#1
AK11
DDR3_CS#2
AK8
DDR3_CS#3
AH23
DDR3_CKE0
AJ24
DDR3_CKE1
AK24
DDR3_CKE2
AH24
DDR3_CKE3
AK10
DDR3_ODT0
AK7
DDR3_ODT1
AL9
DDR3_ODT2
AJ7
DDR3_ODT3
AG15
DDR3_CK0
AF15
DDR3_CK#0
AF17
DDR3_CK1
AG17
DDR3_CK#1
AD17
DDR3_CK2
AC17
DDR3_CK#2
AC15
DDR3_CK3
AD15
DDR3_CK#3
AK25
DDR3_DRAMRST#
AJ27
DDR3_VREF
AL28
DDR3_VREF_NCTF
AC19
DDR3_REFP
AB19
DDR3_REFN
AA5
DDR3_DRAM_PWROK
W7
DDR3_VCCA_PWROK
AJ26
DDR3_ODTPU
AJ25
DDR3_CMDPU
AK27
DDR3_DQPU
AB11
RSVD_TP_AB11
AB13
RSVD_TP_AB13
AF19
RSVD_TP_AF19
AG19
RSVD_TP_AG19
Y28
DDR3_DM0
AB26
DDR3_DM1
AE30
DDR3_DM2
AB21
DDR3_DM3
AG11
DDR3_DM4
AG2
DDR3_DM5
AB8
DDR3_DM6
AA3
DDR3_DM7
CDV_22MM_REV1P10
CDV_22MM_REV1P10
DDR3
DDR3
CEDARVIEW
CEDARVIEW
1.5V
1.5V
REV = 1.10
REV = 1.10
2 OF 6
2 OF 6
2
DDR3_DQ0 DDR3_DQ1 DDR3_DQ2 DDR3_DQ3 DDR3_DQ4 DDR3_DQ5 DDR3_DQ6 DDR3_DQ7 DDR3_DQ8
DDR3_DQ9 DDR3_DQ10 DDR3_DQ11 DDR3_DQ12 DDR3_DQ13 DDR3_DQ14 DDR3_DQ15 DDR3_DQ16 DDR3_DQ17 DDR3_DQ18 DDR3_DQ19 DDR3_DQ20 DDR3_DQ21 DDR3_DQ22 DDR3_DQ23 DDR3_DQ24 DDR3_DQ25 DDR3_DQ26 DDR3_DQ27 DDR3_DQ28 DDR3_DQ29 DDR3_DQ30 DDR3_DQ31 DDR3_DQ32 DDR3_DQ33 DDR3_DQ34 DDR3_DQ35 DDR3_DQ36 DDR3_DQ37 DDR3_DQ38 DDR3_DQ39 DDR3_DQ40 DDR3_DQ41 DDR3_DQ42 DDR3_DQ43 DDR3_DQ44 DDR3_DQ45 DDR3_DQ46 DDR3_DQ47 DDR3_DQ48 DDR3_DQ49 DDR3_DQ50 DDR3_DQ51 DDR3_DQ52 DDR3_DQ53 DDR3_DQ54 DDR3_DQ55 DDR3_DQ56 DDR3_DQ57 DDR3_DQ58 DDR3_DQ59 DDR3_DQ60 DDR3_DQ61 DDR3_DQ62 DDR3_DQ63
DDR3_DQS0 DDR3_DQS1 DDR3_DQS2 DDR3_DQS3 DDR3_DQS4 DDR3_DQS5 DDR3_DQS6 DDR3_DQS7
DDR3_DQS#0 DDR3_DQS#1 DDR3_DQS#2 DDR3_DQS#3 DDR3_DQS#4 DDR3_DQS#5 DDR3_DQS#6 DDR3_DQS#7
Y30 Y29 AC30 AC31 W31 W28 AB28 AB30 AA24 AA22 AE27 AE26 AB27 AA25 AD25 AD27 AD29 AE29 AJ30 AK29 AD28 AD30 AG30 AJ29 AE24 AG24 AD22 AC21 AG27 AG25 AG21 AE21 AD13 AD11 AG8 AG7 AG13 AE13 AD10 AF8 AH2 AG3 AD2 AD3 AH4 AK3 AE2 AD4 AD7 AD6 AA6 AB5 AE8 AE5 AB9 AA8 AB2 AB4 W4 V3 AC2 AB3 Y2 W1
AA30 AB24 AF30 AE22 AG10 AF4 AB6 Y3
AA31 AB25 AF29 AF22 AF10 AF3 AB7 AA2
M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63
M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7
M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7
1
M_A_DQ[63:0] [4]
M_A_DQS[7:0] [4]
M_A_DQS#[7:0] [4]
08
<20110520>Need to confirm with Intel if we need to add series 100ohm resistor
A A
DDR3_DRAMRST#[4]
R537 *0/short_4R537 *0/short_4
C159
C159
0.1U/16V_4
0.1U/16V_4
<20110727> Add C159 to suppress glitch
5
+1.5VSUS
DDR3_DRAMRST#_NS
<20110607>Keep original design first for DRAMRST# <20110707_Nick> Please stuff 100K pull down
<20110607>Keep original design first for DRAMRST# <20110707_Nick> Please un-stuff 1K pull up
R538
R538 *1K/F_4
*1K/F_4
R539 *0/short_4R539 *0/short_4
DDR3_DRAMRST#_R
R474
R474 100K/J_4
100K/J_4
4
<20110727>Connect DDRAM_PWROK between CDV and RT8207L to meet JEDEC timing spec
+1.5VSUS
VCCDDRAON_1.5
DDRAM_PWROK[27,32]
3
R100
R100 10K/J_4
10K/J_4
DDRAM_PWROK
R97
R97
C388
C388
*0/J_4
*0/J_4
*1U/10V_6
*1U/10V_6
<20110727> Reserve C388 for RC delay
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Wednesday, November 02, 2011
Date: Sheet of
Wednesday, November 02, 2011
Date: Sheet of
2
Wednesday, November 02, 2011
PROJECT :
CedarView DDR
CedarView DDR
CedarView DDR
ZE7
ZE7
ZE7
1B
1B
1B
408
408
1
408
1
Cedar View (CPU)
U24F
U24F
CEDARVIEW
CEDARVIEW
A11
VSS
A16
VSS
A21
VSS
REV = 1.10
REV = 1.10
A25
VSS
AA1
VSS
AA10
VSS
AA13
VSS
AA19
VSS
AA21
VSS
AA23
VSS
AA26
VSS
AA27
VSS
AA29
VSS
AA7
VSS
AA9
VSS
AB15
VSS
AB17
VSS
AB23
VSS
AB29
VSS
AC1
VSS
AC10
VSS
AC11
VSS
AC13
VSS
GND
AC22 AC28
AC4 AD19 AD21 AD24 AD26
AD5
AD8
AE1 AE10 AE11 AE15 AE17 AE19
AE3 AE31 AF11 AF13 AF21 AF24 AF28
AF7
AG22
AG5 AH26 AH28
AH6
AH9
AJ2 AJ3
AK13
A A
AK19 AK28
AL13 AL19 AL23 AL25
G11
G13
G15
G17
G19
G21
G31
AK9
AL7 B10 B14 B19 B23 C12 C26 C30
C7 D19 D28
D8
D9
E2
E5
E7 F24
F4
G1
G8 H13
GND
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSSA_CRTDAC VSS VSS VSS VSS VSS
6 OF 6
6 OF 6
CDV_22MM_REV1P10
CDV_22MM_REV1P10
VSS_CDVDET
H19
VSS
H26
VSS
H28
VSS
H6
VSS
J10
VSS
J2
VSS
J21
VSS
J30
VSS
K11
VSS
K15
VSS
K3
VSS
K7
VSS
K8
VSS
K9
VSS
L1
VSS
L10
VSS
L13
VSS
L23
VSS
L25
VSS
L31
VSS
L7
VSS
M29
VSS
M4
VSS
N10
VSS
N14
VSS
N19
VSS
N21
VSS
N22
VSS
N23
VSS
N26
VSS
N27
VSS
N28
VSS
N4
VSS
N7
VSS
P14
VSS
P16
VSS
P4
VSS
T14
VSS
T18
VSS
T3
VSS
U5
VSS
U6
VSS
U9
VSS
V2
VSS
W10
VSS
W14
VSS
W19
VSS
W2
VSS
W21
VSS
W22
VSS
W23
VSS
W24
VSS
W27
VSS
W30
VSS
W5
VSS
W6
VSS
Y4
VSS
A27
VSS
A29
VSS
A3
VSS
AH1
VSS
AJ1
VSS
AJ31
VSS
AK1
VSS
AK2
VSS
AK30
VSS
AK31
VSS
AL2
VSS
AL29
VSS
AL3
VSS
AL30
VSS
AL5
VSS
B2
VSS
B3
VSS
B31
VSS
C1
VSS
C2
VSS
C31
VSS
E1
VSS
L14 D13
09
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Wednesday, November 02, 2011
Date: Sheet of
Wednesday, November 02, 2011
Date: Sheet of
1
Wednesday, November 02, 2011
PROJECT :
CedarView GND/ Deep Standby
CedarView GND/ Deep Standby
CedarView GND/ Deep Standby
ZE7
ZE7
ZE7
1B
1B
1B
409
409
409
1
Tiger Point (CLG)
TGP
U22B
U22B
DMI_RXN0[5]
DMI_RXP0[5] DMI_TXN0[5] DMI_TXP0[5]
DMI_RXN1[5]
DMI_RXP1[5] DMI_TXN1[5] DMI_TXP1[5]
DMI_RXN2[5]
DMI_RXP2[5]
<20110222> ES2 CPU DMI will change from x4 to x2
LAN
WLAN
Card Reader
Media Processor
A A
DMI_TXN2[5] DMI_TXP2[5]
DMI_RXN3[5]
DMI_RXP3[5] DMI_TXN3[5] DMI_TXP3[5]
PCIE_RXN0[22]
PCIE_RXP0[22] PCIE_TXN0[22] PCIE_TXP0[22]
PCIE_RXN1[25]
PCIE_RXP1[25] PCIE_TXN1[25] PCIE_TXP1[25]
PCIE_RXN2[26]
PCIE_RXP2[26] PCIE_TXN2[26] PCIE_TXP2[26]
PCIE_RXN3[25]
PCIE_RXP3[25] PCIE_TXN3[25] PCIE_TXP3[25]
C96 .1U/10V_4C96 .1U/10V_4 C90 .1U/10V_4C90 .1U/10V_4
C113 .1U/10V_4C113 .1U/10V_4 C104 .1U/10V_4C104 .1U/10V_4 R81 *0/J_4R81 *0/J_4 R80 *0/J_4R80 *0/J_4 C110 *.1U/10V_4C110 *.1U/10V_4 C122 *.1U/10V_4C122 *.1U/10V_4 R88 *0/J_4R88 *0/J_4 R86 *0/J_4R86 *0/J_4 C124 *.1U/10V_4C124 *.1U/10V_4 C132 *.1U/10V_4C132 *.1U/10V_4
C63 .1U/10V_4C63 .1U/10V_4 C71 .1U/10V_4C71 .1U/10V_4
C343 .1U/10V_4C343 .1U/10V_4 C344 .1U/10V_4C344 .1U/10V_4
C87 .1U/10V_4C87 .1U/10V_4 C80 .1U/10V_4C80 .1U/10V_4
C347 *.1U/10V_4C347 *.1U/10V_4 C346 *.1U/10V_4C346 *.1U/10V_4
DMI_TXN0_C DMI_TXP0_C
DMI_TXN1_C DMI_TXP1_C DMI_RXN2_R DMI_RXP2_R DMI_TXN2_C DMI_TXP2_C DMI_RXN3_R DMI_RXP3_R DMI_TXN3_C DMI_TXP3_C
PCIE_TXN0_C PCIE_TXP0_C
PCIE_TXN1_C PCIE_TXP1_C
PCIE_TXN2_C PCIE_TXP2_C
PCIE_TXN3_C PCIE_TXP3_C
R23 R24 P21 P20 T21 T20 T24 T25 T19 T18
U23
U24 V21 V20 V24 V23
K21 K22
J23
J24 M18 M19
K24 K25 L23 L24 L22
M21
P17
P18 N25 N24
DMI0RXN DMI0RXP DMI0TXN DMI0TXP DMI1RXN DMI1RXP DMI1TXN DMI1TXP DMI2RXN DMI2RXP DMI2TXN DMI2TXP DMI3RXN DMI3RXP DMI3TXN DMI3TXP
PERN1 PERP1 PETN1 PETP1 PERN2 PERP2 PETN2 PETP2 PERN3 PERP3 PETN3 PETP3 PERN4 PERP4 PETN4 PETP4
<20110630> No support PCI-e in 3G card
<Layout note> Close to pin within 500mil
R425 24.9/F_4R425 24.9/F_4
+1.5V
CLK_PCIE_ICH#[2] CLK_PCIE_ICH[2]
DMI_COMP
H24
J22
W23 W24
DMI_ZCOMP DMI_IRCOMP
DMI_CLKN DMI_CLKP
Tiger Point
Tiger Point
TGP
H7
USBP0N
H6
USBP0P
H3
USBP1N
H2
USBP1P
J2
USBP2N
J3
DMI
DMI
USB
USB
PCI-E
PCI-E
USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P
OC0# OC1# OC2# OC3#
OC4# OC5#/GPIO29 OC6#/GPIO30 OC7#/GPIO31
USBRBIAS
USBRBIAS#
CLK48
2
2
K6 K5 K1 K2 L2 L3 M6 M5 N1 N2
USBOC#R_1
D4
USBOC#R_1
C5
USBOC#
D3
USBOC#L_1
D2
USBOC#
E5
USBOC#
E6
USBOC#
C2
USBOC#
C3
G2 G3
CLKUSB_48
F4
USBRBIAS
USBP0- [21] USBP0+ [21] USBP1- [21] USBP1+ [21] USBP2- [18] USBP2+ [18] USBP3- [21] USBP3+ [21] USBP4- [25] USBP4+ [25] USBP5- [25] USBP5+ [25] USBP6- [19] USBP6+ [19] USBP7- [25] USBP7+ [25]
R435 *0/short_4R435 *0/short_4
R427 *0/short_4R427 *0/short_4
<Layout note> Close to pin within 200mil ; keep away from CLK/High speed signals
R438 22.6/F_4R438 22.6/F_4
EMI
R66
R66 *10/F_4
*10/F_4
C81
C81 *10P/50V_4
*10P/50V_4
SYSTEM (Right Down) SYSTEM (Right Up) CCD SYSTEM (Left/ USB Charger) SIM 3G BT WLAN
USBOC#R [21,27]
USBOC#L [21,27]
CLKUSB_48 [2]
USBOC#R_1 USBOC#L_1 USBOC#
CRB ties unused OC pins together with 1k ohm
R433 8.2K/J_4R433 8.2K/J_4 R429 8.2K/J_4R429 8.2K/J_4 R432 1K/F_4R432 1K/F_4
+3V_S5
10
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Wednesday, November 02, 2011
Date: Sheet of
Wednesday, November 02, 2011
Date: Sheet of
1
Wednesday, November 02, 2011
PROJECT :
Tiger Point DMI/PCIE/USB
Tiger Point DMI/PCIE/USB
Tiger Point DMI/PCIE/USB
ZE7
ZE7
ZE7
1B
1B
1B
4010
4010
4010
5
4
3
2
1
Tiger Point (CLG)
D D
TGP
U22C
U22C
R12
RSVD03
AE20
RSVD04
AD17
RSVD05
AC15
RSVD06
AD18
RSVD07
Y12
RSVD08
AA10
RSVD09
AA12
RSVD10
Y10
RSVD11
AD15
RSVD12
W10
RSVD13
V12
RSVD14
AE21
C C
B B
PCH_GPIO36
AE18 AD19
U12
AC17 AB13 AC13 AB15
Y14
AB16 AE24 AE23
AA14
V14
AD16 AB11 AB10 AD23
RSVD15 RSVD16 RSVD17 RSVD18
RSVD19 RSVD20 RSVD21 RSVD22 RSVD23
RSVD24 RSVD25 RSVD26
RSVD27 RSVD28
RSVD29 RSVD30 RSVD31 GPIO36
Tiger Point
Tiger Point
TGP
SATA0RXN SATA0RXP SATA0TXN
SATA0TXP SATA1RXN SATA1RXP SATA1TXN
SATA1TXP
SATA
SATA
AE6 AD6 AC7 AD7 AE8 AD8 AD9 AC9
SATA_RXN0 [24]
SATA_RXP0 [24] SATA_TXN0 [24] SATA_TXP0 [24]
SATA HDD
<20100811_Jerry> Please follow CRB schematic (8.2K)
<20100811_Jerry>CDV doesn't support A20M, please follow CRB to have a 1K pull up at the moment.
<20110516>Reserve 1K PU to +1.05V for C6-state <20100813_Jerry> Update for the IGNNE#, please no
stuff the resister and follow CRB's circuit first.
<Layout note> Close to pin within 500mil
R466 24.9/F_4R466 24.9/F_4
R533 0/J_4R533 0/J_4
R110 60.4/F_4R110 60.4/F_4
+1.05V
+1.05V
R104
R104
60.4/F_4
60.4/F_4
A20M#
IGNNE#
INIT# INTR
FERR#
NMI
RCIN#
SERIRQ
SMI#
3
3
AD4 AC4
AD11 AC11 AD25
GA20
U16
H_A20M#
Y20
CPUSLP#_R
Y21
H_IGNNE#
Y18 AD21
H_INIT#
AC25
H_INTR
AB24
H_FERR#
Y22
H_NMI
T17
KBRST#
AC21
SERIRQ
AA16
H_SMI#
AA21
H_STPCLK#
V18
PM_THRMTRIP#
AA20
SATA_CLKN
SATA_CLKP
SATARBIAS#
SATARBIAS
SATALED#
A20GATE CPUSLP# INIT3_3V#
HOST
HOST
STPCLK#
THERMTRIP#
CLK_PCIE_SATA# [2] CLK_PCIE_SATA [2]
SATARBIAS# SATALED#
R102 10K/J_4R102 10K/J_4
SATALED# [24]
+3V
GA20 [27] H_A20M# [6]
H_INIT# [6] H_INTR [6]
H_NMI [6] KBRST# [27]
SERIRQ [27] H_SMI# [6] H_STPCLK# [6]
<20110607_C-stage> Stuff 1K to follow CRB V1.5
<20100811_Jerry>you can follow PDG for the pull up
CPUSLP# [6]
<Layout note> Close to pin
H_FERR# [6]
resistor value and tolerance requirement. CRB is more strictly.
<20100811_Jerry>for Thermtrip#, please use 60 ohms+/-5% pull up.
<Layout note> Close to pin within 1"
PM_THRMTRIP# [6]
<Layout note> Close to pin within 200mil
Follow CRB
SERIRQ KBRST#
GA20 PCH_GPIO36
H_A20M# CPUSLP#_R
H_IGNNE#
VCC3_VCC3[12,13,14]
R96 4.7K/J_4R96 4.7K/J_4 R117 10K/J_4R117 10K/J_4
R95 8.2K/J_4R95 8.2K/J_4 R103 *10K/J_4R103 *10K/J_4
R109 1K/J_4R109 1K/J_4 R532 *1K/J_4R532 *1K/J_4
R105 1K/J_4R105 1K/J_4
11
+3V
+1.05V
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Wednesday, November 02, 2011
Date: Sheet of
Wednesday, November 02, 2011
Date: Sheet of
5
4
3
2
Wednesday, November 02, 2011
PROJECT :
Tiger Point Sata/Host
Tiger Point Sata/Host
Tiger Point Sata/Host
ZE7
ZE7
ZE7
1
1B
1B
1B
4011
4011
4011
5
4
3
2
1
Tiger Point (CLG)
TGP
PCI
PCI
TGP
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8
AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
C/BE0# C/BE1# C/BE2# C/BE3#
1
1
B22 D18 C17 C18 B17 C19 B18 B19 D16 D15 A13 E14 H14 L14 J14 E10 C11 E12 B9 B13 L12 B8 A3 B5 A6 G12 H12 C8 D9 C7 C1 B1
H16 M15
<20101104> Reserve R389(PCH_GPIO22 PD) for 27MHz or 96MHz choosing, need vBIOS support
C13
Pull up --> for 27MHz
L16
Pull down --> for 96MHz
R30 *1K/J_4R30 *1K/J_4
R389 *8.2K/J_4R389 *8.2K/J_4
PCI_INTB# PCI_IRDY# PCI_INTG# PCI_INTE#
PCI_LOCK# PCI_INTD# PCI_TRDY# PCI_PERR#
PCI_DEVSEL# PCI_FRAME# PCI_REQ1# PCI_REQ2#
PCI_INTA# PCI_INTC# PCI_INTF# PCI_INTH#
PCI_STOP# PCI_SERR# EC_SCI#
RP3 8.2K_8P4RRP3 8.2K_8P4R
1 3 5 7
RP2 8.2K_8P4RRP2 8.2K_8P4R
1 3 5 7
RP1 8.2K_8P4RRP1 8.2K_8P4R
1 3 5 7
RP4 8.2K_8P4RRP4 8.2K_8P4R
1 3 5 7
R392 8.2K/J_4R392 8.2K/J_4 R391 8.2K/J_4R391 8.2K/J_4 R41 10K/J_4R41 10K/J_4
PCH_GPIO48 PCH_GPIO17
PCH_GPIO22
R35 *1K/J_4R35 *1K/J_4 R421 *1K/J_4R421 *1K/J_4R424 *1K/J_4R424 *1K/J_4
R388 8.2K/J_4R388 8.2K/J_4
2 4 6 8
2 4 6 8
2 4 6 8
2 4 6 8
+3V
+3V
+3V
+3V
+3V
+3V
+3V
U22A
U22A
A5
PCI CLK 33MHz
D D
PCLK_ICH[2]
EMI
R73
R73 *33/J_4
*33/J_4
C99
C99 *10P/50V_4
*10P/50V_4
C C
EC_SCI#[27]
T34T34
VCC3_VCC3[11,13,14]
B B
+3V
R70 10K/J_4R70 10K/J_4 R43 8.2K/J_4R43 8.2K/J_4
PCI_DEVSEL#
T32T32
PCI_IRDY# PCI_SERR#
PCI_STOP# PCI_LOCK# PCI_TRDY# PCI_PERR# PCI_FRAME#
T13T13 T4T4
PCI_REQ1# PCI_REQ2#
PCH_GPIO48 PCH_GPIO17 PCH_GPIO22 EC_SCI#
PCI_INTA# PCI_INTB# PCI_INTC# PCI_INTD# PCI_INTE# PCI_INTF# PCI_INTG# PCI_INTH#
PCH_A16WP
PAR
B15
DEVSEL#
J12
PCICLK
A23
PCIRST#
B7
IRDY#
C22
PME#
B11
SERR#
F14
STOP#
A8
PLOCK#
A10
TRDY#
D10
PERR#
A16
FRAME#
A18
GNT1#
E16
GNT2#
G16
REQ1#
A20
REQ2#
G14
GPIO48/ STRAP1#
A2
GPIO17/ STRAP2#
C15
GPIO22
C9
GPIO1
B2
PIRQA#
D7
PIRQB#
B3
PIRQC#
H10
PIRQD#
E8
PIRQE#/GPIO2
D6
PIRQF#/GPIO3
H8
PIRQG#/GPIO4
F8
PIRQH#/GPIO5
D11
STRAP0#
K9
RSVD01
M13
RSVD02
Tiger Point
Tiger Point
12
<20090601(A1A)_Checklist Rev0.7> Strap1#/strap2#: signals have weak internal pull-ups
ICH Boot BIOS select
PCH_GPIO17 (INT PU)
0 1 SPI 1 0 PCI
1 1 LPC
A16 SWAP Override strap
PCH_A16WP
A A
(INT PU)
PCI_GNT#2
PCH_GPIO48 (INT PU)
Boot BIOS Location
(CURRENTLY USE)
Low = A16 swap override enabled High = Default
Internal PU Should not be PD
5
IRQ
PIRQA PIRQB PIRQC PIRQD PIRQE PIRQF PIRQG PIRQH
4
USB UHCI Controller #1, #4
AC'97 Codec; option for SMBUS USB UH Controller #3; SATA/IDE Native Mode USB UHCI Controller #2 Internal LAN; Option for SCI, TCO, HPET#0,1,2 Option for SCI, TCO, HPET#0,1,2 Option for SCI, TCO, HPET#0,1,2 USB EHCI Controller; Option for SCI, TCO, HPET#0,1,2
Description
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Wednesday, November 02, 2011
Date: Sheet of
Wednesday, November 02, 2011
Date: Sheet of
3
Wednesday, November 02, 2011
2
PROJECT :
TigerPoint PCI
TigerPoint PCI
TigerPoint PCI
ZE7
ZE7
ZE7
1
1B
1B
1B
4012
4012
4012
5
Tiger Point (CLG)
ACZ_BITCLK_AUDIO_R
ACZ_BITCLK_CODEC[20] ACZ_BITCLK_CPU[5]
R90 33/J_4R90 33/J_4 R93 90.9/F_4R93 90.9/F_4
2011/4/28 For EMI Sam request
D D
ACZ_RST#_CODEC[20] ACZ_RST#_CPU[5]
ACZ_SDOUT_CODEC[20] ACZ_SDOUT_CPU[5]
ACZ_SYNC_CODEC[20] ACZ_SYNC_CPU[5]
<20110516_DGv1.5> Change ACZ BITCLK/RST/SDOUT/SYNC to CPU RES from 33ohm to 90.9ohm
C C
R452 33/J_4R452 33/J_4 R454 90.9/F_4R454 90.9/F_4
R461 33/J_4R461 33/J_4
R451 33/J_4R451 33/J_4 R468 90.9/F_4R468 90.9/F_4
ACZ_BITCLK_AUDIO_R
C136
C136 *30P/50V_4
*30P/50V_4
ACZ_RST#_AUDIO_R
ACZ_RST#_AUDIO_R
ACZ_SDOUT_AUDIO_R
ACZ_SDOUT_AUDIO_R
ACZ_SYNC_AUDIO_R
ACZ_SYNC_AUDIO_R
<20090529(A1A)_Checklist Rev0.7> If integrated LAN is not used LAN_RST# tie it to GND.
C348 6P/50V_4C348 6P/50V_4
32.768KHz,+-20PPM
32.768KHz,+-20PPM
C349 6P/50V_4C349 6P/50V_4
4
3
2
1
13
+3V_S5
VCCRTC
Follow CRB
PCLK_SMB PDAT_SMB PM_BATLOW# DNBSWON# EC_SMI# SYS_RST# SMBALERT# SMB_LINK_ALERT# PCIE_WAKE# SMLINK1 SMLINK0 ICH_RI# PCH_GPIO14 PCH_GPIO15 PCH_GPIO9 PCH_GPIO8
PCH_GPIO12 PCH_GPIO13
MCH_SYNC# CLKRUN# BM_BUSY# THERM_ALERT#
DMI_AC_ENABLE TPT_PWROK EC_RSMRST#
TGP
U22D
U22D
AA5
T18T18
LDRQ1#/GPIO23
T21T21
T36T36 T37T37 T14T14 T17T17 T16T16
RTC_X1 RTC_X2
V6
LAD0/FWH0
AA6
LAD1/FWH1
Y5
LAD2/FWH2
W8
LAD3/FWH3
Y8
LDRQ0#
Y4
LFRAME#
P6
HDA_BIT_CLK
U2
HDA_RST#
W2
HDA_SDI0
V2
HDA_SDIN1
P8
HDA_SDIN2
AA1
HDA_SDOUT
Y1
HDA_SYNC
AA3
CLK14
U3
EE_CS
AE2
EE_DIN
T6
EE_DOUT
V3
EE_SHCLK
T4
LAN_CLK
P7
LANR_STSYNC
B23
LAN_RST#
AA2
LAN_RXD0
AD1
LAN_RXD1
AC2
LAN_RXD2
W3
LAN_TXD0
T7
LAN_TXD1
U4
LAN_TXD2
W4
RTCX1
V5
RTCX2
T5
RTCRST#
E20
SMBALERT#/GPIO11
H18
SMBCLK
E23
SMBDATA
H21
SMLALERT#
F25
SMLINK0
F24
SMLINK1
R2
SPI_MISO
T1
SPI_MOSI
M8
SPI_CS#
P9
SPI_CLK
R4
SPI_ARB
Tiger Point
Tiger Point
LAD0[25,27] LAD1[25,27] LAD2[25,27] LAD3[25,27]
LFRAME#[25,27]
ACZ_SDINO[5] ACZ_SDIN1[20]
14M_ICH[2]
Y4
Y4
1 4
2 3
ACZ_BITCLK_AUDIO_R ACZ_RST#_AUDIO_R
ACZ_SDOUT_AUDIO_R ACZ_SYNC_AUDIO_R 14M_ICH
R434
R434 10M/J_4
10M/J_4
RTCRST#
SMBALERT# PCLK_SMB PDAT_SMB SMB_LINK_ALERT# SMLINK0 SMLINK1
TGP
CPUPWRGD/GPIO49
MISC
MISC
SUS_STAT#/LPCPD#
BM_BUSY#/GPIO0
DPRSLPVR
STP_PCI#
STP_CPU#
CLKRUN#
VRMPWRGD
MCH_SYNC#
PWRBTN#
SYS_RESET#
PLTRSTB
INTRUDER#
RSMRST#
INTVRMEN
SLP_S3# SLP_S4# SLP_S5#
BATLOW#
DPRSTP#
LPC AUDIO LAN
LPC AUDIO LAN
EPROM
EPROM
RTC SMB SPI
RTC SMB SPI
GPIO6 GPIO7 GPIO8
GPIO9 GPIO10 GPIO12 GPIO13 GPIO14 GPIO15
GPIO24 GPIO25 GPIO26 GPIO27 GPIO28
GPIO33 GPIO34 GPIO38 GPIO39
THRM#
SUSCLK
WAKE#
PWROK
SPKR
DPSLP# RSVD31
RI#
BM_BUSY#
T15
PCH_GPIO6
W16
PCH_GPIO7
W14
PCH_GPIO8
K18
PCH_GPIO9
H19
EC_SMI#
M17
PCH_GPIO12
A24
PCH_GPIO13
C23
PCH_GPIO14
P5
PCH_GPIO15
E24
PM_DPRSLPVR
AB20 Y16 AB19
PCH_GPIO24
R3
DMI_AC_ENABLE
C24
PCH_GPIO26
D19
PCH_GPIO27
D20
PCH_GPIO28
F22
CLKRUN#
AC19
PCH_GPIO33
U14
BOARDID0
AC1
BOARDID1
AC23
BOARDID2
AC24
H_PWRGD
AB22
THERM_ALERT#
AB17
HWPG
V16
MCH_SYNC#
AC18
DNBSWON#
E21
ICH_RI#
H23 G22
SUSCLK
D22
SYS_RST#
G18
PLT_RST#
G23
PCIE_WAKE#
C25
SM_INTRUDER#
T8
TPT_PWROK
U10
EC_RSMRST#
AC3
ICH_INTVRMEN
AD3 J16
SUSB#
H20
SUSC#
E25 F21
PM_BATLOW#
B25
ICH_DPRSTP_R#
AB23
H_DPSLP#
AA18 F20
T20T20 T19T19
EC_SMI# [27]
T38T38
PM_STPPCI# [2] PM_STPCPU# [2]
T35T35 T8T8
T10T10 T6T6
CLKRUN# [27]
T15T15R472 90.9/F_4R472 90.9/F_4
H_PWRGD [6,16]
THERM_ALERT# [5,6,27] HWPG [2,16,27]
DNBSWON# [16,27]
T5T5
SUSCLK [27]
PCIE_WAKE# [22,25]
TPT_PWROK [16]
EC_RSMRST# [16,27]
SPKR [20] SUSB# [16,27]
SUSC# [16,27]
T12T12
R108 *0/short_4R108 *0/short_4
H_DPSLP# [6]
<20101105> GPIO12 for A3-test CLKREQ setting GPIO12 Command: For CLK Gen Byte5 CLKREQ# strap Pull-high: 0x58 -> SRC2/4/6 Pull-low: 0x00 -> SRC1/3/5
<20101108> GPIO13 for A3-test LAN chip selection Pull-high -> for Atheros LAN AR8158 Pull-down -> for Realtek LAN RTL8105TA-VC-CG
<20110607> PU to +3V_S5 for GPIO12/13 no use to follow checklist v1.0
Stuff -> Unuse thermal sensor Unstuff -> Use thermal sensor
R107 *56/F_4R107 *56/F_4
+1.05V
ICH_DPRSTP# [6]
SM_INTRUDER# ICH_INTVRMEN
R378 8.2K/J_4R378 8.2K/J_4 R383 8.2K/J_4R383 8.2K/J_4 R402 8.2K/J_4R402 8.2K/J_4 R431 *10K/J_4R431 *10K/J_4 R49 10K/J_4R49 10K/J_4 R375 10K/J_4R375 10K/J_4 R379 10K/J_4R379 10K/J_4 R394 10K/J_4R394 10K/J_4 R404 10K/J_4R404 10K/J_4 R418 10K/J_4R418 10K/J_4 R420 10K/J_4R420 10K/J_4 R422 10K/J_4R422 10K/J_4 R28 10K/J_4R28 10K/J_4 R403 10K/J_4R403 10K/J_4 R380 10K/J_4R380 10K/J_4 R393 10K/J_4R393 10K/J_4 R407 10K/J_4R407 10K/J_4 R382 10K/J_4R382 10K/J_4
VCC3_VCC3[11,12,14]
R471 1K/F_4R471 1K/F_4 R464 8.2K/J_4R464 8.2K/J_4 R467 10K/J_4R467 10K/J_4 R465 10K/J_4R465 10K/J_4
R401 1K/J_4R401 1K/J_4 R495 10K/J_4R495 10K/J_4 R460 10K/J_4R460 10K/J_4
R473 1M/F_6R473 1M/F_6 R458 332K/F_4R458 332K/F_4
TPT Power OK (CLG)
+3V
C144 0.1U/10V_4C144 0.1U/10V_4
U4
U4
B B
ECPWROK[5,8,16,27]
HWPG
R101 *0/J_4R101 *0/J_4
TC7SH08FU
TC7SH08FU
2 1
3 5
TPT_PWROK
4
RTC (RTC)
+3VPCU VCCRTC
D16
D16
CH500H-40
CH500H-40
D15
D15
CH500H-40
CH500H-40
R254
R254 1K/J_4
1K/J_4
20MIL 20MIL
A A
12
Q27
Q27
METR3904-G
METR3904-G
CN5
CN5 RTC SOCKET
RTC SOCKET
C222
C222
1U/10V_6
1U/10V_6 R211
R211
20K/F_6
20K/F_6
1 3
2
ML1220 Coin type AHL03001406 Maxell (HML) 18mAH AHL03001424 FDK (SAY) 15mAH AHL03017100 Panasonic (MAT) 17mAH
5
RTCRST#VCCRTC_3
C223
C223
1U/10V_6
1U/10V_6
R218 2K/F_4R218 2K/F_4
R513 *0/J_4R513 *0/J_4 G1
G1
12
*SHORT_PAD
*SHORT_PAD
VCCRTC_2VCCRTC_1VCCRTC_4
<20110426 (G1A)> Add 0.1uF CAP to prevent PWROK glitch issue
C143
C143
0.1U/10V_4
0.1U/10V_4
RTCRST#_EC [27]
+5V_S5
R217 2K/F_4R217 2K/F_4
R216
R216
68.1K/F_4
68.1K/F_4
R215
R215
150K/F_4
150K/F_4
Clock GEN I2C Level Shift
3
3
2N7002K
2N7002K
Q38
Q38
2N7002K
2N7002K
Q37
Q37
2
2
PCH: +3V_S5
PCLK_SMB[25]
PCH: +3V_S5
PDAT_SMB[25]
4
+3V
R374
R374
8.2K/J_4
8.2K/J_4
R376
R376
8.2K/J_4
8.2K/J_4
CLK GEN: +3V
SMBCK1 [2,4,25]
CLK GEN: +3V
SMBDT1 [2,4,25]
3
1
+3V
1
Platform Reset (CLG)
PLT_RST#
R417 0/J_4R417 0/J_4
Mother Board ID (CLG)
R462
R462
R92
R92
*10K/J_4
*10K/J_4
*10K/J_4
*10K/J_4
BOARDID0 BOARDID1 BOARDID2
R87
R87
R463
R463
10K/J_4
10K/J_4
10K/J_4
10K/J_4
<20110428 (G1A)> Stuff 10K PD resistors from ZE7 A2-stage
2
+3V
C338 *0.1U/10V_4C338 *0.1U/10V_4
U21
U21
*TC7SH08FU
*TC7SH08FU
2 1
+3V
R457
R457 *10K/J_4
*10K/J_4
R469
R469 10K/J_4
10K/J_4
4
3 5
PLTRST# [6,16,22,25,26,27]
R395
R395 100K_4
100K_4
ACZ_SDOUT (INT PD)
INTVRMEN
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
ACZ_SYNC (INT PD)
0
0
1
Enable internal VccSus1_5 VRM
1
(default)
Disable
0
Wednesday, November 16, 2011
Wednesday, November 16, 2011
Wednesday, November 16, 2011
Description
4 x 1s
*
0
Reserved1
0
1
Reserved
1 1 x 4s(1 port/4 lanes)
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
TPT ACZ/GPIO/RTC
TPT ACZ/GPIO/RTC
TPT ACZ/GPIO/RTC
1
ZE7
ZE7
ZE7
4013
4013
4013
1B
1B
1B
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