Quanta ZE7 DA0ZE7MB6D0, Aspire One AOD270 Schematic

1

ZE7 Block Diagram (Intel Cedar Trail-M Platform)

2

3

4

5

6

7

8

01

DDI0

P17

LVDS 18bit,SC

1366x768

1920x1200

4

P18

HDMI 1.3a

DDI1

1366x768

DAC

PCIE Gen1

USB 2.0

A A

HDMI CONN

LVDS/eDP CONN

VGA CONN

B B

RTL8105TA-VC-CG

RJ45 CONN

P22

P22

0

2

RTS5209-GR
CARDREADER

C C

USB PORT

Left

5 IN1 CARDREADER

SD3.0, MS, MS PRO,
xD, MMC

3

P21

0 21

USB PORT

Right Down Right Up

P26

P21

P18

P18

3

1

P26

USB PORT

Mini card2

Mini card1

MM-SIM CARD

USB interface
module

P21

P25

P25

P19

0ohm

5

7

P25

6

CCD

Cedarview-M

400 / 640MHz

DC(3.5W) & DC(6.5W)

(32nm)

Micro-FCBGA8

(22x22mm)

P5~9

x2 DMI Gen1

Tigerpoint (NM10)

1.5W

vFBGA

(360 balls,17x17mm)

P10~15

DDR III,800/1066 MT/s

Channel A

HD AUDIO I/F

SATA II I/F

0

Mobile 2.5" HDD

CLK Gen.
SLG8LV631V

UNBUFFERED
DDRIII SODIMM

RC-B/F
CLK2/3, H=4

Audio CODEC
Realtek 271X

P24

P20

P2

P4

MIC In Jack
Analog MIC
Speaker Header (2W)

P20

EC

BATTERY CHAGER

D D

SYSTEM
5V/3V PCU

P29

P30

DDR 1.5VSUS

+1.05V

CPU Core
Gfx Core

P31

1

2

Discharge/+1.8V/

P32

+3.3V_PRIME
Thermal Protection

P33

P34

P35

3

Keyboard

4

Touch Pad

P19 P19 P29

Nuvoton NPCE791L

SPI Flash

5

Charger

P27

PWM FAN

6

P27

P6

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

7

PROJECT :

Block Diagram

Block Diagram

Block Diagram

ZE7

ZE7

ZE7

1B

1B

1 40Wednesday, November 02, 2011

1 40Wednesday, November 02, 2011

1 40Wednesday, November 02, 2011

8

1B

5

CLK GEN (CLK)

+3V

L32

PBY160808T-301Y-N/2A/300ohm_6

D D

PBY160808T-301Y-N/2A/300ohm_6

L32

Place close to L32

VDD_IO can be ranging from 1.05V to 3.3V.

+1.05V

L28

L28
PBY160808T-301Y-N/2A/300ohm_6

R311

R311
*20K/J_4

*20K/J_4

R310

R310
*100K_4

*100K_4

C238

C238
33P/50V_4

33P/50V_4

C236

C236
33P/50V_4

33P/50V_4

PBY160808T-301Y-N/2A/300ohm_6

CG_XIN

21

Y2 14.318MHZY2 14.318MHZ

Load Capacitance=20p

CG_XOUT

<20110110> CFG input hardware strapping to allocate PLL assignment.
LOW = Both CPU and SRC clock drive from PLL3
HIGH = CPU clock drive from PLL1, SRC clock drive from PLL3.
Contains 100kΩ pull-down resistor.

R221 *0/short_6R221 *0/short_6

Place close to L28

C C

<Layout note>
Crystal place within 500mil of CK505

+3V

B B

VDD_CLK_3.3V

C228

C228
10U/10V_8

10U/10V_8

C285

C285
10U/10V_8

10U/10V_8

C278

C278

C254

C254

.1U/10V_4

.1U/10V_4

.1U/10V_4

.1U/10V_4

0.1uF near every power pin

VDD_CLKIO_1.05V

C229

C229

C249

C249

.1U/10V_4

.1U/10V_4

.1U/10V_4

.1U/10V_4

0.1uF near every power pin

CLKUSB_48[10]

14M_ICH[13]

PCLK_ICH[12]
LCLK_EC[27]

PCLK_DEBUG[25]

SMBDT1[4,13,25]
SMBCK1[4,13,25]

C253

C253
.1U/10V_4

.1U/10V_4

C242

C242
.1U/10V_4

.1U/10V_4

R312 33/J_4R312 33/J_4

R293 33/J_4R293 33/J_4

R296 22/J_4R296 22/J_4
R304 22/J_4R304 22/J_4
R291 33/J_4R291 33/J_4

4

CG_XOUT
CG_XIN

SMBDT1
SMBCK1

FSB
USB_48M

FSC

ITP_EN
33M_SEL

U12

U12

5

VDD_REF_3.3

9

VDD_PCI_3.3

14

VDD_48M_3.3

30

VDD_SRC_IO_1.05

35

VDD_SRC_IO_1.05

48

VDD_CPU_IO_1.05

1

NC

2

NC

13

NC

54

NC

3

XTAL_OUT

4

XTAL_IN

7

SDA

8

SCL

15

USB48_1/FSB

17

USB48_2

6

REF/FSC

10

PCIF/ITP_EN

11

25MHz/PCI_2/SEL_33MHz

12

VSS_PCI

16

VSS_48M

22

VSS_LCD

24

VSS_SATA

39

VSS_SRC

51

VSS_CPU

56

VSS_REF

57

Thermal Pad

SLG8LV631V

SLG8LV631V

VDD_CORE_1.5
VDD_CORE_1.5

PCI_STOP#

CPU_STOP#

CPU_0

CPU_0#

CPU_1

CPU_1#

SRC_1/CPU_ITP

SRC_1/CPU_ITP#

SRC_2

SRC_2#

SRC_3

SRC_3#

SRC_4

SRC_4#

SRC_5

SRC_5#

SRC_6

SRC_6#

DOT96/SRC7

DOT96#/SRC7#

LCD_CLK

LCD_CLK#

SATA

SATA#

CLKREQ_A#
CLKREQ_B#
CLKREQ_C#

CKPWRGD/PD#

23
45

36
42

53
52

50
49

44
43

41
40

38
37

34
33

32
31

28
27

18
19

20
21

26
25

CLKREQ_LAN#_R

47

CLKREQ_MPC#_R

46

CLKREQ_MMC#_R

29

HWPG

55

PM_STPPCI#_R
PM_STPCPU#_R

DREFCLK_R
DREFCLK#_R

3

VDD_CLK_1.5V

C277

C277

C225

C225

.1U/10V_4

.1U/10V_4

.1U/10V_4

.1U/10V_4

0.1uF near every power pin

R251 *0/J_4R251 *0/J_4
R229 *0/J_4R229 *0/J_4

R299 *0/J_4R299 *0/J_4
R300 *0/J_4R300 *0/J_4

R204 475/F_4R204 475/F_4
R199 475/F_4R199 475/F_4
R284 475/F_4R284 475/F_4

C357

C357
*0.1U/10V_4

*0.1U/10V_4

2

R219 2.2/J_6R219 2.2/J_6

1 2

C224

C224
10U/10V_8

10U/10V_8

PBY160808T-301Y-N/2A/300ohm_6

PBY160808T-301Y-N/2A/300ohm_6

<20100819_FAE Poyueh> Add 2.2ohm resistor for noise suppress

+1.5V

L27

L27

Place close to L27

<20100803_Sam> Reserve 0ohm to connect to CK505, 10Kohm pull up is required.

PM_STPPCI# [13]
PM_STPCPU# [13]

CLK_MCH_BCLK [6]
CLK_MCH_BCLK# [6]

CLK_DDR3_REFCLK [8]
CLK_DDR3_REFCLK# [8]

CLK_PCIE_LANP [22]
CLK_PCIE_LANN [22]

CLK_PCIE_MNC_P [25]
CLK_PCIE_MNC_N [25]

CLK_PCIE_MPC_P [25]
CLK_PCIE_MPC_N [25]

CLK_PCIE_DMIP [5]
CLK_PCIE_DMIN [5]

CLK_PCIE_MMC_P [26]
CLK_PCIE_MMC_N [26]

CLK_PCIE_ICH [10]
CLK_PCIE_ICH# [10]

DREFCLK [5]
DREFCLK# [5]

DREFSSCLK [5]
DREFSSCLK# [5]

CLK_PCIE_SATA [11]
CLK_PCIE_SATA# [11]

<20100819> Add 475ohm resistors to prevent current leakage

CLKREQ_LAN# [22]
CLKREQ_MPC# [25]
CLKREQ_MMC# [26]

HWPG [13,16,27]

<20110221> Reserve 0.1F cap to solve that PCICLK (EC 33MHz) sometimes
will change to 25MHz after flash BIOS and restart in first time issue.

From SB

To CPU (Host CLK) 100 MHz

To CPU (DDR3 IO CLK)

To Mini Card 2 (3G/Wimax) 100 MHz

To CPU (DMI CLK) 100 MHz

To SB (DMI CLK) 100 MHz

To CPU (DPLSS CLK) 100 MHz

Control SRC_1

Register B5b6 for CLKREQ_A#
0 = SRC1, 1=SRC2
Register B5b4 for CLKREQ_B#

Control SRC_3

0 = SRC3, 1=SRC4

Control SRC_5 Register B5b3 for CLKREQ_C#

0 = SRC5, 1=SRC6

100 MHz

100 MHzTo LAN (LAN)

<20101109> Place R235/ R241/ R248/ R254 close to U13

100 MHzTo Mini Card 1 (WLAN)

100 MHzTo Card Reader (MMC)

96 MHzTo CPU (PLL CLK)

<20110110> DPL_REFSSCCLK is used to drive internal
registers and logics of the display interface and therefore
needs to be present at all times.

100 MHzTo SB (SATA CLK)

1

02

FSC FSB Frequency
0 0 133MHz
0 1 166MHz

R313 *10K/J_4R313 *10K/J_4

+3V

A A

R306 10K/J_4R306 10K/J_4

R301 10K/J_4R301 10K/J_4

+3V +3V +3V

R295 *10K/J_4R295 *10K/J_4

1 = Pin 43/44 as CPU_ITP

ITP_EN

0 = Pin 43/44 as SRC_1

33M_SEL FSC

1 = Pin 11 as 33MHz

0= Pin 11 as 25MHz

5

1 1 200MHz

1 0 100MHz

R289 10K/J_4R289 10K/J_4

R259 *10K/J_4R259 *10K/J_4

<20100720_Sam> Keep 100MHz as default.

R317 *10K/J_4R317 *10K/J_4

FSB

R318 10K/J_4R318 10K/J_4

4

<EMI>

USB_48M

ITP_EN

FSB

FSC

33M_SEL

C280 *10P/50V_4C280 *10P/50V_4

C259 *10P/50V_4C259 *10P/50V_4

C279 *10P/50V_4C279 *10P/50V_4

C245 *10P/50V_4C245 *10P/50V_4

C266 *10P/50V_4C266 *10P/50V_4

3

PM_STPPCI#_R

PM_STPCPU#_R

CLKREQ_MPC#_R

CLKREQ_MMC#_R

CLKREQ_LAN#_R

R250 10K/J_4R250 10K/J_4

R230 10K/J_4R230 10K/J_4

R213 10K/J_4R213 10K/J_4

R279 10K/J_4R279 10K/J_4

R212 10K/J_4R212 10K/J_4

2

+3V

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

PROJECT :

CLOCK GENERATOR

CLOCK GENERATOR

CLOCK GENERATOR

ZE7

ZE7

ZE7

2 40Wednesday, November 02, 2011

2 40Wednesday, November 02, 2011

1

2 40Wednesday, November 02, 2011

1B

1B

1B

5

4

3

2

1

03

D D

C C

B B

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

PROJECT :

Reserved

Reserved

Reserved

ZE7

ZE7

ZE7

1B

1B

1B

3 40Wednesday, November 02, 2011

3 40Wednesday, November 02, 2011

3 40Wednesday, November 02, 2011

1

5

DDR_STD(DDR)

M_A_A[15:0][8]

D D

C C

B B

Populate rules: populate
SODIMM1 first
Strictly follow the mapping
between clock/control signal
groups and SODIMMs, as
well as SMB address. Other
configurations/mappings will
not
be supported by MRC

DESIGN NOTE:

+3V

ADDRESS-(A2)H

R150

R150
10K/J_4

10K/J_4

R170

R170

R151

R151
*10K/J_4

*10K/J_4

10K/J_4

10K/J_4

M_A_BS0[8]
M_A_BS1[8]
M_A_BS2[8]
M_CS#2[8]
M_CS#3[8]
M_CLK2[8]
M_CLK2#[8]
M_CLK3[8]
M_CLK3#[8]
M_CKE2[8]
M_CKE3[8]
M_A_CAS#[8]
M_A_RAS#[8]
M_A_WE#[8]

SMBCK1[2,13,25]
SMBDT1[2,13,25]

M_ODT2[8]
M_ODT3[8]
M_A_DM[7:0][8]

M_A_DQS[7:0][8]

M_A_DQS#[7:0][8]

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

DIMM1_SA0
DIMM1_SA1
SMBCK1
SMBDT1

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

98
97
96
95
92
91
90
86
89
85

107

84
83

119

80
78

109
108

79
114
121
101
103
102
104

73

74
115
110
113
197
201
202
200

116
120

11

28

46

63
136
153
170
187

12

29

47

64
137
154
171
188

10

27

45

62
135
152
169
186

4

DIMM0 H=4mm

JDIM1A

JDIM1A

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15

BA0
BA1
BA2
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE#
SA0
SA1
SCL
SDA

ODT0
ODT1

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7

DDR3-DIMM0_H=4_STD

DDR3-DIMM0_H=4_STD

PC2100 DDR3 SDRAM SO-DIMM

PC2100 DDR3 SDRAM SO-DIMM

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46

(204P)

(204P)

DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

3

+1.5VSUS

+3V

C179

C179

DDR3_DRAMRST#[8]

2.48A

C178

C178

.1U/10V_4

.1U/10V_4

+SMDDR_VREF_DQ0
+SMDDR_VREF_DIMM

5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

M_A_DQ[63:0] [8]

.1U/10V_4

.1U/10V_4

2

JDIM1B

JDIM1B

75

VDD1

76

VDD2

81

VDD3

82

VDD4

87

VDD5

88

VDD6

93

VDD7

94

VDD8

99

VDD9

100

VDD10

105

VDD11

106

VDD12

111

VDD13

112

VDD14

117

VDD15

118

VDD16

123

VDD17

124

VDD18

199

VDDSPD

77

NC1

122

NC2

125

NCTEST

198

EVENT#

30

RESET#

1

VREF_DQ

126

VREF_CA

2

VSS1

3

VSS2

8

VSS3

9

VSS4

13

VSS5

14

VSS6

19

VSS7

20

VSS8

PC2100 DDR3 SDRAM SO-DIMM

VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15

R191 1K/F_4R191 1K/F_4

PC2100 DDR3 SDRAM SO-DIMM

25
26
31
32
37
38
43

DDR3-DIMM0_H=4_STD

DDR3-DIMM0_H=4_STD

<Layout note>
PLACE TWO 1K RESISTORS CLOSE TO CPU DIMM ON
DDR_VREF_CA

+1.5VSUS

C194

C194

.1U/10V_4

.1U/10V_4

44

VSS16

48

VSS17

49

VSS18

54

VSS19

55

VSS20

60

VSS21

61

VSS22

65

VSS23

66

VSS24

71

VSS25

72

VSS26

127

VSS27

128

VSS28

133

VSS29

134

VSS30

138

VSS31

139

VSS32

144

VSS33

145

VSS34

150

VSS35

151

VSS36

155

VSS37

156

VSS38

161

VSS39

162

VSS40

167

VSS41

168

VSS42

172

VSS43

173

VSS44

178

VSS45

179

VSS46

184

VSS47

185

VSS48

189

VSS49

190

VSS50

195

VSS51

196

VSS52

(204P)

(204P)

203

VTT1

204

VTT2

205

GND

206

GND

R198 *0/J_4R198 *0/J_4

+SMDDR_VREF_DIMM_R

R208

R208
1K/F_4

1K/F_4

+0.75V_DDR_VTT

+SMDDR_VREF

R205 0/J_4R205 0/J_4

1

+SMDDR_VREF

+SMDDR_VREF_DIMM

C205

C205

0.1U/50V_6

0.1U/50V_6

04

<Layout note>
PLACE TWO 1K RESISTORS CLOSE TO CPU DIMM ON DDR_VREF_DQ

Place these Caps near DIMM0

+1.5VSUS

+

C199

C198

C198
10U/6.3V_6

10U/6.3V_6

C192

C192
1U/6.3V_4

1U/6.3V_4

C199
10U/6.3V_6

10U/6.3V_6

C189

C189
1U/6.3V_4

1U/6.3V_4

C197

C197
10U/6.3V_6

10U/6.3V_6

C196

C196
10U/6.3V_6

10U/6.3V_6

C168

C169

C169

C193

.1U/10V_4

.1U/10V_4

C162

C162
1U/6.3V_4

1U/6.3V_4

C193
.1U/10V_4

.1U/10V_4

C173

C173
1U/6.3V_4

1U/6.3V_4

C164

C164
1U/6.3V_4

1U/6.3V_4

5

C171

C171
.1U/10V_4

.1U/10V_4

A A

+1.5VSUS

C191

C191
1U/6.3V_4

1U/6.3V_4

C163

C163
10U/6.3V_6

10U/6.3V_6

C165

C165
1U/6.3V_4

1U/6.3V_4

C168
10U/6.3V_6

10U/6.3V_6

C161

C161
1U/6.3V_4

1U/6.3V_4

+

C203

C203

*330U/2V_7343

*330U/2V_7343

4

<20100827> Add by DG request

+0.75V_DDR_VTT

C190

C190

C200

C200

C172

C172

10U/6.3V_6

10U/6.3V_6

LAYOUT NOTE: PLACE CAPS
NEAR DIMM-0

+SMDDR_VREF_DQ0

C170

C170

.1U/10V_4

.1U/10V_4

*10U/6.3V_6

*10U/6.3V_6

C167

2.2U/6.3V_6

2.2U/6.3V_6

*10U/6.3V_6

*10U/6.3V_6

.1U/10V_4

.1U/10V_4

C216

C216

3

C185

C185

1U/6.3V_4

1U/6.3V_4

1U/6.3V_4

1U/6.3V_4

+SMDDR_VREF_DIMM

C214

C214

2.2U/6.3V_6

2.2U/6.3V_6

C176

C176

+1.5VSUS

C160

C160

.1U/10V_4

.1U/10V_4

+0.75V_DDR_VTT

C175

C175

1U/6.3V_4

1U/6.3V_4

R148 1K/F_4R148 1K/F_4

C184

C184

1U/6.3V_4

1U/6.3V_4C167

2

R149 *0/J_4R149 *0/J_4

+SMDDR_VREF_DQ0_R

R147

R147
1K/F_4

1K/F_4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

+SMDDR_VREF

R146 0/J_4R146 0/J_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

DDRIII SO-DIMM-0

DDRIII SO-DIMM-0

DDRIII SO-DIMM-0

+SMDDR_VREF

+SMDDR_VREF_DQ0

C166

C166

0.1U/50V_6

0.1U/50V_6

1

ZE7

ZE7

ZE7

1B

1B

4 40Wednesday, November 02, 2011

4 40Wednesday, November 02, 2011

4 40Wednesday, November 02, 2011

1B

5

Cedar View (CPU)

HDMI: 7.5", 4 via, 1.65 Gbps

Level Shifter For HDMI

D D

TX2_HDMI+[17]
TX2_HDMI-[17]
TX1_HDMI+[17]
TX1_HDMI-[17]
TX0_HDMI+[17]
TX0_HDMI-[17]
TX3_HDMI+[17]
TX3_HDMI-[17]

eDP: 7", 3 via, 2.7Gbps

+1.5V

R32

R32

C55 1U/6.3V_4C55 1U/6.3V_4

0/J_6

0/J_6

<20101125_Colt> Please follow PDG, we will

C C

doing BOM stuff changing in next version CRB

+3V

ACZ_BITCLK_CPU[13]
ACZ_SYNC_CPU[13]

ACZ_SDINO[13]
ACZ_SDOUT_CPU[13]

ACZ_RST#_CPU[13]

DDI0_HDMI_SCL[17]
DDI0_HDMI_SDA[17]

T33T33
T31T31

HDMI_DDI0_HPD#[17]

TX2_HDMI+

C66 .1U/10V_4C66 .1U/10V_4

TX2_HDMI-

C67 .1U/10V_4C67 .1U/10V_4

TX1_HDMI+

C61 .1U/10V_4C61 .1U/10V_4

TX1_HDMI-

C68 .1U/10V_4C68 .1U/10V_4

TX0_HDMI+

C43 .1U/10V_4C43 .1U/10V_4

TX0_HDMI-

C44 .1U/10V_4C44 .1U/10V_4

TX3_HDMI+

C41 .1U/10V_4C41 .1U/10V_4

TX3_HDMI-

C42 .1U/10V_4C42 .1U/10V_4

T3T3
T9T9

R68 *2.2K/J_4R68 *2.2K/J_4
R62 *eDP@2.2K/J_4R62 *eDP@2.2K/J_4

DDI1_AUX_DP[18]
DDI1_AUX_DN[18]

DDI1_HPD#[18]

DDI1_TX0_DP[18]
DDI1_TX0_DN[18]
DDI1_TX1_DP[18]
DDI1_TX1_DN[18]
DDI1_TX2_DP[18]
DDI1_TX2_DN[18]
DDI1_TX3_DP[18]
DDI1_TX3_DN[18]

T11T11
T7T7

R45 7.5K/F_4R45 7.5K/F_4

R42 33/J_4R42 33/J_4

H_RSVD_TP_H15

DDI0_AUXP
DDI0_AUXN

HDMI_DDI0_HPD#
DDI0_TX2_DP

DDI0_TX2_DN
DDI0_TX1_DP
DDI0_TX1_DN
DDI0_TX0_DP
DDI0_TX0_DN
DDI0_TX3_DP
DDI0_TX3_DN

H_RSVD_TP_J15
DDI1_DDC_SCL

DDI1_DDC_SDA
DDI1_AUX_DP

DDI1_AUX_DN
DDI1_HPD#
DDI1_TX0_DP

DDI1_TX0_DN
DDI1_TX1_DP
DDI1_TX1_DN
DDI1_TX2_DP
DDI1_TX2_DN
DDI1_TX3_DP
DDI1_TX3_DN

H_RSVD_TP_H17
H_RSVD_TP_J17

BREF1.8V
EXT_BANDGAP

ACZ_SDINO_R

4

U24C

U24C

H25

DDI0_DDC_SCL

J22

DDI0_DDC_SDA

C8

DDI0_AUXP

B8

DDI0_AUXN

H22

DDI0_HPD

G2

DDI0_TXP0

G3

DDI0_TXN0

F3

DDI0_TXP1

F2

DDI0_TXN1

D4

DDI0_TXP2

C3

DDI0_TXN2

B7

DDI0_TXP3

A7

DDI0_TXN3

H15

RSVD_TP_H15

J15

RSVD_TP_J15

F25

DDI1_DDC_SCL

G27

DDI1_DDC_SDA

D10

DDI1_AUXP

C10

DDI1_AUXN

D26

DDI1_HPD

E11

DDI1_TXP0

F11

DDI1_TXN0

J11

DDI1_TXP1

H11

DDI1_TXN1

F13

DDI1_TXP2

E13

DDI1_TXN2

J13

DDI1_TXP3

K13

DDI1_TXN3

J17

RSVD_TP_J17

H17

RSVD_TP_H17

E15

BREF18V

F15

BREFREXT

H21

AZIL_BCLK

F22

AZIL_SYNC

E22

AZIL_SDI

F21

AZIL_SDO

E21

AZIL_RST#

CDV_22MM_REV1P10

CDV_22MM_REV1P10

CEDARVIEW

CEDARVIEW

DDI

DDI

IHDA

IHDA

REV = 1.10

REV = 1.10

LVDS VGA

LVDS VGA

DPL_REFSSCCLKP
DPL_REFSSCCLKN

LVDS_CTRL_CLK

LVDS_CTRL_DATA

LVDS_DDC_DATA

3 OF 6

3 OF 6

CRT_HSYNC
CRT_VSYNC

CRT_RED

CRT_GREEN

CRT_BLUE

CRT_IRTN
CRT_IREF

CRT_DDC_DATA

CRT_DDC_CLK

DPL_REFCLKP
DPL_REFCLKN

LVDS_DDC_CLK

LVDS_IBG

LVDS_VBG

LVDS_VREFH

LVDS_VREFL

LVDS_TXP0

LVDS_TXN0

LVDS_TXP1

LVDS_TXN1

LVDS_TXP2

LVDS_TXN2

LVDS_TXP3

LVDS_TXN3
LVDS_CLKP

LVDS_CLKN

PANEL_BKLTCTL

PANEL_BKLTEN

PANEL_VDDEN

3

D14
C14

B12
B11
C11

D12
A13

E29
E27

F17
E17

B9
A9

F28
E24

G24
H24

LIBG

E10
F10

H2
H3

G10
H10
F8
E8
H7
H8
G5
G6

H4
J4

G22
E25
F29

CRT_IREF

R408 681/F_6R408 681/F_6

CRT_DDC_SDA [18]
CRT_DDC_SCL [18]

DREFCLK_R1
DREFCLK#_R1

R426 *0/short_6R426 *0/short_6
R428 *0/short_6R428 *0/short_6

LBKLT_EN
INT_LVDS_DIGON_Q

R406 *0/J_4R406 *0/J_4
R405 *0/J_4R405 *0/J_4

R52 *2.2K/J_4R52 *2.2K/J_4
R48 *2.2K/J_4R48 *2.2K/J_4

LCD_CLK [18]
LCD_DATA [18]

R612.37K/F_4 R612.37K/F_4

TXLOUT0+ [18]
TXLOUT0- [18]
TXLOUT1+ [18]
TXLOUT1- [18]
TXLOUT2+ [18]
TXLOUT2- [18]

TXLCLKOUT+ [18]
TXLCLKOUT- [18]

R414

R414
150/F_4

150/F_4

R65

R65
*10K/J_4

*10K/J_4

R397 *1K/J_4R397 *1K/J_4
R398 *1K/J_4R398 *1K/J_4

CRT_HSYNC [18]
CRT_VSYNC [18]

R415

R415

R413

R413

150/F_4

150/F_4

150/F_4

150/F_4

+3V

T51T51
T52T52

INT_LVDS_PWM [18]

2

+3V

CRT_R [18]
CRT_G [18]
CRT_B [18]

LAYOUT NOTE: PLACE THESE 3 RESISTORS
CLOSE TO PIN

<20110110> DPL_REFSSCCLK is used to drive internal

DREFSSCLK [2]
DREFSSCLK# [2]

DREFCLK [2]
DREFCLK# [2]

registers and logics of the display interface and therefore
needs to be present at all times.

<20100818_Jerry> If you implement XDP, you need the PU 2.2K

<20110610> Remove PU resistor for Intel update.
<20110630> Stuff R38/ R39 PU resistor. Intel will fixed EDID issue by VGA driver and vbios

+3V

+3V

R39 2.2K/J_4R39 2.2K/J_4
R38 2.2K/J_4R38 2.2K/J_4

<EMI>

*220P/50V_4

*220P/50V_4

R58 2.2K/J_4R58 2.2K/J_4
R56 2.2K/J_4R56 2.2K/J_4

<EMI>

C58

C58

*220P/50V_4

*220P/50V_4

C50

C50

LCD_CLK
LCD_DATA

*220P/50V_4

*220P/50V_4

CRT_DDC_SDA
CRT_DDC_SCL

*220P/50V_4

*220P/50V_4

1

05

C51

C51

C65

C65

LCD Panel Power (LDS)

+1.5V

R409

R409
0/J_4

0/J_4

27MHz/+-20PPM_20PF

27MHz/+-20PPM_20PF

C334

C334

DMI_TXP0[10]
DMI_TXN0[10]
DMI_TXP1[10]
DMI_TXN1[10]
DMI_TXP2[10]
DMI_TXN2[10]
DMI_TXP3[10]
DMI_TXN3[10]

CLK_PCIE_DMIP[2]
CLK_PCIE_DMIN[2]

R450 *0/short_4R450 *0/short_4

Y3

Y3

R385 1M/J_4R385 1M/J_4

33P/50V_4

33P/50V_4

C354

C354

1U/10V_4

1U/10V_4

R410

R410
0/J_4

0/J_4

2nd source: BG627000289 (ZYG)

C335

C335

+3V

C329 .1U/10V_4C329 .1U/10V_4

U20

R360

R360
100K_4

100K_4

U20

2
1

3 5

R355 *0/J_4R355 *0/J_4

TC7SH08FU

TC7SH08FU

4

INT_LVDS_DIGON [18]

DMI_REF1.5V

For HDMI deep color mode support

ECPWROK

INT_LVDS_DIGON_Q

B B

LCD Panel Backlight (LDS)

(HDM)

+3V

C48 .1U/10V_4C48 .1U/10V_4

U2

R53

R53
100K_4

100K_4

5

U2

2
1

3 5

R51 *0/J_4R51 *0/J_4

TC7SH08FU

TC7SH08FU

4

INT_LVDS_BLON [18]

ECPWROK[8,13,16,27]

A A

ECPWROK
LBKLT_EN

<20100727_Sam> Customer must to use 27MHz due to
accuracy concerns(<1000ppm) from Intel silicon
perspective.

LAYOUT NOTE: PLACE CLOSE TO PIN

DREFCLK_R1
DREFCLK#_R1

33P/50V_4

33P/50V_4

4

U24A

U24A

L3

DMI_RXP0

L2

DMI_RXN0

M3

DMI_RXP1

M2

DMI_RXN1

N2

DMI_RXP2

N1

DMI_RXN2

P2

DMI_RXP3

P3

DMI_RXN3

N9

DMI_REFCLKP

N8

DMI_REFCLKN

T2

DMI_REF1P5

CDV_22MM_REV1P10

CDV_22MM_REV1P10

CEDARVIEW

CEDARVIEW

REV = 1.10

REV = 1.10

DMI

DMI

1 OF 6

1 OF 6

<20101109> Add C354 to follow CRB v0.7

THERMAL SENSOR (THM)

<20110414> Unstuff Thermal Sensor and related circuit.

THERM_ALERT#[6,13,27]

3

K6

DMI_TXP0

K5

DMI_TXN0

L5

DMI_TXP1

L6

DMI_TXN1

L9

DMI_TXP2

L8

DMI_TXN2

N5

DMI_TXP3

N6

DMI_TXN3

R8

RSVD_TP_R8

R7

RSVD_TP_R7

T1

DMI_RCOMP

ALERT# Pull Up Value

2K ohm

7.5K ohm

10.5K ohm
14K ohm

18.7K ohm

DMI_REF1.5V_R

+3V

R115

R115

*

*2K/F_4

*2K/F_4

R111 *0/J_4R111 *0/J_4

*

Alert temperature point

75 degree

90 degree
100 degree
105 degree
110 degree

DMI_RXP0 [10]
DMI_RXN0 [10]
DMI_RXP1 [10]
DMI_RXN1 [10]
DMI_RXP2 [10]
DMI_RXN2 [10]
DMI_RXP3 [10]
DMI_RXN3 [10]

7.5K/F_4

7.5K/F_4

R445

R445

THERMAL_SCL THERMAL_SDA

THERM_ALERT#_1

DMI_REF1.5V

<20101109> Add DMI_REF1.5V to follow CRB v0.7

U5

*

1

SCL

2

GND

3

ALERT#

*NCT7717UU5*NCT7717U

2

*

R119 *0/J_4R119 *0/J_4

C155

C155
*0.1U/16V_4

*0.1U/16V_4

*

**

+3V

C156

C156
*4.7U/6.3V_6

*4.7U/6.3V_6

C148

C148

*0.1U/16V_4

*0.1U/16V_4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Cedarview DMI/Display

Cedarview DMI/Display

Cedarview DMI/Display

Wednesday, November 02, 2011

Wednesday, November 02, 2011

Wednesday, November 02, 2011

5

SDA

4

VDD

2ND_MBCLK [27]

2ND_MBDATA [27]

C154

C154

*0.1U/16V_4

*0.1U/16V_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

ZE7

ZE7

ZE7

1

1B

1B

1B

405

405

405

R114 *0/J_4R114 *0/J_4

<20110414> Pull up at EC side

5

Cedar View (CPU)

R74 2.2K/J_4R74 2.2K/J_4
R71 2.2K/J_4R71 2.2K/J_4

D D

<20100811_Jerry>can be NC but please reserve 2.2K pull
low as CRB. can be removed later depends on CRB
validation status.

<20101019>Stuff R74 R71 for using 0xFFFE_0000
as Punit microbase address

HV_GPIO_RCOMP
MV_GPIO_RCOMP

R72

R72

R69

R69

49.9/F_4

49.9/F_4

49.9/F_4

49.9/F_4

C C

XDP_TCLK

T45T45

XDP_TDI

T46T46

XDP_TDO

T47T47

XDP_TMS

T48T48

XDP_TRST#

T49T49

+1.05V

XDP_TDI

R449 51/J_4R449 51/J_4

XDP_TDO

R459 51/J_4R459 51/J_4

XDP_TMS

R470 51/J_4R470 51/J_4

XDP_TCLK

R446 51/J_4R446 51/J_4

XDP_TRST#

R448 51/J_4R448 51/J_4

L26

RSVD_L26

L27

RSVD_L27

K28

RSVD_K28

K25

RSVD_K25

J28

RSVD_J28

K26

RSVD_K26

K27

RSVD_K27

H27

RSVD_H27

K30

RSVD_K30

L29

RSVD_L29

L30

RSVD_L30

K29

RSVD_K29

J31

RSVD_J31

H30

RSVD_H30

K24

HV_GPIO_RCOMP

K23

MV_GPIO_RCOMP

C25

TCLK

C24

TDI

B25

TDO

D24

TMS

B24

TRST#

R5

RSVD_R5

R6

RSVD_R6

W25

RSVD_W25

W26

RSVD_W26

N24

RSVD_N24

N25

RSVD_N25

U24D

U24D

4

3

2

1

06

CEDARVIEW

CEDARVIEW

REV = 1.10

REV = 1.10

B18

SMI#

C22

NMI/LINT1

RSVD_C18

ICH

ICH

CPU

CPU

STPCLK#

DPRSTP#

DPLSLP#
CPUSLP#

INIT#

INTR/LINT0

THERMTRIP#

RSVD_L11

PBE#

PROCHOT#
PWRGOOD

RESET#

DBR#

PRDY#
PREQ#

HPLL_REFCLK_P

HPLL_REFCLK

RSVD_E19
RSVD_F19

SVID_ALERT#

SVID_CLK

SVID_DATA

RSVD_K21

RSVD_L22
RSVD_L24

R386 *0/short_4R386 *0/short_4

C18
D22

C21
B21
B22

A23
D20

H_THRMTRIP#

B20
L11

H_FERR#_R

C20

H_PROCHOT_R#

A19

H_PWRGD

D23

PLTRST#

G30
E30

XDP_DBRESET_N_CDV

H_BPM4_PRDY#

H29

H_BPM5_PREQ#

G29

CLK_MCH_BCLK

J19

CLK_MCH_BCLK#

K19
E19

F19

B16
D18
C16

K21
L22
L24

R400 *0/short_4R400 *0/short_4

R399

R399
75/J_4

75/J_4

H_SMI# [11]
H_NMI [11]
H_A20M# [11]
H_STPCLK# [11]

ICH_DPRSTP# [13]
H_DPSLP# [13]
CPUSLP# [11]

H_INIT# [11]
H_INTR [11]

H_PWRGD [13,16]
PLTRST# [13,16,22,25,26,27]

R33 1K/J_4R33 1K/J_4

T43T43
T44T44

CLK_MCH_BCLK [2]
CLK_MCH_BCLK# [2]

VR_SVID_ALERT# [31]
VR_SVID_CLK [31]

H_FERR# [11]

+3V

R416

R416
110/F_4

110/F_4

+1.05V

<20100811_Jerry>please use 100+/-5% as in PDG.

R381

R381
100/J_4

100/J_4

R377 *0/short_4R377 *0/short_4

Host CLK 100/133 MHz

+1.05V

VR_SVID_DATA [31]

H_PROCHOT# [31]

H_BPM4_PRDY#
H_BPM5_PREQ#

.1U/10V_4

.1U/10V_4

R442 *51/J_4R442 *51/J_4

R443 51/J_4R443 51/J_4

C268

C268

+1.8V

CDV_22MM_REV1P10

CDV_22MM_REV1P10

B B

125 Degree Protection(CPU)

+1.05V

3

Q2
2N7002KQ22N7002K

2

1

2

Shutdown System Power Immediately

Q1

Q1

1 3

METR3904-G

METR3904-G

SYS_SHDN# [30,35]

To System Power

PM_THRMTRIP# [11]

To Tiger Point

H_THRMTRIP#

5

IMVP_PWRGD

R16 *0/short_4R16 *0/short_4

R17

R17
1K/J_4

1K/J_4

IMVP_PWRGD[27,31]

From CPU

A A

4 OF 6

4 OF 6

CPU FAN CTRL(THM)

+5V

+3V

R512

R512

R505 *0/short_6R505 *0/short_6

10K/J_4

10K/J_4

FANSIG [27]

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Wednesday, November 02, 2011

Date: Sheet of

Wednesday, November 02, 2011

Date: Sheet of

2

Wednesday, November 02, 2011

C365 0.1U/16V_4C365 0.1U/16V_4

CN18

+5V_FANVCC

FANSIG
FAN_PWM_CNCPUFAN#

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

Cedarview Miscellaneous

Cedarview Miscellaneous

Cedarview Miscellaneous

CN18

345
2
1

FAN CONN

FAN CONN

1

6

ZE7

ZE7

ZE7

1B

1B

1B

406

406

406

THERM_ALERT#[5,13,27]

CPUFAN#[27]

EC PWM SIGNAL

R514 *0/J_4R514 *0/J_4

+3V

1 3

Q43 METR3904-GQ43 METR3904-G

2

R509

R509
10K/J_4

10K/J_4

+5V

R507

R507
10K/J_4

10K/J_4

For EMI

FAN_PWM_CN

4

3

FANSIG

C368

C368
*220P/50V_6

*220P/50V_6

C372

C372
*220P/50V_6

*220P/50V_6

1

Cedar View (CPU)

LAYOUT NOTE: place close to VCCADDR pin

C352

C352
*22U/6.3V_8

C129

C129

C149

C149

2.2U/6.3V_6

2.2U/6.3V_6

R77 *0/short_6R77 *0/short_6

+1.8V

*22U/6.3V_8

C128

C128

C130

C130

1U/10V_4

1U/10V_4

1U/10V_4

1U/10V_4

C153

C153

2.2U/6.3V_6

2.2U/6.3V_6

2.2U/6.3V_6

2.2U/6.3V_6

+1.05V

C83

C83

1U/10V_4

1U/10V_4

+3.3V_PRIME

R384 0.2A/600ohm_6R384 0.2A/600ohm_6

R47 *0/short_6R47 *0/short_6

R94 *0/short_6R94 *0/ short_6

A A

<20101126_Colt> Please follow PDG to
placehold the 0805 capacitor

VCCDDRAON_1.5[8]

R134 *0/short_8R134 *0/short_8

+1.5VSUS

*1U/10V_4

*1U/10V_4

For Deep Standby

B B

R31 *0/short_6R 31 *0/short_6

+1.5V

R46 *0/short_6R 46 *0/short_6

+1.8V

<20100830> Add Farrite bead for VCCDAC low pass filter

<20101125_Colt> Please follow PDG, we will doing BOM
stuff changing in next version CRB

C C

+1.05V

C82 *0.1U/10V_4C82 *0.1U/10V_4

C93 1U/10V_4C93 1U/10V_4

+3.3V_PRIME

V_1.05_CORE_RSENSE VCCDMPL_1.05

C120

C120
1U/10V_4

1U/10V_4

C92 *1U/10V_4C92 *1U/10V_4
C116 1U/10V_4C 116 1U/10V_4

VCCDDRAON_1.5

C152

C152

C146

C146

2.2U/6.3V_6

2.2U/6.3V_6

R419 *0/short_6R419 *0/short_6

R55 *0/short_6R55 *0/short_6

C336 22U/6.3V_8C336 22U/6.3V_8
C337 *47U/6.3V_8C337 *47U/6.3V_8

C54 2.2U/6.3V_6C54 2.2U/6.3V_6

*2.2U/6.3V_4

*2.2U/6.3V_4

2

C141

C141
*1U/10V_4

*1U/10V_4

R54 *0/J_6R54 *0/J_6

C59 2.2U/6.3V_6C59 2.2U/6.3V_6

C91 1U/10V_4C91 1U/10V_4

C139

C139

V_1.05_CORE_RSENSE

V_1.05_CORE_EAST

V_1.05_CORE_RSENSE
V_1.05_VCCDDR

V_1.05_VCCDDR

VCCCKDDR_VSM

VCCADP_1.05

C56 1U/10V_4C56 1U/10V_4

VCCADP0_1.5
VCCADP1_1.5

V_1.05_CORE_EAST
VCCAGPIO_1.5
VCCAGPIO_1.8

VCCAGPIO_3.3

VCCADAC_1.8
VCCALVDS_1.8

VCCDLVDS_1.8

V_1.05_CORE_EAST

VCCSFRMPL_1.5

VCCPLLCPU0_1.05
VCCPLLCPU1_1.05

VCCAHPLL_1.05

AA14
AA16

AH14
AH19
AK23

AG31

W16
W18

N30
N31

V4

W8
W9

W11
W13

AJ6

AK6

AK5
AL11
AL16
AL21

B5
C6
D6

K17

L18
L19

L16

N18

D30

D31

B13

H5

J1

L21

B29

A30
AA18

AA11

B27

C29

B30

B26

U24E

U24E

VCCADDR_1
VCCADDR_2
VCCADDR_3
VCCADDR_4

VCCRAMXXX_1
VCCRAMXXX_2
VCCRAMXXX_3

VCCACKDDR_1
VCCACKDDR_2

VCCADLLDDR_1
VCCADLLDDR_2

VCCCKDDR_1
VCCCKDDR_2

V_SM_1
V_SM_2
V_SM_3
V_SM_4
V_SM_5
V_SM_6
V_SM_7
V_SM_8

VCCADP_1
VCCADP_2
VCCADP_3

VCCADP0_SFR
VCCADP1_SFR

VCCAGPIO_LV
VCCAGPIO_REF
VCCAGPIO_DIO

VCCAGPIO_1
VCCAGPIO_2

VCCADAC
VCCALVDS

VCCDLVDS

VCCDIO
VCCAZILAON_1

VCCAZILAON_2
VCCSFRMPL

VCCDMPL
VCCPLLCPU0

VCCPLLCPU1_1
VCCPLLCPU1_2

VCCAHPLL

3

CEDARVIEW

CEDARVIEW

REV = 1.10

REV = 1.10

DDR

DDR

CPU

CPU

POWER

POWER

DMI

DMI

PLL

PLL

4

VCC_CPU_01
VCC_CPU_02
VCC_CPU_03
VCC_CPU_04
VCC_CPU_05
VCC_CPU_06
VCC_CPU_07
VCC_CPU_08
VCC_CPU_09
VCC_CPU_10
VCC_CPU_11
VCC_CPU_12
VCC_CPU_13
VCC_CPU_14
VCC_CPU_15
VCC_CPU_16
VCC_CPU_17
VCC_CPU_18
VCC_CPU_19
VCC_CPU_20
VCC_CPU_21
VCC_CPU_22
VCC_CPU_23
VCC_CPU_24
VCC_CPU_25
VCC_CPU_26
VCC_CPU_27
VCC_CPU_28
VCC_CPU_29

VCC_GFX_01
VCC_GFX_02
VCC_GFX_03
VCC_GFX_04
VCC_GFX_05
VCC_GFX_06
VCC_GFX_07
VCC_GFX_08
VCC_GFX_09
VCC_GFX_10
VCC_GFX_11

VCCADMI_1
VCCADMI_2
VCCADMI_3

VCCADMI_PLLSFR

VCCFHV_1
VCCFHV_2

VCCFHV_3

VCC_CPUSENSE
VSS_CPUSENSE

VCC_GFXSENSE

VSS_GFXSENSE

VCCTHRM_1
VCCTHRM_2

1.1V (0.75V~1.18V)

5.95A

+VCC_CORE

P18

1U/10V_4

1U/10V_4

P19
P21
P28
P29
P30
R22
R23
R24
R25
R26
R27
T19
T21
T29
T30
T31
U22
U23
U24
U25
U26
U27
V18
V19
V21
V28
V29
V30

N11
N13
P11
P13
R10
R9
T11
T13
U10
V11
V13

B4
C5
A4
K4

V16
T16

V14
M28

M30
U8

U7
N16

K2

C100

C100

C126

C126

*1U/10V_4

*1U/10V_4

1U/10V_4

1U/10V_4

1.05V (0.76V~1.05V)

1.98A

VCCGFX

C95

C95

C98

C98

1U/10V_4

1U/10V_4

1U/10V_4

1U/10V_4

C60 1U/10V_4C60 1U/10V_4

VCCADMI_1.05

C88 1U/10V_4C88 1U/10V_4

VCCADMI_1.5
V_1.05_CORE_RSENSEVCCAZILAON_3.3

CPUVCC_SENSE [31]
CPUVSS_SENSE [31]

GTVCC_SENSE [31]
GTVSS_SENSE [31]

V_1.8_RSENSE

C350

C350
*1U/10V_4

*1U/10V_4

5

22U/6.3V_8

22U/6.3V_8

*1U/10V_4

*1U/10V_4

C125

C125

C118

C118

C105

C105

C101

C101

C106

C106

*1U/10V_4

*1U/10V_4

22U/6.3V_8

22U/6.3V_8

LAYOUT NOTE: PLACE
ONE 1U CAP ON BOT LAYER

LAYOUT NOTE: PLACE
TWO CAPS ON BOT LAYER

C117

C117

C94

C94

1U/10V_4

1U/10V_4

1U/10V_4

1U/10V_4

R437 *0/short_6R437 *0/short_6

+1.8V

22U/6.3V_8

22U/6.3V_8

C112

C112

C103

C103

22U/6.3V_8

22U/6.3V_8

C115

C115
22U/6.3V_8

22U/6.3V_8

R423 *0/short_6R423 *0/short_6

R456 *0/short_6R456 *0/short_6

+1.05V

+1.5V

VCCPLLCPU0_1.05 VCCPLLCPU1_1.05

R40 *0/J_6R40 *0/J_6

6

Cedar View PLL Power

Default stuff 1.5VPLL, Intel verify whether

1.05VPLL is ok or not

VCCSFRMPL_1.5

VCCADP0_1.5

VCCADP1_1.5

7

C134

C134
1U/10V_4

1U/10V_4

C52

C52
1U/10V_4

1U/10V_4

C53

C53
1U/10V_4

1U/10V_4

R112 *1.5VPLL@0/short_6R112 *1.5VPLL@0/short_6

L18

L18
*1.05VPLL@10uH/100mA_8

*1.05VPLL@10uH/100mA_8
C142

C142
*10U/6.3V_8

*10U/6.3V_8

R29 *1.5VPLL@0/short_6R29 *1.5VPLL@0/short_6

L3

L3
*1.05VPLL@10uH/100mA_8

*1.05VPLL@10uH/100mA_8
C28

C28
*10U/6.3V_8

*10U/6.3V_8

R36 *1.5VPLL@0/short_6R36 *1.5VPLL@0/short_6

L4

L4
*1.05VPLL@10uH/100mA_8

*1.05VPLL@10uH/100mA_8
C29

C29
*10U/6.3V_8

*10U/6.3V_8

8

07

+1.5V

+1.05V

+1.5V

+1.05V

+1.5V

+1.05V

Cedar View LVDS Power

BOM structure

w/LVDS: stuff R436/ C345/ L38/ C75
w/EDP: unstuff R436/ C75
change L38/ C345 to 0ohm

VCCDLVDS_1.8

VCCALVDS_1.8

C75

C75

LVDS@4.7u/6.3V_6

LVDS@4.7u/6.3V_6

L38BOM@0.1uH/300mA_6 L38BOM@0.1uH/300mA_6

C345

C345

BOM@1U/10V_4

BOM@1U/10V_4

R436 LVDS@0/J_6R436 LVDS@0/J_6

+1.8V

LAYOUT NOTE: OVERLAP RESISTOR AND INDUCTOR

2nd source: CV01001MN32

VCCPLLCPU0_1.05

C31

C31

C40

4.7u/6.3V_6

5 OF 6

CDV_22MM_REV1P10

CDV_22MM_REV1P10

D D

1

2

3

5 OF 6

<20101125_Colt> Please follow PDG, we will doing BOM
stuff changing in next version CRB

4

5

4.7u/6.3V_6

VCCPLLCPU1_1.05

4.7u/6.3V_6

4.7u/6.3V_6

VCCAHPLL_1.05

4.7u/6.3V_6

4.7u/6.3V_6

C40

1U/10V_4

1U/10V_4

C45

C45

C46

C46

1U/10V_4

1U/10V_4

C32

C32

C49

C49

1U/10V_4

1U/10V_4

6

+1.05V

L610uH/100mA_8 L610uH/100mA_8

+1.05V

L1110uH/100mA_8 L1110uH/100mA_8

+1.05V

L1010uH/100mA_8 L1010uH/100mA_8

VCCCKDDR_VSM

C359

C359

C362

10U/6.3V_8

10U/6.3V_8

V_1.05_VCCDDR

V_1.05_CORE_RSENSE

C362

<2010/9/27>Reserve 0805 footprint for farrite bead
CV01001MN16 due to co-layout issue.

R89 *0/short_6R89 *0/short_6

R440 *0/short_6R440 *0/short_6

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Wednesday, November 02, 2011

Date: Sheet of

Wednesday, November 02, 2011

Date: Sheet of

7

Wednesday, November 02, 2011

1U/6.3V_4

1U/6.3V_4

<20101125_Colt> Please follow PDG, we will doing BOM
stuff changing in next version CRB

R489 *0/short_8R489 *0/short_8

+1.05V

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

CedarView Power

CedarView Power

CedarView Power

+1.5VSUS

ZE7

ZE7

ZE7

8

1B

1B

1B

407

407

407

5

Cedar View (CPU)

D D

<Layout note>
PLACE RESISTORS AND CAP CLOSE TO CPU DDR_VREF PIN

VCCDDRAON_1.5[7]

+SMDDR_VREF

C C

<20100810_Jerry> Please refer to Cedar Trail CPET HW section(#454349),
it is to implement Deep Standby. And please waiting the whitepaper for implementation detail.

<20100817_Jerry>DELAY_VR_PWRGOOD on CDV should be connected to the XDP_PWRGOOD
because the SV folks expressed a preference on using PWROK over PWRGOOD for CDV.
This has changed from PNV to CDV.

B B

R482 1K/F_4R482 1K/F_4

R492 *0/J_4R492 *0/J_4

<20110520>Change 12.1K to 121ohm to follow CRBv1.5

R483 *0/short_4R483 *0/short_4

R493

R493
1K/F_4

1K/F_4

ECPWROK[5,13,16,27]

<20110520>Change 10K to 100ohm to follow CRBv1.5

<20100811_Jerry> R485 please follow CRB schematic. (274ohm)

C360

C360

0.1U/16V_4

0.1U/16V_4

R99 121/F_4R99 121/F_4

DRAM Reset (CPU)

4

M_A_A[15:0][4]

M_A_WE#[4]
M_A_CAS#[4]
M_A_RAS#[4]

M_A_BS0[4]
M_A_BS1[4]
M_A_BS2[4]

M_CS#2[4]
M_CS#3[4]

M_CKE2[4]
M_CKE3[4]

M_ODT2[4]
M_ODT3[4]

M_CLK2[4]
M_CLK2#[4]
M_CLK3[4]
M_CLK3#[4]

*

CLK_DDR3_REFCLK[2]
CLK_DDR3_REFCLK#[2]

T53T53

R98

R98
100/F_4

100/F_4

274/F_4

274/F_4

R485

R485

R488

R488

22.6/F_4

22.6/F_4

M_A_DM[7:0][4]

3

DDR3_DRAMRST#_R

DDRAM_PWROK

DELAY_VR_PWRGD_CDV

C361

C361

*0.01U/25V_4

*0.01U/25V_4

M_A_WE#
M_A_CAS#
M_A_RAS#

M_A_BS0
M_A_BS1
M_A_BS2

M_CS#2
M_CS#3

M_CKE2
M_CKE3

M_ODT2
M_ODT3

M_CLK2
M_CLK2#
M_CLK3
M_CLK3#

DDR_VREF

M_ODTPU
M_CMDPU
M_DQPU

R484

R484

33.2/F_4

33.2/F_4

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

U24B

U24B

AK14

DDR3_MA0

AK16

DDR3_MA1

AJ14

DDR3_MA2

AJ16

DDR3_MA3

AK18

DDR3_MA4

AH18

DDR3_MA5

AJ18

DDR3_MA6

AK20

DDR3_MA7

AJ20

DDR3_MA8

AH20

DDR3_MA9

AJ12

DDR3_MA10

AK21

DDR3_MA11

AJ21

DDR3_MA12

AJ8

DDR3_MA13

AH22

DDR3_MA14

AJ22

DDR3_MA15

AH10

DDR3_W E#

AJ10

DDR3_CAS#

AJ11

DDR3_RAS#

AK12

DDR3_BS0

AH13

DDR3_BS1

AK22

DDR3_BS2

AH12

DDR3_CS#0

AH8

DDR3_CS#1

AK11

DDR3_CS#2

AK8

DDR3_CS#3

AH23

DDR3_CKE0

AJ24

DDR3_CKE1

AK24

DDR3_CKE2

AH24

DDR3_CKE3

AK10

DDR3_ODT0

AK7

DDR3_ODT1

AL9

DDR3_ODT2

AJ7

DDR3_ODT3

AG15

DDR3_CK0

AF15

DDR3_CK#0

AF17

DDR3_CK1

AG17

DDR3_CK#1

AD17

DDR3_CK2

AC17

DDR3_CK#2

AC15

DDR3_CK3

AD15

DDR3_CK#3

AK25

DDR3_DRAMRST#

AJ27

DDR3_VREF

AL28

DDR3_VREF_NCTF

AC19

DDR3_REFP

AB19

DDR3_REFN

AA5

DDR3_DRAM_PWROK

W7

DDR3_VCCA_PWROK

AJ26

DDR3_ODTPU

AJ25

DDR3_CMDPU

AK27

DDR3_DQPU

AB11

RSVD_TP_AB11

AB13

RSVD_TP_AB13

AF19

RSVD_TP_AF19

AG19

RSVD_TP_AG19

Y28

DDR3_DM0

AB26

DDR3_DM1

AE30

DDR3_DM2

AB21

DDR3_DM3

AG11

DDR3_DM4

AG2

DDR3_DM5

AB8

DDR3_DM6

AA3

DDR3_DM7

CDV_22MM_REV1P10

CDV_22MM_REV1P10

DDR3

DDR3

CEDARVIEW

CEDARVIEW

1.5V

1.5V

REV = 1.10

REV = 1.10

2 OF 6

2 OF 6

2

DDR3_DQ0
DDR3_DQ1
DDR3_DQ2
DDR3_DQ3
DDR3_DQ4
DDR3_DQ5
DDR3_DQ6
DDR3_DQ7
DDR3_DQ8

DDR3_DQ9
DDR3_DQ10
DDR3_DQ11
DDR3_DQ12
DDR3_DQ13
DDR3_DQ14
DDR3_DQ15
DDR3_DQ16
DDR3_DQ17
DDR3_DQ18
DDR3_DQ19
DDR3_DQ20
DDR3_DQ21
DDR3_DQ22
DDR3_DQ23
DDR3_DQ24
DDR3_DQ25
DDR3_DQ26
DDR3_DQ27
DDR3_DQ28
DDR3_DQ29
DDR3_DQ30
DDR3_DQ31
DDR3_DQ32
DDR3_DQ33
DDR3_DQ34
DDR3_DQ35
DDR3_DQ36
DDR3_DQ37
DDR3_DQ38
DDR3_DQ39
DDR3_DQ40
DDR3_DQ41
DDR3_DQ42
DDR3_DQ43
DDR3_DQ44
DDR3_DQ45
DDR3_DQ46
DDR3_DQ47
DDR3_DQ48
DDR3_DQ49
DDR3_DQ50
DDR3_DQ51
DDR3_DQ52
DDR3_DQ53
DDR3_DQ54
DDR3_DQ55
DDR3_DQ56
DDR3_DQ57
DDR3_DQ58
DDR3_DQ59
DDR3_DQ60
DDR3_DQ61
DDR3_DQ62
DDR3_DQ63

DDR3_DQS0
DDR3_DQS1
DDR3_DQS2
DDR3_DQS3
DDR3_DQS4
DDR3_DQS5
DDR3_DQS6
DDR3_DQS7

DDR3_DQS#0
DDR3_DQS#1
DDR3_DQS#2
DDR3_DQS#3
DDR3_DQS#4
DDR3_DQS#5
DDR3_DQS#6
DDR3_DQS#7

Y30
Y29
AC30
AC31
W31
W28
AB28
AB30
AA24
AA22
AE27
AE26
AB27
AA25
AD25
AD27
AD29
AE29
AJ30
AK29
AD28
AD30
AG30
AJ29
AE24
AG24
AD22
AC21
AG27
AG25
AG21
AE21
AD13
AD11
AG8
AG7
AG13
AE13
AD10
AF8
AH2
AG3
AD2
AD3
AH4
AK3
AE2
AD4
AD7
AD6
AA6
AB5
AE8
AE5
AB9
AA8
AB2
AB4
W4
V3
AC2
AB3
Y2
W1

AA30
AB24
AF30
AE22
AG10
AF4
AB6
Y3

AA31
AB25
AF29
AF22
AF10
AF3
AB7
AA2

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7

M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

1

M_A_DQ[63:0] [4]

M_A_DQS[7:0] [4]

M_A_DQS#[7:0] [4]

08

<20110520>Need to confirm with Intel if
we need to add series 100ohm resistor

A A

DDR3_DRAMRST#[4]

R537 *0/short_4R537 *0/short_4

C159

C159

0.1U/16V_4

0.1U/16V_4

<20110727> Add C159 to suppress glitch

5

+1.5VSUS

DDR3_DRAMRST#_NS

<20110607>Keep original design first for DRAMRST#
<20110707_Nick> Please stuff 100K pull down

<20110607>Keep original design first for DRAMRST#
<20110707_Nick> Please un-stuff 1K pull up

R538

R538
*1K/F_4

*1K/F_4

R539 *0/short_4R539 *0/short_4

DDR3_DRAMRST#_R

R474

R474
100K/J_4

100K/J_4

4

<20110727>Connect DDRAM_PWROK between CDV and RT8207L to meet JEDEC timing spec

+1.5VSUS

VCCDDRAON_1.5

DDRAM_PWROK[27,32]

3

R100

R100
10K/J_4

10K/J_4

DDRAM_PWROK

R97

R97

C388

C388

*0/J_4

*0/J_4

*1U/10V_6

*1U/10V_6

<20110727> Reserve C388 for RC delay

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Wednesday, November 02, 2011

Date: Sheet of

Wednesday, November 02, 2011

Date: Sheet of

2

Wednesday, November 02, 2011

PROJECT :

CedarView DDR

CedarView DDR

CedarView DDR

ZE7

ZE7

ZE7

1B

1B

1B

408

408

1

408

1

Cedar View (CPU)

U24F

U24F

CEDARVIEW

CEDARVIEW

A11

VSS

A16

VSS

A21

VSS

REV = 1.10

REV = 1.10

A25

VSS

AA1

VSS

AA10

VSS

AA13

VSS

AA19

VSS

AA21

VSS

AA23

VSS

AA26

VSS

AA27

VSS

AA29

VSS

AA7

VSS

AA9

VSS

AB15

VSS

AB17

VSS

AB23

VSS

AB29

VSS

AC1

VSS

AC10

VSS

AC11

VSS

AC13

VSS

GND

AC22
AC28

AC4
AD19
AD21
AD24
AD26

AD5

AD8

AE1
AE10
AE11
AE15
AE17
AE19

AE3
AE31
AF11
AF13
AF21
AF24
AF28

AF7

AG22

AG5
AH26
AH28

AH6

AH9

AJ2
AJ3

AK13

A A

AK19
AK28

AL13
AL19
AL23
AL25

G11

G13

G15

G17

G19

G21

G31

AK9

AL7
B10
B14
B19
B23
C12
C26
C30

C7
D19
D28

D8

D9

E2

E5

E7
F24

F4

G1

G8
H13

GND

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSSA_CRTDAC
VSS
VSS
VSS
VSS
VSS

6 OF 6

6 OF 6

CDV_22MM_REV1P10

CDV_22MM_REV1P10

VSS_CDVDET

H19

VSS

H26

VSS

H28

VSS

H6

VSS

J10

VSS

J2

VSS

J21

VSS

J30

VSS

K11

VSS

K15

VSS

K3

VSS

K7

VSS

K8

VSS

K9

VSS

L1

VSS

L10

VSS

L13

VSS

L23

VSS

L25

VSS

L31

VSS

L7

VSS

M29

VSS

M4

VSS

N10

VSS

N14

VSS

N19

VSS

N21

VSS

N22

VSS

N23

VSS

N26

VSS

N27

VSS

N28

VSS

N4

VSS

N7

VSS

P14

VSS

P16

VSS

P4

VSS

T14

VSS

T18

VSS

T3

VSS

U5

VSS

U6

VSS

U9

VSS

V2

VSS

W10

VSS

W14

VSS

W19

VSS

W2

VSS

W21

VSS

W22

VSS

W23

VSS

W24

VSS

W27

VSS

W30

VSS

W5

VSS

W6

VSS

Y4

VSS

A27

VSS

A29

VSS

A3

VSS

AH1

VSS

AJ1

VSS

AJ31

VSS

AK1

VSS

AK2

VSS

AK30

VSS

AK31

VSS

AL2

VSS

AL29

VSS

AL3

VSS

AL30

VSS

AL5

VSS

B2

VSS

B3

VSS

B31

VSS

C1

VSS

C2

VSS

C31

VSS

E1

VSS

L14
D13

09

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Wednesday, November 02, 2011

Date: Sheet of

Wednesday, November 02, 2011

Date: Sheet of

1

Wednesday, November 02, 2011

PROJECT :

CedarView GND/ Deep Standby

CedarView GND/ Deep Standby

CedarView GND/ Deep Standby

ZE7

ZE7

ZE7

1B

1B

1B

409

409

409

1

Tiger Point (CLG)

TGP

U22B

U22B

DMI_RXN0[5]

DMI_RXP0[5]
DMI_TXN0[5]
DMI_TXP0[5]

DMI_RXN1[5]

DMI_RXP1[5]
DMI_TXN1[5]
DMI_TXP1[5]

DMI_RXN2[5]

DMI_RXP2[5]

<20110222> ES2 CPU DMI will
change from x4 to x2

LAN

WLAN

Card Reader

Media Processor

A A

DMI_TXN2[5]
DMI_TXP2[5]

DMI_RXN3[5]

DMI_RXP3[5]
DMI_TXN3[5]
DMI_TXP3[5]

PCIE_RXN0[22]

PCIE_RXP0[22]
PCIE_TXN0[22]
PCIE_TXP0[22]

PCIE_RXN1[25]

PCIE_RXP1[25]
PCIE_TXN1[25]
PCIE_TXP1[25]

PCIE_RXN2[26]

PCIE_RXP2[26]
PCIE_TXN2[26]
PCIE_TXP2[26]

PCIE_RXN3[25]

PCIE_RXP3[25]
PCIE_TXN3[25]
PCIE_TXP3[25]

C96 .1U/10V_4C96 .1U/10V_4
C90 .1U/10V_4C90 .1U/10V_4

C113 .1U/10V_4C113 .1U/10V_4
C104 .1U/10V_4C104 .1U/10V_4
R81 *0/J_4R81 *0/J_4
R80 *0/J_4R80 *0/J_4
C110 *.1U/10V_4C110 *.1U/10V_4
C122 *.1U/10V_4C122 *.1U/10V_4
R88 *0/J_4R88 *0/J_4
R86 *0/J_4R86 *0/J_4
C124 *.1U/10V_4C124 *.1U/10V_4
C132 *.1U/10V_4C132 *.1U/10V_4

C63 .1U/10V_4C63 .1U/10V_4
C71 .1U/10V_4C71 .1U/10V_4

C343 .1U/10V_4C343 .1U/10V_4
C344 .1U/10V_4C344 .1U/10V_4

C87 .1U/10V_4C87 .1U/10V_4
C80 .1U/10V_4C80 .1U/10V_4

C347 *.1U/10V_4C347 *.1U/10V_4
C346 *.1U/10V_4C346 *.1U/10V_4

DMI_TXN0_C
DMI_TXP0_C

DMI_TXN1_C
DMI_TXP1_C
DMI_RXN2_R
DMI_RXP2_R
DMI_TXN2_C
DMI_TXP2_C
DMI_RXN3_R
DMI_RXP3_R
DMI_TXN3_C
DMI_TXP3_C

PCIE_TXN0_C
PCIE_TXP0_C

PCIE_TXN1_C
PCIE_TXP1_C

PCIE_TXN2_C
PCIE_TXP2_C

PCIE_TXN3_C
PCIE_TXP3_C

R23
R24
P21
P20
T21
T20
T24
T25
T19
T18

U23

U24
V21
V20
V24
V23

K21
K22

J23

J24
M18
M19

K24
K25
L23
L24
L22

M21

P17

P18
N25
N24

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP

PERN1
PERP1
PETN1
PETP1
PERN2
PERP2
PETN2
PETP2
PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4

<20110630> No support PCI-e in 3G card

<Layout note>
Close to pin within 500mil

R425 24.9/F_4R425 24.9/F_4

+1.5V

CLK_PCIE_ICH#[2]
CLK_PCIE_ICH[2]

DMI_COMP

H24

J22

W23
W24

DMI_ZCOMP
DMI_IRCOMP

DMI_CLKN
DMI_CLKP

Tiger Point

Tiger Point

TGP

H7

USBP0N

H6

USBP0P

H3

USBP1N

H2

USBP1P

J2

USBP2N

J3

DMI

DMI

USB

USB

PCI-E

PCI-E

USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P

OC0#
OC1#
OC2#
OC3#

OC4#
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31

USBRBIAS

USBRBIAS#

CLK48

2

2

K6
K5
K1
K2
L2
L3
M6
M5
N1
N2

USBOC#R_1

D4

USBOC#R_1

C5

USBOC#

D3

USBOC#L_1

D2

USBOC#

E5

USBOC#

E6

USBOC#

C2

USBOC#

C3

G2
G3

CLKUSB_48

F4

USBRBIAS

USBP0- [21]
USBP0+ [21]
USBP1- [21]
USBP1+ [21]
USBP2- [18]
USBP2+ [18]
USBP3- [21]
USBP3+ [21]
USBP4- [25]
USBP4+ [25]
USBP5- [25]
USBP5+ [25]
USBP6- [19]
USBP6+ [19]
USBP7- [25]
USBP7+ [25]

R435 *0/short_4R435 *0/short_4

R427 *0/short_4R427 *0/short_4

<Layout note>
Close to pin within 200mil ; keep away from CLK/High speed signals

R438 22.6/F_4R438 22.6/F_4

EMI

R66

R66
*10/F_4

*10/F_4

C81

C81
*10P/50V_4

*10P/50V_4

SYSTEM (Right Down)
SYSTEM (Right Up)
CCD
SYSTEM (Left/ USB Charger)
SIM
3G
BT
WLAN

USBOC#R [21,27]

USBOC#L [21,27]

CLKUSB_48 [2]

USBOC#R_1
USBOC#L_1
USBOC#

CRB ties unused OC pins together with 1k ohm

R433 8.2K/J_4R433 8.2K/J_4
R429 8.2K/J_4R429 8.2K/J_4
R432 1K/F_4R432 1K/F_4

+3V_S5

10

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Wednesday, November 02, 2011

Date: Sheet of

Wednesday, November 02, 2011

Date: Sheet of

1

Wednesday, November 02, 2011

PROJECT :

Tiger Point DMI/PCIE/USB

Tiger Point DMI/PCIE/USB

Tiger Point DMI/PCIE/USB

ZE7

ZE7

ZE7

1B

1B

1B

4010

4010

4010

5

4

3

2

1

Tiger Point (CLG)

D D

TGP

U22C

U22C

R12

RSVD03

AE20

RSVD04

AD17

RSVD05

AC15

RSVD06

AD18

RSVD07

Y12

RSVD08

AA10

RSVD09

AA12

RSVD10

Y10

RSVD11

AD15

RSVD12

W10

RSVD13

V12

RSVD14

AE21

C C

B B

PCH_GPIO36

AE18
AD19

U12

AC17
AB13
AC13
AB15

Y14

AB16
AE24
AE23

AA14

V14

AD16
AB11
AB10
AD23

RSVD15
RSVD16
RSVD17
RSVD18

RSVD19
RSVD20
RSVD21
RSVD22
RSVD23

RSVD24
RSVD25
RSVD26

RSVD27
RSVD28

RSVD29
RSVD30
RSVD31
GPIO36

Tiger Point

Tiger Point

TGP

SATA0RXN
SATA0RXP
SATA0TXN

SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN

SATA1TXP

SATA

SATA

AE6
AD6
AC7
AD7
AE8
AD8
AD9
AC9

SATA_RXN0 [24]

SATA_RXP0 [24]
SATA_TXN0 [24]
SATA_TXP0 [24]

SATA HDD

<20100811_Jerry> Please follow CRB schematic (8.2K)

<20100811_Jerry>CDV doesn't support A20M,
please follow CRB to have a 1K pull up at the moment.

<20110516>Reserve 1K PU to +1.05V for C6-state
<20100813_Jerry> Update for the IGNNE#, please no

stuff the resister and follow CRB's circuit first.

<Layout note>
Close to pin within 500mil

R466 24.9/F_4R466 24.9/F_4

R533 0/J_4R533 0/J_4

R110 60.4/F_4R110 60.4/F_4

+1.05V

+1.05V

R104

R104

60.4/F_4

60.4/F_4

A20M#

IGNNE#

INIT#
INTR

FERR#

NMI

RCIN#

SERIRQ

SMI#

3

3

AD4
AC4

AD11
AC11
AD25

GA20

U16

H_A20M#

Y20

CPUSLP#_R

Y21

H_IGNNE#

Y18
AD21

H_INIT#

AC25

H_INTR

AB24

H_FERR#

Y22

H_NMI

T17

KBRST#

AC21

SERIRQ

AA16

H_SMI#

AA21

H_STPCLK#

V18

PM_THRMTRIP#

AA20

SATA_CLKN

SATA_CLKP

SATARBIAS#

SATARBIAS

SATALED#

A20GATE
CPUSLP#
INIT3_3V#

HOST

HOST

STPCLK#

THERMTRIP#

CLK_PCIE_SATA# [2]
CLK_PCIE_SATA [2]

SATARBIAS#
SATALED#

R102 10K/J_4R102 10K/J_4

SATALED# [24]

+3V

GA20 [27]
H_A20M# [6]

H_INIT# [6]
H_INTR [6]

H_NMI [6]
KBRST# [27]

SERIRQ [27]
H_SMI# [6]
H_STPCLK# [6]

<20110607_C-stage> Stuff 1K to follow CRB V1.5

<20100811_Jerry>you can follow PDG for the pull up

CPUSLP# [6]

<Layout note>
Close to pin

H_FERR# [6]

resistor value and tolerance requirement. CRB is more
strictly.

<20100811_Jerry>for Thermtrip#, please use 60 ohms+/-5% pull up.

<Layout note>
Close to pin within 1"

PM_THRMTRIP# [6]

<Layout note>
Close to pin within 200mil

Follow CRB

SERIRQ
KBRST#

GA20
PCH_GPIO36

H_A20M#
CPUSLP#_R

H_IGNNE#

VCC3_VCC3[12,13,14]

R96 4.7K/J_4R96 4.7K/J_4
R117 10K/J_4R117 10K/J_4

R95 8.2K/J_4R95 8.2K/J_4
R103 *10K/J_4R103 *10K/J_4

R109 1K/J_4R109 1K/J_4
R532 *1K/J_4R532 *1K/J_4

R105 1K/J_4R105 1K/J_4

11

+3V

+1.05V

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Wednesday, November 02, 2011

Date: Sheet of

Wednesday, November 02, 2011

Date: Sheet of

5

4

3

2

Wednesday, November 02, 2011

PROJECT :

Tiger Point Sata/Host

Tiger Point Sata/Host

Tiger Point Sata/Host

ZE7

ZE7

ZE7

1

1B

1B

1B

4011

4011

4011

5

4

3

2

1

Tiger Point (CLG)

TGP

PCI

PCI

TGP

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8

AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

C/BE0#
C/BE1#
C/BE2#
C/BE3#

1

1

B22
D18
C17
C18
B17
C19
B18
B19
D16
D15
A13
E14
H14
L14
J14
E10
C11
E12
B9
B13
L12
B8
A3
B5
A6
G12
H12
C8
D9
C7
C1
B1

H16
M15

<20101104> Reserve R389(PCH_GPIO22 PD) for 27MHz or 96MHz choosing, need vBIOS support

C13

Pull up --> for 27MHz

L16

Pull down --> for 96MHz

R30 *1K/J_4R30 *1K/J_4

R389 *8.2K/J_4R389 *8.2K/J_4

PCI_INTB#
PCI_IRDY#
PCI_INTG#
PCI_INTE#

PCI_LOCK#
PCI_INTD#
PCI_TRDY#
PCI_PERR#

PCI_DEVSEL#
PCI_FRAME#
PCI_REQ1#
PCI_REQ2#

PCI_INTA#
PCI_INTC#
PCI_INTF#
PCI_INTH#

PCI_STOP#
PCI_SERR#
EC_SCI#

RP3 8.2K_8P4RRP3 8.2K_8P4R

1
3
5
7

RP2 8.2K_8P4RRP2 8.2K_8P4R

1
3
5
7

RP1 8.2K_8P4RRP1 8.2K_8P4R

1
3
5
7

RP4 8.2K_8P4RRP4 8.2K_8P4R

1
3
5
7

R392 8.2K/J_4R392 8.2K/J_4
R391 8.2K/J_4R391 8.2K/J_4
R41 10K/J_4R41 10K/J_4

PCH_GPIO48
PCH_GPIO17

PCH_GPIO22

R35 *1K/J_4R35 *1K/J_4
R421 *1K/J_4R421 *1K/J_4R424 *1K/J_4R424 *1K/J_4

R388 8.2K/J_4R388 8.2K/J_4

2
4
6
8

2
4
6
8

2
4
6
8

2
4
6
8

+3V

+3V

+3V

+3V

+3V

+3V

+3V

U22A

U22A

A5

PCI CLK 33MHz

D D

PCLK_ICH[2]

EMI

R73

R73
*33/J_4

*33/J_4

C99

C99
*10P/50V_4

*10P/50V_4

C C

EC_SCI#[27]

T34T34

VCC3_VCC3[11,13,14]

B B

+3V

R70 10K/J_4R70 10K/J_4
R43 8.2K/J_4R43 8.2K/J_4

PCI_DEVSEL#

T32T32

PCI_IRDY#
PCI_SERR#

PCI_STOP#
PCI_LOCK#
PCI_TRDY#
PCI_PERR#
PCI_FRAME#

T13T13
T4T4

PCI_REQ1#
PCI_REQ2#

PCH_GPIO48
PCH_GPIO17
PCH_GPIO22
EC_SCI#

PCI_INTA#
PCI_INTB#
PCI_INTC#
PCI_INTD#
PCI_INTE#
PCI_INTF#
PCI_INTG#
PCI_INTH#

PCH_A16WP

PAR

B15

DEVSEL#

J12

PCICLK

A23

PCIRST#

B7

IRDY#

C22

PME#

B11

SERR#

F14

STOP#

A8

PLOCK#

A10

TRDY#

D10

PERR#

A16

FRAME#

A18

GNT1#

E16

GNT2#

G16

REQ1#

A20

REQ2#

G14

GPIO48/ STRAP1#

A2

GPIO17/ STRAP2#

C15

GPIO22

C9

GPIO1

B2

PIRQA#

D7

PIRQB#

B3

PIRQC#

H10

PIRQD#

E8

PIRQE#/GPIO2

D6

PIRQF#/GPIO3

H8

PIRQG#/GPIO4

F8

PIRQH#/GPIO5

D11

STRAP0#

K9

RSVD01

M13

RSVD02

Tiger Point

Tiger Point

12

<20090601(A1A)_Checklist Rev0.7>
Strap1#/strap2#: signals have weak
internal pull-ups

ICH Boot BIOS select

PCH_GPIO17
(INT PU)

0 1 SPI
1 0 PCI

1 1 LPC

A16 SWAP Override strap

PCH_A16WP

A A

(INT PU)

PCI_GNT#2

PCH_GPIO48
(INT PU)

Boot BIOS Location

(CURRENTLY USE)

Low = A16 swap override enabled
High = Default

Internal PU
Should not be PD

5

IRQ

PIRQA
PIRQB
PIRQC
PIRQD
PIRQE
PIRQF
PIRQG
PIRQH

4

USB UHCI Controller #1, #4

AC'97 Codec; option for SMBUS
USB UH Controller #3; SATA/IDE Native Mode
USB UHCI Controller #2
Internal LAN; Option for SCI, TCO, HPET#0,1,2
Option for SCI, TCO, HPET#0,1,2
Option for SCI, TCO, HPET#0,1,2
USB EHCI Controller; Option for SCI, TCO, HPET#0,1,2

Description

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Wednesday, November 02, 2011

Date: Sheet of

Wednesday, November 02, 2011

Date: Sheet of

3

Wednesday, November 02, 2011

2

PROJECT :

TigerPoint PCI

TigerPoint PCI

TigerPoint PCI

ZE7

ZE7

ZE7

1

1B

1B

1B

4012

4012

4012

5

Tiger Point (CLG)

ACZ_BITCLK_AUDIO_R

ACZ_BITCLK_CODEC[20]
ACZ_BITCLK_CPU[5]

R90 33/J_4R90 33/J_4
R93 90.9/F_4R93 90.9/F_4

2011/4/28 For EMI Sam request

D D

ACZ_RST#_CODEC[20]
ACZ_RST#_CPU[5]

ACZ_SDOUT_CODEC[20]
ACZ_SDOUT_CPU[5]

ACZ_SYNC_CODEC[20]
ACZ_SYNC_CPU[5]

<20110516_DGv1.5>
Change ACZ BITCLK/RST/SDOUT/SYNC to CPU RES from 33ohm to 90.9ohm

C C

R452 33/J_4R452 33/J_4
R454 90.9/F_4R454 90.9/F_4

R461 33/J_4R461 33/J_4

R451 33/J_4R451 33/J_4
R468 90.9/F_4R468 90.9/F_4

ACZ_BITCLK_AUDIO_R

C136

C136
*30P/50V_4

*30P/50V_4

ACZ_RST#_AUDIO_R

ACZ_RST#_AUDIO_R

ACZ_SDOUT_AUDIO_R

ACZ_SDOUT_AUDIO_R

ACZ_SYNC_AUDIO_R

ACZ_SYNC_AUDIO_R

<20090529(A1A)_Checklist Rev0.7>
If integrated LAN is not used
LAN_RST# tie it to GND.

C348 6P/50V_4C348 6P/50V_4

32.768KHz,+-20PPM

32.768KHz,+-20PPM

C349 6P/50V_4C349 6P/50V_4

4

3

2

1

13

+3V_S5

VCCRTC

Follow CRB

PCLK_SMB
PDAT_SMB
PM_BATLOW#
DNBSWON#
EC_SMI#
SYS_RST#
SMBALERT#
SMB_LINK_ALERT#
PCIE_WAKE#
SMLINK1
SMLINK0
ICH_RI#
PCH_GPIO14
PCH_GPIO15
PCH_GPIO9
PCH_GPIO8

PCH_GPIO12
PCH_GPIO13

MCH_SYNC#
CLKRUN#
BM_BUSY#
THERM_ALERT#

DMI_AC_ENABLE
TPT_PWROK
EC_RSMRST#

TGP

U22D

U22D

AA5

T18T18

LDRQ1#/GPIO23

T21T21

T36T36
T37T37
T14T14
T17T17
T16T16

RTC_X1
RTC_X2

V6

LAD0/FWH0

AA6

LAD1/FWH1

Y5

LAD2/FWH2

W8

LAD3/FWH3

Y8

LDRQ0#

Y4

LFRAME#

P6

HDA_BIT_CLK

U2

HDA_RST#

W2

HDA_SDI0

V2

HDA_SDIN1

P8

HDA_SDIN2

AA1

HDA_SDOUT

Y1

HDA_SYNC

AA3

CLK14

U3

EE_CS

AE2

EE_DIN

T6

EE_DOUT

V3

EE_SHCLK

T4

LAN_CLK

P7

LANR_STSYNC

B23

LAN_RST#

AA2

LAN_RXD0

AD1

LAN_RXD1

AC2

LAN_RXD2

W3

LAN_TXD0

T7

LAN_TXD1

U4

LAN_TXD2

W4

RTCX1

V5

RTCX2

T5

RTCRST#

E20

SMBALERT#/GPIO11

H18

SMBCLK

E23

SMBDATA

H21

SMLALERT#

F25

SMLINK0

F24

SMLINK1

R2

SPI_MISO

T1

SPI_MOSI

M8

SPI_CS#

P9

SPI_CLK

R4

SPI_ARB

Tiger Point

Tiger Point

LAD0[25,27]
LAD1[25,27]
LAD2[25,27]
LAD3[25,27]

LFRAME#[25,27]

ACZ_SDINO[5]
ACZ_SDIN1[20]

14M_ICH[2]

Y4

Y4

1 4

2 3

ACZ_BITCLK_AUDIO_R
ACZ_RST#_AUDIO_R

ACZ_SDOUT_AUDIO_R
ACZ_SYNC_AUDIO_R
14M_ICH

R434

R434
10M/J_4

10M/J_4

RTCRST#

SMBALERT#
PCLK_SMB
PDAT_SMB
SMB_LINK_ALERT#
SMLINK0
SMLINK1

TGP

CPUPWRGD/GPIO49

MISC

MISC

SUS_STAT#/LPCPD#

BM_BUSY#/GPIO0

DPRSLPVR

STP_PCI#

STP_CPU#

CLKRUN#

VRMPWRGD

MCH_SYNC#

PWRBTN#

SYS_RESET#

PLTRSTB

INTRUDER#

RSMRST#

INTVRMEN

SLP_S3#
SLP_S4#
SLP_S5#

BATLOW#

DPRSTP#

LPC AUDIO LAN

LPC AUDIO LAN

EPROM

EPROM

RTC SMB SPI

RTC SMB SPI

GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15

GPIO24
GPIO25
GPIO26
GPIO27
GPIO28

GPIO33
GPIO34
GPIO38
GPIO39

THRM#

SUSCLK

WAKE#

PWROK

SPKR

DPSLP#
RSVD31

RI#

BM_BUSY#

T15

PCH_GPIO6

W16

PCH_GPIO7

W14

PCH_GPIO8

K18

PCH_GPIO9

H19

EC_SMI#

M17

PCH_GPIO12

A24

PCH_GPIO13

C23

PCH_GPIO14

P5

PCH_GPIO15

E24

PM_DPRSLPVR

AB20
Y16
AB19

PCH_GPIO24

R3

DMI_AC_ENABLE

C24

PCH_GPIO26

D19

PCH_GPIO27

D20

PCH_GPIO28

F22

CLKRUN#

AC19

PCH_GPIO33

U14

BOARDID0

AC1

BOARDID1

AC23

BOARDID2

AC24

H_PWRGD

AB22

THERM_ALERT#

AB17

HWPG

V16

MCH_SYNC#

AC18

DNBSWON#

E21

ICH_RI#

H23
G22

SUSCLK

D22

SYS_RST#

G18

PLT_RST#

G23

PCIE_WAKE#

C25

SM_INTRUDER#

T8

TPT_PWROK

U10

EC_RSMRST#

AC3

ICH_INTVRMEN

AD3
J16

SUSB#

H20

SUSC#

E25
F21

PM_BATLOW#

B25

ICH_DPRSTP_R#

AB23

H_DPSLP#

AA18
F20

T20T20
T19T19

EC_SMI# [27]

T38T38

PM_STPPCI# [2]
PM_STPCPU# [2]

T35T35
T8T8

T10T10
T6T6

CLKRUN# [27]

T15T15R472 90.9/F_4R472 90.9/F_4

H_PWRGD [6,16]

THERM_ALERT# [5,6,27]
HWPG [2,16,27]

DNBSWON# [16,27]

T5T5

SUSCLK [27]

PCIE_WAKE# [22,25]

TPT_PWROK [16]

EC_RSMRST# [16,27]

SPKR [20]
SUSB# [16,27]

SUSC# [16,27]

T12T12

R108 *0/short_4R108 *0/short_4

H_DPSLP# [6]

<20101105> GPIO12 for A3-test CLKREQ setting
GPIO12 Command: For CLK Gen Byte5 CLKREQ# strap
Pull-high: 0x58 -> SRC2/4/6
Pull-low: 0x00 -> SRC1/3/5

<20101108> GPIO13 for A3-test LAN chip selection
Pull-high -> for Atheros LAN AR8158
Pull-down -> for Realtek LAN RTL8105TA-VC-CG

<20110607> PU to +3V_S5 for GPIO12/13 no use to
follow checklist v1.0

Stuff -> Unuse thermal sensor
Unstuff -> Use thermal sensor

R107 *56/F_4R107 *56/F_4

+1.05V

ICH_DPRSTP# [6]

SM_INTRUDER#
ICH_INTVRMEN

R378 8.2K/J_4R378 8.2K/J_4
R383 8.2K/J_4R383 8.2K/J_4
R402 8.2K/J_4R402 8.2K/J_4
R431 *10K/J_4R431 *10K/J_4
R49 10K/J_4R49 10K/J_4
R375 10K/J_4R375 10K/J_4
R379 10K/J_4R379 10K/J_4
R394 10K/J_4R394 10K/J_4
R404 10K/J_4R404 10K/J_4
R418 10K/J_4R418 10K/J_4
R420 10K/J_4R420 10K/J_4
R422 10K/J_4R422 10K/J_4
R28 10K/J_4R28 10K/J_4
R403 10K/J_4R403 10K/J_4
R380 10K/J_4R380 10K/J_4
R393 10K/J_4R393 10K/J_4
R407 10K/J_4R407 10K/J_4
R382 10K/J_4R382 10K/J_4

VCC3_VCC3[11,12,14]

R471 1K/F_4R471 1K/F_4
R464 8.2K/J_4R464 8.2K/J_4
R467 10K/J_4R467 10K/J_4
R465 10K/J_4R465 10K/J_4

R401 1K/J_4R401 1K/J_4
R495 10K/J_4R495 10K/J_4
R460 10K/J_4R460 10K/J_4

R473 1M/F_6R473 1M/F_6
R458 332K/F_4R458 332K/F_4

TPT Power OK (CLG)

+3V

C144 0.1U/10V_4C144 0.1U/10V_4

U4

U4

B B

ECPWROK[5,8,16,27]

HWPG

R101 *0/J_4R101 *0/J_4

TC7SH08FU

TC7SH08FU

2
1

3 5

TPT_PWROK

4

RTC (RTC)

+3VPCU VCCRTC

D16

D16

CH500H-40

CH500H-40

D15

D15

CH500H-40

CH500H-40

R254

R254
1K/J_4

1K/J_4

20MIL 20MIL

A A

12

Q27

Q27

METR3904-G

METR3904-G

CN5

CN5
RTC SOCKET

RTC SOCKET

C222

C222

1U/10V_6

1U/10V_6
R211

R211

20K/F_6

20K/F_6

1 3

2

ML1220 Coin type
AHL03001406 Maxell (HML) 18mAH
AHL03001424 FDK (SAY) 15mAH
AHL03017100 Panasonic (MAT) 17mAH

5

RTCRST#VCCRTC_3

C223

C223

1U/10V_6

1U/10V_6

R218 2K/F_4R218 2K/F_4

R513 *0/J_4R513 *0/J_4
G1

G1

12

*SHORT_PAD

*SHORT_PAD

VCCRTC_2VCCRTC_1VCCRTC_4

<20110426 (G1A)>
Add 0.1uF CAP to prevent PWROK glitch issue

C143

C143

0.1U/10V_4

0.1U/10V_4

RTCRST#_EC [27]

+5V_S5

R217 2K/F_4R217 2K/F_4

R216

R216

68.1K/F_4

68.1K/F_4

R215

R215

150K/F_4

150K/F_4

Clock GEN I2C Level Shift

3

3

2N7002K

2N7002K

Q38

Q38

2N7002K

2N7002K

Q37

Q37

2

2

PCH: +3V_S5

PCLK_SMB[25]

PCH: +3V_S5

PDAT_SMB[25]

4

+3V

R374

R374

8.2K/J_4

8.2K/J_4

R376

R376

8.2K/J_4

8.2K/J_4

CLK GEN: +3V

SMBCK1 [2,4,25]

CLK GEN: +3V

SMBDT1 [2,4,25]

3

1

+3V

1

Platform Reset (CLG)

PLT_RST#

R417 0/J_4R417 0/J_4

Mother Board ID (CLG)

R462

R462

R92

R92

*10K/J_4

*10K/J_4

*10K/J_4

*10K/J_4

BOARDID0
BOARDID1
BOARDID2

R87

R87

R463

R463

10K/J_4

10K/J_4

10K/J_4

10K/J_4

<20110428 (G1A)>
Stuff 10K PD resistors from ZE7 A2-stage

2

+3V

C338 *0.1U/10V_4C338 *0.1U/10V_4

U21

U21

*TC7SH08FU

*TC7SH08FU

2
1

+3V

R457

R457
*10K/J_4

*10K/J_4

R469

R469
10K/J_4

10K/J_4

4

3 5

PLTRST# [6,16,22,25,26,27]

R395

R395
100K_4

100K_4

ACZ_SDOUT
(INT PD)

INTVRMEN

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

ACZ_SYNC
(INT PD)

0

0

1

Enable internal VccSus1_5 VRM

1

(default)

Disable

0

Wednesday, November 16, 2011

Wednesday, November 16, 2011

Wednesday, November 16, 2011

Description

4 x 1s

*

0

Reserved1

0

1

Reserved

1 1 x 4s(1 port/4 lanes)

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

TPT ACZ/GPIO/RTC

TPT ACZ/GPIO/RTC

TPT ACZ/GPIO/RTC

1

ZE7

ZE7

ZE7

4013

4013

4013

1B

1B

1B

1

Tiger Point (CLG)

<Layout note>
Place 0402 caps close to ball
Place 0603/0805 caps close to ICH

TGP

U22E

U22E

A A

TGP

10mA

1.422A

6mA

45mA

24mA
10mA

14mA

VCC5REF

VCC5REF_SUS

VCCSATAPLL

6uA

VCCRTC

VCCDMIPLL

VCCUSBPLL

V_CPU_IO

VCC1_5_1
VCC1_5_2
VCC1_5_3
VCC1_5_4

F12

F5
Y6
AE3
Y25
F6

W18

AA8
M9
M20
N22

VCCP_VCC1_05

VCC1.5_VCC1.5

VCC5_VCC5REF

1U/10V_4C333 1U/10V_4C333

RVCC5_VCC5REF_SUS

C351 .1U/10V_4C351 .1U/10V_4

VCC1.5_SATAPLL

C133 .1U/10V_4C133 .1U/10V_4
C358 .1U/10V_4C358 .1U/10V_4

C355 .01U/25V_4C355 .01U/25V_4

VCC1.5_VCCDMIPLL

C151 .01U/25V_4C151 .01U/25V_4

C127 .1U/10V_4C127 .1U/10V_4
C84 .1U/10V_4C84 .1U/10V_4
C76 1U/6.3V_4C76 1U/6.3V_4
C72 1U/6.3V_4C72 1U/6.3V_4
C157 4.7U/10V_8C157 4.7U/10V_8

VCCRTC

D36 RB500V-40D36 RB500V-40
R390 100/F_4R390 100/F_4

D4 RB500V-40D4 RB500V-40

R37 10/F_4R37 10/F_4

L19 *0/short_6L19 *0/short_6

C147

C147
10U/10V_8

10U/10V_8

L20 *0/short_6L20 *0/short_6

C150

C150
*4.7U/6.3V_6

*4.7U/6.3V_6

R120 *0/short_6R120 *0/short_6

+3V
+5V

+3V_S5

+5V_S5

+1.5V

+1.5V

+1.5V

14

Tiger Point

Tiger Point

POWER

POWER

0.955A

0.216A

0.092A

VCC1_05_1
VCC1_05_2
VCC1_05_3
VCC1_05_4

VCC3_3_1
VCC3_3_2
VCC3_3_3
VCC3_3_4
VCC3_3_5
VCC3_3_6

VCCSUS3_3_1
VCCSUS3_3_2
VCCSUS3_3_3
VCCSUS3_3_4

J10
K17
P15
V10

H25
AD13
F10
G10
R10
T9

F18
N4
K7
F1

VCCP_VCC1_05

VCC3_VCC3

RVCC3_VCCSUS3

C119 1U/6.3V_4C119 1U/6.3V_4
C102 1U/6.3V_4C102 1U/6.3V_4
C137 4.7U/10V_8C137 4.7U/10V_8

C135 1U/6.3V_4C135 1U/6.3V_4
C64 1U/6.3V_4C64 1U/6.3V_4
C74 1U/6.3V_4C74 1U/6.3V_4
C107 .1U/10V_4C107 .1U/10V_4
C121 .1U/10V_4C121 .1U/10V_4

C97 1U/6.3V_4C97 1U/6.3V_4
C70 1U/6.3V_4C70 1U/6.3V_4
C57 .1U/10V_4C57 .1U/10V_4
C69 *10U/10V_8C69 *10U/10V_8

R106 *0/short_6R106 *0/short_6

R503 *0/short_6R503 *0/short_6

VCC3_VCC3 [11,12,13]

R430 *0/short_6R430 *0/short_6

+1.05V

+3.3V_PRIME

+3V_S5

LAYOUT NOTE: place 10U CAP close to pin F18

5

5

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Wednesday, November 02, 2011

Date: Sheet of

Wednesday, November 02, 2011

Date: Sheet of

1

Wednesday, November 02, 2011

PROJECT :

TigerPoint Power

TigerPoint Power

TigerPoint Power

ZE7

ZE7

ZE7

1B

1B

1B

4014

4014

4014

1

Tiger Point (CLG)

U1LB

U1LB

TGP

U22F

U22F

A A

TGP

A1

VSS01

A25

VSS02

B6

VSS03

B10

VSS04

B16

VSS05

B20

VSS06

B24

VSS07

E18

VSS08

F16

VSS09

G4

VSS10

G8

VSS11

H1

VSS12

H4

VSS13

H5

VSS14

K4

VSS15

K8

VSS16

K11

VSS17

K19

VSS18

K20

VSS19

L4

VSS20

M7

VSS21

M11

VSS22

N3

VSS23

N12

VSS24

N13

VSS25

N14

VSS26

N23

VSS27

P11

VSS28

P13

VSS29

P19

VSS30

R14

VSS31

R22

VSS32

T2

VSS33

T22

VSS34

V1

VSS35

V7

VSS36

V8

VSS37

V19

VSS38

V22

VSS39

V25

VSS40

W12

VSS41

W22

VSS42

Y2

VSS43

Y24

VSS44

AB4

VSS45

AB6

VSS46

AB7

VSS47

AB8

VSS48

AC8

VSS49

AD2

VSS50

AD10

VSS51

AD20

VSS52

AD24

VSS53

AE1

VSS54

AE10

VSS55

AE25

VSS56

15

Tiger Point

Tiger Point

VSS57
VSS58
VSS59

RSVD32

G24
AE13
F2

AE16

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Wednesday, November 02, 2011

Date: Sheet of

Wednesday, November 02, 2011

Date: Sheet of

1

Wednesday, November 02, 2011

PROJECT :

TigerPoint GND

TigerPoint GND

TigerPoint GND

ZE7

ZE7

ZE7

1B

1B

1B

4015

4015

4015

5

4

3

2

1

Power Sequence Connector 30pin (CPU)

CN17

D D

S5_ON[27,30,35]
+3V_S5

DNBSWON#[13,27]

SUSB#[13,27]

+1.5VSUS

+5V

+1.05V

+3.3V_PRIME_ON[27,31,34]

+3.3V_PRIME +1.8V

HWPG[2,13,27] ECPWROK [5,8,13,27]

TPT_PWROK[13] H_PWRGD [6,13]

PLTRST#[6,13,22,25,26,27]

C C

1

GND

2

NBSWON#

3

S5_ON

4

+5V_S5

5

+3V_S5

6

RSMRST#

7

DNBSWON#

8

SUSC#

9

SUSB#

10

SUSON

B B

S5_ON

DNBSWON# SUSC#

SUSB# SUSON

+3.3V_PRIME_ON

HWPG ECPWROK

TPT_PWROK H_PWRGD

PLTRST#

11
12
13
14
15
16
17
18
19
20

CN17

1 2
3 4
5 6
7 8

9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32

*30pin POWER SEQ CONN

*30pin POWER SEQ CONN

+1.5VSUS
MAINON
+5V
+1.5V
+1.05V
HWPG_1.05V
VRON
+VCC_CORE
+3.3V_PRIME
+1.8V

NBSWON#

EC_RSMRST#

MAINON

HWPG_1.05V

21

HWPG

22

ECPWROK

23

TPT_PWROK

24

H_PWRGD

25

PLTRST#

26

RESERVE

27

RESERVE

28

RESERVE

29

RESERVE

30

RESERVE

NBSWON# [24,27]

+5V_S5

EC_RSMRST# [13,27]

SUSC# [13,27]

SUSON [27,32,34]

MAINON [27,32,33,34]

+1.5V

HWPG_1.05V [31,33,34]

+VCC_CORE

16

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Wednesday, November 02, 2011

Date: Sheet of

Wednesday, November 02, 2011

Date: Sheet of

5

4

3

2

Wednesday, November 02, 2011

PROJECT :

Cedarview XDP

Cedarview XDP

Cedarview XDP

ZE7

ZE7

ZE7

1B

1B

1B

4016

4016

1

4016

HDMI (HDM)

5

4

3

2

1

17

Level Shifter motherboard topology for max data rate of 1.65Gb/s

Close to HDMI connector

+3V

D D

R233 100K/J_4R233 100K/J_4

R245 100K/J_4R245 100K/J_4

+3V +3V

C C

B B

A A

R209 100K/J_4R209 100K/J_4

R515 100K/J_4R515 100K/J_4

SDVO I2C Control (HDM)

DDI0_HDMI_SCL[5]

DDI0_HDMI_SDA[5]

HDMITX2P_MOS

3

2

Q24

Q24
2N7002K

2N7002K

1

HDMITX2N_MOS

3

2

Q25

Q25
2N7002K

2N7002K

1

HDMITX1P_MOS

3

2

Q22

Q22
2N7002K

2N7002K

1

HDMITX1N_MOS

3

2

Q23

Q23
2N7002K

2N7002K

1

R534 2.2K/J_4R534 2.2K/J_4

R535 2.2K/J_4R535 2.2K/J_4

1

1

R200 620/F_4R200 620/F_4

R189 620/F_4R189 620/F_4
R185 620/F_4R185 620/F_4

+3V

2

3

Q13

Q13
2N7002K

2N7002K

+3V

2

3

Q14

Q14
2N7002K

2N7002K

R500 2.2K/J_4R500 2.2K/J_4

R502 2.2K/J_4R502 2.2K/J_4

TX2_HDMI+
TX2_HDMI-

TX1_HDMI+
TX1_HDMI-

HDMI_DDC_DATA_L

<20100909_Jennifer> Change R500/ R502
from 1.5k to 2.2k to follow CRB.

D39 RB500V-40D39 RB500V-40

L22 BLM18AG601_6L22 BLM18AG601_6

D41 RB500V-40D41 RB500V-40

L23 BLM18AG601_6L23 BLM18AG601_6

+3V

R190 100K/J_4R190 100K/J_4

R192 100K/J_4R192 100K/J_4

R176 100K/J_4R176 100K/J_4

R180 100K/J_4R180 100K/J_4

+5V

+5V

2

2

2

2

C180

C180
*0.1u/10V_4

*0.1u/10V_4

C183

C183
*0.1u/10V_4

*0.1u/10V_4

HDMITX0P_MOS

3

Q18

Q18
2N7002K

2N7002K

1

HDMITX0N_MOS

3

Q19

Q19
2N7002K

2N7002K

1

HDMITX3P_MOS

3

Q16

Q16
2N7002K

2N7002K

1

HDMITX3N_MOS

3

Q17

Q17
2N7002K

2N7002K

1

HDMI_DDC_CLKHDMI_DDC_CLK_L

HDMI_DDC_DATA

R181 620/F_4R181 620/F_4
R177 620/F_4R177 620/F_4R195 620/F_4R195 620/F_4

R174 620/F_4R174 620/F_4
R171 620/F_4R171 620/F_4

The DDC signals are rated at 5V at connector. The
passgate can also be used to protect against
back-power
when computer is OFF but the display is ON and still
pulled up to 5 V.

TX0_HDMI+
TX0_HDMI-

TX3_HDMI+
TX3_HDMI-

TX2_HDMI+[5]
TX2_HDMI-[5]

TX1_HDMI+[5]
TX1_HDMI-[5]

TX0_HDMI+[5]

<20100115(B2A)>
Add fuse to meet IEC 60950-1
2nd certificationand.

+5V

0.22U/6.3V_4

0.22U/6.3V_4

C367

C367

1.1A 8V POLY(SMD1206P110TFT)

1.1A 8V POLY(SMD1206P110TFT)

TX0_HDMI-[5]
TX3_HDMI+[5]

TX3_HDMI-[5]

F2

F2

12

<20101001> Change from 100K to 1M ohm (follow DG0.7)

HDMI_DDI0_HPD#[5]

EMI reserve for HDMI (EMC) ESD Protect (HDM)

Close to HDMI Connector

TX2_HDMI+

TX2_HDMI­TX1_HDMI+

TX1_HDMI­TX0_HDMI+

TX0_HDMI­TX3_HDMI+

TX3_HDMI-

R196

R196
*100/F_4

*100/F_4

R187

R187
*100/F_4

*100/F_4

R179

R179
*100/F_4

*100/F_4

R173

R173
*100/F_4

*100/F_4

<20101209> Change to DFHS19FR015 by ME design change

TX2_HDMI+
TX2_HDMI-

TX1_HDMI+
TX1_HDMI-

TX0_HDMI+
TX0_HDMI-

TX3_HDMI+
TX3_HDMI-

HDMI_DDC_CLK
HDMI_DDC_DATA

+5V_HDMI
HDMI_HPD

R142

R142

1M/F_6

1M/F_6

HDMI_DDI0_HPD#

Q7

2N7002KQ72N7002K

CN16

CN16

1

D2+

2

D2 Shield

3

D2-

4

D1+

5

D1 Shield

6

D1-

7

D0+

8

D0 Shield

9

D0-

10

CK+

11

CK Shield

12

CK-

13

CE Remote

14

NC

15

DDC CLK

16

DDC DATA

17

GND

18

+5V

19

HP DET

HDMI connector

HDMI connector

+3V

R126

R126
10K/J_4

10K/J_4

3

HDMI_HPD

2

R138

R138

1

*100K_4

*100K_4

SHELL1

GND
GND

SHELL2

20

23
22

21

Close to HDMI Connector

U6

HDMI_DDC_DATA
HDMI_DDC_CLK HDMI_DDC_CLK

HDMI_HPD

TX0_HDMI+
TX0_HDMI-

TX3_HDMI+
TX3_HDMI-

TX2_HDMI+
TX2_HDMI-

TX1_HDMI+

U6

1

1

2

2

3

GND_3/8

4

4

5

5

*RClamp0524P

*RClamp0524P

U7

U7

1

1

2

2

3

GND_3/8

4

4

5

5

*RClamp0524P

*RClamp0524P

U9

U9

1

1

2

2

3

GND_3/8

4

4

5

5

*RClamp0524P

*RClamp0524P

HDMI_DDC_DATA

10

10

9

9

7

7

HDMI_HPD

6

6

TX0_HDMI+

10

10

TX0_HDMI-

9

9

TX3_HDMI+

7

7

TX3_HDMI-

6

6

TX2_HDMI+

10

10

TX2_HDMI-

9

9

TX1_HDMI+

7

7

TX1_HDMI-TX1_HDMI-

6

6

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Wednesday, November 16, 2011

Date: Sheet of

Wednesday, November 16, 2011

Date: Sheet of

5

4

3

2

Wednesday, November 16, 2011

PROJECT :

HDMI

HDMI

HDMI

ZE7

ZE7

ZE7

1

1B

1B

1B

4017

4017

4017

5

HALL IC (HSR) LCD POWER SWITCH (LDS) CAMERA POWER (CCD)

+3VPCU

D44 *VPORT_6D44 *VPORT_6

2 1

<G1A>
Change C138 from 4.7U to 1U

D D

C C

+3V

R113

R113
10K_4

10K_4

DISPON

3

Q4

2N7002KQ42N7002K

1

2

Q5

Q5
DTC144EUA

DTC144EUA

1 3

2

BL#

Q6

2N7002KQ62N7002K

C138

C138

1U/10V_6

1U/10V_6

R91 *100K_4R91 *100K_4

R536

R536
47/F_6

47/F_6

+3V

R118

R118
10K_4

10K_4

3

2

1

1

3

D8 RB500V-40D8 RB500V-40

R131

R131
100K_4

100K_4

LID#

2

MR1

MR1
APX9132H AI-TRG

APX9132H AI-TRG

D7 *VPORT_6D7 *VPORT_6

21

LID# [27]

INT_LVDS_BLON [5]

EC_FPBACK# [27]

CRT(CRT)

4

LCDVCC_1

INT_LVDS_DIGON[5]

C319

C319
.1U/10V_4

.1U/10V_4

4.7U/6.3V_6

4.7U/6.3V_6

R349 *0/short_8R349 *0/short_8

C324

C324
*2.2U/6.3V_6

*2.2U/6.3V_6

C328

C328

R350 0/J_4R350 0/J_4

R354

R354
100K/J_4

100K/J_4

C327

C327
.1U/10V_4

.1U/10V_4

+3V

C318

C318
.01U/16V_4

.01U/16V_4

R345 *EDP@0/J_8R345 *EDP@0/J_8

U19

U19

6

IN

4

IN

3

ON/OFF

IC(5P) G5243AT11U

IC(5P) G5243AT11U

Irush=1.5A
AVG=0.24A

LCDVCC

C310

C310

4.7u/10V_8

4.7u/10V_8

3

<EMI>

USBP2-[10]

USBP2+[10]

R19 *0/short_4R19 *0/short_4

R20 *0/short_4R20 *0/short_4

LCD MODULE (LDS)

TXLOUT1+[5]
TXLOUT1-[5]

1

OUT

2

GND

5

GND

DDI1_AUX_DP[5]
DDI1_AUX_DN[5]

TXLOUT2+[5]
TXLOUT2-[5]

DDI1_TX0_DP[5]
DDI1_TX0_DN[5]

TXLOUT0+[5]
TXLOUT0-[5]

DDI1_TX1_DP[5]
DDI1_TX1_DN[5]

TXLCLKOUT+[5]
TXLCLKOUT-[5]

DDI1_TX2_DP[5]
DDI1_TX2_DN[5]

Single-ended 50ohm

LCD_CLK[5]
LCD_DATA[5]

DDI1_TX3_DP[5]
DDI1_TX3_DN[5]

Differential 90ohm

DDI1_AUX_DP
DDI1_AUX_DN

DDI1_TX0_DP
DDI1_TX0_DN

DDI1_TX1_DP
DDI1_TX1_DN

DDI1_TX2_DP
DDI1_TX2_DN

DDI1_TX3_DP
DDI1_TX3_DN

R359 LVDS@0/J_4R359 LVDS@0/J_4
R358 LVDS@0/J_4R358 LVDS@0/J_4

C326 *EDP@.1U/16V_4C326 *EDP@.1U/16V_4
C325 *EDP@.1U/16V_4C325 *EDP@.1U/16V_4

Refer to INTEL DG co-layout

R348 LVDS@0/J_4R348 LVDS@0/J_4
R347 LVDS@0/J_4R347 LVDS@0/J_4

C314 *EDP@.1U/16V_4C314 *EDP@.1U/16V_4
C313 *EDP@.1U/16V_4C313 *EDP@.1U/16V_4

Refer to INTEL DG co-layout

R352 LVDS@0/J_4R352 LVDS@0/J_4
R353 LVDS@0/J_4R353 LVDS@0/J_4

C315 *EDP@.1U/16V_4C315 *EDP@.1U/16V_4
C316 *EDP@.1U/16V_4C316 *EDP@.1U/16V_4

Refer to INTEL DG co-layout

R357 LVDS@0/J_4R357 LVDS@0/J_4
R356 LVDS@0/J_4R356 LVDS@0/J_4

C323 *EDP@.1U/16V_4C323 *EDP@.1U/16V_4
C322 *EDP@.1U/16V_4C322 *EDP@.1U/16V_4

Refer to INTEL DG co-layout

R371 LVDS@0/J_4R371 LVDS@0/J_4
R370 LVDS@0/J_4R370 LVDS@0/J_4

C332 *EDP@.1U/16V_4C332 *EDP@.1U/16V_4
C331 *EDP@.1U/16V_4C331 *EDP@.1U/16V_4

Refer to INTEL DG co-layout

2

USBP2-_R
USBP2+_R

+3V

TXLOUT1_R+_EDP_AUXP
TXLOUT1_R-_EDP_AUXN

TXLOUT1_R+_EDP_AUXP
TXLOUT1_R-_EDP_AUXN

TXLOUT2_R+_EDPTX0+
TXLOUT2_R-_EDPTX0-

TXLOUT2_R+_EDPTX0+
TXLOUT2_R-_EDPTX0-

TXLOUT0_R+_EDPTX1+
TXLOUT0_R-_EDPTX1-

TXLOUT0_R+_EDPTX1+
TXLOUT0_R-_EDPTX1-

TXLCLKOUT+_R_EDPTX2+
TXLCLKOUT-_R_EDPTX2-

TXLCLKOUT+_R_EDPTX2+
TXLCLKOUT-_R_EDPTX2-

LCD_CLK_R_EDPTX3+
LCD_DATA_R_EDPTX3-

LCD_CLK_R_EDPTX3+
LCD_DATA_R_EDPTX3-

R13 0/J_6R13 0/J_6

4.7U/25V_8

4.7U/25V_8

C22

C22

CCD_POWER

C309 4.7U/10V_8

C309 4.7U/10V_8
C308 1000P/50V_4C308 1000P/50V_4
C312 *0.1U/10V_4C312 *0.1U/10V_4

C18

C18

0.1U/50V_6

0.1U/50V_6

LCDVCC

CCD_POWER

C21

C21

*IVO@0.1U/50V_6

*IVO@0.1U/50V_6

+

+

+3V

TXLOUT2_R-_EDPTX0-_R1
TXLOUT2_R+_EDPTX0+_R1

TXLOUT1_R-_EDP_AUXN_R1
TXLOUT1_R+_EDP_AUXP_R1

TXLOUT0_R-_EDPTX1-_R1
TXLOUT0_R+_EDPTX1+_R1

TXLCLKOUT-_R_EDPTX2-_R1
TXLCLKOUT+_R_EDPTX2+_R1

R344 *0/short_6R344 *0/short_6

20mA*24pcs=480mA

VIN

IVO panel : 21.W/5V=0.42A

R26 0/J_6R26 0/J_6

+5V

*IVO@4.7U/25V_8

*IVO@4.7U/25V_8

Reserve for IVO panel

<C-test> Chang to DFHS30FR048 for SMT ME Peter request

Trace Impedance use
single-ended 50ohm and differential 90ohm

1

0.15A

CCD_POWER

C19

C19

CCD_POWER
+5V_LCD

USBP2-_R
USBP2+_R

LCD_CLK_R_EDPTX3+
LCD_DATA_R_EDPTX3­+3V_EDP_HPD

V_BLIGHT

DISPON
LCD_VADJ

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

CN1

CN1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

LCD CONN

LCD CONN

31
32
33
34

18

31
32
33
34

<20100115(B2A)>
Add F1(fuse) to meet IEC 60950-1 2nd certificationand.

F1

F1

+5V

B B

CRT_R[5]
CRT_G[5]
CRT_B[5]

R85

R85

150/F_4

150/F_4

R84

R84

150/F_4

150/F_4

R83

R83

150/F_4

150/F_4

C114

C114
*10P/50V_4

*10P/50V_4

12

1.1A 8V POLY(SMD1206P110TFT)

1.1A 8V POLY(SMD1206P110TFT)

<Layout note>
PLACE inductances 90 DEGREE FROM EACH OTHER

L14 PBY160808T-220Y-NL14 PBY160808T-220Y-N
L15 PBY160808T-220Y-NL15 PBY160808T-220Y-N
L13 PBY160808T-220Y-NL13 PBY160808T-220Y-N

C108

C108

C109

C109

*10P/50V_4

*10P/50V_4

*10P/50V_4

*10P/50V_4

C77

C77

4.7P/50V_4

4.7P/50V_4

C38 .1U/10V_4C38 .1U/10V_4

CRTVDD5

CRT_R1
CRT_G1
CRT_B1 CRTHSYNC

C78

C78

C79

C79

4.7P/50V_4

4.7P/50V_4

4.7P/50V_4

4.7P/50V_4

6
7

2
8
3
9
4

10

5

CN10

CN10

1617

CRT CONN

CRT CONN

CRT_11

111

CRT_SDA

12
13

CRTVSYNC

14

CRT_SCL

15

T2T2

2nd source: 4.7P(+-0.25P) CH-4706TB01

+3V

C35

C35
.1U/10V_4

+3V

.1U/10V_4

C47 0.22U/25V_6C47 0.22U/25V_6

C36

C36
.1U/10V_4

.1U/10V_4

A A

CRTVDD5

CRT_BYP

CRT_R1
CRT_G1
CRT_B1

5

<Layout note>
Close to CONN

U3

U3

1

VCC_SYNC

7

VCC_DDC

8

BYP

2

VCC_VIDEO

3

VIDEO_1

4

VIDEO_2

5

VIDEO_3

6

GND

IP4772_Rout=10ohm

IP4772_Rout=10ohm

SYNC_OUT2
SYNC_OUT1

SYNC_IN2
SYNC_IN1

DDC_IN1
DDC_IN2

DDC_OUT1
DDC_OUT2

16
14

15
13

10
11

9
12

CRT_VSYNC1
CRT_HSYNC1

CRT_SDA

R76 47/F_4R76 47/F_4
R75 47/F_4R75 47/F_4

CRT_VSYNC [5]
CRT_HSYNC [5]

CRT_DDC_SCL [5]
CRT_DDC_SDA [5]

VSYNC_R

L17 0/J_6L17 0/J_6

HSYNC_R

L16 0/J_6L16 0/J_6

CRTVDD5

R79

R79

2.2K/J_4

2.2K/J_4

Pull up at CPU side

4

R78

R78

2.2K/J_4

2.2K/J_4

CRTVSYNC
CRTHSYNC

C37 *10P/50V_4C37 *10P/50V_4
C131 *100P/50V_4C131 *100P/50V_4
C123 *100P/50V_4C123 *100P/50V_4
C85 *100P/50V_4C85 *100P/50V_4
C86 *100P/50V_4C86 *100P/50V_4

CRTVDD5
CRTVSYNC
CRTHSYNC
CRT_SCL
CRT_SDACRT_SCL

3

eDP (LDS)

TXLOUT1_R-_EDP_AUXN
TXLOUT1_R+_EDP_AUXP

DDI1_HPD

+3V

TXLOUT1_R+_EDP_AUXP
TXLOUT1_R-_EDP_AUXN

TXLOUT2_R+_EDPTX0+
TXLOUT2_R-_EDPTX0-

TXLOUT0_R-_EDPTX1­TXLOUT0_R+_EDPTX1+

TXLCLKOUT+_R_EDPTX2+

TXLCLKOUT-_R_EDPTX2-

+3V

R365

R365
*EDP@100K_4

*EDP@100K_4

R366

R366
*EDP@100K_4

*EDP@100K_4

R21 *EDP@0/J_4R21 *EDP@0/J_4
R22 LVDS@0/J_4R22 LVDS@0/J_4

R373 *0/short_4R373 *0/short_4

R372 *0/short_4R372 *0/short_4
R362 *0/short_4R362 *0/short_4

R361 *0/short_4R361 *0/short_4
R364 *0/short_4R364 *0/short_4

R363 *0/short_4R363 *0/short_4
R368 *0/short_4R368 *0/short_4

R367 *0/short_4R367 *0/short_4

DDI1_HPD#[5]

+3V_EDP_HPD
+3V_EDP_HPD

TXLOUT1_R+_EDP_AUXP_R1
TXLOUT1_R-_EDP_AUXN_R1

TXLOUT2_R+_EDPTX0+_R1

TXLOUT2_R-_EDPTX0-_R1

TXLOUT0_R-_EDPTX1-_R1

TXLOUT0_R+_EDPTX1+_R1

TXLCLKOUT+_R_EDPTX2+_R1

TXLCLKOUT-_R_EDPTX2-_R1

2

R27 *EDP@0/J_4R27 *EDP@0/J_4

Q3

Q3

*EDP@2N7002K

*EDP@2N7002K

INT_LVDS_PWM[5]

CONTRAST[27]

+3V

R23

R23
*EDP@1K/J_4

*EDP@1K/J_4

3

DDI1_HPD

2

R25

R25
*EDP@100K/J_4

*EDP@100K/J_4

1

R59 0/J_4R59 0/J_4
R60 *0/J_4R60 *0/J_4

C39 *0.1U/10V_4C39 *0.1U/10V_4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

LCD_VADJ

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

CRT/LVDS/EDP

CRT/LVDS/EDP

CRT/LVDS/EDP

1

ZE7

ZE7

ZE7

18 40Wednesday, November 02, 2011

18 40Wednesday, November 02, 2011

18 40Wednesday, November 02, 2011

1B

1B

1B

5

<20110214(E1A)>
Change CP1~CP6 footprint from
8p4r-0402-smt to 8P4R, for SMT open issue.

CN2

CN2

1
2

KB CONN

KB CONN

3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

25
26

D D

C C

MX7
MX6
MX5
MY0
MY1
MY2
MX4
MY3
MY4
MY5
MY6
MY7
MY8
MX3
MY9
MX2
MX1
MY10
MY11
MX0
MY12
MY13
MY14
MY15

MX7 [27]
MX6 [27]
MX5 [27]
MY0 [27]
MY1 [27]
MY2 [27]
MX4 [27]
MY3 [27]
MY4 [27]
MY5 [27]
MY6 [27]
MY7 [27]
MY8 [27]
MX3 [27]
MY9 [27]
MX2 [27]
MX1 [27]
MY10 [27]
MY11 [27]
MX0 [27]
MY12 [27]
MY13 [27]
MY14 [27]
MY15 [27]

<EMI>

MX7
MX6
MX5
MY0
MY1
MY2
MX4
MY3
MY4
MY5
MY6
MY7
MY8
MX3
MY9
MX2
MX1
MY10
MY11
MX0
MY12
MY13
MY14
MY15

0603 size

4

BLUETOOTH (BTM)KEYBOARD (KBC)

7

8

5

6

CP4

4
2
8
6
4
2
8
6
4
2
8
6
4
2
8
6
4
2
8
6
4
2

CP4
*220P_8P4R

*220P_8P4R

CP1

CP1
*220P_8P4R

*220P_8P4R

CP3

CP3
*220P_8P4R

*220P_8P4R

CP2

CP2
*220P_8P4R

*220P_8P4R

CP6

CP6
*220P_8P4R

*220P_8P4R

CP5

CP5
*220P_8P4R

*220P_8P4R

+3V

3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1

3

2

1

19

Q33

Q33

61mA

T30T30

BT_POWER

BT_LED

1

C283

C283
*BT@0.1U/10V_4

*BT@0.1U/10V_4

R282

BT_POWERON#[25,27]

R282

BT@10K/J_4

BT@10K/J_4

3

BT@AO3413

BT@AO3413

2

C270

C270
*BT@1000p/50V_4

*BT@1000p/50V_4

+

+

C246

C246

BT@0.22u/25V_6

BT@0.22u/25V_6

C248

C248
BT@1000p/50V_4

BT@1000p/50V_4

USBP6+[10]
USBP6-[10]

CN7

CN7

456
3
2

7

1

BT@BT_CONN

BT@BT_CONN

TOUCH PAD (TPD)

+5V_TP

R18

R18

R24

CN3

B B

CN3

1
2
3
4
567

8

TP_CONN

TP_CONN

TP_R#
TP_L#
TPDATA_CN
TPCLK_CN

+5V_TP

C34

C34

10P/50V_4

10P/50V_4

<EMI>

L8 0.4A/120ohm_6L8 0.4A/120ohm_6
L7 0.4A/120ohm_6L7 0.4A/120ohm_6

CX08T121000:0.4A/120ohm_6
CX121T04000:0.4A/120ohm_6

C33

C33
10P/50V_4

10P/50V_4

R24

4.7K/J_4

4.7K/J_4

4.7K/J_4

4.7K/J_4

TPDATA [27]
TPCLK [27]

Left Button

SW2

TP switch

TP switch

SW2

3
4
5
6

Right Button

SW3

TP switch

TP switch

SW3

3
4
5
6

TP_L#

1
2

1
2

TP_R#

12

D43

D43
*14V/38V/100P_4

*14V/38V/100P_4

12

D42

D42
*14V/38V/100P_4

*14V/38V/100P_4

3mA

<EMI>

L9 3A/120ohm_8L9 3A/120ohm_8

C30

C30
.1U/10V_4

.1U/10V_4

+5V+5V_TP

CX121T30001:3A/120ohm_8

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

PROJECT :

KB/BT/TP/LED/Power Connector

KB/BT/TP/LED/Power Connector

KB/BT/TP/LED/Power Connector

ZE7

ZE7

ZE7

1B

1B

1B

19 40Wednesday, November 02, 2011

19 40Wednesday, November 02, 2011

19 40Wednesday, November 02, 2011

1

5

Codec ALC271X (ADO)

Place near codec

D D

+5VA

C207

C207

C217

C217

.1U/10V_4

.1U/10V_4

10U/6.3V_6

10U/6.3V_6

ADOGND

+5V

C230

C230

4.7U/6.3V_6

4.7U/6.3V_6

Place next to pin 38

R220 *0/short_6R220 *0/short_6

C220

C220
.1U/10V_4

.1U/10V_4

+5VPVDD1

C221

C221

4.7U/6.3V_6

4.7U/6.3V_6

Spilt by AGND

C226

C226
.1U/10V_4

.1U/10V_4

Place next to pin 39

Spilt by PGND

+5VPVDD2

C243

C243

C247

C247

4.7U/6.3V_6

4.7U/6.3V_6

.1U/10V_4

.1U/10V_4

Spilt by DGND

Place next to pin 46

+3V

C234

C234

4.7U/6.3V_6

4.7U/6.3V_6

R268 *0/short_6R268 *0/short_6

C258

C258
.1U/10V_4

.1U/10V_4

+5V

C C

ANALOG

L_SPK+
L_SPK-

R_SPK­R_SPK+

EAPD#

R283 *0/short_6R283 *0/short_6

ADOGND

C256

C256

.1U/10V_4

.1U/10V_4

37
38
39
40
41
42
43
44
45
46
47
48
49

Place next to pin 1

T54T54
T55T55

0V : Power down Class D SPK amplifier
5V : Power up Class D SPK amplifier

ADOGND

C206

C206

+

+

2.2U/6.3V_6

2.2U/6.3V_6

C213

C213

+

+

2.2U/6.3V_6

2.2U/6.3V_6

32

33

34

35

36

U11

U11

CBP

CBN

CPVEE

HP-OUT-L

AVSS2
AVDD2
PVDD1
SPK-L+
SPK-L­PVSS1
PVSS2
SPK-R­SPK-R+
PVDD2
SPDIFO2/EAPD
SPDIFO
PGND

+AZA_VDD

C263

C263

4.7U/6.3V_6

4.7U/6.3V_6

DMIC_DAT
DMIC_CLK

PD#

HP-OUT-R

ALC271X-VB3-GR

DVDD11GPIO0/DMIC-DATA2GPIO1/DMIC-CLK3PD#4SDATA-OUT5BIT-CLK6DVSS27SDATA-IN8DVDD-IO9SYNC10RESET#11PCBEEP

30

31

MIC1-VREFO-L

MIC1-VREFO-R

4

HPR
HPL

MIC1-VREFO-L
MIC1-VREFO-R
MIC2-VREFO

INT_AMIC-VREFO

ADOGND

26

27

28

29

VREF

AVSS1

LDO-CAP

MIC2-VREFO

MONO-OUT

ACZ_SDIN1_R

R265 33/J_4R265 33/J_4

C257 *22P/50V_4C257 *22P/50V_4

C208 10U/6.3V_6C208 10U/6.3V_6

C209

C209

2.2U/6.3V_6

2.2U/6.3V_6

25

AVDD1

LINE1-R

LINE1-L
MIC1-R

MIC1-L

JDREF

Sense-B

MIC2-R

MIC2-L

LINE2-R

LINE2-L

Sense A

ALC271X-VB3-GR

ALC271X-VB3-GR

12

DIGITAL

+AZA_VDD_R

ADOGND

Place next to pin 27

+

+

C212

C212

C210

C210

0.1U/10V_4

0.1U/10V_4

*10U/6.3V_6

*10U/6.3V_6

C227

C227

.1U/10V_4

.1U/10V_4

24
23

MIC1_R1

22

MIC1_L1

21

Placement near Audio Codec

20
19
18
17
16
15
14
13

ANALOG

C260 1U/10V_6C 260 1U/10V_6

R226 20K/F_4R226 20K/F_4

SENSEB

R232 20K/F_4R232 20K/F_4

MIC2_R2
MIC2_L2

LIN2_INT_R1

C237 1u/16V_6C237 1u/16V_6

LIN2_INT_L1

C239 1u/16V_6C239 1u/16V_6

SENSEA

R249 39.2K/F_4R249 39.2K/F_4
R257 20K/F_4R257 20K/F_4

PCBEEP dont coupling any signals if possible
8/17 separate PCBEEP to Digital from Realtek suggestion

1.6Vrms

BEEP_1PCBEEP_C

C264

C264
100P/50V_4

100P/50V_4

ACZ_RST#_CODEC [13]
ACZ_SYNC_CODEC [13]

ACZ_SDIN1 [13]

ACZ_SDOUT_CODEC [13]

ACZ_BITCLK_CODEC [13]

Place next to pin 25

ADOGND

MIC2-JD#
AMIC2_INT

C204

C204

<20110428> Add 1n PD to AGND for amic
noise depressing by FAE Vic suggestion

1n/50V_4

1n/50V_4

ADOGND

HP_JD#
MIC1_JD#

R273 47K/J_4R273 47K/J_4

R267

R267

4.7K/J_4

4.7K/J_4

R274 47K/J_4R274 47K/J_4

If either HDA device io power use +1.5V,
all device IO power change to +1.5V

R266 *0/short_6R266 *0/short_6

C265

C265

C252

C252

4.7U/6.3V_6

4.7U/6.3V_6

.1U/10V_4

.1U/10V_4

Place next to pin 9

3

+5VA

C219

C219
10U/6.3V_6

10U/6.3V_6

ADOGND

<20101103> Add EC PWM control
for beep sound volumn control

PCBEEP [27]
SPKR [13]

+AZA_VDD

EARPHONE (AMP)

MIC2_R2

MIC2_L2

<20100917> Add 22k PD by FAE
suggestion for discharing

MIC2-JD#

Q26

Q26

2SK3018

2SK3018

HPR

R172 47/F_4R172 47/F_4
R497 47/F_4R497 47/F_4

HPL-1
HPR-1

R496

R496
*1K/J_4

*1K/J_4

MIC (AMP)

MIC1_L1

C356 4.7u/6.3V_6C356 4.7u/6.3V_6

MIC1_R1

C218 4.7u/6.3V_6C218 4.7u/6.3V_6

MIC1_JD#

12

D12

D12
*VPORT_6

*VPORT_6

C2402.2U/6.3V_6 C2402.2U/6.3V_6

C2442.2U/6.3V_6 C2442.2U/6.3V_6

3

1

R152

R152
*1K/J_4

*1K/J_4

MIC1_L2
MIC1_R2

Near CN13

2

2

ADOGND

L21 0_6L21 0_6
L39 0_6L39 0_6

R455 1K/F_4R455 1K/F_4
R202 1K/F_4R202 1K/F_4

MIC2-VREFO

C231

C231
*10U/6.3V_8

*10U/6.3V_8

C363

C363
2200P/50V_4

2200P/50V_4

MIC1-VREFO-R
MIC1-VREFO-L

1

20

R244

R244

2.2K/J_4

2.2K/J_4

12

D40

D40

*14V/38V/100P_4

*14V/38V/100P_4

ADOGNDADOGND

C187

C187
*470p/50V_4

*470p/50V_4

COMBO_MIC

HPL_SYSHPL
HPR_SYS
HP_JD#

C353

C353
*470p/50V_4

*470p/50V_4

12

*14V/38V/100P_4

*14V/38V/100P_4

ADOGND

MIC1_L
MIC1_R
MIC1_JD#

D11

D11

C201

C201
*0.1u/16V_6

*0.1u/16V_6

Normal Open Jack

CN15

CN15

3
6
1

2
4
5

UNIVERSAL JACK

UNIVERSAL JACK

010030FR006G119ZR

010030FR006G119ZR

Normal Open Jack

CN13

CN13

3
6
1

2
4
5

UNIVERSAL JACK

UNIVERSAL JACK

010030FR006G119ZR

010030FR006G119ZR

R2431K/J_4 R2431K/J_4

R236

R236

22K/F_4

22K/F_4

ADOGND

ADOGND

R23522K/F_4 R23522K/F_4

C174

C174
2200P/50V_4

2200P/50V_4

*14V/38V/100P_4

*14V/38V/100P_4

R453

R453

4.7K/F_4

4.7K/F_4

MIC1_L3
MIC1_R3

12

ADOGND

D38

D38

R178

R178

4.7K/F_4

4.7K/F_4

R447 0_6R447 0_6
R183 0_6R183 0_6

D37

D37

*14V/38V/100P_4

*14V/38V/100P_4

12

B B

Power (ADO)

Internal Speaker (AMP)

GND

Internal Analog MIC (AMP)

ADOGNDADOGND

Demodulation Filter

+5V

Place close to Codec

L25 0/J_8L25 0/J_8

Mute (ADO)

A A

+5V

<20101115> Change to 10K by codec FAE suggestion

R285

R285
*10K/J_4

*10K/J_4

PD#

D25 RB500V-40D25 RB500V-40

D24 RB500V-40D24 RB500V-40

D23 RB500V-40D23 RB500V-40

ACZ_RST#_CODEC

EAPD#

5

AMP_MUTE# [27]

+5VA

ANALOG DIGITAL

40mil for each signal

R_SPK+

R297 *0/short_6R297 *0/short_6

R_SPK-

R290 *0/short_6R290 *0/short_6
R272 *0/short_6R272 *0/short_6

L_SPK+

R242 *0/short_6R242 *0/short_6

R_SPK+_1

C275

C275

*68p/50V_6

*68p/50V_6

4

R_SPK-_1

C269

C269

*68p/50V_6

*68p/50V_6

L_SPK-_1L_SPK-

C261

C261

*68p/50V_6

*68p/50V_6

L_SPK+_1

C241

C241

*68p/50V_6

*68p/50V_6

CN6

CN6

R-L-SPEAKERS

R-L-SPEAKERS

<20110811> For analog mic ESD protection using

R520 *0/J_6R520 *0/J_6

ADOGND

R501 0/J_6R501 0/J_6

R439 *0/J_6R439 *0/J_6
R261 *0/J_6R261 *0/J_6
R188 *0/J_6R188 *0/J_6
R225 *0/J_6R225 *0/J_6
R175 *0/J_6R175 *0/J_6
R184 *0/J_6R184 *0/J_6
R441 *0/J_6R441 *0/J_6
R168 *0/J_6R168 *0/J_6

R511 *Short_6R511 * Short_6
R203 0/J_6R203 0/J_6
R444 0/J_6R444 0/J_6

4
3
2
1

C195 1000P/50V_4C195 1000P/50V_4
C251 1000P/50V_4C251 1000P/50V_4

3

<20101115> Change to 10K by codec FAE suggestion

INT_AMIC-VREFO
AMIC2_INT AMIC2_INT_R

R14010K/J_4 R14010K/J_4

R1301K/J_4 R1301K/J_4

C158

C158

*22P-50V_4

*22P-50V_4

ADOGND ADOGND

<20110706> Stuff TVS BC040201Z00 for ESD solution

2

TVS/6pF_4D9TVS/6pF_4

12

D9

ADOGND

CN4

CN4

1
2

INT_MIC

INT_MIC

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

PROJECT :

ALC271X / AMP / SPK

ALC271X / AMP / SPK

ALC271X / AMP / SPK

1

ZE7

ZE7

ZE7

20 40Wednesday, November 02, 2011

20 40Wednesday, November 02, 2011

20 40Wednesday, November 02, 2011

1B

1B

1B

5

USB Left (USB)

+5VPCU

D D

C C

C380

C380

1U/6.3V_4

1U/6.3V_4

USB_EN#

U25

U25
IC(8P)G547E2P81U

IC(8P)G547E2P81U

2

IN1

OUT3

3

IN2

OUT2
OUT1

4

EN

1

GND

OC#

G547E2P81U: Enable: Low Active /2.5A
Follow ZH9

2A

5VUSB_1

8
7
6

5

USBOC#L [10,27]

4

3

2

1

21

<Layout note>

<Layout note>3528 type H=1.9mm

<2nd Source> CH71001M687

R248 *0/short_4R248 *0/short_4

USBP3-[10]
USBP3+[10]

R253 *0/short_4R253 *0/short_4

Close to CONN

+

+

C379

C379
100U/6.3V_3528

100U/6.3V_3528

12

D20

D20
*5V/30V/0.2P_4

*5V/30V/0.2P_4

C377

C377
.1U/10V_4

.1U/10V_4

USBP3-_CN
USBP3+_CN

12

D18

D18
*5V/30V/0.2P_4

*5V/30V/0.2P_4

Left

CN21

CN21

1

VDD

2

D-

3

D+

4

GND1

USB_CONN

USB_CONN

GND6
GND5

GND7
GND8

6
5

7
8

USB Right (USB)

+5VPCU
+3VPCU

R82

R82

*10K/J_4

*10K/J_4

USB_EN#[27]

B B

A A

C111

C111

4.7u/10V_6

4.7u/10V_6

G547E2P81U: Enable: Low Active /2.5A
Follow ZH9

5

USB_EN#

U23

U23
IC(8P)G547E2P81U

IC(8P)G547E2P81U

2

IN1

3

IN2

4

EN

1

GND

OUT3
OUT2
OUT1

OC#

8
7
6

5

2A

5VUSB_0

USBOC#R [10,27]

<Layout note>
Close to CONN

+

+

C26

C26
220u/6.3V_7343

220u/6.3V_7343

R15 *0/short_4R15 *0/short_4

USBP1-[10]
USBP1+[10]

R14 *0/short_4R14 *0/short_4

R50 *0/short_4R50 *0/short_4

USBP0-[10]
USBP0+[10]

R44 *0/short_4R44 *0/short_4

4

USBP1-_CN
USBP1+_CN

USBP0-_CN
USBP0+_CN

3

12

<Layout note>
Close to CONN

+

+

C89

C89
*100u/6.3V_3528

*100u/6.3V_3528

12

D2

D2
*5V/30V/0.2p_4

*5V/30V/0.2p_4

D5

D5
*5V/30V/0.2p_4

*5V/30V/0.2p_4

C24

C24

0.1u/10V_4

0.1u/10V_4

12

D3

D3
*5V/30V/0.2p_4

*5V/30V/0.2p_4

C73

C73

0.1u/10V_4

0.1u/10V_4

12

D6

D6
*5V/30V/0.2p_4

*5V/30V/0.2p_4

Right up

CN9

CN9

1

VDD

2

D-

3

D+

4

GND1

USB_CONN

USB_CONN

Right down

CN12

CN12

1

VDD

2

D-

3

D+

4

GND1

USB_CONN

USB_CONN

2

GND6
GND5

GND7
GND8

GND6
GND5

GND7
GND8

6
5

7
8

6
5

7
8

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

PROJECT :

USB Port

USB Port

USB Port

1

ZE7

ZE7

ZE7

21 43Wednesday, November 02, 2011

21 43Wednesday, November 02, 2011

21 43Wednesday, November 02, 2011

D3E

D3E

D3E

5

LAN (LAN)

4

3

2

1

22

+3V_S5 +3V_LAN

R351 *0/short_6R351 *0/short_6

Close to IC

D D

C304

C304

0.1U/16V_4

0.1U/16V_4

C320

C320

C307

C307 C317

0.1U/16V_4

0.1U/16V_4

0.1U/16V_4

0.1U/16V_4

12

C317
*4.7U/10V/8

*4.7U/10V/8

<20110510> Change from 27P to 33P by vendor's measure report.

C7 33P/50V_4C7 33P/50V_4

Y1

Y1

25MHz-LAN

25MHz-LAN

2 1

C4 33P/50V_4C4 33P/50V_4

TX0P

C C

Pull-Up at CLK Gen side

CLKREQ_LAN#[2]

R343 *0/short_4R343 *0/short_4

TX0N
TX1P

PCIE_RXP0[10]
PCIE_RXN0[10]

R3 2.49K/F_4R3 2.49K/F_4

+3V_LAN

VDD10

CLKREQ_LAN#_R1

PCIE_TXP0[10]
PCIE_TXN0[10]

CLK_PCIE_LANP[2]

CLK_PCIE_LANN[2]

C8 .1U/10V_4C8 .1U/10V_4
C14 .1U/10V_4C14 .1U/10V_4

VDD10 EVDD10

Close To IC Close To IC Pin 13.

U1

U1

33
34
35
36

1
2
3
4
5
6
7
8

37
38
39

GND
GND
GND
GND

HV
MDIP0
MDIN0
MDIP1
MDIN1
NC
VDD1
CLKREQBPIN

GND
GND
GND

GND40GND41GND

EVDD10
PCIE_RXP0_LAN
PCIE_RXN0_LAN

C1

C1

0.1U/16V_4

0.1U/16V_4

25MCLKX1
25MCLKX2
RSET

32

31

RSET

CTRL12

RTL8105TA-VC-CG

RTL8105TA-VC-CG

HSIP9HSIN10REFCLK_P11REFCLK_N12VDDTX13HSOP14HSON

42

29

28

CKXTAL230CKXTAL1

C16

C16

0.1U/16V_4

0.1U/16V_4

LAN_ACTLED#

27

26

25

VDD3

GPOUTPIN

LEDPIN/SPICSB

16

15

GPOCTRL12

LAN_LINKLED#

EESKPIN/LED1/TCLK/SPISCK

GNDTX

C2

C2

0.1U/16V_4

0.1U/16V_4

EEDIPIN/TDI/SPISI/SDA

EEDOPIN/LED3/SPISO

EECSPIN/TCS/SCL

LANWAKEBPIN

R6 1K/J_4R6 1K/J_4

VDD1
VDD3

ISOLATEBPIN

PERSTBPIN

R1 *0/short_4R1 *0/short_4

12

R2 *0/short_4R2 *0/short_4

+3V_LAN

EEDI/SDA

24

LED3/EEDO

23

EECS/SCL

22

VDD10

21

PCIE_WAKE#TX1N

20
19

ISOLATE#

18
17

R12 *0/short_4R12 *0/short_4

12

C17

C17
*4.7U/10V/8

*4.7U/10V/8

C6
1U/10V_4C61U/10V_4

+3V_LAN

C5

C5

0.1U/16V_4

0.1U/16V_4

CTRL12

C3

C3

0.1U/16V_4

0.1U/16V_4

T1T1

R11 1K/J_4R11 1K/J_4
R10 15K/J_4R10 15K/J_4

Close To IC Pin 31.

CLKREQ_LAN#_R1
PCIE_WAKE#
EEDI/SDA
EECS/SCL

PCIE_WAKE# [13,25]

+3V

PLTRST# [6,13,16,25,26,27]

+3V_LAN

R342 *10K/J_4R342 *10K/J_4
R7 *10K/J_4R7 *10K/J_4
R9 10K/J_4R9 10K/J_4
R8 10K/J_4R8 10K/J_4

Int. PU in SB

TRANSFORMER (LAN) RJ45 Connector (LAN)

For Rural

B B

CN8

U17

C301

C301

*10P/50V_4

*10P/50V_4

U17

1

1

2

2

3

3
445

*UCLAMP2512T.TCT

*UCLAMP2512T.TCT

TX1N_R
TX1P_R

TX0P_R

C306

C306

0.01U/25V_4

0.01U/25V_4

The value should be

0.01uF-0.4uF

8

8

7

7

6

6

5

8
7
6
5
4
3
2

X-TX0P
X-TX0N
X-TX1P
X-TX1N

For Rural, stuff 0/J_4 (CS00002JB38)

U16

U16

For Normal, unstuff 0/J_4 (CS00002JB38)

TD­TD+
CT
NC
NC
CT
RD­RD+1RX+

NS0014 LF_Bothhand

NS0014 LF_Bothhand

9

TX-

10

TX+

11

CT

12

NC

13

NC

14

CT

15

RX-

16

X-TX1N
X-TX1P

TERM0

X-TX0NTX0N_R
X-TX0P

TX0P

R335 0/J_4R335 0/J_4

TX0N

R336 0/J_4R336 0/J_4

TX1P

R338 0/J_4R338 0/J_4

TX1N

R337 0/J_4R337 0/J_4

For Rural, use 1/F_4 (CS-1002FB23)
For Normal, use 0/J_4 (CS00002JB38)

C303

C303

C302

*10P/50V_4

*10P/50V_4

A A

C302

*10P/50V_4

*10P/50V_4

TX0P_R
TX0N_R
TX1P_R
TX1N_R

C300

C300

*10P/50V_4

*10P/50V_4

Reserve for EMI request

C305

C305

1000P/3KV_1808

1000P/3KV_1808

5

4

U15

U15

1
2
3

*UCLAMP2512T.TCT

*UCLAMP2512T.TCT

R339 *0/J_4R339 *0/J_4

R340

R340
75/F_8

75/F_8

TERM9

1
2
3
445

R341

R341
75/F_8

75/F_8

8

8

7

7

6

6

5

D35

D35

*P3100SBLRP

*P3100SBLRP

1 2

3

LAN_LINKLED#

LAN_ACTLED#

<20110105> Will add RJ45 connector without LED type by inner document

2

R346 *510/J_6R346 *510/J_6

+3V_LAN

C311

C311
*0.1U/50V_8

*0.1U/50V_8

C299

C299
*0.1U/50V_8

*0.1U/50V_8

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

TERM9

X-TX1N

TERM9

X-TX1P
X-TX0N
X-TX0P

R334 *510/J_6R334 *510/J_6

+3V_LAN

DFTJ08FR221 (FOX)
DFTJ08FR222 (AEC)

LAN RTL8105TA-VC-CG

LAN RTL8105TA-VC-CG

LAN RTL8105TA-VC-CG

CN8

11

G-

12

8
7
6
5
4
3
2
1

9

10

RJ45-CONN

RJ45-CONN

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

G+

NC4/3­NC/3+
RX-/1­NC2/2­NC1/2+
RX+/1+
TX-/0­TX+/0+

A­A+

GND
GND

1

14
13

ZE7

ZE7

ZE7

GREEN

AMBER

22 40Wednesday, November 02, 2011

22 40Wednesday, November 02, 2011

22 40Wednesday, November 02, 2011

1B

1B

1B

5

4

3

2

1

23

Stitching Capacitor (CLG)

For RF Request

D D

+1.05V

C145

C145
1000P/50V_4

1000P/50V_4

For CRT R/G/B Signals

VIN

C140

C140
1U/25V_6

1U/25V_6

C C

C27

C27
1000P/50V_4

1000P/50V_4

B B

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

5

4

3

Date: Sheet of

2

PROJECT :

Stitching Cap

Stitching Cap

Stitching Cap

ZE7

ZE7

ZE7

1

1B

1B

1B

23 40Wednesday, November 02, 2011

23 40Wednesday, November 02, 2011

23 40Wednesday, November 02, 2011

5

4

3

2

1

2.5" SATA HDD (HDD)

D D

CN11

CN11

1
2
3
4
5
6
7

8
9
10

14

11

15

12

16

13

17

MAIN_SATA

MAIN_SATA

C C

SATA_TXP0_C1
SATA_TXN0_C1

SATA_RXN0_C1
SATA_RXP0_C1

C25

C25

0.1U/10V_4

0.1U/10V_4

0.01u/16V_4C340 0.01u/16V_4C340

0.01u/16V_4C339 0.01u/16V_4C339

0.01u/16V_4C342 0.01u/16V_4C342

0.01u/16V_4C341 0.01u/16V_4C341

5V_SATA1

C23

C23
*0.1U/10V_4

*0.1U/10V_4

1A

SATA_TXP0
SATA_TXN0

SATA_RXN0
SATA_RXP0

C20

C20

4.7U/10V_8

4.7U/10V_8

R369 *0/short_8R369 *0/short_8

+

+

C330

C330
*100U/6.3V_3528

*100U/6.3V_3528

SATA_TXP0 [11]
SATA_TXN0 [11]

SATA_RXN0 [11]
SATA_RXP0 [11]

+5V

24

LED/SW (UIF)

<20110223> In S5 and battery only mode,

+3V_S5

PWR LED

SUS LED

B B

LED3

LED3

LED_AMBER/BLUE

LED_AMBER/BLUE

D31 *5.5V/25V/410P_4D31 *5.5V/25V/410P_4

1 2

23
1

R330 33/J_4R330 33/J_4
R331 220/F_4R331 220/F_4

D32 *5.5V/25V/410P_4D32 *5.5V/25V/410P_4

1 2

PWRLED# [27]
SUSLED# [27]

EC will turn off PWRLED#/SUSLED# while EC is idle.

PWR indicator

+3V

LED1

LED1

2 1

LED_BLUE_TOP

LED_BLUE_TOP

R333 51/J_4R333 51/J_4

+3VPCU

FULL LED

CHG LED

+5V

3G LED

WLAN LED

A A

+5V

HDD LED

LED2

LED2

LED_AMBER/BLUE

LED_AMBER/BLUE

<20110530> Change from +3V to +5V Due to there is the
internal series resister in 3G/WLAN module, cause the forward voltage of LED4 is too small

LED4

LED4

LED_AMBER/BLUE

LED_AMBER/BLUE

LED5

LED5

3 1

*LED_BULE_SIDE

*LED_BULE_SIDE

<20101229> Unstuff HDD LED

5

D33 *5.5V/25V/410P_4D33 *5.5V/25V/410P_4

1 2

23
1

23
1

R327 33/J_4R327 33/J_4
R328 220/F_4R328 220/F_4

D34 *5.5V/25V/410P_4D34 *5.5V/25V/410P_4

1 2

D28 *3G@5.5V/25V/410P_4D28 *3G@5.5V/25V/410P_4

1 2

R325 3G@150/F_4R325 3G@150/F_4
R326 470/J_4R326 470/J_4

D29 *5.5V/25V/410P_4D29 *5.5V/25V/410P_4

1 2

R329 *330/J_4R329 *330/J_4

D30 *5.5V/25V/410P_4D30 *5.5V/25V/410P_4

1 2

SW1

BATLED0# [27]

PWR button

BATLED1# [27]

3G_MINI_LED# [25]
WLAN_LED# [25]

SATALED# [11]

*BSS84

*BSS84

2

Q36

Q36

1

4

<20090609(A1A)_Checklist Rev1.0>
Need the buffer for LED driving
capability since the IOL is 6mA only.

3

3

2

SW1

3
5

6

Power Switch

Power Switch

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

NBSWON#

2
14

12

D1

D1
*5.5V/25V/410P_4

*5.5V/25V/410P_4

SATA HDD/LED/SW

SATA HDD/LED/SW

SATA HDD/LED/SW

NBSWON# [16,27]

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

1

ZE7

ZE7

ZE7

24 40Wednesday, November 02, 2011

24 40Wednesday, November 02, 2011

24 40Wednesday, November 02, 2011

1B

1B

1B

5

Mini Card 1 (MPC)

+3.3V
+1.5V

LED_WPAN#

LED_WLAN#

LED_WWAN#

USB_D+
USB_D-

SMB_DATA

SMB_CLK

+1.5V

+3.3Vaux

PERST#

W_DISABLE#

UIM_VPP

UIM_RESET

UIM_CLK

UIM_DATA

UIM_PWR

+1.5V
+3.3V

GND54GND

WLAN CO NN

WLAN CO NN

GND

GND

GND

GND

GND

GND

+3V_Mini1_VDD

52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18

16
14
12
10
8
6
4
2

+3V_Mini1_VDD

BT_POWE RON#[19 ,27]

PCLK_DEB UG[2]

D D

PCIE_W AKE#[13,22]

+3V_Mini1_VDD

PCIE_TXP1[10]
PCIE_TXN1[10]

PCIE_RXP1[10]
PCIE_RXN1[10 ]

CLK_PCIE_MPC_P[2]
CLK_PCIE_MPC_N[2]

CLKREQ_MPC#[2]

3

2

R528 *0 /J_4R528 *0/J_4

PLTRST#

R529 0/J_4R5 29 0/J_4
R526 0/J_4R5 26 0/J_4

Q44

Q44

MINI1_WAKE#

1

*2N7002K

*2N7002K
R530 *10K /J_4R530 *1 0K/J_4

CN22

CN22

51

Reserved

49

Reserved

47

Reserved

45

Reserved

43

GND

41

+3.3Vaux

39

+3.3Vaux

37

GND

35

GND

33

PETp0

31

PETn0

29

GND

27

GND

25

PERp0

23

PERn0

21

GND

19

UIM_C4

17

UIM_C8

15

GND

13

REFCLK+

11

REFCLK-

9

GND

7

CLKREQ#

5

Reserved

3

Reserved

1

WAKE#

53

4

+1.5V_Mini1 _VDD

WL_SMDATA
WL_SMCLK

PLTRST#_2
RF_EN

WLAN_L ED1#
WIMAX_LED#

R521 *0 /short_4R521 *0 /short_4

R517 *0 /short_4R517 *0 /short_4
R518 *0 /short_4R518 *0 /short_4
R519 *0 /short_4R519 *0 /short_4
R522 *0 /short_4R522 *0 /short_4
R523 *0 /short_4R523 *0 /short_4

R525 *0 /short_4R525 *0 /short_4

USBP7+ [10]
USBP7- [10]

LFRAME# [1 3,27]
LAD3 [13,27]
LAD2 [13,27]
LAD1 [13,27]
LAD0 [13,27]

+3V_Mini1_VDD

R302

R302

4.7K/J_4

4.7K/J_4

1

PLTRST# [6,13,16,22,26,27]
RF_EN [27]

RF_LED_ON

Q30

Q30

2

2N7002K

2N7002K

3

Turn off WLAN LED when 3G module is on

R308 *0 /short_4R308 *0 /short_4

3

WLAN_L ED# [24 ]

3G_MINI_L ED#

2

+3V_Mini1_VDD

2

4

RN1

RN1
*4.7K_4P 2R

Q32

Q32

2

*2N7002E

*2N7002E

SMBDT1[2,4,13]

SMBCK1[2,4,13]

3

R314 *0/J_4R31 4 *0/J_4

+3V_Mini1_VDD

2

3

R294 *0/J_4R29 4 *0/J_4

Q29

Q29
*2N7002E

*2N7002E

*4.7K_4P 2R

1

3

WL_SMDATA

1

WL_SMCLK

1

1

25

+1.5V_Mini1 _VDD

0.5A

C385

C385

*1000P/5 0V_4

*1000P/5 0V_4

R516 *3G@0/J_4R516 *3G@0/J_4

3G_EN [27]

Max: 7.5mA (Option)

UIM_PWR
UIM_VPP
UIM_RST
UIM_DATA

4

PLTRST#

<20110609> Un-stuff C9 since EM820W doesn't use Vpp

C250

C250

C383

C383

*10U/10V_8

*10U/10V_8

*0.1U/10V _4

*0.1U/10V _4

no matter have 3G function or not,
need to stuff this PU.

+3V_Mini2_VDD

R262

R262
100K/J_4

100K/J_4

3G_MINI_L ED# [2 4]

UIM_PWR

C13 3G@27P/50V_4C13 3G@27P/50V_4

UIM_DATA

C11 3G@10P/50V_4C11 3G@10P/50V_4

UIM_CLK

C12 3G@10P/50V_4C12 3G@10P/50V_4

UIM_RST

C10 3G@27P/50V_4C10 3G@27P/50V_4

UIM_VPP

C9 *3G@33P/50V_4C9 *3G@33P/50 V_4

+3VSUS

R241 *0/sh ort_8R241 *0/short_8
R252 *0/sh ort_6R252 *0/short_6

+3V

R224 *3G@0/J_8R224 *3G@0 /J_8
R222 *3G@0/J_6R222 *3G@0 /J_6

+1.5V

R228 *3G @0/J_8R228 *3G @0/J_8

UIM_CLK

3

U18

U18

1

CH1

2

VN
CH23CH3

*3G@CM129 3-04SO

*3G@CM129 3-04SO

+3V_Mini2_VDD

+1.5V_Mini2 _VDD

CH4

VP

C233

C233

3G@10U/10V_8

3G@10U/10V_8

C235

C235
*3G@1000 P/50V_4

*3G@1000 P/50V_4

UIM_VPPUIM_RST

6
5

UIM_DATA

4

Peak:2.75A
Normal:1.1A

C373

C373

3G@0.1U/1 0V_4

3G@0.1U/1 0V_4

0.5A

+3V

C371

C371

3G@0.1U/1 0V_4

3G@0.1U/1 0V_4

C369

C369
*3G@0.1U/10V_4

*3G@0.1U/10V_4

2nd source: CH4471K9B03

12

C389

C370

C370

3G@0.1U/1 0V_4

3G@0.1U/1 0V_4

<20090604(A1A)_Qualcomm design guide>
Place 0.1uF near connector's VCC pin

UIM_PWR

C321

C321

3G@1U/10V_6

3G@1U/10V_6

C389

C366

C366

3G@0.47U/6.3V_4

3G@0.47U/6.3V_4

3G@0.1U/1 0V_4

3G@0.1U/1 0V_4 R194

C15

C15
3G@0.1U/1 0V_4

3G@0.1U/1 0V_4

1 2

2

C378

C378
3G@10P/5 0V_4

3G@10P/5 0V_4

*3G@2N7002E

*3G@2N7002E

PDAT_SMB[13]

PCLK_SMB[13]

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

3

*3G@2N7002E

*3G@2N7002E

PCLK_SMB 3G_SMCLK

3

Mini-Card/WL/3G/SIM

Mini-Card/WL/3G/SIM

Mini-Card/WL/3G/SIM

+3V_Mini2_VDD

+3V_Mini2_VDD

*3G@10K_ 4

*3G@10K_ 4

Q21

Q21

2

R207 *3G@0_4R207 *3G@0_ 4

+3V_Mini2_VDD

Q15

Q15

2

R201 *3G@0_4R201 *3G@0_ 4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

1

R194

R210

R210

*3G@10K_ 4

*3G@10K_ 4

3G_SMDATAPDAT_SMB

1

1

ZE7

ZE7

ZE7

25 4 0Wednesday, November 02, 2011

25 4 0Wednesday, November 02, 2011

25 4 0Wednesday, November 02, 2011

1B

1B

1B

C384

C384
.1U/10V_4

.1U/10V_4

+3V_Mini2_VDD

52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18

16
14
12
10
8
6
4
2

+1.5V

+1.5V_Mini2 _VDD

WLAN_L ED1#
3G_MINI_L ED#

USBP5+_R
USBP5-_R

3G_SMDATA
3G_SMCLK

PLTRST#_1

UIM_VPP
UIM_RST
UIM_CLK
UIM_DATA
UIM_PWR

USBP5+ [10]
USBP5- [10]

R260 *0/J_8R260 *0 /J_8

+3V_Mini1_VDD+3V

+3V_Mini2_VDD

CLKREQ_3 G#

C390

C390
*10U/10V_8

*10U/10V_8

USBP5+_R
USBP5-_R

0.75A

C391

C391
.1U/10V_4

.1U/10V_4

51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17

15
13
11

9
7
5
3
1

CN19

CN19

Reserved
Reserved
Reserved
Reserved
GND
+3.3Vaux
+3.3Vaux
GND
GND
PETp0
PETn0
GND
GND
PERp0
PERn0
GND
UIM_C4
UIM_C8

GND
REFCLK+
REFCLK­GND
CLKREQ#
Reserved
Reserved
WAKE#

R508 3G@0_4R508 3G@0_4

R510 3G@0_4R510 3G@0_4

C382

C382
.1U/10V_4

.1U/10V_4

53

C386

C386
.1U/10V_4

.1U/10V_4

<2011/1/24(E1A)> Change from 10k to 100k to reduce leakage

+3.3V

GND

+1.5V

LED_WPAN#

LED_WLAN#

LED_WWAN#

GND

USB_D+

USB_D-

GND

SMB_DATA

SMB_CLK

+1.5V

GND

+3.3Vaux

PERST#

W_DISABLE#

GND

UIM_VPP

UIM_RESET

UIM_CLK

UIM_DATA

UIM_PWR

+1.5V

GND

+3.3V

GND54GND

3G@3G CONN

3G@3G CONN

+3VSUS

R531 *0/short_8R531 *0/short_8

R527 *0/J_8R527 *0 /J_8

C C

Mini Card 2 (MNC)

T39T39

PCIE_TXP3[10]
PCIE_TXN3[10]

PCIE_RXP3[10]

B B

PCIE_RXN3[10 ]

CLK_PCIE_MNC_P[2]
CLK_PCIE_MNC_N[2]

T42T42

T41T41

MultiMedia SIM (MNC)

A A

USBP4-[10]
USBP4+[10 ]

5

<Layout Notes> Keep USIM signals max length within 8000mils.

JSIM1

JSIM1

UIM_CLK

6

CLK(C3)
D-(C8)7VCC(C1)

8

D+(C4)

9

CT

10

CD

3G@SIM-CONN

3G@SIM-CONN

1

GND(C5)

2
3

VPP(C6)

4

RST(C2)

5

DATA(C7)

GND14GND12GND11GND

13

5

Card reader controller (MMC)

4

3

2

5 IN 1 Card Reader CONN (MMC)

1

26

HSIP
HSIN
REFCLKP
REFCLKN
AV12
HSOP
HSON
GND
DV12
Card1_3V3
3V3_IN
Card2_3V3

+3V3_IN

R319

R319
*100K_4

*100K_4

C286

C286
*1U/6.3V_ 4

*1U/6.3V_ 4

+3V3_IN

CARDREFXD_CD#

46

47

48

RREF

3V3_IN

RTS5209-GR

RTS5209-GR

VCC_XD VCC_XD

CN20

CN20

13

SD_CD#
SD_WP/ XD_D7
SD_D1_R
SD_D0_R
SD_CLK_R
SD_CMD_R
SD_D3_R
SD_D2_R
SD_D7/XD_ RDY
SD_D6/XD_ RE#
SD_D5/XD_ CE#
SD_D4/XD_ WE#

TP1TP1

TP2TP2

TP3TP3

EEDO

EECS

PLTRST#

EESK

41

42

43

44

45

EESK

EECS

EEDO

PERST#

CLK_REQ#

GPIO/EEDI

<Layout Note> Place Close to Chip Pin

R305 33/J_4R3 05 33/J_4

XD_D6

SD_WP/XD_D7

SD_CD#

MS_INS#

38

39

40

SP1437SP15

SD_CD#

MS_INS#

MS_CLK

C276 10P/50V _4C276 1 0P/50V_ 4

MS_D7/XD_ D5

36

SP13

MS_D3/XD_ D4

35

SP12

MS_D6/XD_ D3

34

SP11

MS_D2/XD_ D2

33

SP10

MS_D0/XD_ D1

32

SP9

MS_D4/XD_ D0

31

SP8

MS_D1/XD_ WP#

30

SP7

MS_D5/XD_ ALE

29

SP6

MS_BS/XD_CLE

28

SP5

DV12_S

27

DV12_S

GND

26

GND

SD_D2

R269 33/J_4R269 33 /J_4

25

SD_D2

<Layout Note> Place Close to Chip Pin

C255 4.7U/6.3V_6C255 4.7U/6.3V_6

C262 0.1U/10V _4C262 0.1U/10V _4

SD_D2_R

MS_BS/XD_CLE
MS_D1/XD_ WP#
MS_D0/XD_ D1
MS_D2/XD_ D2
MS_INS#
MS_D3/XD_ D4
MS_CLK

SD-VCC

1

SD-CD-SW

2

SD-WP-SW

3

SD-DAT1

4

SD-DAT0

10

SD-CLK

19

SD-CMD

23

SD-DATA3

25

SD-DAT2

5

MMC-DATA7

8

MMC-DATA6

17

MMC-DATA5

21

MMC-DATA4

7

SD-GND1

15

SD-GND2

26

SD-WP-GND

27

SD-CD-GND

22

MS-VCC

9

MS-BS

11

MS-DATA1

12

MS-DATA0

14

MS-DATA2

16

MS-INS

18

MS-DATA3

20

MS-SCLK

6

MS-GND1

24

MS-GND2

Card Reader CONN

Card Reader CONN

<20101206> Change to DFHS44FR015 by ME design change

VCC_XD

C297

C297

C381

C381

C376

C376

0.1u/10V _4

0.1u/10V _4

0.1u/10V _4

0.1u/10V _4

0.1u/10V _4

0.1u/10V _4

XD-VCC

XD-CD
XD-R/B

XD-RE

XD-CE
XD-CLE
XD-ALE

XD-WE
XD-WP

XD-D0

XD-D1

XD-D2

XD-D3

XD-D4

XD-D5

XD-D6

XD-D7

XD-GND1
XD-GND2
XD-GND3

C387

C387

4.7U/10V_8

4.7U/10V_8

45

28
29
30
31
32
33
34
35

37
38
39
40
41
42
43
44

36
46
47

XD_CD#
SD_D7/XD_ RDY
SD_D6/XD_ RE#
SD_D5/XD_ CE#
MS_BS/XD_CLE
MS_D5/XD_ ALE
SD_D4/XD_ WE#
MS_D1/XD_ WP#

MS_D4/XD_ D0
MS_D0/XD_ D1
MS_D2/XD_ D2
MS_D6/XD_ D3
MS_D3/XD_ D4
MS_D7/XD_ D5
XD_D6
SD_WP/ XD_D7

D D

PLTRST#[6,13,16,22,25,27]

CLKREQ_MMC#[2]

C289 0.1U/10V _4C289 0.1U/10V _4

R323 6.2K/F_4R323 6.2K/F_4

C C

U14

U14

AV12
PCIE_RXP2_C
PCIE_RXN2 _C

GND

DV12

VCC_XD

+3V3_IN

1
2
3
4
5
6
7
8

9
10
11
12

Zdiff = 80 ohm

Zdiff = 95 ohm

Zdiff = 80 ohm

B B

CLK_PCIE_MMC_P[ 2]
CLK_PCIE_MMC_N[2]

+3V

PCIE_TXP2[10]

PCIE_TXN2[10]

PCIE_RXP2[1 0]
PCIE_RXN2[10]

R332 *0/short_ 6R332 *0/short_6

C298

C298

4.7U/10V_8

4.7U/10V_8

C295 4.7U/6.3V_6C295 4.7U/6.3V_6
C292 0.1U/10V _4C292 0.1U/10V _4
C293 0.1U/10V _4C293 0.1U/10V _4

C294 0.1U/10V _4C294 0.1U/10V _4

C290

C290

0.1U/10V_4

0.1U/10V_4

TP4TP4

AV12

L33 *PBY1608 08T-601Y-N_1AL33 *PBY1608 08T-601Y-N_1A

A A

5

DV12

XD_CD#13DV33_1814GND15SP116SP217SP318SP419SD_D120SD_D021SD_CLK22SD_CMD23SD_D3

GND

DV33_18

SD_D7/XD_RDY

C288

C288
*4.7U/6.3V_6

*4.7U/6.3V_6

C287

C287

0.1U/10V_4

0.1U/10V_4

4

SD_D1

SD_D6/XD_RE#

SD_D5/XD_CE#

SD_D4/XD_WE#

24

<Layout Note> Place Close to Chip Pin

SD_D0

SD_CLK

SD_CMD

SD_D3

R286 33/J_4R2 86 33/J_4
R292 33/J_4R2 92 33/J_4
R303 33/J_4R3 03 33/J_4
R307 33/J_4R3 07 33/J_4
R315 33/J_4R3 15 33/J_4

SD_CLK_R

C274 10P/50 V_4C274 10P/50V_4

SD_D3_R
SD_CMD_R
SD_CLK_R
SD_D0_R
SD_D1_R

<EMI>

SD_D3_R

C282 *1 0P/50V_4C282 *10P/50V_4

SD_CMD_R

C284 *1 0P/50V_4C284 *10P/50V_4

SD_CLK_R

C291 *1 0P/50V_4C291 *10P/50V_4

SD_D0_R

C296 *1 0P/50V_4C296 *10P/50V_4

SD_D1_R

C392 *1 0P/50V_4C392 *10P/50V_4

SD_D2_R

C393 *1 0P/50V_4C393 *10P/50V_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

3

2

Date: Sheet of

PROJECT :

RTS5209-GR (Card Reader)

RTS5209-GR (Card Reader)

RTS5209-GR (Card Reader)

1

ZE7

ZE7

ZE7

1B

1B

26 40Wednesday, November 0 2, 2011

26 40Wednesday, November 0 2, 2011

26 40Wednesday, November 0 2, 2011

1B

5

EC (KBC)

+3VPCU

R504 2.2/J_6R504 2.2/J_6

1 2

D D

C C

L26 PBY160808T-250Y-N/3A/25ohm_6L26 PBY160808T-250Y-N/3A/25ohm_6

+3VPCU_EC

C177

C177

4.7U/6.3V_6

4.7U/6.3V_6

0.03A (30mils)

C182

C182

.1U/10V_4

.1U/10V_4

LFRAME#[13,25]
LAD0[13,25]
LAD1[13,25]
LAD2[13,25]
LAD3[13,25]

LCLK_EC[2]

CLKRUN#[13]

GA20[11]
KBRST#[11]

EC_SCI#[12]

EC_FPBACK#[18]

AMP_MUTE#[20]

PLTRST#[6,13,16,22,25,26]

SERIRQ[11]

EC_SMI#[13]

FOR CPU Thermal Sensor

C181

C181

.1U/10V_4

.1U/10V_4

RF_EN[25]

2ND_MBCLK[5]
2ND_MBDATA[5]

FOR VGA

B B

BT_POWERON#[19,25]

SUSCLK[13]

30mil

C267

C267

.1U/10V_4

.1U/10V_4

LCLK_EC

E791AGND

MX0
MX1
MX2
MX3
MX4
MX5
MX6
MX7

MY0
MY1
MY2
MY3
MY4
MY5
MY6
MY7
MY8
MY9
MY10
MY11
MY12
MY13
MY14
MY15

MBCLK
MBDATA
2ND_MBCLK
2ND_MBDATA

TPCLK
TPDATA

E791AGND

C374

C374

.1U/10V_4

.1U/10V_4

MX0[19]
MX1[19]
MX2[19]
MX3[19]
MX4[19]
MX5[19]
MX6[19]
MX7[19]

MY0[19]
MY1[19]
MY2[19]
MY3[19]
MY4[19]
MY5[19]
MY6[19]
MY7[19]
MY8[19]

MY9[19]
MY10[19]
MY11[19]
MY12[19]
MY13[19]
MY14[19]
MY15[19]

MBCLK[29]
MBDATA[29]

T23T23
T24T24

TPCLK[19]
TPDATA[19]

R161 *0/short_4R161 *0/short_4

R275 *0/short_4R275 *0/short_4

If PECI 3.0 access functionality is not used,
connect VTT pin to GND.

C232

C232

.1U/10V_4

.1U/10V_4

E775_32KX1

4

+A3VPCU

C202

C202

C211

C211

4.7U/6.3V_6

4.7U/6.3V_6

.1U/10V_4

.1U/10V_4

19

46

76

U10

U10

VCC1

VCC2

VCC3

3

LFRAME

126

LAD0

127

LAD1

128

LAD2

1

LAD3

2

LCLK

8

GPIO11/CLKRUN

121

GPIO85/GA20

122

KBRST/GPIO86

29

ECSCI/GPIO54

6

GPIO24/LDRQ

124

GPIO10/LPCPD

7

LREST

123

GPIO67/PWUREQ

125

SERIRQ

9

GPIO65/SMI

54

KBSIN0

55

KBSIN1

56

KBSIN2

57

KBSIN3

58

KBSIN4

59

KBSIN5

60

KBSIN6

61

KBSIN7

53

KBSOUT0/JENK

52

KBSOUT1/TCK

51

KBSOUT2/TMS

50

KBSOUT3/TDI

49

KBSOUT4/JEN0

48

KBSOUT5/TDO

47

KBSOUT6/RDY

43

KBSOUT7

42

KBSOUT8

41

KBSOUT9/SDP_VIS

40

KBSOUT10/P80_CLK

39

KBSOUT11/P80_DAT

38

KBSOUT12/GPIO64

37

KBSOUT13/GPIO63

36

KBSOUT14/GPIO62

35

KBSOUT15/GPIO61/XOR_OUT

34

GPIO60/KBSOUT16

33

GPIO57/KBSOUT17

70

GPIO17/SCL1

69

GPIO22/SDA1

67

GPIO73/SCL2

68

GPIO74/SDA2

119

GPIO23/SCL3

120

GPIO31/SDA3

72

GPIO37/PSCLK1

71

GPIO35/PSDAT1

10

GPIO26/PSCLK2

11

GPIO27PSDAT2

77

GPIO00/32KCLKIN

12

VTT

13

PECI

NPCE791L

NPCE791L

L24

L24
PBY160808T-250Y-N/3A/25ohm_6

PBY160808T-250Y-N/3A/25ohm_6

E791AGND

<Layout note>
Place every 0.1uF
close to every
power pin

88

102

115

VCC4

VCC5

AVCC

LPC

LPC

KB

KB

SMB

SMB

PS/2

PS/2

GND1

GND2

GND3

GND4

GND5

5

18

45

78

89

E791AGND

A/D

A/D

D/A

D/A

GPIO06/IOX_DOUT/RTS1

GPIO42/SCL3B/TCK

GPIO43/SDA3B/TMS

GPIO

GPIO

GPIO50/PSCLK3/TDO
GPIO52/PSDAT3/RDY

GPIO75/SPI_SCK

GPO82/IOX_LDSH/TEST

GPO84/IOX_SCLK/XORTR

GPIO20/TA2/IOX_DIN_DIO

TIMER

TIMER

GND6

116

GPIO15/A_PWM
GPIO21/B_PWM
GPIO13/C_PWM
GPIO32/D_PWM
GPIO45/E_PWM

GPIO40/F_PWM/RI1

GPIO66/G_PWM

GPIO33/H_PWM/SOUT1

GPIO87/CIRRXM/SIN_CR

GPIO34/SIN1/CIRRXL

IR

IR

GPIO46/CIRRXM/TRST

GPO83/SOUT_CR/TRIST

F_SDI/F_SDIO1

F_SDO/F_SDIO0

FIU

FIU

GPIO55/CLKOUT/IOX_DIN_DIO

VCORF

AGND

44

103

VCORF_uR

C375

C375

1U/6.3V_4

1U/6.3V_4

GPIO90/AD0
GPIO91/AD1
GPIO92/AD2
GPIO93/AD3

GPIO94/DA0

GPI95/DA1
GPI96/DA2

GPIO01/TB2

GPIO02
GPIO03
GPIO04
GPIO05

GPIO07
GPIO16
GPIO30

GPIO36/CTS1

GPIO41

GPIO44/TDI

GPO47/SCL4

GPIO51

GPIO53/SDA4

GPIO70
GPIO71
GPIO72

GPO76/SHBM

GPIO77
GPIO81

GPIO97

GPIO56/TA1
GPIO14/TB1

F_CS0
F_SCK

VCC_POR

VREF

3

10mA

+3V_EC

4

VDD

R281 *0/short_6R281 *0/short_6

D22 *RB500V-40D22 *RB500V-40

C272

C272

.1U/10V_4

.1U/10V_4

C186 .01U/16V_4C186 .01U/16V_4

E791AGND

97
98
99

ICMNT_EC

100

101
105
106

64
79
95

USBOC#R2_R

96

USBOC#R1_R

108
93
94

CHARGE_IC_ON

114
109
15

+3.3V_PRIME_ON

80

HWPG

17

THERM_ALERT#_R

20
21

USB_CHARGE_ON

24
25

S5_ON

26

HDMI_IN

27
28
73

PWROK_EC_uR

74

RSMRST#_uR

75
82
83
84

DNBSWON#_1

91
110
112
107

31
117
63

32
118
62
65
22
16
81
66

113
14
23
111

SPI_SDI_uR

86

SPI_SDO_uR SPI_SDO_uR_R

87

SPI_CS0#_uR

90

SPI_SCK_uR SPI_SCK_uR_R

92

ECDB_CLOCK

30

VCC_POR#

85

VREF_uR +A3VPCU

104

E791AGND

R182 *0/short_4R182 *0/short_4
C188 3300P/50V_4C188 3300P/50V_4

R155 *0/J_4R155 *0/J_4
R214 *0/J_4R214 *0/J_4

T56T56
T25T25

R276 *0/J_4R276 *0/J_4

T28T28

T27T27

R163 *0/short_4R163 *0/short_4
R162 *0/short_4R162 *0/short_4

T22T22

D10 RB500V-40D10 RB500V-40

T40T40

R156 22/J_4R156 22/J_4
R153 22/J_4R153 22/J_4

T26T26

R506 47K/J_4R506 47K/J_4
R206 *0/short_4R206 *0/short_4

+3V

<20090602(A1A)_Vendor suggest>
Place 10nF-0.1uF capacitors for

C281

C281

every AD input. And close to the AD

4.7U/6.3V_6

4.7U/6.3V_6

input.

TEMP_MBAT [29]

ICMNT [29]

ACIN [29]
NBSWON# [16,24]

USBOC#R [10,21]
USBOC#L [10,21]
LID# [18]

+3.3V_PRIME_ON [16,31,34]

THERM_ALERT# [5,6,13]

SUSB# [13,16]
D/C# [29]

S5_ON [16,30,35]

SUSC# [13,16]
ECPWROK [5,8,13,16]

EC_RSMRST# [13,16]
MAINON [16,32,33,34]
3G_EN [25]

DNBSWON# [13,16]

USB_EN# [21]

RTCRST#_EC [13]
SUSON [16,32,34]
FANSIG [6]

CONTRAST [18]

PCBEEP [20]

PWRLED# [24]

BATLED0# [24]

CPUFAN# [6]

SUSLED# [24]

BATLED1# [24]

+3VPCU

2

<20090721_FAE suggestion>
Stuff 100K and close to EC side
for improving power consumption

SPI_SDI_uR

R157

R157
100K/J_4

100K/J_4

1

I/O ADDRESS SETTING(KBC)

SHBM=0: Enable shared memory with host BIOS

3G_EN

SHBM

1/13 Comfirm by vendor mail :
Disabled ('1') if using FWH device on LPC.
Enabled ('0') if using SPI flash for both system BIOS and EC firmware

R160 10K/J_4R160 10K/J_4

SM BUS PU(KBC)

+3VPCU

*

MBCLK
MBDATA

2ND_MBCLK
2ND_MBDATA

1ST: Battery
2ND: CPU Thermal Sensor / DTS
3RD: VGA Thermal Sensor

<20090831(A1A)_EC team suggest>

1.change R166/R167 to 1M or 100K ohm

2.change PWR/SUS LED's power from +3VPCU to +3V_S5 or +3VSUS
can reduce pull-high resistor of SUSLED#/PWRLED#

R164 4.7K/J_4R164 4.7K/J_4
R165 4.7K/J_4R165 4.7K/J_4

R154 *4.7K/J_4R154 *4.7K/J_4

*

R169 *4.7K/J_4R169 *4.7K/J_4

BATLED0#
BATLED1#

*

+3V

*

*

R167 100K/J_4R167 100K/J_4
R166 100K/J_4R166 100K/J_4

<20110308> Change from +3V_S5 to
+3V for thermal sensor

+3VPCU

SPI FLASH(KBC)

1/13 Comfirm by vendor mail :
If the Southbridge enables 'Long Wait Abort' by default, the
flash device should be 50MHz (or faster)

U8

SPI_SDI_uR SPI_SDI_uR_R

+3VPCU

ZS9 A1~A3-test

ZS9 A4-test
ZS9 A5-test
ZS9 A6-test

R159 22/J_4R159 22/J_4

R158 10K/J_4R158 10K/J_4

SPI_SDO_uR_R
SPI_SCK_uR_R
SPI_CS0#_uR

W25Q16BVSSIG
W25Q16CVSSIG
MX25L1606EM2I-12G
MX25L1606EM2I-12G

ZS9 A7-test W25Q16BVSSIG

Winbond W25Q16BVSSIG AKE38FP0N01
EON EN25F16-75HCP AKE38ZA0Q00
MXIC MX25L1606EM2I-12G AKE38FP0Z01 (ZE6 MAC ID fail)

U8

2

SO

5

SI

6

SCK

1

CE

W25Q16BVSSIG

W25Q16BVSSIG

AKE38FP0N01
AKE38ZP0N02
AKE38FP0Z01
AKE38FP0Z01
AKE38FP0N01

VDD

HOLD

VSS

WP

8
7
3
4

16M bit
16M bit
16M bit
16M bit
16M bit

+3VPCU

27

C364

C364

0.1U/16V_4

0.1U/16V_4

INTERNAL KEYBOARD STRIP SET (KBC) HWPG (KBC)

A A

+3VPCU

RP5 10K/J_10P8RRP5 10K/J_10P8R

10

9
8
7 4

1
2
3

56

+3VPCU

MX4 MX2
MX5
MX6
MX7

MX3
MX1

MX0

5

10/26 UnStuff

MY0

R193 *10K/J_4R193 *10K/J_4

+3VPCU

HWPG_VCCGFX[31]
DDRAM_PWROK[8,32]

HWPG_1.8V[34]
SYS_HWPG[30]
IMVP_PWRGD[6,31]

4

<20110829> DDRAM_PWROK no need connecting to EC side

D17 *RB500V-40D17 *RB500V-40
D14 *RB500V-40D14 *RB500V-40
D19 RB500V-40D19 RB500V-40
D21 *RB500V-40D21 *RB500V-40
D13 *RB500V-40D13 *RB500V-40

HWPG_R

MAINON_ON_G[34]

R277 *0/short_4R277 *0/short_4

2

+3V

R278

R278

10K/J_4

10K/J_4

HWPG

3

Q28

Q28
2N7002K

2N7002K

1

3

HWPG [2,13,16]

LCLK_EC

R280

R280
*22/J_4

*22/J_4

C271

C271
*10P/50V_4

*10P/50V_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

PROJECT :

NPCE791L & FLASH

NPCE791L & FLASH

NPCE791L & FLASH

ZE7

ZE7

ZE7

1B

1B

27 40W ednesday, November 02, 2011

27 40W ednesday, November 02, 2011

1

27 40W ednesday, November 02, 2011

1B

<EMI>

5

4

3

2

1

HOLE (OTH)

D D

TOP(HDD Hole)

HOLE12

HOLE5

HOLE5

2
3
4

*HG-C276D98P2

*HG-C276D98P2

2
3

C C

4

*HG-TC276BC256D98P2

*HG-TC276BC256D98P2

2
3
4

*HG-TC276BC315D98P2

*HG-TC276BC315D98P2

1

8

HOLE9

HOLE9

1

8

HOLE7

HOLE7

1

8

5
6
7

9

5
6
7

9

5
6
7

9

HOLE8

HOLE8

2
3
4

*HG-C276D98P2

*HG-C276D98P2

2
3
4

*HG-C276D98P2

*HG-C276D98P2

2
3
4

*HG-TC276BC315D98P2

*HG-TC276BC315D98P2

1

8

9

HOLE14

HOLE14

1

8

9

HOLE2

HOLE2

1

8

9

5
6
7

5
6
7

5
6
7

HOLE12

2
3
4

*HG-C276D98P2

*HG-C276D98P2

2
3
4

* ZE7-P2

* ZE7-P2

2
3
4

*HG-TC276BC315D98P2

*HG-TC276BC315D98P2

1

8

HOLE16

HOLE16

1

8

HOLE3

HOLE3

1

8

5
6
7

9

5
6
7

9

5
6
7

9

HOLE15

HOLE15

2
3
4

1

8

9

*ZE7-P1

*ZE7-P1

HOLE4

HOLE4

2
3
4

1

8

9

*HG-C276D98P2

*HG-C276D98P2

HOLE1

HOLE1

2
3
4

1

8

9

*ZE7-P3

*ZE7-P3

2

5

3

6

4

7

*HG-C276D98P2

*HG-C276D98P2

2

5

3

6

4

7

*HG-TC276BC315D98P2

*HG-TC276BC315D98P2

5
6
7

HOLE13

HOLE13

1

8

HOLE10

HOLE10

1

8

HOLE6

HOLE6

1

*O-ZE6-2

*O-ZE6-2

5
6
7

9

5
6
7

9

BOT(Thermal Hole) BOT(Mini-PCIe Hole) LED ESD PAD TP ESD PAD

HOLE19

HOLE18

HOLE18

1

h-tc177bc295d120p2

h-tc177bc295d120p2

HOLE17

HOLE17

1

h-tc177bc295d120p2

h-tc177bc295d120p2

HOLE19

1

h-c197d63p2

h-c197d63p2

HOLE20

HOLE20

1

h-c197d63p2

h-c197d63p2

HOLE21

HOLE21

1

h-c197d63p2

h-c197d63p2

PAD1PAD1

28

PAD2PAD2

B B

A A

HOLE11

HOLE11

1

*O-ZE6-3

*O-ZE6-3

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Wednesday, November 02, 2011

Date: Sheet of

Wednesday, November 02, 2011

Date: Sheet of

5

4

3

2

Wednesday, November 02, 2011

PROJECT :

EMI/Hole

EMI/Hole

EMI/Hole

ZE7

ZE7

ZE7

1B

1B

1B

4028

4028

1

4028

1
2

3

ACIN[27]

5

PC85

PC85

0.1U/50V_6

0.1U/50V_6

TEMP_MBAT_C

PC6

PC6

47P/50V_4

47P/50V_4

PR27

PR27
100/J_4

100/J_4

5

VAVA

PR24 100/J_4PR24 100/J_4

47P/50V_4

47P/50V_4

PR26

PR26
100/J_4

100/J_4

PC84

PC84

2200P/50V_6

2200P/50V_6

+3VPCU

PC5

PC5

MBCLK [27]

MBDATA [27]

PL6

PL6

FBMA-11-201209-800A50T

FBMA-11-201209-800A50T

+3VPCU

PR59

PR59
100K/F_4

100K/F_4

PR25

PR25
100K_4

100K_4

PC8

PC8

0.1U/25V_4

0.1U/25V_4

Add ESD diode base on EC FAE suggestion

FBMA-11-201209-800A50T

FBMA-11-201209-800A50T

FBMA-11-201209-800A50T

FBMA-11-201209-800A50T

PC4

PC4
100P/50V_4

100P/50V_4

PU1

PU1
*CM1293A-04SO

*CM1293A-04SO

1

CH1

2

VN
CH23CH3

POWER_JACK

POWER_JACK

dcjk-2dc2003-000111-3p-v

dcjk-2dc2003-000111-3p-v

PJ1

PJ1

456

7

D D

C C

B B

PJ2

PJ2

1

10

2
3
4
5
6
7
89

Batt_Conn

Batt_Conn

bat-btj-08tc0b-8p-l-v

bat-btj-08tc0b-8p-l-v

PR23

PR23

*0/short_4

*0/short_4

A A

VA1

PC86

PC86

0.1U/50V_6

0.1U/50V_6

PD6

PD6
1SS355

1SS355

PL2

PL2

PL1

PL1

CH4

VP

4

PD7

PD7

SBR1045SP5-13

SBR1045SP5-13

TEMP_MBAT [27]

MBDATA

6
5

+3VPCU

MBCLKTEMP_MBAT

4

4

1

3

2

PD8

PD8

SMAJ20A(400W,20V)

SMAJ20A(400W,20V)

PR170

PR170

49.9/F_4

49.9/F_4

PR48

PR48

82.5K/F_4

82.5K/F_4

88731ACSET

PR51

PR51

22K/F_4

22K/F_4

BAT-VMBAT+

PC24

PC24

*1U/10V_4

*1U/10V_4

2 1

+3VPCU

PC34

PC34
1U/10V_4

1U/10V_4

MBDATA

MBCLK

DCIN

PC28

PC28

0.01U/25V_4

0.01U/25V_4

PC21

PC21

0.1U/25V_4

0.1U/25V_4

PC30

PC30
*0.01U/25V_4

*0.01U/25V_4

1

11

VDDSMB

9

SDA

10

SCL

13

ACOK

22

DCIN

2

ACIN

3

VREF

4

ICOMP

5

NC

6

VCOMP

PR57

PR57

2.21K/F_4

2.21K/F_4

PC33

PC33
.01U/25V_4

.01U/25V_4

NC

10/F_6

10/F_6

VIN

CSIP_1

PR42

PR42

GND33GND32GND31GND

30

NC

7

PC83

PC83

0.1U/50V_6

0.1U/50V_6

PC22

PC22

0.1U/25V_4

0.1U/25V_4

CSIP

28

CSSP

ISL88731C

ISL88731C

3

PU2

PU2

8

3

ICM

CSIN

27

ICMNT

CSSN

PR43

PR43
10/F_6

10/F_6

VA2

PR132

PR132
220K/F_6

220K/F_6

1 6

PR131

PR131

2

220K/F_6

220K/F_6

3

PQ39

PQ39

IMD2AT108

IMD2AT108

PC100

PC100

1U/10V_4

1U/10V_4

PR173

PR173

4.7/J_6

4.7/J_6

ISL88731_VDDP

21

26

VCC

VDDP

BOOT

UGATE

PHASE

LGATE

PGND

CSOP

CSON

GND
GND

NC

12

14

VBF

NC

88731B_2

25

ISL88731_UGATE

24

ISL88731_PHASE

23

ISL88731_LGATE

20

19

CSOP

18

CSON

17

16

15
29

PR47

PR47

2.7/J_6

2.7/J_6

PR58

PR58
*0/short_4

*0/short_4

ISL88731 thermal pad
tie to Pin12

ICMNT [27]

2

PR133

PQ38

PQ38
AO4427

AO4427

4

PC25

PC25

1U/10V_4

1U/10V_4

PD1

PD1
*RB500V-40

*RB500V-40
PC17

PC17

PR148

PR148
100/J_4

100/J_4

CSOP_1

BAT-V

8
7
6
5

PR134

PR134
*0/short_4

*0/short_4

4

4

BAT-V

1
2
3

5
4

0.1U/50V_6

0.1U/50V_6

88731B_1

PR55

PR55

10/F_6

10/F_6 PC26

PC31

PC31

0.1U/25V_4

0.1U/25V_4

PR56

PR56

10/F_6

10/F_6

PR133
.01_3216

.01_3216

1 2

CSIP_1 VIN

PC20

PC20

2200P/50V_4

2200P/50V_4

52

PQ1

PQ1
AON7410

AON7410

3

1

52

PQ50

PQ50

3

1

AON7410

AON7410

Close battery side

2

0.1U/50V_6

0.1U/50V_6

D/C# [27]

PC19

PC19

0.1U/50V_6

0.1U/50V_6

6.8uH/4.5A_7X7X3

6.8uH/4.5A_7X7X3

PR54

PR54

2.2/F_4

2.2/F_4

PC26
2200P/50V_4

2200P/50V_4

1

PQ41

PQ41
AO4427

PR157

PR157
33K/J_6

33K/J_6

PC91

PC91

1

AO4427

1
2
3

4

3

2

1

PC90

PC90

10U/25V_1206

10U/25V_1206

ZE7

ZE7

ZE7

PR156

PR156

10K/J_6

10K/J_6

PQ40

PQ40
2N7002K

2N7002K

29 40Wednesday, November 16, 2011

29 40Wednesday, November 16, 2011

29 40Wednesday, November 16, 2011

BAT-V

8
7
6
5

PC9

PC9
.01U/25V_4

.01U/25V_4

VIN

PC88

PC87

PC87

VIN

PC99

PC99

4.7U/25V_8

4.7U/25V_8

PL7

PL7

CSOP_1

BAT-V

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

PC88

2200P/50V_4

2200P/50V_4

.01_3216

.01_3216
PR155

PR155

1 2

PC10

PC10

2200P/50V_4

2200P/50V_4

10U/25V_1206

10U/25V_1206

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

CHARGER (ISL88731)

CHARGER (ISL88731)

CHARGER (ISL88731)

29

1B

1B

1B

MAIND

SUSD

5

MAIND [32,34]

SUSD [34]

SYS_SHDN#

4

SYS_SHDN# [6,35]

3

2

1

30

SYS_HWPG[27]

D D

+5VPCU

VIN

+5VPCU

PC44

PC44

4.7u/25V_8

4.7u/25V_8

PC45

PC45
2200p/50V_6

2200p/50V_6

PR75

PR75

*0/short_4

*0/short_4

52

5 Volt +/- 5%
TDC : 4.858A
PEAK : 6.5A
OCP : 8A
Width : 200mil

PR182

PC113

PC113

0.1u/50V_6

0.1u/50V_6

PR182

15.4K/F_4

15.4K/F_4

PR185

PR185
10K/F_4

10K/F_4

C C

+

+

PC46

PC46

220uF/6.3V_6X4.2

220uF/6.3V_6X4.2

PL3

PL3

2.2uH_7X7X3

2.2uH_7X7X3

PR188

PR188

4.7_6

4.7_6

PC112

PC112
680p/50V_6

680p/50V_6

OCP:8A

L(ripple current)
=(9-5)*5/(2.2u*0.4M*9)

B B

=2.525A
Iocp=8-(2.525/2)=6.74A

Vth=6.74A*14mOhm=94.32mV
R(Ilim)=(94.32mV*10)/10uA
~94.32K

+15V

PC51

PC51

0.1u/50V_6

0.1u/50V_6

PR191

PR191
22_8

22_8

PQ14

PQ14

AON7410

AON7410

PQ21

PQ21

AON7702

AON7702

+15V_ALWP

1

52

1

PD3

PD3
1PS302

1PS302

PD2

PD2
1PS302

1PS302

3

3

2

1

2

1

PC115

PC115

0.1u/50V_6

0.1u/50V_6

4

4

3

3

PC42

PC42

0.1u/50V_6

0.1u/50V_6

PC52

PC52

0.1u/50V_6

0.1u/50V_6

+3VPCU

PR73

PR73
100K/F_4

100K/F_4

PC50

PC50

0.1u/50V_6

0.1u/50V_6

PR76

PR76
1/F_6

1/F_6

PR82

PR82
665K/F_4

665K/F_4

SYS_SHDN#

8223_EN

PR84

PR84
100K/F_4

100K/F_4

PR83

PR83
330K/F_4

330K/F_4

+3V_PG
+5V_DH

+5V_LX
+5V_DL

+5V_FB

PR86

PR86
*0/short_6

*0/short_6

PC47

PC47

0.1u/25V_4

0.1u/25V_4

+5V_B

1 2

PR85

PR85
*0_6

*0_6

13
23
21
22
20
19
24

2

PR81

PR81

*0/short_4

*0/short_4

PC48

PC48

0.1u/10V_4

0.1u/10V_4

PR190

PR190
10_8

10_8

EN
PGOOD
UGATE1
BOOT1
PHASE1
LGATE1
VOUT1
FB1

+5V_DL

+3V_DL

8223_VIN

16

VIN

ENC

18

PR70

PR70

97.6K/F_4

97.6K/F_4

1

8223_EN

8

ENTRIP1

VREG3

PU3

PU3
RT8223M

RT8223M

PC38 4.7u/6.3V_6PC38 4.7u/6.3V_6

17

VREG5

ENTRIP2

6

PR69

PR69

48.7K/F_4

48.7K/F_4

VL

25

GND

PC49 4.7u/6.3V_6PC49 4.7u/6.3V_6

3

REF

SKIPSEL

TONSEL
UGATE2

BOOT2

PHASE2

LGATE2

OUT2

FB2

GND

15

8223REF +3VPCUVINVIN

14
4
10
9
11
12
7
5

PC37

PC37
1u/6.3V_4

1u/6.3V_4

PR186

PR186
*0/short_4

*0/short_4

+3V_SKIP
+3V_TON

+3V_DH
+3V_B
+3V_LX
+3V_DL

+3V_FB

PR71

PR71

*0/short_6

*0/short_6

PR68

PR68
*0/short_6

*0/short_6

PR78

PR78
1/F_6

1/F_6

PR189

PR189
*0_4

*0_4

PR72

PR72
*0_4

*0_4

PR67

PR67
*0/short_4

*0/short_4

PC43

PC43

0.1u/50V_6

0.1u/50V_6

PQ17

PQ17

AON7702

AON7702

52

PQ13

PQ13
AON7410

4

4

AON7410

3

1

52

3

1

OCP:4A

L(ripple current)
=(9-3.3)*3.3/(2.2u*0.5M*9)
~1.9A

Iocp=4-(1.9/2)=3.05A
Vth=3.05A*14mOhm=42.7mV
R(Ilim)=(42.7mV*10)/10uA
=42.7K

PL4

PL4

2.2uH_7X7X3

2.2uH_7X7X3

PR187

PR187

4.7_6

4.7_6

PC111

PC111
680p/50V_6

680p/50V_6

PC40

PC40
2200p/50V_6

2200p/50V_6

PC39

PC39

4.7u/25V_8

4.7u/25V_8

+3VPCU
3 Volt +/- 5%
TDC : 2.368A
PEAK : 3.16A
OCP : 4A
Width : 100mil

PR183

PR183

6.81K/F_4

6.81K/F_4

PR184

PR184
10K/F_4

10K/F_4

VIN

PC118

PC118

0.1u/50V_6

0.1u/50V_6

+3VPCU

+

+

PC58

PC58

220uF/6.3V_6X4.2

220uF/6.3V_6X4.2

+5V_S5+3V_S5

PR124

PR123

PR123
1M_6

1M_6

A A

S5_ON[16,27,35]

2

PQ32

PQ32

DTC144EU

DTC144EU

PR126

1 3

PR126
1M_6

1M_6

PR124
22/J_8

22/J_8

3

2

PQ33

PQ33
2N7002K

2N7002K

1

PR74

PR74
22/J_8

22/J_8

3

2

PQ16

PQ16
2N7002K

2N7002K

1

+15VVIN

PR125

PR125
1M_6

1M_6

S5D

3

2

1

PQ34

PQ34
2N7002K

2N7002K

3

2

1

MAIND MAIND

PQ35

PQ35
AO3404

AO3404

+5V_S5

TDC : 0.008A
PEAK : 0.01A
Width : 10mil

5

4

+5VPCU

3

2

PQ12

PQ12
AO3404

AO3404

1

TDC : 1.858A
PEAK : 2.477A
Width : 80mil

+3VPCU

3

2

PQ22

PQ22
AO3404

AO3404

1

+5V

+3V

TDC : 1.03A
PEAK : 1.38A
Width : 50mil

3

S5D

+3VPCU+5VPCU

3

TDC : 0.15A
PEAK : 0.2A

2

PQ15

PQ15
AO3404

AO3404

1

2

Width : 10mil

+3V_S5

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

+3VPCU

3

TDC : 0.94A

SUSD

2

SYSTEM 5V/3V (RT8206)

SYSTEM 5V/3V (RT8206)

SYSTEM 5V/3V (RT8206)

PEAK : 1.25A
Width : 40mil

PQ24

PQ24
AO3404

AO3404

1

+3VSUS

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

ZE7

ZE7

ZE7

1B

1B

30 40Wednesday, November 02, 2011

30 40Wednesday, November 02, 2011

30 40Wednesday, November 02, 2011

1

1B

5

4

3

2

1

31

+5V_S58165_VCC

PC123

PC123
*22U/25V_1210

8165_VCC

PC89

D D

PR32

PR32

100/F_4

100/F_4

VCCGFX

GTVCC_SENSE[7]

GTVSS_SENSE[7]

Place close to VR

+1.05V

PR19 54.9/F_4PR19 54.9/F_4
PR15 110/F_4PR15 110/F_4
PR1 *90.9/F_4PR1 *90.9/F_4

C C

PR12 100/J_4PR12 100/J_4

+3V

PR14 10K/F_4PR14 10K/F_4
PR13 10K/F_4PR13 10K/F_4

B B

PR168

PR168
10K_6_NTC

10K_6_NTC

place close to
GFX inductor

A A

PC2

PC2

1u/10V_4

1u/10V_4

8165_VCLK
8165_VDIO
8165_ALERT#
8165_VRHOT#

8165_VRA
8165_VR

8165_VCC

PR18

PR18

10K/F_4

10K/F_4

PR16

PR16
750/F_4

750/F_4

8165_TSENA 8165_TSEN

PR9

PR9
1K/F_4

1K/F_4

5

PR20

PR20
10K/F_4

10K/F_4

PR17

PR17
750/F_4

750/F_4

PR7

PR7
1K/F_4

1K/F_4

PR172

PR172
10K_6_NTC

10K_6_NTC

place close to
Vcore inductor

PC1

PC1
1u/10V_4

1u/10V_4

+VCC_CORE

CPUVCC_SENSE[7]

CPUVSS_SENSE[7]

HWPG_1.05V[16,33,34]

+3.3V_PRIME_ON[16,27,34]

PR28

PR28

100/F_4

100/F_4

8165_VCC

PR137 51K/F_4PR137 51K/F_4
PR138 274K/F_4PR138 274K/F_4
PR139 182K/F_4PR139 182K/F_4
PR141 21K/F_4PR141 21K/F_4
PR140 11.8K/F_4PR140 11.8K/F_4
PR135 16.9K/F_4PR135 16.9K/F_4
PR136 16.9K/F_4PR136 16.9K/F_4
PR145 *0_4PR145 *0_4

PR158

PR158
100/F_4

100/F_4

PR151

PR151
100/F_4

100/F_4

PC7

PC7

100p/50V_4

100p/50V_4

PR35

PR35
750/F_4

750/F_4

for compensation fine
tune

PR153

PR153

*0/short_4

*0/short_4

VR_SVID_CLK[6]
VR_SVID_DATA[6]
VR_SVID_ALERT#[6]
HWPG_VCCGFX[27]
IMVP_PWRGD[6,27]
H_PROCHOT#[6]

PR50 0_4PR50 0_4

For HW Debug

PR49 *0_4PR49 *0_4

PC3

PC3
470p/50V_4

470p/50V_4

PR30

PR30

2.55K/F_4

2.55K/F_4

for droop fine tune

PR152

PR152

*0/short_4

*0/short_4

PR3 10K/F_4PR3 10K/F_4

PR147 10K/F_4PR147 10K/F_4

PR29

PR29
*0/short_4

*0/short_4

PR22

PR22
*0/short_4

*0/short_4

PR2 10K/F_4PR2 10K/F_4

PR34

PR34
11K/F_4

11K/F_4

PR31

PR31
10K/F_4

10K/F_4

PR8 10K/F_4PR8 10K/F_4

PR39

PR39
*0/short_4

*0/short_4

PR150 *0/short_4PR150 *0/short_4
PR149 *0/short_4PR149 *0/short_4
PR146 *0/short_4PR146 *0/short_4
PR144 *0/short_4PR144 *0/short_4
PR143 *0/short_4PR143 *0/short_4
PR142 *0/short_4PR142 *0/short_4

PR40

PR40
100K_4

100K_4

PR36

PR36
*0/short_4

*0/short_4

PR6 2.21K/F_4PR6 2.21K/F_4

PR4 33K/F_4PR4 33K/F_4

PR5 5.1K/F_4PR5 5.1K/F_4

PR10 10K/F_4PR10 10K/F_4

4

PC12

PC12
33P/50V_4

33P/50V_4

PR41

PR41

88.7K/F_4

88.7K/F_4

PR44

PR44

*0/short_4

*0/short_4

PR38

PR38

88.7K/F_4

88.7K/F_4

8165_TEMPMAX
8165_ICCMAX
8165_ICCMAXA
8165_OCSETA
8165_OCSET
8165_SETINIA
8165_SETINI
8165_GFXPS2

PC11

PC11
36p/50V_4

36p/50V_4

PC89

4.7u/6.3V_6

4.7u/6.3V_6

8165_FBA

27

8165_COMPA

28

8165_RGNDA

26

8165_VCLK

25

8165_VDIO

24

8165_ALERT#

23

8165_VRA

22

8165_VR

21

8165_VRHOT#

20

8165_EN

32

8165_TEMPMAX

12

8165_ICCMAX

13

8165_ICCMAXA

14

8165_OCSET

16

8165_OCSETA

18

8165_SETINI

11

8165_SETINIA

10

8165_TSEN

15

8165_TSENA

17

8165_FB

6

8165_COMP

5

8165_RGND

7

8165_GFXPS2

Temp max=100C
VICCMAX=164mV, /19.2mV=8.563
VICCMAXA=68mV, /19.2mV=3.532
OCSETA=2.619V
OCSET=2.56V
VBOOTA=1V
VBOOT=1V
GFX Not force PS2

9

VCC

FBA

COMPA

RGNDA

VCLK
VDIO
ALERT
VRA_READY
VR_READY
VRHOT

EN

TEMPMAX
ICCMAX
ICCMAXA
OCSET
OCSETA
SETINI
SETINIA
TSEN
TSENA

FB

COMP

RGND

GFXPS2

8

PR21 *0/short_8PR21 *0/short_8

PR33 *0/short_8PR33 *0/short_8

PR37

PR37
2_6

2_6

PU8

PU8
RT8167BGQW

RT8167BGQW

19

8165_IBIAS

37

PVCC

IBIAS

PR11

PR11

53.6K/F_4

53.6K/F_4

TONSETA

UGATEA

BOOTA

PHASEA

LGATEA

ISENAP

ISENAN

TONSET

UGATE1

BOOT1

PHASE1

LGATE1

ISEN1P

ISEN1N

GND

PC98

PC98

4.7u/6.3V_6

4.7u/6.3V_6

3

31

34

33

35

36

30

29

2

40

1

39

38

3

4

41

8165_TONSETA

8165_DH2

8165_BOOTA

8165_LX2

8165_DL2

8165_ISENAP

8165_ISENAN

8165_TONSET

8165_DH1

8165_BOOT1

8165_LX1

8165_DL1

PR46

PR46
130K/F_4

130K/F_4

PR166

PR166

2.2_6

2.2_6

0.22U/25V_6

0.22U/25V_6

PC94

PC94
*0.1u/10V_4

*0.1u/10V_4

PC15

PC15
*0.1u/50V_6

*0.1u/50V_6

PR169

PR169

2.2_6

2.2_6

8165_ISEN1P

8165_ISEN1N

PC13

PC13
*0.1u/50V_6

*0.1u/50V_6

for noise filtering,
place close to
RT8165B

PC96

PC96

PR45

PR45
130K/F_4

130K/F_4

PC23

PC23

0.1u/25V_6

0.1u/25V_6

PC97

PC97

0.22U/25V_6

0.22U/25V_6

PC93

PC93
*0.1u/10V_4

*0.1u/10V_4

PR53

PR53

4.7_6

4.7_6

PC18

PC18

0.1u/25V_6

0.1u/25V_6

PR52

PR52

4.7_6

4.7_6

PQ5

PQ5
AON7410

AON7410

PQ3

PQ3
AON7702

AON7702

4

PQ2

PQ2
AON7410

AON7410

4

PQ4

PQ4
AON7702

AON7702

52

4

3

52

4

3

Rsense=4.24m-ohm

Rsense=12.63m-ohm

1

1

*22U/25V_1210

<20110428> For EMI request

52

3

1

52

PC108

PC108

3

1

*1000P/50V_6

*1000P/50V_6

<20110428> For EMI request

PC29

PC29
2200P/50V_4

2200P/50V_4

PR174

PR174
*2.2/F_6

*2.2/F_6

PC101

PC101
*1000P/50V_6

*1000P/50V_6

2

PC124

PC124
*22U/25V_1210

*22U/25V_1210

PC27

PC27
2200P/50V_4

2200P/50V_4

PR175

PR175
*2.2/F_6

*2.2/F_6

PC104

PC104

0.1u/50V_6

0.1u/50V_6

L=1.5uH, typ.DCR=14m-ohm

PL9

PL9

1.5uH_7X7X3

1.5uH_7X7X3

PR162

PR162

3.57K/F_4

3.57K/F_4

PC102

PC102

PC103

PC103

0.1u/50V_6

0.1u/50V_6

4.7u/25V_8

4.7u/25V_8

L=2.2uH, typ.DCR=18m-ohm

PL8

PL8

2.2uH_7X7X3

2.2uH_7X7X3

PR163

PR163

6.98K/F_4

6.98K/F_4

PR165

PR165

1.15K/F_4

1.15K/F_4

PC106

PC106

4.7u/25V_8

4.7u/25V_8

PR160

PR160
*0/short_4

*0/short_4

PC92 0.1u/25V_4PC92 0.1u/25V_4

1K_6_NTC(B=3650)

1K_6_NTC(B=3650)

PR164

PR164
1K/F_4

1K/F_4

PR161

PR161
*0/short_4

*0/short_4

PC95

PC95

0.1u/25V_4

0.1u/25V_4

PR167

PR167

1K_6_NTC(B=3650)

1K_6_NTC(B=3650)

PR159

PR159
1K/F_4

1K/F_4

PC105

PC105

4.7u/25V_8

4.7u/25V_8

PC109

PC109

0.1u/50V_6

0.1u/50V_6

PR171

PR171

PR154

PR154
1K/F_4

1K/F_4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

CPU CORE (RT8165B)

CPU CORE (RT8165B)

CPU CORE (RT8165B)

Date: Sheet of

Date: Sheet of

Date: Sheet of

VIN

PC127

PC127
*22U/25V_1210

*22U/25V_1210

VIN

VCCGFX

PC16

PC16

0.1u/50V_6

0.1u/50V_6

VCCGFX
TDC : 2.58A
PEAK : 3.44A
OCP : 9A
Width : 120mil

VIN

+

+

+

+

330U/2V_7343

330U/2V_7343

PC32

PC32

PC107

PC107

*330u/2V_7343

*330u/2V_7343

+VCC_CORE
TDC : 3.18A
PEAK : 4.23A
OCP : 10.4A
Width : 160mil

Load-line = -5.9mv/A
for Cedar trial-M

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

ZE7

ZE7

ZE7

1

assume
ESR=9m-ohm

+

+

PC14

PC14

330u/2V_7343

330u/2V_7343

assume
ESR=9m-ohm

31 40Wednesday, November 02, 2011

31 40Wednesday, November 02, 2011

31 40Wednesday, November 02, 2011

+VCC_CORE

1B

1B

1B

5

4

3

2

1

32

[PWM]

PC67

PC67
10U/10V_8

20mil

0.375A

D D

+0.75V_DDR_VTT

10mil

PC60

PC60

10U/10V_8

10U/10V_8

+1.5VSUS

PC59

PC59
10U/10V_8

10U/10V_8

0.188A

+SMDDR_VREF

PC56

PC56

0.033U/50V_6

0.033U/50V_6

+5V_S5

C C

PR97

PR97

*0/short_6

*0/short_6

PR96

PR96

*0/short_6

*0/short_6

10U/10V_8

24

25

VTT

GND

1

VTTGND

2

VTTSNS

3

GND

4

MODE

5

VTTREF

6

COMP

NC7VDDQSNS8VDDQSET9S310S511NC

23

VLDOIN

22

VBST

PU5

PU5
RT8207L

RT8207L

8207A_VBST

21

DRVH

S3_1.8V

PR100

PR100
*0/J_4

*0/J_4

PR111

PR111

*0/short_6

*0/short_6

19LL20

DRVL

PGND

CS_GND

CS

V5IN

V5FILT

PGOOD

12

S5_1.8V

PR118 *0/short_4PR118 *0/short_4

PR113 *0/short_4PR113 *0/short_4

+5V_S5

18

17

16

15

14

13

PR120

PR120
620K/F_4

620K/F_4

0.1U/50V_6

0.1U/50V_6

PC73

PC73

8207A_DH
8207A_LX
8207A_DL

PR119

PR119
13K/F_4

13K/F_4

PR122

PR122

5.1/F_6

5.1/F_6

PC77

PC77
1U/10V_4

1U/10V_4

PR121 *100K/F_4PR121 *100K/F_4

PR198 0/J_4PR198 0/J_4

(For RT8207A 400KHZ) close to PC2016

VIN

SUSON [16,27,34]

MAINON [16,27,33,34]

+3V_S5

+5V_S5

12

PC76

PC76
1U/10V_4

1U/10V_4

<20110728> Change DDRAM_PWROK PU from +3V_S5 to +1.5VSUS (no connect at EC side )

DDRAM_PWROK [8,27]

PQ25

PQ25

AON7410

AON7410

PQ28

PQ28

AON7702

AON7702

VIN

52

4

PL5

3

1

PL5

2.2uH_7X7X3

2.2uH_7X7X3

PC63

PC63

2200P/50V_6

2200P/50V_6

PC65

PC65

4.7U/25V_8

4.7U/25V_8

PC66

PC66

4.7U/25V_8

4.7U/25V_8

+1.5VSUS

+1.5VSUS

52

4

3

1

PR115

PR115
*4.7/J_6

*4.7/J_6

PC72

PC72
*680p/50V_6

*680p/50V_6

+

+

PC61

PC61
330U/2V_7343

330U/2V_7343

PC64

PC64
10U/10V_8

10U/10V_8

1.5 Volt +/- 5%
TDC : 4.32A
PEAK : 5.76A
OCP : 10A
Width : 200mil

PR103

PC68

PC68

*33P/50V_6

B B

A A

5

*33P/50V_6

PR103
10K/F_4

10K/F_4

8207A_SET

PR110

PR110
10K/F_4

10K/F_4

Vout = (PR150/PR149) X 0.75 + 0.75

PR117 *0/J_4PR117 *0/J_4

4

S3_1.8VS5_1.8V

MAIND[30,34]

MAIND

+1.5VSUS

3

2

PQ11

PQ11
AO3404

AO3404

1

TDC : 1.24A
PEAK : 1.65A
Width : 60mil

3

+1.5V

AON7702 Rdson=11~14mOhm

L(ripple current)
=(19-1.5)*1.5/(2.2u*400k*19)
~1.57A

Vtrip= (10-1.57/2)*14mohm=0.12901V
RILIM=Vtrip/10uA~12.901Kohm

S3 S5

S0

S3

S4/S5

2

1 1

0 0

10

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

ON ON ON

ON ON

OFF

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

DDR 1.5V(TPS51116)

DDR 1.5V(TPS51116)

DDR 1.5V(TPS51116)

1

VTTREF+1.5VSUS

OFF

OFFOFF

ZE7

ZE7

ZE7

1B

1B

32 40Wednesday, November 02, 2011

32 40Wednesday, November 02, 2011

32 40Wednesday, November 02, 2011

1B

5

4

3

2

1

33

[PWM]

+5V_S5

D D

PD4

PR104

PR104
*0/short_6

*0/short_6

PD4
RB500V-40

RB500V-40

PC69

PC69

0.1U/50V_6

0.1U/50V_6

PC70

PC70
1U/10V_4

1U/10V_4

R1

R2

UGATE-1.05V
PHASE-1.05V

PR108

PR108
3K/F_4

3K/F_4

LGATE-1.05V

PR88

PR88

4.02K/F_4

4.02K/F_4

PR93

PR93
10K/F_4

10K/F_4

12

PC74

PC74

4.7U/10V_6

4.7U/10V_6

PC53

PC53
*33P/50V_6

*33P/50V_6

*0/short_6

*0/short_6

52

4

PQ45

PQ45
AON7410

AON7410

3

1

52

4

PQ51

PQ51
AON7702

AON7702

3

1

VOUT=(1+R1/R2)*0.75

PR94

PR94

PR89

PR89
10/J_6

10/J_6

PR114

PR114

2.2/F_6

BOOT

UGATE

PHASE

VDDP

LGATE

PGND

TPAD

1.05V_FB

OC

2.2/F_6

13
12
11
10
9
8
7
17

PR92

PR92
1M/F_4

1M/F_4

PR99

PR99
33K/J_4

MAINON[16,27,32,34]

PR90

PR90
10K/J_4

10K/J_4

C C

HWPG_1.05V[16,31,34]

B B

+3V

33K/J_4

PC57

PC57

0.1U/50V_6

0.1U/50V_6

1U/10V_4

1U/10V_4

PC54

PC54

PC55

PC55

*1000P/50V_6

*1000P/50V_6

PU4 G5602PU4 G5602

15

EN/DEM

16

TON

1

VOUT

2

VDD

3

FB

4

PGOOD

6

GND

5

NC

14

NC

PC121

PC121

2.2n/50V_4

2.2n/50V_4

2.2uH_7X7X3

2.2uH_7X7X3

PR192

PR192
*4.7/J_6

*4.7/J_6

PC119

PC119
*680p/50V_6

*680p/50V_6

PL10

PL10

PC114

PC114

330U/2.5V

330U/2.5V

PC122

PC122

4.7U/25V_8

4.7U/25V_8

+

+

PC116

PC116
*10U/10V_8

*10U/10V_8

12

PC117

PC117
.1U/10V_4

.1U/10V_4

+1.05V

+1.05V

1.05 Volt +/- 5%
TDC : 1.36A
PEAK : 1.82A
OCP : 5A
Width : 60mil

VIN

PR95

TON=3.85p*RTON*Vout/(Vin-0.5)

Frequency=Vout/(Vin*TON)

A A

TON=3.85p*1M*1/(Vin-0.5)

AON7702 Rdson=11~14mOhm

L(ripple current)
=(19-1.05)*1.05/(2.2u*272k*19)
~1.658A

Rth=14m*(5-0.829)/20uA

Frequency=1/(0.0036767)=272K

5

RILIM=2.92Kohm

4

3

PR95

*0/short_6

*0/short_6

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

ZE7

ZE7

1

ZE7

1B

1B

1B

33 40Wednesday, November 02, 2011

33 40Wednesday, November 02, 2011

33 40Wednesday, November 02, 2011

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

+1.05V(UP6111AQDD)

+1.05V(UP6111AQDD)

+1.05V(UP6111AQDD)

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

PROJECT :

5

VIN

PR194

PR194
1M/J_4

1M/J_4

PR193

PR193

PQ46

PQ46

SUSON[16,27,32]

D D

2

1 3

DTC144EU

DTC144EU

1M/J_4

1M/J_4

2

+1.5VSUS

3

1

PR195

PR195
*22/J_8

*22/J_8

PQ47

PQ47
*DMN601K-7

*DMN601K-7

2

4

+3VSUS +15V

PR197

PR197
22/J_8

22/J_8

3

2

PQ48

PQ48
2N7002K

2N7002K

1

3

2

1

34

PR196

PR196
1M/J_4

1M/J_4

SUSDSUS_ON_G

3

PQ49

PQ49
2N7002K

2N7002K

1

PC120

PC120
*2200P/50V_4

*2200P/50V_4

SUSD [30]

VIN

PR98

PR101

PR91

PR91
1M/J_4

1M/J_4

PR87

PR87

PQ23

PQ23

MAINON[16,27,32,33]

C C

2

1 3

MAINON_ON_G

DTC144EU

DTC144EU

1M/J_4

1M/J_4

MAINON_ON_G [27]

PR101
22/J_8

22/J_8

3

2

PQ26

PQ26
2N7002K

2N7002K

1

PR98
22/J_8

22/J_8

3

2

1

PQ27

PQ27
2N7002K

2N7002K

3

2

1

Reserve For VCCGFX

B B

PR80

PR80
*22/J_8

*22/J_8

PQ20

PQ20
*DMN601K-7

*DMN601K-7

+1.5V

PR79

PR79
22/J_8

22/J_8

3

2

PQ18

PQ18
2N7002K

2N7002K

1

+15V+5V+3V +1.05V

PR77

PR77
1M/J_4

1M/J_4

MAINDMAINON_ON_G

3

2

PQ19

PQ19
2N7002K

2N7002K

1

PC41

PC41
*2200P/50V_4

*2200P/50V_4

MAIND [30,32]

+1.8V

1.8Volt +/- 5%
TDC : 0.113A
PEAK : 0.151A
Width : 20mil

+1.8V

PC79

PC79

10U/10V_8

10U/10V_8

PR129

PR129
261/F_4

261/F_4

PC82

PC82

10U/10V_8

10U/10V_8

PR130

PR130
100/F_4

100/F_4

Vout1 = (1+Rg/Rh)*0.5

PQ29

PQ29
AO4468

AO4468

1
2
3 6

Rg

Rh

4

PR107

PR107
47/F_4

47/F_4

PC62

PC62
33N/25V_4

33N/25V_4

8
7

5

+3VSUS

PC81

PC81
10U/10V_8

10U/10V_8

PU7

PU7
G9334 ADJ

G9334 ADJ

5

PGD

DRV

EN

3

FB

VCC

GND

2

PR105 *30K/F_4PR105 *30K/F_4

12

4

1

6

PC80

PC80
.1U/10V_4

.1U/10V_4

+5V

12

PC71

PC71
.1U/10V_4

.1U/10V_4

+3V

PR102

PR102
100K_4

100K_4

HWPG_1.8V [27]

12

PC110

PC110
*0.1U/10V_4

*0.1U/10V_4

PR181 0/J_4PR181 0/J_4
PR180 *0/J_4PR180 *0/J_4

+3.3V_PRIME_ON

<20100902> reserve for H/W debug

<20101217> Reserve 30K for Duncan suggestion

VIN VCCGFX

PR176

PR176
*1M/J_4

*1M/J_4

PR177

PR177

PQ42

PQ42

HWPG_1.05V[16,31,33]

A A

2

5

*DTC144EU

*DTC144EU

1 3

*1M/J_4

*1M/J_4

PR178

PR178
*22/J_8

*22/J_8

3

2

PQ43

PQ43
*DMN601K-7

*DMN601K-7

1

For +3V_PRIME

+3.3V_PRIME_ON[16,27,31]

MAINON_ON_G

4

PR66 *0/short_4PR66 *0/short_4

PR65 *0/short_4PR65 *0/short_4

2

3

PC35

PC35

*1U/10V_4

2

*1U/10V_4

PQ9

PQ9
2N7002K

2N7002K

1

12

PR63

PR63
*100K_4

*100K_4

3

PQ7

PQ7
DTC144EU

DTC144EU

1 3

VIN

PR62

PR62
1M/J_4

1M/J_4

PR60

PR60
1M/J_4

1M/J_4

PR179

PR179
22/J_8

22/J_8

3

2

PQ44

PQ44
2N7002K

2N7002K

1

+1.8V

PR61

PR61
22/J_8

22/J_8

3

2

PQ8

PQ8
2N7002K

2N7002K

1

2

+15V+3.3V_PRIME

PR64

PR64
1M/J_4

1M/J_4

3

2

PQ6

PQ6
2N7002K

2N7002K

1

+3V

3

2

PQ10

PQ10
AO3404

AO3404

1

PC36

PC36
*2.2n/50V_4

*2.2n/50V_4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Discharge/1.8V

Discharge/1.8V

Discharge/1.8V

Date: Sheet of

Date: Sheet of

Date: Sheet of

+3.3V_PRIME

TDC : 0.17A
PEAK : 0.22A
Width : 10mil

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

ZE7

ZE7

ZE7

34 40Wednesday, November 02, 2011

34 40Wednesday, November 02, 2011

1

34 40Wednesday, November 02, 2011

1B

1B

1B

1

2

3

4

5

Thermal Protection (DCD)

VIN

A A

S5_ON

PR112

PR112

1.5K/F_4

1.5K/F_4

VLVL

B B

Thermal protection temperature = 70C

<20111018>
Change PR112 from CS22212FB11 to CS21502FB14,
for change M/B from 60 to 70℃ ℃

PR116

PR116

10K/J(NTC) _6

10K/J(NTC) _6

3

C C

S5_ON[16,27,30]

2

PQ31

PQ31
2N7002K

2N7002K

1

PR106

PR106
200K/F_4

200K/F_4

2.52V

2.469V

PR109

PR109
200K/F_4

200K/F_4

2

PQ37

PQ37

DTC144EU

DTC144EU

3
2

84

+

+

-

-

PD5

PD5
1SS355

1SS355

PR127

PR127
1M/F_4

1M/F_4

TSNS_ON

1 3

PC75

PC75

0.1U/25V_4

0.1U/25V_4

1

PU6A

PU6A
AS393MTR-E1

AS393MTR-E1

1

PQ30

PQ30
AO3409

3

PR128

PR128
200K/F_4

200K/F_4

PC78

PC78

0.1U/25V_4

0.1U/25V_4

AO3409

SYS_SHDN# [6,30]

3

2

PQ36

PQ36
2N7002K

2N7002K

1

2

35

5

+

+

-

-

PU6B

PU6B
AS393MTR-E1

AS393MTR-E1

7

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

3

4

Date: Sheet of

PROJECT :

Thermal protect

Thermal protect

Thermal protect

ZE7

ZE7

ZE7

1B

1B

1B

35 40Wednesday, November 02, 2011

35 40Wednesday, November 02, 2011

35 40Wednesday, November 02, 2011

5

6

D D

1

2

5

D D

LVDS_CLKP/N

DDR_CLK0P/N

DDR_CLK1P/N

DDR3 SO-DIMM0

Page 4

C C

10.1" LED Panel

Page 18

(400/533MHz)

(400/533MHz)

(Max. 112MHz)

Cedarview-M

DDR_CLK2P/N

DDR_CLK3P/N

HPLLREFCLK_P/N

DPL_REFSSCLKIN_P/N

DPLREFCLK_P/N

LVDS_CLKP/N

Page 5~9

HDMI

Page 17

B B

(Max. 340MHz)

DDI0_TXP/N3

4

DDR3REF_P/N

DMICLKIN_P/N

AZIL_BCLK

(100/133MHz)

(100/133MHz)

(100MHz)

(100MHz)

(96MHz)

CPU_ITPP/N

CLOCK GEN CK505
SLG8LV631V

CPU_0P/N

CPU_1P/N

LCD_CLKP/N

SRC_P/N

DOT_96P/N

Page 2

3

SRC_P/N

PCI_33

SATAP/N

SRC_P/N

USB_48

REF

PCI_33

SRC_P/N

(100MHz)

(33MHz)

(100MHz)

(100MHz)

(48MHz)

(14.318MHz)

(33MHz)

(100MHz)

2

WLAN(Mini Card 1)

Debug Card

Page 25

SATACLKP/N

Tigerpoint

DMICLK100P/N

CLK48

CLK14

PCICLK

BIT_CLK

SUSCLK

Page 10~15

Y4(32.768K KHz)

EC
WPCE791L

SPICLK

Page 27

Card Reader
RTS5209-GR

(24MHz)

(32.768KHz)

(33MHz)

1

36

To CPU

Audio
ALC271X

Page 20

SPI Flash

Page 27

Page 26

Y3(27 MHz)

SRC_P/N

(24MHz)

A A

5

4

From TPT

SRC_P/N

Y2(14.318 MHz)

3

(100MHz)

(100MHz)

LAN
RTL8105TA-VC-CG

Page 22

WLAN(Mini Card 2)

Page 25

2

Y5(25 MHz)

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

PROJECT :

Clock Distribution Diagram

Clock Distribution Diagram

Clock Distribution Diagram

ZE7

ZE7

ZE7

36 40Wednesday, November 02, 2011

36 40Wednesday, November 02, 2011

36 40Wednesday, November 02, 2011

1

1B

1B

1B

5

CPU core

(RT8165)

PU8

VIN

D D

C C

VIN

+1.05V
(G5602)

PU4

SYSTEM

5V/3V

(RT8223)

+5VPCU

(6.517A)

PU3

+3VPCU

(3.034A)

4

+VCC_CORE(0.75V-1.18V,4.234A)

<HWPG_1.05V>

VCCGFX(0.76V~1.05V,3.438A)

<HWPG_1.05V>

+1.05V(1.8164A)

<MAINON+RC>

+5VPCU(4.03A)

<AC/DC Insert>

AO3404

PQ35

AO3404

PQ12

+3VPCU(55mA)

<AC/DC Insert>

AO3404

PQ15

AO3404

PQ24

+5V_S5(10mA)

<S5D>

+5V(2.477A)

<MAIND>

+3V_S5(197mA)

<S5D>

+3VSUS(1.1A)

<SUSD>

3

2

1

37

BOM Structure

Description

w/o 3G module
w/ BT module
w/o BT module
w/ LVDS (default)

w/ EDP

stuff 3G@
unstuff 3G@
stuff BT@
unstuff BT@
stuff LVDS@

L38: CV+1003JN01 (0.1UH)
C334: CH5102K9B06 (1UF)

stuff EDP@
L38: CS00003J951 (0ohm)
C334:CS00002JB38 (0ohm)

stuff 1.5VPLL@
stuff 1.05VPLL@

3G

BT

LVDS/EDP

PLL Power

Function
3G@ w/ 3G module

BT@

LVDS@

EDP@

1.5VPLL@ w/ 1.5VPLL (default)

1.05VPLL@ w/ 1.05VPLL

(1.182A)

(1.6A)

G9334
AO4468

PU7/PQ29

+3V(1.38A)

AO3404

PQ10

+1.5V(1.646A)

<MAIND>

+1.8V(151mA)

<+3.3V_PRIME_ON>

+3.3V_PRIME(220mA)

<+3.3V_PRIME_ON>

ADAPTER

CHARGER

(ISL88731)

BATTERY PU9001

VIN
(5.48A)

AO3404

+3VSUS

PQ22 <MAIND>

B B

+3V

+1.5VSUS(3.362A)

<SUSON>

VIN

DDR PWR

1.5V

(RT8207)

+1.5VSUS

(5.008A)

AO3404

PQ11

PU5

+SMDDR_VREF(0.25A)

A A

5

<SUSON>

+0.75V_DDR_VTT(0.5A)

<MAINON>

4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

ZE7

PROJECT :

ZE7

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

3

2

Date: Sheet of

1

Power Tree

Power Tree

Power Tree

ZE7

1B

1B

1B

37 40Wednesday, November 02, 2011

37 40Wednesday, November 02, 2011

37 40Wednesday, November 02, 2011

5

JE01_CT(Cedar Trail) Power On Sequence

4

3

2

1

38

From AC,BATT

D D

From PWM to EC

From Button to EC

From EC to PWM

From EC to SB
From EC to SB

From SB to EC

From EC to PWM

From PWM to EC

C C

From EC to PWM

From PWM to CPU VR

VIN

+5VPCU +3VPCU VCCRTC

HWPG_SYS(PCU)

RTCRST#

(VCCRTC to RTCRST#)(t200)

>=18ms

NBSWON#

S5_ON

+5V_S5
+3V_S5

EC_RSMRST#

DNBSWON#(PWRBTN#)

(VCCRTC to S5 well)(t203)

>=0ms

+5V_S5 power up before +3V_S5, or
after +3V_S5 within 0.7V (t201)

>=5ms

(S5 well to EC_RSMRST#)(t205)

100ms

SUSB#(SLP_S3#),SUSC#(SLP_S4#)

SUSON

+3VSUS +SMDDR_VREF +1.5VSUS(to DDR3_DRAM_PWROK)

HWPG_1.5V (SUS)

MAINON

+5V +3V +1.5V +0.75V_DDR_VTT

+1.05V (also for V_CPU_IO of PCH)

HWPG_1.05V

(EC define)

1~2 RTCCLK (SUSC# to SUSB#)(t234)

+5V power up before +3V, or
after +3V within 0.7V (t209)

CPU: +1.5V power up before +1.05V ; PCH: +1.5V power up
before V_CPU_IO, or after V_CPU_IO within 0.7V (t211)

(1RTC: 28.992 µs to 32.044 µs)

+3V_S5 power down before +5V_S5,
or after +5V_S5 within 0.7V

+3V power down before +5V,
or after +5V within 0.7V

V_CPU_IO power down before +1.5V,
or after +1.5V within 0.7V

+VCC_CORE VCCGFX

From PWM to EC IMVP_PWRGD/HWPG_VCCGFX

From EC

From PWM to EC

B B

From EC to CPU,SB

From PWM

From CLK Gen

+3.3V_PRIME_ON

+3V_PRIME +1.8V

HWPG_1.8V
HWPG(to EC,VRMPWRGD,CK505)

ECPWROK(AND with HWPG to PWROK,to DDR3_VCCA_PWROK)

BCLK

CPU:+3V_PRIME and +1.8V needs to be <700mV

100ms(EC define)

From EC to SB

From SB to CPU
From SB to All

TPT_PWROK

H_PWRGD
PLTRST#

99ms(S0 well of TPT to TPT_PWROK)(t214)

NOTE:PWROK assertion indicates that PCICLK has been stable for at least 1 ms.

*Note: EC will sampling SUSB# & SUSC# every 5ms.

ICH SMBUS Table

A A

(SMB_DATA)/(SMB_CLK) (+3V_S5)

Power Plane

MOS CKT (Level shift)

CLK GEN RAM *Mini Card (WLAN)

V

+3V +3V

Stuff Stuff

VV

+3V

Stuff Stuff

*=Reserve

5

4

*XDP

V

+3V

EC791 SDA1 / SCL1 (+3VPCU)
EC791 SDA2 / SCL2
EC791 SDA3 / SCL3

Power Plane +3VPCU
MOS CKT (Level shift)

3

EC SMBUS Table

V

X

GFX Thermal SensorCPU Thermal SensorBattery

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Documen t Number Rev

Size Documen t Number Rev

Size Documen t Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

PROJECT :

Power Sequence

Power Sequence

Power Sequence

1

ZE7

ZE7

ZE7

1B

1B

38 40Wednesday, November 02, 2011

38 40Wednesday, November 02, 2011

38 40Wednesday, November 02, 2011

1B

5

SLP_S3#(SUSB#):
S3 Sleep Power plane control Assertion of SLP_S3# shuts off power to non-critical components
when system transitions to S3, S4, or S5 states.

SLP_S4#(SUSC#):
S4 Sleep Power plane control - Assertion of SLP_S4# shuts power off to non-critical components
when system transitions to S4 or S5 state.

AC Adapter

D D

Battery

BATT Charger

PU2

10

SUSON(SUSD)

4

1

VIN

Always System power

Regulator

+3VPCU

+5VPCU

PU2

3

2

3

NBSWON#

2

4

5

S5_ON
(S5D)

+5VPCU

MOS

PQ33

+3VPCU

MOS

PQ12

+5V_S5

6

+3V_S5

1

39

7

EC_RSMRST#

RSMRST#

8

DNBSWON#

PWRBTN#

13

SUSC#

MAINON(MAIND)

MAIND

MAIND

C C

MAINON
+RC

+3VPCU/+5VPCU

MOS

+1.5VSUS

MOS

VIN

VR

+3V

+5V

+1.5V

+1.05V

14

15

EC

100ms

SUSB#

22

ECPWROK

HWPG_1.05V

16

VIN

Regulator

PU8

+3.3V_PRIME_ON

(From EC)

19a

+3V

MOS

B B

PQ9

+3VSUS

MOS

PU7

D

NMOS

MAINON_ON_G

G

S

For Power Down Sequence

GND

MAINON

SUSON

VIN

Regulator

PU5

SUSD

+3VPCU

MOS

+VCC_CORE

VCCGFX

IMVP_PWRGD/ HWPG_VCCGFX

+3V_PRIME

19b

20

+1.8V

+0.75V_DDR_VTT

+SMDDR_VREF

+1.5VSUS

+3VSUS

11

17

HWPG_SYS

18

21

HWPG

HWPG_1.8V

HWPG_1.5V

12

MAINON_ON_G

For Power Down Sequence

D

NMOS

G

S

GND

9

EN

CK505

23

TPT_PWROK

SLP_S4#

SLP_S3#

PCH

PWRGD

VRM_PWRGOOD

CPU_PG

PLTRST#

24 25

H_PWRGD PLTRST_N

RESET_L

PWRGD

DDR3_VCCA_PWROK

CPU

DDR3_DRAM_PWROK

PQ22

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

ZE7

PROJECT :

ZE7

PROJECT :

Size Document Numb er Rev

Size Document Numb er Rev

Size Document Numb er Rev

power sequence block diagram

power sequence block diagram

power sequence block diagram

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

1

ZE7

1B

1B

1B

39

39

39

40Wednes day, November 0 2, 2011

40Wednes day, November 0 2, 2011

40Wednes day, November 0 2, 2011

Model

ZE7 MB

5

REV

First Released (PCB: A)

1A

4

CHANGE LIST

3

2

MODEL

1

ZE7

FROM To

1A 1B

<Page 5> Update CPU P/N to MP P/N

D D

1B

<Page 19> Un-stuff CA122084N98 at CP1 - CP6 by EMI confirmation
<Page 18> Stuff R26 CS00003J951 (0/J_6) for +5V_LCD (IVO panel)

Change 0ohm resistors to short PAD

C C

B B

A A

Quanta Computer Inc.

Quanta Computer Inc.

DOC NO.

APPROVED BY:PROJECT MODEL : ZE7

PART NUMBER: DRAWING BY: REVISON:

5

4

3

DATE:

2011/11/2

1B

2

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

Change List1

Change List1

Change List1

ZE7

ZE7

ZE7

40 40Wednesday, November 02, 2011

40 40Wednesday, November 02, 2011

40 40Wednesday, November 02, 2011

1

1B

1B

1B