Quanta ZD1, Aspire 5920G Schematic
www.RahasiaLaptop.com
5
4
3
2
1
X'TAL
14.318MHZ
ZD1(CHAPALA) SYSTEM BLOCK DIAGRAM
VCORE(ISL6262A)
CLOCK GENERATOR
SELGO: SLG8SP512K05
D D
P2
TVOUT
CRT
TFT LCD Panel
WXGA
WSXGA+
WUXGA
C C
P19
VGA
LVDS
P18
HDD (SATA)
P24
Merom 479
uFCPGA
FSB
NB
Crestline
PM965
P5,P6,P7,P8,P9,P10,P11
P3,P4
667/800 Mhz
X4 DMI interface
Dual Channel DDR2
533/667 MHz
PCI-Express 16X Lan
SATA0
SATA1
PATA
USB 2.0
Azalia
SB
ICH8M
P12,P13,P14,P15
X'TAL
32.768KHZ
Bluetooth
USB4 P21
USB Port x 4
USB0~3
P25
ODD (PATA)
P24
CPU
Thermal Sensor
DVI
LVDS
VGA/TV out
PCI-Express
PCI Bus
P3
DDRII
SO-DIMM 0
SO-DIMM 1
P16
MXM-NB8P-GS
( nVidia )
VRAM 256M
VRAM 512M
P17
X'TAL24.576MHZ
1394
5V/3.3V (ISL6236)
DISCHARGE
USB6
Mini Card /
WLAN / 3G(TV)
P22
PCIE-4PCIE-2
+Cardreader
CCD
B B
P21USB7
Int MIC
P27
Controller
R5C832/833
+1.2V/+1.25V/1.5V/2.5V
P33
BATTERYCHARGER
(ISL6251)
P33
+1.8V / +1.05V
P37
USB5
New Card
PCIE-1 PCIE-5
BROADCOM
10/100/1G LAN
P23
PCIE-6
5787M
P35,36
Robson
X'TAL
25M
P20
P37
P32
P29
LPC
Azalia Audio
Audio Amplifier
P27
MIC Jack
Connector
Speaker
A A
Phone Jack
5
Controller
ALC268&888
Line in
P27 P27
P27P27 P26
MDC 1.5
P26
4
X'TAL
32.768K
EC (WPC8769LDG)
SPI ROM
Touch Pad
K/B COON.
P30
P30
P31
P31
IEEE 1394 Port
P28
P28
Media Card Reader
P28
Transformer
P20
Fan Header
P21,P30
RJ45
P21
VR
P26
BOM MARK
CIR
P21
3
EV@ EXT VGA
IV@ INT VGA
268@ AUDIO 268
888@ AUDIO 888
2
要打
要打
要打
要打
PROJECT : ZD1
PROJECT : ZD1
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
Quanta Computer Inc.
Block Diagram
Block Diagram
Block Diagram
of
138Wednesday, April 25, 2007
138Wednesday, April 25, 2007
138Wednesday, April 25, 2007
1
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www.RahasiaLaptop.com
5
4
3
2
1
Clock Generator
Change list:
B-test
1.Change U31 P/N to ALPRS365K13 (ICS)
C345
C345
.1U/10V_4
.1U/10V_4
C339
C339
10U/6.3V
10U/6.3V
+3V_VDD_A
R435
R435
*10K_4
*10K_4
R439
R439
10K_4
10K_4
R205
R205
+3V
BKP1608HS181-T
BKP1608HS181-T
D D
C347
C347
4.7U/10V
4.7U/10V
C349
C349
.1U/10V_4
.1U/10V_4
C340
C340
.1U/10V_4
.1U/10V_4
C352
C352
.1U/10V_4
.1U/10V_4
C362
C362
.1U/10V_4
.1U/10V_4
C342
C342
.1U/10V_4
.1U/10V_4
+3V+3V
R443
R443
*10K_4
*10K_4
PCLK_ICHPCI_CLK_SIO
R207
R207
10K_4
10K_4
R220
R220
+1.25V
BKP1608HS181-T
BKP1608HS181-T
C C
C: For EMI solution
14M_ICH
B B
C645
C645
*30P/50V_4
*30P/50V_4
C350
C350
C375
C375
C355
C355
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
4.7U/10V
4.7U/10V
SATACLKREQ#<14>
PCLK_PCM<28>
PCLK_DEBUG<22,30>
PCLK_591<31>
PCLK_ICH<13>
CLKUSB_48<14>
14M_ICH<14>
CLK_DREFCLK<7>
CLK_DREFCLK#<7>
C563 33P/50V_4C563 33P/50V_4
<check list>
XTAL length < 500mils
C565 33P/50V_4C565 33P/50V_4
C372
C372
.1U/10V_4
.1U/10V_4
C353
C353
.1U/10V_4
.1U/10V_4
C360
C360
.1U/10V_4
.1U/10V_4
Y4
Y4
14.318MHz
14.318MHz
+1.25V_VDD
C358
C358
C359
C359
10U/6.3V
10U/6.3V
.1U/10V_4
.1U/10V_4
PCI_CLK_SIO PCI_CLK_SIO_R
MCH_BSEL1
CGCLK_SMB
CGDAT_SMB
CG_XIN
CG_XOUT
+3V_VDD_A
CG_XOUT
CG_XIN
R430 475_4R430 475_4
R432 33_4R432 33_4
R434 33_4R434 33_4
R436 33_4R436 33_4
R440 33_4R440 33_4
R444 33_4R444 33_4
R447 33_4R447 33_4
R423 33_4R423 33_4
RP43 IV@0X2RP43 IV@0X2
4
2
SATACLKREQ#_R
PCI_CLK_7412_R
PCLK_MINI_R
PCLK_591_R
PCLK_ICH_R
FSA
FSC
3
1
R2060_4 R2060_4
R4310_4 R4310_4
DREFCLK_R
DREFCLK#_R
VDD_A_48
VDD_A_REF
U31
U31
2
VDD_PCI
9
VDD_48
16
VDD_PLL3
39
VDD_SRC
55
VDD_CPU
61
VDD_REF
59
XTAL_OUT
60
XTAL_IN
1
PCI_0/CLKREQ_A#
3
PCI_1/CLKREQ_B#
4
PCI_2
5
PCI_3
6
^PCI_4/LCDCLK_SEL
7
PCIF_5/ITP_EN
10
USB_48MHz/FS_A
57
FS_B/TEST_MODE
62
REF/FS_C/TEST_SEL
13
SRC_0/DOT_96
14
SRC_0#/DOT_96#
64
SCL
63
SDA
8
VSS_PCI
11
VSS_48
15
VSS_I/O
19
VSS_PLL3
23
VSS_SRC_1
29
VSS_SRC_2
42
VSS_SRC_3
52
VSS_CPU
58
VSS_REF
ICS9LPRS365BGLFT
ICS9LPRS365BGLFT
Main: ICS9LPRS365BGLFT:ALPRS365K13
SLG8SP512T: AL8SP512K05
VDD_PLL3_I/O
VDD_SRC_I/O_1
VDD_SRC_I/O_2
VDD_SRC_I/O_3
VDD_CPU_I/O
CKPWRGD/PD#
CPU_1_MCH
CPU_1_MCH#
SRC_8/CPU_ITP
SRC_8#/CPU_ITP#
LCDCLK/27M
LCDCLK#/27M_SS
SRC_3/CLKREQ_C#
SRC_3#/CLKREQ_D#
SRC_7/CLKREQ_F#
SRC_7#/CLKREQ_E#
SRC_11/CLKREQ_H#
SRC_11#/CLKREQ_G#
VDD_I/O
CPU_STOP#
PCI_STOP#
CPU_0
CPU_0#
SRC_2
SRC_2#
SRC_4
SRC_4#
SRC_6
SRC_6#
SRC_9
SRC_9#
SRC_10
SRC_10#
12
20
26
36
45
49
37
38
56
54
53
51
50
47
46
48
NC
17
18
21
22
24
25
27
28
41
40
44
43
30
31
34
35
33
32
+1.25V_VDD
CLK_CPU_BCLK_R
CLK_CPU_BCLK#_R
CLK_MCH_BCLK_R
CLK_MCH_BCLK#_R
PCIE_CLK_RBS_R
PCIE_CLK_RBS#_R
CLK_DREFSSCLK_R
CLK_DREFSSCLK#_R
CLK_PCIE_SATA_R
CLK_PCIE_SATA#_R
CLK_PCIE_LAN_R
CLK_PCIE_LAN#_R
CLK_PCIE_MINI1_R
CLK_PCIE_MINI1#_R
CLK_PCIE_ICH_R
CLK_PCIE_ICH#_R
PECLK_VGA_R
PECLK_VGA#_R
CLK_PCIE_NEW_C_R
CLK_PCIE_NEW_C#_R
CLK_PCIE_3GPLL_R
CLK_PCIE_3GPLL#_R
CLK_PCIE_TV_R
CLK_PCIE_TV#_R
RP42 0X2RP42 0X2
RP44 0X2RP44 0X2
RP46 0X2RP46 0X2
RP45 IV@0X2RP45 IV@0X2
RP47 0X2RP47 0X2
RP49 0X2RP49 0X2
RP51 0X2RP51 0X2
RP50 0X2RP50 0X2
RP48 EV@0X2RP48 EV@0X2
RP53 0X2RP53 0X2
RP52 0X2RP52 0X2
RP36 0X2RP36 0X2
2
1
4
3
2
1
4
3
2
1
4
3
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
2
1
4
3
2
1
4
3
4
3
2
1
4
3
2
1
4
3
2
1
PM_STPCPU# <14>
PM_STPPCI# <14>
CK_PWRGD <14>
CLK_CPU_BCLK <3>
CLK_CPU_BCLK# <3>
CLK_MCH_BCLK <5>
CLK_MCH_BCLK# <5>
PCIE_CLK_RBS <29>
PCIE_CLK_RBS# <29>
CLK_DREFSSCLK <7>
CLK_DREFSSCLK# <7>
CLK_PCIE_SATA <12>
CLK_PCIE_SATA# <12>
CLK_PCIE_LAN <20>
CLK_PCIE_LAN# <20>
CLK_PCIE_MINI1 <22>
CLK_PCIE_MINI1# <22>
CLK_PCIE_ICH <13>
CLK_PCIE_ICH# <13>
CLK_MXM <17>
CLK_MXM# <17>
CLK_PCIE_NEW_C <23>
CLK_PCIE_NEW_C# <23>
CLK_PCIE_3GPLL <7>
CLK_PCIE_3GPLL# <7>
CLK_PCIE_TV <22>
CLK_PCIE_TV# <22>
+3V
MCH_BSEL0
MCH_BSEL2
Clock Gen I2C
PDAT_SMB<14,16,22,23>
PCLK_SMB<14,16,22,23>
R433 10K_4R433 10K_4
R446 2.2K_4R446 2.2K_4
R424 10K_4R424 10K_4
Q27
Q27
RHU002N06
RHU002N06
3
Q28
Q28
RHU002N06
RHU002N06
3
+3V
+3V
2
2
PCLK_DEBUG
CLKUSB_48
FSC
R428
R428
10K_4
10K_4
1
1
R429
R429
10K_4
10K_4
CGDAT_SMB
CGCLK_SMB
CPU Clock select
A A
5
CPU_BSEL0<3>
+1.05V
CPU_BSEL1<3>
+1.05V
CPU_BSEL2<3>
+1.05V
R455 0_4R455 0_4
R456 *56_4R456 *56_4
R450 *1K_4R450 *1K_4
R451 0_4R451 0_4
R449 *0_4R449 *0_4
R454 *1K_4R454 *1K_4
R425 0_4R425 0_4
R427 *0_4R427 *0_4
R426 *1K_4R426 *1K_4
MCH_BSEL0
MCH_BSEL0 <7>
BSEL Frequency Select Table
FSC FSB FSA Frequency
0
0
MCH_BSEL1
MCH_BSEL2
4
MCH_BSEL1 <7>
MCH_BSEL2 <7>
3
0
0
0
0
1
1
1
1
1
1
1
0
1
01
1
1
0
1
0
0
2
266Mhz0
133Mhz
166Mhz
200Mhz
400Mhz
Reserved
100Mhz
333Mhz
PROJECT : ZD1
PROJECT : ZD1
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet of
Date: Sheet of
Quanta Computer Inc.
CLOCK GENERATOR CK505 W/REGULATOR
CLOCK GENERATOR CK505 W/REGULATOR
CLOCK GENERATOR CK505 W/REGULATOR
1
of
238Monday, May 07, 2007
238Monday, May 07, 2007
238Monday, May 07, 2007
E
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www.RahasiaLaptop.com
5
H_A#[16:3]<5>
CPU(HOST)
D D
C C
H_STPCLK#<12>
B B
+1.05V
R365
R365
1K/F_4
A A
1K/F_4
R364
R364
2K/F
2K/F
H_ADSTB0#<5>
H_REQ#[4:0]<5>
H_A#[35:17]<5>
H_ADSTB1#<5>
H_A20M#<12>
H_FERR#<12>
H_IGNNE#<12>
R350 0_4R350 0_4
H_INTR<12>
H_NMI<12>
H_SMI#<12>
H_D#[15:0]<5>
H_DSTBN#0<5>
H_DSTBP#0<5>
H_DINV#0<5>
H_D#[31:16]<5>
<Check list & CRB>
Layout note: Z=55 ohm
H_GTLREF<0.5"
H_DSTBN#1<5>
H_DSTBP#1<5>
H_DINV#1<5>
R101 *1K_4R101 *1K_4
R369 *1K_4R369 *1K_4
T10T10
T74T74
T7T7
T73T73
CPU_BSEL0<2>
CPU_BSEL1<2>
CPU_BSEL2<2>
5
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_STPCLK_R#
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_GTLREF
CPU_TEST1
CPU_TEST2
CPU_TEST3
CPU_TEST4
CPU_TEST5
CPU_TEST6
U22A
U22A
J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1
K3
H2
K2
J3
L1
Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1
A6
A5
C4
D5
C6
B4
A3
M4
N5
T2
V3
B2
C3
D2
D22
D3
F6
Merom Ball-out Rev 1a
Merom Ball-out Rev 1a
U22B
U22B
E22
D[0]#
F24
D[1]#
E26
D[2]#
G22
D[3]#
F23
D[4]#
G25
D[5]#
E25
D[6]#
E23
D[7]#
K24
D[8]#
G24
D[9]#
J24
D[10]#
J23
D[11]#
H22
D[12]#
F26
D[13]#
K22
D[14]#
H23
D[15]#
J26
DSTBN[0]#
H26
DSTBP[0]#
H25
DINV[0]#
N22
D[16]#
K25
D[17]#
P26
D[18]#
R23
D[19]#
L23
D[20]#
M24
D[21]#
L22
D[22]#
M23
D[23]#
P25
D[24]#
P23
D[25]#
P22
D[26]#
T24
D[27]#
R24
D[28]#
L25
D[29]#
T25
D[30]#
N25
D[31]#
L26
DSTBN[1]#
M26
DSTBP[1]#
N24
DINV[1]#
AD26
GTLREF
C23
TEST1
D25
TEST2
C24
TEST3
AF26
TEST4
AF1
TEST5
A26
TEST6
B22
BSEL[0]
B23
BSEL[1]
C21
BSEL[2]
Merom Ball-out Rev 1a
Merom Ball-out Rev 1a
ADDR GROUP 0 ADDR GROUP 1
ADDR GROUP 0 ADDR GROUP 1
A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#
A20M#
FERR#
IGNNE#
STPCLK#
LINT0
LINT1
SMI#
RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]
RSVD[10]
DATA GRP 1
DATA GRP 1
MISC
MISC
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
CONTROL
CONTROL
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
HIT#
HITM#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDO
TMS
TRST#
XDP/ITP SIGNALS
XDP/ITP SIGNALS
DBR#
THERMAL
THERMAL
PROCHOT#
THERMDA
THERMDC
ICH
ICH
THERMTRIP#
H CLK
H CLK
BCLK[0]
BCLK[1]
RESERVED
RESERVED
D[32]#
D[33]#
D[34]#
DATA GRP 0
DATA GRP 0
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
DATA GRP 2DATA GRP 3
DATA GRP 2DATA GRP 3
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
COMP[0]
COMP[1]
COMP[2]
COMP[3]
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
TDI
SLP#
PSI#
H1
E2
G5
H5
F21
E1
F1
H_IERR#
D20
B3
H4
C1
F3
F4
G3
G2
G6
E4
XDP_BPM#0
AD4
XDP_BPM#1
AD3
XDP_BPM#2
AD1
XDP_BPM#3
AC4
XDP_BPM#4
AC2
XDP_BPM#5
AC1
XDP_TCK
AC5
XDP_TDI
AA6
XDP_TDO
AB3
XDP_TMS
AB5
XDP_TRST#
AB6
XDP_DBRESET#
C20
H_PROCHOT_R#
D21
H_THERMDA
A24
H_THERMDC
B25
PM_THRMTRIP#
C7
A22
A21
Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
R26
U26
AA1
Y1
E5
B5
D24
D6
D7
AE6
4
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
COMP0
COMP1
COMP2
COMP3
4
H_ADS# <5>
H_BNR# <5>
H_BPRI# <5>
H_DEFER# <5>
H_DRDY# <5>
H_DBSY# <5>
R79 56.2/F_4R79 56.2/F_4
R358 0_4R358 0_4
R355 56.2/F_4R355 56.2/F_4
R82 *2.2K_4R82 *2.2K_4
<check list>
Default PU 56ohm if no use.
Serial R NC, If connect to power side PU 68ohm. Serial R 2.2K
CLK_CPU_BCLK <2>
CLK_CPU_BCLK# <2>
H_D#[47:32] <5>
H_DSTBN#2 <5>
H_DSTBP#2 <5>
H_DINV#2 <5>
H_D#[63:48] <5>
H_DSTBN#3 <5>
H_DSTBP#3 <5>
R367 27.4/FR367 27.4/F
R366 54.9/F_4R366 54.9/F_4
R48 27.4/FR48 27.4/F
R43 54.9/F_4R43 54.9/F_4
H_DINV#3 <5>
H_DPSLP# <12>
H_DPWR# <5>
H_CPUSLP# <5>
PSI# <34>
H_BREQ#0 <5>
+1.05V
H_INIT# <12>
H_LOCK# <5>
H_CPURST# <5>
H_RS#0 <5>
H_RS#1 <5>
H_RS#2 <5>
H_TRDY# <5>
H_HIT# <5>
H_HITM# <5>
T8T8
T2T2
T3T3
T6T6
T4T4
T5T5
SYS_RST# <14>
+1.05V
H_PROCHOT# <34>
<Check list & CRB>
Layout note: L<0.5"
COMP0/2 Z=27.4ohm
COMP1/3 Z=54.9
<CRB & Design guide>
Layout Note:Connect from
SB and daisy chain to CPU
CORE VR.Not use T
connect.(SB/VR/CPU/NB)
ICH_DPRSTP# <7,12,34>
3
H_PWRGD <12>
3
CPU Thermal monitor
MBCLK<31,32>
MBDATA<31,32>
THERM_ALERT#<14,17>
+3V
3
+3V
3
Thermal Trip
DELAY_VR_PWRGOOD<7,14,34>
+1.05V
R56
R56
56.2/F_4
56.2/F_4
PM_THRMTRIP#
<CRB & Design guide>
Layout Note: Thermal trip should connect to ICH8 & GMCH without T-ing
(ZS1 default NC)
2
2
+3V
CPUFAN#_ON<30>
Q25
Q25
RHU002N06
RHU002N06
Q26
Q26
RHU002N06
RHU002N06
2
1
1
R362 *0_4R362 *0_4
R363 *10K_4R363 *10K_4
+1.05V
3
Q3
2
FDV301NQ3FDV301N
1
Q4
Q4
2
MMBT3904
MMBT3904
1 3
2
R360
R360
10K_4
10K_4
CPUFAN#_ON
D4
R55
R55
*BAS316D4*BAS316
*10K_4
*10K_4
C39 *1UC39 *1U
SYS_SHDN# <33>
PM_THRMTRIP# <7,12>
1
+3V
R357
R357
R361
R361
200
200
10K_4
10K_4
U24
U24
8
SCLK
7
SDA
6
ALERT#
4
OVERT#
MAX6657
MAX6657
ADDRESS: 98H
LM86VCC
1
VCC
2
DXP
3
DXN
5
GND
<check list>
Layout Note:Routing 10:10 mils and away
from noise source with ground gard
C517
C517
.1U/10V_4
.1U/10V_4
C518
C518
2200P/50V_4
2200P/50V_4
H_THERMDA
H_THERMDC
PU/PD (ITP700)
+1.05V
XDP_TMS
XDP_TDI
XDP_BPM#5
XDP_TDO
PROJECT : ZD1
PROJECT : ZD1
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Quanta Computer Inc.
CPU(1 of 2)/FAN/Thermal
CPU(1 of 2)/FAN/Thermal
CPU(1 of 2)/FAN/Thermal
XDP_TCK
XDP_TRST#
R44 39/F_4R44 39/F_4
R42 150/F_4R42 150/F_4
R47 *54.9/F_4R47 *54.9/F_4
R45 54.9/F_4R45 54.9/F_4
R54 27/F_4R54 27/F_4
R46 680/F_4R46 680/F_4
of
of
of
338Monday, May 07, 2007
338Monday, May 07, 2007
338Monday, May 07, 2007
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5
CPU(Power)
VCC_CORE
C55
C43
C43
C46
D D
C C
<Check list>
Option1:330U*6(ESR=1.5m ohm aggregate , ESL=0.8nH/6) and 22U*20(ESR=3mohm typ/20 , ESL=0.6nH/20)
Option2:330U*6(ESR=1.5m ohm aggregate , ESL=1.8nH/6) and 22U*32(ESR=3mohm typ/32 , ESL=0.6nH/32)
B B
10U/6.3V_8
10U/6.3V_8
C60
C60
10U/6.3V_8
10U/6.3V_8
C93
C93
10U/6.3V_8
10U/6.3V_8
C86
C86
10U/6.3V_8
10U/6.3V_8
+
+
C40
C40
330U/2.5V_7
330U/2.5V_7
C46
10U/6.3V_8
10U/6.3V_8
C42
C42
10U/6.3V_8
10U/6.3V_8
C97
C97
10U/6.3V_8
10U/6.3V_8
C77
C77
10U/6.3V_8
10U/6.3V_8
C49
C49
10U/6.3V_8
10U/6.3V_8
C47
C47
10U/6.3V_8
10U/6.3V_8
C91
C91
10U/6.3V_8
10U/6.3V_8
C61
C61
10U/6.3V_8
10U/6.3V_8
C55
10U/6.3V_8
10U/6.3V_8
C53
C53
10U/6.3V_8
10U/6.3V_8
C44
C44
10U/6.3V_8
10U/6.3V_8
C57
C57
10U/6.3V_8
10U/6.3V_8
C59
C59
10U/6.3V_8
10U/6.3V_8
C58
C58
10U/6.3V_8
10U/6.3V_8
C83
C83
10U/6.3V_8
10U/6.3V_8
C52
C52
10U/6.3V_8
10U/6.3V_8
+
+
C41
C41
330U_7
330U_7
C69
C69
10U/6.3V_8
10U/6.3V_8
C63
C63
10U/6.3V_8
10U/6.3V_8
C70
C70
10U/6.3V_8
10U/6.3V_8
C48
C48
10U/6.3V_8
10U/6.3V_8
<Part Number>
<Part Number>
<Description>
<Description>
+
+
C100
C100
330U/2.5V_7
330U/2.5V_7
C94
C94
C84
C84
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
C80
C80
C90
C90
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
DESIGN GUIDE
CHANGE FROM 22UF *20 TO 10UF *32
C102
C102
10U/6.3V_8
10U/6.3V_8
C99
C99
10U/6.3V_8
10U/6.3V_8
4
C56
C56
10U/6.3V_8
10U/6.3V_8
C51
C51
10U/6.3V_8
10U/6.3V_8
U22C
U22C
A7
VCC[001]
A9
VCC[002]
A10
VCC[003]
A12
VCC[004]
A13
VCC[005]
A15
VCC[006]
A17
VCC[007]
A18
VCC[008]
A20
VCC[009]
B7
VCC[010]
B9
VCC[011]
B10
VCC[012]
B12
VCC[013]
B14
VCC[014]
B15
VCC[015]
B17
VCC[016]
B18
VCC[017]
B20
VCC[018]
C9
VCC[019]
C10
VCC[020]
C12
VCC[021]
C13
VCC[022]
C15
VCC[023]
C17
VCC[024]
C18
VCC[025]
D9
VCC[026]
D10
VCC[027]
D12
VCC[028]
D14
VCC[029]
D15
VCC[030]
D17
VCC[031]
D18
VCC[032]
E7
VCC[033]
E9
VCC[034]
E10
VCC[035]
E12
VCC[036]
E13
VCC[037]
E15
VCC[038]
E17
VCC[039]
E18
VCC[040]
E20
VCC[041]
F7
VCC[042]
F9
VCC[043]
F10
VCC[044]
F12
VCC[045]
F14
VCC[046]
F15
VCC[047]
F17
VCC[048]
F18
VCC[049]
F20
VCC[050]
AA7
VCC[051]
AA9
VCC[052]
AA10
VCC[053]
AA12
VCC[054]
AA13
VCC[055]
AA15
VCC[056]
AA17
VCC[057]
AA18
VCC[058]
AA20
VCC[059]
AB9
VCC[060]
AC10
VCC[061]
AB10
VCC[062]
AB12
VCC[063]
AB14
VCC[064]
AB15
VCC[065]
AB17
VCC[066]
AB18
VCC[067]
Merom Ball-out Rev 1a
Merom Ball-out Rev 1a
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
VCCA[01]
VCCA[02]
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VCCSENSE
VSSSENSE
.
.
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
B26
C26
AD6
AF5
AE5
AF4
AE3
AF3
AE2
AF7
AE7
3
+VCCA_PROC
0C Delete R75,R63 0104
H_VID0 <34>
H_VID1 <34>
H_VID2 <34>
H_VID3 <34>
H_VID4 <34>
H_VID5 <34>
H_VID6 <34>
2
<REV.NO. 0.5/REF.NO.19343>
Ivcc Max 52A
Ivccp Max 6A(VCCP supply before Vcc stable)
Max 2A(VCCP supply after Vcc stable)
Ivcca Max 130mA
+1.05V
C81
C75
C75
.1U/16V
.1U/16V
R368 0R368 0
C130
C130
10U/10V_8
10U/10V_8
VCCSENSE <34>
VSSSENSE <34>
C81
.1U/16V
.1U/16V
+
+
VCC_CORE
C45
C45
C76
C76
.1U/16V
.1U/16V
.1U/16V
.1U/16V
C54
C54
<Check list>
330U/2.5V_7
330U/2.5V_7
ESR=12m ohm
<CRB>
.01U near to B26 ball
C520
C520
.01U/16V_4
.01U/16V_4
R62
R62
100/F
100/F
<Demo board>
R58
R58
Routing 27.4ohm with 50mils spacing
PU/PD near to CPU 1"
100/F
100/F
C89
C89
.1U/16V
.1U/16V
+1.05V
+1.5V
C82
C82
.1U/16V
.1U/16V
1
U22D
U22D
A4
VSS[001]
A8
VSS[002]
A11
VSS[003]
A14
VSS[004]
A16
VSS[005]
A19
VSS[006]
A23
VSS[007]
AF2
VSS[008]
B6
VSS[009]
B8
VSS[010]
B11
VSS[011]
B13
VSS[012]
B16
VSS[013]
B19
VSS[014]
B21
VSS[015]
B24
VSS[016]
C5
VSS[017]
C8
VSS[018]
C11
VSS[019]
C14
VSS[020]
C16
VSS[021]
C19
VSS[022]
C2
VSS[023]
C22
VSS[024]
C25
VSS[025]
D1
VSS[026]
D4
VSS[027]
D8
VSS[028]
D11
VSS[029]
D13
VSS[030]
D16
VSS[031]
D19
VSS[032]
D23
VSS[033]
D26
VSS[034]
E3
VSS[035]
E6
VSS[036]
E8
VSS[037]
E11
VSS[038]
E14
VSS[039]
E16
VSS[040]
E19
VSS[041]
E21
VSS[042]
E24
VSS[043]
F5
VSS[044]
F8
VSS[045]
F11
VSS[046]
F13
VSS[047]
F16
VSS[048]
F19
VSS[049]
F2
VSS[050]
F22
VSS[051]
F25
VSS[052]
G4
VSS[053]
G1
VSS[054]
G23
VSS[055]
G26
VSS[056]
H3
VSS[057]
H6
VSS[058]
H21
VSS[059]
H24
VSS[060]
J2
VSS[061]
J5
VSS[062]
J22
VSS[063]
J25
VSS[064]
K1
VSS[065]
K4
VSS[066]
K23
VSS[067]
K26
VSS[068]
L3
VSS[069]
L6
VSS[070]
L21
VSS[071]
L24
VSS[072]
M2
VSS[073]
M5
VSS[074]
M22
VSS[075]
M25
VSS[076]
N1
VSS[077]
N4
VSS[078]
N23
VSS[079]
N26
VSS[080]
VSS[081]P3VSS[162]
Merom Ball-out Rev 1a
Merom Ball-out Rev 1a
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[163]
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
.
.
A A
5
4
3
2
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
CPU(2 of 2)
CPU(2 of 2)
CPU(2 of 2)
Date: Sheet
Date: Sheet
Date: Sheet
PROJECT : ZD1
PROJECT : ZD1
Quanta Computer Inc.
Quanta Computer Inc.
438Monday, May 07, 2007
438Monday, May 07, 2007
438Monday, May 07, 2007
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5
4
3
2
1
NB(HOST)
D D
U30A
W10
AD12
AC14
AD11
AC11
AJ14
AE11
AH12
AH13
M10
N12
AE3
AD9
AC9
AC7
AB2
AD7
AB1
AC6
AE2
AC5
AG3
AH8
AE9
AH5
AE7
AE5
AH2
E2
G2
G7
M6
H7
H3
G4
F3
N8
H2
N9
H5
P13
K9
M2
Y8
V4
M3
J1
N5
N3
W6
W9
N2
Y7
Y9
P4
W3
N1
Y3
AJ9
AJ5
AJ6
AJ7
AJ2
AJ3
B3
C2
W1
W2
B6
E5
B9
A9
U30A
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
H_SWING
H_RCOMP
H_SCOMP
H_SCOMP#
H_CPURST#
H_CPUSLP#
H_AVREF
H_DVREF
CRESTLINE_1p0
CRESTLINE_1p0
HOST
HOST
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
H_RS#_0
H_RS#_1
H_RS#_2
J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19
G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7
K5
L2
AD13
AE13
M7
K3
AD2
AH11
L7
K2
AC2
AJ10
M14
E13
A11
H13
B12
E12
D7
D8
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
H_D#[63:0]<3>
+1.05V
R376
R376
221_4
221_4
R378
R378
100_4
100_4
C C
R370
R370
24.9_4
24.9_4
B B
+1.05V
+1.05V
H_SWING
C530
C530
<check list>
0.1U close to B3
.1U/10V_4
.1U/10V_4
H_RCOMP
<check list>
10:20 mils(Width:Spacing)
R111
R111
54.9_4
54.9_4
R110
R110
54.9_4
54.9_4
H_SCOMP
H_SCOMP#
H_CPURST#<3>
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_SWING
H_RCOMP
H_SCOMP
H_SCOMP#
H_AVREF
H_DVREF
H_A#[35:3] <3>
H_A#[35:32] are not supported in
Calero Interposer
Crestline support 36 bit address
H_ADS# <3>
H_ADSTB0# <3>
H_ADSTB1# <3>
H_BNR# <3>
H_BPRI# <3>
H_BREQ#0 <3>
H_DEFER# <3>
H_DBSY# <3>
CLK_MCH_BCLK <2>
CLK_MCH_BCLK# <2>
H_DPWR# <3>
H_DRDY# <3>
H_HIT# <3>
H_HITM# <3>
H_LOCK# <3>
H_TRDY# <3>
H_DINV#[3:0] <3>
H_DSTBN#[3:0] <3>
H_DSTBP#[3:0] <3>
H_REQ#[4:0] <3>
H_RS#[2:0] <3>H_CPUSLP#<3>
R383
R383
1K_4
A A
1K_4
R382
R382
2K_4
2K_4
5
R384 0_4R384 0_4
C153
C153
<check list>
0.1U close to B9
.1U/10V_4
.1U/10V_4
H_DVREFH_AVREF
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
GMCH HOST(1/7)
GMCH HOST(1/7)
GMCH HOST(1/7)
Date: Sheet
Date: Sheet
4
3
2
Date: Sheet
PROJECT : ZD1
PROJECT : ZD1
Quanta Computer Inc.
Quanta Computer Inc.
538Monday, May 07, 2007
538Monday, May 07, 2007
538Monday, May 07, 2007
1
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E
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of
of
www.RahasiaLaptop.com
5
4
3
2
1
<check list>
For EV@
Connect to GND
D D
L_BKLT_CTRL<18>
INT_LVDS_BLON<23>
R406 10K_4R406 10K_4
+3V
R413 10K_4R413 10K_4
INT_LVDS_EDIDCLK<18>
INT_LVDS_EDIDDATA<18>
INT_LVDS_DIGON<18>
INT_TXLCLKOUT-<18>
INT_TXLCLKOUT+<18>
INT_TXUCLKOUT-<18>
INT_TXUCLKOUT+<18>
INT_TXLOUT0-<18>
INT_TXLOUT1-<18>
INT_TXLOUT2-<18>
INT_TXLOUT0+<18>
INT_TXLOUT1+<18>
INT_TXLOUT2+<18>
INT_TXUOUT0-<18>
INT_TXUOUT1-<18>
INT_TXUOUT2-<18>
INT_TXUOUT0+<18>
INT_TXUOUT1+<18>
INT_TXUOUT2+<18>
INT_TV_COMP<19>
INT_TV_Y/G<19>
INT_TV_C/R<19>
+3V
<FAE>
If no use can be NC
INT_CRT_BLU<19>
INT_CRT_GRN<19>
INT_CRT_RED<19>
INT_CRT_DDCCLK<19>
INT_CRT_DDCDAT<19>
INT_HSYNC<19>
INT_VSYNC<19>
R182 IV@2.4K_4R182 IV@2.4K_4
IV&EV Dis/Enable
setting
R151 *2.2K_4R151 *2.2K_4
R200 *2.2K_4R200 *2.2K_4
R169 IV@39_4R169 IV@39_4
R405 IV@39_4R405 IV@39_4
<check list>
HSYNC/VSYNC
serial R
place close
to NB
<check list & CRB>
For Calero : 1.5K
For Cresstline:2.4K
C C
B B
IV&EV Dis/Enable setting
<check list & CRB>
For Calero : 255
For Cresstline:1.3K/F
For external VGA:0 ohm
R397 0R397 0
<FAE>
Flexible and safe
T45T45
INT_TV_COMP
INT_TV_Y/G
INT_TV_C/R
TV_DCONSEL_0
TV_DCONSEL_1
INT_CRT_BLU
INT_CRT_GRN
INT_CRT_RED
LVDS_IBG
LVDS_VBG
HSYNC1
CRTIREF
VSYNC1
U30C
U30C
J40
H39
E39
E40
C37
D35
K40
L41
L43
N41
N40
D46
C45
D44
E42
G51
E51
F49
G50
E50
F48
G44
B47
B45
E44
A47
A45
E27
G27
K27
F27
J27
L27
M35
P33
H32
G32
K29
J29
F29
E29
K33
G35
F33
C32
E33
CRESTLINE_1p0
CRESTLINE_1p0
L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK
LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
TVA_DAC
TVB_DAC
TVC_DAC
TVA_RTN
TVB_RTN
TVC_RTN
TV_DCONSEL_0
TV_DCONSEL_1
CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC
PEG_COMPI
PEG_COMPO
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
LVDS
LVDS
TV VGA
TV VGA
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PCI-EXPRESS GRAPHICS
PCI-EXPRESS GRAPHICS
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
<check list>
Vcc1_5 for Calero
Vcc1_25/Vcc1_05 for Crestline
EXP_A_COMPX
N43
M43
PEG_RXN0
J51
PEG_RXN1
L51
PEG_RXN2
N47
PEG_RXN3
T45
PEG_RXN4
T50
PEG_RXN5
U40
PEG_RXN6
Y44
PEG_RXN7
Y40
PEG_RXN8
AB51
PEG_RXN9
W49
PEG_RXN10
AD44
PEG_RXN11
AD40
PEG_RXN12
AG46
PEG_RXN13
AH49
PEG_RXN14
AG45
PEG_RXN15
AG41
PEG_RXP0
J50
PEG_RXP1
L50
PEG_RXP2
M47
PEG_RXP3
U44
PEG_RXP4
T49
PEG_RXP5
T41
PEG_RXP6
W45
PEG_RXP7
W41
PEG_RXP8
AB50
PEG_RXP9
Y48
PEG_RXP10
AC45
PEG_RXP11
AC41
PEG_RXP12
AH47
PEG_RXP13
AG49
PEG_RXP14
AH45
PEG_RXP15
AG42
N45
U39
U47
N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44
M45
T38
T46
N50
R51
U43
W42
Y47
Y39
AC38
AD47
AC50
AD43
AG39
AE50
AH43
C_PEG_TXN0
C_PEG_TXN1
C_PEG_TXN2
C_PEG_TXN3
C_PEG_TXN4
C_PEG_TXN5
C_PEG_TXN6
C_PEG_TXN7
C_PEG_TXN8
C_PEG_TXN9
C_PEG_TXN10
C_PEG_TXN11
C_PEG_TXN12
C_PEG_TXN13
C_PEG_TXN14
C_PEG_TXN15
C_PEG_TXP0
C_PEG_TXP1
C_PEG_TXP2
C_PEG_TXP3
C_PEG_TXP4
C_PEG_TXP5
C_PEG_TXP6
C_PEG_TXP7
C_PEG_TXP8
C_PEG_TXP9
C_PEG_TXP10
C_PEG_TXP11
C_PEG_TXP12
C_PEG_TXP13
C_PEG_TXP14
C_PEG_TXP15
C305 EV@.1U/10V_4C305 EV@.1U/10V_4
C300 EV@.1U/10V_4C300 EV@.1U/10V_4
C309 EV@.1U/10V_4C309 EV@.1U/10V_4
C307 EV@.1U/10V_4C307 EV@.1U/10V_4
C308 EV@.1U/10V_4C308 EV@.1U/10V_4
C301 EV@.1U/10V_4C301 EV@.1U/10V_4
C316 EV@.1U/10V_4C316 EV@.1U/10V_4
C331 EV@.1U/10V_4C331 EV@.1U/10V_4
C320 EV@.1U/10V_4C320 EV@.1U/10V_4
C311 EV@.1U/10V_4C311 EV@.1U/10V_4
C326 EV@.1U/10V_4C326 EV@.1U/10V_4
C313 EV@.1U/10V_4C313 EV@.1U/10V_4
C322 EV@.1U/10V_4C322 EV@.1U/10V_4
C318 EV@.1U/10V_4C318 EV@.1U/10V_4
C315 EV@.1U/10V_4C315 EV@.1U/10V_4
C329 EV@.1U/10V_4C329 EV@.1U/10V_4
C303 EV@.1U/10V_4C303 EV@.1U/10V_4
C299 EV@.1U/10V_4C299 EV@.1U/10V_4
C306 EV@.1U/10V_4C306 EV@.1U/10V_4
C304 EV@.1U/10V_4C304 EV@.1U/10V_4
C310 EV@.1U/10V_4C310 EV@.1U/10V_4
C302 EV@.1U/10V_4C302 EV@.1U/10V_4
C317 EV@.1U/10V_4C317 EV@.1U/10V_4
C325 EV@.1U/10V_4C325 EV@.1U/10V_4
C321 EV@.1U/10V_4C321 EV@.1U/10V_4
C312 EV@.1U/10V_4C312 EV@.1U/10V_4
C327 EV@.1U/10V_4C327 EV@.1U/10V_4
C324 EV@.1U/10V_4C324 EV@.1U/10V_4
C323 EV@.1U/10V_4C323 EV@.1U/10V_4
C319 EV@.1U/10V_4C319 EV@.1U/10V_4
C314 EV@.1U/10V_4C314 EV@.1U/10V_4
C328 EV@.1U/10V_4C328 EV@.1U/10V_4
IV&EV Dis/Enable setting
+1.05_PEG
R201 24.9/F_4R201 24.9/F_4
PEG_RXN[15:0] <17>
<check list>
SDVO/PCIE/LVDS not
implement
16 lanes NC
PEG_RXP[15:0] <17>
PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15
PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15
CRT R/G/B
TV A/B/C
HSYNC/VSYNC
R167 EV@0_4R167 EV@0_4
R166 EV@0_4R166 EV@0_4
R147 IV@150/F_4R147 IV@150/F_4
R145 IV@150/F_4R145 IV@150/F_4
R144 IV@150/F_4R144 IV@150/F_4
R157 IV@150/F_4R157 IV@150/F_4
R148 IV@150/F_4R148 IV@150/F_4
R155 IV@150/F_4R155 IV@150/F_4
PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13PEG_TXN10
PEG_TXN14
PEG_TXN15
<check list>
For IV@
Connect to 150ohm
CRT R/G/B
TV A/B/C
Connect to 39ohm
HSYNC/VSYNC
HSYNC1
VSYNC1
INT_TV_COMP
INT_TV_Y/G
INT_TV_C/R
INT_CRT_BLU
INT_CRT_GRN
INT_CRT_RED
PEG_TXN[15:0] <17> PEG_TXP[15:0] <17>
PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15
TV_DCONSEL_0
TV_DCONSEL_1
A A
R513 EV@0_4R513 EV@0_4
R514 EV@0_4R514 EV@0_4
INTEL FAE reuqest PD.
PROJECT : ZD1
PROJECT : ZD1
Quanta Computer Inc.
Quanta Computer Inc.
GMCH GRAPHICS(2/7)
GMCH GRAPHICS(2/7)
GMCH GRAPHICS(2/7)
E
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638Monday, May 07, 2007
638Monday, May 07, 2007
638Monday, May 07, 2007
1
5
4
3
2
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
www.RahasiaLaptop.com
5
4
3
2
1
Strapping table
All strap are sampled with respect to the leading edge of the GMCH power ok signal
CFG[17:3] have internal pull-up
CFG[18:19] have internal pull-down
Any CFG signal strapping option not list below should be left NC pin
Pin Name
CFG[2:0]
CFG[4:3]
D D
CFG5
CFG6
CFG7
CFG8
CFG9
CFG[11:10] Reserved
CFG[13:12]
CFG[15:14]
CFG16
CFG[18:17]
CFG19
CFG20
SDVO_CTRLDATA
C C
<check list & CRB>
R Value select
For Calero : 80.6ohm
For Cresstline:20ohm
But check list use 80.6ohm
+3V
R170 10K_4R170 10K_4
R395 10K_4R395 10K_4
R149 10K_4R149 10K_4
B B
MCH_CFG_5
MCH_CFG_9
MCH_CFG_12
MCH_CFG_13
MCH_CFG_16
A A
R138 *4.02K/F_4R138 *4.02K/F_4
R127 *4.02K/F_4R127 *4.02K/F_4
R139 *4.02K/F_4R139 *4.02K/F_4
R137 *4.02K/F_4R137 *4.02K/F_4
R129 *4.02K/F_4R129 *4.02K/F_4
+1.8VSUS
Strap Description
FSB Frequency Select
Reserved
DMI X2 Select
Reserved
CPU Strap
Low Power PCI Express
PCI Express Graphics
Lane Reversal
Clock Un gating
Reserved
FSB Dynamic ODT
Reserved
DMI Lane Reversal
SDVO/PCIe concurrent
SDVO Present
CLK_MCH_OE#
PM_EXTTS#0
PM_EXTTS#1
+SMDDR_VREF
R416
R416
*1K/F_4
*1K/F_4
R418
R418
*1K/F_4
*1K/F_4
5
M_RCOMP#
R417
R417
BK1608LL121
BK1608LL121
+SM_VREF_MCH
C143
C143
C295
C295
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
Configuration
010 = FSB 800MHz
011 = FSB 667MHz
0 = DMI X2
1 = DMI X4 (Default)
0 = Reserved
1 = Mobile CPU (Default)
0 = Normal mode
1 = Low Power mode
0 = Reserved Lanes
1 = Normal operation (Default)
00 = Clock gating disableXOR/ ALLZ/
01 = ALL-Z Mode Enable
10 = XOR Mode Enable
11 = Normal Cperation (Default)
0 = Dynamic ODT disable
1 = Dynamic ODT Enable (Default)
0 = Normal operation
1 = Reverse Lanes (Default)
0 = Only SDVO or PCIE x1 is operation
(Default)
1 = SDVO and PCIE x1 are operating
simultaneously via the PEG port
0 = No SDVO Card present (Default)
1 = SDVO Card Present
INTEL CRB
CRESSTLINE SHOULD USE 20OHM
+1.8VSUS
<FAE>
R387
R387
20/F_4
20/F_4
80.6ohm
M_RCOMP
MCH_CFG_19
MCH_CFG_20
+1.8VSUS
R388
R388
20/F_4
20/F_4
R171 *4.02K/F_4R171 *4.02K/F_4
R174 *4.02K/F_4R174 *4.02K/F_4
R154 1K/F_4R154 1K/F_4
4
+3V
SM_RCOMP_VOH
R165
R165
3.01K/F_4
3.01K/F_4
SM_RCOMP_VOL
C250
C250
R163
R163
.01U/16V_4
.01U/16V_4
1K/F_4
1K/F_4
C241
C241
.01U/16V_4
.01U/16V_4
DELAY_VR_PWRGOOD<3,14,34>
C233
C233
2.2U/6.3V
2.2U/6.3V
PM_BMBUSY#<14>
ICH_DPRSTP#<3,12,34>
PM_EXTTS#0<16>
PM_EXTTS#1<16>
PM_THRMTRIP#<3,12>
PM_DPRSLPVR<14,34>
C232
C232
2.2U/6.3V
2.2U/6.3V
INTEL CRB
ADD 0.1UF
MCH_BSEL0<2>
MCH_BSEL1<2>
PLTRST#_NB<13>
MCH_BSEL2<2>
CLK_DREFCLK
CLK_DREFCLK#
CLK_DREFSSCLK
CLK_DREFSSCLK#
T30T30
T75T75
T34T34
T24T24
T29T29
T37T37
T28T28
T25T25
T27T27
T32T32
T40T40
R184 0_4R184 0_4
R177 0_4R177 0_4
R401 0_4R401 0_4
R150 0_4R150 0_4
R140 100_4R140 100_4
R130 *0_4R130 *0_4
R407 0_4R407 0_4
R409 *4.7K_4R409 *4.7K_4
R529 EV@0_4R529 EV@0_4
R531 EV@0_4R531 EV@0_4
R411 *4.7K_4R411 *4.7K_4
R532 EV@0_4R532 EV@0_4
R533 EV@0_4R533 EV@0_4
PM_THRMTRIP#_GMCH
PM_DPRSLPVR_GMCH
INTEL FAE suggest PD for external graphics
3
C165 .1U/10V_4C165 .1U/10V_4
MCH_CFG_3
MCH_CFG_4
MCH_CFG_5
MCH_CFG_6
MCH_CFG_7
MCH_CFG_8
MCH_CFG_9
MCH_CFG_10
MCH_CFG_11
MCH_CFG_12
MCH_CFG_13
MCH_CFG_14
MCH_CFG_15
MCH_CFG_16
MCH_CFG_17
MCH_CFG_18
MCH_CFG_19
MCH_CFG_20
PM_BMBUSY#_R
ICH_DPRSTP#_R
PM_EXTTS#0_R
PM_EXTTS#1_R
RST_IN#_MCH
+1.25V
AR12
AR13
AM12
AN13
AR37
AM36
AL36
AM37
BJ20
BK22
BF19
BH20
BK18
BJ18
BF23
BG23
BC23
BD24
BH39
AW20
BK20
AW49
AV20
BJ51
BK51
BK50
BL50
BL49
P36
P37
R35
N35
J12
D20
H10
B51
C48
D47
B44
C44
A35
B37
B36
B34
C34
P27
N27
N24
C21
C23
F23
N23
G23
J20
C20
R24
L23
J23
E23
E20
K23
M20
M24
L32
N33
L35
G41
L39
L36
J36
N20
G36
BL3
BL2
BK1
BJ1
C51
B50
A50
A49
BK2
U30B
U30B
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
PM_BM_BUSY#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
E1
NC_10
A5
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
CRESTLINE_1p0
CRESTLINE_1p0
0C Delete R410 and R408 0110
SM_CK_0
SM_CK_1
SM_CK_3
SM_CK_4
SM_CK#_0
SM_CK#_1
SM_CK#_3
SM_CK#_4
SM_CKE_0
SM_CKE_1
SM_CKE_3
SM_CKE_4
SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3
DDR MUXING
DDR MUXING
SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3
SM_RCOMP
SM_RCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_VREF_0
SM_VREF_1
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
PEG_CLK
CLK
CLK
PEG_CLK#
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI
DMI
DMI_TXN_1
CFGRSVD
CFGRSVD
PM
PM
NC
NC
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VR_EN
GRAPHICS VID
GRAPHICS VID
CL_DATA
CL_PWROK
CL_VREF
ME
ME
SDVO_CTRL_CLK
SDVO_CTRL_DATA
CLK_REQ#
ICH_SYNC#
MISC
MISC
2
CL_CLK
CL_RST#
TEST_1
TEST_2
AV29
BB23
BA25
AV23
AW30
BA23
AW25
AW23
BE29
AY32
BD39
BG37
BG20
BK16
BG16
BE13
BH18
BJ15
BJ14
BE16
BL15
BK14
BK31
BL31
AR49
AW4
B42
C42
H48
H47
K44
K45
AN47
AJ38
AN42
AN46
AM47
AJ39
AN41
AN45
AJ46
AJ41
AM40
AM44
AJ47
AJ42
AM39
AM43
E35
A39
C38
B39
E36
AM49
AK50
AT43
AN49
AM50
H35
K36
G39
G40
A37
R32
M_CLK0 <16>
M_CLK1 <16>
M_CLK2 <16>
M_CLK3 <16>
M_CLK#0 <16>
M_CLK#1 <16>
M_CLK#2 <16>
M_CLK#3 <16>
M_CKE0 <16>
M_CKE1 <16>
M_CKE2 <16>
M_CKE3 <16>
M_CS#0 <16>
M_CS#1 <16>
M_CS#2 <16>
M_CS#3 <16>
M_ODT0 <16>
M_ODT1 <16>
M_ODT2 <16>
M_ODT3 <16>
M_RCOMP
M_RCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
+SM_VREF_MCH
CLK_DREFCLK
CLK_DREFCLK#
CLK_DREFSSCLK
CLK_DREFSSCLK#
CLK_PCIE_3GPLL
CLK_PCIE_3GPLL#
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
MCH_GFX_VID_0
MCH_GFX_VID_1
MCH_GFX_VID_2
MCH_GFX_VID_3
R183 *0_4R183 *0_4
+1.25V_CL_VREF
CLK_MCH_OE#
GMCH_TEST1
GMCH_TEST2
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
DMI_TXN[3:0] <13>
DMI_TXP[3:0] <13>
DMI_RXN[3:0] <13>
DMI_RXP[3:0] <13>
CL_CLK0 <14>
CL_DATA0 <14>
MPWROK <14,31>
CL_RST#0 <14>
MCH_ICH_SYNC# <14>
R178 0_4R178 0_4
R168 20K_4R168 20K_4
PROJECT : ZD1
PROJECT : ZD1
Quanta Computer Inc.
Quanta Computer Inc.
GMCH (STRAPPING/OTHER 3/7)
GMCH (STRAPPING/OTHER 3/7)
GMCH (STRAPPING/OTHER 3/7)
CLK_DREFCLK <2>
CLK_DREFCLK# <2>
CLK_DREFSSCLK <2>
CLK_DREFSSCLK# <2>
CLK_PCIE_3GPLL <2>
CLK_PCIE_3GPLL# <2>
T41T41
T42T42
T43T43
T44T44
SUSB# <14,31>
C559
C559
.1U/10V_4
.1U/10V_4
1
+1.25V
738Monday, May 07, 2007
738Monday, May 07, 2007
738Monday, May 07, 2007
R422
R422
1K/F_4
1K/F_4
R420
R420
392/F
392/F
of
of
of
E
E
E
www.RahasiaLaptop.com
5
4
3
2
1
NB(Memory controller)
D D
M_A_DQ[63:0]<16>
C C
B B
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
AR43
AW44
BA45
AY46
AR41
AR45
AT42
AW47
BB45
BF48
BG47
BJ45
BB47
BG50
BH49
BE45
AW43
BE44
BG42
BE40
BF44
BH45
BG40
BF40
AR40
AW40
AT39
AW36
AW41
AY41
AV38
AT38
AV13
AT13
AW11
AV11
AU15
AT11
BA13
BA11
BE10
BD10
BG10
AW9
AM8
AN10
AN9
AM9
AN11
BD8
AY9
BD7
BB9
BB5
AY7
AT5
AT7
AY6
BB7
AR5
AR8
AR9
AN3
AT9
U30D
U30D
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
CRESTLINE_1p0
CRESTLINE_1p0
BB19
SA_BS_0
BK19
SA_BS_1
BF29
SA_BS_2
BL17
SA_CAS#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
SA_RAS#
SA_RCVEN#
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
SA_WE#
M_A_DM0
AT45
M_A_DM1
BD44
M_A_DM2
BD42
M_A_DM3
AW38
M_A_DM4
AW13
M_A_DM5
BG8
M_A_DM6
AY5
M_A_DM7
AN6
M_A_DQS0
AT46
M_A_DQS1
BE48
M_A_DQS2
BB43
M_A_DQS3
BC37
M_A_DQS4
BB16
M_A_DQS5
BH6
M_A_DQS6
BB2
M_A_DQS7
AP3
M_A_DQS#0
AT47
M_A_DQS#1
BD47
M_A_DQS#2
BC41
M_A_DQS#3
BA37
M_A_DQS#4
BA16
M_A_DQS#5
BH7
M_A_DQS#6
BC1
M_A_DQS#7
AP2
M_A_A0
BJ19
M_A_A1
BD20
M_A_A2
BK27
M_A_A3
BH28
M_A_A4
BL24
M_A_A5
BK28
M_A_A6
BJ27
M_A_A7
BJ25
M_A_A8
BL28
M_A_A9
BA28
M_A_A10
BC19
M_A_A11
BE28
M_A_A12
BG30
M_A_A13
BJ16
M_A_A14 M_B_A14
BJ29
BE18
TP_SA_RCVEN#
AY20
BA19
M_A_BS0 <16>
M_A_BS1 <16>
M_A_BS2 <16>
M_A_CAS# <16>
M_A_DM[7:0] <16>
M_A_DQS[7:0] <16>
M_A_DQS#[7:0] <16>
M_A_A[13:0] <16>
M_A_A14 <16> M_B_A14 <16>
M_A_RAS# <16>
T35T35
M_A_WE# <16>
M_B_DQ[63:0]<16>
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
AP49
AR51
AW50
AW51
AN51
AN50
AV50
AV49
BA50
BB50
BA49
BE50
BA51
AY49
BF50
BF49
BJ50
BJ44
BJ43
BL43
BK47
BK49
BK43
BK42
BJ41
BL41
BJ37
BJ36
BK41
BJ40
BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12
BJ10
BK10
BH5
BG1
BC2
BD3
AR1
AU2
BL9
BK5
BL5
BK9
BJ8
BJ6
BF4
BK3
BE4
BJ2
BA3
BB3
AT3
AY2
AY3
AT2
U30E
U30E
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
CRESTLINE_1p0
CRESTLINE_1p0
AY17
SB_BS_0
BG18
SB_BS_1
BG36
SB_BS_2
BE17
SB_CAS#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
SB_RAS#
SB_RCVEN#
SB_WE#
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
AR50
BD49
BK45
BL39
BH12
BJ7
BF3
AW2
AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3
BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13
BE24
AV16
AY18
BC17
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
TP_SB_RCVEN#
M_B_BS0 <16>
M_B_BS1 <16>
M_B_BS2 <16>
M_B_CAS# <16>
M_B_DM[7:0] <16>
M_B_DQS[7:0] <16>
M_B_DQS#[7:0] <16>
M_B_A[13:0] <16>
M_B_RAS# <16>
T26T26
M_B_WE# <16>
A A
PROJECT : ZD1
PROJECT : ZD1
Quanta Computer Inc.
Quanta Computer Inc.
GMCH DDR(4/7)
GMCH DDR(4/7)
GMCH DDR(4/7)
E
E
E
of
of
of
838Monday, May 07, 2007
838Monday, May 07, 2007
838Monday, May 07, 2007
1
5
4
3
2
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
www.RahasiaLaptop.com
5
4
3
2
1
NB(Power-1)
+1.05V
U30G
U30G
AT35
VCC_1
AT34
VCC_2
AH28
D D
0C Delete R156 0104
+1.8VSUS
+
+
C247
C254
C254
.1U/10V_4
.1U/10V_4
C C
B B
A A
C552
C552
330U/2V_7
330U/2V_7
C247
10U/10V_8
10U/10V_8
C249
C249
10U/10V_8
10U/10V_8
+1.05V_AXG
AC32
AC31
AK32
AJ31
AJ28
AH32
AH31
AH29
AF32
AU32
AU33
AU35
AV33
AW33
AW35
AY35
BA32
BA33
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35
BJ32
BJ33
BJ34
BK32
BK33
BK34
BK35
BL33
AU30
W13
W14
AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31
AJ20
AN14
R30
R20
T14
Y12
VCC_3
VCC_5
VCC_4
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36
VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC CORE
VCC CORE
POWER
POWER
VCC SMVCC GFX
VCC SMVCC GFX
VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC GFX NCTF
VCC GFX NCTF
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
VCC SM LF
VCC SM LF
T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31
AW45
BC39
BE39
BD17
BD4
AW8
AT6
+1.05V_AXG
VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7
+1.05V
+1.05V_AXG
+
+
C521
C521
IV@330U_7
IV@330U_7
+1.05V_AXG
R152
R152
EV@0_4
EV@0_4
C156
C156
.1U/10V_4
.1U/10V_4
+1.05V_AXG
R100 IV@0_8R100 IV@0_8
R118 IV@0_8R118 IV@0_8
+
+
C522
C522
IV@330U_7
IV@330U_7
+1.05V
C239
C239
10U/10V_8
10U/10V_8
C154
C154
.1U/10V_4
.1U/10V_4
+1.05V_AXG
C151
C151
.22U/6.3V_4
.22U/6.3V_4
C191
C191
IV@.47U
IV@.47U
C174
C174
IV@1U
IV@1U
C235
C235
.22U/6.3V_4
.22U/6.3V_4
C171
C171
.22U/6.3V_4
.22U/6.3V_4
+1.05V
C238
C238
10U/10V_8
10U/10V_8
C172
C172
IV@10U_8
IV@10U_8
C262
C262
.22U/6.3V_4
.22U/6.3V_4
C252
C252
.22U/6.3V_4
.22U/6.3V_4
C264
C264
.47U/10V
.47U/10V
C201
C201
IV@.1U_4
IV@.1U_4
C203
C203
.1U/10V_4
.1U/10V_4
C257
C257
1U/16V
1U/16V
C243
C243
.22U/6.3V_4
.22U/6.3V_4
C185
C185
IV@.1U_4
IV@.1U_4
C220
C220
.1U/10V_4
.1U/10V_4
C291
C291
1U/16V
1U/16V
C214
C214
.1U/10V_4
.1U/10V_4
C263
C263
.1U/10V_4
.1U/10V_4
AB33
AB36
AB37
AC33
AC35
AC36
AD35
AD36
AF33
AF36
AH33
AH35
AH36
AH37
AJ33
AJ35
AK33
AK35
AK36
AK37
AD33
AJ36
AM35
AL33
AL35
AA33
AA35
AA36
AP35
AP36
AR35
AR36
AL24
AL26
AL28
AM26
AM28
AM29
AM31
AM32
AM33
AP29
AP31
AP32
AP33
AL29
AL31
AL32
AR31
AR32
AR33
Y32
Y33
Y35
Y36
Y37
T30
T34
T35
U29
U31
U32
U33
U35
U36
V32
V33
V36
V37
U30F
U30F
CRESTLINE_1p0
CRESTLINE_1p0
VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
VCC_NCTF_45
VCC_NCTF_46
VCC_NCTF_47
VCC_NCTF_48
VCC_NCTF_49
VCC_NCTF_50
VCC_AXM_NCTF_1
VCC_AXM_NCTF_2
VCC_AXM_NCTF_3
VCC_AXM_NCTF_4
VCC_AXM_NCTF_5
VCC_AXM_NCTF_6
VCC_AXM_NCTF_7
VCC_AXM_NCTF_8
VCC_AXM_NCTF_9
VCC_AXM_NCTF_10
VCC_AXM_NCTF_11
VCC_AXM_NCTF_12
VCC_AXM_NCTF_13
VCC_AXM_NCTF_14
VCC_AXM_NCTF_15
VCC_AXM_NCTF_16
VCC_AXM_NCTF_17
VCC_AXM_NCTF_18
VCC_AXM_NCTF_19
VSS NCTF
VSS NCTF
VCC NCTF
VCC NCTF
POWER
POWER
VCC AXM NCTF
VCC AXM NCTF
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_SCB1
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6
VSS SCBVCC AXM
VSS SCBVCC AXM
VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_5
VCC_AXM_6
VCC_AXM_7
T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28
A3
B2
C1
BL1
BL51
A51
AT33
AT31
AK29
AK24
AK23
AJ26
AJ23
+1.05V
CRESTLINE_1p0
CRESTLINE_1p0
5
4
3
2
PROJECT : ZD1
PROJECT : ZD1
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
Quanta Computer Inc.
GMCH Power-1(5/7)
GMCH Power-1(5/7)
GMCH Power-1(5/7)
of
of
of
938Wednesday, April 25, 2007
938Wednesday, April 25, 2007
938Wednesday, April 25, 2007
1
E
E
E
www.RahasiaLaptop.com
5
NB(Power-2)
+1.25V
D D
+1.25V
+1.25V
C C
+3V
B B
IV&EV Dis/Enable setting
+1.5V
A A
L50 10UH_8L50 10UH_8
+
+
L24 10UH_8L24 10UH_8
+
+
C132 22U/6.3V_8C132 22U/6.3V_8
CRB RECOMMEND
180OHM@100MHz
Rdc= 0.09OHM (max)
L21
L21
IV@BKP1608HS181-T
IV@BKP1608HS181-T
C540
C540
IV@22U_8
IV@22U_8
C543
C543
IV@10U_8
IV@10U_8
R402 0R402 0
R153 IV@100R153 IV@100
Change to
100 ohm Resistor
5
C557
C557
C558
C558
.1U/10V_4
.1U/10V_4
470U/2V_7
470U/2V_7
C296
C296
C338
C338
.1U/10V_4
.1U/10V_4
470U/2V_7
470U/2V_7
L14 BKP1608HS181-TL14 BKP1608HS181-T
L15 BKP1608HS181-TL15 BKP1608HS181-T
V1.25M_MPLL_RC
+1.25V
C198
C198
IV@.1U_4
IV@.1U_4
C229
C229
IV@.1U_4
IV@.1U_4
C226
C226
IV@.1U_4
IV@.1U_4
C535
C535
+
+
100U/10V_7
100U/10V_7
C227
C227
IV@22N_4
IV@22N_4
C228
C228
IV@22N_4
IV@22N_4
C215
C215
IV@22N_4
IV@22N_4
<FAE>
INT VGA disable
VCCD_TVDAC still +1.5V
C218
C218
C217
C217
.1U/10V_4
.1U/10V_4
22N/16V_4
22N/16V_4
C219
C219
IV@.1U_4
IV@.1U_4
R172 IV@0R172 IV@0
+3V
<FAE>
INT VGA disable
VCCSYNC connect to GND
L47 IV@BKP1608HS181-TL47 IV@BKP1608HS181-T
+3V
+3V_TV_DAC
C547
C547
*IV@22U_8
*IV@22U_8
R396 IV@0R396 IV@0
IV&EV Dis/Enable setting
C145
C145
C135
C135
.1U/10V_4
.1U/10V_4
22U/6.3V_8
22U/6.3V_8
C136
C136
R106
R106
0.5/F
0.5/F
.1U/10V_4
.1U/10V_4
R390 0R390 0
+1.25V
R135
R135
EV@0_4
EV@0_4
R136
R136
EV@0_4
EV@0_4
R146
R146
EV@0_4
EV@0_4
C200
C200
IV@22N_4
IV@22N_4
C539
C539
*22U_8
*22U_8
R185 0R185 0
R133
R133
EV@0_4
EV@0_4
+1.8VSUS
+1.25V
4
C246
C246
IV@.1U_4
IV@.1U_4
C237
C237
IV@.1U_4
IV@.1U_4
C544
C544
IV@.1U_4
IV@.1U_4
R179 IV@0R179 IV@0
R415 0_8R415 0_8
+3V
C173
C173
4.7U/10V
4.7U/10V
C265
C265
C253
C253
*1U
*1U
*1U
*1U
R173 EV@0_4R173 EV@0_4
R164 IV@0R164 IV@0
+1.25V
L23 BKP1608HS181-TL23 BKP1608HS181-T
+V1.25S_PEGPLL_FB
C341
C341
2.2U/10V_8
2.2U/10V_8
R414 IV@0R414 IV@0
+1.8VSUS
C189
C189
IV@1U
IV@1U
Use site for filter
cap with Gfx
enabled CS
4
C245
C245
IV@22N_4
IV@22N_4
C546
C546
IV@22N_4
IV@22N_4
EV@0_4
EV@0_4
C538
C538
22U/6.3V_8
22U/6.3V_8
C258
C258
22U/6.3V_8
22U/6.3V_8
R105 0R105 0
R403
R403
EV@0_4
EV@0_4
R186
R186
C297
C297
.1U/10V_4
.1U/10V_4
C163
C163
1U/16V
1U/16V
C225
C225
.1U/10V_4
.1U/10V_4
C142
C142
.1U/10V_4
.1U/10V_4
R203
R203
1/F_8
1/F_8
C279
C279
IV@1U
IV@1U
R162
R162
EV@0_4
EV@0_4
R404
R404
EV@0_4
EV@0_4
3
CRT/TV Disable/Enable guideline
External VGA with EV@part, Internal VGA with IV@ part
Ball
VCCA_CRT
VCCD_CRT
VCCDQ_CRT
VCCA_A_TVO
VCCA_B_TVO
+3V_VCCSYNC
+3V_VCCA_CRT_DAC
+3V_VCCA_DAC_BG
+1.25V_VCCA_DPLLA
+1.25V_VCCA_DPLLB
+1.25VM_VCCA_HPLL
+1.25VM_VCCA_MPLL
+1.8VSUS_VCC_LVDS
C270
C270
IV@1000P_4
IV@1000P_4
+3V_VCCA_PEG_BG
+1.25V_VCCD_PEG_PLL
+1.25VM_VCCA_SM
+1.25VM_VCCA_SM_CK
+3V_TV_DAC
+1.5V_VCCD_CRT
+1.5V_VCCD_TVDAC
+1.5V_VCCD_QDAC
+1.25VM_MCH_VCCD_HPLL
+1.25V_VCCD_PEG_PLL
+
+
+1.8V_VCCD_LVDS
C334
C334
220U/2.5V_7
220U/2.5V_7
C555
C555
*IV@10U_8
*IV@10U_8
C298
C298
.1U/10V_4
.1U/10V_4
Enable
3.3V
1.5V
1.5V
3.3V
3.3V
R187
R187
EV@0_4
EV@0_4
AW18
AV19
AU19
AU18
AU17
AT22
AT21
AT19
AT18
AT17
AR17
AR16
BC29
BB29
Ball
Disable
VCCA_C_TVO
GND
GND
VCCD_TVO
GND
VCCABG_DAC GND
VSSABG_DAC
GND
GND
U30H
U30H
J32
VCCSYNC
A33
VCCA_CRT_DAC_1
B33
VCCA_CRT_DAC_2
A30
VCCA_DAC_BG
B32
VSSA_DAC_BG
B49
VCCA_DPLLA
H49
VCCA_DPLLB
AL2
VCCA_HPLL
AM2
VCCA_MPLL
A41
VCCA_LVDS
B41
VSSA_LVDS
K50
VCCA_PEG_BG
K49
VSSA_PEG_BG
U51
VCCA_PEG_PLL
VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
VCCA_SM_10
VCCA_SM_11
VCCA_SM_NCTF_1
VCCA_SM_NCTF_2
VCCA_SM_CK_1
VCCA_SM_CK_2
C25
VCCA_TVA_DAC_1
B25
VCCA_TVA_DAC_2
C27
VCCA_TVB_DAC_1
B27
VCCA_TVB_DAC_2
B28
VCCA_TVC_DAC_1
A28
VCCA_TVC_DAC_2
M32
VCCD_CRT
L29
VCCD_TVDAC
N28
VCCD_QDAC
AN2
VCCD_HPLL
U48
VCCD_PEG_PLL
J41
VCCD_LVDS_1
H42
VCCD_LVDS_2
CRESTLINE_1p0
CRESTLINE_1p0
+1.05V
+3V
3
2
Enable
Disable
GND GND
3.3V
1.5V
GND
3.3V
GND
GND
GND
3.3VVCC_SYNC
U13
VTT_1
U12
VTT_2
U11
VTT_3
U9
VTT_4
U8
VTT_5
U7
VTT_6
U5
VTT_7
CRTPLLA PEGA SMTV
CRTPLLA PEGA SMTV
AXD
AXD
VCC_AXD_NCTF
POWER
POWER
A CK A LVDS
A CK A LVDS
D TV/CRTLVDS
D TV/CRTLVDS
<CRB>
+1.25V AND +1.25M shall be
+1.5V for Calero Interposer
D41
D41
2 1
PDZ5.6B
PDZ5.6B
AXF
AXF
VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4
SM CK
SM CK
VCC_TX_LVDS
PEG
PEG
VCC_RXR_DMI_1
VCC_RXR_DMI_2
DMI
DMI
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT
VTT
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VCC_AXD_1
VCC_AXD_2
VCC_AXD_3
VCC_AXD_4
VCC_AXD_5
VCC_AXD_6
VCC_AXF_1
VCC_AXF_2
VCC_AXF_3
VCC_DMI
VCC_HV_1
VCC_HV_2
HV
HV
VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5
VTTLF1
VTTLF2
VTTLF3
VTTLF
VTTLF
+1.05V_SD
U3
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1
AT23
AU28
AU24
AT29
AT25
AT30
AR29
+1.25V_VCC_AXF
B23
B21
A21
+1.25V_VCC_DMI
AJ50
+1.8VSUS_VCC_SM_CK
BK24
BK23
BJ24
BJ23
+1.8VSUS_VCC_TX_LVDS
A43
C40
B40
AD51
W50
W51
V49
V50
AH50
AH51
A7
F2
AH1
C138
C138
.47U/6.3V_4
.47U/6.3V_4
R51510R515
10
R181 0R181 0
+1.25VM_AXD
+3V_VCC_HV
C524
C524
.47U/6.3V_4
.47U/6.3V_4
2
LVDS Disable/Enable guideline
External VGA with EV@part,Internal VGA with IV@ part
Signal
VCCD_LVDS
VCCA_LVDS
VCCTX_LVDS
C221
C221
1U/16V
1U/16V
2.2U/10V_8
2.2U/10V_8
C202
C202
*22U_8
*22U_8
C192
C192
.1U/10V_4
.1U/10V_4
If SDVO Disable
LVDS Disable
GND
EXTERNAL
C134
C134
R134 0R134 0
C196
C196
1U/16V
1U/16V
C542
C542
22U/6.3V_8
22U/6.3V_8
C144
C144
2.2U/10V_8
2.2U/10V_8
R124 0R124 0
C182
C182
10U/10V_8
10U/10V_8
R421 0R421 0
C560
C560
.1U/10V_4
.1U/10V_4
L46 1UH_8L46 1UH_8
R391 1/FR391 1/F
If SDVO enable
LVDS Disable
1.8V
GND
GND
C137
C137
.47U/10V
.47U/10V
+
+
C523
C523
330U/2V_7
330U/2V_7
+1.25V
+V1.8_SMCK_RC
IV&EV Dis/Enable setting
C554
C554
R412
R412
IV@1000P_4
IV@1000P_4
EV@0_4
EV@0_4
+1.05_PEG
L22 91nHL22 91nH
+
+
C330
C330
C332
C532
C532
.47U/6.3V_4
.47U/6.3V_4
+3V_VCC_HV
C269
C269
.1U/10V_4
.1U/10V_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
GMCH Power-2(6/7)
GMCH Power-2(6/7)
GMCH Power-2(6/7)
Date: Sheet
Date: Sheet
Date: Sheet
C332
2.2U/10V_8
2.2U/10V_8
220U/2.5V_7
220U/2.5V_7
PROJECT : ZD1
PROJECT : ZD1
Quanta Computer Inc.
Quanta Computer Inc.
1
If SDVO enable
LVDS enable
1.8V
1.8V1.5V
1.8V
INTERNAL
+1.05V
+1.25V
+1.25V
+1.8VSUS
C541 22U/6.3V_8C541 22U/6.3V_8
L48 IV@1UH_8L48 IV@1UH_8
+
+
C553
C553
IV@220U_7
IV@220U_7
<FAE>
VCC_RXR_DMI and VCC_PEG
connect to+1.05V
1
+1.8VSUS
+1.05V
of
of
of
10 38Wednesday, April 25, 2007
10 38Wednesday, April 25, 2007
10 38Wednesday, April 25, 2007
E
E
E
www.RahasiaLaptop.com
5
4
3
2
1
NB(Power-3)
U30I
AA21
AA24
AA29
AB20
AB23
AB26
AB28
AB31
AC10
AC13
AC39
AC43
AC47
AD21
AD26
AD29
AD41
AD45
AD49
AD50
AE10
AE14
AF20
AF23
AF24
AF31
AG38
AG43
AG47
AG50
AH40
AH41
AJ11
AJ13
AJ21
AJ24
AJ29
AJ32
AJ43
AJ45
AJ49
AK20
AK21
AK26
AK28
AK31
AK51
AM11
AM13
AM3
AM4
AM41
AM45
AN38
AN39
AN43
AP48
AP50
AR11
AR39
AR44
AR47
AT10
AT14
AT41
AT49
AU23
AU29
AU36
AU49
AU51
AV39
AV48
AW1
AW12
AW16
AG2
AH3
AH7
AH9
AN1
AN5
AN7
AP4
AR2
AR7
AU1
AU3
A13
A15
A17
A24
AC3
AD1
AD3
AD5
AD8
AE6
AL1
U30I
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
CRESTLINE_1p0
CRESTLINE_1p0
VSS
VSS
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41
4
U30J
U30J
C46
VSS_199
C50
VSS_200
C7
VSS_201
D13
VSS_202
D24
VSS_203
D3
VSS_204
D32
VSS_205
D39
VSS_206
D45
VSS_207
D49
VSS_208
E10
VSS_209
E16
VSS_210
E24
VSS_211
E28
VSS_212
E32
VSS_213
E47
VSS_214
F19
VSS_215
F36
VSS_216
F4
VSS_217
F40
VSS_218
F50
VSS_219
G1
VSS_220
G13
VSS_221
G16
VSS_222
G19
VSS_223
G24
VSS_224
G28
VSS_225
G29
VSS_226
G33
VSS_227
G42
VSS_228
G45
VSS_229
G48
VSS_230
G8
VSS_231
H24
VSS_232
H28
VSS_233
H4
VSS_234
H45
VSS_235
J11
VSS_236
J16
VSS_237
J2
VSS_238
J24
VSS_239
J28
VSS_240
J33
VSS_241
J35
J39
K12
K47
K8
L1
L17
L20
L24
L28
L3
L33
L49
M28
M42
M46
M49
M5
M50
M9
N11
N14
N17
N29
N32
N36
N39
N44
N49
N7
P19
P2
P23
P3
P50
R49
T39
T43
T47
U41
U45
U50
V2
V3
CRESTLINE_1p0
CRESTLINE_1p0
3
VSS_242
VSS_243
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS
VSS
2
W11
VSS_287
W39
VSS_288
W43
VSS_289
W47
VSS_290
W5
VSS_291
W7
VSS_292
Y13
VSS_293
Y2
VSS_294
Y41
VSS_295
Y45
VSS_296
Y49
VSS_297
Y5
VSS_298
Y50
VSS_299
Y11
VSS_300
P29
VSS_301
T29
VSS_302
T31
VSS_303
T33
VSS_304
R28
VSS_305
AA32
VSS_306
AB32
VSS_307
AD32
VSS_308
AF28
VSS_309
AF29
VSS_310
AT27
VSS_311
AV25
VSS_312
H50
VSS_313
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
0C Delete R142,R197,R198,R143 0104
PROJECT : ZD1
PROJECT : ZD1
Quanta Computer Inc.
Quanta Computer Inc.
GMCH Power-3(7/7)
GMCH Power-3(7/7)
GMCH Power-3(7/7)
1
E
E
E
of
of
of
11 38Wednesday, April 25, 2007
11 38Wednesday, April 25, 2007
11 38Wednesday, April 25, 2007
D D
C C
B B
A A
5
www.RahasiaLaptop.com
RTC
5
4
3
2
1
D D
+3VPCU
R_3VRTC RTC_RST#
R319
R319
1K_4
1K_4
RTC_N02
CN39
CN39
1
2
3
4
RTC CONN
RTC CONN
C C
SB Strap
+VCCRTC
B B
HDA
ACZ_SDOUT
+VCCRTC
2 1
D27 RB500VD27 RB500V
2 1
D28 RB500VD28 RB500V
1 3
INTVRMEN Low = Internal VR disable
LAN100_SLP Low = Internal VR disable
R259
R259
332K/F
332K/F
ICH_INTVRMEN
R264
R264
*0_4
*0_4
R291 33_4R291 33_4
R307 33_4R307 33_4
R348 20K_4R348 20K_4
C499
C499
1U/10V
1U/10V
R331 1KR331 1K
Q20
Q20
MMBT3904
MMBT3904
2
High = Internal VR enable(Default)
High = Internal VR enable(Default)
R326 1.2KR326 1.2K
RTC_N03
+VCCRTC
ACZ_SDOUT_AUDIO <26>
ACZ_SDOUT_MDC <26>
C506
C506
1U/10V
1U/10V
R252
R252
332K/F
332K/F
LAN100_SLP
R263
R263
*0_4
*0_4
12
JP5
JP5
*RTC_RST
*RTC_RST
+5VPCU
R320
R320
47K
47K
R314 150KR314 150K
SATA_RXN0<24>
SATA_RXP0<24>
SATA_TXN0<24>
SATA_TXP0<24>
SATA_RXN1<24>
SATA_RXP1<24>
SATA_TXN1<24>
SATA_TXP1<24>
C461 10P/50V_4C461 10P/50V_4
Y3
Y3
32.768KHZ
32.768KHZ
C448 18P/50V_4C448 18P/50V_4
+VCCRTC
C628 3900P/25V_4C628 3900P/25V_4
C629 3900P/25V_4C629 3900P/25V_4
C627 *3900P/25V_4C627 *3900P/25V_4
C626 *3900P/25V_4C626 *3900P/25V_4
R280
R280
10M
10M
2 1
R304 1M_4R304 1M_4
T69T69
ACZ_SDIN0<26>
ACZ_SDIN1<26>
ACZ_SDOUT<14>
SATA_LED#<30>
CLK_PCIE_SATA#<2>
CLK_PCIE_SATA<2>
R277 24.9/F_4R277 24.9/F_4
<check list>
L<500mils
T83T83
T61T61
T65T65
T71T71
CLK_32KX1
CLK_32KX2
RTC_RST#
ICH_INTRUDER#
ICH_INTVRMEN
ICH_GPIO13
ACZ_BCLK
ACZ_SYNC
ACZ_RST#
ACZ_SDIN2
ACZ_SDIN3
ACZ_SDOUT
GPIO33#
GPIO34#
SATA_LED#
SATA_TXN0_C
SATA_TXP0_C
SATA_TXN1_C
SATA_TXP1_C
SATA_BIAS
U34A
U34A
AG25
RTCX1
AF24
RTCX2
AF23
RTCRST#
AD22
INTRUDER#
AF25
INTVRMEN
AD21
LAN100_SLP
B24
GLAN_CLK
D22
LAN_RSTSYNC
C21
LAN_RXD0
B21
LAN_RXD1
C22
LAN_RXD2
D21
LAN_TXD0
E20
LAN_TXD1
C20
LAN_TXD2
AH21
GLAN_DOCK#/GPIO13
D25
GLAN_COMPI
C25
GLAN_COMPO
AJ16
HDA_BIT_CLK
AJ15
HDA_SYNC
AE14
HDA_RST#
AJ17
HDA_SDIN0
AH17
HDA_SDIN1
AH15
HDA_SDIN2
AD13
HDA_SDIN3
AE13
HDA_SDOUT
AE10
HDA_DOCK_EN#/GPIO33
AG14
HDA_DOCK_RST#/GPIO34
AF10
SATALED#
AF6
SATA0RXN
AF5
SATA0RXP
AH5
SATA0TXN
AH6
SATA0TXP
AG3
SATA1RXN
AG4
SATA1RXP
AJ4
SATA1TXN
AJ3
SATA1TXP
AF2
SATA2RXN
AF1
SATA2RXP
AE4
SATA2TXN
AE3
SATA2TXP
AB7
SATA_CLKN
AC6
SATA_CLKP
AG1
SATARBIAS#
AG2
SATARBIAS
ICH8M REV 1.0
ICH8M REV 1.0
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
FWH4/LFRAME#
LDRQ0#
LDRQ1#/GPIO23
RTCLAN / GLAN
LPCCPU
RTCLAN / GLAN
LPCCPU
A20GATE
A20M#
DPRSTP#
DPSLP#
FERR#
CPUPWRGD/GPIO49
IGNNE#
RCIN#
STPCLK#
THRMTRIP#
IHDA
IHDA
IDE
IDE
SATA
SATA
DCS1#
DCS3#
DIOR#
DIOW#
DDACK#
IDEIRQ
IORDY
DDREQ
INIT#
INTR
SMI#
DD10
DD11
DD12
DD13
DD14
DD15
NMI
TP8
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DA0
DA1
DA2
E5
F5
G8
F6
C4
G9
E6
AF13
AG26
AF26
AE26
AD24
AG29
AF27
AE24
AC20
AH14
AD23
AG28
AA24
AE27
AA23
V1
U2
V3
T1
V4
T5
AB2
T6
T3
R2
T4
V6
V5
U1
V2
U6
AA4
AA1
AB3
Y6
Y5
W4
W3
Y2
Y3
Y1
W5
LDRQ0#
ICH_GPIO23LAN100_SLP
GATEA20
H_DPRSTP#_R
H_DPSLP#_R
H_PWRGD_R
RCIN#
H_THERMTRIP_R
ICH_TP8
PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15
PDA0
PDA1
PDA2
LAD0 <22,30,31>
LAD1 <22,30,31>
LAD2 <22,30,31>
LAD3 <22,30,31>
LFRAME# <22,30,31>
T53T53
T50T50
GATEA20 <31>
H_A20M# <3>
R261 0_4R261 0_4
R255 0_4R255 0_4
R480 0_4R480 0_4
T59T59
PDD[15:0] <24>
PDA[2:0] <24>
PDCS1# <24>
PDCS3# <24>
PDIOR# <24>
PDIOW# <24>
PDDACK# <24>
IRQ14 <24>
PIORDY <24>
PDDREQ <24>
+1.05V
R254
R254
*56.2/F_4
*56.2/F_4
H_PWRGD <3>
H_IGNNE# <3>
H_INIT# <3>
H_INTR <3>
RCIN# <31>
H_NMI <3>
H_SMI# <3>
H_STPCLK# <3>
R258 24/FR258 24/F
R260
R260
*56.2/F_4
*56.2/F_4
ICH_DPRSTP# <3,7,34>
H_DPSLP# <3>
+1.05V
R268
R268
56.2/F_4
56.2/F_4
R267 *0_4R267 *0_4
Placement close SB L<2"
+1.05V
R475
R475
56.2/F_4
56.2/F_4
PM_THRMTRIP# <3,7>
H_FERR# <3>
ACZ_SYNC
ACZ_BCLK
A A
ACZ_RST#
R487 33_4R487 33_4
R502 33_4R502 33_4
R489 33R489 33
R503 33R503 33
R309 33_4R309 33_4
R289 33_4R289 33_4
5
ACZ_SYNC_AUDIO <26>
ACZ_SYNC_MDC <26>
BIT_CLK_AUDIO <26>
BIT_CLK_MDC <26>
ACZ_RST#_AUDIO <26,27>
ACZ_RST#_MDC <26>
0810 UR FAE:
RCIN# DOESN'T NEED PU
RCIN#
R498 *10K_4R498 *10K_4
GATEA20
R290 8.2K_4R290 8.2K_4
4
3
+3V
2
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
ICH8M HOST(1/4)
ICH8M HOST(1/4)
ICH8M HOST(1/4)
Date: Sheet
Date: Sheet
Date: Sheet
PROJECT : ZD1
PROJECT : ZD1
Quanta Computer Inc.
Quanta Computer Inc.
12 38Monday, May 07, 2007
12 38Monday, May 07, 2007
12 38Monday, May 07, 2007
1
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E
E
E
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