Quanta Z8VR Schematic

5

www.vinafix.com

4

3

2

1

01

D D

Cardreader

C C

CONN. 2in 1

P28

I/O board

B B

Z8VR Serials SKL ULT SYSTEM BLOCK DIAGRAM

DDR4-SODIMM CHA

DDR4-SODIMM CHB

SATA - HDD

SATA ODD

RTS5170
(cardreader)

POA

CCD(Camera)

Touch Screen

Blue Tooth

I/O Board Conn.USB2 IO*1

Dual Channel DDR IV
1066/1333/1600 MHZ

P12

P13

P25

P25

USB2-3

P28

USB2-3

P25

USB2-7

P21

P21

P26

P28

USB2-6

USB2-5

USB2-4

Azalia

P6

SATA0

SATA1

BATTERY

SKY LAKE ULT 15W

MCP 1356pins

IMC

DC+GT3e

42 mm X 24 mm

SATA

Integrated PCH

USB2.0

DMIC_CLK0
DMIC_DATA0

RTC

IHDA

P2~P10

LPC

PCI-E x4
TX/RX

CLK

eDP

USB3.0/2.0

CLK

PCI-E x1

CLK

I2C_0

SPI

DP

PCIE1-4

EDP

DDI2

DDI1

USB3-1 & USB3-2

USB2-1 & USB2-2

X'TAL

32.768KHz

X'TAL 24MHz

SPI ROM
8M

N16S-GT

P7

GPU

P14~P18

RTD2166-CG

P20

PTN3366BS

P22

X'TAL 27MHz

PCIE-6

PCIE-5

VRAM

GDDR5

eDP Conn.

VGA Conn.

HDMI Conn.

P21

P21

P22

USB3 Port MB side
CN13 -> USB3 port 2 ( up )
CN16 -> USB3 port 1 ( down )

MINI CARD
WLAN+BT

RTL8111H

10/100/1G

P19

P26

P23

X'TAL 25MHz

IV@ : iGPU
EV@ : Optimus
KBL@ : Keyboard backlight
TPM@ : TPM
NTPM@: Non TPM
GS@ : G-SENSOR
NGS@ : NonG-SENSOR
TDI@ : TOUCH PAD I2C
TSU@ : TOUCH SCREEN USB
TSI@ : TOUCH SCREEN I2C
GT3@ : GT3 CPU
NAC@ : Non IOAC
IOAC@ : For IOAC
FPD@ :PBA

P28

RJ45

P23

BOM

K/B
BL
Con.

EC

IT8987

P27

Touch PAD

TPM(option)

P29

HALL
SENSOR

P27

3

P17

Fan Driver

(Fan signal)

P27

P25

2

BQ24780RUYR

Batery Charger

RT6575AGQ

+3V/+5V

RT8237CZQW

+1V_S5

NB681GD-Z

+VCCOPC/+VCCEOPIO

G5316RZ1D

+1.2VSUS

P30

MDV1528Q

+5V_S5/+3V_S5/+3V/+5V

P31

ISL95859HRTZ-T

+VCORE/VCCSA/VCCGT

P32

P33

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet of

Date: Sheet of

Thermal Protection

P34

Discharger

UP1658RQKF

+VGPU_CORE

P31

RT8068AZQW

P35

+1.05V_GFX/+3V_GFX
+1.5V_GFX

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

P7

Block Diagram

Block Diagram

Block Diagram

1

Z8VR

Z8VR

Z8VR

D-MIC

Int. D-MIC

P24

Universal HP

A A

5

ALC255

AUDIO CODEC

P24 P24

Speaker*2

P24

LED

4

K/B Con.

P27

P27

P38

P39

P40

1A

1A

1A

of

1 46Thursday, June 22, 2017

1 46Thursday, June 22, 2017

1 46Thursday, June 22, 2017

5

4

3

2

1

Skylake ULT (DISPLAY,eDP)

AT16
AU16

D63
A54
C65
C63
A65

C55
D55
B54
C56

A6

A7
BA5
AY5

H66
H65

SKL_ULT

DDI

DISPLAY SIDEBANDS

+3V_S5
+3V_S5

+3V_S5
+3V_S5

+3V_S5
+3V_S5

U34D

CATERR#
PECI
PROCHOT#
THERMTRIP#
SKTOCC#

CPU MISC

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]

GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3

PROC_POPIRCOMP
PCH_OPIRCOMP
OPCE_RCOMP
OPC_RCOMP

SKL_ULT/BGA

SKL_ULT

1 OF 20

+3V_S5
+3V_S5
+3V_S5
+3V_S5

EDP

+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5

4 OF 20

EDP_TXN[0]

EDP_TXP[0]

EDP_TXN[1]

EDP_TXP[1]

EDP_TXN[2]

EDP_TXP[2]

EDP_TXN[3]

EDP_TXP[3]

EDP_AUXN
EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
DDI3_AUXN
DDI3_AUXP

GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

JTAG

PROC_TCK

PROC_TDI
PROC_TDO
PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS

PCH_TRST#

JTAGX

EDP_TXN0

C47

EDP_TXP0

C46

EDP_TXN1

D46

EDP_TXP1

C45

EDP_TXN2

A45

EDP_TXP2

B45

EDP_TXN3

A47

EDP_TXP3

B47

EDP_AUXN

E45

EDP_AUXP

F45

B52

G50
F50

CRT_AUX#_C

E48

CRT_AUX_C

F48
G46
F46

INT_HDMI_HPD

L9

CRT_HPD

L7

SIO_EXT_SMI#

L6

SIO_EXT_SCI#

N9

EDP_HPD

L10

PCH_BLON

R12

PCH_BRIGHT

R11

EDP_VDD_EN

U13

XDP_TCK0

B61

XDP_TDI_CPU

D60

XDP_TDO_CPU

A61

XDP_TMS_CPU

C60

XDP_TRST#

B59

XDP_TCK1

B56

XDP_TDI_CPU

D59

XDP_TDO_CPU

A56

XDP_TMS_CPU

C59

XDP_TRST#

C61

XDP_TCK0

A59

If use Intel DCI USB 3.0 fixture need to short

1. XDP_TDO <--> XDP_TDO_CPU

2. XDP_TDI <--> XDP_TDI_CPU

3. XDP_TMS <--> XDP_TMS_CPU

R432 *0_4
R444 *0_4

R703 0_4
R704 0_4

EDP_TXN0 [20]
EDP_TXP0 [20]
EDP_TXN1 [20]
EDP_TXP1 [20]
EDP_TXN2 [20]
EDP_TXP2 [20]
EDP_TXN3 [20]
EDP_TXP3 [20]

EDP_AUXN [20]
EDP_AUXP [20]

PCH_BRIGHTDP_UTIL

PCH_BLON [20]
PCH_BRIGHT [20]

EDP_VDD_EN [20]

CRT_AUXN [19]
CRT_AUXP [19]

INT_HDMI_HPD [21]
CRT_HPD [19]

TP14

SIO_EXT_SCI# [28]
EDP_HPD [20]

eDP Panel

Reserve 2 Lane for 4K x 2K

PCH JTAG

JTAG_TCK,JTAG_TMS
Trace Length < 9000mils

TCK,TMS
Trace Length < 9000mils

H_PWRGOOD (50ohm)
Trace Length: 1~11.25 inches

Don't stuff if we use DP to VGA IC

CRT_AUXN

CRT_AUXP

CRT_DATA
CRT_CLK

12/25 Change R134

SIO_EXT_SMI#
SIO_EXT_SCI#

CRT_HPD
EDP_HPD

R424 *100K_4

R423 *100K_4

R135 2.2K_4
R134 *2.2K_4

、

R135 pull-up to +3V_S5

R115 10K_4
R123 10K_4

R82 100K_4
R84 100K_4

100k pull-down on PCH side

XDP_TDO_CPU
XDP_TMS_CPU
XDP_TDI_CPU

XDP_TCK0
XDP_TCK1
XDP_TRST#

,XDP_TCK1,XDP_TMS
don't need pull up or pull down

R448 51_4
R408 *51_4
R409 *51_4

R447 51_4
R425 *51_4
R446 *51_4

TP53

DGPU_PW_CTRL#

R590 49.9/F_4
R595 49.9/F_4
R100 49.9/F_4
R96 49.9/F_4

U34A

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22/DDPD_CTRLCLK

N12

GPP_E23/DDPD_CTRLDATA

E52

EDP_RCOMP

SKL_ULT/BGA

CATERR#
H_PECI
H_PROCHOT#_RH_PROCHOT#
CPU_THRMTRIP#

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3

D D

HDMICRT

+VCCIO

C C

+1V_VCCST

CPU_THRMTRIP#

R4001K_4

R40749.9/F_4

Stuff only for Debug
Ramp will not stuff

+VCCIO

R441 1K_4

B B

CATERR#

H_PROCHOT#

H_PROCHOT#[28,29,34]

Avoid 125Mhz

BPM#[0:7]
Trace Length 1~6 inches
Length match < 300 mils

H_PECI (50ohm)
Route on microstrip only
Spacing >18 mils
Trace Length: 0.4~6.125 iches

INT_HDMITX2N[21]
INT_HDMITX2P[21]
INT_HDMITX1N[21]
INT_HDMITX1P[21]
INT_HDMITX0N[21]
INT_HDMITX0P[21]

INT_HDMICLK-[21]
INT_HDMICLK+[21]

CRT_TXN0[19]
CRT_TXP0[19]
CRT_TXN1[19]

ITE FAE suggest CAP
should be at PCH side.

HDMI_DDCCLK_SW[21]

HDMI_DDCDATA_SW[21]

SM_RCOMP[0:2]
Trace length < 500 mils
Trace width = 12~15 mils
Trace spacing = 20 mils

CRT_TXP1[19]

TP8071

PCH_ODD_EN[24]

eDP_RCOMP
Trace length < 100 mils
Trace width = 20 mils
Trace spacing = 25 mils

H_PECI[28]

THRMTRIP#

DGPU_PW_CTRL#[4]

HDMI_DDCCLK_SW
HDMI_DDCDATA_SW

CRT_CLK
CRT_DATA

EDP_RCOMP

R8724.9/F_4

R442 499/F_4
R395 100/F_4

TP54
TP52
TP59
TP56

02

+3V

+3V_S5

+3V

MP remove(Intel)

+1V_VCCST

XDP_TCK0 R558 Stuff

+1V_VCCST

+1V_VCCST

2

R414

*1K_4

1 3

Q33 MMBT3904-7-F

3

Q34

FDV301N_G

1

R454
1K_4

2

SYS_SHDN# [28,30,37]

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Thursday, June 22, 2017

Date: Sheet of

Thursday, June 22, 2017

Date: Sheet of

3

2

Thursday, June 22, 2017

PROJECT :

Skylake 1/4 (DDI/eDP)

Skylake 1/4 (DDI/eDP)

Skylake 1/4 (DDI/eDP)

Z8VR

Z8VR

Z8VR

2 46

2 46

2 46

1

1A

1A

1A

CPU thermal trip

+1V_VCCST

C537

+3V

12

R402
10K_4

IMVP_PWRGD_3V [8]

U27

5

NC1VCC

A A

IMVP_PWRGD[34]

2

A

*0.1u/16V_4

4

GND3Y

*74AUP1G07GW

R401 *0_4

5

IMVP_PWRGD_3V

THRMTRIP#

4

5

4

3

2

1

Change Data and DQS to interleave.

03

SKL ULT (DDR4)SKL ULT (DDR4)

U34C

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

SKL_ULT/BGA

M_A_ALERT#
M_B_ALERT#

REV:E connect to GND

R8746

*10_5%_4

R312 *0_4
R291 *0_4

12

DDR3_DRAMRST# [11,12]

C8795

*0.1u/16V_4

Reserved for ESD
Power sequence issue no stuff

2

SKL_ULT

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[5]/DDR1_DQSP[3]

DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]

DDR1_ALERT#

DRAM_RESET#
DDR_RCOMP[0]
DDR_RCOMP[1]

DDR CH - B

3 OF 20

DDR_RCOMP[2]

DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]

DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]

DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]
DDR1_ODT[1]

DDR1_MA[3]
DDR1_MA[4]

DDR1_PAR

AN45
AN46
AP45
AP46

AN56
AP55
AN55
AP53

BB42
AY42
BA42
AW42

AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52

BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47

AH66
AH65
AG69
AG70
AR66
AR65
AR61
AR60
AT38
AR38
AT32
AR32
AR25
AR27
AR22
AR21

AN43
AP43
AT13
AR18
AT18
AU18

M_B_A5
M_B_A9
M_B_A6
M_B_A8
M_B_A7

M_B_A12
M_B_A11
M_B_ACT#

M_B_A13

M_B_A2

M_B_A10
M_B_A1
M_B_A0
M_B_A3
M_B_A4

M_B_DQS#0

M_B_DQS0

M_B_DQS#1

M_B_DQS1

M_B_DQS#2

M_B_DQS2

M_B_DQS#3

M_B_DQS3

M_B_DQS#4

M_B_DQS4

M_B_DQS#5

M_B_DQS5

M_B_DQS#6

M_B_DQS6

M_B_DQS#7

M_B_DQS7

M_B_ALERT#
M_B_PARITY

CPU_DRAMRST#

SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2

M_B_A[13:0]

M_B_DQS#[7:0]

M_B_DQS[7:0]

M_B_CLK0# [12]
M_B_CLK1# [12]

M_B_CLK0 [12]
M_B_CLK1 [12]

M_B_CKE0 [12]
M_B_CKE1 [12]

M_B_CS#0 [12]
M_B_CS#1 [12]
M_B_ODT0_DIMM [12]
M_B_ODT1_DIMM [12]

M_B_BG#0 [12]

M_B_ACT# [12]
M_B_BG#1 [12]

M_B_CAS# [12]
M_B_WE# [12]
M_B_RAS# [12]
M_B_BA#0 [12]

M_B_BA#1 [12]

M_B_ALERT# [12]

M_B_PARITY [12]

M_B_A[13:0] [12]

M_B_DQS#[7:0] [12]

M_B_DQS[7:0] [12]

DRAM COMP

SM_RCOMP_0

SM_RCOMP_1

SM_RCOMP_2

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size D ocument Number Rev

Size D ocument Number Rev

Size D ocument Number Rev

Date: Sheet of

Thursday, June 22, 2017

Date: Sheet of

Thursday, June 22, 2017

Date: Sheet of

Thursday, June 22, 2017

PROJECT :

Skylake 2/3 (DDR3 I/F)

Skylake 2/3 (DDR3 I/F)

Skylake 2/3 (DDR3 I/F)

R598120/F_4

R58980.6/F_4

R596100/F_4

Z8VR

Z8VR

Z8VR

3 46

3 46

1

3 46

1A

1A

1A

M_A_A[13:0]

M_A_DQS#[7:0]

M_A_DQS[7:0]

SKL_ULT

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]

DDR CH - A

2 OF 20

M_A_A[13:0] [11]

M_A_DQS#[7:0] [11]

M_A_DQS[7:0] [11]

DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]

DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]

DDR0_CS#[0]

DDR0_CS#[1]
DDR0_ODT[0]
DDR0_ODT[1]

DDR0_MA[3]
DDR0_MA[4]

DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSP[1]

DDR0_ALERT#

DDR0_PAR

DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ

DDR_VTT_CNTL

AU53
AT53
AU55
AT55

BA56
BB56
AW56
AY56

AU45
AU43
AT45
AT43

M_A_A5

BA51

M_A_A9

BB54

M_A_A6

BA52

M_A_A8

AY52

M_A_A7

AW52
AY55

M_A_A12

AW54

M_A_A11

BA54

M_A_ACT#

BA55
AY54

M_A_A13

AU46
AU48
AT46
AU50
AU52

M_A_A2

AY51
AT48

M_A_A10

AT50

M_A_A1

BB50

M_A_A0

AY50

M_A_A3

BA50

M_A_A4

BB52

M_A_DQS#0

AM70

M_A_DQS0

AM69

M_A_DQS#1

AT69

M_A_DQS1

AT70

M_A_DQS#2

BA64

M_A_DQS2

AY64

M_A_DQS#3

AY60

M_A_DQS3

BA60

M_A_DQS#4

BA38

M_A_DQS4

AY38

M_A_DQS#5

AY34

M_A_DQS5

BA34

M_A_DQS#6

BA30

M_A_DQS6

AY30

M_A_DQS#7

AY26

M_A_DQS7

BA26

AW50
AT52

AY67

+VREFDQ_SA_M3

AY68
BA67

AW67

R545 *10K_4

M_A_CLK0# [11]

M_A_CLK0 [11]

M_A_CLK1# [11]

M_A_CLK1 [11]

M_A_CKE0 [11]
M_A_CKE1 [11]

M_A_CS#0 [11]
M_A_CS#1 [11]
M_A_ODT0_DIMM [11]
M_A_ODT1_DIMM [11]

M_A_BG#0 [11]

M_A_ACT# [11]
M_A_BG#1 [11]

M_A_CAS# [11]
M_A_WE# [11]
M_A_RAS# [11]
M_A_BA#0 [11]

M_A_BA#1 [11]

M_A_ALERT#
M_A_PARITY

DDR_VTT_CTRL

M_A_ALERT# [11]

M_A_PARITY [11]

+VREF_CA_CPU

TP77

+VREFDQ_SB_M3

+1.2VSUS +3V_S5

2

1 3

Q36
*DTC144EU

12

C755

0.1u/16V_4

Stuff Q54 for both UMA and GPU in DDR_VTT_CN TL

R544
*100K_4

DDR_VTTT_PG_CTRL [33]

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8

M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

D D

M_A_DQ[63:0][11] M_B_DQ[63:0][12]

C C

B B

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8

M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

U34B

AL71

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

SKL_ULT/BGA

DRAMRST

+1.2VSUS

A A

CPU DRAM

CPU_DRAMRST#

5

4

12

R577
470_4

R593 0_4

3

5

4

3

2

1

SKL ULT (SIDEBAND ) GPIO

H_PECI (50ohm)
If route on microstrip,
Spacing need >18 mils
Trace Length: 2~15 iches

H_PWRGOOD (50ohm)

D D

+3V_S5

I2C0_SDA

R1372.2K_4

I2C0_SCL

R1252.2K_4

I2C1_SDA

R119*2.2K_4

I2C1_SCL

R126*2.2K_4

Trace Length: 1~11.25 inches

Touch PAD

Touch Screen

PU 2.2K for touch pad I2C bus(400 KHz)

+3V

+3V

C C

DGPU_PW_CTRL#

DGPU_PW_CTRL#[2]

R208 EV@100K_4

UMA Only

SG/Optimise

GPU Control PU/PD

DGPU_PWR_EN

R575*EV@10K_4

R192GC6@10K_4

20131015 For GC6 NV DG GC6_FB_EN PD.1A-1

R197 EV@10K_4

UMA Only

high

GPU power is control by PCH
GPIO (Discrete, SG or Optimize)

low

DGPU_PW_CTRL#

DGPU_PWROK

DGPU_PWROK PD on GPU side

DGPU_PW_CTRL#

1

0

GC6_FB_EN

DGPU_HOLD_RST#

VGA H/W
Signal

UMA

GPU

R587*EV@100K_4

R209 IV@1K_4

R104 *EV@10K_4

Setup
Menu

Hidden

UMA boot

Hidden

GPU boot

R188*GC6@10K_4

+3V

SPKR

PCH_AZ_CODEC_SYNC[23]

PCH_AZ_CODEC_BITCLK[23]

PCH_AZ_CODEC_SDOUT[23]

PCH_AZ_CODEC_SDIN0[23]

PCH_AZ_CODEC_RST#[23]

545659-103

UART2 for RMT

Touch PAD

Touch Screen

HDA

R549 *20K/F_4

Add GPU Power Control Siganls

TP4398

DGPU_HOLD_RST#[14]

DGPU_PWR_EN[40]

DGPU_PWROK[14,16]
GC6_FB_EN[15,17]

DGPU_EVENT#[17]

ACCEL_INTA[26]

ODD_PRSNT#[24]

TPD_INT#[26,28]

TP_INT_PCH[20]

I2C0_SDA[26]
I2C0_SCL[26]

I2C1_SDA[20]
I2C1_SCL[20]

C644 *10p/50V_4

R583 33_4
R553 33_4
R569 33_4

R560 33_4

C636
*10p/50V_4

TP70
TP57

Strapping

SPKR[23]

TPD_INT#

UART2_RXD
UART2_TXD
UART2_RTS#
UART2_CTS#

I2C0_SDA
I2C0_SCL

I2C1_SDA
I2C1_SCL

HDA_SYNC_R
HDA_BCLK_R
HDA_SDO_R

HDA_RST#_R

C8796
*10p/50V_4

DMIC_CLK0_R
DMIC_DATA0_R

SPKR

GSPI0_MOSI

GSPI1_MOSI

Skylake-U Strapping Table

Pin Name Strap description

GPP_B14 (SPKR)

B B

GPP_B18
(GSPI0_MOSI)

GPP_C2
(SMBALERT#)

GPP_B22
(GSPI1_MOSI)

GPP_C5
(SML0ALERT#)

SPI0_MOSI

SPI0_MISO

GPP_B23
(SML1ALERT#
/PCHHOT#)

SPI0_IO2

A A

SPI0_IO3

HDA_SDO /
I2S_TXD0

GPP_E19
(DDPB_CTRLDATA)

GPP_E21
(DDPC_CTRLDATA)

Top-Block Swap override PCH_PWROK

No reboot PCH_PWROK

TLS Confidentiality

Boot BIOS Strap Bit (BBS)

eSPI or LPC

Reserved

Reserved

Reserved

Reserved

Reserved

Flash Descriptor Security
Override / Intel ME Debug Mode

Display Port B Detected

Display Port C Detected

5

Sampled

RSMRST#

PCH_PWROK

RSMRST#

RSMRST#

RSMRST#

RSMRST#

RSMRST#

RSMRST#

PCH_PWROK

PCH_PWROK

PCH_PWROK

Configuration note

0 = *Disable Top Swap (iPD 20K)

1 = Enable Top Swap Mode

0 = *Disable No Reboot (iPD 20K)

1 = Enable No Reboot Mode

0 = *Disable Intel ME Cryp to TLS(iPD 20K)

1 = Enable Intel ME Cryp to TLS

0 = *SPI (iPD 20K)

1 = LPC

0 = *LPC is selected for EC (iPD 20K)

1 = eSPI selected for EC

+3V

+3V

+3V_S5

+3V

+3V_S5

(iPU 15 ~ 40K)

(iPU 15 ~ 40K)

(iPD 20K)

(iPU 15 ~ 40K)

(iPU 15 ~ 40K)

0 = *Enable security in the Flash
Description (iPD 20K)

1 = Disable Flash Descriptor Security (Override)

0 = *Port B is not detected (iPD 20K)

1 =Port B is detected

0 = *Port C is not detected (iPD 20K)

1 =Port C is detected

4

change location to near CPU to prevent impact HDA_SDO signal

HDA_SDO_R

AN8

GPP_B15/GSPI0_CS#

AP7

GPP_B16/GSPI0_CLK

AP8

GPP_B17/GSPI0_MISO

AR7

GPP_B18/GSPI0_MOSI

AM5

GPP_B19/GSPI1_CS#

AN7

GPP_B20/GSPI1_CLK

AP5

GPP_B21/GSPI1_MISO

AN5

GPP_B22/GSPI1_MOSI

AB1

GPP_C8/UART0_RXD

AB2

GPP_C9/UART0_TXD

W4

GPP_C10/UART0_RTS#

AB3

GPP_C11/UART0_CTS#

AD1

GPP_C20/UART2_RXD

AD2

GPP_C21/UART2_TXD

AD3

GPP_C22/UART2_RTS#

AD4

GPP_C23/UART2_CTS#

U7

GPP_C16/I2C0_SDA

U6

GPP_C17/I2C0_SCL

U8

GPP_C18/I2C1_SDA

U9

GPP_C19/I2C1_SCL

AH9

GPP_F4/I2C2_SDA

AH10

GPP_F5/I2C2_SCL

AH11

GPP_F6/I2C3_SDA

AH12

GPP_F7/I2C3_SCL

AF11

GPP_F8/I2C4_SDA

AF12

GPP_F9/I2C4_SCL

BA22

HDA_SYNC/I2S0_SFRM

AY22

HDA_BLK/I2S0_SCLK

BB22

HDA_SDO/I2S0_TXD

BA21

HDA_SDI0/I2S0_RXD

AY21

HDA_SDI1/I2S1_RXD

AW22

HDA_RST#/I2S1_SCLK

J5

GPP_D23/I2S_MCLK

AY20

I2S1_SFRM

AW20

I2S1_TXD

AK7

GPP_F1/I2S2_SFRM

AK6

GPP_F0/I2S2_SCLK

AK9

GPP_F2/I2S2_TXD

AK10

GPP_F3/I2S2_RXD

H5

GPP_D19/DMIC_CLK0

D7

GPP_D20/DMIC_DATA0

D8

GPP_D17/DMIC_CLK1

C8

GPP_D18/DMIC_DATA1

AW5

GPP_B14/SPKR

R550 *1K_4

R543 *1K_4

R144 *10K_4

R191 *1K_4

R481 *1K_4

R570 1K_4

U34F

LPSS ISH

SKL_ULT/BGA

U34G

AUDIO

+3V_S5

SKL_ULT/BGA

SPKR

GSPI0_MOSI

GSPI1_MOSI

3

+3V_S5
+3V_S5
+3V_S5
+3V_S5

+3V_S5
+3V_S5
+3V_S5
+3V_S5

+3V_S5
+3V_S5
+3V_S5
+3V_S5

+3V_S5
+3V_S5
+3V_S5
+3V_S5

+3V_S5
+3V_S5

+3V_S5
+3V_S5

+1.8V_S5
+1.8V_S5

+1.8V_S5
+1.8V_S5

+1.8V_S5
+1.8V_S5

+3V_S5

+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5

+3V_S5
+3V_S5

+3V_S5
+3V_S5

ME_WR# [28]

SKL_ULT

+3V_S5
+3V_S5
+3V_S5
+3V_S5

+3V_S5
+3V_S5
+3V_S5
+3V_S5

SKL_ULT

+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5

+3V_S5
+3V_S5

SMBALERT# [7]

SML0ALERT# [7]

+3V_S5
+3V_S5
+3V_S5
+3V_S5

GPP_D5/ISH_I2C0_SDA

+3V_S5

GPP_D6/ISH_I2C0_SCL

+3V_S5

GPP_D7/ISH_I2C1_SDA

+3V_S5

GPP_D8/ISH_I2C1_SCL

+3V_S5

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

+1.8V_S5

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

+1.8V_S5

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

6 OF 20

SD GPI
SD GPI
SD GPI
SD GPI
SD GPI
SD GPI
SD GPI
SD GPI

GPP_A17/SD_PWR_EN#/ISH_GP7

7 OF 20

GPP_D15/ISH_UART0_RTS#

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#

+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5

GPP_A12/BM_BUSY#/ISH_GP6

+3V_S5

SDIO/SDXC

GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3

GPP_G5/SD_CD#
GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A16/SD_1P8_SEL

SD_RCOMP

GPP_F23

+1.8V_S5

GPP_D9
GPP_D10
GPP_D11
GPP_D12

GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5

AB11
AB13
AB12
W12
W11
W10
W8
W7

BA9
BB9

AB7

AF13

P2
P3
P4
P1

M4
N3

N1
N2

AD11
AD12

U1
U2
U3
U4

AC1
AC2
AC3
AB4

AY8
BA8
BB7
BA7
AY7
AW7
AP13

R148200/F_4

2

Reserve UART FFC TP for Win 7 debug

UART2_RXD

TP68

UART2_TXD

TP69

UART2_RTS#

TP67

UART2_CTS#

TP66

Touchpad INT

TPD_INT#

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

R490 *49.9K/F_4
R489 *49.9K/F_4
R484 *49.9K/F_4
R488 *49.9K/F_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

Skylake 6/7 (PEG/DMI/FD I)

Skylake 6/7 (PEG/DMI/FD I)

Skylake 6/7 (PEG/DMI/FD I)

Thursday, June 22, 2017

Thursday, June 22, 2017

Thursday, June 22, 2017

+3V_S5

R117TDI@10K_4

1

+3V_S5

Z8VR

Z8VR

Z8VR

4 46

4 46

4 46

04

1A

1A

1A

5

Backside cap

C203
1U/6.3V_2

C247
22u/6.3V_6

C227
22u/6.3V_6

C132
22u/6.3V_6

C301
22u/6.3V_6

C273
22u/6.3V_6

C209
22u/6.3V_6

C228
22u/6.3V_6

Backside cap

C300

C235
1U/6.3V_2

C275
22u/6.3V_6

C575
10u/6.3V_4

C208
22u/6.3V_6

C312
1U/6.3V_2

D D

C107
22u/6.3V_6

C269

10u/6.3V_4

10u/6.3V_4

Backside cap

C327
22u/6.3V_6

C545
10u/6.3V_4

C223
1U/6.3V_2

10u/6.3V_4

C204
1U/6.3V_2

Backside cap

C279
10u/6.3V_4

C230
10u/6.3V_4

C267
10u/6.3V_4

C581
10u/6.3V_4

C287
1U/6.3V_2

Backside cap

C314

C214

C246

C221
1U/6.3V_2

C8794
*22u/6.3V_6

上件

上件

1U/6.3V_2

C8791
*22u/6.3V_6

+1.2VSUS

1U/6.3V_2

C8792

C8793

*22u/6.3V_6

*22u/6.3V_6

C C

B B

A A

R109 U42@0.0002_5%_8

+VCCCORE

R8740 *U42@0.0002_5%_8

R8741 U22@0_5%_8

+VCCGT

R116 *U22@0_5%_8

Backside cap

For 2+3e CPU

Backside cap

For 2+3e CPU

Backside cap

For 2+3e CPU

1.0V_CPU 3A

+VCCGT_+VCORE

For U42

+VCCGT_+VCORE

For U22

5

10u/6.3V_4

C8789
*22u/6.3V_6

Reserved 01/17

+VCCGT

C375
10u/6.3V_4

Backside cap

+1V_SUS

+VCCIO

+1V_SUS

C195
10u/6.3V_4

C8788
*22u/6.3V_6

R181 0_4

4

C248
22u/6.3V_6

10u/6.3V_4

C580
10u/6.3V_4

C243
10u/6.3V_4

C307
10u/6.3V_4

C8790
*22u/6.3V_6

Und er CPU

C140
10u/6.3V_4

C316
10u/6.3V_4

Backside cap

C262

C263

1U/6.3V_2

1U/6.3V_2

C238

C211

1U/6.3V_2

1U/6.3V_2

Backside cap

C407
C360
10u/6.3V_4

1U/6.3V_2

Prima ry s ide cap

C421

C466

10u/6.3V_4

10u/6.3V_4

+VDDQC

C322

1U/6.3V_2

R430 0_6

Primary si de cap

R81 0_6

R431 0_6

4

+VCCCORE

C284
22u/6.3V_6

C252
10u/6.3V_4

C217
10u/6.3V_4

C315
1U/6.3V_2

C256
10u/6.3V_4

C8787
*22u/6.3V_6

C250

C224

10u/6.3V_4

10u/6.3V_4

C116

C131

10u/6.3V_4

10u/6.3V_4

C261

C212

1U/6.3V_2

1U/6.3V_2

C237

C210

1U/6.3V_2

1U/6.3V_2

+VCCGT

VCCGT_SENSE[34]
VSSGT_SENSE[34]

100 ohm Near CPU

C329

1U/6.3V_2

C450

C435

10u/6.3V_4

10u/6.3V_4

+1V_VCCST

C308
10u/6.3V_4

Backside cap

Prima ry s ide cap

TP13

TP27

Remove (2017/01/17)

+VCCGT_+VCORE

+VCCGT

C80

C92

10u/6.3V_4

10u/6.3V_4

C241

C215

10u/6.3V_4

10u/6.3V_4

+VCCGT_+VCORE

+VCCGT

+VCCGT

+VCCGT_+VCORE

R8739 U22@0_4

C213

C260

1U/6.3V_2

1U/6.3V_2

C265

C239

1U/6.3V_2

1U/6.3V_2

R83 100/F_4

R78
100/F_4

C410

C355

1U/6.3V_2

1U/6.3V_2

C576

+VCCSTG

1U/6.3V_4

C136

1U/6.3V_4

+VCCPLL

+1.2VSUS

C577

1U/6.3V_4

A30
A34
A39

A44
AK33
AK35
AK37
AK38
AK40
AL33
AL37
AL40

AM32
AM33
AM35
AM37
AM38

G30

K32

AK32

AB62

P62

V62

H63

G61

AC63

AE63

AE62

AG62

AL63
AJ62

A48
A53
A58
A62

A66
AA63
AA64
AA66
AA67
AA69
AA70
AA71

AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71

J43

J45

J46

J48

J50

J52

J53

J55

J56

J58

J60

K48

K50

K52

K53

K55

K56

K58

K60

L62

L63

L64

L65

L66

L67

L68

L69

L70

L71

M62
N63
N64
N66
N67
N69

J70

J69

AU23
AU28
AU35
AU42

BB23
BB32
BB41
BB47
BB51

AM40

A18

A22

AL23

K20
K21

SKL_ULT

U34L

CPU POWER 1 OF 4

VCC_A30

S0

VCC_A34
VCC_A39
VCC_A44
VCC_AK33
VCC_AK35
VCC_AK37
VCC_AK38
VCC_AK40
VCC_AL33
VCC_AL37
VCC_AL40
VCC_AM32
VCC_AM33
VCC_AM35
VCC_AM37
VCC_AM38
VCC_G30

RSVD_K32

RSVD_AK32

VCCOPC_AB62
VCCOPC_P62
VCCOPC_V62

VCC_OPC_1P8_H63

VCC_OPC_1P8_G61

VCCOPC_SENSE
VSSOPC_SENSE

VCCEOPIO

S0

VCCEOPIO

VCCEOPIO_SENSE
VSSEOPIO_SENSE

SKL_ULT/BGA

SKL_ULT

U34M

CPU POWER 2 OF 4

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

S0

VCCGT

0.55~1.5V

VCCGT
VCCGT
VCCGT
VCCGT

2+3e peak 6A

VCCGT

2+3e TPY 4A

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

VCCGT_SENSE
VSSGT_SENSE

SKL_ULT/BGA

SKL_ULT

U34N

CPU POWER 3 OF 4

S3

DDR4

VDDQ_AU23
VDDQ_AU28

1.2V

VDDQ_AU35
VDDQ_AU42
VDDQ_BB23
VDDQ_BB32
VDDQ_BB41
VDDQ_BB47
VDDQ_BB51

VDDQC

VCCST

S3

1.0V120mA

VCCSTG_A22

S0

VCCPLL_OC

S0

1.0V

VCCPLL_K20
VCCPLL_K21

S3

120mA

1.0V

SKL_ULT/BGA

3

VCC

0.55V~1 .5V

2+2 peak 24A
2+2 TPY 17A

2+3e peak 24A
2+3e TPY 17A

1.0V

S0

Sx

1.8V

GT3 CPU

3A

1.0V

12 OF 20

VCCGT

S0

0.55~1.5V

2+2 peak 31A
2+2 TPY 15A

2+3e peak 56A
2+3e TPY 17A

VCCGTX

2+2 X

VCCGTX_SENSE
VSSGTX_SENSE

13 OF 20

S0

0.85V/0.95V

3.0A

2A

S0

1.15V

2+2 peak 5A
2+2 TPY 4A
2+3e peak 5.1A
2+3e TPY 5A

1.0V

40mA

260mA

VCCIO_SENSE

VSSIO_SENSE

VSSSA_SENSE
VCCSA_SENSE

14 OF 20

3

3A

50mA

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

VCCGTX_AK42
VCCGTX_AK43
VCCGTX_AK45
VCCGTX_AK46
VCCGTX_AK48
VCCGTX_AK50
VCCGTX_AK52
VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60
VCCGTX_AK70
VCCGTX_AL43
VCCGTX_AL46
VCCGTX_AL50
VCCGTX_AL53
VCCGTX_AL56
VCCGTX_AL60
VCCGTX_AM48
VCCGTX_AM50
VCCGTX_AM52
VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58
VCCGTX_AU58
VCCGTX_AU63
VCCGTX_BB57
VCCGTX_BB66

VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO

VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA

VCC_G32
VCC_G33
VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42

VCC_J30
VCC_J33
VCC_J37

VCC_J40
VCC_K33
VCC_K35
VCC_K37
VCC_K38
VCC_K40
VCC_K42
VCC_K43

VCC_SENSE
VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG_G20

N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62

AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66

AK62
AL61

AK28

AK30

AL30

AL42

AM28

AM30

AM42

AK23

AK25

G23

G25

G27

G28

J22

J23

J27

K23

K25

K27

K28

K30

AM23

AM22

H21

H20

+VCCCORE

G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43

E32
E33

B63
A63
D64

G20

+VCCGT

TP28
TP26

R90 100/F_4

VSASS_SENSE [34]
VSA_SENSE [34]

R89 100/F_4

100 ohm near CPU

R29 100/F_4

R32 100/F_4

C119

1U/6.3V_4

Close CPU

C61
47u/6.3V_8

C599
22u/6.3V_6

C598
22u/6.3V_6

C294
U42@22u/6.3V_6

C293
U42@22u/6.3V_6

C291
U42@22u/6.3V_6

+VCCSA

Prima ry s ide cap

C66

C531

47u/6.3V_8

47u/6.3V_8

Prima ry s ide cap

C106
10u/6.3V_4

+VCCSTG

C83
10u/6.3V_4

+VCCCORE

C122
10u/6.3V_4

100 ohm Near CPU

H_CPU_SVIDART#
H_CPU_SVIDCLK
H_CPU_SVIDDAT

Prima ry s ide cap

C244

C59

47u/6.3V_8

47u/6.3V_8

Prima ry s ide cap

C620

C134

22u/6.3V_6

22u/6.3V_6

Prima ry s ide cap

C619

C600

22u/6.3V_6

22u/6.3V_6

+VCCGTX_+VCORE

C292
U42@22u/6.3V_6

+VCCGTX_+VCORE

+VCCGTX_+VCORE +VCCGTX_+VCORE

C317
U42@22u/6.3V_6

+VCCIO

Backside cap

C305
10u/6.3V_4

C304
10u/6.3V_4

Prima ry s ide cap

C608

C627

1U/6.3V_4

Backside cap

C280
10u/6.3V_4

Backside cap

C194

1U/6.3V_2

1U/6.3V_4

C249
10u/6.3V_4

C303

1U/6.3V_2

+VCCSA

Prima ry s ide cap

C245

C133

10u/6.3V_4

10u/6.3V_4

2

C74

C538

47u/6.3V_8

47u/6.3V_8

C573
10u/6.3V_4

VCORE_SENSE [34]
VCORESS_SENSE [34]

C302

C219

47u/6.3V_8

47u/6.3V_8

C621

C114

22u/6.3V_6

22u/6.3V_6

C597
22u/6.3V_6

C296

1U/6.3V_2

C605

1U/6.3V_4

C266
10u/6.3V_4

C207

1U/6.3V_2

C231
10u/6.3V_4

2

C534

C56

47u/6.3V_8

47u/6.3V_8

C574

C100

10u/6.3V_4

10u/6.3V_4C558

SVID

H_CPU_SVIDDAT

Place PU resistor
close to CPU

Place PU resistor
close to CPU

H_CPU_SVIDART#

H_CPU_SVIDCLK

C60
47u/6.3V_8

C617

C277

22u/6.3V_6

22u/6.3V_6

Remove (2017/01/17)

Prima ry s ide cap
Backside cap

1.U22--->R8744/R8745

2.U42--->R8744/R8745

Imax 3(A)

C297

C320

1U/6.3V_2

1U/6.3V_2

C628

1U/6.3V_4

C222

C236

10u/6.3V_4

10u/6.3V_4

C285

C259

1U/6.3V_2

1U/6.3V_2

C87

C115

10u/6.3V_4

10u/6.3V_4

C138

C570

10u/6.3V_4

10u/6.3V_4C552

+1V_VCCST

Must close to CPU

C535

R418

1000P/50V_4

100/F_4

+1V_VCCST

R393

54.9/F_4

R419 220/F_4

C96
22u/6.3V_6

R8744 U42@0.0002_5%_8

R8745 *U42@0.0002_5%_8

C321

1U/6.3V_2

C311

C288

10u/6.3V_4

10u/6.3V_4

C276

C295

1U/6.3V_2

1U/6.3V_2

C102
10u/6.3V_4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

+VCCCORE

不上件

上件

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

Skylake 12/13/14 (POWER)

Skylake 12/13/14 (POWER)

Skylake 12/13/14 (POWER)

Thursday, June 22, 2017

Thursday, June 22, 2017

Thursday, June 22, 2017

1

H_CPU_SVIDDAT [34]

VR_SVID_ALERT#_VCORE [34]

H_CPU_SVIDCLK [34]

1

Z8VR

Z8VR

Z8VR

05

5 46

5 46

5 46

1A

1A

1A

5

4

3

2

1

Skylake ULT (GPU, SATA , ODD, CLK ,USB2&3)

U34H

PCIE/USB3/SATA

PEG_RX#0[14]

PEG_RX0[14]

SSD

PEG_TX#0[14]

PEG_TX0[14]

PEG_RX#1[14]

PEG_RX1[14]

PEG_TX#1[14]

PEG_TX1[14]

PEG_RX#2[14]

PEG_RX2[14]

PEG_TX#2[14]

PEG_TX2[14]

PEG_RX#3[14]

PEG_RX3[14]

PEG_TX#3[14]

PEG_TX3[14]

SATA_RXN0[24]
SATA_RXP0[24]

SATA_TXN0[24]
SATA_TXP0[24]

SATA_RXN1[24]
SATA_RXP1[24]

SATA_TXN1[24]
SATA_TXP1[24]

PCIE_RX5-_LAN[22]

PCIE_RX5+_LAN[22]
PCIE_TX5-_LAN[22]

PCIE_TX5+_LAN[22]

PCIE_RX6-_WLAN[25]

PCIE_RX6+_WLAN[25]
PCIE_TX6-_WLAN[25]
PCIE_TX6+_WLAN[ 25]

SATA_RXN1/PEG_RXN10_L2[25]

SATA_RXP1/PEG_RXP10_L2[25]
SATA_TXN1/PEG_TXN10_L2[25]

SATA_TXP1/PEG_TXP10_L2[25]
SATA_RXN3/PEG_RXN9_L0[25]

SATA_RXP3/PEG_RXP9_L0[25]
SATA_TXN3/PEG_TXN9_L0[25]

SATA_TXP3/PEG_TXP9_L0[25]

CLK_PCIE_VGA#[14]

CLK_PCIE_VGA[14]

CLK_PEGA_REQ#[14]

CLK_PCIE_NGFF1_N[25]
CLK_PCIE_NGFF1_P[25]

PCIE_CLKREQ_NGFF1#[25]

CLK_PCIE_LANN[22]
CLK_PCIE_LANP[22]

CLK_PCIE_LAN_REQ#[22]

CLK_PCIE_WLANN[25]
CLK_PCIE_WLANP[25]

PCIE_CLKREQ_WLAN#[25]

CLK_PCIE_REQ0#
CLK_PCIE_REQ1#
CLK_PCIE_REQ2#
CLK_PCIE_REQ3#
CLK_PCIE_REQ4#
CLK_PCIE_REQ5#

5

D D

dGPU PEG*4

HDD

ODD

C C

LAN

WIFI

B B

N16S VGALANWLAN

M.2

A A

C564 EV@0.22u/10V_4
C563 EV@0.22u/10V_4

C550 EV@0.22u/10V_4
C549 EV@0.22u/10V_4

C547 EV@0.22u/10V_4
C548 EV@0.22u/10V_4

C542 EV@0.22u/10V_4
C543 EV@0.22u/10V_4

C560 0.1u/16V_4
C561 0.1u/16V_4

C541 0.1u/16V_4
C540 0.1u/16V_4

R440 100/F_4

TP55
TP51

R258 10K_4
R205 10K_4
R223 *10K_4
R574 *10K_4
R227 10K_4
R210 10K_4

XDP_PRDY#
XDP_PREQ#
PIRQA#

SATA_RXN1/PEG_RXN10_L2
SATA_RXP1/PEG_RXP10_L2

SATA_TXN1/PEG_TXN10_L2
SATA_TXP1/PEG_TXP10_L2
SATA_RXN3/PEG_RXN9_L0

SATA_RXP3/PEG_RXP9_L0
SATA_TXN3/PEG_TXN9_L0

SATA_TXP3/PEG_TXP9_L0

CLK_PCIE_REQ0#

R259 0_4

CLK_PCIE_REQ1#

R211 0_4

CLK_PCIE_REQ2#

TP31

CLK_PCIE_REQ3#

TP78

CLK_PCIE_REQ4#

R230 0_4

CLK_PCIE_REQ5#

R213 0_4 R330

+3V

C_PEG_TX#0
C_PEG_TX0

C_PEG_TX#1
C_PEG_TX1

C_PEG_TX#2
C_PEG_TX2

C_PEG_TX#3
C_PEG_TX3

PCIE_TX5­PCIE_TX5+

PCIE_TX6­PCIE_TX6+

PCIE_RCOMPN
PCIE_RCOMPP

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

F5

PCIE_RCOMPN

E5

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

SKL_ULT/BGA

U34J

D42

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

AR10

GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3

AT10

GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

AU7

GPP_B10/SRCCLKREQ5#

SKL_ULT/BGA

+3V_S5

4

SKL_ULT

+3V_S5
+3V_S5
+3V_S5

8 OF 20

SKL_ULT

CLOCK SIGNALS

+3V_S5

+3V_S5

+3V_S5

+3V_S5

+3V_S5

+3V_S5

+3V_S5

10 OF 20

add for EC reset RTC

CLR_CMOS[ 28]

SSIC / USB3

USB3_2_RXN/SSIC_1_RXN
USB3_2_RXP/SSIC_1_RXP

USB3_2_TXN/SSIC_1_TXN
USB3_2_TXP/SSIC_1_TXP

USB3_3_RXN/SSIC_2_RXN
USB3_3_RXP/SSIC_2_RXP

USB3_3_TXN/SSIC_2_TXN
USB3_3_TXP/SSIC_2_TXP

USB2

+3V_S5
+3V_S5
+3V_S5
+3V_S5

+3V_S5
+3V_S5
+3V_S5

GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#

GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2

+3V_S5

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIASREF

RTCX1
RTCX2

SRTCRST#

RTCRST#

R594
100K_4

USB3_1_RXN
USB3_1_RXP
USB3_1_TXN
USB3_1_TXP

USB3_4_RXN
USB3_4_RXP
USB3_4_TXN
USB3_4_TXP

USB2N_1
USB2P_1

USB2N_2
USB2P_2

USB2N_3
USB2P_3

USB2N_4
USB2P_4

USB2N_5
USB2P_5

USB2N_6
USB2P_6

USB2N_7
USB2P_7

USB2N_8
USB2P_8

USB2N_9
USB2P_9

USB2N_10
USB2P_10

USB2_COMP

USB2_ID

USB2_VBUSSENSE

GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2

GPP_E8/SATALED#

CLK_PCIE_XDPN

F43

CLK_PCIE_XDPP

E43

BA17

SUSCLK

XTAL24_IN

E37

XTAL24_OUT

E35

XCLK_BIASREF

E42

RTC_X1

AM18

RTC_X2

AM20

SRTC_RST#

AN18

RTC_RST#

AM16

3

2

1

Q41
*2N7002K

SRTC_RST#

H8
G8
C13
D13

J6
H6
B13
A13

J10
H10
B15
A15

E10
F10
C15
D15

AB9
AB10

AD6
AD7

AH3
AJ3

AD9
AD10

AJ1
AJ2

AF6
AF7

AH1
AH2

AF8
AF9

AG1
AG2

AH7
AH8

AB6

USBCOMP
USB2_ID

AG3
AG4

USB_OC0#

A9

USB_OC1#

C9

USB_OC2#

D9

USB_OC3#

B9

J1

DEVSLP0

J2

DEVSLP1

J3

DEVSLP2

H2

SATAGP0

H3

SATAGP1

G4

R436 0_4

H1

R452 2.7K/F_4

3

USB3_RXN0 [27]
USB3_RXP0 [27]
USB3_TXN0 [27]
USB3_TXP0 [27]

USB3_RXN1 [27]
USB3_RXP1 [27]
USB3_TXN1 [27]
USB3_TXP1 [27]

1A-1

USBP0- [27]
USBP0+ [27]

USBP1- [27]
USBP1+ [27]

USBP2- [27]
USBP2+ [27]

USBP3- [24]
USBP3+ [24]

USBP4- [25]
USBP4+ [25]

USBP5- [20]
USBP5+ [20]

USBP6- [20]
USBP6+ [20]

USBP7- [27]
USBP7+ [27]

R138 113/F_4
R492 1K_4
R185 1K_4

TP6
TP9

SUSCLK [25]

1V power plane

0.71 checklist p14

MB USB3.0 CN16 ( Charger IC ) Down

MB USB3.0 CN13 -> Up

DB USB2.0

POA (Reserved)

BT

Touch Screen

CCD

Card reader

DEVSLP0 [24]

DEVSLP2 [25]

NGFF3_DET [25]

+1V_S5

CLR_CMOS

2

MB USB3.0 CN16 ( Charger IC ) Down

MB USB3.0 CN13 -> Up

USBCOMP
Impedance = 50 ohm
Trace length < 500 mils
Trace spacing = 15 mils

C87970.1u/ 16V_4

C87980.1u/ 16V_4

Near CPU
01/17

RTC_RST#

3

Q39
2N7002K

1

C87990.1u/ 16V_4

C88000.1u/ 16V_4

USB_OC0# [27]
USB_OC1# [27]
USB_OC2# [27]

Add SSD ID 1/14

Hight is SSD , Low is ODD

SSD_ID[24]

Skylake-U userd 24 MHz (50 Ohm ESR) XTAL

XTAL24_IN

MB U3
MB U3
DB U2

XTAL24_OUT

Note: Change Y4 to 38.4 MHz(ESR 30 ohm) for Cannonlake U

RTC Clock 32.768KHz (RTC)

Trace length < 1000 mils

RTC Circuitry (RTC)

+3VPCU

On SKL voltage at VCCRTC does not exceed 3.2V

R329

1.5K/F_4

VCCRTC_2

45.3K/F_4

2013/10/16 Chage +3V_RTC_0 to VCCTC_2.

1A-2

1. AHL03003057 DBV CR2032

2. AHL03003003 VDE CR2032

2

PCH PU/PD

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#

DEVSLP0
DEVSLP1
DEVSLP2
PIRQA#

SATAGP1

R438 10K_4

C349 6.8p/50V_4

C350 6.8p/50V_4

1B-1

R335 1K_4

12

BT1

BAT_CONN

SATAGP0

R8753 U22@0_4

01/17

R8754 U22@0_4

12

+3V_RTC_2

+3V_RTC_1

+3V_RTC_[0:2]
Trace width = 20 mils

BAT54CW_0.2A

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Thursday, June 22, 2017

Date: Sheet of

Thursday, June 22, 2017

Date: Sheet of

Thursday, June 22, 2017

+3V_S5

R411 10K_4
R405 10K_4
R404 10K_4
R422 10K_4

R469 *10K_4
R470 *10K_4
R471 *10K_4
R572 10K_4

R439 *10K_4

+3V_S5

R437 100K_4

C556 U22@10P/50V_4

R426 U22@1M_4

4

3

Y3
U22@24MHz

1

2

C544 U22@10P/50V_4

RTC_X1

R225

Y2

10M_4

32.768KHZ

RTC_X2

+3V_RTC

+3V_RTC

Trace width = 30 mils

D9

R237

20K/F_4

R233

20K/F_4

C363
1u/6.3V_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

Skylake 9/10 (PEG/USB/CL K)

Skylake 9/10 (PEG/USB/CL K)

Skylake 9/10 (PEG/USB/CL K)

06

+3V

BG624000078 -> HHE(1st)

BG624000044 -> TXC(2nd)

CH01006JB08 -> 10p
CH01506JB06 -> 15p
CH-6806TB01 -> 6.8p

BG3327680C6 -> HHE(1st)

BG332768099 -> TXC(2nd)--EOD
Change to BG332768104

RTC_RST#

12

C357

J1

1u/6.3V_4

*JUMP

SRTC_RST#

C354
1u/6.3V_4

Z8VR

Z8VR

Z8VR

6 46

6 46

1

6 46

1A

1A

1A

5

4

3

2

1

+3V_S5

+3V_S5

43

1

+3V_S5

07

R464

2.2K_4

CLK_SDATA [11,12,19,26]

CLK_SCLK [11,12,19, 26]

SMB_ME1_CLK
SMB_ME1_DAT

U34E

PCH_SPI_CLK
PCH_SPI_SO
PCH_SPI_SI
PCH_SPI_IO2

D D

PCH_SPI_IO3
PCH_SPI_CS0#

For M.2 wifi module must

EC_RCIN#

SIO_RCIN#[28]

IRQ_SERIRQ[24, 28]

C C

PCH_SPI_CLK_EC[28]

PCH_SPI_SO_EC[28]

R573 0_4

IRQ_SERIRQ

PCH_SPI_CLK_EC

PCH_SPI_SI_EC[28]

PCH_SPI_SI_EC
PCH_SPI_SO_EC

AW13

SP@ socket P/N: DFHS08FS023 only for A-TEST

SPI ROM

Skylake

3.3V

B B

Vender Size Quanta P/N Vender P/N

WND

GGD

AKE3EFP0N07

8M

AKE2EZN0Q00

8M

16M

AKE3DZN0Q02 GD25B127DSIGR

16M

W25Q64FVSSIQWND

GD25B64CSIGRGGD

W25Q128FVSIQAKE3DZN0N01

SPI - FLASH

AV2

SPI0_CLK

AW3

SPI0_MISO

AV3

SPI0_MOSI

AW2

SPI0_IO2

AU4

SPI0_IO3

AU3

SPI0_CS0#

AU2

SPI0_CS1#

AU1

SPI0_CS2#

SPI - TOUCH

M2

GPP_D1/SPI1_CLK

M3

GPP_D2/SPI1_MISO

J4

GPP_D3/SPI1_MOSI

V1

GPP_D21/SPI1_IO2

V2

GPP_D22/SPI1_IO3

M1

GPP_D0/SPI1_CS#

C LINK

G3

CL_CLK

G2

CL_DATA

G1

CL_RST#

GPP_A0/RCIN#

AY11

GPP_A6/SERIRQ

SKL_ULT/BGA

PCH SPI ROM(8M)

15ohm CS01502JB12
33ohm CS03302JB29

PCH_SPI_SO
PCH_SPI_SO_EC

1A-13

+3V_S5

+3V_S5

+3V_PCH_ME

SKL_ULT

+3V_S5

+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5

PCH_SPI_CS0#

R453 15_4
R457 15_4

3.3K is original and for no
support fast read function

LPC

R433 1K_4

SMBUS, SMLINK

+3V_S5
+3V_S5
+3V_S5

+3V_S5
+3V_S5
+3V_S5

+3V_S5
+3V_S5

GPP_B23/SML1ALERT#/PCHHOT#

+3V_S5

+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5

GPP_A14/SUS_STAT#/ESPI_RESET#

+3V_S5

+3V_S5

GPP_A9/CLKOUT_LPC0/ESPI_CLK

+3V_S5
+3V_S5

5 OF 20

+3V_LDO_EC

+3V_S5

SPI_SO_8M

SPI_WP_IO2_ME

PCH_SPI_IO2

PCH_SPI_IO3

SPI_CS0#_UR_ME[ 28]

+3V_PCH_ME

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

R462 *0_6

R475 0_6

1

CS#

2

IO1/DO

3

IO2/WP#

4

GND

W25Q128FV -- 8MB

IO3/HOLD#

PCH_SPI_CLK_EC
PCH_SPI_SI_EC

R415 15_4

R477 15_4

R445 10K_4

VCC

CLK

IO0/DI

R428 0_4

PCH_MBCLK0_R

R7

PCH_MBDAT0_R

R8
R10

SMBALERT#

VGA_MBCLK

R9

VGA_MBDATA

W2
W1

SML0ALERT#

SMB_ME1_CLK

W3

SMB_ME1_DAT

V3
AM7

SMB1ALERT#

eSPI change to 15 ohm

AY13

R559 0_4

BA13

R547 0_4

BB13

R556 0_4

AY12

R548 0_4

BA12
BA11

R226 *0_4

C348 *0.1u/16V_4

eSPI change to 15 ohm

AW9

R551 22/J_4

AY9
AW11

R557 22/J_4

R558 22/J_4

CLKRUN#

C8801

C8802

*10p/50V_4

*10p/50V_4

01/17

+3V_PCH_ME

8

SPI_HOLD_IO3_ME

7

SPI_CLK_8M

6

SPI_SI_8M

5

R463 15_4
R468 15_4

SPI_HOLD_IO3_ME

PCH_SPI_CS0#

SPI_CS0#_UR_ME

LPC_LAD0 [24,25,28]
LPC_LAD1 [24,25,28]
LPC_LAD2 [24,25,28]
LPC_LAD3 [24,25,28]

LPC_LFRAME# [24,25,28]

TP36

CLK_PCI_EC [28]

PCLK_TPM [24]

C582 0. 1u/16V_4U29

R466 1K_4

R461 15_4

R465 15_4

SPI_WP_IO2_ME

reserve for SPI fast read

only 0ohm option

Strapping

SMBALERT# [4]

SML0ALERT# [4]

SMB1ALERT# [26]

ckl v0.71 p.24

CLKRUN# [24,28]

+3V_PCH_ME

PCH_SPI_CLK

PCH_SPI_SI

C587
*22p/50V_4

CLK_PCI_LPC [25]

CLKRUN#
IRQ_SERIRQ
EC_RCIN#

R564 8.2K/F_4
R566 10K_4
R546 10K_4

SMBus

PCH_MBCLK0_R
PCH_MBDAT0_R
VGA_MBDATA
VGA_MBCLK

SMB1ALERT#

Termination Resistor Requirement for PCH PCHHOT# Pin
Reserve PU 150K resister

+3V

S5 S0

SMBus(PCH)

PCH_MBDAT0_R

PCH_MBCLK0_R

PCH_XDP_WLAN/S5 DDR_TP/S0

R4732.2K_4
R4722.2K_4
R4792.2K_4
R1452.2K_4

R187*150K_4

Change to 2.2k

Q35

5

2

6

DMN601DWK-7

R456

2.2K_4

SMBus(EC)

2ND_MBCLK[17, 28]
2ND_MBDATA[17,28]

2ND_MBCLK
2ND_MBDATA

R480 0_4
R476 0_4

EC/S5

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Thursday, June 22, 2017

Date: Sheet of

Thursday, June 22, 2017

Date: Sheet of

5

4

3

2

Thursday, June 22, 2017

PROJECT :

Skylake 5 (SATA/HDA/SPI)

Skylake 5 (SATA/HDA/SPI)

Skylake 5 (SATA/HDA/SPI)

Z8VR

Z8VR

Z8VR

7 46

7 46

1

7 46

1A

1A

1A

5

4

3

2

1

PCI_PLTRST#

SYS_RESET#

R451 10K_4

VCCST_PWRGD

01/17

Near CPU

1 2

C8805 0.1u/16V_4

TP29

PCIE_LAN_WAKE#

For 15" / 17"
(R501)

ReserveReserved

(R520)

PCH_RSMRST#

PROC_PWRGD

SYS_PWROK_R
EC_PWROK_R

DPWROK_R PCH_ACPRESENT

PCH_SUSPWRDNACK_C

SUSACK#_R

TP25

HighLow

R420 0_4

R568 *0_4

R597 *0_4

+1.8V_S5

For 14"
(R495)

(Def ault)

Z8V
(R519)

R580 0_4

+VCCIO

Reserve PU 10K

R450 *10K_4

D D

PROC_PWRGD

EC only PD, so PD 10K

R579

10K_4

RSMRST#[28]

EC_PWROK

PCH_SUSPWRDNACK[28]

PCIE_LAN_WAKE#[22,25]

Board ID

C C

B B

01/17

BOARD_ID0

BOARD_ID1

BOARD_ID2

BOARD_ID3

BOARD_ID4

R526 U22@10K_4
R524 10K_4

R506 10K_4
R504 NAC@10K_4
R521 NGS@10K_4
R498 NTPM@10K_4

R495 10K_4
R493 10K_4
R519 *10K_4

VRAM X32
(R506)

Non IOAC
(R504)

Non G-sensor
(R521)

No TPM
(R498)

No-Touch panel

RAM_ID1

R527 U42@10K_4

RAM_ID2

R525 *10K_4

RAM_ID3

R540 *10K_4

Board_ID0

R507 *10K_4

Board_ID1

R505 IOAC@10K_4

Board_ID2

R522 GS@10K_4

Board_ID3

R499 TPM@10K_4

Board_ID4

R500 TSU@10K_4

Board_ID5

R501 *10K_4

Board_ID6

R494 *10K_4

Board_ID7

R520 10K_4

Low

High

VRAM X16
(R507)

IOAC
(R505)

G-sensor
(R522)

TPM
(R499)

Touch panel
(R500)

BOARD_ID5

BOARD_ID6

BOARD_ID7 Z8VR

U34K

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

SKL_ULT/BGA

U34I

CSI-2

A36

CSI2_DN0

B36

CSI2_DP0

C38

CSI2_DN1

D38

CSI2_DP1

C36

CSI2_DN2

D36

CSI2_DP2

A38

CSI2_DN3

B38

CSI2_DP3

C31

CSI2_DN4

D31

CSI2_DP4

C33

CSI2_DN5

D33

CSI2_DP5

A31

CSI2_DN6

B31

CSI2_DP6

A33

CSI2_DN7

B33

CSI2_DP7

A29

CSI2_DN8

B29

CSI2_DP8

C28

CSI2_DN9

D28

CSI2_DP9

A27

CSI2_DN10

B27

CSI2_DP10

C27

CSI2_DN11

D27

CSI2_DP11

SKL_ULT/BGA

Power Sequence

PCH_PWROK[28]

For platforms not supp or ting Deep
Sx, connect directly to RSMRST#

PLTRST# Buffer

+3V

C341 0.1u/16V_4

2

A A

PCI_PLTRST#

1

U8

3 5

MC74VHC1G08

4

12

R212
100K_4

5

R8747

*10_5%_4

C8803

0.1u/16V_4

Reserved for ESD
01/17

PLTRST# [14,22,24,25,28]

SYSPWOK

EC_PWROK

4

SKL_ULT

SYSTEM POWER MANAGEMENT

+3V_S5

I
I

+3V_S5

+3V_S5
+3V_S5
+3V_S5

SKL_ULT

+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5
+1.8V_S5

+1.8V_S5
+1.8V_S5
+1.8V_S5

DPWROK_R PCH_RSMRST#

+3V_S5

+3V_S5
+3V_S5

11 OF 20

GPP_D4/FLASHTRIG

+3V_S5

EMMC

GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

9 OF 20

No Deep Sx

R582 0_4

+3V_S5
+3V_S5
+3V_S5
+3V_S5

+3V_S5
+3V_S5

+3V_S5
+3V_S5
+3V_S5

+3V_S5

GPP_B11/EXT_PWR_GATE#

CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3

CSI2_COMP

EMMC_RCOMP

Remove

R403 *0_4

GPP_B12/SLP_S0#

GPD4/SLP_S3#
GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS#

SLP_LAN#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

INTRUDER#

GPP_B2/VRALERT#

C37
D37
C32
D32
C29
D29
B26
A26

E13
B7

AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1

AM2
AM3
AP4

AT1

Non Deep Sx

R552 0_4

R410
*10K_4

AT11
AP15
BA16
AY16

AN15
AW15
BB17
AN16

BA15
AY15
AU13

AU11
AP16

INTRUDER#

MPHY_EXT_PWR

AM10

PCH_VRALERT#

AM11

R86 100/F_4

RAM_ID1
RAM_ID2
RAM_ID3
Board_ID0
Board_ID1
Board_ID2
Board_ID3
Board_ID4

Board_ID5
Board_ID6
Board_ID7

R542200/F_4

EC_PWROK_R

EC_PWROK [28]

3

SUS0#
SUSB#
SUSC#
PCH_SLP_S5#

PCH_SLP_SUS#
PCH_SLP_LAN#
PCH_SLP_WLAN#
PCH_SLP_A#

PCH_PWRBTN#

PCH_BATLOW#

R585 0_4
R584 0_4

R222 1M_4

TP58

Board_ID4 [20]

REV:E tPLT17(max
200us) ->SLP_S3#
assertion to IMVP
VR_ON(VRON) deassertion

VRON_R[34]

SUS0# [ 31]
SUSB# [ 28,31]
SUSC# [28]

TP79

TP23

TP33
TP72

TP75

TP35

TP32

TP30

4

U13
*MC74VHC1G08DFT2G

R244 0_4

Close t o CPU

VCCST_PWRGD

C557
1000P/50V_4

Stuff 1000P/50V

DNBSWON# [ 28]
SB_ACDC [28]

+3V_RTC

+3V_S5

C368 *0.1u/16V_4

2

SUSB#

1

VRON

3 5

+1V_VCCST

R427 60.4/F_4

Shor tpad change
to 60.4 ohm. 11/6

VCCST_PWRGD_EN

2013/10/21 Del APWORK.1A-6

REV:E tPLT15(max 200us)

->SLP_S4# assertion to
VDDQ(+1.35VSUS) ramp
down start(SUSON)

SUSON_R

SUSON_R[31,33]

VRON [28]

CRB is via +1.05V PGVCCST PWRGD

+3V_S5

U25

5

VCC

C528

R416

0.1u/16V_4

1K_4

VCCST_PWRGD_R

4

R390 *0_4
R391 0_4

2

Y

74AUP1G07GW

08

+3V

+3V_S5

SUSON [28]

B2A
S0->S5 & S0->S3
Power of sequence 1us
SUSB# -> VCCST_PWRGD

+3V_S5

C529 0.1u/16V_4

2

4

U24
MC74VHC1G08DFT2G

R388 *0_4

Skylake 9/11 (PWROK/Bo ard_ID)

Skylake 9/11 (PWROK/Bo ard_ID)

Skylake 9/11 (PWROK/Bo ard_ID)

SUSB#

VCCST_PWRGD_EN

1

3 5

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

Z8VR

Z8VR

Z8VR

1

4

U12
*TC7SH08FU

R235 0_4R538 10K_4

SYS_RESET#

PCH_ACPRESENT
PCH_BATLOW#

PCIE_LAN_WAKE#

MPHY_EXT_PWRPCH_SUSPWRDNACK_C

PCH_VRALERT#

PCH_RSMRST#
PCH_PWROK
SYS_PWROK_R

+3V_S5

3 5

R429 10K_4

R565 8.2K/F_4
R229 8.2K/F_4

R236 10K_4

R184 *1K_4

R206 10K_4

12/25 Change R206 pull-up to +3V_S5

R567 10K_4
R555 10K_4
R435 10K_4

C361 *0.1u/16V_4

2

1

12/28 Delete U12/C361 & Add R695

SUSC#

SUSON

12/28 Delete U14/R245/C372 & Change "MAINON_R" to "MAINON"

1

NC

VCCST_PWRGD_EN_L

2

A

3

GND

PCH_PWROK
HWPG

Rev:D change netmane for HWPG

C527

C530

*1000P/50V_4

*1000P/50V_4

HWPG [28]IMVP_PWRGD_3V [2]

Reserve 1000P/50V

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Thursday, June 22, 2017

Date: Sheet of

Thursday, June 22, 2017

Date: Sheet of

Thursday, June 22, 2017

8 46

8 46

8 46

1A

1A

1A

5

4

3

2

1

U34S

E68

AL25
AL27

BA70
BA68

B67
D65
D67

E70
C68
D68
C67

F71
G69

F70
G68
H70
G71
H69
G70

E63

F63

E66

F66

E60

E8

AY2
AY1

D1
D3

K46

K45

C71

B70

F60

A52

J71
J68

F65
G65

F61

E61

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]

CFG[16]
CFG[17]

CFG[18]
CFG[19]

CFG_RCOMP

ITP_PMODE

RSVD_AY2
RSVD_AY1

RSVD_D1
RSVD_D3

RSVD_K46
RSVD_K45

RSVD_AL25
RSVD_AL27

RSVD_C71
RSVD_B70

RSVD_F60

RSVD_A52

RSVD_TP_BA70
RSVD_TP_BA68

RSVD_J71
RSVD_J68

VSS_F65
VSS_G65

RSVD_F61
RSVD_E61

SKL_ULT/BGA

D D

CFG4

R79 49.9/F_4

+1V_S5

C C

B B

CFG_RCOMP

R88 1.5K/F_4

SKL_ULT

RESERVED SIGNALS-1

19 OF 20

RSVD_TP_BB68
RSVD_TP_BB69

RSVD_TP_AK13
RSVD_TP_AK12

RSVD_BB2
RSVD_BA3

RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2

RSVD_B3
RSVD_A3

RSVD_AW1

RSVD_E1
RSVD_E2

RSVD_BA4
RSVD_BB4

RSVD_A4
RSVD_C4

RSVD_A69
RSVD_B69

RSVD_AY3

RSVD_D71
RSVD_C70

RSVD_C54
RSVD_D54

VSS_AY71

ZVM#

RSVD_TP_AW71
RSVD_TP_AW70

MSM#

PROC_SELECT#

TP5
TP6

TP4

TP1
TP2

BB68
BB69

AK13
AK12

Rev:F reserve TP

BB2
BA3

AU5
AT5

D5
D4
B2
C2

B3
A3

AW1

E1
E2

BA4
BB4

A4
C4

BB5

A69
B69

R8748 *0_4

AY3

D71
C70

C54
D54

AY4
BB3

AY71

R8749 *0_4

AR56

AW71
AW70

AP56

R417 *100K_4

C64

TP24

+1V_VCCST

+1V_S5

+1V_S5

+1V_S5

+1V_S5

+1V_S5

+1V_S5

+3VPCU
+3V_S5

+1.5V

+3V_S5

+1V_S5

+3V_S5

+1V_S5

+1V_S5

+3V

VCCPRIM_1P0 & VCCPRIM_CORE Short

AB19
AB20

C199 1U/6.3V_4

C603 1U/6.3V_4
C8810 22u/6.3V_6
C8811 22u/6.3V_6

C233 1U/6.3V_4

C121 1U/6.3V_4

C117 47u/6.3V_8

C8807 Near CPU

R155 0_6

C111 1U/6.3V_4
C8807 0.1U/16V_4

C8808 0.1U/16V_4

C282 *1U/6.3V_4

R200 *0_6
R194 0_6

R588 0_6
R600 *0_6

C652 1U/6.3V_4

R174 0_6

C108 1U/6.3V_4

C278 1U/6.3V_4

C8815 0.1U/16V_4

C110 1U/6.3V_4

For 2+3e CPU No Stuff

+VCCDSW_1P0

C6231U/6.3V_4

C602 1U/6.3V_4

+VCCPDSW_3P3

C3360.1U/16V_4

+VCCHDA

+VCCPSPI

+VCCPRIM_3P3

AF18
AF19

AB17

AD17
AD18

AJ17

AJ19

AJ16

AF20
AF21

AJ21

AK20

P18

V20
V21

AL1

K17

N15
N16
N17

P15
P16

K15
L15

V15

Y18

T19
T20

N18

U34O

VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0

VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE

DCPDSW_1P0

VCCMPHYAON_1P0

L1

VCCMPHYAON_1P0

VCCMPHYGT_1P0_N15
VCCMPHYGT_1P0_N16
VCCMPHYGT_1P0_N17
VCCMPHYGT_1P0_P15
VCCMPHYGT_1P0_P16

VCCAMPHYPLL_1P0
VCCAMPHYPLL_1P0

VCCAPLL_1P0

VCCPRIM_1P0_AB17
VCCPRIM_1P0_Y18

VCCDSW_3P3_AD17
VCCDSW_3P3_AD18
VCCDSW_3P3_AJ17

VCCHDA

VCCSPI

VCCSRAM_1P0
VCCSRAM_1P0
VCCSRAM_1P0
VCCSRAM_1P0

VCCPRIM_3P3_AJ21

VCCPRIM_1P0_AK20

VCCAPLLEBB

SKL_ULT/BGA

SKL_ULT

CPU POWER 4 OF 4

1.5V

3.3V

1.0V

1.0V

S5

1.0V

1.0V

30mA

11mA

1.0V

642mA

1.0V

S5

1.0V

22mA

S5

1.0V

1.258A

1.0V

S5

1.0V

S5

3.3V

118mA

3.3V

1.0V

33mA

696mA

2.574A

75mA with AJ21 pin

6mA

26mA

696mA

S5

S5

+3V

75mA

696mA

15 OF 20

44mA

S5

33mA
41mA

VCCPRIM_3P3_V19

1.0V

VCCPRIM_1P0_T1

1.8V

<1mA

VCCRTCPRIM_3P3

3.0V+

RTC

1.0V

135mA

S5

GPP_B0/CORE_VID0
GPP_B1/CORE_VID1

S5

S5

VCCATS_1P8

VCCRTC_AK19
VCCRTC_BB14

GPIO Group Power Plane

AK15

VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE
VCCPGPPF

VCCPGPPG

DCPRTC

VCCCLK1

VCCCLK2

VCCCLK3

VCCCLK4

VCCCLK5

VCCCLK6

+VCCPGPPA

AG15

+VCCPGPPB

Y16

+VCCPGPPC

Y15

+VCCPGPPD

T16

+VCCPGPPE

AF16

+VCCPGPPF

AD15

+VCCPGPPG

+VCCPRIM_3P3

V19

+VCCPRIM_1P0

T1

+VCCATS_1P8

AA1

+VCCPRTCPRIM_3P3

AK17

AK19
BB14

BB10

A14

K19

L21

N20

L19

A10

V0P85A_VID0

AN11
AN13

C8812 0.1U/16V_4

C286 1U/6.3V_4

C358 1U/6.3V_4

+VCCPRTC

C352 1U/6.3V_4

C353 0.1U/16V_4

DCPRTC

C198 *1U/6.3V_4

C578 1U/6.3V_4

C325 *1U/6.3V_4
C309 1U/6.3V_4
C255 1U/6.3V_4

C274 *1U/6.3V_4
R186 0_6
R180 0_6
R154 0_6
R153 0_6
R161 0_6
R166 0_6
R171 0_6

C283 1U/6.3V_4

C299 *1U/6.3V_4

R165 0_6
R248 0_6

C362 0.1U/16V_4

R231 0_6

C641 0.1U/16V_4

TP37

+3V_S5
+3V_S5

+3V_S5
+3V_S5

+3V_S5

+1.8V_S5

+3V_S5

C8812 Near CPU

+1V_S5

+1.8V_S5
+3V_S5

+3V_RTC

+1V_S5

09

Pin Name Strap description Configuration

CFG[0]

CFG[1]

CFG[2]

CFG[3]

CFG[4]

CFG[6:5]

A A

CFG[7]

CFG[19:8]

Stall reset sequence after PCU PLL lock until de-asserted

Reserved Configuration lane

PCI Express* Static x16 Lane Numbering Reversal

Reserved Configuration lane

eDP enable

PCI Express* Bifunction

PEG Training

Reserved Configuration lane

5

1 = *Normal Operation; No stall (iPU 3K)

0 = Stall

1 = *Normal Operation(iPU 3K)

0 = Lan number reversed

1 = Disabled (iPU 3K)

0 = *Enabled

00 = 1x8, 2x4 PCI Express*
01 = reserved
10 = 2x8 PCI Express*
11 = 1x16 PCI Express*

1 = *PEG Train immediatedly follow
RESET# de-assertion (iPU 3K)

0 = PEG wait for BIOS for training

4

Note

H & S processor used only

R455 1K_4

CFG4

H & S processor used only

H & S processor used only

3

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Thursday, June 22, 2017

Date: Sheet of

Thursday, June 22, 2017

Date: Sheet of

2

Thursday, June 22, 2017

PROJECT :

Skylake PCH-LP 15/19 (POWER)

Skylake PCH-LP 15/19 (POWER)

Skylake PCH-LP 15/19 (POWER)

Z8VR

Z8VR

Z8VR

1A

1A

9 46

9 46

1

9 46

1A

5

4

3

2

1

Skylake ULT (GND)

G10
G22
G43
G45
G48

G52
G55
G58

G60
G63
G66

H15
H18
H71

K16
K18
K22
K61
K63
K64
K65
K66
K67
K68
K70
K71

F8

G5

G6

J11
J13
J25
J28
J32
J35
J38
J42

J8

L11
L16
L17

SKL_ULT

GND 3 OF 3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SKL_ULT/BGA

18 OF 20

U34R

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21

AW69

+1.8V_S5

XTAL24_OUT_C7

R491 *0_4

*1U/6.3V_4

Reserve 1uF no stuff in CPU U11,U12 ball
support Cannonlake-U PCH

XTAL24_IN_E3

XTAL24_OUT_C7

2

R8751 U42@0_5%_4

R8752 U42@0_5%_4

AW68

AU56

AW48

C7
U12
U11
H11

C614

REV = 1

R8750

U42@1M_5%_4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Thursday, June 22, 2017

Date: Sheet of

Thursday, June 22, 2017

Date: Sheet of

Thursday, June 22, 2017

U34T

RSVD_AW69
RSVD_AW68
RSVD_AU56
RSVD_AW48
RSVD_C7
RSVD_U12
RSVD_U11
RSVD_H11

SKL_ULT/BGA

Skylake 10/17/18 (GND)

Skylake 10/17/18 (GND)

Skylake 10/17/18 (GND)

AA2

AA4
AA65
AA68
AB15
AB16
AB18
AB21

AB8
AD13
AD16
AD19
AD20
AD21
AD62

AD8
AE64
AE65
AE66
AE67
AE68
AE69

AF1

AF10
AF15
AF17

AF2

AF4

AF63
AG16
AG17
AG18
AG19
AG20
AG21
AG71
AH13

AH6
AH63
AH64
AH67

AJ15
AJ18
AJ20

AK11
AK16
AK18
AK21
AK22
AK27
AK63
AK68
AK69

AK8

AL28
AL32
AL35
AL38

AL45
AL48
AL52
AL55
AL58
AL64

A67
A70

AJ4

AL2

AL4

A5

SKL_ULT

GND 1 OF 3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SKL_ULT/BGA

D D

C C

B B

A A

5

16 OF 20

U34P

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AL65
AL66
AM13
AM21
AM25
AM27
AM43
AM45
AM46
AM55
AM60
AM61
AM68
AM71
AM8
AN20
AN23
AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48
AR5
AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58

4

AT63
AT68
AT71
AU10
AU15
AU20
AU32
AU38

AV1
AV68
AV69
AV70
AV71

AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57

AW6
AW60
AW62
AW64
AW66

AW8

AY66

B10
B14
B18
B22
B30
B34
B39
B44
B48
B53
B58
B62
B66
B71

BA1
BA10
BA14
BA18

BA2
BA23
BA28
BA32
BA36

F68

BA45

SKL_ULT

GND 2 OF 3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SKL_ULT/BGA

17 OF 20

U34Q

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

BA49
BA53
BA57
BA6
BA62
BA66
BA71
BB18
BB26
BB30
BB34
BB38
BB43
BB55
BB6
BB60
BB64
BB67
BB70
C1
C25
C5
D10
D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58
D6
D62
D66
D69
E11
E15
E18
E21
E46
E50
E53
E56
E6
E65
E71
F1
F13
F2
F22
F23
F27
F28
F32
F33
F35
F37
F38
F4
F40
F42
BA41

3

?

SKL_ULT

SPARE

20 OF 20

RSVD_C11
RSVD_B11
RSVD_A11
RSVD_D12
RSVD_C12
RSVD_F52

RSVD_F6

RSVD_E3

?

F6

XTAL24_IN_E3

E3
C11
B11
A11
D12
C12
F52

For KBL R U42
(i)Non-stuff on KBL-U

XTAL24_IN_E3_R

XTAL24_OUT_C7_R

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

C232 U42@27p/50V_4

4

3

Y8004
U42@24MHZ/20ppm

1

2

C8806 U42@27p/50V_4

Z8VR

Z8VR

Z8VR

10 46

10 46

10 46

1

1A

1A

1A

5

4

3

2

1

M_A_A[13:0][3] M_A_DQ[63:0] [3]

D D

M_A_WE#[3]
M_A_CAS#[3]
M_A_RAS#[3]

+1.2VSUS

R315
240/F_4

M_A_EVENT#

+3V

C C

B B

R311

R313

*10K_4

*10K_4

CHA_SA0 CHA_SA1 CHA_SA2

R322

R320

10K_4

10K_4

R332
*10K_4

R333
10K_4

DDR3_DRAMRST#[3,12]

+1.2VSUS

M_A_ACT#[3]
M_A_PARITY[3]
M_A_ALERT#[3]

M_A_BA#0[3]
M_A_BA#1[3]
M_A_BG#0[3]
M_A_BG#1[3]

M_A_CS#0[3]
M_A_CS#1[3]
M_A_CKE0[3]
M_A_CKE1[3]

M_A_CLK0[3]
M_A_CLK0#[3]
M_A_CLK1[3]
M_A_CLK1#[3]

M_A_ODT0_DIMM[3]
M_A_ODT1_DIMM[3]

CLK_SCLK[7,12,19,26]
CLK_SDATA[7,12,19, 26]

C460 0.1U/16V_4

CHA_SA0
CHA_SA1
CHA_SA2

R319 240/F_4
R305 240/F_4
R308 240/F_4
R309 240/F_4
R318 240/F_4
R304 240/F_4
R317 240/F_4
R316 240/F_4

+1.2VSUS

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13

TP41
TP40

M_A_EVENT#

M_A_CB0
M_A_CB1
M_A_CB2
M_A_CB3
M_A_CB4
M_A_CB5
M_A_CB6
M_A_CB7

P/N and F/P

JDIM2A

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10/AP

120

A11

119

A12

158

A13

151

A14/WE#

156

A15/CAS#

152

A16/RAS#

162

S2#/C0

165

S3#/C1

114

ACT#

143

PARITY

116

ALERT#

134

EVENT#

108

RESET#

150

BA0

145

BA1

115

BG0

113

BG1

149

S0#

157

S1#

109

CKE0

110

CKE1

137

CK0

139

CK0#

138

CK1

140

CK1#

155

ODT0

161

ODT1

253

SCL

254

SDA

256

SA0

260

SA1

166

SA2

92

CB0

91

CB1

101

CB2

105

CB3

88

CB4

87

CB5

100

CB6

104

CB7

12

DM0

33

DM1

54

DM2

75

DM3

178

DM4

199

DM5

220

DM6

241

DM7

96

DM8

DDR4 SODIMM 260 PIN

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48

(260P)

DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8

DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7
DQS#8

M_A_DQ0

8

M_A_DQ1

7

M_A_DQ3

20

M_A_DQ6

21

M_A_DQ5

4

M_A_DQ4

3

M_A_DQ7

16

M_A_DQ2

17

M_A_DQ9

28

M_A_DQ8

29

M_A_DQ11

41

M_A_DQ10

42

M_A_DQ13

24

M_A_DQ12

25

M_A_DQ14

38

M_A_DQ15

37

M_A_DQ21

50

M_A_DQ16

49

M_A_DQ19

62

M_A_DQ22

63

M_A_DQ17

46

M_A_DQ20

45

M_A_DQ23

58

M_A_DQ18

59

M_A_DQ25

70

M_A_DQ28

71

M_A_DQ27

83

M_A_DQ30

84

M_A_DQ24

66

M_A_DQ29

67

M_A_DQ26

79

M_A_DQ31

80

M_A_DQ33

174

M_A_DQ37

173

M_A_DQ35

187

M_A_DQ34

186

M_A_DQ36

170

M_A_DQ32

169

M_A_DQ38

183

M_A_DQ39

182

M_A_DQ45

195

M_A_DQ41

194

M_A_DQ46

207

M_A_DQ42

208

M_A_DQ44

191

M_A_DQ40

190

M_A_DQ47

203

M_A_DQ43

204

M_A_DQ52

216

M_A_DQ53

215

M_A_DQ50

228

M_A_DQ51

229

M_A_DQ48

211

M_A_DQ49

212

M_A_DQ55

224

M_A_DQ54

225

M_A_DQ63

237

M_A_DQ58

236

M_A_DQ56

249

M_A_DQ61

250

M_A_DQ59

232

M_A_DQ62

233

M_A_DQ60

245

M_A_DQ57

246

M_A_DQS0

13

M_A_DQS1

34

M_A_DQS2

55

M_A_DQS3

76

M_A_DQS4

179

M_A_DQS5

200

M_A_DQS6

221

M_A_DQS7

242

M_A_DQS8

97

M_A_DQS#0

11

M_A_DQS#1

32

M_A_DQS#2

53

M_A_DQS#3

74

M_A_DQS#4

177

M_A_DQS#5

198

M_A_DQS#6

219

M_A_DQS#7

240

M_A_DQS#8

95

0-7

8-15

16-23

24-31

32-39

40-47

48-55

R306

56-63

M_A_DQS[7:0] [3]

M_A_DQS#[7:0] [3]

M_A_DQS8

M_A_DQS#8

240/F_4

R307

240/F_4

12/21 Change JDIM2 footprint to "ddr4-d4as0-26001-1p52-std-smt " for SMT requset

VREF DQ0 M1 Solution

+1.2VSUS

+1.2VSUS

+VREF_CA_CPU

+1.2VSUS

2250mA

2 1

C473

0.022U/25V_4

JDIM2B

111

VDD1

112

VDD2

117

VDD3

118

VDD4

123

VDD5

124

VDD6

129

VDD7

130

VDD8

135

VDD9

136

VDD10

141

VDD11

142

VDD12

147

VDD13

148

VDD14

153

VDD15

154

VDD16

159

VDD17

160

VDD18

163

VDD19

1

VSS1

5

VSS2

9

VSS3

15

VSS4

19

VSS5

23

VSS6

27

VSS7

31

VSS8

35

VSS9

39

VSS10

43

VSS11

47

VSS12

51

VSS13

57

VSS14

61

VSS15

65

VSS16

69

VSS17

73

VSS18

77

VSS19

81

VSS20

85

VSS21

89

VSS22

93

VSS23

99

VSS24

103

VSS25

107

VSS26

167

VSS27

171

VSS28

175

VSS29

181

VSS30

185

VSS31

189

VSS32

193

VSS33

197

VSS34

201

VSS35

205

VSS36

209

VSS37

213

VSS38

217

VSS39

223

VSS40

227

VSS41

231

VSS42

235

VSS43

239

VSS44

243

VSS45

247

VSS46

251

VSS47

R327 2/F_6

R334 24.9/F_4

DDR4 SODIMM 260 PIN

+1.2VSUS

VDDSPD

VPP1
VPP2

VTT

VREF_CA

VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68

(260P)

VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94

GND
GND

R321
1K/F_4

VREF_CA_DIMM0

R328
1K/F_4

255

257
259

258

164

2
6
10
14
18
22
26
30
36
40
44
48
52
56
60
64
68
72
78
82
86
90
94
98
102
106
168
172
176
180
184
188
192
196
202
206
210
214
218
222
226
230
234
238
244
248
252

261
262

VREF_CA_DIMM0

C379 2.2U/6.3V/X7R_6

C377 0.1U/25V_4

R271 *0_4

R282 0_4

0.5A

600mA

R325*0_4

+2.5V_SUS

+VDDQ_VTT

11

+2.5V

+3V

12/4 Change for +3.3V to +3V

+VDDQ

Place these Caps near So-Dimm1.

1uF/10uF 4pcs on each side of connector

+1.2VSUS

C399 1U/6.3V_4

C391 1U/6.3V_4

C408 1U/6.3V_4

C381 1U/6.3V_4

C449 1U/6.3V_4

C414 1U/6.3V_4

A A

+1.2VSUS[3,5,12,33,40]

+VDDQ_VTT[12,33]

+3V[2,4,6,7,8,9,12,14,15,16,17, 19,20,21,22,23,24,25,26,27,28,30,31,33,34,37, 38,39,40]

5

4

C427 1U/6.3V_4

C438 1U/6.3V_4

C392 10U/6.3V_6
C385 10U/6.3V_6

C383 10U/6.3V_6
C382 10U/6.3V_6

C393 10U/6.3V_6
C426 10U/6.3V_6

C416 10U/6.3V_6
C386 10U/6.3V_6

3

+VDDQ_VTT

+3V

C425 1U/6.3V_4

C412 1U/6.3V_4

C423 1U/6.3V_4

C415 1U/6.3V_4

C409 10U/6.3V_6

C444 0.1U/16V_4

C441 2.2U/6.3V_6

VREF_CA_DIMM0

+2.5V_SUS

C465 0.1U/16V_4

C464 2.2U/6.3V_6

C374 0.1U/16V_4

C378 2.2U/6.3V_6

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Thursday, June 22, 2017

Date: Sheet of

Thursday, June 22, 2017

Date: Sheet of

2

Thursday, June 22, 2017

PROJECT :

DDR4 DIMM-RVS(5.2H) CHA

DDR4 DIMM-RVS(5.2H) CHA

DDR4 DIMM-RVS(5.2H) CHA

Z8VR

Z8VR

Z8VR

11 46

11 46

11 46

1

1A

1A

1A

5

4

3

2

1

M_B_A[13:0][3]

D D

M_B_WE#[3]
M_B_CAS#[3]
M_B_RAS#[3]

M_B_ACT#[3]
M_B_PARITY[3]

R290
*10K_4

R287
10K_4

DDR3_DRAMRST#[3,11]

+1.2VSUS

M_B_ALERT#[3]

M_B_BA#0[3]
M_B_BA#1[3]
M_B_BG#0[3]
M_B_BG#1[3]

M_B_CS#0[3]
M_B_CS#1[3]
M_B_CKE0[3]
M_B_CKE1[3]

M_B_CLK0[3]
M_B_CLK0#[3]
M_B_CLK1[3]
M_B_CLK1#[3]

M_B_ODT0_DIMM[3]
M_B_ODT1_DIMM[3]

CLK_SCLK[7,11,19,26]
CLK_SDATA[7,11,19, 26]

+1.2VSUS

R301
240/F_4

M_B_EVENT#

+3V

C C

R300

R302

*10K_4

10K_4

CHB_SA0 CHB_SA1 CHB_SA2

R294

R295

10K_4

*10K_4

B B

M_B_A0
M_B_A1 M_B_DQ8
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13

M_B_EVENT#

C461 0.1U/16V_4

CHB_SA0
CHB_SA1
CHB_SA2

R292 240/F_4
R272 240/F_4
R280 240/F_4
R275 240/F_4
R293 240/F_4
R273 240/F_4
R288 240/F_4
R303 240/F_4

+1.2VSUS

TP39
TP38

M_B_CB0

M_B_CB1
M_B_CB2
M_B_CB3

M_B_CB4

M_B_CB5
M_B_CB6
M_B_CB7

JDIM1A

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10/AP

120

A11

119

A12

158

A13

151

A14/WE#

156

A15/CAS#

152

A16/RAS#

162

S2#/C0

165

S3#/C1

114

ACT#

143

PARITY

116

ALERT#

134

EVENT#

108

RESET#

150

BA0

145

BA1

115

BG0

113

BG1

149

S0#

157

S1#

109

CKE0

110

CKE1

137

CK0

139

CK0#

138

CK1

140

CK1#

155

ODT0

161

ODT1

253

SCL

254

SDA

256

SA0

260

SA1

166

SA2

92

CB0

91

CB1

101

CB2

105

CB3

88

CB4

87

CB5

100

CB6

104

CB7

12

DM0

33

DM1

54

DM2

75

DM3

178

DM4

199

DM5

220

DM6

241

DM7

96

DM8

DDR4 SODIMM 260 PIN

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48

(260P)

DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8

DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7
DQS#8

M_B_DQ9

8
7

M_B_DQ10

20

M_B_DQ15

21

M_B_DQ13

4

M_B_DQ12

3

M_B_DQ11

16

M_B_DQ14

17

M_B_DQ5

28

M_B_DQ1

29

M_B_DQ6

41

M_B_DQ7

42

M_B_DQ4

24

M_B_DQ0

25

M_B_DQ2

38

M_B_DQ3

37

M_B_DQ17

50

M_B_DQ21

49

M_B_DQ23

62

M_B_DQ19

63

M_B_DQ16

46

M_B_DQ20

45

M_B_DQ22

58

M_B_DQ18

59

M_B_DQ28

70

M_B_DQ25

71

M_B_DQ26

83

M_B_DQ27

84

M_B_DQ29

66

M_B_DQ24

67

M_B_DQ30

79

M_B_DQ31

80

M_B_DQ37

174

M_B_DQ32

173

M_B_DQ39

187

M_B_DQ34

186

M_B_DQ36

170

M_B_DQ33

169

M_B_DQ38

183

M_B_DQ35

182

M_B_DQ44

195

M_B_DQ45

194

M_B_DQ42

207

M_B_DQ47

208

M_B_DQ41

191

M_B_DQ40

190

M_B_DQ43

203

M_B_DQ46

204

M_B_DQ49

216

M_B_DQ53

215

M_B_DQ54

228

M_B_DQ50

229

M_B_DQ52

211

M_B_DQ48

212

M_B_DQ51

224

M_B_DQ55

225

M_B_DQ56

237

M_B_DQ60

236

M_B_DQ58

249

M_B_DQ62

250

M_B_DQ61

232

M_B_DQ57

233

M_B_DQ59

245

M_B_DQ63

246

M_B_DQS1

13

M_B_DQS0

34

M_B_DQS2

55

M_B_DQS3

76

M_B_DQS4

179

M_B_DQS5

200

M_B_DQS6

221

M_B_DQS7

242

M_B_DQS8

97

M_B_DQS#1

11

M_B_DQS#0

32

M_B_DQS#2

53

M_B_DQS#3

74

M_B_DQS#4

177

M_B_DQS#5

198

M_B_DQS#6

219

M_B_DQS#7

240

M_B_DQS#8

95

M_B_DQ[63:0] [3]

8-15

0-7

16-23

24-31

32-39

40-47

48-55

56-63

M_B_DQS[7:0] [3]

M_B_DQS#[7:0] [3]

M_B_DQS8

M_B_DQS#8

R277

240/F_4

R278

240/F_4

+1.2VSUS

2250mA

+1.2VSUS

+1.2VSUS

JDIM1B

111

VDD1

112

VDD2

117

VDD3

118

VDD4

123

VDD5

124

VDD6

129

VDD7

130

VDD8

135

VDD9

136

VDD10

141

VDD11

142

VDD12

147

VDD13

148

VDD14

153

VDD15

154

VDD16

159

VDD17

160

VDD18

163

VDD19

1

VSS1

5

VSS2

9

VSS3

15

VSS4

19

VSS5

23

VSS6

27

VSS7

31

VSS8

35

VSS9

39

VSS10

43

VSS11

47

VSS12

51

VSS13

57

VSS14

61

VSS15

65

VSS16

69

VSS17

73

VSS18

77

VSS19

81

VSS20

85

VSS21

89

VSS22

93

VSS23

99

VSS24

103

VSS25

107

VSS26

167

VSS27

171

VSS28

175

VSS29

181

VSS30

185

VSS31

189

VSS32

193

VSS33

197

VSS34

201

VSS35

205

VSS36

209

VSS37

213

VSS38

217

VSS39

223

VSS40

227

VSS41

231

VSS42

235

VSS43

239

VSS44

243

VSS45

247

VSS46

251

VSS47

12/21 Change JDIM1 footprint to "ddr4-d4ar0-26001-1p52-rvs-smt " for SMT requset

DDR4 SODIMM 260 PIN

VDDSPD

VPP1
VPP2

VTT

VREF_CA

VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68

(260P)

VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94

GND
GND

C395 2.2U/6.3V/X7R_6

255

257
259

258

VREF_CA_DIMM1

164

2
6
10
14
18
22
26
30
36
40
44
48
52
56
60
64
68
72
78
82
86
90
94
98
102
106
168
172
176
180
184
188
192
196
202
206
210
214
218
222
226
230
234
238
244
248
252

261
262

C401 0.1U/25V_4

R276 *0_4

R281 0_4

0.5A

600mA

+2.5V

+3V

+2.5V_SUS

12/4 Change for +3.3V to +3V

+VDDQ_VTT

+3V[2,4,6,7,8,9,11,14,15,16,17, 19,20,21,22,23,24,25,26,27,28,30,31,33,34,37, 38,39,40]

+1.2VSUS[3,5,11,33,40]

+VDDQ_VTT[11,33]

12

For EMI RESERVE

+1.2VSUS

EC1 *120P/50V_4 C448 1U/6. 3V_4

EC8 *120P/50V_4

EC2 *120P/50V_4

EC4 *120P/50V_4

EC5 *120P/50V_4

EC6 *120P/50V_4

A A

+VDDQ_VTT

EC7 *120P/50V_4

EC14 *120P/50V_4

5

+1.2VSUS

EC16 *120P/50V_4

EC10 *120P/50V_4

EC12 *120P/50V_4

EC11 *0.1U/16V_4

EC15 *0.1U/16V_4

EC13 *0.1U/16V_4

4

Place these Caps near So-Dimm0.

1uF/10uF 4pcs on each side of connector

+1.2VSUS +VDDQ_VTT

C380 1U/6.3V_4

C458 1U/6.3V_4

C454 1U/6.3V_4

C457 1U/6.3V_4

C456 1U/6.3V_4

C436 1U/6.3V_4

C432 1U/6.3V_4

C469 10U/6.3V_6

C437 10U/6.3V_6

C470 10U/6.3V_6

C468 10U/6.3V_6

C439 10U/6.3V_6

C463 10U/6.3V_6

C462 10U/6.3V_6

C440 10U/6.3V_6

VREF_CA_DIMM1

+2.5V_SUS

+3V

C471 1U/6.3V_4

C453 1U/6.3V_4

C459 1U/6.3V_4

C467 1U/6.3V_4

C424 1U/6.3V_4EC9 *0.1U/16V_4

C411 0.1U/16V_4

C413 2.2U/6.3V_6

C434 0.1U/16V_4

C430 2.2U/6.3V_6

C428 0.1U/16V_4

C431 2.2U/6.3V_6

3

VREF DQ1 M1 Solution

+VREFDQ_SB_M3

+1.2VSUS

R286

+VREFDQ_SB_M3 VREF_CA_DIMM1

R298 2/F_6

C419

0.022U/25V_4

2 1

R299

24.9/F_4

2

1K/F_4EC3 120P/50V_4

R297
1K/F_4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Thursday, June 22, 2017

Date: Sheet of

Thursday, June 22, 2017

Date: Sheet of

Thursday, June 22, 2017

R296*0_4

+VDDQ

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

DDR4 DIMM-STD(5.2H ) CHB

DDR4 DIMM-STD(5.2H ) CHB

DDR4 DIMM-STD(5.2H ) CHB

Z8VR

Z8VR

Z8VR

12 46

12 46

12 46

1

1A

1A

1A

1

+1.03_GFX

A A

Near GPU

C8672 EV@22u/6.3V_6
C8372 EV@22u/6.3V_6
C8373 EV@4.7U/10V_6
C8376 EV@4.7U/10V_6
C8380 EV@4.7U/10V_6

C8384 EV@1U/6.3V_4
C8383 EV@1U/6.3V_4

Under GPU

PEX_IOVDD + PEX_IOVDDQ = 1.042A

+1.03_GFX

+1.8_GFX_MAIN

N16_1.03V-->R1008/R1009
N17_1.8V--->R1010/R1011

PEX_PLL_HVDD +
PEX_SVDD_3V3 = 143mA

B B

C C

N16-->R8240 Mount
N17--->R8240 N/A

+1.03_GFX

D D

R1008 N16@0_6

R1009 N16@0_6

R1010 N17@0_6

R1011 N17@0_6

N16-->R1012 Mount
N17--->R1013Mount

C8381 EV@0.1U/16V_4
C8379 EV@4.7U/10V_6

100 ohm near GPU

VGA_VCCSENSE[38]

VGA_VSSSENSE[38]

R8597 *200/F_4

R8240 N16@0_6

Near GPU

Under GPU

EV@10K/F_4

1

C8378 EV@22u/6.3V_6
C8374 EV@22u/6.3V_6
C8369 EV@10U/10V_6
C8375 EV@4.7U/10V_6
C8670 EV@4.7U/10V_6

Near GPU

Under GPU

C8395 EV@1U/6.3V_4

+3V_GFX+1.8_GFX_MAIN

R1013

N17@0_6

C8388 EV@4.7U/10V_6

Near GPU

R1014 N16@0_6

N16-->R1014 Mount
N17--->R1014 N/A

+VGPU_CORE

R8311
EV@100_4

R8315
EV@100_4

PEX_TSTCLK
PEX_TSTCLK#

CX300T30001 Change to 0ohm

PEX_PLLVDD

C8344EV@4.7U/10V_6
C8394EV@1U/6.3V_4

C8391EV@0.1U/16V_4

PEX_PLLVDD = 130mA

TESTMODE

R8259

PEX_TERMP

R8599EV@2.49K/F_4

R1012

N16@0_6

AA22
AB23
AC24
AD25
AE26
AE27

AA10
AA12
AA13
AA16
AA18
AA19
AA20
AA21
AB22
AC23
AD24
AE25
AF26
AF27

AF22
AE22

AA14
AA15

AF25

AA8
AA9

AB8

F2

F1

AD9

2

U8039A

PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD
PEX_IOVDD

PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ
PEX_IOVDDQ

PEX_PLL_HVDD
PEX_PLL_HVDD

PEX_SVDD_3V3

VDD_SENSE

GND_SENSE

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT

PEX_PLLVDD
PEX_PLLVDD

TESTMODE

PEX_TERMP

2

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

1/14 PCI_EXPRESS

PEX_WAKE

PEX_RST

PEX_CLKREQ

PEX_REFCLK
PEX_REFCLK

PEX_TX0
PEX_TX0

PEX_RX0
PEX_RX0

PEX_TX1
PEX_TX1

PEX_RX1
PEX_RX1

PEX_TX2
PEX_TX2

PEX_RX2
PEX_RX2

PEX_TX3
PEX_TX3

PEX_RX3
PEX_RX3

PEX_TX4
PEX_TX4

PEX_RX4
PEX_RX4

PEX_TX5
PEX_TX5

PEX_RX5
PEX_RX5

PEX_TX6
PEX_TX6

PEX_RX6
PEX_RX6

PEX_TX7
PEX_TX7

PEX_RX7
PEX_RX7

PEX_TX8
PEX_TX8

PEX_RX8
PEX_RX8

PEX_TX9
PEX_TX9

PEX_RX9
PEX_RX9

PEX_TX10
PEX_TX10

PEX_RX10
PEX_RX10

PEX_TX11
PEX_TX11

PEX_RX11
PEX_RX11

PEX_TX12
PEX_TX12

PEX_RX12
PEX_RX12

PEX_TX13
PEX_TX13

PEX_RX13
PEX_RX13

PEX_TX14
PEX_TX14

PEX_RX14
PEX_RX14

PEX_TX15
PEX_TX15

PEX_RX15
PEX_RX15

GF119GF117

COMMONbga595-nvidia-n13p-gv2-s-a2

3

AB6

AC7

AC6

AE8
AD8

AC9
AB9

AG6
AG7

AB10
AC10

AF7
AE7

AD11
AC11

AE9
AF9

AC12
AB12

AG9
AG10

AB13
AC13

AF10
AE10

AD14
AC14

AE12
AF12

AC15
AB15

AG12
AG13

AB16
AC16

AF13
AE13

AD17
AC17

AE15
AF15

AC18
AB18

AG15
AG16

AB19
AC19

AF16
AE16

AD20
AC20

AE18
AF18

AC21
AB21

AG18
AG19

AD23
AE23

AF19
AE19

AF24
AE24

AE21
AF21

AG24
AG25

AG21
AG22

3

C8352 *0.1U/16V_4

VGA_RST#

R8243 EV@0_4

PEX_CLKREQ#

PEG_RXP0_C
PEG_RXN0_C

PEG_RXP1_C
PEG_RXN1_C

PEG_RXP2_C
PEG_RXN2_C

PEG_RXP3_C
PEG_RXN3_C

R8281 N16@10K/F_4
R8282 N17@10K/F_4

C8684 EV@0.22U/10V_4
C8685 EV@0.22U/10V_4

C8682 EV@0.22U/10V_4
C8683 EV@0.22U/10V_4

C8687 EV@0.22U/10V_4
C8686 EV@0.22U/10V_4

C8681 EV@0.22U/10V_4
C8680 EV@0.22U/10V_4

+1V8_AON

R11321 N17@0_4

DGPU_HOLD_RST#[4]

PLTRST#[8,22,24,25,28]

N16V stuff i t, not support GC6 2.0

GPU_PEX_RST_HOLD#[17]

EV@NL17SZ08DFT2G

SYS_PEX_RST_MON#

SYS_PEX_RST

PEX_CLKREQ#

4

PEGX_RST# [17]

+3V_GFX
+1V8_AON

CLK_PCIE_VGA [6]
CLK_PCIE_VGA# [6]

PEG_RX0 [6]
PEG_RX#0 [6]

PEG_TX0 [6]
PEG_TX#0 [6]

PEG_RX1 [6]
PEG_RX#1 [6]

PEG_TX1 [6]
PEG_TX#1 [6]

PEG_RX2 [6]
PEG_RX#2 [6]

PEG_TX2 [6]
PEG_TX#2 [6]

PEG_RX3 [6]
PEG_RX#3 [6]

PEG_TX3 [6]
PEG_TX#3 [6]

+3V

U8018

2

1

R8317 N17@0_4

GPU_PEX_RST_HOLD#

4

R11320

N16@0_4

C8398
EV@0.1U/16V_4

SYS_PEX_RST

4

3 5

SYS_PEX_RST_MON# [17]

U8021

N16@MC74VHC1G08DFT2G

2

1

+3V_GFX+1.8_GFX_MAIN

R90031

R90030

N16@0_4

N17@0_4

Follow Z09 to isolate CLK_REQ#

2

Q8017

EV@PJA138K

3

1

R8267 *0_4

5

12

+

SYS_PEX_RST_MON#

C8469

N16@0.1U/16V_4

PEGX_RST#

R8316
EV@100K/F_4

CLK_PEGA_REQ# [6]

5

+VGPU_CORE

K10
K12
K14
K16
K18
L11
L13
L15
L17
M10
M12
M14
M16
M18
N11
N13
N15
N17
P10
P12
P14
P16
P18
R11
R13
R15
R17
T10
T12
T14
T16
T18
U11
U13
U15
U17
V10
V12
V14
V16
V18

R8329

N16@100K/F_4

U8039E

11/14 NVVDD

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

bga595-nvidia-n13p-gv2-s-a2

COMMON

NVDD = 32.22 ~ 26.66 A

Under GPU

C8393 EV@1U/6.3V_4
C8403 EV@1U/6.3V_4
C8424 EV@1U/6.3V_4
C8414 EV@1U/6.3V_4
C8426 EV@4.7U/10V_6
C8435 EV@4.7U/10V_6
C8434 EV@4.7U/10V_6
C8441 EV@4.7U/10V_6
C8416 EV@4.7U/10V_6
C8428 EV@4.7U/10V_6
C8415 EV@4.7U/10V_6
C8408 EV@4.7U/10V_6
C8400 EV@4.7U/10V_6
C8432 EV@4.7U/10V_6

C8413
EV@330u_2.5V_3528

C8402 EV@22U/6.3V_8
C8401 EV@47u/6.3V_8

C8417 EV@4.7U/6.3VS_6
C8404 EV@4.7U/6.3VS_6
C8405 EV@4.7U/6.3VS_6
C8406 EV@4.7U/6.3VS_6
C8418 EV@4.7U/6.3VS_6

Near GPU

R8318 N16@0_4

+3V

4

3 5

change power from +3V-GFX t o DGPU_PWROK 02/20
add N17/N16 option t o avoid leakage 03/ 21

PU at page 9

6

+1.8_GFX_MAIN

R1015

N17@0_6

AD10

AD7
B19

F11

V5
V6

G1
G2
G3
G4
G5
G6
G7

W1
W2
W3
W4

ALL 3.3V
+3VGFX(+1.8V_AON)

ALL 3.3V
3V3_MAIN(+1.8_GFX_MAIN)

+VGACORE

PEX_VDD
+1.05V_GFX

FBVDDQ
+1.5V_GFX

6

N16-->R1015 N/A
N17--->R1015 Mount

VDD33 = 56mA

U8039C

14/14 XVDD/VDD33

NC
NC
NC

3V3AUX_NC

FERMI_RSVD1_NC
FERMI_RSVD2_NC

CONFIGURABLE

POWER CHANNELS

* nc on substrate

XPWR_G1
XPWR_G2
XPWR_G3
XPWR_G4
XPWR_G5
XPWR_G6
XPWR_G7

V1

XPWR_V1

V2

XPWR_V2

XPWR_W1
XPWR_W2
XPWR_W3
XPWR_W4

bga595-nvidia-n13p-gv2-s-a2 COMMON

t>0NVVDD

7

N16-->R1017
N17--->R1016(初始)

VDD33
VDD33

VDD33
VDD33

R1016 N17@0_6

G10

R1017

G12

C8452 EV@0.1U/16V_4

C8461 EV@4.7U/10V_6
C8460 EV@1U/10V_6

G8
G9

C8449 EV@4.7U/10V_6
C8448 EV@1U/10V_6

C8443 EV@0.1U/16V_4
C8444 EV@0.1U/16V_4C8386 EV@1U/6.3V_4

1 2

1 2

N16@0_6

+1V8_AON
+3V_GFX

Under GPU

Near GPU

N16-->R1031
N17--->R1030(初始)

Under GPU

Power up
sequence

t>=0

Power down
sequence

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Doc ument Number Rev

Size Doc ument Number Rev

Size Doc ument Number Rev

Date: Sheet of

Thursday, June 22, 2017

Date: Sheet of

Thursday, June 22, 2017

Date: Sheet of

Thursday, June 22, 2017

7

PROJECT :

N16S-GT (PCIE I/F) /NVDD

N16S-GT (PCIE I/F) /NVDD

N16S-GT (PCIE I/F) /NVDD

N16@0_6

N17@0_6

Z8VR

Z8VR

Z8VR

8

R1031

R1030

14 47

14 47

14 47

8

14

+3V_MAIN

+1.8_GFX_MAIN

2A

2A

2A

1

R8644 EV@10K/F_4

A A

FBA_CMD0[18]
FBA_CMD1[18]
FBA_CMD2[18]
FBA_CMD3[18]
FBA_CMD4[18]
FBA_CMD5[18]
FBA_CMD6[18]
FBA_CMD7[18]

B B

C C

+1.35V_GFX

FB_PLLAVDD = 55mA

+1.8_GFX_MAIN

+1.03_GFX

D D

N16_L8007-->1.05V
N17_L8010--->1.8V

L8010

N17@BLM15PX330SN1DEV_4

N16@BLM15PX330SN1DEV_4

L8007

C8365 EV@22u/6.3 V_6
C8453 EV@0.1 U/16V_4
C8447 EV@0.1 U/16V_4
C8445 EV@0.1 U/16V_4

FBA_CMD8[18]

FBA_CMD9[18]
FBA_CMD10[18]
FBA_CMD11[18]
FBA_CMD12[18]
FBA_CMD13[18]
FBA_CMD14[18]
FBA_CMD15[18]
FBA_CMD16[18]

FBA_CMD17[18]

FBA_CMD18[18]
FBA_CMD19[18]
FBA_CMD20[18]
FBA_CMD21[18]
FBA_CMD22[18]
FBA_CMD23[18]
FBA_CMD24[18]
FBA_CMD25[18]
FBA_CMD26[18]
FBA_CMD27[18]
FBA_CMD28[18]
FBA_CMD29[18]
FBA_CMD30[18]
FBA_CMD31[18]

R8339 *60.4_4
R8341 *60.4_4

VMA_CLK0[18]

VMA_CLK0#[18]

VMA_CLK1[18]

VMA_CLK1#[18]

VMA_WCK01[18]

VMA_WCK01#[18]

VMA_WCK23[18]

VMA_WCK23#[18]

VMA_WCK45[18]

VMA_WCK45#[18]

VMA_WCK67[18]

VMA_WCK67#[18]

FB_DLLAVDD = 15mA

1

PS_FB_CLAMP

+FB_PLLAVDD

2

F3

C27
C26
E24
F24
D27
D26
F25
F26
F23
G22
G23
G24
F27
G25
G27
G26
M24
M23
K24
K23
M27
M26
M25
K26
K22
J23
J25
J24
K27
K25
J27
J26

F22
J22

D24
D25
N22
M22

D18
C18
D17
D16
T24
U24
V24
V25

F16

P22

H22

2

U8039B

FB_CLAMP

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31

FBA_DEBUG0
FBA_DEBUG1

FBA_CLK0
FBA_CLK0
FBA_CLK1
FBA_CLK1

FBA_WCK01
FBA_WCK01
FBA_WCK23
FBA_WCK23
FBA_WCK45
FBA_WCK45
FBA_WCK67
FBA_WCK67

FB_PLLAVDD

FB_PLLAVDD

FB_DLLAVDD

INT

bga595-nvidia-n13p-gv2-s-a2

GF119NC

GF117

GF119

GF117FB_PLLAVDD

3

3

2/14 FBA

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8

FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7

FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7

FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7

FB_VREF_PROBE

COMMON

VMA_DQ0

E18

VMA_DQ1

F18

VMA_DQ2

E16

VMA_DQ3

F17

VMA_DQ4

D20

VMA_DQ5

D21

VMA_DQ6

F20

VMA_DQ7

E21

VMA_DQ8

E15

VMA_DQ9

D15

VMA_DQ10

F15

VMA_DQ11

F13

VMA_DQ12

C13

VMA_DQ13

B13

VMA_DQ14

E13

VMA_DQ15

D13

VMA_DQ16

B15

VMA_DQ17

C16

VMA_DQ18

A13

VMA_DQ19

A15

VMA_DQ20

B18

VMA_DQ21

A18

VMA_DQ22

A19

VMA_DQ23

C19

VMA_DQ24

B24

VMA_DQ25

C23

VMA_DQ26

A25

VMA_DQ27

A24

VMA_DQ28

A21

VMA_DQ29

B21

VMA_DQ30

C20

VMA_DQ31

C21

VMA_DQ32

R22

VMA_DQ33

R24

VMA_DQ34

T22

VMA_DQ35

R23

VMA_DQ36

N25

VMA_DQ37

N26

VMA_DQ38

N23

VMA_DQ39

N24

VMA_DQ40

V23

VMA_DQ41

V22

VMA_DQ42

T23

VMA_DQ43

U22

VMA_DQ44

Y24

VMA_DQ45

AA24

VMA_DQ46

Y22

VMA_DQ47

AA23

VMA_DQ48

AD27

VMA_DQ49

AB25

VMA_DQ50

AD26

VMA_DQ51

AC25

VMA_DQ52

AA27

VMA_DQ53

AA26

VMA_DQ54

W26

VMA_DQ55

Y25

VMA_DQ56

R26

VMA_DQ57

T25

VMA_DQ58

N27

VMA_DQ59

R27

VMA_DQ60

V26

VMA_DQ61

V27

VMA_DQ62

W27

VMA_DQ63

W25

FBA_DBI0

D19

FBA_DBI1

D14

FBA_DBI2

C17

FBA_DBI3

C22

FBA_DBI4

P24

FBA_DBI5

W24

FBA_DBI6

AA25

FBA_DBI7

U25

FBA_EDC0

E19

FBA_EDC1

C15

FBA_EDC2

B16

FBA_EDC3

B22

FBA_EDC4

R25

FBA_EDC5

W23

FBA_EDC6

AB26

FBA_EDC7

T26

F19
C14
A16
A22

GDDR5 NO USE

P25
W22
AB27
T27

D23

TP8038

4

VMA_DQ[63:0]

FBVDDQ + FBVDD = 3.116A

C8385 EV@0.1U/16V_4
C8450 EV@0.1U/16V_4

1 2

C8451 EV@1U/10V_6
C8440 EV@1U/10V_61 2
C8433 EV@4.7U/10V_6
C8387 EV@4.7U/10V_6
C8397 EV@10U/6.3V_6
C8425 EV@22u/6.3V_6
C8816 *EV@22u/6.3V_6

FBA_DBI[7:0] [18]

FBA_EDC[7:0] [18]

4

5

VMA_DQ[63:0] [18]

+1.35V_GFX

5

U8039D

12/14 FBVDDQ

B26

FBVDDQ

C25

FBVDDQ

E23

FBVDDQ

E26

FBVDDQ

F14

FBVDDQ

F21

FBVDDQ

G13

FBVDDQ

G14

FBVDDQ

G15

FBVDDQ

G16

FBVDDQ

G18

FBVDDQ

G19

FBVDDQ

G20

FBVDDQ

G21

FBVDDQ

H24

FBVDDQ

H26

FBVDDQ

J21

FBVDDQ

K21

FBVDDQ

L22

FBVDDQ

L24

FBVDDQ

L26

FBVDDQ

M21

FBVDDQ

N21

FBVDDQ

R21

FBVDDQ

T21

FBVDDQ

V21

FBVDDQ

W21

FBVDDQ

bga595-nvidia-n13p-gv2-s-a2

COMMON

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_CALTERM_GND

6

FB_CAL_PD_VDDQ

D22

FB_CAL_PU_GND

C24

FB_CAL_TERM_GND

B25

6

7

R8340 EV@40.2/F_4

+1.35V_GFX

R8320 EV@40.2/F_4

R8319 EV@60.4/F_4

For support GC6 1.0

For support GC6 2.0

GC6_FB_EN[4,17]

GPU_PWR_GD[38,40]

R8292 EV@0_4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

7

U8039F

A2
AB17
AB20
AB24

AC2
AC22
AC26

AC5

AC8
AD12
AD13

A26
AD15
AD16
AD18
AD19
AD21
AD22
AE11
AE14
AE17
AE20
AB11

AF1

AF11
AF14
AF17
AF20
AF23

AF5

AF8

AG2
AG26
AB14

B1
B11
B14
B17
B20
B23
B27

B5

B8
E11
E14
E17

E2
E20
E22
E25

E5

E8

H2
H23
H25

H5
K11
K13
K15
K17

L10
L12
L14
L16
L18

L2
L23
L25

L5

M11

bga595-nvidia-n13p-gv2-s-a2 COMMON

+3V

C8370
EV@0.1U/16V_4

EV@NL17SZ32DFT2G2

1

Thursday, June 22, 2017

Thursday, June 22, 2017

Thursday, June 22, 2017

4

U8017

3 5

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

N16S-GT (MEMORY/GND)

N16S-GT (MEMORY/GND)

N16S-GT (MEMORY/GND)

13/14 GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

R8272
EV@100K/F_4

Z8VR

Z8VR

Z8VR

8

15

M13

GND

M15

GND

M17

GND

N10

GND

N12

GND

N14

GND

N16

GND

N18

GND

P11

GND

P13

GND

P15

GND

P17

GND

P2

GND

P23

GND

P26

GND

P5

GND

R10

GND

R12

GND

R14

GND

R16

GND

R18

GND

T11

GND

T13

GND

T15

GND

T17

GND

U10

GND

U12

GND

U14

GND

U16

GND

U18

GND

U2

GND

U23

GND

U26

GND

U5

GND

V11

GND

V13

GND

V15

GND

V17

GND

Y2

GND

Y23

GND

Y26

GND

Y5

GND

AA7

GND

AB7

GND

FBVDDQ_EN [39]

15 47

15 47

15 47

8

2A

2A

2A

1

U8039G

4/14 IFPAB

GF119

GF117

GF117GF119

GF117

GF117

NC

NC

GF117

NC

NC
NC

NC

NC

NC

NC

NC

NC

NC

GF119

AA6

IFPAB_RSET

V7

TP8062

TP8058

A A

TP8061

TP8059

B B

TP8032
TP8065

C C

TP8064

TP8063

TP8030

D D

TP8031

IFPAB_PLLVDD

W7

IFPAB_PLLVDD

W6

IFPA_IOVDD

Y6

IFPB_IOVDD

IFPAB

bga595-nvidia-n13p-gv2-s-a2

U8039H

5/14 IFPC

T6

IFPC_RSET

M7

IFPC_PLLVDD

N7

IFPC_PLLVDD

P6

IFPC_IOVDD

bga595-nvidia-n13p-gv2-s-a2

U8039I

6/14 IFPD

GF119

U6

IFPD_RSET

T7

IFPD_PLLVDD

R7

IFPD_PLLVDD

IFPD

R6

IFPD_IOVDD

1

GF119

NC

2

GF117

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC

DVI/HDMI DP

I2CW_SDA

NC

I2CW_SCL

NC

NC
NC

NC
NC

NC
NC

NC
NC

NC

GF117

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC

2

GF119

IFPA_TXC
IFPA_TXC

IFPA_TXD0
IFPA_TXD0

IFPA_TXD1
IFPA_TXD1

IFPA_TXD2
IFPA_TXD2

IFPA_TXD3
IFPA_TXD3

IFPB_TXC
IFPB_TXC

IFPB_TXD4
IFPB_TXD4

IFPB_TXD5
IFPB_TXD5

IFPB_TXD6
IFPB_TXD6

IFPB_TXD7
IFPB_TXD7

TXC
TXC

TXD0
TXD0

TXD1
TXD1

TXD2
TXD2

I2CX_SDA
I2CX_SCL

GPIO14

COMMON

TXC
TXC

TXD0
TXD0

TXD1
TXD1

TXD2
TXD2

3

U8039J

7/14 IFPEF

AC4
AC3

Y3

TP8033

Y4

AA2

TP8066

AA3

AA1
AB1

AA5
AA4

AB4
AB5

AB2
AB3

TP8068

AD2
AD3

TP8067

AD1
AE1

AD5
AD4

B3

J7

K7

K6

H6

J6

GF119

IFPEF_PLLVDD

IFPEF_PLLVDD

IFPEF_RSET

GF119

IFPE_IOVDD

IFPF_IOVDD

IFPE

IFPF

IFPC

GF119GF117

bga595-nvidia-n13p-gv2-s-a2

N5

IFPC_AUX

N4

IFPC_AUX

N3

IFPC_L3
IFPC_L3

IFPC_L2
IFPC_L2

IFPC_L1
IFPC_L1

IFPC_L0
IFPC_L0

GPIO15

COMMON

+1.8_GFX_MAIN

N2

R3
R2

R1
T1

T3

+1.8_GFX_MAIN

T2

+1.03_GFX

C3

+1.03_GFX

L8012 N17@HCB1005KF-181T15(180,1500MA)
L8008 N16@HCB1005KF-181T15(180,1500MA)

GF117

NC

GF117

NC

NC

NC
NC

NC

NC
NC

NC

NC
NC

NC
NC

GF117

NC

GF117

NC

NC
NC

NC
NC

NC
NC

NC
NC

NC
NC

NC

PLLVDD = 38mA

L8011 N17@BLM15PX330SN1D_4

L8009 N16@BLM15PX330SN1D_4

C8438 EV@0.1U/16V_4

C8439 EV@22u/6.3V_6

SP_PLLVDD = 17mA

C8429 EV@0.1U/16V_4

C8420 EV@0.1 U/16V_4
C8423 EV@4.7 U/10V_6

C8422 EV@22u/6.3V_6

VID_PLLVDD = 41mA

R8683 EV@10K/F_4

GF119

DPDVI/HDMI

P4

IFPD_AUX

P3

IFPD_AUX

R5

IFPD_L3

R4

IFPD_L3

T5

IFPD_L2

T4

IFPD_L2

U4

IFPD_L1

U3

IFPD_L1

V4

IFPD_L0

V3

IFPD_L0

D4

GPIO17

COMMONbga595-nvidia-n13p-gv2-s-a2

HWPG_1.35VGFX[39]

3

4

DVI-DL

I2CY_SDA
I2CY_SCL

TXC
TXC

TXD0
TXD0

TXD1
TXD1

TXD2
TXD2

HPD_ENC

DVI-DL

TXD3
TXD3

TXD4
TXD4

TXD5
TXD5

27M_XTAL_IN_R 27M_XTAL_OUT

R11316 N17@0_4

R8226 N16@4.7K_4

4

GF119

DVI-SL/HDMI

I2CY_SDA
I2CY_SCL

TXC
TXC

TXD0
TXD0

TXD1
TXD1

TXD2
TXD2

HPD_E

GF119

DVI-SL/HDMI

I2CZ_SDA
I2CZ_SCL

TXC
TXC

TXD0
TXD0

TXD1
TXD1

TXD2
TXD2

HPD_F

NV_PLLVDD

SP_PLLVDD

R25

N17@0_6

XTAL_SSIN

DGPU_POK2

C8334
*N16@1000P/50V_4

L6

M6

N6

A10

C11

2

1 3

DP

IFPE_AUX
IFPE_AUX

IFPE_L3
IFPE_L3

IFPE_L2
IFPE_L2

IFPE_L1
IFPE_L1

IFPE_L0
IFPE_L0

GPIO18

DP

IFPF_AUX
IFPF_AUX

IFPF_L3
IFPF_L3

IFPF_L2
IFPF_L2

IFPF_L1
IFPF_L1

IFPF_L0
IFPF_L0

GPIO19

COMMON

U8039M

9/14 XTAL_PLL

PLLVDD
SP_PLLVDD

VID_PLLVDD

XTALSSIN

XTALIN

bga595-nvidia-n13p-gv2-s-a2

DGPU_PGOK-1

Q8014
N16@METR3904-G

5

J3
J2

J1
K1

K3
K2

M3
M2

M1
N1

C2

H4
H3

J5
J4

K5
K4

L4
L3

M5
M4

TP8060

TP8056

GC6 Power control

+3V_MAIN_EN[17,38,40]

F7

R8223 N16@4.7K_4

+3V_MAIN

GF119

NC

GF117

XTALOUTBUFF

+3V_GFX

+3V

5

R8255
N16@4.7K_4

C8377
N16@1000P/50V_4

2

R8241
N16@4.7K_4

3

Q8028

N16@PJA138K

1

U8039K

W5

AE2

AF2

bga595-nvidia-n13p-gv2-s-a2

+1V8_AON

R8414

N17@10K_4

C8328
*1000p/50V_4

XTALOUT

COMMON

R8235
N16@100K/F_4

3/14 DACA

GF119

DACA_VDD

DACA_VREF

DACA_RSET

+3V_GFX

C10

B10

6

GF117

TSEN_VREF

R8413

N16@10K_4

2

2

Q8013

1 3

N16@MMBT3904-7-F

BXTALOUT

DGPU_PWROK [4,14]

6

GF117

NC

NC

NC
NC

NC
NC

NC

NC

NC

3V MAIN POWER

R8409
N16@10K_4

R8402 N16@100K_4

3

Q8027

N16@PJA138K

1

+3V

R8220
N16@4.7K_4

C8327
N16@1000p/50V_4

R8678 EV@10K/F_4

7

GF119

I2CA_SCL
I2CA_SDA

DACA_HSYNC

DACA_VSYNC

DACA_RED

DACA_GREEN

DACA_BLUE

COMMON

B7
A7

AE3
AE4

AG3

AF4

AF3

I2CA_SCL
I2CA_SDA

+1V8_AON

R90022 N17@0_4

R8670 EV@1.8K_4
R8669 EV@1.8K_4

8

16

R90021

N16@0_4

+3V_GFX+3V_GFX

C8505

1

N16@0.022U/25V_4

2

Q8026

N16@AO3413

C8504

3

+3V_MAIN

N16@0.022U/25V_4

1A-7

+3V_GFX

R8204
EV@1.5K/F_4

2

Q8011

1 3

N16@DTC144EU

3V_MAIN_PWGD

R8203
*100K/F_4

3V_MAIN_PWGD [38,40]

+1.05V_GFX and GPU core power EN

DB-->SI change 10/25
Use G-CLK

C8730

41

2 3

Z8VR

Z8VR

Z8VR

EV@10P/50V_4

C8731

EV@10P/50V_4

16 47

16 47

16 47

8

27M_XTAL_IN_R
27M_XTAL_OUT

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Thursday, June 22, 2017

Date: Sheet of

Thursday, June 22, 2017

Date: Sheet of

Thursday, June 22, 2017

7

Y8003

EV@27MHZ +-10PPM

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

N16S-GT (DISPLAY)

N16S-GT (DISPLAY)

N16S-GT (DISPLAY)

2A

2A

2A

1

TP8039
TP8035

THERM-

THERM+

JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST#

PEGX_RST#[14]

VGA_OVT#

R8351

N17@0_4

E12

F12

AE5
AD6
AE6
AF6
AG4

+1V8_AON

+3V_GFX+1V8_AON

R8350

N16@0_4

R8642 N16@40.2K/F_4

R8642 N17-->NC.
N16-->ADD

U8039N

8/14 MISC1

THERMDN

THERMDP

JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TRST

bga595-nvidia-n13p-gv2-s-a2

2

3

1

Q8025

EV@PJA138K

R11317 N17@0_4

GPIO12_ACIN

R8335EV@10K/F_4

R8659EV@10K/F_4

R8355EV@100K/F_4

R8643EV@10K/F_4

R8658EV@10K/F_4

R8660EV@10K/F_4

R8661*10K/F_4

R8568*10K/F_4

R8569*10K/F_4

R8573EV@10K/F_4

R8574*10K/F_4

R8662EV@10K/F_4

A A

TP8037

TP8034

TP8053
TP8052
TP8055
TP8054

B B

C C

2

U8039L

10/14 MISC2

E10

VMON_IN0

F10

VMON_IN1

D1

STRAP0

STRAP0

D2

STRAP1

STRAP1

E4

STRAP2

STRAP2

E3

STRAP3

STRAP3

D3

STRAP4

STRAP4

GF119

C1

STRAP5

STRAP5_NC

F6

MULTISTRAP_REF0_GND

GF119

F4

MULTISTRAP_REF1_GND

F5

MULTISTRAP_REF2_GND

bga595-nvidia-n13p-gv2-s-a2 COMMON

I2CS_SCL
I2CS_SDA

I2CC_SCL

I2CC_SDA

GF119

GF117

I2CB_SCL

NC

I2CB_SDA

NC

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
OVERT

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13

GF117

GF119

GPIO16

NC

GPIO20

NC

GPIO21

NC

COMMON

DGPU_OTP# [28]

+3V_GFX

GPIO12 AC detect
AC high
DC low

R11318

dGPU_OPP# = EC control

N16@0_4

2

3

1

EV@PJA138K

GPIO12_ACIN

DGPU_PSI

VGA_OVT#

GPU_PEX_RST_HOLD#

GPU_EVENT#

GPIO10_VREF

JTAG_TRST#

GPIO10_VREF

Q8022

JTAG_TMS

JTAG_TDI

JTAG_TCK

DGPU_OPP# [28]

ALERT

GF117

NC

D9
D8

A9
B9

C9
C8

C6
B2
D6
C7
F9
A3
A4
B6
A6
F8
C5
E7
D7
B4

D5
E6
C4

GPUT_CLK_L
GPUT_DATA_L

DGPU_EDIDCLK
DGPU_EDIDDATA

N12E_SCL
N12E_SDA

R8283 N16@@0_4

R8285 N17@0_4
N17_GC6

R8287 N17@0_4

ALERT

GPIO10_VREF

GPIO12_ACIN

GPU_GPIO16

GPU_PEX_RST_HOLD#

GF117

NC

NC

R8682 EV@2.2K_4
R8679 EV@2.2K_4

R8676 EV@2.2K_4
R8675 EV@2.2K_4

R90025 N16@0_4

FB_CLAMP_MON
PWM-VID

R8286 N17@0_4

GPU_EVENT#

R90024 N17@0_4
R90023 N16@0_4

R8288 N16@0_4

R8289 N17@0_4

R8291 EV@0_4

R8284 N16@0_4

R8290 N16@0_4

GPIO ASSIGNMENTS

3

ROM_CS

ROM_SI
ROM_SO

ROM_SCLK

BUFRST

PGOOD

CEC

+1V8_AON

+3V_MAIN_EN
+3V_MAIN_EN

DGPU_PSI

GPIO10_VREF [18]

TP8069

GPU_PEX_RST_HOLD# [14]

D12

B12
A12
C12

D11

D10

E9

R90027

N17@0_4

EV@10K_4

2

VGA_OVT#

PWM-VID [38]

DGPU_PSI [38,39]

ROM_CS

ROM_SI
ROM_SO
ROM_SCLK

R8337 N16@10K/F_4

SYS_PEX_RST_MON#

+3V

R45

3

Q8030
EV@PJA138K

1

+3V_MAIN_EN [16,38, 40]

R8353 *10K/F_4

+3V_GFX

3

Q8031
EV@PJA138K

2

level shift circuit for N17

1

GPU_EVENT#

option N17 or N16

R11311 N17@0_4

+1V8_AON

2ND_MBDATA[7, 28]

2ND_MBCLK[7,28]

4

+3V_GFX

SYS_PEX_RST_MON# [14]

suggest to use backdrive diode

R11312

N16@0_4

2ND_MBDATA GPUT_DATA_L

GPIO I/O PIN USAGE

FB_CLAMP_MON

IN

0

GC6_FB_EN

OUT

0

+3V_MAIN_EN

OUT

5

FB_CLAMP_REQ#

OUT

6

DGPU_EVENT#

IN

6

VGA_OVT#

OUT

8

ALERT

9

OUT

PWR_VID

11

OUT

PWR_LEVEL

12

IN

OUT

PSI

13

N16S-GT VRAM Configuration Table ROM_SI

RAMCFG

DESCRIPTION 1.35V DDR5

[3:0]

256Mx32

DDR5 256Mx32, 64bit, 8Gb,2500MHz

0000 0x0

DDR5 256Mx32, 64bit, 8Gb,3000MHz

0001 0x1

DDR5 256Mx32, 64bit, 8Gb,2500MHz

0001 0x1 DDR5 256Mx32, 64bit, 8Gb,3000MHz

0101 0x5

DDR5 256Mx32, 64bit, 8Gb,2500MHz

0101 0x5 H5GC8H24MJR-R0C

DDR5 256Mx32, 64bit, 8Gb,3000MHz

N17S-G1-A1 VRAM Configuration Table STRAP0 , STRAP1 , STRAP2

RAMCFG

DESCRIPTION 1.35V DDR5

[3:0]

0000 0x0

0001 0x1

0010 0x2

256Mx32

DDR5 256Mx32, 64bit, 8Gb,3000MHz

DDR5 256Mx32, 64bit, 8Gb,3000MHz

DDR5 256Mx32, 64bit, 8Gb,3000MHz

FB Clamp monitor (GC6 1.0)

GC6 FB Enable (GC6 2.0)

Enable GC6 +3V_MAIN

Active low FB Clamp toggle request (GC6 1.0)

DGPU EVENT from CPU (GC6 2.0)

ACTIVE LOW THERMAL OVER TEMP

ACTIVE LOW THERMAL ALERT

GPU CORE_VDD PWM Control signal

AC Power detect or power supply overdraw input

Phase Shedding

Vendor Vendor P/N ROM_SI STN B/S

SAMSUNG B-die

SAMSUNG B-die

Micron A-die

Micron A-die MT51J256M32HF-70:A AKG5QGUTL15

HYNIX M-die

HYNIX M-die

Vendor Vendor P/N

SAMSUNG B-die

Micron A-die

HYNIX M-die

N16S-GT/ N16V-GM Straping table

R8709
NV@100K/F_4

ROM_SI
ROM_SO
ROM_SCLK

R8708
NV@100K/F_4

Dual

For GC6 2.0

GC6_FB_EN [4,15]

+3V

change power from +3V-GFX to +3V

R8264
*10K/F_4

D4015EV@RB500V-40

N16S (GC2.0) -> GPIO0 un-stuff Q14 and R129
GPIO6 un-stuff Q15 \ R99 and R125

+3V_GFX

N16S (GC1.0) -> GPIO0 stuff Q14 and R129, un-stuff R120 \ R128
GPIO6 stuff Q15 and R125, un-stuff R107,R106.

EV@SSM6N43FU

5

43

R8371 N17@2.2K_4
R8396 N16@2.2K_4

Dual

621

Q8024

R8360 N16@2.2K_4
R8370 N17@2.2K_4

K4G80325FB-HC03

K4G80325FB-HC280000 0x0

MT51J256M32HF-60:A

H5GC8H24MJR-T2C

K4G80325FB-HC28

H5GC8H24MJR-R0C

5

R8712
NV@100K/F_4

1 2

R8711
NV@100K/F_4

1 2

R8247 EV@0_4

GPUT_CLK_L2ND_MBCLK

N16S-GT/ N16V-GM Straping table

ROM_SI N16S-GT [ 940M ]
2G Hynix 128Mx16 -->34.8K PD
2G Micron 128Mx16 -->45.3K PD
2G Samsumg 128Mx16 -->4.99K PU
4G Hynix 256Mx16 -->30.1K PU Single Rank
4G Hynix 256Mx16 -->24.9K PU Dual Rank
4G Micron 256Mx16 -->10K PD
4G Samsumg 256Mx16 -->15K PD

ROM_SO
N16S-GT --> 4.99K PD

ROM_SCLK
N16S-GT --> 4.99K PD

STRAP0
N16S-GT --> 49.9K PU

+3V_MAIN

+1V8_AON

R8349

R8336

N17@0_4

N16@0_4

R8706
NV@100K/F_4

1 2

1 2

R8705
NV@100K/F_4

1 2

1 2

For GC6 1.0

DGPU_EVENT# [4]

For GC6 2.0

+1V8_AON
+3V_GFX
+3V_GFX
+1V8_AON

STRAP0

AKG5QGDT502

AKG5QGDT518

AKG5LGUTL04

AKG5QFUTW04

AKG5QGUTW06

STRAP1 STRAP2

PD 100K ohm PD 100K ohmPU 100K ohm

PD 4.99K ohm

PD 4.99K ohm

PD 10K ohm

PD 10K ohm

PD 30.1K ohm

PD 30.1K ohm

PD 100K ohm PD 100K ohm PD 100K ohm

PD 100K ohm

6

N16S-GT 940M

R8649
NV@100K/F_4

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
STRAP5

R8650
NV@100K/F_4

R8649 ---> 49.9K pull up

R8647
NV@100K/F_4

1 2

R8648
NV@100K/F_4

1 2

1 2

1 2

R8655
NV@100K/F_4

R8656
NV@100K/F_4

+1V8_AON

R8334

N17@0_4

R8645
NV@100K/F_4

1 2

R8646
NV@100K/F_4

1 2

7

+3V_GFX

R8327

N16@0_4

R11314

R8652

*N17@100K/F_4

1 2

1 2

NV@100K/F_4

R8653
NV@100K/F_4

1 2

1 2

R11315
N17@100K/F_4

1 2

1 2

for N17 strap5 ( N16 unstuff )Defual Samsung VRAM (STRAP 0,1,2 ---> low)

N16S-GT DID=0x1347 [940M]

ROM_SCLK = Stuff 4.99K pull down
ROM_SO = Stuff 4.99K pull down
STRAP0 = Stuff 49.9K pull up
STRAP1 = NC
STRAP2 = NC
STRAP3 = NC
STRAP4 = NC
ROM_SI = VRAM Configuration follow below table

N17S-G1-A1 DID=0x1D10 [1040]

ROM_SI = Stuff 100K pull up
ROM_SO = Stuff 100K pull up
ROM_SCLK = Stuff 100K pull up and Stuff 100K pull down
STRAP0 = VRAM Configuration follow below table
STRAP1 = VRAM Configuration follow below table
STRAP2 = VRAM Configuration follow below table
STRAP3 = Stuff 100K pull down
STRAP4 = Stuff 100K pull down
STRAP5 = Stuff 100K pull down

Note: GC6 2.0 is supported by N16x GPU in the GB2B
,GB4B-128,and GB3B-256 packages.

Logical Strap Bit Mapping

Resistor P/N

4.99K---> CS24992FB26
10K ---> CS31002FB26
15K ---> CS31502FB24
20K ---> CS32002FB29

24.9K --->CS32492FB16

30.1K --->CS33012FB18

34.8K---> CS33482FB22

45.3K ---> CS34532FB18

49.9K ---> CS34992FB10

N16S-GTR-S-A2 PN : AJ0N16S0T44

N17S-G1-A1 PN : AJ0N17S0T00

4.99K
10K
15K
20K

24.9K

30.1K

34.8K

45.3K

PU-VDD PD

1000 0000
1001 0001

1011 0011
1100
1101
1110 0110
1111

STN B/S

AKG5QGDT518

PD 100K ohmPU 100K ohm

AKG5QGUTL15MT51J256M32HF-70:A

AKG5QGUTW06

8

17

00101010

0100
0101

0111

D D

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

Z8VR

PROJECT :

Z8VR

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

N16S-GT (GPIO/STRAPS)

N16S-GT (GPIO/STRAPS)

N16S-GT (GPIO/STRAPS)

Date: Sheet of

Thursday, June 22, 2017

Date: Sheet of

Thursday, June 22, 2017

Date: Sheet of

1

2

3

4

5

6

7

Thursday, June 22, 2017

Z8VR

8

17 47

17 47

17 47

2A

2A

2A

1

VMA_DQ[63..0][15]

VMA_DQ[63..0]

2

3

4

5

6

7

8

CHANNEL A: 1024MB GDDR5x32

VMA_DQ31
VMA_DQ30
VMA_DQ29
VMA_DQ28
VMA_DQ27
VMA_DQ26
VMA_DQ25
VMA_DQ24
VMA_DQ23
VMA_DQ22
VMA_DQ21
VMA_DQ20
VMA_DQ19
VMA_DQ18
VMA_DQ17
VMA_DQ16
VMA_DQ15
VMA_DQ14
VMA_DQ13
VMA_DQ12
VMA_DQ11
VMA_DQ10
VMA_DQ9
VMA_DQ8
VMA_DQ7
VMA_DQ6
VMA_DQ5
VMA_DQ4
VMA_DQ3
VMA_DQ2
VMA_DQ1
VMA_DQ0

SEN_A

Channel A
<0-31>

U8045

M2

DQ31 | DQ7

M4

DQ30 | DQ6

N2

DQ29 | DQ5

N4

DQ28 | DQ4

T2

DQ27 | DQ3

T4

DQ26 | DQ2

U2

DQ25 | DQ1

U4

DQ24 | DQ0

M13

DQ23 | DQ15

M11

DQ22 | DQ14

N13

DQ21 | DQ13

N11

DQ20 | DQ12

T13

DQ19 | DQ11

T11

DQ18 | DQ10

U13

DQ17 | DQ9

U11

DQ16 | DQ8

F13

DQ15 | DQ23

F11

DQ14 | DQ22

E13

DQ13 | DQ21

E11

DQ12 | DQ20

B13

DQ11 | DQ19

B11

DQ10 | DQ18

A13

DQ9 | DQ17

A11

DQ8 | DQ16

F2

DQ7 | DQ31

F4

DQ6 | DQ30

E2

DQ5 | DQ29

E4

DQ4 | DQ28

B2

DQ3 | DQ27

B4

DQ2 | DQ26

A2

DQ1 | DQ25

A4

DQ0 | DQ24

J5

RFU/A12/NC

K4

A7/A8 | A0/A10

K5

A6/A11 | A1/A9

K10

A5/BA1 | A3/BA3

K11

A4/BA2 | A2/BA0

H10

A3/BA3 | A5/BA1

H11

A2 /BA0 | A4/BA2

H5

A1/A9 | A6/A11

H4

A0/A10 | A7/A8

D4

WCK01 | WCK23

D5

WCK01# | WCK23#

P4

WCK23 | WCK01

P5

WCK23# | WCK01#

R2

EDC3 | EDC0

R13

EDC2 | EDC1

C13

EDC1 | EDC2

C2

EDC0 | EDC3

P2

DBI3# | DBI0#

P13

DBI2 #| DBI1#

D13

DBI1# | DBI2#

D2

DBI0# | DBI3#

G3

RAS# | CAS#

L3

CAS# | RAS#

J3

CKE#

J11

CK#

J12

CK

G12

CS# | WE#

L12

WE# | CS#

J13

ZQ

J10

SEN

J2

RESET#

J1

MF

A5

Vpp,NC

U5

Vpp,NC1

A10

VREFD1

U10

VREFD2

J14

VREFC

J4

ABI#

EV_A@GDDR5

VDDQ-B1

VDDQ-B3
VDDQ-B12
VDDQ-B14

VDDQ-D1

VDDQ-D3
VDDQ-D12
VDDQ-D14

VDDQ-E5
VDDQ-E10

VDDQ-F1

VDDQ-F3
VDDQ-F12
VDDQ-F14

VDDQ-G2
VDDQ-G13

VDDQ-H3
VDDQ-H12

VDDQ-K3
VDDQ-K12

VDDQ-L2
VDDQ-L13

VDDQ-M1

VDDQ-M3

VDDQ-M12
VDDQ-M14

VDDQ-N5
VDDQ-N10

VDDQ-P1

VDDQ-P3
VDDQ-P12
VDDQ-P14

VDDQ-T1

VDDQ-T3
VDDQ-T12
VDDQ-T14

VDD-C5
VDD-C10
VDD-D11

VDD-G1

VDD-G4
VDD-G11
VDD-G14

VDD-L1

VDD-L4

VDD-L11
VDD-L14
VDD-P11

VDD-R5
VDD-R10

VSSQ-A1

VSSQ-A3
VSSQ-A12
VSSQ-A14

VSSQ-C1
VSSQ-C3

VSSQ-C4
VSSQ-C11
VSSQ-C12
VSSQ-C14

VSSQ-E1

VSSQ-E3
VSSQ-E12
VSSQ-E14

VSSQ-F5
VSSQ-F10

VSSQ-H2

VSSQ-H13

VSSQ-K2
VSSQ-K13

VSSQ-M5

VSSQ-M10

VSSQ-N1

VSSQ-N3
VSSQ-N12
VSSQ-N14

VSSQ-R1

VSSQ-R3

VSSQ-R4
VSSQ-R11
VSSQ-R12
VSSQ-R14

VSSQ-V1

VSSQ-V3
VSSQ-V12
VSSQ-V14

VSS-B5
VSS-B10
VSS-D10

VSS-G5

VSS-G10

VSS-H1

VSS-H14

VSS-K1
VSS-K14

VSS-L5

VSS-L10

VSS-P10

VSS-T5
VSS-T10

U8045

+1.35V_GFX

B1
B3
B12
B14
D1
D3
D12
D14
E5
E10
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
P12
P14
T1
T3
T12
T14

C5
C10
D11
G1
G4
G11
G14
L1
L4
L11
L14
P11
R5
R10

A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
U1
U3
U12
U14

B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10

DQA32~39

DQA40~47

DQA48~55

DQA56~63

FBA_CMD25[15]
FBA_CMD26[15]
FBA_CMD27[15]
FBA_CMD17[15]
FBA_CMD18[15]
FBA_CMD20[15]
FBA_CMD19[15]
FBA_CMD23[15]
FBA_CMD22[15]

VMA_WCK67[15]
VMA_WCK67#[15]

VMA_WCK45[15]
VMA_WCK45#[15]

FBA_EDC4[15]
FBA_EDC5[15]
FBA_EDC6[15]
FBA_EDC7[15]

FBA_DBI4[15]
FBA_DBI5[15]
FBA_DBI6[15]
FBA_DBI7[15]

FBA_CMD31[15]
FBA_CMD28[15]

FBA_CMD30[15]
VMA_CLK1#[15]
VMA_CLK1[15]

FBA_CMD21[15]
FBA_CMD16[15]

R1510 EV_A@120/F_4

+1.35V_GFX

FBA_CMD29[15]

12

C1551 EV_A@820P/50V_4

FBA_CMD24[15]

VREFC_VMA2VREFC_VMA1

Non-mirror, MF=0 Mirror, MF=1

A A

DQA24~31

DQA16~23

DQA8~15

DQA0~7

FBA_CMD9[15]
FBA_CMD6[15]
FBA_CMD7[15]
FBA_CMD4[15]
FBA_CMD3[15]
FBA_CMD1[15]
FBA_CMD2[15]
FBA_CMD11[15]
FBA_CMD10[15]

B B

C C

VMA_WCK01[15]
VMA_WCK01#[15]

VMA_WCK23[15]
VMA_WCK23#[15]

FBA_EDC3[15]
FBA_EDC2[15]
FBA_EDC1[15]
FBA_EDC0[15]

FBA_DBI3[15]
FBA_DBI2[15]
FBA_DBI1[15]
FBA_DBI0[15]

FBA_CMD12[15]
FBA_CMD15[15]

FBA_CMD14[15]
VMA_CLK0#[15]
VMA_CLK0[15]

FBA_CMD0[15]
FBA_CMD5[15]

R1415 EV_A@120/F_4
R1438 EV_A@1K_4

FBA_CMD13[15]

12

C1432 EV_A@820P/50V_4

FBA_CMD8[15]

KB OnlyA

VMA_DQ39
VMA_DQ38
VMA_DQ37
VMA_DQ36
VMA_DQ35
VMA_DQ34
VMA_DQ33
VMA_DQ32
VMA_DQ47
VMA_DQ46
VMA_DQ45
VMA_DQ44
VMA_DQ43
VMA_DQ42
VMA_DQ41
VMA_DQ40
VMA_DQ55
VMA_DQ54
VMA_DQ53
VMA_DQ52
VMA_DQ51
VMA_DQ50
VMA_DQ49
VMA_DQ48
VMA_DQ63
VMA_DQ62
VMA_DQ61
VMA_DQ60
VMA_DQ59
VMA_DQ58
VMA_DQ57
VMA_DQ56

SEN_A

M2
M4
N2
N4
T2
T4
U2

U4
M13
M11

N13
N11
T13
T11
U13
U11
F13
F11
E13
E11
B13
B11
A13
A11

F2

F4

E2

E4

B2

B4

A2

A4

J5
K4
K5

K10
K11
H10
H11

H5
H4

D4
D5

P4
P5

R2

R13
C13

C2

P2

P13
D13

D2

G3

L3

J3

J11
J12

G12

L12

J13
J10

J2

J1

A5
U5

A10
U10

J14

J4

Channel A
<32-63>

U8043

DQ31 | DQ7

VDDQ-B1

DQ30 | DQ6

VDDQ-B3

DQ29 | DQ5

VDDQ-B12

DQ28 | DQ4

VDDQ-B14

DQ27 | DQ3

VDDQ-D1

DQ26 | DQ2

VDDQ-D3

DQ25 | DQ1

VDDQ-D12

DQ24 | DQ0

VDDQ-D14

DQ23 | DQ15

VDDQ-E5

DQ22 | DQ14

VDDQ-E10

DQ21 | DQ13

VDDQ-F1
VDDQ-F3

DQ20 | DQ12
DQ19 | DQ11

VDDQ-F12

DQ18 | DQ10

VDDQ-F14

DQ17 | DQ9

VDDQ-G2

DQ16 | DQ8

VDDQ-G13

DQ15 | DQ23

VDDQ-H3

DQ14 | DQ22

VDDQ-H12

DQ13 | DQ21

VDDQ-K3

DQ12 | DQ20

VDDQ-K12

DQ11 | DQ19

VDDQ-L2

DQ10 | DQ18

VDDQ-L13

DQ9 | DQ17

VDDQ-M1

DQ8 | DQ16

VDDQ-M3

DQ7 | DQ31

VDDQ-M12

DQ6 | DQ30

VDDQ-M14

DQ5 | DQ29

VDDQ-N5

DQ4 | DQ28

VDDQ-N10

DQ3 | DQ27

VDDQ-P1

DQ2 | DQ26

VDDQ-P3

DQ1 | DQ25

VDDQ-P12

DQ0 | DQ24

VDDQ-P14

VDDQ-T1

VDDQ-T3
VDDQ-T12
VDDQ-T14

RFU/A12/NC
A7/A8 | A0/A10
A6/A11 | A1/A9
A5/BA1 | A3/BA3
A4/BA2 | A2/BA0
A3/BA3 | A5/BA1
A2 /BA0 | A4/BA2
A1/A9 | A6/A11
A0/A10 | A7/A8

WCK01 | WCK23
WCK01# | WCK23#

WCK23 | WCK01
WCK23# | WCK01#

EDC3 | EDC0
EDC2 | EDC1
EDC1 | EDC2
EDC0 | EDC3

DBI3# | DBI0#
DBI2 #| DBI1#
DBI1# | DBI2#
DBI0# | DBI3#

RAS# | CAS#
CAS# | RAS#

CKE#
CK#
CK

CS# | WE#
WE# | CS#

ZQ
SEN

RESET#
MF

Vpp,NC
Vpp,NC1

VREFD1
VREFD2

VREFC

ABI#

EV_A@GDDR5

VDD-C5
VDD-C10
VDD-D11

VDD-G1

VDD-G4
VDD-G11
VDD-G14

VDD-L1

VDD-L4

VDD-L11
VDD-L14

VDD-P11

VDD-R5
VDD-R10

VSSQ-A1
VSSQ-A3

VSSQ-A12
VSSQ-A14

VSSQ-C1
VSSQ-C3
VSSQ-C4

VSSQ-C11
VSSQ-C12
VSSQ-C14

VSSQ-E1
VSSQ-E3

VSSQ-E12
VSSQ-E14

VSSQ-F5

VSSQ-F10

VSSQ-H2

VSSQ-H13

VSSQ-K2

VSSQ-K13

VSSQ-M5

VSSQ-M10

VSSQ-N1
VSSQ-N3

VSSQ-N12
VSSQ-N14

VSSQ-R1
VSSQ-R3
VSSQ-R4

VSSQ-R11
VSSQ-R12
VSSQ-R14

VSSQ-V1
VSSQ-V3

VSSQ-V12
VSSQ-V14

VSS-B5

VSS-B10
VSS-D10

VSS-G5
VSS-G10

VSS-H1

VSS-H14

VSS-K1

VSS-K14

VSS-L5
VSS-L10
VSS-P10

VSS-T5
VSS-T10

U8043

+1.35V_GFX

B1
B3
B12
B14
D1
D3
D12
D14
E5
E10
F1
F3
F12
F14
G2
G13
H3
H12
K3
K12
L2
L13
M1
M3
M12
M14
N5
N10
P1
P3
P12
P14
T1
T3
T12
T14

C5
C10
D11
G1
G4
G11
G14
L1
L4
L11
L14
P11
R5
R10

A1
A3
A12
A14
C1
C3
C4
C11
C12
C14
E1
E3
E12
E14
F5
F10
H2
H13
K2
K13
M5
M10
N1
N3
N12
N14
R1
R3
R4
R11
R12
R14
U1
U3
U12
U14

B5
B10
D10
G5
G10
H1
H14
K1
K14
L5
L10
P10
T5
T10

VMA_CLK0

R1426
EV_A@80.6/F_4

VMA_CLK0#

D D

+1.35V_GFX

VMA_CLK1

R1500
EV_A@80.6/F_4

VMA_CLK1#

+

1 2

C73 EV@330u_2.5V_3528

C1399 EV_A@10U/6.3V_6

201201117 Add C764 for EMI suggestion.

1

+1.35V_GFX +1.35V_GFX

R1417

EV_A@549/F_4

R1416

EV_A@1.33K/F_4 R1508

+1.35V_GFX

2

VREF_VMA1_MOSVREFC_VMA1 VREF_VMA1_MOSVREFC_VMA2

12

R1410 EV_A@931/F_4

Pleasement need close to U5

C4788 EV_A@10U/6.3V_6

C1538 EV_A@1u/6.3V_4
C1498 EV_A@1u/6.3V_4
C1549 EV_A@1u/6.3V_4

EV_A@0.1u/16V_4C1764
EV_A@0.1u/16V_4C1413
EV_A@0.1u/16V_4C1396
EV_A@0.1u/16V_4C1499
EV_A@0.1u/16V_4C1440
EV_A@0.1u/16V_4C8804

EV_A@549/F_4

EV_A@1.33K/F_4

+1.35V_GFX

3

R1509

R1513 EV_A@931/F_4

C1448 EV_A@1u/6.3V_4C1394 EV_A@1u/6.3V_4
C1401 EV_A@1u/6.3V_4
C1398 EV_A@1u/6.3V_4
C1543 EV_A@1u/6.3V_4

EV_A@0.1u/16V_4C1391
EV_A@0.1u/16V_4C1377
EV_A@0.1u/16V_4C1497
EV_A@0.1u/16V_4C1386
EV_A@0.1u/16V_4C1435
EV_A@0.1u/16V_4C1537

12

4

VREF_VMA1_MOS

3

Q129

2

1

R1467 EV_A@10K_4
R1473 EV_A@10K_4

R1466 EV_A@10K_4
R1472 EV_A@10K_4

GPIO10_VREF [17]

+1.35V_GFX

5

EV_A@PJA138K

FBA_CMD14
FBA_CMD30

CKE* is strap pin to set ODT value of memory chip

FBA_CMD13
FBA_CMD29

RST PD place @ the end of daisy-chain.

GDDR5 Mode H Mapping

< 0-31 > < 32-63 > Memory

CMD0 CMD16 CS*
CMD1 CMD17 A3_BA3
CMD2 CMD18 A2_BA0
CMD3 CMD19 A4_BA2
CMD4 CMD20 A5_BA1
CMD5 CMD21 WE*
CMD6 CMD22 A7_A8
CMD7 CMD23 A6_A11
CMD8 CMD24 ABI*
CMD9 CMD25 A12_RFU
CMD10 CMD26 A0_A10
CMD11 CMD27 A1_A9
CMD12 CMD28 RAS*
CMD13 CMD29 RST*
CMD14 CMD30 CKE*
CMD15 CMD31 CAS*

6

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

Z8VR

PROJECT :

Z8VR

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

N16x - 6/6 (GDDR5x32)

N16x - 6/6 (GDDR5x32)

N16x - 6/6 (GDDR5x32)

Date: Sheet of

Thursday, June 22, 2017

Date: Sheet of

Thursday, June 22, 2017

Date: Sheet of

Thursday, June 22, 2017

7

Z8VR

18 47

18 47

18 47

8

3A

3A

3A

5

4

3

2

1

19

DP TO VGA

D D

Power

+3V +3V

L7

60ohm@100MHz_6

VDD_DAC_33

CRT_HPD

AUX_CH_N

AUX_CH_P

LANE0_P

LANE0_N

LANE1_P

LANE1_N

L8

60ohm@100MHz_6

CPU

C C

CRT_AUXN[2]

CRT_AUXP[2]

CRT_TXP0[2]

CRT_TXN0[2]

CRT_TXP1[2]

CRT_TXN1[2]

B B

AVCC33

CRT_HPD[2]

C137 0.1U/16V_4

C135 0.1U/16V_4

C104 0.1U/16V_4

C97 0.1U/16V_4

C82 0.1U/16V_4

C77 0.1U/16V_4

CLK_SDATA[7,11,12,26]
CLK_SCLK[7,11,12,26]

C141

0.1U/16V_4

AVCC33

AUX_CH_P

AUX_CH_N

VCCK_V12

LANE0_P

LANE0_N

LANE1_P

LANE1_N

R95 *0_4
R94 *0_4

1

2

3

4

5

6

7

8

+3V

CRT_HPD

32

33

U5

HPD

EPAD

AVCC_33

AUX_P

AUX_N

AVCC_12

RTD2166

LANE0_P

LANE0_N

LANE1_P

LANE1_N

POL29POL1/SPI_CEB10SPI_CLK11SPI_SI12SPI_SO13VCC_3314VGA_SCL15VGA_SDA

R73

+3V

4.7K_4

R693 *4.7K_4

R694 4.7K_4

31

EXT1.2V_CTRL

R74

4.7K_4

VGA

C150

0.1U/16V_4

+3V

27

LDO_RSTB

+3V

25

PVCC_3326VCCK_12

GREEN_P

VDD_DAC_33

HVSYNC_PWR

16

DDCCLK

DDCDAT

VCCK_V12

GND

RED_P

BLUE_P

HSYNC

VSYNC

24

23

22

21

20

19

18

17

0.1U/16V_4

CRT_RED

CRT_GRE

CRT_BLU

VDD_DAC_33

HSYNC

VSYNC

C555

C559

0.1U/16V_4

+5V

C546

4.7U/6.3V_6

C156

2.2U/6.3V_6

0.1U/16V_4

C565

DDCDAT

DDCCLK

HSYNC

VSYNC

CRT_RED

CRT_GRE

CRT_BLU

DDCDAT [20]

DDCCLK [20]

HSYNC [20]

VSYNC [20]

CRT_RED [20]

CRT_GRE [20]

CRT_BLU [20]

CIIC_SDA

CIIC_SCL

30

29XI28

SMB_SCL

SMB_SDA

TP7

Note:

1- C1,C3,C4,C5,C11,C16, C21 should be placed close to chip

2- C5 shold be X5R material

3- R6, R7, R8 should be 75 ohm with +/-1%

4- Suggest to connect Pin 29 and Pin 30 to PCH SMBUS for debug purpose.

5- This configuration is for internal ROM mode and using embedded LDO mode.

A A

+3V[2,4,6,7,8,9,11,12,14,15,16,17,20,21,22,23,24,25,26,27,28,30,31,33,34,37,38,39,40]
+5V[20,21,23,24,26,30,37]

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sh eet of

Date: Sh eet of

5

4

3

2

Date: Sh eet of

PROJECT :

DP to VGA iT6165

DP to VGA iT6165

DP to VGA iT6165

Z8VR

Z8VR

Z8VR

1A

1A

19 46Thursday, June 22, 2017

19 46Thursday, June 22, 2017

19 46Thursday, June 22, 2017

1

1A

5

CRT

RTD2166 integrate 5V HSYNC/VSYNC buffer inside IC

HSYNC[19]

D D

VSYNC[19]

12/24 Delete R449

HSYNC

12/24 Delete R396

VSYNC

R458 *0_4

R392 *0_4

U30

1

OE#

VCC

2

A

3

GND

*M74VHC1GT125DF2G

Co-Layout

U26

1

OE#

VCC

2

A

3

GND

*M74VHC1GT125DF2G

12/18 Change R412 to 47ohm for vendor requset

R412 47/F_4

5

4

R421 *33_4

Y

12/18 Change R399 to 47ohm for vendor requset

R399 47/F_4

5

4

R406 *33_4

Y

Realtek FAE suggest close to connector

+5V

CRTHSYNC

+5V

CRTVSYNC

C562

0.1u/16V_4

C533

0.1u/16V_4

4

CRT_RED[19]

CRT_GRE[19]

CRT_BLU[ 19]

R91

U28

Line-1

Line-2

GND#1

Line-3

Line-45NC#1

AZ1045-04F.R7G

NC#4

NC#3

NC#2

75/F_4

10

9

7

6

DDCCLK

Close to RTD2166 IC

1

CRTHSYNC CRTHSYNC

2

3

4

CRTVSYNC CRTVSYNC

DDCCLK

3

OUT

GND

C88

5.6p/16V_4

NC#4

NC#3

NC#2

CRTVDD5

1
2

10

CRT_G1

9

7

CRT_B1CRT_B1

6

C95

*5.6p/16V_4

C70 *0.1u/16V_4

CRTVDD5

CRT_R1

CRT_G1

CRT_B1

C128

C148

*5.6p/16V_4

*5.6p/16V_4

C67 *0.22u/6.3V_4

C68 *220p/50V_4

C69 0.1u/16V_4

*33P/50V_4

C539

*33P/50V_4

C551

C532 1000p/50V_4

C571 1000p/50V_4

Realtek FAE suggest close to connector

12/18 Un-Stuff C539/C551 for vendor requset

Q8

3

+5V

IN

AP2331SA-7

12/18 Change to BLM15BB220SN1D (CX5BB220005)
for vendor request

L4 BLM15BB220SN1D_4

L3 BLM15BB220SN1D_4

L2 BLM15BB220SN1D_4

C143

R77

R85

75/F_4

75/F_4

CRTVDD5CRTVDD5

C112

5.6p/16V_4

5.6p/16V_4

12/18 Un-Stuff C95/C128/C148 for vendor requset

U6

CRT_R1 CRT_R1

1

Line-1

CRT_G1

2

Line-2

3

GND#1

4

DDCDAT DDCDAT

Line-3

Line-45NC#1

AZ1045-04F.R7G

2

CN5

1617

12/21 Change CN5 footprint to "dsub-95-0005-01-15p" for layout requset

6

7
2
8
3
9
4

10

5

CRTVDD5

CRTVSYNC

CRTHSYNC

DDCCLK

DDCDAT

111

12

13

14

15

CRT CONN

CRT_11

DDCDAT

CRTHSYNC

CRTVSYNC

DDCCLK

TP61

DDCDAT [19]

DDCCLK [19]

Power trace tracking

DDCDAT
DDCCLK

R4432.2K_4
R3982.2K_4

1

20

CRTVDD5

+3V[2,4,6,7,8,9,11,12,14,15,16, 17,19,21,22,23,24,25,26,27,28,30,31,33,34,37, 38,39,40]
+5V[19,21,23,24,26,30,37]

+3VPCU[6,9,22,23,24,25,26,28,29,30,37, 40]

VIN[23,24,29,30,31,33,34,35,36,37,38, 39]

VIN

ESD

C C

EDP_AUX_C

R373 *100K_4
R374 *100K_4

2013/12/12 change eDP pin define
colayout FHD Panel for A2 stage

Prevent ESD/EOS Layout near device

EDP_HPD[ 2]

EDP_AUX#_C

TP_RST#

R371 *100K_4

R23 *TSI@10K_4

R18 33_4

C4
180P/50V_4

eDP FHD

B B

Touch Panel-I2C

Touch Panel-USB

eDP 4k*2k

R1 *0_4

1C1-2 2014/03/11 Add R698 for TS_EN short TP_INT,

for issue debug.

A A

Touch Panel interrupt

TP_INT_PCH[4]

S5 S0

R2 *TSI@0_4

5

C8814
C8813
100p/50V_4

I2C1_SCL_C

USBP5+[6]
USBP5-[6]

TS_EN[28]

3

Q1
*TSI@2N7002K

+3V

2

C21

0.1u/16V_4

4.7u/25V_8

+3V VIN

PCH_BRIGHT[2]

EDP_AUXP[2]
EDP_AUXN[2]

EDP_TXP1[2]
EDP_TXN1[2]

EDP_TXP0[2]
EDP_TXN0[2]

R10 *TSI@0_4
R9 *TSI@0_4

USBP5+

R8 TSU@0_4

USBP5-

R7 TSU@0_4

EDP_TXP2[2]
EDP_TXN2[2]

EDP_TXP3[2]
EDP_TXN3[2]

Board_ID4[8]

S5

TP_INTTS_EN

R3
*TSI@10K_4

TP_INT

1

C19

1000p/50V_4

1A-5

TP_PWR +3V

LCDVCC

R24 0_8

+3V

+5V
+3V

EDP_AUXP

C508 0.1U/16V_4

EDP_AUXN

C509 0.1U/16V_4

EDP_TXP1

C504 0.1U/16V_4

EDP_TXN1

C503 0.1U/16V_4

EDP_TXP0

C500 0.1U/16V_4

EDP_TXN0

C499 0.1U/16V_4

CCD-USB

EDP_TXP2

C497 0.1U/16V_4

EDP_TXN2

C496 0.1U/16V_4

EDP_TXP3

C495 0.1U/16V_4

EDP_TXN3

C494 0.1U/16V_4

R353 33_4

C492
180P/50V_4

Prevent ESD/EOS Layout near device

C507

C8

0.1u/16V_4
1000p/50V_4

MAX 1.5A

C17

*1u/6.3V_4

C1642 *22U/6.3V_6

R22 0_6
R21 *0_4

PCH_BRIGHT

EDP_HPD_R

USBP6+[6]

USBP6-[6]

TS_EN TS_EN_R

BOARD_ID4_TOUCH_S

Hall Sensor (HSR)

4

C10

0.1u/16V_4_X7R

R26 0_8
R27 0_8

C16

LCDVCC_R

R362 0_4
R359 0_4

R356 0_4

*1u/6.3V_4

D4
*VPORT_6

EDP_AUX_C
EDP_AUX#_C

EDP_TXP1_C
EDP_TXN1_C

EDP_TXP0_C
EDP_TXN0_C

EDP_TXP2_C
EDP_TXN2_C

EDP_TXP3_C
EDP_TXN3_C

C11

1000p/50V_4

V_BLIGHT

TP_PWR
TP_RST#

BL_ON

USBP6+_R
USBP6-_RI2C1_SDA_C

TP_INT

+3VPCU

R678 *100K_4

21

1

C396

4.7U/6.3V_6

1st:AL009249000 -- BCD
2nd:AL009132001 -- ANC

CN2

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

3

MR1
AH9249NTR-G1

G_5

G_4

G_1

G_0

2

50398-04071-001

21

3

LID#

D31
*VPORT_6

LCD PowerLCD CONNECTOR

C20

1u/6.3V_4

EDP_VDD_EN[2]

R30 0_4

Touch screen level shift I2C(reserve)

S5

I2C1_SDA[4]
I2C1_SCL[ 4]

PCH_BLON[2]

PCH_BLON_R[28]

EDP_VDD_EN_R

+3V

*TSI@DMN601DWK-7

R43 0_4

R42 0_4

2

+3V

U2

6

IN

4

IN

3

ON/OFF

G5245AT11U

R31

100K_4R372 *100K_4

R13 *TSI@0_4

Q2

6

1

2

43

5

R12 *TSI@0_4

10K_4

PCH_BLON_C

R44

100K_4

Q6

DMN601DWK-7

1B-3 2013/12/10 change Q3.3 from +3V to +3VPCU.

I2C1_SDA_C

I2C1_SCL_C

R28

5

4 3

1

OUT

2

GND

5

GND

+3V

R6

R16

*TSI@10K_4

*TSI@10K_4

+3V

R20

10K_4

BL#

6

2

1

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

C7

C12

*0.1u/16V_4

*2.2u/50V_8

1st : AL005245000---GMT

2nd : AL007553000---UPI

S0

TPD->100kHz,TS=400Khz
Intel design guide suggestion
MCP PIN 10u.
Per inch 3u TS=3x5inch
400kHz10~100u =2.4~0.4k.
100Khz 10~100u=9k~1k.

+3VPCU

R11
*100K_4

LID#

LID591#,EC intrnal PU

D1
1N4148WS

BL_ON

2

Q4
DTC144EUA

1 3

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

CRT/LVDS/CAMERA/L ID

CRT/LVDS/CAMERA/L ID

CRT/LVDS/CAMERA/L ID

1

C6

0.1u/16V_4

LCDVCC

C9

0.01u/50V_4

LID# [28]

EC_FPBACK# [28]

Z8VR

Z8VR

Z8VR

20 46Thursday, June 22, 2017

20 46Thursday, June 22, 2017

20 46Thursday, June 22, 2017

LCDVCC

C18

22u/6.3V_8

1A

1A

1A

5

HDMI

D D

C C

B B

A A

<HDM>

HDMI-detect

S5 input high

INT_HDMI_HPD[2]

From PCH

HDMI_5V

HDMI_DDCDATA_SW[2]

HDMI_DDCCLK_SW[2]

INT_HDMITX0P[2]
INT_HDMITX0N[2]
INT_HDMITX1P[2]
INT_HDMITX1N[2]
INT_HDMITX2P[2]
INT_HDMITX2N[2]
INT_HDMICLK+[2]
INT_HDMICLK-[2]

+3V+3V

R274

2

*1M_4

1

R251 2.2K_4

+3V

R252 2.2K_4

D8 RB500V-40

2 1

D7 RB500V-40

2 1

R285 0_4

3

Q27
*2N7002K

HDMI_DDCCLK_SW

HDMI_DDCDATA_SW

R283 2.2K_4

R284 2.2K_4

Power trace tracking

+3V[2,4,6,7,8,9,11,12,14, 15,16,17,19,20,22,23,24,25,26,27,28,30, 31,33,34,37,38,39,40]
+5V[19,20,23,24,26,30,37]

5

HDMI_DDCDATA_SW
HDMI_DDCCLK_SW

INT_HDMITX1P
INT_HDMITX1N
INT_HDMITX2P
INT_HDMITX2N
INT_HDMICLK+
INT_HDMICLK-

S0

HDMI_MB_HPD_R

HDMI_DDCCLK_MB

D52 *AZ5725-01F.R7G

HDMI_DDCDATA_MB

D51 *AZ5725-01F.R7G

4

C397 0.1u/16V_4
C394 0.1u/16V_4
C390 0.1u/16V_4
C384 0.1u/16V_4
C376 0.1u/16V_4
C373 0.1u/16V_4
C371 0.1u/16V_4
C370 0.1u/16V_4

12

12

Close connector

4

0.1U/16V_4_X7R

INT_HDMITX0P_C_RINT_HDMITX0P
INT_HDMITX0N_C_RINT_HDMITX0N
INT_HDMITX1P_C_R
INT_HDMITX1N_C_R
INT_HDMITX2P_C_R
INT_HDMITX2N_C_R
INT_HDMICLK+_C_R
INT_HDMICLK-_C_R

C369

0.1U/16V_4

C404

3

HDMI_EQ0 HDMI_EQ1

+3V

C402 0.1U/16V_4_X7R

+3V

HDMI_DDCDATA_MB

HDMI_MB_HPD

24

23

22

21

20

GND

DDC_EN

HPD_SNK

TERM_EN

25

IN_D1-

26

IN_D1+

27

IN_D2-

28

IN_D2+

29

IN_D3-

30

IN_D3+

31

IN_D4-

32

IN_D4+

33

CEN_PAD

VDD1EQ12GND3REXT4HPD_SRC5SDA_SRC6SCL_SRC7EQ0

+3V

HDMI_EQ1

HDMI_MB_HPD_R

R253 12.4K/F_4

U15

19

18

17

PTN3366BS

VDD

OE_N

SCL_SNK

SDA_SNK

HDMI_DDCCLK_SW

HDMI_DDCDATA_SW HDMI_DDCCLK_MB

8

HDMI_EQ0

3

OUT_D1-

OUT_D1+

OUT_D2-

OUT_D2+

OUT_D3-

OUT_D3+

OUT_D4-

OUT_D4+

16
15
14
13
12
11
10
9

37

GND

36

GND

35

GND

34

GND

+5V

DDS AL002331000

3

IN

AP2331SA-7

C403

0.1U/16V_4_X7R

Q26

1

OUT

2

GND

C351
*220p/50V_4

INT_HDMITX2P_C

INT_HDMITX1P_C

INT_HDMITX0P_C

INT_HDMICLK+_C

R250 *10K_4

R249 0_4

+3V

0.1U/16V_4_X7R

D54

VARISTOR

EMI

R261 *120/F_4

R264 *120/F_4

R268 *120/F_4

R257 *120/F_4

2

INT_HDMITX0P_C
INT_HDMITX0N_C
INT_HDMITX1P_C
INT_HDMITX1N_C
INT_HDMITX2P_C
INT_HDMITX2N_C
INT_HDMICLK+_C
INT_HDMICLK-_C

C365

0.1U/16V_4_X7R

HDMI_MB_HPD

INT_HDMITX2N_C

INT_HDMITX1N_C

INT_HDMITX0N_C

INT_HDMICLK-_C

2

C364

12

R246
*20K_4

1

+3V+3V

C366

0.1U/16V_4_X7R

0.1U/16V_4_X7R

C405

0.1U/16V_4_X7R

R255 10K_4

R254 *0_4

C367

0.1U/16V_4_X7R

HDMI connector

INT_HDMITX2P_C

INT_HDMITX2N_C
INT_HDMITX1P_C

INT_HDMITX1N_C
INT_HDMITX0P_C

INT_HDMITX0N_C
INT_HDMICLK+_C

INT_HDMICLK-_C

HDMI_DDCCLK_MB
HDMI_DDCDATA_MB

HDMI_5V

D53

VARISTOR

INT_HDMITX0P_C

INT_HDMITX0N_C

INT_HDMITX1P_C

INT_HDMITX1N_C

INT_HDMITX2P_C

INT_HDMITX2N_C

INT_HDMICLK+_C

INT_HDMICLK-_C

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

CN10

1

D2+

2

D2 Shield

3

D2-

4

D1+

5

D1 Shield

6

D1-

7

D0+

8

D0 Shield

9

D0-

10

CK+

11

CK Shield

12

CK-

13

CE Remote

14

NC

15

DDC CLK

16

DDC DATA

17

GND

18

+5V

19

HP DET

HDMI connector

ESD7

1

Line-1

2

Line-2

3

GND#1

4

Line-3

Line-45NC#1

AZ1045-04F.R7G

ESD6

1

Line-1

2

Line-2

3

GND#1

4

Line-3

Line-45NC#1

AZ1045-04F.R7G

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

HDMI (PS8407 4k*2k)

HDMI (PS8407 4k*2k)

HDMI (PS8407 4k*2k)

SHELL1

SHELL2

NC#4

NC#3

NC#2

NC#4

NC#3

NC#2

GND

GND

1

20

23

22

21

INT_HDMITX0P_C

10

INT_HDMITX0N_C

9

INT_HDMITX1P_C

7

INT_HDMITX1N_C

6

INT_HDMITX2P_C

10

INT_HDMITX2N_C

9

INT_HDMICLK+_C

7

INT_HDMICLK-_C

6

21

Z8VR

Z8VR

Z8VR

21 46T hursday, June 22, 2017

21 46T hursday, June 22, 2017

21 46T hursday, June 22, 2017

C406

1A

1A

1A

5

4

3

2

1

Giga LAN (LAN)

LANVCC

XTAL2

C324 12p/50V_4

1

2

Y1

25MHZ +-30PPM

4

D D

VDD10

VDD10

C C

MDI_0+
MDI_0-

MDI_1+
MDI_1­MDI_2+
MDI_2-

VDD10

R196 2.49K/F_4

LANVCC

U7

33

GND

1

MDIP0

2

MDIN0

3

AVDD10

4

MDIP1

5

MDIN1

6

MDIP2(NC)

7

MDIN2(NC)

8

AVDD10

MDI_3+
MDI_3-

LANVCC

RSET

10 mils

32

RTL8111H-CG

31

30

RSET

AVDD33

10

XTAL1

28

AVDD10

CKXTAL229CKXTAL1

HSIP13HSIN14REFCLK_P15REFCLK_N

CLKREQB

AVDD3311MDIP3(NC)9MDIN3(NC)

12

27

3

C306 12p/50V_4

26

LED0

LED225LED1

REGOUT
VDDREG

DVDD10

LANWAKEB

ISOLATEB

PERSTB

16

PCIE_REQ_LAN#_R

HSON
HSOP

TP22
TP19
TP20

24
23
22

PCIE_LAN_WAKE#_R

21
20

ISOLATEB

19

PERSTB

18
17

CLK_PCIE_LANN [6]
CLK_PCIE_LANP [6]

PCIE_TX5-_LAN [6]
PCIE_TX5+_LAN [6]

BG625000081 -> TXC(1st)

BG625000085 -> HHE(2nd)

REGOUT
LANVCC
VDD10

PCIE_RX5-_LAN_C
PCIE_RX5+_LAN_C

R128 NAC@0_4
R131 IOAC@0_4
C226 180P/50V_4

C257 0.1u/16V_4
C258 0.1u/16V_4

Consider VCC33 may be connected to Main
Power or chipset/bios's GPO, the pull-low
resistor R14 can be NC only when Main Power
or chipset/bios's GPO can ensure to drive the
ISOLATEB pin to a voltage lev el < 0.8V at the
system state S3~S5.
If the ISOLATEB pin can not be well-controlled to
a voltage level < 0.8V at S3~S5, the pull-low
resistor R14 is needed to make sure the LAN
chip is well isolated.

PLTRST# [8,14,24,25,28]
IOAC_RST# [25,28]

PCIE_RX5-_LAN [6]
PCIE_RX5+_LAN [6]

For RTL8111H
Place 0.1uF,4.7uF CAP close to each VDD33 pin-- 11, 32

RTL8111H (LDO mode)

REGOUT

+3V

R146
1K_4

R147
*15K_4

40 mils (Iout=1A)

C328

0.1u/16V_4

C337

0.1u/16V_4

C339

4.7U/6.3V_6

C332

4.7U/6.3V_6

close to each VDD10 pin-- 3, 8, 22, 30

40 mils (Iout=1A) 40 mils (Iout=1A)

R136 0_8

C268

0.1u/16V_4

C335

0.1u/16V_4

C338

0.1u/16V_4

C611

0.1u/16V_4

C333

0.1u/16V_4

close to each VDD10 pin-- 22
(reserve)

C612
*1U/6.3V_4

VDD10

22

C613
*0.1u/16V_4

Leakage circuit (MPC)

+3V

CLK_PCIE_REQ4 # have PU 10k.

B B

S0

CLK_PCIE_LAN_REQ#[6]

R168
*10K/F_4

3

Q19

2N7002K

R177 *0/J_4

EC_PCU LANVCC

Q13 IOAC@AO3413

1

2

R112 NAC@0_4

R111 IOAC@0_4

+3V_LAN

3

R118

IOAC@0_8

C185

*IOAC@1000p/50V_4

PCIE_LAN_WAKE#[8,25]

IOAC_LAN_WAKE#[28]

Reserve IOAC No Stuff

+3VPCU

A A

*IOAC@0.1U/16V_4

LANPWR#[28]

C206

5

R124
*IOAC@100K/J_4

R108
IOAC@10K_4

+3V

+3V

2

1

2

3

Q12
IOAC@2N7002K

R130 NAC@0/J_4

C234
10u/6.3V_6

R178
10K/F_4

MAIN POWER(3V_S0)

PCIE_REQ_LAN#_R

LANVCC

FAE suggest to
change to 1K

R129
IOAC@1K_4

PCIE_LAN_WAKE#_R

1

C272

C253

0.1u/16V_4

*0.1u/16V_4

4

LANVCC

+3V_S5

R105 NAC@0_8 C342

C323
*0.1u/16V_4

Tramsformer

U11

1

TCT1

2

TD1+

3

TD1-

4

TCT2

5

TD2+

6

TD2-

7

TCT3

8

TD3+

9

TD3-

10

TCT4

11

TD4+

12

TD4-

C346

0.01U/50V/X7R_4

MDI_3+
MDI_3-

MDI_2+
MDI_2-

MDI_1+
MDI_1-

MDI_0+
MDI_0-

4/20 REV:D add TP85 ~TP100 for AZ chip ICT/ATE Capacitor test

3

24

MCT1

23

MX1+

22

MX1-

21

MCT2

20

MX2+

19

MX2-

18

MCT3

17

MX3+

16

MX3-

15

MCT4

14

MX4+

13

MX4-

GND

TRANSFORMER

25

12/16 Change P/N to CS07504FA11
RES CHIP 75 1/8W +-1%(0805)

Layout:All termination
signal should have 30
mil trace

LAN_MCT0
LAN_MX3+
LAN_MX3-

LAN_MCT1
LAN_MX2+
LAN_MX2-

LAN_MCT2
LAN_MX1+
LAN_MX1-

LAN_MCT3
LAN_MX0+
LAN_MX0-

RJ45 Connector

CN9

LAN_MX0+
LAN_MX0­LAN_MX1+
LAN_MX2+
LAN_MX2­LAN_MX1­LAN_MX3+
LAN_MX3-

R217 75/F_8

R221 75/F_8

R215 75/F_8

R224 75/F_8

TERM9

1000P/3KV_1808

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

LAN(RTL8111H)

LAN(RTL8111H)

LAN(RTL8111H)

Thursday, June 22, 2017

Thursday, June 22, 2017

Thursday, June 22, 2017

1

0+

2

0-

3

1+

4

2+

5

2-

6

1-

7

3+

8

3-

RJ45

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

1

Z8VR

Z8VR

Z8VR

9

9

10

10

11

11

12

12

1A

1A

1A

4622

4622

4622

5

Codec(ADO)

D D

+1.5VA

C704

10u/6.3V_4

ADOGND

Place next to pin 40

Analog

Digital

C C

B B

L12

PVDD

PBY160808T-600Y-N(60,3A)

Close to codec

Tied at one point only under
the codec or near the codec

R660 *0_4 C686
R661 *0_4
R665 *0_4
R655 *0_4
R326 *0_4 C679 *22p/50V_4
R331 0_4
C728 *1000p/50V_4

C727 *0.1u/16V _4

ADOGND

Cap need near AVDD1
and AVDD2
power source input

C706

0.1u/16V_4

Change to 1U from Realtek's suggestion

ADOGND

C707 10u/6.3V_4

+5V_PVDD

C697

C698

10u/6.3V_4

0.1u/16V_4

Low is power down
amplifier output

C691

C692

10u/6.3V_4

TP83

0.1u/16V_4

R630 0_6

+3V

DMIC_DAT_L

DMIC_CLK_L

Close to codec

L_SPK+

L_SPK-

R_SPK-

R_SPK+

PD#

C676

0.1u/16V_4

C71210u/6.3V_4

C7161U/6.3V_4

+AZA_VDD

35

36

CPVDD

37

CBP

38

AVSS2

39

LDO2-CAP

40

AVDD2

41

PVDD1

42

SPK-L+

43

SPK-L-

44

SPK-R-

45

SPK-R+

46

PVDD2

47

PDB

48

SPDIF-OUT

49

DGND

DVDD1GPIO0/DMIC-DATA2GPIO1/DMIC-CLK3DVSS4SDATA-OUT5BIT-CLK6LDO3-CAP7SDATA-IN8DVDD-IO9SYNC10RESETB11PCBEEP

+AZA_VDD

DMIC_DAT

C685
10u/6.3V_4

R639 0_4

C674
10p/50V_4

Codec PWR 5V(ADO)

+5V

C732

A A

*0.1u/16V_4

C672

*10u/6.3V_6

5

ANALOG DIGITAL

L14 HCB2012KF220T60/6A/22ohm_8

C718

*10u/6.3V_6

CBN

C7201U/6.3V_4

34

CPVEE

DMIC_CLK

ADOGND

33

DC-DET

+5VA

4

31

32

HP-OUT-L

HP-OUT-R

LINE1-VREFO-L

ALC255

R323 0_4

C722

*0.1u/16V_4

4

HP-R2

HP-L2

LINE1-VREFO-L

LINE1-VREFO-R

MIC2-VREFO

CODEC_VREF

INT_AMIC-VREFO

25

26

27

28

29

30

VREF

AVDD1

LDO1-CAP

MIC2-VREFO

LINE1-VREFO-R

MIC2-R/SLEEVE

MIC2-L/RING2

MONO-OUT

SPDIFO/FRONT JD

MIC2/LIN2 JD

HP/LINE1 JD

ACZ_SDIN

12

R314 33_4

C455 10u/6.3V_4

Mute(ADO)

Internal Speaker

Rev:D change to shortpad

Close to codec

C719 2.2U/6.3V_4

C715 10u/6.3V_4

R657 100K_4

ADOGND

ADOGND

C710

0.1u/16V_4

+5VA

C709

10u/6.3V_4

Place next to pin 26

U37

AVSS1

24

LINE2-L

23

LINE2-R

22

LINE1-L

LINE1-L

21

LINE1-R

LINE1-R

20

R324 0_6

NC

analog digital

19

MIC-CAP

18

SLEEVE

17

RING2

16

15

14

13

SENSEA

1.6Vrms

C688 0.1u/16V_4

PCBEEP

+AZA_VDD +1.5V

PD#

R635
1K_4

R640
*10K/J_4

C678
100p/50V_4

40mil for each signal

R_SPK+

R688 0_6

R_SPK-

R687 0_6

L_SPK-

R686 0_6

L_SPK+

R685 0_6

ADOGND

+3VPCU

C472 10u/6.3V_4

trace width of SLEEVE & RING2
are required at least 40mil and
its length should be asshort as possible

Placement near Audio Codec

R643 200K_4

R644 100K_4

BEEP_1

PCH_AZ_CODEC_RST# [4]

PCH_AZ_CODEC_SYNC [4]

PCH_AZ_CODEC_SDIN0 [4]

PCH_AZ_CODEC_BITCLK [4]

PCH_AZ_CODEC_SDOUT [4]

C690
*1u/10V_4

Change 47K to 22K for PCBEEP

R627 22K_4

R632

10K_4

DVDD_IO

D28 *RB500V-40

D29 RB500V-40

4 ohm : 40mil for each signal

1003 change 0603type

C743

C744

1000p/50V_4

1000p/50V_4

ADOGND

HP_JD#

Change to 10K from Realtek's suggestion

3

Close to codec

+3V

Analog

Digital

D21 1N4148WS

D20 1N4148WS

CPU 3.3V

R631 0_4

R628 *0_4R638 22_4

C677

10u/6.3V_4

0.1u/16V_4

Place next to pin 9

2

3

C742

1000p/50V_4

3

PCH_AZ_CODEC_RST#

1

Q44

*PJA138K

AMP_MUTE# [28]

R_SPK+_1
R_SPK-_1
L_SPK-_1
L_SPK+_1

C741

1000p/50V_4

1B-2 2013/12/04 Change PN and footprint.

1B-5 2013/12/17 Change CN14 pin define

SPKR [4]

PCBEEP_EC [28]

+3V +1.5V

SPK_CONN_4P

1
2
345

CN18

DC-DET circuit(ADO)

D-Mic (MIC)

+3V

C344 10u/6.3V_4
C345 0.1u/16V_4
C343 10p/50V_4

U10

1

2

5
6

KMM40301026-18DS

VDD

CLK

LR

DATA

GND

GND

GND

GND

Single DMIC

DUAL MAIN

3

DMIC_DAT_L1

4

7
8

Left Right

Universal Audio Jack

MIC2-VREFO

SLEEVE

RING2

HP-L2

HP-R2

LINE1-L

LINE1-VREFO-L

LINE1-VREFO-R

LINE1-R

Codec PWR 1.5V(ADO)

6

2

R218 0_4

R586 0_4

R646 2.2K/J_4

R645 2.2K/J_4

C711 4.7U/6.3V_6

R654 4.7K_4

R656 4.7K_4

C705 4.7U/6.3V_6

+1.5V

2

Rev:D change to shortpad

+5V

VIN

DC-DET

R629 *0_4

+5V

R634
*100K_4

2

Q42
*DTC144EU

1 3

R624
*1M_6

C671
*10u/6.3V_4

Single DMIC and Dual DIMC same PN: AL403010A00

Far away rubber

DMIC_CLK_L

DMIC_DAT_L

C347*10p/50V_4

+3V

C340 *10u/6.3V_4
C179 *0.1u/16V_4
C181 *10p/50V_4

D2TVS/6pF_4

12

C648*10p/50V_4

12

D26TVS/6pF_4

Place very closed

DMIC_CLK_L2

R220 *0_4

DMIC_DAT_L2

R219 *0_4

HEADPHONE/MIC/LINE combo (ADO)

SLEEVE/RING2 trace > 40mils
HP/LINE trace > 10mils
L/R spacing > 10mils

R420& R422 change to 62 ohm -> 3/11

R663 62/F_4

R664 62/F_4

R649

1U/6.3V_4

C708

R653

*10K/J_4

*10K/J_4

ADOGND

ANALOG DIGITAL

L13 HCB1608KF-121T30_3A

C723

100p/50V_4

+1.5VA

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

R626 0_6

3

2

U9

1

VDD

2

LR

DATA

5

GND

6

GND

*KMM40301026-18DS

DUAL SECOND

C729

100p/50V_4

ALC255/HP/SPK

ALC255/HP/SPK

ALC255/HP/SPK

Thursday, June 22, 2017

Thursday, June 22, 2017

Thursday, June 22, 2017

1

1

PVDD

Q43
*AO3404

DMIC_CLK_L3DMIC_CLK_L1

3

CLK

GND
GND

C733

100p/50V_4

R578 *0_4

DMIC_DAT_L3

4

R554 *0_4

7
8

DMIC_CLK_L2

DMIC_DAT_L2

HP-L3

HP-R3

HP_JD#

C734

100p/50V_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

1

23

DMIC_CLK_L2

DMIC_DAT_L2

12

C645*10p/50V_4

Z8VR

Z8VR

Z8VR

D16*TVS/6pF_4

SLEEVE [27]

RING2 [27]

HP-L3 [27]

HP-R3 [27]

HP_JD# [27]

12

D15*TVS/6pF_4

C640*10p/50V_4

1A

1A

1A

4623

4623

4623

5

4

3

2

1

SATA HDD

CN11

24

26

23

25

22
21
20
19
18

D D

17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

MAIN_SATA_CONN

ODD Power (SATA)

C C

Reserve IOAC Power No Stuff

CLKRUN#[7,28]

PLTRST#[8,14,22,25,28]

C673

CLKRUN#

TPM@33P/50V_4

R141 IOAC@0_4

R152 *IOAC@0_4

AL009655K01

AL000650K01

ODD_POWER[28]

PCH_ODD_EN[2]

TPM NPCT650 (TPM)

B B

AL000650K01 :NPCT650AAAWX

TPMM 1.2

TPMM 2.0

3/4 EMI request add 33p near TPM IC

A A

20120921 change Cn10 Pin define following Z09.

DEVSLP0_R

120mil

C669

C670

+

10u/6.3V_6

*100u/6.3V_3528

SATA_RXP0_C
SATA_RXN0_C

SATA_TXN0_C
SATA_TXP0_C

R167
IOAC@100K

ODD_EN

12

5

R133
*IOAC@100K

LPC_LAD3[7,25,28]
LPC_LAD2[7,25,28]
LPC_LAD1[7,25,28]
LPC_LAD0[7,25,28]

LPC_LFRAME#[7,25,28]

IRQ_SERIRQ[7,28]

5

PCLK_TPM[7]

R633 0_4
R636 0_4

LPCPD

R648 *TPM@4.7K_4

CLKRUN#
PLTRST#

R637 *0_4

+5V_HDD

C689

C680

*0.1u/16V_4

*0.1u/16V_4

R310 *0_4

C681 0.01u/50V_4
C682 0.01u/50V_4

C683 0.01u/50V_4
C684 0.01u/50V_4

+3VPCU

VIN

12

ODD_EN_Q

6

2

1

4 3

SP@ BOM
A,B,C P/N:AL009655K01(SLB9655TT1.2- FW4.31)
RAMP P/N: AL000650K01 (NPCT650AAAWX)

+3V_S5

R647 0_6

LPC_LAD3
LPC_LAD2
LPC_LAD1
LPC_LAD0
LPC_LFRAME#
IRQ_SERIRQ
PCLK_TPM

TPM_CLKRUN#
TPM_LRESET#

LPCPD

+3V3_TPM

+5V

6
5
2
1

R110

12

IOAC@100K

IOAC@DMN601DWK-7
Q15

周邊上

NPCT650

+3V3_TPM

TPM@10u/6.3V_6C699
TPM@0.1u/16V_4C696
TPM@0.1u/16V_4C695
TPM@0.1u/16V_4C687

U36

15

LAD3

18

LAD2/SPI_IRQ

21

LAD1/MOSI

24

LAD0/MISO

20

LFRAME/SCS

27

SERIRQ

19

LCLK/SCLK

13

CLKRUN/GPIO04

17

LRESET/SPI_RST

28

LPCPD

26

NC7

31

NC8

Q14
IOAC@AO6402A

C675

0.01u/50V_4

3

MOD_EN_5V

12

C189
IOAC@0.1u/25V_6

+3V3_TPM_VSB

22

8

14

VDD3

VDD1

VDD2

GND19GND323GND4

B.M.

16

33

DEVSLP0 [6]

R625 0_8

ACCEL_INT2 [26]

SATA_RXP0 [6]
SATA_RXN0 [6]

SATA_TXN0 [6]
SATA_TXP0 [6]

4

ODD_EN_Q

R662 0_6

1

VSB

GPX/GPIO2

GPIO1

GPIO0/XOR_OUT

GPIO3/BADD

TEST

NC1
NC2
NC3
NC4
NC5
NC6

GND2

TPM@NPCT620/650_QFN32

32

4

2

Q17

IOAC@2N7002K

TPM@10u/6.3V_6C721
TPM@0.1u/16V_4C700

4

PP

3
30

29
6
5

2
7
10
11
12
25

+5V

+5V_ODD

Connect to G-sensor INT2

+5V

R121 NAC@0_8

R139
IOAC@22_8

3

1

+3V_S5

TPM_PP
GPX

TPM_BADD

TP84
TP85
TP87

TP86

R642 *TPM@10K_4

BADD SELECTION

01EEh - EFh

7Eh - 7Fh

'1' - pin is left open.
'0' - pin is pulled down.

CN7

14

GND14

1

GND1

2

RXP

3

RXN

4

GND2

5

TXN

6

TXP

7

GND3

8

DP

9

+5V

10

+5V

11

MD

12

GND

13

GND

15

GND15

6030D-13G20

POA(FPD)

+3V_LDO_EC

+3VPCU

+3V

USBP3+
USBP3-

+3VPCU

R650 *FPD@0_4

HOLE23
MBZ8V001010

1

HOLE7
*H-TC315IC186BC146D146PT

1

3

SATA_TXP1_C
SATA_TXN1_C

SATA_RXN1_C
SATA_RXP1_C

ODD_PRSNT#_C

R859 *FPD@0_4

R860 FPD@0_4

R865 *FPD@0_4

SSD_ID [6]

C584

0.01u/50V_4

R97 10K_4

C622 0.01u/50V_4
C616 0.01u/50V_4

C610 0.01u/50V_4
C606 0.01u/50V_4

+POA_PWR

POA_FP_PWREN#[28]

R101 10K_4

C178 *15p/50V_4

C586

C583

0.01u/50V_4

*0.1u/16V_4

EC_ODD_EJ# [28]

+3V

Can not change to shortpad in ramp stage

Co-Layout

USBP3+_R3
USBP3-_R3

R1531*FPD@0_4
R1532*FPD@0_4

R651 *FPD@10_4

MAINON[28,30,33,37]

C703

*FPD@0.1U/16V/X7R_4

HOLE2

*HG-C354D118P2

8
9

123

USBP3+_U
USBP3-_U

USBP3+[6]
USBP3-[6]

C702

*FPD@0.01u/50V_4

R1526 FPD@0_4
R1527 FPD@0_4

12/30 Delete Hole3 & Hole22 for DXF

HOLE11
*H-TC315IC186BC146D146PT

1

HOLE6
*H-TC315IC186BC146D146PT

1

SSD NUT

HOLE15
MBZAA001010

1

HOLE1
*h-c197d197n

HOLE16
MBZAA001010

1

HOLE14

HOLE17

*H-C118D118N

*H-O118X157D118X157N

1

1

12/30 Modify Hole1、Hole14、Hole17 to NC

SATA_TXP1 [6]
SATA_TXN1 [6]

SATA_RXN1 [6]
SATA_RXP1 [6]

R102 33_4

Prevent ESD/EOS Layout near device

+3V

+5VODD

C585

C601

*0.1u/16V_4

10u/6.3V_6

R652 FPD@10K/J_4

C927

*FPD@1000p/50V_4

R1528 FPD@0_4
R1529 FPD@0_4

1
2
3
9

HOLE13

*HG-Z8V-1

67

8

5

9

4

HOLE20
MBZAA001010

1

123

1

C182 180P/50V_4

R483 0_8

+

C588

*100u/6.3V_3528

1A-8

+POA_PWR

1

2

3

20mil 20mil

C731

FPD@4.7u/6.3V_6

USBP3+_R
USBP3-_R

U39

Y+
Y­GND
VCC
SEL10OE#

*FPD@PI3USB102

HOLE10
*H-TC315IC186BC146D146PT

67
5
4

1

HOLE21

*HG-Z8V-3

8
9

123

4

M-

5

M+

6

D-

7

D+

8

67
5
4

2

ODD_PRSNT# [4]

+5V_ODD

C726 *FPD@2.2u/16V_6

Q45
FPD@AO3413

*FPD@0_4

+3V_POA

C724

FPD@0.01u/50V_4

POA_EN#[28]

POA_PWR_INT#[28]
POA_AUTH_ERR[28]
POA_POWERREQ[28]

USBP3-_R2
USBP3+_R2

R659 *FPD@0_4

HOLE18

*HG-TC315BC236D118P2

8
9

123

HOLE8

*HG-Z8V-C2

8
9

123

R1530

R666 FPD@0_4

TP88
TP89

R1534*FPD@0_4
R1533*FPD@0_4

HOLE12

*HG-C315D118P2

8
9

123

67
5
4

67
5
4

D49 *FPD@D5V0X1B2LP-7B

USBP3+_R

1 2

D50 *FPD@D5V0X1B2LP-7B

USBP3-_R

1 2

+3V_POA_R

USBP3+_R
USBP3-_R

R1535FPD@0_4
R1536FPD@0_4
R1537FPD@0_4
R1538FPD@0_4

Can not change to shortpad

USBP3-_R
USBP3+_R

CN17

219
3
4
5
6
7
8

FPD@CONN_AOP

SEL OE# Y+ Y-

X Hi-Z Hi-Z

H

Spec define: High Active

HOLE4

67

*H-C315D118P2

5
4

1

SPAD1

SPAD2

*SPAD-C315

*SPAD-C315

1

1

HOLE19

*HG-TC354BC315D118P2

67
5

8

4

9

123

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

HOLE9
EV@MBZRQ001010

1/4 Add for DXF

12/31 Add for D-Shape Hole

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

HDD/ODD/TPM NPCT 650

HDD/ODD/TPM NPCT 650

HDD/ODD/TPM NPCT 650

1

SATA ODD Connector

10

H

L

L

1

HOLE24
*o-z8v-1

For GPU skuWLAN NUT

SPAD4
*pad-z8v-2-np

1

1

M+ M-L

Z8VR

Z8VR

Z8VR

24

HOLE5
EV@MBZRQ001010

1

24 46Thursday, June 22, 2017

24 46Thursday, June 22, 2017

24 46Thursday, June 22, 2017

D-D+

1A

1A

1A

5

NGFF_M.2 WiFi & BT (NGF)

USBP4+

USBP4+[6]

USBP4-

USBP4-[6]

D D

PCIE_TX6+_WLAN[6]
PCIE_TX6-_WLAN[6]

PCIE_RX6+_WLAN[6]
PCIE_RX6-_WLAN[6]

CLK_PCIE_WLANP[6]
CLK_PCIE_WLANN[6]

CLK_PCI_LPC[7]

LPC_LFRAME#[7,24,28]

Reserve only for Intel module no need to stuff by default 11/24

C C

SUSCLK[6]

NGFF_M.2 SSD (NGF)

B B

CLK_PCI_LPC
LPC_LFRAME#

R17 **10K_4

SUSCLK

SATA_RXN1/PEG_RXN10_L2[6]

SATA_RXP1/PEG_RXP10_L2[6]

SATA_TXN1/PEG_TXN10_L2[6]
SATA_TXP1/PEG_TXP10_L2[6]

SATA_RXP3/PEG_RXP9_L0[6]
SATA_RXN3/PEG_RXN9_L0[6]

SATA_TXN3/PEG_TXN9_L0[6]
SATA_TXP3/PEG_TXP9_L0[6]

CLK_PCIE_NGFF1_N[6]
CLK_PCIE_NGFF1_P[6]

PCIE_TX6+_WLAN
PCIE_TX6-_WLAN

PCIE_RX6+_WLAN
PCIE_RX6-_WLAN

CLK_PCIE_WLANP
CLK_PCIE_WLANN

WLAN_CLKREQ#
WLAN_WAKE_R#

R5 0_4
R4 0_4

For Debud Card use

Low

High

U1

NC1VCC

2

A

GND3Y

*74AUP1G07GW

SATA_RXN1/PEG_RXN10_L2
SATA_RXP1/PEG_RXP10_L2

SATA_TXN1/PEG_TXN10_L2
SATA_TXP1/PEG_TXP10_L2

SATA_RXP3/PEG_RXP9_L0
SATA_RXN3/PEG_RXN9_L0

SATA_TXN3/PEG_TXN9_L0
SATA_TXP3/PEG_TXP9_L0

CLK_PCIE_NGFF1_N
CLK_PCIE_NGFF1_P

NGFF3_DET[6]

CLK_PCI_LPC_C
LPC_LFRAME#_C

4

CN3

NGFF

1

GND

3

USB_D+

5

USB_D-

7

GND

9

SDIO CLK(O)

11

SDIO CMDIO)

13

SDIO DAT0(IO)

15

SDIO DAT1(IO)

17

SDIO DAT2(IO)

19

SDIO DAT3(IO)

21

SDIO Wake(I)

23

SDIO Reset

25

KEY1

27

KEY2

29

KEY3

31

KEY4

33

GND

35

PETp0

37

PETn0

39

GND

41

PERp0

43

PERn0

45

GND

47

REFCLKP0

49

REFCLKN0

51

GND

53

CLKREQ0#

55

PEWake0#

57

GND

59

PETp1

61

PETn1

63

GND

65

PERp1

67

PERn1

69

GND

71

Reserved1

73

Reserved2

75

GND

WLAN_NGFF CONN(Type 2230)

Mini card +3V power enable

Mini card +3V power disable

+3V_S5

+WL_VDD

5

12

R19

C5

*10K_4

*0.1u/16V_4

WIFI_SUSCLK

4

R503 0_4
R502 0_4

0.1u/16V_4C630

0.1u/16V_4C629

R497 0_4
R496 0_4

0.1u/16V_4C626

0.1u/16V_4C625

12/17 Add R692 for Sata SSD

NGFF3_DET

3

Q23

2N7002K

1

3

+3VPCU [6,9,20,22,23,24,26,28,29,30,37,40]
+1.5V [9,23,37]
+3V [2,4,6,7,8,9,11,12,14,15,16,17,19,20,21,22,23,24,26,27,28,30,31,33,34,37,38,39,40]

+WL_VDD+WL_VDD

PCM_CLK

PCM_SYNC

PCM_IN

PCM_OUT

UART Wake

UART Rx

UART Tx
UART CTS
UART RTS

Clink RESET

CLink DATA

CLink CLK

SUSCLK(32KHz)

PERST0#

W_DISABLE#2
W_DISABLE#1

NFC I2C SM DATA

NFC I2C SM CLK

NFC I2C IRQ

NFC Reset#
RESERVED3
RESERVED4
RESERVED5

3.3Vaux

3.3Vaux
LED#1

LED#2

COEX3
COEX2
COEX1

3.3Vaux

3.3Vaux

2
4
6
8
10
12
14
16
18

GND

20
22
24

Key 5

26

Key 6

28

Key 7

30

Key 8

32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74

WIFI_SUSCLK

R360 IOAC@0_4

WLAN_RST#

R361 NAC@0_4

BT_EN
RF_EN

LPC_LAD0_C

R358 0_4

LPC_LAD1_C

R357 0_4

LPC_LAD2_C

R355 0_4

LPC_LAD3_C

R354 0_4

+WL_VDD

Rev:D change to shortpad

10u/6.3V_6C493

0.1u/16V_4C2

0.1u/16V_4C14

0.1u/16V_4C15

0.1u/16V_4C1

C498 180P/50V_4

BT_EN [28]
RF_EN [28]

S0

S0

APU Internal PU
APU External nu-PU

WLAN_CLKREQ#

IOAC

WLAN_WAKE_R#

IOAC No Stuff

PLTRST#

LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3

+3V

R15

4.7K/J_4

IOAC_RST# [22,28]
PLTRST# [8,14,22,24,28]

LPC_LAD0 [7,24,28]
LPC_LAD1 [7,24,28]
LPC_LAD2 [7,24,28]
LPC_LAD3 [7,24,28]

12/21 Change CN3 footprint to "ngff-nase0-s6701-ts48-ke-smt " for SMT requset

Q29 IOAC@AO3413

+3V_WLAN

3

R692 *10K_4

R189 1M_4

2

+3VPCU

*IOAC@0.1U/16V_4

WLANPWR#[28]

WLANPWR#

Reserve IOAC No Stuff

Reserver +1.5v for WIFI module

+1.5V+3V_S5

**IOAC@0.1U/16V_4

WLANPWR#

No Stuff

SATA_RXN1/PEG_RXN10_L2_N
SATA_RXP1/PEG_RXP10_L2_N

SATA_TXN1/PEG_TXN10_L2_N
SATA_TXP1/PEG_TXP10_L2_N

SATA_RXP3/PEG_RXP9_L0_N

SATA_RXN3/PEG_RXN9_L0_N

SATA_TXN3/PEG_TXN9_L0_N
SATA_TXP3/PEG_TXP9_L0_N

+3V3_SATA_N1

NGFF3_PEDET

R183

*0_4

C505

C502

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75

R370

IOAC@10K_4

R366

*IOAC@10K_4

CN8

GND
GND
PERn3
PERp3
GND
PETn3
PETp3/NOTCH
GND/NOTCH
PERn2/NOTCH
PERp2/NOTCH
GND/CONFIG_0
PETn2
PETp2
GND
PERn1
PERp1
GND
PETn1
PETp1
GND
PERn0/SATA-B+
PERp0/SATA-B­GND
PETn0/SATA-A­PETp0/SATA-A+
GND
REFCLKn
REFCLKp
GND
NOTCH
NOTCH
NOTCH
NOTCH
NC
PEDET
GND
GND
GND

1

R369

*IOAC@100K/J_4

1

R367

**IOAC@100K/J_4

NGFF

SUSCLK(32KHz)

GND76GND

77

2

C506

*IOAC@1000p/50V_4

Q28 *IOAC@AO3413

+3V_WLAN

3

2

C501

**IOAC@1000p/50V_4

3.3V

3.3V
NC
NC

DAS
NOTCH/3.3V
NOTCH/3.3V
NOTCH/3.3V
NOTCH/3.3V

NC
NC
NC
NC
NC
NC
NC
NC
NC

DEVSLP

NC
NC
NC
NC
NC

PERST#
CLKREQ#
PEWake#

N/C

N/C
NOTCH
NOTCH
NOTCH
NOTCH

3.3V

3.3V

3.3V

NGFF_SSD

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74

+3V3_SATA_N1

+3V3_SATA_N1

R375

IOAC@0_8

TP73

DEVSLP_N1

NGFF1_RST#
PCIE_CLKREQ_NGFF1#

TP74
TP76

2

Leakage circuit (MPC)

+WL_VDD+WL_VDD

R14

4.7K/J_4

+3V

2N7002KDW

5

4 3

2

6

1

Q3

R363 *0/J_4
R368 *0/J_4

WIFI card reset (non-IOAC)
WIFI card reset (IOAC)
Debug card reset

C510

C3

*10u/6.3V_6

*0.1u/16V_4

10u/6.3V_6C638

0.1u/16V_4C639

0.1u/16V_4C642

0.1u/16V_4C643

0.1u/16V_4C637

+3V3_SATA_N1

12/17 Delete R571 & Net "+3V3_SATA_N1_N"

R563 0_4

R562 0_4

DEVSLP2

PLTRST#

R561 *10K_4

R364
*10K_4

IOAC

PCIE_CLKREQ_WLAN# [6]

EC_PCU

IOAC_WLAN_WAKE# [28]

R365

PCIE_LAN_WAKE# [8,22]

*0_4

Stuff

R352 NAC@0_8

C511

C13

**0.1u/16V_4

**0.1u/16V_4

+3V3_SATA_N1 +3V

R576 0_8

DEVSLP2 [6]

PCIE_CLKREQ_NGFF1# [6]

1

25

S0

S0

+3V+WL_VDD

10u/6.3V_6C649

0.1u/16V_4C647

12/21 Change CN8 footprint to "ngff-nasm0-s6701-ts50-km-smt " for SMT requset

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

Z8VR

PROJECT :

Z8VR

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

NGFF WiFi & BT & SSD

NGFF WiFi & BT & SSD

NGFF WiFi & BT & SSD

Date: Sheet of

Date: Sheet of

5

4

3

Date: Sheet of

2

Z8VR

25 46Thursday, June 22, 2017

25 46Thursday, June 22, 2017

25 46Thursday, June 22, 2017

1

1A

1A

1A

5

KEYBOARD (KBC)

CN15

1

MX0

2

MX1

3

MX2

4

MX3

5

MX4

6

MX5

7

MX6

8

MX7

9

D D

KB CONN

C C

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

29
30

*VPORT_6

MY17
MY16
MY15
MY14
MY13
MY12
MY11
MY10
MY9
MY8
MY7
MY6
MY5
MY4
MY3
MY2
MY1
MY0

D30

2 1

R674 33_4

MX0 [28]
MX1 [28]
MX2 [28]
MX3 [28]
MX4 [28]
MX5 [28]
MX6 [28]

MX7 [28]
MY17 [28]
MY16 [28]
MY15 [28]
MY14 [28]
MY13 [28]
MY12 [28]
MY11 [28]
MY10 [28]
MY9 [28]
MY8 [28]
MY7 [28]
MY6 [28]
MY5 [28]
MY4 [28]
MY3 [28]
MY2 [28]
MY1 [28]
MY0 [28]

C735
180P/50V_4

Prevent ESD/EOS
Layout near
device

<EMI>

MX4
MX5
MX6
MX7
MY3
MY2
MY1
MY0
MY7
MY6
MY5
MY4
MY11
MY10
MY9
MY8
MX0
MX1
MX2
MX3
MY15
MY14
MY13
MY12

NBSWON# [28]

1

2

3

4

CP4

5

6

*220P_8P4R

7

8

1

2

3

4

CP1

5

6

*220P_8P4R

7

8

1

2

3

4

CP2

5

6

*220P_8P4R

7

8

1

2

3

4

CP3

5

6

*220P_8P4R

7

8

1

2

3

4

CP5

5

6

*220P_8P4R

7

8

1

2

3

4

CP6

5

6

*220P_8P4R

7

8

KB_BL LED (KBC)

+5V+5V

R33

10K_4

DTC144EU

2

Q7

1 3

KB_BL_LED[28]

B B

G-sensor(ACS)

+3V

to CPU
to SATA HDD

A A

ACCEL_INTA

C420
*22P/50V_4

ACCEL_INTA[4]
ACCEL_INT2[24]

CLK_SDATA[7,11,12,19]
CLK_SCLK[7,11,12,19]

+G_SEN_PW

5

C36 *2.2u/6.3V_6

1

Q5
AO3413

2

20mil 20mil

3

+5V_KB

C23

4.7u/6.3V_6

R265GS@0_6

GS@0.1U/16V_4

G_MBDATA_R

G_MBCLK_R

R266 GS@0_4
R269 GS@0_4
R279 GS@0_4

+G_SEN_PW

CLK_SDATA
CLK_SCLK

+G_SEN_PW

R267 *4.7K_4
R289 *4.7K_4

+G_SEN_PW

C429

GS@10u/6.3V_6

D6GS@RB500V -40
D5GS@RB500V -40

C389 *33P/50V_4

C400 *33P/50V_4

G_MBDATA_R
G_MBCLK_R

C22

0.01u/50V_4

ACCEL_INTA_R
ACCEL_INT2_R

2013/10/22 change CN25 pin define for spec.1A-7

2013/10/23 change CN25 footprint.1A-8

G_MBDATA_R
G_MBCLK_R

+3VPCU

MX4
MX6
MX5
MX7

U16

1

Vdd_IO

14

VDD

11

INT1

9

INT2

7

SA0

6

SDA

4

SCL

8

CS

GS@LIS3DHTR

10

4

RP1 *10K_10P8R

1

9

2

8

3

7 4

56

CN4

346
2
1

KBL@KB_backlight

NC
NC

RESERVED
RESERVED

GND
GND
GND
GND

4

3

2014/01/13 Change TP power rail from +3V_S5

TOUCHPAD BOARD CONN (TPD I2C/PS2 co-lay)

TPD->100kHz,TS=400Khz
Intel design guide suggestion
MCP PIN 10u.
Per inch 3u TS=3x5inch
400kHz10~100u =2.4~0.4k.
100Khz 10~100u=9k~1k.

R668 0_4

*TDI@DMN601DWK-7

SMB1ALERT#[7]

1

4 3

Q48

R677 0_4

+3V_S5

R691

*10K_4

S5 S5

I2C0_SDA[4]
I2C0_SCL[4]

MX3

MX2
MX0
MX1

CPU FAN (THM)

R667 0_4

+3V_S5

R670

10K_4

TPCLK[28]

TPDATA[28]

6

I2C_TP_SDA_R

2

I2C_TP_SCL_R

5

12/16 Change FAN design from PWM-type to DAC-type

+3V

+3V

2

1

1C-2

R669

10K_4

R672 0_4
R673 0_4

2.2U/6.3V_6
Q49
2N7002K

3

FAN1_DAC[28]

EC DAC SIGNAL

to +3V_SUS.

R675*2.2K_4

R676*2.2K_4

I2C PU at CPU side

C747

2

+3V_S5

PTP_PWR_EN#[28]

+TPVDD

C738

*0.1u/16V_4

TPD_INT#[4,28]

+5V

AL000991000 EOD, change to AL005606002

U40

1 2

VIN2VO

GND

1

/FON

GND
GND

4

VSET

GND

G991P11U

FANPWR = 1.6*VSET

1

2014/01/15 reserve TP power rail +3V_S5.1C-4

1C1-1 2014/02/17 Add Q47 for PTP

power EN and soft up R694\C713.
and C712\C686.

*AO3413

3

+

C739

C736

Q47

2

0.22u/25V_6

C725 *1000p/50V_4

TPD_EN[28]

2013/10/29 Change CN21 power rail to S5
change Q42 direction and net name,

1A-12

reseve PS2 PU to +3V.

FAN1_RPM[28]

TH_FAN_POWER

C746

2.2U/6.3V_6

0.1u/16V_4

50mil

I2C_TP_SDA_R
I2C_TP_SCL_R
TPD_INT#
TPD_EN

2013/10/18 Change CN21 Pin8 for

1A-5

I2C/PS2 TPD idendify.

30mils

C748

C745

.01U/50V_4

*.01U/50V_4

+3V

TPCLK_R
TPDATA_R

R690

10K_4

+TPVDD

CN19

1
234

FAN_3P

TP CN

789
6
5
4
3
2
1

5

CN16

1

C730

0.1u/16V_4

R658 *0_4

C737

*0.1u/16V_4

3
5
6
7
8

R671 0_6

1 2

1A-12013/10/15 change pin define and add pwm IC U17.

26

10

1A-42013/10/17 Change U17 to G991P11U and PU U17 pin1.

1A-92013/10/24 Add alert on U17.1 for CPU themal tempture.

1A-13 2013/10/31CN15 Pin2/3 swap.

5

R684 *1M_4

POWER LED(UIF)

R679 *1M_4

R683 *1M_4

Power LED

2
3

10
15

5
12
13
16

PWRLED#[28]

SUSLED#[28]

Battery

BATLED0#[28]

BATLED1#[28]

3

R348 150/F_4

R350 182/F_4C388

Rev:D change

R343 *1M_4

R680 *1M_4

R345 150/F_4

R344 182/F_4

Rev:D change

+3VPCU

+3V

+3VPCU

D10 *5.5V/25V/410P_4

LED_AMBER/BLUE

D11 *5.5V/25V/410P_4

D13 *5.5V/25V/410P_4

LED_AMBER/BLUE

D12 *5.5V/25V/410P_4

Blue 150 ohm CS11502FB21 -> Rev D

Amber 182 ohm CS11822FB21 -> Rev D

1 2

Blue

LED1

2 3

1

Amber

1 2

+3VPCU

1 2

Blue

LED2

2 3

1

Amber

1 2

R347 0_4

R349 *0_4

R681 0_4

R682 *0_4

2

+3VPCU

+3V_S5

+3VPCU

+3V_S5

+3VPCU

C740

39P/50V_4

for ESD

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Z8VR

Z8VR

PROJECT :

PROJECT :

Size D ocument Number Rev

Size D ocument Number Rev

Size D ocument Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

PROJECT :

KB/TP/FAN

KB/TP/FAN

KB/TP/FAN

Z8VR

26 46Thursday, June 22, 2017

26 46Thursday, June 22, 2017

1

26 46Thursday, June 22, 2017

1A

1A

1A

5

USB Charger to 3.0 (UBC)

+5VPCU

80 mils (Iout=2A)

C482

1U/10V_4

USB_OC0#[6]

USB_BC_ON[28]

D D

GMT:AL003703000(G3703)
TI:AL002544001(TPS2544)
Silergy: AL055544000 (SLGC55544VTR)

USB_CHARGE_ON[28]

USB_CLT1[28]

+5VPCU

R339 100K_4

R337 10K_4
R336 10K_4

U19

1

IN

OUT

ILIM_LO

ILIM_HI

9

STATUS

GND_PAD

13

FAULT

4

ILIM_SEL

EN

CTL1
CTL2
CTL3

GND
GND
GND

TPS2544RTER

DM_IN

DP_IN

DM_OUT

DP_OUT

GND

GND
GND

5

6
7

CTL2

8

CTL3

18
19
20

12

ILIM_LO

15

ILIM_HI

16

17

14

USBP0-_C

11

USBP0+_C

10

2
3

21
22

4

(RILIM_LO 1.2A)

(RILIM_HI 2.3A)

80 mils (Iout=2A)

R340
20K/F_4

iPAD charging current is about 2.1A so set on 2.3A

1.2A current limit of USB 3.0 SDP mode

USBP0- [6]
USBP0+ [6]

R338
39K/F_4

USBPWR0

+

C477
100u/6.3V_1206

C476
470P/50V_4

3

C474

0.1u/16V_4

2

CTL1 CTL2 CTL3 ILIM_SEL

SDP 1 1 1 0

1

27

CDP 1 1 1 1

DCP 0 1 1 X

RILIM_LO is optional and the ILIM_LO pin may be left unconnected if the following conditions are met:

1. ILIM_SEL is always set high

2. Load Detection - Port Power Management is not used

3. Mouse / Keyboard wake function is not used
If conditions 1 and 2 are met but the mouse / keyboard wake function is also desired, it is recommended to use
RILIM_LO < 80.6 kΩ.
The following equation programs the typical current limit:
(1)
RILIM_XX corresponds to either RILIM_HI or RILIM_LO as appropriate.

IOS_typ(m A) = 50,250/ {RILIM_XX(KΩ)+0 .1}

USB 3.0 Connector (UB3)

12/18 Add for ESD

C C

USBON#[28]

USB_OC1#[6]

B B

USB2.0 DB (UB2)

USB_OC2#[6]

A A

+5V_S5

C422

1u/6.3V_4

5

4

USBON#

Enable: Low Active /2.5A
BCD:AL002822000
GMT:AL000524007

1u/6.3V_4
C694

USBON#

USB_OC2#

USBP2-[6]
USBP2+[6]

HP_JD#[23]

SLEEVE[23]

RING2[23]

HP-L3[23]

HP-R3[23]

5

U17

IN

/EN

G524B2T11U

+5V_S5

5

4

USBP2­USBP2+

OUT

GND

/OC

U38

IN

/EN

G524B2T11U

USBPWR2

HP_JD#

SLEEVE

RING2

HP-L3

HP-R3

USB3_TXN0[6]

Close USB3.0

1

2

3

1

OUT

2

GND

3

/OC

USBPWR1

C418

C417

470P/50V_4

0.1u/16V_4

C714
470P/50V_4

Enable: Low Active /2.5A
BCD:AL002822000
GMT:AL000524007

ADOGND

C433
100U/6.3V_1206

USBPWR2

C713

0.1u/16V_4

CN13

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

CONN SMD FFC 24P 1R FR(P0.5,H2.0)

4

C701

C717

100U/6.3V_1206

10U/6.3V_6

Pin Numbers:
USBPWR: 5
GND: 7
Audio Signal: 5
ADOGND: 4
NC: 1
USBP2+/-: 2

12/18 Add for ESD

Card Reader (CRD)

+3V

R341 0_6

USB3_TXP0[6]

USB3_TXN1[6]
USB3_TXP1[6]

+3V_CR SD_CLK

C487

4.7U/6.3V_6

USBP1-[6]

USBP1+[6]

C490

0.1u/16V_4

USB3_RXN0[6]
USB3_RXP0[6]

USB3_RXN1[6]
USB3_RXP1[6]

R346 6.2K/F_4

USBP7-[6]
USBP7+[6]

R342
*0_4

3

USBP0-_C
USBP0+_C

C484 *1.6P/50V_4

C483 *1.6P/50V_4

C481 0.1u/16V_4
C479 0.1u/16V_4

C452 *1.6P/50V_4

C451 *1.6P/50V_4

C445 0.1u/16V_4
C442 0.1u/16V_4

C488
1u/10V_4

C489

0.1u/16V_4

R90028 0_4
R90029 0_4

C491 1u/10V_4

RREF

VCC_XD
SDREG

25

USB3_TXN0_C
USB3_TXP0_C

USB3_TXN1_C
USB3_TXP1_C

U21

1

RREF

2

DM

3

DP

4

3V3_IN

5

CARD_3V3

6

SDREG

GND

USBP1-_C
USBP1+_C

TP46

TP44

V18

XD_D7

SP14

24

22

23

V18

XD_D7

RTS5170

XD_CD#7SP18SP29SP310SP411SP5

XD_CD#

SD_WP/MS_D1

SP2

TP42

TP43

11111010131312

11111010131312

R351 0_4

reserve for EMI

C486

4.7u/6.3V_6

C1647

*10p/50V_4

USBPWR0

C475

0.1u/16V_4

USBP0-_C

USB3_RXP0

USBPWR1

C447

0.1u/16V_4

C485

0.1u/16V_4

0218 reserve for EMI

C1643

*10p/50V_4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

U20

USB3_TXP0_C

1

I/O 1

USB3_TXN0_C

10

I/O 6

2

VDD

9

GND_2

3

NC_1

8

NC_2

4

I/O 2

USBP0+_C

7

I/O 5

5

I/O 3

USB3_RXN0

6

I/O 4
GND_1

11

USB30_ESD_AZ1165-06F.R7G

USB protection diodes for ESD .
as close as possible to USB connector pins.

USBP1-_C

USB3_TXP1_C

USB3_RXP1

USB protection diodes for ESD .
as close as possible to USB connector pins.

U18

1

I/O-1

I/O-6

2

VDD

GND#1

3

NC#1

NC#2

4

I/O-2

I/O-5

5

I/O-3

I/O-4
GND#2

11

AZ1065-06F.R7G

CN1

11
10

9
8
7

SD_CLK_R

6
5
4
3
2
1

C1644

C1645

*10p/50V_4

*10p/50V_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

USB3/Charger/ CR/USB2 DB

USB3/Charger/ CR/USB2 DB

USB3/Charger/ CR/USB2 DB

WP
CD
DATA2
DATA1
DATA0
VSS2
CLK
VDD
VSS1
CMD
CD/DATA3

1

USBP1+_C

10

9

8

USB3_TXN1_C

7

USB3_RXN1

6

C1646

*10p/50V_4

SD_CLK_R
SD_CMD
SD_D2/MS_D5
SD_D1/MS_D7
SD_D0/MS_D6
SD_D3/MS_D4

GND

GND

GND12GND

14

13

Z8VR

Z8VR

Z8VR

27 46Thursday, June 22, 2017

27 46Thursday, June 22, 2017

27 46Thursday, June 22, 2017

15

NC
NC

SD-CARD

16
17

1A

1A

1A

USBPWR0

CN14
USB3.0 CONN

1

VBUS

1

2

D-

2

3

D+

3

4

4

GND

5

SSRX-

5

6

6

SSRX+

7

7

GND

8

8

SSTX-

9

SSTX+

9

12

C478

C480

*1.6P/50V_4

*1.6P/50V_4

USBPWR1

CN12
USB3.0 CONN

1

VBUS

1

2

D-

2

3

D+

3

4

4

GND

5

SSRX-

5

6

6

SSRX+

7

7

GND

8

8

SSTX-

9

SSTX+

9

12

C446

C443

*1.6P/50V_4

*1.6P/50V_4

SD_WP/MS_D1
SD_CDZ
SD_D2/MS_D5

TP49
TP50

TP47

2

SD_D1/MS_D7
SD_D0/MS_D6

SD_CLK
VCC_XD

SD_CMD
SD_D3/MS_D4

R696
*2K/F_4

12/31 Add R696 for discharge

EMI

C1648

*10p/50V_4

TP48

SD_D2/MS_D5

SD_D3/MS_D4

SP11

SD_CMD

SP1119SP1220SP1321SP14

18

SP10

17

GPIO0

GPIO0

16

SP9

SP9

15

SP8

14

SP7

SP7

SD_CDZ

13

SP6

12

SD_D1/MS_D7

SD_D0/MS_D6

SP5

TP45

5

EC(KBC)

R616 2.2_6

+3V_LDO_EC

+3VPCU_EC and +3V_RTC
minimum trace width 12mils.

D D

+3V_LDO_EC

1 2

TS_EN[20]

Prevent ESD/EOS Layout near device

C C

12/16 SWAP with "TS_EN_C" to pin81

Prevent ESD/EOS Layout near device

EC_ODD_EJ#[24]

CLK_PCI_EC

R602

*22_4

C651
*10p/50V_4

B B

NBSWON#

A A

1 2

D17

R603

SDMK0340L-7-F

100K_4

2 1

C653
1u/6.3V_4

R270 33_4

C387 180P/50V_4

FAN1_DAC[26]

R621 33_4

C666 180P/50V_4

12/16 SWAP with "FAN1_DAC" to pin32

+3V_LDO_EC

R641
10K_4

C693

0.1u/16V_4

5

L11
BLM15AG121SN1D(120,500MA)_4

12 mils

C662

C658

0.1u/16V_4

0.1u/16V_4

+3V

+3V_S5

LPC_LAD0[7,24,25]
LPC_LAD1[7,24,25]
LPC_LAD2[7,24,25]
LPC_LAD3[7,24,25]

C359 180P/50V_4

PLTRST#[8,14,22,24,25]

CLK_PCI_EC[7]

LPC_LFRAME#[7,24,25]

TS_EN_C

Reserve switch for test
(MP remove)

1

SIO_EXT_SCI#[2]

5

PCH_SUSPWRDNACK[8]

IOAC_WLAN_WAKE#[25]

IOAC_LAN_WAKE#[22]

PCH_SPI_CLK_EC[7]

SPI_CS0#_UR_ME[7]

TS_EN_C

Near EC

IRQ_SERIRQ[7,24]

SIO_RCIN#[7]

KB_BL_LED[26]
DNBSWON#[8]

Pi n 80 EC_APWROK reserve TP

SUSB#[8,31]

EC_PWROK[8]

PCH_BLON_R[20]

ME_WR#[4]

AMP_MUTE#[23]

ODD_POWER[24]

ACIN[29]

TEMP_MBAT#[29]

WLANPWR#[25]

PCBEEP_EC[23]

DDR4_SUSON_2V5[33]

+1V_S5_ON[31]

PCH_SPI_SI_EC[7]

PCH_SPI_SO_EC[7]

MY16[26]
MY17[26]

S5_ON[30,37]

PTP_PWR_EN#[26]

MY0[26]
MY1[26]
MY2[26]
MY3[26]
MY4[26]
MY5[26]
MY6[26]
MY7[26]
MY8[26]

MY9[26]
MY10[26]
MY11[26]
MY12[26]
MY13[26]
MY14[26]
MY15[26]

SW2
POWER_SW

3
42

6

TP81

TP82

C661

0.1u/16V_4

1 2
1 2

R605 2.2_6

PROCHOT_EC

+1V_S5_ON
EC_ODD_EJ_R#

S5_ON

+A3VPCU

C667

0.1u/16V_4

ECAGND

+3VPCU_EC

C660

C356

0.1u/16V_4

0.1u/16V_4

+3V_EC

C654

0.1u/16V_4

10

9
8

7
22
13

6

17

0.1u/16V_4

126

C8809

5
15
23
14

WRST#

4
16

113
123

80

119

33
88
81
87

109
108

71
72
73
35
34

122

95
94

105
101
102
103

56
57
32

100
125

36
37
38
39
40
41
42
43
44
45
46
51
52
53
54
55

MX0[26]
MX1[26]
MX2[26]
MX3[26]
MX4[26]
MX5[26]
MX6[26]
MX7[26]

Reset SW (FSW)

BI[29]

4

11/11 FAE
suggestion
pin106 +3V_RTC
change to
+3VPCU_EC

C665

0.1u/16V_4

VSTBY_FSPI

U35

11

114

LAD0/GPM0(3)
LAD1/GPM1(3)
LAD2/GPM2(3)
LAD3/GPM3(3)
LPCRST#/GPD2
LPCCLK/GPM4(3)
LFRAME#/GPM5(3)

LPCPD#/GPE6

GA20/GPB5(3)
SERIRQ/GPM6(3)
ECSMI#/GPD4(3)
ECSCI#/GPD3
WRST#
KBRST#/GPB6(3)
PWUREQ#/BBO/SMCLK2ALT/GPC7(3)

CRX0/GPC0
CTX0/TMA0/GPB2(3)

DAC4/DCD0#/GPJ4(3)
DSR0#/GPG6
GINT/CTS0#/GPD5
PS2DAT1/RTS0#/GPF3
DAC5/RIG0#/GPJ5(3)
PS2CLK1/DTR0#/GPF2
TXD/SOUT0/GPB1
RXD/SIN0/GPB0

ADC5/DCD1#/GPI5(3)
ADC6/DSR1#/GPI6(3)
ADC7/CTS1#/GPI7(3)
RTS1#/GPE5
PWM7/RIG1#/GPA7
DTR1#/SBUSY/GPG1/ID7
CTX1/SOUT1/GPH2/SMDAT3/ID2
CRX1/SIN1/SMCLK3/GPH1/ID1

FSCK/GPG7
FSCE#/GPG3
FMOSI/GPG4
FMISO/GPG5

KSO16/SMOSI/GPC3(3)
KSO17/SMISO/GPC5(3)
PWM6/SSCK/GPA6

SSCE0#/GPG2
SSCE1#/GPG0

KSO0/PD0
KSO1/PD1
KSO2/PD2
KSO3/PD3
KSO4/PD4
KSO5/PD5
KSO6/PD6
KSO7/PD7
KSO8/ACK#
KSO9/BUSY
KSO10/PE
KSO11/ERR#
KSO12/SLCT
KSO13
KSO14
KSO15

121

VCC

VSTBY26VSTBY50VSTBY92VSTBY

VSTBY

LPC

CIR

EXTERNAL SERIAL FLASH

SPI ENABLE

KBMX

KSI0/STB#58KSI1/AFD#59KSI2/INIT#60KSI3/SLIN#61KSI462KSI563KSI664KSI7

Battery Detect Switch

R689 *0_4

3

4

+3VPCU_ECPLL

L9
BLM15AG121SN1D(120,500MA)_4

C657

0.1u/16V_4

106

74

VSTBY_FSPI

19

127

AVCC

VSTBY(PLL)

3

84

82

20

GPH7

EGAD/GPE1

EGCS#/GPE283EGCLK/GPE3

L80LLAT/GPE7

L80HLAT/BAO/GPE0

GPIO

IT8987E/CX
LQFP

UART port

RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7

VSS

VSS

VSS27VSS

AVSS

VSS

1

49

75

91

65

104

ECAGND

R234*0_4

R2620_4

R609*0_4

R622*0_4

12/14 Add R689 for Acer requset

SW3

2
14

PJA138K

EC_GND

Q37

L10

BLM15AG121SN1D(120,500MA)_4

3

Vgs = 1.5V

1

+3VPCU[6,9,20,22,23,24,25,26,29,30,37,40]

+3V_S5[2,3,4,6,7,8,9,22,24,25,26,30,33,39]

97

ID5/GPH598ID6/GPH699ID3/GPH396ID4/GPH4

WAKE UP

VCORE

12

C655

0.1u/16V_4

2

12

+3V[2,4,6,7,8,9,11,12,14,15,16,17,19,20,21,22,23,24,25,26,27,30,31,33,34,37,38,39,40]

(For PLL Power)

93

SM BUS

CLKRUN#/ID0/GPH0

A/D D/A

+3VPCU_EC

SB_ACDC [8]
POA_EN# [24]

POA_PWR_INT# [24]
POA_POWERREQ [24]

TP80

USBON# [27]

USB_BC_ON [27]
USB_CHARGE_ON [27]

CLKRUN# [7,24]

SMCLK0/GPB3
SMDAT0/GPB4
SMCLK1/GPC1
SMDAT1/GPC2

PECI/SMCLK2/GPF6(3)

SMDAT2/PECIRQT#/GPF7(3)

PS/2

PS2CLK0/CEC/TMB0/GPF0

PS2DAT0/TMB1/GPF1

PS2CLK2/GPF4
PS2DAT2/GPF5

PWM0/GPA0
PWM1/GPA1
PWM2/GPA2
PWM3/GPA3
PWM4/GPA4
PWM5/GPA5

PWM

TACH0A/GPD6(3)

TACH1A/TMA1/GPD7(3)

TMRI0/GPC4(3)
TMRI1/GPC6(3)

PWRSW/GPE4

RI1#/GPD0(3)

RI2#/GPD1

ADC0/GPI0(3)
ADC1/GPI1(3)
ADC2/GPI2(3)
ADC3/GPI3(3)
ADC4/GPI4(3)

TACH2/GPJ0(3)

DAC2/TACH0B/GPJ2(3)
DAC3/TACH1B/GPJ3(3)

CLOCK

AJ089870F02 IT8987E/CX

+3V_RTC

12

R536
100K_4

BI_GATE

SW1

C634

42

3

POWER_SW

*0.1u/25V_6

6

5

1

GPJ1(3)

GPJ7
GPJ6

IT8987/CX

3

Prevent ESD/EOS Layout near device

110

MBCLK

111

MBDATA
2ND_MBCLK

115

2ND_MBDATA

116

EC_PECR_R

117

LID#_C

118

R607 33_4

C659 180P/50V_4

85
86
89
90

24
25
28

SUSLED#

29
30
31

47
48

120
124

107

NBSWON#

18
21

HWPG

112

ICMNT

66
67

C398 10u/6.3V_6

68
69
70

76

SYS_HWPG

77
78
79

2
128

C656
180P/50V_4

R592 *0_4

R591 *0_4

R581
*10K_4

C646
*0.1u/16V_4

Q38

*PJ4N3KDW

3

R612 *0_4

R613 0_4

+3V_S5 VSTBY_FSPI

TPD_EN [26]

MBCLK [29]
MBDATA [29]

2ND_MBCLK [7,17]

2ND_MBDATA [7,17]

H_PECI [2]

LID# [20]

R617 33_4R601 *2.2_6

C663
180P/50V_4

+3V_LDO_EC

R608 43_4

Prevent ESD/EOS Layout near EC

IOAC_RST# [22,25]

EC_FPBACK# [20]

TPCLK [26]
TPDATA [26]

PWRLED# [26]
BATLED1# [26]
SUSLED# [26]

BATLED0# [26]

MAINON [24,30,33,37]
USB_CLT1 [27]

FAN1_RPM [26]
POA_AUTH_ERR [24]

SUSON [8]

DGPU_OTP# [17]

NBSWON# [26]
SUSC# [8]
HWPG [8]

RSMRST# [8]

ICMNT [29]

ECAGND

DGPU_OPP# [17]

VRON [8]

LANPWR# [22]

POA_FP_PWREN# [24]

PCH_PWROK [8]

CLR_CMOS [6]

R606 33_4

Prevent ESD/EOS Layout near device

SYS_SHDN# [2,30,37]

TPD_INT# [4,26]

SM BUS ARRANGEMENT TABLE

SM Bus 1

Battery

SM Bus 2

PCH/VGA

SM Bus 3

SM Bus 4

+3V_RTC

+3VPCU

WRST#

Vgs = 1.5V

6

215

4 3

2

Prevent ESD/EOS Layout near device

R623 33_4

C668
180P/50V_4

12/16 Add D32 for production-line requset

LID#_C

1 2

TVS PN:
Priority1: CY000220Z00
Priority2: CY402220B00

Prevent ESD/EOS Layout near device

R618 33_4

C664
180P/50V_4

RF_EN [25]

Reserve no stuff

2

BT_EN [25]

D32
TVM0G5R5M220R

S5_ON
NBSWON#

DGPU_OTP#
DGPU_OPP#

MAINON

SUSON

VRON

PCH_SPI_SI_EC

PCH_SPI_SO_EC

SM BUS PU(KBC)

MBCLK

Battery module

UMA& VGA SKU
Need Stuff

HWPG(KBC)

MBDATA

2ND_MBCLK
2ND_MBDATA

PROCHOT_EC

DDR=1.5V, D1 DNP and D2 POP
DDR=1.35V, D1 POP and D2 DNP

HWPG_1.5V[37]

HWPG_1.8VS5[37]

HWPG_VDDR[33]

HWPG_1VS5[31]

SYS_HWPG[30]

HWPG_2.5V[33]

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

R599

100K_4

1

+3V_LDO_EC

R615 10K_4
R260 10K_4

+3V

R232 EV@10K_4
R620 EV@10K_4

R256 100K_4

R239 100K_4

R619 100K_4

R614 *10K_4

R263 *10K_4

+3V_LDO_EC

R611 4.7K_4
R610 4.7K_4

+3V_S5

R247 2.2K_4
R243 2.2K_4

3

Q40

2

2N7002K

1

D23 RB500V-40

D22 *RB500V-40

D27 *RB500V-40

D24 *RB500V-40

D18 *RB500V-40

D25 *RB500V-40

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

KBC IT8587

KBC IT8587

KBC IT8587

1

28

H_PROCHOT# [2,29,34]

+3V

R604
10K_4

HWPG

Z8VR

Z8VR

Z8VR

28 46Thursday, June 22, 2017

28 46Thursday, June 22, 2017

28 46Thursday, June 22, 2017

1A

1A

1A

5

4

3

2

1

Double Check ADP-In Type

12/22 Change PJ2 footprint to "50320-0040n-001-4p-l-smt"
& reverse Pin1~4 for SMT request

PJ2

4

4

3

3

2

2

1

1

D D

C C

B B

Power conn

UMA-> PR342 CS31542FB14 15.4K 1/16W +-1% (0402) For 78W

Dis -> PR342 CS31272FB17 12.7K 1/16W +-1% (0402) For 95W

9

889

7

7

6

6

5

5

4

4

3

3

2

2

1

10

1

10

50458-00801-V01

PJ1

Double Check BATT-In Type

A A

PC10

*47p/50V_4

5

PC167

0.1u/50V_6

PC168

*100p/50V_4

1 2

12

1 2

PC14

0.1u/50V_6

ACIN[28]

12

PR10 *0_4

1 2

PR14 100_4

12

PR13
100_4

2 1

PD3

PDZ5.6B

1 2

PC13

2200p/50V_4

PR39
100K/F_4

PR40
100K/F_4 PU1

12

12

PR12
100_4

2 1

PD4

PDZ5.6B

VA VA1

PD2

2 1

P4SMAFJ20A

REGN6V

PMON[34]

BAT-V

TEMP_MBAT#

1 2

PR18 1M_4

12

PC11

*47p/50V_4

1

2

PMON

PR23
SP@12.7K/F_4

+3VPCU

MBCLK [28]

MBDATA [28]

PD1
SV1040

3

ICMNT[28]

TP1

1 2

BI [28]

TEMP_MBAT# [28]

*

+3VPCU

1 2

PR211
137K/F_4

MBDATA

MBCLK

ICMNT

1

no stuff

PC5

0.1u/50V_6

PR31
866K/F_4

D/C#

PC18

4

*100P/50V_4

PR9 10K_4

PR15 *10K_4

PC20

PR204
316K/F_4

PC1
1n/50V_4

100P/50V_4

12

12

12

PQ1
AON6414AL

5

PR16
20_1206

PC37

100P/50V_4

PR206
100K/F_4

3
2
1

4

PR29

4.02K/F_4

PC16

0.47u/25V_6

1 2

PR30 0_4

PR19 0_4

PR17 0_4

PR32 0_4

PR26 0_4

PR25 0_4

1 2

PC8

0.01u/50V_4

VA2

PC2

47n/50V_6

24780_CMSRC

24780_ACDRV

24780_VCC

24780_ACDET

24780_BM#

24780_CMPOUT

24780_ILIM

24780_CMPIN

PR207
100K_4

1 2

PR28

4.02K/F_4

PC36

PC25

0.1u/50V_6

0.1u/50V_6

1 2

1 2

2

3

CMSRC

ACP

4

ACDRV

28

VCC

6

ACDET

5

ACOK

11

SDA

12

SCL

7

BQ24780SRUYR

IADP

8

IDCHG

9

PMON

16

TB_STAT

14

CMPOUT

21

ILIM

13

CMPIN

PROCHOT

GND#135GND#236GND#337GND#4

10

15

38

PR8 0_4

TEMP_MBAT#

12

PR22

C756

0.1u/16V_4

*100K_4

+VCCIO

12

Check PU high with HW side

1

GND#5

BATPRES

PAD29GND#630GND#731GND#832GND#933GND#10

22

1 2

PR205 *0_4

H_PROCHOT#

3

ACN

1 2

24780_ACP

24780_ACN

PC35

0.1u/50V_6

1 2

BATDRV

BATSRC

REGN

BTST

HIDRV

PHASE

LDODRV

SRP

SRN

34

PR3

0.01/F_0612

24780_BATDRV

18

24780_BATSRC

17

24780_REGN

24

24780_BST

25

24780_DH

26

24780_LX

27

24780_DL

23

20

PR5

19

PR6 0_6

H_PROCHOT# [2,28,34]

PR2 0_4

PR1 0_4

REGN6V

PR11 0_6

12

0_6

12

12

VIN

24780_ACN

24780_ACP

PC9

2.2u/10V_6 PC172

PC15
47n/50V_6

1 2

24780_SRP

24780_SRN

PC6

0.1u/25V_4

PC3

0.1u/25V_4

PC4

0.1u/25V_4

PC12

0.1u/50V_6

4

4

52

3

52

3

PR7 10/F_6

PQ30

AON7410

1

PQ29

AON7410

1

2

PC7
2200p/50V_4

1 2

1 2

PR33
*4.7_6

12

PC19
*680p/50V_6

5

12

2200p/50V_4

PQ2
AON6414AL

6.8uH_7X7X3

4

12

PL5

VIN

PR4
0_6

12

3
2
1

PC170

10u/25V_8

PC17

*0.01u/50V_4

PR209

0.01/F_0612

1 2

PR210

PR208

0_4

24780_SRP

24780_SRN

0_4

REGN MAX voltage 6.5V
V_ILIM=20*(VSRP-VSRN)=20*Ichg*Rsr
=0.793V for 3.965A current limit

ILIM=0.793V
Rsr = 0.01ohm

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Charger (BQ24780S)

Charger (BQ24780S)

Charger (BQ24780S)

Date: Sheet of

Date: Sheet of

Date: Sheet of

BAT-V

12

1 2

PC165

PC164

2200p/50V_4

10U/25V_8

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

1

29

BAT-V

PC166

10U/25V_8

Z8VR

Z8VR

Z8VR

29 46Thursday, June 22, 2017

29 46Thursday, June 22, 2017

29 46Thursday, June 22, 2017

12

1A

1A

1A

5

VIN

12

+

PC128
*33u/25V_6x4.5

D D

C C

+5VPCU

+5VPCU
5 Volt +/- 5%
TDC : 7A
PEAK : 9.3A
OCP : 12A
Width : 2800mil

12

+

PC127

220u/6.3V_6X4.2

OCP:12A

L(ripple current)
=(9-5)*5/(2.2u*0.3M*9)
=3.367A
Iocp=12-(3.367/2)=10.316A
Vth=(10.316A*14.5mOhm)+1mV=150.589mV
R(Ilim)=(150.589mV*8)/10uA
~120.47K

1 2

PC125

0.1u/50V_6

PR184

15.8K/F_4

PR185
10K/F_4

12

PC140

10u/25V_8

PL2

2.2uH_7X7X3

1 2

Power auto recovery

SYS_SHDN#[2,28,37]

12

PC135

2200p/50V_4

PR167
*4.7_6

12

PC130

*680p/50V_6

Rds(on)=14.5m ohm

3V_LDO

+3VPCU

4

52

1

52

1

PR312 0_6

PR287 *0_6

SYS_HWPG[ 28]

3

3

SYS_SHDN#

SYS_SHDN#

PQ21

AON7410

4

4

PQ23

AON7752

12

PR179

0_4

+3V_LDO_EC

PC148

0.1u/50V_6

PR181
100K/F_4

12

12

51225_EN1

PR177

1/F_6

PR180

0_4

+3VPCU

51225_DH1

51225_VBST1

51225_SW1

51225_DL1

51225_FB1

PR183
10K/F_4

20

16

17

18

15

14

3

VL 3V_LDO

1 2

PC141 10u/6.3V_6

7

PGOOD

EN1

DRVH1

VBST1

SW1

DRVL1

2

VFB1

VO1

19

13

VREG5

PU9

TPS51225RUKR

CS11CS25VCLK

51225_CS1

51225_CS2

PR190 102K/F_4

PR182 120K/F_4

2

PR171 0_6

12

PR186
10K/F_4

12

PC131

*680p/50V_6

2200p/50V_4

PR168
*4.7_6

12

1 2

PC142 0.1u/25V_4

PC151 4.7u/6.3V_6

51225_VIN

12

3

VIN

VREG3

26

PR192
0_6

DRVH2

VBST2

DRVL2

VFB2

GND#1

GND#2

GND#323GND#424GND#525GND#6

SYS_SHDN#

6

EN2

51225_DH2

10

9

8

SW2

11

4

21

22

12

PR178

51225_VBST2

51225_SW2

51225_DL2

51225_FB2

PC149

1/F_6

0.1u/50V_6

OCP:10A

L(ripple current)
=(9-3.3)*3.3/(2.2u*0.355M*9)
~2.676A
Iocp=10-(2.676/2)=8.662A
Vth=(8.662A*14.5mOhm)+1mV=126.599mV
R(Ilim)=(126.599mV*8)/10uA
=101.279K

52

PQ22

AON7410

4

3

1

12

52

4

PQ24

3

AON7752

1

Rds(on)=14.5m ohm

12

PC136

PL3

2.2uH_7X7X3

1 2

PR189 change to 9.31K for IR camera

1

PC139

10u/25V_8

+3VPCU

3.3 Volt +/- 5%
TDC : 5.53A
PEAK : 7.4A
OCP : 10A
Width : 240mil

PR188

6.49K/F_4

PC126

0.1u/50V_6

220u/6.3V_6X4.2

1 2

PR189

9.31K/F_4

PC124

30

VIN

+3VPCU

12

+

B B

+5VPCU

TDC : 3.38A
PEAK : 4.5A
Width : 140mil

+5V_S5

12

PR136 0_4

+5VPCU

A A

S5_ON

S5_ON[28,37]

PR131 0_4

PC97
10U/6.3V_6

12

PC99

0.1U/16V_4

PC108

0.1U/16V_4

12

PC103
1u/25V_4

12

12

PC106
*0.1U/16V_4

13

VOUT1#1

14

VOUT1#2

4

VBIAS

3

ON1

1000P/50V_4

PC100

1

VIN1#22VIN1#1

PU5

APL3523A

CT1

12
12

Soft-Start

5

+5VPCU +3VPCU

3

TDC : 1.05A
PEAK : 1.4A
Width : 60mil

+3V_S5+5V

+5VPCU

PR175 0_4

S5_ON

PR174 0_4

7

OUT2#1

VIN2#16VIN2#2

OUT2#2

CT2

10
12

PC101
1000P/50V_4

GND#1

GND#2

ON2

4

12

PC104
1u/25V_4

8
9

11

15

5

PR132 0_4

12

PC107
*0.1U/16V_4

12

PC102

0.1U/16V_4

12

MAINON

PC98
10U/6.3V_6

TDC : 3.6A
PEAK : 4.8A
Width : 160mil

MAINON [24,28,33,37]

12

PC133
10U/6.3V_6

12

PC137

0.1U/16V_4

PC145

0.1U/16V_4

12

PC143
1u/25V_4

12

12

PC147
*0.1U/16V_4

13

VOUT1#1

14

VOUT1#2

4

VBIAS

3

ON1

1000P/50V_4

2

1

PC129

VIN1#22VIN1#1

PU8

APL3523A

CT1

12
12

Soft-Start

VIN2#16VIN2#2

CT2

10
12

7

+3VPCU

12

PC144
1u/25V_4

8

OUT2#1

9

OUT2#2

11

GND#1

15

GND#2

5

PR176 0_4

ON2

12

PC146
*0.1U/16V_4

PC132
1000P/50V_4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

12

12

PC134

PC138

10U/6.3V_6

0.1U/16V_4

MAINON

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

SYSTEM 5V/3V (TPS51225R)

SYSTEM 5V/3V (TPS51225R)

SYSTEM 5V/3V (TPS51225R)

TDC : 3.15A
PEAK : 4.2A
Width : 140mil

+3V

Z8VR

Z8VR

Z8VR

1

1A

1A

30 46Thursday, June 22, 2017

30 46Thursday, June 22, 2017

30 46Thursday, June 22, 2017

1A

5

4

3

2

1

31

PQ2010

VIN

PC220

22U/6.3V_6

VFB=0.8V

1 3

PC224

PC219

22U/6.3V_6

*22U/6.3V_6

VIN

12

PR2056
*1M_6

12

PR2055
*1M_6

2

PC231

+VCCIO

PC233

0.1U/16V_4

*22U/6.3V_6

12

PR2057
*22_8

2

3

PQ2009
*2N7002K

1

12/28 Change VCCIO design

12

G5335-AGND-1

MAIND[33,37]

VIN

12

PR2058
*1M_6

3

PQ2007
*AO3404

1

12

12

R1

PR269

4.99K/F_4

R2

PR270
20K/F_4

PC225

*1000P/50V_4

Vo=0.8*(R1+R2)/R2
=1V

PR2060 0_4

PR2059 *0_4

PC2064
*2200p/50V_4

1 2

+1V_S5

1.0 Volt +/- 5%
TDC : 6.82A
PEAK : 9.1A
Width : 280mil

+1V_S5

+1V_S5

52

4

3

1

TDC : 2.36A
PEAK : 3.14A
Width : 100mil

PQ35

RQ3E070BNFU7TB

PC236
*22u/6.3V_6

+VCCIO

PU16

D D

HWPG_1VS5[28]

G5335-AGND-1

+5VPCU

PR275
100K/F_4

+5VPCU

PR98 *0_4

PR272 0_4

PR104
10_6

1 2

+3V

1 2

PR276 0_4

12

PC234
10U/6.3V_6

G5335-PWRGD-1

Pulse-Skipping mode

2

PQ7

DTC144EU

PR274 0_4

1 3

12

PC228

*0.047U/10V_4

G5335-AGND-1

12

PC232

0.047U/10V_4

G5335-AGND-1

VIN VIN

12

PR79
1M_6

12

2

PR80
1M_6

C C

B B

A A

+1V_S5_ON[28]

SUSON_R[8,33]

G5335-VCC-1

G5335-PFM-1

G5335-EN-1

G5335-SS-1

12

PR105
22_8

3

PQ10
2N7002K

1

2

7

21

1

3

2

23

NC

VCC

PGOOD

PFM

EN

SS

3

1

2N7002K

G5335QT2U

PQ25

12

PC152

1 2

*2.2n/50V_4

PGND#1

PGND#2

PGND#3

PGND#4

PGND#5

PR191
1M_6

IN#1

IN#2

IN#3

IN#4

TON

LX#1
LX#2
LX#3
LX#4
LX#5
LX#6

AGND

SUSD

BST

FB

8

9

22

24

6

G5335-TON-1

20

G5335-BST-1

10

G5335-LX-1

11
16
17
18
25

12

13

14

15

19

4

5

G5335-FB-1

PR273 0_4

G5335-AGND-1

+1V_S5+1V_SUS

3

2

1

Fsw=550KHz

1 2

G5335-AGND-1

PQ11
AO3404

PC83
22u/6.3V_6

PR268

73.2K/F_4

12

PR277

2.2_6

+1V_SUS

TDC : 0.18A
PEAK : 0.24A
Width : 20mil

1 2

PC235

0.1U/25V_4

PC221
*0.01U/50V_4

1 2

PR99
*4.7_6

12

PC82
*680p/50V_6

PL12

0.68uH_7X7X3

1 2

SUS0#[8]

SUSB#[8,28]

PC81

*0.1U/25V_4

12

PC217

PC218

1 2

PC230

22U/6.3V_6

2

1

2200p/50V_4

+3V

3 5

10u/25V_8

PC222

22U/6.3V_6

4

PU20
*74AHC1G09GW

PC227

22U/6.3V_6

*DTC144EU

2

ZRW Rev F Add

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size D ocument Number Rev

Size D ocument Number Rev

Size D ocument Number Rev

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

PROJECT :

+1V_S5 (G5335QT2U)

+1V_S5 (G5335QT2U)

+1V_S5 (G5335QT2U)

Z8VR

Z8VR

Z8VR

31 46Thursday, June 22, 2017

31 46Thursday, June 22, 2017

1

31 46Thursday, June 22, 2017

1A

1A

1A

5

4

3

2

1

+3V

PR2016
100K/F_4

1 2

HWPG_VDDR[28]

D D

TDC : 0.38A
PEAK : 0.5A
Width : 20mil

C C

SUSON_R[8,31]

MAINON[24,28,30,37]

TDC : 0.45A
PEAK : 0.6A
Width : 20mil

+VDDQ

12

PC2034

0.1U/16V_4

1P35V_S3 1P35V_S5

DDR_VTTT_PG_CTRL[3]

PR2017 0_4

PR2018 0_4

PR2020 0_4

PR2023

100/F_4

PR2027 *0_4

PR2029 *0_4

+VDDQ_VTT

12

PC2030

0.033U/10V_4

+1.2VSUS

1P35V_S3

12

12

PC2022
*0.1U/16V_4

PC2026
10U/6.3V_6

VID

High

Low

OCP=9A
L ripple current
=(19-1.2)*1.2/(1u*500k*19)
=2.248A
Vtrip=9-(2.248/2)*14.5mohm
=114.202mV
Rlimit=114.202mV/5uA*10=228.4Kohm

12

+5V_S5

12

PC2021
*0.1U/16V_4

20

VTT

2

VTTSNS

1

VTTGND

4

VTTREF

19

VLDOIN

PC2038

*10U/6.3V_6

PR2028 0_4

PR2030 0_4

PR2031 * 0_4

Ref. Voltage

0.675V

0.75V

1P35V_PGOOD

1P35V_S5

1P35V_S3

7CS13

10

S58S3

PU2001

RT8231BGQW

GND

VID

3

14

11

1P35V_VID

DDR=1.2V
PR2032=7.87K/F_4
PR2033=10K/F_4

PGOOD

PGND

12

1P35V_CS

FB

6

1P35V_FB

12

Ilimit=9A

PR2019
232K/F_4

1P35V_TON

9

TON

VDDQ

5

21

1P35V_VDDQ

PR2032

1 2

7.87K/F_4

PR2033
10K/F_4

PAD

UGATE

BOOT1

PHASE

LGATE

Fsw=500KHz

PR2021

1 2

499K/F_4

1P35V_UGATE

17

18

16

15

12

VDD

1P35V_BOOT

1P35V_PHASE

1P35V_LGATE

1P35V_VDD

12

PC2040
1U/6.3V_4

PR2024 0_4

PR2022

2.2_6

12

0.1u/50V_6

+5V_S5

S4/S5

PC2029

1 2

+VDDQ_VTT[11,12]

1

VIN[20,23,24,29,30,31,34,35,36,37,38,39]

+5V_S5[27,30,34,35,36,38,39,40]

+VDDQ[11,12]

+1.2VSUS[3,5,11,12,40]

52

PQ2005

AON7410

4

3

1

52

4

PQ2006

3

AON7752

1

Rds(on)=14.5mohm

VDDQ VTTREF VTT

S5S3

1

1S3 (mainon off)S00

0

12

12

1 2

PC2023

0.1U/25V_4

PR2025
*4.7_6

12

PC2039
*680p/50V_6

ON

OFF0 OFF

PC2027

10u/25V_8

1 2

ONON

OFF

PC2024

10u/25V_8

PL2001

1uH_7X7X3

1 2

ONON

OFF

0.1U/25V_4

12

PC2031

0.1U/16V_4

+1.2VSUS

1.2 Volt +/- 5%
TDC : 5A
PEAK : 6.67A
OCP : 9A
Width : 200mil

+1.2VSUS

12

12

PC2035

22U/6.3V_8

12

12

PC2036

PC2032

22U/6.3V_8

PC2037

22U/6.3V_8

22U/6.3V_8

VIN

PC2028

2200P/50V_4

PR2026

PC2025

0_4

33

+

PC2033

*330u/2.5V_6X4.2

B B

+2.5VSUS Power Rail For DDR4

+2.5V_SUS

2.5Volt +/- 5%
TDC : 0.91A
PEAK : 1.21A
Width : 40mil

+2.5V_SUS

12

PC260

10U/6.3V_6

+2.5V_SUS [11,12]

12

PC261

1 2

*10U/6.3V_6

PC262

0.1U/16V_4

3

PR310 0_6

PC263

0.47uF/6.3V_4

PU19

5

PG

1

EN

G5719BTB1U

12

12

PC264

4.7U/6.3V_6

4

3

VIN

LX

2

GND

FB

6

R1

PR307

47.5K/F_4

PR308
15K/F_4

R2

1 2

4

1 2

G5719LX2.5V

2.2uH/1.85A_2.5X2X1.2

PR303
0_4

Vo=(0.6(R1+R2)/R2)

PL15

+3V_S5

+3V

Check PU high with HW

SUSON_R

DDR4_SUSON_2V5[28]

A A

5

HWPG_2.5V[28]

PR304 *0_4

PR305 0_4

PR311

100K/F_4

1 2

PR309 0_4

PR306 10K_4

10/26 Reserve +2.5V for DDR4 VDDSPD

+2.5V_SUS

3

2

MAIND[31,37]

MAIND

2

PQ40
*AO3404

1

TDC : 0.16A
PEAK : 0.21A
Width : 20mil

+2.5V

+2.5V [11, 12,37]

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

DDR4_+1.2VSUS (G5316RZ1D)

DDR4_+1.2VSUS (G5316RZ1D)

DDR4_+1.2VSUS (G5316RZ1D)

Z8VR

Z8VR

Z8VR

33 46Thursday, June 22, 2017

33 46Thursday, June 22, 2017

33 46Thursday, June 22, 2017

1

1A

1A

1A

5

4

3

2

1

Check PU high with HW

VRON_R[8]

+1V_VCCST

PR53

PC43

45.3/F_4

1000P/50V_4

+3V +VCCIO

12

PR49

PR47

10K/F_4

*10K/F_4

+3V

PR37
0_4

ISL95857_PSYS

ISL95857_IMON_B

ISL95857_NTC_B

ISL95857_COMP_B

ISL95857_FB_B

ISL95857_RTN_B

ISL95857_ISUMN_B

ISEN1_B [35]

ISEN2_B [35]

+5V_S5

PR38 0_4

PR42 0_4

PR45 0_4

12

12

PR48 0_4

PR46 0_4

PR43 0_4

PR44

*10K/F_4

1 2

PR230

90.9K_1%_4

12

PR57
100/F_4

PR56 10_4

1 2

PR52 49.9/F_4

ISL95857_VR_HOT

ISL95857_VR_READY

ISL95857_VR_EN

1

2

3

4

5

6

7

8

9

10

41

PC40 330P/50V_4

PSYS

IMON_B

NTC_B

COMP_B

FB_B

RTN_B

ISUMP_B

ISUMN_B

ISEN1_B

ISEN2_B

EP

40

11

ISL95857_FCCM_B

PR261 27.4K/F_4

Close to
VCCGT MOS

PR250 13.7K/F_4

ISL95857_SDA

ISL95857_SCLK

39

VR_ENABLE

FCCM_B

ISL95857_PWM1_B

+5V_S5

37

38

36

35

SDA

SCLK

ALERT#

VR_HOT#

VR_READY

PU2

ISL95859AHRTZ-T

PWM1_B12PWM2_B13IMON_A14NTC_A15COMP_A16FB_A

ISL95857_COMP_A

ISL95857_PWM2_B

ISL95857_IMON_A

ISL95857_NTC_A

12

PR231

PR263 470K_4_4700NTC

1 2

PC41 33P/50V_4

PC177 2200p/50V_4

VIN

12

12

PR236 0_8

PR234 1/F_6

ISL95857_VIN

ISL95857_VCC

34

33

VIN

VCC

RTN_A18ISUMP_A19ISUMN_A

17

ISL95857_FB_A

ISL95857_RTN_A

PR55

12

2K/F_4

SP@2.87K_1%_4

PC42 330p/50V_4

PR235

ISL95857_PROG1

ISL95857_PROG2

31

PROG132PROG2

PWM_C

FCCM_C

ISUMN_C

ISUMP_C

RTN_C

FB_C

COMP_C

IMON_C

PWM_A

FCCM_A

20

ISL95857_ISUMN_A

12

PR58

PC44

PR233 1.96K_1%_4

U22 : PR231 2.87k Ohm

U42 : PR231 2.87k Ohm

3

9.31K_1%_4

30

29

28

27

26

25

24

23

22

21

499/F_4

1000P/50V_4

PC48

PR232

88.7K_1%_4

ISL95857_PWM_C

ISL95857_FCCM_C

ISL95857_ISUMN_C

ISL95857_RTN_C

ISL95857_FB_C

ISL95857_COMP_C

ISL95857_IMON_C

ISL95857_PWM_A

ISL95857_FCCM_A

PC62

2200p/50V_4

1 2

0.1u/25V_4

PR65 0_4

PR68 0_4

PR71 0_4

PR243

267/F_4

SVID near PU1

PR36

PR225

SP@1.54K_1%_4

PC24

PC28

2200P/50V_4

PR220

1 2

SP@267/F_4

12

PC27 U42@0.022U/25V_4

12

PC26 U42@0.022U/25V_4

U22 : PR34 0 ohm

U42 : PR34 Unstuff

ZRW REV:F add 1000p

VR_SVID_ALERT#_VCORE[5]

12

H_PROCHOT#[2,28,29]

IMVP_PWRGD[2]

2K/F_4

PMON[29]

SP@470P/50V_4

PR34 SP@0_4

FCCM_B[35]

PWM1_B[35]

PWM2_B[35]

Rail B

4

H_CPU_SVIDDAT[5]

H_CPU_SVIDCLK[5]

PR224 SP@93.1K_1%_4

D D

ISUMP_B[35]

ISUMN_B[35]

PR94 0_4

PR90 0_4

Close to
VCORE Choke

0.1U/25V_4

VCORE_SENSE[5]

C C

B B

VCORESS_SENSE[5]

PC34 330P/50V_4

PR249 13.7K/F_4

1 2

PC33 33P/50V_4

PC169

3300P/50V_4

*0.01U/50V_4

0.01U/50V_4

PR222

2.61K/F_4

1 2

PR221

11K/F_4

1 2

PR265
10K/F_4_3435NTC

1 2

PC21

PR223

3K/F_4

PC22

PC32

12

PC30

Close to
VCORE MOS

PR262

470K_4_4700NTC

PR260 27.4K/F_4

12

PC31
*0.01U/50V_4

PC29

2 1

0.022U/25V_4

SP@0.1U/25V_4

12

12

PR35

1K/F_4

PC23

220p/50V_4

U22 : PC24 470pF

U42 : PC24 560pF

PR27

1 2

1K/F_4

KBL U-Line - 15W/28W

U22

(1+1+1 Phase)

Vcore

Icc Max：32A
Icc TDC：21A
OCP：38.4A

A A

VCCGT

Icc Max：31A
Icc TDC：18A
OCP：37A

VCCSA

Icc Max：4.5A
OCP：10A

5

U42

(2+1+1 Phase)

Vcore

Icc Max：64A
Icc TDC：42A
OCP：76.8A

VCCGT

Icc Max：28A
Icc TDC：12A
OCP：37A

VCCSA

Icc Max：5A
OCP：10A

U22 : PC30 CH41002KB93 0.1uF/10V

U22 : PR34 CS00002JB38 0 ohm

U22 : PR225 CS21542FB00 1.54K U42 : PR225 CS23092FB00 3.09K

U22 : PR224 CS38872FB18 88.7K

U22 : PC26 Unstuff U42 : PC26 CH3224K1B01 0.022U/25V

U22 : PC27 Unstuff U42 : PC27 CH3224K1B01 0.022U/25V

PC45

0.1u/25V_4

Rail C

PWM_C [36]

FCCM_C [36]

PC61

0.1u/25V_4

PWM_A [35]

FCCM_A [35]

PR239

PC54

0.1u/25V_4

PR63 0_4

PR66 0_4

PR72 0_4

PR74

1 2

1K/F_4

PC47

*0.01u/50V_4

PC49
*0.01u/50V_4

PC50

0.01u/50V_4

Rail A

U42 : PC30 CH4152K9B02 0.15uF/10V

U42 : PR34 Unstuff

U42 : PR220 CS13322FB10 332 ohmU22 : PR220 CS12672FB02 267 ohm

U42 : PR224 CS39312FB15 93.1K

U42 : PR217 CS41003F932 100KU22 : PR217 Unstuff

PC55

PR77

1 2

2200p/50V_4

1K/F_4

PR238 SP@392_1%_4

U22 : PR238 392Ohm

U42 : PR238 392 Ohm

1 2

113K_1%_4

PC57 33P/50V_4

PC56 330P/50V_4

12

PC53
10n/50V_4

1 2

2

PR70
11K/F_4

PC64

12

PR240

PC184

Close to
VCCGT Choke

PC52

0.1u/25V_4

0.015UF/16V_4

12

2.49K/F_4

PR241

2200P/50V_4

PC185

PR266
10K/F_4_3435NTC

1 2

12

PR69

2.61K/F_4

VCCGT_SENSE [5]

VSSGT_SENSE [5]

IMVP8 Vcore Controller

Rail A（1 phase）：VCCGT
Rail B（2 phase）：VCORE
Rail C（1 phase）：VCCSA

Close to
VCCSA Choke

12

PR75

PC60

11K/F_4

0.047U/10V_4

1 2

12

PR73

PC63

PR76 1.74K_1%_4

ISUMN_A [35]

ISUMP_A [35]

301/F_4

PC65

*0.01U/50V_4

1000P/50V_4

PC58
*0.01U/50V_4

PC59

0.01U/50V_4

*2K/F_4

*680P/50V_4

ISUMN_C [36]

PR264
10K/F_4_3435NTC

1 2

12

PR78

2.61K/F_4

ISUMP_C [36]

PR93 0_4

PR89 0_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

PROJECT :

CPU_CORE (ISL95859HRTZ-T)

CPU_CORE (ISL95859HRTZ-T)

CPU_CORE (ISL95859HRTZ-T)

1

VSA_SENSE [5]

VSASS_SENSE [5]

Z8VR

Z8VR

Z8VR

34 46Thursday, June 22, 2017

34 46Thursday, June 22, 2017

34 46Thursday, June 22, 2017

34

1A

1A

1A

5

4

3

2

1

VIN[20,23,24, 29,30,31,33,34,36,37,38,39]

+VCCCORE[5]

+VCCGT[5]

+5V_S5[27,30,33,34,36,38,39, 40]

U22 : PR217 Unstuff U42 : PR217 CS41003F932 100K

35

VCORE

D D

PR82
0_6

12

+5V_S5

PC191

PWM1_B[34]

FCCM_B[34]

PR258 0_4

PR259 0_4

PR83
U42@0_6

12

PC192

U42@4.7U/6.3V_6

PR254 U42@0_4

PR255 U42@0_4

4.7U/6.3V_6

Rail B

C C

B B

VCORE = 1 Phase for U22 , 不上件
VCORE = 2 Phase for U42 , 上件

+5V_S5

Rail B

PWM2_B[34]

FCCM_B

VCORE_VCC

VCCGT_VCC2

PU15 AOZ5049QI

23

PVCC

24

VCC

1

PWM

2

FCCM

PGND#2

21

PU13 U42@AOZ5049QI

23

PVCC

24

VCC

1

PWM

2

FCCM

PGND#2

9

21

6

VIN#1

22

VIN#2

4

GH

VCORE_VBST

3

BOOT

5

VSWH#1

VCORE_PHASE

13

VSWH#2

19

GL#1

20

GL#2

PGND#1

9

6

VIN#1

22

VIN#2

4

GH

VCCGT_VBST2

3

BOOT

5

VSWH#1

VCCGT_PHASE2

13

VSWH#2

19

GL#1

20

GL#2

PGND#1

1 2

PR253 0_6

PR251 U42@0_6

PC71

12

12

1 2

12

12

PC188
U42@0.1u/50V_6

12

12

+VIN_VCCCORE

10u/25V_8

PC190

0.1u/50V_6

ISUMP_B[34]

ISUMN_B[34]

PC194

U42@10u/25V_8

PR85
U42@2.2/F_6

PC75
U42@1000P/50V_4

1 2

12

12

ISUMN_B

PC195

PR87

2.2/F_6

PC77
1000P/50V_4

ISEN1_B

1 2

ISUMP_B

ISEN2_B

10u/25V_8

PR245 3.65K/ F_6

PR217 U42@100K/F_6

PC70

U42@10u/25V_8

PR215 U42@3.65K/F_6

PR214 U42@100K/F_6

PR213 U42@10/F_6

+VIN_VCCCORE

PC74

0.1U/50V_6

1 2

1 2

1 2

PR244 10/F_6

PC69

U42@0.1U/50V_6

1 2

1 2

1 2

PC199

2200P/50V_4

0.15uH_7X7X4

1 2

+VIN_VCCCORE

U42@0.15uH_7X7X4

1 2

PJ9008

0.001_1%_3720

PL10

3

4

U22 : PR217 Unstuff

U42 : PR217 CS41003F932 100K

PR218 *100K/F_4

PC72

U42@2200P/50V_4

PL8

3

4

PR219 *U42@100K/F_4

VIN

12

+

PC182

33U/25V_6x4.5

DCR=0.66mOhm

PC208

PC205

22u/6.3V_8

0.1u/16V_4

1 2

DCR=0.66mOhm

PC214

PC216

U42@0.1u/16V_4

U42@22u/6.3V_8

1 2

PC210

22u/6.3V_8

ISEN2_B [34]

+VCCCORE

PC215

U42@22u/6.3V_8

ISEN1_B [34]

+VCCCORE

+

+

PC78

PC203

330u/2V_7343

330u/2V_7343

+

PC207

U42@330u/2V_7343

VCCGT

PJ9007

PC198

10u/25V_8

PR212 1/F_6

PC193

0.1U/50V_6

1 2

PR216 3.65K/F_6

1 2

+VIN_VCCGT

0.15uH_7X7X4

1 2

PC197

2200P/50V_4

PL9

3

4

2

0.001_1%_3720

VIN

12

+

PC181

*33U/25V_6x4.5

+VCCGT

DCR=0.66mOhm

PC211

0.1u/16V_4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

+

PC209

PC212

PC213

22u/6.3V_8

22u/6.3V_8

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

VCORE/VCCGT (ISL95808HRZ-T)

VCORE/VCCGT (ISL95808HRZ-T)

VCORE/VCCGT (ISL95808HRZ-T)

330u/2V_7343

Z8VR

Z8VR

Z8VR

35 46Thursday, June 22, 2017

35 46Thursday, June 22, 2017

35 46Thursday, June 22, 2017

1

PR84
0_6

12

+5V_S5

PC196

Rail A

PWM_A[34]

FCCM_A[34]

A A

5

4.7U/6.3V_6

PR256 0_4

PR257 0_4

VCCGT_VCC1

4

PU14 AOZ5049QI

23

PVCC

24

VCC

1

PWM

2

FCCM

PGND#2

21

6

VIN#1

22

VIN#2

4

GH

VCCGT_VBST1

3

BOOT

VSWH#1
VSWH#2

GL#1
GL#2

PGND#1

9

PR252 0_6

5

VCCGT_PHASE1

13

19
20

3

1 2

1 2

PC73

10u/25V_8

12

12

PC189

0.1u/50V_6

12

PR86

2.2/F_6

12

PC76
1000P/50V_4

ISUMP_A[34]

ISUMN_A[34]

1A

1A

1A

5

4

3

2

1

36

VIN[20,23,24,29,30,31,33,34,35,37,38,39]

D D

VCCSA

PR64

12

Rail C

FCCM_C[34]

PWM_C[34]

0_6

PC180

4.7U/6.3V_6

PR242 0_4

PR237 0_4

VCCSA_VCC

PU12

6

VCC

7

FCCM

3

PWM

9

E_PAD

4

GND

ISL95808

+5V_S5

C C

+VCCSA[5]

+5V_S5[27,30,33,34,35,38,39,40]

UGATE

BOOT

PHASE

LGATE

VCCSA_DRVH

1

VCCSA_VBST

2

VCCSA_SW

8

VCCSA_DRVL

5

PQ32
AON7410

PR246 0_6

PC183

0.1u/50V_6

PQ31
AON7752

PJ9024

0.001_1%_3720

VIN

VCCSA

52

1 2

4

12

3

1

12

52

4

3

1

PC186

10u/25V_8

12

PR81

2.2/F_6

12

PC68
1000P/50V_4

1 2

PC66

10u/25V_8

PC187

PL7

0.47uH_7X7x3

1 2

3

4

PC67

0.1U/50V_6
2200P/50V_4

DCR=4.2mOhm

Icc TDC PL2：5A

Icc Max：5A

+VCCSA

OCP：6A

Fsw：800KHz

VCCSA L/L：

PC204

PC202

0.1u/16V_4

PC206

22u/6.3V_8

22u/6.3V_8

R_DC_LL：10.3mV/A

R_AC_LL：10.3mV/A

B B

A A

5

4

ISUMP_C[34]

ISUMN_C[34]

3

1 2

PR248 3.65K/F_6

1 2

PR247 1/F_6

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

VCCSA (ISL95808HRZ-T)

VCCSA (ISL95808HRZ-T)

VCCSA (ISL95808HRZ-T)

PROJECT :

1

Z8VR

Z8VR

Z8VR

36 46Thursday, June 22, 2017

36 46Thursday, June 22, 2017

36 46Thursday, June 22, 2017

1A

1A

1A

5

4

3

2

1

+1.8V_S5

1.8Volt +/- 5%
TDC : 2.61A
PEAK : 3.48A

0.001_1%_3720

S5_ON [28,30]

3

2

1

Width : 120mil

+1.8V_S5

PJ9020

PC9078

0.1u/25V_4

PQ15
2N7002K

PC9079

22u/6.3V_6

SYS_SHDN# [2,28,30]

1 2

PQ16
DTC144EU

1 3

PR156 0_4

12

PC112

10u/6.3V_6

VIN

12

PR116
1M_6

MAINON_ON_G

12

PR118
1M_6

PC113

0.1u/50V_6

2

+3VPCU

12

2

PR120
*100K/F_6

MAINON

PR151 0_8

MAINON[24,28,30,33]

MAINON

+3V

D D

Check PU high with HW

HWPG_1.8VS5[28]

+3VPCU

C C

B B

PR66982
100K_1%_4

PJ9021

0.001_1%_3720

PC9075

PR66984
0_5%_4

8068PG_1.8V

PR66987
10_5%_6

8068SVIN_1.8V

PC9082
10u/6.3V_6

PC9080

0.01u/50V_4

1 2

PC9083
1u/6.3V_4

4

9

10

8

11

PU9004

POK

VIN#1

VIN#2

VCC

GND

M5671RE1U

Thermal protection

Need fine tune
for thermal protect point

Note placement position

TEMP=85C

12

PR117

1.47K/F_4

LM393_PIN2

S5_ON

PR267

10K/F_4_3435NTC

1 2

3

2

PQ20
2N7002K

1

*2200p/50V_4

S5_ON

VLVL

NC#1

SW#1

SW#2

NC#2

12

12

FB

EN

PR114
200K/F_4

2.469V

PR115
200K/F_4

PR66983

*2.2_5%_6

1

2

3

7

6

5

2

PQ18

DTC144EU

8068LX_1.8V

8068NC_1.8V

8068FB_1.8V

8068EN_1.8V

VIN

84

3

+

2

-

1 2

PC9076
*68p/50V_4

PC9081
*0.1u/16V_4

21

PD5
DA2J10100L

12

PR119
1M_6

1 3

PU4A
AS393MTR-E1

PL9003

1uH_7x7x3

*22p/50V_4

2

1 2

1

PC9077

PR66988
0_5%_4

1

3

12

PC91

0.1u/50V_6

8068FB_1.8V_S

R1

R2

PQ17
AO3409

PR283
0_6

PR66985 0_5%_4

PR66986
20K_1%_4

Vo=0.6*(R1+R2)/R2

PR66989
10K_1%_4

=1.8V

12

PR284
200K_6

PC92

0.1u/50V_6

1 2

1 2

PC153 1u/6.3V_4

1 2

PC110 *1u/10V_4

PR154

100K_4

1 2

12

PR106
*22_8

3

PQ12
*2N7002K

1

+5VPCU

PR143
0_4

12

1 2

PC123

*0.1u/50V_6

PR153 Change to
220 ohm for bo bo
sound issue.

+5V+3V

2

12

3

1

4

2

3
8
9

PR126
*220_8

PQ19
*2N7002K

PU7
G9661MF11U

PGOOD

VPP

VEN

VIN
GND#1
GND#2

1

6

VO

5

NC

ADJ

7

VFB=0.8V

Vo =0.8(1+R1/R2)
=1.5V

+VCCIO

12

PR111
22_8

3

2

PQ14
2N7002K

1

Check PU high with HW

1 2

R1

R2

2

PR155 100K_4

12

PR152
30K/F_4

12

PR153
34K/F_4

12

3

1

PR298
*22_8

PQ41
*2N7002K

PR145 0_8

12

PC111
10u/6.3V_6

+3V

1 2

2

HWPG_1.5V [28]

VIN+2.5V

12

PR59
1M_6

MAIND

3

PQ6
2N7002K

1

+1.5V

+1.5V

1.5Volt +/- 5%
TDC : 0.49A
PEAK : 0.66A
Width : 20mil

PC51
2200p/50V_4

1 2

ZRW Rev:D Stuff

37

MAIND [31,33]

5

A A

For EC control thermal protection (output 3.3V)

5

+

7

6

-

PU4B
AS393MTR-E1

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

4

3

2

Date: Sheet of

PROJECT :

+1.8V/+1.5V/Thermal Protect

+1.8V/+1.5V/Thermal Protect

+1.8V/+1.5V/Thermal Protect

1

Z8VR

Z8VR

Z8VR

1A

1A

37 46Thursday, June 22, 2017

37 46Thursday, June 22, 2017

37 46Thursday, June 22, 2017

1A

5

4

3

2

1

VGPU_CORE

VIN [20,23,24,29,30,31,33,34,35,36,37,39]
+VGPU_CORE [14]
+5V_S5 [27,30,33,34,35,36,39,40]
+3V [2,4,6,7,8, 9,11,12,14,15,16,17,19,20,21,22,23,24,25,26,27,28,30,31,33,34,37,39,40]
+1V8_AON [14,16,17,39, 40]

D D

PR9001
EV@1_5%_6

+5V_S5

PWM-VID[17]

+3V

+1V8_AON

TP4401

C

Fsw: 300KHz

PR9000
EV@1_5%_6

PC9004
EV@1u/25V_6

PR9005 N16@10K_1%_4

PR9008 EV@0_5%_4

PR9009 N17@10K_1%_4

PR9015 EV@0_5%_4

PR9017 EV@0_5%_4

8813VREF

R2

PR9021

SP@20.5K_1%_4

R3

PC9025

SP@4700p/25V_4

R4

R5

4

PR9002
EV@499K_1%_4

VREF=2V

R1

PR9023
SP@6.19K_1%_4

PR9024
SP@4.32K_1%_4

PR9027
SP@16.5K_1%_4

PR9030
SP@309_1%_4

PR9033

EV@10K_1%_4

8813REFADJ

PR9007

3V_MAIN_PWGD[16,40]

+3V_MAIN_EN[16,17,40]

C C

+1.8_GFX_MAIN

DGPU_PSI[17,39]

+1V8_AON

PR67234 *N17@0_5%_4

N16@1K_1%_4

PD9000
*N17@RB500V-40

1

PR9012
N17@1K_1%_4

PR9016
EV@0_5%_4

PR9018
*N17@12K_1%_4

2

PR9022
*N17@10K_1%_4

PC9013
EV@0.22u/10V_4

+VIN_VGPU_CORE

GPU_PWR_GD[15,40]

RT8813DGQW

PSI

B B

0V ~ 0.4V

0.8V ~ 1V

1.4V-5.5V

NV16 Config : B

R1

R2

R3

A A

R4

R5

C

Mode

1 Phase DCM

1 Phase CCM

2 /3Phase CCM

20K

20K

2K

18K

0 ohm

2.7nF

5

NV17 Config : Type2+

R1

R2

R3

R4

R5

C

6.19K

20.5K

4.32K

16.5K

0.309K

4.7nF

8813PVCC

PC9000
EV@2.2u/10V_4

8813TON

8813PSI

8813VID

8813VREF

PC9023
EV@0.1u/16V_4

8813REFIN

PC9026

EV@1500p/50V_4

8813VREF

PU9000 EV@RT8813DGQW

21

9

16

3

4

5

8

6

7

13

PVCC

TON

PGOOD

EN

PSI

VID

VREF

REFADJ

REFIN

TSNS/ISEN3

UGATE1

BOOT1

PHASE1

LGATE1

VCC/ISEN1

UGATE2

BOOT2

PHASE2

LGATE2

TALERT/ISEN2

VSNS

RGND

PWM3

2

1

24

23

15

17

18

19

20

14

11

10

12

SS

22

25

GND

PR9006
EV@1_5%_6

PC9008
EV@0.22u/25V_6

PR9014
EV@1_5%_6

PC9020
EV@0.22u/25V_6

PC9030
*EV@56p/50V_4

8813UGATE1_1

PR9011
EV@14.7K_1%_4

3

8813UGATE1

8813BOOT1

8813PHASE1

8813LGAT1

8813ISEN18813EN

PC9014
*EV@0.22u/10V_4

8813UGATE2

8813BOOT2

8813PHASE2

8813LGAT2

8813ISEN2

8813VOUT1

PC9027

EV@56p/50V_4

8813RGN

PC9029

EV@56p/50V_4

8813ILIM

PR9032 EV@14.7K_1%_4

PR9034 EV@0_5%_4

Rds(on)=3mohm(MAX)

PR9013
EV@10K_1%_4

8813UGATE2_1

PR9025
*EV@10K_1%_4

OCP=74A

3

D1

G1

1

S1/D2

2

PQ9000
EV@AOE6936

G2

8

+5V_S5

1

2

PQ9001
EV@AOE6936

8

Rds(on)=3mohm(MAX)

PC9028
*EV@100p/50V_4

D2/S1

S2

G1

S1/D2

G2

+VIN_VGPU_CORE

+VIN_VGPU_CORE

4

9

10

4

3

D1

D2/S1

S2

10

5
6
7

9

5
6
7

PR9028
EV@0_5%_4

PR9029
EV@0_5%_4

PC9001

EV@10u/25V_8

8813PHASE1

PR9004
*EV@2.2_5%_6

PC9012
*EV@2200p/50V_4

8813PHASE2

PR9019
*EV@2.2_5%_6

PC9024
*EV@2200p/50V_4

PC9005

EV@10u/25V_8

PC9015

EV@10u/25V_8

PR9026
EV@100_1%_4

PR9031
EV@100_1%_4

PC9002

*EV@10u/25V_8

PC9016

PC9017

EV@10u/25V_8

+VGPU_CORE

VGA_VCCSENSE [14]

VGA_VSSSENSE [14]

routing in parallel

PC9003

*EV@10u/25V_8

EV@0.1u/25V_4

PC9006

EV@2200p/50V_4

EV@0.22uH/23A_7x7x3

1 2

Isat=40A
DCR(MAX)=2.8mohm

+VIN_VGPU_CORE

PC9019

PC9018

EV@0.1u/25V_4

PJ9000
EV@0.001_1%_3720

PL9001

EV@2200p/50V_4

EV@0.22uH/23A_7x7x3

1 2

Isat=40A
DCR(MAX)=2.8mohm

+

PL9000

VIN

PC9007

EV@33u/25V_D6.3H4.5

+VGPU_CORE

+

+

PC9011

EV@330u/2V_7343H1.9

+VGPU_CORE

PC9022

EV@22u/6.3V_8

PC9010

EV@330u/2V_7343H1.9

+

PC9021

EV@330u/2V_7343H1.9

PC9009

EV@22u/6.3V_8

N16S-GTR (23W/GDDR5)

OpenVreg Config : B
Vboot : 0.9V

EDP-C:26.5A
EDP-P:53A
OCP:74A
FSW:300KHz

N17S-G1 (23W/GDDR5)

OpenVreg Config : Type2+
Vboot : 0.8V

EDP-C:27.9A
EDP-P:62.2A
OCP:74A
FSW:300KHz

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

PROJECT :

+NVVDD (RT8813DGQW)

+NVVDD (RT8813DGQW)

+NVVDD (RT8813DGQW)

1

38

Z8VR

Z8VR

Z8VR

38 47Thursday, June 22, 2017

38 47Thursday, June 22, 2017

38 47Thursday, June 22, 2017

1A

1A

1A

5

4

3

2

1

PC9041

VIN

+1.35V_GFX

39

N16S-GTR (23W/GDDR5)

OpenVreg Config : B

PC9042

*EV@330u/2V_7343H1.9

Vboot : 0.9V

EDP-C:4.2A
EDP-P:6.8A
OCP:12A

+

+

PC9036

PC9037

*EV@22u/6.3V_8

*EV@22u/6.3V_8

EV@330u/2V_7343H1.9

1.35V_GFX

D D

PR9035

+5V_S5

+3V

HWPG_1.35VGFX[16]

FBVDDQ_EN[15]

1.03_GFX_PGD[40]

C C

EV@1_5%_6

PR9040 EV@10K_1% _4

PR9037 EV@0_5%_4

PR9041 EV@2.2 K_4

PR66999 *EV@0_5%_4

8816APVCC

PC9038
EV@2.2u/10V_4

8816APG

8816AEN

PC9043
EV@0.22u/10V_4

VIN [20,23,24,29,30,31,33, 34,35,36,37,38]
+1.35V_GFX [15,18]
+5V_S5 [27,30,33,34,35,36,38,40]
+3V_S5 [2,3,4, 6,7,8,9,22,24,25,26,28,30,33]
+1V8_AON [ 14,16,17,38,40]
+3V [2,4, 6,7,8,9,11,12,14,15,16,17,19,20, 21,22,23,24,25,26,27,28,30,31,33,34,37,38,40]

PU9001 EV@RT8816AGQW

PR9036
EV@1_5%_6

18

PVCC

13

PGOOD

3

EN

UGATE1

BOOT1

PHASE1

LGATE1

2

1

20

19

8816AUGATE1

8816ABOOT1

8816APHASE1

8816ALGATE1

8816AUGATE1_1

PC9039
EV@0.22u/25V_6

+VIN_1.35VGFX

PC9031

EV@10u/25V_8

PQ9002

2

AON6978

D1

D1

D1

G1

1

S1/D2

9

8816APHASE1

8

G2

567

PR9042
*EV@2.2_5%_6

S2S2S2

PC9044
*EV@2200p/50V_4

+VIN_1.35VGFX

PC9033

PC9032

EV@10u/25V_8

EV@0.1u/25V_4

PL9002

EV@0.47uH/17.5A_7x7x3

1 2

Isat=26A
DCR(MAX)=4.2mohm

PC9034

PJ9001
EV@0.001_1%_3720

PC9035

EV@0.1u/25V_4

EV@2200p/50V_4

PC9040

EV@22u/6.3V_8

FSW:400KHz

4

RT8816AGQW

PSI

0V to 0.4V

0.7V to 0.88V

1.08V to 1.35V

1.6V to 5.5V

B B

Mode

1 Phase DCM

1 Phase CCM

2 Phase DCM

2 Phase CCM

+3V_S5

+1V8_AON

DGPU_PSI[17,38]

Remove N16 controlled Pin 02/06

PR9043 N16@30.1K_1%_4

PR9044 N17@12K_1%_4

PR9045 *EV@0_5%_4

1 Phase Only Setting:
(1)PSI=0.823V(N16)
(2)PSI=0.818V(N17)

8816AVREF

PR9049

EV@10.2K/F_4

PR9052

EV@21.5K/F_4

Fsw : 400KHz

A A

5

+VIN_1.35VGFX

PR9061
EV@1_5%_6

PC9051

EV@1u/25V_6

PR9062
EV@402K_1%_4

8816APSI

PR9046
EV@10K_1%_4

VREF=2V

8816AVREF

PC9045
EV@0.1u/16V_4

8816AREFIN

PC9048
EV@100p/50V_4

8816ATON

PC9052

4

PSI

UGATE2

14

Rds(on)=5mohm(MAX)

N17S-G1 (23W/GDDR5)

OpenVreg Config : Type2+
Vboot : 0.8V

EDP-C:4.6A
EDP-P:TBD (預估TDC*1.5=7A)
OCP:12A
FSW:400KHz

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

+FBVDDQ_MEM (RT8816AGQW)

+FBVDDQ_MEM (RT8816AGQW)

+FBVDDQ_MEM (RT8816AGQW)

Z8VR

Z8VR

Z8VR

39 47Thursday, June 22, 2017

39 47Thursday, June 22, 2017

1

39 47Thursday, June 22, 2017

1A

1A

1A

PR9047

EV@22_5%_8

PQ9004

EV@2N7002K

+1.35V_GFX

3

1

2

+5V_S5

PR9048
EV@100K_1%_4

PR9050
EV@1M_5%_4

3

2

1

PQ9005
EV@DMG1012T-7

8816AEN

5

8

6

7

9

VID

VREF

REFADJ

REFIN

TON

BOOT2

PHASE2

LGATE2

RGND

VSNS

OCSET

15

16

17

10

11

12

8816ARGDN

8816AVSNS

8816ASS

PR9060
EV@51K_1%_4

PC9046
*EV@56p/50V_4

PC9049
*EV@56p/50V_4

PC9050
*EV@56p/50V_4

PC9047
*EV@100p/50V_4

PR9053
EV@0_5%_4

PR9055
EV@0_5%_4

PR9058
EV@100_1%_4

TP8070

For N17 1.35GFX_Sense (reference ZGL) page 15

+1.35V_GFX

OCP=12A

21

*EV@0.1u/25V_4

GND

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

3

2

Date: Sheet of

1

2

3

+1.8V_S5 [8,9,10,37]
+1.8_GFX_MAIN [14,15,16]
+1V8_AON [14,16,17,38,39]

4

5

+5VPCU [27,30,31,37]
+1.2VSUS [3,5,11,12,33]
+1.03_GFX [14,15, 16]
+5V_S5 [27,30,33,34, 35,36,38,39]
+3V [2,4,6,7,8,9, 11,12,14,15,16,17,19,20,21,22,23,24,25,26,27,28, 30,31,33,34,37,38,39]

6

7

8

40

N16S-GTR

+3V_GFX

A A

TDC : 0.06A
Width : 20mil

PR9084 For N17
use only

+3V_GFX

PR9066

N16@0_5%_8

+1.8V_S5 +1.8V_S5

+3VPCU

PR9064

PR9063

N17@0_5%_8

N16@0_5%_8

PR9065

N17@0_5%_8

PR9084

DGPU_PWR_EN[4]

+3V_MAIN_EN[16,17,38]

+1.8_GFX_MAIN

PR67231
N17@22_5%_8

3

PQ9084
N17@2N7002KW

1

+1V8_AON

N17@0_5%_8

PR9067

N17@0_5%_8

PR9076
N17@10K_1%_4

+5VPCU

EV@10u/6.3V_6

+5VPCU

PR9071

N16@0_5%_4

PR9072

N17@0_5%_4

+1.2VSUS

PR9078
N17@0_5%_4

PC9055

PJ9002
EV@0.001_1%_3720

PC9065

EV@0.1u/16V_4

PU9003
EV@G9336ADJTP1U

3

4

1

PC9072
EV@0.1u/16V_4

EV@0.1u/16V_4

PR9069
EV@0_5%_4

PC9061

*N16@0.1u/16V_4

PC9064

*N17@820p/50V_4

PC9066

PGD

EN

VCC

EV@10u/6.3V_6

DRV

ADJ

GND

2

+1.8_GFX_MAIN

+1.8V_MAIN
TDC : 1.13A
PEAK : 1.5A
Width : 60mil

A2

B B

PQ9083

N17@LTC044EUBFS8TL

+3V_MAIN_EN

2

PR67233

*N17@100K_1%_6

C C

VIN

PR67230
N17@1M_5%_6

+3V_MAIN_EN_G

2

PR67232
N17@1M_5%_6

1 3

Check N16 Power Good

Check PU high wit h HW

GPU_PWR_GD[15,38]

3V_MAIN_PWGD[16,38]

D D

1.03_GFX_PGD[39]

PR9079
N17@0_5%_4

PR9083
N16@1K_1%_4

PC9073
*N17@0.1u/16V_4

PC9074
N16@0.22u/10V_4

PC9056

PC9059

EV@0.1u/16V_4

5

6

5

R2

PC9053
EV@1u/25V_4

13
14

EV@1000p/50V_4

PQ9008
EV@AON7408

D

S

G

4

9336DRV

9336ADJ

PR9082
EV@124/F_4

4

3

VOUT1#1
VOUT1#2

VBIAS

ON1

PC9062

3
2
1

1

VIN1#22VIN1#1

VIN2#16VIN2#2

PU9002

EV@AOZ1331DI

CT1

12

10

PR9080
EV@47_1%_4

PR9081
EV@133_1%_4

R1

N16S:Vo=(1+R1/R2)*0.5=1.03V
N17S:Vo=(1+R1/R2)*0.5=1.03V

N16S

N17S

7

OUT2#1
OUT2#2

GND#1

GND#2

ON2

CT2

PC9063
N17@1000p/50V_4

PEX_VDD_S

PC9067

EV@10u/6.3V_6

PC9071
EV@0.01u/50V_4

PEX_VDD_S

R1 R2

133 ohm

133 ohm

PC9054

N17@1u/25V_4

8
9

11

15

5

PC9068

EV@10u/6.3V_6

PD9001
EV@1SS355

PC9057

N17@0.1u/16V_4

PR9070

N17@0_5%_4

PC9060

*N17@0.1u/16V_4

PC9069

EV@0.1u/16V_4

+3V

21

124 ohm

124 ohm

1V8_AON_S

DGPU_PWR_EN

PC9058

N17@10u/6.3V_6

PR9068

N17@0_5%_8

N16S-GTR N17S-G1

+1.05V
TDC : 0.8A
PEAK : 2.1A
Width : 80mil

+1.03_GFX

PJ9003
EV@0.001_1%_3720

+

PC9070

PR9075
EV@10K_1%_4

PQ9011
EV@2N7002K

3

2

1

*EV@220u/2V_7343H1.9

PQ9009
EV@2N7002K

+1V8_AON

+1V
TDC : 0.9A
PEAK : 1.1A
Width : 40mil

PR9073
EV@5.6_5%_8

3

2

1

+5V_S5

PR9074
EV@100K_1%_4

N17S-G1N17S-G1

+1.8V_AON
TDC : 1.13A
PEAK : 1.5A
Width : 60mil

3

PR9077

1

EV@1M_5%_4

PQ9010
EV@DMG1012T-7

2

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

1

2

3

4

5

Date: Sheet of

6

PROJECT :

+1.8V_AON (A OZ1331DI)

+1.8V_AON (A OZ1331DI)

+1.8V_AON (A OZ1331DI)

7

Z8VR

Z8VR

Z8VR

40 47Thursday, June 22, 2017

40 47Thursday, June 22, 2017

40 47Thursday, June 22, 2017

1A

1A

1A

8

5

Battery Mode

Non Deep Sx

MAINON

+5V

+3V

MAINON

9

8

21

22

17

11

10

8

18

19

23

24

24

12

2929

21

28

27

29

21

12

PG

MAINON

SUSON

PG

PG

+1V_S5

+5V_S5

+3V_S5

S5_ON

+1.2VSUS

+VDDQ

+VDDQ_VTT

HWPG_VDDR

26

+1.5V

HWPG_1.5V

HWPG_1VS5

+1V_S5

+5VPCU

3

+3VPCU

D D

3

S5 PWR

VIN

1

DDR VDDQ
VR

S3

S5

C C

3

DDR_VTTT_PG_CTRL

+3VPCU

1.5V
VR

EN

VIN

1

RUN PWR

MOS1

MOS2

MOS3

G

B B

+5VPCU

3

+3VPCU

3

+1V_S59 +VCCIO

+1V_S5

VR

A A

EN

4

VIN

3V/5V

VR

EN2

1

EN1

NBSWON#

3 3

+3VPCU +5VPCU

5V_LDO

2

PWR
BTN

7

30

HWPG

HWPG_VDDR

HWPG_1V_S5

HWPG_1.5V

SVID

+1VSUS

VIN

1

IMVP
VR

0 ohm

EN

PG

+1V_VCCST

+VCC_CORE

+VCCSA

+VCCGT

IMVP_PWRGD

VRON

EC_PWROK

31C

+15V

32b

VL

33

33

33

34

32a

VRON

2

4

EC

MAINON

1721

SUSON

9

3

S5_ON

+1V_S5_ON

8

6

DPWROK

13

RSMRST#

14

ACPRESENT

DNBSWON#

15

SUSC#

SUSB#

PCH_SUSACK#

PCH_SUSPWARN#

PCH_SLP_SUS#

31b

PCH_PWROK

35

38

31C

31C

12

31b

36

16
20

IMVP_PWRGD

EC_PWROK

EC_PWROK

HWPG_1VS5

PCH_PWROK

SYS_PWROK

HWPG+1ms

2

Delay DSW power well 10ms

VCCST_PWRGD

31a

31C

EC_PWROK

PCH_CLK

PLTRST#

VCCST_PWRGD_EN

36

SYS_PWROK

10K ohm

1

CHARGER

DPWROK

RSMRST#

ACPRESENT

PWRBTN#

SLP_S4#

SLP_S3#

SUSACK

SUSWRAN

SLP_SUS#

VCCST_PWRGD

PCH_PWROK

PLTRST#

SYS_PWROK

38

PLTRST#

PROCPWRGD

SVID

SVID

37

BAT-VVIN

Battery

3

+3VPCU or +3V_S5

DSW PWR

VCCPRIM PWR

VCCMPHY PWR

HSIO PWR

PCH

CORE PWR

VCCSRAM PWR

VCCPGPPA PWR
VCCPGPPB PWR
VCCPGPPC PWR
VCCPGPPD PWR
VCCPGPPE PWR
VCCPGPPG PWR
VCCPGPPF PWR

CORE PWR

CPU

VDDQ PWR

RESET#

VCCST PWR

VR_READY

SM_PG_CNTL1

VCCST_PWRGD

DDR_PG_CTRL

22

IMVP_PWRGD

VCCST_PWRGD_EN

34

1

SPI PWR

PLL PWR

HDA PWR

VR_ENVRON

32a

41

+1V_S5

+1V_S5

+1.8V_S5

V1_MPHY

V1_MPHY

+1V_S5

+1V_S5

+1.5V

+3V_S5

+1.8V_S5

+VCCIN

+1.2VSUS

+1V_VCCST

37

CPU

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

Power Sequence

Power Sequence

Power Sequence

Z8VR

Z8VR

Z8VR

41 46Thursday, June 22, 2017

41 46Thursday, June 22, 2017

41 46Thursday, June 22, 2017

1

1A

1A

1A

5

4

3

2

1

42

Skylake U Non-Deep Sx Platform
Power on sequence

D D

C C

B B

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

PROJECT :

Power on Sequence

Power on Sequence

Power on Sequence

Z8VR

Z8VR

Z8VR

42 46Thursday, June 22, 2017

42 46Thursday, June 22, 2017

42 46Thursday, June 22, 2017

1

1A

1A

1A

3V_LDO

5

SYS_HWPG

PWRGD5V_LDO

TPS51225

Vin

S5_Vout

S3_Vout

EN1

EN1

5V

3V

實線表defult
虛線表reserve

D D

PWR

VIN

C C

HWPG_1VS5

PWRGD

VIN

EC

B B

Vin

+1V_S5_ON

+1.0V_S5

RT8237CZQW

EN

Vout

+1V_S5

EC

HWPG_VDDR

EC

MAINON

A A

EC

DDR_VTTT_PG_CTRL

S5 EN

S3 EN

PWRGDSUSON

+1.2VSUS

G5316RZ1D

Vin

S5_Vout

S3_Vout

PCH

VIN

5

+5VPCU

+3VPCU

PCH

4

PCH

MAIND

SUSON

MPHY_EXT_PWR

+1.2VSUS

+VDDQ_VTT

+VDDQ

4

S5D

MAIND

S5D

MAIND

3V_MAIN_PWGD

dGPU_PWR_EN

MDV1528Q

AO3404

0 ohm

TPS22965DSGR

MDV1528Q

MDV1528Q

AO3404

MDV1528Q

RT8068AZQW

AO3404

+3V_S5

+VCCIO

+1V_SUS

V1_MPHY

Vin

S5_ON

3

+5V_S5

+5V

+3V_S5

+3V

+1.05V_GFX

+3V_GFX

HWPG_1.8VS5

PWRGD

+1.8V_S5

APW8824

EN

3

Vout

+1.8V_S5

VIN

VIN

VIN

VRON

SVID

VRON

SVID

VRON

SVID

VIN

VIN

+3V_S5

3V_MAIN_PWGD

FBVDDQ_EN

+VCC_CORE

Vin

ISL95857HRTZ-T

+VCCSA

Vin

ISL95857HRTZ-T

+VCCGT

Vin

ISL95857HRTZ-T

2

Vin

Vin

IMVP_PWRGD

PWRGD

IMVP_PWRGD

PWRGD

IMVP_PWRGD

PWRGD

Vin

MAINON

2

PWRGD

VGPU Core

up1658

EN

PWRGD

+1.5V_GFX

NB671GQ-Z

EN

PWRGD

+1.5V

APW8824

EN

VGPU_PWRGD

Vout

HWPG_1.5VGFX

Vout

VIN

VIN

VIN

HWPG_1.5V

Vout

1

+VGPU_CORE

+1.5V_GFX

Vin

PWM_A
FCCM_A

Vin

PWM_C
FCCM_C

Vin

PWM1_B
FCCM_B

AOZ5029QI

EN

AOZ5029QI

EN

AOZ5029QI

EN

Vout

Vout

Vout

+VCCCORE

+VCCSA

+VCCGT

+1.5V

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

Size Doc ument Number Rev

Size Doc ument Number Rev

Size Doc ument Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet

PROJECT :

SKL PCH PWR CONTROL

SKL PCH PWR CONTROL

SKL PCH PWR CONTROL

1

Z8VR

Z8VR

Z8VR

43 46Thursday, June 22, 2017

43 46Thursday, June 22, 2017

43 46Thursday, June 22, 2017

43

of

1A

1A

1A

1

2

3

4

5

6

7

8

+3V_S5

+3V

44

SDRAM

2.2K2.2K

R7

A A

SMB_PCH_CLK

R8

SMB_PCH_DAT

+3V

2N7002DW
Level shift

CLK_SCLK

CLK_SDATA

2.2K2.2K

G-Sensor

XDP

Skylake U

+3V_S5

B B

R9

VGA_MBCLK

W2

VGA_MBDATA

+3V_S5

*2.2K*2.2K

W3

SMB_ME1_CLK

V3

SMB_ME1_DAT

+3V_S5

2.2K2.2K

+3V_S5

*2N7002DW
Level shift

+3V_GFX

C C

2ND_MBCLK

115

2ND_MBDATA

116

00

2.2K2.2K

2.2K2.2K

+3V_MAIN

2N7002DW
Level shift

GFX_SCL

GFX_SDA

VGA

EC

IT8987CX

D D

110

MBCLK

111 MBDATA

1

2

3

+3VPCU

4.7K4.7K

CHARGER

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

4

5

6

Date: Sheet of

7

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

PROJECT :

PROJECT :

SMBUS Block Diagram

SMBUS Block Diagram

SMBUS Block Diagram

Z8VR

Z8VR

Z8VR

44 46Thursday, June 22, 2017

44 46Thursday, June 22, 2017

44 46Thursday, June 22, 2017

8

1A

1A

1A

Model

Z8VR REV:A

Z8VR REV:B

5

Date

First release

03/14

Change SW3 Footprint to Sw-ds-a40e-4p-smt for SMT issue

03/16

Remove C460/C461 for 16G memory module can't power on issue

4

3

2

1

CHANGE LIST

Change SPI ROM GGD 16M P/N to GD25B127DSIGR, original PN is EOL

D D

Z8VR REV:C

C C

according to Intel DG to unstuff R8748,R8749 and R417.

03/28

label PR23 as sp@(UMA and DIS value are different)

04/28

Change 0 Ohm to shortpad

05/15

add EV@ for PQ9002 value that no need to stuff on UMA SKU

Change for Power Noise issue

06/01

1.Add PC181 with 33uF in +VIN_VCCGT net

2.Change PC210,PC216 from 22 uF to 47 uF

3.Change PC208,PC212 from 22uF to no stuff

B B

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

Z8VR

PROJECT :

Z8VR

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet

Change list

Change list

Change list

5

Z8VR

45 46Thursday, June 22, 2017

45 46Thursday, June 22, 2017

45 46Thursday, June 22, 2017

of

DOC NO.

1A

1A

1A

PROJECT MODEL :

PART NUMBER: DRAWING BY: REVISON:

4

Z8VR

APPROVED BY:

3

DATE:

2

1

5

Model

D D

C C

Date

4

3

2

1

CHANGE LIST

B B

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT :

Z8VR

PROJECT :

Z8VR

PROJECT :

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

Change list

Change list

Change list

5

Z8VR

46 46Thursday, June 22, 2017

46 46Thursday, June 22, 2017

46 46Thursday, June 22, 2017

DOC NO.

1A

1A

1A

PROJECT MODEL :

PART NUMBER: DRAWING BY: REVISON:

4

Z8VR

APPROVED BY:

3

DATE:

2

1