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QUANTA
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Z8V
Schematics
44 pgs1.73 Mb0

QUANTA Z8V Schematics

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3
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1
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RJ45
BOM
P23
D D
Cardreader
C C
CONN. 2in 1
P28
I/O board
B B
Z8V Serials SKL ULT SYSTEM BLOCK DIAGRAM
DDR4-SODIMM CHA
DDR4-SODIMM CHB
SATA - HDD
SATA ODD
RTS5170 (cardreader)
POA
CCD(Camera)
Touch Screen
Blue Tooth
I/O Board Conn.USB2 IO*1
P28
P25
P21
P21
P26
P28
P12
P13
P25
P25
Dual Channel DDR IV 1066/1333/1600 MHZ
SATA0
SATA1
USB2-3
USB2-3
USB2-7
USB2-6
USB2-5
USB2-4
P6
BATTERY
Azalia
SKY LAKE ULT 15W
MCP 1356pins
IMC
DC+GT3e
42 mm X 24 mm
SATA
Integrated PCH
USB2.0
DMIC_CLK0 DMIC_DATA0
RTC IHDA
P2~P10
LPC
PCI-E x4 TX/RX
CLK
eDP
USB3.0/2.0
CLK
PCI-E x1
CLK I2C_0
SPI
DP
PCIE1-4
EDP
DDI2
DDI1
USB3-1 & USB3-2
USB2-1 & USB2-2
X'TAL
32.768KHz
X'TAL 24MHz
SPI ROM 8M
GPU
N16S-GT
P14~P18
RTD2166-CG
P20
PTN3366BS
P22
P7
X'TAL 27MHz
PCIE-6
PCIE-5
VRAM
GDDR5
eDP Conn.
VGA Conn.
HDMI Conn.
P21
P21
P22
USB3 Port MB side CN13 -> USB3 port 2 ( up ) CN16 -> USB3 port 1 ( down )
MINI CARD WLAN+BT
RTL8111H
10/100/1G
P19
P26
P23
X'TAL 25MHz
IV@ : iGPU EV@ : Optimus KBL@ : Keyboard backlight TPM@ : TPM GS@ :G-SENSOR TDI@ : TOUCH PAD I2C TSU@ : TOUCH SCREEN USB TSI@ : TOUCH SCREEN I2C GT3@ : GT3 CPU NAC@ : Non IOAC IOAC@ : For IOAC
P28
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D-MIC
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Int. D-MIC
P24
Universal HP
A A
ALC255
AUDIO CODEC
P24 P24
P24
Speaker*2
LED
P27
K/B Con.
P27
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EC
K/B BL Con.
IT8987
P27
Touch PAD
P27
HALL SENSOR
P17
P29
Fan Driver
(Fan signal)
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3
TPM(option)
P27
BQ24780RUYR
P25
Batery Charger
RT6575AGQ
+3V/+5V
RT8237CZQW
+1V_S5
NB681GD-Z
+VCCOPC/+VCCEOPIO
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2
G5316RZ1D
+1.2VSUS
P30
MDV1528Q
+5V_S5/+3V_S5/+3V/+5V
P31
ISL95859HRTZ-T
+VCORE/VCCSA/VCCGT
P32
P33
Thermal Protection
P34
UP1658RQKF
+VGPU_CORE
P31
RT8068AZQW
P35
+1.05V_GFX/+3V_GFX +1.5V_GFX
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
P7
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Block Diagram
Block Diagram
Block Diagram
1
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P38
P39
P40
ZRW
ZRW
ZRW
1 46Monday, February 22, 2016
1 46Monday, February 22, 2016
1 46Monday, February 22, 2016
1A
1A
1A
5
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4
Skylake ULT (DISPLAY,eDP)
3
2
1
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
AT16
AU16
D63 A54 C65 C63 A65
C55 D55 B54 C56
A6
A7 BA5 AY5
H66 H65
SKL_ULT
DDI
DISPLAY SIDEBANDS
+3V_S5 +3V_S5
+3V_S5 +3V_S5
+3V_S5 +3V_S5
U34D
CATERR# PECI PROCHOT# THERMTRIP# SKTOCC#
CPU MISC
BPM#[0] BPM#[1] BPM#[2] BPM#[3]
GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3
PROC_POPIRCOMP PCH_OPIRCOMP OPCE_RCOMP OPC_RCOMP
SKL_ULT/BGA
1 OF 20
SKL_ULT
+3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5
+3V_S5 +3V_S5 +3V_S5 +3V_S5
EDP
4 OF 20
EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]
EDP_AUXN
EDP_AUXP
EDP_DISP_UTIL
DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP DDI3_AUXN DDI3_AUXP
GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3
GPP_E17/EDP_HPD
EDP_BKLTEN
EDP_BKLTCTL
EDP_VDDEN
JTAG
PROC_TCK
PROC_TDI PROC_TDO PROC_TMS
PROC_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS
PCH_TRST#
JTAGX
C47
EDP_TXN0
C46
EDP_TXP0
D46
EDP_TXN1
C45
EDP_TXP1
A45
EDP_TXN2
B45
EDP_TXP2
A47
EDP_TXN3
B47
EDP_TXP3
E45
EDP_AUXN
F45
EDP_AUXP
B52 G50
F50 E48
CRT_AUX#_C
F48
CRT_AUX_C
G46 F46
L9
INT_HDMI_HPD
L7
CRT_HPD
L6
SIO_EXT_SMI#
N9
SIO_EXT_SCI#
L10
EDP_HPD
R12
PCH_BLON
R11
PCH_BRIGHT
U13
EDP_VDD_EN
B61
XDP_TCK0
D60
XDP_TDI_CPU
A61
XDP_TDO_CPU
C60
XDP_TMS_CPU
B59
XDP_TRST#
B56
XDP_TCK1
D59
XDP_TDI_CPU
A56
XDP_TDO_CPU
C59
XDP_TMS_CPU
C61 A59
XDP_TRST#
XDP_TCK0
If use Intel DCI USB 3.0 fixture need to short
1. XDP_TDO <--> XDP_TDO_CPU
2. XDP_TDI <--> XDP_TDI_CPU
3. XDP_TMS <--> XDP_TMS_CPU
EDP_TXN0 (20) EDP_TXP0 (20) EDP_TXN1 (20) EDP_TXP1 (20) EDP_TXN2 (20) EDP_TXP2 (20) EDP_TXN3 (20) EDP_TXP3 (20)
EDP_AUXN (20) EDP_AUXP (20)
R432 *0_4 R444 *0_4
C569 *short_4 C568 *short_4
PCH_BRIGHTDP_UTIL
PCH_BLON (20) PCH_BRIGHT (20)
EDP_VDD_EN (20)
CRT_AUXN (19) CRT_AUXP (19)
INT_HDMI_HPD (21) CRT_HPD (19)
TP14
SIO_EXT_SCI# (28) EDP_HPD (20)
eDP Panel
Reserve 2 Lane for 4K x 2K
PCH JTAG
JTAG_TCK,JTAG_TMS Trace Length < 9000mils
TCK,TMS Trace Length < 9000mils
H_PWRGOOD (50ohm) Trace Length: 1~11.25 inches
Don't stuff if we use DP to VGA IC
CRT_AUXN CRT_AUXP
CRT_DATA CRT_CLK
12/25 Change R1 34R135 pull-up to +3V_S5
SIO_EXT_SMI# SIO_EXT_SCI#
CRT_HPD EDP_HPD
R424 *100K_4 R423 *100K_4
R135 2.2K_4 R134 *2.2K_4
R115 10K_4 R123 10K_4
R82 100K_4 R84 100K_4
+3V
+3V_S5
+3V
100k pull-down on PCH side
MP remove(Intel)
XDP_TDO_CPU XDP_TMS_CPU XDP_TDI_CPU
XDP_TCK0 XDP_TCK1 XDP_TRST#
,XDP_TCK1,XDP_TMS don't need pull up or pull down
R448 51_4 R408 *51_4 R409 *51_4
R447 51_4 R425 *51_4 R446 *51_4
+1V_VCCST
D D
HDMICRT
+VCCIO
C C
+1V_VCCST
CPU_THRMTRIP#
R4001K_4
CATERR#
Stuff only for Debug Ramp will not stuff
+VCCIO
R441 1K_4
B B
R40749.9/F_4
H_PROCHOT#
H_PROCHOT#(28,29,34)
Avoid 125Mhz
BPM#[0:7] Trace Length 1~6 inches Length match < 300 mils
H_PECI (50ohm) Route on microstrip only Spacing >18 mils Trace Length: 0.4~6.125 iches
SM_RCOMP[0:2] Trace length < 500 mils Trace width = 12~15 mils Trace spacing = 20 mils
INT_HDMITX2N(21) INT_HDMITX2P(21) INT_HDMITX1N(21) INT_HDMITX1P(21) INT_HDMITX0N(21) INT_HDMITX0P(21)
INT_HDMICLK-(21) INT_HDMICLK+(21)
CRT_TXN0(19) CRT_TXP0(19) CRT_TXN1(19)
ITE FAE suggest CAP should be at PCH side.
HDMI_DDCCLK_SW(21)
HDMI_DDCDATA_SW(21)
CRT_TXP1(19)
PCH_ODD_EN(24)
eDP_RCOMP Trace length < 100 mils Trace width = 20 mils Trace spacing = 25 mils
H_PECI(28)
THRMTRIP#
DGPU_PW_CTRL#(4)
HDMI_DDCCLK_SW HDMI_DDCDATA_SW
CRT_CLK CRT_DATA
EDP_RCOMP
R8724.9/F_4
TP53
R442 499/F_4 R395 100/F_4
TP54 TP52 TP59 TP56
U34A
E55
DDI1_TXN[0]
F55
DDI1_TXP[0]
E58
DDI1_TXN[1]
F58
DDI1_TXP[1]
F53
DDI1_TXN[2]
G53
DDI1_TXP[2]
F56
DDI1_TXN[3]
G56
DDI1_TXP[3]
C50
DDI2_TXN[0]
D50
DDI2_TXP[0]
C52
DDI2_TXN[1]
D52
DDI2_TXP[1]
A50
DDI2_TXN[2]
B50
DDI2_TXP[2]
D51
DDI2_TXN[3]
C51
DDI2_TXP[3]
L13
GPP_E18/DDPB_CTRLCLK
L12
GPP_E19/DDPB_CTRLDATA
N7
GPP_E20/DDPC_CTRLCLK
N8
GPP_E21/DDPC_CTRLDATA
N11
GPP_E22/DDPD_CTRLCLK
N12
GPP_E23/DDPD_CTRLDATA
E52
EDP_RCOMP
SKL_ULT/BGA
CATERR# H_PECI H_PROCHOT#_RH_PROCHOT# CPU_THRMTRIP#
XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3
DGPU_PW_CTRL#
R590 49.9/F_4 R595 49.9/F_4 R100 49.9/F_4 R96 49.9/F_4
XDP_TCK0 R558 Stuff
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Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Monday, February 22, 2016
Monday, February 22, 2016
Monday, February 22, 2016
Date: Sheet of
Date: Sheet of
PROJECT :
Skylake 1/4 (DDI/eDP)
Skylake 1/4 (DDI/eDP)
Skylake 1/4 (DDI/eDP)
ZRW
ZRW
ZRW
of
2 46
2 46
2 46
1
1A
1A
1A
+1V_VCCST
+1V_VCCST
2
R414 *1K_4
1 3
Q33 MMBT3904-7-F
3
Q34 FDV301N_G
1
R454 1K_4
2
SYS_SHDN# (28,30,37)
3
CPU thermal trip
+1V_VCCST
U27
NC1VCC
A A
IMVP_PWRGD(34)
2
A
GND3Y
*74AUP1G07GW
5
R401 *0_4
5
C537
*0.1u/16V_4
4
+3V
12
R402 10K_4
IMVP_PWRGD_3V (8)
IMVP_PWRGD_3V
THRMTRIP#
4
5
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Change Data and DQS to interleave.
D D
M_A_DQ[63:0](11) M_B_DQ[63:0](12)
C C
B B
A A
M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8
M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63
U34B
AL71
DDR0_DQ[0]
AL68
DDR0_DQ[1]
AN68
DDR0_DQ[2]
AN69
DDR0_DQ[3]
AL70
DDR0_DQ[4]
AL69
DDR0_DQ[5]
AN70
DDR0_DQ[6]
AN71
DDR0_DQ[7]
AR70
DDR0_DQ[8]
AR68
DDR0_DQ[9]
AU71
DDR0_DQ[10]
AU68
DDR0_DQ[11]
AR71
DDR0_DQ[12]
AR69
DDR0_DQ[13]
AU70
DDR0_DQ[14]
AU69
DDR0_DQ[15]
BB65
DDR0_DQ[16]/DDR0_DQ[32]
AW65
DDR0_DQ[17]/DDR0_DQ[33]
AW63
DDR0_DQ[18]/DDR0_DQ[34]
AY63
DDR0_DQ[19]/DDR0_DQ[35]
BA65
DDR0_DQ[20]/DDR0_DQ[36]
AY65
DDR0_DQ[21]/DDR0_DQ[37]
BA63
DDR0_DQ[22]/DDR0_DQ[38]
BB63
DDR0_DQ[23]/DDR0_DQ[39]
BA61
DDR0_DQ[24]/DDR0_DQ[40]
AW61
DDR0_DQ[25]/DDR0_DQ[41]
BB59
DDR0_DQ[26]/DDR0_DQ[42]
AW59
DDR0_DQ[27]/DDR0_DQ[43]
BB61
DDR0_DQ[28]/DDR0_DQ[44]
AY61
DDR0_DQ[29]/DDR0_DQ[45]
BA59
DDR0_DQ[30]/DDR0_DQ[46]
AY59
DDR0_DQ[31]/DDR0_DQ[47]
AY39
DDR0_DQ[32]/DDR1_DQ[0]
AW39
DDR0_DQ[33]/DDR1_DQ[1]
AY37
DDR0_DQ[34]/DDR1_DQ[2]
AW37
DDR0_DQ[35]/DDR1_DQ[3]
BB39
DDR0_DQ[36]/DDR1_DQ[4]
BA39
DDR0_DQ[37]/DDR1_DQ[5]
BA37
DDR0_DQ[38]/DDR1_DQ[6]
BB37
DDR0_DQ[39]/DDR1_DQ[7]
AY35
DDR0_DQ[40]/DDR1_DQ[8]
AW35
DDR0_DQ[41]/DDR1_DQ[9]
AY33
DDR0_DQ[42]/DDR1_DQ[10]
AW33
DDR0_DQ[43]/DDR1_DQ[11]
BB35
DDR0_DQ[44]/DDR1_DQ[12]
BA35
DDR0_DQ[45]/DDR1_DQ[13]
BA33
DDR0_DQ[46]/DDR1_DQ[14]
BB33
DDR0_DQ[47]/DDR1_DQ[15]
AY31
DDR0_DQ[48]/DDR1_DQ[32]
AW31
DDR0_DQ[49]/DDR1_DQ[33]
AY29
DDR0_DQ[50]/DDR1_DQ[34]
AW29
DDR0_DQ[51]/DDR1_DQ[35]
BB31
DDR0_DQ[52]/DDR1_DQ[36]
BA31
DDR0_DQ[53]/DDR1_DQ[37]
BA29
DDR0_DQ[54]/DDR1_DQ[38]
BB29
DDR0_DQ[55]/DDR1_DQ[39]
AY27
DDR0_DQ[56]/DDR1_DQ[40]
AW27
DDR0_DQ[57]/DDR1_DQ[41]
AY25
DDR0_DQ[58]/DDR1_DQ[42]
AW25
DDR0_DQ[59]/DDR1_DQ[43]
BB27
DDR0_DQ[60]/DDR1_DQ[44]
BA27
DDR0_DQ[61]/DDR1_DQ[45]
BA25
DDR0_DQ[62]/DDR1_DQ[46]
BB25
DDR0_DQ[63]/DDR1_DQ[47]
SKL_ULT/BGA
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5
SKL_ULT
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]
DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]
DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]
DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR CH - A
2 OF 20
M_A_A[13:0] M_A_DQS#[7:0] M_A_DQS[7:0]
M_A_A[13:0] (11) M_A_DQS#[7:0] (11) M_A_DQS[7:0] (11)
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4
DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]
DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]
DDR0_CS#[0] DDR0_CS#[1] DDR0_ODT[0] DDR0_ODT[1]
DDR0_MA[3] DDR0_MA[4]
DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1]
DDR0_DQSP[1] DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSN[7]/DDR1_DQSN[5] DDR0_DQSP[7]/DDR1_DQSP[5]
DDR0_ALERT#
DDR0_PAR
DDR_VREF_CA
DDR0_VREF_DQ DDR1_VREF_DQ
DDR_VTT_CNTL
4
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AU53 AT53 AU55 AT55
BA56 BB56 AW56 AY56
AU45 AU43 AT45 AT43
BA51
M_A_A5
BB54
M_A_A9
BA52
M_A_A6
AY52
M_A_A8
AW52
M_A_A7
AY55 AW54
M_A_A12
BA54
M_A_A11
BA55
M_A_ACT#
AY54 AU46
M_A_A13
AU48 AT46 AU50 AU52 AY51
M_A_A2
AT48 AT50
M_A_A10
BB50
M_A_A1
AY50
M_A_A0
BA50
M_A_A3
BB52
M_A_A4
AM70
M_A_DQS#0
AM69
M_A_DQS0
AT69
M_A_DQS#1
AT70
M_A_DQS1
BA64
M_A_DQS#2
AY64
M_A_DQS2
AY60
M_A_DQS#3
BA60
M_A_DQS3
BA38
M_A_DQS#4
AY38
M_A_DQS4
AY34
M_A_DQS#5
BA34
M_A_DQS5
BA30
M_A_DQS#6
AY30
M_A_DQS6
AY26
M_A_DQS#7
BA26
M_A_DQS7
AW50 AT52
AY67 AY68
+VREFDQ_SA_M3
BA67 AW67
R545 *10K_4
M_A_ALERT# M_A_PARITY
DDR_VTT_CTRL
Stuff Q54 for both UMA and GPU in DDR_VTT_CNTL
M_A_CLK0# (11)
M_A_CLK0 (11)
M_A_CLK1# (11)
M_A_CLK1 (11)
M_A_CKE0 (11) M_A_CKE1 (11)
M_A_CS#0 (11) M_A_CS#1 (11) M_A_ODT0_DIMM (11) M_A_ODT1_DIMM (11)
M_A_BG#0 (11)
M_A_ACT# (11) M_A_BG#1 (11)
M_A_CAS# (11) M_A_WE# (11) M_A_RAS# (11) M_A_BA#0 (11)
M_A_BA#1 (11)
M_A_ALERT# (11)
M_A_PARITY (11)
+VREF_CA_CPU
TP77
+VREFDQ_SB_M3
+1.2VSUS
2
1 3
Q36 *DTC144EU
3
+3V_S5
R544 *100K_4
DRAMRST
3
2
https://t.me/schematicslaptop https://t.me/biosarchive
SKL ULT (DDR4)SKL ULT (DDR4)
U34C
AF65
DDR_VTTT_PG_CTRL (33)
M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8
M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63
DDR1_DQ[0]/DDR0_DQ[16]
AF64
DDR1_DQ[1]/DDR0_DQ[17]
AK65
DDR1_DQ[2]/DDR0_DQ[18]
AK64
DDR1_DQ[3]/DDR0_DQ[19]
AF66
DDR1_DQ[4]/DDR0_DQ[20]
AF67
DDR1_DQ[5]/DDR0_DQ[21]
AK67
DDR1_DQ[6]/DDR0_DQ[22]
AK66
DDR1_DQ[7]/DDR0_DQ[23]
AF70
DDR1_DQ[8]/DDR0_DQ[24]
AF68
DDR1_DQ[9]/DDR0_DQ[25]
AH71
DDR1_DQ[10]/DDR0_DQ[26]
AH68
DDR1_DQ[11]/DDR0_DQ[27]
AF71
DDR1_DQ[12]/DDR0_DQ[28]
AF69
DDR1_DQ[13]/DDR0_DQ[29]
AH70
DDR1_DQ[14]/DDR0_DQ[30]
AH69
DDR1_DQ[15]/DDR0_DQ[31]
AT66
DDR1_DQ[16]/DDR0_DQ[48]
AU66
DDR1_DQ[17]/DDR0_DQ[49]
AP65
DDR1_DQ[18]/DDR0_DQ[50]
AN65
DDR1_DQ[19]/DDR0_DQ[51]
AN66
DDR1_DQ[20]/DDR0_DQ[52]
AP66
DDR1_DQ[21]/DDR0_DQ[53]
AT65
DDR1_DQ[22]/DDR0_DQ[54]
AU65
DDR1_DQ[23]/DDR0_DQ[55]
AT61
DDR1_DQ[24]/DDR0_DQ[56]
AU61
DDR1_DQ[25]/DDR0_DQ[57]
AP60
DDR1_DQ[26]/DDR0_DQ[58]
AN60
DDR1_DQ[27]/DDR0_DQ[59]
AN61
DDR1_DQ[28]/DDR0_DQ[60]
AP61
DDR1_DQ[29]/DDR0_DQ[61]
AT60
DDR1_DQ[30]/DDR0_DQ[62]
AU60
DDR1_DQ[31]/DDR0_DQ[63]
AU40
DDR1_DQ[32]/DDR1_DQ[16]
AT40
DDR1_DQ[33]/DDR1_DQ[17]
AT37
DDR1_DQ[34]/DDR1_DQ[18]
AU37
DDR1_DQ[35]/DDR1_DQ[19]
AR40
DDR1_DQ[36]/DDR1_DQ[20]
AP40
DDR1_DQ[37]/DDR1_DQ[21]
AP37
DDR1_DQ[38]/DDR1_DQ[22]
AR37
DDR1_DQ[39]/DDR1_DQ[23]
AT33
DDR1_DQ[40]/DDR1_DQ[24]
AU33
DDR1_DQ[41]/DDR1_DQ[25]
AU30
DDR1_DQ[42]/DDR1_DQ[26]
AT30
DDR1_DQ[43]/DDR1_DQ[27]
AR33
DDR1_DQ[44]/DDR1_DQ[28]
AP33
DDR1_DQ[45]/DDR1_DQ[29]
AR30
DDR1_DQ[46]/DDR1_DQ[30]
AP30
DDR1_DQ[47]/DDR1_DQ[31]
AU27
DDR1_DQ[48]
AT27
DDR1_DQ[49]
AT25
DDR1_DQ[50]
AU25
DDR1_DQ[51]
AP27
DDR1_DQ[52]
AN27
DDR1_DQ[53]
AN25
DDR1_DQ[54]
AP25
DDR1_DQ[55]
AT22
DDR1_DQ[56]
AU22
DDR1_DQ[57]
AU21
DDR1_DQ[58]
AT21
DDR1_DQ[59]
AN22
DDR1_DQ[60]
AP22
DDR1_DQ[61]
AP21
DDR1_DQ[62]
AN21
DDR1_DQ[63]
SKL_ULT/BGA
M_A_ALERT# M_B_ALERT#

+1.2VSUS
12
R577 470_4
CPU DRAM
CPU_DRAMRST#
R593 *Short/0_4
12
C650
*0.1u/16V_4
SKL_ULT
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR CH - B
3 OF 20
R312 *0_4 R291 *0_4
DDR3_DRAMRST# (11,12)
2
DDR1_CKN[0] DDR1_CKN[1] DDR1_CKP[0] DDR1_CKP[1]
DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3]
DDR1_CS#[0] DDR1_CS#[1] DDR1_ODT[0] DDR1_ODT[1]
DDR1_MA[3]
DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQSP[5]/DDR1_DQSP[3]
DDR1_MA[4]
DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]
DDR1_ALERT#
DDR1_PAR DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2]
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
AN45 AN46 AP45 AP46
AN56 AP55 AN55 AP53
BB42 AY42 BA42 AW42
AY48
M_B_A5
AP50
M_B_A9
BA48
M_B_A6
BB48
M_B_A8
AP48
M_B_A7
AP52 AN50
M_B_A12
AN48
M_B_A11
AN53
M_B_ACT#
AN52 BA43
M_B_A13
AY43 AY44 AW44 BB44 AY47
M_B_A2
BA44 AW46
M_B_A10
AY46
M_B_A1
BA46
M_B_A0
BB46
M_B_A3
BA47
M_B_A4
AH66
M_B_DQS#0
AH65
M_B_DQS0
AG69
M_B_DQS#1
AG70
M_B_DQS1
AR66
M_B_DQS#2
AR65
M_B_DQS2
AR61
M_B_DQS#3
AR60
M_B_DQS3
AT38
M_B_DQS#4
AR38
M_B_DQS4
AT32
M_B_DQS#5
AR32
M_B_DQS5
AR25
M_B_DQS#6
AR27
M_B_DQS6
AR22
M_B_DQS#7
AR21
M_B_DQS7
AN43
M_B_ALERT#
AP43
M_B_PARITY
AT13
CPU_DRAMRST#
AR18
SM_RCOMP_0
AT18
SM_RCOMP_1
AU18
SM_RCOMP_2
M_B_A[13:0] M_B_DQS#[7:0] M_B_DQS[7:0]
SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2
Skylake 2/3 (DDR3 I/F)
Skylake 2/3 (DDR3 I/F)
Skylake 2/3 (DDR3 I/F)
Monday, February 22, 2016
Monday, February 22, 2016
Monday, February 22, 2016
1

M_B_CLK0# (12) M_B_CLK1# (12)
M_B_CLK0 (12) M_B_CLK1 (12)
M_B_CKE0 (12) M_B_CKE1 (12)
M_B_CS#0 (12) M_B_CS#1 (12) M_B_ODT0_DIMM (12) M_B_ODT1_DIMM (12)
M_B_BG#0 (12)
M_B_ACT# (12) M_B_BG#1 (12)
M_B_CAS# (12) M_B_WE# (12) M_B_RAS# (12) M_B_BA#0 (12)
M_B_BA#1 (12)
M_B_ALERT# (12)
M_B_PARITY (12)
M_B_A[13:0] (12) M_B_DQS#[7:0] (12) M_B_DQS[7:0] (12)

R598120/F_4 R58980.6/F_4 R596100/F_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
ZRW
ZRW
ZRW
3 46
3 46
1
3 46
1A
1A
1A
5
4
3
2
1
SKL ULT (SIDEBAND ) GPIO
H_PECI (50ohm) If route on microstrip, Spacing need >18 mils Trace Length: 2~15 iches
H_PWRGOOD (50ohm)
Touch PAD Touch Screen
R198*IV@10K_4
R587*100K_4
R188*10K_4
UMA boot
GPU boot
+3V
Trace Length: 1~11.25 inches
UART2 for RMT
HDA
PCH_AZ_CODEC_SYNC(23)
PCH_AZ_CODEC_BITCLK(23)
PCH_AZ_CODEC_SDOUT(23)
PCH_AZ_CODEC_SDIN0(23)
PCH_AZ_CODEC_RST#(23)
SPKR
R549 *20K/F_4
D D
+3V_S5
I2C0_SDA
R1372.2K_4
I2C0_SCL
R1252.2K_4
I2C1_SDA
R119*2.2K_4
I2C1_SCL
R126*2.2K_4
PU 2.2K for touch pad I2C bus(400 KHz)
+3V
+3V
DGPU_PW_CTRL#
C C
high
low
DGPU_PW_CTRL#(2)
R208 EV@100K_4
GPU Control PU/PD
R201*EV@10K_4 R575*10K_4
R192*10K_4
20131015 For GC6 NV DG GC6_FB_EN PD.1A-1
R197 10K_4
UMA Only
GPU power is control by PCH GPIO (Discrete, SG or Optimize)
DGPU_PW_CTRL#
VGPU_EN
DGPU_PWR_EN
GC6_FB_EN
DGPU_HOLD_RST#
DGPU_PWROK
R209 IV@1K_4
R104 *10K_4
DGPU_PWROK PD on GPU side
Setup
DGPU_PW_CTRL#
UMA Only
SG/Optimise
VGA H/W
Menu
Signal
UMA
1
0
Hidden
Hidden
GPU
545659-103
Add GPU Power Control Siganls
Touch PAD
Touch Screen
DGPU_HOLD_RST#(13)
DGPU_PWR_EN(39)
DGPU_PWROK(15) GC6_FB_EN(13,16)
DGPU_EVENT#(16)
ODD_PRSNT#(24)
C636 *10p/50V_4
VGPU_EN(38)
ACCEL_INTA(26)
TPD_INT#(26,28)
TP_INT_PCH(20)
I2C0_SDA(26)
I2C0_SCL(26)
I2C1_SDA(20)
I2C1_SCL(20)
C644 *10p/50V_4 R583 33_4
R553 33_4 R569 33_4
R560 33_4
TP70 TP57
Strapping
SPKR(23)
TPD_INT#
UART2_RXD UART2_TXD UART2_RTS# UART2_CTS#
I2C0_SDA I2C0_SCL
I2C1_SDA I2C1_SCL
HDA_SYNC_R HDA_BCLK_R HDA_SDO_R
HDA_RST#_R
DMIC_CLK0_R DMIC_DATA0_R
SPKR
GSPI0_MOSI
GSPI1_MOSI
Skylake-U Strapping Table
Pin Name Strap description
GPP_B14 (SPKR)
B B
GPP_B18 (GSPI0_MOSI)
GPP_C2 (SMBALERT#)
GPP_B22 (GSPI1_MOSI)
GPP_C5 (SML0ALERT#)
SPI0_MOSI
SPI0_MISO
GPP_B23 (SML1ALERT# /PCHHOT#)
SPI0_IO2
A A
SPI0_IO3
HDA_SDO / I2S_TXD0
GPP_E19 (DDPB_CTRLDATA)
GPP_E21 (DDPC_CTRLDATA)
Top-Block Swap override PCH_PWROK
No reboot PCH_PWROK
TLS Confidentiality
Boot BIOS Strap Bit (BBS)
eSPI or LPC
Reserved
Reserved
Reserved
Reserved
Reserved
Flash Descriptor Security Override / Intel ME Debug Mode
Display Port B Detected
Display Port C Detected
5
Sampled
RSMRST#
PCH_PWROK
RSMRST#
RSMRST#
RSMRST#
RSMRST#
RSMRST#
RSMRST#
PCH_PWROK
PCH_PWROK
PCH_PWROK
Configuration note
0 = *Disable Top Swap (iPD 20K)
1 = Enable Top Swap Mode
0 = *Disable No Reboot (iPD 20K)
1 = Enable No Reboot Mode
0 = *Disable Intel ME Cryp to TLS(iPD 20K)
1 = Enable Intel ME Cryp to TLS
0 = *SPI (iPD 20K)
1 = LPC
0 = *LPC is selected for EC (iPD 20K)
1 = eSPI selected for EC
+3V
+3V
+3V_S5
+3V
+3V_S5
(iPU 15 ~ 40K)
(iPU 15 ~ 40K)
(iPD 20K)
(iPU 15 ~ 40K)
(iPU 15 ~ 40K)
0 = *Enable security in the Flash Description (iPD 20K)
1 = Disable Flash Descriptor Security (Override)
0 = *Port B is not detected (iPD 20K)
1 =Port B is detected
0 = *Port C is not detected (iPD 20K)
1 =Port C is detected
4
R550 *1K_4
R543 *1K_4
R144 *10K_4
R191 *1K_4
change location to near CPU to prevent impact HDA_SDO signal
HDA_SDO_R
AN8 AP7 AP8 AR7
AM5 AN7 AP5 AN5
AB1 AB2
W4
AB3 AD1
AD2 AD3 AD4
U7 U6
U8 U9
AH9
AH10 AH11
AH12 AF11
AF12
BA22 AY22 BB22 BA21 AY21
AW22
J5
AY20
AW20
AK7 AK6 AK9
AK10
H5 D7
D8 C8
AW5
R481 *1K_4
R570 1K_4
U34F
LPSS ISH
GPP_B15/GSPI0_CS# GPP_B16/GSPI0_CLK GPP_B17/GSPI0_MISO GPP_B18/GSPI0_MOSI
GPP_B19/GSPI1_CS# GPP_B20/GSPI1_CLK GPP_B21/GSPI1_MISO GPP_B22/GSPI1_MOSI
GPP_C8/UART0_RXD GPP_C9/UART0_TXD GPP_C10/UART0_RTS# GPP_C11/UART0_CTS#
GPP_C20/UART2_RXD GPP_C21/UART2_TXD GPP_C22/UART2_RTS# GPP_C23/UART2_CTS#
GPP_C16/I2C0_SDA GPP_C17/I2C0_SCL
GPP_C18/I2C1_SDA GPP_C19/I2C1_SCL
GPP_F4/I2C2_SDA GPP_F5/I2C2_SCL
GPP_F6/I2C3_SDA GPP_F7/I2C3_SCL
GPP_F8/I2C4_SDA GPP_F9/I2C4_SCL
SKL_ULT/BGA
U34G
AUDIO
HDA_SYNC/I2S0_SFRM HDA_BLK/I2S0_SCLK HDA_SDO/I2S0_TXD HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_RST#/I2S1_SCLK GPP_D23/I2S_MCLK I2S1_SFRM I2S1_TXD
GPP_F1/I2S2_SFRM GPP_F0/I2S2_SCLK GPP_F2/I2S2_TXD GPP_F3/I2S2_RXD
GPP_D19/DMIC_CLK0 GPP_D20/DMIC_DATA0
GPP_D17/DMIC_CLK1 GPP_D18/DMIC_DATA1
+3V_S5
GPP_B14/SPKR
SKL_ULT/BGA
SPKR
GSPI0_MOSI
GSPI1_MOSI
3
+3V_S5 +3V_S5 +3V_S5 +3V_S5
+3V_S5 +3V_S5 +3V_S5 +3V_S5
+3V_S5 +3V_S5 +3V_S5 +3V_S5
+3V_S5 +3V_S5 +3V_S5 +3V_S5
+3V_S5 +3V_S5
+3V_S5 +3V_S5
+1.8V_S5 +1.8V_S5
+1.8V_S5 +1.8V_S5
+1.8V_S5 +1.8V_S5
+3V_S5
+1.8V_S5 +1.8V_S5 +1.8V_S5 +1.8V_S5
+3V_S5 +3V_S5
+3V_S5 +3V_S5
ME_WR# (28)
SKL_ULT
+3V_S5 +3V_S5 +3V_S5 +3V_S5
+3V_S5 +3V_S5 +3V_S5 +3V_S5
SKL_ULT
+3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5
+3V_S5 +3V_S5
7 OF 20
SMBALERT# (7)
SML0ALERT# (7)
+3V_S5 +3V_S5 +3V_S5 +3V_S5
+3V_S5 +3V_S5
+3V_S5 +3V_S5
+1.8V_S5 +1.8V_S5
GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
GPP_D16/ISH_UART0_CTS#/SML0BALERT#
GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#
+3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5
6 OF 20
SDIO/SDXC
SD GPI SD GPI SD GPI SD GPI SD GPI SD GPI SD GPI SD GPI
GPP_A17/SD_PWR_EN#/ISH_GP7
GPP_D5/ISH_I2C0_SDA GPP_D6/ISH_I2C0_SCL
GPP_D7/ISH_I2C1_SDA GPP_D8/ISH_I2C1_SCL
GPP_F10/I2C5_SDA/ISH_I2C2_SDA
GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_D15/ISH_UART0_RTS#
GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5
GPP_A12/BM_BUSY#/ISH_GP6
GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3
GPP_G5/SD_CD# GPP_G6/SD_CLK
GPP_G7/SD_WP
GPP_A16/SD_1P8_SEL
SD_RCOMP
GPP_F23
+1.8V_S5
https://t.me/schematicslaptop https://t.me/biosarchive
AB11 AB13 AB12 W12 W11 W10 W8 W7
BA9 BB9
AB7
AF13
GPP_D9 GPP_D10 GPP_D11 GPP_D12
P2 P3 P4 P1
M4 N3
N1 N2
AD11 AD12
U1 U2 U3 U4
AC1 AC2 AC3 AB4
AY8 BA8 BB7 BA7 AY7 AW7 AP13
R148200/F_4
Touchpad INT
Reserve UART FFC TP for Win 7 debug
UART2_RXD UART2_TXD UART2_RTS# UART2_CTS#
TPD_INT#
R490 *49.9K/F_4 R489 *49.9K/F_4 R484 *49.9K/F_4 R488 *49.9K/F_4
TP68 TP69 TP67 TP66
+3V_S5
R117TDI@10K_4
https://t.me/schematicslaptop https://t.me/biosarchive
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Monday, February 22, 2016
Date: Sheet of
Monday, February 22, 2016
Date: Sheet of
Monday, February 22, 2016
2
Date: Sheet
PROJECT :
Skylake 6/7 (PEG/DMI/FDI)
Skylake 6/7 (PEG/DMI/FDI)
Skylake 6/7 (PEG/DMI/FDI)
1
+3V_S5
ZRW
ZRW
ZRW
4 46
4 46
4 46

of
1A
1A
1A
5
Backside cap
C203 1U/6.3V_2
C247 22u/6.3V_6
C227 22u/6.3V_6
C132 22u/6.3V_6
C301 22u/6.3V_6
C273 22u/6.3V_6
C209 22u/6.3V_6
C228 22u/6.3V_6
Backside cap
C312
C235
1U/6.3V_2
1U/6.3V_2
D D
C107
C275 22u/6.3V_6
C208 22u/6.3V_6
22u/6.3V_6
C575 10u/6.3V_4
C327 22u/6.3V_6
C300
C269
10u/6.3V_4
10u/6.3V_4
Backside cap
C223 1U/6.3V_2
C545 10u/6.3V_4
C580 1U/6.3V_2
C552 10u/6.3V_4
Backside cap
C581
C230
C279 1U/6.3V_2
C246 1U/6.3V_2
+VCCEOPIO
C310
GT3@10u/6.3V_4
+1.8V_PRIM
GT3@10u/6.3V_4
C C
B B
A A
C205
C220 GT3@10u/6.3V_4
R92
GT3@0_6
C267
1U/6.3V_2
1U/6.3V_2
C314
C221
1U/6.3V_2
1U/6.3V_2
Backside cap
For 2+3e CPU
C313 GT3@10u/6.3V_4
Backside cap
For 2+3e CPU
+1.8V_PRIM+1.8V_S5
C316 10u/6.3V_4
C210 1U/6.3V_2
C287
1U/6.3V_2
1U/6.3V_2
Backside cap
C214 1U/6.3V_2
C116
C131
10u/6.3V_4
10u/6.3V_4
C237
C239
1U/6.3V_2
1U/6.3V_2
+1.2VSUS
C243 1U/6.3V_2
C195 1U/6.3V_2
Backside cap
C593
C595
GT3@1U/6.3V_2
GT3@10u/6.3V_4
Backside cap
C215 10u/6.3V_4
Backside cap
C265 1U/6.3V_2
C375 10u/6.3V_4
Backside cap
+1V_SUS
+VCCIO
+1V_SUS
C315 1U/6.3V_2
C307 1U/6.3V_2
C241 10u/6.3V_4
C263 1U/6.3V_2
C466 10u/6.3V_4
R181 *short/0_4
1 2
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5
4
C248
C284
22u/6.3V_6
22u/6.3V_6
C558
C252
10u/6.3V_4
10u/6.3V_4
C217
C204
1U/6.3V_2
1U/6.3V_2
C256 1U/6.3V_2
100 ohm near CPU
1.0V_CPU 3A
C589
C591
GT3@1U/6.3V_2
GT3@1U/6.3V_2
For 2+3e CPU
C140 10u/6.3V_4
C262 1U/6.3V_2
Backside cap
C407
C360
1U/6.3V_2
10u/6.3V_4
Primary side cap
C421 10u/6.3V_4
+VDDQC
C322 1U/6.3V_2
R430 *short/0_6
Primary side cap
R81 *short/0_6
R431 *short/0_6
4
+VCCCORE
+1.8V_PRIM
+VCCOPC
+VCCOPC_SRC(32)
681_AGND(32)
For 2+3e CPU
+VCCOPC_SRC 681_AGND
+VCCOPC
C590
C592
GT3@1U/6.3V_2
GT3@1U/6.3V_2
C250
C224
10u/6.3V_4
10u/6.3V_4
C261
C212
1U/6.3V_2
1U/6.3V_2
100 ohm Near CPU
VCCGT_SENSE(34) VSSGT_SENSE(34)
C410
C329
1U/6.3V_2
1U/6.3V_2
C450
C435
10u/6.3V_4
10u/6.3V_4
+1V_VCCST
C308 10u/6.3V_4
C576 1U/6.3V_4
Backside cap
Primary side cap
+VCCOPC
For 2+3e CPU
+1.8V_PRIM
C594 GT3@1U/6.3V_2
+VCCGT
C92 10u/6.3V_4
C213 1U/6.3V_2
C211 1U/6.3V_2
R83 100/F_4
R78 100/F_4
C355 1U/6.3V_2
+VCCSTG
TP13 TP27
R162 GT3@100/F_4
R170 GT3@0_4 R175 GT3@0_4
R179 GT3@100/F_4
+VCCEOPIO
R164 GT3@0_4 R176 GT3@0_4
C80 10u/6.3V_4
C260 1U/6.3V_2
C238 1U/6.3V_2
+VCCGT
+1.2VSUS
C136 1U/6.3V_4
+VCCPLL
C577 1U/6.3V_4
A30 A34 A39
A44 AK33 AK35 AK37 AK38 AK40
AL33 AL37
AL40 AM32 AM33 AM35 AM37 AM38
G30
K32 AK32 AB62
P62
V62
H63
G61 AC63
AE63 AE62
AG62
AL63 AJ62
A48
A53
A58
A62
A66
AA63 AA64 AA66 AA67 AA69 AA70 AA71 AC64 AC65 AC66 AC67 AC68 AC69 AC70 AC71
J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60
K48
K50
K52
K53
K55
K56
K58
K60
L62
L63
L64
L65
L66
L67
L68
L69
L70
L71
M62
N63
N64
N66
N67
N69
J70
J69
AU23 AU28 AU35 AU42 BB23 BB32 BB41 BB47 BB51
AM40
A18
A22
AL23
K20
K21
U34L
VCC_A30 VCC_A34 VCC_A39 VCC_A44 VCC_AK33 VCC_AK35 VCC_AK37 VCC_AK38 VCC_AK40 VCC_AL33 VCC_AL37 VCC_AL40 VCC_AM32 VCC_AM33 VCC_AM35 VCC_AM37 VCC_AM38 VCC_G30
RSVD_K32 RSVD_AK32 VCCOPC_AB62
VCCOPC_P62 VCCOPC_V62
VCC_OPC_1P8_H63 VCC_OPC_1P8_G61 VCCOPC_SENSE
VSSOPC_SENSE VCCEOPIO
VCCEOPIO VCCEOPIO_SENSE
VSSEOPIO_SENSE
SKL_ULT/BGA
U34M
CPU POWER 2 OF 4
VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT
VCCGT_SENSE VSSGT_SENSE
SKL_ULT/BGA
U34N
CPU POWER 3 OF 4
S3
VDDQ_AU23 VDDQ_AU28 VDDQ_AU35 VDDQ_AU42 VDDQ_BB23 VDDQ_BB32 VDDQ_BB41 VDDQ_BB47 VDDQ_BB51
VDDQC VCCST VCCSTG_A22
S0
VCCPLL_OC
S0
VCCPLL_K20 VCCPLL_K21
S3
1.0V
SKL_ULT/BGA
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SKL_ULT
CPU POWER 1 OF 4
S0
S0
S0
SKL_ULT
S0
VCCGTX
S0
0.55~1.5V
2+2 X
2+3e peak 6A
2+3e TPY 4A
SKL_ULT
DDR4
1.2V
2A
2+2 peak 5A 2+2 TPY 4A 2+3e peak 5.1A 2+3e TPY 5A
S3
1.0V
1.0V
1.0V
120mA
3
VCC
0.55V~1.5V
2+2 peak 24A 2+2 TPY 17A
2+3e peak 24A 2+3e TPY 17A
1.0V
Sx
1.8V
GT3 CPU
3A
1.0V
12 OF 20
VCCGT
0.55~1.5V
2+2 peak 31A 2+2 TPY 15A
2+3e peak 56A 2+3e TPY 17A
VCCGTX_AM48 VCCGTX_AM50 VCCGTX_AM52 VCCGTX_AM53 VCCGTX_AM56 VCCGTX_AM58 VCCGTX_AU58 VCCGTX_AU63 VCCGTX_BB57 VCCGTX_BB66
VCCGTX_SENSE VSSGTX_SENSE
13 OF 20
S0
0.85V/0.95V
3.0A
S0
1.15V
120mA
40mA
260mA
VCCIO_SENSE VSSIO_SENSE
VSSSA_SENSE VCCSA_SENSE
14 OF 20
3
3A
50mA
VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT
VCCGTX_AK42 VCCGTX_AK43 VCCGTX_AK45 VCCGTX_AK46 VCCGTX_AK48 VCCGTX_AK50 VCCGTX_AK52 VCCGTX_AK53 VCCGTX_AK55 VCCGTX_AK56 VCCGTX_AK58 VCCGTX_AK60 VCCGTX_AK70 VCCGTX_AL43 VCCGTX_AL46 VCCGTX_AL50 VCCGTX_AL53 VCCGTX_AL56 VCCGTX_AL60
VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO
VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA
VCC_G32 VCC_G33 VCC_G35 VCC_G37 VCC_G38 VCC_G40 VCC_G42 VCC_J30 VCC_J33 VCC_J37 VCC_J40 VCC_K33 VCC_K35 VCC_K37 VCC_K38 VCC_K40 VCC_K42 VCC_K43
VCC_SENSE VSS_SENSE
VIDALERT#
VIDSCK
VIDSOUT
VCCSTG_G20
N70 N71 R63 R64 R65 R66 R67 R68 R69 R70 R71 T62 U65 U68 U71 W63 W64 W65 W66 W67 W68 W69 W70 W71 Y62
AK42 AK43 AK45 AK46 AK48 AK50 AK52 AK53 AK55 AK56 AK58 AK60 AK70 AL43 AL46 AL50 AL53 AL56 AL60 AM48 AM50 AM52 AM53 AM56 AM58 AU58 AU63 BB57 BB66
AK62 AL61
AK28 AK30 AL30 AL42 AM28 AM30 AM42
AK23 AK25 G23 G25 G27 G28 J22 J23 J27 K23 K25 K27 K28 K30
AM23 AM22
H21 H20
2
+VCCCORE
G32 G33 G35 G37 G38 G40 G42 J30 J33 J37
J40 K33 K35 K37 K38 K40 K42 K43
E32 E33
B63 A63 D64
G20
+VCCGT
C119 1U/6.3V_4
C531 47u/6.3V_8
C106 10u/6.3V_4
R29 100/F_4
R32 100/F_4
+VCCSTG
Primary side cap
C66 47u/6.3V_8
Primary side cap
C83 10u/6.3V_4
+VCCCORE
100 ohm Near CPU
H_CPU_SVIDART# H_CPU_SVIDCLK H_CPU_SVIDDAT
C74 47u/6.3V_8
C122 10u/6.3V_4
VCORE_SENSE (34) VCORESS_SENSE (34)
Primary side cap
C61
C244 47u/6.3V_8
C59 47u/6.3V_8
47u/6.3V_8
Primary side cap
C599 22u/6.3V_6
C620 22u/6.3V_6
C134 22u/6.3V_6
C621 22u/6.3V_6
Primary side cap
C619 22u/6.3V_6
C93 47u/6.3V_8
C600 22u/6.3V_6
C598 22u/6.3V_6
C202 change back to 47u/6.3v_8 for cost
+VCCGT
C294 22u/6.3V_6
Primary side cap
C292
C604
22u/6.3V_6
GT3@22u/6.3V_6
C609 GT3@22u/6.3V_6
Stuff C277,C274,C275
For 2+3e CPU
Backside cap
C319 GT3@10u/6.3V_4
GT3@10u/6.3V_4
+VCCIO
C305 10u/6.3V_4
C216
10u/6.3V_4
10u/6.3V_4
Backside cap
C304 10u/6.3V_4
C251
C271
Primary side cap
C608
C627
1U/6.3V_4
1U/6.3V_4
Backside cap
C280
C249
10u/6.3V_4
10u/6.3V_4
Backside cap
C303
C194
1U/6.3V_2
1U/6.3V_2
Primary side cap
C245
C133
10u/6.3V_4
10u/6.3V_4
TP28 TP26
R90 100/F_4
VSASS_SENSE (34) VSA_SENSE (34)
R89 100/F_4
100 ohm near CPU
+VCCSA
+VCCSA
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2
C538 47u/6.3V_8
C573 10u/6.3V_4
C296 1U/6.3V_2
C605 1U/6.3V_4
C266 10u/6.3V_4
C207 1U/6.3V_2
C231 10u/6.3V_4
C534 47u/6.3V_8
C100 10u/6.3V_4
SVID
H_CPU_SVIDDAT
H_CPU_SVIDART#
H_CPU_SVIDCLK
C302
C219
47u/6.3V_8
47u/6.3V_8
C617
C114
22u/6.3V_6
22u/6.3V_6
C210 change back to 47u/6.3v_8 for cost
C618
C597
22u/6.3V_6
22u/6.3V_6
C596 GT3@22u/6.3V_6
C270 GT3@10u/6.3V_4
Imax 3(A)
C320 1U/6.3V_2
C628 1U/6.3V_4
C236 10u/6.3V_4
C259 1U/6.3V_2
C87 10u/6.3V_4
C56 47u/6.3V_8
C574 10u/6.3V_4
+1V_VCCST
R418 100/F_4
Place PU resistor close to CPU
Place PU resistor close to CPU
R419 220/F_4
C60 47u/6.3V_8
C96 47u/6.3V_8
C293 22u/6.3V_6
C318
C242
GT3@10u/6.3V_4
10u/6.3V_4
C297
C321
1U/6.3V_2
1U/6.3V_2
C222
C288
10u/6.3V_4
10u/6.3V_4
C285
C295
1U/6.3V_2
1U/6.3V_2
C102
C115
10u/6.3V_4
10u/6.3V_4
1
C138
C570
10u/6.3V_4
10u/6.3V_4
Must close to CPU
C535 1000P/50V_4
+1V_VCCST
R393
54.9/F_4
C277 47u/6.3V_8
C317
C291
22u/6.3V_6
22u/6.3V_6
C225 10u/6.3V_4
C311 10u/6.3V_4
C276 1U/6.3V_2
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Monday, February 22, 2016
Date: Sheet of
Monday, February 22, 2016
Date: Sheet of
Monday, February 22, 2016
Date: Sheet
PROJECT :
Skylake 12/13/14 (POWER)
Skylake 12/13/14 (POWER)
Skylake 12/13/14 (POWER)
1

H_CPU_SVIDDAT (34)
VR_SVID_ALERT#_VCORE (34)
H_CPU_SVIDCLK (34)
ZRW
ZRW
ZRW
of
5 46
5 46
5 46
1A
1A
1A
5
4
3
2
1
Skylake ULT (GPU, SATA , ODD, CLK ,USB2&3)
U34H
PCIE/USB3/SATA
PEG_RX#0(13)
PEG_RX0(13)
D
dGPU PEG*4
C
LAN
WIFI
B
N16S VGALANWLAN
M.2
SSD
A
PEG_TX#0(13)
PEG_TX0(13)
PEG_RX#1(13)
PEG_RX1(13)
PEG_TX#1(13)
PEG_TX1(13)
PEG_RX#2(13)
PEG_RX2(13)
PEG_TX#2(13)
PEG_TX2(13)
PEG_RX#3(13)
PEG_RX3(13)
PEG_TX#3(13)
PEG_TX3(13)
PCIE_RX5-_LAN(22)
PCIE_RX5+_LAN(22)
PCIE_TX5-_LAN(22)
PCIE_TX5+_LAN(22)
PCIE_RX6-_WLAN(25)
PCIE_RX6+_WLAN(25)
PCIE_TX6-_WLAN(25)
PCIE_TX6+_WLAN(25)
SATA_RXN1/PEG_RXN10_L2(25)
SATA_RXP1/PEG_RXP10_L2(25)
SATA_TXN1/PEG_TXN10_L2(25)
SATA_TXP1/PEG_TXP10_L2(25)
SATA_RXN3/PEG_RXN9_L0(25)
SATA_RXP3/PEG_RXP9_L0(25)
SATA_TXN3/PEG_TXN9_L0(25)
SATA_TXP3/PEG_TXP9_L0(25)
CLK_PCIE_VGA#(13)
CLK_PCIE_VGA(13)
CLK_PEGA_REQ#(13)
CLK_PCIE_NGFF1_N(25)
CLK_PCIE_NGFF1_P(25)
PCIE_CLKREQ_NGFF1#(25)
CLK_PCIE_LANN(22)
CLK_PCIE_LANP(22)
CLK_PCIE_LAN_REQ#(22)
CLK_PCIE_WLANN(25)
CLK_PCIE_WLANP(25)
PCIE_CLKREQ_WLAN#(25)
CLK_PCIE_REQ0#
CLK_PCIE_REQ1#
CLK_PCIE_REQ2#
CLK_PCIE_REQ3#
CLK_PCIE_REQ4#
CLK_PCIE_REQ5#
5
HDD
ODD
C564 EV@0.22u/10V_4
C563 EV@0.22u/10V_4
C550 EV@0.22u/10V_4
C549 EV@0.22u/10V_4
C547 EV@0.22u/10V_4
C548 EV@0.22u/10V_4
C542 EV@0.22u/10V_4
C543 EV@0.22u/10V_4
SATA_RXN0(24)
SATA_RXP0(24)
SATA_TXN0(24)
SATA_TXP0(24)
SATA_RXN1(24)
SATA_RXP1(24)
SATA_TXN1(24)
SATA_TXP1(24)
C560 0.1u/16V_4
C561 0.1u/16V_4
C541 0.1u/16V_4
C540 0.1u/16V_4
R440 100/F_4
TP55
TP51
R259
R211
TP31
TP78
R230
R213
R258 10K_4
R205 10K_4
R223 *10K_4
R574 *10K_4
R227 10K_4
R210 10K_4
XDP_PRDY#
XDP_PREQ#
PIRQA#
SATA_RXN1/PEG_RXN10_L2
SATA_RXP1/PEG_RXP10_L2
SATA_TXN1/PEG_TXN10_L2
SATA_TXP1/PEG_TXP10_L2
SATA_RXN3/PEG_RXN9_L0
SATA_RXP3/PEG_RXP9_L0
SATA_TXN3/PEG_TXN9_L0
SATA_TXP3/PEG_TXP9_L0
CLK_PCIE_REQ0#
*Short/0_4
CLK_PCIE_REQ1#
*Short/0_4
CLK_PCIE_REQ2#
CLK_PCIE_REQ3#
CLK_PCIE_REQ4#
*Short/0_4
CLK_PCIE_REQ5#
*Short/0_4
+3V
C_PEG_TX#0
C_PEG_TX0
C_PEG_TX#1
C_PEG_TX1
C_PEG_TX#2
C_PEG_TX2
C_PEG_TX#3
C_PEG_TX3
PCIE_TX5-
PCIE_TX5+
PCIE_TX6-
PCIE_TX6+
PCIE_RCOMPN
PCIE_RCOMPP
H13
PCIE1_RXN/USB3_5_RXN
G13
PCIE1_RXP/USB3_5_RXP
B17
PCIE1_TXN/USB3_5_TXN
A17
PCIE1_TXP/USB3_5_TXP
G11
PCIE2_RXN/USB3_6_RXN
F11
PCIE2_RXP/USB3_6_RXP
D16
PCIE2_TXN/USB3_6_TXN
C16
PCIE2_TXP/USB3_6_TXP
H16
PCIE3_RXN
G16
PCIE3_RXP
D17
PCIE3_TXN
C17
PCIE3_TXP
G15
PCIE4_RXN
F15
PCIE4_RXP
B19
PCIE4_TXN
A19
PCIE4_TXP
F16
PCIE5_RXN
E16
PCIE5_RXP
C19
PCIE5_TXN
D19
PCIE5_TXP
G18
PCIE6_RXN
F18
PCIE6_RXP
D20
PCIE6_TXN
C20
PCIE6_TXP
F20
PCIE7_RXN/SATA0_RXN
E20
PCIE7_RXP/SATA0_RXP
B21
PCIE7_TXN/SATA0_TXN
A21
PCIE7_TXP/SATA0_TXP
G21
PCIE8_RXN/SATA1A_RXN
F21
PCIE8_RXP/SATA1A_RXP
D21
PCIE8_TXN/SATA1A_TXN
C21
PCIE8_TXP/SATA1A_TXP
E22
PCIE9_RXN
E23
PCIE9_RXP
B23
PCIE9_TXN
A23
PCIE9_TXP
F25
PCIE10_RXN
E25
PCIE10_RXP
D23
PCIE10_TXN
C23
PCIE10_TXP
F5
PCIE_RCOMPN
E5
PCIE_RCOMPP
D56
PROC_PRDY#
D61
PROC_PREQ#
BB11
GPP_A7/PIRQA#
E28
PCIE11_RXN/SATA1B_RXN
E27
PCIE11_RXP/SATA1B_RXP
D24
PCIE11_TXN/SATA1B_TXN
C24
PCIE11_TXP/SATA1B_TXP
E30
PCIE12_RXN/SATA2_RXN
F30
PCIE12_RXP/SATA2_RXP
A25
PCIE12_TXN/SATA2_TXN
B25
PCIE12_TXP/SATA2_TXP
SKL_ULT/BGA
U34J
D42
CLKOUT_PCIE_N0
C42
CLKOUT_PCIE_P0
AR10
GPP_B5/SRCCLKREQ0#
B42
CLKOUT_PCIE_N1
A42
CLKOUT_PCIE_P1
AT7
GPP_B6/SRCCLKREQ1#
D41
CLKOUT_PCIE_N2
C41
CLKOUT_PCIE_P2
AT8
GPP_B7/SRCCLKREQ2#
D40
CLKOUT_PCIE_N3
C40
CLKOUT_PCIE_P3
AT10
GPP_B8/SRCCLKREQ3#
B40
CLKOUT_PCIE_N4
A40
CLKOUT_PCIE_P4
AU8
GPP_B9/SRCCLKREQ4#
E40
CLKOUT_PCIE_N5
E38
CLKOUT_PCIE_P5
AU7
GPP_B10/SRCCLKREQ5#
SKL_ULT/BGA
+3V_S5
4
SKL_ULT
+3V_S5 +3V_S5 +3V_S5
8 OF 20
SKL_ULT
CLOCK SIGNALS
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
10 OF 20
add for EC reset RTC
CLR_CMOS(28)
SSIC / USB3
USB3_2_RXN/SSIC_1_RXN
USB3_2_RXP/SSIC_1_RXP
USB3_2_TXN/SSIC_1_TXN
USB3_2_TXP/SSIC_1_TXP
USB3_3_RXN/SSIC_2_RXN
USB3_3_RXP/SSIC_2_RXP
USB3_3_TXN/SSIC_2_TXN
USB3_3_TXP/SSIC_2_TXP
USB2
+3V_S5 +3V_S5 +3V_S5 +3V_S5
+3V_S5 +3V_S5 +3V_S5
GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
+3V_S5
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
GPD8/SUSCLK
XTAL24_IN
XTAL24_OUT
XCLK_BIASREF
SRTCRST#
RTCRST#
USB3_1_RXN
USB3_1_RXP
USB3_1_TXN
USB3_1_TXP
USB3_4_RXN
USB3_4_RXP
USB3_4_TXN
USB3_4_TXP
USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9
USB2P_9
USB2N_10
USB2P_10
USB2_COMP
USB2_ID
USB2_VBUSSENSE
GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2
GPP_E8/SATALED#
F43
E43
BA17
E37
XTAL24_IN
E35
XTAL24_OUT
E42
XCLK_BIASREF
AM18
RTC_X1
RTCX1
AM20
RTC_X2
RTCX2
AN18
SRTC_RST#
AM16
RTC_RST#
3
2
R594
1
100K_4
H8
G8
C13
D13
J6
H6
B13
A13
J10
H10
B15
A15
E10
F10
C15
D15
AB9
AB10
AD6
AD7
AH3
AJ3
AD9
AD10
AJ1
AJ2
AF6
AF7
AH1
AH2
AF8
AF9
AG1
AG2
AH7
AH8
AB6
AG3
AG4
A9
C9
D9
B9
J1
J2
J3
H2
H3
G4
H1
CLK_PCIE_XDPN
CLK_PCIE_XDPP
SUSCLK
SRTC_RST#
Q41 *2N7002K
USBCOMP
R138 113/F_4
USB2_ID
R492 1K_4
R185 1K_4
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
DEVSLP0
DEVSLP1
DEVSLP2
SATAGP0
SATAGP1
R436 *Short/0_4
R452 2.7K/F_4
3
USB3_RXN0 (27)
USB3_RXP0 (27)
USB3_TXN0 (27)
USB3_TXP0 (27)
USB3_RXN1 (27)
USB3_RXP1 (27)
USB3_TXN1 (27)
USB3_TXP1 (27)
MB USB3.0 CN16 ( Charger IC ) Down
MB USB3.0 CN13 -> Up
1A-1
USBP0- (27)
USBP0+ (27)
USBP1- (27)
USBP1+ (27)
USBP2- (27)
USBP2+ (27)
USBP3- (24)
USBP3+ (24)
USBP4- (25)
USBP4+ (25)
USBP5- (20)
USBP5+ (20)
USBP6- (20)
USBP6+ (20)
USBP7- (27)
USBP7+ (27)
USB_OC0# (27)
USB_OC1# (27)
USB_OC2# (27)
TP6
TP9
SUSCLK (25)
1V power plane
0.71 checklist p14
MB USB3.0 CN16 ( Charger IC ) Down MB USB3.0 CN13 -> Up DB USB2.0 POA (Reserved) BT Touch Screen CCD Card reader
USBCOMP Impedance = 50 ohm Trace length < 500 mils Trace spacing = 15 mils
MB U3 MB U3 DB U2
DEVSLP0 (24)
DEVSLP2 (25)
NGFF3_DET (25)
+1V_S5
3
CLR_CMOS
2
1
Q39 2N7002K
RTC_RST#
Add SSD ID 1/14
Hight is SSD , Low is ODD
SSD_ID(24)
Skylake-U userd 24 MHz (50 Ohm ESR) XTAL
XTAL24_IN
XTAL24_OUT
Note: Change Y4 to 38.4 MHz(ESR 30 ohm) for Cannonlake U
RTC Clock 32.768KHz (RTC)
Trace length < 1000 mils
RTC Circuitry (RTC)
+3VPCU
On SKL voltage at VCCRTC does not exceed 3.2V
R329
1.5K/F_4
VCCRTC_2
R330
45.3K/F_4
2013/10/16 Chage +3V_RTC_0 to VCCTC_2.
1A-2
1. AHL03003057 DBV CR2032
2. AHL03003003 VDE CR2032
2
PCH PU/PD
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
DEVSLP0
DEVSLP1
DEVSLP2
PIRQA#
SATAGP1
R438 10K_4
C349 6.8p/50V_4
C350 6.8p/50V_4
1B-1
R335 1K_4
1
BT1
BAT_CONN
2
SATAGP0
C556 10P/50V_4
3
4
Y3
R426
24MHz
1M_4
2
1
C544 10P/50V_4
1
2
+3V_RTC_2
+3V_RTC_1
+3V_RTC_[0:2] Trace width = 20 mils
BAT54CW_0.2A
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Monday, February 22, 2016
Date: Sheet
Monday, February 22, 2016
Date: Sheet
Monday, February 22, 2016
Date: Sheet
+3V_S5
R411 10K_4
R405 10K_4
R404 10K_4
R422 10K_4
R469 *10K_4
R470 *10K_4
R471 *10K_4
R572 10K_4
R439 *10K_4
+3V_S5
R437 100K_4
CH01006JB08 -> 10p CH01506JB06 -> 15p CH-6806TB01 -> 6.8p
RTC_X1
Y2
R225
32.768KHZ
10M_4
RTC_X2
+3V_RTC
+3V_RTC
Trace width = 30 mils
D9
R237
20K/F_4
R233
20K/F_4
C363 1u/6.3V_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
Skylake 9/10 (PEG/USB/CLK)
Skylake 9/10 (PEG/USB/CLK)
Skylake 9/10 (PEG/USB/CLK)

+3V
BG624000078 -> HHE(1st) BG624000044 -> TXC(2nd)
BG3327680C6 -> HHE(1st)
BG332768099 -> TXC(2nd)--EOD Change to BG332768104
RTC_RST#
1
J1
C357
*JUMP
1u/6.3V_4
2
SRTC_RST#
C354 1u/6.3V_4
ZRW
ZRW
ZRW
of
6 46
of
6 46
of
1
6 46
D
C
B
A
1A
1A
1A
5
4
3
2
1
D
For M.2 wifi module must
SIO_RCIN#(28)
IRQ_SERIRQ(24,28)
C
PCH_SPI_CLK_EC(28)
PCH_SPI_SI_EC(28)
PCH_SPI_SO_EC(28)
SP@ socket P/N: DFHS08FS023 only for A-TEST
SPI ROM
Skylake
3.3V
Vender Size Quanta P/N Vender P/N
AKE3EFP0N07
8M
AKE2EZN0Q00
8M
PCH_SPI_CLK
PCH_SPI_SO
PCH_SPI_SI
PCH_SPI_IO2
PCH_SPI_IO3
PCH_SPI_CS0#
R573 *short_4
IRQ_SERIRQ
PCH_SPI_CLK_EC
PCH_SPI_SI_EC
PCH_SPI_SO_EC
W25Q64FVSSIQWND GD25B64CSIGRGGD
EC_RCIN#
AW3
AW2
AW13
AY11
AV2
AV3
AU4
AU3
AU2
AU1
M2
M3
J4
V1
V2
M1
G3
G2
G1
U34E
SPI - FLASH
SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_IO2
SPI0_IO3
SPI0_CS0#
SPI0_CS1#
SPI0_CS2#
GPP_D1/SPI1_CLK
GPP_D2/SPI1_MISO
GPP_D3/SPI1_MOSI
GPP_D21/SPI1_IO2
GPP_D22/SPI1_IO3
GPP_D0/SPI1_CS#
CL_CLK
CL_DATA
CL_RST#
GPP_A0/RCIN#
GPP_A6/SERIRQ
SKL_ULT/BGA
+3V_S5
SPI - TOUCH
+3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5
C LINK
+3V_S5 +3V_S5
PCH SPI ROM(8M)
15ohm CS01502JB12 33ohm CS03302JB29
PCH_SPI_CS0#
1A-13
PCH_SPI_SO
PCH_SPI_SO_EC
R453 15_4
R457 15_4
+3V_PCH_ME
3.3K is original and for no support fast read function
SKL_ULT
LPC
R433 1K_4
SMBUS, SMLINK
+3V_S5 +3V_S5 +3V_S5
+3V_S5 +3V_S5 +3V_S5
+3V_S5 +3V_S5
GPP_B23/SML1ALERT#/PCHHOT#
+3V_S5
+3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5
GPP_A14/SUS_STAT#/ESPI_RESET#
+3V_S5
GPP_A9/CLKOUT_LPC0/ESPI_CLK
+3V_S5 +3V_S5
+3V_S5
5 OF 20
+3V_LDO_EC
+3V_S5
SPI_SO_8M
SPI_WP_IO2_ME
PCH_SPI_IO2
PCH_SPI_IO3
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C2/SMBALERT#
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C5/SML0ALERT#
GPP_C6/SML1CLK
GPP_C7/SML1DATA
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
GPP_A5/LFRAME#/ESPI_CS#
GPP_A10/CLKOUT_LPC1
GPP_A8/CLKRUN#
R462 *0_6
R475 0_6
U29
1
CS#
2
IO1/DO
3
IO2/WP#
4
GND
W25Q64FV -- 8MB
IO3/HOLD#
IO0/DI
PCH_SPI_CLK_EC
PCH_SPI_SI_EC
R415 15_4
R477 15_4
VCC
CLK
R7
PCH_MBCLK0_R
R8
PCH_MBDAT0_R
R10
SMBALERT#
R9
VGA_MBCLK
W2
VGA_MBDATA
W1
SML0ALERT#
W3
SMB_ME1_CLK
V3
SMB_ME1_DAT
AM7
SMB1ALERT#
eSPI change to 15 ohm
AY13
R559 *short_4
BA13
R547 *short_4
BB13
R556 *short_4
AY12
R548 *short_4
BA12
BA11
R226 *0_4
C348 *0.1u/16V_4
eSPI change to 15 ohm
AW9
R551 22/J_4
AY9
AW11
R557 22/J_4
R558 22/J_4
CLKRUN#
2/10 add C806 for EMI request , R748 no stuiff from EC site move at CPU site
+3V_PCH_ME
8
7
SPI_HOLD_IO3_ME
6
SPI_CLK_8M
5
SPI_SI_8M
R463 15_4
R468 15_4
R461 15_4
R465 15_4
SPI_WP_IO2_ME
SPI_HOLD_IO3_ME
Strapping
SMBALERT# (4)
SML0ALERT# (4)
SMB1ALERT# (26)
ckl v0.71 p.24
LPC_LAD0 (24,25,28)
LPC_LAD1 (24,25,28)
LPC_LAD2 (24,25,28)
LPC_LAD3 (24,25,28)
LPC_LFRAME# (24,25,28)
TP36
CLK_PCI_EC (28)
PCLK_TPM (24)
CLK_PCI_LPC (25)
CLKRUN# (24,28)
+3V_PCH_ME
C582 0.1u/16V_4
R466 1K_4
PCH_SPI_CLK
PCH_SPI_SI
C587 *22p/50V_4
reserve for SPI fast read

+3V_S5
CLKRUN#
IRQ_SERIRQ
EC_RCIN#
SMBus
PCH_MBCLK0_R
PCH_MBDAT0_R
VGA_MBDATA
VGA_MBCLK
SMB1ALERT#
Termination Resistor Requirement for PCH PCHHOT# Pin Reserve PU 150K resister
S5 S0
SMBus(PCH)
PCH_MBDAT0_R
PCH_MBCLK0_R
PCH_XDP_WLAN/S5 DDR_TP/S0
SMBus(EC)
R564 8.2K/F_4
R566 10K_4
R546 10K_4
+3V
Change to 2.2k
Q35
5
3
2
6
DMN601DW K-7
+3V_S5
R4732.2K_4
R4722.2K_4
R4792.2K_4
R1452.2K_4
+3V_S5
R187*150K_4
R456
R464
2.2K_4
2.2K_4
4
1
CLK_SDATA (11,12,19,26)
CLK_SCLK (11,12,19,26)
D
C
B
A
5
4
SPI_CS0#_UR_ME(28)
+3V_PCH_ME
R428 *Short/0_4
R445 10K_4
PCH_SPI_CS0#
SPI_CS0#_UR_ME
only 0ohm option
3
2ND_MBCLK(16,28)
2ND_MBDATA(16,28)
EC/S5
2
2ND_MBCLK
2ND_MBDATA
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Monday, February 22, 2016
Date: Sheet
Monday, February 22, 2016
Date: Sheet
Monday, February 22, 2016
Date: Sheet
R480 *Short/0_4
R476 *Short/0_4
Skylake 5 (SATA/HDA/SPI)
Skylake 5 (SATA/HDA/SPI)
Skylake 5 (SATA/HDA/SPI)
SMB_ME1_CLK
SMB_ME1_DAT
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
ZRW
ZRW
ZRW
of
7 46
of
7 46
of
1
7 46
B
A
1A
1A
1A
5
4
3
2
1
+VCCIO
Reserve PU 10K
R450 *10K_4
D
EC only PD, so PD 10K
PCH_SUSPWRDNACK_C
Board ID
C





B
PLTRST# Buffer
A
PROC_PWRGD
R579 10K_4
R526 10K_4
R524 10K_4
R538 10K_4
R506 10K_4
R504 NAC@10K_4
R521 10K_4
R498 *10K_4
R495 10K_4
R493 10K_4
R519 10K_4
#$
VRAM X32 (R506)
Non IOAC (R504)
Non G-sensor (R521)
No TPM (R498)
No-Touch panel
PCI_PLTRST#
2
1
5
RAM_ID1
RAM_ID2
RAM_ID3
Board_ID0
Board_ID1
Board_ID2
Board_ID3
Board_ID4
Board_ID5
Board_ID6
Board_ID7
 !"
VRAM X16 (R507)
IOAC (R505)
G-sensor (R522)
TPM (R499)
Touch panel (R500)
+3V
C341 0.1u/16V_4
5
U8
3
MC74VHC1G08
RSMRST#(28)
EC_PWROK
R420 *short_4
R568 *0_4
PCH_SUSPWRDNACK(28)
PCIE_LAN_WAKE#(22,25)
+1.8V_S5
R527 *10K_4
R525 *10K_4
R540 *10K_4
R507 *10K_4
R505 IOAC@10K_4
R522 *GS@10K_4
R499 TPM@10K_4
R500 TSU@10K_4
R501 *10K_4
R494 *10K_4
R520 *10K_4


 Reserve
4
R212 100K_4
For 14" (R495)
(Default)
Reserved (Default)
PLTRST# (13,22,24,25,28)
R580 *short_4
R451 10K_4
R597 *0_4
PCI_PLTRST#
SYS_RESET#
VCCST_PWRGD
TP29
PCIE_LAN_WAKE#
 !"#$
For 15" / 17" (R501)
ReserveReserved
PCH_RSMRST#
PROC_PWRGD
SYS_PWROK_R
EC_PWROK_R
DPWROK_R
PCH_SUSPWRDNACK_C
SUSACK#_R
TP25
U34K
SYSTEM POWER MANAGEMENT
AN10
GPP_B13/PLTRST#
B5
SYS_RESET#
AY17
RSMRST#
A68
PROCPWRGD
B65
VCCST_PWRGD
B6
SYS_PWROK
BA20
PCH_PWROK
BB20
DSW_PWROK
AR13
GPP_A13/SUSWARN#/SUSPWRDNACK
AP11
GPP_A15/SUSACK#
BB15
WAKE#
AM15
GPD2/LAN_WAKE#
AW17
GPD11/LANPHYPC
AT15
GPD7/RSVD
SKL_ULT/BGA
A36
CSI2_DN0
B36
CSI2_DP0
C38
CSI2_DN1
D38
CSI2_DP1
C36
CSI2_DN2
D36
CSI2_DP2
A38
CSI2_DN3
B38
CSI2_DP3
C31
CSI2_DN4
D31
CSI2_DP4
C33
CSI2_DN5
D33
CSI2_DP5
A31
CSI2_DN6
B31
CSI2_DP6
A33
CSI2_DN7
B33
CSI2_DP7
A29
CSI2_DN8
B29
CSI2_DP8
C28
CSI2_DN9
D28
CSI2_DP9
A27
CSI2_DN10
B27
CSI2_DP10
C27
CSI2_DN11
D27
CSI2_DP11
U34I
CSI-2
SKL_ULT/BGA
+3V_S5
I I
+3V_S5
+3V_S5 +3V_S5 +3V_S5
SKL_ULT
+1.8V_S5 +1.8V_S5 +1.8V_S5 +1.8V_S5 +1.8V_S5 +1.8V_S5 +1.8V_S5 +1.8V_S5
+1.8V_S5 +1.8V_S5 +1.8V_S5
Power Sequence
PCH_PWROK(28)
For platforms not supporting Deep Sx, connect directly to RSMRST#
DPWROK_R
SYSPWOK
EC_PWROK
4
SKL_ULT
+3V_S5
11 OF 20
+3V_S5
9 OF 20
R403 *0_4
+3V_S5 +3V_S5 +3V_S5
+3V_S5
+3V_S5 +3V_S5
+3V_S5 +3V_S5 +3V_S5
+3V_S5
GPP_B11/EXT_PWR_GATE#
+3V_S5 +3V_S5
CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3
CSI2_COMP
GPP_D4/FLASHTRIG
EMMC
GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7
GPP_F21/EMMC_RCLK
GPP_F22/EMMC_CLK
GPP_F12/EMMC_CMD
EMMC_RCOMP
Non Deep Sx
No Deep Sx
R582 0_4
Remove
GPP_B12/SLP_S0#
GPD4/SLP_S3#
GPD5/SLP_S4#
GPD10/SLP_S5#
SLP_SUS#
SLP_LAN#
GPD9/SLP_WLAN#
GPD6/SLP_A#
GPD3/PWRBTN#
GPD1/ACPRESENT
GPD0/BATLOW#
GPP_A11/PME#
INTRUDER#
GPP_B2/VRALERT#
C37
D37
C32
D32
C29
D29
B26
A26
E13
B7
AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1
AM2
AM3
AP4
AT1
R552 0_4
PCH_RSMRST#
R410 *10K_4
AT11
AP15
BA16
AY16
AN15
AW15
BB17
AN16
BA15
AY15
AU13
AU11
AP16
AM10
AM11
R86 100/F_4
RAM_ID1
RAM_ID2
RAM_ID3
Board_ID0
Board_ID1
Board_ID2
Board_ID3
Board_ID4
Board_ID5
Board_ID6
Board_ID7
R542200/F_4
EC_PWROK_R
IMVP_PWRGD_3V (2)
EC_PWROK (28)
3
SUS0#
SUSB#
SUSC#
PCH_SLP_S5#
PCH_SLP_SUS#
PCH_SLP_LAN#
PCH_SLP_WLAN#
PCH_SLP_A#
PCH_PWRBTN#
PCH_ACPRESENT
PCH_BATLOW#
R222 1M_4
INTRUDER#
MPHY_EXT_PWR
PCH_VRALERT#
TP58
Board_ID4 (20)
REV:E tPLT17(max 200us) ->SLP_S3# assertion to IMVP VR_ON(VRON) deassertion
VRON_R(32,34)
TP33
TP72
R585*short_4
R584*short_4
TP32
TP30
Close to CPU
VCCST_PWRGD
Stuff 1000P/50V
SUS0# (31)
SUSB# (28,31)
SUSC# (28)
TP79
TP23
TP75
TP35
+3V_RTC
+3V_S5
C368 *0.1u/16V_4
5
4
U13
3
*MC74VHC1G08DFT2G
R244 0_4
R427 60.4/F_4
C557 1000P/50V_4
VCCST_PWRGD_EN
DNBSWON# (28)
SB_ACDC (28)
REV:E tPLT15(max 200us)
->SLP_S4# assertion to VDDQ(+1.35VSUS) ramp down start(SUSON)
SUSON_R(31,33)
2
SUSB#
1
VRON
+1V_VCCST
R416 1K_4
VCCST_PWRGD_R
Shortpad change to 60.4 ohm. 11/6
2013/10/21 Del APWORK.1A-6
SYS_RESET#
PCH_ACPRESENT
PCH_BATLOW#
PCIE_LAN_WAKE#
MPHY_EXT_PWR
PCH_VRALERT#
12/25 Change R206 pull-up to +3V_S5
PCH_RSMRST#
PCH_PWROK
SYS_PWROK_R
+3V_S5
C361 *0.1u/16V_4
5
3
R235 0_4
2
1
SUSON_R
4
U12 *TC7SH08FU
12/28 Delete U14/R245/C372 & Change "MAINON_R" to "MAINON"
12/28 Change from "SUSB#" to "MAINON"
VRON (28)
CRB is via +1.05V PGVCCST PWRGD
U25
+3V_S5
5
C528
0.1u/16V_4
4
R390 *0_4
R391 0_4
2
74AUP1G07GW
1
VCC
NC
2
VCCST_PWRGD_EN_L
A
3
Y
GND
PCH_PWROK
HWPG
Rev:D change netmane for HWPG
R429 10K_4
R565 8.2K/F_4
R229 8.2K/F_4
R236 10K_4
R184 *1K_4
R206 10K_4
R567 10K_4
R555 10K_4
R435 10K_4
+3V
+3V_S5
12/28 Delete U12/C361 & Add R695
SUSC#
SUSON
C527 *1000P/50V_4
HWPG (28)
SUSON (28)
B2A S0->S5 & S0->S3 Power of sequence 1us SUSB# -> VCCST_PWRGD
+3V_S5
C529 0.1u/16V_4
5
2
1
3
SUSB#
VCCST_PWRGD_EN
C530 *1000P/50V_4
4
U24 MC74VHC1G08DFT2G
R388 *0_4
Reserve 1000P/50V
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Monday, February 22, 2016
Date: Sheet
Monday, February 22, 2016
Date: Sheet
Monday, February 22, 2016
Date: Sheet
PROJECT :
Skylake 9/11 (PWROK/Board_ID)
Skylake 9/11 (PWROK/Board_ID)
Skylake 9/11 (PWROK/Board_ID)
1

ZRW
ZRW
ZRW
8 46
8 46
8 46
D
C
B
A
1A
1A
1A
of
of
of
5
4
3
2
1
U34S
E68
AL25
AL27
BA70
BA68
B67
D65
D67
E70
C68
D68
C67
F71
G69
F70
G68
H70
G71
H69
G70
E63
F63
E66
F66
E60
E8
AY2
AY1
D1
D3
K46
K45
C71
B70
F60
A52
J71
J68
F65
G65
F61
E61
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
CFG[18]
CFG[19]
CFG_RCOMP
ITP_PMODE
RSVD_AY2
RSVD_AY1
RSVD_D1
RSVD_D3
RSVD_K46
RSVD_K45
RSVD_AL25
RSVD_AL27
RSVD_C71
RSVD_B70
RSVD_F60
RSVD_A52
RSVD_TP_BA70
RSVD_TP_BA68
RSVD_J71
RSVD_J68
VSS_F65
VSS_G65
RSVD_F61
RSVD_E61
SKL_ULT/BGA
D
CFG4
R79 49.9/F_4
+1V_S5
C
B
CFG_RCOMP
R88 1.5K/F_4
SKL_ULT
RESERVED SIGNALS-1
19 OF 20
RSVD_TP_BB68
RSVD_TP_BB69
RSVD_TP_AK13
RSVD_TP_AK12
RSVD_BB2
RSVD_BA3
RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2
RSVD_B3
RSVD_A3
RSVD_AW1
RSVD_E1
RSVD_E2
RSVD_BA4
RSVD_BB4
RSVD_A4
RSVD_C4
RSVD_A69
RSVD_B69
RSVD_AY3
RSVD_D71
RSVD_C70
RSVD_C54
RSVD_D54
VSS_AY71
ZVM#
RSVD_TP_AW71
RSVD_TP_AW70
MSM#
PROC_SELECT#
TP5
TP6
TP4
TP1
TP2
BB68
BB69
AK13
AK12
Rev:F reserve TP
BB2
BA3
AU5
AT5
D5
D4
B2
C2
B3
A3
AW1
E1
E2
BA4
BB4
A4
C4
BB5
A69
B69
AY3
D71
C70
C54
D54
AY4
BB3
AY71
AR56
R172 GT3@0_4
AW71
AW70
AP56
C64
R417 100K_4
TP24
Rev:F Stuff C699
+1V_VCCST
+1V_S5
+1V_S5
+1V_S5
+1V_S5
+1V_S5
+1V_S5
+3VPCU
+3V_S5
+1.5V
+3V_S5
+1V_S5
+3V_S5
+1V_S5
+1V_S5
+3V
VCCPRIM_1P0 & VCCPRIM_CORE Short
AB19
AB20
C199 1U/6.3V_4
C603 1U/6.3V_4
C554 47u/6.3V_8
C233 1U/6.3V_4
C121 1U/6.3V_4
C117 47u/6.3V_8
C111 1U/6.3V_4
C282 *1U/6.3V_4
R200 *0_6
R194 *short_6
R588 0_6
R600 *0_6
C652 1U/6.3V_4
R174 *short_6
R155 *short_6
LPM_ZVM_N (32)
C108 1U/6.3V_4
C278 1U/6.3V_4
C110 1U/6.3V_4
For 2+3e CPU No Stuff
TP21
+VCCDSW_1P0
C6231U/6.3V_4
C602 1U/6.3V_4
+VCCPDSW_3P3
C336*0.1U/16V_4
+VCCHDA
+VCCPSPI
+VCCPRIM_3P3
P18
AF18
AF19
V20
V21
AL1
K17
N15
N16
N17
P15
P16
K15
V15
AB17
Y18
AD17
AD18
AJ17
AJ19
AJ16
AF20
AF21
AJ21
AK20
N18
L1
L15
T19
T20
SKL_ULT
U34O
CPU POWER 4 OF 4
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
DCPDSW_1P0
VCCMPHYAON_1P0
VCCMPHYAON_1P0
VCCMPHYGT_1P0_N15
VCCMPHYGT_1P0_N16
VCCMPHYGT_1P0_N17
VCCMPHYGT_1P0_P15
VCCMPHYGT_1P0_P16
VCCAMPHYPLL_1P0
VCCAMPHYPLL_1P0
VCCAPLL_1P0
VCCPRIM_1P0_AB17
VCCPRIM_1P0_Y18
VCCDSW_3P3_AD17
VCCDSW_3P3_AD18
VCCDSW_3P3_AJ17
VCCHDA
VCCSPI
VCCSRAM_1P0
VCCSRAM_1P0
VCCSRAM_1P0
VCCSRAM_1P0
VCCPRIM_3P3_AJ21
VCCPRIM_1P0_AK20
VCCAPLLEBB
SKL_ULT/BGA
1.5V
3.3V
1.0V
1.0V
30mA
11mA
1.0V
642mA
1.0V
S5
1.0V
S5
1.0V
22mA
1.0V
1.0V
S5
1.0V
3.3V
118mA
3.3V
1.0V
696mA
2.574A
S5
1.0V
1.258A
26mA
696mA
S5
S5
33mA
44mA
33mA 41mA
75mA with AJ21 pin
1.0V
6mA
1.8V
<1mA
3.0V+
RTC
135mA
S5
+3V
75mA
S5
696mA
S5
15 OF 20
S5
VCCPGPPG
VCCPRIM_3P3_V19
VCCPRIM_1P0_T1
VCCATS_1P8
VCCRTCPRIM_3P3
VCCRTC_AK19
VCCRTC_BB14
1.0V
S5
GPP_B0/CORE_VID0
GPP_B1/CORE_VID1
GPIO Group Power Plane
AK15
VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE
VCCPGPPF
DCPRTC
VCCCLK1
VCCCLK2
VCCCLK3
VCCCLK4
VCCCLK5
VCCCLK6
+VCCPGPPA
AG15
+VCCPGPPB
Y16
+VCCPGPPC
Y15
+VCCPGPPD
T16
+VCCPGPPE
AF16
+VCCPGPPF
AD15
+VCCPGPPG
V19
+VCCPRIM_3P3
T1
+VCCPRIM_1P0
AA1
+VCCATS_1P8
AK17
+VCCPRTCPRIM_3P3
AK19
BB14
BB10
A14
K19
L21
N20
L19
A10
AN11
V0P85A_VID0
AN13
C286 1U/6.3V_4
C358 1U/6.3V_4
+VCCPRTC
C352 1U/6.3V_4
DCPRTC
C198 *1U/6.3V_4
C578 1U/6.3V_4
C325 *1U/6.3V_4
C309 1U/6.3V_4
C255 1U/6.3V_4
C274 *1U/6.3V_4
R186*short_6
R180*short_6
R154*short_6
R153*short_6
R161*short_6
R166*short_6
R171*short_6
C283 1U/6.3V_4
C299 *1U/6.3V_4
R165*short_6
R248*short_6
C362 0.1U/16V_4
R231*short_6
C353 0.1U/16V_4
C641 0.1U/16V_4
TP37
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+1.8V_S5
+1V_S5
+1.8V_S5
+3V_S5
+3V_RTC
+1V_S5
%
D
C
B
Pin Name Strap description Configuration
CFG[0] Stall reset sequence after PCU PLL lock until de-asserted
CFG[1]
CFG[2]
CFG[3] Reserved Configuration lane
CFG[4]
CFG[6:5] PCI Express* Bifunction
A
CFG[7] PEG Training
CFG[19:8]
Reserved Configuration lane
PCI Express* Static x16 Lane Numbering Reversal
eDP enable
Reserved Configuration lane
5
1 = *Normal Operation; No stall (iPU 3K)
0 = Stall
1 = *Normal Operation(iPU 3K)
0 = Lan number reversed
1 = Disabled (iPU 3K)
0 = *Enabled
00 = 1x8, 2x4 PCI Express* 01 = reserved 10 = 2x8 PCI Express* 11 = 1x16 PCI Express*
1 = *PEG Train immediatedly follow RESET# de-assertion (iPU 3K)
0 = PEG wait for BIOS for training
4
Note
H & S processor used only
CFG4
R455 1K_4
H & S processor used only
H & S processor used only
3
A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Monday, February 22, 2016
Date: Sheet
Monday, February 22, 2016
Date: Sheet
Monday, February 22, 2016
2
Date: Sheet
PROJECT :
Skylake PCH-LP 15/19 (POWER)
Skylake PCH-LP 15/19 (POWER)
Skylake PCH-LP 15/19 (POWER)
ZRW
ZRW
ZRW
1A
1A
1A
of
9 46
of
9 46
of
1
9 46
5
4
3
2
1
Skylake ULT (GND)
A67
A70
AA2
AA4
AA65
AA68
AB15
AB16
AB18
AB21
AB8
AD13
AD16
AD19
AD20
AD21
AD62
AD8
AE64
AE65
AE66
AE67
AE68
AE69
AF1
AF10
AF15
AF17
AF2
AF4
AF63
AG16
AG17
AG18
AG19
AG20
AG21
AG71
AH13
AH6
AH63
AH64
AH67
AJ15
AJ18
AJ20
AJ4
AK11
AK16
AK18
AK21
AK22
AK27
AK63
AK68
AK69
AK8
AL2
AL28
AL32
AL35
AL38
AL4
AL45
AL48
AL52
AL55
AL58
AL64
A5
SKL_ULT
GND 1 OF 3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SKL_ULT/BGA
D
C
B
A
5
16 OF 20
U34P
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AL65
AL66
AM13
AM21
AM25
AM27
AM43
AM45
AM46
AM55
AM60
AM61
AM68
AM71
AM8
AN20
AN23
AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48
AR5
AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58
4
AT63
AT68
AT71
AU10
AU15
AU20
AU32
AU38
AV1
AV68
AV69
AV70
AV71
AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57
AW6
AW60
AW62
AW64
AW66
AW8
AY66
B10
B14
B18
B22
B30
B34
B39
B44
B48
B53
B58
B62
B66
B71
BA1
BA10
BA14
BA18
BA2
BA23
BA28
BA32
BA36
F68
BA45
SKL_ULT
GND 2 OF 3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SKL_ULT/BGA
17 OF 20
U34Q
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BA49
BA53
BA57
BA6
BA62
BA66
BA71
BB18
BB26
BB30
BB34
BB38
BB43
BB55
BB6
BB60
BB64
BB67
BB70
C1
C25
C5
D10
D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58
D6
D62
D66
D69
E11
E15
E18
E21
E46
E50
E53
E56
E6
E65
E71
F1
F13
F2
F22
F23
F27
F28
F32
F33
F35
F37
F38
F4
F40
F42
BA41
3
G10
G22
G43
G45
G48
G52
G55
G58
G60
G63
G66
H15
H18
H71
J11
J13
J25
J28
J32
J35
J38
J42
K16
K18
K22
K61
K63
K64
K65
K66
K67
K68
K70
K71
L11
L16
L17
F8
G5
G6
J8
SKL_ULT
GND 3 OF 3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SKL_ULT/BGA
18 OF 20
U34R
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21
AW69
RSVD_AW69
AW68
+1.8V_S5
R491 *0_4
C614
*1U/6.3V_4
Reserve 1uF no stuff in CPU U11,U12 ball support Cannonlake-U PCH
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
RSVD_AW68
AU56
RSVD_AU56
AW48
RSVD_AW48
C7
RSVD_C7
U12
RSVD_U12
U11
RSVD_U11
H11
RSVD_H11
REV = 1
Skylake 10/17/18 (GND)
Skylake 10/17/18 (GND)
Skylake 10/17/18 (GND)
Monday, February 22, 2016
Monday, February 22, 2016
Monday, February 22, 2016
U34T
SKL_ULT/BGA
?
SKL_ULT
SPARE
RSVD_F6
RSVD_E3
RSVD_C11
RSVD_B11
RSVD_A11
RSVD_D12
RSVD_C12
RSVD_F52
20 OF 20
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
1
ZRW
ZRW
ZRW

F6
E3
C11
B11
A11
D12
C12
F52
?
of
10 46
of
10 46
of
10 46
D
C
B
A
1A
1A
1A
5
4
3
2
1
+2.5V
+3V

D
C
B
+VDDQ
M_A_A[13:0](3)
D
M_A_WE#(3)
M_A_CAS#(3)
M_A_RAS#(3)
+1.2VSUS
R315 240/F_4
M_A_EVENT#
+3V
C
B
R313 *10K_4
CHA_SA0
R322 10K_4
R311 *10K_4
CHA_SA1
R320 10K_4
R332 *10K_4
CHA_SA2
R333 10K_4
DDR3_DRAMRST#(3,12)
M_A_ODT0_DIMM(3)
M_A_ODT1_DIMM(3)
+1.2VSUS
CLK_SCLK(7,12,19,26)
CLK_SDATA(7,12,19,26)
M_A_ACT#(3)
M_A_PARITY(3)
M_A_ALERT#(3)
M_A_BA#0(3)
M_A_BA#1(3)
M_A_BG#0(3)
M_A_BG#1(3)
M_A_CS#0(3)
M_A_CS#1(3)
M_A_CKE0(3)
M_A_CKE1(3)
M_A_CLK0(3)
M_A_CLK0#(3)
M_A_CLK1(3)
M_A_CLK1#(3)
R319 240/F_4
R305 240/F_4
R308 240/F_4
R309 240/F_4
R318 240/F_4
R304 240/F_4
R317 240/F_4
R316 240/F_4
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_EVENT#
C460 *0.1U/16V_4
CHA_SA0
CHA_SA1
CHA_SA2
+1.2VSUS
TP41
TP40
M_A_CB0
M_A_CB1
M_A_CB2
M_A_CB3
M_A_CB4
M_A_CB5
M_A_CB6
M_A_CB7
P/N and F/P
JDIM2A
144
A0
133
A1
132
A2
131
A3
128
A4
126
A5
127
A6
122
A7
125
A8
121
A9
146
A10/AP
120
A11
119
A12
158
A13
151
A14/WE#
156
A15/CAS#
152
A16/RAS#
162
S2#/C0
165
S3#/C1
114
ACT#
143
PARITY
116
ALERT#
134
EVENT#
108
RESET#
150
BA0
145
BA1
115
BG0
113
BG1
149
S0#
157
S1#
109
CKE0
110
CKE1
137
CK0
139
CK0#
138
CK1
140
CK1#
155
ODT0
161
ODT1
253
SCL
254
SDA
256
SA0
260
SA1
166
SA2
92
CB0
91
CB1
101
CB2
105
CB3
88
CB4
87
CB5
100
CB6
104
CB7
12
DM0
33
DM1
54
DM2
75
DM3
178
DM4
199
DM5
220
DM6
241
DM7
96
DM8
8
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
(260P)
DDR4 SODIMM 260 PIN
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7
DQS#8
M_A_DQ0
7
M_A_DQ1
20
M_A_DQ3
21
M_A_DQ6
4
M_A_DQ5
3
M_A_DQ4
16
M_A_DQ7
17
M_A_DQ2
28
M_A_DQ9
29
M_A_DQ8
41
M_A_DQ11
42
M_A_DQ10
24
M_A_DQ13
25
M_A_DQ12
38
M_A_DQ14
37
M_A_DQ15
50
M_A_DQ21
49
M_A_DQ16
62
M_A_DQ19
63
M_A_DQ22
46
M_A_DQ17
45
M_A_DQ20
58
M_A_DQ23
59
M_A_DQ18
70
M_A_DQ25
71
M_A_DQ28
83
M_A_DQ27
84
M_A_DQ30
66
M_A_DQ24
67
M_A_DQ29
79
M_A_DQ26
80
M_A_DQ31
174
M_A_DQ33
173
M_A_DQ37
187
M_A_DQ35
186
M_A_DQ34
170
M_A_DQ36
169
M_A_DQ32
183
M_A_DQ38
182
M_A_DQ39
195
M_A_DQ45
194
M_A_DQ41
207
M_A_DQ46
208
M_A_DQ42
191
M_A_DQ44
190
M_A_DQ40
203
M_A_DQ47
204
M_A_DQ43
216
M_A_DQ52
215
M_A_DQ53
228
M_A_DQ50
229
M_A_DQ51
211
M_A_DQ48
212
M_A_DQ49
224
M_A_DQ55
225
M_A_DQ54
237
M_A_DQ63
236
M_A_DQ58
249
M_A_DQ56
250
M_A_DQ61
232
M_A_DQ59
233
M_A_DQ62
245
M_A_DQ60
246
M_A_DQ57
13
M_A_DQS0
34
M_A_DQS1
55
M_A_DQS2
76
M_A_DQS3
179
M_A_DQS4
200
M_A_DQS5
221
M_A_DQS6
242
M_A_DQS7
97
M_A_DQS8
11
M_A_DQS#0
32
M_A_DQS#1
53
M_A_DQS#2
74
M_A_DQS#3
177
M_A_DQS#4
198
M_A_DQS#5
219
M_A_DQS#6
240
M_A_DQS#7
95
M_A_DQS#8
M_A_DQ[63:0] (3)
0-7
8-15
+1.2VSUS
2250mA
16-23
24-31
32-39
40-47
48-55
+1.2VSUS
R306
56-63
M_A_DQS[7:0] (3)
M_A_DQS#[7:0] (3)
M_A_DQS8
M_A_DQS#8
240/F_4
R307
240/F_4
+1.2VSUS
12/21 Change JDIM2 footprint to "ddr4-d4as0-26001-1p52-std-smt " for SMT requset
VREF DQ0 M1 Solution
+VREF_CA_CPU
1
C473
0.022U/25V_4
2
JDIM2B
111
VDD1
112
VDD2
117
VDD3
118
VDD4
123
VDD5
124
VDD6
129
VDD7
130
VDD8
135
VDD9
136
VDD10
141
VDD11
142
VDD12
147
VDD13
148
VDD14
153
VDD15
154
VDD16
159
VDD17
160
VDD18
163
VDD19
1
VSS1
5
VSS2
9
VSS3
15
VSS4
19
VSS5
23
VSS6
27
VSS7
31
VSS8
35
VSS9
39
VSS10
43
VSS11
47
VSS12
51
VSS13
57
VSS14
61
VSS15
65
VSS16
69
VSS17
73
VSS18
77
VSS19
81
VSS20
85
VSS21
89
VSS22
93
VSS23
99
VSS24
103
VSS25
107
VSS26
167
VSS27
171
VSS28
175
VSS29
181
VSS30
185
VSS31
189
VSS32
193
VSS33
197
VSS34
201
VSS35
205
VSS36
209
VSS37
213
VSS38
217
VSS39
223
VSS40
227
VSS41
231
VSS42
235
VSS43
239
VSS44
243
VSS45
247
VSS46
251
VSS47
R327 2/F_6
R334 24.9/F_4
DDR4 SODIMM 260 PIN
VDDSPD
VREF_CA
(260P)
+1.2VSUS
255
257
VPP1
259
VPP2
258
VTT
164
2
VSS48
6
VSS49
10
VSS50
14
VSS51
18
VSS52
22
VSS53
26
VSS54
30
VSS55
36
VSS56
40
VSS57
44
VSS58
48
VSS59
52
VSS60
56
VSS61
60
VSS62
64
VSS63
68
VSS64
72
VSS65
78
VSS66
82
VSS67
86
VSS68
90
VSS69
94
VSS70
98
VSS71
102
VSS72
106
VSS73
168
VSS74
172
VSS75
176
VSS76
180
VSS77
184
VSS78
188
VSS79
192
VSS80
196
VSS81
202
VSS82
206
VSS83
210
VSS84
214
VSS85
218
VSS86
222
VSS87
226
VSS88
230
VSS89
234
VSS90
238
VSS91
244
VSS92
248
VSS93
252
VSS94
261
GND
262
GND
R321 1K/F_4
VREF_CA_DIMM0
R328 1K/F_4
C379 2.2U/6.3V/X7R_6
C377 0.1U/25V_4
R271 *0_4
R282 *short/0_4
0.5A
600mA
VREF_CA_DIMM0
+2.5V_SUS
12/4 Change for +3.3V to +3V
+VDDQ_VTT
R325*0_4
Place these Caps near So-Dimm1.
1uF/10uF 4pcs on each side of connector
+1.2VSUS
C399 1U/6.3V_4
C391 1U/6.3V_4
C408 1U/6.3V_4
C381 1U/6.3V_4
C449 1U/6.3V_4
C414 1U/6.3V_4
A
+1.2VSUS(3,5,12,33)
+VDDQ_VTT(12,33)
+3V(2,4,6,7,8,9,12,13,15,19,20,21,22,23,24,25,26,27,28,30,31,32,33,34,37,38,39)
5
4
C427 1U/6.3V_4
C438 1U/6.3V_4
C392 10U/6.3V_6
C385 10U/6.3V_6
C383 10U/6.3V_6
C382 10U/6.3V_6
C393 10U/6.3V_6
C426 10U/6.3V_6
C416 10U/6.3V_6
C386 10U/6.3V_6
3
+VDDQ_VTT
+3V
C425 1U/6.3V_4
C412 1U/6.3V_4
C423 1U/6.3V_4
C415 1U/6.3V_4
C409 10U/6.3V_6
C444 0.1U/16V_4
C441 2.2U/6.3V_6
VREF_CA_DIMM0
+2.5V_SUS
C465 0.1U/16V_4
C464 2.2U/6.3V_6
C374 0.1U/16V_4
C378 2.2U/6.3V_6
A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Monday, February 22, 2016
Date: Sheet
Monday, February 22, 2016
Date: Sheet
Monday, February 22, 2016
2
Date: Sheet
PROJECT :
DDR4 DIMM-RVS(5.2H) CHA
DDR4 DIMM-RVS(5.2H) CHA
DDR4 DIMM-RVS(5.2H) CHA
ZRW
ZRW
ZRW
11 46
11 46
11 46
1
1A
1A
1A
of
of
of
5
4
3
2
1
M_B_A[13:0](3)
D
M_B_WE#(3)
M_B_CAS#(3)
M_B_RAS#(3)
M_B_ACT#(3)
M_B_PARITY(3)
+1.2VSUS
R301 240/F_4
M_B_EVENT#
+3V
C
R302
R300 *10K_4
CHB_SA0
R294 10K_4
B
10K_4
CHB_SA1
R295 *10K_4
R290 *10K_4
CHB_SA2
R287 10K_4
DDR3_DRAMRST#(3,11)
+1.2VSUS
M_B_ODT0_DIMM(3)
M_B_ODT1_DIMM(3)
CLK_SCLK(7,11,19,26)
CLK_SDATA(7,11,19,26)
M_B_ALERT#(3)
M_B_BA#0(3)
M_B_BA#1(3)
M_B_BG#0(3)
M_B_BG#1(3)
M_B_CS#0(3)
M_B_CS#1(3)
M_B_CKE0(3)
M_B_CKE1(3)
M_B_CLK0(3)
M_B_CLK0#(3)
M_B_CLK1(3)
M_B_CLK1#(3)
R292 240/F_4
R272 240/F_4
R280 240/F_4
R275 240/F_4
R293 240/F_4
R273 240/F_4
R288 240/F_4
R303 240/F_4
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_EVENT#
C461 *0.1U/16V_4
CHB_SA0
CHB_SA1
CHB_SA2
+1.2VSUS
TP39
TP38
M_B_CB0
M_B_CB1
M_B_CB2
M_B_CB3
M_B_CB4
M_B_CB5
M_B_CB6
M_B_CB7
JDIM1A
144
A0
133
A1
132
A2
131
A3
128
A4
126
A5
127
A6
122
A7
125
A8
121
A9
146
A10/AP
120
A11
119
A12
158
A13
151
A14/WE#
156
A15/CAS#
152
A16/RAS#
162
S2#/C0
165
S3#/C1
114
ACT#
143
PARITY
116
ALERT#
134
EVENT#
108
RESET#
150
BA0
145
BA1
115
BG0
113
BG1
149
S0#
157
S1#
109
CKE0
110
137
139
138
140
155
161
253
254
256
260
166
92
91
101
105
88
87
100
104
12
33
54
75
178
199
220
241
96
CKE1
CK0
CK0#
CK1
CK1#
ODT0
ODT1
SCL
SDA
SA0
SA1
SA2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
DDR4 SODIMM 260 PIN
(260P)
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7
DQS#8
8
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
M_B_DQ9
7
M_B_DQ8
20
M_B_DQ10
21
M_B_DQ15
4
M_B_DQ13
3
M_B_DQ12
16
M_B_DQ11
17
M_B_DQ14
28
M_B_DQ5
29
M_B_DQ1
41
M_B_DQ6
42
M_B_DQ7
24
M_B_DQ4
25
M_B_DQ0
38
M_B_DQ2
37
M_B_DQ3
50
M_B_DQ17
49
M_B_DQ21
62
M_B_DQ23
63
M_B_DQ19
46
M_B_DQ16
45
M_B_DQ20
58
M_B_DQ22
59
M_B_DQ18
70
M_B_DQ28
71
M_B_DQ25
83
M_B_DQ26
84
M_B_DQ27
66
M_B_DQ29
67
M_B_DQ24
79
M_B_DQ30
80
M_B_DQ31
174
M_B_DQ37
173
M_B_DQ32
187
M_B_DQ39
186
M_B_DQ34
170
M_B_DQ36
169
M_B_DQ33
183
M_B_DQ38
182
M_B_DQ35
195
M_B_DQ44
194
M_B_DQ45
207
M_B_DQ42
208
M_B_DQ47
191
M_B_DQ41
190
M_B_DQ40
203
M_B_DQ43
204
M_B_DQ46
216
M_B_DQ49
215
M_B_DQ53
228
M_B_DQ54
229
M_B_DQ50
211
M_B_DQ52
212
M_B_DQ48
224
M_B_DQ51
225
M_B_DQ55
237
M_B_DQ56
236
M_B_DQ60
249
M_B_DQ58
250
M_B_DQ62
232
M_B_DQ61
233
M_B_DQ57
245
M_B_DQ59
246
M_B_DQ63
13
M_B_DQS1
34
M_B_DQS0
55
M_B_DQS2
76
M_B_DQS3
179
M_B_DQS4
200
M_B_DQS5
221
M_B_DQS6
242
M_B_DQS7
97
M_B_DQS8
11
M_B_DQS#1
32
M_B_DQS#0
53
M_B_DQS#2
74
M_B_DQS#3
177
M_B_DQS#4
198
M_B_DQS#5
219
M_B_DQS#6
240
M_B_DQS#7
95
M_B_DQS#8
M_B_DQ[63:0] (3)
8-15
0-7
16-23
24-31
32-39
40-47
48-55
56-63
M_B_DQS[7:0] (3)
M_B_DQS#[7:0] (3)
M_B_DQS8
M_B_DQS#8
R277
240/F_4
R278
240/F_4
+1.2VSUS
2250mA
+1.2VSUS
+1.2VSUS
JDIM1B
111
VDD1
112
VDD2
117
VDD3
118
VDD4
123
VDD5
124
VDD6
129
VDD7
130
VDD8
135
VDD9
136
VDD10
141
VDD11
142
VDD12
147
VDD13
148
VDD14
153
VDD15
154
VDD16
159
VDD17
160
VDD18
163
VDD19
1
VSS1
5
VSS2
9
VSS3
15
VSS4
19
VSS5
23
VSS6
27
VSS7
31
VSS8
35
VSS9
39
VSS10
43
VSS11
47
VSS12
51
VSS13
57
VSS14
61
VSS15
65
VSS16
69
VSS17
73
VSS18
77
VSS19
81
VSS20
85
VSS21
89
VSS22
93
VSS23
99
VSS24
103
VSS25
107
VSS26
167
VSS27
171
VSS28
175
VSS29
181
VSS30
185
VSS31
189
VSS32
193
VSS33
197
VSS34
201
VSS35
205
VSS36
209
VSS37
213
VSS38
217
VSS39
223
VSS40
227
VSS41
231
VSS42
235
VSS43
239
VSS44
243
VSS45
247
VSS46
251
VSS47
12/21 Change JDIM1 footprint to "ddr4-d4ar0-26001-1p52-rvs-smt " for SMT requset
C395 2.2U/6.3V/X7R_6
C401 0.1U/25V_4
255
257
259
258
164
VREF_CA_DIMM1
2
6
10
14
18
22
26
30
36
40
44
48
52
56
60
64
68
72
78
82
86
90
94
98
102
106
168
172
176
180
184
188
192
196
202
206
210
214
218
222
226
230
234
238
244
248
252
261
262
R276 *0_4
R281 *short/0_4
0.5A
600mA
VDDSPD
VPP1
VPP2
VTT
VREF_CA
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
(260P)
DDR4 SODIMM 260 PIN
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
GND
GND
+2.5V
+3V
+2.5V_SUS
12/4 Change for +3.3V to +3V
+VDDQ_VTT
+3V(2,4,6,7,8,9,11,13,15,19,20,21,22,23,24,25,26,27,28,30,31,32,33,34,37,38,39)
+1.2VSUS(3,5,11,33)
+VDDQ_VTT(11,33)
D
C
B

For EMI RESERVE
+1.2VSUS
EC1 *120P/50V_4
EC8 *120P/50V_4
EC2 *120P/50V_4
EC3 120P/50V_4
EC4 *120P/50V_4
EC5 *120P/50V_4
EC6 *120P/50V_4
5
+VDDQ_VTT
EC7 *120P/50V_4
EC14 *120P/50V_4
A
+1.2VSUS
EC16 *120P/50V_4
EC10 *120P/50V_4
EC12 *120P/50V_4
EC9 *0.1U/16V_4
EC11 *0.1U/16V_4
EC15 *0.1U/16V_4
EC13 *0.1U/16V_4
4
1uF/10uF 4pcs on each side of connector
+1.2VSUS
Place these Caps near So-Dimm0.
C380 1U/6.3V_4
C448 1U/6.3V_4
C458 1U/6.3V_4
C454 1U/6.3V_4
C457 1U/6.3V_4
C456 1U/6.3V_4
C436 1U/6.3V_4
C432 1U/6.3V_4
C469 10U/6.3V_6
C437 10U/6.3V_6
C470 10U/6.3V_6
C468 10U/6.3V_6
C439 10U/6.3V_6
C463 10U/6.3V_6
C462 10U/6.3V_6
C440 10U/6.3V_6
+VDDQ_VTT
VREF_CA_DIMM1
+2.5V_SUS
+3V
C471 1U/6.3V_4
C453 1U/6.3V_4
C459 1U/6.3V_4
C467 1U/6.3V_4
C424 1U/6.3V_4
C411 0.1U/16V_4
C413 2.2U/6.3V_6
C434 0.1U/16V_4
C430 2.2U/6.3V_6
C428 0.1U/16V_4
C431 2.2U/6.3V_6
3
VREF DQ1 M1 Solution
+VREFDQ_SB_M3
+VREFDQ_SB_M3
2
R298 2/F_6
1
C419
0.022U/25V_4
2
R299
24.9/F_4
+1.2VSUS
R286 1K/F_4
VREF_CA_DIMM1
R297 1K/F_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Monday, February 22, 2016
Date: Sheet
Monday, February 22, 2016
Date: Sheet
Monday, February 22, 2016
Date: Sheet
R296*0_4
+VDDQ
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
DDR4 DIMM-STD(5.2H) CHB
DDR4 DIMM-STD(5.2H) CHB
DDR4 DIMM-STD(5.2H) CHB
ZRW
ZRW
ZRW
1
of
12 46
of
12 46
of
12 46
A
1A
1A
1A
+3V_GFX
Z8V
Z8V
Z8V
8

R1471 *EV@10K_4
PEGX_RST#
R1469 EV@100K_4
13 46
13 46
13 46
8
A
B
C
D
1A
1A
1A
of
of
of
6
3V MAIN POWER
+3V_GFX
3/11 GC6 timing issue from 200K change to 100K
R1140 EV@10K_4
R1145 *EV@10K_4
3
2
1
2
1
C1630
EV@1000p/50V_4
R1148 EV@100K_4
Q1017 EV@2N7002K
+3V
5
3
GC6 FBVDDQ_EN
GC6_FB_EN(4,16)
GPU_PWR_GD(38)
6
SYS_PEX_RST_MON#(16)
C1621 EV@0.1U/16V_4X
4
RST_MON#
U1032 EV@74AHC1G09GW
GPU_PEX_RST_HOLD#(16)
RST_MON#
GC6_FB_EN
C1294 EV@0.022U/25V_4
2
C1311 EV@0.022U/25V_4
1A-7
R1470
GC6@BAT54CW_200MA
2
Q1011
5
GC6:+3V_MAIN
GC6 Power control
+3V_MAIN_EN(16)
GC6 PEGX_RST#
+1.05V_GFX
B2A
PLACE NEAR GPU
PLACE NEAR GPU
PLACE UNDER GPU BALLS
3
5
+3V_GFX
already PU@P.17
PLTRST#(8,22,24,25,28)
DGPU_HOLD_RST#(4)
CLK_PEGA_REQ# (6)
AG19
AG21
AG22
AG24
AH21
AH25
AG13
AG15
AG16
AG18
AG25
AH15
AH18
AH26
AH27
AJ27
AK27
AL27
AM28
AN28
AJ28
AL11
AC6
AJ4
AJ5
C15
D19
D20
D23
D26
H31
T8
V32
Y1
Y2
Y3
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
J8
K8
L8
M8
2
U1030A N15P-GT
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5
PEX_IOVDD_6
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
PEX_IOVDDQ_14
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
3V3_AON_1
3V3_AON_2
3V3_MAIN_1
3V3_MAIN_2
2
[PEG Interface]
PEX_TSTCLK_OUT_N
1
&)*(
To be placed no further from the GPU than bewteen the PS and GPU
A
B
C
D
+1.05V_GFX
C1175 EV@22U/6.3V_6X
C1139 EV@22U/6.3V_6X
C1143 EV@22U/6.3V_6X
C1140 EV@22U/6.3V_6X
C1138 EV@10U/6.3V_6X
C1104 EV@10U/6.3V_6X
C1102 EV@10U/6.3V_6X
C1103 EV@10U/6.3V_6X
PLACE NEAR BALLS
C1159 EV@1U/6.3V_4X
C1182 EV@1U/6.3V_4X
C1165 EV@1U/6.3V_4X
C1077 EV@1U/6.3V_4X
PLACE UNDER BGA
C1097 EV@4.7U/10V_6X
C1126 EV@4.7U/10V_6X
PLACE CLOSE TO BGA
C1343 EV@4.7U/6.3V_4X
C1210 EV@1U/6.3V_4X
C1209 EV@0.1u/16V_4
C1183 *EV@0.1U/16V_4X
C1188 *EV@0.1U/16V_4X
PLACE CLOSE TO GPU BALLS
+3V_GFX
+3V_MAIN
1
(
PLACE CLOSE TO BGA
C1344 EV@4.7U/6.3V_4X
C1200 EV@1U/6.3V_4X
PLACE CLOSE TO GPU BALLS
C1201 EV@0.1u/16V_4
C1302 EV@0.1u/16V_4
PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N
PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N
PEX_REFCLK
PEX_REFCLK_N
PEX_TSTCLK_OUT
PEX_RST_N
PEX_CLKREQ_N
PEX_TERMP
TESTMODE
PEX_PLLVDD
PEX_PLL_HVDD
PEX_SVDD_3V3
3.3V_AUX_NC
VDD_SENSE
GND_SENSE
3
AN12
AM12
AN14
AM14
AP14
AP15
AN15
AM15
AN17
AM17
AP17
AP18
AN18
AM18
AN20
AM20
AP20
AP21
AN21
AM21
AN23
AM23
AP23
AP24
AN24
AM24
AN26
AM26
AP26
AP27
AN27
AM27
PEG_RXP0_C
PEG_RXN0_C
PEG_RXP1_C
PEG_RXN1_C
PEG_RXP2_C
PEG_RXN2_C
PEG_RXP3_C
PEG_RXN3_C
&'(
C1186 EV@0.22U/10V_4
C1179 EV@0.22U/10V_4
C1176 EV@0.22U/10V_4
C1167 EV@0.22U/10V_4
C1136 EV@0.22U/10V_4
C1118 EV@0.22U/10V_4
C1162 EV@0.22U/10V_4
C1152 EV@0.22U/10V_4
CLK_PCIE_VGA (6)
CLK_PCIE_VGA# (6)
R1063 *EV@200/F_4
R1092 EV@10K_4
R1056 EV@2.49K/F_4
R1462 EV@10K_4
&##(
PLACE NEAR BGA
VGA_VCCSENSE (38)
VGA_VSSSENSE (38)
AK14
AJ14
AH14
AG14
AK15
AJ15
AL16
AK16
AK17
AJ17
AH17
AG17
AK18
AJ18
AL19
AK19
AK20
AJ20
AH20
AG20
AK21
AJ21
AL22
AK22
AK23
AJ23
AH23
AG23
AK24
AJ24
AL25
AK25
AL13
AK13
AJ26
PEX_TSTCLK
AK26
PEX_TSTCLK#
AJ11
NC
AJ12
PEGX_RST#
AK12
PEX_CLKREQ#
AP29
PEX_TERMP
AK11
TESTMODE
AG26
PEX_PLLVDD
AH12
AG12
P8
3.3V_AUX
L4
L5
3
PEG_TX0 (6)
PEG_TX#0 (6)
PEG_TX1 (6)
PEG_TX#1 (6)
PEG_TX2 (6)
PEG_TX#2 (6)
PEG_TX3 (6)
PEG_TX#3 (6)
C1339EV@0.1u/16V_4
C1203EV@4.7U/6.3V_4X
C1303EV@4.7U/6.3V_4X
TP1016
4
PEGX_RST# (16)
4
+3V_GFX
+3V_GFX
PEG_RX0 (6)
PEG_RX#0 (6)
PEG_RX1 (6)
PEG_RX#1 (6)
PEG_RX2 (6)
PEG_RX#2 (6)
PEG_RX3 (6)
PEG_RX#3 (6)
R1397 EV@0_6
C1575 EV@4.7U/6.3V_4X
C1574 EV@1U/6.3V_4X
C1076 EV@0.1u/16V_4
PEX_CLKREQ#
EV@2N7002KW_115MA
+3V_MAIN
1
7
+3V_GFX
1
Q1023 EV@AO3413
3
*EV@0_4
1
2
D1015
+3V_MAIN
+3V
C1613 EV@0.1U/16V_4X
5
2
1
PEGX_RST#
3
1
R1444 EV@100K_4
2
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Monday, February 22, 2016
Monday, February 22, 2016
Date: Sheet
Monday, February 22, 2016
Date: Sheet
Date: Sheet
7
4
3
U1031 EV@MC74VHC1G08
FBVDDQ_EN (39)
C3A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
N16S-GT - 1/5 (PCIE)
N16S-GT - 1/5 (PCIE)
N16S-GT - 1/5 (PCIE)
A
FBA_DBI[7:0](18)
B
FBA_EDC[7:0](18)
PLACE CLOSE TO GPU BALLS
C
D
1
FBA_CMD0(18)
FBA_CMD1(18)
FBA_CMD2(18)
FBA_CMD3(18)
FBA_CMD4(18)
FBA_CMD5(18)
FBA_CMD6(18)
FBA_CMD7(18)
FBA_CMD8(18)
FBA_CMD9(18)
FBA_CMD10(18)
FBA_CMD11(18)
FBA_CMD12(18)
FBA_CMD13(18)
FBA_CMD14(18)
FBA_CMD15(18)
FBA_CMD16(18)
FBA_CMD17(18)
FBA_CMD18(18)
FBA_CMD19(18)
FBA_CMD20(18)
FBA_CMD21(18)
FBA_CMD22(18)
FBA_CMD23(18)
FBA_CMD24(18)
FBA_CMD25(18)
FBA_CMD26(18)
FBA_CMD27(18)
FBA_CMD28(18)
FBA_CMD29(18)
FBA_CMD30(18)
FBA_CMD31(18)
GDDR5 NO USE
+1.35V_GFX
C1065 EV@1U/10V_4X
C1061 EV@1U/10V_4X
C1116 EV@1U/10V_4X
C1107 EV@1U/10V_4X
C1088 EV@0.1U/16V_4X
C1193 EV@0.1U/16V_4X
C1199 EV@0.1U/16V_4X
C1174 EV@0.1U/16V_4X
PLACE CLOSE TO BGA
C1164 EV@4.7U/6.3V_4X
C1137 EV@4.7U/6.3V_4X
C1178 EV@4.7U/6.3V_4X
C1215 EV@4.7U/6.3V_4X
C1028 EV@10U/6.3V_6X
C1084 EV@10U/6.3V_6X
C1051 EV@22U/6.3V_6X
C1075 EV@22U/6.3V_6X
B2A
B2A
1
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31
FBA_DBI0
FBA_DBI1
FBA_DBI2
FBA_DBI3
FBA_DBI4
FBA_DBI5
FBA_DBI6
FBA_DBI7
FBA_EDC0
FBA_EDC1
FBA_EDC2
FBA_EDC3
FBA_EDC4
FBA_EDC5
FBA_EDC6
FBA_EDC7
AA31
AA29
AA28
AC34
AC33
AA32
AA33
W31
AA34
AD31
AL29
AM32
AF34
AE31
AK30
AN33
AF33
AF30
AK31
AM34
AF32
AA27
AA30
AB27
AB33
AC27
AD27
AE27
AF27
AG27
W27
W30
W33
M32
M31
G31
M33
M30
H30
M34
H10
H11
H12
H13
H14
H18
H19
H20
H21
H22
H23
H24
M27
N27
R27
H15
H16
U30
T31
U29
R34
R33
U32
U33
U28
V28
V29
V30
U34
U31
V34
V33
Y32
Y28
Y29
Y30
Y31
Y34
Y33
V31
P30
F31
F34
E33
E34
B13
B19
E13
E19
H8
H9
L27
P27
T27
T30
T33
Y27
B16
E16
V27
2
U1030B N15P-GT
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7
FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9
FBVDDQ_10
FBVDDQ_12
FBVDDQ_13
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
FBVDDQ_28
FBVDDQ_29
FBVDDQ_30
FBVDDQ_31
FBVDDQ_32
FBVDDQ_33
FBVDDQ_34
FBVDDQ_35
FBVDDQ_36
FBVDDQ_37
FBVDDQ_38
FBVDDQ_39
FBVDDQ_44
FBVDDQ_AON_1
FBVDDQ_AON_2
FBVDDQ_AON_3
FBVDDQ_AON_4
FBVDDQ_AON_5
FBVDDQ_AON_6
FBVDDQ_AON_7
FBVDDQ_AON_8
2
[MEMORY I/F A]
FB_VDDQ_SENSE
FB_GND_SENSE
FB_CAL_PD_VDDQ
FB_CAL_PU_GND
FB_CALTERM_GND
FBA_D00
FBA_D01
FBA_D02
FBA_D03
FBA_D04
FBA_D05
FBA_D06
FBA_D07
FBA_D08
FBA_D09
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
FBA_CLK0
FBA_CLK0_N
FBA_CLK1
FBA_CLK1_N
FBA_CMD32
FBA_CMD33
FBA_CMD34
FBA_CMD35
FB_VREF
FBA_WCK01
FBA_WCK01_N
FBA_WCK23
FBA_WCK23_N
FBA_WCK45
FBA_WCK45_N
FBA_WCK67
FBA_WCK67_N
FB_CLAMP
FB_DLL_AVDD
FBA_PLL_AVDD
NC
NC
NC
NC
NC
NC
NC
NC
3
L28
M29
L29
M28
N31
P29
R29
P28
J28
H29
J29
H28
G29
E31
E32
F30
C34
D32
B33
C33
F33
F32
H33
H32
P34
P32
P31
P33
L31
L34
L32
L33
AG28
AF29
AG29
AF28
AD30
AD29
AC29
AD28
AJ29
AK29
AJ30
AK28
AM29
AM31
AN29
AM30
AN31
AN32
AP30
AP32
AM33
AL31
AK33
AK32
AD34
AD32
AC30
AD33
AF31
AG34
AG32
AG33
R30
R31
AB31
AC31
R28
FBA_DEBUG0_K
AC28
FBA_DEBUG1_K
R32
FBA_DEBUG0
AC32
FBA_DEBUG1
H26
K31
L30
H34
J34
AG30
AG31
AJ34
AK34
J30
J31
J32
J33
AH31
AJ31
AJ32
AJ33
E1
PS_FB_CLAMP
K27
U27
F1
FBVDDQ_SENSE
F2
FB_GND_SENSE
J27
FB_CAL_PD_VDDQ
H27
FB_CAL_PU_GND
H25
FB_CAL_TERM_GND
3
VMA_DQ0
VMA_DQ1
VMA_DQ2
VMA_DQ3
VMA_DQ4
VMA_DQ5
VMA_DQ6
VMA_DQ7
VMA_DQ8
VMA_DQ9
VMA_DQ10
VMA_DQ11
VMA_DQ12
VMA_DQ13
VMA_DQ14
VMA_DQ15
VMA_DQ16
VMA_DQ17
VMA_DQ18
VMA_DQ19
VMA_DQ20
VMA_DQ21
VMA_DQ22
VMA_DQ23
VMA_DQ24
VMA_DQ25
VMA_DQ26
VMA_DQ27
VMA_DQ28
VMA_DQ29
VMA_DQ30
VMA_DQ31
VMA_DQ32
VMA_DQ33
VMA_DQ34
VMA_DQ35
VMA_DQ36
VMA_DQ37
VMA_DQ38
VMA_DQ39
VMA_DQ40
VMA_DQ41
VMA_DQ42
VMA_DQ43
VMA_DQ44
VMA_DQ45
VMA_DQ46
VMA_DQ47
VMA_DQ48
VMA_DQ49
VMA_DQ50
VMA_DQ51
VMA_DQ52
VMA_DQ53
VMA_DQ54
VMA_DQ55
VMA_DQ56
VMA_DQ57
VMA_DQ58
VMA_DQ59
VMA_DQ60
VMA_DQ61
VMA_DQ62
VMA_DQ63
VMA_DQ0 (18)
VMA_DQ1 (18)
VMA_DQ2 (18)
VMA_DQ3 (18)
VMA_DQ4 (18)
VMA_DQ5 (18)
VMA_DQ6 (18)
VMA_DQ7 (18)
VMA_DQ8 (18)
VMA_DQ9 (18)
VMA_DQ10 (18)
VMA_DQ11 (18)
VMA_DQ12 (18)
VMA_DQ13 (18)
VMA_DQ14 (18)
VMA_DQ15 (18)
VMA_DQ16 (18)
VMA_DQ17 (18)
VMA_DQ18 (18)
VMA_DQ19 (18)
VMA_DQ20 (18)
VMA_DQ21 (18)
VMA_DQ22 (18)
VMA_DQ23 (18)
VMA_DQ24 (18)
VMA_DQ25 (18)
VMA_DQ26 (18)
VMA_DQ27 (18)
VMA_DQ28 (18)
VMA_DQ29 (18)
VMA_DQ30 (18)
VMA_DQ31 (18)
VMA_DQ32 (18)
VMA_DQ33 (18)
VMA_DQ34 (18)
VMA_DQ35 (18)
VMA_DQ36 (18)
VMA_DQ37 (18)
VMA_DQ38 (18)
VMA_DQ39 (18)
VMA_DQ40 (18)
VMA_DQ41 (18)
VMA_DQ42 (18)
VMA_DQ43 (18)
VMA_DQ44 (18)
VMA_DQ45 (18)
VMA_DQ46 (18)
VMA_DQ47 (18)
VMA_DQ48 (18)
VMA_DQ49 (18)
VMA_DQ50 (18)
VMA_DQ51 (18)
VMA_DQ52 (18)
VMA_DQ53 (18)
VMA_DQ54 (18)
VMA_DQ55 (18)
VMA_DQ56 (18)
VMA_DQ57 (18)
VMA_DQ58 (18)
VMA_DQ59 (18)
VMA_DQ60 (18)
VMA_DQ61 (18)
VMA_DQ62 (18)
VMA_DQ63 (18)
VMA_CLK0 (18)
VMA_CLK0# (18)
VMA_CLK1 (18)
VMA_CLK1# (18)
R1059*EV@60.4/F_4
R1055*EV@60.4/F_4
VMA_WCK01 (18)
VMA_WCK01# (18)
VMA_WCK23 (18)
VMA_WCK23# (18)
VMA_WCK45 (18)
VMA_WCK45# (18)
VMA_WCK67 (18)
VMA_WCK67# (18)
R1512 EV@10K_4
FB_PLLAVDD
+,##(
+1.35V_GFX
R1502 *EV@0_4
R1501 *EV@0_4
R1058 EV@40.2/F_4
R1057 EV@40.2/F_4
R1064 EV@60.4/F_4
PLACE CLOSE TO GPU BALLS
4
TP1003
TP1004
+1.35V_GFX
C1078 EV@0.1U/16V_4X
C1085 EV@0.1U/16V_4X
C1086 EV@22U/6.3V_6X
+1.35V_GFX
4
B2A
5
+1.05V_GFX
L1001EV@HCB1005KF-330T30
C574 close to K27 (under GPU) C575 close to U27 (under GPU)
C576 near to GPU
5
U1030C N15P-GT
D13
E14
F14
A12
B12
C14
B14
G15
F15
E15
D15
A14
D14
A15
B15
C17
D18
E18
F18
A20
B20
C18
B18
G18
G17
F17
D16
A18
D17
A17
B17
E17
E11
E3
A3
C9
F23
F27
C30
A24
D10
D5
C3
B9
E23
E28
B30
A23
D9
E4
B2
A9
D22
D28
A30
B23
FBB_CMD0
FBB_CMD1
FBC_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBC_CMD7
FBB_CMD8
FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CMD27
FBB_CMD28
FBB_CMD29
FBC_CMD30
FBC_CMD31
FBC_DQM0
FBC_DQM1
FBC_DQM2
FBC_DQM3
FBC_DQM4
FBC_DQM5
FBC_DQM6
FBC_DQM7
FBC_DQS_WP0
FBC_DQS_WP1
FBC_DQS_WP2
FBC_DQS_WP3
FBC_DQS_WP4
FBC_DQS_WP5
FBC_DQS_WP6
FBC_DQS_WP7
FBC_DQS_RN0
FBC_DQS_RN1
FBC_DQS_RN2
FBC_DQS_RN3
FBC_DQS_RN4
FBC_DQS_RN5
FBC_DQS_RN6
FBC_DQS_RN7
6
MEMORY I/F C
6
FBC_D00
FBC_D01
FBC_D02
FBC_D03
FBC_D04
FBC_D05
FBC_D06
FBC_D07
FBC_D08
FBC_D09
FBC_D10
FBC_D11
FBC_D12
FBC_D13
FBC_D14
FBC_D15
FBC_D16
FBC_D17
FBC_D18
FBC_D19
FBC_D20
FBC_D21
FBC_D22
FBC_D23
FBC_D24
FBC_D25
FBC_D26
FBC_D27
FBC_D28
FBC_D29
FBC_D30
FBC_D31
FBC_D32
FBC_D33
FBC_D34
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47
FBC_D48
FBC_D49
FBC_D50
FBC_D51
FBC_D52
FBC_D53
FBC_D54
FBC_D55
FBC_D56
FBC_D57
FBC_D58
FBC_D59
FBC_D60
FBC_D61
FBC_D62
FBC_D63
FBC_CLK0
FBC_CLK0_N
FBC_CLK1
FBC_CLK1_N
FBB_CMD32
FBB_CMD33
FBB_CMD34
FBB_CMD35
FBB_WCK01
FBB_WCK01_N
FBB_WCK23
FBB_WCK23_N
FBB_WCK45
FBB_WCK45_N
FBB_WCK67
FBB_WCK67_N
FBB_PLL_AVDD
7
G9
E9
G8
F9
F11
G11
F12
G12
G6
F5
E6
F6
F4
G4
E2
F3
C2
D4
D3
C1
B3
C4
B5
C5
A11
C11
D11
B11
D8
A8
C8
B8
F24
G23
E24
G24
D21
E21
G21
F21
G27
D27
G26
E27
E29
F29
E30
D30
A32
C31
C32
B32
D29
A29
C29
B29
B21
C23
A21
C21
B24
C24
B26
C26
D12
E12
E20
F20
G14
FBB_DEBUG0_K
G20
FBB_DEBUG1_K
C12
FBB_DEBUG0
C20
FBB_DEBUG1
F8
E8
A5
A6
D24
D25
WCK only for GDDR5
B27
C27
D6
NC
D7
NC
C6
NC
B6
NC
F26
NC
E26
NC
A26
NC
A27
NC
H17
FB_PLLAVDD
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Monday, February 22, 2016
Monday, February 22, 2016
Date: Sheet
Monday, February 22, 2016
Date: Sheet
Date: Sheet
7
R1087 *EV@60.4/F_4
R1069 *EV@60.4/F_4
C262 close to H27 (under GPU)
B2A
C1157 EV@0.1U/16V_4X
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
N16S-GT - 2/5 (Memory)
N16S-GT - 2/5 (Memory)
N16S-GT - 2/5 (Memory)
8
Z8V
Z8V
Z8V
14 45
14 45
14 45
8
TP1009
TP1008
+1.35V_GFX

of
of
of
A
B
C
D
1A
1A
1A
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