Quanta Z09 Schematic

5

4

3

2

1

VER : 3A

BOM P/N

Description

Z09 SYSTEM BLOCK DIAGRAM

D D

Memory Down

DDRIII-SODIMM1

256MB*16

Max. 2G

C C

B B

CCD Conn.

DMIC

BOM Option Table

A A

Reference

SNB@ IVB@ IV@

Optimize SKU

EV@

For Sandy bridge. For Ivy bridge. For UMA.

* do not stuff

Description

P14

mSATA - HDD

P20

SATA - HDD

P20

SATA - ODD

P21

USB3.0 *2 USB2.0 *2

USB2.0

P15

USB Port

(Charger)

P23

23

P

ALC271-VB6

AUDIO CODEC Daugther board

Speaker

5

Dual Channel DDR III 1333/1600 MHZ

P13

USB3.0(USB2.0)

P8 RTC

Azalia

P19

MIC/HP JACK

4

BATTERY

USB2.0

W25X16VSS1G

SPI FLASH

IMC

SATA

USB3.0

PCI-E x1

USB2.0

IHDA

Ivy Bridge

BGA 1023 17W

P2,3,4,5,6

FDI

Panther Point

PCH BGA 989

P7, 8, 9, 10, 11, 12

WPCE885

K/B Con.

P22

EM-6781-T3

HALL SENSOR

P8

DMI

LPC

EC

3

PCI-E X16

DMI(x4)

Display

PCI-E x1

LPC

eDP

SPI

P15

PCIE

2.5GT/s

Touch Pad Con.

NVIDIA GPU

N13P-GV 1GB

P27,28,29,30,31,32

X'TAL

32.768KHz

X'TAL 25MHz

SPI ROM

2M+4M

P19

Fan Driver

(128Mb x 32 IO x 4 pcs)

HDMI

PCIE-8

PCIE-3

PCIE-2

P8

P24

P19

X'TAL

27.0MHz

BCM57780

GIGA LAN

P17

X'TAL 25MHz

RTS5209-GR

Cardreader controller

Daugther board

Batery Charger

3V/5V

+VGPU_CORE

2

eDP Conn.

P15

HDMI Conn.

P16

MINI CARD WLAN+BT

USB-10

P19

P31

P32

P38

Size Document Number Rev

Date: Sheet of

RJ45 Conn.

Cardreader Conn.(2in1)

+1.05V

+1.8V/+1V

+VGPU_IO

P19

P18

+VGFX_AXG

P34

CPU core

P37

Discharger

P38

Thermal Protection

Quanta Computer Inc.

PROJECT :

Block Diagram

Z09

1 40Monday, April 09, 2012

1

P33

P37

3A

5

Ivy Bridge Processor (DMI,PEG,FDI)

DMI_TXN0<7> DMI_TXN1<7> DMI_TXN2<7>

D D

C C

B B

DP_COMPIO and ICOMPO signals should be shorted near balls and routed with

- typical impedance < 25 mohms

DMI_TXN3<7> DMI_TXP0<7>

DMI_TXP1<7> DMI_TXP2<7> DMI_TXP3<7>

DMI_RXN0<7> DMI_RXN1<7> DMI_RXN2<7> DMI_RXN3<7>

DMI_RXP0<7> DMI_RXP1<7> DMI_RXP2<7> DMI_RXP3<7>

FDI_TXN0<7> FDI_TXN1<7> FDI_TXN2<7> FDI_TXN3<7> FDI_TXN4<7> FDI_TXN5<7> FDI_TXN6<7> FDI_TXN7<7>

FDI_TXP0<7> FDI_TXP1<7> FDI_TXP2<7> FDI_TXP3<7> FDI_TXP4<7> FDI_TXP5<7> FDI_TXP6<7> FDI_TXP7<7>

FDI_FSYNC0<7> FDI_FSYNC1<7>

FDI_INT<7>

FDI_LSYNC0<7> FDI_LSYNC1<7>

eDP_ICOMPO 12mil eDP_COMPIO 4mil

EDP_AUX#<15> EDP_AUX<15>

EDP_TX0#<15>

EDP_TX0<15>

EDP_COMP INT_EDP_HPD#

EDP_AUX# EDP_AUX

EDP_TX0#

EDP_TX0

DP & PEG Compensation

+1.05V_VTT

A A

EDP_COMP

R564 24.9/F_4

+1.05V_VTT

PEG_COMP

R193 24.9/F_4

5

M2 P6 P1

P10

N3 P7 P3

P11

K1 M8 N4 R2

K3 M7 P4 T3

U7

W11

W1

AA6

W6

V4 Y2

AC9

U6

W10

W3

AA7

W7

T4 AA3 AC8

AA11 AC12

U11

AA10

AG8

AF3 AD2

AG11

AG4 AF4

AC3 AC4

AE11

AE7 AC1

AA4

AE10

AE6

eDP Hot-plug (Disable)

CAD Note: Place PU resistor within 2 inches of CPU

HPD PU/PD resistor values based on CRB and different to DG

4

U9A

DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3]

DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3]

DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3]

DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3]

FDI0_TX#[0] FDI0_TX#[1] FDI0_TX#[2] FDI0_TX#[3] FDI1_TX#[0] FDI1_TX#[1] FDI1_TX#[2] FDI1_TX#[3]

FDI0_TX[0] FDI0_TX[1] FDI0_TX[2] FDI0_TX[3] FDI1_TX[0] FDI1_TX[1] FDI1_TX[2] FDI1_TX[3]

FDI0_FSYNC FDI1_FSYNC

FDI_INT FDI0_LSYNC

FDI1_LSYNC

eDP_COMPIO eDP_ICOMPO eDP_HPD

eDP_AUX# eDP_AUX

eDP_TX#[0] eDP_TX#[1] eDP_TX#[2] eDP_TX#[3]

eDP_TX[0] eDP_TX[1] eDP_TX[2] eDP_TX[3]

SNB_2CBGA_1P0

DG 1.0 : The recommended AC cap value is changed to 220nF for compatibility with PCIe Gen3 on future platforms. For Gen2 only designs, it is acceptable to continue to use the 100nF capacitor.

DMI Intel(R) FDI DP

PCI EXPRESS -- GRAPHICS

INT_EDP_HPD#

Q2

2N7002E

4

G3

PEG_ICOMPI

G1

PEG_ICOMPO

G4

PEG_RCOMPO

H22

PEG_RX#[0]

J21

PEG_RX#[1]

B22

PEG_RX#[2]

D21

PEG_RX#[3]

A19

PEG_RX#[4]

D17

PEG_RX#[5]

B14

PEG_RX#[6]

D13

PEG_RX#[7]

A11

PEG_RX#[8]

B10

PEG_RX#[9]

G8

PEG_RX#[10]

A8

PEG_RX#[11]

B6

PEG_RX#[12]

H8

PEG_RX#[13]

E5

PEG_RX#[14]

K7

PEG_RX#[15]

K22

PEG_RX[0]

K19

PEG_RX[1]

C21

PEG_RX[2]

D19

PEG_RX[3]

C19

PEG_RX[4]

D16

PEG_RX[5]

C13

PEG_RX[6]

D12

PEG_RX[7]

C11

PEG_RX[8]

C9

PEG_RX[9]

F8

PEG_RX[10]

C8

PEG_RX[11]

C5

PEG_RX[12]

H6

PEG_RX[13]

F6

PEG_RX[14]

K6

PEG_RX[15]

G22

PEG_TX#[0]

C23

PEG_TX#[1]

D23

PEG_TX#[2]

F21

PEG_TX#[3]

H19

PEG_TX#[4]

C17

PEG_TX#[5]

K15

PEG_TX#[6]

F17

PEG_TX#[7]

F14

PEG_TX#[8]

A15

PEG_TX#[9]

J14

PEG_TX#[10]

H13

PEG_TX#[11]

M10

PEG_TX#[12]

F10

PEG_TX#[13]

D9

PEG_TX#[14]

J4

PEG_TX#[15]

F22

PEG_TX[0]

A23

PEG_TX[1]

D24

PEG_TX[2]

E21

PEG_TX[3]

G19

PEG_TX[4]

B18

PEG_TX[5]

K17

PEG_TX[6]

G17

PEG_TX[7]

E14

PEG_TX[8]

C15

PEG_TX[9]

K13

PEG_TX[10]

G13

PEG_TX[11]

K10

PEG_TX[12]

G10

PEG_TX[13]

D8

PEG_TX[14]

K4

PEG_TX[15]

0.22uF AC coupling Caps for PCIE GEN1/2/3

+1.05V_VTT

20111104 change from 10k to 1k.

R192 1K_4

3

2

EDP_HPD

R191

1

100K_4

3

PEG_COMP

PEG_ICOMPO 12mil PEG_ICOMPI, PEG_RCOMPO 4mil,

GRN15 GRN14 GRN13 GRN12 GRN11 GRN10 GRN9 GRN8 GRN7 GRN6 GRN5 GRN4 GRN3 GRN2 GRN1 GRN0

GRP15 GRP14 GRP13 GRP12 GRP11 GRP10 GRP9 GRP8 GRP7 GRP6 GRP5 GRP4 GRP3 GRP2 GRP1 GRP0

GTN15C

C154 EV@0.22u/10V_4

GTN14C GTN14

C152 EV@0.22u/10V_4

GTN13C

C149 EV@0.22u/10V_4

GTN12C

C148 EV@0.22u/10V_4

GTN11C

C146 EV@0.22u/10V_4

GTN10C

C143 EV@0.22u/10V_4

GTN9C

C142 EV@0.22u/10V_4

GTN8C

C140 EV@0.22u/10V_4

GTN7C

C137 EV@0.22u/10V_4

GTN6C GTN6

C136 EV@0.22u/10V_4

GTN5C

C156 EV@0.22u/10V_4

GTN4C

C134 EV@0.22u/10V_4

GTN3C

C162 EV@0.22u/10V_4

GTN2C

C132 EV@0.22u/10V_4

GTN1C

C130 EV@0.22u/10V_4

GTN0C

C128 EV@0.22u/10V_4

GTP15C GTP15

C153 EV@0.22u/10V_4

GTP14C

C151 EV@0.22u/10V_4

GTP13C

C150 EV@0.22u/10V_4

GTP12C

C147 EV@0.22u/10V_4

GTP11C

C145 EV@0.22u/10V_4

GTP10C

C144 EV@0.22u/10V_4

GTP9C

C141 EV@0.22u/10V_4

GTP8C

C139 EV@0.22u/10V_4

GTP7C GTP7

C138 EV@0.22u/10V_4

GTP6C

C135 EV@0.22u/10V_4

GTP5C

C155 EV@0.22u/10V_4

GTP4C

C133 EV@0.22u/10V_4

GTP3C

C161 EV@0.22u/10V_4

GTP2C

C131 EV@0.22u/10V_4

GTP1C

C129 EV@0.22u/10V_4

GTP0C

C127 EV@0.22u/10V_4

EDP_HPD <15>

3

GRN[0..15] <25>

GRP[0..15] <25>

GTN15 GTN13

GTN12 GTN11 GTN10 GTN9 GTN8 GTN7

GTN5 GTN4 GTN3 GTN2 GTN1 GTN0

GTP14 GTP13 GTP12 GTP11 GTP10 GTP9 GTP8

GTP6 GTP5 GTP4 GTP3 GTP2 GTP1 GTP0

2

PEG_ICOMPI and RCOMPO signals should be shorted and routed with

- max length = 500 mils

- typical impedance = 43 mohms PEG_ICOMPO signals should be routed with

- max length = 500 mils

- typical impedance = 14.5 mohms

GTN[0..15] <25>

GTP[0..15] <25>

Size Document Number Rev

Date: Sheet of

2

Date: Sheet of

Ivy Bridge 1/5

Monday, April 09, 2012

1

Quanta Computer Inc.

PROJECT :

Z09

1

2 40

3A

5

4

3

2

Boot S3 S3 RSM

1

+1.5V_CPU

Ivy Bridge Processor (CLK,MISC,JTAG)

R196 *750/F_4

U9B

F49

PROC_SELECT#

C57

PROC_DETECT#

C49

CATERR#

A48

PECI

C45

PROCHOT#

D45

THERMTRIP#

C48

PM_SYNC

B46

UNCOREPWRGOOD

BE45

SM_DRAMPWROK

D44

RESET#

SNB_2CBGA_1P0

DPLL_REF_CLK#

MISC

BCLK

BCLK#

DPLL_REF_CLK

BCLK_ITP

BCLK_ITP#

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

PRDY#

PREQ#

TRST#

DBR#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

TCK TMS

TDI

TDO

MISC THERMAL PWR MANAGEMENT

CLOCKS

DDR3

JTAG & BPM

J3 H2

AG3 AG1

N59

CLK_PCIE_XDPP_R

N58

CLK_PCIE_XDPN_R

Isolate Space:20mils

AT30

BF44

SM_RCOMP_0

BE43

SM_RCOMP_1

BG43

SM_RCOMP_2

Impedance 85ohm

N53 N55

L56 L55 J58

M60 L59

K58

XDP_DBRST#_R

G58 E55 E59 G55 G59 H60 J59 J61

CLK_CPU_BCLKP <9> CLK_CPU_BCLKN <9>

20111121 Remove R5306/R5311/R5474/R5476.

TP95

TP53

R230 *0_4 R229 *0_4

CPU_DRAMRST# <4,24>

R209 140/F_4 R204 200/F_4

TP79 TP83

XDP_TCLK_VT <8,22>

XDP_TRST#

XDP_TMS_VT <8,22>

TP103

XDP_TDI_VT <22> PCH_XDP_TDO_VT <8>

20111021 Add 10k to +3V,CRB 1k 20111103 del R601

TP97 TP82 TP81 TP80 TP98 TP100 TP99 TP101

XDP_PREQ#

R233 0_4

CAD NOTE: All DDR_COMP signals should be routed such that :-

- max length = 500 mils

- trace width = 15mils and

- MB trace impedance < 68 mohms (worst case resistance)

XDP_DBRST# <7>

D D

H_SNB_IVB#<8>

EC_PECI<10,24>

H_PROCHOT#<24,33>

PM_THRMTRIP#<10>

C C

Over 130 degree C will drive low

PM_SYNC<7>

H_PWRGOOD<10>

Isolate Space:20mils

R194 75/F_4

+1.05V_VTT

B B

TP85

TP_CATERR#

TP78

H_PROCHOT#_R

R207 56_4 R206 25.5/F_4

C253

12

*43P/50V_4N

C718 0.1U/10V_4

TP67

PM_SYNC_R

H_PWRGOOD_R

CPU_PLTRST#_RCPU_PLTRST#

R214 *SHORT_4

R596 *SHORT_4 R595 10K_4

PM_DRAM_PWRGD_R

R190 43_4

DRAM_PWRGD

SYS_PWROK

SM_DRAMPWROK

CLK_DPLL_SSCLKP <9> CLK_DPLL_SSCLKN <9>

CLK_PCIE_XDPP <9> CLK_PCIE_XDPN <9>

100 ns after +1.5V_CPU reaches 80%

If motherboard only supports external graphics or if it supports Processor Graphics but without eDP: Connect DPLL_REF_SSCLK on Processor to GND through 1K +/5% resistor. Connect DPLL_REF_SSCLK# on Processor to VCCP through 1K +/

- 5% resistor

Place near to XDP connector

PCH_XDP_TDO_VT

+1.05V_VTT

Option for Prochot# function 68 ohm for unused, 62 ohm for used

H_PROCHOT#

XDP_TMS_VT XDP_TDI_VT

XDP_PREQ# XDP_TCLK_VT

XDP_TRST#

When MP, JTAG PU/PD resistor can be removed? (Yes Intel, TDI, TDO, TMS, TRST#, TCK,PREQ#, PRDY#)

R23251 _4

R219 62_ 4

R606 51_ 4 R231 51_ 4

R612 *5 1_4 R611 51_ 4

R228 51_ 4

+1.05V_VTT

+3V

Thermal Trip

IMVP_PWRGD<7,33>

A A

<CPU>

PM_THRMTRIP#

5

2

1 3

+1.05V_VTT

3

1

R195 1K_4

2

Q6 2N7002_200MA

Q5 MMBT3904-7-F_200MA

+1.5V_CPU

SYS_SHDN# <32,37>

4

s3 leakage circuit

+3V_S5

20111121 add Q31 becaue Vh=2.1/Vl=0.9.

R603

R604

*10K_4

*1K_4

6

215

4 3

PM_DRAM_PWRGD<7>

20111030 add resistor.

SYS_PWROK<7>

*2N7002DW Q42

R602 0_4

If PM_DRAM_PWEGD connector,the R5180 must stuff.

+3V_S5

+1.5V_CPU

R605 200/F_4

R610 *39_4

R598 130/F_4

MAINON_G<5,37>

3

2 1

3 5

R608 *0_4

C727

0.1u/10V_4

U33

74AHC1G09

4

PM_DRAM_PWRGD_RPM_DRAM_PWRGD_Q

3

Q44 *2N7002K

2

U8

20111128 change net to PCI_PLTRST#

PCI_PLTRST#<9,24>

1

Size Document Number Rev

Date: Sheet of

Ivy Bridge 2/5

Monday, April 09, 2012

1 2

IN GND3OUT

74LVC1G07GW_NC

R186 *1.5K/F_4

IN OUT

L L H High-Z

Quanta Computer Inc.

PROJECT :

1

VCC5NC

CPU_PLTRST#_R

Z09

C190

0.1U/10V_4X

4

CPU_PLTRST#

3 40

3A

5

4

3

2

1

Sandy Bridge Processor (DDR3)

AW59 AW58

BD13 BF12

BD10 BD14 BE13 BF16 BE17 BE18 BE21 BE14 BG14 BG18 BF19 BD50 BF48 BD53 BF52 BD49 BE49 BD54 BE53 BF56 BE57 BC59 AY60 BE54 BG54 BA58

AU58 AN61 AN59 AU59 AU61 AN58 AR58 AK58 AL58 AG58 AG59 AM60 AL59 AF61 AH60

BG39 BD42 AT22

AV43 BF40 BD45

AL4 AL1 AN3 AR4 AK4 AK3 AN4 AR1 AU4 AT2 AV4 BA4 AU3 AR3 AY2 BA3 BE9 BD9

BF8

U9D

SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10 ] SB_DQ[11 ] SB_DQ[12 ] SB_DQ[13 ] SB_DQ[14 ] SB_DQ[15 ] SB_DQ[16 ] SB_DQ[17 ] SB_DQ[18 ] SB_DQ[19 ] SB_DQ[20 ] SB_DQ[21 ] SB_DQ[22 ] SB_DQ[23 ] SB_DQ[24 ] SB_DQ[25 ] SB_DQ[26 ] SB_DQ[27 ] SB_DQ[28 ] SB_DQ[29 ] SB_DQ[30 ] SB_DQ[31 ] SB_DQ[32 ] SB_DQ[33 ] SB_DQ[34 ] SB_DQ[35 ] SB_DQ[36 ] SB_DQ[37 ] SB_DQ[38 ] SB_DQ[39 ] SB_DQ[40 ] SB_DQ[41 ] SB_DQ[42 ] SB_DQ[43 ] SB_DQ[44 ] SB_DQ[45 ] SB_DQ[46 ] SB_DQ[47 ] SB_DQ[48 ] SB_DQ[49 ] SB_DQ[50 ] SB_DQ[51 ] SB_DQ[52 ] SB_DQ[53 ] SB_DQ[54 ] SB_DQ[55 ] SB_DQ[56 ] SB_DQ[57 ] SB_DQ[58 ] SB_DQ[59 ] SB_DQ[60 ] SB_DQ[61 ] SB_DQ[62 ] SB_DQ[63 ]

SB_BS[0] SB_BS[1] SB_BS[2]

SB_CAS# SB_RAS# SB_WE #

SNB_2CBGA_1P0

BA34

SB_CLK[0 ]

AY34

SB_CLK#[0]

AR22

SB_CKE[0 ]

BA36 BB36 BF27

BE41 BE47

AT43 BG47

AL3 AV3 BG11 BD17 BG51 BA59 AT60 AK59

AM2 AV1 BE11 BD18 BE51 BA61 AR59 AK61

BF32 BE33 BD33 AU30 BD30 AV30 BG30 BD29 BE30 BE28 BD43 AT28 AV28 BD46 AT26 AU22

M_B_CLK1 M_B_CLK1# M_B_CKE1

M_B_CS#1

M_B_ODT1

M_B_DQSN0 M_B_DQSN1 M_B_DQSN2 M_B_DQSN3 M_B_DQSN4 M_B_DQSN5 M_B_DQSN6 M_B_DQSN7

M_B_DQSP0 M_B_DQSP1 M_B_DQSP2 M_B_DQSP3 M_B_DQSP4 M_B_DQSP5 M_B_DQSP6 M_B_DQSP7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

SB_CLK[1 ]

SB_CLK#[1]

SB_CKE[1 ]

SB_CS#[0 ] SB_CS#[1 ]

SB_ODT[0] SB_ODT[1]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0 ] SB_DQS[1 ] SB_DQS[2 ] SB_DQS[3 ] SB_DQS[4 ] SB_DQS[5 ] SB_DQS[6 ] SB_DQS[7 ]

DDR SYSTEM MEMORY B

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]

SB_MA[9] SB_MA[10 ] SB_MA[11 ] SB_MA[12 ] SB_MA[13 ] SB_MA[14 ] SB_MA[15 ]

M_B_CLK0 <14> M_B_CLK0# <14> M_B_CKE0 <14>

TP31

M_B_CS#0 <14>

TP32

M_B_ODT0 <14>

TP33

M_B_DQSN[7:0] <14>

M_B_DQSP[7:0] <14>

M_B_A[15:0] <14>

M_B_CLK1

AR11

AT13 AU13

BA13 BB11

AY13 AV14 AR14 AY17 AR19 BA14 AU14 BB14 BB17 BA45 AR43

AW48

BC48 BC45 AR45 AT48 AY48 BA49 AV49 BB51 AY53 BB49 AU49 BA53 BB55 BA55 AV56 AP50 AP53 AV54 AT54 AP56 AP52 AN57 AN53 AG56 AG53 AN55 AN52 AG55 AK56

BD37 BF36 BA28

BE39 BD39 AT41

AP11 AJ10

AG6

AJ6 AL6 AJ8

AL8 AL7

AP6 AU6 AV9 AR6 AP8

BC7 BB7

BA7 BA9 BB9

U9C

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10 ] SA_DQ[11 ] SA_DQ[12 ] SA_DQ[13 ] SA_DQ[14 ] SA_DQ[15 ] SA_DQ[16 ] SA_DQ[17 ] SA_DQ[18 ] SA_DQ[19 ] SA_DQ[20 ] SA_DQ[21 ] SA_DQ[22 ] SA_DQ[23 ] SA_DQ[24 ] SA_DQ[25 ] SA_DQ[26 ] SA_DQ[27 ] SA_DQ[28 ] SA_DQ[29 ] SA_DQ[30 ] SA_DQ[31 ] SA_DQ[32 ] SA_DQ[33 ] SA_DQ[34 ] SA_DQ[35 ] SA_DQ[36 ] SA_DQ[37 ] SA_DQ[38 ] SA_DQ[39 ] SA_DQ[40 ] SA_DQ[41 ] SA_DQ[42 ] SA_DQ[43 ] SA_DQ[44 ] SA_DQ[45 ] SA_DQ[46 ] SA_DQ[47 ] SA_DQ[48 ] SA_DQ[49 ] SA_DQ[50 ] SA_DQ[51 ] SA_DQ[52 ] SA_DQ[53 ] SA_DQ[54 ] SA_DQ[55 ] SA_DQ[56 ] SA_DQ[57 ] SA_DQ[58 ] SA_DQ[59 ] SA_DQ[60 ] SA_DQ[61 ] SA_DQ[62 ] SA_DQ[63 ]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE #

SNB_2CBGA_1P0

AU36

SA_CLK[0 ]

AV36

SA_CLK#[0]

AY26

SA_CKE[0 ]

AT40 AU40 BB26

BB40 BC41

AY40 BA41

AL11 AR8 AV11 AT17 AV45 AY51 AT55 AK55

AJ11 AR10 AY11 AU17 AW45 AV51 AT56 AK54

M_A_CLK1 M_A_CLK1# M_A_CKE1

M_A_CS#1

M_A_ODT1

M_A_DQSN0 M_A_DQSN1 M_A_DQSN2 M_A_DQSN3 M_A_DQSN4 M_A_DQSN5 M_A_DQSN6 M_A_DQSN7

M_A_DQSP0 M_A_DQSP1 M_A_DQSP2 M_A_DQSP3 M_A_DQSP4 M_A_DQSP5 M_A_DQSP6 M_A_DQSP7

SA_CLK[1 ]

SA_CLK#[1]

SA_CKE[1 ]

SA_CS#[0 ] SA_CS#[1 ]

SA_ODT[0] SA_ODT[1]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0 ] SA_DQS[1 ] SA_DQS[2 ] SA_DQS[3 ] SA_DQS[4 ] SA_DQS[5 ] SA_DQS[6 ] SA_DQS[7 ]

DDR SYSTEM MEMORY A

BG35 BB34 BE35 BD35 AT34 AU34 BB32 AT32 AY32 AV32 BE37 BA30 BC30 AW41 AY28 AU26

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10 ] SA_MA[11 ] SA_MA[12 ] SA_MA[13 ] SA_MA[14 ] SA_MA[15 ]

M_A_CLK0 <13> M_A_CLK0# <13> M_A_CKE0 <13>

M_A_CLK1 <13> M_A_CLK1# <13> M_A_CKE1 <13>

M_A_CS#0 <13> M_A_CS#1 <13>

M_A_ODT0 <13> M_A_ODT1 <13>

M_A_DQSN[7:0] <13>

M_A_DQSP[7:0] <13>

M_A_A[15:0] <13>

M_A_DQ[63:0]<13>

D D

C C

M_A_BS#0<13> M_A_BS#1<13>

B B

M_A_BS#2<13>

M_A_CAS#<13> M_A_RAS#<13> M_A_WE#<13>

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

M_B_DQ[63:0]<14>

M_B_BS#0<14> M_B_BS#1<14> M_B_BS#2<14>

M_B_CAS#<14> M_B_RAS#<14> M_B_WE#<14>

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

R588

+0.75V_DDR_VTT

C758

1u/6.3V_4

20120112 for memory down PU CAP.

+3V_S5

s3 leakage circuit

S3 circuit:- DRAM_RST# to memory should be high during S3

A A

DDR3_DRAMRST#<13,14> CPU_DRAMRST# <3,24>

DRAMRST_CNTRL_PCH<9>

EC_DRAMRST_CNTRL<24>

DEEPS3_EC<13,14>

20120204 Change to EC for new BIOS 0.6

5

+1.5VSUS

R577 1K/F_4

R573 *0_4

201201119 move R358 to near Q38 and del net DRAMRST_CNTRL_PCH, and EC_DRAMRST_CNTRL and R616.

R358 1K_4

R579 *0_4

Q38 2N7002K

3

1

R580 1K/F_4

2

R582

4.99K/F_4R574 0_4

C610

0.047u/10V_4

4

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

R550 36_4 R555 36_4 R554 36_4 R531 36_4 R562 36_4 R565 36_4 R570 36_4 R569 36_4 R571 36_4 R557 36_4 R537 36_4 R563 36_4 R549 36_4 R567 36_4 R568 36_4 R536 36_4

3

+0.75V_DDR_VTT

M_B_WE# M_B_CAS# M_B_RAS# M_B_BS#0 M_B_BS#2 M_B_CKE0 M_B_ODT0 M_B_CS#0 M_B_BS#1

R535 36_4 R539 36_4 R542 36_4 R534 36_4 R533 36_4 R540 36_4 R541 36_4 R538 36_4 R532 36_4

2

1u/6.3V_4

+0.75V_DDR_VTT

C753

C755

C756

C757

C759

C754

10u/6.3V_8

1u/6.3V_4

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

Date: Sheet of

Monday, April 09, 2012

Date: Sheet of

Monday, April 09, 2012

Date: Sheet of

Monday, April 09, 2012

PROJECT :

Ivy Bridge 3/5

Z09

1

M_B_CLK1#

4 40

75/F_4

3A

5

20120120 remove C621 for debug IC.

20120120 remove C622 for debug IC.

C244

C240

2.2u/10V_4

C658

C683

2.2u/10V_4

C646

C628

2.2u/10V_4

C685

C687

2.2u/10V_4

C245

C672

2.2u/10V_4

R203 *SHORT_4

C235 10u/6.3V_6

C697 10u/6.3V_6

C696 10u/6.3V_6

C629

2.2u/10V_4

C684

2.2u/10V_4

C232

2.2u/10V_4

C695

2.2u/10V_4

C648

2.2u/10V_4

5

D D

C231

2.2u/10V_4

C C

C669

2.2u/10V_4

C251

2.2u/10V_4

C671

2.2u/10V_4

C673

2.2u/10V_4

CPU Core Power

IVY 17W:TDC 33A

B B

IVY SPEC

1.9mΩ/LoadlineDesign total : 2.2uF x 35 total : 22uF x 12 tatal : 470u x3(Power side*1)

Cose down

IVY SPEC

1.9mΩ/LoadlineDesign total : 2.2uF x 35 total : 10uF x 12 tatal : 470u x1(Power side*1)

A A

Layout note: need routing together and ALERT need between CLK and DATA

SVID CLK

H_CPU_SVIDCLK

Sandy Bridge Processor (POWER)

U9F

+VCC_CORE

A26

VCC[1]

A29

VCC[2]

A31

VCC[3]

C674

+

470u/2V_7343

C238 10u/6.3V_6

C704 10u/6.3V_6

C703 10u/6.3V_6

C241

2.2u/10V_4

C645

2.2u/10V_4

C239

2.2u/10V_4

C647

2.2u/10V_4

C661

2.2u/10V_4

C247

+

470u/2V_7343

A34 A35 A38 A39 A42 C26 C27 C32 C34 C37 C39 C42 D27 D32 D34 D37 D39 D42 E26 E28 E32 E34 E37 E38 F25 F26 F28 F32 F34 F37 F38 F42 G42 H25 H26 H28 H29 H32 H34 H35 H37 H38 H40 J25 J26 J28 J29 J32 J34 J35 J37 J38 J40 J42 K26 K27 K29 K32 K34 K35 K37 K39 K42 L25 L28 L33 L36 L40 N26 N30 N34 N38

VCC[4] VCC[5] VCC[6] VCC[7] VCC[8] VCC[9] VCC[10] VCC[11] VCC[12] VCC[13] VCC[14] VCC[15] VCC[16] VCC[17] VCC[18] VCC[19] VCC[20] VCC[21] VCC[22] VCC[23] VCC[24] VCC[25] VCC[26] VCC[27] VCC[28] VCC[29] VCC[30] VCC[31] VCC[32] VCC[33] VCC[34] VCC[35] VCC[36] VCC[37] VCC[38] VCC[39] VCC[40] VCC[41] VCC[42] VCC[43] VCC[44] VCC[45] VCC[46] VCC[47] VCC[48] VCC[49] VCC[50] VCC[51] VCC[52] VCC[53] VCC[54] VCC[55] VCC[56] VCC[57] VCC[58] VCC[59] VCC[60] VCC[61] VCC[62] VCC[63] VCC[64] VCC[66] VCC[67] VCC[68] VCC[69] VCC[70] VCC[71] VCC[72] VCC[73] VCC[74] VCC[75] VCC[76]

SNB_2CBGA_1P0

C692 10u/6.3V_6

C246

2.2u/10V_4

C670

2.2u/10V_4

C678

2.2u/10V_4

C686

2.2u/10V_4

C649

2.2u/10V_4

C237 10u/6.3V_6

C236 10u/6.3V_6

C693 10u/6.3V_6

C653

2.2u/10V_4

C657

2.2u/10V_4

C250

2.2u/10V_4

C659

2.2u/10V_4

C660

2.2u/10V_4

Place PU resistor close to CPU

SVID DATA

VR_SVID_CLK <33>

H_CPU_SVIDDAT

CORE SUPPLY

POWER

+1.05V_VTT +1.05V_VTT

R202 130/F_4

R205 *SHORT_4

VCCIO[10] VCCIO[11] VCCIO[12] VCCIO[13] VCCIO[14] VCCIO[15] VCCIO[16] VCCIO[17] VCCIO[18] VCCIO[19] VCCIO[20] VCCIO[21] VCCIO[22] VCCIO[23] VCCIO[24] VCCIO[25] VCCIO[26] VCCIO[27] VCCIO[28] VCCIO[29]

VCCIO[30] VCCIO[31] VCCIO[32] VCCIO[33]

PEG AND DDRSENSE LINES SVID QUIET RAILS

VCCIO[34] VCCIO[35] VCCIO[36] VCCIO[37] VCCIO[38] VCCIO[39] VCCIO[40] VCCIO[41] VCCIO[42] VCCIO[43] VCCIO[44] VCCIO[45] VCCIO[46] VCCIO[47] VCCIO[48] VCCIO[49]

VCCIO_SEL

VCCPQE[1] VCCPQE[2]

VIDALERT#

VCC_SENSE VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

VR_SVID_DATA <33>

4

CPU VCCIO

IVY 17W:8.5A

Cose down

SNB : Spec

330uF/6mohm x 2

+1.05V_VTT

AF46

VCCIO[1]

AG48

VCCIO[3]

AG50

VCCIO[4]

AG51

VCCIO[5]

AJ17

VCCIO[6]

AJ21

VCCIO[7]

AJ25

+

AJ43 AJ47 AK50 AK51 AL14 AL15 AL16 AL20 AL22 AL26 AL45 AL48 AM16 AM17 AM21 AM43 AM47 AN20 AN42 AN45 AN48

AA14 AA15 AB17 AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20 AG15 AG16 AG17 AG20 AG21 AJ14 AJ15

W16 W17

BC22

AM25 AN22

A44 B43 C44

F43 G43

AN16 AN17

C181 10u/6.3V_6

C656 10u/6.3V_6

C630 1u/6.3V_4

C619 1u/6.3V_4

R187 *SHORT_6

VCCIO_SEL

R581 *SHORT_4 C632 1U/6.3V_4X

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

R591 100_4

R589 100_4

R576 10_4

R578 10_4

C603 *330u/2V_7343

C639 10u/6.3V_6

C180 10u/6.3V_6

C620 1u/6.3V_4

C615 1u/6.3V_4

TP64

VCCIO[8] VCCIO[9]

VCCIO50 VCCIO51

VIDSCLK VIDSOUT

330uF/6mohm x 1

10uF x 10

1uF x 26

+

C215 330u/2V_7343

C652

C182

C184

10u/6.3V_6

C183

C604

C710

10u/6.3V_6

C642

C611

C624

C635

1u/6.3V_4

C641

C694

C623

C633

1u/6.3V_4

IVY SPEC 22uF_8 x7 Socket TOP cavity 22uF_8 x5 Socket BOT cavity 22uF_8 x2 Socket TOP cavity (no stuff) 22uF_8 x5 Socket BOT cavity (no stuff) 330uF_7343 x2

+1.05V_VTT

Voltage select ion for VCCIO: this pin must be pulled high on the motherb oard

On CRB H_SNB_IVB#_PWRCTRL = low, 1 .0V H_SNB_IVB#_PWRCTRL = high/N C, 1.05V

+1.05V_VTT

+VCC_CORE

VCC_SENSE <33> VSS_SENSE <33>

+1.05V_VTT

VCCP_SENSE <34> VSSP_SENSE <34>

C709

C626

C186

C702

1u/6.3V_4

C634

C616

C605

C705

1u/6.3V_4

Place PU resistor close to CPU

R213 75/F_4

VR_SVID_ALERT#_RH_CPU_SVIDALRT#

4

R208 43_4

C715 1u/6.3V_4

C612 1u/6.3V_4

R212 *SHORT_4

C716 1u/6.3V_4

C613 1u/6.3V_4

SVID ALERT

C185 1u/6.3V_4

C614 1u/6.3V_4

3

CPU VCCAXG

IVY 17W:TDC 18A

Spec

3.9mΩ/LoadlineDesign total : 1uF x 11 total : 10uF x 6 total : 22uF x 6 tatal : 470u x 1(power side*2)

IVY SPEC 330uF x1, 10uF_8 x1 Socket BOT edge, 10uF_8 x2 Socket BOT cavity.

CPU VCCSA

IVY 17W: 6A

Spec

330uF/7mohm x 1 10uF x 5 1uF x 5

VR_SVID_ALERT# <33 >

3

Cose down

3.9mΩ/LoadlineDesign total : 1uF x 11 total : 10uF x 12 tatal : 470u x 1(power side*2)

C729 10u/6.3V_6

C278 10u/6.3V_6

C711 1u/6.3V_4

VCCAXG_SENSE/V SSAXG_SENSE R =100, Trace impedanc e 15.5~34.5, <25mils.

CPU VCCPL

IVY 17W:1.5A

Real

Spec

10uF x 1

330uF/7mohm x 1 1uF x 2

IVY SPEC 330uF x1, 10uF_8 x1, 1uF_4 x2 Socket BOT edge.

Real

10uF x 3

S3 circuit: 1.5V input to IVB is gated & IVB Read Vref 0.75V is gated

+1.8V

1uF x 2

C627 10u/6.3V_6

+SMDDR_VREF +VDDR_REF_CPU +1.5V_CPU

R234 *0_8

321

MAIND

MAIND<32,35,37>

2

Sandy Bridge Processor (GRAPHIC POWER)

C730

+

470u/2V_7343

C283

C282

C281

C728

C726

10u/6.3V_6

C725 10u/6.3V_6

C712 1u/6.3V_4

C706 1u/6.3V_4

C284

C724

C285 10u/6.3V_6

C708 1u/6.3V_4

C714 1u/6.3V_4

VCC_AXG_SENSE<33> VSS_AXG_SENSE<33>

R566 *SHORT_8 R560 *SHORT_8

C618 10u/6.3V_6

C608 1u/6.3V_4

S3 S TUFF N O_STUFF enable - disable -

Q7 2N7002K

C292

10u/6.3V_6

C701

C707

C713

1u/6.3V_4

C700

C698

C699

1u/6.3V_4

R593 100_4

+VCC_GFX

R594 100_4

CPU_VCCPLL

C192

C200

1u/6.3V_4

+

C636

C609

C651

10u/6.3V_6

C631

C637

C617

C625

1u/6.3V_4

R5347/R6362

20111024 from +1.5VSUS change to +1.5V_CPU

R221 *1K/F_4

R218 100K_4

R215 *1K/F_4

change to 1K/F_4

2

TP69

TP70

C178 330u/2V_7343

+VCC_GFX

+

C177

*330u/2V_7343

U9G

AA46 AB47 AB50 AB51 AB52 AB53 AB55 AB56 AB58 AB59 AC61 AD47 AD48 AD50 AD51 AD52 AD53 AD55 AD56 AD58 AD59 AE46

N45 P47 P48 P50 P51 P52 P53 P55 P56 P61 T48 T58 T59 T61 U46 V47 V48 V50 V51 V52 V53 V55 V56 V58

V59 W50 W51 W52 W53 W55 W56 W61

Y48

Y61

F45

G45

BB3 BC1 BC4

+VCCSA

L17

L21

N16

N20

N22

P17

P20

R16

R18

R21

U15

V16

V17

V18

V21 W20

SNB_2CBGA_1P0

VAXG[1] VAXG[2] VAXG[3] VAXG[4] VAXG[5] VAXG[6] VAXG[7] VAXG[8] VAXG[9] VAXG[10] VAXG[11] VAXG[12] VAXG[13] VAXG[14] VAXG[15] VAXG[16] VAXG[17] VAXG[18] VAXG[19] VAXG[20] VAXG[21] VAXG[22] VAXG[23] VAXG[24] VAXG[25] VAXG[26] VAXG[27] VAXG[28] VAXG[29] VAXG[30] VAXG[31] VAXG[32]

GRAPHICS

VAXG[33] VAXG[34] VAXG[35] VAXG[36] VAXG[37] VAXG[38] VAXG[39] VAXG[40] VAXG[41] VAXG[42] VAXG[43] VAXG[44] VAXG[45] VAXG[46] VAXG[47] VAXG[48] VAXG[49] VAXG[50] VAXG[51] VAXG[52] VAXG[53] VAXG[54] VAXG[55] VAXG[56]

SENSE

LINES

VAXG_SENSE VSSAXG_SENSE

1.8V RAIL

VCCPLL[1] VCCPLL[2] VCCPLL[3]

VCCSA[1] VCCSA[2] VCCSA[3]

SA RAIL

VCCSA[4] VCCSA[5] VCCSA[6] VCCSA[7] VCCSA[8] VCCSA[9] VCCSA[10] VCCSA[11] VCCSA[12] VCCSA[13] VCCSA[14] VCCSA[15] VCCSA[16]

20111107 stuff Q5010 and un-staff R5347/R362.

4.5A

R210 *0_1206

R211 *0_1206

Q41 AO4496

782 5

MAIND

MAINON_G<3,37>

DDR3 - 1.5V RAILS

POWER

QUIET RAILS

VDDQ_SENSE

VSS_SENSE_VDDQ

SENSE LINES

VCCSA_SENSE

VCCSA_VID[0]

VCCSA_VID[1]

1 36

4

C688 470P/50V_4

MAINON_G

CAD Note: +VDDR_REF_CPU should have 10 mil trace width

AY43

+VDDR_REF_CPU

SM_VREF

+1.5V_CPU

AJ28

VDDQ[1]

AJ33

VDDQ[2]

AJ36

VDDQ[3]

AJ40

C667

VDDQ[4]

AL30

10u/6.3V_6

VDDQ[5]

AL34

VDDQ[6]

AL38

VDDQ[7]

AL42

VDDQ[8]

AM33

VDDQ[9]

AM36

VDDQ[10]

AM40

VDDQ[11]

AN30

VDDQ[12]

AN34

C666

VDDQ[13]

AN38

10u/6.3V_6

VDDQ[14]

AR26

VDDQ[15]

AR28

VDDQ[16]

AR30

VDDQ[17]

AR32

VDDQ[18]

AR34

VDDQ[19]

AR36

C655

VDDQ[20]

AR40

VDDQ[21]

AV41

1u/6.3V_4

VDDQ[22]

AW26

VDDQ[23]

BA40

VDDQ[24]

BB28

VDDQ[25]

BG33

VDDQ[26]

C676 1u/6.3V_4

AM28

VCCDQ[1]

AN26

VCCDQ[2]

C650 1U/6.3V_4X

BC43

R590 *51_4

BA43

R592 *51_4

R575 *100/F_4

U10

SNB_IVB# N.A at SNB EDS #27637 0.7v1

R217 *10K_4

C767 *33n/10V_4

D48

R220 IVB@0_4

D49

R597 *10K_4

R94 for SN Bridge

+1.5V_CPU+1.5VSUS

R583 220_8

3

2

Q39 DMN601K-7

Size Document Number Rev

1

Date: Sheet of

1

CPU VDDQ

IVY 45W: 5A

Spec

330uF/6mohm x 1 10uF x 8 1uF x 10

C682

C681

C662

10u/6.3V_6

C691

*10u/6.3V_6

C665 1u/6.3V_4

C690 1u/6.3V_4

Monday, April 09, 20 12

C668

10u/6.3V_6

C242

+

C680

*10u/6.3V_6

330u/2V_7343

C664

C677

C654

1u/6.3V_4

C689

C675

C663

1u/6.3V_4

+1.5V_CPU

+VCCSA

VCCSA_SENSE <36>

201201117 C767 for Intel fw issue, if solve need un-stuff.

VCCSA_VID0 <36> VCCSA_VID1 <36>

A 1-K pull-down resistor should be placed on the VCCSA VID lines. This will ensure the VID is 00 prior to VCCIO stability..

For SN Bridge

VID[1] +VCCSA

0.9V

0

0.8V

1

For IV Bridge

VID[1]

VID[0]

0

1

0

1

Quanta Computer Inc.

PROJECT :

Z09

PROJECT :

Z09

PROJECT :

Z09

Ivy Bridge 4/5

1

5 40

+VCCSA

0.9V

0.8V

0.725V

0.675V

3A

5

4

3

2

1

Sandy Bridge Processor (GND)

U9H

A13

VSS[1]

AG10 AG14 AG18 AG47 AG52 AG61

AM13 AM20 AM22 AM26 AM30 AM34

AA13 AA50 AA51 AA52 AA53 AA55 AA56

AB16 AB18 AB21 AB48 AB61 AC10 AC14 AC46

AD17 AD20

AD61 AE13

AF17 AF21 AF47 AF48 AF50 AF51 AF52 AF53 AF55 AF56 AF58 AF59

AH58 AJ13 AJ16 AJ20 AJ22 AJ26 AJ30 AJ34 AJ38 AJ42 AJ45 AJ48

AK52 AL10 AL13 AL17 AL21 AL25 AL28 AL33 AL36 AL40 AL43 AL47 AL61

A17 A21 A25 A28 A33 A37 A40 A45 A49 A53

A9

AA1

AA8

AC6

AD4

AE8 AF1

AG7 AH4

AJ7

AK1

VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90]

SNB_2CBGA_1P0

5

VSS

D D

C C

B B

A A

VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98]

VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180]

AM38 AM4 AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54 AP10 AP51 AP55 AP7 AR13 AR17 AR21 AR41 AR48 AR61 AR7 AT14 AT19 AT36 AT4 AT45 AT52 AT58 AU1 AU11 AU28 AU32 AU51 AU7 AV17 AV21 AV22 AV34 AV40 AV48 AV55 AW13 AW43 AW61 AW7 AY14 AY19 AY30 AY36 AY4 AY41 AY45 AY49 AY55 AY58 AY9 BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53 BC13 BC5 BC57 BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56 BD8 BE5 BG13

R599

*SNB@0_4

U9I

BG17

VSS[181]

BG21

VSS[182]

BG24

VSS[183]

BG28

VSS[184]

BG37

VSS[185]

BG41

VSS[186]

BG45

VSS[187]

BG49

VSS[188]

BG53

VSS[189]

BG9

VSS[190]

C29

VSS[191]

C35

VSS[192]

C40

VSS[193]

D10

VSS[194]

D14

VSS[195]

D18

VSS[196]

D22

VSS[197]

D26

VSS[198]

D29

VSS[199]

D35

VSS[200]

D4

VSS[201]

D40

VSS[202]

D43

VSS[203]

D46 D50 D54 D58

D6 E25 E29

E3 E35 E40 F13 F15 F19 F29 F35 F40 F55 G48 G51

G6 G61 H10 H14 H17 H21

H4 H53 H58

J1

J49

J55 K11 K21 K51

K8 L16 L20 L22 L26 L30 L34 L38 L43 L48 L61 M11 M15

VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249] VSS[250]

SNB_2CBGA_1P0

VSS

Processor Strapping

CFG2 (PCI-E Static x16 Lane Reversal)

CFG3 (PCI-E Static x4 Lane Reversal)

CFG4

(DP Presence Strap)

CFG7 (PEG Defer Training)

4

M4

VSS[251]

M58

VSS[252]

M6

VSS[253]

N1

VSS[254]

N17

VSS[255]

N21

VSS[256]

N25

VSS[257]

N28

VSS[258]

N33

VSS[259]

N36

VSS[260]

N40

VSS[261]

N43

VSS[262]

N47

VSS[263]

N48

VSS[264]

N51

VSS[265]

N52

VSS[266]

N56

VSS[267]

N61

VSS[268]

P14

VSS[269]

P16

VSS[270]

P18

VSS[271]

P21

VSS[272]

P58

VSS[273]

P59

VSS[274]

P9

VSS[275]

R17

VSS[276]

R20

VSS[277]

R4

VSS[278]

R46

VSS[279]

T1

VSS[280]

T47

VSS[281]

T50

VSS[282]

T51

VSS[283]

T52

VSS[284]

T53

VSS[285]

T55

VSS[286]

T56

VSS[287]

U13

VSS[288]

U8

VSS[289]

V20

VSS[290]

V61

VSS[291]

W13

VSS[292]

W15

VSS[293]

W18

VSS[294]

W21

VSS[295]

W46

VSS[296]

W8

VSS[297]

Y4

VSS[298]

Y47

VSS[299]

Y58

VSS[300]

Y59

VSS[301]

A5

VSS_NCTF_1

A57

VSS_NCTF_2

BC61

VSS_NCTF_3

BD3

VSS_NCTF_4

BD59

VSS_NCTF_5

BE4

VSS_NCTF_6

BE58

VSS_NCTF_7

BG5

VSS_NCTF_8

BG57

VSS_NCTF_9

C3

VSS_NCTF_1 0 VSS_NCTF_1 1 VSS_NCTF_1 2 VSS_NCTF_1 3 VSS_NCTF_1 4

C58 D59 E1 E61

NCTF

The CFG signals have a default value of '1' if not terminated on the board.

1 0

Normal Operation

Disable; No physical DP attached to eDP

PEG train immediately following xxRESETB de assertion

3

TP76 TP96

Lane Reversed

Enable; An ext DP device is connected to eDP

PEG wait for BIOS training

Sandy Bridge Processor (RESERVED, CFG)

BE7 SA_DIMM_VREFDQ B

G7 SB_DIMM_VREFDQ

BE7

RSVD28

BG7

RSVD29

N42

RSVD30

L42

RSVD31

L45

RSVD32

L47

RSVD33

M13

RSVD34

M14

RSVD35

U14

RSVD36

W14

RSVD37

P13

RSVD38

AT49

RSVD39

K24

RSVD40

AH2

RSVD41

AG13

RSVD42

AM14

RSVD43

AM15

RSVD44

N50

RSVD45

A4 C4 D3 D1 A58 A59 C59 A61 C61 D61 BD61 BE61 BE59 BG61 BG59 BG58 BG4 BG3 BE3 BG1 BE1 BD1

CFG2

R226 1K/F_4

20111102 stuff for revers

CFG3

R224 *1K/F_4

CFG4

R223 1K/F_4

CFG7

R222 *1K/F_4

Quanta Computer Inc.

PROJECT :

Ivy Bridge 5/5

Monday, April 09, 2012

R572 *1K_4

SMDDR_VREF_DQ0_M3 <13> SMDDR_VREF_DQ1_M3 <14>

R197 *1K_4

processor signal balls BF3 and BG4 for Ivy Bridge 4-core and balls BE7 and BG7 for Ivy Bridge 2-core

for M3 solution need R5265/R5266, W/O M3 then NC

Z09

1

TP65 TP68

TP66 TP72

TP74

TP71 TP73

CFG1 CFG2 CFG3 CFG4CFG4 CFG5 CFG6 CFG7

U9E

B50

CFG[0]

C51

CFG[1]

B54

CFG[2]

D53

CFG[3]

A51

CFG[4]

C53

CFG[5]

C55

CFG[6]

H49

CFG[7]

A55

CFG[8]

H51

CFG[9]

K49

CFG[10]

K53

CFG[11]

F53

CFG[12]

G53

CFG[13]

L51

CFG[14]

F51

CFG[15]

D52

CFG[16]

L53

CFG[17]

H43

VCC_VAL_ SENSE

K43

VSS_VAL _SENSE

H45

VAXG_VA L_SENSE

K45

VSSAXG_ VAL_SE NSE

F48

VCC_DIE_S ENSE

H48

RSVD6

K48

RSVD7

BA19

RSVD8

AV19

RSVD9

AT21

RSVD10

BB21

RSVD11

BB19

RSVD12

AY21

RSVD13

BA22

RSVD14

AY22

RSVD15

AU19

RSVD16

AU21

RSVD17

BD21

RSVD18

BD22

RSVD19

BD25

RSVD20

BD26

RSVD21

BG22

RSVD22

BE22

RSVD23

BG26

RSVD24

BE26

RSVD25

BF23

RSVD26

BE24

RSVD27

SNB_2CBGA_1P0

2

RESERVED

DC_TEST_A4 DC_TEST_C4 DC_TEST_D3

DC_TEST_D1 DC_TEST_A58 DC_TEST_A59 DC_TEST_C59 DC_TEST_A61 DC_TEST_C61 DC_TEST_D61

DC_TEST_BD61 DC_TEST_BE61 DC_TEST_BE59 DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58

DC_TEST_BG4 DC_TEST_BG3 DC_TEST_BE3 DC_TEST_BG1 DC_TEST_BE1 DC_TEST_BD1

CFG5

R225 *1K/F_4

CFG6

R227 *1K/F_4

CFG[6:5] (PCIE Port Bifurcation Straps)

11: (Default) x16 - Device 1 functions 1 and 2 disabled 10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

Size Document Number Rev

Date: Sheet of

6 40

3A

5

CPT/PPT (DMI,FDI,PM)

D D

20111102 DMI reverse 20111111 DMI change to normal

C C

SYS_PWROK

PWROK_EC

B B

PCH Pull-high/low(CLG) System PWR_OK(CLG)

CRB 1.0 change R5196 to 1K

CLKRUN# XDP_DBRST#

PCH_RSMRST#

A A

SYS_PWROK

DMI_RXN0<2> DMI_RXN1<2> DMI_RXN2<2> DMI_RXN3<2>

DMI_RXP0<2> DMI_RXP1<2> DMI_RXP2<2> DMI_RXP3<2>

DMI_TXN0<2> DMI_TXN1<2> DMI_TXN2<2> DMI_TXN3<2>

DMI_TXP0<2> DMI_TXP1<2> DMI_TXP2<2> DMI_TXP3<2>

R505 49.9/F_4

+1.05V_VTT

R502 750/F_4

20110214 add SUSWAEN to SUSACK connector.

SUSWARN#_R

R642 0_4 R91 *0_4

SUSACK#<24>

XDP_DBRST#<3>

C431 *1U/10V_4

R405 *SHORT_4

PM_DRAM_PWRGD<3>

PCH_RSMRST#<24>

IOAC_PCIERST#<20,24>

DNBSWON#<24>

ACPRESENT<31>

R433 4.99K/F_4 R432 *1K_4 R76 10K_4

R382 *0_4

R414 *SHORT_4

PM_PWRBTN#

TP40

R403 *SHORT_4

R404 *SHORT_4

R635 *0_4

R69 *SHORT_4

ACPRESENT

+3V

PM_RI# PM_BATLOW# PCIE_WAKE#_ LAN SLP_LAN# SUSWARN#_R ACPRESENT

PM_DRAM_PWRGD

wo S3 leakage, un-stuff R5180

5

XDP_DBRST#

CRB 1.0 uses 1k

BC24 BE20 BG18 BG20

BE24 BC20 BJ18 BJ20

AW24 AW20 BB18 AV18

AY24 AY20 AY18 AU18

BJ24 BG25

DMI_COMP

BH21

SUSACK#_R

SYS_PWROK_ R

EC_PWROK_R

APWROK_R

PM_DRAM_PWRGD

PCH_RSMRST#PCH_RSMRST#

SUSWARN#_R

PM_BATLOW#

PM_RI#

R359 10K_4R429 8.2K_4

R398 10K_4 R84 *10K_4 R62 10K_4 R346 *10K_4R352 *10K_4

201201119 stuff R346.

R396 200/F_4

20111107 R5180 un-stuff.

U26C

DMI0RXN DMI1RXN DMI2RXN DMI3RXN

DMI0RXP DMI1RXP DMI2RXP DMI3RXP

DMI0TXN DMI1TXN DMI2TXN DMI3TXN

DMI0TXP DMI1TXP DMI2TXP DMI3TXP

DMI_ZCOMP DMI_IRCOMP DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPWRDNACK/GPIO 30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

Panther Point_R1P 0

+3V_S5

DMI

+3V

+3V_S5

System Power Management

DSW

+3V_S5

to PCH Pin12, XDP and EE debug

SYS_PWROK<3>

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6

FDI

FDI_RXP7

FDI_INT FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GP IO63

SLP_S4#

+3V_S5

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN# / GPIO29

4

Need notice BIOS if DMI or FDI reverse.

BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9

BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

AW16 AV12 BC10 AV14 BB10

A18

E22

B9

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

SYS_PWROK

4

DPWROK_R

PCIE_WAKE#_ LAN

CLKRUN#

PCH_SUSCLK

SLP_A#

SLP_SUS#

SLP_LAN#

U24

4

TC7SH08FU

DSWVREN <8>

R94 0_4

R397 0_4

20111206 add R5193 un-stuff for normal s3 PCIE LAN wake up.

TP36

TP35

TP37

IMVP_PWRGD PU +3V PWROK_EC PD

+3V_S5

so AND gate output dont need PD again

C426

0.1u/10V_4R363 8.2K_4

2 1

PWROK_EC

3 5

R411 100K_4

R406 *0_4

FDI_TXN0 <2> FDI_TXN1 <2> FDI_TXN2 <2> FDI_TXN3 <2> FDI_TXN4 <2> FDI_TXN5 <2> FDI_TXN6 <2> FDI_TXN7 <2>

FDI_TXP0 <2> FDI_TXP1 <2> FDI_TXP2 <2> FDI_TXP3 <2> FDI_TXP4 <2> FDI_TXP5 <2> FDI_TXP6 <2> FDI_TXP7 <2>

20111102 FDI reverse

20111111 FDI change to normal

FDI_INT <2> FDI_FSYNC0 <2> FDI_FSYNC1 <2> FDI_LSYNC0 <2> FDI_LSYNC1 <2>

DPWROK need to be shorted to RSMRST# when Deep S4/S5 state is not support

DPWROK <24 >

PCIE_LAN_WAKE# <17>

CLKRUN# <1 9,24>

LPCPD# <1 9>

20111123 add for TPM LPCPD# pin.

SUSC# <24>

SUSB# <24>

SLP_SUS# <11,24>

PM_SYNC <3>

PWROK_EC <24 >

20120104 change DPWROK from PCH_Rsmrst# to EC control.

3

INT_LVDS_BLON<15>

INT_LVDS_DIGON<15 > INT_LVDS_BRIGHT<15>

DAC_IREF

R120 1K/F_4

1% or 5%

+3V_S5

C434 *0.1U/10V_4

U25

2

IMVP_PWRGD_R

include GFX_PWRGD to SYS_ PWROK for PCH check

3

4

1

*TC7SH08

3 5

R409 0_4

20111128 add 0ohm to passed IMVP_PERGD

2

CPT/PPT (LVDS,DDI)

U26D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

Panther Point_R1P 0

IMVP_PWRGD <3,33> GFX_PWRGD <24, 33>

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_CTRLCLK

SDVO_CTRLDATA

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

CRT

2

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

DDPB_AUXN DDPB_AUXP

DDPB_HPD

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_AUXN DDPC_AUXP

DDPC_HPD

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_AUXN DDPD_AUXP

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AP43 AP45

AM42 AM40

AP39 AP40

P38 M39

AT49 AT47 AT40

AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

INT_HDMITX2N_C INT_HDMITX2P_C INT_HDMITX1N_C INT_HDMITX1P_C INT_HDMITX0N_C INT_HDMITX0P_C INT_HDMICLK-_C INT_HDMICLK+_C

DisplayPort C DisplayPort D

INT_HDMITX2N_C <16> INT_HDMITX2P_C <16> INT_HDMITX1N_C <16> INT_HDMITX1P_C <16> INT_HDMITX0N_C <16> INT_HDMITX0P_C <16> INT_HDMICLK-_C <16> INT_HDMICLK+_C <16>

Size Document Number Rev

Panther Point 1/6

Date: Sheet of

Monday, April 09, 201 2

Date: Sheet of

Monday, April 09, 201 2

Date: Sheet of

Monday, April 09, 201 2

1

07

HDMI_DDCCLK_SW <16> HDMI_DDCDATA_SW <1 6>

HDMI_HP <16 >

Quanta Computer Inc.

PROJECT :

Z09

PROJECT :

Z09

PROJECT :

Z09

7 40

1

INT. HDMI

3A

5

RTC Circuitry(RTC)

20mils

R545 *SHORT_6

+3VPCU

R530 1K_4

D D

20MIL 20MIL

VCCRTC_2 VCCRTC_3 VCCRTC_4

12

BT1 RTC SOCKET

20MIL

20111117 change back RTC connect

20111118 change RTC connect to 2P. 20111121 change back RTC connector to socket.

HDA Bus(CLG)

PCH JTAG Debug (CLG)

C C

R428 51_4

PCH Dual SPI (CLG)

+3V_S5

B B

PCH_SPI_CS0# PCH_SPI_CLK PCH_SPI_SI PCH_SPI_SO

R520 3. 3K_4

+3V_PCH_ME

10/11 add

PCH_SPI_CS1# PCH_SPI_CLK

R486 33 _4

PCH_SPI_SI

R494 33 _4

PCH_SPI_SO

R525 33 _4

C508 *22p/5 0V_4

20111129 conta ct to EC thou gth series res istor.

PCH_SPI_CLK_EC<24>

PCH_SPI_SI_EC<24> PCH_SPI_SO_EC<24 >

+3V_PCH_ME

A A

SPI_CS0#_UR_ME<24>

+3V_RTC

R35 20K _4

D14

3

VCCRTC_1

20MIL

Q33

MMBT3904

PCH_AZ_CODEC_BITCLK<19>

PCH_AZ_CODEC_SYNC<19>

PCH_AZ_CODEC_RST#<19>

PCH_AZ_CODEC_SDOUT<19>

+3V_S5

R423 210/F_4

R422 100/F_4

R523 3.3K_4

SPI_CS0#_UR_ME

0mils

R48 20K _4

BAT54C

C38 1u/6.3V_4

1 3

R519 4.7 K_4

20120109 change footprint.

2

20111116 For EMI solution.

C430 22p/50V_4

R421

R97

210/F_4

XDP_TMS_VT PCH_XDP_TDO_VT PCH_XDP_TDO XDP_TCLK_VT

R419

R96

100/F_4

(Default for WIN8)

W25Q32BVSSIG / AKE391P0N00-- --->4MB W25Q16BVSSIG / AKE38FP0N01-- --->2MB

R492 *SHORT_6

10/11 add

U27

1

CE#

6

R490 33 _4 R489 33 _4 R522 33 _4

20111103 add pull up 10k to PSI CS#.

C520 *22p/50V_4

5

SCK

5

SI

2

SO

HOLD#

3

WP#

ROM-2M_ME

U28

1

CE#

6

SCK

5

SI

2

SO

HOLD#

3

WP#

ROM-4M_EC

R521 *0_ 4

R526 0_ 4

R620 47K_4

C31 1u/6.3V_4

C36 1u/6.3V_4

R390 33 _4 R347 33 _4 R51 33 _4 R376 33 _4

8

VDD

7

R491 3. 3K_4

4

VSS

8

VDD

7

R488 3. 3K_4

4

VSS

+3V_PCH_ME

12

J2

*SHORT_ PAD1

SRTC_RST#

12

J1

*SHORT_ PAD1

R518 4.7 K_4

ACZ_BITCLK_RACZ_BITCLK_ R ACZ_SYNC_CODEC ACZ_RST#_R ACZ_SDOUT_R

+3V_PCH_ME

RTC_RST#

68.1K/F_4

150K/F_4

C114

0.1u/10V_4

C580

0.1u/10V_4

PCH_SPI_CS0#

PCH_SPI_CS1#

R517

R529

4

PCH2(CLG)

+5V_S5

Add MOSFET to separate CODEC SYNC signal

+5V

PCH Strap Table

Pin Name

SPKR

GNT3# / GPIO55

INTVRMEN

GNT1# / GPIO51

GPIO19

HDA_SDO

DF_TVS

GPIO28

HDA_SYNC On-Die PLL VR Voltage Select RSMRST

GPIO15

DSWVREN

NV_ALE

4

3

C424 18p/5 0V_4

C425 18p/5 0V_4

20110530-modif y

R349 *SHORT_4

ACZ_SYNC_CODEC

CRB 1.0

R348 1M_4

20111128 Remove net TP_INT#, becaue change to pin E12.

Strap description

No reboot mode setting PWROK

Top-Block Swap Override

1

+3V_RTC

ZRH use 2N7002D

2

3

Q21 2N7002K

PCH_AZ_CODEC_SDIN0<19>

XDP_TCLK_VT<3,2 2> XDP_TMS_VT<3,2 2> PCH_XDP_TDO_VT<3>

+3V_PCH_ME

12

Y4

32.768KHZ

R68 1M_ 4

TP2 TP13

TP14

R524 *47 K_4

Sampled

PWROK

R408

RTC_X1

10M_4

RTC_X2 RTC_RST# SRTC_RST# SM_INTRUDER# PCH_INVRMEN

ACZ_BITCLK_R

ACZ_SYNC_R

SPKR

SPKR<1 9>

ACZ_RST#_R

ACZ_SDOUT_R

PCH_GPIO33 PCH_GPIO13

XDP_TCLK_VT XDP_TMS_VT PCH_XDP_TDO_VT

PCH_XDP_TDO

PCH_SPI_CLK PCH_SPI_CS0#

PCH_SPI_CS1#

PCH_SPI_SI PCH_SPI_SO

Configuration

0 = Default (weak pull-down 20K)

1 = Setting to No-Reboot mode 0 = "top-block swap" mode

1 = Default (weak pull-up 20K)

Integrated 1.05V VRM enable ALWAYS Should be always pull-up

Boot BIOS Selection 1 [bit-1]

Boot BIOS Selection 0 [bit-0]

Flash Descriptor Security

DMI/FDI Termination voltage

On-die PLL Voltage Regulator RSMRST#

Intel ME Crypto Transport Layer Security (TLS) cipher suite internal PD

DEEP S4/S5 well On Die DSW VR Enable

Intel Anti-Theft HDD protection

Only for Interposer

PWROK

0 = effect (default)(weak pull-down 20K)

RSMRST

1 = overridden 0 = Set to Vss (weak pull-down 20K)

PWROK

1 = Set to Vcc

0 = Disable

1 = Enable (weak pull-up 20K)

0 = Support by 1.8V (weak pull-down)

1 = Support by 1.5V

0 = Disable (Default)

RSMRST

1 = Enable

High = Enable (Default)

DSW

Low = Disable

PWROK 0 = Disable (Internal pull-down 20kohm)

3

CPT/PPT (HDA,JTAG,SATA)

U26A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

TP9

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST# / GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

Panther Point_R1P 0

GNT0#GNT1#

Boot Location

11

SPI

*

00

LPC

RTCIHDA

JTAG

SPI

+3V_RTC

+3V +3V

+3V_RTC

+3V_S5

+3V

+3V +

ME_WR#<24>

+1.8V

3V_S5

+3V

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

LPC

FWH4 / LFRAME#

LDRQ1# / GPIO23

SATA 6G

SATA

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATA0GP / GPIO21 SATA1GP / GPIO19

R482 2.2K_4 R483 1K_4

R439 *1K _4

+3V_S5

R60 33 0K_4

2

C38 A38 B37 C37

D36 E36

PCH_DRQ#0

LDRQ0#

SERIRQ

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA1RXN SATA1RXP SATA1TXN SATA1TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SATALED#

R460 *1K _4

R418 *1K _4

R391 33 0K_4

R412 *1K _4 R448 *1K _4

R350 1K_4

R413 1K _4

R479 *1K_4

2

K36 V5

AM3 AM1 AP7 AP5

AM10 AM8 AP11 AP10

AD7 AD5 AH5 AH4

AB8 AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11 Y10

AB12 AB13

AH1

P3 V14 P1

R377 *SHORT_4

+1.8V

TP5

PCH_DRQ#1

TP11

R135 8. 2K_4

UM77 SATA port 1,3 disabl e.

SATA_COMP

R128 37 .4/F_4

SATA3_COMP

R131 49 .9/F_4

SATA3_RBIAS

R464 75 0/F_4

20111108 PU 10k to +3V, becaue no sata LED.20111110 change power plant to +3V_PCH_ME

SATA_ACT#

R443 10K _4

PCH_ODD_EN BBS_BIT0

20111127 add R444 PU 10K to +3V for PCH_ODD_EN not use.

SPKR

PCI_GNT3# <9>

PCH_INVRMEN

BBS_BIT1 <9>

BBS_BIT0

ACZ_SDOUT_R

DF_TVS <10> H_SNB_IVB# <3>

PLL_ODVR_EN <10 >

ACZ_SYNC_R

PCH_GPIO15 <10>

R59 *33 0K_4

DSWVREN <7>

NV_ALE <9>

1

LPC_LAD0 <19,20,24> LPC_LAD1 <19,20,24> LPC_LAD2 <19,20,24> LPC_LAD3 <19,20,24>

LPC_LFRAME# <19,20, 24>

SERIRQ <19,24>

TP15

TP26

+3V

R459 10K _4

CRB 1.0 uses 10kohm

+3V

SATA_RXN0 <21> SATA_RXP0 <21> SATA_TXN0 <21> SATA_TXP0 <21>

SATA_RXN1 <20> SATA_RXP1 <20> SATA_TXN1 <20> SATA_TXP1 <20>

DG recomm ended that A C couplin g capacitors sho uld be close to the co nnector (<100 m ils) for o ptimal si gnal qual ity.

SATA_RXN5_C <21> SATA_RXP5_C < 21> SATA_TXN5 <21> SATA_TXP5 <21>

PCH_ODD_EN <21>

+3V

SATA HDD

20110908 acer request HDD,MSATA need SATA3.

mSATA

SATA ODD

+1.05V_VTT

SATA0GP/GPIO21 SATA4GP/GPIO16 SATA5GP/GPIO49 If these pins are unused use 8.2k to 10k pull-up to +Vcc3_3 or 8.2k to 10k pull-do wn to ground

Used as GPIO only. at chklist 1.2

Default weak pull-up on GNT0/1# [Need external pull-down for LPC BIOS]

ME_WR default EC setting folating

for future CPU , Sandy Bridge NC DF_TVS needs t o be pulled up to VccDFTERM power rail through 2.2 kO hm ±5% - R8361 change to 0 or not??

Needs to be pu lled High for Huron River p latform. chklist 1.2

Quanta Computer Inc.

PROJECT :

Panther Point 2/6

Monday, April 09, 201 2

PROJECT :

1

Size Document Number Rev

Date: Sheet o f

Z09

08

8 40

3A

5

CPT/PPT (PCI,USB,NVRAM)

U26E

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

TP17 TP30

TP20 TP29

TP18 TP21

TP16 TP19

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

DGPU_EDIDSEL# DGPU_SELECT# REQ#3

BOARD_ID2

MPC_PWR_CTRL# DGPU_PWR_EN DGPU_HOLD_RST# EXTTS_SNI_DRV1_PCH

TP12

PCI_PLTRST#

PCLK_TPM_R CLK_LPC_DEBUG_C

CLK_PCI_775_C

PLTRST#

R379 RAMID@10K_4 R71 *RAMID@10K_4

DGPU_PWR_EN

PCI_PME#

R351 100K_4

R370 10K_4

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

H3

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

B21

TP21

M20

TP22

AY16

TP23

BG46

TP24

BE28

TP25

BC30

TP26

BE32

TP27

BJ32

TP28

BC28

TP29

BE30

TP30

BF32

TP31

BG32

TP32

AV26

TP33

BB26

TP34

AU28

TP35

AY30

TP36

AU26

TP37

AY26

TP38

AV28

TP39

AW30

TP40

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1# / GPIO50

C44

REQ2# / GPIO52

E40

REQ3# / GPIO54

D47

GNT1# / GPIO51

E42

GNT2# / GPIO53

F46

GNT3# / GPIO55

G42

PIRQE# / GPIO2

G40

PIRQF# / GPIO3

C42

PIRQG# / GPIO4

D44

PIRQH# / GPIO5

K10

PME#

C6

PLTRST#

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

Panther Point_R1P0

PLTRST# <17,19,20,24,25>

+3V_S5

+3V

USB3.0

USB30_RX1N USB30_RX2N USB30_RX3N USB30_RX4N USB30_RX1P USB30_RX2P USB30_RX3P USB30_RX4P USB30_TX1N USB30_TX2N USB30_TX3N

USB30_TX4N USB30_TX1P USB30_TX2P USB30_TX3P USB30_TX4P

Hynix

Elpida

+3V +3V +3V

+3V +3V +3V +3V

RSVD

PCI

+3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5

USB

OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43 OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14

RAM_IDnRAM

0x000

0x001

D D

TX AC cap place at connector side, AC cap to connector < 400mils

C C

20111108 Add PCLK_TPM for TPM.

PCLK_TPM<19> CLK_LPC_DEBUG<20>

B B

PLTRST#(CLG)

PCI_PLTRST#

DDRIII Memory down strap

A A

USB30_RX1-<23> USB30_RX2-<23>

USB30_RX1+<23> USB30_RX2+<23>

USB30_TX1-<23> USB30_TX2-<23>

USB30_TX1+<23> USB30_TX2+<23>

BBS_BIT1<8>

BOARD_ID2<10>

PCI_GNT3#<8>

DGPU_PWR_EN<39>

DGPU_HOLD_RST#<25>

PCI_PLTRST#<3,24>

R104 22_4

CLK_PCI_FB CLK_PCI_FB_C

R431 22_4 R115 22_4

CLK_PCI_EC<24>

R99 22_4

20111128 change power plant to +3V.

+3V

C417

0.1u/10V_4

2

4

1

U23

3 5

TC7SH08FU

R366 *0_4

RAM_ID0

R394 *RAMID@5K/F_4

RAM_ID1

R393 RAMID@15K/F_4 R378 *RAMID@10K_4

RAM_ID2

R70 RAMID@15K/F_4

RAM_ID3

R395 RAMID@15K/F_4

R386 *100K_4

5

AY7

RSVD1

AV7

RSVD2

AU3

RSVD3

BG4

RSVD4

AT10

RSVD5

BC8

RSVD6

AU2

RSVD7

AT4

RSVD8

AT3

RSVD9

AT1

RSVD10

AY3

RSVD11

AT5

RSVD12

AV3

RSVD13

AV1

RSVD14

BB1

RSVD15

BA3

RSVD16

BB5

RSVD17

BB3

RSVD18

BB7

RSVD19

BE8

RSVD20

BD4

RSVD21

BF6

RSVD22

AV5

RSVD23

AV10

RSVD24

AT8

RSVD25

AY5

RSVD26

BA2

RSVD27

AT12

RSVD28

BF3

RSVD29

C24

USBP0N

A24

USBP0P

C25

USBP1N

B25

USBP1P

C26

USBP2N

A26

USBP2P

K28

USBP3N

H28

USBP3P

E28

USBP4N

D28

USBP4P

C28

USBP5N

A28

USBP5P

C29

USBP6N

B29

USBP6P

N28

USBP7N

M28

USBP7P

L30

USBP8N

K30

USBP8P

G30

USBP9N

E30

USBP9P

C30

USBP10N

A30

USBP10P

L32

USBP11N

K32

USBP11P

G32

USBP12N

E32

USBP12P

C32

USBP13N

A32

USBP13P

C33

USB_BIAS

USBRBIAS#

B33

USBRBIAS

A14

USB_OC0#

K20

USB_OC1#

B17

USB_OC2#

C16

RAM_ID0

L16

USB_OC4#

A16

RAM_ID1

D14

RAM_ID2

C14

RAM_ID3

PCI/USBOC# Pull-up(CLG)

MPC Switch Control

MPC_PWR_CTRL#

Optimize SKU

+3V

R93 EV@10K_4 R100 IV@10K_4

+3V

R108 EV@10K_4 R114 IV@10K_4

4

NV_ALE <8>

port9 can be used on debug mode

USBP0- <23> USBP0+ <23> USBP1- <23>

USBP1+ <23>

TP7 TP1

USB port6/7 may not be available on all PCH sku (HM55 support 12port only)

USBP8- <15>

USBP8+ <15>

USBP9- <23>

USBP9+ <23>

USBP10- <20>

USBP10+ <20>

TP4 TP6

UM77 USB port 6,7,12,13 disable.

R86 22.6/F_4

USB_OC0# <23>

USB_OC0#

R55 10K_4

USB_OC1#

R82 10K_4

USB_OC2#

R392 10K_4

USB_OC4#

Low = MPC ON High = MPC OFF (Default)

R49 *1K_4

SKU_ID1

SKU_ID0 <10>

4

MB USB left side MB usb left side

XHCI for USBP0-3

EHCI1

Camera MB USB right side BT+WL

+3V_S5

EHCI2

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

+3V

MPC_PWR_CTRL# EXTTS_SNI_DRV1_PCH REQ#3

dGPU_PW_CTRL#

SKU_ID1

(GPIO68)

(GPIO64)

CTL : dGPU_VRON

1

UMA Only

GPU Only

d

Switchable (Mux)

Optimize (Muxless)

dGPU_PW_CTRL# 0 = GPU power is control by PCH GPIO (Discrete, SG or Optimize) 1 = GPU power is control by H/W (pure Discrete SKU)

0

0 or 1

0

1

0

1

Cardreader

Wireless

R44

10

9 8 7 4

10KX8

SKU_ID0 (GPIO16)

LAN

R74 8.2K_4 R75 8.2K_4 R373 8.2K_4

1 2 3

56

VGA H/W Signal

0

1

0

UMA+GPU

1

3

PCIE port 1 for commeral model S3 can't weak up.

PCIE_RX2-<19> PCIE_RX2+<19> PCIE_TX2-<19> PCIE_TX2+<19>

PCIE_RX3-<17> PCIE_RX3+<17> PCIE_TX3-<17> PCIE_TX3+<17>

PCIE_RX8-<20> PCIE_RX8+<20> PCIE_TX8-<20> PCIE_TX8+<20>

Cardreader

20110908 WLAN support S3 wake up function.

Wireless

LAN

CLK_PCIE_XDPN<3> CLK_PCIE_XDPP<3>

+3V

DGPU_HOLD_RST#

DGPU_EDIDSEL#

dGPU_SELECT#

Setup Menu

UMA boot

UMA

Hidden

GPU boot

GPU

Hidden

UMA boot

dGPU/SG

UMA boot

UMA

UMA/SG

3

PCIE_TX2-_C

C108 0.1U/10V_4

PCIE_TX2+_C

C105 0.1U/10V_4

C103 0.1u/10V_4 C100 0.1u/10V_4

UM77 4~7 PCIE port disable

C106 0.1u/10V_4 C109 0.1u/10V_4

CLK_PCIE_MMC#<19> CLK_PCIE_MMC<19>

PCIE_CLKREQ0#

PCIE_CLKREQ0#<19>

TP61

PCIE_CLKREQ1#

PCIE_CLKREQ2#

PCIE_CLKREQ4#

CLK_PCIE_WLAN#<20> CLK_PCIE_WLAN<20>

PCIE_CLKREQ5#

PCIE_CLKREQ5#<20>

CLK_PCIE_LOM#<17> CLK_PCIE_LOM<17>

CLK_PCIE_LAN_REQ#<17>

CLK_PCIE_REQ6#

CLK_PCIE_REQ7#

CLK_REQ/Strap Pin(CLG)

+3V_S5

R79 10K_4R40 8.2K_4 R364 10K_4R88 10K_4 R430 10K_4 R399 10K_4 R402 10K_4 R365 10K_4 R83 10K_4

+3V

R424 10K_4 R124 10K_4

+3V_S5

R102 10K_4

20111021 remove pull/down resistor

CLK_BUF_BCLKN CLK_BUF_BCLKP

CLK_BUF_PCIE_3GPLLN CLK_BUF_PCIE_3GPLLP CLK_BUF_DREFCLKN CLK_BUF_DREFCLKP CLK_BUF_DREFSSCLKN CLK_BUF_DREFSSCLKP CLK_PCH_14M

CLOCK TERMINATION for FCIM

2

CPT/PPT (PCI-E,SMBUS,CLK)

U26B

BG34

PERN1

PCIE_TXN3_C PCIE_TXP3_C

PCIE_TXN8_C PCIE_TXP8_C

PCIE_CLKREQ3#

CLK_PCIE_LAN_REQ#

TP34

TP42

PCIE_CLKREQ4# PCIE_CLKREQ5# PCIE_CLKREQ0# PCIE_CLKREQ3# CLK_PCIE_LAN_REQ# CLK_PCIE_REQ6# CLK_PCIE_REQ7#

PCIE_CLKREQ1# PCIE_CLKREQ2#

PCIE_CLKREQ_PEG#_R

R504 10K_4 R503 10K_4

R164 10K_4R380 *RAMID@10K_4 R163 10K_4 R89 10K_4 R90 10K_4 R480 10K_4 R478 10K_4 R111 10K_4

BJ34 AV32 AU32

BE34 BF34 BB32 AY32

BG36 BJ36 AV34 AU34

BF36 BE36 AY34 BB34

BG37 BH37 AY36 BB36

BJ38 BG38 AU36 AV36

BG40 BJ40 AY40 BB40

BE38 BC38

AW38

AY38

Y40 Y39

J2

AB49 AB47

M1

AA48 AA47

V10

Y37 Y36

A8

Y43 Y45

L12

V45 V46

L14

AB42 AB40

E6

V40 V42

T13

V38 V37

K12

AK14 AK13

Panther Point_R1P0

PERP1 PETN1 PETP1

PERN2 PERP2 PETN2 PETP2

PERN3 PERP3 PETN3 PETP3

PERN4 PERP4 PETN4 PETP4

PERN5 PERP5 PETN5 PETP5

PERN6 PERP6 PETN6 PETP6

PERN7 PERP7 PETN7 PETP7

PERN8 PERP8 PETN8 PETP8

CLKOUT_PCIE0N CLKOUT_PCIE0P

PCIECLKRQ0# / GPIO73

CLKOUT_PCIE1N CLKOUT_PCIE1P

PCIECLKRQ1# / GPIO18

CLKOUT_PCIE2N CLKOUT_PCIE2P

PCIECLKRQ2# / GPIO20

CLKOUT_PCIE3N CLKOUT_PCIE3P

PCIECLKRQ3# / GPIO25

CLKOUT_PCIE4N CLKOUT_PCIE4P

PCIECLKRQ4# / GPIO26

CLKOUT_PCIE5N CLKOUT_PCIE5P

PCIECLKRQ5# / GPIO44

CLKOUT_PEG_B_N CLKOUT_PEG_B_P

PEG_B_CLKRQ# / GPIO56

CLKOUT_PCIE6N CLKOUT_PCIE6P

PCIECLKRQ6# / GPIO45 CLKOUT_PCIE7N

CLKOUT_PCIE7P PCIECLKRQ7# / GPIO46 CLKOUT_ITPXDP_N

CLKOUT_ITPXDP_P

+3V_S5

SMBUSController

+3V_S5

SML1ALERT# / PCHHOT# / GPIO74

PCI-E*

+3V_S5

CLOCKS

+3V

+3V_S5

SMBus(EC)

+3V_S5

2ND_MBCLK<24>

2ND_MBDATA<24>

+3V_S5

if net DRAMRST_CNTRL_PCH change to PCH control need stuff R358.

R72 10K_4 R343 2.2K_4 R340 2.2K_4 R361 2.2K_4 R360 2.2K_4 R357 10K_4

2

+3V_S5 +3V_S5

Link

PEG_A_CLKRQ# / GPIO47

+3V_S5

+3V +3V +3V +3V

FLEX CLOCKS

5

621

SMBALERT# SMB_PCH_CLK SMB_PCH_DAT SMB_ME0_CLK SMB_ME0_DAT SML1ALERT#_R

SMBALERT# / GPIO11

SMBCLK

SMBDATA

SML0ALERT# / GPIO60

SML0CLK

SML0DATA

SML1CLK / GPIO58

SML1DATA / GPIO75

CL_CLK1

CL_DATA1

CL_RST1#

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N CLKOUT_DP_P

CLKIN_DMI_N

CLKIN_DMI_P

CLKIN_GND1_N CLKIN_GND1_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_SATA_N CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64 CLKOUTFLEX1 / GPIO65 CLKOUTFLEX2 / GPIO66 CLKOUTFLEX3 / GPIO67

R338

2.2K_4

Q19

43

2N7002DW

20111117 change footprint to dual type.

1

20111122 add for Touch pad interrupt pin from GPIO13 to GPIO11.

E12

SMBALERT#

H14 C9

A12 C8 G12

C13 E14 M16

M7

T11

P10

M10

PCIE_CLKREQ_PEG#_R

AB37 AB38

AV22 AU22

AM12 AM13

BF18

CLK_BUF_PCIE_3GPLLN

BE18

CLK_BUF_PCIE_3GPLLP

BJ30

CLK_BUF_BCLKN

BG30

CLK_BUF_BCLKP

G24

CLK_BUF_DREFCLKN

E24

CLK_BUF_DREFCLKP

AK7

CLK_BUF_DREFSSCLKN

AK5

CLK_BUF_DREFSSCLKP

K45

CLK_PCH_14M

H45

CLK_PCI_FB

V47

XTAL25_IN

V49

XTAL25_OUT

Y47

XCLK_RCOMP

K43

CLK_FLEX0

F47

CLK_FLEX1

H47 K49

R339

2.2K_4

SMB_ME1_CLK

SMB_ME1_DAT

SMBALERT# <19>

SMB_PCH_CLK

SMB_PCH_CLK <20>

SMB_PCH_DAT

SMB_PCH_DAT <20>

DRAMRST_CNTRL_PCH SMB_ME0_CLK SMB_ME0_DAT

SML1ALERT#_R SMB_ME1_CLK SMB_ME1_DAT

CL_CLK1

CL_DATA1

CL_RST1#

DRAMRST_CNTRL_PCH <4>

20110907 del net SML1ALERT#

TP24

CL_CLK1 <20>

CL_DATA1 <20>

CL_RST1# <20>

R103 EV@0_4

CLK_PCIE_VGAN <25> CLK_PCIE_VGAP <25>

CLK_CPU_BCLKN <3> CLK_CPU_BCLKP <3>

CLK_DPLL_SSCLKN <3> CLK_DPLL_SSCLKP <3>

R132 90.9/F_4

+1.05V_VTT

R85 *SHORT_4

TP59

R457 *SHORT_4

SMBus(PCH)

+3V

S5 S0

5

SMB_PCH_DAT

621

SMB_PCH_CLK

2N7002DW

Size Document Number Rev

Panther Point 3/6

Date: Sheet of

Monday, April 09, 2012

Date: Sheet of

Monday, April 09, 2012

Date: Sheet of

Monday, April 09, 2012

1

09

For LAN

For EC

PEG_CLKREQ# <25>

XTAL25_IN

Y2 25MHz_XTAL

2 4

1 3

XTAL25_OUT

C87 10p/50V_4 R133

1M_4 C74 10p/50V_4

20120201 Change CAP from 27P to 10P.

SKU_ID1

BOARD_ID4 <10,19>

ODD_PRSNT# <21>

R316

R317

4.7K_4

Q20

43

CLK_SDATA <13,14,19>

CLK_SCLK <13,14,19>

Quanta Computer Inc.

PROJECT :

Z09

PROJECT :

Z09

PROJECT :

Z09

9 40

3A

5

S_GPIO

R112 100_4

SIO_EXT_SMI#<2 4>

D D

C C

20110907 del R5217 and net SML1ALERT#

B B

SATA2GP : strap for reserved at chklist 1.2 SATA3GP : strap for reserved at chklist 1.2 NOTE: The internal pull-down is disabled after PLTRST# deasserts. NOTE: This signal should not be pulled high when strap is sampled.

A A

2011/09/01 add select resistor

LCD_SELECT

LVDS = Pull HIGH eDP = Pull LOW

SIO_EXT_SCI#<24>

PCH_GPIO15<8>

WK_GPIO27<2 4>

PLL_ODVR_EN<8>

DGPU_VRON<38,39>

TP23

R371 *LVDS@1.5K/F_ 4

5

SKU_ID0<9>

DGPU_PW ROK<25>

R387 EDP @1K_4

SIO_EXT_SMI# BOARD_ID1 SIO_EXT_SCI# ICC_EN# PLL_ODVR_EN

TP25

SMIB

DGPU_PW ROK G_SENSOR_ID PCH_GPIO24 WK_GPIO27 PLL_ODVR_EN STP_PCI#

DGPU_VRON DMI_OVRVLTG FDI_OVRVLTG MFG_MODE BOARD_ID0 TEST_SET_UP CRIT_TEMP_RE P# SV_DET

+3V

FDI TERMINATION VOLTAGE OVERRIDE

4

CPT/PPT (GPIO,VSS_NCTF,RSVD)

U26F

R436 100K_4

T7

BMBUSY# / GPIO0

A42

TACH1 / GPIO1

H36

TACH2 / GPIO6

E38

TACH3 / GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL / GPIO12

G2

GPIO15

U2

SATA4GP / GPIO16

D40

TACH0 / GPIO17

T5

SCLOCK / GPIO22

E8

GPIO24 / MEM_LED

E16

GPIO27

P8

GPIO28

K1

STP_PCI# / GPIO34

K4

GPIO35

V8

SATA2GP / GPIO36

M5

SATA3GP / GPIO37

N2

SLOAD / GPIO38

M3

SDATAOUT0 / GPIO39

V13

SDATAOUT1 / GPIO48

V3

SATA5GP / GPIO49

D6

GPIO57

A4

VSS_NCTF_1

A44

VSS_NCTF_2

A45

VSS_NCTF_3

A46

VSS_NCTF_4

A5

VSS_NCTF_5

A6

VSS_NCTF_6

B3

VSS_NCTF_7

B47

VSS_NCTF_8

BD1

VSS_NCTF_9

BD49

VSS_NCTF_10

BE1

VSS_NCTF_11

BE49

VSS_NCTF_12

BF1

VSS_NCTF_13

BF49

VSS_NCTF_14

Panther Point_R1P0

FDI_OVRVLTG G_SENSOR_ID

4

+3V +3V +3V +3V

+3V_S5

+3V

GPIO

+3V_S5

DSW +3V_S5

+3V

+3V +3V

+3V

+3V_S5

R437 * 1K_4

LOW - Tx, Rx terminated to same voltage

+3V

TACH4 / GPIO68

+3V

TACH5 / GPIO69

+3V

TACH6 / GPIO70

+3V

TACH7 / GPIO71

+3V_S5

A20GATE

PECI

RCIN#

PROCPWRGD

THRMTRIP#

INIT3_3V#

DF_TVS

CPU/MISC

TS_VSS1 TS_VSS2 TS_VSS3 TS_VSS4

NC_1

VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23

NCTF

VSS_NCTF_24 VSS_NCTF_25 VSS_NCTF_26 VSS_NCTF_27 VSS_NCTF_28 VSS_NCTF_29 VSS_NCTF_30 VSS_NCTF_31 VSS_NCTF_32

+3V +3V

G_SENSOR_ID

3

C40

DGPU_PW _CTRL#

B41

LCD_SELECT

C41

BOARD_ID3

A40

R407 1.5K/F_4

P4

SIO_A20GATE

AU16

EC_PECI_R

P5

SIO_RCIN#

AY11 AY10

PCH_THR MTRIP#

T14 AY1

AH8 AK11 AH10 AK10

P37

BG2 BG48 BH3 BH47 BJ4 BJ44 BJ45 BJ46 BJ5 BJ6 C2 C48 D1 D49 E1 E49 F1 F49

R117 10K_4

R119 *1K_4

High = Disable (Default) Low = Enable

3

+3V

R162 *0_4

R156 390_4

TP75

SIO_A20GATE <24>

EC_PECI <3,24>

SIO_RCIN# <24> H_PWRG OOD <3> PM_THRMTR IP# <3>

DF_TVS <8>

SMIB

High = Strong (Default)

TEST_SET_UP

SGPIO

S_GPIO

MFG-TEST

MFG_MODE

2

GPIO Pull-up/Pull-down(CLG)

PCH_GPIO24

SIO_EXT_SMI# SIO_EXT_SCI#

STP_PCI# SIO_A20GATE SIO_RCIN# CRIT_TEMP_RE P#

20120201 reserve GPIO27 PU +3VPCU

WK_GPIO27

20111017 un-stuff R5126 for DSW

DGPU_PW ROK

GPIO27 : If not used then use 8.2-kΩ to 10-kΩ pull-down to GND.

Low = Tx, Rx terminated to same voltage (DC Coupling Mode) (DEFAULT)

R148 *10K_4

high VDDR=+1.35V_SUS for DDR3L Low VDDR =+1.5V_SUS(default)

R362 *10K_4

assign to VID for VDDR control

R106 10K_4 R389 10K_4 R385 10K_4 R384 *10K_4 R425 *10K_4

BOARD_ID2<9> BOARD_ID4<9,19>

high

low

DGPU_PW _CTRL#

Quanta Computer Inc.

PROJECT :

Panther Point 4/6

USB3.0 IC CTL

LOW = USB3.0 IC

R401 10K_4

SV_SET_UP

R147 10K_4

R149 *1K_4

R113 1K _4 R116 * 1K_4

R445 10K_4

R444 *1K_4

2

DMI TERMINATION VOLTAGE OVERRIDE

+3V_S5

+3V

Board_ID4 Hight=Symatic, LOW=ELAN.

+3V

R372 IV@1K_4

+3V

Size D ocument Numb er Rev

Monday, April 09, 2 012

Date: Sheet of

Monday, April 09, 2 012

Date: Sheet of

Monday, April 09, 2 012

Date: Sheet

1

R73 *10K_4 R440 10K_4

R39 10K_4 R50 10K_4

R420 *10K_4 R105 10K_4 R98 10K_4 R458 10K_4

R616 10K_4 R101 *10K_4

R87 *10K_4

DMI_OVRVLTG

R146 *200K/F _4

SV_DET

R400 100K_4

BOARD_ID0

R107 *10K_4

BOARD_ID1

R374 *10K_4

BOARD_ID2

R369 *10K_4

BOARD_ID3

R368 10K_4

BOARD_ID4

R427 10K_4

GPU power is control by H/W (pure Discrete SKU)

GPU power is control by PCH GPIO (Discrete, SG or Optimize)

R388 EV@100K_4

Z09

10 40

1

10

+3V_S5

+3VPCU

+3V

of

+3V

3A

+1.05V_VTT

L6 *1uH/25mA_6

+1.05V_VTT

R170 *SHORT_6 R171 *0_6

5

20111021 remove vcc core power sense net

VccCORE =1.3 A(60mils)

C82

C92

C81

1u/6.3V_4

+1.05V_VTT

20111117 remove 0ohm resistor.

C119 *10u/6.3V_6

VccIO =2.925 A(140mils)

C98

C91

C99

1u/6.3V_4

C94

C101

1u/6.3V_4

10u/6.3V_6

+3V_VCC_EXP+3V

R167 *SHORT_8

C121

0.1u/10V_4

+VCCAFDI_VRM

R506 *0_8

+1.05V_VTT

R158 *SHORT_8

+1.1V_VCC_DMI

+1.1V VCC_DMI witdth >= 20m ils.

+VCCAFDI_VRM

VCCVRM: 1.8V ( Destop) 02/20 del for Pre-E S1

1.5V ( Mobile)

5

C88

4.7u/6.3V_6

+VCCAFDI_VRM

+1.05V_VCCAPLL_FDI

+1.05V_VCCDPLL_FDI

CPT/PPT (POWER)

U26G

AA23

VCCCORE[1]

AC23

VCCCORE[2]

AD21

VCCCORE[3]

AD23

VCCCORE[4]

AF21

VCCCORE[5]

AF23

VCCCORE[6]

AG21

VCCCORE[7]

AG23

VCCCORE[8]

AG24

VCCCORE[9]

AG26

VCCCORE[10]

AG27

VCCCORE[11]

AG29

VCCCORE[12]

AJ23

VCCCORE[13]

AJ26

VCCCORE[14]

AJ27

VCCCORE[15]

AJ29

VCCCORE[16]

AJ31

VCCCORE[17]

AN19

VCCIO[28]

BJ22

VCCAPLLEXP

AN16

VCCIO[15]

AN17

VCCIO[16]

AN21

VCCIO[17]

AN26

VCCIO[18]

AN27

VCCIO[19]

AP21

VCCIO[20]

AP23

VCCIO[21]

AP24

VCCIO[22]

AP26

VCCIO[23]

AT24

VCCIO[24]

AN33

VCCIO[25]

AN34

VCCIO[26]

BH29

VCC3_3[3]

AP16

VCCVRM[2]

BG6

VccAFDIPLL

AP17

VCCIO[27]

AU20

VCCDMI[2]

Panther Point_R1P0

PCH5(CLG)

20111117 remove 0ohm resistor.

D D

R5285 near PCH ball for VCCP GND sense

+1.05V_VTT +1.05V _VCCAPLL_EXP

20111117 remove 0ohm resistor.

C C

VccDMI needs to be powered by the same 1.05 V voltage source as the CPU VCCIO, and the trace needs to be at least 20 mils width with full VSS/ VCC reference plane.

B B

+1.5V

+1.05V_VTT

A A

4

POWER

VCC CORE

VCCIO

FDI

U48

VCCADAC

U47

VSSADAC

CRTLVDS

AK36

VCCALVDS

AK37

VSSALVDS

AM37

VCCTX_LVDS[1]

AM38

VCCTX_LVDS[2]

AP36

VCCTX_LVDS[3]

AP37

VCCTX_LVDS[4]

V33

VCC3_3[6]

V34

VCC3_3[7]

AT16

VCCVRM[3]

AT20

VCCDMI[1]

DMI

AB36

VCCCLKDMI

AG16

VCCDFTERM[1]

AG17

VCCDFTERM[2]

AJ16

VCCDFTERM[3]

AJ17

VCCDFTERM[4]

DFT / SPI HVCMOS

V1

VCCSPI

20120105 change power plant to +3V for power saving.

+3V_VCCME_SPI

Reserve +3V_S5 to VCCSPI fo r EC 795 co-la yout

+3V

R118 *0_6 R126 1/F_4

4

+VCCA_DAC_1_2

VccADAC =1mA(8mils)

C61

C47

0.01u/25V_4

10u/6.3V_6

When Dis sku and eDP , LVDS power can short to GND

20111101 remove vccalcd and vcctx_lds power, when LVDS disable.

R125 *SHORT_6 C66

0.1u/10V_4

+VCCAFDI_VRM

C77

C78

*10u/6.3V_6

1u/6.3V_4

R159 *SHORT_8

C93

0.1u/10V_4

+3V_VCCME_SPI

C67 1u/6.3V_4

+3V

R634 *0_6 R121 0_6

L3 10u H/100mA_8

L2 180ohm/5A

C55

C43

0.1u/10V_4

10u/6.3V_6

+3V+3V_VCC_GIO

VCCDMI = 42mA( 10mils)

+1.1V_VCC_DMI

C104 1u/6.3V_4

VCCCLKDMI = 20 mA(8mils)

+VCC_DMI_CCI +1.05V _VTT+1.1V_VCC_DMI_CCI

L4 *10uH/100mA_8

+1.8V+VCCP_NAND

VCCPNAND = 190 mA(15mils)

R144 *1/F_4 R139 *SHORT_4

VCCSPI = 20mA( 8mils)

+3V_S5

20120216 remove R172 for power plant chnge to +1.05V_VTT.

+3V_SUS_CLKF33

C57

C68

1u/10V_4

4.7u/6.3V_6

R169 *SHORT_4

+1.1V VCC_DMI witdth >= 20m ils.

3

+3V

20120104 change power plant from +3V_S5 to +3VPCU.

+1.05V_VTT

L7 *10uH/100mA_8

VCCME(+1.05V) = ??A(??mils)

+1.05V_VTT

20120216 remove R168 for power plant chnge to +1.05V_VTT.

+1.05V_VTT

VCCRTC<1mA(8mi ls)

+1.05V_VTT

3

R134 *SHORT_6

R138 *SHORT_6

R143 *SHORT_6

R127 *0_6

R173 *SHORT_4

+3V_RTC

L5 10uH/100mA_8

L26 10uH/100mA_8

+3VPCU

+VCCAPLL_CPY_PCH

+1.05V_VTT

R449 *SHORT_4

C86 1u/6.3V_4

C85 1u/6.3V_4

C90 1u/6.3V_4

C63 *1u/6.3V_4

1mA(8mils)

C111

4.7u/6.3V_6

C40 1u/6.3V_4

R136 *0_8

+1.05V_VTT

VCCDSW3_3= 3mA

C52

0.1u/10V_4

R141 *SHORT_6

+1.05V_VTT

C118 *10u/6.3V_6

VccASW =1.01 A(60mils)

C79

C84

1u/6.3V_4

C69 10u/6.3V_6

C51 0.1u/10V_4

65mA(10mils) 8mA(8mils)

VCCDIFFCLKN= 5 5mA(10mils) VCCSSC= 95mA(1 0mils)

C58 0.1u/10V_4

C120

0.1u/10V_4

C37

0.1u/10V_4

+

C529 220u/2.5V_3528

+

C512 220u/2.5V_3528

C80 1u/6.3V_4

C70 10u/6.3V_6

+VCCAFDI_VRM

C116

0.1u/10V_4

C39

0.1u/10V_4

+1.05V_VCCA_A_DPL

C115 1u/6.3V_4

+1.05V_VCCA_B_DPL

C112 1u/6.3V_4

C65 *0.1u/10V_4

C97 *1u/6.3V_4

+VCCRTCEXT

+VCCAFDI_VRM

+1.05V_VCCA_A_DPL +1.05V_VCCA_B_DPL

+VCCDIFFCLK +VCCDIFFCLKN

+V1.05V_SSCVCC

+VCCSST

+V1.05M_VCCSUS

+VTT_VCCPCPU

2

CPT/PPT (POWER)

U26J

AD49

+VCCACLK

T16

+VCCPDSW

V12

PCH_VCCDSW

T38

+3V_SUS_CLKF33

BH23 AL29

+VCCDPLL_CPY

AL24

+VCCSUS1

AA19 AA21 AA24 AA26 AA27 AA29 AA31 AC26 AC27 AC29 AC31 AD29 AD31

W21 W23 W24 W26 W29 W31 W33

N16

Y49

BD47 BF47

AF17 AF33 AF34 AG34

AG33

V16

T17 V19

BJ8

A22

Panther Point_R1P0

+5V_S5

2

POWER

VCCACLK

VCCDSW3_3

DCPSUSBYP

VCC3_3[5]

VCCAPLLDMI2 VCCIO[14]

DCPSUS[3]

VCCASW[1] VCCASW[2] VCCASW[3] VCCASW[4] VCCASW[5] VCCASW[6] VCCASW[7] VCCASW[8] VCCASW[9] VCCASW[10] VCCASW[11] VCCASW[12] VCCASW[13] VCCASW[14]

Clock and Miscellaneous

VCCASW[15] VCCASW[16] VCCASW[17] VCCASW[18] VCCASW[19] VCCASW[20]

DCPRTC

VCCVRM[4]

VCCADPLLA VCCADPLLB

VCCIO[7] VCCDIFFCLKN[1] VCCDIFFCLKN[2] VCCDIFFCLKN[3]

VCCSSC

DCPSST

DCPSUS[1] DCPSUS[2]

V_PROC_IO

CPURTC

VCCRTC

C411

*0.33u/10V_6

SLP_SUS#<7,24>

20111018 ADD DSW Cricuit 20111030 modify cuirucit.

PCI/GPIO/LPCMISC

SATA USB

HDA

N26

VCCIO[29]

P26

VCCIO[30]

P28

VCCIO[31]

T27

VCCIO[32]

T29

VCCIO[33]

T23

+3V_VCCPUSB

VCCSUS3_3[7]

T24

VCCSUS3_3[8]

V23

VCCSUS3_3[9]

V24

VCCSUS3_3[10]

P24

+3V_VCCAUBG

VCCSUS3_3[6]

T26

+VCCAUPLL

VCCIO[34]

M26

+5V_PCH_VCC5REFSUS

V5REF_SUS

AN23

+VCCA_USBSUS

DCPSUS[4]

AN24

+3V_VCCPSUS

VCCSUS3_3[1]

P34

+5V_PCH_VCC5REF

V5REF

N20

VCCSUS3_3[2]

N22

VCCSUS3_3[3]

P20

+3V_VCCPSUS

VCCSUS3_3[4]

P22

VCCSUS3_3[5]

AA16

VCC3_3[1]

W16

+3V_VCCPCORE

VCC3_3[8]

T34

+3V

C56

0.1u/10V_4

AJ2

AF13

AH13 AH14

AF14 AK1

+V1.1LAN_VCCAPLL

VCCVRM= 114mA( 15mils)

AF11

+VCCAFDI_VRM

AC16 AC17

20111117 remove 0ohm resistor.

C76

AD17

1u/6.3V_4

+1.05V_VTT

T21

V21

T19

P32

+V3.3A_1.5A_HDA_IO

C429

C53

0.1u/10V_4

*1u/6.3V_4

+5VCC_S5 +3VCC_S5

+3V_S5

321

Q23AO3413

R344 *SHORT_6

4 3

VCCAPLLSATA

VCCVRM[1]

VCCASW[22]

VCCASW[23]

VCCASW[21]

VCCSUSHDA

R354 100K_4

VCC3_3[4]

VCC3_3[2]

VCCIO[5]

VCCIO[12] VCCIO[13]

VCCIO[6]

VCCIO[2] VCCIO[3] VCCIO[4]

1

11

+1.05V_VTT

20111117 remove 0ohm resistor.

C59 1u/6.3V_4

R123 *SHORT_6

C96 *1u/6.3V_4

+1.05V_VTT

20111107 remove R5144 PU 1.5VSUS.

6

215

Size Document Number Rev

Date: Sheet of

VCCSUS3_3 = 11 9mA(15mils)

+3VCC_S5

20111018 change for DSW

R56 *SHORT_6

C62

0.1u/10V_4

R57 *SHORT_6

C50

0.1u/10V_4

+1.05V_VTT

VCC5REFSUS=1mA

R110 10/F_4

D11 RB500V-40

C44

0.1u/10V_4

V5REF= 1mA

R353 10/F_4

D10 RB500V-40 C49 1u/6.3V_4

R58 *SHORT_6

VCCSUS3_3 = 11 9mA(15mils)

C48 1u/10V_4

R130 *SHORT_6

VCCPCORE = 28m A(10mils)

C71

0.1u/10V_4

+3V

C95

0.1u/10V_4

+1.05V_VTT

20111117 remove 0ohm resistor.

C89 1u/10V_4

??mA(??mils)

L24 *10uH/100mA_8 C476

*10u/6.3V_6

+1.05V_VTT

VCCME = 1.01A( 60mils)

R375 *SHORT_4

C412

*0.33u/10V_6

VCCSUSHDA= 10m A(8mils)

+3V_S5

Q22AO3413

R355 100K_4

R345 *SHORT_6

Q24 2N7002DW

20111117 change mose footprint to dual type.

Quanta Computer Inc.

PROJECT :

Panther Point 5 /6

Monday, April 09, 2012

1

+5VCC_S5 +3VCC_S5

20111018 change for DSW

+5V +3V

20111018 change for DSW

+3VCC_S5

+3V

321

Z09

11 40

3A

5

4

3

2

1

PCH6(CLG)

12

U26I

AY4

VSS[159]

D D

IBEX PEAK-M (GND)

U26H

H5

VSS[0]

AA17

VSS[1]

AA2

VSS[2]

AA3

VSS[3]

AA33

VSS[4]

AA34

VSS[5]

AB11

VSS[6]

AB14

VSS[7]

AB39

VSS[8]

AB4

VSS[9]

AB43

VSS[10]

AB5

VSS[11]

AB7

VSS[12]

AC19

VSS[13]

AC2

VSS[14]

AC21

VSS[15]

AC24

VSS[16]

AC33

VSS[17]

AC34

VSS[18]

AC48

AG19 AG31

AG48

AD10 AD11 AD12 AD13 AD19 AD24 AD26 AD27 AD33 AD34 AD36 AD37 AD38 AD39

AD40 AD42 AD43 AD45 AD46

AF10 AF12 AD14 AD16 AF16 AF19 AF24 AF26 AF27 AF29 AF31 AF38

AF42 AF46

AH11 AH36

AH39 AH40 AH42 AH46

AJ19 AJ21 AJ24 AJ33 AJ34 AK12

AD4

AD8 AE2 AE3

AF4

AF5 AF7 AF8

AG2

AH3

AH7

AK3

VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79]

Panther Point_R1P0

C C

B B

A A

5

VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98]

VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158]

AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28

4

AY42 AY46

BB12 BB16 BB20 BB22 BB24 BB28 BB30 BB38

BB46 BC14 BC18

BC22 BC26 BC32 BC34 BC36 BC40 BC42 BC48 BD46

BE22 BE26 BE40 BF10 BF12 BF16 BF20 BF22 BF24 BF26 BF28

BF30 BF38 BF40

BG17 BG21 BG33 BG44

BH11 BH15 BH17 BH19

BH27 BH31 BH33 BH35 BH39 BH43

AY8

B11 B15 B19 B23 B27 B31 B35 B39

B7

F45

BB4

BC2

BD5

BD3

BF8

BG8

H10

BH7

D3 D12 D16 D18 D22 D24 D26 D30 D32 D34 D38 D42

D8

E18

E26 G18 G20 G26 G28 G36 G48 H12 H18 H22 H24 H26 H30 H32 H34

F3

VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249] VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258]

Panther Point_R1P0

3

VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[328] VSS[329] VSS[330] VSS[331] VSS[333] VSS[334] VSS[335] VSS[337] VSS[338] VSS[340] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352]

H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

Date: Sheet of

Monday, April 09, 2012

Date: Sheet of

Monday, April 09, 2012

Date: Sheet of

2

Monday, April 09, 2012

PROJECT :

Panther Point 6/6

Z09

1

12 40

3A

5

DDR3 DIMM-A

M_A_A[15:0]<4>

D D

M_A_BS#0<4> M_A_BS#1<4> M_A_BS#2<4> M_A_CS#0<4> M_A_CS#1<4> M_A_CLK0<4> M_A_CLK0#<4> M_A_CLK1<4> M_A_CLK1#<4> M_A_CKE0<4> M_A_CKE1<4> M_A_CAS#<4> M_A_RAS#<4>

R238 10K_4

C C

R239 10K_4

B B

M_A_WE#<4>

CLK_SCLK<9,14,19>

CLK_SDATA<9,14,19>

M_A_ODT0<4> M_A_ODT1<4>

M_A_DQSP[7:0]<4>

M_A_DQSN[7:0]<4>

Place these Caps near So-Dimm0.

+1.5VSUS

C720

C717

C638 10u/6.3V_6

A A

+3V

C731

2.2u/6.3V_6

10u/6.3V_6

C736 .1u/16V_4

+0.75V_DDR_VTT

5

10u/6.3V_6

C323 1U/6.3V_4

C719 .1u/16V_4

M_A_DQSP0 M_A_DQSP1 M_A_DQSP2 M_A_DQSP3 M_A_DQSP4 M_A_DQSP5 M_A_DQSP6 M_A_DQSP7 M_A_DQSN0 M_A_DQSN1 M_A_DQSN2 M_A_DQSN3 M_A_DQSN4 M_A_DQSN5 M_A_DQSN6 M_A_DQSN7

C324 1U/6.3V_4

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

DIMM1_SA0 DIMM1_SA1 CLK_SCLK CLK_SDATA

C248 .1u/16V_4

C312 1U/6.3V_4

107

119

109 108

114 121 101 103 102 104

115 110 113 197 201 202 200

116 120

136 153 170 187

137 154 171 188

135 152 169 186

C243 .1u/16V_4

4

JDIM1A

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9 A10/AP

84

A11

83

A12/BC# A13

80

A14

78

A15 BA0

BA1

79

BA2 S0# S1# CK0 CK0# CK1 CK1#

73

CKE0

74

CKE1 CAS# RAS# WE# SA0 SA1 SCL SDA

ODT0 ODT1

11

DM0

28

DM1

46

DM2

63

DM3 DM4 DM5 DM6 DM7

PC2100 DDR3 SDRAM SO-DIMM

12

DQS0

29

DQS1

47

DQS2

64

DQS3 DQS4 DQS5 DQS6 DQS7

10

DQS#0

27

DQS#1

45

DQS#2

62

DQS#3 DQS#4 DQS#5 DQS#6 DQS#7

DDR3-DIMM1_H=5.2_Reverse

C640 .1u/16V_4

C317 1U/6.3V_4

4

(204P)

C643 .1u/16V_4

C318 *10u/6.3V_6

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9

5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194

C267

+

*150u/6.3V_3528

M_A_DQ5 M_A_DQ1 M_A_DQ6 M_A_DQ7 M_A_DQ4 M_A_DQ0 M_A_DQ3 M_A_DQ2 M_A_DQ13 M_A_DQ8 M_A_DQ14 M_A_DQ15 M_A_DQ12 M_A_DQ9 M_A_DQ11 M_A_DQ10 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ19 M_A_DQ16 M_A_DQ17 M_A_DQ23 M_A_DQ18 M_A_DQ29 M_A_DQ28 M_A_DQ30 M_A_DQ25 M_A_DQ27 M_A_DQ24 M_A_DQ26 M_A_DQ31 M_A_DQ33 M_A_DQ32 M_A_DQ39 M_A_DQ38 M_A_DQ36 M_A_DQ37 M_A_DQ35 M_A_DQ34 M_A_DQ41 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ40 M_A_DQ44 M_A_DQ42 M_A_DQ43 M_A_DQ48 M_A_DQ52 M_A_DQ50 M_A_DQ55 M_A_DQ53 M_A_DQ49 M_A_DQ54 M_A_DQ51 M_A_DQ57 M_A_DQ60 M_A_DQ63 M_A_DQ58 M_A_DQ56 M_A_DQ61 M_A_DQ62 M_A_DQ59

3

M_A_DQ[63:0] <4>

SMDDR_VREF_DQ0_M3<6>

+SMDDR_VREF

M1 solution

SMDDR_VREF_DQ0_M3

CRV add

DEEPS3_EC<4,14>

CHA0 CHA1 CHB0 CHB1

3

R559 *M3@0_6

+SMDDR_VREF_DIMM_A

1

SA0SA1 00

1100 1 1

+3V

DDR3_DRAMRST#<4,14>

R558 *0_6

Q36

2

*AP2302GN

2

+1.5VSUS

2.48A

TP22

+SMDDR_VREF_DQ0

+1.5VSUS +1.5VSUS

20110817 change to 1K/F_4 20110817 change to 1K/F_4

R556 1K/F_4

+SMDDR_VREF_DQ0 +SMDDR_VREF_DIMM_A

3

R546 1K/F_4

C600

C602

.1u/16V_4

2.2u/6.3V_6

2

JDIM1B

75

VDD1

76

VDD2

81

VDD3

82

VDD4

87

VDD5

88

VDD6

93

VDD7

94

VDD8

99

VDD9

100

VDD10

105

VDD11

106

VDD12

111

VDD13

112

VDD14

117

VDD15

118

VDD16

123

VDD17

124

VDD18

199

VDDSPD

77

NC1

122

NC2

125

NCTEST

198

EVENT#

30

RESET#

1

VREF_DQ

126

VREF_CA

2

VSS1

3

VSS2

8

VSS3

9

VSS4

13

VSS5

14

VSS6

19

VSS7

20

VSS8

25

VSS9

26

VSS10

31

VSS11

32

VSS12

37

VSS13

38

VSS14

43

VSS15

DDR3-DIMM1_H=5.2_Reverse

C601 470p/X7R_4

Size Document Number Rev

Date: Sheet of

VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52

(204P)

PC2100 DDR3 SDRAM SO-DIMM

VTT1 VTT2

GND GND

R607 *0_6

+SMDDR_VREF_DIMM_A+SMDDR_VREF_DQ0

C721 .1u/16V_4

DDRIII SO-DIMM-0

1

44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196

203 204

205 206

R601 1K/F_4

R600 1K/F_4

C722

2.2u/6.3V_6

Quanta Computer Inc.

PROJECT :

C723 470p/X7R_4

Z09

1

13

+0.75V_DDR_VTT

13 40Monday, April 09, 2012

3A

1

M_B_DQSP[7:0]<4>

<DDR>

M_B_DQSN[7:0]<4>

M_B_DQ[63:0]<4>

+SMDDR_VREF_DIMM +SMDDR_VREF_DIMM

SMDDR_VREF_DQ1_M3<6>

A A

SO-DIMMB SPD Address is 0XA4 SO-DIMMB TS Address is 0X34

B B

M_B_CLK0

M_B_CLK0#

C C

Place these Caps near Memory Down

+1.5VSUS

C196

C198

1u/6.3V_4

+1.5VSUS

C223

C229

1u/6.3V_4

+1.5VSUS

C276

C271

D D

1u/6.3V_4

+1.5VSUS

C304

C303

1u/6.3V_4

R587 *M3@0_6

M_B_A[15:0]<4>

M_B_BS#0<4> M_B_BS#1<4> M_B_BS#2<4>

M_B_CLK0<4>

M_B_CLK0#< 4>

M_B_CKE0<4>

M_B_ODT0<4> M_B_CS#0<4> M_B_RAS#<4> M_B_CAS#<4>

M_B_WE#<4>

DDR3_DRAMRST#<4,13>

Should be 240 Ohms +-1%

C301

1.6P/50V_4

R543

R544

30/F_4

C593

0.1u/10V_4

C194

C188

C191

1u/6.3V_4

C220

C222

C227

1u/6.3V_4

1u/6.3V_4 C210

1u/6.3V_4

C274

C270

C275

1u/6.3V_4

1u/6.3V_4 C254

1u/6.3V_4

C309

C306

C308

1u/6.3V_4

1

SMDDR_VREF_DQ1

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_DQSP0 M_B_DQSP1

M_B_DQSN0 M_B_DQSN1

R185 240/F_4

1 2

C187 1u/6.3V_4

C221 1u/6.3V_4

C268 1u/6.3V_4

C307 1u/6.3V_4

C189 1u/6.3V_4

C226 1u/6.3V_4

C269 1u/6.3V_4

C302 1u/6.3V_4

M8 H1

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7

M2 N8 M3

J7 K7 K9

K1 L2 J3 K3 L3

F3 C7

E7 D3

G3 B7

T2 L8

J1 L1 J9 L9

2

U30

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15

BA0 BA1 BA2

CK CK CKE

ODT CS RAS CAS WE

DQSL DQSU

DML DMU

DQSL DQSU

RESET ZQ

NC#J1 NC#L1 NC#J9 NC#L9

RAM _DDR3

C195 1u/6.3V_4

C228 1u/6.3V_4

C273 1u/6.3V_4

C305 1u/6.3V_4

2

100-BALL SDRAM DDR3

VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9

VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9

+1.5VSUS

VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9

VSS#A9 VSS#B3 VSS#E1 VSS#G8

VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9

VSS#J2 VSS#J8

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

C167 1u/6.3V_4

C206 1u/6.3V_4

C255 1u/6.3V_4

C300 1u/6.3V_4

BYTE0_0-7 BYTE1_8-15

E3

M_B_DQ3

F7

M_B_DQ2

F2

M_B_DQ7

F8

M_B_DQ6

H3

M_B_DQ5

H8

M_B_DQ4

G2

M_B_DQ1

H7

M_B_DQ0

D7

M_B_DQ12

C3

M_B_DQ15

C8

M_B_DQ13

C2

M_B_DQ14

A7

M_B_DQ10

A2

M_B_DQ9

B8

M_B_DQ11

A3

M_B_DQ8

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

C171 1u/6.3V_4

C207 1u/6.3V_4

C263 1u/6.3V_4

C294 1u/6.3V_4

+1.5VSUS

Should be 240 Ohms +-1%

C165 1u/6.3V_4

C216 1u/6.3V_4

C260 1u/6.3V_4

C291 1u/6.3V_4

C173 1u/6.3V_4

C212 1u/6.3V_4

C259 1u/6.3V_4

C289 1u/6.3V_4

3

SMDDR_VREF_DQ1

DDR3_DRAMRST#

1 2

C174 1u/6.3V_4

C214 1u/6.3V_4

C261 1u/6.3V_4

C295 1u/6.3V_4

3

M_B_ZQ2M_B_ZQ1

R198 240/F_4

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_BS#0 M_B_BS#1 M_B_BS#2

M_B_CLK0 M_B_CLK0# M_B_CKE0

M_B_ODT0 M_B_CS#0 M_B_RAS# M_B_CAS# M_B_WE#

M_B_DQSP2 M_B_DQSP3

M_B_DQSN2 M_B_DQSN3

C179 1u/6.3V_4

C208 1u/6.3V_4

C257 1u/6.3V_4

C297 1u/6.3V_4

4

BYTE2_16-23

100-BALL SDRAM DDR3

VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9

VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9

VSS#A9 VSS#B3 VSS#E1 VSS#G8

VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9

VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8

VSSQ#F9 VSSQ#G1 VSSQ#G9

C166 1u/6.3V_4

C213 1u/6.3V_4

C265 1u/6.3V_4

C298 1u/6.3V_4

VSS#J2 VSS#J8

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

BYTE3_24-31

E3

M_B_DQ23

F7

M_B_DQ18

F2

M_B_DQ19

F8

M_B_DQ22

H3

M_B_DQ21

H8

M_B_DQ16

G2

M_B_DQ20

H7

M_B_DQ17

D7

M_B_DQ31

C3

M_B_DQ28

C8

M_B_DQ30

C2

M_B_DQ25

A7

M_B_DQ27

A2

M_B_DQ29

B8

M_B_DQ26

A3

M_B_DQ24

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

+1.5VSUS

C193 10u/6.3V_6

+1.5VSUS

10u/6.3V_6

+1.5VSUS

10u/6.3V_6

+1.5VSUS

C299 10u/6.3V_6

4

+1.5VSUS

C199 10u/6.3V_6

C205 10u/6.3V_6

C264 10u/6.3V_6

C286 10u/6.3V_6

C168 10u/6.3V_6

C217 10u/6.3V_6

C266 10u/6.3V_6

C288 10u/6.3V_6

Should be 240 Ohms +-1%

U31

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

RAM _DDR3

C172 1u/6.3V_4

C218 1u/6.3V_4

C256 1u/6.3V_4

C290 1u/6.3V_4

C170 10u/6.3V_6

C224 10u/6.3V_6

C272 10u/6.3V_6

C287 10u/6.3V_6

5

+SMDDR_VREF_DIMM SMDDR_VREF_DQ1

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_BS#0 M_B_BS#1 M_B_BS#2

M_B_CLK0 M_B_CLK0# M_B_CKE0

M_B_ODT0 M_B_CS#0 M_B_RAS# M_B_CAS# M_B_WE#

M_B_DQSP4 M_B_DQSP5

M_B_DQSN4 M_B_DQSN5

DDR3_DRAMRST#

M_B_ZQ3

R216 240/F_4

1 2

C176 10u/6.3V_6

C230 10u/6.3V_6

C277 10u/6.3V_6

C310 10u/6.3V_6

5

BYTE4_32-39 BYTE5_40-47

U32

M8 H1

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3

L7 R7 N7 T3 T7 M7

M2 N8 M3

J7 K7 K9

K1

L2

J3 K3

L3

F3 C7

E7 D3

G3 B7

T2

L8

J1

L1

J9

L9

C679

+

*150u/6.3V_3528

E3

M_B_DQ38

DQL0

VREFCA

F7

M_B_DQ35

DQL1

VREFDQ

F2

M_B_DQ34

DQL2

F8

M_B_DQ39

DQL3

A0

H3

M_B_DQ33

DQL4

A1

H8

A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15

BA0 BA1 BA2

CK CK CKE

ODT CS RAS CAS WE

DQSL DQSU

DML DMU

DQSL DQSU

RESET ZQ

NC#J1 NC#L1 NC#J9 NC#L9

RAM _DDR3

100-BALL SDRAM DDR3

+SMDDR_VREF_DIMM

M_B_DQ37

DQL5

G2

M_B_DQ32

DQL6

H7

M_B_DQ36

DQL7

D7

M_B_DQ42

DQU0

C3

M_B_DQ44

DQU1

C8

M_B_DQ47

DQU2

C2

M_B_DQ45

DQU3

A7

M_B_DQ46

DQU4

A2

M_B_DQ41

DQU5

B8

M_B_DQ43

DQU6

A3

M_B_DQ40

VDD#G7

VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9

VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8 VSSQ#F9 VSSQ#G1 VSSQ#G9

+1.5VSUS

VDD#B2 VDD#D9

VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9

VSS#A9 VSS#B3 VSS#E1 VSS#G8 VSS#J2 VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9 VSS#T1 VSS#T9

DQU7

C175

0.1u/10V_4

R200 1K/F_4

R199 1K/F_4

+1.5VSUS

B2

D9

G7

K2

K8

N1

N9

R1

R9

+1.5VSUS

A1

A8

C1

C9

D2

E9

F1

H2

H9

A9

B3

E1

G8

J2

J8

M1

M9

P1

P9

T1

T9

B1

B9

D1

D8

E2

E8

F9

G1

G9

C262

C296

0.1u/10V_4

+SMDDR_VREF_DIMM

+SMDDR_VREF_DIMM SMDDR_VREF_DQ1SMDDR_VREF_DQ1_M3

R201 *0_6

C211

0.1u/10V_4

CLK_SCLK<9,13,19> CLK_SDATA<9,13,19>

6

+SMDDR_VREF_DIMM

Should be 240 Ohms +-1%

C258

C169

0.1u/10V_4

+SMDDR_VREF

REV:B Add

201201118 Unstuff U34 and C732

U34

6

CLK_SCLK

SCL

5

CLK_SDATA

SDA

7

WP

*M24C02-WMN6TP

address:A2

WP =1 : WRITE DISABLE

6

SMDDR_VREF_DQ1

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_BS#0 M_B_BS#1 M_B_BS#2

M_B_CLK0 M_B_CLK0# M_B_CKE0

M_B_ODT0 M_B_CS#0 M_B_RAS# M_B_CAS# M_B_WE#

M_B_DQSP6 M_B_DQSP7

M_B_DQSN6 M_B_DQSN7

DDR3_DRAMRST#

M_B_ZQ4

R235 240/F_4

1 2

C293

0.1u/10V_4

DEEPS3_EC<4,13>

A0 A1 A2

VCC

GND

7

BYTE6_48-55

U35

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

RAM _DDR3

C209

0.1u/10V_4

+3V

1 2 3

8 4

BYTE7_56-63

E3

M_B_DQ54

DQL0

F7

M_B_DQ50

DQL1

F2

M_B_DQ55

DQL2

F8

M_B_DQ51

DQL3

H3

M_B_DQ49

DQL4

H8

M_B_DQ48

DQL5

G2

M_B_DQ53

DQL6

H7

M_B_DQ52

DQL7

D7

M_B_DQ59

DQU0

C3

M_B_DQ61

DQU1

C8

M_B_DQ62

DQU2

C2

M_B_DQ57

DQU3

A7

M_B_DQ58

DQU4

A2

M_B_DQ56

DQU5

B8

M_B_DQ63

DQU6

A3

M_B_DQ60

100-BALL SDRAM DDR3

SMDDR_VREF_DQ1

DQU7

VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9

VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9

VSS#A9 VSS#B3 VSS#E1

VSS#G8

VSS#J2

VSS#J8 VSS#M1 VSS#M9

VSS#P1

VSS#P9

VSS#T1

VSS#T9

VSSQ#B1

VSSQ#B9 VSSQ#D1 VSSQ#D8

VSSQ#E2

VSSQ#E8

VSSQ#F9 VSSQ#G1 VSSQ#G9

C202

0.1u/10V_4

change to 1K/F_4

Q40 *AP2302GN

+1.5VSUS

B2 D9 G7 K2 K8 N1 N9 R1 R9

+1.5VSUS

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

SMDDR_VREF_DQ1+SMDDR_VREF_DIMM

C233

C203

0.1u/10V_4

+1.5VSUS

321

4/27 add

C732 *0.1u/10V_4

Size Document Number Rev

Date: Sheet of

Monday, April 09, 2012

Date: Sheet of

Monday, April 09, 2012

Date: Sheet of

7

Monday, April 09, 2012

R585 1K/F_4

R584 1K/F_4

8

C314

C313

C280

0.1u/10V_4

R586 *0_6

C234

0.1u/10V_4

Quanta Computer Inc.

PROJECT :

Z09

PROJECT :

Z09

PROJECT :

Z09

DDR3 MEMOR Y DOWN

8

14

C279

0.1u/10V_4

+SMDDR_VREF

14 40

3A

Lid Switch (Hall sensor)

D D

5

+3VPCU

D2 *5.5V/25 V/410P_4

1 2

0.1u/10V_4_X7 RC9

1

3

HE1

EM-6781-T3

25mil

2

25mil

1 2

R19 *100K_4

LID#

D4 *5.5V/25V/410P_ 4

eDP

PT3661-BB : AL003661003

EDP_AUX<2>

EDP_AUX#<2>

EDP_TX0<2 > EDP_TX0#<2>

INT_LVDS_DIGON<7> INT_LVDS_BLON<7>

INT_LVDS_BRIGHT<7>

R52 *10 0K_4 R61 *10 0K_4

CONTRAST<24 >

4

7/28 modify

R32 *0_4

R25 0_4

EDP_AUX_C EDP_AUX#_C

EDP_AUX# EDP_TX0 EDP_TX0#

INT_LVDS_DIGON INT_LVDS_BLON

R45 *10 0K_4 R65 *10 0K_4

C33 0. 1U/10V_4 C34 0. 1U/10V_4 C42 0. 1U/10V_4 C41 0. 1U/10V_4

LVDS_BRIGHT

3

EDP_AUX_CEDP_AUX

EDP_AUX#_C

EDP_TX0_C

EDP_TX0#_C

+3V

2

1

C C

Penal SPEC: Iout:78~79.5mA Vout:32~34V

LED Driver-IC

VIN

20120222 del 0 ohm R299.

LVDS_BRIGHT LVDS_BRIGHT_R

20111024 If phas shift PWM mode replace R65 to 10K.

C369

2.2U/25V_6

B B

A A

C20 1u/6.3V_4

BL_ON

R21 1. 2K_4

R23 620 K/F_4

R26 45 .3K_4

R33 *10K_4

+3V

20111024 Reserve if Host need to know any fault trigger on backlight driver

VIN

C393

4.7u/25V_8

20111122 change to 10u 1A inductor for FAE suggest. 20111121 change to 10u 0.1A indecator.

R20 10K_4

23

30

PAD

1

VDDIO

2

EN

3

FSLCT

4

ISET

5

FPO

27

20111013 Creat e LED D-IC

VOUT

C397 1000p/50V_4

20111024 Bypass CAP for FAE request. 20120116 change Bypass CAP to 50V.

5

22

PAD

C406 *0.1u/50V_8

40V, 2A, 1mm(m ax)

L22

10uH_1A

20

21

19

PAD

PWM

TPS61187

IFB66IFB4

PAD29PAD28PAD

7

DFLS240-7-F

2 1

17

18

16

U22

NC

SW

VIN

PAD

FAULT

PAD GNDP PGND

OVC

RFPWM/MODE

IFB1

IFB2 IFB3

GND9IFB5

8

10

FB3

R67 Select is from 210Hz~20 KHz,866K~9.09K .

VDDIO MODE

R22 *0_ 4

Close to Pin1

20111024 Reserve Phase shift PWM mode cirucit, if R67 high impedance, bypassing capacitor is for improves noise sensitivit and not exceed 33pf.

D9

20120111 Change C407 to 4.7uf 50V 1206 size.

C407

4.7u/50V_1206

24 25 26 15 14 13 12 11

20111111 change to R423 to 56K.

MODE

FB1 FB2

Vovc=[Rupper/R dowm+1]*Vov_th (Rupper=1M,Vov _th=1.95V)

R

FLCT

833K

625K

499K

20120111 Un-stuff C410 for LCD flacking issue, FAE suggestion.

C410

R341

*0.033u/16V_4_ X7R

9.09K_4

4

R324 1M_4

R334 56K_4

F

600KHz

800KHz

1MHz

VOUT

SW

LCD CONNECTOR

CCD +3V-curren t budget 0.2A

LCDVCC

VOUT

CCD_PWR

+3V

C26

0.1u/10V_4_X7 R

0.8A

+3V

R34 *SHORT_6

CCD-USB

EDP_HPD<2>

USBP8+<9> USBP8-<9 >

C22

1000p/50V_4

FB1 FB2 FB3

USBP8-_R USBP8+_R

EDP_HPD

EDP_AUX_C EDP_AUX#_C

EDP_TX0_C EDP_TX0#_C

R41 *SHORT_4

R36 *SHORT_4

3

LCD Power

+3V

C17

1U/6.3V_4

INT_LVDS_DIGON

20120221 add CN7 pin33/34 to GND.20120222 del 0 ohm R315.

LVDS

30

29

34

29

34

28

27

33

27

33

26

25

32

25

32

24

23

31

23

31

22

21 20 19 18 17 16 15 14 13 12 11 10

USBP8+_R USBP8-_R

21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

CN7

Backlight Control

U2

6

IN

4

IN

3

ON/OFF

AAT4280-4

R24

100K_4

INT_LVDS_BLON

R284 100K_4

20111117 change mose footprint to dual type.

2

1

OUT

2

GND

20111118 Remove C21/C12.

5

GND

+3VPCU

+3V

R314

R296

10K_4

BL#

6

215

4 3

BL_ON

Q16 2N7002DW

2

Q17 DTC144EUA

1 3

Size Document Number Rev

Date: Sheet o f

C25

0.1u/10V_4

R275 *100K_4

LID#,EC intrnal PU

D8 BAS316

2 1

Quanta Computer Inc.

PROJECT :

LVDS/CAMERA/LID

LCDVCC

C21

C29

.01u/25V_4

2.2U/6.3V_6

LID#

LID# <24>

EC_FPBACK# <24>

Z09

15 40Monday, April 09, 201 2

1

3A

5

HDMI

D D

from PCH

INT_HDMITX0N_C<7> INT_HDMITX0P_C<7>

INT_HDMITX2N_C<7> INT_HDMITX2P_C<7>

INT_HDMITX1N_C<7> INT_HDMITX1P_C<7>

INT_HDMICLK-_C<7> INT_HDMICLK+_C<7>

C354 0.1u/10V_4 C353 0.1u/10V_4

C350 0.1u/10V_4 C349 0.1u/10V_4

C352 0.1u/10V_4 C351 0.1u/10V_4

C356 0.1u/10V_4 C355 0.1u/10V_4

20111118 change R747 to 100K.

+3V

R294

*100K/F_4

4

R1

R8

R7

680_4

3

Q1

2

2N7002D

1

680_4

R2 680_4

R3 680_4

R4 680_4

3

INT_HDMITX0N INT_HDMITX0P

INT_HDMITX2N INT_HDMITX2P

INT_HDMITX1N INT_HDMITX1P

INT_HDMICLKINT_HDMICLK+

R6

R5

680_4

2

1

I2C

C C

R292 *10K_4

+3V

R310 10K_4

+3V

R266 10K_4

5

4 3

Q10 2N7002DW

1

20111117 change mose footprint to dual type.

6

2

HDMI_HP <7>

HDMI-detect

HDMI_HPD_EC#<24>

+5V

HDMI_MB_HP

B B

MOS close to connector

HDMI_DDCCLK_SW<7>

HDMI_DDCDATA_SW<7>

+3V

R288

2.2K_4

R289

2.2K_4

+3V

Q12

2

BSN20

1

+3V

Q13

2

BSN20

1

+5V

21

D6 RB501V-40

R260

3

2.2K_4

HDMI_DDCCLK_MBHDMI_DDCCLK_SW

follow CRB 1.0 change to 2.2K

+5V

21

D7 RB501V-40

R261

2.2K_4

HDMI_DDCDATA_MBHDMI_DDCDATA_SW

follow CRB 1.0 change to 2.2K

EMI

R254 *100/F_4

R253 *100/F_4

R255 *100/F_4

A A

R256 *100/F_4

INT_HDMITX2P

D1

SSM22LLPT

HDMI_MB_HP

INT_HDMITX2P INT_HDMITX2N

INT_HDMITX1P INT_HDMITX1N

INT_HDMITX0P INT_HDMITX0N

INT_HDMICLK+ INT_HDMICLK-

HDMI_DDCCLK_MB HDMI_DDCDATA_MB

HDMI_5V

R263 *SHORT_4

R262 20K_4

20110919 change to 20k.

INT_HDMITX2N INT_HDMITX1P

INT_HDMITX1N INT_HDMITX0P

INT_HDMITX0N INT_HDMICLK+

INT_HDMICLK-

5

+5V

F1 KMC3S110RY

4

12

C1 470p/X7R_4

HDMI_5V_R

HDMI connector

HP_DET_CN

3

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19

CN1

D2+ D2 Shield D2D1+ D1 Shield D1D0+ D0 Shield D0CK+ CK Shield CKCE Remote NC DDC CLK DDC DATA GND +5V HP DET

HDMI

SHELL1

GND GND

SHELL2

20

23 22

21

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

Date: Sheet of

Date: Sheet

2

PROJECT :

HDMI (PS8101)

Z09

1

3A

of

16 40Monday, April 09, 2012

5

Giga-LAN BCM57780

+3V_LAN

20110214 Add C 622 and C621 f or power noise.

D D

C C

20120201 Change CAP from 27P to 15P.

15p/50V_4C334

Y3

25MHz-LAN

15p/50V_4C336

B B

VAUX_12

R248 200_4

2 4

1 3

L21

BLM18AG601SN1D_6

L16

BLM18AG601SN1D_6

L14

BLM18AG601SN1D_6

PCIE_RX3+<9> PCIE_RX3-<9> PCIE_TX3+<9> PCIE_TX3-<9>

PCIE_LAN_WAKE#<7>

PLTRST#<9,19,20,24,25> CLK_PCIE_LOM<9> CLK_PCIE_LOM#<9>

XTALO

XTALI

+3V

VAUX_12

15mil

4.7U/6.3V_6C370

0.1u/10V_4_X7RC347

4.7U/6.3V_6C622

15mil

4.7U/6.3V_6C343

0.1u/10V_4_X7RC342

15mil

4.7U/6.3V_6C335

0.1u/10V_4_X7RC341

C340 0.1u/10V_4_X7R C339 0.1u/10V_4_X7R

PCIE_LAN_WAKE#

R286 1K/F_4 R267 4.7K_4

R250 1.24K/F_4

R264 4.7K_4

+3V_LAN

BCM_CLKREQ#

AVDDL

GPHY_PLLVDD

PCIE_PLLVDD

PCIE_RX3+_R PCIE_RX3-_R

VMA_PRES LOW_PWR

XTALO XTALI

RDAC

U10

42

VDDO

6

VDDC

15

VDDC

41

VDDC

27

AVDDL

33

AVDDL

39

AVDDL

24

GPHY_PLLVDDL

18

PCIE_PLLVDDL

21

PCIE_PLLVDDL

17

PCIE_TXDP

16

PCIE_TXDN

22

PCIE_RXDP

23

PCIE_RXDN

4

WAKE#

2

PERST#

20

PCIE_REFCLK_P

19

PCIE_REFCLK_N

40

VMAIN_PRSNT

1

LOW_PWR

13

XTALO

12

XTALI

26

RDAC

3

CLK_REQ#

4

BCM57780

7mm X 7mm 48-Pin QFN

GND

49

SPD100LED# SPD1000LED# TRAFFICLED#

BCM57780

BIASVDDH

XTALVDDH

AVDDH AVDDH

TRD3_N

TRD3_P

TRD2_N

TRD2_P

TRD1_N

TRD1_P

TRD0_N

TRD0_P

LINKLED#

MODE

EECLK

EEDATA

SR_LX

SR_VFB

SR_VDDP

SR_VDD

3

15mil

25

BIASVDD

L15 BLM18AG601SN1 D_6

0.1u/10V_4_X7RC344

14

XTALVDD

L13 BLM18AG601SN1 D_6

0.1u/10V_4_X7RC337

30 36

37 38

35 34

31 32

29 28

48 47 46 45

5

44 43

11 8

10 9

7

NC

L20 BLM18AG601SN1 D_6

AVDDH

LAN_TRD3N <18> LAN_TRD3P <18>

LAN_TRD2N <18> LAN_TRD2P <18>

LAN_TRD1N <18> LAN_TRD1P <18>

LAN_TRD0N <18> LAN_TRD0P <18>

LAN_LINKLED#

LAN_ACTLED#

BCM_EEC BCM_EED

C387

C348

0.1u/10V_4_X7R

4.7U/6.3V_6

2111201 change C6108 power from +3V_S5 to +3V_LAN.

0.1u/10V_4_X7RC365

0.1u/10V_4_X7RC357

4.7U/6.3V_6C621

L17 4.7uh

+3V_LAN

LAN_LINKLED# <18>

LAN_ACTLED# <18>

VAUX_12

Don't route under Choke.

C372

C345

10u/6.3V_6

0.1u/10V_4_X7R

2

1

31

LAN POWER

20111122 Remove Q44 and change plant to +3V_S5.

+3V_LAN

R291 2.2/F_6

+3V_S5

A A

5

VAUX_12

20mil

0.1u/10V_4_X7RC 338

4.7U/6.3V_6C373

0.1u/10V_4_X7RC362

4.7U/6.3V_6C374

0.1u/10V_4_X7RC358

0.1u/10V_4_X7RC359

4

EEPROM

+3V_LAN

BCM_EED BCM_EEC

EEPROM Strapping

EEPROM Type

24LC02

Internal

REV:B 6/11

R326

R306

*1K_4

1K_4

R327

R307 *1K_4

1K_4

EECLK EEDATA

1 1

1 0

3

5 6

7 4

U21

SDA SCL

WP GND

*AT24C02

WAKE_SRC_2<24>

1

A0

2

A1

3

A2

8

+3V_S5

VCC

C385

0.1u/10V_4_X7R

CLK_PCIE_LAN_REQ#<9>

2

+3V_LAN

2

Q18

R303

*DTC144EUA

*4.7K_4

13

R298 0_4

+3V_LAN

S5 IOAC

2

3

1

Q8 2N7002K

R251 *0_4

Size Document Number Rev

Date: Sheet of

Monday, April 09, 2012

Date: Sheet of

Monday, April 09, 2012

Date: Sheet of

Monday, April 09, 2012

PCIE_LAN_WAKE#

20120305 Stuff R298.

BCM_CLKREQ#

Quanta Computer Inc.

PROJECT :

GLAN BCM57780

1

Z09

17 40

3A

1

2

3

4

5

6

7

8

TRANSFORMER

U11

LAN_TRD3P<17> LAN_TRD3N<17>

A A

B B

C13

0.1u/10V_4_X7R

C10

0.1u/10V_4_X7R

C12

0.1u/10V_4_X7R

C11

0.1u/10V_4_X7R

LAN_TRD2N<17> LAN_TRD2P<17>

LAN_TRD1P<17> LAN_TRD1N<17>

LAN_TRD0N<17> LAN_TRD0P<17>

LAN_TRD3P LAN_TRD3N

LAN_TRD2N LAN_TRD2P

LAN_TRD1P X-TX1P LAN_TRD1N

LAN_TRD0N LAN_TRD0P

2011/08/31 Change to small size DB0KL3LAN0

20111121 change from dual to single transformer.

1 2 3

4 5 6

7 8 9

10 11 12

TD1+ TD1TCT1

TCT2 TD2+ TD2-

TD3+ TD3TCT3

TCT4 TD4+ TD4-

NS692417

MX1+ MX1MCT1

MCT2 MX2+

MX3+

MCT3

MCT4 MX4+

MX2-

MX3-

MX4-

24 23 22

21 20 19

18 17 16

15 14 13

R9

R13

75/F_8

R12 75/F_8

R11 75/F_8

X-TX3P X-TX3N

X-TX2N X-TX2P

X-TX1N

X-TX0N X-TX0P

C6 1500p/3KV_18

CN2

X-TX0P X-TX0N X-TX1P X-TX2P X-TX2N X-TX1N X-TX3P X-TX3N

9

10

1 2 3 4 5 6 7 8

11 12

YELLOW_N YELLOW_P

0+ 01+ 2+ 213+ 3-

GREEN_N GREEN_P

RJ45

3

GND4 GND3 GND2 GND1

16 15 14 13

R257 *0_6

4

C368 *0.1u//50V_8

2

LAN_ACTLED# LAN_ACT_LED_PWR

LAN_LINKLED# LAN_LNK_LED_PWR

LAN_ACTLED# LAN_LINKLED#

C16

*0.1u//50V_8

LAN_ACTLED#<17>

C C

LAN_LINKLED#<17>

D D

1

+3V_S5

R18 220_8

R14 220_8

For EMI

LAN_TRD3P LAN_TRD3N LAN_TRD2N LAN_TRD2P

1

2

3

3 445

*UCLAMP2512T.TCT

1

2

3

3 445

*UCLAMP2512T.TCT

Size Document Number Rev

Date: Sheet of

6

LAN_TRD1P LAN_TRD1N LAN_TRD0N LAN_TRD0P

5

D3

*P640P3100SBRP

1 2

U18

8

LAN_TRD1P

8

7

LAN_TRD1N

7

6

LAN_TRD0N

6

5

LAN_TRD0P

U17

8

7

6

5

LAN Transformer and RJ45

Monday, April 09, 2012

R17 *1M_8

LAN_TRD3P LAN_TRD3N LAN_TRD2N LAN_TRD2P

Quanta Computer Inc.

PROJECT :

7

Z09

18 40

3A

8

5

LED/Card reader/Touchpad B CON

+5V +3V

L10 0_6

D D

C C

L9 *0_6

+5V

+3V

R2430_4 R245*0_4

R244 10K_4

TPCLK<24>

TPDATA<24>

+TPVDD

C322

0.1u/10V_4_X7R

20111128 change net name to SMBALERT#

*.01u/25V_4

SMBALERT#<9>

C327

R246 10K_4

L11 0_6 L12 0_6

TPCLK_R

TPDATA_R

C329 *.01u/25V_4

CPU FAN

+3V

R553 1K_4

2

B B

CPUFAN#<24>

1 3

Q37 MMBT3904

+5V

R561 10K_4

FANSIG<24>

FAN_PWM_CN

30mil

4

+3V

2

3

Q45

*2N7002K

20120302 Add net BOARD_ID 4.

+5V

+3V

R552 10K_4

1

R551 *SHORT_8

+3VPCU

+3V_S5

+3V

CLK_SDATA<9,13,14>

CLK_SCLK<9,13,14>

CLK_PCIE_MMC<9>

TP_INT#_D

CN10

345 2 1

CLK_PCIE_MMC#<9>

PCIE_CLKREQ0#<9>

KEY_BL_EN<24>

BOARD_ID4<9,10>

20111122 change pin29/30 for Touch pad use.

6

FAN

3

C328

C326

*0.1U/10V_4

+TPVDD

TPCLK_R

TPDATA_R

R236*0_4

PCIE_TX2+<9> PCIE_TX2-<9>

PCIE_RX2+<9> PCIE_RX2-<9>

PLTRST#<9,17,20,24,25>

PWRLED#<24> SUSLED#<24> BATLED1#<24> BATLED0#<24> NBSWON#<24>

R237*0_4

TP_INT#_D

Audio Connector

C321 *0.1U/10V_4

CN13

1 2 3 4 5 6 7 8 9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 293031

CON30P

20111114 Change con

L6, C6495

󵙉󵙉󵙉󵙉󲒇󲒇󲒇󲒇󱙱󱙱󱙱󱙱

32

PCH_AZ_CODEC_SYNC<8>

PCH_AZ_CODEC_SDIN0<8> PCH_AZ_CODEC_SDOUT<8> PCH_AZ_CODEC_BITCLK<8>

PCH_AZ_CODEC_RST#<8>

Top layer

2

1

TPM

CN14

CLKRUN#<7,24>

SERIRQ<8,24>

LPCPD#<7> LPC_LAD0<8,20,24> LPC_LAD1<8,20,24>

LPC_LFRAME#<8,20,24>

PCLK_TPM<9> LPC_LAD2<8,20,24> LPC_LAD3<8,20,24>

PCBEEP_EC<24>

SPKR<8>

AMP_MUTE#<24>

L8 FCM1608KF-121T04 C204

22p/50V_4

󰵝󰵝󰵝󰵝󵚩󵚩󵚩󵚩󴼚󴼚󴼚󴼚

CN9

20111116 For EMI solution. 20111116 Change R256 to L6 for EMI reqeust.

R241 *0_4 R247 *0_4

R240 0_4

20111127 add R221/C6496 for EMI request.

C225 *0.1U/10V_4

+5V

+3V

PCH_AZ_CODEC_BITCLK_R

R242 0_4

PLTRST#

C325 *10p/50V_4

*0.1U/10V_4

C330

+3V_S5

+3V

SERIRQ_R

LPCPD#_R

20111201 modify pin define for BTB connector. 20111205 modify pin out define.

C219 *0.1U/10V_4

CN11

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

Audo_CON

1 2 3 4 5 6 7 8

9 10 11 12 13 14

PCLK_TPM_C

15 16

20111121 change footprint

17

18

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

TPM_CON

3/5VPCU reset switch

SW2SWITCH_1.5

2

A A

3 14

12

D5

C346

5

6

0.1u/16V_4

5

*14V/38V/100P_4

8223_EN <32>

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

mSATA/CR/LED

Monday, April 09, 2012

Date: Sheet of

Monday, April 09, 2012

Date: Sheet of

Monday, April 09, 2012

4

3

2

Date: Sheet

PROJECT :

Z09

1

of

19 40

3A

1

MINI-CARD WLAN(MPC)

+3.3V: 1000mA +3.3Vaux:330mA +1.5V:500mA

A A

B B

BT_POWERON<24>

mSATA

C C

Debug

D D

20111107 move debuge port to cn3

PLTRST#<9,17,19,24,25>

CLK_LPC_DEBUG<9>

SATA_TXP1<8>

SATA_TXN1<8>

SATA_RXN1<8> SATA_RXP1<8>

1

C378 .01u/25V_4 C379 .01u/25V_4

C380 .01u/25V_4 C381 .01u/25V_4

2

20111207 change Pin51 net name to BT_POWERON 20111107 move debuge port to cn3

R332 *SHORT_4

PCIE_TX8+<9> PCIE_TX8-<9>

PCIE_RX8+<9> PCIE_RX8-<9>

SATA_TXP1_C SATA_TXN1_C

SATA_RXN1_C SATA_RXP1_C

2

R320 *0_4 R321 *0_4 R311 *0_4

CLK_PCIE_WLAN_REQ#_R

PCIE_WAKE#_R

CN6

51

Reserved

49

Reserved

47

Reserved

45

Reserved

43

GND

41

+3.3Vaux

39

+3.3Vaux

37

GND

35

GND

33

PETp0

31

PETn0

29

GND

27

GND

25

PERp0

23

PERn0

21

GND

19

UIM_C4

17

UIM_C8

15

GND

13

REFCLK+

11

REFCLK-

9

GND

7

CLKREQ#

5

Reserved

3

Reserved

1

WAKE#

MINI-CARD1

CL_RST1#<9> CL_DATA1<9>

CL_CLK1<9>

CLK_PCIE_WLAN<9> CLK_PCIE_WLAN#<9>

R269 *0_4 R295 *0_4

3

4

Check LED signal. (active high or low)

H=7.0mm

CN5

51

Reserved

+3.3V

GND

+1.5V LED_WPAN# LED_WLAN#

LED_WWAN#

GND USB_D+ USB_D-

GND

SMB_DATA

SMB_CLK

+1.5V

GND

+3.3Vaux

PERST#

W_DISABLE#

GND

UIM_VPP

UIM_RESET

UIM_CLK

UIM_DATA

UIM_PWR

+1.5V

GND

+3.3V

GND54GND

3

49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17

15 13 11

9 7 5 3 1

MINI-CARD1

52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18

16 14 12 10 8 6 4 2

Reserved Reserved Reserved GND +3.3Vaux +3.3Vaux GND GND PETp0 PETn0 GND GND PERp0 PERn0 GND UIM_C4 UIM_C8

GND REFCLK+ REFCLKGND CLKREQ# Reserved Reserved WAKE#

53

+3V

+3V_SATA

A_LFRAME#_R A_LAD3_R A_LAD2_R A_LAD1_R A_LAD0_R

CL_RST1#_WLAN CL_DATA1_WLAN CL_CLK1_WLAN

+WL_VDD

2011017 : stuff q21 to enable wake function on WLAN for IOAC check IOAC power rail can reduce Q21

53

modify 20111102

52

+3.3V

50

GND

48

+1.5V

46

LED_WPAN#

44

LED_WLAN#

42

LED_WWAN#

40

GND

38

USB_D+

36

USB_D-

34

GND

32

SMB_DATA

30

SMB_CLK

28

+1.5V

26

GND

24

+3.3Vaux

22

PERST#

20

W_DISABLE#

18

GND

16

UIM_VPP

14

UIM_RESET

12

UIM_CLK

10

UIM_DATA

8

UIM_PWR

6

+1.5V

4

GND

2

+3.3V

GND54GND

R10 *SHORT_8

+3V_SATA

10U/10V_8

rating = 1000mA @ 128G

20111107 move debuge port to cn3

R27 0_4 R28 0_4 R29 0_4 R30 0_4 R31 0_4

4

20111107 move debuge port to cn3

C3

5

+WL_VDD +1.5V_Mini1_VDD

TP57

WLAN_CLK_SDATA WLAN_CLK_SCLK

+1.5V_Mini1_VDD +WL_VDD

RF_EN <24>

+1.5V_Mini1_VDD +WL_VDD

Close CN3

C23

0.1U/10V_4

Debug

LPC_LFRAME# <8,19,24> LPC_LAD3 <8,19,24> LPC_LAD2 <8,19,24> LPC_LAD1 <8,19,24> LPC_LAD0 <8,19,24>

5

20120217 reserve R648 PU 100k.

+3VPCU

IOAC_LANPWR#<24>

WLAN_OFF <24>

201201118 add IOAC WLAN OFF function.

USBP10+ <9> USBP10- <9>

R650 *0_4 R643 0_4 R646 *0_4

1

R648 *100K_4

BT

20120221 add R650 for PLTRST#. 20120216 add R643/R646 un-stuff for iRST reserve.

PLTRST#

IOAC_PCIERST#

leakage circuit

C24

0.1U/10V_4

20111117 change mose footprint to dual type.

PCIE_CLKREQ5#<9>

6

Q11 AO3413

2

SMB_PCH_DAT<9>

SMB_PCH_CLK<9>

WAKE_SRC_1<24>

6

7

3

20111122 change to Pmose

high

Mini card +3V power enable

low Mini card +3V power disable

R293 *SHORT_8

IOAC_PCIERST# <7,24> PCIERST# <24>

C389 10u/6.3V_6

+WL_VDD

C405

0.1u/10V_4

+1.5V_Mini1_VDD

500mA for +1.5V

C404

C367

1000p/50V_4

0.1u/10V_4

Close CN13

20120105 Change power plant for leakage issue.

+3V_S5

S5 IOAC

S5

Size Document Number Rev

Date: Sheet of

2N7002DW

4 3

1

2N7002DW

4 3

1

R258 *0_4 R259 *0_4

20111118 change mose footprint to dual type.

7

R287

4.7K_4

5

2 6

Q14

20120105 Change power plant for leakage issue.

+WL_VDD

+3V_S5

R265

4.7K_4

5

2 6

Q9

Quanta Computer Inc.

PROJECT :

MINI PCI-E card/TV

8

+WL_VDD

C361 *0.1u/10V_4

R249 *0_8

C333 10u/6.3V_6

+WL_VDD

R285

4.7K_4

WLAN_CLK_SDATA

WLAN_CLK_SCLK

R252

4.7K_4

CLK_PCIE_WLAN_REQ#_R

PCIE_WAKE#_R

Z09

20 40Monday, April 09, 2012

8

C332 *0.1u/10V_4

+1.5V

IOAC

3A

1

2

3

4

MAIN SATA HDD RE-DRIVER

A A

B B

21111207 change Cn12 Pin define following ZHA.

CN9

24

26

23

25

22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

MAIN_SATA_CONN

C C

R528 *SHORT_8

+5V

C595

+

100u/6.3V_3528

SATA_RXP0_C SATA_RXN0_C

SATA_TXN0_C SATA_TXP0_C

+5V_HDD

C592 10u/6.3V_6

C596 .01u/25V_4 C597 .01u/25V_4

C598 .01u/25V_4 C599 .01u/25V_4

1A (MAX.)

C159 *.1u/16V_4

C157 *.1u/16V_4

SATA_RXP0 <8> SATA_RXN0 <8>

SATA_TXN0 <8> SATA_TXP0 <8>

C160 .01u/25V_4

C158 .01u/25V_4

EE RETURN-PATH CAPACITORSMAIN SATA HDD

+3V

*.1u/10V_4

C311

*.1u/10V_4

C249

*.1u/10V_4

C122

+3V

*.1u/10V_4

C32

*.1u/10V_4

C102

*.1u/10V_4

C433

*.1u/10V_4

C28

C27 *470p_4

C124 *2200p/50V_4 C252 *2200p/50V_4 C331 *2200p/50V_4 C320 *2200p/50V_4

+1.5VSUS

+1.05V_VTT

+1.05V_GFX

+VGPU_CORE

VIN

*0.1u/25V_4

C315

0.1u/25V_4

C30

*0.1u/25V_4

C15

*0.1u/25V_4

C741

*0.1u/25V_4

C201

*0.1u/25V_4

C163

*0.1u/25V_4

C46

*0.1u/25V_4

C444

*0.1u/25V_4

C18

C316 *0.1u/25V_4

C319 0.1u/25V_4

C14 *0.1u/25V_4 C360 *0.1u/25V_4

C7 0.1u/25V_4

C2 *0.1u/25V_4

+3V

+5V

+1.5VSUS

+VCC_CORE

+VGPU_CORE

+3VPCU

VIN

C125 *2200p/50V_4

+1.05V_VTT

C35 *.1u/10V_4

C72 *2200p/50V_4

*220p/50V_4

C545

+1.05V_GFX

*220p/50V_4

C123

+1.05V_VTT

*220p/50V_4

C579

+1.5VSUS

*.1u/10V_4

C607

+1.05V_VTT

.1u/10V_4

C740

VIN

*.1u/10V_4

C606

+3V

.1u/10V_4

C164

+1.05V_GFX

.1u/10V_4

C765

.1u/10V_4

C197

*470p/X7R_4

C742

20111128 del C508/C704/C479/C497 and change path cap power well.

201201117 C765 for EMI suggestion. 201201119 Add C2765 for EMI suggestion to GND.

VIN

+3V

R470

100K

2N7002DW Q30

+5V

12

Q32 AO6402A

6 524

1

MOD_EN_5V

3

12

C492

0.1u/25V_6

+5V_ODD

3

2

ODD_EN_Q

Q28

DMN601K-7

1

Size Document Number Rev

Date: Sheet of

+5V

R477 *0_8

R475 22_8

Quanta Computer Inc.

PROJECT :

SATA-HDD/ODD/USB-ESATA

Z09

21 40Monday, April 09, 2012

4

21 40Monday, April 09, 2012

3A

ODD Power (SATA)

ODD (SATA)

CN8

14

GND14

1

GND

2

SATA_TXP5_C

A+

3

SATA_TXN5_C

A-

4

GND

5

SATA_RXN5

B-

6

SATA_RXP5

B+

7

GND

D D

DP

5V 5V

MD GND GND

GND15

SATA_ODD_H=7.7

8 9 10 11 12 13

15

R154 10K_4

C766 15p/50V_4

C107 .01u/25V_4

R166 10K_4

1

C60 .01u/25V_4 C64 .01u/25V_4

C75 .01u/25V_4 C83 .01u/25V_4

C117 .01u/25V_4

SATA_TXP5 <8> SATA_TXN5 <8>

SATA_RXN5_C <8> SATA_RXP5_C <8>

201201117 C766 for EMI suggestion.

+3V

20120201 change R154 to 10k PU +3V.

ODD_PRSNT# <9>

C113

C110

*.1u/16V_4

EC_ODD_EJ <24>

+3V

C507 10u/6.3V_6

+5V_ODD

+

C532 100u/6.3V_3528

2

ODD_POWER<24> PCH_ODD_EN<8>

R461 *SHORT_4 R462 *0_4

ODD_EN

+3VPCU

+15V

12

R469 100K

ODD_EN_Q

12

R463 *100K

20111118 change mose footprint to dual type.

6

2

5

1

4 3

3

1

7 8

K/B

5 3 1

CP6 *100 p/50Vx4

7 8 5 3 1

CP5 *100 p/50Vx4

7 8 5 3

A A

B B

1

CP1 *100 p/50Vx4

7 8 5 3 1

CP2 *100 p/50Vx4

7 8 5 3 1

CP3 *100 p/50Vx4

7 8 5 3 1

CP4 *100 p/50Vx4 C750 *100p/50V_4 C751 *100p/50V_4

MX3

6

MX2

4

MX4

2

MX5 MX6

6

MX7

4

MY17

2

MY16 MY3

6

MY2

4

MY1

2

MY0 MY7

6

MY6

4

MY5

2

MY4 MY11

6

MY10

4

MY9

2

MY8 MY15

6

MY14

4

MY13

2

MY12 MX1

MX0

ICT TEST FIXTURE(VOLTAGE TRANSLATOR)

R639 10K_4

TP8

JTAG_TDO<28> JTAG_CLK_VT<28> JTAG_TMS_VT<28>

TP45

C C

TP46

2

+3V +1.05V_VTT

R638 10K_4

U37

1

VCCA

2

1DIR

3

2DIR

4

1A1

5

1A2

6

2A1

7

2A2

8

GND

*74AVC4T245PW

201201113 change KB con footprint. 201201117 change KB con footprint.

MY0<24> MY1<24> MY2<24> MY3<24> MY4<24> MY5<24> MY6<24> MY7<24> MY8<24> MY9<24> MY10<24> MY11<24> MY12<24> MY13<24> MY14<24> MY15<24> MY16<24> MY17<24> MX7<24> MX6<24> MX5<24> MX4<24> MX3<24> MX2<24> MX1<24> MX0<24>

+3VPCU

RP5 10K_1 0P8R

10

1

9

2

MX4 MX2

8

3

MX5

7 4

MX6

56

MX7

20111125 modify pin define

16

VCCB

15

1OE#

14

2OE#

13

1B1

12

1B2

11

2B1

10

2B2

9

GND

MX3 MX1

MX0

MY0 MY1 MY2 MY3 MY4 MY5 MY6 MY7 MY8 MY9 MY10 MY11 MY12 MY13 MY14 MY15 MY16 MY17 MX7 MX6 MX5 MX4 MX3 MX2 MX1 MX0

R636 100/F_4

TP44 TP43 TP10

TP84

3

KB

1 2 3 4 5 6 7 8 9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

CN12

R637 100/F_4

27 28

XDP_TMS_VT <3,8> XDP_TCLK_VT <3,8> XDP_TDI_VT <3>

TP77

4

SCREW HOLE

HOLE9 *H-TC236I150BC27 6D150NP2

1

HOLE10 *H-TC236I150BC27 6D150NP2

1

HOLE13 *H-TC236I150BC27 6D150NP2

1

HOLE12 *H-TC236I150BC27 6D150NP2

1

5

PAD1

*spad-re118x362np

1

HOLE8

HG-C217D118P2

8 9

123

HOLE3

*HG-C256D118P2

8 9

123

6

HOLE6

*HG-C217D118P2

67 5 4

8 9

123

HOLE15

*HG-C256D118P2

9

123

HOLE17

*HG-C256D118P2

9

123

67 5 4

5678 4

HOLE4 H-C236D142P2

1

HOLE18 *H-C94D94N

7

HOLE2 *H-C236D118P2

1

HOLE5

HG-C236D122P2

5678 4

9

123

HOLE16 H-C217D102P2

1

HOLE1

*HG-C256D118P2

8 9

123

HOLE7

H-C236I122D122 NP2

8

67 5 4

1

BATT Enable short pad

HOLE11

*hg-te256x256i118bc256d118p2-v3

1 2 3

20111208 Change Hole8 to BATT short pad.

HOLE14

*hg-te256x256i118bc256d118p2-v3

1 2 3

BATT_EN# <31>

D D

Quanta Computer Inc.

PROJECT :

XDP/ Hole

PROJECT :

Size Doc ument Number Rev

Date: Sheet of

1

2

3

4

5

6

Date: Sheet of

7

Z09

3A

22 40Monday, April 09, 2012

8

5

USB3.0 CONN

D D

C382 0.1U/10V_4

USB30_TX2-<9>

C383 0.1U/10V_4

USB30_TX2+<9>

USB30_RX2-<9> USB30_RX2+<9>

C C

USB charger

B B

A A

20111117 remove 0ohm resistor R61112/R61110

+5VPCU

R300

4.7K_4

R290 *4.7K_4

Pull high CDP/SDP autodetect. Pull Low SDP only.

Name

USB data Apple DeviceMax Current

SDP CDP

DCP,Auto S4~S5

State

YES

S0~S3

YES NO

R282 15_4

USB30_TX2-_C USB30_TX2-_R USB30_TX2+_C USB30_TX2+_R

R283 15_4

R280 15_4

USB30_RX2-_R USB30_RX2+_R

R281 15_4

USBP1-

USBP1- <9>

USBP1+

USBP1+ <9>

U20

1

BC_CEN

CEN

CB1

USB1-_CHARGER

USB1+_CHARGER

2

TDM

DM

3

DP

TDP

4

SELCDP

VDD

PGND

500mA 1500mA 1800mA

SLG55584A

500mAS0~S3 500mA 1800mA

System status(CB) > Hi: S0 Charging with CDP/SDP. > Lo: S3,DCP autodetect.

8 7 6 5 9

USB1-_CHARGER

USB1+_CHARGER

USBP1USBP1+

R304*0_4

R305 *SHOR T_4

+5VPCU

4

R273 *SHOR T_4

R272 *SHOR T_4

MAINON <24,34,35,37,39>

USB_CHG_MODE <24>

C392 0.1u/10V_4 C400 *10u/6.3V_6

Battery Status, EC GPO control it. > Hi: S0 and S3~S5 Battery over 30% > Lo: S3~S5/ Battery under 30%

USBPWR2

USB1-_CHARGER_R USB1+_CHARGER_R

USB30_RX2-_R USB30_RX2+_R

USB30_TX2-_R USB30_TX2+_R

USB_CHG_EN<24>

+5VPCU

USB_BC_EN

C395

1U/6.3V_4

2010/11/21 add 47K pull high

BC_CEN

USB 3.0

CN3 USB3.0 CONN

1

VBUS

1

2

D-

2

3

D+

4

GND

5

SSRX-

5

6

SSRX+

7

GND

8

SSTX-

9

SSTX+

9

11111010131312

12

R268 47K_4

3

U19 G547E1P81U

2

IN1

OUT3

3

IN2

OUT2 OUT1

4

EN

1

GND

OC#

+3VPCU

C371 *0.1U/10V_4

2 1

3 5

U16 TC7SH08FU

R274 *0/J_4

U13

USB30_RX2-_R USB30_RX2-_R USB30_RX2+_R USB30_RX2+_R

USB30_TX2-_R USB30_TX2-_R USB30_TX2+_R USB30_TX2+_R

8

USBPWR2

7 6

5

4

USB_BC_EN

1

2

3

GND_3/8

4

4 556

*RClamp0524P

U12

1

GND

2

USB1-_CHARGER_R USB1-_CHARGER_R USB1+_CHARGER_R USB1+_CHARGER_R

2

3

*RClamp0582N

Close USB3.0

C366

C363

470P/50V_4

.1U/10V_4

USB_OC0# <9>

+

C364 150u/6.3V_3528

2

Reserve for Debug

USBP9-<9> USBP9+<9>

USBP0-<9> USBP0+<9>

10

9

7

6

USB30_RX1+<9> USB30_RX1-<9>

6

USBPWR2

6

5

4

USB30_TX1+<9> USB30_TX1-<9>

USBON#<24>

R16 *0_4 R15 *0_4

R271 *SHOR T_4

R270 *SHOR T_4

0.1U/10V_4

C376

USB30_TX1-_C USB30_TX1-_R

C375

0.1U/10V_4

+5V_S5

C5

U1

2

1U/6.3V_4

IN1 IN23OUT2

4

EN#

1

GND

G547F2P81U

USB30_RX1-_R USB30_RX1-_R USB30_RX1+_R USB30_RX1+_R

USB30_TX1-_R USB30_TX1-_R USB30_TX1+_R USB30_TX1+_R

USBP0-_R USBP0-_R USBP0+_R USBP0+_R

USBP0-_R

USBP0+_R

R277 15_4

R276 15_4 R279 15_4

R278 15_4

OUT3 OUT1

OC#

USB_OC0#

U15

1

2

3

GND_3/8

4

4 556

*RClamp0524P

1 2 3

USBP0-_R

USBP0+_R

8 7 6

5

U14

GND 2 3

*RClamp0582N

1

USBPWR1

USB30_RX1-_R USB30_RX1+_R

USB30_TX1-_R USB30_TX1+_R

USB30_RX1+_R USB30_RX1-_R

10

9

7

6

6 5 4

USB30_TX1+_RUSB30_TX1+_C

+

C8 150u/6.3V_3528

6 5 4

USB 3.0

USBPWR1

CN4 USB3.0 CONN

1

2

3

4

5

6

7

8

9

C4

1000p/50V_4

SSRX-

VBUS DD+ GND

SSRX+ GND SSTXSSTX+

12

11111010131312

Quanta Computer Inc.

PROJECT :

Z09

PROJECT :

Z09

PROJECT :

Size Document Number Rev

Date: Sheet of

5

4

3

2

Date: Sheet

USB 3.0

Z09

1

3A

of

23 40Monday, April 09, 2012

5

EC(KBC)

+3VPCU

R618 2.2_6

D D

CLK_PCI_EC

R617 *22_4

C739 *10p/50V_4

C C

B B

pin14 +VCC_GFX pin22 +3V_D for ATI pin24 +1V for ATI pin26 +1.8V_GPU for ATI pin28 GPU_RST#

A A

L29 PBY160808T-250Y-N/3A/25ohm_6

+3VPCU_EC

C743

4.7u/6.3V_6

EC_PECI<3,10>

pin13 GFX_PWRGD pin21 dGPU_VRON pin23 +VGPU_CORE pin25 +1.5V_GPU pin27 dGPU_PWROK

5

0.03A(30mils)

C735

C745

0.1u/10V_4

*.1u/16V_4

LPC_LFRAME#<8,19,20>

LPC_LAD0<8,19,20> LPC_LAD1<8,19,20> LPC_LAD2<8,19,20> LPC_LAD3<8,19,20>

CLK_PCI_EC<9>

CLKRUN#<7,19>

SIO_A20GATE<10>

SIO_RCIN#<10>

SIO_EXT_SCI#<10>

EC_FPBACK#<15>

AMP_MUTE#<19>

PLTRST#<9,17,19,20,25>

RF_EN<20>

SERIRQ<8,19>

SIO_EXT_SMI#<10>

+1.05V_VTT

C747

0.1u/10V_4

MY10<22> MY11<22> MY12<22> MY13<22> MY14<22> MY15<22> MY16<22> MY17<22>

MBCLK<31>

MBDATA<31>

2ND_MBCLK<9>

2ND_MBDATA<9>

VGA_CLK<28>

VGA_DATA<28>

TPCLK<19>

TPDATA<19>

ME_WR#<8>

BT_POWERON<20>

ODD_POWER<21>

R623 *SHORT_4

R625 43_4

MX0<22> MX1<22> MX2<22> MX3<22> MX4<22> MX5<22> MX6<22> MX7<22>

MY0<22> MY1<22> MY2<22> MY3<22> MY4<22> MY5<22> MY6<22> MY7<22> MY8<22> MY9<22>

1 2

Reserve for writing ME ROM

VTT - the power supply for the PECI signal PECI - the PECI 3.0 data bus, bidirectional signal.

DG0.9 and chklist 0.9 apply one series 43ohm near EC side

30mil

C748 *.1u/16V_4

+1.05V_VTT_EC

EC_PECR_R

E775AGND

C752

0.1u/10V_4

MBCLK MBDATA 2ND_MBCLK 2ND_MBDATA VGA_CLK VGA_DATA

4

+A3VPCU

C734

C738

10u/6.3V_60.1u/10V_4

19

46

76

88

115

102

U36

VCC1

VCC2

VCC3

VCC4

VCC5

3

LFRAME

126

LAD0

127

LAD1

128

LAD2

1

LAD3

2

LCLK

8

GPIO11/CLKRUN

121

GPIO85/GA20

122

KBRST/GPIO86

29

ECSCI/GPIO54

6

GPIO24/LDRQ

124

GPIO10/LPCPD

7

LREST

123

GPIO67/PWUREQ

125

SERIRQ

9

GPIO65/SMI

54

KBSIN0

55

KBSIN1

56

KBSIN2

57

KBSIN3

58

KBSIN4

59

KBSIN5

60

KBSIN6

61

KBSIN7

53

KBSOUT0/JENK

52

KBSOUT1/TCK

51

KBSOUT2/TMS

50

KBSOUT3/TDI

49

KBSOUT4/JEN0

48

KBSOUT5/TDO

47

KBSOUT6/RDY

43

KBSOUT7

42

KBSOUT8

41

KBSOUT9/SDP_VIS

40

KBSOUT10/P80_CLK

39

KBSOUT11/P80_DAT

38

KBSOUT12/GPIO64

37

KBSOUT13/GPIO63

36

KBSOUT14/GPIO62

35

KBSOUT15/GPIO61/XOR_OUT

34

GPIO60/KBSOUT16

33

GPIO57/KBSOUT17

70

GPIO17/SCL1

69

GPIO22/SDA1

67

GPIO73/SCL2

68

GPIO74/SDA2

119

GPIO23/SCL3

120

GPIO31/SDA3

72

GPIO37/PSCLK1

71

GPIO35/PSDAT1

10

GPIO26/PSCLK2

11

GPIO27PSDAT2

77

GPIO00/32KCLKIN

12

VTT

13

PECI

NPCE885LA0DX

5

L28 PBY160808T-250Y-N/3A/25ohm_6

RSVD for power on

NBSWON#

4

AVCC

GND1

GND2

18

45

E775AGND

LPC

KB

SMB

PS/2

GND3

GND4

GND5

78

89

A/D

D/A

GPIO06/IOX_DOUT/RTS1

GPIO42/SCL3B/TCK GPIO43/SDA3B/TMS

GPIO

GPIO50/PSCLK3/TDO GPIO52/PSDAT3/RDY

GPO82/IOX_LDSH/TEST

GPO84/IOX_SCLK/XORTR

GPIO20/TA2/IOX_DIN_DIO

TIMER

GPIO40/F_PWM/RI1

GPIO33/H_PWM/SOUT1

GPIO87/CIRRXM/SIN_CR

GPIO34/SIN1/CIRRXL

IR

GPIO46/CIRRXM/TRST

GPO83/SOUT_CR/TRIST

FIU

GPIO55/CLKOUT/IOX_DIN_DIO

AGND

GND6

44

103

116

1 3

D15

RB500V-40

GPIO90/AD0 GPIO91/AD1 GPIO92/AD2 GPIO93/AD3

GPIO94/DA0

GPI95/DA1 GPI96/DA2

GPIO01/TB2

GPIO02 GPIO03 GPIO04 GPIO05

GPIO07 GPIO16 GPIO30

GPIO36/CTS1

GPIO41

GPIO44/TDI

GPO47/SCL4

GPIO51

GPIO53/SDA4

GPIO70 GPIO71 GPIO72

GPIO75/SPI_SCK

GPO76/SHBM

GPIO77 GPIO81

GPIO97

GPIO56/TA1 GPIO14/TB1

GPIO15/A_PWM

GPIO21/B_PWM

GPIO13/C_PWM GPIO32/D_PWM GPIO45/E_PWM

GPIO66/G_PWM

F_SDI/F_SDIO1

F_SDO/F_SDIO0

F_CS0 F_SCK

VCC_POR

VCORF

VCORF_uR

C749

1u/6.3V_4

SW1 *SWITCH_1.5

3

+3V

C744

4.7u/6.3V_6

4

VDD

97 98 99 100

101 105 106

64 79 95 96 108 93 94 114 109 15 80 17 20 21 24 25 26 27 28 73 74 75 82 83 84 91 110 112 107

31 117 63

32 118 62 65 22 16 81 66

113 14 23 111

86 87 90 92

30 85 104

VREF

ICMNT_R

SM_DRAMRST#

HWPG

PWROK_EC_uR RSMRST#_uR

Do not use it

PROCHOT_EC

PCH_SPI_SO_R PCH_SPI_SI_R

PCH_SPI_CLK_R

VCC_POR# VREF_uR

C746

0.1u/10V_4

201201117 C762 for EMI suggestion.

C762

0.1u/10V_4

C733 10u/6.3V_6

R615 * SHORT_4

ICMNTE775AGND

C737 0.01u/16V_4

EC_DRAMRST_CNTRL

TP89

SB_ACDC <7,20>

R628 *SHORT_4 R626 *SHORT_4

TP90

TP56

R622 33_4 R621 33_4

R619 33_4

20111129 add 33ohm series resistor and for EC FAE suggestion

TP93

contact to SPI 4M ROM.

R624 47K/F_4 R614 *SHORT_4

ICMNT

+A3VPCU

+3VPCU

TEMP_MBAT <31>

WAKE_SRC_1 <20>

WAKE_SRC_2 <17>

ICMNT <31>

EC_DRAMRST_CNTRL <4>

KEY_BL_EN <19>

WK_GPIO27 <10>

ACIN <31>

SUSACK# <7>

NBSWON# <19>

IOAC_PCIERST# <7,20>

LID# <15>

DPWROK <7>

dGPU_OPP# <28>

VRON <33>

GPU_THAL# <28>

SUSB# <7>

GPU_TRIP# <28>

D/C# <31>

S5_ON <32,37>

HDMI_HPD_EC# <16>

GPU_PWR_ALERT# <38>

SUSC# <7> PWROK_EC <7> PCH_RSMRST# <7>

MAINON <23,34,35,37,39>

EC_ODD_EJ <21>

DNBSWON# <7>

USBON# <23>

USB_CHG_MODE <23>

SLP_SUS# <7,11> SUSON <35> FANSIG <19>

CONTRAST <15> PCBEEP_EC <19> PWRLED# <19> BATLED0# <19> CPUFAN# <19> SUSLED# <19> WLAN_OFF <20> BATLED1# <19>

USB_CHG_EN <23> +0.75V_ON <35> IOAC_LANPWR# <20>

PCH_SPI_SO_EC <8> PCH_SPI_SI_EC <8> SPI_CS0#_UR_ME <8> PCH_SPI_CLK_EC <8>

SM BUS ARRANGEMENT TABLE

SM Bus 1

Battery

SM Bus 2

PCH

SM Bus 3

VGA

SM Bus 4

HDMI

R645 *100K_4

+3V

C644

U38

3 5

*TC7SH08FU

*0.1u/10V_4

4

2 1

iRST

2 4 5 6

IOAC_PCIERST#

PCI_PLTRST#<3,9>

R649

*100K_4

3

2

20120220 Add KB backlight EN function.

SM BUS PU(KBC)

20120217 Change SUSWRAN# to IOAC_PCIRST#.

20120119 AddSM_DRAMRST# for deep S3. 20120104 Add DPWROK for deep S3.

20120105 Add GPU_TRIP# to NV GPIO8.

20120105 Add GPU_PWR_ALERT# to GPU_core IC.

20120117 Add WLAN_OFF to CN5 pin46 for IOAC.

HWPG(KBC)

20120217 reserve iRST function.

PCIERST#

PCIERST# <20>

2

S5_ON

R630 795@47K_4

20120217 Change R630 from10k to 47k for S5 current reduce..

MBCLK MBDATA

2ND_MBCLK 2ND_MBDATA

PROCHOT_EC

R613 100K_4

CPU_DRAMRST#<3,4>

HWPG_VCCSA<36>

HWPG_1.8V<37> HWPG_VTT<34,36> HWPG_1.5V<35>

SYS_HWPG<32> GFX_PWRGD<7,33>

Size Document Number Rev

Date: Sheet of

R629 10K_4 R631 10K_4

R633 10K_4 R632 10K_4

R609 * SHORT_4

3

Q43

2

2N7002K

1

Q5006 need Replacement at BOT layer.

+3V_S5

D20 BAS316 D17 BAS316 D18 BAS316 D21 BAS316 D19 BAS316 D16 *BAS316

1

+3VPCU

+3V_S5

H_PROCHOT# <3,33>

R640

R641 *10K_4

*1K_4

SM_DRAMRST#

6

215

*2N7002DW Q46

4 3

201201119 Add Q46 for DS3 function.

+3V

R627

10K_4

HWPG

Quanta Computer Inc.

PROJECT :

WPCE791 & FLASH

Z09

24 40Monday, April 09, 2012

1

1A

1

2

3

4

5

D13 EV@BAS3 16

+3V_GFX+VGPU_CORE

D12 EV@BAS3 16

+1.5V_GFX +3V_GFX

For power-down sequence purpose

6

GF108:N12P GF117:N13M

GK107:N13P

7

Feedback179

8

+3V_NV

U6A

bga908-nvidia-n13p-gs-a1

A A

PEGX_RST#

PCIE_CLKREQ_PE G#

CLK_PCIE_VGAP<9> CLK_PCIE_VGAN<9>

PEG_CLKREQ# <9>

GRP0C GRN0C

GRP1C GRN1C

GRP2C GRN2C

GRP3C GRN3C

GRP4C GRN4C

GRP5C GRN5C

GRP6C GRN6C

GRP7C GRN7C

GRP8C GRN8C

GRP9C GRN9C

GRP10C GRN10C

GRP11C GRN11C

GRP12C GRN12C

GRP13C GRN13C

GRP14C GRN14C

GRP15C GRN15C

2

C582 EV@0.2 2u/10V_4 C581 EV@0.2 2u/10V_4

GTP0<2> GTN0<2>

C558 EV@0.2 2u/10V_4 C559 EV@0.2 2u/10V_4

GTP1<2> GTN1<2>

C584 EV@0.2 2u/10V_4 C583 EV@0.2 2u/10V_4

GTP2<2> GTN2<2>

C561 EV@0.2 2u/10V_4 C560 EV@0.2 2u/10V_4

GTP3<2> GTN3<2>

C586 EV@0.2 2u/10V_4 C585 EV@0.2 2u/10V_4

GTP4<2> GTN4<2>

C563 EV@0.2 2u/10V_4 C562 EV@0.2 2u/10V_4

GTP5<2> GTN5<2>

C588 EV@0.2 2u/10V_4 C587 EV@0.2 2u/10V_4

GTP6<2> GTN6<2>

C553 EV@0.2 2u/10V_4 C554 EV@0.2 2u/10V_4

GTP7<2> GTN7<2>

C590 EV@0.2 2u/10V_4 C589 EV@0.2 2u/10V_4

GTP8<2> GTN8<2>

C564 EV@0.2 2u/10V_4 C565 EV@0.2 2u/10V_4

GTP9<2> GTN9<2>

C567 EV@0.2 2u/10V_4 C566 EV@0.2 2u/10V_4

GTP10<2> GTN10<2>

C569 EV@0.2 2u/10V_4 C570 EV@0.2 2u/10V_4

GTP11<2> GTN11<2>

C571 EV@0.2 2u/10V_4 C572 EV@0.2 2u/10V_4

GTP12<2> GTN12<2>

C573 EV@0.2 2u/10V_4 C574 EV@0.2 2u/10V_4

GTP13<2> GTN13<2>

C575 EV@0.2 2u/10V_4 C576 EV@0.2 2u/10V_4

GTP14<2> GTN14<2>

C577 EV@0.2 2u/10V_4 C578 EV@0.2 2u/10V_4

GTP15<2> GTN15<2>

GRP0<2> GRN0<2>

GRP1<2> GRN1<2>

GRP2<2> GRN2<2>

GRP3<2> GRN3<2>

B B

C C

D D

R514 EV@10K/F_4

+3V_GFX

PCIE_CLKREQ_PE G#

1

GRP4<2> GRN4<2>

GRP5<2> GRN5<2>

GRP6<2> GRN6<2>

GRP7<2> GRN7<2>

GRP8<2> GRN8<2>

GRP9<2> GRN9<2>

GRP10<2> GRN10<2>

GRP11<2> GRN11<2>

GRP12<2> GRN12<2>

GRP13<2> GRN13<2>

GRP14<2> GRN14<2>

GRP15<2> GRN15<2>

+3V_GFX

2

3

1

Q34EV@2N700 2D

COMMON

1/19 PCI_EXPRESS

AJ11

TP28

PEX_WAKE

AJ12

PEX_RST

AK12

PEX_CLKREQ

AL13

PEX_REFCLK

AK13

PEX_REFCLK

AK14

PEX_TX0

AJ14

PEX_TX0

AN12

PEX_RX0

AM12

PEX_RX0

AH14

PEX_TX1

AG14

PEX_TX1

AN14

PEX_RX1

AM14

PEX_RX1

AK15

PEX_TX2

AJ15

PEX_TX2

AP14

PEX_RX2

AP15

PEX_RX2

AL16

PEX_TX3

AK16

PEX_TX3

AN15

PEX_RX3

AM15

PEX_RX3

AK17

PEX_TX4

AJ17

PEX_TX4

AN17

PEX_RX4

AM17

PEX_RX4

AH17

PEX_TX5

AG17

PEX_TX5

AP17

PEX_RX5

AP18

PEX_RX5

AK18

PEX_TX6

AJ18

PEX_TX6

AN18

PEX_RX6

AM18

PEX_RX6

AL19

PEX_TX7

AK19

PEX_TX7

AN20

PEX_RX7

AM20

PEX_RX7

AK20

PEX_TX8

AJ20

PEX_TX8

AP20

PEX_RX8

AP21

PEX_RX8

AH20

PEX_TX9

AG20

PEX_TX9

AN21

PEX_RX9

AM21

PEX_RX9

AK21

PEX_TX10

AJ21

PEX_TX10

AN23

PEX_RX10

AM23

PEX_RX10

AL22

PEX_TX11

AK22

PEX_TX11

AP23

PEX_RX11

AP24

PEX_RX11

AK23

PEX_TX12

AJ23

PEX_TX12

AN24

PEX_RX12

AM24

PEX_RX12

AH23

PEX_TX13

AG23

PEX_TX13

AN26

PEX_RX13

AM26

PEX_RX13

AK24

PEX_TX14

AJ24

PEX_TX14

AP26

PEX_RX14

AP27

PEX_RX14

AL25

PEX_TX15

AK25

PEX_TX15

AN27

PEX_RX15

AM27

PEX_RX15

3

PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD

PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ

PEX_PLL_HVDD

PEX_SVDD_3V3

VDD_SENSE

GND_SENSE

3V3AUX_NC

PEX_TSTCLK_OUT PEX_TSTCLK_OUT

PEX_PLLVDD

TESTMODE

PEX_TERMP

4

PEX_IOVDD+PEX_IOVDDQ+PEX_PLLVDD >2.2A

AG19 AG21

C536 EV@1U/6.3 V/X7R_4

AG22

C535 EV@1U/6.3 V/X7R_4

AG24 AH21 AH25

C518 EV@4.7 U/6.3V_6 C591 EV@10U/6 .3V_8 C525 EV@10U/6 .3V_8 C547 EV@22U/6 .3V_8 C539 EV@22U/6 .3V_8

AG13 AG15 AG16 AG18

C533 EV@1U/6.3 V/X7R_4

AG25

C546 EV@1U/6.3 V/X7R_4

AH15 AH18 AH26

C550 EV@4.7 U/6.3V_6

AH27

C526 EV@10U/6 .3V_8

AJ27

C527 EV@10U/6 .3V_8

AK27

C568 EV@22U/6 .3V_8

AL27

C548 EV@22U/6 .3V_8

AM28 AN28

PLACE NEAR BALLS

AH12 AG12

L4

GPUVCC_SENSE <38>

L5

GPUVSS_SENSE <38>

P8

TP27

AJ26

PEX_TSTCLK

AK26

PEX_TSTCLK#

AG26

+PEX_PLLVDD

AK11

TESTMODE

AP29

PEX_TERMP

C521 EV@0.1 U/10V_4 C534 EV@4.7 U/6.3V_6 C528 EV@4.7 U/6.3V_6

20110907 del C6219,C6221,L5077,L5059

R501 *EV@200_4

C552 EV@4.7 U/6.3V/X7R_6 C522 EV@1U/6.3 V/X7R_4 C516 EV@0.1 U/10V/X7R_4

R515

R507 EV@2. 49K/F_4

R512 *SHORT_6

PLACE NEAR BGA

EV@10K_4

PLTRST#<9,17,19,20,24 >

DGPU_HOLD_RST#<9>

5

FAE suggest change to 1uF

+3V_GFX

150mA

+1.05V_GFX

PLACE NEAR BGA

3300mA

+1.05V_GFX

PLACE NEAR BGA

210mA

+1.05V_GFX

R511 *SHORT_4

EV@MC74VHC1G08DFT2G

+3V_GFX

2 1

U29

3 5

R497 *EV@0_4

C540 EV@0.1 U/10V_4

4

6

+VGPU_CORE

+1.5V_NV

IFPx_IOVDD (1.05V)

PEX_VDD (1.05V)

All rails must be powered off within 10 ms from the first rail powering off.

NB9M: VGACORE +0.90V (Normal) , +1.09V

NVVDD Maximum Settling Time

+VGPU_CORE

GPIO

tsNVVDD<= 192us

PEX_RST timing

I/O 3.3V

PEX_RST

Trise >= 1uS Tfail <=500nS

GPU all PWROK

+3V_S5

R182

EV@10K_4

2

+1.05V_GFX

Q4

1 3

EV@PDTC143TT

PEGX_RST#

R499

EV@100K/F_4

Size Document Number Rev

N13P-LP (PCIE I/F) 1/5

Monday, April 09, 201 2

Date: Sheet o f

Monday, April 09, 201 2

Date: Sheet o f

Monday, April 09, 201 2

Date: Sheet

7

+3V_GFX

R178

EV@10K_4

DGPU_PWROK <1 0>

3

Q3

EV@2N7002D

1

Quanta Computer Inc.

PROJECT :

Z09

PROJECT :

Z09

PROJECT :

Z09

of

25 40

8

3A

1

VMA_DQ[63..0]<30>

FBA_EDC[7..0]<30>

VMA_DQ[63..0] FBA_DBI[7..0]

FBA_DBI[7..0]<30>

FBA_EDC[7..0]

2

3

4

VMB_DQ[63..0]<30>

FBC_DBI[7..0]<30>

FBC_EDC[7..0]<30>

VMB_DQ[63..0] FBC_DBI[7..0] FBC_EDC[7..0]

5

6

7

8

17

E1

K27

U30 T31 U29 R34 R33 U32 U33 U28 V28 V29 V30 U34 U31 V34 V33 Y32 AA31 AA29 AA28 AC34 AC33 AA32 AA33 Y28 Y29 W31 Y30 AA34 Y31 Y34 Y33 V31

R32 AC32

R28 AC28

R30 R31 AB31 AC31

K31 L30 H34 J34 AG30 AG31 AJ34 AK34

J30 J31 J32 J33 AH31 AJ31 AJ32 AJ33

U27

FB_PLL_AVDD

FBA_DEBUG0 FBA_DEBUG1

5500mA

R92 EV@1 0K_4

C488 EV@0.1U/10V_4

FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31

TP62 TP63

POP For Debug only

lace close to ball

P

R468 *EV@60 .4/F_4 R493 *EV@60 .4/F_4

VMA_WCK01 <30> VMA_WCK01# <30> VMA_WCK23 <30> VMA_WCK23# <30> VMA_WCK45 <30> VMA_WCK45# <30> VMA_WCK67 <30> VMA_WCK67# <30>

FB_PLL_AVDD

C437 EV@22U/6 .3V_8 C464 EV@0.1 U/10V_4

C443 EV@0.1 U/10V_4

FBA_CMD[31:0] <30>

VMA_CLKP0 <3 0> VMA_CLKN0 <30> VMA_CLKP1 <3 0> VMA_CLKN1 <30>

30ohm

L23 EV@BLM18PG30 0SN1

+1.5V_GFX

+1.05V_GFX

VMB_DQ0 VMB_DQ1 VMB_DQ2 VMB_DQ3 VMB_DQ4 VMB_DQ5 VMB_DQ6 VMB_DQ7 VMB_DQ8 VMB_DQ9 VMB_DQ10 VMB_DQ11 VMB_DQ12 VMB_DQ13 VMB_DQ14 VMB_DQ15 VMB_DQ16 VMB_DQ17 VMB_DQ18 VMB_DQ19 VMB_DQ20 VMB_DQ21 VMB_DQ22 VMB_DQ23 VMB_DQ24 VMB_DQ25 VMB_DQ26 VMB_DQ27 VMB_DQ28 VMB_DQ29 VMB_DQ30 VMB_DQ31 VMB_DQ32 VMB_DQ33 VMB_DQ34 VMB_DQ35 VMB_DQ36 VMB_DQ37 VMB_DQ38 VMB_DQ39 VMB_DQ40 VMB_DQ41 VMB_DQ42 VMB_DQ43 VMB_DQ44 VMB_DQ45 VMB_DQ46 VMB_DQ47 VMB_DQ48 VMB_DQ49 VMB_DQ50 VMB_DQ51 VMB_DQ52 VMB_DQ53 VMB_DQ54 VMB_DQ55 VMB_DQ56 VMB_DQ57 VMB_DQ58 VMB_DQ59 VMB_DQ60 VMB_DQ61 VMB_DQ62 VMB_DQ63

FBC_EDC0 FBC_EDC1 FBC_EDC2 FBC_EDC3 FBC_EDC4 FBC_EDC5 FBC_EDC6 FBC_EDC7

FBC_DBI0 FBC_DBI1 FBC_DBI2 FBC_DBI3 FBC_DBI4 FBC_DBI5 FBC_DBI6 FBC_DBI7

U6C

G9

FBB_D0

E9

FBB_D1

G8

FBB_D2

F9

FBB_D3

F11

FBB_D4

G11

FBB_D5

F12

FBB_D6

G12

FBB_D7

G6

FBB_D8

F5

FBB_D9

E6

FBB_D10

F6

FBB_D11

F4

FBB_D12

G4

FBB_D13

E2

FBB_D14

F3

FBB_D15

C2

FBB_D16

D4

FBB_D17

D3

FBB_D18

C1

FBB_D19

B3

FBB_D20

C4

FBB_D21

B5

FBB_D22

C5

FBB_D23

A11

FBB_D24

C11

FBB_D25

D11

FBB_D26

B11

FBB_D27

D8

FBB_D28

A8

FBB_D29

C8

FBB_D30

B8

FBB_D31

F24

FBB_D32

G23

FBB_D33

E24

FBB_D34

G24

FBB_D35

D21

FBB_D36

E21

FBB_D37

G21

FBB_D38

F21

FBB_D39

G27

FBB_D40

D27

FBB_D41

G26

FBB_D42

E27

FBB_D43

E29

FBB_D44

F29

FBB_D45

E30

FBB_D46

D30

FBB_D47

A32

FBB_D48

C31

FBB_D49

C32

FBB_D50

B32

FBB_D51

D29

FBB_D52

A29

FBB_D53

C29

FBB_D54

B29

FBB_D55

B21

FBB_D56

C23

FBB_D57

A21

FBB_D58

C21

FBB_D59

B24

FBB_D60

C24

FBB_D61

B26

FBB_D62

C26

FBB_D63

E11

FBB_DQM0

E3

FBB_DQM1

A3

FBB_DQM2

C9

FBB_DQM3

F23

FBB_DQM4

F27

FBB_DQM5

C30

FBB_DQM6

A24

FBB_DQM7

D10

FBB_DQS_WP0

D5

FBB_DQS_WP1

C3

FBB_DQS_WP2

B9

FBB_DQS_WP3

E23

FBB_DQS_WP4

E28

FBB_DQS_WP5

B30

FBB_DQS_WP6

A23

FBB_DQS_WP7

D9

FBB_DQS_RN0

E4

FBB_DQS_RN1

B2

FBB_DQS_RN2

A9

FBB_DQS_RN3

D22

FBB_DQS_RN4

D28

FBB_DQS_RN5

A30

FBB_DQS_RN6

B23

FBB_DQS_RN7

EV@U_GPU_GB4_128

3/19 FBB

FBB_CMD0 FBB_CMD1 FBB_CMD2 FBB_CMD3 FBB_CMD4 FBB_CMD5 FBB_CMD6 FBB_CMD7 FBB_CMD8

FBB_CMD9 FBB_CMD10 FBB_CMD11 FBB_CMD12 FBB_CMD13 FBB_CMD14 FBB_CMD15 FBB_CMD16 FBB_CMD17 FBB_CMD18 FBB_CMD19 FBB_CMD20 FBB_CMD21 FBB_CMD22 FBB_CMD23 FBB_CMD24 FBB_CMD25 FBB_CMD26 FBB_CMD27 FBB_CMD28 FBB_CMD29 FBB_CMD30 FBB_CMD31

FBB_CMD_RFU0 FBB_CMD_RFU1

FBB_DEBUG0 FBB_DEBUG1

FBB_CLK0 FBB_CLK0 FBB_CLK1 FBB_CLK1

FBB_WCK01 FBB_WCK01 FBB_WCK23 FBB_WCK23 FBB_WCK45 FBB_WCK45 FBB_WCK67 FBB_WCK67

FBB_WCKB01 FBB_WCKB01 FBB_WCKB23 FBB_WCKB23 FBB_WCKB45 FBB_WCKB45 FBB_WCKB67 FBB_WCKB67

FBB_PLL_AVDD

D13 E14 F14 A12 B12 C14 B14 G15 F15 E15 D15 A14 D14 A15 B15 C17 D18 E18 F18 A20 B20 C18 B18 G18 G17 F17 D16 A18 D17 A17 B17 E17

C12 C20

G14 G20

D12 E12 E20 F20

F8 E8 A5 A6 D24 D25 B27 C27

D6 D7 C6 B6 F26 E26 A26 A27

H17

FBC_CMD0 FBC_CMD1 FBC_CMD2 FBC_CMD3 FBC_CMD4 FBC_CMD5 FBC_CMD6 FBC_CMD7 FBC_CMD8 FBC_CMD9 FBC_CMD10 FBC_CMD11 FBC_CMD12 FBC_CMD13 FBC_CMD14 FBC_CMD15 FBC_CMD16 FBC_CMD17 FBC_CMD18 FBC_CMD19 FBC_CMD20 FBC_CMD21 FBC_CMD22 FBC_CMD23 FBC_CMD24 FBC_CMD25 FBC_CMD26 FBC_CMD27 FBC_CMD28 FBC_CMD29 FBC_CMD30 FBC_CMD31

FBB_DEBUG0 FBB_DEBUG1

FB_PLL_AVDD

TP58 TP87

POP For Debug only Place close to ball

R452 *EV@60 .4/F_4 R453 *EV@60 .4/F_4

VMC_CLKP0 <30> VMC_CLKN0 <30> VMC_CLKP1 <30> VMC_CLKN1 <30>

VMC_WCK01 <30> VMC_WCK01# <30> VMC_WCK23 <30> VMC_WCK23# <30> VMC_WCK45 <30> VMC_WCK45# <30> VMC_WCK67 <30> VMC_WCK67# <30>

C453 EV@0.1U/10V_4

FBC_CMD[31:0] <30>

+1.5V_GFX

GDDR5 Mode H M apping

< 0-31 > < 32- 63 > Memory

CMD0 CMD16 CS* CMD1 CMD17 A3_BA3 CMD2 CMD18 A2_BA0 CMD3 CMD19 A4_BA2 CMD4 CMD20 A5_BA1 CMD5 CMD21 WE* CMD6 CMD22 A7_A8 CMD7 CMD23 A6_A11 CMD8 CMD24 ABI* CMD9 CMD25 A12_RFU CMD10 CMD26 A0_A10 CMD11 CMD27 A1_A9 CMD12 CMD28 RAS* CMD13 CMD29 RST* CMD14 CMD30 CKE* CMD15 CMD31 CAS*

A A

B B

C C

D D

VMA_DQ0 VMA_DQ1 VMA_DQ2 VMA_DQ3 VMA_DQ4 VMA_DQ5 VMA_DQ6 VMA_DQ7 VMA_DQ8

VMA_DQ9 VMA_DQ10 VMA_DQ11 VMA_DQ12 VMA_DQ13 VMA_DQ14 VMA_DQ15 VMA_DQ16 VMA_DQ17 VMA_DQ18 VMA_DQ19 VMA_DQ20 VMA_DQ21 VMA_DQ22 VMA_DQ23 VMA_DQ24 VMA_DQ25 VMA_DQ26 VMA_DQ27 VMA_DQ28 VMA_DQ29 VMA_DQ30 VMA_DQ31 VMA_DQ32 VMA_DQ33 VMA_DQ34 VMA_DQ35 VMA_DQ36 VMA_DQ37 VMA_DQ38 VMA_DQ39 VMA_DQ40 VMA_DQ41 VMA_DQ42 VMA_DQ43 VMA_DQ44 VMA_DQ45 VMA_DQ46 VMA_DQ47 VMA_DQ48 VMA_DQ49 VMA_DQ50 VMA_DQ51 VMA_DQ52 VMA_DQ53 VMA_DQ54 VMA_DQ55 VMA_DQ56 VMA_DQ57 VMA_DQ58 VMA_DQ59 VMA_DQ60 VMA_DQ61 VMA_DQ62 VMA_DQ63

FBA_EDC0 FBA_EDC1 FBA_EDC2 FBA_EDC3 FBA_EDC4 FBA_EDC5 FBA_EDC6 FBA_EDC7

FBA_DBI0 FBA_DBI1 FBA_DBI2 FBA_DBI3 FBA_DBI4 FBA_DBI5 FBA_DBI6 FBA_DBI7

TP60

L28

M29

L29

M28

N31 P29 R29 P28 J28 H29 J29 H28

G29

E31 E32 F30 C34 D32 B33 C33 F33 F32 H33 H32 P34 P32 P31 P33 L31 L34 L32

L33 AG28 AF29 AG29 AF28 AD30 AD29 AC29 AD28 AJ29 AK29 AJ30 AK28

AM29 AM31

AN29

AM30

AN31 AN32 AP30 AP32

AM33

AL31 AK33 AK32 AD34 AD32 AC30 AD33 AF31 AG34 AG32 AG33

P30

F31

F34

M32 AD31 AL29

AM32

AF34

M31

G31

E33

M33 AE31 AK30 AN33 AF33

M30

H30 E34

M34 AF30 AK31

AM34

AF32

H26

U6B

2/19 FBA

FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63

FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7

FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7

FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7

FB_VREF

EV@U_GPU_GB4_128

RSVD

FB_DLL_AVDD

FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8

FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31

FBA_CMD_RFU0 FBA_CMD_RFU1

FBA_DEBUG0 FBA_DEBUG1

FBA_CLK0 FBA_CLK0 FBA_CLK1 FBA_CLK1

FBA_WCK01 FBA_WCK01 FBA_WCK23 FBA_WCK23 FBA_WCK45 FBA_WCK45 FBA_WCK67 FBA_WCK67

FBA_WCKB01 FBA_WCKB01 FBA_WCKB23 FBA_WCKB23 FBA_WCKB45 FBA_WCKB45 FBA_WCKB67 FBA_WCKB67

FBA_PLL_AVDD

Quanta Computer Inc.

PROJECT :

Z09

PROJECT :

Z09

PROJECT :

Size Document Number Rev

N13P-LP (MEMORY I/F) 2/5

Date: Sheet o f

Monday, April 09, 201 2

Date: Sheet o f

Monday, April 09, 201 2

Date: Sheet o f

1

2

3

4

5

6

7

Monday, April 09, 201 2

Z09

8

26 40

3A

1

IFPAB ONLY: NO STUFF RSET is default Required when external refer ence is used

A A

B B

R165 *EV@1K /F_4

C C

R175 *EV@1K /F_4

D D

1

R181 *EV@1K /F_4

R179 EV@10 K_4

R177 EV@10 K_4

R487 EV@10 K_4

(1.05V +/- 3% )

R498 EV@10 K_4

R176 EV@10 K_4

R174 EV@10 K_4

2

IFPD_RSET

2

U6J

6/19 IFPAB

ALL PINS NC FOR GF117

AJ8

IFPAB_RSET

AH8

IFPAB_PLLVDD

AG8

IFPA_IOVDD

AG9

IFPB_IOVDD

IFPAB

EV@U_GPU_GB4_128

U6K

7/19 IFPC

AF8

IFPC_RSET

AF7

IFPC_PLLVDD

AF6

IFPC_IOVDD

EV@U_GPU_GB4_128

U6L

8/19 IFPD

AN2

IFPD_RSET

AG7

IFPD_PLLVDD

AG6

IFPD_IOVDD

EV@U_GPU_GB4_128

ALL PINS NC FOR GF117

I2CW_SDA I2CW_SCL

TXC TXC

TXD0

IFPC

TXD0 TXD1

TXD1

TXD2 TXD2

ALL PINS NC FOR GF117

DVI/HDMI

I2CX_SDA I2CX_SCL

TXC TXC

TXD0

IFPD

TXD0 TXD1

TXD1

TXD2 TXD2

3

AN6

IFPA_TXC

AM6

IFPA_TXC

AN3

IFPA_TXD0

AP3

IFPA_TXD0

AM5

IFPA_TXD1

AN5

IFPA_TXD1

AK6

IFPA_TXD2

AL6

IFPA_TXD2

AH6

IFPA_TXD3

AJ6

IFPA_TXD3

AH9

IFPB_TXC

AJ9

IFPB_TXC

AP5

IFPB_TXD4

AP6

IFPB_TXD4

AL7

IFPB_TXD5

AM7

IFPB_TXD5

AM8

IFPB_TXD6

AN8

IFPB_TXD6

AL8

IFPB_TXD7

AK8

IFPB_TXD7

N4

GPIO14

DPDVI/HDMI

AG2

IFPC_AUX

AG3

IFPC_AUX

AG4

IFPC_L3

AG5

IFPC_L3

AH4

IFPC_L2

AH3

IFPC_L2

AJ2

IFPC_L1

AJ3

IFPC_L1

AJ1

IFPC_L0

AK1

IFPC_L0

P2

GPIO15

DP

AK2

IFPD_AUX

AK3

IFPD_AUX

AK5

IFPD_L3

AK4

IFPD_L3

AL4

IFPD_L2

AL3

IFPD_L2

AM4

IFPD_L1

AM3

IFPD_L1

AM2

IFPD_L0

AM1

IFPD_L0

M6

GPIO17

3

4

L25 EV@BLM18PG30 0SN1

+1.05V_GFX

105mA

L27 EV@180ohm/5A

+1.05V_GFX

4

30ohm

180ohm

5

R151 EV@10 K_4

R161 *EV@1K /F_4

R157 EV@10 K_4

R153 EV@10 K_4

R180 EV@10 K_4

C524 EV@0.1 U/10V_4 C486 EV@22U/6 .3V_8

C523 EV@0.1 U/10V_4 C519 EV@0.1 U/10V_4

C510 EV@4.7 U/6.3V_6 C506 EV@22U/6 .3V_8

5

120 mA 220 mA

+DACA_VDD

U6M

220 mA

AB8

IFPEF_PLLVDD

AD6

IFPEF_RSET

AC7

IFPE_IOVDD

AC8

IFPF_IOVDD

EV@U_GPU_GB4_128

AG10

AP9 AP8

R122 EV@10K_4

9/19 IFPEF

IFPE

IFPF

U6N

4/19 DACA

DACA_VDD

DACA_VREF

DACA_RSET

EV@U_GPU_GB4_128

AD8 AE8

AD7

H1

H3

R109 *SHORT_4

XTALI_27M

EV@10p/50V_4

ALL PINS NC FOR GF117

6

I2CY_SDA

TXC TXC

TXD0 TXD0

TXD1 TXD1

TXD2 TXD2

HPD_E

TXD3 TXD3

TXD4 TXD4

TXD5 TXD5

GF117GF108/GKx

NC NC

TSEN_VREF

NC

U6O

12/19 XTAL_PLL

PLLVDD SP_PLLVDD

VID_PLLVDD

NC

GF117GF108/GKx

XTALSSIN

XTALIN

EV@U_GPU_GB4_128

Y1

1 3 2 4

C45

EV@27MHz

20120201 Change CAP from 27P to 10P.

6

I2CY_SDA I2CY_SCLI2CY_SCL

TXC TXC

TXD0 TXD0

TXD1 TXD1

TXD2 TXD2

HPD_E

I2CZ_SDA I2CZ_SCL

TXC TXC

TXD0 TXD0

TXD1 TXD1

TXD2 TXD2

HPD_F

GF117 GF10 8/GKx

NC

NC NC

NC

XTALOUTBUFF

7

DPDV I-SL/HDMIDVI-DL

AB4

IFPE_AUX

AB3

IFPE_AUX

AC5

IFPE_L3

AC4

IFPE_L3

AC3

IFPE_L2

AC2

IFPE_L2

AC1

IFPE_L1

AD1

IFPE_L1

AD3

IFPE_L0

AD2

IFPE_L0

R1

GPIO18

AF2

IFPF_AUX

AF3

IFPF_AUX

AF1

IFPF_L3

AG1

IFPF_L3

AD5

IFPF_L2

AD4

IFPF_L2

AF5

IFPF_L1

AF4

IFPF_L1

AE4

IFPF_L0

AE3

IFPF_L0

P3

GPIO19

R4

I2CA_SCL I2CA_SDA

DACA_HSYNC DACA_VSYNC

DACA_RED

DACA_GREEN

DACA_BLUE

I2CA_SCL

R5

I2CA_SDA

AM9 AN9

AK9 AL10 AL9

R155EV@2.2K_4 R160EV@2.2K_4

J4

H2

XTALOUT

XTALO_27M

C54 EV@10p/50V_4

EV@10K_4 R454

Quanta Computer Inc.

PROJECT :

N13P-LP (DISPLAY) 3/5

Monday, April 09, 201 2

PROJECT :

Size Document Number Rev

Date: Sheet o f

7

+3V_GFX

8

18

Z09

8

27 40

3A

1

U6Q

11/19 MISC1

A A

K4

VGA_THERMDN

TP48

VGA_THERMDP

TP47

JTAG_CLK_VT<22> JTAG_TMS_VT<22>

TP3

JTAG_TDO<22>

JTAG_TRST#

TP39

B B

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

R129

C C

D D

EV@40.2K/F_4

dGPU_OPP#<24>

20111128 change Q5044 to dual mose, because NV FAE suggestion prevent backdriver GPIO12, ACIN high DC low.

JTAG_TDI

K3

AM10 AP11 AM11 AP12 AN11

U6P

13/19 MISC2

J2

STRAP0

J7

STRAP1

J6

STRAP2

J5

STRAP3

J3

STRAP4

J1

MULTISTRAP_REF_GND

EV@U_GPU_GB4_128

+3V_GFX

R451 EV@10K_4

4 3

THERMDN

THERMDP

JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO JTAG_TRST

EV@U_GPU_GB4_128

VGA_ACIN

6

215

R450 EV@10K_4

Q27 EV@2N7002DW

I2CS_SCL

I2CS_SDA

I2CC_SCL I2CC_SDA

I2CB_SCL I2CB_SDA

2

ROM_CS

ROM_SI

ROM_SO

ROM_SCLK

BUFRST

CEC

3

VGA Thermal

+3V_GFX

R476EV@2.2K_4 R474EV@2.2K_4

R142EV@2.2K_4 R145EV@2.2K_4

R150EV@2.2K_4 R152EV@2.2K_4

T4

I2CS_SCL

T3

I2CS_SDA

R2

I2CC_SCL

R3

I2CC_SDA

R7

I2CB_SCL

R6

I2CB_SDA

P6

GPIO0

M3

GPIO1

L6

GPIO2

P5

GPIO3

P7

GPIO4

L7

GPIO5

M7

GPIO6

N8

GPIO7

M1

GPIO8

M2

GPIO9

L1

GPIO10

M5

GPIO11

N3

GPIO12

M4

GPIO13

R8

GPU_DPRSLPVR_R

GPIO16

P4

GPIO20

TP38

P1

GPIO21

TP41

+3V_GFX

R95 EV@10K/F_4

H6 H5

ROM_SI

H7

ROM_SO

H4

ROM_SCLK

L2

R137 EV@10K/F_4

L3

R140 *EV@10K/F_4

unstuff @ N13P-GS stuff @ N13P-PL

20111117 change mose footprint to dual type. 20111128 change to singal mose because re-allocation GPIO for ADPS.

GPU_ALERT#

.1u/10V_4

VGA_OVT#

201201117 c761 for EMI suggestion.

I2CS_SCL

I2CS_SDA

I2CS_SCL I2CS_SDA

I2CC_SCL I2CC_SDA

I2CB_SCL I2CB_SDA

GPU_VID4 <38>

VGA_OVT#

VGA_ACIN

1

R435 *EV@0_4

1

R383 *EV@0_4

R484 *SHORT_4

+3V_GFX

Q26

2

EV@2N7002D

+3V_GFX

Q25

2

EV@2N7002D

TP52

3

GPU_VID3 <38>

GPU_VID1 <38> GPU_VID2 <38>

LOW active , need external PU. LOW active , need external PU.

GPIO10_VREF <30> GPU_VID0 <38>

GPU_VID5 <38>

GPU_DPRSLPVR <38>

TP49 TP50 TP51

GPU_ALERT#

20111129 add 0ohm at net GPU_DPRSLPVR for NV FAE request.

C761

20111128 add PU+3V resistor on VGA_CLK and DATA. 20120217 Change +3V to +3VPCU.

20120220 Change +3V .

R547 *EV@0_4 R548 *EV@0_4

Q35

1

4 3

EV@2N7002DW

20111117 change mose footprint to dual type.

LOW active , need external PU.

20110907 del R6035.

+3V

R527

R516

EV@10K_4

6 2

5

GPU_THAL# <24>

GPU_TRIP# <24>

20120106 contact to EC for ADPS.

4

VGA_CLK <24>

VGA_DATA <24>

+3V_GFX

5

Logical

Strapping Bit3 Strapping Bit1

N13P-LP FB[1]

ROM_SO

N13P-GL XCLK_417

PCI_DEVIDE[4]

ROM_SCLK

RAMCFG[3] RAMCFG[2]

ROM_SI

STRAP0

3GIO_PADCFG[3]

STRAP1

PCI_DEVID[3] PCI_DEVID[1]

STRAP2

SOR_EXPOSED[3] SOR_EXPOSED[1]

STRAP3

Reserve

STRAP4

RAMCFG [3:0]

0x1(0001)

1250MHz 2GB(64M*32) Samsung

*

0x0(0000)

1250MHz 2GB(64M*32) Hynix 1250MHz 2GB(64M*32) Hynix0x0(0100) 1250MHz 2GB(64M*32) Elpida EDW2032BBBG-50-FAKG5MGUT400

ROM_SO

N13P-LP 10K pull up.

ROM_SCLK

N13P-LP need 4.99K pull up;

2G:Hynix =4.99k pull down(M-die)

ROM_SI

2G:Hynix =24.9k pull down(A-die)

STRAP0

N13P-LP 45.3K pull high

STRAP1

N13P-LP 4.99k pull down

STRAP2

N13P-LP need 20K pull down.

STRAP3

STRAP3 N13P-LP need 4.99K pull down.

STRAP4

STRAP4 N13P-LP need 45.3K pull down for GEN3.

Strapping Bit2

N13P-LP FB[0] N13P-GL FB_0_BAR_SIZE

SUB_VENDOR

3GIO_PADCFG[2] PCI_DEVID[2]

PCIE_SPEED_ CHANGE_GEN3

N13P-LP PCI_DEVIDE[5] N13P-GL SLOT_CLK_CFG

VRAM Configuration Table

DESCRIPTION

Elpida Need confirmation with NV RVL Hynix H5GQ2H24AFR-T2C will build next or MP.

Register value

Quanta PN(Q buy)

AKG5MWDT505 AKG5MWUTW01 AKG5MWUTW10

ROM_SI Strap Bit for RAM Mapping N13P-LP DID => 0X0FD3

R46

R37

R42 *EV@4.99K/F_4

ROM_SI ROM_SO STRAP3 ROM_SCLK

R43

Hynix

EV@4.99K/F_4

EV@10K/F_4

R38 *EV@10K/F_4

EV@4.99K/F_4

R47 *EV@34.8K/F_4

STRAP0 STRAP1 STRAP2

6

LogicalLogical

Logical

Strapping Bit0

VGA_DEVICESMB_ALT_ADDR

PEX_PLL_EN_TERM

RAMCFG[1] USER[1] 3GIO_PADCFG[1] 3GIO_PADCFG[0]

PCI_MAX_SPEED DP_PLL_VDD33V

RAMCFG[0] USER[0]USER[3] USER[2]

PCI_DEVID[0] SOR_EXPOSED[0]SOR_EXPOSED[2]

Quanta PN(W buy)

+3V_GFX+3V_GFX +3V_GFX

N13P-LPN13P-LP

R81 EV@45.3K/F_4

R80 *EV@4.99K/F_4

R53 *EV@4.99K/F_4

13P-LP

R54 EV@4.99K/F_4

N13P-GS N13P-GL

1001

1010

xxxx

1111

0110

0011

0000

0001

Vendor PN

K4G20325FD-FC04 H5GQ2H24MFR-T2C H5GQ2H24AFR-T2C

R63 *EV@4.99K/F_4

R64 EV@20K/F_4

20120113 Strap1 NV change to PD 4.99K.

dGPU_OPP#

R651 *EV@10K_4

GPU_THAL#

R644 *EV@10K_4

GPU_TRIP#

R647 *EV@10K_4

JTAG_TMS_VT

R183 *EV@10K_4

JTAG_TDI

R184 *EV@10K_4

VGA_OVT#

R356 EV@10K_4

GPU_ALERT#

R434 EV@10K_4

JTAG_TDO

R299 *EV@10K_4

20120223 add PU resistor for ICT request.

JTAG_TRST#

R188 EV@10K_4

JTAG_CLK_VT

R189 *EV@10K_4

+3V

+3V_GFX

7

R66 *EV@34.8K/F_4

STRAP4

N13P-LPN

R67 EV@4.99K/F_4

Strap4 QS smple need PD 45.3K.

GPIOINACTIVE

I/O

OUT

0

OUT

1

OUT

2

OUT

3

OUT

4

OUT

5

OUT

6

OUT

7

I/O

8 9

OUT

10

OUT

11 12

OUT

13

IN

14

IN

15

OUT

16

IN

17

IN

18

IN

19

N/A

20

N/A

21

1000

1001

1010

1011

1100

1101

1110

1111

PD to GND

0000

0001

0010

0011

0100

0101

0110

0111

PU to VDD33

4.99K

10K

15K

20K

24.9K

30.1K

34.8K

45.3K

4.99K/F_4 ==> CS24992FB26 10K/F_4 ==> CS31002FB26 15K/F_4 ==> CS31502FB24 20K/F_4 ==> CS32002FB29

24.9K/F_4 ==> CS32492FB16

30.1K/F_4 ==> CS33012FB18

34.8K/F_4 ==> CS33482FB22

35.7K/F_4 ==> CS33572FB13

45.3K/F_4 ==> CS34532FB18

R77 *EV@10K/F_4

R78 EV@45.3K/F_4

GPIO ASSIGNMENTS

USAGE

NVVDD VID4

N/A

NVVDD VID3

N/A HIGH

PANEL BACKLIGHT PWM PANEL POWER ENABLE

HIGH

PANEL BACKLIGHT ENABLE

HIGH

NVVDD VID1

N/A

NVVDD VID2

N/A

3D STEREO

N/A LOW

GPU Overtemp GPU ALERT

LOWI/O

FB Vref Control (not used sDDR3)

N/A N/A

NVVDD VID0 PWR_Level AC Detect

N/A

NVVDD VID5

N/A

HPD for IFP AB (not used)

N/A

HPD for IFP C (HDMI)

N/A

MEM_VDD_CTL

N/A

HPD for IFP D (not used)

N/A

HPD for IFP E (TMDS)

N/A

HPD for IFP F (not used)

N/A

NVGEM Debug GPIO13

N/A

NVGEM Debug GPIO14

N/A

8

19

GF108:N12P GF117:N13M

GK107:N13P

Quanta Computer Inc.

ADDRESS: 98H

1

2

3

4

5

6

Size Document Number Rev

Date: Sheet of

7

Quanta Computer Inc.

PROJECT :

N13P-LP (GPIO&STRAPS)4/5

Monday, April 09, 2012

Z09

8

28 40

3A

1

+VGPU_CO RE

C482 EV@ 0.1U/10V_ 4 C491 EV@ 0.1U/10V_ 4 C509 EV@ 0.1U/10V_ 4 C490 EV@ 0.1U/10V_ 4 C470 EV@ 0.1U/10V_ 4 C469 EV@ 0.1U/10V_ 4

+VGPU_CO RE

C517 EV@ 0.1U/10V_ 4 C483 EV@ 0.1U/10V_ 4

C480 EV@ 4.7U/6.3V_ 6 C514 EV@ 4.7U/6.3V_ 6 C495 EV@ 4.7U/6.3V_ 6 C481 EV@ 4.7U/6.3V_ 6 C502 EV@ 4.7U/6.3V_ 6 C487 EV@ 4.7U/6.3V_ 6 C511 EV@ 4.7U/6.3V_ 6 C479 EV@ 4.7U/6.3V_ 6 C493 EV@ 4.7U/6.3V_ 6 C468 EV@ 4.7U/6.3V_ 6

C503 EV@ 22U/6.3V_ 8 C126 EV@ 22U/6.3V_ 8 C556 EV@ 22U/6.3V_ 8 C485 EV@ 4.7U/6.3V_ 6 C478 EV@ 4.7U/6.3V_ 6 C496 EV@ 4.7U/6.3V_ 6 C515 EV@ 4.7U/6.3V_ 6 C494 EV@ 4.7U/6.3V_ 6

C463 EV@ 4.7U/16V_ 8 C557 EV@ 4.7U/16V_ 8 C555 EV@ 4.7U/16V_ 8 C489 EV@ 4.7U/16V_ 8 C475 EV@ 4.7U/16V_ 8 C466 EV@ 22U/6.3V_ 8 C505 EV@ 47U/4V_8

C594

+

EV@330u/2 V_7343

1

PLACE UNDER BALLS

A A

B B

C C

D D

+VGPU_CO RE

AA12 AA14 AA16 AA19 AA21 AA23 AB13 AB15 AB17 AB18 AB20 AB22 AC12 AC14 AC16 AC19 AC21 AC23

M12 M14 M16 M19 M21 M23

N13 N15 N17 N18 N20 N22 P12 P14 P16 P19 P21 P23 R13 R15 R17 R18 R20 R22 T12 T14 T16 T19 T21 T23 U13 U15 U17 U18 U20 U22 V13 V15 V17 V18 V20

V22 W12 W14 W16 W19 W21 W23

Y13

Y15

Y17

Y18

Y20

Y22

2

VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD

2

14/19 NVVDD

EV@U_GPU_ GB4_12 8

U6E

PLACE NEAR BALLS

+1.5V_GF X

PLACE UNDER BALLS

U6F

18/19 NC/VDD33

AC6

NC

AJ28

NC

AJ4

NC

AJ5

NC

AL11

NC

C15

NC

D19

NC

D20

NC

D23

NC

D26

NC

H31

NC

T8

NC

V32

NC

EV@U_GPU_ GB4_12 8

3

C484 EV@ 0.1U/10V_ 4 C446 EV@ 0.1U/10V_ 4 C500 EV@ 0.1U/10V_ 4 C531 EV@ 0.1U/10V_ 4 C452 EV@ 0.1U/10V_ 4 C467 EV@ 0.1U/10V_ 4 C445 EV@ 0.1U/10V_ 4 C449 EV@ 0.1U/10V_ 4

C454 EV@ 1U/10V_6 C477 EV@ 1U/10V_6

C465 EV@ 4.7U/6.3V_ 6 C542 EV@ 4.7U/6.3V_ 6

C462 EV@ 10U/6.3V_ 8 C471 EV@ 10U/6.3V_ 8 C461 EV@ 10U/6.3V_ 8 C455 EV@ 10U/6.3V_ 8

R481

EV@0_6

J8

VDD33

K8

VDD33

L8

VDD33

M8

VDD33

3

+3V_GFX

1

Q31

2

*EV@AO34 04

3

C451 EV@0 .1U/10V_4 C459 EV@0 .1U/10V_4 C456 EV@1 U/10V_6 C501 EV@4 .7U/6.3V_6

+3V_GFX

C472 EV@ 0.1U/10V_ 4 C460 EV@ 0.1U/10V_ 4 C473 EV@ 1U/10V_6 C474 EV@ 4.7U/6.3V_ 6

U6D

15/19 FBVDDQ

AA27

FBVDDQ

AA30

FBVDDQ

AB27

FBVDDQ

AB33

FBVDDQ

AC27

FBVDDQ

AD27

FBVDDQ

AE27

FBVDDQ

AF27

FBVDDQ

AG27

FBVDDQ

B13

FBVDDQ

B16

FBVDDQ

B19

FBVDDQ

E13

FBVDDQ

E16

FBVDDQ

E19

FBVDDQ

H10

FBVDDQ

H11

FBVDDQ

H12

FBVDDQ

H13

FBVDDQ

H14

FBVDDQ

H15

FBVDDQ

H16

FBVDDQ

H18

FBVDDQ

H19

FBVDDQ

H20

FBVDDQ

H21

FBVDDQ

H22

FBVDDQ

H23

FBVDDQ

H24

FBVDDQ

H8

FBVDDQ

H9

FBVDDQ

L27

FBVDDQ

M27

FBVDDQ

N27

FBVDDQ

P27

FBVDDQ

R27

FBVDDQ

T27

FBVDDQ

T30

FBVDDQ

T33

FBVDDQ

V27

FBVDDQ

W27

FBVDDQ

W30

FBVDDQ

W33

FBVDDQ

Y27

FBVDDQ

FB_CALTERM_GND

EV@U_GPU_ GB4_12 8

150mA Width : 15mil

DGPU_D <39>

3V3MISC

PLACE UNDER BALLS

PLACE NEAR BALLS

PLACE UNDER BALLS

PLACE NEAR BALLS

FBVDDQ_PROBE

GND_PROBE

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

4

F1

FBVDDQ _SENSE_ P

F2

FBVDDQ _SENSE_ N

J27

FB_CAL _PD_VD DQ

H27

FB_CAL _PU_GND

H25

FB_CAL TERM_GND

4

NVDD Turbo:40A NVDD P0:21A NVDD EDP:30A

1.5V_GFX GDDR5:9A

1.05V_GFX:3.5A

TP91

TP92

R456 EV@ 40.2/F_4

+1.5V_GF X

R455 EV@ 40.2/F_4

R447 EV@ 60.4/F_4

PLACE NEAR BALLS

5

U6G

A2

GND

AA17

GND

AA18

GND

AA20

GND

AA22

GND

AB12

GND

AB14

GND

AB16

GND

AB19

GND

AB2

GND

AB21

GND

A33

GND

AB23

GND

AB28

GND

AB30

GND

AB32

GND

AB5

GND

AB7

GND

AC13

GND

AC15

GND

AC17

GND

AC18

GND

AA13

GND

AC20

GND

AC22

GND

AE2

GND

AE28

GND

AE30

GND

AE32

GND

AE33

GND

AE5

GND

AE7

GND

AH10

GND

AA15

GND

AH13

GND

AH16

GND

AH19

GND

AH2

GND

AH22

GND

AH24

GND

AH28

GND

AH29

GND

AH30

GND

AH32

GND

AH33

GND

AH5

GND

AH7

GND

AJ7

GND

AK10

GND

AK7

GND

AL12

GND

AL14

GND

AL15

GND

AL17

GND

AL18

GND

AL2

GND

AL20

GND

AL21

GND

AL23

GND

AL24

GND

AL26

GND

AL28

GND

AL30

GND

AL32

GND

AL33

GND

AL5

GND

AM13

GND

AM16

GND

AM19

GND

AM22

GND

EV@U_GPU_ GB4_12 8

5

6

16/19 GND_1/2

AM25

GND

AN1

GND

AN10

GND

AN13

GND

AN16

GND

AN19

GND

AN22

GND

AN25

GND

AN30

GND

AN34

GND

AN4

GND

AN7

GND

AP2

GND

AP33

GND

B1

GND

B10

GND

B22

GND

B25

GND

B28

GND

B31

GND

B34

GND

B4

GND

B7

GND

C10

GND

C13

GND

C19

GND

C22

GND

C25

GND

C28

GND

C7

GND

D2

GND

D31

GND

D33

GND

E10

GND

E22

GND

E25

GND

E5

GND

E7

GND

F28

GND

F7

GND

G10

GND

G13

GND

G16

GND

G19

GND

G2

GND

G22

GND

G25

GND

G28

GND

G3

GND

G30

GND

G32

GND

G33

GND

G5

GND

G7

GND

K2

GND

K28

GND

K30

GND

K32

GND

K33

GND

K5

GND

K7

GND

M13

GND

M15

GND

M17

GND

M18

GND

M20

GND

M22

GND

N12

GND

N14

GND

N16

GND

AG11

U6H

10/19 XVDD

CONFIGURABLE POWER CHANNELS

N19

N2 N21 N23 N28 N30 N32 N33

N5

N7 P13 P15 P17 P18 P20 P22 R12 R14 R16 R19 R21 R23 T13 T15 T17 T18

T2 T20 T22

EV@U_GPU_ GB4_12 8

1.Level 1 Environment-related Substances Should Never be Used.

2.Recycled Resin and Coated Wire should be procured from Green Partners.

6

7

U6I

17/19 GND_2/2

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

GND

Optional CMD GNDs (2) NC for 4-Lyr cards

EV@U_GPU_ GB4_12 8

T28

GND

T32

GND

T5

GND

T7

GND

U12

GND

U14

GND

U16

GND

U19

GND

U21

GND

U23

GND

V12

GND

V14

GND

V16

GND

V19

GND

V21

GND

V23

GND

W13

GND

W15

GND

W17

GND

W18

GND

W20

GND

W22

GND

W28

GND

Y12

GND

Y14

GND

Y16

GND

Y19

GND

Y21

GND

Y23

GND

AH11

GND

C16

GND_OPT

W32

GND_OPT

U1

XVDD

U2

XVDD

U3

XVDD

U4

XVDD

U5

XVDD

U6

XVDD

U7

XVDD

U8

XVDD

V1

XVDD

V2

XVDD

V3

XVDD

V4

XVDD

V5

XVDD

V6

XVDD

V7

XVDD

V8

XVDD

To be configured as neede d on the PCB

W2

XVDD

W3

XVDD

W4

XVDD

W5

XVDD

W7

XVDD

W8

XVDD

Y1

XVDD

Y2

XVDD

Y3

XVDD

Y4

XVDD

Y5

XVDD

Y6

XVDD

Y7

XVDD

Y8

XVDD

AA1

XVDD

AA2

XVDD

AA3

XVDD

AA4

XVDD

AA5

XVDD

AA6

XVDD

AA7

XVDD

AA8

XVDD

Size Document Num ber Rev

N13P-LP(POWER&THM)5/5

Date: Sheet of

Monday, April 09, 2 012

Date: Sheet of

Monday, April 09, 2 012

Date: Sheet of

Monday, April 09, 2 012

7

8

Quanta Computer Inc.

PROJECT :

Z09

PROJECT :

Z09

PROJECT :

Z09

29 4 0

8

3A

1

VMA_DQ[63..0]

VMA_DQ[63..0]<26>

FBA_DBI[7..0]

FBA_DBI[7..0]<26>

FBA_EDC[7..0]

FBA_EDC[7..0]<26>

VMB_DQ[63..0]

VMB_DQ[63..0]<26>

FBC_DBI[7..0]

FBC_DBI[7..0]<26>

FBC_EDC[7..0]

FBC_EDC[7..0]<26>

VMA_DQ31 VMA_DQ30 VMA_DQ29 VMA_DQ28 VMA_DQ27

A A

QD24~31

QD16~23

QD8~15

QD0~7

B B

C C

FBA_CMD8<26>

VMA_CLKP0

VMA_CLKP1

R426

R500

EV@80.6/F_4

VMA_CLKN0

VMA_CLKN1

D D

+1.5V_GFX

+

C73 EV@330u/2V_7343

EV@0.1u/16V_4C764 C408 EV@10U/6.3V_6 C399 EV@10U/6.3V_6 C447 EV@10U/6.3V_6

201201117 Add C764 for EMI suggestion.

1

VMA_DQ26 VMA_DQ25 VMA_DQ24 VMA_DQ23 VMA_DQ22 VMA_DQ21 VMA_DQ20 VMA_DQ19 VMA_DQ18 VMA_DQ17 VMA_DQ16 VMA_DQ15 VMA_DQ14 VMA_DQ13 VMA_DQ12 VMA_DQ11 VMA_DQ10 VMA_DQ9 VMA_DQ8 VMA_DQ7 VMA_DQ6 VMA_DQ5 VMA_DQ4 VMA_DQ3 VMA_DQ2 VMA_DQ1 VMA_DQ0

FBA_CMD9<26> FBA_CMD6<26> FBA_CMD7<26> FBA_CMD4<26> FBA_CMD3<26> FBA_CMD1<26> FBA_CMD2<26> FBA_CMD11<26> FBA_CMD10<26>

VMA_WCK01<26> VMA_WCK01#<26>

VMA_WCK23<26> VMA_WCK23#<26>

FBA_EDC3 FBA_EDC2 FBA_EDC1 FBA_EDC0

FBA_DBI3 FBA_DBI2 FBA_DBI1 FBA_DBI0

FBA_CMD12<26> FBA_CMD15<26>

FBA_CMD14<26> VMA_CLKN0<26> VMA_CLKP0<26>

FBA_CMD0<26> FBA_CMD5<26>

R415 EV@120/F_4

SEN_A

R438 EV@1K_4

FBA_CMD13<26>

R465 EV@1K_4

VREFD_VMA1

12

C442 EV@820P/50V_4

12

C441 EV@820P/50V_4

12

C432 EV@820P/50V_4

+1.5V_GFX +1.5V_GFX +1.5V_GFX +1.5V_GFX

R417

EV@931/F_4

EV@549/F_4

VREFC_VMA1 VREFD_VMA1

R416

EV@1.33K/F_4

+1.5V_GFX +1.5V_GFX +1.5V_GFX +1.5V_GFX

Channel 0 <0-31>

U5

M2

DQ31 | DQ7

M4

DQ30 | DQ6

N2

DQ29 | DQ5

N4

DQ28 | DQ4

T2

DQ27 | DQ3

T4

DQ26 | DQ2

U2

DQ25 | DQ1

U4

DQ24 | DQ0

M13

DQ23 | DQ15

M11

DQ22 | DQ14

N13

DQ21 | DQ13

N11

DQ20 | DQ12

T13

DQ19 | DQ11

T11

DQ18 | DQ10

U13

DQ17 | DQ9

U11

DQ16 | DQ8

F13

DQ15 | DQ23

F11

DQ14 | DQ22

E13

DQ13 | DQ21

E11

DQ12 | DQ20

B13

DQ11 | DQ19

B11

DQ10 | DQ18

A13

DQ9 | DQ17

A11

DQ8 | DQ16

F2

DQ7 | DQ31

F4

DQ6 | DQ30

E2

DQ5 | DQ29

E4

DQ4 | DQ28

B2

DQ3 | DQ27

B4

DQ2 | DQ26

A2

DQ1 | DQ25

A4

DQ0 | DQ24

J5

RFU/A12/NC

K4

A7/A8 | A0/A10

K5

A6/A11 | A1/A9

K10

A5/BA1 | A3/BA3

K11

A4/BA2 | A2/BA0

H10

A3/BA3 | A5/BA1

H11

A2 /BA0 | A4/BA2

H5

A1/A9 | A6/A11

H4

A0/A10 | A7/A8

D4

WCK01 | WCK23

D5

WCK01# | WCK23#

P4

WCK23 | WCK01

P5

WCK23# | WCK01#

R2

EDC3 | EDC0

R13

EDC2 | EDC1

C13

EDC1 | EDC2

C2

EDC0 | EDC3

P2

DBI3# | DBI0#

P13

DBI2 #| DBI1#

D13

DBI1# | DBI2#

D2

DBI0# | DBI3#

G3

RAS# | CAS#

L3

CAS# | RAS#

J3

CKE#

J11

CK#

J12

CK

G12

CS# | WE#

L12

WE# | CS#

J13

ZQ

J10

SEN

J2

RESET#

J1

MF

A5

Vpp,NC

U5

Vpp,NC1

A10

VREFD1

U10

VREFD2

J14

VREFC

J4

ABI#

EV@GDDR5

VREF_VMA1_MOS

R410

R442

EV@549/F_4

1 2

R441

EV@1.33K/F_4

C394 EV@1u/6.3V_4 C538 EV@1u/6.3V_4 C498 EV@1u/6.3V_4 C549 EV@0.047u/10V_4 C440 EV@0.047u/10V_4

EV@0.1u/16V_4C413 EV@0.1u/16V_4C396 EV@0.1u/16V_4C499 EV@0.1u/16V_4C19

2

3

4

5

CHANNEL A: 1024MB GDDR5x32

MF=1 MirroredMF=0 Non-mirrored

VMA_DQ39 VMA_DQ38 VMA_DQ37 VMA_DQ36 VMA_DQ35 VMA_DQ34 VMA_DQ33 VMA_DQ32 VMA_DQ47 VMA_DQ46 VMA_DQ45 VMA_DQ44 VMA_DQ43 VMA_DQ42 VMA_DQ41 VMA_DQ40 VMA_DQ55 VMA_DQ54 VMA_DQ53 VMA_DQ52 VMA_DQ51 VMA_DQ50 VMA_DQ49 VMA_DQ48 VMA_DQ63 VMA_DQ62 VMA_DQ61 VMA_DQ60 VMA_DQ59 VMA_DQ58 VMA_DQ57 VMA_DQ56

12 12

VREFC_VMA2 VREFC_VMC1 VREFC_VMC2VREFC_VMA1

12

C551 EV@820P/50V_4

VREF_VMA1_MOS

3

Q29

EV@2N7002D

1

C439 EV@1u/6.3V_4 C421 EV@1u/6.3V_4 C422 EV@1u/6.3V_4 C513 EV@1u/6.3V_4

Channel 0 <32-63>

U7

M2

DQ31 | DQ7

M4

DQ30 | DQ6

N2

DQ29 | DQ5

N4

DQ28 | DQ4

T2

DQ27 | DQ3

T4

DQ26 | DQ2

U2

DQ25 | DQ1

U4

DQ24 | DQ0

M13

DQ23 | DQ15

M11

DQ22 | DQ14

N13

DQ21 | DQ13

N11

DQ20 | DQ12

T13

DQ19 | DQ11

T11

DQ18 | DQ10

U13

DQ17 | DQ9

U11

DQ16 | DQ8

F13

DQ15 | DQ23

F11

DQ14 | DQ22

E13

DQ13 | DQ21

E11

DQ12 | DQ20

B13

DQ11 | DQ19

B11

DQ10 | DQ18

A13

DQ9 | DQ17

A11

DQ8 | DQ16

F2

DQ7 | DQ31

F4

DQ6 | DQ30

E2

DQ5 | DQ29

E4

DQ4 | DQ28

B2

DQ3 | DQ27

B4

DQ2 | DQ26

A2

DQ1 | DQ25

A4

DQ0 | DQ24

J5

RFU/A12/NC

K4

A7/A8 | A0/A10

K5

A6/A11 | A1/A9

K10

A5/BA1 | A3/BA3

K11

A4/BA2 | A2/BA0

H10

A3/BA3 | A5/BA1

H11

A2 /BA0 | A4/BA2

H5

A1/A9 | A6/A11

H4

A0/A10 | A7/A8

D4

WCK01 | WCK23

D5

WCK01# | WCK23#

P4

WCK23 | WCK01

P5

WCK23# | WCK01#

R2

EDC3 | EDC0

R13

EDC2 | EDC1

C13

EDC1 | EDC2

C2

EDC0 | EDC3

P2

DBI3# | DBI0#

P13

DBI2 #| DBI1#

D13

DBI1# | DBI2#

D2

DBI0# | DBI3#

G3

RAS# | CAS#

L3

CAS# | RAS#

J3

CKE#

J11

CK#

J12

CK

G12

CS# | WE#

L12

WE# | CS#

J13

ZQ

J10

SEN

J2

RESET#

J1

MF

A5

Vpp,NC

U5

Vpp,NC1

A10

VREFD1

U10

VREFD2

J14

VREFC

J4

ABI#

EV@GDDR5

2

GPIO10_VREF <28>

EV@0.1u/16V_4C388 EV@0.1u/16V_4C436 EV@0.1u/16V_4C423 *EV@0.1u/16V_4C418 *EV@0.1u/16V_4C415 *EV@0.1u/16V_4C504

VDDQ-B1

VDDQ-B3 VDDQ-B12 VDDQ-B14

VDDQ-D1

VDDQ-D3 VDDQ-D12 VDDQ-D14

VDDQ-E5 VDDQ-E10

VDDQ-F1

VDDQ-F3 VDDQ-F12 VDDQ-F14

VDDQ-G2

VDDQ-G13

VDDQ-H3 VDDQ-H12

VDDQ-K3 VDDQ-K12

VDDQ-L2

VDDQ-L13 VDDQ-M1

VDDQ-M3 VDDQ-M12 VDDQ-M14

VDDQ-N5

VDDQ-N10

VDDQ-P1

VDDQ-P3 VDDQ-P12 VDDQ-P14

VDDQ-T1

VDDQ-T3 VDDQ-T12 VDDQ-T14

VDD-C10

VDD-D11

VDD-G11

VDD-G14

VDD-L11

VDD-L14

VDD-P11

VDD-R10

VSSQ-A1

VSSQ-A3

VSSQ-A12 VSSQ-A14

VSSQ-C1

VSSQ-C3

VSSQ-C4 VSSQ-C11 VSSQ-C12 VSSQ-C14

VSSQ-E1

VSSQ-E3

VSSQ-E12 VSSQ-E14

VSSQ-F5

VSSQ-F10

VSSQ-H2 VSSQ-H13

VSSQ-K2

VSSQ-K13

VSSQ-M5 VSSQ-M10

VSSQ-N1

VSSQ-N3 VSSQ-N12 VSSQ-N14

VSSQ-R1

VSSQ-R3

VSSQ-R4 VSSQ-R11 VSSQ-R12 VSSQ-R14

VSSQ-V1

VSSQ-V3

VSSQ-V12 VSSQ-V14

VSS-B10

VSS-D10

VSS-G10

VSS-H14

VSS-K14

VSS-L10

VSS-P10

VSS-T10

VDD-C5

VDD-G1 VDD-G4

VDD-L1 VDD-L4

VDD-R5

VSS-B5

VSS-G5 VSS-H1 VSS-K1 VSS-L5

VSS-T5

B1 B3 B12 B14 D1 D3 D12 D14 E5 E10 F1 F3 F12 F14 G2 G13 H3 H12 K3 K12 L2 L13 M1 M3 M12 M14 N5 N10 P1 P3 P12 P14 T1 T3 T12 T14

C5 C10 D11 G1 G4 G11 G14 L1 L4 L11 L14 P11 R5 R10

A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12 E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 U1 U3 U12 U14

B5 B10 D10 G5 G10 H1 H14 K1 K14 L5 L10 P10 T5 T10

U7

C402 EV@1u/6.3V_4 C403 EV@1u/6.3V_4 C457 EV@1u/6.3V_4 C419 EV@0.047u/10V_4 C420 EV@0.047u/10V_4

4

EV@0.1u/16V_4C438

EV@0.1u/16V_4C544 EV@0.1u/16V_4C458 EV@0.1u/16V_4C450 EV@0.1u/16V_4C414

MF=0 Non-mirrored

VMB_DQ31 VMB_DQ30 VMB_DQ29 VMB_DQ28 VMB_DQ27

QD24~31 QD16~23

QD8~15

VMC_WCK01<26> VMC_WCK01#<26> VMC_WCK67#<26>

VMC_WCK23<26> VMC_WCK23#<26>

FBC_CMD8<26>

VMB_DQ26 VMB_DQ25

VMB_DQ24 VMB_DQ23 VMB_DQ22 VMB_DQ21 VMB_DQ20 VMB_DQ19 VMB_DQ18 VMB_DQ17 VMB_DQ16

VMB_DQ15

VMB_DQ14

VMB_DQ13

VMB_DQ12

VMB_DQ11

VMB_DQ10

VMB_DQ9

VMB_DQ8

VMB_DQ7

VMB_DQ6 VMB_DQ5

VMB_DQ4 VMB_DQ3

VMB_DQ2

VMB_DQ1

VMB_DQ0

FBC_CMD9<26> FBC_CMD6<26> FBC_CMD7<26> FBC_CMD4<26> FBC_CMD3<26> FBC_CMD1<26> FBC_CMD2<26> FBC_CMD11<26> FBC_CMD10<26>

FBC_EDC3 FBC_EDC2 FBC_EDC1 FBC_EDC0

FBC_DBI3 FBC_DBI2 FBC_DBI1 FBC_DBI0

FBC_CMD12<26> FBC_CMD15<26>

FBC_CMD14<26> VMC_CLKN0<26> VMC_CLKP0<26>

FBC_CMD0<26> FBC_CMD5<26>

R335 EV@120/F_4

SEN_B

R323 EV@1K_4

FBC_CMD13<26>

R328 EV@1K_4

VREFD_VMC1VREFD_VMA2

12

C390 EV@820P/50V_4

12

C428 EV@820P/50V_4

12

C409 EV@820P/50V_4

FBC_CMD14 FBC_CMD30

FBA_CMD14 FBA_CMD30

CKE* is strap pin to set ODT value of memory chip

FBA_CMD13 FBA_CMD29

FBC_CMD13 FBC_CMD29

RST PD place @ the end of da isy-chain.

5

LOWER HALF UPPER HALF

+1.5V_GFX +1.5V_GFX

B1

VDDQ-B1

B3

VDDQ-B3

B12

VDDQ-B12

B14

VDDQ-B14

D1

QD32~39

D3 D12 D14 E5 E10 F1 F3 F12

QD40~47

F14 G2 G13 H3 H12 K3 K12 L2

QD48~55

L13 M1 M3 M12 M14 N5 N10 P1

QD56~63 QD0~7

P3 P12 P14 T1 T3 T12 T14

C5 C10 D11 G1 G4 G11 G14 L1 L4 L11 L14 P11 R5 R10

A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12 E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 U1 U3 U12 U14

B5 B10 D10 G5 G10 H1 H14 K1 K14 L5 L10 P10 T5 T10

U5

EV@931/F_4

R509

EV@549/F_4

VREFC_VMA2 VREFD_VMA2

R508

EV@1.33K/F_4

C448 EV@1u/6.3V_4 C401 EV@1u/6.3V_4 C398 EV@1u/6.3V_4 C543 EV@1u/6.3V_4 C391 EV@0.047u/10V_4 C377 EV@0.047u/10V_4

R513

+1.5V_GFX

FBA_CMD24<26>

VREF_VMA1_MOS

R485

EV@549/F_4

1 2

R496

EV@1.33K/F_4

EV@0.1u/16V_4C497 EV@0.1u/16V_4C386 EV@0.1u/16V_4C435 EV@0.1u/16V_4C537

FBA_CMD25<26> FBA_CMD26<26> FBA_CMD27<26> FBA_CMD17<26> FBA_CMD18<26> FBA_CMD20<26> FBA_CMD19<26> FBA_CMD23<26> FBA_CMD22<26>

VMA_WCK67<26> VMA_WCK67#<26>

VMA_WCK45<26> VMA_WCK45#<26>

FBA_CMD31<26> FBA_CMD28<26>

FBA_CMD30<26> VMA_CLKN1<26> VMA_CLKP1<26>

FBA_CMD21<26> FBA_CMD16<26>

R510 EV@120/F_4

FBA_CMD29<26>

R471 EV@1K_4

R495

EV@931/F_4

FBA_EDC4 FBA_EDC5 FBA_EDC6 FBA_EDC7

FBA_DBI4 FBA_DBI5 FBA_DBI6 FBA_DBI7

C530 EV@820P/50V_4 C541 EV@820P/50V_4

1 2

3

R446

EV@931/F_4

2

VDDQ-D1

VDDQ-D3 VDDQ-D12 VDDQ-D14

VDDQ-E5 VDDQ-E10

VDDQ-F1

VDDQ-F3 VDDQ-F12 VDDQ-F14

VDDQ-G2

VDDQ-G13

VDDQ-H3

VDDQ-H12

VDDQ-K3

VDDQ-K12

VDDQ-L2 VDDQ-L13

VDDQ-M1

VDDQ-M3 VDDQ-M12 VDDQ-M14

VDDQ-N5 VDDQ-N10

VDDQ-P1

VDDQ-P3 VDDQ-P12 VDDQ-P14

VDDQ-T1

VDDQ-T3 VDDQ-T12 VDDQ-T14

VDD-C5 VDD-C10 VDD-D11

VDD-G1

VDD-G4 VDD-G11 VDD-G14

VDD-L11 VDD-L14 VDD-P11

VDD-R5 VDD-R10

VSSQ-A1 VSSQ-A3

VSSQ-A12 VSSQ-A14

VSSQ-C1 VSSQ-C3 VSSQ-C4

VSSQ-C11 VSSQ-C12 VSSQ-C14

VSSQ-E1 VSSQ-E3

VSSQ-E12 VSSQ-E14

VSSQ-F5

VSSQ-F10

VSSQ-H2

VSSQ-H13

VSSQ-K2

VSSQ-K13

VSSQ-M5

VSSQ-M10

VSSQ-N1 VSSQ-N3

VSSQ-N12 VSSQ-N14

VSSQ-R1 VSSQ-R3 VSSQ-R4

VSSQ-R11 VSSQ-R12 VSSQ-R14

VSSQ-V1 VSSQ-V3

VSSQ-V12 VSSQ-V14

VSS-B10 VSS-D10

VSS-G10 VSS-H14 VSS-K14

VSS-L10 VSS-P10

VSS-T10

VDD-L1 VDD-L4

VSS-B5

VSS-G5 VSS-H1 VSS-K1 VSS-L5

VSS-T5

1 2

Channel 1 <0-31>

U3

M2

DQ31 | DQ7

M4

DQ30 | DQ6

N2

DQ29 | DQ5

N4

DQ28 | DQ4

T2

DQ27 | DQ3

T4

DQ26 | DQ2

U2

DQ25 | DQ1

U4

DQ24 | DQ0

M13

DQ23 | DQ15

M11

DQ22 | DQ14

N13

DQ21 | DQ13

N11

DQ20 | DQ12

T13

DQ19 | DQ11

T11

DQ18 | DQ10

U13

DQ17 | DQ9

U11

DQ16 | DQ8

F13

DQ15 | DQ23

F11

DQ14 | DQ22

E13

DQ13 | DQ21

E11

DQ12 | DQ20

B13

DQ11 | DQ19

B11

DQ10 | DQ18

A13

DQ9 | DQ17

A11

DQ8 | DQ16

F2

DQ7 | DQ31

F4

DQ6 | DQ30

E2

DQ5 | DQ29

E4

DQ4 | DQ28

B2

DQ3 | DQ27

B4

DQ2 | DQ26

A2

DQ1 | DQ25

A4

DQ0 | DQ24

J5

RFU/A12/NC

K4

A7/A8 | A0/A10

K5

A6/A11 | A1/A9

K10

A5/BA1 | A3/BA3

K11

A4/BA2 | A2/BA0

H10

A3/BA3 | A5/BA1

H11

A2 /BA0 | A4/BA2

H5

A1/A9 | A6/A11

H4

A0/A10 | A7/A8

D4

WCK01 | WCK23

D5

WCK01# | WCK23#

P4

WCK23 | WCK01

P5

WCK23# | WCK01#

R2

EDC3 | EDC0

R13

EDC2 | EDC1

C13

EDC1 | EDC2

C2

EDC0 | EDC3

P2

DBI3# | DBI0#

P13

DBI2 #| DBI1#

D13

DBI1# | DBI2#

D2

DBI0# | DBI3#

G3

RAS# | CAS#

L3

CAS# | RAS#

J3

CKE#

J11

CK#

J12

CK

G12

CS# | WE#

L12

WE# | CS#

J13

ZQ

J10

SEN

J2

RESET#

J1

MF

A5

Vpp,NC

U5

Vpp,NC1

A10

VREFD1

U10

VREFD2

J14

VREFC

J4

ABI#

EV@GDDR5

VREF_VMA3_MOS

3

Q15

2

EV@2N7002D

1

R308 EV@10K_4 R309 EV@10K_4

R467 EV@10K_4 R473 EV@10K_4

R466 EV@10K_4 R472 EV@10K_4

R318 EV@10K_4 R319 EV@10K_4

VDDQ-B1

VDDQ-B3 VDDQ-B12 VDDQ-B14

VDDQ-D1

VDDQ-D3 VDDQ-D12 VDDQ-D14

VDDQ-E5 VDDQ-E10

VDDQ-F1

VDDQ-F3 VDDQ-F12 VDDQ-F14

VDDQ-G2 VDDQ-G13

VDDQ-H3 VDDQ-H12

VDDQ-K3 VDDQ-K12

VDDQ-L2

VDDQ-L13

VDDQ-M1

VDDQ-M3 VDDQ-M12 VDDQ-M14

VDDQ-N5 VDDQ-N10

VDDQ-P1

VDDQ-P3 VDDQ-P12 VDDQ-P14

VDDQ-T1

VDDQ-T3 VDDQ-T12 VDDQ-T14

VDD-C5 VDD-C10 VDD-D11

VDD-G1

VDD-G4 VDD-G11 VDD-G14

VDD-L1

VDD-L4 VDD-L11 VDD-L14 VDD-P11

VDD-R5 VDD-R10

VSSQ-A1 VSSQ-A3

VSSQ-A12 VSSQ-A14

VSSQ-C1 VSSQ-C3

VSSQ-C4 VSSQ-C11 VSSQ-C12 VSSQ-C14

VSSQ-E1

VSSQ-E3 VSSQ-E12 VSSQ-E14

VSSQ-F5 VSSQ-F10

VSSQ-H2

VSSQ-H13

VSSQ-K2 VSSQ-K13

VSSQ-M5

VSSQ-M10

VSSQ-N1

VSSQ-N3 VSSQ-N12 VSSQ-N14

VSSQ-R1

VSSQ-R3

VSSQ-R4 VSSQ-R11 VSSQ-R12 VSSQ-R14

VSSQ-V1

VSSQ-V3 VSSQ-V12 VSSQ-V14

VSS-B5 VSS-B10 VSS-D10

VSS-G5 VSS-G10

VSS-H1 VSS-H14

VSS-K1 VSS-K14

VSS-L5 VSS-L10 VSS-P10

VSS-T5

VSS-T10

GPIO10_VREF <28>

+1.5V_GFX

6

B1 B3 B12 B14 D1 D3 D12 D14 E5 E10 F1 F3 F12 F14 G2 G13 H3 H12 K3 K12 L2 L13 M1 M3 M12 M14 N5 N10 P1 P3 P12 P14 T1 T3 T12 T14

C5 C10 D11 G1 G4 G11 G14 L1 L4 L11 L14 P11 R5 R10

A1 A3 A12 A14 C1 C3 C4 C11 C12 C14 E1 E3 E12 E14 F5 F10 H2 H13 K2 K13 M5 M10 N1 N3 N12 N14 R1 R3 R4 R11 R12 R14 U1 U3 U12 U14

B5 B10 D10 G5 G10 H1 H14 K1 K14 L5 L10 P10 T5 T10

U3

6

QD32~39

QD40~47

QD48~55

QD56~63

+1.5V_GFX

FBC_CMD24<26>

R330

EV@931/F_4

R331

EV@549/F_4

VREFC_VMC1 VREFD_VMC1

R337

EV@1.33K/F_4

VMC_WCK67<26>

VMC_WCK45<26> VMC_WCK45#<26>

1 2

EV@1.33K/F_4

GDDR5 Mode H M apping

< 0-31 > < 32-63 > Memory

CMD0 CMD16 CS* CMD1 CMD17 A3_BA3 CMD2 CMD18 A2_BA0 CMD3 CMD19 A4_BA2 CMD4 CMD20 A5_BA1 CMD5 CMD21 WE* CMD6 CMD22 A7_A8 CMD7 CMD23 A6_A11 CMD8 CMD24 ABI* CMD9 CMD25 A12_RFU CMD10 CMD26 A0_A10 CMD11 CMD27 A1_A9 CMD12 CMD28 RAS* CMD13 CMD29 RST* CMD14 CMD30 CKE* CMD15 CMD31 CAS*

FBC_CMD25<26> FBC_CMD26<26> FBC_CMD27<26> FBC_CMD17<26> FBC_CMD18<26> FBC_CMD20<26> FBC_CMD19<26> FBC_CMD23<26> FBC_CMD22<26>

FBC_EDC4 FBC_EDC5 FBC_EDC6 FBC_EDC7

FBC_DBI4 FBC_DBI5 FBC_DBI6 FBC_DBI7

FBC_CMD31<26> FBC_CMD28<26>

FBC_CMD30<26> VMC_CLKN1<26> VMC_CLKP1<26>

FBC_CMD21<26> FBC_CMD16<26>

R333 EV@120/F_4

FBC_CMD29<26>

R329 EV@1K_4

VREFD_VMC2

C384 EV@820P/50V_4 C427 EV@820P/50V_4

C416 EV@820P/50V_4

VREF_VMA3_MOS

R312

EV@549/F_4

R325

7

Channel 1 <32-63>

MF=1 Mirrored

U4

M2

VMB_DQ39

DQ31 | DQ7

M4

VMB_DQ38

DQ30 | DQ6

N2

VMB_DQ37

DQ29 | DQ5

N4

VMB_DQ36

DQ28 | DQ4

T2

VMB_DQ35

DQ27 | DQ3

T4

VMB_DQ34

DQ26 | DQ2

U2

VMB_DQ33

DQ25 | DQ1

U4

VMB_DQ32

DQ24 | DQ0

M13

VMB_DQ47

DQ23 | DQ15

M11

VMB_DQ46

DQ22 | DQ14

N13

VMB_DQ45

DQ21 | DQ13

N11

VMB_DQ44

DQ20 | DQ12

T13

VMB_DQ43

DQ19 | DQ11

T11

VMB_DQ42

DQ18 | DQ10

U13

VMB_DQ41

DQ17 | DQ9

U11

VMB_DQ40

DQ16 | DQ8

F13

VMB_DQ55

DQ15 | DQ23

F11

VMB_DQ54

DQ14 | DQ22

E13

VMB_DQ53

DQ13 | DQ21

E11

VMB_DQ52

DQ12 | DQ20

B13

VMB_DQ51

DQ11 | DQ19

B11

VMB_DQ50

DQ10 | DQ18

A13

VMB_DQ49

DQ9 | DQ17

A11

VMB_DQ48

DQ8 | DQ16

F2

VMB_DQ63

DQ7 | DQ31

F4

VMB_DQ62

DQ6 | DQ30

E2

VMB_DQ61

DQ5 | DQ29

E4

VMB_DQ60

DQ4 | DQ28

B2

VMB_DQ59

DQ3 | DQ27

B4

VMB_DQ58

DQ2 | DQ26

A2

VMB_DQ57

DQ1 | DQ25

A4

VMB_DQ56

DQ0 | DQ24

J5

RFU/A12/NC

K4

A7/A8 | A0/A10

K5

A6/A11 | A1/A9

K10

A5/BA1 | A3/BA3

K11

A4/BA2 | A2/BA0

H10

A3/BA3 | A5/BA1

H11

A2 /BA0 | A4/BA2

H5

A1/A9 | A6/A11

H4

A0/A10 | A7/A8

D4

WCK01 | WCK23

D5

WCK01# | WCK23#

P4

WCK23 | WCK01

P5

WCK23# | WCK01#

R2

EDC3 | EDC0

R13

EDC2 | EDC1

C13

EDC1 | EDC2

C2

EDC0 | EDC3

P2

DBI3# | DBI0#

P13

DBI2 #| DBI1#

D13

DBI1# | DBI2#

D2

DBI0# | DBI3#

G3

RAS# | CAS#

L3

CAS# | RAS#

J3

CKE#

J11

CK#

J12

CK

G12

CS# | WE#

L12

WE# | CS#

J13

ZQ

J10

SEN_BSEN_A

SEN

J2

RESET#

J1

MF

A5

Vpp,NC

U5

Vpp,NC1

A10

VREFD1

U10

VREFD2

12 12

J14

VREFC

12

J4

ABI#

EV@GDDR5

+1.5V_GFX +1.5V_GFX+1.5V_GFX +1.5V_GFX

R301

EV@931/F_4

R381

EV@931/F_4

EV@549/F_4

1 2

VREFC_VMC2 VREFD_VMC2

R367

EV@1.33K/F_4

Size Document Number Rev

Date: Sheet of

7

B1

VDDQ-B1

B3

VDDQ-B3

B12

VDDQ-B12

B14

VDDQ-B14

D1

VDDQ-D1

D3

VDDQ-D3

D12

VDDQ-D12

D14

VDDQ-D14

E5

VDDQ-E5

E10

VDDQ-E10

F1

VDDQ-F1

F3

VDDQ-F3

F12

VDDQ-F12

F14

VDDQ-F14

G2

VDDQ-G2

G13

VDDQ-G13

H3

VDDQ-H3

H12

VDDQ-H12

K3

VDDQ-K3

K12

VDDQ-K12

L2

VDDQ-L2

L13

VDDQ-L13

M1

VDDQ-M1

M3

VDDQ-M3

M12

VDDQ-M12

M14

VDDQ-M14

N5

VDDQ-N5

N10

VDDQ-N10

P1

VDDQ-P1

P3

VDDQ-P3

P12

VDDQ-P12

P14

VDDQ-P14

T1

VDDQ-T1

T3

VDDQ-T3

T12

VDDQ-T12

T14

VDDQ-T14

C5

VDD-C5

C10

VDD-C10

D11

VDD-D11

G1

VDD-G1

G4

VDD-G4

G11

VDD-G11

G14

VDD-G14

L1

VDD-L1

L4

VDD-L4

L11

VDD-L11

L14

VDD-L14

P11

VDD-P11

R5

VDD-R5

R10

VDD-R10

A1

VSSQ-A1

A3

VSSQ-A3

A12

VSSQ-A12

A14

VSSQ-A14

C1

VSSQ-C1

C3

VSSQ-C3

C4

VSSQ-C4

C11

VSSQ-C11

C12

VSSQ-C12

C14

VSSQ-C14

E1

VSSQ-E1

E3

VSSQ-E3

E12

VSSQ-E12

E14

VSSQ-E14

F5

VSSQ-F5

F10

VSSQ-F10

H2

VSSQ-H2

H13

VSSQ-H13

K2

VSSQ-K2

K13

VSSQ-K13

M5

VSSQ-M5

M10

VSSQ-M10

N1

VSSQ-N1

N3

VSSQ-N3

N12

VSSQ-N12

N14

VSSQ-N14

R1

VSSQ-R1

R3

VSSQ-R3

R4

VSSQ-R4

R11

VSSQ-R11

R12

VSSQ-R12

R14

VSSQ-R14

U1

VSSQ-V1

U3

VSSQ-V3

U12

VSSQ-V12

U14

VSSQ-V14

B5

VSS-B5

B10

VSS-B10

D10

VSS-D10

G5

VSS-G5

G10

VSS-G10

H1

VSS-H1

H14

VSS-H14

K1

VSS-K1

K14

VSS-K14

L5

VSS-L5

L10

VSS-L10

P10

VSS-P10

T5

VSS-T5

T10

VSS-T10

U4

VREF_VMA3_MOS

R297

R313

EV@549/F_4

1 2

R322

EV@1.33K/F_4

VMC_CLKP0

R336 EV@80.6/F_4

VMC_CLKN0

N13PGV GDDR 5x32-VRAM

8

+1.5V_GFX+1.5V_GFX

R302

EV@931/F_4

1 2

VMC_CLKP1

R342 EV@80.6/F_4

VMC_CLKN1

Quanta Computer Inc.

PROJECT :

Z09

PROJECT :

Z09

PROJECT :

Z09

30 40Monday, April 09, 2012

8

3A

POWER_JACK

dcjk-2dc2003-000111- 3p-v

20111102 Change fooptprint

PJ1

456

7

D D

C C

20120110 add Acpresent to PCH.

ACPRESENT<7>

20111102 ADD Switch 20111117 change to 0402 20111129 Remove R5760

BATT_EN#

PJ9002 componet pin1 and footprint pin1 is reverse.

B B

HEADER _BATT

1 2 3 4 5 6 7 8 9

10

PJ2

C stage must un-stuff PR9023.

A A

5

1 2

3

PC11

0.1u/50V_6

20120220 remove VA2 plant and PC205/PC202 PR124, move PD3 between PQ3 and PR10 for S5 current reduce.

201201119 Add PC205 for EMI suggestion.

R653 0_4

SB_ACDC <31>

R652 *0_4

BATT_EN# <22>

100p/50V_4

BATT_EN#

PC178

*47p/50V_6

PR256

PR258

*0_4

100_4

PU11 IP4223-CZ6

1

6

CH1

2

VN CH23CH3

MBDATA

CH4

5

+3VPCU

VP

4

MBCLKTEMP_MBAT

5

VA

PC9

2200p/50V_6

201201117 PC202 for EMI suggestion

+3VPCU

PR266 *10K_4 PR123

<24>

ACIN

6

PC71

0.1u/50V_6

PC70

20111123 del PL9004/PL9005.

PR242 100_4

PC173 *47p/50V_6

PR245 100_4

MBCLK <24>

MBDATA <24>

PL3

FBMA-11-201209-80 0A50T

PL2

FBMA-11-201209-80 0A50T

1N4148WS

+3VPCU

100K_4

PR117 100K_4

215

PQ50 2N7002DW

4 3

BAT-V

TEMP_MBAT

PR243 1M_4

ErP lot6

4

201201117 PC204 for EMI suggestion

VA1

201201119 Add PC205 for EMI suggestion.

PC201

0.1u/50V_6

PC1

0.1u/50V_6

PC204

0.1u/50V_6

PD5

recommend 200mA at least.

PR265 *SHORT_6

PC195

0.1u/25V_4

201201117 PC197/PC196 for EMI suggestion

0.1u/25V_4

TEMP_MBAT <2 4>

201201117 PC203 for EMI suggestion

+3VPCU

PC203

4

+3VPCU

3/30 REV:E add

68n/10V_4

PC196

PR115 10K/F_4

PR118 20_1206

PR114 *SHORT_4

MBDATA

PR112 *SHORT_4

MBCLK

PR107 10K_4

PR119 *10K_4

PR108 316K/F_4

PR109

PC78

100K/F_4

0.01u/25V_4

20111101 change net name from ICM to ICMNT

201201117 PC197 for EMI suggestion

PC197

0.1u/50V_6

PC86

0.1u/50V_6 PD1 SMAJ20A

2 1

PC84

0.1u/50V_6

PR116

63.4K/F_4

6

24707_ACDET

ACDET

20

24707_VCC

VCC

PC81

0.47u/25V_6

5

ACOK#

8

SDA

9

SCL

11

24707_IFAULT#

24707_CMPOUT

24707_ILIM

ICMNT<24 >

24707_CMPIN

PR122 *100K_4

3

10

4

ICMNT

PC80

100p/50V_4

IFAULT#

CMPOUT

ILIM

CMPIN

3

PD3

PQ3

SBR1045SP5-13

AOL1413

1

PU6 BQ24707A

GND

21

3

1 6 2 3

1

ACN

GND22GND24GND23GND

25

PQ25

IMD2AT108

24707_ACP

24707_ACN

PC83

0.1u/50V_6

REGN

HIDRV

PHASE

LCDRV

PGND

3

BTST

SRP

SRN

PR131 220K_4

PR134 220K_4

PC82

0.1u/50V_6

2

ACP

IOUT

7

12

1

52

2

4

PR135 *SHORT_4

5 4

16

24707_REGN

PR113

17

24707_BST

*SHORT_6

18

24707_DH

19

24707_LX

15

14

PR110 10_6

13

12

24707_SRP

24707_SRN

PR111

7.5_6

For battery reverse

REGN MAX voltage 6.5V V_ILIM=20*(VSRP-VSRN)=20*Ichg*Rsr =0.793V for 3.965A current limit

Pin10 ILIM=0.793V Rsr = 0.01ohm

3

1u/10V_6

PD4 RB500V-40

PC79 47n/50V_6

PR10

0.01/F_0612

1 2

PC72

0.1u/25V_4

PC75

0.1u/25V_4

PC73

0.1u/25V_4

D/C# <24>

4

2

PR17

*SHORT_4

24707_ACN

24707_ACP

PR16

*SHORT_4

201201117 PC189 For EMI suggestion

PC189

0.1u/50V_6PC77

PC186

2200p/50V_6

52

PQ51 AON7410

3

1

52

3

1

2

PQ49 AON7410

PR263 *4.7_6

PC179 *680p/50V_6

PL13

6.8uH_7X7X2.4

201201117 PC187 For EMI suggestion

VIN

PC155

0.1u/50V_6

PC158 2200p/50V_6

VIN

PC182

4.7u/25V_8

PR240

0.01/F_0612

1 2

PR232

*SHORT_4

24707_SRP 24707_SRN

Size Document Number Rev

Charger(BQ24707A)

Date: Sheet of

1

PQ48 AOL1413

1

PC187

0.1u/50V_6

PR233 *SHORT_4

PC170

2200p/50V_6

Quanta Computer Inc.

PROJECT :

3

PR101 33K/F_4

PQ22 2N7002K

1

2

PC167

10u/25V_1206

11/22

Z09

52

4

PR97 10K_4

3

1

BAT-V24707_DL

31 40Monday, April 09, 2012

PC166

10u/25V_1206

3A

MAIND

5

MAIND <5,35,37>

SYS_SHDN#

4

SYS_SHDN# <3,37>

3

2

1

Ven=7.23V

PC5

4.7u/25V_8

SYS_HWPG<24>

PQ2

AON7410

PQ6

AON7702

PC6 2200p/50V_6

1

52

4

3

52

4

3

D D

+5VPCU

20120216 remove JP1 for C stage. 20120216 remove JP2 for C stage.

20120130 for C change..

C C

VIN

+5VPCU 5 Volt +/- 5% TDC : 5.9A PEAK : 7.8A OCP : 9.5A Width : 240mil

+

PC8

0.1u/50V_6

PC85

220u/6.3V_7343

12

+

PC192

0.1u/50V_6

PC193 2200p/50V_6

201201117 PC192~PC194 for EMI suggestion

PR6

15.4K/F_4

PR13 10K/F_4

PL1

2.2uH_7X7X3

PR138 *4.7_6

PC90 *680p/50V_6

20120216 remove JP6 for C stage.

PC194

PC104

1000p/50V_4

15u/25V_7343

20111101 Add 3 /5VPCU reset n et.

+15V_ALWP

PD6 1PS302

PD7 1PS302

2

1

2

1

PC103

0.1u/50V_6

OCP:9.5A

L(ripple current) =(9-5)*5/(2.2u*0.4M*9) =2.525A

B B

Iocp=9.5-(2.525/2)=8.24A Vth=8.24A*14mOhm=115.32mV R(Ilim)=(115.32mV*10)/10uA ~115K Inductor max current ~10A

PC97

0.1u/50V_6

+15V

PR28 22_8

PR7

*SHORT_4

PC2

0.1u/50V_6

3

8223_EN<19>

0.1u/50V_6

+3VPCU

PR18 PR40 665K/F_4

*100K/F_4

SYS_SHDN#

PR5 1/F_6

+5V_FB

8223_EN

PR3 100K/F_4

PC96

PR151 *SHORT_6

PC102

0.1u/50V_6

10_8

PC13

PR39 330K/F_4

+3V_PG +5V_DH

+5V_B +5V_LX +5V_DL

0.1u/25V_4

1 2

*SHORT_4

PC3

0.1u/10V_4

8223_EN

8223_VIN

16

8

VIN

13

EN

23 21 22 20 19 24

VREG3 PGOOD UGATE1 BOOT1

PU1 RT8223P

PHASE1 LGATE1 VOUT1

2

FB1

ENTRIP1

ENC

1

18

PR1

PR30

PR9

127K/F_4

115K/F_4

20111103 change footprint becasue wrong.

+3V_DL

ENTRIP2

6

8223REF VLVINVIN

VL

VIN

PR29 PC7 1u/6.3V_4

PC4 10u/6.3V_8

PC29 4.7u/6.3V_6

17

VREG5

GND

25

3

SKIPSEL

TONSEL UGATE2

BOOT2 PHASE2 LGATE2

GND

15

OUT2

REF

FB2

PR32

*SHORT_4

14

+3V_SKIP

4

+3V_TON

10

+3V_DH

9

+3V_B

11

+3V_LX

12

+3V_DL

7 5

+3V_FB

PR2 *SHORT_6

PR19

*0_4

*SHORT_4

PR15 *0_4PR8

PR42 1/F_6

52

4

3

1

PC23

0.1u/50V_6

52

4

PQ10

3

1

AON7702

OCP:10A

L(ripple current) =(9-3.3)*3.3/(2.2u*0.5M*9) ~1.9A

Iocp=10-(1.9/2)=9.05A Vth=9.05A*14mOhm=126.7mV R(Ilim)=(126.7mV*10)/10uA ~126K Inductor max current ~9.24A

PQ13 AON7410

2.2uH_7X7X3

PR142 *4.7_6

PC95 *680p/50V_6

PL4

PC27 2200p/50V_6

20120216 remove JP4 for C stage.

PC28

4.7u/25V_8

+3VPCU

3.3 Volt +/- 5% TDC : 6.5A PEAK : 8.5A OCP : 10A Width : 260mil

PR31

6.81K/F_4

PC12

0.1u/50V_6

PR20 10K/F_4

+3VPCU

+

PC35 220u/6.3V_7343

+15VVIN

+5V_S5+3V_S5

PR149

PR159

22_8

1M_6

A A

2

S5_ON<24,37>

1 3

PQ32

DTC144EU

5

PR160 1M_6

3

2

1

PQ29 2N7002K

PR148 22_8

3

2

PQ30 2N7002K

1

VIN

PR150 1M_6

3

2

PQ31

2N7002K

1

4

+5VPCU

PR141

52

*1M_6

4

S5D MAIND MAIND S5D

PC109 *2.2n/50V_4

PQ5

MDV1528Q

3

1

+5V_S5

TDC : 3.75A PEAK : 5A Width : 150mil

+5VPCU

52

4

3

TDC : 2.13A PEAK : 2.84A Width : 90mil

3

1

PQ9

MDV1528Q

+3VPCU

52

4

PQ11

MDV1528Q

3

1

+5V

+3V +3V_S5

TDC : 4.21A PEAK : 5.6A Width : 160mil

+3VPCU

3

2

1

TDC : 0.5A PEAK : 0.65A Width : 20mil

2

PQ28 AO3404

Quanta Computer Inc.

PROJECT :

Size Docum ent Number Rev

Date: Sheet of

PROJECT :

SYSTEM 5V/3V (RT8223M)

Z09

32 40Monday, April 09, 2012

1

3A

5

+VCC_CORE

VCC_SENSE<5 >

PC176

0.1u/10V_4

+1.05V_VTT

PR252

54.9/F_4

5

20111106 unstuff.

PR261 *SHORT_4

PR250

130/F_4

VSS_SENSE<5>

Parallel

21111207 remove PR1001/PR1004 0ohm.

PR226

PR247

*0_4

200K/F_4

PR99

PR91

100K/F_4

30.1K/F_4

PR253

PR249

1.91K/F_4

*499/F_4

PC175

43p/50V_4

VCC_AXG_SENSE<5> VSS_AXG_SENSE<5>

Parallel

21111207 remove PR1043/PR1044 0ohm.

Close to VR

PR251

*75/F_4

VR_SVID_ALERT# VR_SVID_DATA VR_SVID_CLK

51650_VREF

PR102

PR255

4.7K/F_4

*22.6K/F_4

PR96

20K/F_4

PR100

75K/F_4

+3V_S5+3V+1.05V_VTT

PR95

PR254

1.91K/F_4

*100K/F_4

PC177

1u/6.3V_4

+VCC_GFX

PR94

100K/F_4_4250NTC

Place NTC close to the GFX_CORE Hot-Spot.

D D

C C

Check pull up resister to

1.05V for H_PROCHOT#

VRON<24> IMVP_PWRGD<3,7 > GFX_PWRGD<7,24> H_PROCHOT#<3,24>

B B

+5V_S5

PR264 *0_4

A A

51650_VRON 51650_CTHERM51650_GTHERM

PR260 100K/F_4

PR210 *10_4

PR209 *10_4

Close to the CPU side.

51650_VREF

VR_SVID_ALERT#<5> VR_SVID_DATA<5>

PR211 *10_4

PR212 *10_4

Close to the CPU side.

PR230

200K/F_4

PR92

30K/F_4

VR_SVID_CLK<5 >

PR93

15.8K/F_4

PC165 *330p/50V_4

PC172 *0.01u/50V_4

PR227

PR90

PR248 *0_4

PC164

*330p/50V_4

PC168 *0.01u/50V_4

4

69.8K/F_4

51650_COCP-R

100K/F_4

51650_CF-I MAX 51650_GOCP-R 51650_SLE W 51650_GF-IMAX 51650_GSKIP #

51650_VRON

VR_SVID_CLK VR_SVID_ALERT# VR_SVID_DATA

51650_VREF

PR224

15.8K/F_4

PR85

100K/F_4_4250NTC

Place NTC close to the VCORE Hot-Spot.

4

51650_VREF

PR237 8.06K/F_4

PC162 47p/50V_4

51650_VREF

PC76 1u/6.3V_4

14

2

COCP-R

3

CF-IMAX

13

GOCP-R

22

SLEW

24

GF-IMAX

33

GSKIP

15

V3R3

16

VR_ON

17

CPGOOD

23

GPGOOD

21

VR_HOT

18

VCLK

19

ALERT

20

VDIO

PC169 100p/50V_4

51650_VREF

IV@ for Internal VGA(+VCC_GFX enable) EV@ for External VGA(+VCC_GFX disable discrete only)

51650_CCOMP

11

10

8

12

9

CVFB

VREF

CGFB

CCSN3

CCOMP

PU9

TPS51650RSLR

GGFB25GVFB26GCOMP27GCSN128GCSP129GCSP230GCSN231GTHERM

51650_GCSN1

51650_GCSP1

+3V

PR103 5.49K/F_4

+3V_S5

32

51650_GTHERM

CCSP27CCSP3

PC154

0.1u/10V_4

6

GPWM134GPWM235CPWM3

51650_GPWM1

51650_CCSP1

51650_CCSN1

4

CCSP1

CCSN15CCSN2

36

3

51650_CTHERM

1

CTHERM

V5DRV

CBST1

CBST2

PAD49TPAD150TPAD251TPAD352TPAD453TPAD554TPAD655TPAD756TPAD857TPAD958TPAD1059TPAD1160TPAD1261TPAD1362TPAD1463TPAD1564TPAD16

3

VBAT

V5

CDH1

CSW1 CDL1 CDL2 CSW2

CDH2 PGND

65

*SHORT_6

51650_GSKIP # 51650_GPW M1

PR98

37 48 43 47 46 45 44 41 40 39 38 42

PC148

51650_VBAT 51650_V5 51650_V5DRV 51650_CDH1 51650_CBST1 51650_CSW 1 51650_CDL1

VIN +5V_S5

PR222

10K/F_4

0.1u/10V_4

201201117 Add GND on PU9 Pin40.

51650_CBST3

PU5

1

BST

2

SKIP

3

PWM GND4DRVL

12

PAD

13

PAD

14

PAD

TPS51601DRBR

PR229

2.2/F_6

PC150

0.22u/25V_6

DRVH

SW

VDD PAD

PAD PAD

2

20120222 Un-stuff PR219/PC137.

20111202 del PC1005/PC1004.

PR221

2.2/F_6

51650_CBST1

PC144

0.22u/25V_6

51650_CDH1

51650_CSW 1

51650_CDL1

PR88

PR87

0_6

10_6

PC143

PC145

2.2u/6.3V_4

4.7u/6.3V_6

8

51650_CDH3

7

51650_CSW 3

6 5 9 10 11

+3V

4

51650_CCSP 1

Close to the VR side.

51650_CCSN1

4

+5V_S5

PC147 1u/10V_4

4

51650_CDL3

PR234 *0_4

51650_GCSP1

51650_GCSN1

PR238 *0_4

Close to the VR side.

2

20111205 add PC1004.

5

213

5

213

20111205 change PC1015 to 33n 25V.

20120222 Un-stuff PR228/PC151.

5

213

5

213

PQ19

AON6414AL

PQ18 AON6780

PC66 *0.1u/25V_4

PC68 *0.1u/25V_4

PQ23

AON6414AL

PQ21 AON6780

PC65 *0.1u/25V_4

PC67 *0.1u/25V_4

PC64

0.1u/50V_6

PC157

33n/25V_4

Close with phase1 inductor

PC163

0.1u/50V_6

PC160

27n/16V_4

Close with AXG inductor

12

201201117 PC190/PC200 For EMI suggestion

12

201201117 PC191 For EMI suggestion

PC139

15u/25V_7343

PC140

PR219

*2.2_6

PC137

*2200p/50V_6

PC153

4.7u/25V_8

*2.2_6

PR228

PC151

*2200p/50V_6

PC62

4.7u/25V_8

PR84

PR83

PR89

PR86

2200p/50V_4

PL9

0.36uH

DCR=1.1mOhm

1 2

3

4

PC60

0.1u/10V_4

PR216 13K/F_4

PR213 *SHORT_4

23.2K/F_4

PR231

*140K/F_4

100K/F_4_4250NTC

PC180

AXG

15u/25V_7343

12

+

PC74

PC159

2200p/50V_4

4.7u/25V_8

PL10

0.36uH

DCR=1.1mOhm

1 2

3

4

PC138

0.1u/10V_4

PR220 *SHORT_4

PR223 17.4K/F_4

28.7K/F_4

PR236

191K/F_4

100K/F_4_4250NTC

Size Document Number Rev

Date: Sheet o f

Monday, April 09, 2012

Date: Sheet o f

Monday, April 09, 2012

Date: Sheet o f

Monday, April 09, 2012

1

20120216 remove JP11 for C stage.

12

+

PC136

10u/6.3V_8

PC190

0.1u/50V_6

PC61

10u/6.3V_8

+VCC_CORE/+VGFX (TPS51650)

VIN

0.1u/50V_6

PC191

+VCC_CORE

+

PC135

330u/2V_7343

+VCC_CORE TDC : 16A PEAK : 33A OCP : 40A Width : 1320mil

VCORE Load Line :

2.9mV/A

20120216 remove JP11 for C stage.

VIN

PC200

0.1u/50V_6

+VCC_GFX

+

PC142

+VCC_GFX

330u/2V_7343

TDC : 21.5A PEAK : 33A OCP : 35.8A Width : 1320mil

GFX_CORE Load Line :

-3.9mV/A for GT2

Quanta Computer Inc.

PROJECT :

Z09

PROJECT :

Z09

PROJECT :

Z09

1

33 40

3A

5

4

3

2

20120216 remove JP3 for C stage.

201201117 PC199 for EMI suggestion

1

VIN

D D

+3V

+5V_S5

PC31 2200p/50V_4

PC32

4.7u/25V_8

PC33

4.7u/25V_8

PC199

0.1u/50V_6

20111121 Change

PR24 100K_4

HWPG_VTT<24,36>

MAINON

C C

B B

OCP=20A L ripple current =(19-1.05)*1.5/(0.68u*500k*19) =2.918A Vtrip=20-(2.918/2)*3.5mohm =0.06489V

A A

Rlimit = 0.06489/10uA*8=51.9Kohm

5

PR25

*SHORT_4

PC98

*0.1u/10V_4

PR154 10_6

51219_EN 51219_V5 51219_MODE

51219_TRIP

PR143

PC38 1u/6.3V_4

20120130 for A2 change..

1K/F_4

+3V_S5

0.1u/10V_4

PR144 *SHORT_4

PC18

PR153

41.2K/F_4

16 14

9

15

6

VREF=2V

51219_REF

PR35 *10K/F_4

PR140 *11K/F_4

4

PGOOD EN V5 MODE TRIP

22

PU3

TPS51219RTER

VREF1REFIN

2

51219_REFIN

PC22 0.01u/25V_4

2

PQ12

D1D1D1

FDMS3606S

G1

1

S1/D2

9

51219_SW

8

PR155

G2

S2S2S2

4.7_6

567

PC108

1000p/50V_4

201201117 PC108 for EMI suggestion

RDSon 3.5mOhm

PL6

0.68uH_7X7X3

PC205 *1000p/50V_6

Close to output cap

20120216 remove JP5/9 and power plant +5V_PCH for C stage.

+

PC45

330u/2V_7343

Size Document Number Rev

+PCH&VTT (TPS51219)

Date: Sheet of

PC43

0.1u/50V_6

VCCP_SENSE <5> VSSP_SENSE <5>

Quanta Computer Inc.

PROJECT :

2

PR46 *100_4

PR156

*SHORT_4

PR45

*SHORT_4

PR44 *100_4

11 13 12 10 8

PR139

*SHORT_6

PC37 1n/50V_4

51219_DH

PR27

PC20

2_6

0.1u/25V_6

51219_SW 51219_DL

PR47 10_4

PR152 10_4

RC filter is for improve Jitter performance.

3

PAD17PAD18PAD19PAD20PAD21PAD

DH

BST

SW

DL

PGND

GND

VSNS4GSNS3COMP

7

5

PC36

51219_GSNS

51219_VSNS

0.01u/16V_4

PC34 1n/50V_4

+1.05V_VTT

+1.05V_PCH+VTT

1.05 Volt +/- 2% TDC : 13.5A PEAK : 18A OCP : 20A Width : 520mil

Z09

34 40Monday, April 09, 2012

1

3A

5

TDC : 0.75A PEAK : 1A Width : 40mil

MAINON<23,24,34,37,39>

SUSON<24>

20120130 for A2 change..

TDC : 0.38A PEAK : 0.5A Width : 20mil

PR259

100K/F_4

PR244

*0_4

PR239

*SHORT_4

PR257 200K/F_4

PR246

39.2K/F_4

+SMDDR_VREF

PC181

0.22u/10V_4

+3V

51216_S3

51216_S5

51216_MODE

51216_TRIP

VREF=1.8V

0.1u/10V_4

PC174

20

PGOOD

17

S3

16

S5

19

MODE

18

TRIP

26

PAD

51216_REF

PR104 10K/F_4

22

6

D D

C C

B B

HWPG_1.5V<24>

+0.75V_DDR_VTT

PC184 10u/6.3V_8

PAD21PAD

51216_REFIN

4

20111109 remove PC2002 20111116 Add PC2002

PC185 10u/6.3V_8

1

5

4

VTTREF

VTTSNS

VTTGND

PU10

TPS51216RUKR

VDDQSNS9REFIN8REF

25

2

3

VTT

VLDOIN

GND

PAD23PAD24PAD

7

Close to IC

PC183 10u/6.3V_8

12

V5IN

14

51216_DRVH

DRVH

15

51216_VBST

VBST

13

51216_SW

SW

11

51216_DRVL

DRVL

10

PGND

PR262 *SHORT_6

3

Greater than or equal 40mil

+5VPCU

20120209 change power plant from +5V_S5 to +5VPCU.

PC161 1u/10V_4

2

PR235

PC156

2_6 PC152

0.1u/50V_6

FDMS3606S

D1D1D1

G1

1

S1/D2

8

G2

PQ20

S2S2S2

567

*1000P/50V_6

RDSon=3.5mohm

PC69

2200p/50V_4

9

51216_SW

PC202

201201117 PC146 for EMI suggestion

PR225

4.7_6

PC146 1000p/50V_4

PL11

0.68uH_7X7X3

4.7u/25V_8

2

Close to output cap

PC149

4.7u/25V_8

+

PC141

330u/2V_7343

20111109 remove Jump.

PC63

0.1u/50V_6

VIN

+1.5V_SUS

1.5 Volt +/- 5% TDC : 15A PEAK : 18A OCP : 20A Width : 600mil

+1.5VSUS

1

+1.5VSUS

MAIND

3

2

PQ37 AO3404

1

+1.5V

Z09

35 40Monday, April 09, 2012

1

3A

20120130 for A2 change..

OCP=20A L ripple current

A A

=(19-1.5)*1.5/(0.68u*400k*19) =5.079A Vtrip=20-(5.079/2)*3.5mohm =0.06111V Rlimit=0.06111/10uA*8=48.88Kohm

5

PR241

60.4K/F_4

PC171

0.01u/25V_4

51216_S551216_S3

+0.75V_ON<24>

20111101 add If S3 power reduce then stuff PR2012 else stuff PR2002

PR106

*SHORT_4

S3 S5

S0

S3 (mainon off)

1 0

S4/S5

4

PR105 *0_4

VTTREF+1.5VSUS

ON

1

ON ON

1

OFF

3

ON ON

OFF

OFF OFF0 0

2

MAIND<5,32,37>

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

DDR 1.5V(TPS51216)

Date: Sheet of

PROJECT :

5

4

3

+3V

2

1

D D

PC92

PC94

10u/10V_8

0.1u/10V_4

+5V_S5

PC89

+3V

PR132

PC10

*0.1u/10V_4

100K_4

C C

B B

A A

HWPG_VCCSA<24>

HWPG_VTT<24,34>

PR158 *SHORT_6

PR157 *SHORT_6

PR133 *SHORT_4

2.2u/6.3V_6

*SHORT_6 PC87 1u/6.3V_4

51461_FILT

51461_EN

VCCSA_VID0<5>

VCCSA_VID1<5>

PR12

PR11

1K_4

VID0 +VCCSA

0 0

1 1 1

22

PR130

VID1

10 0 0.775V

24

18

V5DRV

17

V5FILT

16

PGOOD

13

EN

14

VID0

15

VID1

25

AGND

MODE

6

51461_MODE

PR145 *33K/F_4

201201117 PR146 change to 365ohm,un-stuff PR36,stuff PR43,stuff PR145, PU7 change to TPS51463. 20120220 PR145 un-stuff,PR145 change to 100,PR43 un-stuff, PR36 short pad.

0.9V

0.85V

0.75V

21

20

19

VIN

VIN23VIN

PGND

PU7 TPS51463

GND1VREF2COMP3SLEW4VOUT

51461_VREF

PC100

0.22u/10V_4

5

51461_SLEW

PR147 4.99K/F_4

PC99

0.01u/16V_4

PC101

3.3n/50V_4

PR145 33kohm PR146 change to 365ohm PR36 nc PR43 10kohm PU7 Change to 51463

12

PGND

BST

11

SW

10

SW

9

SW

8

SW

7

SW

20120216 remove JP7 for C stage.

PC93 10u/10V_8

PC88

0.1u/50V_6

51461_BST

51461_SW

PL12

0.47uH_7X7X2.4

11/21 Change

PC24 10u/6.3V_8

PC106 10u/6.3V_8

PC39 10u/6.3V_8

default 0.9V

5

4

3

2

+VCCSA

0.9 Volt +/- 2% TDC : 3A PEAK : 4A Width : 120mil

+VCCSA

20120216 remove JP8 for C stage.

10u/6.3V_8

PC30

PC42 10u/6.3V_8

PC110 10u/6.3V_8

51461_VOUT

Size Document Number Rev

VCCSA(TPS51461)

Date: Sheet of

PR146 100/F_4

PC105 0.1u/50V_6

PR36

*SHORT_4

PR43 *10K/F_4

Quanta Computer Inc.

PROJECT :

1

Z09

36 40Monday, April 09, 2012

VCCSA_SENSE <5>

3A

5

4

3

2

1

+3VPCU

PC26

PC25

+3V +1.8V

D D

HWPG_1.8V<24>

MAINON<23,24,34,35,39>

C C

PR21

*SHORT_4

PR22

*100K/F_4

PR23 *100K/F_4

PC14 1000p/50V_4

PC107

*100p/50V_4

Thermal protection

2

S5_ON

S5_ON<24,32>

B B

PR37

10K_6_NTC

3

2

S5_ON

A A

1

PQ7 2N7002K

LM393_PIN2

PR34

1.74K/F_4

PQ4

DTC144EUA

VLVL

PR33 200K/F_4

84

3

2.469V

+

2

-

PR41 200K/F_4

5 6

VIN

1 3

+

-

10u/6.3V_8

PD2 DA2J10100L

PR14 1M_6

1

PU4A BA10393F

PU4B BA10393F

PR50 10K/F_4

PC40 1200p/50V_4

2

PC44

0.1u/50V_6

7

1

3

0.1u/25V_4

PQ1 AO3409

PR4 *SHORT_6

PR51 121K/F_4

PR38 200K_6

PC41

0.01u/25V_4

PC21

0.1u/50V_6

16

1

2 14 15

7

8

9

PU2 TPS54318RTER

VIN VIN VIN

BOOT

PWRGD EN COMP RT/CLK SS

AGND

PAD17PAD18PAD19PAD20PAD21PAD

22

3

2

PQ8 2N7002K

1

10

PH

11

PH

12

PH

13 6

VSNS

3

GND

4

GND

5

SYS_SHDN# <3,3 2>

PL5

PC19

0.1u/50V_6

1uH_7X7X3

54318_VSNS

PR26

*SHORT_6

V0=0.8*(R1+R2)/R2

201201117 PC188 For EMI suggestion

MAINON

2

PR215 *100K/F_6

0.1u/50V_6

PC188

1 3

PQ47 DTC144EUA

VIN

For EC control thermal protection (output 3.3V)

5

4

3

PR48 100K/F_4

PR49

78.7K/F_4

PR218 1M_4

MAINON_G

PR217 1M_4

R1

PC17

0.1u/25V_4

R2

3

2

1

+1.8V

1.8 Volt +/- 5% TDC : 1.54A PEAK : 2A Width : 60mil

PC16

10u/6.3V_8

PR208 22_8

2

PQ45 2N7002K

3

1

PC15

10u/6.3V_8

PR207 22_8

PQ44 2N7002K

201201117 PC198 for EMI suggestion

+0.75V_DDR_VTT

PC198

.1u/10V_4

PR214 22_8

3

2

PQ46 2N7002K

1

2

+1.5V

+1.8V

+15V+5V+3V

PR206

PR205 22_8

3

1

3

2

PQ41

2N7002K

1

Size Document Number Rev

Date: Sheet of

*22_8

PQ43

*2N7002K

PR203 1M_4

MAIND

3

2

PQ38 2N7002K

1

Quanta Computer Inc.

PROJECT :

+1.8V/Discharge/Thermal

PC133 *2200p/50V_4

1

MAIND <5,32,35>MAINON_G<3,5>

Z09

3A

37 40Monday, April 09, 2012

5

+3V_GFX

PR73 *EV@10K/F_4 PR72 *EV@10K/F_4 PR67 *EV@10K/F_4 PR68 *EV@10K/F_4

D D

PR69 EV@10K/F_4 PR70 EV@10K/F_4

20111116 adjust strap to 0.09V

C C

B B

A A

default 0.90V

PR181 *EV@10K/F_4

PR182 *EV@10K/F_4

VGA_PG<39>

GPU_DPRSLPVR<28>

dGPU_VRON<10,39>

GPU_PWR_ALERT#<24>

51728_V5FILT

20111206 PR3034 and CPC3018 change to AGND, PR3041 change to DGND.

GPUVCC_SENSE<25> GPUVSS_SENSE<25>

5

PR180 EV@10K/F_4

PR168 *EV@0_4

Parallel

PR179 EV@10K/F_4

PR177 EV@10K/F_4

PR178 EV@10K/F_4

PR169 *EV@0_4

H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5

PR58 EV@*100K/F_4

PR55 EV@2.2K_4

PR59 EV@100K/F_4

PR170 *SHORT_4

GPU_VID0<28> GPU_VID1<28> GPU_VID2<28> GPU_VID3<28> GPU_VID4<28> GPU_VID5<28>

+3V

PR60 *SHORT_4

+VGPU_CORE

PR162 *SHORT_4

PR163

*SHORT_4

+3V

PR63 *EV@10K/F_4

PR172 EV@100K/F_4

PR189 *SHORT_4 PR190 *SHORT_4 PR191 *SHORT_4 PR192 *SHORT_4 PR193 *SHORT_4 PR194 *SHORT_4

PC117 EV@68p/50V_4

PR56 EV@309K/F_4

EV@100K/F_4_3540NTC

PR61 EV@100K/F_4

PR171 EV@200_4

51728_DROOP

PR167

PC116

EV@8.2K/F_4

EV@1200p/50V_4

PC115 EV@0.22u/10V_6

PR82

PR54 EV@11.8K/F_4

Place NTC close to the GPU Hot-Spot.

PR161 *EV@100_4

51728_VFB 51728_GFB

PR164 *EV@100_4

Close to the GPU side.

4

51728_PCNT

51728_EN

H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5

51728_VREF

PR57 *EV@0_4

51728_SLEW

PC114 EV@1n/50V_4

4

3

PR175 EV@2.2/F_6

51728_VBST2

PC119 EV@0.22u/25V_6

+5V_S5

PC120 EV@2.2u/10V_6

26

33

PGD

34

PG

13

PCNT

12

SLP

35

EN

10

THAL

20

VID0

19

VID1

18

VID2

17

VID3

16

VID4

15

VID5

14

VID6

PU8

EV@TPS51728RHAR

39

DROOP

40

VREF

37

SLEW

9

THRM

GFB7VFB

8

PC113 EV@1n/50V_4

V5IN

IMON

11

51728_IMON

PR53 EV@16.9K/F_4

41

TONSEL TRIPSEL OSRSEL

PwPd

DRVH2 VBST2

DRVL2

DRVH1 VBST1

DRVL1

V5FILT

LL2

CSP2 CSN2

LL1

CSP1 CSN1

PGND

PU

GND2TPAD142TPAD243TPAD344TPAD445TPAD546TPAD647TPAD748TPAD849TPAD950TPAD1051TPAD1152TPAD1253TPAD1354TPAD1455TPAD1556TPAD16

57

PC46 EV@3300p/50V_4

30 29 28 27 3 4

21 22 23 24 6 5

25

36

51728_TONSEL

31

51728_TRIPSEL

32

51728_OSRSEL

1 38

51728_V5FILT51728_TONSEL

51728_DRVH2 51728_VBST2 51728_LL2 51728_DRVL2 51728_CSP2 51728_CSN2

51728_DRVH1 51728_VBST1 51728_LL1 51728_DRVL1 51728_CSP1 51728_CSN1

PR173

*SHORT_4

PC47

EV@2.2u/10V_6

PR71*EV@0_4

PR52

*SHORT_8

51728_DRVH2

PR65 *EV@10K/F_4

51728_LL2

51728_DRVL2

EV@FDMS3606S

Close to the VR side.

+3V

51728_VBST1

51728_DRVH1

51728_LL1

51728_DRVL1

PR176 EV@2.2/F_6

PC121 EV@0.22u/25V_6

PR66 *EV@10K/F_4

Close to the VR side.

EV@FDMS3606S

PR174 *SHORT_4

PR62*EV@0_4

PR64*EV@0_4

3

2

20120222 Un-stuff PR195/PC125.

20111123 Change footprint to 4P choke.

12

+

PC55

EV@4.7u/25V_8

EV@2200p/50V_4

DCR=1.1mOhm

+

PC124

PC53

PC54

EV@0.1u/10V_4

+VGPU_CORE Countinue current:30A Peak current:40A OCP minimum 48A Loadline=0mV/A

EV@330u/2V_7343

EV@10u/6.3V_8

G1

1

S1/D2

8

G2

PQ15

51728_CSP2

PC48 *EV@0.1u/25V_4

51728_CSN2

PC49 *EV@0.1u/25V_4

2

567

D1D1D1

9

PC206

S2S2S2

*1000p/50V_6

PC56

EV@0.1u/50V_6

51728_LL2

PR195

PC125

PR76

PC111

EV@15n/25V_4

PR75

EV@100K/F_4_3540NTC

PC123

EV@4.7u/25V_8

PL7

EV@0.24uH_7X7X3

1 2

3

4

*EV@2.2_6

PR77 EV@27K/F_4

*EV@2200p/50V_4

EV@30K/F_4

PR165 EV@75K/F_4

PC122

PR74 *SHORT_4

20120217 Change Resistor value.PR77/PR165/PR76/PR166/PR80/PR81

20120222 Un-stuff PR120/PC126.

20111123 Change footprint to 4P choke.

12

+

PC57

PC129

EV@4.7u/25V_8

EV@2200p/50V_4

DCR=1.1mOhm

+

PC128

PC59

EV@0.1u/10V_4

Size Document Number Rev

Date: Sheet of

EV@330u/2V_7343

PC134

EV@10u/6.3V_8

VGPU Core (TPS51728)

G1

1

S1/D2

8

G2

PQ16

PC51 *EV@0.1u/25V_4

PC50 *EV@0.1u/25V_4

2

567

D1D1D1

9

PC207

S2S2S2

*1000p/50V_6

51728_CSP1

51728_CSN1

2

PC112

PC58

EV@0.1u/50V_6

EV@0.24uH_7X7X3

1 2

51728_LL1

PR201

*EV@2.2_6

PC126

*EV@2200p/50V_4

PR80

EV@30K/F_4

EV@15n/25V_4

PR79

EV@100K/F_4_3540NTC

PC130

EV@4.7u/25V_8

PL8

3

4

PR78*SHORT_4

PR81 EV@27K/F_4

PR166 EV@75K/F_4

1

20111109 remove Jump.

PC52 EV@15u/25V_7343

PC132 EV@15u/25V_7343

VIN

+VGPU_CORE

20111109 remove Jump.

Quanta Computer Inc.

PROJECT :

+VGPU_CORE

1

VIN

Z09

38 40Monday, April 09, 2012

3A

5

4

3

2

1

D D

+1.5V_GFX

5

PR197 *SHORT_4

PR196 *EV@0_4

PC127

EV@1u/10V_4

PR127 *EV@0_4

PR125 *SHORT_4

PR188 *SHORT_4

PR198 EV@100K_4

PR126 EV@100K_4

PR184 EV@100K_4

2

VGA_PG<38>

dGPU_VRON<10,38>

C C

MAINON<23,24,34,35,37>

dGPU_PWR_EN<9>

B B

A A

PQ39

1 3

EV@PDTC143TT

PQ24

1 3

EV@PDTC143TT

PQ34

1 3

EV@PDTC143TT

VIN

4

PR200 EV@1M_4

PR202 EV@1M_4

PR129 EV@1M_4

PR128 EV@1M_4

PR187 EV@1M_4

PR185 EV@1M_4

+1.5V_GFX +15V

PR204 EV@22_8

3

2

PQ42 EV@2N7002K

1

DGPU_D<29>

PR137 EV@22_8

3

2

PQ27 EV@2N7002K

1

+1.05V_GFX +15V

PR186 EV@22_8

3

2

PQ35 EV@2N7002K

1

PR199 EV@1M_4

dGPU_D1

3

2

PQ40 EV@2N7002K

1

+15V+3V_GFX

PR136 EV@1M_4

dGPU_D

3

2

PQ26 EV@2N7002K

1

PR183 EV@1M_4

dGPU_D2

3

2

PQ33 EV@2N7002K

1

3

4

PC131 *EV@2200p/50V_4

PC91 *EV@2200p/50V_4

4

PC118 *EV@2200p/50V_4

+1.5VSUS

2

+1.05V_VTT

3

5

213

+3V

3

1

52

PQ17 EV@AOL1718

PQ14 EV@AO3404

EV@MDV1528Q

1

PQ36

TDC : 5.67A PEAK : 7.56A Width : 240mil

+1.5V_GFX

TDC : 1.04A PEAK : 1.38A Width : 50mil

+3V_GFX

TDC : 2.33A PEAK : 3.1A Width : 100mil

+1.05V_GFX

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

GPU_PWR

Date: Sheet of

2

Date: Sheet of

PROJECT :

Z09

39 40Monday, April 09, 2012

1

3A

5

REV

Model

10.28

FIRST RELEASED

Z09

D D

C C

B B

A A

Size Document Number Rev

Change list

Date: Sheet of

1. 20111031 Modify U18 symbol(Add PAD gnd*9).

1A

2. 20111031 Page 19 Add LED/Cardreader con.(only Power and Battery)

3. 20111031 Page 20/21 remove mSATA/Mian HDD re-driver IC.

4. 20111031 Page24 Change U5039 USB power switch power well from +5VPCU to +5V_S5.

5. 20111031 Page 24 Un-staff USB9+/- resistor because it si reserve only debug use.

6. 20111031 Page 11 Add Q18/19 mose for DSW circuit.

7. 201111101 Page 07 Remove LVDS Data/clock.

8. 201111101 Page 03 Add Resistor R182/R185.

9. 201111101 Page 20 stuff R304 for BT power.

10. 201111101 Page 32~40 Power updata circuit.

12. 201111102 Page17 Change R554 from 0ohm to 2.2ohm for Prevent EDS issue.

13. 20111102 del R160

14. 20111102 page7 FDI and DMI reverse.

15. 20111102 page6 R5757 stuff for PGE reverse.

16. 20111102 page6 Ball G48 connect test point.

17. 20111102 update connector list without LVDS/HDMI/Audio/USB3/RJ45/ODD/KB.

18. 20111102 Page 02 Reverse PEG.

19. 20111103 page 25 add pull up 10k R305 to PSI CS#.

20. 20111103 page 9 remove dGPU_PWM_SELECT# change to dGPU_PRW_RN PD.

21. 20111104 page 3 R5332 PU from +1.5VSUS TO +1.5V_CPU becaue leakage issue.

22. 20111104 page 40,41 add memory down.

23. 20111104 page 26~31 change GPU solution from 13P-GV to 13P-PL.

24. 20111104 page 02 change R5459 from 10K to 1K PU.PR1029

25. 20111106 page 32 Un-stuf PR1029.base on CRB.20111107 R5180 un-stuff.

26. 20111107 page 07 R5180 un-stuff. because DRAMPWEGD change to +5V_CPU.

27. 20111107 page 14 unstuff R5347/R362 and stuff Q5010 for Deep S3.

28. 20111107 page 14 remove R5144 PU +1.5VSUS.

28. 20111107 page 20 move debuge port to CN3.

29. 20111107 page 07 R469 change from 10k to 4.99k.

30. 20111108 page08 PU 10k to +3V, becaue no sata LED.

31. 20111108 page15 add feature board con.

32. 20111108 page19 add TPM con.

33. 20111109 page09 VCC core CAP change to. total : 22uF x 12 tatal : 470u x 3(power side*1) AXG: tatal : 470u x 1(power side*1)

34. 20111109 page36 remove PC2002 and JUMP.

35. 20111109 page39 remove JUMP.

36. 20111109 page14 remove XDP.

37. 20111109 page02 add PEG tox16.

38. 20111110 page07 remove R600/R601.

39. 20111110 page08 R411 change power plant to +3V_PCH_ME

40. 20111110 Move R6168 to page04.

41. 20111111 page07 Reverse DMI/FDI to normal.

42. 20111111 page16 R423 change to 56K(Vout=36V,R65 to 10K, R36 un-stuff,stuff R67/C27 and R67 change to 9.09K (for phas shif mode). R5312

43. 20111111 page07 add 0ohm R5312 on DRB#.

44. 20111111 Remove codec to DB board.

45. 20111111 page20 Remove Feature con and CRT cricuit, add RJ45.

46. 20111114 Update CN25,CN5008,CN5007 footprint .

47. 20111114 Page19 Un-stuff D8/R45.

48. 20111114 Page20 CN17 from 24pin change to 30pin, add TP function and add TPM and Audio connector

49. 20111115 Update CN23 footprint.

50. 20111116 page36 add PC2002.

51. 20111116 page08 Base on EMI request add C2494 22P on PCH BlTCLK and R256/C6495 and Stuff R411.

52. 20111116 page25 EC add GPIO36 dGPU_OVT# to GPU for ADPS,Change net name GPIO87 to USB_CHG_EN, GPIO97 to USB_CHG_MODE,GPI043 net name change to GPU_THAL#.

53. 20111116 page19 change transfromer from GigaLan to 10/100*2, remove ESD U8/12.

54. 20111116 page08 Change RTC connector and un-stuff Q36,R415,R416,R422,R414.

55. 20111116 page08 Change back RTC connector and stuff Q36,R415,R416,R422,R414.

56. 20111117 page32 BTT_EN# from push button change to short pad and connect to DB board.

57. 20111117 page11 Remove 0ohm short pad,R5051/R5044/R5034/R5149/R5220/R5039/R5042.

58. 20111117 update CN3/Cn18/CN12/CN17/SW2 footprint.

59. 20111117 page24 remove R61112/R61110 no charge option.R5176,del PQ35 change Q48 for dul mose type.

60. 20111117 page09 R5176 change to singal resistor becaue GPIO40~42 GPIO9 for memory down ID.

61. 20111117 change Q5003/Q29/Q16/Q30/Q26/Q41/Q4040/Q5043 footprint to dual type mose Del Q17/Q31/Q27/Q42/Q5041/Q5045.

62. 20111117 page20 Change R256 to L6 for EMI reqeust.

63. 20111118 page17 Change R474 to 100kohm.

64. 20111118 page16 Remove LCD power C21/C12

65. 20111118 page16 Change RTC connector.

66. 20111118 change Q21/Q39 footprint to dual type mose Del Q43/Q40, mose return back to Q26/Q27.

67. 20111118 page09 GPIO40~42,GPIO09 change net name to RAM_ID0~3.

68. 20111121 page08 Change RTC battery back to socket.

69. 20111121 page21 change back transformer to single giga LAN.

70. 20111121 page23 Add screw hole*13.

71. 20111121 page16 change L96 to 10u 0.1A .

72. 20111121 page03 remove R5306/R5311/R5474/R5475 .CX12B900000

73. 20111121 page16 L2 change P/N to CX12B900000.

74. 20111121 page06 add R95 for G48 ball to GND for sandy bridge.

75. 20111121 page03 add Q31 and R182 to 1k/R185 10K.

76. 20111121 page20 change CN8 footprint and update CN9 footprint.

77. 20111121 page23 modify all hole footprint.

78. 20111122 page19 Swap U5103 pin define for layout.

79. 20111122 page20 modify CN6/cn17 pin define, cn17 pin29/30 for TP.

80. 20111122 Update footprint PJ9002.

81. 20111122 page35 add a jump JP6008 at 1.05V.

82. 20111122 Q37 change to P mose and remove Q44 change power plant to +3V_S5.

83. 20111122 page16 L97 Change inductor to 1A for FAE reqeust.

83. 20111122 page08 add net TP_INT# pin at CN17 pin29 to PCH N32 and add Q5005 and R444 for leakage issue..

84. 20111123 page20 CN8 add LPCPD# net to PCH G8.

85. 20111123 change PJ9002 pin define.

86. 20111123 update Hole3/4/10 footprint.

87. 20111123 page39 PL3002/PL3001 change footprint to 4pin.

88. 20111123 page32 Del PL9004/PL9005.

89. 20111123 page23 modify Keyboard Pin define for match matrix.

90. 20111124 midfy CN5008/CN5007 USB footprint.

91. 20111124 page09 modify RAM_ID from GPIO40~42,GPIO09 change to GPIO42,9,10,14.

92. 20111124 page14 DDRIII on board RAM change to 256x16.

93. 20111125 Update Cn11/JDIM1/RJ45 footprint.

94. 20111125 Update KB pin define.

95. 20111128 Update CN5010/CN2/U32~U35 footprint.

96. 20111128 page28 change Q5044 to dual mose and del Q5042, GPIO12 ACIN high DC low prevent backdriver add mose. add PU +3V resistor R5306/R5308 reserve.

97. 20111128 page08 change net TP_INT# to pin E12 GPIO11 and net name to SMBALERTL, add R444 10K to PCH_ODD_EN not use.

98. 20111128 page19 add R221/C6496 for EMI request and change Cn8 pin9 to LPC_LFRAME#,Pin10,pin12 to GND,Pin11 PCLK_TPM.

99. 20111129 page29 change Q5043 to singal mose and add back Q5045, VGA_OVT# connect to SYS_SHDN# un-stuff, GPU_ALERT# to EC GPU_THAL, DGPU_OPP# to VGA_ACIN.

100. 20111129 page22 Remove BKT1 and add hole14~16.

101. 20111129 page03 change U5013.3 net to PCI_PLTRST#.

102. 20111129 page09 change U5001 power plant to +3V.

103. 20111129 page21 change path cap power well and del C497/C704/C479/C508.

104. 20111129 page28 add R27 0ohm at net GPU_DPRSLPVR.

105. 20111129 page31remove R5068 becasue double connect GND.

106. 20111129 page24 add R437~R439 SPI series resistor,and SPI net contact to SPI 4M ROM.

107. 20111130 page22 add hole18.

108. 20111130 page18 CN5010 add two GND pin15/16.

108. 20111130 page09 change PCIE_CLKREQ5# PU +3V_S5, PCIE_CLKREQ2# PU +3V.

109. 20111201 page17 change C6108 power from +3V_S5 to +3V_LAN.

110. 20111201 page19 update CN8 footprint.

111. 20111201 Power Update : a.PL3001 and PL3002 change to 0.24uH inductor. b.PR3019 and PR3046 change to 26.14kohm. c.PR3021 and PR3049 change to 29.65kohm. d.PR3023 and PR3053 change to 76.49kohm. e.PC3013 and PC3030 change to 15nF. f.Change PR3040 to 312.5kohm. g.Change PR3055 to 17kohm. h.Change PR3031 to 8.2kohm. i.Change PC3016 to 1200PF. j.Change PC3015 to 68PF. k.change PR3011 to 200ohm. l.Change PR1007 to 13.07khom. m.Change PR1015 to 23.02kohm. n.Change PR1022 to 30kohm o.Change PR1013 to 201.8kohm. p.Add PR1066 for default test mode.

112. 20111202 Hole18 change Footprint to HG-C256D118P2-V3

113. 20111202 page03 ADD NET DEEPS3_EC .connect to Q15 , Q5050.

114. 20111202 page33 Del PC1004/PC1005 for Power reqeust.

115. 20111205 page19 Change CN8 pin define and add 0ohm R222 on net SERIRQ.

116. 20111205 page33 add back PC1004.

117. 20111206 page38 PR3034 and CPC3018 change to AGND, PR3041 change to DGND.

118. 20111206 page07 add R5193 un-stuff for normal s3 PCIE LAN wake up.

119. 20111207 page33 remove PR1001/PR1004/ PR1043/PR1044 0ohm

120. 20111207 page21 Modify CN12 Pin define following up ZHA.

121. 20111207 page20 CN3 Pin51 to GND.

122. 20111207 page20 change CN13 Pin5/U5006.11 net name BT_POWERON# to BT_POWERON.

123. 20111207 page38 swap PR3042 and PR3041.

124. 20111207 page08 Change Y5000 footprint.

125. 20111207 page22 modify hole8 footprint and add net BATT_EN at Pin2.

126. 20111207 page22 modify hole8 footprint and change net BATT_EN to Pin3.

1. 20120104 page11 VCCDSW3_3 change power plant to +3VPCU.

1B

2. 20120104 page07 Change DPWEOK from REREST# to EC.

3. 20120109 page08 change Q33 footprint.

4. 20120105 page11 +3V_VCCM_SPI change to +3V_S5 and reserve +3V.

5. 20120105 page20 Q14/Q9 change transistor direct and power plant to +3V_S5.

6. 20120111 page15 Change C407 to 50V CAP and un-stuff C410 and change C406 to 50V 0805 size.

7. 20120112 page04 Add C753~C758 1uf CAP on +0.75V_DDR_VTT.

8. 20120113 page22 Change KB con footprint.

9. 20120113 page28 Change Q25.2 to GPU_TRIP# EC.

10. 20120113 page28 Change GPU Strap1 PD4.99k,strap4 PD 45.3k.

11. 20120113 page31 stuff PR256 for Battery enable, change PQ50 to dual mose of ACIN to EC and PCH acpresent# pin.

13. 20120117 Update EMI CAP.

11. 20120117 page24 Add net WLAN_OFF for IOAC on U36.81 to CN5.64.

12. 20120117 page36 PR146 change to 365ohm,un-stuff PR36,stuff PR43,stuff PR145, PU7 change to TPS51463.

13. 20120118 page22 Change CN12 footprint.

14. 20120118 page22 Add u37 for ICT test use.

15. 20120119 page24 Add Q46 to EC U36.114.

16. 20120119 Unstuff PR266 and stuff R346 .

17. 20120119 move R358 to near Q38 and del net DRAMRST_CNTRL_PCH,and EC_DRAMRST_CNTRL and R616.

18. 20120119 Change PR266 from 100k to 10k .

19. 20120120 Remove C644/C621/C622.

20. 20120120 Page 24 change R640/R61 power plant to +3V_S5.

21. 20120120 unstuff R573 and stuff R574 for DS3 function.

1. 20120214 Page17Add c613 and c614 for LAN power noise.

1C

2. 20120214 Page07 Add R642 between SUSWARN to SUSACK.

3. 20120216 Page24 Add iRST Gate and change 108pin SUSWRAN# to IOAC_PCIERST#.

4. 20120216 Page20 CN5 pin22 reserve IOAC_PCIERST# solution.

5. 20120217 Page28 un-stuff R547/R548, stuff Q35,un-stuff R383/R435, stuff Q26/Q25,add PU 10k +3V GPU_THAL# and GPU_TRIP#. R543/R548 PU from+3V to +3VPCU, for S5 current reduce.

6. 20120217 Page38 change PR77/PR81 to 27k,PR165/PR166 to 75k,PR76/PR80 to 30k

7. 20120217 change 0ohm to short pad.

8. 20120220 page 31 remove VA2 plant and PC205/PC202 PR124, move PD3 between PQ3 and PR10 for S5 current reduce.

9. 20120220 change PQ11, PQ2, PQ6, PQ10, PQ13, PQ5, PQ9, PQ49, PQ51 footprint to WDFN5-3_05X3_05-65.

10. 20120220 page7 Change net suswarn# to suswarn#_R PU.

11. 20120220 page36 PR145 un-stuff,PR145 change to 100,PR43 un-stuff, PR36 short pad.

12. 20120220 page24 add U36.105 GPIO KB_BL_EN pin to CN13.23.

13. 20120220 page20 Change Cn6 footprint

14. 20120221 page28 R527/R516 change power plant to +3V.

15. 20120221 page08 Change R620/R534 to 47K and stuff R620, R524 un-stuff

16. 20120221 page20 Add R650 for iRST selection.

17. 20120221 page15 CN7 pin33/34 connect to GND.

18. 20120222 page38 Unstuff PR219/PC137/PR288PC151.

19. 20120222 page38 Unstuff PR195/PC125/PR201/PC126.

20. 20120222 page15 del R299/R315.

21. 20120222 page14 Change Footprint U30/31/32/35.

22. 20120223 page15 Change Footprint L22.

23. 20120223 page08 Change JTAG TDI form CPU TDO, TCK and TMS form U37 and CPU .

24. 20120223 page28 add dGPU_OPP# PU reserve R651.

25. 20120223 page28 add JTAG_TDO PU reserve R299.

1. 20120302 page19 add CN13.30 net to BIOAED_ID4.

2C

2. 20120305 page07 R397 from short pad to RC0402 footprint.

3. 20120322 page23 Remove RP1/RP2/RP3/RP4/L18/L19

4. 20120322 page31&37 , delete PR120 & PR121.

5. 20120322 page32 Reserve PC196 for PU1_PIN13

6. 20120322 page15 delete L1

7. 20120322 page24&31 Add NET<SB_ACDC> , add R653,Unstuff PR266 & R652 Wait for EC confirm by the result.

8. 20120328 page32 Remove PC196

9. 20120328 page35 Reserve PC202

10. 20120328 page34 Reserve PC205

11. 20120328 page38 Reserve PC206 , PC207

12. 20120328 page3 R204,R605 CS12002FB00 change to CS12002FB25

13. 20120328 page22 HOLE14 follow Hole11

14. 20120329 page22 HOLE11,HOLE14 footprint change to H-TE256X256I118BC256D118P2

14. 20120330 page23 R280/R281/R282/R283/R276/R277/R278/R279 change back to 0 ohm resistor.

15. 20120330 page31 PC196 add

15. 20120405 page23 R276,R277,R278,R279,R280,R281,R282,R283 change to 15 ohm

Quanta Computer Inc.

PROJECT :

Z09

PROJECT :

Z09

PROJECT :

Z09

40 40Monday, April 09, 2012

5

4

DOC NO.

3A

4

PART NUMBER:

3

CHANGE LIST

3

2

APPROVED BY:PROJECT MODEL : Z09 DRAWING BY: REVISON:

2

DATE:

MODEL

1

Z09

FROM To

2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 2A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A

2010/7/20

1A

1

3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3A 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B 3B

Quanta Z09 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual