Quanta Z09 Schematic

VER : 3A

BOM P/N

Description

Z09 SYSTEM BLOCK DIAGRAM

D D

Memory Down

DDRIII-SODIMM1

256MB*16

Max. 2G

C C

B B

CCD Conn.

DMIC

BOM Option Table

A A

Reference

SNB@ IVB@ IV@

Optimize SKU

EV@

For Sandy bridge. For Ivy bridge. For UMA.

* do not stuff

Description

P14

mSATA - HDD

P20

SATA - HDD

P20

SATA - ODD

P21

USB3.0 *2 USB2.0 *2

USB2.0

P15

USB Port

(Charger)

P23

ALC271-VB6

AUDIO CODEC Daugther board

Speaker

Dual Channel DDR III 1333/1600 MHZ

P13

USB3.0(USB2.0)

P8 RTC

Azalia

P19

MIC/HP JACK

BATTERY

USB2.0

W25X16VSS1G

SPI FLASH

IMC

SATA

USB3.0

PCI-E x1

USB2.0

IHDA

Ivy Bridge

BGA 1023 17W

P2,3,4,5,6

FDI

Panther Point

PCH BGA 989

P7, 8, 9, 10, 11, 12

WPCE885

K/B Con.

P22

EM-6781-T3

HALL SENSOR

DMI

LPC

PCI-E X16

DMI(x4)

Display

PCI-E x1

LPC

eDP

SPI

P15

PCIE

2.5GT/s

Touch Pad Con.

NVIDIA GPU

N13P-GV 1GB

P27,28,29,30,31,32

X'TAL

32.768KHz

X'TAL 25MHz

SPI ROM

2M+4M

P19

Fan Driver

(128Mb x 32 IO x 4 pcs)

HDMI

PCIE-8

PCIE-3

PCIE-2

P24

P19

X'TAL

27.0MHz

BCM57780

GIGA LAN

P17

X'TAL 25MHz

RTS5209-GR

Cardreader controller

Daugther board

Batery Charger

3V/5V

+VGPU_CORE

eDP Conn.

P15

HDMI Conn.

P16

MINI CARD WLAN+BT

USB-10

P19

P31

P32

P38

Size Document Number Rev

Date: Sheet of

RJ45 Conn.

Cardreader Conn.(2in1)

+1.05V

+1.8V/+1V

+VGPU_IO

P19

P18

+VGFX_AXG

P34

CPU core

P37

Discharger

P38

Thermal Protection

Quanta Computer Inc.

PROJECT :

Block Diagram

Z09

1 40Monday, April 09, 2012

P33

P37

Ivy Bridge Processor (DMI,PEG,FDI)

DMI_TXN0<7> DMI_TXN1<7> DMI_TXN2<7>

D D

C C

B B

DP_COMPIO and ICOMPO signals should be shorted near balls and routed with

- typical impedance < 25 mohms

DMI_TXN3<7> DMI_TXP0<7>

DMI_TXP1<7> DMI_TXP2<7> DMI_TXP3<7>

DMI_RXN0<7> DMI_RXN1<7> DMI_RXN2<7> DMI_RXN3<7>

DMI_RXP0<7> DMI_RXP1<7> DMI_RXP2<7> DMI_RXP3<7>

FDI_TXN0<7> FDI_TXN1<7> FDI_TXN2<7> FDI_TXN3<7> FDI_TXN4<7> FDI_TXN5<7> FDI_TXN6<7> FDI_TXN7<7>

FDI_TXP0<7> FDI_TXP1<7> FDI_TXP2<7> FDI_TXP3<7> FDI_TXP4<7> FDI_TXP5<7> FDI_TXP6<7> FDI_TXP7<7>

FDI_FSYNC0<7> FDI_FSYNC1<7>

FDI_INT<7>

FDI_LSYNC0<7> FDI_LSYNC1<7>

eDP_ICOMPO 12mil eDP_COMPIO 4mil

EDP_AUX#<15> EDP_AUX<15>

EDP_TX0#<15>

EDP_TX0<15>

EDP_COMP INT_EDP_HPD#

EDP_AUX# EDP_AUX

EDP_TX0#

EDP_TX0

DP & PEG Compensation

+1.05V_VTT

A A

EDP_COMP

R564 24.9/F_4

+1.05V_VTT

PEG_COMP

R193 24.9/F_4

M2 P6 P1

P10

N3 P7 P3

P11

K1 M8 N4 R2

K3 M7 P4 T3

W11

AA6

V4 Y2

AC9

W10

AA7

T4 AA3 AC8

AA11 AC12

U11

AA10

AG8

AF3 AD2

AG11

AG4 AF4

AC3 AC4

AE11

AE7 AC1

AA4

AE10

AE6

eDP Hot-plug (Disable)

CAD Note: Place PU resistor within 2 inches of CPU

HPD PU/PD resistor values based on CRB and different to DG

U9A

DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3]

DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3]

DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3]

DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3]

FDI0_TX#[0] FDI0_TX#[1] FDI0_TX#[2] FDI0_TX#[3] FDI1_TX#[0] FDI1_TX#[1] FDI1_TX#[2] FDI1_TX#[3]

FDI0_TX[0] FDI0_TX[1] FDI0_TX[2] FDI0_TX[3] FDI1_TX[0] FDI1_TX[1] FDI1_TX[2] FDI1_TX[3]

FDI0_FSYNC FDI1_FSYNC

FDI_INT FDI0_LSYNC

FDI1_LSYNC

eDP_COMPIO eDP_ICOMPO eDP_HPD

eDP_AUX# eDP_AUX

eDP_TX#[0] eDP_TX#[1] eDP_TX#[2] eDP_TX#[3]

eDP_TX[0] eDP_TX[1] eDP_TX[2] eDP_TX[3]

SNB_2CBGA_1P0

DG 1.0 : The recommended AC cap value is changed to 220nF for compatibility with PCIe Gen3 on future platforms. For Gen2 only designs, it is acceptable to continue to use the 100nF capacitor.

DMI Intel(R) FDI DP

PCI EXPRESS -- GRAPHICS

INT_EDP_HPD#

2N7002E

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

H22

PEG_RX#[0]

J21

PEG_RX#[1]

B22

PEG_RX#[2]

D21

PEG_RX#[3]

A19

PEG_RX#[4]

D17

PEG_RX#[5]

B14

PEG_RX#[6]

D13

PEG_RX#[7]

A11

PEG_RX#[8]

B10

PEG_RX#[9]

PEG_RX#[10]

PEG_RX#[11]

PEG_RX#[12]

PEG_RX#[13]

PEG_RX#[14]

PEG_RX#[15]

K22

PEG_RX[0]

K19

PEG_RX[1]

C21

PEG_RX[2]

D19

PEG_RX[3]

C19

PEG_RX[4]

D16

PEG_RX[5]

C13

PEG_RX[6]

D12

PEG_RX[7]

C11

PEG_RX[8]

PEG_RX[9]

PEG_RX[10]

PEG_RX[11]

PEG_RX[12]

PEG_RX[13]

PEG_RX[14]

PEG_RX[15]

G22

PEG_TX#[0]

C23

PEG_TX#[1]

D23

PEG_TX#[2]

F21

PEG_TX#[3]

H19

PEG_TX#[4]

C17

PEG_TX#[5]

K15

PEG_TX#[6]

F17

PEG_TX#[7]

F14

PEG_TX#[8]

A15

PEG_TX#[9]

J14

PEG_TX#[10]

H13

PEG_TX#[11]

M10

PEG_TX#[12]

F10

PEG_TX#[13]

PEG_TX#[14]

PEG_TX#[15]

F22

PEG_TX[0]

A23

PEG_TX[1]

D24

PEG_TX[2]

E21

PEG_TX[3]

G19

PEG_TX[4]

B18

PEG_TX[5]

K17

PEG_TX[6]

G17

PEG_TX[7]

E14

PEG_TX[8]

C15

PEG_TX[9]

K13

PEG_TX[10]

G13

PEG_TX[11]

K10

PEG_TX[12]

G10

PEG_TX[13]

PEG_TX[14]

PEG_TX[15]

0.22uF AC coupling Caps for PCIE GEN1/2/3

+1.05V_VTT

20111104 change from 10k to 1k.

R192 1K_4

EDP_HPD

R191

100K_4

PEG_COMP

PEG_ICOMPO 12mil PEG_ICOMPI, PEG_RCOMPO 4mil,

GRN15 GRN14 GRN13 GRN12 GRN11 GRN10 GRN9 GRN8 GRN7 GRN6 GRN5 GRN4 GRN3 GRN2 GRN1 GRN0

GRP15 GRP14 GRP13 GRP12 GRP11 GRP10 GRP9 GRP8 GRP7 GRP6 GRP5 GRP4 GRP3 GRP2 GRP1 GRP0

GTN15C

C154 EV@0.22u/10V_4

GTN14C GTN14

C152 EV@0.22u/10V_4

GTN13C

C149 EV@0.22u/10V_4

GTN12C

C148 EV@0.22u/10V_4

GTN11C

C146 EV@0.22u/10V_4

GTN10C

C143 EV@0.22u/10V_4

GTN9C

C142 EV@0.22u/10V_4

GTN8C

C140 EV@0.22u/10V_4

GTN7C

C137 EV@0.22u/10V_4

GTN6C GTN6

C136 EV@0.22u/10V_4

GTN5C

C156 EV@0.22u/10V_4

GTN4C

C134 EV@0.22u/10V_4

GTN3C

C162 EV@0.22u/10V_4

GTN2C

C132 EV@0.22u/10V_4

GTN1C

C130 EV@0.22u/10V_4

GTN0C

C128 EV@0.22u/10V_4

GTP15C GTP15

C153 EV@0.22u/10V_4

GTP14C

C151 EV@0.22u/10V_4

GTP13C

C150 EV@0.22u/10V_4

GTP12C

C147 EV@0.22u/10V_4

GTP11C

C145 EV@0.22u/10V_4

GTP10C

C144 EV@0.22u/10V_4

GTP9C

C141 EV@0.22u/10V_4

GTP8C

C139 EV@0.22u/10V_4

GTP7C GTP7

C138 EV@0.22u/10V_4

GTP6C

C135 EV@0.22u/10V_4

GTP5C

C155 EV@0.22u/10V_4

GTP4C

C133 EV@0.22u/10V_4

GTP3C

C161 EV@0.22u/10V_4

GTP2C

C131 EV@0.22u/10V_4

GTP1C

C129 EV@0.22u/10V_4

GTP0C

C127 EV@0.22u/10V_4

EDP_HPD <15>

GRN[0..15] <25>

GRP[0..15] <25>

GTN15 GTN13

GTN12 GTN11 GTN10 GTN9 GTN8 GTN7

GTN5 GTN4 GTN3 GTN2 GTN1 GTN0

GTP14 GTP13 GTP12 GTP11 GTP10 GTP9 GTP8

GTP6 GTP5 GTP4 GTP3 GTP2 GTP1 GTP0

PEG_ICOMPI and RCOMPO signals should be shorted and routed with

- max length = 500 mils

- typical impedance = 43 mohms PEG_ICOMPO signals should be routed with

- max length = 500 mils

- typical impedance = 14.5 mohms

GTN[0..15] <25>

GTP[0..15] <25>

Size Document Number Rev

Date: Sheet of

Ivy Bridge 1/5

Monday, April 09, 2012

Quanta Computer Inc.

PROJECT :

Z09

2 40

Boot S3 S3 RSM

+1.5V_CPU

Ivy Bridge Processor (CLK,MISC,JTAG)

R196 *750/F_4

U9B

F49

PROC_SELECT#

C57

PROC_DETECT#

C49

CATERR#

A48

PECI

C45

PROCHOT#

D45

THERMTRIP#

C48

PM_SYNC

B46

UNCOREPWRGOOD

BE45

SM_DRAMPWROK

D44

RESET#

SNB_2CBGA_1P0

DPLL_REF_CLK#

MISC

BCLK

BCLK#

DPLL_REF_CLK

BCLK_ITP

BCLK_ITP#

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

PRDY#

PREQ#

TRST#

DBR#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

TCK TMS

TDI

TDO

MISC THERMAL PWR MANAGEMENT

CLOCKS

DDR3

JTAG & BPM

J3 H2

AG3 AG1

N59

CLK_PCIE_XDPP_R

N58

CLK_PCIE_XDPN_R

Isolate Space:20mils

AT30

BF44

SM_RCOMP_0

BE43

SM_RCOMP_1

BG43

SM_RCOMP_2

Impedance 85ohm

N53 N55

L56 L55 J58

M60 L59

K58

XDP_DBRST#_R

G58 E55 E59 G55 G59 H60 J59 J61

CLK_CPU_BCLKP <9> CLK_CPU_BCLKN <9>

20111121 Remove R5306/R5311/R5474/R5476.

TP95

TP53

R230 *0_4 R229 *0_4

CPU_DRAMRST# <4,24>

R209 140/F_4 R204 200/F_4

TP79 TP83

XDP_TCLK_VT <8,22>

XDP_TRST#

XDP_TMS_VT <8,22>

TP103

XDP_TDI_VT <22> PCH_XDP_TDO_VT <8>

20111021 Add 10k to +3V,CRB 1k 20111103 del R601

TP97 TP82 TP81 TP80 TP98 TP100 TP99 TP101

XDP_PREQ#

R233 0_4

CAD NOTE: All DDR_COMP signals should be routed such that :-

- max length = 500 mils

- trace width = 15mils and

- MB trace impedance < 68 mohms (worst case resistance)

XDP_DBRST# <7>

D D

H_SNB_IVB#<8>

EC_PECI<10,24>

H_PROCHOT#<24,33>

PM_THRMTRIP#<10>

C C

Over 130 degree C will drive low

PM_SYNC<7>

H_PWRGOOD<10>

Isolate Space:20mils

R194 75/F_4

+1.05V_VTT

B B

TP85

TP_CATERR#

TP78

H_PROCHOT#_R

R207 56_4 R206 25.5/F_4

C253

*43P/50V_4N

C718 0.1U/10V_4

TP67

PM_SYNC_R

H_PWRGOOD_R

CPU_PLTRST#_RCPU_PLTRST#

R214 *SHORT_4

R596 *SHORT_4 R595 10K_4

PM_DRAM_PWRGD_R

R190 43_4

DRAM_PWRGD

SYS_PWROK

SM_DRAMPWROK

CLK_DPLL_SSCLKP <9> CLK_DPLL_SSCLKN <9>

CLK_PCIE_XDPP <9> CLK_PCIE_XDPN <9>

100 ns after +1.5V_CPU reaches 80%

If motherboard only supports external graphics or if it supports Processor Graphics but without eDP: Connect DPLL_REF_SSCLK on Processor to GND through 1K +/5% resistor. Connect DPLL_REF_SSCLK# on Processor to VCCP through 1K +/

- 5% resistor

Place near to XDP connector

PCH_XDP_TDO_VT

+1.05V_VTT

Option for Prochot# function 68 ohm for unused, 62 ohm for used

H_PROCHOT#

XDP_TMS_VT XDP_TDI_VT

XDP_PREQ# XDP_TCLK_VT

XDP_TRST#

When MP, JTAG PU/PD resistor can be removed? (Yes Intel, TDI, TDO, TMS, TRST#, TCK,PREQ#, PRDY#)

R23251 _4

R219 62_ 4

R606 51_ 4 R231 51_ 4

R612 *5 1_4 R611 51_ 4

R228 51_ 4

+1.05V_VTT

+3V

Thermal Trip

IMVP_PWRGD<7,33>

A A

<CPU>

PM_THRMTRIP#

1 3

+1.05V_VTT

R195 1K_4

Q6 2N7002_200MA

Q5 MMBT3904-7-F_200MA

+1.5V_CPU

SYS_SHDN# <32,37>

s3 leakage circuit

+3V_S5

20111121 add Q31 becaue Vh=2.1/Vl=0.9.

R603

R604

*10K_4

*1K_4

215

4 3

PM_DRAM_PWRGD<7>

20111030 add resistor.

SYS_PWROK<7>

*2N7002DW Q42

R602 0_4

If PM_DRAM_PWEGD connector,the R5180 must stuff.

+3V_S5

+1.5V_CPU

R605 200/F_4

R610 *39_4

R598 130/F_4

MAINON_G<5,37>

2 1

3 5

R608 *0_4

C727

0.1u/10V_4

U33

74AHC1G09

PM_DRAM_PWRGD_RPM_DRAM_PWRGD_Q

Q44 *2N7002K

20111128 change net to PCI_PLTRST#

PCI_PLTRST#<9,24>

Size Document Number Rev

Date: Sheet of

Ivy Bridge 2/5

Monday, April 09, 2012

1 2

IN GND3OUT

74LVC1G07GW_NC

R186 *1.5K/F_4

IN OUT

L L H High-Z

Quanta Computer Inc.

PROJECT :

VCC5NC

CPU_PLTRST#_R

Z09

C190

0.1U/10V_4X

CPU_PLTRST#

3 40

Sandy Bridge Processor (DDR3)

AW59 AW58

BD13 BF12

BD10 BD14 BE13 BF16 BE17 BE18 BE21 BE14 BG14 BG18 BF19 BD50 BF48 BD53 BF52 BD49 BE49 BD54 BE53 BF56 BE57 BC59 AY60 BE54 BG54 BA58

AU58 AN61 AN59 AU59 AU61 AN58 AR58 AK58 AL58 AG58 AG59 AM60 AL59 AF61 AH60

BG39 BD42 AT22

AV43 BF40 BD45

AL4 AL1 AN3 AR4 AK4 AK3 AN4 AR1 AU4 AT2 AV4 BA4 AU3 AR3 AY2 BA3 BE9 BD9

BF8

U9D

SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10 ] SB_DQ[11 ] SB_DQ[12 ] SB_DQ[13 ] SB_DQ[14 ] SB_DQ[15 ] SB_DQ[16 ] SB_DQ[17 ] SB_DQ[18 ] SB_DQ[19 ] SB_DQ[20 ] SB_DQ[21 ] SB_DQ[22 ] SB_DQ[23 ] SB_DQ[24 ] SB_DQ[25 ] SB_DQ[26 ] SB_DQ[27 ] SB_DQ[28 ] SB_DQ[29 ] SB_DQ[30 ] SB_DQ[31 ] SB_DQ[32 ] SB_DQ[33 ] SB_DQ[34 ] SB_DQ[35 ] SB_DQ[36 ] SB_DQ[37 ] SB_DQ[38 ] SB_DQ[39 ] SB_DQ[40 ] SB_DQ[41 ] SB_DQ[42 ] SB_DQ[43 ] SB_DQ[44 ] SB_DQ[45 ] SB_DQ[46 ] SB_DQ[47 ] SB_DQ[48 ] SB_DQ[49 ] SB_DQ[50 ] SB_DQ[51 ] SB_DQ[52 ] SB_DQ[53 ] SB_DQ[54 ] SB_DQ[55 ] SB_DQ[56 ] SB_DQ[57 ] SB_DQ[58 ] SB_DQ[59 ] SB_DQ[60 ] SB_DQ[61 ] SB_DQ[62 ] SB_DQ[63 ]

SB_BS[0] SB_BS[1] SB_BS[2]

SB_CAS# SB_RAS# SB_WE #

SNB_2CBGA_1P0

BA34

SB_CLK[0 ]

AY34

SB_CLK#[0]

AR22

SB_CKE[0 ]

BA36 BB36 BF27

BE41 BE47

AT43 BG47

AL3 AV3 BG11 BD17 BG51 BA59 AT60 AK59

AM2 AV1 BE11 BD18 BE51 BA61 AR59 AK61

BF32 BE33 BD33 AU30 BD30 AV30 BG30 BD29 BE30 BE28 BD43 AT28 AV28 BD46 AT26 AU22

M_B_CLK1 M_B_CLK1# M_B_CKE1

M_B_CS#1

M_B_ODT1

M_B_DQSN0 M_B_DQSN1 M_B_DQSN2 M_B_DQSN3 M_B_DQSN4 M_B_DQSN5 M_B_DQSN6 M_B_DQSN7

M_B_DQSP0 M_B_DQSP1 M_B_DQSP2 M_B_DQSP3 M_B_DQSP4 M_B_DQSP5 M_B_DQSP6 M_B_DQSP7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

SB_CLK[1 ]

SB_CLK#[1]

SB_CKE[1 ]

SB_CS#[0 ] SB_CS#[1 ]

SB_ODT[0] SB_ODT[1]

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0 ] SB_DQS[1 ] SB_DQS[2 ] SB_DQS[3 ] SB_DQS[4 ] SB_DQS[5 ] SB_DQS[6 ] SB_DQS[7 ]

DDR SYSTEM MEMORY B

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]

SB_MA[9] SB_MA[10 ] SB_MA[11 ] SB_MA[12 ] SB_MA[13 ] SB_MA[14 ] SB_MA[15 ]

M_B_CLK0 <14> M_B_CLK0# <14> M_B_CKE0 <14>

TP31

M_B_CS#0 <14>

TP32

M_B_ODT0 <14>

TP33

M_B_DQSN[7:0] <14>

M_B_DQSP[7:0] <14>

M_B_A[15:0] <14>

M_B_CLK1

AR11

AT13 AU13

BA13 BB11

AY13 AV14 AR14 AY17 AR19 BA14 AU14 BB14 BB17 BA45 AR43

AW48

BC48 BC45 AR45 AT48 AY48 BA49 AV49 BB51 AY53 BB49 AU49 BA53 BB55 BA55 AV56 AP50 AP53 AV54 AT54 AP56 AP52 AN57 AN53 AG56 AG53 AN55 AN52 AG55 AK56

BD37 BF36 BA28

BE39 BD39 AT41

AP11 AJ10

AG6

AJ6 AL6 AJ8

AL8 AL7

AP6 AU6 AV9 AR6 AP8

BC7 BB7

BA7 BA9 BB9

U9C

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10 ] SA_DQ[11 ] SA_DQ[12 ] SA_DQ[13 ] SA_DQ[14 ] SA_DQ[15 ] SA_DQ[16 ] SA_DQ[17 ] SA_DQ[18 ] SA_DQ[19 ] SA_DQ[20 ] SA_DQ[21 ] SA_DQ[22 ] SA_DQ[23 ] SA_DQ[24 ] SA_DQ[25 ] SA_DQ[26 ] SA_DQ[27 ] SA_DQ[28 ] SA_DQ[29 ] SA_DQ[30 ] SA_DQ[31 ] SA_DQ[32 ] SA_DQ[33 ] SA_DQ[34 ] SA_DQ[35 ] SA_DQ[36 ] SA_DQ[37 ] SA_DQ[38 ] SA_DQ[39 ] SA_DQ[40 ] SA_DQ[41 ] SA_DQ[42 ] SA_DQ[43 ] SA_DQ[44 ] SA_DQ[45 ] SA_DQ[46 ] SA_DQ[47 ] SA_DQ[48 ] SA_DQ[49 ] SA_DQ[50 ] SA_DQ[51 ] SA_DQ[52 ] SA_DQ[53 ] SA_DQ[54 ] SA_DQ[55 ] SA_DQ[56 ] SA_DQ[57 ] SA_DQ[58 ] SA_DQ[59 ] SA_DQ[60 ] SA_DQ[61 ] SA_DQ[62 ] SA_DQ[63 ]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE #

SNB_2CBGA_1P0

AU36

SA_CLK[0 ]

AV36

SA_CLK#[0]

AY26

SA_CKE[0 ]

AT40 AU40 BB26

BB40 BC41

AY40 BA41

AL11 AR8 AV11 AT17 AV45 AY51 AT55 AK55

AJ11 AR10 AY11 AU17 AW45 AV51 AT56 AK54

M_A_CLK1 M_A_CLK1# M_A_CKE1

M_A_CS#1

M_A_ODT1

M_A_DQSN0 M_A_DQSN1 M_A_DQSN2 M_A_DQSN3 M_A_DQSN4 M_A_DQSN5 M_A_DQSN6 M_A_DQSN7

M_A_DQSP0 M_A_DQSP1 M_A_DQSP2 M_A_DQSP3 M_A_DQSP4 M_A_DQSP5 M_A_DQSP6 M_A_DQSP7

SA_CLK[1 ]

SA_CLK#[1]

SA_CKE[1 ]

SA_CS#[0 ] SA_CS#[1 ]

SA_ODT[0] SA_ODT[1]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0 ] SA_DQS[1 ] SA_DQS[2 ] SA_DQS[3 ] SA_DQS[4 ] SA_DQS[5 ] SA_DQS[6 ] SA_DQS[7 ]

DDR SYSTEM MEMORY A

BG35 BB34 BE35 BD35 AT34 AU34 BB32 AT32 AY32 AV32 BE37 BA30 BC30 AW41 AY28 AU26

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10 ] SA_MA[11 ] SA_MA[12 ] SA_MA[13 ] SA_MA[14 ] SA_MA[15 ]

M_A_CLK0 <13> M_A_CLK0# <13> M_A_CKE0 <13>

M_A_CLK1 <13> M_A_CLK1# <13> M_A_CKE1 <13>

M_A_CS#0 <13> M_A_CS#1 <13>

M_A_ODT0 <13> M_A_ODT1 <13>

M_A_DQSN[7:0] <13>

M_A_DQSP[7:0] <13>

M_A_A[15:0] <13>

M_A_DQ[63:0]<13>

D D

C C

M_A_BS#0<13> M_A_BS#1<13>

B B

M_A_BS#2<13>

M_A_CAS#<13> M_A_RAS#<13> M_A_WE#<13>

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

M_B_DQ[63:0]<14>

M_B_BS#0<14> M_B_BS#1<14> M_B_BS#2<14>

M_B_CAS#<14> M_B_RAS#<14> M_B_WE#<14>

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

R588

+0.75V_DDR_VTT

C758

1u/6.3V_4

20120112 for memory down PU CAP.

+3V_S5

s3 leakage circuit

S3 circuit:- DRAM_RST# to memory should be high during S3

A A

DDR3_DRAMRST#<13,14> CPU_DRAMRST# <3,24>

DRAMRST_CNTRL_PCH<9>

EC_DRAMRST_CNTRL<24>

DEEPS3_EC<13,14>

20120204 Change to EC for new BIOS 0.6

+1.5VSUS

R577 1K/F_4

R573 *0_4

201201119 move R358 to near Q38 and del net DRAMRST_CNTRL_PCH, and EC_DRAMRST_CNTRL and R616.

R358 1K_4

R579 *0_4

Q38 2N7002K

R580 1K/F_4

R582

4.99K/F_4R574 0_4

C610

0.047u/10V_4

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

R550 36_4 R555 36_4 R554 36_4 R531 36_4 R562 36_4 R565 36_4 R570 36_4 R569 36_4 R571 36_4 R557 36_4 R537 36_4 R563 36_4 R549 36_4 R567 36_4 R568 36_4 R536 36_4

+0.75V_DDR_VTT

M_B_WE# M_B_CAS# M_B_RAS# M_B_BS#0 M_B_BS#2 M_B_CKE0 M_B_ODT0 M_B_CS#0 M_B_BS#1

R535 36_4 R539 36_4 R542 36_4 R534 36_4 R533 36_4 R540 36_4 R541 36_4 R538 36_4 R532 36_4

1u/6.3V_4

+0.75V_DDR_VTT

C753

C755

C756

C757

C759

C754

10u/6.3V_8

1u/6.3V_4

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

Date: Sheet of

Monday, April 09, 2012

Date: Sheet of

Monday, April 09, 2012

Date: Sheet of

Monday, April 09, 2012

PROJECT :

Ivy Bridge 3/5

Z09

M_B_CLK1#

4 40

75/F_4

20120120 remove C621 for debug IC.

20120120 remove C622 for debug IC.

C244

C240

2.2u/10V_4

C658

C683

2.2u/10V_4

C646

C628

2.2u/10V_4

C685

C687

2.2u/10V_4

C245

C672

2.2u/10V_4

R203 *SHORT_4

C235 10u/6.3V_6

C697 10u/6.3V_6

C696 10u/6.3V_6

C629

2.2u/10V_4

C684

2.2u/10V_4

C232

2.2u/10V_4

C695

2.2u/10V_4

C648

2.2u/10V_4

D D

C231

2.2u/10V_4

C C

C669

2.2u/10V_4

C251

2.2u/10V_4

C671

2.2u/10V_4

C673

2.2u/10V_4

CPU Core Power

IVY 17W:TDC 33A

B B

IVY SPEC

1.9mΩ/LoadlineDesign total : 2.2uF x 35 total : 22uF x 12 tatal : 470u x3(Power side*1)

Cose down

IVY SPEC

1.9mΩ/LoadlineDesign total : 2.2uF x 35 total : 10uF x 12 tatal : 470u x1(Power side*1)

A A

Layout note: need routing together and ALERT need between CLK and DATA

SVID CLK

H_CPU_SVIDCLK

Sandy Bridge Processor (POWER)

U9F

+VCC_CORE

A26

VCC[1]

A29

VCC[2]

A31

VCC[3]

C674

470u/2V_7343

C238 10u/6.3V_6

C704 10u/6.3V_6

C703 10u/6.3V_6

C241

2.2u/10V_4

C645

2.2u/10V_4

C239

2.2u/10V_4

C647

2.2u/10V_4

C661

2.2u/10V_4

C247

470u/2V_7343

A34 A35 A38 A39 A42 C26 C27 C32 C34 C37 C39 C42 D27 D32 D34 D37 D39 D42 E26 E28 E32 E34 E37 E38 F25 F26 F28 F32 F34 F37 F38 F42 G42 H25 H26 H28 H29 H32 H34 H35 H37 H38 H40 J25 J26 J28 J29 J32 J34 J35 J37 J38 J40 J42 K26 K27 K29 K32 K34 K35 K37 K39 K42 L25 L28 L33 L36 L40 N26 N30 N34 N38

VCC[4] VCC[5] VCC[6] VCC[7] VCC[8] VCC[9] VCC[10] VCC[11] VCC[12] VCC[13] VCC[14] VCC[15] VCC[16] VCC[17] VCC[18] VCC[19] VCC[20] VCC[21] VCC[22] VCC[23] VCC[24] VCC[25] VCC[26] VCC[27] VCC[28] VCC[29] VCC[30] VCC[31] VCC[32] VCC[33] VCC[34] VCC[35] VCC[36] VCC[37] VCC[38] VCC[39] VCC[40] VCC[41] VCC[42] VCC[43] VCC[44] VCC[45] VCC[46] VCC[47] VCC[48] VCC[49] VCC[50] VCC[51] VCC[52] VCC[53] VCC[54] VCC[55] VCC[56] VCC[57] VCC[58] VCC[59] VCC[60] VCC[61] VCC[62] VCC[63] VCC[64] VCC[66] VCC[67] VCC[68] VCC[69] VCC[70] VCC[71] VCC[72] VCC[73] VCC[74] VCC[75] VCC[76]

SNB_2CBGA_1P0

C692 10u/6.3V_6

C246

2.2u/10V_4

C670

2.2u/10V_4

C678

2.2u/10V_4

C686

2.2u/10V_4

C649

2.2u/10V_4

C237 10u/6.3V_6

C236 10u/6.3V_6

C693 10u/6.3V_6

C653

2.2u/10V_4

C657

2.2u/10V_4

C250

2.2u/10V_4

C659

2.2u/10V_4

C660

2.2u/10V_4

Place PU resistor close to CPU

SVID DATA

VR_SVID_CLK <33>

H_CPU_SVIDDAT

CORE SUPPLY

POWER

+1.05V_VTT +1.05V_VTT

R202 130/F_4

R205 *SHORT_4

VCCIO[10] VCCIO[11] VCCIO[12] VCCIO[13] VCCIO[14] VCCIO[15] VCCIO[16] VCCIO[17] VCCIO[18] VCCIO[19] VCCIO[20] VCCIO[21] VCCIO[22] VCCIO[23] VCCIO[24] VCCIO[25] VCCIO[26] VCCIO[27] VCCIO[28] VCCIO[29]

VCCIO[30] VCCIO[31] VCCIO[32] VCCIO[33]

PEG AND DDRSENSE LINES SVID QUIET RAILS

VCCIO[34] VCCIO[35] VCCIO[36] VCCIO[37] VCCIO[38] VCCIO[39] VCCIO[40] VCCIO[41] VCCIO[42] VCCIO[43] VCCIO[44] VCCIO[45] VCCIO[46] VCCIO[47] VCCIO[48] VCCIO[49]

VCCIO_SEL

VCCPQE[1] VCCPQE[2]

VIDALERT#

VCC_SENSE VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

VR_SVID_DATA <33>

CPU VCCIO

IVY 17W:8.5A

Cose down

SNB : Spec

330uF/6mohm x 2

+1.05V_VTT

AF46

VCCIO[1]

AG48

VCCIO[3]

AG50

VCCIO[4]

AG51

VCCIO[5]

AJ17

VCCIO[6]

AJ21

VCCIO[7]

AJ25

AJ43 AJ47 AK50 AK51 AL14 AL15 AL16 AL20 AL22 AL26 AL45 AL48 AM16 AM17 AM21 AM43 AM47 AN20 AN42 AN45 AN48

AA14 AA15 AB17 AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20 AG15 AG16 AG17 AG20 AG21 AJ14 AJ15

W16 W17

BC22

AM25 AN22

A44 B43 C44

F43 G43

AN16 AN17

C181 10u/6.3V_6

C656 10u/6.3V_6

C630 1u/6.3V_4

C619 1u/6.3V_4

R187 *SHORT_6

VCCIO_SEL

R581 *SHORT_4 C632 1U/6.3V_4X

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

R591 100_4

R589 100_4

R576 10_4

R578 10_4

C603 *330u/2V_7343

C639 10u/6.3V_6

C180 10u/6.3V_6

C620 1u/6.3V_4

C615 1u/6.3V_4

TP64

VCCIO[8] VCCIO[9]

VCCIO50 VCCIO51

VIDSCLK VIDSOUT

330uF/6mohm x 1

10uF x 10

1uF x 26

C215 330u/2V_7343

C652

C182

C184

10u/6.3V_6

C183

C604

C710

10u/6.3V_6

C642

C611

C624

C635

1u/6.3V_4

C641

C694

C623

C633

1u/6.3V_4

IVY SPEC 22uF_8 x7 Socket TOP cavity 22uF_8 x5 Socket BOT cavity 22uF_8 x2 Socket TOP cavity (no stuff) 22uF_8 x5 Socket BOT cavity (no stuff) 330uF_7343 x2

+1.05V_VTT

Voltage select ion for VCCIO: this pin must be pulled high on the motherb oard

On CRB H_SNB_IVB#_PWRCTRL = low, 1 .0V H_SNB_IVB#_PWRCTRL = high/N C, 1.05V

+1.05V_VTT

+VCC_CORE

VCC_SENSE <33> VSS_SENSE <33>

+1.05V_VTT

VCCP_SENSE <34> VSSP_SENSE <34>

C709

C626

C186

C702

1u/6.3V_4

C634

C616

C605

C705

1u/6.3V_4

Place PU resistor close to CPU

R213 75/F_4

VR_SVID_ALERT#_RH_CPU_SVIDALRT#

R208 43_4

C715 1u/6.3V_4

C612 1u/6.3V_4

R212 *SHORT_4

C716 1u/6.3V_4

C613 1u/6.3V_4

SVID ALERT

C185 1u/6.3V_4

C614 1u/6.3V_4

CPU VCCAXG

IVY 17W:TDC 18A

Spec

3.9mΩ/LoadlineDesign total : 1uF x 11 total : 10uF x 6 total : 22uF x 6 tatal : 470u x 1(power side*2)

IVY SPEC 330uF x1, 10uF_8 x1 Socket BOT edge, 10uF_8 x2 Socket BOT cavity.

CPU VCCSA

IVY 17W: 6A

Spec

330uF/7mohm x 1 10uF x 5 1uF x 5

VR_SVID_ALERT# <33 >

Cose down

3.9mΩ/LoadlineDesign total : 1uF x 11 total : 10uF x 12 tatal : 470u x 1(power side*2)

C729 10u/6.3V_6

C278 10u/6.3V_6

C711 1u/6.3V_4

VCCAXG_SENSE/V SSAXG_SENSE R =100, Trace impedanc e 15.5~34.5, <25mils.

CPU VCCPL

IVY 17W:1.5A

Real

Spec

10uF x 1

330uF/7mohm x 1 1uF x 2

IVY SPEC 330uF x1, 10uF_8 x1, 1uF_4 x2 Socket BOT edge.

Real

10uF x 3

S3 circuit: 1.5V input to IVB is gated & IVB Read Vref 0.75V is gated

+1.8V

1uF x 2

C627 10u/6.3V_6

+SMDDR_VREF +VDDR_REF_CPU +1.5V_CPU

R234 *0_8

321

MAIND

MAIND<32,35,37>

Sandy Bridge Processor (GRAPHIC POWER)

C730

470u/2V_7343

C283

C282

C281

C728

C726

10u/6.3V_6

C725 10u/6.3V_6

C712 1u/6.3V_4

C706 1u/6.3V_4

C284

C724

C285 10u/6.3V_6

C708 1u/6.3V_4

C714 1u/6.3V_4

VCC_AXG_SENSE<33> VSS_AXG_SENSE<33>

R566 *SHORT_8 R560 *SHORT_8

C618 10u/6.3V_6

C608 1u/6.3V_4

S3 S TUFF N O_STUFF enable - disable -

Q7 2N7002K

C292

10u/6.3V_6

C701

C707

C713

1u/6.3V_4

C700

C698

C699

1u/6.3V_4

R593 100_4

+VCC_GFX

R594 100_4

CPU_VCCPLL

C192

C200

1u/6.3V_4

C636

C609

C651

10u/6.3V_6

C631

C637

C617

C625

1u/6.3V_4

R5347/R6362

20111024 from +1.5VSUS change to +1.5V_CPU

R221 *1K/F_4

R218 100K_4

R215 *1K/F_4

change to 1K/F_4

TP69

TP70

C178 330u/2V_7343

+VCC_GFX

C177

*330u/2V_7343

U9G

AA46 AB47 AB50 AB51 AB52 AB53 AB55 AB56 AB58 AB59 AC61 AD47 AD48 AD50 AD51 AD52 AD53 AD55 AD56 AD58 AD59 AE46

N45 P47 P48 P50 P51 P52 P53 P55 P56 P61 T48 T58 T59 T61 U46 V47 V48 V50 V51 V52 V53 V55 V56 V58

V59 W50 W51 W52 W53 W55 W56 W61

Y48

Y61

F45

G45

BB3 BC1 BC4

+VCCSA

L17

L21

N16

N20

N22

P17

P20

R16

R18

R21

U15

V16

V17

V18

V21 W20

SNB_2CBGA_1P0

VAXG[1] VAXG[2] VAXG[3] VAXG[4] VAXG[5] VAXG[6] VAXG[7] VAXG[8] VAXG[9] VAXG[10] VAXG[11] VAXG[12] VAXG[13] VAXG[14] VAXG[15] VAXG[16] VAXG[17] VAXG[18] VAXG[19] VAXG[20] VAXG[21] VAXG[22] VAXG[23] VAXG[24] VAXG[25] VAXG[26] VAXG[27] VAXG[28] VAXG[29] VAXG[30] VAXG[31] VAXG[32]

GRAPHICS

VAXG[33] VAXG[34] VAXG[35] VAXG[36] VAXG[37] VAXG[38] VAXG[39] VAXG[40] VAXG[41] VAXG[42] VAXG[43] VAXG[44] VAXG[45] VAXG[46] VAXG[47] VAXG[48] VAXG[49] VAXG[50] VAXG[51] VAXG[52] VAXG[53] VAXG[54] VAXG[55] VAXG[56]

SENSE

LINES

VAXG_SENSE VSSAXG_SENSE

1.8V RAIL

VCCPLL[1] VCCPLL[2] VCCPLL[3]

VCCSA[1] VCCSA[2] VCCSA[3]

SA RAIL

VCCSA[4] VCCSA[5] VCCSA[6] VCCSA[7] VCCSA[8] VCCSA[9] VCCSA[10] VCCSA[11] VCCSA[12] VCCSA[13] VCCSA[14] VCCSA[15] VCCSA[16]

20111107 stuff Q5010 and un-staff R5347/R362.

4.5A

R210 *0_1206

R211 *0_1206

Q41 AO4496

782 5

MAIND

MAINON_G<3,37>

DDR3 - 1.5V RAILS

POWER

QUIET RAILS

VDDQ_SENSE

VSS_SENSE_VDDQ

SENSE LINES

VCCSA_SENSE

VCCSA_VID[0]

VCCSA_VID[1]

1 36

C688 470P/50V_4

MAINON_G

CAD Note: +VDDR_REF_CPU should have 10 mil trace width

AY43

+VDDR_REF_CPU

SM_VREF

+1.5V_CPU

AJ28

VDDQ[1]

AJ33

VDDQ[2]

AJ36

VDDQ[3]

AJ40

C667

VDDQ[4]

AL30

10u/6.3V_6

VDDQ[5]

AL34

VDDQ[6]

AL38

VDDQ[7]

AL42

VDDQ[8]

AM33

VDDQ[9]

AM36

VDDQ[10]

AM40

VDDQ[11]

AN30

VDDQ[12]

AN34

C666

VDDQ[13]

AN38

10u/6.3V_6

VDDQ[14]

AR26

VDDQ[15]

AR28

VDDQ[16]

AR30

VDDQ[17]

AR32

VDDQ[18]

AR34

VDDQ[19]

AR36

C655

VDDQ[20]

AR40

VDDQ[21]

AV41

1u/6.3V_4

VDDQ[22]

AW26

VDDQ[23]

BA40

VDDQ[24]

BB28

VDDQ[25]

BG33

VDDQ[26]

C676 1u/6.3V_4

AM28

VCCDQ[1]

AN26

VCCDQ[2]

C650 1U/6.3V_4X

BC43

R590 *51_4

BA43

R592 *51_4

R575 *100/F_4

U10

SNB_IVB# N.A at SNB EDS #27637 0.7v1

R217 *10K_4

C767 *33n/10V_4

D48

R220 IVB@0_4

D49

R597 *10K_4

R94 for SN Bridge

+1.5V_CPU+1.5VSUS

R583 220_8

Q39 DMN601K-7

Size Document Number Rev

Date: Sheet of

CPU VDDQ

IVY 45W: 5A

Spec

330uF/6mohm x 1 10uF x 8 1uF x 10

C682

C681

C662

10u/6.3V_6

C691

*10u/6.3V_6

C665 1u/6.3V_4

C690 1u/6.3V_4

Monday, April 09, 20 12

C668

10u/6.3V_6

C242

C680

*10u/6.3V_6

330u/2V_7343

C664

C677

C654

1u/6.3V_4

C689

C675

C663

1u/6.3V_4

+1.5V_CPU

+VCCSA

VCCSA_SENSE <36>

201201117 C767 for Intel fw issue, if solve need un-stuff.

VCCSA_VID0 <36> VCCSA_VID1 <36>

A 1-K pull-down resistor should be placed on the VCCSA VID lines. This will ensure the VID is 00 prior to VCCIO stability..

For SN Bridge

VID[1] +VCCSA

0.9V

0.8V

For IV Bridge

VID[1]

VID[0]

Quanta Computer Inc.

PROJECT :

Z09

PROJECT :

Z09

PROJECT :

Z09

Ivy Bridge 4/5

5 40

+VCCSA

0.9V

0.8V

0.725V

0.675V

Sandy Bridge Processor (GND)

U9H

A13

VSS[1]

AG10 AG14 AG18 AG47 AG52 AG61

AM13 AM20 AM22 AM26 AM30 AM34

AA13 AA50 AA51 AA52 AA53 AA55 AA56

AB16 AB18 AB21 AB48 AB61 AC10 AC14 AC46

AD17 AD20

AD61 AE13

AF17 AF21 AF47 AF48 AF50 AF51 AF52 AF53 AF55 AF56 AF58 AF59

AH58 AJ13 AJ16 AJ20 AJ22 AJ26 AJ30 AJ34 AJ38 AJ42 AJ45 AJ48

AK52 AL10 AL13 AL17 AL21 AL25 AL28 AL33 AL36 AL40 AL43 AL47 AL61

A17 A21 A25 A28 A33 A37 A40 A45 A49 A53

AA1

AA8

AC6

AD4

AE8 AF1

AG7 AH4

AJ7

AK1

VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90]

SNB_2CBGA_1P0

VSS

D D

C C

B B

A A

VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98]

VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180]

AM38 AM4 AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54 AP10 AP51 AP55 AP7 AR13 AR17 AR21 AR41 AR48 AR61 AR7 AT14 AT19 AT36 AT4 AT45 AT52 AT58 AU1 AU11 AU28 AU32 AU51 AU7 AV17 AV21 AV22 AV34 AV40 AV48 AV55 AW13 AW43 AW61 AW7 AY14 AY19 AY30 AY36 AY4 AY41 AY45 AY49 AY55 AY58 AY9 BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53 BC13 BC5 BC57 BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56 BD8 BE5 BG13

R599

*SNB@0_4

U9I

BG17

VSS[181]

BG21

VSS[182]

BG24

VSS[183]

BG28

VSS[184]

BG37

VSS[185]

BG41

VSS[186]

BG45

VSS[187]

BG49

VSS[188]

BG53

VSS[189]

BG9

VSS[190]

C29

VSS[191]

C35

VSS[192]

C40

VSS[193]

D10

VSS[194]

D14

VSS[195]

D18

VSS[196]

D22

VSS[197]

D26

VSS[198]

D29

VSS[199]

D35

VSS[200]

VSS[201]

D40

VSS[202]

D43

VSS[203]

D46 D50 D54 D58

D6 E25 E29

E3 E35 E40 F13 F15 F19 F29 F35 F40 F55 G48 G51

G6 G61 H10 H14 H17 H21

H4 H53 H58

J49

J55 K11 K21 K51

K8 L16 L20 L22 L26 L30 L34 L38 L43 L48 L61 M11 M15

VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249] VSS[250]

SNB_2CBGA_1P0

VSS

Processor Strapping

CFG2 (PCI-E Static x16 Lane Reversal)

CFG3 (PCI-E Static x4 Lane Reversal)

CFG4

(DP Presence Strap)

CFG7 (PEG Defer Training)

VSS[251]

M58

VSS[252]

VSS[253]

VSS[254]

N17

VSS[255]

N21

VSS[256]

N25

VSS[257]

N28

VSS[258]

N33

VSS[259]

N36

VSS[260]

N40

VSS[261]

N43

VSS[262]

N47

VSS[263]

N48

VSS[264]

N51

VSS[265]

N52

VSS[266]

N56

VSS[267]

N61

VSS[268]

P14

VSS[269]

P16

VSS[270]

P18

VSS[271]

P21

VSS[272]

P58

VSS[273]

P59

VSS[274]

VSS[275]

R17

VSS[276]

R20

VSS[277]

VSS[278]

R46

VSS[279]

VSS[280]

T47

VSS[281]

T50

VSS[282]

T51

VSS[283]

T52

VSS[284]

T53

VSS[285]

T55

VSS[286]

T56

VSS[287]

U13

VSS[288]

VSS[289]

V20

VSS[290]

V61

VSS[291]

W13

VSS[292]

W15

VSS[293]

W18

VSS[294]

W21

VSS[295]

W46

VSS[296]

VSS[297]

VSS[298]

Y47

VSS[299]

Y58

VSS[300]

Y59

VSS[301]

VSS_NCTF_1

A57

VSS_NCTF_2

BC61

VSS_NCTF_3

BD3

VSS_NCTF_4

BD59

VSS_NCTF_5

BE4

VSS_NCTF_6

BE58

VSS_NCTF_7

BG5

VSS_NCTF_8

BG57

VSS_NCTF_9

VSS_NCTF_1 0 VSS_NCTF_1 1 VSS_NCTF_1 2 VSS_NCTF_1 3 VSS_NCTF_1 4

C58 D59 E1 E61

NCTF

The CFG signals have a default value of '1' if not terminated on the board.

1 0

Normal Operation

Disable; No physical DP attached to eDP

PEG train immediately following xxRESETB de assertion

TP76 TP96

Lane Reversed

Enable; An ext DP device is connected to eDP

PEG wait for BIOS training

Sandy Bridge Processor (RESERVED, CFG)

BE7 SA_DIMM_VREFDQ B

G7 SB_DIMM_VREFDQ

BE7

RSVD28

BG7

RSVD29

N42

RSVD30

L42

RSVD31

L45

RSVD32

L47

RSVD33

M13

RSVD34

M14

RSVD35

U14

RSVD36

W14

RSVD37

P13

RSVD38

AT49

RSVD39

K24

RSVD40

AH2

RSVD41

AG13

RSVD42

AM14

RSVD43

AM15

RSVD44

N50

RSVD45

A4 C4 D3 D1 A58 A59 C59 A61 C61 D61 BD61 BE61 BE59 BG61 BG59 BG58 BG4 BG3 BE3 BG1 BE1 BD1

CFG2

R226 1K/F_4

20111102 stuff for revers

CFG3

R224 *1K/F_4

CFG4

R223 1K/F_4

CFG7

R222 *1K/F_4

Quanta Computer Inc.

PROJECT :

Ivy Bridge 5/5

Monday, April 09, 2012

R572 *1K_4

SMDDR_VREF_DQ0_M3 <13> SMDDR_VREF_DQ1_M3 <14>

R197 *1K_4

processor signal balls BF3 and BG4 for Ivy Bridge 4-core and balls BE7 and BG7 for Ivy Bridge 2-core

for M3 solution need R5265/R5266, W/O M3 then NC

Z09

TP65 TP68

TP66 TP72

TP74

TP71 TP73

CFG1 CFG2 CFG3 CFG4CFG4 CFG5 CFG6 CFG7

U9E

B50

CFG[0]

C51

CFG[1]

B54

CFG[2]

D53

CFG[3]

A51

CFG[4]

C53

CFG[5]

C55

CFG[6]

H49

CFG[7]

A55

CFG[8]

H51

CFG[9]

K49

CFG[10]

K53

CFG[11]

F53

CFG[12]

G53

CFG[13]

L51

CFG[14]

F51

CFG[15]

D52

CFG[16]

L53

CFG[17]

H43

VCC_VAL_ SENSE

K43

VSS_VAL _SENSE

H45

VAXG_VA L_SENSE

K45

VSSAXG_ VAL_SE NSE

F48

VCC_DIE_S ENSE

H48

RSVD6

K48

RSVD7

BA19

RSVD8

AV19

RSVD9

AT21

RSVD10

BB21

RSVD11

BB19

RSVD12

AY21

RSVD13

BA22

RSVD14

AY22

RSVD15

AU19

RSVD16

AU21

RSVD17

BD21

RSVD18

BD22

RSVD19

BD25

RSVD20

BD26

RSVD21

BG22

RSVD22

BE22

RSVD23

BG26

RSVD24

BE26

RSVD25

BF23

RSVD26

BE24

RSVD27

SNB_2CBGA_1P0

RESERVED

DC_TEST_A4 DC_TEST_C4 DC_TEST_D3

DC_TEST_D1 DC_TEST_A58 DC_TEST_A59 DC_TEST_C59 DC_TEST_A61 DC_TEST_C61 DC_TEST_D61

DC_TEST_BD61 DC_TEST_BE61 DC_TEST_BE59 DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58

DC_TEST_BG4 DC_TEST_BG3 DC_TEST_BE3 DC_TEST_BG1 DC_TEST_BE1 DC_TEST_BD1

CFG5

R225 *1K/F_4

CFG6

R227 *1K/F_4

CFG[6:5] (PCIE Port Bifurcation Straps)

11: (Default) x16 - Device 1 functions 1 and 2 disabled 10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled 01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

Size Document Number Rev

Date: Sheet of

6 40

CPT/PPT (DMI,FDI,PM)

D D

20111102 DMI reverse 20111111 DMI change to normal

C C

SYS_PWROK

PWROK_EC

B B

PCH Pull-high/low(CLG) System PWR_OK(CLG)

CRB 1.0 change R5196 to 1K

CLKRUN# XDP_DBRST#

PCH_RSMRST#

A A

SYS_PWROK

DMI_RXN0<2> DMI_RXN1<2> DMI_RXN2<2> DMI_RXN3<2>

DMI_RXP0<2> DMI_RXP1<2> DMI_RXP2<2> DMI_RXP3<2>

DMI_TXN0<2> DMI_TXN1<2> DMI_TXN2<2> DMI_TXN3<2>

DMI_TXP0<2> DMI_TXP1<2> DMI_TXP2<2> DMI_TXP3<2>

R505 49.9/F_4

+1.05V_VTT

R502 750/F_4

20110214 add SUSWAEN to SUSACK connector.

SUSWARN#_R

R642 0_4 R91 *0_4

SUSACK#<24>

XDP_DBRST#<3>

C431 *1U/10V_4

R405 *SHORT_4

PM_DRAM_PWRGD<3>

PCH_RSMRST#<24>

IOAC_PCIERST#<20,24>

DNBSWON#<24>

ACPRESENT<31>

R433 4.99K/F_4 R432 *1K_4 R76 10K_4

R382 *0_4

R414 *SHORT_4

PM_PWRBTN#

TP40

R403 *SHORT_4

R404 *SHORT_4

R635 *0_4

R69 *SHORT_4

ACPRESENT

+3V

PM_RI# PM_BATLOW# PCIE_WAKE#_ LAN SLP_LAN# SUSWARN#_R ACPRESENT

PM_DRAM_PWRGD

wo S3 leakage, un-stuff R5180

XDP_DBRST#

CRB 1.0 uses 1k

BC24 BE20 BG18 BG20

BE24 BC20 BJ18 BJ20

AW24 AW20 BB18 AV18

AY24 AY20 AY18 AU18

BJ24 BG25

DMI_COMP

BH21

SUSACK#_R

SYS_PWROK_ R

EC_PWROK_R

APWROK_R

PM_DRAM_PWRGD

PCH_RSMRST#PCH_RSMRST#

SUSWARN#_R

PM_BATLOW#

PM_RI#

R359 10K_4R429 8.2K_4

R398 10K_4 R84 *10K_4 R62 10K_4 R346 *10K_4R352 *10K_4

201201119 stuff R346.

R396 200/F_4

20111107 R5180 un-stuff.

U26C

DMI0RXN DMI1RXN DMI2RXN DMI3RXN

DMI0RXP DMI1RXP DMI2RXP DMI3RXP

DMI0TXN DMI1TXN DMI2TXN DMI3TXN

DMI0TXP DMI1TXP DMI2TXP DMI3TXP

DMI_ZCOMP DMI_IRCOMP DMI2RBIAS

C12

SUSACK#

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPWRDNACK/GPIO 30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

Panther Point_R1P 0

+3V_S5

DMI

+3V

+3V_S5

System Power Management

DSW

+3V_S5

to PCH Pin12, XDP and EE debug

SYS_PWROK<3>

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6

FDI

FDI_RXP7

FDI_INT FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GP IO63

SLP_S4#

+3V_S5

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

SLP_LAN# / GPIO29

Need notice BIOS if DMI or FDI reverse.

BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9

BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

AW16 AV12 BC10 AV14 BB10

A18

E22

N14

D10

G10

G16

AP14

K14

SYS_PWROK

DPWROK_R

PCIE_WAKE#_ LAN

CLKRUN#

PCH_SUSCLK

SLP_A#

SLP_SUS#

SLP_LAN#

U24

TC7SH08FU

DSWVREN <8>

R94 0_4

R397 0_4

20111206 add R5193 un-stuff for normal s3 PCIE LAN wake up.

TP36

TP35

TP37

IMVP_PWRGD PU +3V PWROK_EC PD

+3V_S5

so AND gate output dont need PD again

C426

0.1u/10V_4R363 8.2K_4

2 1

PWROK_EC

3 5

R411 100K_4

R406 *0_4

FDI_TXN0 <2> FDI_TXN1 <2> FDI_TXN2 <2> FDI_TXN3 <2> FDI_TXN4 <2> FDI_TXN5 <2> FDI_TXN6 <2> FDI_TXN7 <2>

FDI_TXP0 <2> FDI_TXP1 <2> FDI_TXP2 <2> FDI_TXP3 <2> FDI_TXP4 <2> FDI_TXP5 <2> FDI_TXP6 <2> FDI_TXP7 <2>

20111102 FDI reverse

20111111 FDI change to normal

FDI_INT <2> FDI_FSYNC0 <2> FDI_FSYNC1 <2> FDI_LSYNC0 <2> FDI_LSYNC1 <2>

DPWROK need to be shorted to RSMRST# when Deep S4/S5 state is not support

DPWROK <24 >

PCIE_LAN_WAKE# <17>

CLKRUN# <1 9,24>

LPCPD# <1 9>

20111123 add for TPM LPCPD# pin.

SUSC# <24>

SUSB# <24>

SLP_SUS# <11,24>

PM_SYNC <3>

PWROK_EC <24 >

20120104 change DPWROK from PCH_Rsmrst# to EC control.

INT_LVDS_BLON<15>

INT_LVDS_DIGON<15 > INT_LVDS_BRIGHT<15>

DAC_IREF

R120 1K/F_4

1% or 5%

+3V_S5

C434 *0.1U/10V_4

U25

IMVP_PWRGD_R

include GFX_PWRGD to SYS_ PWROK for PCH check

*TC7SH08

3 5

R409 0_4

20111128 add 0ohm to passed IMVP_PERGD

CPT/PPT (LVDS,DDI)

U26D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

Panther Point_R1P 0

IMVP_PWRGD <3,33> GFX_PWRGD <24, 33>

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_CTRLCLK

SDVO_CTRLDATA

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

CRT

SDVO_STALLN SDVO_STALLP

SDVO_INTN SDVO_INTP

DDPB_AUXN DDPB_AUXP

DDPB_HPD

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_AUXN DDPC_AUXP

DDPC_HPD

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_AUXN DDPD_AUXP

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

AP43 AP45

AM42 AM40

AP39 AP40

P38 M39

AT49 AT47 AT40

AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49

P46 P42

AP47 AP49 AT38

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43 BH41

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

INT_HDMITX2N_C INT_HDMITX2P_C INT_HDMITX1N_C INT_HDMITX1P_C INT_HDMITX0N_C INT_HDMITX0P_C INT_HDMICLK-_C INT_HDMICLK+_C

DisplayPort C DisplayPort D

INT_HDMITX2N_C <16> INT_HDMITX2P_C <16> INT_HDMITX1N_C <16> INT_HDMITX1P_C <16> INT_HDMITX0N_C <16> INT_HDMITX0P_C <16> INT_HDMICLK-_C <16> INT_HDMICLK+_C <16>

Size Document Number Rev

Panther Point 1/6

Date: Sheet of

Monday, April 09, 201 2

Date: Sheet of

Monday, April 09, 201 2

Date: Sheet of

Monday, April 09, 201 2

HDMI_DDCCLK_SW <16> HDMI_DDCDATA_SW <1 6>

HDMI_HP <16 >

Quanta Computer Inc.

PROJECT :

Z09

PROJECT :

Z09

PROJECT :

Z09

7 40

INT. HDMI

RTC Circuitry(RTC)

20mils

R545 *SHORT_6

+3VPCU

R530 1K_4

D D

20MIL 20MIL

VCCRTC_2 VCCRTC_3 VCCRTC_4

BT1 RTC SOCKET

20MIL

20111117 change back RTC connect

20111118 change RTC connect to 2P. 20111121 change back RTC connector to socket.

HDA Bus(CLG)

PCH JTAG Debug (CLG)

C C

R428 51_4

PCH Dual SPI (CLG)

+3V_S5

B B

PCH_SPI_CS0# PCH_SPI_CLK PCH_SPI_SI PCH_SPI_SO

R520 3. 3K_4

+3V_PCH_ME

10/11 add

PCH_SPI_CS1# PCH_SPI_CLK

R486 33 _4

PCH_SPI_SI

R494 33 _4

PCH_SPI_SO

R525 33 _4

C508 *22p/5 0V_4

20111129 conta ct to EC thou gth series res istor.

PCH_SPI_CLK_EC<24>

PCH_SPI_SI_EC<24> PCH_SPI_SO_EC<24 >

+3V_PCH_ME

A A

SPI_CS0#_UR_ME<24>

+3V_RTC

R35 20K _4

D14

VCCRTC_1

20MIL

Q33

MMBT3904

PCH_AZ_CODEC_BITCLK<19>

PCH_AZ_CODEC_SYNC<19>

PCH_AZ_CODEC_RST#<19>

PCH_AZ_CODEC_SDOUT<19>

+3V_S5

R423 210/F_4

R422 100/F_4

R523 3.3K_4

SPI_CS0#_UR_ME

0mils

R48 20K _4

BAT54C

C38 1u/6.3V_4

1 3

R519 4.7 K_4

20120109 change footprint.

20111116 For EMI solution.

C430 22p/50V_4

R421

R97

210/F_4

XDP_TMS_VT PCH_XDP_TDO_VT PCH_XDP_TDO XDP_TCLK_VT

R419

R96

100/F_4

(Default for WIN8)

W25Q32BVSSIG / AKE391P0N00-- --->4MB W25Q16BVSSIG / AKE38FP0N01-- --->2MB

R492 *SHORT_6

10/11 add

U27

CE#

R490 33 _4 R489 33 _4 R522 33 _4

20111103 add pull up 10k to PSI CS#.

C520 *22p/50V_4

SCK

HOLD#

WP#

ROM-2M_ME

U28

CE#

SCK

HOLD#

WP#

ROM-4M_EC

R521 *0_ 4

R526 0_ 4

R620 47K_4

C31 1u/6.3V_4

C36 1u/6.3V_4

R390 33 _4 R347 33 _4 R51 33 _4 R376 33 _4

VDD

R491 3. 3K_4

VSS

VDD

R488 3. 3K_4

VSS

+3V_PCH_ME

*SHORT_ PAD1

SRTC_RST#

*SHORT_ PAD1

R518 4.7 K_4

ACZ_BITCLK_RACZ_BITCLK_ R ACZ_SYNC_CODEC ACZ_RST#_R ACZ_SDOUT_R

+3V_PCH_ME

RTC_RST#

68.1K/F_4

150K/F_4

C114

0.1u/10V_4

C580

0.1u/10V_4

PCH_SPI_CS0#

PCH_SPI_CS1#

R517

R529

PCH2(CLG)

+5V_S5

Add MOSFET to separate CODEC SYNC signal

+5V

PCH Strap Table

Pin Name

SPKR

GNT3# / GPIO55

INTVRMEN

GNT1# / GPIO51

GPIO19

HDA_SDO

DF_TVS

GPIO28

HDA_SYNC On-Die PLL VR Voltage Select RSMRST

GPIO15

DSWVREN

NV_ALE

C424 18p/5 0V_4

C425 18p/5 0V_4

20110530-modif y

R349 *SHORT_4

ACZ_SYNC_CODEC

CRB 1.0

R348 1M_4

20111128 Remove net TP_INT#, becaue change to pin E12.

Strap description

No reboot mode setting PWROK

Top-Block Swap Override

+3V_RTC

ZRH use 2N7002D

Q21 2N7002K

PCH_AZ_CODEC_SDIN0<19>

XDP_TCLK_VT<3,2 2> XDP_TMS_VT<3,2 2> PCH_XDP_TDO_VT<3>

+3V_PCH_ME

32.768KHZ

R68 1M_ 4

TP2 TP13

TP14

R524 *47 K_4

Sampled

PWROK

R408

RTC_X1

10M_4

RTC_X2 RTC_RST# SRTC_RST# SM_INTRUDER# PCH_INVRMEN

ACZ_BITCLK_R

ACZ_SYNC_R

SPKR

SPKR<1 9>

ACZ_RST#_R

ACZ_SDOUT_R

PCH_GPIO33 PCH_GPIO13

XDP_TCLK_VT XDP_TMS_VT PCH_XDP_TDO_VT

PCH_XDP_TDO

PCH_SPI_CLK PCH_SPI_CS0#

PCH_SPI_CS1#

PCH_SPI_SI PCH_SPI_SO

Configuration

0 = Default (weak pull-down 20K)

1 = Setting to No-Reboot mode 0 = "top-block swap" mode

1 = Default (weak pull-up 20K)

Integrated 1.05V VRM enable ALWAYS Should be always pull-up

Boot BIOS Selection 1 [bit-1]

Boot BIOS Selection 0 [bit-0]

Flash Descriptor Security

DMI/FDI Termination voltage

On-die PLL Voltage Regulator RSMRST#

Intel ME Crypto Transport Layer Security (TLS) cipher suite internal PD

DEEP S4/S5 well On Die DSW VR Enable

Intel Anti-Theft HDD protection

Only for Interposer

PWROK

0 = effect (default)(weak pull-down 20K)

RSMRST

1 = overridden 0 = Set to Vss (weak pull-down 20K)

PWROK

1 = Set to Vcc

0 = Disable

1 = Enable (weak pull-up 20K)

0 = Support by 1.8V (weak pull-down)

1 = Support by 1.5V

0 = Disable (Default)

RSMRST

1 = Enable

High = Enable (Default)

DSW

Low = Disable

PWROK 0 = Disable (Internal pull-down 20kohm)

CPT/PPT (HDA,JTAG,SATA)

U26A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

TP9

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST# / GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

SPI_CLK

Y14

SPI_CS0#

SPI_CS1#

SPI_MOSI

SPI_MISO

Panther Point_R1P 0

GNT0#GNT1#

Boot Location

SPI

LPC

RTCIHDA

JTAG

SPI

+3V_RTC

+3V +3V

+3V_RTC

+3V_S5

+3V

+3V +

ME_WR#<24>

+1.8V

3V_S5

+3V

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

LPC

FWH4 / LFRAME#

LDRQ1# / GPIO23

SATA 6G

SATA

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATA0GP / GPIO21 SATA1GP / GPIO19

R482 2.2K_4 R483 1K_4

R439 *1K _4

+3V_S5

R60 33 0K_4

C38 A38 B37 C37

D36 E36

PCH_DRQ#0

LDRQ0#

SERIRQ

SATA0RXN SATA0RXP SATA0TXN SATA0TXP

SATA1RXN SATA1RXP SATA1TXN SATA1TXP

SATA2RXN SATA2RXP SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATA5RXN SATA5RXP SATA5TXN SATA5TXP

SATALED#

R460 *1K _4

R418 *1K _4

R391 33 0K_4

R412 *1K _4 R448 *1K _4

R350 1K_4

R413 1K _4

R479 *1K_4

K36 V5

AM3 AM1 AP7 AP5

AM10 AM8 AP11 AP10

AD7 AD5 AH5 AH4

AB8 AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11 Y10

AB12 AB13

AH1

P3 V14 P1

R377 *SHORT_4

+1.8V

TP5

PCH_DRQ#1

TP11

R135 8. 2K_4

UM77 SATA port 1,3 disabl e.

SATA_COMP

R128 37 .4/F_4

SATA3_COMP

R131 49 .9/F_4

SATA3_RBIAS

R464 75 0/F_4

20111108 PU 10k to +3V, becaue no sata LED.20111110 change power plant to +3V_PCH_ME

SATA_ACT#

R443 10K _4

PCH_ODD_EN BBS_BIT0

20111127 add R444 PU 10K to +3V for PCH_ODD_EN not use.

SPKR

PCI_GNT3# <9>

PCH_INVRMEN

BBS_BIT1 <9>

BBS_BIT0

ACZ_SDOUT_R

DF_TVS <10> H_SNB_IVB# <3>

PLL_ODVR_EN <10 >

ACZ_SYNC_R

PCH_GPIO15 <10>

R59 *33 0K_4

DSWVREN <7>

NV_ALE <9>

LPC_LAD0 <19,20,24> LPC_LAD1 <19,20,24> LPC_LAD2 <19,20,24> LPC_LAD3 <19,20,24>

LPC_LFRAME# <19,20, 24>

SERIRQ <19,24>

TP15

TP26

+3V

R459 10K _4

CRB 1.0 uses 10kohm

+3V

SATA_RXN0 <21> SATA_RXP0 <21> SATA_TXN0 <21> SATA_TXP0 <21>

SATA_RXN1 <20> SATA_RXP1 <20> SATA_TXN1 <20> SATA_TXP1 <20>

DG recomm ended that A C couplin g capacitors sho uld be close to the co nnector (<100 m ils) for o ptimal si gnal qual ity.

SATA_RXN5_C <21> SATA_RXP5_C < 21> SATA_TXN5 <21> SATA_TXP5 <21>

PCH_ODD_EN <21>

+3V

SATA HDD

20110908 acer request HDD,MSATA need SATA3.

mSATA

SATA ODD

+1.05V_VTT

SATA0GP/GPIO21 SATA4GP/GPIO16 SATA5GP/GPIO49 If these pins are unused use 8.2k to 10k pull-up to +Vcc3_3 or 8.2k to 10k pull-do wn to ground

Used as GPIO only. at chklist 1.2

Default weak pull-up on GNT0/1# [Need external pull-down for LPC BIOS]

ME_WR default EC setting folating

for future CPU , Sandy Bridge NC DF_TVS needs t o be pulled up to VccDFTERM power rail through 2.2 kO hm ±5% - R8361 change to 0 or not??

Needs to be pu lled High for Huron River p latform. chklist 1.2

Quanta Computer Inc.

PROJECT :

Panther Point 2/6

Monday, April 09, 201 2

PROJECT :

Size Document Number Rev

Date: Sheet o f

Z09

8 40

CPT/PPT (PCI,USB,NVRAM)

U26E

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

TP17 TP30

TP20 TP29

TP18 TP21

TP16 TP19

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

DGPU_EDIDSEL# DGPU_SELECT# REQ#3

BOARD_ID2

MPC_PWR_CTRL# DGPU_PWR_EN DGPU_HOLD_RST# EXTTS_SNI_DRV1_PCH

TP12

PCI_PLTRST#

PCLK_TPM_R CLK_LPC_DEBUG_C

CLK_PCI_775_C

PLTRST#

R379 RAMID@10K_4 R71 *RAMID@10K_4

DGPU_PWR_EN

PCI_PME#

R351 100K_4

R370 10K_4

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

B21

TP21

M20

TP22

AY16

TP23

BG46

TP24

BE28

TP25

BC30

TP26

BE32

TP27

BJ32

TP28

BC28

TP29

BE30

TP30

BF32

TP31

BG32

TP32

AV26

TP33

BB26

TP34

AU28

TP35

AY30

TP36

AU26

TP37

AY26

TP38

AV28

TP39

AW30

TP40

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1# / GPIO50

C44

REQ2# / GPIO52

E40

REQ3# / GPIO54

D47

GNT1# / GPIO51

E42

GNT2# / GPIO53

F46

GNT3# / GPIO55

G42

PIRQE# / GPIO2

G40

PIRQF# / GPIO3

C42

PIRQG# / GPIO4

D44

PIRQH# / GPIO5

K10

PME#

PLTRST#

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

Panther Point_R1P0

PLTRST# <17,19,20,24,25>

+3V_S5

+3V

USB3.0

USB30_RX1N USB30_RX2N USB30_RX3N USB30_RX4N USB30_RX1P USB30_RX2P USB30_RX3P USB30_RX4P USB30_TX1N USB30_TX2N USB30_TX3N

USB30_TX4N USB30_TX1P USB30_TX2P USB30_TX3P USB30_TX4P

Hynix

Elpida

+3V +3V +3V

+3V +3V +3V +3V

RSVD

PCI

+3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5 +3V_S5

USB

OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43 OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14

RAM_IDnRAM

0x000

0x001

D D

TX AC cap place at connector side, AC cap to connector < 400mils

C C

20111108 Add PCLK_TPM for TPM.

PCLK_TPM<19> CLK_LPC_DEBUG<20>

B B

PLTRST#(CLG)

PCI_PLTRST#

DDRIII Memory down strap

A A

USB30_RX1-<23> USB30_RX2-<23>

USB30_RX1+<23> USB30_RX2+<23>

USB30_TX1-<23> USB30_TX2-<23>

USB30_TX1+<23> USB30_TX2+<23>

BBS_BIT1<8>

BOARD_ID2<10>

PCI_GNT3#<8>

DGPU_PWR_EN<39>

DGPU_HOLD_RST#<25>

PCI_PLTRST#<3,24>

R104 22_4

CLK_PCI_FB CLK_PCI_FB_C

R431 22_4 R115 22_4

CLK_PCI_EC<24>

R99 22_4

20111128 change power plant to +3V.

+3V

C417

0.1u/10V_4

U23

3 5

TC7SH08FU

R366 *0_4

RAM_ID0

R394 *RAMID@5K/F_4

RAM_ID1

R393 RAMID@15K/F_4 R378 *RAMID@10K_4

RAM_ID2

R70 RAMID@15K/F_4

RAM_ID3

R395 RAMID@15K/F_4

R386 *100K_4

AY7

RSVD1

AV7

RSVD2

AU3

RSVD3

BG4

RSVD4

AT10

RSVD5

BC8

RSVD6

AU2

RSVD7

AT4

RSVD8

AT3

RSVD9

AT1

RSVD10

AY3

RSVD11

AT5

RSVD12

AV3

RSVD13

AV1

RSVD14

BB1

RSVD15

BA3

RSVD16

BB5

RSVD17

BB3

RSVD18

BB7

RSVD19

BE8

RSVD20

BD4

RSVD21

BF6

RSVD22

AV5

RSVD23

AV10

RSVD24

AT8

RSVD25

AY5

RSVD26

BA2

RSVD27

AT12

RSVD28

BF3

RSVD29

C24

USBP0N

A24

USBP0P

C25

USBP1N

B25

USBP1P

C26

USBP2N

A26

USBP2P

K28

USBP3N

H28

USBP3P

E28

USBP4N

D28

USBP4P

C28

USBP5N

A28

USBP5P

C29

USBP6N

B29

USBP6P

N28

USBP7N

M28

USBP7P

L30

USBP8N

K30

USBP8P

G30

USBP9N

E30

USBP9P

C30

USBP10N

A30

USBP10P

L32

USBP11N

K32

USBP11P

G32

USBP12N

E32

USBP12P

C32

USBP13N

A32

USBP13P

C33

USB_BIAS

USBRBIAS#

B33

USBRBIAS

A14

USB_OC0#

K20

USB_OC1#

B17

USB_OC2#

C16

RAM_ID0

L16

USB_OC4#

A16

RAM_ID1

D14

RAM_ID2

C14

RAM_ID3

PCI/USBOC# Pull-up(CLG)

MPC Switch Control

MPC_PWR_CTRL#

Optimize SKU

+3V

R93 EV@10K_4 R100 IV@10K_4

+3V

R108 EV@10K_4 R114 IV@10K_4

NV_ALE <8>

port9 can be used on debug mode

USBP0- <23> USBP0+ <23> USBP1- <23>

USBP1+ <23>

TP7 TP1

USB port6/7 may not be available on all PCH sku (HM55 support 12port only)

USBP8- <15>

USBP8+ <15>

USBP9- <23>

USBP9+ <23>

USBP10- <20>

USBP10+ <20>

TP4 TP6

UM77 USB port 6,7,12,13 disable.

R86 22.6/F_4

USB_OC0# <23>

USB_OC0#

R55 10K_4

USB_OC1#

R82 10K_4

USB_OC2#

R392 10K_4

USB_OC4#

Low = MPC ON High = MPC OFF (Default)

R49 *1K_4

SKU_ID1

SKU_ID0 <10>

MB USB left side MB usb left side

XHCI for USBP0-3

EHCI1

Camera MB USB right side BT+WL

+3V_S5

EHCI2

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

+3V

MPC_PWR_CTRL# EXTTS_SNI_DRV1_PCH REQ#3

dGPU_PW_CTRL#

SKU_ID1

(GPIO68)

(GPIO64)

CTL : dGPU_VRON

UMA Only

GPU Only

Switchable (Mux)

Optimize (Muxless)

dGPU_PW_CTRL# 0 = GPU power is control by PCH GPIO (Discrete, SG or Optimize) 1 = GPU power is control by H/W (pure Discrete SKU)

0 or 1

Cardreader

Wireless

R44

9 8 7 4

10KX8

SKU_ID0 (GPIO16)

LAN

R74 8.2K_4 R75 8.2K_4 R373 8.2K_4

1 2 3

VGA H/W Signal

UMA+GPU

PCIE port 1 for commeral model S3 can't weak up.

PCIE_RX2-<19> PCIE_RX2+<19> PCIE_TX2-<19> PCIE_TX2+<19>

PCIE_RX3-<17> PCIE_RX3+<17> PCIE_TX3-<17> PCIE_TX3+<17>

PCIE_RX8-<20> PCIE_RX8+<20> PCIE_TX8-<20> PCIE_TX8+<20>

Cardreader

20110908 WLAN support S3 wake up function.

Wireless

LAN

CLK_PCIE_XDPN<3> CLK_PCIE_XDPP<3>

+3V

DGPU_HOLD_RST#

DGPU_EDIDSEL#

dGPU_SELECT#

Setup Menu

UMA boot

UMA

Hidden

GPU boot

GPU

Hidden

UMA boot

dGPU/SG

UMA boot

UMA

UMA/SG

PCIE_TX2-_C

C108 0.1U/10V_4

PCIE_TX2+_C

C105 0.1U/10V_4

C103 0.1u/10V_4 C100 0.1u/10V_4

UM77 4~7 PCIE port disable

C106 0.1u/10V_4 C109 0.1u/10V_4

CLK_PCIE_MMC#<19> CLK_PCIE_MMC<19>

PCIE_CLKREQ0#

PCIE_CLKREQ0#<19>

TP61

PCIE_CLKREQ1#

PCIE_CLKREQ2#

PCIE_CLKREQ4#

CLK_PCIE_WLAN#<20> CLK_PCIE_WLAN<20>

PCIE_CLKREQ5#

PCIE_CLKREQ5#<20>

CLK_PCIE_LOM#<17> CLK_PCIE_LOM<17>

CLK_PCIE_LAN_REQ#<17>

CLK_PCIE_REQ6#

CLK_PCIE_REQ7#

CLK_REQ/Strap Pin(CLG)

+3V_S5

R79 10K_4R40 8.2K_4 R364 10K_4R88 10K_4 R430 10K_4 R399 10K_4 R402 10K_4 R365 10K_4 R83 10K_4

+3V

R424 10K_4 R124 10K_4

+3V_S5

R102 10K_4

20111021 remove pull/down resistor

CLK_BUF_BCLKN CLK_BUF_BCLKP

CLK_BUF_PCIE_3GPLLN CLK_BUF_PCIE_3GPLLP CLK_BUF_DREFCLKN CLK_BUF_DREFCLKP CLK_BUF_DREFSSCLKN CLK_BUF_DREFSSCLKP CLK_PCH_14M

CLOCK TERMINATION for FCIM

CPT/PPT (PCI-E,SMBUS,CLK)

U26B

BG34

PERN1

PCIE_TXN3_C PCIE_TXP3_C

PCIE_TXN8_C PCIE_TXP8_C

PCIE_CLKREQ3#

CLK_PCIE_LAN_REQ#

TP34

TP42

PCIE_CLKREQ4# PCIE_CLKREQ5# PCIE_CLKREQ0# PCIE_CLKREQ3# CLK_PCIE_LAN_REQ# CLK_PCIE_REQ6# CLK_PCIE_REQ7#

PCIE_CLKREQ1# PCIE_CLKREQ2#

PCIE_CLKREQ_PEG#_R

R504 10K_4 R503 10K_4

R164 10K_4R380 *RAMID@10K_4 R163 10K_4 R89 10K_4 R90 10K_4 R480 10K_4 R478 10K_4 R111 10K_4

BJ34 AV32 AU32

BE34 BF34 BB32 AY32

BG36 BJ36 AV34 AU34

BF36 BE36 AY34 BB34

BG37 BH37 AY36 BB36

BJ38 BG38 AU36 AV36

BG40 BJ40 AY40 BB40

BE38 BC38

AW38

AY38

Y40 Y39

AB49 AB47

AA48 AA47

V10

Y37 Y36

Y43 Y45

L12

V45 V46

L14

AB42 AB40

V40 V42

T13

V38 V37

K12

AK14 AK13

Panther Point_R1P0

PERP1 PETN1 PETP1

PERN2 PERP2 PETN2 PETP2

PERN3 PERP3 PETN3 PETP3

PERN4 PERP4 PETN4 PETP4

PERN5 PERP5 PETN5 PETP5

PERN6 PERP6 PETN6 PETP6

PERN7 PERP7 PETN7 PETP7

PERN8 PERP8 PETN8 PETP8

CLKOUT_PCIE0N CLKOUT_PCIE0P

PCIECLKRQ0# / GPIO73

CLKOUT_PCIE1N CLKOUT_PCIE1P

PCIECLKRQ1# / GPIO18

CLKOUT_PCIE2N CLKOUT_PCIE2P

PCIECLKRQ2# / GPIO20

CLKOUT_PCIE3N CLKOUT_PCIE3P

PCIECLKRQ3# / GPIO25

CLKOUT_PCIE4N CLKOUT_PCIE4P

PCIECLKRQ4# / GPIO26

CLKOUT_PCIE5N CLKOUT_PCIE5P

PCIECLKRQ5# / GPIO44

CLKOUT_PEG_B_N CLKOUT_PEG_B_P

PEG_B_CLKRQ# / GPIO56

CLKOUT_PCIE6N CLKOUT_PCIE6P

PCIECLKRQ6# / GPIO45 CLKOUT_PCIE7N

CLKOUT_PCIE7P PCIECLKRQ7# / GPIO46 CLKOUT_ITPXDP_N

CLKOUT_ITPXDP_P

+3V_S5

SMBUSController

+3V_S5

SML1ALERT# / PCHHOT# / GPIO74

PCI-E*

+3V_S5

CLOCKS

+3V

+3V_S5

SMBus(EC)

+3V_S5

2ND_MBCLK<24>

2ND_MBDATA<24>

+3V_S5

if net DRAMRST_CNTRL_PCH change to PCH control need stuff R358.

R72 10K_4 R343 2.2K_4 R340 2.2K_4 R361 2.2K_4 R360 2.2K_4 R357 10K_4

+3V_S5 +3V_S5

Link

PEG_A_CLKRQ# / GPIO47

+3V_S5

+3V +3V +3V +3V

FLEX CLOCKS

621

SMBALERT# SMB_PCH_CLK SMB_PCH_DAT SMB_ME0_CLK SMB_ME0_DAT SML1ALERT#_R

SMBALERT# / GPIO11

SMBCLK

SMBDATA

SML0ALERT# / GPIO60

SML0CLK

SML0DATA

SML1CLK / GPIO58

SML1DATA / GPIO75

CL_CLK1

CL_DATA1

CL_RST1#

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N CLKOUT_DP_P

CLKIN_DMI_N

CLKIN_DMI_P

CLKIN_GND1_N CLKIN_GND1_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_SATA_N CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64 CLKOUTFLEX1 / GPIO65 CLKOUTFLEX2 / GPIO66 CLKOUTFLEX3 / GPIO67

R338

2.2K_4

Q19

2N7002DW

20111117 change footprint to dual type.

20111122 add for Touch pad interrupt pin from GPIO13 to GPIO11.

E12

SMBALERT#

H14 C9

A12 C8 G12

C13 E14 M16

T11

P10

M10

PCIE_CLKREQ_PEG#_R

AB37 AB38

AV22 AU22

AM12 AM13

BF18

CLK_BUF_PCIE_3GPLLN

BE18

CLK_BUF_PCIE_3GPLLP

BJ30

CLK_BUF_BCLKN

BG30

CLK_BUF_BCLKP

G24

CLK_BUF_DREFCLKN

E24

CLK_BUF_DREFCLKP

AK7

CLK_BUF_DREFSSCLKN

AK5

CLK_BUF_DREFSSCLKP

K45

CLK_PCH_14M

H45

CLK_PCI_FB

V47

XTAL25_IN

V49

XTAL25_OUT

Y47

XCLK_RCOMP

K43

CLK_FLEX0

F47

CLK_FLEX1

H47 K49

R339

2.2K_4

SMB_ME1_CLK

SMB_ME1_DAT

SMBALERT# <19>

SMB_PCH_CLK

SMB_PCH_CLK <20>

SMB_PCH_DAT

SMB_PCH_DAT <20>

DRAMRST_CNTRL_PCH SMB_ME0_CLK SMB_ME0_DAT

SML1ALERT#_R SMB_ME1_CLK SMB_ME1_DAT

CL_CLK1

CL_DATA1

CL_RST1#

DRAMRST_CNTRL_PCH <4>

20110907 del net SML1ALERT#

TP24

CL_CLK1 <20>

CL_DATA1 <20>

CL_RST1# <20>

R103 EV@0_4

CLK_PCIE_VGAN <25> CLK_PCIE_VGAP <25>

CLK_CPU_BCLKN <3> CLK_CPU_BCLKP <3>

CLK_DPLL_SSCLKN <3> CLK_DPLL_SSCLKP <3>

R132 90.9/F_4

+1.05V_VTT

R85 *SHORT_4

TP59

R457 *SHORT_4

SMBus(PCH)

+3V

S5 S0

SMB_PCH_DAT

621

SMB_PCH_CLK

2N7002DW

Size Document Number Rev

Panther Point 3/6

Date: Sheet of

Monday, April 09, 2012

Date: Sheet of

Monday, April 09, 2012

Date: Sheet of

Monday, April 09, 2012

For LAN

For EC

PEG_CLKREQ# <25>

XTAL25_IN

Y2 25MHz_XTAL

2 4

1 3

XTAL25_OUT

C87 10p/50V_4 R133

1M_4 C74 10p/50V_4

20120201 Change CAP from 27P to 10P.

SKU_ID1

BOARD_ID4 <10,19>

ODD_PRSNT# <21>

R316

R317

4.7K_4

Q20

CLK_SDATA <13,14,19>

CLK_SCLK <13,14,19>

Quanta Computer Inc.

PROJECT :

Z09

PROJECT :

Z09

PROJECT :

Z09

9 40

S_GPIO

R112 100_4

SIO_EXT_SMI#<2 4>

D D

C C

20110907 del R5217 and net SML1ALERT#

B B

SATA2GP : strap for reserved at chklist 1.2 SATA3GP : strap for reserved at chklist 1.2 NOTE: The internal pull-down is disabled after PLTRST# deasserts. NOTE: This signal should not be pulled high when strap is sampled.

A A

2011/09/01 add select resistor

LCD_SELECT

LVDS = Pull HIGH eDP = Pull LOW

SIO_EXT_SCI#<24>

PCH_GPIO15<8>

WK_GPIO27<2 4>

PLL_ODVR_EN<8>

DGPU_VRON<38,39>

TP23

R371 *LVDS@1.5K/F_ 4

SKU_ID0<9>

DGPU_PW ROK<25>

R387 EDP @1K_4

SIO_EXT_SMI# BOARD_ID1 SIO_EXT_SCI# ICC_EN# PLL_ODVR_EN

TP25

SMIB

DGPU_PW ROK G_SENSOR_ID PCH_GPIO24 WK_GPIO27 PLL_ODVR_EN STP_PCI#

DGPU_VRON DMI_OVRVLTG FDI_OVRVLTG MFG_MODE BOARD_ID0 TEST_SET_UP CRIT_TEMP_RE P# SV_DET

+3V

FDI TERMINATION VOLTAGE OVERRIDE

CPT/PPT (GPIO,VSS_NCTF,RSVD)

U26F

R436 100K_4

BMBUSY# / GPIO0

A42

TACH1 / GPIO1

H36

TACH2 / GPIO6

E38

TACH3 / GPIO7

C10

GPIO8

LAN_PHY_PWR_CTRL / GPIO12

GPIO15

SATA4GP / GPIO16

D40

TACH0 / GPIO17

SCLOCK / GPIO22

GPIO24 / MEM_LED

E16

GPIO27

GPIO28

STP_PCI# / GPIO34

GPIO35

SATA2GP / GPIO36

SATA3GP / GPIO37

SLOAD / GPIO38

SDATAOUT0 / GPIO39

V13

SDATAOUT1 / GPIO48

SATA5GP / GPIO49

GPIO57

VSS_NCTF_1

A44

VSS_NCTF_2

A45

VSS_NCTF_3

A46

VSS_NCTF_4

VSS_NCTF_5

VSS_NCTF_6

VSS_NCTF_7

B47

VSS_NCTF_8

BD1

VSS_NCTF_9

BD49

VSS_NCTF_10

BE1

VSS_NCTF_11

BE49

VSS_NCTF_12

BF1

VSS_NCTF_13

BF49

VSS_NCTF_14

Panther Point_R1P0

FDI_OVRVLTG G_SENSOR_ID

+3V +3V +3V +3V

+3V_S5

+3V

GPIO

+3V_S5

DSW +3V_S5

+3V

+3V +3V

+3V

+3V_S5

R437 * 1K_4

LOW - Tx, Rx terminated to same voltage

+3V

TACH4 / GPIO68

+3V

TACH5 / GPIO69

+3V

TACH6 / GPIO70

+3V

TACH7 / GPIO71

+3V_S5

A20GATE

PECI

RCIN#

PROCPWRGD

THRMTRIP#

INIT3_3V#

DF_TVS

CPU/MISC

TS_VSS1 TS_VSS2 TS_VSS3 TS_VSS4

NC_1

VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23

NCTF

VSS_NCTF_24 VSS_NCTF_25 VSS_NCTF_26 VSS_NCTF_27 VSS_NCTF_28 VSS_NCTF_29 VSS_NCTF_30 VSS_NCTF_31 VSS_NCTF_32

+3V +3V

G_SENSOR_ID

C40

DGPU_PW _CTRL#

B41

LCD_SELECT

C41

BOARD_ID3

A40

R407 1.5K/F_4

SIO_A20GATE

AU16

EC_PECI_R

SIO_RCIN#

AY11 AY10

PCH_THR MTRIP#

T14 AY1

AH8 AK11 AH10 AK10

P37

BG2 BG48 BH3 BH47 BJ4 BJ44 BJ45 BJ46 BJ5 BJ6 C2 C48 D1 D49 E1 E49 F1 F49

R117 10K_4

R119 *1K_4

High = Disable (Default) Low = Enable

+3V

R162 *0_4

R156 390_4

TP75

SIO_A20GATE <24>

EC_PECI <3,24>

SIO_RCIN# <24> H_PWRG OOD <3> PM_THRMTR IP# <3>

DF_TVS <8>

SMIB

High = Strong (Default)

TEST_SET_UP

SGPIO

S_GPIO

MFG-TEST

MFG_MODE

GPIO Pull-up/Pull-down(CLG)

PCH_GPIO24

SIO_EXT_SMI# SIO_EXT_SCI#

STP_PCI# SIO_A20GATE SIO_RCIN# CRIT_TEMP_RE P#

20120201 reserve GPIO27 PU +3VPCU

WK_GPIO27

20111017 un-stuff R5126 for DSW

DGPU_PW ROK

GPIO27 : If not used then use 8.2-kΩ to 10-kΩ pull-down to GND.

Low = Tx, Rx terminated to same voltage (DC Coupling Mode) (DEFAULT)

R148 *10K_4

high VDDR=+1.35V_SUS for DDR3L Low VDDR =+1.5V_SUS(default)

R362 *10K_4

assign to VID for VDDR control

R106 10K_4 R389 10K_4 R385 10K_4 R384 *10K_4 R425 *10K_4

BOARD_ID2<9> BOARD_ID4<9,19>

high

low

DGPU_PW _CTRL#

Quanta Computer Inc.

PROJECT :

Panther Point 4/6

USB3.0 IC CTL

LOW = USB3.0 IC

R401 10K_4

SV_SET_UP

R147 10K_4

R149 *1K_4

R113 1K _4 R116 * 1K_4

R445 10K_4

R444 *1K_4

DMI TERMINATION VOLTAGE OVERRIDE

+3V_S5

+3V

Board_ID4 Hight=Symatic, LOW=ELAN.

+3V

R372 IV@1K_4

+3V

Size D ocument Numb er Rev

Monday, April 09, 2 012

Date: Sheet of

Monday, April 09, 2 012

Date: Sheet of

Monday, April 09, 2 012

Date: Sheet

R73 *10K_4 R440 10K_4

R39 10K_4 R50 10K_4

R420 *10K_4 R105 10K_4 R98 10K_4 R458 10K_4

R616 10K_4 R101 *10K_4

R87 *10K_4

DMI_OVRVLTG

R146 *200K/F _4

SV_DET

R400 100K_4

BOARD_ID0

R107 *10K_4

BOARD_ID1

R374 *10K_4

BOARD_ID2

R369 *10K_4

BOARD_ID3

R368 10K_4

BOARD_ID4

R427 10K_4

GPU power is control by H/W (pure Discrete SKU)

GPU power is control by PCH GPIO (Discrete, SG or Optimize)

R388 EV@100K_4

Z09

10 40

+3V_S5

+3VPCU

+3V

+1.05V_VTT

L6 *1uH/25mA_6

+1.05V_VTT

R170 *SHORT_6 R171 *0_6

20111021 remove vcc core power sense net

VccCORE =1.3 A(60mils)

C82

C92

C81

1u/6.3V_4

+1.05V_VTT

20111117 remove 0ohm resistor.

C119 *10u/6.3V_6

VccIO =2.925 A(140mils)

C98

C91

C99

1u/6.3V_4

C94

C101

1u/6.3V_4

10u/6.3V_6

+3V_VCC_EXP+3V

R167 *SHORT_8

C121

0.1u/10V_4

+VCCAFDI_VRM

R506 *0_8

+1.05V_VTT

R158 *SHORT_8

+1.1V_VCC_DMI

+1.1V VCC_DMI witdth >= 20m ils.

+VCCAFDI_VRM

VCCVRM: 1.8V ( Destop) 02/20 del for Pre-E S1

1.5V ( Mobile)

C88

4.7u/6.3V_6

+VCCAFDI_VRM

+1.05V_VCCAPLL_FDI

+1.05V_VCCDPLL_FDI

CPT/PPT (POWER)

U26G

AA23

VCCCORE[1]

AC23

VCCCORE[2]

AD21

VCCCORE[3]

AD23

VCCCORE[4]

AF21

VCCCORE[5]

AF23

VCCCORE[6]

AG21

VCCCORE[7]

AG23

VCCCORE[8]

AG24

VCCCORE[9]

AG26

VCCCORE[10]

AG27

VCCCORE[11]

AG29

VCCCORE[12]

AJ23

VCCCORE[13]

AJ26

VCCCORE[14]

AJ27

VCCCORE[15]

AJ29

VCCCORE[16]

AJ31

VCCCORE[17]

AN19

VCCIO[28]

BJ22

VCCAPLLEXP

AN16

VCCIO[15]

AN17

VCCIO[16]

AN21

VCCIO[17]

AN26

VCCIO[18]

AN27

VCCIO[19]

AP21

VCCIO[20]

AP23

VCCIO[21]

AP24

VCCIO[22]

AP26

VCCIO[23]

AT24

VCCIO[24]

AN33

VCCIO[25]

AN34

VCCIO[26]

BH29

VCC3_3[3]

AP16

VCCVRM[2]

BG6

VccAFDIPLL

AP17

VCCIO[27]

AU20

VCCDMI[2]

Panther Point_R1P0

PCH5(CLG)

20111117 remove 0ohm resistor.

D D

R5285 near PCH ball for VCCP GND sense

+1.05V_VTT +1.05V _VCCAPLL_EXP

20111117 remove 0ohm resistor.

C C

VccDMI needs to be powered by the same 1.05 V voltage source as the CPU VCCIO, and the trace needs to be at least 20 mils width with full VSS/ VCC reference plane.

B B

+1.5V

+1.05V_VTT

A A

POWER

VCC CORE

VCCIO

FDI

U48

VCCADAC

U47

VSSADAC

CRTLVDS

AK36

VCCALVDS

AK37

VSSALVDS

AM37

VCCTX_LVDS[1]

AM38

VCCTX_LVDS[2]

AP36

VCCTX_LVDS[3]

AP37

VCCTX_LVDS[4]

V33

VCC3_3[6]

V34

VCC3_3[7]

AT16

VCCVRM[3]

AT20

VCCDMI[1]

DMI

AB36

VCCCLKDMI

AG16

VCCDFTERM[1]

AG17

VCCDFTERM[2]

AJ16

VCCDFTERM[3]

AJ17

VCCDFTERM[4]

DFT / SPI HVCMOS

VCCSPI

20120105 change power plant to +3V for power saving.

+3V_VCCME_SPI

Reserve +3V_S5 to VCCSPI fo r EC 795 co-la yout

+3V

R118 *0_6 R126 1/F_4

+VCCA_DAC_1_2

VccADAC =1mA(8mils)

C61

C47

0.01u/25V_4

10u/6.3V_6

When Dis sku and eDP , LVDS power can short to GND

20111101 remove vccalcd and vcctx_lds power, when LVDS disable.

R125 *SHORT_6 C66

0.1u/10V_4

+VCCAFDI_VRM

C77

C78

*10u/6.3V_6

1u/6.3V_4

R159 *SHORT_8

C93

0.1u/10V_4

+3V_VCCME_SPI

C67 1u/6.3V_4

+3V

R634 *0_6 R121 0_6

L3 10u H/100mA_8

L2 180ohm/5A

C55

C43

0.1u/10V_4

10u/6.3V_6

+3V+3V_VCC_GIO

VCCDMI = 42mA( 10mils)

+1.1V_VCC_DMI

C104 1u/6.3V_4

VCCCLKDMI = 20 mA(8mils)

+VCC_DMI_CCI +1.05V _VTT+1.1V_VCC_DMI_CCI

L4 *10uH/100mA_8

+1.8V+VCCP_NAND

VCCPNAND = 190 mA(15mils)

R144 *1/F_4 R139 *SHORT_4

VCCSPI = 20mA( 8mils)

+3V_S5

20120216 remove R172 for power plant chnge to +1.05V_VTT.

+3V_SUS_CLKF33

C57

C68

1u/10V_4

4.7u/6.3V_6

R169 *SHORT_4

+1.1V VCC_DMI witdth >= 20m ils.

+3V

20120104 change power plant from +3V_S5 to +3VPCU.

+1.05V_VTT

L7 *10uH/100mA_8

VCCME(+1.05V) = ??A(??mils)

+1.05V_VTT

20120216 remove R168 for power plant chnge to +1.05V_VTT.

+1.05V_VTT

VCCRTC<1mA(8mi ls)

+1.05V_VTT

R134 *SHORT_6

R138 *SHORT_6

R143 *SHORT_6

R127 *0_6

R173 *SHORT_4

+3V_RTC

L5 10uH/100mA_8

L26 10uH/100mA_8

+3VPCU

+VCCAPLL_CPY_PCH

+1.05V_VTT

R449 *SHORT_4

C86 1u/6.3V_4

C85 1u/6.3V_4

C90 1u/6.3V_4

C63 *1u/6.3V_4

1mA(8mils)

C111

4.7u/6.3V_6

C40 1u/6.3V_4

R136 *0_8

+1.05V_VTT

VCCDSW3_3= 3mA

C52

0.1u/10V_4

R141 *SHORT_6

+1.05V_VTT

C118 *10u/6.3V_6

VccASW =1.01 A(60mils)

C79

C84

1u/6.3V_4

C69 10u/6.3V_6

C51 0.1u/10V_4

65mA(10mils) 8mA(8mils)

VCCDIFFCLKN= 5 5mA(10mils) VCCSSC= 95mA(1 0mils)

C58 0.1u/10V_4

C120

0.1u/10V_4

C37

0.1u/10V_4

C529 220u/2.5V_3528

C512 220u/2.5V_3528

C80 1u/6.3V_4

C70 10u/6.3V_6

+VCCAFDI_VRM

C116

0.1u/10V_4

C39

0.1u/10V_4

+1.05V_VCCA_A_DPL

C115 1u/6.3V_4

+1.05V_VCCA_B_DPL

C112 1u/6.3V_4

C65 *0.1u/10V_4

C97 *1u/6.3V_4

+VCCRTCEXT

+VCCAFDI_VRM

+1.05V_VCCA_A_DPL +1.05V_VCCA_B_DPL

+VCCDIFFCLK +VCCDIFFCLKN

+V1.05V_SSCVCC

+VCCSST

+V1.05M_VCCSUS

+VTT_VCCPCPU

CPT/PPT (POWER)

U26J

AD49

+VCCACLK

T16

+VCCPDSW

V12

PCH_VCCDSW

T38

+3V_SUS_CLKF33

BH23 AL29

+VCCDPLL_CPY

AL24

+VCCSUS1

AA19 AA21 AA24 AA26 AA27 AA29 AA31 AC26 AC27 AC29 AC31 AD29 AD31

W21 W23 W24 W26 W29 W31 W33

N16

Y49

BD47 BF47

AF17 AF33 AF34 AG34

AG33

V16

T17 V19

BJ8

A22

Panther Point_R1P0

+5V_S5

POWER

VCCACLK

VCCDSW3_3

DCPSUSBYP

VCC3_3[5]

VCCAPLLDMI2 VCCIO[14]

DCPSUS[3]

VCCASW[1] VCCASW[2] VCCASW[3] VCCASW[4] VCCASW[5] VCCASW[6] VCCASW[7] VCCASW[8] VCCASW[9] VCCASW[10] VCCASW[11] VCCASW[12] VCCASW[13] VCCASW[14]

Clock and Miscellaneous

VCCASW[15] VCCASW[16] VCCASW[17] VCCASW[18] VCCASW[19] VCCASW[20]

DCPRTC

VCCVRM[4]

VCCADPLLA VCCADPLLB

VCCIO[7] VCCDIFFCLKN[1] VCCDIFFCLKN[2] VCCDIFFCLKN[3]

VCCSSC

DCPSST

DCPSUS[1] DCPSUS[2]

V_PROC_IO

CPURTC

VCCRTC

C411

*0.33u/10V_6

SLP_SUS#<7,24>

20111018 ADD DSW Cricuit 20111030 modify cuirucit.

PCI/GPIO/LPCMISC

SATA USB

HDA

N26

VCCIO[29]

P26

VCCIO[30]

P28

VCCIO[31]

T27

VCCIO[32]

T29

VCCIO[33]

T23

+3V_VCCPUSB

VCCSUS3_3[7]

T24

VCCSUS3_3[8]

V23

VCCSUS3_3[9]

V24

VCCSUS3_3[10]

P24

+3V_VCCAUBG

VCCSUS3_3[6]

T26

+VCCAUPLL

VCCIO[34]

M26

+5V_PCH_VCC5REFSUS

V5REF_SUS

AN23

+VCCA_USBSUS

DCPSUS[4]

AN24

+3V_VCCPSUS

VCCSUS3_3[1]

P34

+5V_PCH_VCC5REF

V5REF

N20

VCCSUS3_3[2]

N22

VCCSUS3_3[3]

P20

+3V_VCCPSUS

VCCSUS3_3[4]

P22

VCCSUS3_3[5]

AA16

VCC3_3[1]

W16

+3V_VCCPCORE

VCC3_3[8]

T34

+3V

C56

0.1u/10V_4

AJ2

AF13

AH13 AH14

AF14 AK1

+V1.1LAN_VCCAPLL

VCCVRM= 114mA( 15mils)

AF11

+VCCAFDI_VRM

AC16 AC17

20111117 remove 0ohm resistor.

C76

AD17

1u/6.3V_4

+1.05V_VTT

T21

V21

T19

P32

+V3.3A_1.5A_HDA_IO

C429

C53

0.1u/10V_4

*1u/6.3V_4

+5VCC_S5 +3VCC_S5

+3V_S5

321

Q23AO3413

R344 *SHORT_6

4 3

VCCAPLLSATA

VCCVRM[1]

VCCASW[22]

VCCASW[23]

VCCASW[21]

VCCSUSHDA

R354 100K_4

VCC3_3[4]

VCC3_3[2]

VCCIO[5]

VCCIO[12] VCCIO[13]

VCCIO[6]

VCCIO[2] VCCIO[3] VCCIO[4]

+1.05V_VTT

20111117 remove 0ohm resistor.

C59 1u/6.3V_4

R123 *SHORT_6

C96 *1u/6.3V_4

+1.05V_VTT

20111107 remove R5144 PU 1.5VSUS.

215

Size Document Number Rev

Date: Sheet of

VCCSUS3_3 = 11 9mA(15mils)

+3VCC_S5

20111018 change for DSW

R56 *SHORT_6

C62

0.1u/10V_4

R57 *SHORT_6

C50

0.1u/10V_4

+1.05V_VTT

VCC5REFSUS=1mA

R110 10/F_4

D11 RB500V-40

C44

0.1u/10V_4

V5REF= 1mA

R353 10/F_4

D10 RB500V-40 C49 1u/6.3V_4

R58 *SHORT_6

VCCSUS3_3 = 11 9mA(15mils)

C48 1u/10V_4

R130 *SHORT_6

VCCPCORE = 28m A(10mils)

C71

0.1u/10V_4

+3V

C95

0.1u/10V_4

+1.05V_VTT

20111117 remove 0ohm resistor.

C89 1u/10V_4

??mA(??mils)

L24 *10uH/100mA_8 C476

*10u/6.3V_6

+1.05V_VTT

VCCME = 1.01A( 60mils)

R375 *SHORT_4

C412

*0.33u/10V_6

VCCSUSHDA= 10m A(8mils)

+3V_S5

Q22AO3413

R355 100K_4

R345 *SHORT_6

Q24 2N7002DW

20111117 change mose footprint to dual type.

Quanta Computer Inc.

PROJECT :

Panther Point 5 /6

Monday, April 09, 2012

+5VCC_S5 +3VCC_S5

20111018 change for DSW

+5V +3V

20111018 change for DSW

+3VCC_S5

+3V

321

Z09

11 40

PCH6(CLG)

U26I

AY4

VSS[159]

D D

IBEX PEAK-M (GND)

U26H

VSS[0]

AA17

VSS[1]

AA2

VSS[2]

AA3

VSS[3]

AA33

VSS[4]

AA34

VSS[5]

AB11

VSS[6]

AB14

VSS[7]

AB39

VSS[8]

AB4

VSS[9]

AB43

VSS[10]

AB5

VSS[11]

AB7

VSS[12]

AC19

VSS[13]

AC2

VSS[14]

AC21

VSS[15]

AC24

VSS[16]

AC33

VSS[17]

AC34

VSS[18]

AC48

AG19 AG31

AG48

AD10 AD11 AD12 AD13 AD19 AD24 AD26 AD27 AD33 AD34 AD36 AD37 AD38 AD39

AD40 AD42 AD43 AD45 AD46

AF10 AF12 AD14 AD16 AF16 AF19 AF24 AF26 AF27 AF29 AF31 AF38

AF42 AF46

AH11 AH36

AH39 AH40 AH42 AH46

AJ19 AJ21 AJ24 AJ33 AJ34 AK12

AD4

AD8 AE2 AE3

AF4

AF5 AF7 AF8

AG2

AH3

AH7

AK3

VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79]

Panther Point_R1P0

C C

B B

A A

VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98]

AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28

AY42 AY46

BB12 BB16 BB20 BB22 BB24 BB28 BB30 BB38

BB46 BC14 BC18

BC22 BC26 BC32 BC34 BC36 BC40 BC42 BC48 BD46

BE22 BE26 BE40 BF10 BF12 BF16 BF20 BF22 BF24 BF26 BF28

BF30 BF38 BF40

BG17 BG21 BG33 BG44

BH11 BH15 BH17 BH19

BH27 BH31 BH33 BH35 BH39 BH43

AY8

B11 B15 B19 B23 B27 B31 B35 B39

F45

BB4

BC2

BD5

BD3

BF8

BG8

H10

BH7

D3 D12 D16 D18 D22 D24 D26 D30 D32 D34 D38 D42

E18

E26 G18 G20 G26 G28 G36 G48 H12 H18 H22 H24 H26 H30 H32 H34

VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249] VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258]

Panther Point_R1P0

VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[328] VSS[329] VSS[330] VSS[331] VSS[333] VSS[334] VSS[335] VSS[337] VSS[338] VSS[340] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352]

H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28

Quanta Computer Inc.

PROJECT :

Size Document Number Rev

Date: Sheet of

Monday, April 09, 2012

Date: Sheet of

Monday, April 09, 2012

Date: Sheet of

Monday, April 09, 2012

PROJECT :

Panther Point 6/6

Z09

12 40

DDR3 DIMM-A

M_A_A[15:0]<4>

D D

M_A_BS#0<4> M_A_BS#1<4> M_A_BS#2<4> M_A_CS#0<4> M_A_CS#1<4> M_A_CLK0<4> M_A_CLK0#<4> M_A_CLK1<4> M_A_CLK1#<4> M_A_CKE0<4> M_A_CKE1<4> M_A_CAS#<4> M_A_RAS#<4>

R238 10K_4

C C

R239 10K_4

B B

M_A_WE#<4>

CLK_SCLK<9,14,19>

CLK_SDATA<9,14,19>

M_A_ODT0<4> M_A_ODT1<4>

M_A_DQSP[7:0]<4>

M_A_DQSN[7:0]<4>

Place these Caps near So-Dimm0.

+1.5VSUS

C720

C717

C638 10u/6.3V_6

A A

+3V

C731

2.2u/6.3V_6

10u/6.3V_6

C736 .1u/16V_4

+0.75V_DDR_VTT

10u/6.3V_6

C323 1U/6.3V_4

C719 .1u/16V_4

M_A_DQSP0 M_A_DQSP1 M_A_DQSP2 M_A_DQSP3 M_A_DQSP4 M_A_DQSP5 M_A_DQSP6 M_A_DQSP7 M_A_DQSN0 M_A_DQSN1 M_A_DQSN2 M_A_DQSN3 M_A_DQSN4 M_A_DQSN5 M_A_DQSN6 M_A_DQSN7

C324 1U/6.3V_4

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

DIMM1_SA0 DIMM1_SA1 CLK_SCLK CLK_SDATA

C248 .1u/16V_4

C312 1U/6.3V_4

107

119

109 108

114 121 101 103 102 104

115 110 113 197 201 202 200

116 120

136 153 170 187

137 154 171 188

135 152 169 186

C243 .1u/16V_4

JDIM1A

A9 A10/AP

A11

A12/BC# A13

A14

A15 BA0

BA1

BA2 S0# S1# CK0 CK0# CK1 CK1#

CKE0

CKE1 CAS# RAS# WE# SA0 SA1 SCL SDA

ODT0 ODT1

DM0

DM1

DM2

DM3 DM4 DM5 DM6 DM7

PC2100 DDR3 SDRAM SO-DIMM

DQS0

DQS1

DQS2

DQS3 DQS4 DQS5 DQS6 DQS7

DQS#0

DQS#1

DQS#2

DQS#3 DQS#4 DQS#5 DQS#6 DQS#7

DDR3-DIMM1_H=5.2_Reverse

C640 .1u/16V_4

C317 1U/6.3V_4

(204P)

C643 .1u/16V_4

C318 *10u/6.3V_6

DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9

5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194

C267

*150u/6.3V_3528

M_A_DQ5 M_A_DQ1 M_A_DQ6 M_A_DQ7 M_A_DQ4 M_A_DQ0 M_A_DQ3 M_A_DQ2 M_A_DQ13 M_A_DQ8 M_A_DQ14 M_A_DQ15 M_A_DQ12 M_A_DQ9 M_A_DQ11 M_A_DQ10 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ19 M_A_DQ16 M_A_DQ17 M_A_DQ23 M_A_DQ18 M_A_DQ29 M_A_DQ28 M_A_DQ30 M_A_DQ25 M_A_DQ27 M_A_DQ24 M_A_DQ26 M_A_DQ31 M_A_DQ33 M_A_DQ32 M_A_DQ39 M_A_DQ38 M_A_DQ36 M_A_DQ37 M_A_DQ35 M_A_DQ34 M_A_DQ41 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ40 M_A_DQ44 M_A_DQ42 M_A_DQ43 M_A_DQ48 M_A_DQ52 M_A_DQ50 M_A_DQ55 M_A_DQ53 M_A_DQ49 M_A_DQ54 M_A_DQ51 M_A_DQ57 M_A_DQ60 M_A_DQ63 M_A_DQ58 M_A_DQ56 M_A_DQ61 M_A_DQ62 M_A_DQ59

M_A_DQ[63:0] <4>

SMDDR_VREF_DQ0_M3<6>

+SMDDR_VREF

M1 solution

SMDDR_VREF_DQ0_M3

CRV add

DEEPS3_EC<4,14>

CHA0 CHA1 CHB0 CHB1

R559 *M3@0_6

+SMDDR_VREF_DIMM_A

SA0SA1 00

1100 1 1

+3V

DDR3_DRAMRST#<4,14>

R558 *0_6

Q36

*AP2302GN

+1.5VSUS

2.48A

TP22

+SMDDR_VREF_DQ0

+1.5VSUS +1.5VSUS

20110817 change to 1K/F_4 20110817 change to 1K/F_4

R556 1K/F_4

+SMDDR_VREF_DQ0 +SMDDR_VREF_DIMM_A

R546 1K/F_4

C600

C602

.1u/16V_4

2.2u/6.3V_6

JDIM1B

VDD1

VDD2

VDD3

VDD4

VDD5

VDD6

VDD7

VDD8

VDD9

100

VDD10

105

VDD11

106

VDD12

111

VDD13

112

VDD14

117

VDD15

118

VDD16

123

VDD17

124

VDD18

199

VDDSPD

NC1

122

NC2

125

NCTEST

198

EVENT#

RESET#

VREF_DQ

126

VREF_CA

VSS1

VSS2

VSS3

VSS4

VSS5

VSS6

VSS7

VSS8

VSS9

VSS10

VSS11

VSS12

VSS13

VSS14

VSS15

DDR3-DIMM1_H=5.2_Reverse

C601 470p/X7R_4

Size Document Number Rev

Date: Sheet of

VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52

(204P)

PC2100 DDR3 SDRAM SO-DIMM

VTT1 VTT2

GND GND

R607 *0_6

+SMDDR_VREF_DIMM_A+SMDDR_VREF_DQ0

C721 .1u/16V_4

DDRIII SO-DIMM-0

44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196

203 204

205 206

R601 1K/F_4

R600 1K/F_4

C722

2.2u/6.3V_6

Quanta Computer Inc.

PROJECT :

C723 470p/X7R_4

Z09

+0.75V_DDR_VTT

13 40Monday, April 09, 2012

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