Quanta Y19C Schematic
1
www.schematic-x.blogspot.com
2
3
4
5
6
7
8
Y33 INTEL SYSTEM DIAGRAM
+3V/+5V S5
PG.29
+1.05V/+1.5V
A A
CPU Core
DDR3L
Charge
PG.15
PG.32~33
PG.30
PG.28
SODIMM1
Max. 8GB
STD
PG.13
SODIMM2
Max. 8GB
RVS
PG.14
mSATA/NGFF
B B
HDD
ODD
PCI-E x 1
LANE2 LANE1
LAN
RTL8161GSH
10/100
C C
Accelerometer
PG.34
SMBUS
WLAN
BT COMBO
PCI-E x 1
Card Reader
RTS5237
KBC
ITE IT8987E/BX
LPC Interface
TPM
PAGE 31SLB9656TT1.2
SLG3NB242
L
D D
GreenCLK
25MHz
TPKB
PG.32PG.32 PG.32PG.31
PAGE 29
PG.33
PG.33
PG.33
LANE3
PG.31
FANROM
1600MT/s
DDR3 L
Channel A
1600MT/s
DDR3 L
Channel B
SATA5 6GB/s
SATA4 6GB/s
SATA0 3GB/s
PG.26PG.20
PG.21
LPC
USB 2.0
PORT10
INTEL
Haswell
Processor : Daul / Quad Core
Power : 37 / 47 (Watt)
Package : BGA1364
Size : 37.5 x 37.5 (mm)
PG.2~5
FDI
DMI
INTEL PCH
Lynx Point
Power : 3.5 Watt
Package : FCBGA695
Size : 20 x 20 (mm)
PG.6~11
Azalia
AUDIO
CODEC
ALC 3241
Speaker
PAGE 18
DDI (5.4Gb/s)
USB 3.0
PORT1,2,5
USB 2.0
PG.18
Dual Digital MIC
PAGE 18
eDP
DP Port B
USB3.0 Ports
combo
Headphone amplifier
HPA0022642RTJR
Subwoofer amplifier
HPA01081RTJR
X3
PG.24
PORT0,1,9
PAGE 19
PAGE 19
RTD 2136 S/R
DP to LVDS Converter
PAGE 15
Webcam
PORT2
Leap Motion
Hp
Combo Jack
MIC
PAGE 18
Subwoofer
PAGE 19
PG.16
PORT8
PG.24
LVDS InterfaceeDP (5.4Gb/s)
PG.17
LVDS
PG.15
HDMI
PORT11
Fingerprint
PG.24
Touch Screen
Elan EKTH3915 for 14",15"
Elan EKTH3918 for 17"
Stackup
TOP
GND
IN1
IN2
VCC
BOT
01
PORT5
PG.24
1
2
PROJECT : Y19C
PROJECT : Y19C
PROJECT : Y19C
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
BLOCK DIAGRAM
BLOCK DIAGRAM
NB5
NB5
3
4
5
6
NB5
7
BLOCK DIAGRAM
Date: Sheet of
Date: Sheet of
Date: Sheet of
134Wednesday, February 19, 2014
134Wednesday, February 19, 2014
134Wednesday, February 19, 2014
8
2A
2A
2A
5
Haswell Processor (DMI,PEG,FDI)
DMI_TXN0[7]
DMI_TXN1[7]
DMI_TXN2[7]
DMI_TXN3[7]
DMI_TXP0[7]
DMI_TXP1[7]
DMI_TXP2[7]
R179 *0_4/S
DPB_LANE0_N
DPB_LANE1_N
DPB_LANE2_N
DPB_LANE3_N
DPB_LANE0_P
DPB_LANE1_P
DPB_LANE2_P
DPB_LANE3_P
DMI_TXP3[7]
DMI_RXN0[7]
DMI_RXN1[7]
DMI_RXN2[7]
DMI_RXN3[7]
DMI_RXP0[7]
DMI_RXP1[7]
DMI_RXP2[7]
DMI_RXP3[7]
FDI_CSYNC_R
D D
FDI_CSYNC[7]
FDI_INT[7]
FDI_CSYNC & FDI_INT
Trace length < 10000 Mils
Impendance = 50 ohm
C C
IN_D2#[17]
IN_D1#[17]
IN_D0#[17]
IN_CLK#[17]
IN_D2[17]
IN_D1[17]
IN_D0[17]
B B
IN_CLK[17]
AB2
AB3
AC3
AC1
AB1
AB4
AC4
AC2
AF2
AF4
AG4
AG2
AF1
AF3
AG3
AG1
F11
F12
C25
A25
C24
A24
D25
B25
D24
B24
C21
A21
C20
A20
D21
B21
D20
B20
C17
A17
C16
A16
D17
B17
D16
B16
U28A
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
FDI_CSYNC
DISP_INT
U28J
DDIB_TXN0
DDIB_TXN1
DDIB_TXN2
DDIB_TXN3
DDIB_TXP0
DDIB_TXP1
DDIB_TXP2
DDIB_TXP3
DDIC_TXN0
DDIC_TXN1
DDIC_TXN2
DDIC_TXN3
DDIC_TXP0
DDIC_TXP1
DDIC_TXP2
DDIC_TXP3
DDID_TXN0
DDID_TXN1
DDID_TXN2
DDID_TXN3
DDID_TXP0
DDID_TXP1
DDID_TXP2
DDID_TXP3
HASWEL L_B GA_E
DMI
PEG
FDI
1 OF 12
HASWEL L_B GA_E
EDP_RCOMP
EDP_DISP_UTIL
eDPFDI
INTEL (R) DDI
PEG_RCOMP
PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15
PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15
PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15
PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15
EDP_HPD
EDP_AUXP
EDP_AUXN
EDP_TXP0
EDP_TXP1
EDP_TXN0
EDP_TXN1
FDI_TXN0
FDI_TXN1
FDI_TXP0
FDI_TXP1
AH6
E10
C10
B10
E9
D9
B9
L5
L2
M4
L4
M2
V5
V4
V1
Y3
Y2
F10
D10
A10
F9
C9
A9
M5
L1
M3
L3
M1
Y5
V3
V2
Y4
Y1
B6
C5
E6
D4
G4
E3
J5
G3
J3
J2
T6
R6
R2
R4
T4
T1
C6
B5
D6
E4
G5
E2
J6
G2
J4
J1
T5
R5
R1
R3
T3
T2
AG6
eDP_RCOMP
E12
E14
INT_eDP_HPD_Q
F14
F15
D14
B12
C14
A12
C12
A14
D12
B14
4
PEG_COMP
R173*0_4
EDP_DISP_UTIL [7,15,16]
INT_eDP_AUXP [15]
INT_eDP_AUXN [15]
INT_eDP_TXP0 [15]
INT_eDP_TXP1 [15]
INT_eDP_TXN0 [15]
INT_eDP_TXN1 [15]
FDI_TXN0 [16]
FDI_TXN1 [16]
FDI_TXP0 [16]
FDI_TXP1 [16]
H_PECI (50ohm)
Route on microstrip only
Spacing > 18 mils
Trace Length: 15 inch
HPECI Ra,Ca need placement close to EC.
PROCHOT# (50ohm)
Trace Length <11 inches
THERMTRIP# (50ohm)
Trace Length: 1.1~12 inches
Rb need placment near PCH
4/30 CRB 1.0 Add
PM_SYNC (50ohm)
Trace Length: 1~11.25 inches
H_PWRGOOD (50ohm)
Trace Length: 1~11.25 inches
CPU RESET#
PLTRST#[9,20,21,22,26,27]
CPU_PLTRST# (50ohm)
Trace Length: 10~17 inches
SM_DRAMPWROK Processor Input.
+3VS5
R193
100K_4
1P35V_PGOOD[30]
PM_DRAM_PWRGD (50ohm)
Trace Length: 2~7 inches
0.047U/25V_4
3
EC_PECI[10,27]
H_PROCHOT#[27,32]
C56
Cb
PM_THRMTRIP#_R[10,27]
PM_SYNC[7]
H_PWRGOOD[10]
CPU_PLTRST#R[10,27]
R533 *1.5K/F_4
7/26: DB phase modify
PM_DRAM_PWRGD_C (50ohm)
Trace Length: < 1 inches
R192
100K_4
U11
2
1
74AHC1G09GW
3 5
C168
D7 *MEK500V-40
2
Haswell Processor (CLK,MISC,JTAG)
U28B
C51
G50
TP_CA TERR#
G51
E50
D53
D52
F50
AP48
L54
DG 498556 -> 1.8K
C210
*0.047U/25V_4
DG 498556 -> 3.3K
PM_DRAM_PWRGD_R (50ohm)
Trace Length: 0.5~1 inches
PROC_DETECT#
CATERR#
PECI
PROCHOT#
THERMTRI P#
PM_SYNC
UNCOREPWRGOOD
SM_DRAMPWROK
RESET
PM_DRAM_PWRGD_R
H_PECI
PM_THRMTRIP#_R
Rb
PM_SYNC_R
R534
*750/F_4
R203
1.8K/F_4
R205
3.3K_4
PROC_DETECT#
H_PROCHOT#_R
PM_DRAM_PWRGD_R
+1.35V_CPU
TP21
TP23
Ra
R239 43_4
Ca
C246 *47P/50V_4
R172 56.2/F_4
Cb need placment near VR
47P/50V_4
R474 *100/F_4
+1.05V
R526 0_4
C153 *0.1U/10V_4
R183 10K_4
To change the resistor values in the DRAMPWROK logic to reduce the
leakage on V DDPWRGOOD
C164
0.1U/10V_4
4
HASWEL L_B GA_E
MISC
PWR MANAGEMENT THERMAL
SSC_DPLL_REF_CLKP
SSC_DPLL_REF_CLKN
DPLL_REF_CLKP
DPLL_REF_CLKN
CLOCKSJTAG & BPM DDR3
SM_DRAMRST#
MISC
2 OF 12
BCLKP
BCLKN
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
PRDY#
PREQ#
TRST#
DBR#
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7
Host CLK:
Trace length < 11000 MILS
Trace spacing = 15 ,20 MILS, Impendence 90 ohm
AA6
CLK_CPU_BCLKP
AB6
CLK_CPU_BCLKN
Y6
CLK_DPLL_SSCLK P
V6
CLK_DPLL_SSCLK N
AE6
CLK_DPLL_NSCCLKP
AC6
CLK_DPLL_NSCCLKN
BE51
TCK
TMS
TDO
DDR3_DRAMRST#
BB51
SM_RCOMP_0
BB53
SM_RCOMP_1
BB52
SM_RCOMP_2
N53
XDP_PRDY#
N52
XDP_PREQ#
N54
XDP_TCLK
M51
XDP_TMS
M53
XDP_TRST#
N49
XDP_TDI_R
TDI
M49
XDP_TDO
F53
XDP_DBRST#
R51
XDP_BPM0
R50
XDP_BPM1
P49
XDP_BPM2
N50
XDP_BPM3
R49
XDP_BPM4
P53
XDP_BPM5
U51
XDP_BPM6
P51
XDP_BPM7
+VCCIO_OUT [4,32]
+VCCIOA_OUT [4]
+1.05V [4,10,11,2 4,27,31]
+1.35V_CPU [4 ,13,14,17,30 ]
+1.35VSUS [4,1 3,14,17,30]
+3VS5 [7,8,10,11,2 6,29,31,34]
+3V [7,8,9,10,11, 13,14,15,16,1 7,18,19,20,2 1,22,23,24,25,26 ,27,32,34]
DDR3_DRAMRST# [13,14]
R215 100/F_4
R213 75/F_4
R214 100/F_4
TP34
TP26
TP31
TP29
TP32
TP28
TP59
TP27
TP61
1
02
CLK_CPU_BCLKP [9]
CLK_CPU_BCLKN [9]
CLK_DPLL_SSCLK P [9]
CLK_DPLL_SSCLK N [9]
CLK_DPLL_NSCCLKP [9]
CLK_DPLL_NSCCLKN [9]
SM_RCOMP[0] W:12mils/S:15mils/L: 500mils,
SM_RCOMP[1] W:12mils/S:15mils/L: 500mils,
SM_RCOMP[2] W:12mils/S:15mils/L: 500mils,
TP58
CPU XDP
TP60
TP24
TP57
TP30
TP25
R525 *1K_4
+3V
XDP_DBRST# [7]
4/30 CRB V1.0 -> 10K
+VCCIO_OUT
R166
Q13
2N7002K
10K_4
3
2
EDP_HPD [15,16]
R161
1
100K_4
5
4
A A
DP & PEG Compensation
+VCCIOA_OUT
+VCCIOA_OUT
R195 24.9/F_4
eDP_RCOMP
Trace length < 100 Mils
Trace Width 20 Mils Trace Spacing 25 Mils
R199 24.9/F_4
PEG_RCOMP
Trace length < 400 MILS
Trace width = 12 MILS
Trace spacing = 15 MILS
eDP_RCOMP
PEG_COMP
3
Processor pull-up (CPU)
H_PROCHOT#
CLK_DPLL_SSCLK PINT_eDP_HPD_Q
CLK_DPLL_SSCLK N
XDP_TDO
XDP_TMS
XDP_TDI_R
XDP_PREQ#
XDP_TCLK
XDP_TRST#
2
R167 62_4
R191 *10K_4
R188 *10K_4
R186 51_4
R184 *51_4
R187 *51_4
R190 *51_4
R536 51_4
R535 51_4
+VCCIO_OUT
+1.05V
PROJECT : Y19C
PROJECT : Y19C
PROJECT : Y19C
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
SNB 1/5 (PCIE&DMI&FDI)
SNB 1/5 (PCIE&DMI&FDI)
NB5
NB5
NB5
SNB 1/5 (PCIE&DMI&FDI)
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
2A
2A
2A
234Wednesday, February 19, 2014
234Wednesday, February 19, 2014
234Wednesday, February 19, 2014
5
4
3
2
1
Haswell Processor (DDR3)
D D
C C
B B
M_A_DQ[63:0][13]
M_A_BS#1[13]
M_A_BS#2[13]
M_A_RAS#[13]
M_A_WE#[13]
M_A_CAS#[13]
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
AH54
AH52
AK51
AK54
AH53
AH51
AK52
AK53
AN54
AN52
AR51
AR53
AN53
AN51
AR52
AR54
AV52
AV53
AY52
AY51
AV51
AV54
AY54
AY53
AY47
AY49
BA47
BA45
AY45
AY43
BA49
BA43
BF14
BC14
BC11
BF11
BE14
BD14
BD11
BE11
BC9
BE9
BE6
BC6
BD9
BF9
BE5
BD6
BB4
BC2
AW3
AW2
BB3
BB2
AW4
AW1
AU3
AU1
AR1
AR4
AU2
AU4
AR2
AR3
BC20
BD21
BD32
BC21
BF20
BF21
BE21
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
SA_BS0
SA_BS1
SA_BS2
VSS
SA_RAS#
SA_WE#
SA_CAS#
HASWELL_BGA_E
3 OF 12
U28C
RSVD
SA_CK0
SA_CKN0
SA_CKE0
SA_CK1
SA_CKN1
SA_CKE1
SA_CK2
SA_CKN2
SA_CKE2
SA_CK3
SA_CKN3
SA_CKE3
SA_CS#0
SA_CS#1
SA_CS#2
SA_CS#3
SA_ODT0
SA_ODT1
SA_ODT2
SA_ODT3
SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7
RSVD
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
RSVD
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
SM_VREF
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
BD31
BF25
BE25
BE34
BC25
BD25
BF34
BF23
BE23
BC34
BC23
BD23
BD34
BE16
BC17
BE17
BD16
BC16
BF16
BF17
BD17
AJ52
AP53
AW52
AY46
BD12
BE7
BA3
AT2
AW39
AJ53
AP52
AW53
BA46
BE12
BD7
BA2
AT3
AW40
BD28
BD27
BF28
BE28
BF32
BC27
BF27
BC28
BE27
BC32
BD20
BF31
BC31
BE20
BE32
BE31
AM6
AR6
AN6
BC53
BA40
AY40
BA39
AY39
AV40
AU40
AV39
AU39
M_A_DQSN0
M_A_DQSN1
M_A_DQSN2
M_A_DQSN3
M_A_DQSN4
M_A_DQSN5
M_A_DQSN6
M_A_DQSN7
M_A_DQSP0
M_A_DQSP1
M_A_DQSP2
M_A_DQSP3
M_A_DQSP4
M_A_DQSP5
M_A_DQSP6
M_A_DQSP7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
+SM_VREF
SMDDR_VREF_DQ0_M3
SMDDR_VREF_DQ1_M3
R207*1K_4
R206*1K_4
M_A_CLKP0 [13]
M_A_CLKN0 [13]
M_A_CKE0 [13]
M_A_CLKP1 [13]
M_A_CLKN1 [13]
M_A_CKE1 [13]
M_A_CS#0 [13]
M_A_CS#1 [13]
M_A_ODT0 [13]
M_A_ODT1 [13]
M_A_DQSN[7:0] [13]
M_A_DQSP[7:0] [13]
M_A_A[15:0] [13]
SM_VREF [13]
SMDDR_VREF_DQ0_M3 [13]
SMDDR_VREF_DQ1_M3 [14]M_A_BS#0[13]
M_B_DQ[63:0][14]
M_B_BS#0[14]
M_B_BS#1[14]
M_B_BS#2[14]
M_B_RAS#[14]
M_B_WE#[14]
SI...Swap M_M_RAS# and M_B_WE#...11/30
M_B_CAS#[14]
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
AC54
AC52
AE51
AE54
AC53
AC51
AE52
AE53
AU47
AU49
AV43
AV45
AU43
AU45
AV47
AV49
BC49
BE49
BD47
BC47
BD49
BD50
BE47
BF47
BE44
BD44
BC42
BF42
BF44
BC44
BD42
BE42
BA16
AU16
BA15
AV15
AY16
AV16
AY15
AU15
AU12
AY12
BA10
AU10
AV12
BA12
AY10
AV10
AU8
BA8
AV6
BA6
AV8
AY8
AU6
AY6
AM2
AM3
AK1
AK4
AM1
AM4
AK2
AK3
AY23
BA23
BA36
AU30
AV23
AW23
AV20
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
SB_BS0
SB_BS1
SB_BS2
VSS
SB_RAS
SB_WE
SB_CAS
HASWELL_BGA_E
4 OF 12
U28D
RSVD
SB_CK0
SB_CKN0
SB_CKE0
SB_CK1
SB_CKN1
SB_CKE1
SB_CK2
SB_CKN2
SB_CKE2
SB_CK3
SB_CKN3
SB_CKE3
SB_CS#0
SB_CS#1
SB_CS#2
SB_CS#3
SB_ODT0
SB_ODT1
SB_ODT2
SB_ODT3
SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7
RSVD
SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
RSVD
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
AY36
AV27
AW27
AU36
AV26
AW26
AU35
AY26
BA26
AV35
AY27
BA27
AV36
BA20
AY19
AU19
AW20
AY20
BA19
AV19
AW19
AD52
AU46
BD48
BD43
AW16
AW10
AW8
AL2
BE38
AD53
AV46
BE48
BE43
AW15
AW12
AW6
AL3
BD38
BA30
AW30
AY30
AV30
AW32
AY32
AT30
AV32
BA32
AU32
AU23
AY35
AW35
AU20
AW36
BA35
BF39
BE39
BF37
BE37
BD39
BC39
BC37
BD37
M_B_DQSN0
M_B_DQSN1
M_B_DQSN2
M_B_DQSN3
M_B_DQSN4
M_B_DQSN5
M_B_DQSN6
M_B_DQSN7
M_B_DQSP0
M_B_DQSP1
M_B_DQSP2
M_B_DQSP3
M_B_DQSP4
M_B_DQSP5
M_B_DQSP6
M_B_DQSP7
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_CLKP0 [14]
M_B_CLKN0 [14]
M_B_CKE0 [14]
M_B_CLKP1 [14]
M_B_CLKN1 [14]
M_B_CKE1 [14]
M_B_CS#0 [14]
M_B_CS#1 [14]
M_B_ODT0 [14]
M_B_ODT1 [14]
M_B_DQSN[7:0] [14]
M_B_DQSP[7:0] [14]
M_B_A[15:0] [14]
03
RSVD_V10 must be grounde d
CPU SM_VREF
A A
PROJECT : Y19C
PROJECT : Y19C
PROJECT : Y19C
Quanta Computer Inc.
Quanta Computer Inc.
+1.35V_CPU [2,4,13,14,17,30]
NB5
NB5
NB5
5
4
3
2
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
SNB 2/5 (DDR3 I/F)
SNB 2/5 (DDR3 I/F)
SNB 2/5 (DDR3 I/F)
1
334Wednesday, February 19, 2014
334Wednesday, February 19, 2014
334Wednesday, February 19, 2014
2A
2A
2A
5
4
3
2
1
Haswell Processor (POWER)
+VCCIN 95A
+VCC_CORE
B43
VCC
B45
VCC
B46
VCC
B48
VCC
C27
VCC
AA46
AA47
C28
C31
C32
C34
C36
C38
C39
C42
C43
C45
C46
C48
D27
D28
D31
D32
D34
D36
D38
D39
D42
D43
D45
D46
D48
E27
E28
E31
E32
E34
E36
E38
E39
E42
E43
E45
E46
E48
F27
F28
F31
F32
F34
F36
F38
F39
F42
F43
F45
F46
F48
G27
G29
G31
G32
G34
G36
G38
G39
G42
G43
G45
G46
G48
H11
H12
H13
H14
H16
H17
H18
H19
H20
H21
H23
H24
H25
H26
H27
H29
A36
A38
A39
A42
A43
A45
A46
A48
AA8
AA9
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
L6
VCC
M6
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
D D
C C
B B
C181
22U/6.3V_6
C180
22U/6.3V_6
C169
22U/6.3V_6
C158
22U/6.3V_6
C577
22U/6.3V_6
C572
22U/6.3V_6
C161
22U/6.3V_6
C175
*22U/6.3V_6
C179
22U/6.3V_6
C162
10U/6.3V_6
C167
22U/6.3V_6
C174
22U/6.3V_6
C160
22U/6.3V_6
C173
22U/6.3V_6
C573
22U/6.3V_6
C570
22U/6.3V_6
C157
22U/6.3V_6
C163
*22U/6.3V_6
C171
22U/6.3V_6
C177
10U/6.3V_6
C170
22U/6.3V_6
C576
22U/6.3V_6
C159
22U/6.3V_6
C176
22U/6.3V_6
C574
22U/6.3V_6
C571
22U/6.3V_6
C178
22U/6.3V_6
C575
22U/6.3V_6
C166
10U/6.3V_6
C172
10U/6.3V_6
VCC Output Decoupling Recommendations
470uFx4 7343
22uFx8
22uFx11
A A
10uFx11
TOP socket side
4 on TOP, 4 on BOT near socket edge
0805
0805
TOP, inside socket cavity
0805
BOT, inside socket cavity
HASWELL_BGA_E
PEG AND DDRSVID
CORE SUPPLY
VCCIO_OUT
VCCIO2PCH
VCOMP_OUT
VIDALERT#
PWR_DEBUG#
IVR_ERRO R
IST_TRIGG ER
5 OF 12
VCC_SENSE
U28E
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VIDSCLK
VIDSOUT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RSVD_TP
RSVD_TP
FC_D5
FC_D3
AR29
AR31
AR33
AT13
AT19
AT23
AT27
AT32
AT36
AV37
AW22
AW25
AW29
AW33
AY18
BB21
BB22
BB26
BB27
BB30
BB31
BB34
BB36
BD22
BD26
BD30
BD33
BE18
BE22
BE26
BE30
BE33
AN33
W9
J12
AR49
J17
J21
J26
J31
AH9
AN31
AN22
AN18
D51
F17
AK6
+VCCIO_OUT_R
+VCCIO_PCH_R
+VCCIOA_OUT_R
C202
1U/6.3V_4
C221
22U/6.3VS_6
C197
1U/6.3V_4
C229
22U/6.3VS_6
C198
1U/6.3V_4
C223
10U/6.3V_6
C196
1U/6.3V_4
PV..R163/R162/R201 change to footprint 0805
J53
H_CPU_SVIDALRT#
J52
H_CPU_SVIDCLK
J50
H_CPU_SVIDDAT
F19
PWR_DEBUG_R
B51
E52
V50
AN49
AJ49
AG50
AK49
AJ50
AP49
AB50
AP50
AD50
AM50
V49
Sense resistor should be placed within 2
U49
inches (50.8 mm) of the processor socket
AM49
W49
Trace Impendence 50 ohm
C50
D5
CPU_EC_PWR
D3
CPU_EC_PWROK
R529 100_4
SENSE LINES
5
4
+1.35V_CPU 4.2A
+1.35V_CPU
C226
22U/6.3VS_6
C219
22U/6.3VS_6
C205
1U/6.3VS_4
C228
22U/6.3VS_6
C227
10U/6.3V_6
C207
1U/6.3V_4
C200
1U/6.3V_4
R1630/F_0805
R162*0/F_0805
R2010/F_0805
R168*0_4/S
R5270_4
+VCC_CORE
VCC_SENSE [32]
C206
1U/6.3V_4
C199
1U/6.3V_4
C225
22U/6.3VS_6
C222
10U/6.3V_6
C201
1U/6.3V_4
C422
10U/6.3V_6
C418
10U/6.3V_6
TP20
+
+VCCIO_OUT
+VCCIO_PCH
+VCCIOA_OUT
Layout note: It is recommended to shield VIDSOUT signal by
routing it in between the VIDSCLK and VIDALERT# signals.
Place PU resistor
close to CPU
Place PU resistor close to CPU
The VIDALERT# signal must have a damping resistor to prevent
overshoot
3
VDDQ Output Decoupling Recommendations
330uFx2 7343
22uFx11
0805
10uFx10
RESERVE THIS CIRCUIT FOR
FUTURE COMPATIBILITY CRB0.7
+1.05V
R164 *0_8
CPU_EC_PWROK
C587
*330U/2V_7343
300mA
300mA
4/30: DG 498550
Haswell PWR_DEBUG requires a 150-Ohm pull-up resistor to PCH 1.05-V VCC
Core when routed to XDP
H_CPU_SVIDCLK
+VCCIO_OUT
R532
H_CPU_SVIDDAT
+VCCIO_OUT
H_CPU_SVIDALRT#
130/F_4
C578 0.1U/10V_4
R530 75/F_4
R531 43_4
BOT socket side
5 onTOP, 6 on BO T inside socket cavity
5 onTOP, 5 on BO T inside socket cavity0805
CPU_EC_PWR
C148
*22U/6.3VS_6
R170
*2K_4
R175
*1K_4
C149
*1U/6.3V_4
EC_PWROK [7,27]
SVID CLK
7/26: DB sch modi fy, Del R23
Place PU resistor
close to VR
DG V0.7 -> 1 10 Ohm
SCH V0.7 -> 130 Ohm
DG V0.7 -> 4 4 Ohm
SCH V0.7 -> 43 Ohm
VR_SVID_CLK [32]
SVID DATA
VR_SVID_DATA [32]
SVID ALERT
VR_SVID_ALERT# [32]
2
+3VPCU
R178
16.5K/F_4
THRM_MOINTOR
R174
Power Test Propose
+1.05V +VCCIO_OUT
R165
150/F_4
PWR_DEBUG_R
R176
*10K_4
CPU VDDQ
+1.35V_CPU
Note: please keep plane is enough for VDDQ 4.2A
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
NB5
NB5
NB5
Date: Sheet of
Date: Sheet of
Date: Sheet of
+VCCIOA_OUT [2]
+VCCIO_OUT [2,32]
+VCCIO_PCH [2,10,11,24,27,31]
+1.5V [7,8,9,11,18,25,26,31]
+1.35V_CPU [2,13,14,17,30]
+1.05V [2,10,11,24,27,31]
+VCC_CORE [5,6,32,33]
+1.35VSUS [2,13,14,17,30]
IO Thrm Protect
C147
0.1U/10V_4
R169
3.3K/F_4
For 75 degree, 1.2v limit, (HW)
100K_4 NTC
PROJECT : Y19C
PROJECT : Y19C
PROJECT : Y19C
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
SNB 3/5 (POWER)
SNB 3/5 (POWER)
SNB 3/5 (POWER)
1 2
C141
0.1U/10V_4
1 2
+1.35VSUS
Placement close to CPU.
C203 0.1U/10V_4
C204 *0.1U/10V_4
1
THRM_MOINTOR1 [27]
+VCCIO_PCH+1.05V
04
C130
10U/6.3V_6
C129
*4.7U/6.3V_4
434Wednesday, February 19, 2014
434Wednesday, February 19, 2014
434Wednesday, February 19, 2014
P
2A
2A
2A
5
+VCC_CORE +VCC_CORE
AB45
AB46
AB8
AC46
C145
C133
C138
0.1U/10V_4
0.1U/10V_4
1 2
D D
C190
0.1U/10V_4
1 2
C186
0.1U/10V_4
1 2
C C
C187
0.1U/10V_4
1 2
B B
A A
1 2
C146
0.1U/10V_4
1 2
C136
0.1U/10V_4
1 2
C132
0.1U/10V_4
1 2
1 2
1 2
1 2
1 2
5
0.1U/10V_4
C185
0.1U/10V_4
C137
0.1U/10V_4
C140
0.1U/10V_4
AC47
AD46
AE46
AE47
AG46
AH46
AH47
AJ45
AJ46
AK46
AK47
AL45
AL46
AM46
AM47
AN10
AN12
AN13
AN14
AN15
AN16
AN17
AN19
AN20
AN21
AN23
AN24
AN25
AN26
AN27
AN29
AN30
AN32
AN34
AN36
AN38
AN39
AN40
AN41
AN42
AN43
AN44
AN45
AN46
AP10
AP12
AP13
AP14
AP15
AP16
AP17
AP18
AP19
AP20
AP21
AP22
AP23
AP24
AP25
AP26
AP27
AP29
AP30
AP31
AP32
AP33
AP34
AP35
AP36
AP37
AP38
AP39
AP40
AP41
AP42
AP43
AP44
AP46
AP47
AR35
AR37
AR39
AR41
AR43
AR45
AR46
AC8
AC9
AD8
AE8
AF8
AG8
AH8
AK8
AL8
AL9
AM8
AM9
AN8
AN9
AP8
AP9
H30
H31
H32
HASWEL L_B GA_E
U28F
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
6 OF 12
H33
VCC
H34
VCC
H36
VCC
H37
VCC
H38
VCC
H39
VCC
H40
VCC
H42
VCC
H43
VCC
H45
VCC
H46
VCC
H48
VCC
H8
VCC
H9
VCC
J10
VCC
J14
VCC
J19
VCC
J24
VCC
J29
VCC
J33
VCC
J36
VCC
J37
VCC
J38
VCC
J39
VCC
J40
VCC
J42
VCC
J43
VCC
J45
VCC
J46
VCC
J48
VCC
J8
VCC
J9
VCC
K38
VCC
K40
VCC
K43
VCC
K44
VCC
K45
VCC
K46
VCC
K48
VCC
K8
VCC
K9
VCC
L37
VCC
L38
VCC
L39
VCC
L40
VCC
L42
VCC
L43
VCC
L44
VCC
L46
VCC
L47
VCC
L8
VCC
M37
VCC
M38
VCC
M39
VCC
M40
VCC
M42
VCC
M43
VCC
M44
VCC
M45
VCC
M46
VCC
M8
VCC
M9
VCC
N37
VCC
N38
VCC
N39
VCC
N40
VCC
N42
VCC
N43
VCC
N44
VCC
N46
VCC
N47
VCC
N8
VCC
N9
VCC
P45
VCC
P46
VCC
P8
VCC
R46
VCC
R47
VCC
R8
VCC
R9
VCC
T45
VCC
T46
VCC
U46
VCC
U47
VCC
U8
VCC
U9
VCC
V45
VCC
V46
VCC
V8
VCC
W46
VCC
W47
VCC
W8
VCC
Y45
VCC
Y46
VCC
Y8
VCC
A27
VCC
A28
VCC
A31
VCC
A32
VCC
A34
VCC
B27
VCC
B28
VCC
B31
VCC
B32
VCC
B34
VCC
B36
VCC
B38
VCC
B39
VCC
B42
VCC
4
1 2
1 2
C143
0.1U/10V_4
1 2
4
C189
0.1U/10V_4
C134
0.1U/10V_4
1 2
1 2
C139
0.1U/10V_4
1 2
C135
0.1U/10V_4
C188
0.1U/10V_4
1 2
1 2
C131
0.1U/10V_4
1 2
C144
0.1U/10V_4
C142
0.1U/10V_4
BC10
BC12
BC15
BC18
BC22
BC26
BC30
BC33
BC36
BC38
BC41
BC43
BC46
BC48
BC50
BC52
BD10
BD15
BD18
BD36
BD41
BD46
BD51
BE10
BE15
BE36
BE41
BE46
BF10
BF12
BF15
BF18
BF22
BF26
BF30
BF33
BF36
BF38
BF41
BF43
BF46
BF48
3
HASWEL L_B GA_E
U28I
VSS
VSS
VSS
VSS
VSS
VSS
BC3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BC5
VSS
VSS
VSS
BC7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BD5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BF7
VSS
C11
VSS
C15
VSS
C19
VSS
C22
VSS
C26
VSS
C30
VSS
C33
VSS
C37
VSS
C4
VSS
C40
VSS
C44
VSS
C49
VSS
C52
VSS
C8
VSS
D11
VSS
D15
VSS
D19
VSS
D22
VSS
D26
VSS
D30
VSS
D33
VSS
D37
VSS
D40
VSS
D44
VSS
D49
VSS
D8
VSS
E11
VSS
E15
VSS
E16
VSS
E17
VSS
E19
VSS
E20
VSS
E21
VSS
E22
VSS
E24
VSS
E25
VSS
E26
VSS
E30
VSS
E33
VSS
E37
VSS
E40
VSS
E44
VSS
E49
VSS
E51
VSS
E53
VSS
E8
VSS
F2
VSS
F26
VSS
F3
VSS
F30
VSS
F33
VSS
F37
VSS
F4
VSS
F40
VSS
F44
VSS
F49
VSS
F5
VSS
G11
VSS
G13
VSS
G16
VSS
9 OF 12
3
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_SENSE
G20
VSS
G23
VSS
G25
VSS
G26
VSS
G30
VSS
G33
VSS
G37
VSS
G40
VSS
G44
VSS
G49
VSS
G52
VSS
G54
VSS
G7
VSS
G8
VSS
G9
VSS
H44
VSS
H49
VSS
H7
VSS
J44
VSS
J49
VSS
J51
VSS
J54
VSS
J7
VSS
K1
VSS
K2
VSS
K3
VSS
K4
VSS
K5
VSS
K6
VSS
K7
VSS
L48
VSS
L7
VSS
L9
VSS
M48
VSS
M50
VSS
M52
VSS
M54
VSS
M7
VSS
N48
VSS
N7
VSS
P1
VSS
P2
VSS
P3
VSS
P4
VSS
P48
VSS
P5
VSS
P50
VSS
P52
VSS
P54
VSS
P6
VSS
P7
VSS
R48
VSS
R7
VSS
T48
VSS
U1
VSS
U2
VSS
U3
VSS
U4
VSS
U48
VSS
U5
VSS
U50
VSS
U52
VSS
U54
VSS
U6
VSS
U7
VSS
V48
VSS
V7
VSS
V9
VSS
W48
VSS
W50
VSS
W52
VSS
W54
VSS
W7
VSS
Y48
VSS
Y7
VSS
Y9
VSS
AR22
VSS
AB48
VSS
P9
VSS
G18
VSS
A49
A50
A8
B4
BA1
BA54
BB1
BB54
BD2
BD53
BF49
BF5
BF50
BF6
C53
D2
E54
F54
G1
D50
R528
100_4
VSS_SENSE [32]
2
HASWEL L_B GA_E
U28L
A3
DAISY_CHAIN_NCTF_A3
A4
DAISY_CHAIN_NCTF_A4
A51
DAISY_CHAIN_NCTF_A51
A52
DAISY_CHAIN_NCTF_A52
A53
DAISY_CHAIN_NCTF_A53
B2
DAISY_CHAIN_NCTF_B2
B3
DAISY_CHAIN_NCTF_B3
B52
DAISY_CHAIN_NCTF_B52
B53
DAISY_CHAIN_NCTF_B53
B54
DAISY_CHAIN_NCTF_B54
BC1
DAISY_CHAIN_NCTF_BC1
BC54
DAISY_CHAIN_NCTF_BC54
BD1
DAISY_CHAIN_NCTF_BD1
BD54
DAISY_CHAIN_NCTF_BD54
BE1
DAISY_CHAIN_NCTF_BE1
BE2
DAISY_CHAIN_NCTF_BE2
BE3
DAISY_CHAIN_NCTF_BE3
BE52
DAISY_CHAIN_NCTF_BE52
BE53
DAISY_CHAIN_NCTF_BE53
BE54
DAISY_CHAIN_NCTF_BE54
BF2
DAISY_CHAIN_NCTF_BF2
BF3
DAISY_CHAIN_NCTF_BF3
BF4
DAISY_CHAIN_NCTF_BF4
12 OF 12
Sense resistor should be placed within 2
inches (50.8 mm) o f the processor soc ket
Trace Impendence 50 ohm
2
DAISY_CHAIN_NCTF_BF51
DAISY_CHAIN_NCTF_BF52
DAISY_CHAIN_NCTF_BF53
DAISY_CHAIN_NCTF_C1
DAISY_CHAIN_NCTF_C2
DAISY_CHAIN_NCTF_C3
DAISY_CHAIN_NCTF_C54
DAISY_CHAIN_NCTF_D1
DAISY_CHAIN_NCTF_D54
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
1
BF51
BF52
BF53
C1
C2
C3
C54
D1
D54
AN35
AN37
AF9
AE9
G14
G17
AD45
AG45
PROJECT : Y19C
PROJECT : Y19C
PROJECT : Y19C
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
SNB 4/5 (POWER & GND)
SNB 4/5 (POWER & GND)
NB5
NB5
NB5
SNB 4/5 (POWER & GND)
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
05
534Wednesday, February 19, 2014
534Wednesday, February 19, 2014
534Wednesday, February 19, 2014
2A
2A
2A
5
4
3
2
1
Haswell Processor (GND)
HASWELL_BGA_E
U28G
A11
VSS
A15
VSS
A19
VSS
A22
VSS
A26
VSS
A30
AA1
AA2
AA3
AA4
AA48
AA5
AA7
AB5
AB51
AB52
AB53
AB54
AB7
AB9
AC48
AC5
AC50
AC7
AD48
AD51
AD54
AD7
AD9
AE1
AE2
AE3
AE4
AE48
AE5
AE50
AE7
AF5
AF6
AF7
AG48
AG5
AG51
AG52
AG53
AG54
AG7
AG9
AH1
AH2
AH3
AH4
AH48
AH5
AH50
AH7
VSS
A33
VSS
A37
VSS
A40
VSS
A44
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
7 OF 12
D D
C C
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ48
AJ51
AJ54
AK48
AK5
AK50
AK7
AK9
AL1
AL4
AL48
AL5
AL7
AM5
AM51
AM52
AM53
AM54
AM7
AN1
AN2
AN3
AN4
AN48
AN5
AN50
AN7
AP51
AP54
AP7
AR12
AR14
AR16
AR18
AR20
AR24
AR26
AR48
AR5
AR50
AR7
AR8
AR9
AT1
AT10
AT12
AT15
AT16
AT18
AT20
AT22
AT25
AT26
AT29
AT33
AT35
AT37
AT39
AT4
AT40
AT42
AT43
AT45
AT46
AT47
AT49
AT50
AT51
AT52
AT53
AT54
AU13
AU18
AU22
AU25
AU29
AU33
AU37
AU42
AV13
AV18
AV22
AV25
AV29
AV33
AV42
AV50
AW13
AW18
AW37
AW42
AW43
AW45
AW46
AW47
AW49
AW5
AW50
AW51
AW54
AW9
AY13
AY22
AY25
AY29
AY33
AY37
AY42
AT5
AT6
AT8
AT9
AU5
AU9
AV1
AV2
AV3
AV4
AV5
AV9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
U28H
HASWELL_BGA_E
8 OF 12
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AY50
AY9
B11
B15
B19
B22
B26
B30
B33
B37
B40
B44
B49
B8
BA13
BA18
BA22
BA25
BA29
BA33
BA37
BA4
BA42
BA5
BA50
BA51
BA52
BA53
BA9
BB10
BB11
BB12
BB14
BB15
BB16
BB17
BB18
BB20
BB23
BB25
BB28
BB32
BB33
BB37
BB38
BB39
BB41
BB42
BB43
BB44
BB46
BB47
BB48
BB49
BB5
BB6
BB7
BB9
R539 *1K_4
R177 49.9/F_4
R171 49.9/F_4
+VCC_CORE
Haswell Processor (RESERVED, CFG)
HASWELL_BGA_E
U28K
AG49
CFG9
R53749.9/F_4
CFG_RCOMP
TESTLO_F20
TESTLO_F21
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
AD49
AC49
AE49
AB49
W51
W53
Y50
V51
Y49
Y54
Y53
U53
V54
R53
R52
Y52
Y51
V53
V52
R54
F20
F21
F22
H54
H53
H51
H52
G19
F51
F52
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG_RCOMP
TESTLO_F20
TESTLO_F21
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CFG
11 OF 12
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
F1
E1
A5
A6
G12
G10
BE4
BD3
F6
G6
G21
G24
L52
L53
L51
F24
F25
L50
L49
E5
B50
AH49
AM48
AU27
AU26
BD4
BC4
AL6
F8
N51
G53
H50
F16
TP38
TP36
TP37
TP35
TP62
TP33
06
B B
CFG[3] (PHYSICAL_DEBUG_E NABLED (DFX PRIVACY))
0 Enable; SET DFX ENABLED BIT IN DEBUG
1 , Disable;
CFG3
R200 *1K_4
Processor Strapping
The CFG signals have a default value of '1' if not terminated on the board.
1 0
A A
CFG2
(PEG Static Lane Reversal)
CFG4
(DP Presence Strap)
CFG7
(PEG Defer Training)
5
Normal Operation Lane Reversed
Disable; No physical DP attached to eDP
PEG train immediately following
xxRESETB de assertion
4
Enable; An ext DP device is connected to eDP
PEG wait for BIOS training
CFG2
R194 *1K_4
CFG4
R538 1K_4
3
CFG[6:5] (PCIE Port Bifurcation Straps)
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
PROJECT : Y19C
PROJECT : Y19C
PROJECT : Y19C
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
NB5
NB5
NB5
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
SNB 5/5 (GND)
SNB 5/5 (GND)
SNB 5/5 (GND)
1
2A
2A
634Wednesday, February 19, 2014
634Wednesday, February 19, 2014
634Wednesday, February 19, 2014
2A
5
4
3
2
1
RSMRST#
EC_PWROK
D D
C253 *220P/50V_4
C274 *220P/50V_4
DMI_RXN0[2]
DMI_RXN1[2]
DMI_RXN2[2]
DMI_RXN3[2]
DMI_RXP0[2]
DMI_RXP1[2]
DMI_RXP2[2]
DMI_RXP3[2]
DMI_TXN0[2]
DMI_TXN1[2]
DMI_TXN2[2]
DMI_TXN3[2]
DMI_TXP0[2]
DMI_TXP1[2]
DMI_TXP2[2]
DMI_TXP3[2]
+1.5V
R481 *0_4/S
R113 7.5K/F_4
DMI_IREF
DMI_COMP
SI..Add SUSWARN# to SUSACK#...11/30
SUSWARN#
R565 *0_4
SUSACK#EC[27]
C C
B B
XDP_DBRST#[2]
SUSWARN#_EC[27]
DNBSWON#[27]
AC_PRESENT_EC[27]
SI..Change RF_OFF_DSW to U25.K7 GPIO72...12/25
RF_OFF_DSW[26]
SYS_PWROK_R
R563 0_4
XDP_DBRST#1
SYS_PWROK SYS_PWROK_R
EC_PWROK[4,27]
RSMRST#[27]
R564 0_4
C29
*0.1U/10V_4
EC_PWROK_R
APWROK_REC_PWROK_R
PM_DRAM_PWRGD
RSMRST#
DNBSWON#_R
AC_PRESENT_R
PM_BATLOW#
PM_RI#
Lynx Point (DMI,FDI,PM)
U25C
AW22
DMI0RXN
AR20
DMI1RXN
AP17
DMI2RXN
AV20
DMI3RXN
AY22
DMI0RXP
AP20
DMI1RXP
AR17
DMI2RXP
AW20
DMI3RXP
BD21
DMI0TXN
BE20
DMI1TXN
BD17
DMI2TXN
BE18
DMI3TXN
BB21
DMI0TXP
BC20
DMI1TXP
BB17
DMI2TXP
BC18
DMI3TXP
DMI
FDI
SUS_STAT# / GPIO61 (SUS)
SUSCLK / GPIO62 (SUS)
SLP_S5# / GPIO63 ( SUS)
System Power Management
SLP_WLAN#/ GPIO29 ( DSW )
SUSACK#
SUSWARN#
TP12
BE16
DMI_IREF
AY17
DMI_IRCOMP
AW17
TP12
AV17
TP7
R6
SUSACK#
AM1
SYS_RESET#
AD7
SYS_PWROK
F10
PWROK
AB7
APWROK
H3
DRAMPWROK
J2
RSMRST#
J4
SUSWARN#/SUSPW RDNACK/GPIO30 (SUS)
(+3VS5)
K1
PWRBTN#
E6
ACPRESENT / GPIO31(DSW)
(DSW)
K7
BATLOW# / GPIO72 (SUS)
N4
DSW (+3VS5)
RI#
AB10
TP21
LPT_PCH_M_EDS/BGA
FDI_RXN0
FDI_RXN1
FDI_RXP0
FDI_RXP1
FDI_CSYNC
FDI_INT
FDI_IREF
FDI_RCOMP
TP16
TP15
TP10
TP17
TP13
DSWVRMEN
DPWROK
WAKE#
(+3V)
CLKRUN#
(+3VS5)
(+3VS5)
(+3VS5)
SLP_S4#
SLP_S3#
SLP_A#
SLP_SUS#
PMSYNCH
SLP_LAN#
TP5
AJ35
AL35
AJ36
AL36
AL39
AL40
AT45
R522 *0_4/S
AR44
R521 7.5K/F_4
AV43
AY45
AV45
AW44
AU42
AU44
C8
DSWVREN
L13
DPWROK
K3
PCIE_WAKE#
AN7
CLKRUN#
U7
SUS_STAT#
Y6
PCH_SUSCLK_L
Y7
C6
H1
F3
F1
AY3
G5
D2
TP7
TP45
SLP_LAN#
FDI_TXN0_P [16]
FDI_TXN1_P [16]
FDI_TXP0_P [16]
FDI_TXP1_P [16]
FDI_CSYNC [2]
FDI_INT [2]
+1.5V
PCIE_WAKE# [20,21,26,27]
CLKRUN# [27]
TP8
R80 *0_4/S
SUSC# [27]
SUSB# [27]
SLP_SUS#EC [27]
PM_SYNC [2]
DPWROK_EC [27]
PCH_SUSCLK [8]
TP6
LVDS_BLON[16]
DISP_ON[16]
DPST_PWM[2,15,16]
PD Res place close to PCH
PCH to Res routeing 37.5 ohm Impedance.
Res to connector filter routeing 50ohm Imped ance.
R515 *150/F_4
R516 *150/F_4
R517 *150/F_4
R151 649/F_4
DAC_IREF (50ohm)
Trace length < 500 MILS
Trace spacing = 30 MILS
Reserve for power on sequence
PCH Pull-high/low(CLG)
PM_DRAM_PWRGD
PM_RI#
SUS_STAT#
PCIE_WAKE#
SLP_LAN#
SUSACK#
SUSWARN#
PCIE_WAKE#
PM_BATLOW#
DNBSWON#_R
AC_PRESENT_R
A A
DPWROK
CLKRUN#
XDP_DBRST#
RSMRST#
R448 *200/F_4
R452 10K_4
R53 *10K_4
R451 *1K_4
R48 *10K_4
R51 *10K_4
R449 *10K_4
R450 1K_4
R26 8.2K_4
R420 *10K_4
R25 10K_4
R24 *100K_4
R74 100K/F_4
R59 10K_4
R462 1K_4
R435 *1K_4
R419 10K_4
5
+3V_DEEP_SUS
+3VS5
+3V
for DS3
INT HDMI Detect Function
DPB_HPD_Q
4
R148 *0_4/S
HDMI_HPD_CON [17]
R95 330K_4
+3V_RTC
On Die DSW VR Enable
High = Enab le (Default)
Low = Disable
3
Lynx Point ( DDI)
U25D
K36
EDP_BKLTEN
G36
EDP_VDD_EN
N36
EDP_BKLTCTL
T45
CRT_BLUE
U44
CRT_GREEN
V45
CRT_RED
M43
CRT_DDC_CLK
M45
CRT_DDC_DATA
N42
CRT_HSYNC
N44
CRT_VSYNC
U40
DSWVREN
DAC_IREF
7/26 DB Modify
U39
2
DAC_IREF
CRT_IRTN
LPT_PCH_M_EDS/BGA
DDPB_HPD
R40
R39
H45
H43
K40
DPB_HPD_Q
DDPB_CTRLCLK
DDPB_CTRLDATA
DDPB_AUXN
DDPB_AUXP
LVDS
DDPC_HPD
DDPD_HPD
R35
R36
K43
K45
K38
N40
N38
J42
J44
H39
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPD_AUXN
Digital Display Interface
DDPD_AUXP
CRT
+3V_DEEP_SUS [8,9,10,11]
+3V_RTC [8,11,24]
+1.05V [2,4,10,11,24,27,31]
+3VPCU [4,8,18,22,24,26,27,28,29]
+3VS5 [2,8,10,11,26,29,31,34]
+3V [2,8,9,10,11,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,32,34]
+5V [17,18,19,22,23,24,26,34]
System PWR_OK(CLG)
SYS_PWROK IMVP_PWRGD
R55
10K_4
PROJECT : Y19C
PROJECT : Y19C
PROJECT : Y19C
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
NB5
NB5
NB5
Date: Sheet of
Date: Sheet of
Date: Sheet of
PCH 1/6 (DMI/FDI/VIDEO)
PCH 1/6 (DMI/FDI/VIDEO)
PCH 1/6 (DMI/FDI/VIDEO)
SDVO_CLK [17]
SDVO_DATA [17]
EC_PWROK
1
07
INT. HDMI
IMVP_PW RGD [3 2]
734Wednesday, February 19, 2014
734Wednesday, February 19, 2014
734Wednesday, February 19, 2014
2A
2A
2A
5
TP13
R103 *0_4/S
R94 1M_4
D D
+3V_RTC
Reserve for EMI
C553
*10P/50V_4
for DS3
+3V_DEEP_SUS
SIO_EXT_SCI#[27]
C C
PCH Strap Table
B B
Pin Name Strap description Sampled Configuration
ACZ_SPKR[18]
ACZ_SDIN0[18]
TP16
R503 10K_4
SIO_EXT_SCI#
TP46
TP42
TP47
TP41
SPKR
GNT3# / GPIO55 Top-Block Swap Override
RTC_X1
RTC_X2
RTC_RST#
SRTC_RST#
SM_INTRUDER#
PCH_INVRMEN
ACZ_BCLK
ACZ_SYNC
ACZ_SPKR
ACZ_RST#
ACZ_SDOUT
GPIO33
PCH_JTAG_TCK_R
PCH_JTAG_TMS
PCH_JTAG_TDI_R
PCH_JTAG_TDO_R
R79 0_4
TP9
PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_CS1#
PCH_SPI_SI
PCH_SPI_SO
PCH_SPI_IO2
PCH_SPI_IO3
No reboot mode setting PWROK
Lynx Point (HDA,JTAG,SATA)
U25A
B5
RTCX1
B4
RTCX2
D9
RTCRST#
B9
SRTCRST#
A8
INTRUDER #
G10
INTVRMEN
B25
HDA_BCLK
A22
HDA_SYNC
AL10
SPKR
C24
HDA_RST#
L22
HDA_SDIN0
K22
HDA_SDIN1
G22
HDA_SDIN2
F22
HDA_SDIN3
A24
HDA_SDO
(+3V)
B17
HDA_DOCK_EN# / GPIO33
(+3VS5)
C22
HDA_DOCK_RST# / GPIO13
AB3
JTAG_TCK
AD1
JTAG_TMS
AE2
JTAG_TDI
AD3
JTAG_TDO
F8
TP25
C26
TP22
AB6
TP20
AJ11
SPI_CLK
AJ7
SPI_CS0#
AL7
SPI_CS1#
AJ10
SPI_CS2#
AH1
SPI_MOSI
AH3
SPI_MISO
AJ4
SPI_IO2
AJ2
SPI_IO3
LPT_PCH_M_EDS/BGA
PWROK
INTVRMEN Integrated 1.05V VRM enable ALW AYS
HDA_DOCK_EN#/GPIO33
GNT1# / GPIO51
GPIO19
Flash Descriptor Security
Only for Interposer
Boot BIOS Selection 1 [bit-1]
Boot BIOS Selection 0 [bit-0]
PWROK
PWROK
PWROK
HDA_SYNC On-Die PLL VR Voltage Select RSMRST
HDA_SDO PWROKFlash Descriptor Security
SATA2GP/GPIO36
A A
SATA3GP/GPIO37
GPIO62 / SUSCLK
DMI RX Termination
TLS Confidentiality
PLL On-Die Voltage
Regulator Enable
5
PLTRST#
PLTRST#
RSMRST#
4
A20
LAD0
C20
LAD1
A18
LAD2
C18
LAD3
B21
LFRAME#
D21
LDRQ0#
RTCIHDA
LDRQ1# / GPIO23
SATA 6G LPC
SATA4RXN / PERN1
SATA4RXP / PERP1
SATA4TXN / PETN1
SATA4TXP / PETP1
SATA5RXN / PERN2
SATA5RXP / PERP2
SATA5TXN / PETN2
SATA5TXP / PETP2
SATA_RCOMP
SATA0GP / GPIO21
SATA1GP / GPIO19
SPI JTAG
0 = Default (weak pull-down 20K)
1 = Setting to No-Reboot mode
0 = "top-block swap" mode
1 = Default (Int P U)
0 = Disable
1 = Enable
0 = Override
1 = Default (weak pull-up 20K)
GNT0#GN T1#
11
00
0 = Support by 1.8V (weak pull-down)
1 = Support by 1.5V
0 = Security Effect (Int PD)
1 = Can be Overridden
0 = DMI RX is t erminated to VSS
1 = DMI RX is t erminated to VCC/ 2
0 = TLS no conf identiality (Int PD)
1 = TLS with c onfidentiali ty
0 = Disable
1 = Enable (Int PU)
4
(+3V)
SERIRQ
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA_IREF
SATALED#
(+3V)
(+3V)
TP9
TP8
G20
AL11
BC8
BE8
AW8
AY8
BC10
BE10
AV10
AW10
BB9
BD9
AY13
AW13
BC12
BE12
AR13
AT13
BD13
BB13
AV15
AW15
BC14
BE14
AP15
AR15
AY5
SATA_RCOMP
Impedance = 50 ohm
Trace length < 500 mils
Trace spacing = 15 mils
DG V0.7 -> 7 50 ohm
SCH V0.7 -> 0 ohm
BD4
AP3
AT1
AU2
BA2
BB2
Boot Location
SPI
LPC
PCH_DRQ#0
PCH_DRQ#1
SERIRQ
SATA_RCOMP
SATA_IREF
DGT_STOP#
BBS_BIT0
3
LAD0 [22,26,27]
LAD1 [22,26,27]
LAD2 [22,26,27]
LAD3 [22,26,27]
LFRAME# [22,26,27]
TP15
TP14
R57 8.2K_4
R84 7.5K/F_4
R81 *0_4/S
R464 10K_4
R466 10K_4
R439 *10K_4
DG recommended that AC coupling capacitors should be
close to the connector (<100 mils) for optimal signal quality.
+1.5V
+1.5V
SATA_LED# [18]
+3V
+3V
+3V
SERIRQ [22,27]
SATA_RXN0 [23]
SATA_RXP0 [23]
SATA_TXN0 [23]
SATA_TXP0 [23]
SATA_RXN4 [23]
SATA_RXP4 [23]
SATA_TXN4 [23]
SATA_TXP4 [23]
SATA_RXN5 [25]
SATA_RXP5 [25]
SATA_TXN5 [25]
SATA_TXP5 [25]
+3V
Circuit
ACZ_SPKR
PCH_INVRMEN
GPIO33
[Need external pull-down for LPC BIOS]
Default weak pull -up on GNT0/1#
+VCC_HDA_IO
DGPU_PWR_EN_R[10]
R32 *1K_4
GPIO33_EC[27]
FDI_OVRVLTG[10]
R58 *1K_4
PCI_GNT3# [9]
R96 330K_4
R488 *0_4
1 2
R467 *1K_4
R105 *1K_4
R499 *1K_4
ACZ_SDOUT
DGPU_PWR_EN_R
FDI_OVRVLTG
R30 *1K_4
3
+1.05V [2,4,10,11,24,27,31]
+3V_RTC [7,11,24]
+3VPCU [4,18,22,24,26,27,28,29]
+3V [2,7,9,10,11,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,32,34]
+3V_DEEP_SUS [7,9,10,11]
+3VS5 [2,7,10,11,26,29,31,34]CLKGEN_RTC_X1[24]
+5V [17,18,19,22,23,24,26,34]
+3V_RTC_0 [24]
ODD (SATA0 3Gb/s)
PCH JTAG Debug(CLG)
BIT_CLK_AUDIO
EMI
C560
*33P/50V_4
HDD0 (SATA4 6.0Gb/s)
mSATA (SATA5 6Gb/s)
+3V
+3V_RTC
+3V
BBS_BIT0
BBS_BIT1 [9]
ACZ_SYNC
R504 *1K_4
R465 *1K_4
R432 *1K_4
+VCC_HDA_IO
+3V
+3V
PCH_SUSCLK [7]
TP48
TP54
TP52
TP51
TP49
TP17
2
RTC Clock 32.768KHz
RTC Circuitry(RTC)
10/11: SI change footprint
+3VPCU
+3V_RTC_0
+3V_RTC_0
R257 *1K_4
12
CN25
BAT_CONN
DFHS02FS027
BAT-23_2-4_2
RTC Power trace width 20mils.
HDA Bus(CLG)
BIT_CLK_AUDIO[18]
ACZ_RST#_AUDIO[18]
ACZ_SDOUT_AUDIO[18]
ACZ_SYNC_AUDIO[18]
R497 33_4
PCH SPI ROM(CLG)
PCH_SPI_CS1#
PCH_SPI_CS0#
PCH_SPI_CLK
PCH_SPI_SI
PCH_SPI_SO
PCH_SPI_CS0#_R[27]
PCH_SPI1_CLK_R[27]
PCH_SPI1_SI_R[27]
PCH_SPI1_SO_R[27]
U27&U26 footprint
PCH_SPI_CS0#_R
PCH_SPI1_CLK_R
PCH_SPI1_SI_R
BIOS_WP#
R493 *0_4
R492 0_4
R144 33_4
R145 0_4
R494 0_4
PCH_SPI_CS0#_R
PCH_SPI1_CLK_R
PCH_SPI1_SI_R
PCH_SPI1_SO_R
BIOS_WP#
HOLD#
U26
1
CE#
6
SCK
5
SI
2
SO
3
WP#
*A25LQ32AM-F/Q
AKE3EFP0N07
91960-0084L-8P-SOCKET
11/29: Pre PV modify
2
+SPI_PWR
VDD
HOLD#
PCH_SPI_CS0#_R
PCH_SPI1_CLK_R
PCH_SPI1_SI_R
PCH_SPI1_SO_R
PCH_SPI_IO2
PCH_SPI_IO3
VSS
30mils
+3V_RTC
+3V_RTC_2
+3V_RTC_1
D11
*BAT54C
ACZ_SYNC
R495 3.3K_4
R496 0_4
R143 0_4
Vender Size
EON
Winbond
GigaDevice
NB5
NB5
NB5
ACZ_BCLK
ACZ_RST#
ACZ_SDOUT
C119
*22P/50V_4
BIOS_WP#
TP50
8MB AKE3EZN0Q01 (EN25QH64-104HIP (QE)
8MB
8MB
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
R507 33_4
R502 33_4
R506 33_4
R498
*1M_4
If EC support embedded flash , SPI
power must be used S5_0N power rail
for EC load code.
PCH_SPI_CS0#_R
PCH_SPI1_CLK_R
PCH_SPI1_SI_R
PCH_SPI1_SO_R
+SPI_PWR
8
7
HOLD#PCH_SPI1_SO_R
4
1
RTC_RST#
3
2
Q25
*2N7002K
1
R293
*100/F_4
R272 20K/F_4
R259 20K/F_4
C270
1U/6.3V_4
R429
*210/F_4
R428
*100/F_4
C120
*22P/50V_4
U27
1
CE#
6
SCK
5
SI
2
SO
3
WP#
EN25QH32-10 4HIP
HOLD#
+3VS5
C273
1U/6.3V_4
C266
1U/6.3V_4
R430
*210/F_4
R458
*100/F_4
+SPI_PWR
VDD
HOLD#
VSS
12
R457
*210/F_4
PCH_JTAG_TMS
PCH_JTAG_TDI_R
PCH_JTAG_TDO_R
R427
*100/F_4
R139 *0_4
R147 *0_4/S
8
7
4
P/N
AKE3EFP0N07 (W25Q64FVSSIQ)
AKE3EGN0Q01 (GD25B64BSIGR)
PROJECT : Y19C
PROJECT : Y19C
PROJECT : Y19C
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PCH 2/6 (SATA/HDA/SPI)
PCH 2/6 (SATA/HDA/SPI)
PCH 2/6 (SATA/HDA/SPI)
1
08
EC_RTC_RST [27]
RTC_RST#
J6
*SOLDERJUMPER -2
SRTC_RST#
PCH_JTAG_TCK_R
R426
*51_4
+3VS5
+3V_DEEP_SUS
R149 3.3K_4
C115
0.1U/10V_4
834Wednesday, February 19, 2014
834Wednesday, February 19, 2014
834Wednesday, February 19, 2014
2A
2A
2A
5
PCI/USBOC# Pull-up(CLG)
PCI_PIRQA#
R125 8.2K_4
PCI_PIRQB#
R124 8.2K_4
PCI_PIRQC#
R119 8.2K_4
PCI_PIRQD#
R120 8.2K_4
+3V
RP9
10
9
for DS3
8
7 4
10K_10P8R_6
+3V_DEEP_SUS
RP8
10
9
8
7 4
10K_10P8R_6
BT_COMBO_EN#[26]
USB30_RX1-[24]
USB30_RX2-[24]
USB30_RX5-[26]
USB30_RX1+[24]
USB30_RX2+[24]
USB30_RX5+[26]
USB30_TX1-[24]
USB30_TX2-[24]
USB30_TX5-[26]
USB30_TX1+[24]
USB30_TX2+[24]
USB30_TX5+[26]
BBS_BIT1[8]
ACC_LED#[18]
PCI_GNT3#[8]
R121 *0_4/S
PM_EXTTS#0[13,14]
EXTTS#1[14]
D D
EDID_SELECT#
USB_OC4#
USB_OC1#
USB_OC3#
USB3.0
C C
ACCEL_INTH#[24]
B B
MPC Switch Control
MPC_PWR_CT RL#
MPC_PWR_CTRL#
+3V
1
ACC_LED#
2
ACCEL_INTH#MPC_PWR_CTRL#
3
BT_COMBO_EN#
DGPU_SELECT#
56
4/30: CRB 1.0 =>rename PCH_TP26
1
USB_OC6#
2
USB_OC0#
3
PCH_AOCS#
USB_OC5#USB_OC2#
56
TP11
Low = MPC ON
High = MPC OFF (Default)
R112 *1K_4
PLTRST#(CLG)
PLTRST#
A A
PLTRST# [2,20,21,22,26,27]
5
Lynx Point (PCI,USB,NVRAM)
U25E
BA45
TP1
BC45
TP2
BE44
TP3
BE43
TP4
AY43
PCH_TP26
R5238.2K_4
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
BT_COMBO_EN#
DGPU_SELECT#
EDID_SELECT#
BBS_BIT1
ACC_LED#
PCI_GNT3#
MPC_PWR_CTRL#
PCI_PME#
PLTRST#
PLTRST#
R101
100K_4
TD_IREF
AR26
USB3RXN1
AW26
USB3RXN2
AW29
USB3RXN5
AR29
USB3RXN6
AP26
USB3RXP1
AV26
USB3RXP2
AV29
USB3RXP5
AP29
USB3RXP6
BE24
USB3TXN1
BD25
USB3TXN2
BE26
USB3TXN5
BD27
USB3TXN6
BD23
USB3TXP1
BC24
USB3TXP2
BC26
USB3TXP5
BE28
USB3TXP6
H20
PIRQA#
L20
PIRQB#
K17
PIRQC#
M20
PIRQD#
A12
GPIO50
B13
GPIO52
C12
GPIO54
C10
GPIO51
A10
GPIO53
AL6
GPIO55
G17
PIRQE# / GPIO2
F17
PIRQF# / GPIO3
L15
PIRQG# / GPIO4
M15
PIRQH# / GPIO5
AD10
PME#
Y11
PLTRST#
LPT_PCH_M_EDS/B GA
12/18 PV modify
MBCLK2[14,15,27]
MBDATA2[14,15,27]
+3V
SMB_PCH_DAT
SMB_PCH_CLK
Thermal
(+3V)
(+3V)
(+3V)
(+3V)
PCI
(+3V)
(+3V)
USB
(+3V)
(+3V)
(+3V)
(+3V)
(+3VS5)
(+3VS5)
(+3VS5)
(+3VS5)
(+3VS5)
(+3VS5)
(+3VS5)
(+3VS5)
SMBus/Pull-up(CLG)
Q7
2N7002KDW
2N7002KDW
5
2
6
Q6
43
1
4 3
1
5
2
6
4
C- Link
CL_CLK1
CL_DATA1
CL_RST1#
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
USBRBIAS#
USBRBIAS
TP24
TP23
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
+3V
R447 2.2K_4
SMB_ME1_CLK
+3V_DEEP_SUS
SMB_ME1_DAT
R446 2.2K_4
SMB_RUN_DAT [13,14,15,22]
R41 4.7K_4
R71 4.7K_4
SMB_RUN_CLK [13,14,15,22]
4
AF11
AF10
AF7
B37
D37
A38
C38
A36
C36
A34
C34
B33
D33
F31
G31
K31
L31
G29
H29
A32
C32
A30
C30
B29
D29
A28
C28
G26
F26
F24
G24
K24
K26
M33
L33
P3
V1
U2
P1
M3
T1
N2
M1
for DS3
WLAN
LAN
Cardreader
USB_BIAS
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
PCH_AOCS#
USBP0- [24]
USBP0+ [24]
USBP1- [24]
USBP1+ [24]
USBP2- [24]
USBP2+ [24]
USBP5- [24]
USBP5+ [24]
USBP8- [16]
USBP8+ [16]
USBP9- [18]
USBP9+ [18]
USBP10- [26]
USBP10+ [26]
USBP11- [24]
USBP11+ [24]
R131
22.6/F_4
PCIE_RXN3_CARD[21]
PCIE_RXP3_CARD[21]
PCIE_TXN3_CARD[21]
PCIE_TXP3_CARD[21]
USB2.0
USB2.0
Leap Motion
Touch screen
Webcam
USB2.0/USB3.0 CO MBO 3nd
WLAN
FPR
CLK_REQ/Strap Pin(CLG)
PCIE_CLKREQ_LAN#
CLK_PCIE_REQ2#
PCIE_CLKREQ_WLAN#
CLK_PCIE_REQ3#
CLK_PCIE_REQ4#
CLK_PEGB_REQ#
CLK_PEGA_REQ#
CLK_BUF_BCLK_N
CLK_BUF_BCLK_P
CLK_BUF_PCIE_3GPLL#
CLK_BUF_PCIE_3GPLL
+3V
CLK_BUF_DREFCLK#
CLK_BUF_DREFCLK
CLK_BUF_DREFSSCLK#
CLK_BUF_DREFSSCLK
CLK_PCH_14M
PCIE_RXN1[26]
PCIE_RXP1[26]
PCIE_TXN1[26]
PCIE_TXP1[26]
PCIE_RXN2_LAN[20]
PCIE_RXP2_LAN[20]
PCIE_TXN2_LAN[20]
PCIE_TXP2_LAN[20]
USB2.0/USB3.0 CO MBO 1st
USB2.0/USB3.0 CO MBO 2nd
+1.5V
WLAN
R16 10K_4
R17 10K_4
R456 10K_4
R453 10K_4
R454 10K_4
R421 10K_4
R56 10K_4
SG : Rb ; UM A : Ra
R123 10K_4
R126 10K_4
R129 10K_4
R132 10K_4
R142 10K_4
R141 10K_4
R479 10K_4
R477 10K_4
R513 10K_4
C554 0.1U/10V_4
C552 0.1U/10V_4
C559 0.1U/10V_4
C558 0.1U/10V_4
C557 0.1U/10V_4
C562 0.1U/10V_4
CLK_PCIE_WLAN#[26]
CLK_PCIE_WLAN[26]
PCIE_CLKREQ_WLAN#[26]
CLK_PCIE_LANN[20]
CLK_PCIE_LANP[20]
LAN
PCIE_CLKREQ_LAN#[20]
CLK_PCIE_CARDN[21]
CLK_PCIE_CARDP[21]
CLK_PCIE_REQ2#[21]
+3V
+3V_DEEP_SUS
3
Lynx Point (PCI-E,SMBUS,CLK)
PCIE_TXN1_C
PCIE_TXP1_C
PCIE_TXN2_LAN_C
PCIE_TXP2_LAN_C
PCIE_TXN3_CARD_C
PCIE_TXP3_CARD_C
R138 *0_4/S
R133 7.5K/F_4
PCIE_IREF
PCIE_RCOMP
CLK_PCIE_REQ2#
CLK_PCIE_REQ3#
CLK_PCIE_REQ4#
BOARD_ID0[10]
BOARD_ID1[10]
BOARD_ID2[10]
CLK_PEGA_REQ#
for DS3
U25B
AW31
PERN1 / USB3RN3
AY31
PERP1 / USB3RP3
BE32
PETN1 / USB3TN3
BC32
PETP1 / USB3TP3
AT31
PERN2/ USB3RN4
AR31
PERP2/ USB3RP4
BD33
PETN2/ USB3TN4
BB33
PETP2/ USB3TP4
AW33
PERN3
AY33
PERP3
BE34
PETN3
BC34
PETP3
AT33
PERN4
AR33
PERP4
BE36
PETN4
BC36
PETP4
AW36
PERN5
AV36
PERP5
BD37
PETN5
BB37
PETP5
AY38
PERN6
AW38
PERP6
BC38
PETN6
BE38
PETP6
AT40
PERN7
AT39
PERP7
BE40
PETN7
BC40
PETP7
AN38
PERN8
AN39
PERP8
BD42
PETN8
BD41
PETP8
BE30
PCIE_IREF
BD29
PCIE_RCOMP
BC30
TP11
BB29
TP6
Y43
CLKOUT_PCIE0N
Y45
CLKOUT_PCIE0P
AB1
PCIECLKRQ0# / GPIO73
AA44
CLKOUT_PCIE1N
AA42
CLKOUT_PCIE1P
AF1
PCIECLKRQ1# / GPIO18
AB43
CLKOUT_PCIE2N
AB45
CLKOUT_PCIE2P
AF3
PCIECLKRQ2# / GPIO20/ SMI#
AD43
CLKOUT_PCIE3N
AD45
CLKOUT_PCIE3P
T3
PCIECLKRQ3# / GPIO25
AF43
CLKOUT_PCIE4N
AF45
CLKOUT_PCIE4P
V3
PCIECLKRQ4# / GPIO26
AE44
CLKOUT_PCIE5N
AE42
CLKOUT_PCIE5P
AA2
PCIECLKRQ5# / GPIO44
AB40
CLKOUT_PCIE6N
AB39
CLKOUT_PCIE6P
AE4
PCIECLKRQ6# / GPIO45
AJ44
CLKOUT_PCIE7N
AJ42
CLKOUT_PCIE7P
Y3
PCIECLKRQ7# / GPIO46
AB35
CLKOUT_PEG_A_N
AB36
CLKOUT_PEG_A_P
AF6
PEG_A_CLKRQ# / GPIO47
AD39
TP19
AD38
TP18
LPT_PCH_M_EDS/B GA
PCIE Clock
3
SMBUS
PCI-E*
(+3VS5)
(+3V)
(+3V)
(+3VS5)
(+3VS5)
(+3VS5)
(+3VS5)
(+3VS5)
(+3VS5)
2
(+3VS5)
SMBALERT# / GPIO11
SMBCLK
SMBDATA
(+3VS5)
SML0ALERT# / GPIO60
SML0CLK
SML0DATA
SML1ALERT# / PCHHOT# / GPIO74
CLOCKS
(+3VS5)
(+3VS5)
SML1CLK / GPIO58
(+3VS5)
SML1DATA / GPIO75
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
PEG_B_CLKRQ# / GPIO56
(+3VS5)
CLKOUT_ITPXDP _N
CLKOUT_ITPXDP _P
CLKOUT_DPNS_N
CLKOUT_DPNS_P
CLKOUT_DP_N
CLKOUT_DP_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_GND1_N
CLKIN_GND1_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKIN_SATA_N
CLKIN_SATA_P
REFCLK14IN
CLKIN_PCILOOPB ACK
XTAL25_IN
XTAL25_OUT
ICLK_IREF
DIFFCLK_BIA SREF
CLKOUT_33MHZ0
CLKOUT_33MHZ1
CLKOUT_33MHZ2
CLKOUT_33MHZ3
CLKOUT_33MHZ4
(+3V)
CLKOUTFLEX0 / GPIO64
(+3V)
CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
(+3V)
CLKOUTFLEX3 / GPIO67
(+3V)
FLEX CLOCKS
2
N7
SMBALERT#
R10
SMB_PCH_CLK
U11
SMB_PCH_DAT
N8
DRAMRST_CNTRL_PCH
U8
SMB_ME0_CLK
R7
SMB_ME0_DAT
H6
SML1ALERT#_R
K6
SMB_ME1_CLK
N11
SMB_ME1_DAT
Y39
Y38
U4
CLK_PEGB_REQ#
AH43
CLK_PCH_ITPN
AH45
CLK_PCH_ITPP
AF35
AF36
AJ40
AJ39
AF39
AF40
AY24
CLK_BUF_PCIE_3GPLL#
AW24
CLK_BUF_PCIE_3GPLL
AR24
CLK_BUF_BCLK_N
AT24
CLK_BUF_BCLK_P
H33
CLK_BUF_DREFCLK#
G33
CLK_BUF_DREFCLK
BE6
CLK_BUF_DREFSSCLK#
BC6
CLK_BUF_DREFSSCLK
F45
CLK_PCH_14M
D17
CLK_PCI_FB
AM43
XTAL25_IN
AL44
XTAL25_OUT XTAL25_OUT_1
AM45
ICLK_IREF
AN44
ICLK_BIAS
D44
CLK_PCI_TPM_R
E44
CLK_PCI_CARD_R
B42
CLK_PCI_FB_R CLK_PCI_FB
F41
CLK_PCI_LPC_R
A40
CLK_PCI_EC_R
C40
F38
F36
F39
for DS3
TP10
TP19
TP18
TP44
TP53
TP55
CLK_DPLL_NSCCLKN [2]
CLK_DPLL_NSCCLKP [2]
CLK_DPLL_SSCLKN [2]
CLK_DPLL_SSCLKP [2]
CLK_CPU_BCLKN [2]
CLK_CPU_BCLKP [2]
R158 *0_4
R518 *0_4/S
R519 *7.5K/F_4
R520 7.5K/F_4
TP56
+1.05V [2,4,10,11,24,27,31]
+1.5V [7,8,11,18,25,26,31]
+3VS5 [2,7,8,10,11,26,29,31,34]
+3V [2,7,8,10,11,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,32,34]
+3V_DEEP_SUS [7,8,10,11]
SMBus/Pull-up(CLG)
+3V_DEEP_SUS
R27 1K_4
R50 10K_4
R445 2.2K_4
R444 2.2K_4
R52 2.2K_4
R28 2.2K_4
R49 10K_4
NB5
NB5
NB5
XTAL25_IN
R157 *0_4/S
XTAL25_IN_1
C125 *33P/50V_4
R156
*1M_4
C126 *33P/50V_4
+1.5V
+VCCAXCK_VRM
R15222_4
R51222_4
R51422_4
R51122_4
DRAMRST_CNTRL_PCH
SMBALERT#
SMB_PCH_CLK
SMB_PCH_DAT
SMB_ME0_CLK
SMB_ME0_DAT
SML1ALERT#_R
PROJECT : Y19C
PROJECT : Y19C
PROJECT : Y19C
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
PCH 3/6 (PCIE/USB/CLK)
PCH 3/6 (PCIE/USB/CLK)
PCH 3/6 (PCIE/USB/CLK)
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
CLK_PCH_14M
C564
*22P/50V_4
CLK_33M_DEBUG
CLK_33M_DEBUG
CLK_33M_KBC
C565
*22P/50V_4
10/12: SI modify
Y8
*25MHZ
CLK_PCI_TPM [22]
CLK_33M_DEBUG [26]
CLK_33M_KBC [27]
1
09
RF
C563
*22P/50V_4
PCH_XTAL25_IN [24]
934Wednesday, February 19, 2014
934Wednesday, February 19, 2014
934Wednesday, February 19, 2014
2A
2A
2A
5
Lynx Point (GPIO,VSS_NCTF,RSVD)
Lynx Point (GPIO,VSS_NCTF,RSVD)
Lynx Point (GPIO,VSS_NCTF,RSVD)Lynx Point (GPIO,VSS_NCTF,RSVD)
U25F
PCI_SERR#[27]
SIO_EXT_SMI#[27]
D D
Reserve
C C
BT_OFF[26]
RF_OFF[26]
ZERO_ODD_DP#[23]
TP40
DGPU_PWR_EN_R[8]
FDI_OVRVLTG[8]
TP43
R35 100_4
R436 *0_4
S_GPIO
SIO_EXT_SMI#
BOARD_ID4
BOARD_ID5
BT_OFF
LAN_DISABLE#_R
RF_OFF
ODD_PRSN T#_R
DGPU_PWROK
BIOS_REC
GPIO24
GPIO27
BOARD_ID3
GPIO35
DGPU_PWR_EN_R
FDI_OVRVLTG
MFG_MODE
DGPU_PRSNT#
TEST_SET_UP
GPIO49
SV_DET
AT8
BMBUSY# / GPIO0
(+3V)
F13
TACH1 / GPIO1
(+3V)
A14
TACH2 / GPIO6
(+3V)
G15
TACH3 / GPIO7
(+3V)
Y1
GPIO8
(+3VS5)
K13
LAN_PHY_PW R_CTRL / GPIO12
DSW
AB11
GPIO15
(+3VS5)
AN2
SATA4GP / GPIO16
(+3V)
C14
TACH0 / GPIO17
(+3V)
BB4
SCLOCK / GPIO22
(+3V)
Y10
GPIO24
(+3VS5)
R11
GPIO27
(DSW)
AD11
GPIO28
(+3VS5)
AN6
GPIO34
(+3V)
AP1
GPIO35 / NMI#
(+3V)
AT3
SATA2GP / GPIO36
(+3V)
AK1
SATA3GP / GPIO37
(+3V)
AT7
SLOAD / GPIO38
(+3V)
AM3
SDATAOUT0 / GPIO39
(+3V)
AN4
SDATAOUT1 / GPIO48
(+3V)
AK3
SATA5GP / GPIO49
(+3V)
U12
GPIO57
(+3VS5)
BE41
VSS_NCTF_1
BE5
VSS_NCTF_2
C45
VSS_NCTF_3
A5
VSS_NCTF_4
4
3
2
1
Clock Gen Power OK (CLG)
GPIO
NCTF
TACH4 / GPIO68
(+3V)
TACH5 / GPIO69
(+3V)
TACH6 / GPIO70
(+3V)
TACH7 / GPIO71
(+3V)
RCIN#
PROCPWRGD
THRMTRIP#
PLTRST_PROC#
CPU/MISC
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NTCF_25
VSS_NCTF_8
VSS_NCTF_12
VSS_NCTF_15
TP14
PECI
C16
D13
G13
H15
AN10
AY1
AT6
AV3
AV1
AU4
A2
A41
A43
B1
B2
B44
BA1
BC1
BD2
BD44
BD45
BE2
BE3
D1
E1
E45
A4
N10
A44
B45
BD1
GPIO70
GPIO71
R478 *0_4
EC_RCIN#
PCH_THRMTRIP#
R471 *0_4/S
BOARD_ID6
BOARD_ID7
R473 390_4
EC_A20GATE [27]
EC_PECI [2,27]
EC_RCIN# [27]
H_PWRGOOD [2]
PM_THRMTRIP#_R [2,27]
CPU_PLTRST#R [2,27]
MFG_MODE
S_GPIO
TEST_SET_UP
BIOS_REC
SV_DET
R34 10K_4
R36 1K_4
R437 10K_4
R62 10K_4
R29 10K_4
+3V
+3V_DEEP_SUS
+3V_DEEP_SUS [7,8,9,11]
+3VS5 [2,7,8,11,26,29,31,34]
+3V [2,7,8,9,11,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,32,34]
+5VS5 [18,24,29,30,31,32,33,34]
PCH MISC PU /PD
EC_A20GATE
EC_RCIN#
PCH_THRMTRIP#
R37 10K_4
R61 10K_4
R472 *1K_4
GPIO Pull-up/Pull-down(CLG)
RF_OFF
GPIO24
BT_OFF
GPIO35
SIO_EXT_SMI#
GPIO70
GPIO71
ODD_PRSN T#_R
DGPU_PWROK
Power already stuffed.
GPIO49
DGPU_PWROK
LAN_DISABLE#_R
GPIO27
R31 1K_4
R54 *10K_4
R423 10K_4
R438 10K_4
R104 10K_4
R83 10K_4
R110 10K_4
R463 10K_4
R491 10K_4
R433 10K_4
R434 *10K_4
R487 *10K_4
R78 *10K_4
R77 10K_4
10
+3V
+1.05V
+3V_DEEP_SUS
+3V
+3VS5
B B
LPT_PCH_M_EDS/BGA
BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4
BOARD_ID5
BOARD_ID6
BOARD_ID7
BOARD_ID0
BOARD_ID1
BOARD_ID2
RU0
R425 *10K_4
RU1
R431 10K_4
RU2
R455 *10K_4
R33 10K_4
R489 *10K_4
R118 *10K_4
RU6
R490 *10K_4
RU7
R482 *10K_4
3
for DS3
+3V_DEEP_SUS
+3V
GFX Present
R461 100K_4
DGPU_PRSNT#
Stuff
NC
SG
Ra
Rb
RaRb
R460 *10K_4
UMA
Rb
Ra
2
+3V
PROJECT : Y19C
PROJECT : Y19C
PROJECT : Y19C
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
NB5
NB5
NB5
Date: Sheet of
Date: Sheet of
Date: Sheet of
PCH 4/6 (GPIO/MISC)
PCH 4/6 (GPIO/MISC)
PCH 4/6 (GPIO/MISC)
1
10 34Wednesday, February 19, 2014
10 34Wednesday, February 19, 2014
10 34Wednesday, February 19, 2014
2A
2A
2A
BOARD ID SETTING
Model
Pavillian 14” 0
Pavillian 15.6”
Pavillian 17"
Envy 14"
A A
Envy 15.6"
Envy 17"
BOARD_ID7
0000
000
000
000
000
000
5
0
0
0
0
0
BOARD_ID2BOARD_ID3BOARD_ID5BOARD_ID 5
0
0
0
1
1
0
1
0
0
11
BOARD_ID0BOARD_ID1BOARD_ID4
0
0
1
0
0
0
0
0
1
0
0
0
4
BOARD_ID0[9]
BOARD_ID1[9]
BOARD_ID2[9]
RD0
R424 10K_4
RD1
R459 10K_4
RD2
R422 10K_4
RD3 RU3
R60 *10K_4
RD4 RU4
R485 10K_4
RD5 RU5
R109 10K_4
RD6
R486 10K_4
RD7
R483 10K_4
5
Lynx Point (POWER)
U25J
AF34
C118
1U/6.3V_4
VCCVRM[5]
AP45
VCC[3]
M29
VCCCLK3_3[1]
L29
VCCCLK3_3[2]
L26
VCCCLK3_3[3]
M26
VCCCLK3_3[4]
U32
VCCCLK3_3[5]
V32
VCCCLK3_3[6]
Y32
VCCCLK[1]
AD34
VCCCLK[2]
AA30
VCCCLK[3]
AA32
VCCCLK[4]
AD35
VCCCLK[5]
AG30
VCCCLK[6]
AG32
VCCCLK[7]
AD36
VCCCLK[8]
AE30
VCCCLK[9]
AE32
VCCCLK[10]
AW40
VCCVRM[6]
AK30
VCC3_3[7]
AK32
VCC3_3[8]
AJ12
V_PROC_IO[1]
AJ14
V_PROC_IO[2]
K8
VCCSUS3_3[9]
A6
VCCRTC
P14
DCPRTC[1]
P16
DCPRTC[2]
LPT_PCH_M_EDS/BGA
C122
10U/6.3V_6
0.15A (20mils)
+V1.5S_VCCATS
0.13A (20mils)
4mA (10mils)
POWER
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCCSUS3_3[6]
VCCUSBPLL
VCC3_3[3]
VCCIO[11]
VCCIO[12]
VCCIO[13]
VCCIO[14]
VSS
DCPSUS2
VCCSUS3_3[7]
VCCSUS3_3[8]
VCCDSW3_3
VCC3_3[4]
VCC3_3[5]
VCC3_3[6]
GPIO/LPCFUSE
SATA USB
HDA
VCCIO[15]
DCPSST
VCC[1]
VCC[2]
VCCASW[12]
VCCASW[13]
VCCVRM[7]
VCCIO[16]
VCCSUSHDA
Clock and Miscellaneous
THERMAL
CPURTC
+V3.3S_VCC_FLEX0
C941U/6.3V_4
+V3.3S_VCC_FLEX1
C1091U/6.3V_4
+V3.3S_VCC_FLEX23
C1131U/6.3V_4
+V3.3S_VCC_ASEPCI
C1031U/6.3V_4
+V1.05S_VCC_SSCFF
C1071U/6.3V_4
+VCCCLKF135
C991U/6.3V_4
+V1.05S_VCCCLKF100
C1011U/6.3V_4
+V1.05S_VCCSSCF100
C1021U/6.3V_4
C116*0.1U/10V_4
C980.1U/10V_4
+V1.05S_VCCPCPU
C68 0.1U/10V_4
C60 0.1U/10V_4
C58 1U/6.3V_4
0.261A (40mils)
C401U/6.3V_4
C530.1U/10V_4
C590.1U/10V_4
C551U/6.3V_4
+VCCRTCEXT
C720.1U/10V_4
0.15A (20mils)
C123
*10U/6.3V_6
0.3A (20mils)
+V3.3S_VCCPTS
+VCCPRTCSUS_3P3
+VCCAXCK_VRM_R +VCCAXCK_VRM+1.05V
R155 *1/F_4
+1.05V
D D
+3V
+3V
+3V
+3V
+1.05V
+1.05V
+V1.05S_VCC_SSCFF
+1.05V
C C
+1.05V
+VCCIO_PCH
B B
L17 *10uH/100MA_8
R154 *0_8/S
+1.5V
+VCC_AXCK_DCB +V1.05S_VCC_AXCK_DCB
1.09A (40mils)
50mA (10mils)
+V1.05S_VCCCLKF100
+V1.05S_VCCSSCF100
R150 *0_6/S
+1.5V
+3V
R100*0_6/S
+3V_DEEP_SUS
R67 *0_6/S
+3V_RTC
4
0.26A (40mils)
R24
+V3.3A_VCCPUSB
R26
R28
U26
U35
+V1.05S_VCCAUSB
L24
+V3.3S_VCCAUBG
U30
+V1.05S_VCCUSBCORE
V28
V30
Y30
3.629A (160mils)
M24
Y35
+V1.05M_VCCDUSBSUS
28mA (10mils)
0.26A (40mils)
R20
R22
15mA (10mils)
A16
+VCCPDSW
AE14
+V3.3S_VCCPCORE
AF12
AG14
U36
+V1.05S_VCCAUX
AA14
+VCCSST
P18
+V3.3S_VCCPFUSE
P20
L17
PCH_VCC_1_1_20
R18
PCH_VCC_1_1_21
+V1.05S_VCCAPLL_SATA3
AN11
AK22
10mA (10mils)
+VCC_HDA_IO
A26
C870.1U /10V_4
C930.1U /10V_4
C1101U/6.3V _4
+V3.3A_VCCPSUS
for DS3
C73 0.1U/10V_4
R128 *0_6/S
R122 *0_6
C821U/6.3V_4
PCH VRM Power
+V1.05S_VCC_EXP
3.629A (160mils)
C5550.1U/10V_4
C670.01U /25V_4
C660.1U/10V_4
C1050.1U/10V _4
+1.05V
C117*1U/6.3V_4
+1.05V
+3V
+1.05V
+1.05V
+1.05V
L15*10uH/100MA_8
R99*0_8/S
C63*10U /6.3V_6
+3V_DEEP_SUS
for DS3
+3V_DEEP_SUS
for DS3
+3V
+1.05V
+3VS5
+3V
+1.05V
+1.5V
3
PCH VRM Power
+1.05V
+1.5V
PCH VRM Power
+1.05V
+1.5V
+1.05V
+1.05V
C741U/6.3V_4
3.629A (160mils)
+V3.3A_VCCPSUS
L48 *10uH/100mA_8
R484 *0_8/S
C548*10U/6.3V_6
+V1.05S_VCC_EXP
L16 *1uH/25mA_6
R153 *0_8/S
+V1.05S_VCC_EXP
3.629A (160mils)
1.29A (60mils)
0.67A (40mils)
+V1.05M_VCCASW
C95 1U/6.3V_4
C80 1U/6.3V_4
C70 22U/6.3VS_6
R111 5.11/F_4
+V1.05S_VCC_EXP
+V3.3A_VCCPSUS
C83*1U/6.3V_4
C91*10U/6.3V_6
+VCCAPLL_USB3
C65*1U/6.3V_4
+V1.05S_VCCAPLL_FDI
+3V_DEEP_SUS [7,8,9,10]
+5VS5 [18,24,29,30,31,32,33,34]
+5V [17,18,19,22,23,24,26,34]
+V1.05S_PCH_VCC
C811U/6.3V_4
C891U/6.3V_4
C841U/6.3V_4
C9710U /6.3VS_6
+PCH_VCCDSW
0.261A (40mils)
0.476A (30mils)
+VCCA_USBSUS
+V1.05M_VCCSUS
98mA (15mils)
C124*10U/6.3V_6
0.179A (20mils)
2
Lynx Point (POWER)
POWER
U25G
AA24
VCCCORE[1]
AA26
VCCCORE[2]
AD20
VCCCORE[3]
AD22
VCCCORE[4]
AD24
VCCCORE[5]
AD26
VCCCORE[6]
AD28
VCCCORE[7]
AE18
VCCCORE[8]
AE20
VCCCORE[9]
AE22
VCCCORE[10]
AE24
VCCCORE[11]
AE26
VCCCORE[12]
AG18
VCCCORE[13]
AG20
VCCCORE[14]
AG22
VCCCORE[15]
AG24
VCCCORE[16]
Y26
VCCCORE[17]
AA18
VCCASW[1]
U18
VCCASW[2]
U20
VCCASW[3]
U22
VCCASW[4]
U24
VCCASW[5]
V18
VCCASW[6]
V20
VCCASW[7]
V24
VCCASW[8]
Y18
VCCASW[9]
Y20
VCCASW[10]
Y22
VCCASW[11]
V22
VCCASW[12]
U14
DCPSUSBYP
AM18
VCCIO[1]
AM20
VCCIO[2]
AM22
VCCIO[3]
AP22
VCCIO[4]
AR22
VCCIO[5]
AT22
VCCIO[6]
AJ30
VCCSUS3_3[1]
AJ32
VCCSUS3_3[2]
AJ26
DCPSUS3_3[1]
AJ28
DCPSUS3_3[2]
AK26
VCCVRM[1]
AK28
VCCVRM[2]
AK20
VCCIO[7]
Y12
DCPSUS1
BB44
VCCVRM[3]
AN34
VCCIO[8]
AN35
VCCIO[9]
LPT_PCH_M_EDS/BGA
CRT
VCC CORE
VCCMPHY
DMI / PCIE
USB3
SPI HVCMOS
FDI
VCCADAC1_5
VCCADACBG3_3
VCC3_3[1]
VCC3_3[2]
VCCVRM[4]
VCCIO[10]
VCCSPI
+VCCIO_PCH [2,4,10,24,27,31]+3V [2,7,8,9,10,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,32,34]
+1.05V [2,4,10,24,27,31]
+1.5V [7,8,9,18,25,26,31]
+3VS5 [2,7,8,10,26,29,31,34]
+VCCA_DAC_1_2
70mA (15 mils)
L50
*HCB1608KF-181T15/1.5A_6
P45
R510 *0_4/S
P43
VSS
13mA (10mils)
M31
+V3.3S_ADACBG
R134 *0_6
R135 *0_4/S
133mA (20mils)
R30
R32
+V3.3S_VCC_GIO
PCH VRM Power
BE22
L49 *1uH/25mA_6
R501 *0_8/S
AK18
+V1.05S_VCC_EXP
3.629A (160mils)
+V3.3M_VCCPSPI
R38 *0_6
AD12
R39 *0_6/S
22mA (10mils)
If EC support embedded flash , SPI
power must be used S5_0N power rail
for EC load code.
1
11
+1.5V
+3V
C1110.1U/10V_4
+3V
+1.05V+V1.05S_VCCAPLL_EXP
+1.5V
C550*10U/6.3V_6
+3VS5
+3V_DEEP_SUS
C361U/6.3V_4
PCH VCCIO Pow er
C78
10U/6.3V_6
3.629A (160mils)
C90
1U/6.3V_4
C114
1U/6.3V_4
C88
1U/6.3V_4
+V1.05S_VCC_EXP+1.05V
A A
5
C75
1U/6.3V_4
Near Pin
AN34,AN35
C112
1U/6.3V_4
PCH VCCSUS
+3V_DEEP_SUS
for DS3
4
+V3.3A_VCCPSUS
C106
0.1U/10V_4
PV...R 140 c hange t o 10k
PV...A dd C10 8
PV...A dd R137
PV...A dd C92
PV...D el 1 46
Q12A
5
C100
*1U/6.3V_4
+3VS5 +3VS5
R146
*100K/F_4
34
1U/6.3V_4
R140 10K/F_4
C121
*1U/6.3V_4
C104
2
+3VS5
R598
100K/F_4
SLP_SUS_ON[27]
3
2N7002KDW
R137
100K/F_4
Q11 AO3409
1
C108
.1U/10V_4
+3V_DEEP_SUS
3
2
C92
0.01U/25V_4
C96
.1U/10V_4
12
R130
22_8
61
2
Q12B
2N7002KDW
NB5
NB5
NB5
PROJECT : Y19C
PROJECT : Y19C
PROJECT : Y19C
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
PCH 5/6 (POWER)
PCH 5/6 (POWER)
PCH 5/6 (POWER)
Date: Sheet of
Date: Sheet
Date: Sheet
1
of
of
11 34Wednesday, February 19, 2014
11 34Wednesday, February 19, 2014
11 34Wednesday, February 19, 2014
2A
2A
2A
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