QUANTA Y0DD Schematics
5
www.vinafix.com
4
3
2
1
01
PCB 10L STACK UP
D D
SATA - 1st NGFF SSD
C C
Package : 9.5 (mm)
Power :
Pike Intel SKYLAKE ULT Platform Block Diagram
LPDDR3 1600MHz
16Gb x64 1PCS
LPDDR3 1600MHz
16Gb x64 1PCS
PAGE 26
LPDDR3L x1600MHz 1.2V
PAGE 17
LPDDR3L x1600MHz 1.2V
PAGE 18
SATA0/PCIE 4XLANE
SKYLAKE U
Processor
Processor : Daul Core
Power : 15 (Watt)
Package : BGA1356
Size : 40 X 24 (mm)
eDP X4
DP Port 2
DP Port 1
USB3.0 Interface
USB2.0 Interface
USB 3.0* Port 1,2 ,3
PS8330B
Package : QFN-40
PS8201A
Package : QFN-40
TP2546
Package : QFN-16 3x3
PAGE 25
eDP
PAGE 20
Mini-DP
PAGE 21
HDMI Conn
PAGE 22
USB3.0 Port x 3
(total 3.5A)
Port1,2,3
PAGE 25
LAYER 1 : TOP
LAYER 2 : SGND
LAYER 3 : IN1(High)
LAYER 4 : IN2(High)
LAYER 5 : SGND
LAYER 6 : SVCC
LAYER 7 : IN3(Low)
LAYER 8 : IN4(High)
LAYER 9 : SGND
LAYER 10 : BOT
Camera
Port6
System BIOS
SPI ROM
PAGE 10
SPI Interface
HP
PAGE 2~16
TPM
SLB9665 V2.0
B B
Home Capacitve button
PAGE 24
ITE 8987
Embedded Controller
Power :
Keyboard
Touch Pad
PAGE 27
PS2
Package : BGA128
Size : 7x 7 (mm)
SMBUS
PAGE 27
A A
5
FAN
PAGE 26
PAGE 30
PAGE 24
CX7501
Power :
Package : MQFN
Size : 7 x 7 (mm)
PAGE 23
Speaker
Headphone amplifier
HPA0022642RTJR
Digital MIC
4
PCIE Gen 1 x 1 Lane
Port2
Carde Reader
RTS5237
PAGE 23
PAGE 24
PAGE 20
PCIE Port5
PAGE 26
Combo Jack
iPHONE type
PAGE 20
Touch Screen
Port8
PAGE 20
Halt Mini Card
Intel Rambo Peak
WLAN / BT Combo
PCIE Port6
USB20 Port7
PAGE 28
3
ISH
EC
2
G-Sensor
HP3DC2TR
COLAY
PAGE 29
SM BUS
IT8350
Sensor Hub
Size : 14 x 14 (mm)
Port4
NB5
NB5
NB5
Accelerometer/Compass/Gryoscope
HP9DS0TR
PAGE 29
PROJECT : Y0DD
PROJECT : Y0DD
PROJECT : Y0DD
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Block Diagram
Block Diagram
Block Diagram
1
1A
1A
1 41Tuesday, May 26, 2015
1 41Tuesday, May 26, 2015
1 41Tuesday, May 26, 2015
1A
I'm from VIETNAM sualaptop365
5
+3V <4,10,11,12,13,14,15,16,20,21,22,23,25,26,27,29,30,31,37,38>
+1.0V <4,6,16,30,36>
+VCCSTPLL <4,5,6,9,36,38>
+VCCIO <6,16,36>
D D
DDPB_CTRLDATA/ GPP_E19
Display Port B Detected
This signal has a weak internal pull-down.
0 = Port B is not detected.
1 = Port B is detected.
This signal has a weak internal pull-down.
0 = Port C and D is not detected.
1 = Port C and D is detected.
DDPD_CTRLDATA
C C
INT_DP_SCL
INT_DP_SDA
R51 10K_2
R245 2.2K_2
R246 2.2K_2
HDMI
+3V
eDP_COMPIO and ICOMPO signals should be shorted near
balls and routed with typical impedance <25 mohms
SDVO_CLK<22>
SDVO_DATA<22>
INT_DP_SCL<21>
INT_DP_SDA<21>
+VCCIO
IN_D2#<22>
IN_D2<22>
IN_D1#<22>
IN_D1<22>
IN_D0#<22>
IN_D0<22>
IN_CLK#<22>
IN_CLK<22>
4
IN_D2#
IN_D2
IN_D1#
IN_D1
IN_D0#
IN_D0
IN_CLK#
IN_CLK
INT_DP_TXN0<21>
INT_DP_TXP0<21>
INT_DP_TXN1<21>
INT_DP_TXP1<21>
INT_DP_TXN2<21>
INT_DP_TXP2<21>
INT_DP_TXN3<21>
INT_DP_TXP3<21>
DDPD_CTRLDATA
R47 24.9/F_2
EDP_RCOMP
U11A
E55
DDI1_TXN[0]
F55
DDI1_TXP[0]
E58
DDI1_TXN[1]
F58
DDI1_TXP[1]
F53
DDI1_TXN[2]
G53
DDI1_TXP[2]
F56
DDI1_TXN[3]
G56
DDI1_TXP[3]
C50
DDI2_TXN[0]
D50
DDI2_TXP[0]
C52
DDI2_TXN[1]
D52
DDI2_TXP[1]
A50
DDI2_TXN[2]
B50
DDI2_TXP[2]
D51
DDI2_TXN[3]
C51
DDI2_TXP[3]
L13
GPP_E18/DDPB_CTRLCLK
L12
GPP_E19/DDPB_CTRLDATA
N7
GPP_E20/DDPC_CTRLCLK
N8
GPP_E21/DDPC_CTRLDATA
N11
GPP_E22/DDPD_CTRLCLK
N12
GPP_E23/DDPD_CTRLDATA
E52
EDP_RCOMP
*SKL_ULT
REV = 1
SKL_ULT
DDI
DISPLAY SIDEBANDS
3
?
Need apply PN
EDP
GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3
GPP_E17/EDP_HPD
EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]
EDP_AUXN
EDP_AUXP
EDP_DISP_UTIL
DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
DDI3_AUXN
DDI3_AUXP
EDP_BKLTEN
EDP_BKLTCTL
EDP_VDDEN
?1 OF 20
C47
C46
D46
C45
A45
B45
A47
B47
E45
F45
B52
G50
F50
E48
F48
G46
F46
L9
L7
L6
N9
L10
R12
R11
U13
INT_EDP_TXN0
INT_EDP_TXP0
INT_EDP_TXN1
INT_EDP_TXP1
INT_EDP_TXN2
INT_EDP_TXP2
INT_EDP_TXN3
INT_EDP_TXP3
INT_EDP_AUXN
INT_EDP_AUXP
EDP_DISP_UTIL
HDMI_HPD_CON
ULT_EDP_HPD
PCH_LVDS_BLON
PCH_DPST_PWM
PCH_DISP_ON
2
INT_EDP_TXN0 <20>
INT_EDP_TXP0 <20>
INT_EDP_TXN1 <20>
INT_EDP_TXP1 <20>
INT_EDP_TXN2 <20>
INT_EDP_TXP2 <20>
INT_EDP_TXN3 <20>
INT_EDP_TXP3 <20>
INT_EDP_AUXN <20>
INT_EDP_AUXP <20>
TP46
INT_DP_AUXN <21>
INT_DP_AUXP <21>
HDMI_HPD_CON <22>
INT_DP_HPD_Q <21>
ULT_EDP_HPD <20>
PCH_LVDS_BLON <20>
PCH_DPST_PWM <20>
PCH_DISP_ON <20>
Reserve EDP_HPD opposites circuit!
ULT_EDP_HPD
Mini-DP
+3V
R188
*10K_2
R187
100K_2
1
02
?
4 OF 20
Need apply PN
JTAG
PROC_TCK
PROC_TDI
PROC_TDO
PROC_TMS
PROC_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_TRST#
JTAGX
PDC
B61
XDP_TCK0
D60
XDP_TDI_CPU
A61
XDP_TDO_CPU
C60
XDP_TMS_CPU
B59
XDP_TRST#_CPU
B56
JTAG_TCK_PCH
D59
JTAG_TDI_PCH
A56
JTAG_TDO_PCH
C59
JTAG_TMS_PCH
C61
XDP_TRST#_CPU
A59
JTAGX_PCH
XDP_TCK0 <16>
XDP_TDI_CPU <16>
XDP_TDO_CPU <16>
XDP_TMS_CPU <16>
XDP_TRST#_CPU <2,16>
JTAG_TCK_PCH <16>
JTAG_TDI_PCH <16>
JTAG_TDO_PCH <16>
JTAG_TMS_PCH <16>
XDP_TRST#_CPU <2,16>
JTAGX_PCH <16>
2
Close to EC
PM_THRMTRIP#
Processor pull-up (CPU)
TO BE REPLACED WITH 1K OHMS FOR SKL .
470 OHM IS FOR I/P
PLACE NEAR CPU
XDP_TMS_CPU
XDP_TDI_CPU
XDP_TDO_CPU
H_PROCHOT#
XDP_TCK0
XDP_TRST#_CPU
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
NB5
NB5
NB5
Date: Sheet of
Date: Sheet of
Date: Sheet of
R213 1K_4
R36 *51_2
R31 *51_2
R28 *51_2
R142 1K_2
R177 51_2
R27 51_2
PROJECT : Y0DD
PROJECT : Y0DD
PROJECT : Y0DD
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
SKLU (1/14)
SKLU (1/14)
SKLU (1/14)
1
+VCCSTPLL
+1.0V
+1.0V
2 41Tuesday, May 26, 2015
2 41Tuesday, May 26, 2015
2 41Tuesday, May 26, 2015
1A
1A
1A
U11D
AT16
AU16
D63
A54
C65
C63
A65
C55
D55
B54
C56
A6
A7
BA5
AY5
H66
H65
CATERR#
PECI
PROCHOT#
THERMTRIP#
SKTOCC#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3
PROC_POPIRCOMP
PCH_OPIRCOMP
OPCE_RCOMP
OPC_RCOMP
*SKL_ULT
REV = 1
CATERR#
H_PROCHOT#<30,32,38>
+VCCSTPLL
R165 *49.9/F_2
+1.0V
B B
A A
CATERR#
R29 *51_2
R30 51_2
R35 51_2
R25 51_2
R23 51_2
Close to Chipset
5
JTAGX_PCH
JTAG_TMS_PCH
JTAG_TDI_PCH
JTAG_TDO_PCH
JTAG_TCK_PCH
R164 499/F_4
4
EC_PECI<30>
PM_THRMTRIP#<30>
XDP_BPM0<16>
XDP_BPM1<16>
TP45
TP47
TP35
TP34
R61 49.9/F_2
R58 49.9/F_2
R48 49.9/F_2
R45 49.9/F_2
EC_PECI
PROCHOT#
PM_THRMTRIP#
CPU_GP0
CPU_GP1
CPU_GP2
CPU_GP3
PROC_POPIRCOMP
PCH_OPI_RCOMP
EDRAM_OPIO_RCOMP
EOPIO_RCOMP
SKL_ULT
CPU MISC
3
I'm from VIETNAM sualaptop365
5
M_A_DQSN[7:0]<17>
M_A_DQSP[7:0]<17>
M_B_DQSN[7:0]<18>
M_B_DQSP[7:0]<18>
M_A_DQ[63:0]<17>
M_B_DQ[63:0]<18>
D D
C C
B B
+1.2VSUS <6,17,18,34,36>
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
U11B
AL71
DDR0_DQ[0]
AL68
DDR0_DQ[1]
AN68
DDR0_DQ[2]
AN69
DDR0_DQ[3]
AL70
DDR0_DQ[4]
AL69
DDR0_DQ[5]
AN70
DDR0_DQ[6]
AN71
DDR0_DQ[7]
AR70
DDR0_DQ[8]
AR68
DDR0_DQ[9]
AU71
DDR0_DQ[10]
AU68
DDR0_DQ[11]
AR71
DDR0_DQ[12]
AR69
DDR0_DQ[13]
AU70
DDR0_DQ[14]
AU69
DDR0_DQ[15]
AF65
DDR1_DQ[0]/DDR0_DQ[16]
AF64
DDR1_DQ[1]/DDR0_DQ[17]
AK65
DDR1_DQ[2]/DDR0_DQ[18]
AK64
DDR1_DQ[3]/DDR0_DQ[19]
AF66
DDR1_DQ[4]/DDR0_DQ[20]
AF67
DDR1_DQ[5]/DDR0_DQ[21]
AK67
DDR1_DQ[6]/DDR0_DQ[22]
AK66
DDR1_DQ[7]/DDR0_DQ[23]
AF70
DDR1_DQ[8]/DDR0_DQ[24]
AF68
DDR1_DQ[9]/DDR0_DQ[25]
AH71
DDR1_DQ[10]/DDR0_DQ[26]
AH68
DDR1_DQ[11]/DDR0_DQ[27]
AF71
DDR1_DQ[12]/DDR0_DQ[28]
AF69
DDR1_DQ[13]/DDR0_DQ[29]
AH70
DDR1_DQ[14]/DDR0_DQ[30]
AH69
DDR1_DQ[15]/DDR0_DQ[31]
BB65
DDR0_DQ[16]/DDR0_DQ[32]
AW65
DDR0_DQ[17]/DDR0_DQ[33]
AW63
DDR0_DQ[18]/DDR0_DQ[34]
AY63
DDR0_DQ[19]/DDR0_DQ[35]
BA65
DDR0_DQ[20]/DDR0_DQ[36]
AY65
DDR0_DQ[21]/DDR0_DQ[37]
BA63
DDR0_DQ[22]/DDR0_DQ[38]
BB63
DDR0_DQ[23]/DDR0_DQ[39]
BA61
DDR0_DQ[24]/DDR0_DQ[40]
AW61
DDR0_DQ[25]/DDR0_DQ[41]
BB59
DDR0_DQ[26]/DDR0_DQ[42]
AW59
DDR0_DQ[27]/DDR0_DQ[43]
BB61
DDR0_DQ[28]/DDR0_DQ[44]
AY61
DDR0_DQ[29]/DDR0_DQ[45]
BA59
DDR0_DQ[30]/DDR0_DQ[46]
AY59
DDR0_DQ[31]/DDR0_DQ[47]
AT66
DDR1_DQ[16]/DDR0_DQ[48]
AU66
DDR1_DQ[17]/DDR0_DQ[49]
AP65
DDR1_DQ[18]/DDR0_DQ[50]
AN65
DDR1_DQ[19]/DDR0_DQ[51]
AN66
DDR1_DQ[20]/DDR0_DQ[52]
AP66
DDR1_DQ[21]/DDR0_DQ[53]
AT65
DDR1_DQ[22]/DDR0_DQ[54]
AU65
DDR1_DQ[23]/DDR0_DQ[55]
AT61
DDR1_DQ[24]/DDR0_DQ[56]
AU61
DDR1_DQ[25]/DDR0_DQ[57]
AP60
DDR1_DQ[26]/DDR0_DQ[58]
AN60
DDR1_DQ[27]/DDR0_DQ[59]
AN61
DDR1_DQ[28]/DDR0_DQ[60]
AP61
DDR1_DQ[29]/DDR0_DQ[61]
AT60
DDR1_DQ[30]/DDR0_DQ[62]
AU60
DDR1_DQ[31]/DDR0_DQ[63]
*SKL_ULT
REV = 1
Need apply PN
?
SKL_ULT
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]
DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]
DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]
DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
NIL-DDR CH A
2 OF 20
4
DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]
DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]
DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]
DDR0_ODT[1]
DDR0_MA[3]
DDR0_MA[4]
DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSP[1]
DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR0_ALERT#
DDR0_PAR
DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ
DDR_VTT_CNTL
3
SkyLake ULT Processor (DDR3L)
AU53
AT53
AU55
AT55
BA56
BB56
AW56
AY56
AU45
AU43
AT45
AT43
BA51
BB54
BA52
AY52
AW52
AY55
AW54
BA54
BA55
AY54
AU46
AU48
AT46
AU50
AU52
AY51
AT48
AT50
BB50
AY50
BA50
BB52
AM70
AM69
AT69
AT70
AH66
AH65
AG69
AG70
BA64
AY64
AY60
BA60
AR66
AR65
AR61
AR60
AW50
AT52
AY67
AY68
BA67
AW67
M_A_CKE2
M_A_CKE3
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_B0
M_A_B1
M_A_B2
M_A_B3
M_A_B4
M_A_B5
M_A_B6
M_A_B7
M_A_B8
M_A_B9
M_A_DQSN0
M_A_DQSP0
M_A_DQSN1
M_A_DQSP1
M_A_DQSN2
M_A_DQSP2
M_A_DQSN3
M_A_DQSP3
M_A_DQSN4
M_A_DQSP4
M_A_DQSN5
M_A_DQSP5
M_A_DQSN6
M_A_DQSP6
M_A_DQSN7
M_A_DQSP7
DDR_VTT_CNTL
M_A_CKE2 <17,19>
M_A_CKE3 <17,19>
M_A_A0 <17,19>
M_A_A1 <17,19>
M_A_A2 <17,19>
M_A_A3 <17,19>
M_A_A4 <17,19>
M_A_A5 <17,19>
M_A_A6 <17,19>
M_A_A7 <17,19>
M_A_A8 <17,19>
M_A_A9 <17,19>
M_A_B0 <17,19>
M_A_B1 <17,19>
M_A_B2 <17,19>
M_A_B3 <17,19>
M_A_B4 <17,19>
M_A_B5 <17,19>
M_A_B6 <17,19>
M_A_B7 <17,19>
M_A_B8 <17,19>
M_A_B9 <17,19>
M_A_CLKN0 <17,19>
M_A_CLKP0 <17,19>
M_A_CLKN1 <17,19>
M_A_CLKP1 <17,19>
M_A_CKE0 <17,19>
M_A_CKE1 <17,19>
M_A_CS#0 <17,19>
M_A_CS#1 <17,19>
M_A_ODT0 <17,19>
20mils width
SM_VREF_CA <17>
SM_VREF_DQ0 <17>
SM_VREF_DQ1 <18>
DDR_VTT_CNTL <4,34>
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
U11C
AY39
DDR0_DQ[32]/DDR1_DQ[0]
AW39
DDR0_DQ[33]/DDR1_DQ[1]
AY37
DDR0_DQ[34]/DDR1_DQ[2]
AW37
DDR0_DQ[35]/DDR1_DQ[3]
BB39
DDR0_DQ[36]/DDR1_DQ[4]
BA39
DDR0_DQ[37]/DDR1_DQ[5]
BA37
DDR0_DQ[38]/DDR1_DQ[6]
BB37
DDR0_DQ[39]/DDR1_DQ[7]
AY35
DDR0_DQ[40]/DDR1_DQ[8]
AW35
DDR0_DQ[41]/DDR1_DQ[9]
AY33
DDR0_DQ[42]/DDR1_DQ[10]
AW33
DDR0_DQ[43]/DDR1_DQ[11]
BB35
DDR0_DQ[44]/DDR1_DQ[12]
BA35
DDR0_DQ[45]/DDR1_DQ[13]
BA33
DDR0_DQ[46]/DDR1_DQ[14]
BB33
DDR0_DQ[47]/DDR1_DQ[15]
AU40
DDR1_DQ[32]/DDR1_DQ[16]
AT40
DDR1_DQ[33]/DDR1_DQ[17]
AT37
DDR1_DQ[34]/DDR1_DQ[18]
AU37
DDR1_DQ[35]/DDR1_DQ[19]
AR40
DDR1_DQ[36]/DDR1_DQ[20]
AP40
DDR1_DQ[37]/DDR1_DQ[21]
AP37
DDR1_DQ[38]/DDR1_DQ[22]
AR37
DDR1_DQ[39]/DDR1_DQ[23]
AT33
DDR1_DQ[40]/DDR1_DQ[24]
AU33
DDR1_DQ[41]/DDR1_DQ[25]
AU30
DDR1_DQ[42]/DDR1_DQ[26]
AT30
DDR1_DQ[43]/DDR1_DQ[27]
AR33
DDR1_DQ[44]/DDR1_DQ[28]
AP33
DDR1_DQ[45]/DDR1_DQ[29]
AR30
DDR1_DQ[46]/DDR1_DQ[30]
AP30
DDR1_DQ[47]/DDR1_DQ[31]
AY31
DDR0_DQ[48]/DDR1_DQ[32]
AW31
DDR0_DQ[49]/DDR1_DQ[33]
AY29
DDR0_DQ[50]/DDR1_DQ[34]
AW29
DDR0_DQ[51]/DDR1_DQ[35]
BB31
DDR0_DQ[52]/DDR1_DQ[36]
BA31
DDR0_DQ[53]/DDR1_DQ[37]
BA29
DDR0_DQ[54]/DDR1_DQ[38]
BB29
DDR0_DQ[55]/DDR1_DQ[39]
AY27
DDR0_DQ[56]/DDR1_DQ[40]
AW27
DDR0_DQ[57]/DDR1_DQ[41]
AY25
DDR0_DQ[58]/DDR1_DQ[42]
AW25
DDR0_DQ[59]/DDR1_DQ[43]
BB27
DDR0_DQ[60]/DDR1_DQ[44]
BA27
DDR0_DQ[61]/DDR1_DQ[45]
BA25
DDR0_DQ[62]/DDR1_DQ[46]
BB25
DDR0_DQ[63]/DDR1_DQ[47]
AU27
DDR1_DQ[48]
AT27
DDR1_DQ[49]
AT25
DDR1_DQ[50]
AU25
DDR1_DQ[51]
AP27
DDR1_DQ[52]
AN27
DDR1_DQ[53]
AN25
DDR1_DQ[54]
AP25
DDR1_DQ[55]
AT22
DDR1_DQ[56]
AU22
DDR1_DQ[57]
AU21
DDR1_DQ[58]
AT21
DDR1_DQ[59]
AN22
DDR1_DQ[60]
AP22
DDR1_DQ[61]
AP21
DDR1_DQ[62]
AN21
DDR1_DQ[63]
*SKL_ULT
REV = 1
2
?
SKL_ULT
Need apply PN
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
NIL-DDR CH B
3 OF 20
DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]
DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]
DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]
DDR1_ODT[1]
DDR1_MA[3]
DDR1_MA[4]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSP[5]/DDR1_DQSP[3]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSP[7]/DDR1_DQSP[5]
DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]
DDR1_ALERT#
DDR1_PAR
DRAM_RESET#
DDR_RCOMP[0]
DDR_RCOMP[1]
DDR_RCOMP[2]
PDC
AN45
AN46
AP45
AP46
AN56
AP55
AN55
AP53
BB42
AY42
BA42
AW42
AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52
BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47
BA38
AY38
AY34
BA34
AT38
AR38
AT32
AR32
BA30
AY30
AY26
BA26
AR25
AR27
AR22
AR21
AN43
AP43
AT13
AR18
AT18
AU18
M_B_CKE2
M_B_CKE3
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_B0
M_B_B1
M_B_B2
M_B_B3
M_B_B4
M_B_B5
M_B_B6
M_B_B7
M_B_B8
M_B_B9
M_B_DQSN0
M_B_DQSP0
M_B_DQSN1
M_B_DQSP1
M_B_DQSN2
M_B_DQSP2
M_B_DQSN3
M_B_DQSP3
M_B_DQSN4
M_B_DQSP4
M_B_DQSN5
M_B_DQSP5
M_B_DQSN6
M_B_DQSP6
M_B_DQSN7
M_B_DQSP7
SM_DRAMRST#
M_B_CLKN0 <18,19>
M_B_CLKN1 <18,19>
M_B_CLKP0 <18,19>
M_B_CLKP1 <18,19>
M_B_CKE0 <18,19>
M_B_CKE1 <18,19>
M_B_CKE2 <18,19>
M_B_CKE3 <18,19>
M_B_CS#0 <18,19>
M_B_CS#1 <18,19>
M_B_ODT0 <18,19>
M_B_A0 <18,19>
M_B_A1 <18,19>
M_B_A2 <18,19>
M_B_A3 <18,19>
M_B_A4 <18,19>
M_B_A5 <18,19>
M_B_A6 <18,19>
M_B_A7 <18,19>
M_B_A8 <18,19>
M_B_A9 <18,19>
M_B_B0 <18,19>
M_B_B1 <18,19>
M_B_B2 <18,19>
M_B_B3 <18,19>
M_B_B4 <18,19>
M_B_B5 <18,19>
M_B_B6 <18,19>
M_B_B7 <18,19>
M_B_B8 <18,19>
M_B_B9 <18,19>
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
1
+1.2VSUS
R65 200/F_2
R66 80.6/F_2
R64 162/F_2
03
R69
0_2
PV
A A
PROJECT : Y0DD
PROJECT : Y0DD
PROJECT : Y0DD
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
SKL U (2/14)
SKL U (2/14)
NB5
NB5
5
4
3
2
NB5
SKL U (2/14)
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
3 41Tuesday, May 26, 2015
3 41Tuesday, May 26, 2015
3 41Tuesday, May 26, 2015
1A
1A
1A
I'm from VIETNAM sualaptop365
5
+3V_DEEP_SUS<10,11,12,14,15,16>
+3V<2,10,11,12,13,14,15,16,20,21,22,23,25,26,27,29,30,31,37,38>
+3VS5<15,16,22,28,30,31,33,35,36,37>
+VCCSTPLL<2,5,6,9,36,38>
+1.0V<2,6,16,30,36>
+3V_RTC<13,15,27,31,32>
D D
RSMRST#<30>
SI
R4120_4
EC26
*220P/50V_4
SYS_RESET#<16>
R161 *10K_2
SYS_PWROK<16>
EC_PWROK<16,30>
SUSWARN#_EC<30>
PCIE_WAKE#<26,28,30>
RF_OFF_PCH<28>
DDR_VTT_CNTL<3,34>
C229 *0.1U/10V_2
R410 *0_2/S
SI
4
PLTRST#
SYS_RESET#
RSMRST#
PROCPWRGD
H_VCCST_PWRGD
SYS_PWROK
PCH_PWROK
DSWROK_EC_R
SUSWARN#
SUSACK#SUSWARN#
PCIE_WAKE#
RF_OFF_PCH
U11K
SYSTEM POWER MANAGEMENT
AN10
GPP_B13/PLTRST#
B5
SYS_RESET#
AY17
RSMRST#
A68
PROCPWRGD
B65
VCCST_PWRGD
B6
SYS_PWROK
BA20
PCH_PWROK
BB20
DSW_PW ROK
AR13
GPP_A13/SUSW ARN#/SUSPWRDNACK
AP11
GPP_A15/SUSACK#
BB15
WAKE#
AM15
GPD2/LAN_WAKE#
AW17
GPD11/LANPHYPC
AT15
GPD7/RSVD
*SKL_ULT
REV = 1
SKL_ULT
?
11 OF 20
3
Need apply PN
GPP_B12/SLP_S0#
GPD4/SLP_S3#
GPD5/SLP_S4#
GPD10/SLP_S5#
GPD9/SLP_WLAN#
GPD6/SLP_A#
GPD3/PWRBTN#
GPD1/ACPRESENT
GPD0/BATLOW #
GPP_A11/PME#
GPP_B11/EXT_PW R_GATE#
INTRUDER#
GPP_B2/VRALERT#
SLP_SUS#
SLP_LAN#
2
1
04
AT11
PCH_SLP_S0_N
AP15
BA16
AY16
AN15
SLP_SUS#_EC
AW15
BB17
PCH_SLP_WLAN#
AN16
BA15
DNBSWON#
AY15
AC_PRESENT_EC
AU13
BATLOW#
AU11
AP16
INTRUDER#_R
AM10
AM11
GPP_B2
?
TP21
PCH_SLP_S0_N <16,36>
SUSB# <16,30>
SUSC# <16,30>
SLP_S5# <16>
SLP_SUS#_EC <30>
PCH_SLP_WLAN# <30>
SLP_A# <16,30>
DNBSWON# <30>
AC_PRESENT_EC <30>
R621M_2
+3V_RTC
PCH Pull-high/low(CLG)
SUSWARN#
SUSACK#
BATLOW#
PCIE_WAKE#
AC_PRESENT_EC
SYS_RESET#
RSMRST#
DSWROK_EC_R
R409 *10K/F_4
R413 *10K/F_4
R59 10K_2
R391 1K_2
R387 *10K_2
R169 10K_2
R411 10K_2
R384 100K_2
+3V_DEEP_SUS
PV
+3VS5
+3V
C C
For DS3 Sequence
For DS3 -->Ra
Non-DS3 -->Rb
RSMRST#
DPWROK_EC<30>
PLTRST#(CLG)
Check Q2010 Rise/Fall time less than 100ns
R60
B B
100K_2
Rb
R382 *0_2
R376 0_2
Ra
PLTRST# <16,26,28,30>
SI
C558
0.1U/25V_4
DSWROK_EC_R
+1.0V
HWPG<16,30,33,34,35,37>
D2 RB501V-40
21
R10479 close to CPU side
H_VCCST_PWRGD trace 0.3" - 1.5"
1218 Reserve
+VCCSTPLL and R523
+VCCSTPLL
R127
1K_2
H_VCCST_PWRGD_R
C164
*10P/50V_4
R134
*1K_2
R128 60.4_4
H_VCCST_PWRGD
System PWR_OK(CLG)
R170 *0_2/S
A A
EC_PWROKSYS_PWROK
R156
10K/F_2
+1.0V +3VS5+5VS5
R440
15K/F_4
+1.0V_PWRGD_G1
C458
0.1U/10V_2
R437
100K_2
2
R425
100K_2
+1.0V_PWRGD_G2
Q23
METR3904-G
1 3
R423
10K_2
3
2
Q24
2N7002K
1
1110 Add Citcuit for +1.0V Power Good
1118 Change Change Q7062 P/N from BA051440000 to
BA039040020, Del D7002,D7003, R10526, R10527
R426
100K_4
HWPG
5
4
I'm from VIETNAM sualaptop365
PROJECT : Y0DD
PROJECT : Y0DD
PROJECT : Y0DD
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
NB5
NB5
NB5
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
SKL U (3/14)
SKL U (3/14)
SKL U (3/14)
1
4 41Tuesday, May 26, 2015
4 41Tuesday, May 26, 2015
4 41Tuesday, May 26, 2015
1A
1A
1A
5
+VCC_CORE<39>
+1.0V<2,4,6,16,30,36>
+VCCSTG<6>
+VCCSTPLL<2,4,6,9,36,38>
C174
C219
10U/6.3V_4
C172
22U/6.3V_6
R145 *0_4C28
VID0_VCC_EDRAM<41>
VID1_VCC_EDRAM<41>
C47
*1uF/6.3_2
C193
22U/6.3V_6
C158
10U/6.3V_4
C154
22U/6.3V_6
C24
*1uF/6.3_2
TP28
TP24
22U/6.3V_6
C36
*1uF/6.3_2
C187
C225
10U/6.3V_4
+V1.8S_EDRAM
10U/6.3V_4
C150
22U/6.3V_6
C152
22U/6.3V_6
C149
10U/6.3V_4
C134
22U/6.3V_6
C3
*1uF/6.3_2
C42
*1uF/6.3_2
C23
*1uF/6.3_2
+1.8V
22U/6.3V_6
C198
*1uF/6.3_2
C44
*1uF/6.3_2
C30
*1uF/6.3_2
C141
C221
10U/6.3V_4
C148
22U/6.3V_6
22U/6.3V_6
C1
*1uF/6.3_2
C160
22U/6.3V_6
+VCC_EDRAM
*1uF/6.3_2
10U/6.3V_6
C224
10U/6.3V_4
C175
22U/6.3V_6
+VCC_EDRAM
C25
*1uF/6.3_2
C2
*1uF/6.3_2
C29
*1uF/6.3_2
D D
+VCC_EOPIO
C C
4
C151
22U/6.3V_6
3A
50mA
VID0_VCC_EDRAM
VID1_VCC_EDRAM
3A
VID0_VCC_EOPIO
VID1_VCC_EOPIO
3
?
SKL_ULT
CPU POWER 1 OF 4
12 OF 20
Need apply PN
VCC_G32
VCC_G33
VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42
VCC_J30
VCC_J33
VCC_J37
VCC_J40
VCC_K33
VCC_K35
VCC_K37
VCC_K38
VCC_K40
VCC_K42
VCC_K43
VCC_SENSE
VSS_SENSE
VIDALERT#
VIDSCK
VIDSOUT
VCCSTG_G20
PDC
?
G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43
E32
E33
B63
H_CPU_SVIDALRT#
A63
VR_SVID_CLK_R
D64
H_CPU_SVIDDAT
G20
AK33
AK35
AK37
AK38
AK40
AL33
AL37
AL40
AM32
AM33
AM35
AM37
AM38
G30
K32
AK32
AB62
P62
V62
H63
G61
AC63
AE63
AE62
AG62
AL63
AJ62
A30
A34
A39
A44
U11L
VCC_A30
VCC_A34
28A
VCC_A39
VCC_A44
VCC_AK33
VCC_AK35
VCC_AK37
VCC_AK38
VCC_AK40
VCC_AL33
VCC_AL37
VCC_AL40
VCC_AM32
VCC_AM33
VCC_AM35
VCC_AM37
VCC_AM38
VCC_G30
RSVD_K32
RSVD_AK32
VCCOPC_AB62
VCCOPC_P62
VCCOPC_V62
VCC_OPC_1P8_H63
VCC_OPC_1P8_G61
VCCOPC_SENSE
VSSOPC_SENSE
VCCEOPIO
VCCEOPIO
VCCEOPIO_SENSE
VSSEOPIO_SENSE
*SKL_ULT
REV = 1
+VCC_CORE +VCC_CORE
Close U9052
+VCC_CORE
C188
C153
22U/6.3V_6
+VCC_CORE
C186
22U/6.3V_6
C192
22U/6.3V_6
C156
22U/6.3V_6
22U/6.3V_6
C64
1uF/6.3_2
C53
1uF/6.3_2
C133
22U/6.3V_6
C16
1uF/6.3_2
C18
1uF/6.3_2
R50 100/F_2
R49 100/F_2
+VCCSTG
C162
22U/6.3V_6
2
C65
1uF/6.3_2C143
C17
1uF/6.3_2
100- ±1%
pull-up to VCC
near processor.
C55
1uF/6.3_2
C33
1uF/6.3_2
+VCC_CORE
VCC_SENSE <38>
VSS_SENSE <38>
C19
1uF/6.3_2
C13
1uF/6.3_2C218
C14
1uF/6.3_2
C39
1uF/6.3_2
C15
1uF/6.3_2
C63
1uF/6.3_2
C54
1uF/6.3_2
Layout note: need routing together and ALERT need between CLK and DATA.
+VCCSTPLL
CLOSE TO CPU
PLACE THE PU RESISTORS
C163
22U/6.3V_6
H_CPU_SVIDALRT#
1119 Update R10372 P/N to
CS12202FB06
R178 220/F_4
R167
56.2/F_4
C234
*0.1U/10V_2
SVID ALERT
1
05
VR_SVID_ALERT# <38>
R181
100/F_2
+VCCSTPLL
1014 Change to empty
R157
*54.9/F_4
SVID CLK
VR_SVID_CLK <38>
R175 0_2
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
NB5
NB5
NB5
Date: Sheet of
Date: Sheet of
Date: Sheet of
SVID DATA
VR_SVID_DATA <38>
PROJECT : Y0DD
PROJECT : Y0DD
PROJECT : Y0DD
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
SKL U (4/14)
SKL U (4/14)
SKL U (4/14)
1
1A
1A
5 41Tuesday, May 26, 2015
5 41Tuesday, May 26, 2015
5 41Tuesday, May 26, 2015
1A
C223
B B
A A
5
4
10U/6.3V_4
C222
10U/6.3V_4
C217
10U/6.3V_4
C171
10U/6.3V_4
C220
10U/6.3V_4
3
C159
10U/6.3V_4
C191
10U/6.3V_4
C199
10U/6.3V_4
PLACE THE PU RESISTORS
CLOSE TO VR
PULL UP IS IN THE VR MODULE
CLOSE TO CPU
PLACE THE PU RESISTORS
VR_SVID_CLK_R
H_CPU_SVIDDAT
2
R174 0_2
+VCCSTPLL
I'm from VIETNAM sualaptop365
5
+VCCSTPLL <2,4,5,9,36,38>
+VCCSA <38,39>
+1.2VSUS <3,17,18,34,36>
+1.0V_DEEP_SUS <9,13,15,16,35,36>
+1.0V <2,4,16,30,36>
+3VPCU <13,15,27,28,30,31,32,33,41>
+1.2V_VCCPLL_OC <36>
+1.2VSUS
D D
10U/6.3V_4
C C
C422
+1.0V
+1.2V_VCCPLL_OC
C416
10U/6.3V_4
C409
10U/6.3V_4
+VCCSTPLL
10U/6.3V_4
10U/6.3V_4
C404
C428
R1300_4
R129*0_4
PV
C71
1uF/6.3_2
C407
10U/6.3V_4
C74
1uF/6.3_2
1uF/6.3_2
C397
*10U/6.3V_4
+VCCSTG
Close U11 Under U11
+VCCPLL_OC+1.2VSUS
R544*0_2
R5790_4
C76
C77
1uF/6.3_2
C73
1U/6.3V_2
+VCCSTPLL
+VCCSTG
+VCCPLL_OC
+VCCPLL
4
120mA
3
2
1
06
Need apply PN
?
SKL_ULT
U11N
CPU POWER 3 OF 4
AU23
VDDQ_AU23
AU28
VDDQ_AU28
AU35
VDDQ_AU35
AU42
VDDQ_AU42
BB23
VDDQ_BB23
BB32
VDDQ_BB32
BB41
VDDQ_BB41
BB47
VDDQ_BB47
BB51
VDDQ_BB51
AM40
VDDQC
A18
0.12A
VCCST
A22
VCCSTG_A22
AL23
VCCPLL_OC
K20
VCCPLL_K20
K21
VCCPLL_K21
+VCCPLL+VCCSTPLL
*SKL_ULT
REV = 1
2A
0.04A
0.12A
14 OF 20
3.1A
5A
VCCIO_SENSE
VSSIO_SENSE
VSSSA_SENSE
VCCSA_SENSE
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
AK28
AK30
AL30
AL42
AM28
AM30
AM42
AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30
AM23
AM22
H21
H20
C50
1uF/6.3_2
+VCCSA
C38
1uF/6.3_2
VCCIO_VCCSENSE
VCCIO_VSSSENSE
C51
1uF/6.3_2
C9
1uF/6.3_2
C212
10U/6.3V_4
C226
C52
10U/6.3V_4
1uF/6.3_2
C37
C27
1uF/6.3_2
1U/6.3V_2
C168
C170
10U/6.3V_4
10U/6.3V_4
VSSSA_SENSE <38>
VCCSA_SENSE <38>
C247
10U/6.3V_4
C66
1U/6.3V_2
C173
10U/6.3V_4
C239
10U/6.3V_4
C31
1U/6.3V_2
C213
10U/6.3V_4
VCCIO_VCCSENSE
VCCIO_VSSSENSE
C58
1uF/6.3_2
C21
1uF/6.3_2
C232
10U/6.3V_4
C49
1uF/6.3_2
C169
10U/6.3V_4
R57 100/F_2
R56 100/F_2
C48
1uF/6.3_2
C189
10U/6.3V_4
+VCCIO
C57
1uF/6.3_2
C196
10U/6.3V_4
+VCCIO
C190
10U/6.3V_4
C195
10U/6.3V_4
C157
10U/6.3V_4
C231
10U/6.3V_4
Under U11 Close U11
+VCCSTG +VCCPLL_OC +VCCPLL
C10
1U/6.3V_2
C72
1uF/6.3_2
C227
1U/6.3V_2
+VCCSTPLL
C194
1uF/6.3_2
+3VPCU
IO Thrm Protect
For 65 degree, 1.8v limit, (SW)
Close A18 Ball
+VCCSTPLL
PV
R137
20K/F_4
For 75 degree, 1.2v limit, (HW)
C238
B B
A A
*1U/6.3V_2
C197
*22U/6.3V_6
THER_CPU
R138
100K_4 NTC
+1.2VSUS
C421
10U/6.3V_6
5
4
C415
10U/6.3V_6
10U/6.3V_6
C178
0.1U/10V_4
1 2
3
C398
THRM_MOINTOR1 <30>
C406
10U/6.3V_6
10U/6.3V_6
C429
C408
10U/6.3V_6
Close to CPU
C70
1uF/6.3_2
1uF/6.3_2
C69
C75
1uF/6.3_2
2
C67
1uF/6.3_2
PROJECT : Y0DD
PROJECT : Y0DD
PROJECT : Y0DD
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
NB5
NB5
NB5
Date: Sheet of
Date: Sheet of
Date: Sheet of
SKL U (5/14)
SKL U (5/14)
SKL U (5/14)
1
1A
1A
6 41Tuesday, May 26, 2015
6 41Tuesday, May 26, 2015
6 41Tuesday, May 26, 2015
1A
I'm from VIETNAM sualaptop365
5
+VCCGT <38,40>
D D
C C
B B
C400
22U/6.3V_6
C419
10U/6.3V_4
C11
1uF/6.3_2
C20
1uF/6.3_2
C401
22U/6.3V_6
C399
10U/6.3V_4
C413
22U/6.3V_6
C347
10U/6.3V_4
1uF/6.3_2
VCCGT_SENSE<38>
VSSGT_SENSE<38>
4
C402
22U/6.3V_6
C273
10U/6.3V_4
C7
1uF/6.3_2
C414
22U/6.3V_6
C430
10U/6.3V_4
C12
1uF/6.3_2
+VCCGT
AA63
AA64
AA66
AA67
AA69
AA70
AA71
AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71
M62
N63
N64
N66
N67
N69
A48
A53
A58
A62
A66
J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60
K48
K50
K52
K53
K55
K56
K58
K60
L62
L63
L64
L65
L66
L67
L68
L69
L70
L71
J70
J69
SKL_ULT
U11M
CPU POWER 2 OF 4
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT_SENSE
VSSGT_SENSE
*SKL_ULT
REV = 1
57A
PDC
13 OF 20
?
Need apply PN
VCCGTX_AK42
VCCGTX_AK43
VCCGTX_AK45
VCCGTX_AK46
VCCGTX_AK48
VCCGTX_AK50
VCCGTX_AK52
VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60
VCCGTX_AK70
VCCGTX_AL43
VCCGTX_AL46
VCCGTX_AL50
VCCGTX_AL53
VCCGTX_AL56
VCCGTX_AL60
VCCGTX_AM48
VCCGTX_AM50
VCCGTX_AM52
VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58
VCCGTX_AU58
VCCGTX_AU63
VCCGTX_BB57
VCCGTX_BB66
VCCGTX_SENSE
VSSGTX_SENSE
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
3
+VCCGT
N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62
AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66
AK62
AL61
+VCC_GTX
C393
*22U/6.3V_6
C364
22U/6.3V_6
C403
22U/6.3V_6
C288
22U/6.3V_6
C411
22U/6.3V_6
C424
22U/6.3V_6
C384
22U/6.3V_6
C358
22U/6.3V_6
C309
22U/6.3V_6
C359
22U/6.3V_6
7A
C395
C388
*22U/6.3V_6
+VCC_GTX +VCCGT
*22U/6.3V_6
C390
*22U/6.3V_6C6
R383 *0_8
R373 *0_8
2
C363
22U/6.3V_6
C380
22U/6.3V_6
C425
22U/6.3V_6
Close U11
C394
*22U/6.3V_6
C427
22U/6.3V_6
C426
22U/6.3V_6
C389
22U/6.3V_6
C271
22U/6.3V_6
C412
22U/6.3V_6
C379
22U/6.3V_6
1
07
A A
PROJECT : Y0DD
PROJECT : Y0DD
PROJECT : Y0DD
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
NB5
NB5
NB5
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
SKL U (6/14)
SKL U (6/14)
SKL U (6/14)
1
7 41Tuesday, May 26, 2015
7 41Tuesday, May 26, 2015
7 41Tuesday, May 26, 2015
1A
1A
1A
I'm from VIETNAM sualaptop365
5
4
3
2
1
08
AT63
AT68
AT71
AU10
AU15
AU20
AU32
AU38
AV68
AV69
AV70
AV71
AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57
AW6
AW60
AW62
AW64
AW66
AW8
AY66
BA10
BA14
BA18
BA23
BA28
BA32
BA36
BA45
U11Q
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AV1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B10
VSS
B14
VSS
B18
VSS
B22
VSS
B30
VSS
B34
VSS
B39
VSS
B44
VSS
B48
VSS
B53
VSS
B58
VSS
B62
VSS
B66
VSS
B71
VSS
BA1
VSS
VSS
VSS
VSS
BA2
VSS
VSS
VSS
VSS
VSS
F68
VSS
VSS
*SKL_ULT
REV = 1
SKL_ULT
GND 2 OF 3
?
17 OF 20
Need apply PNNeed apply PN
BA49
VSS
BA53
VSS
BA57
VSS
BA6
VSS
BA62
VSS
BA66
VSS
BA71
VSS
BB18
VSS
BB26
VSS
BB30
VSS
BB34
VSS
BB38
VSS
BB43
VSS
BB55
VSS
BB6
VSS
BB60
VSS
BB64
VSS
BB67
VSS
BB70
VSS
C1
VSS
C25
VSS
C5
VSS
D10
VSS
D11
VSS
D14
VSS
D18
VSS
D22
VSS
D25
VSS
D26
VSS
D30
VSS
D34
VSS
D39
VSS
D44
VSS
D45
VSS
D47
VSS
D48
VSS
D53
VSS
D58
VSS
D6
VSS
D62
VSS
D66
VSS
D69
VSS
E11
VSS
E15
VSS
E18
VSS
E21
VSS
E46
VSS
E50
VSS
E53
VSS
E56
VSS
E6
VSS
E65
VSS
E71
VSS
F1
VSS
F13
VSS
F2
VSS
F22
VSS
F23
VSS
F27
VSS
F28
VSS
F32
VSS
F33
VSS
F35
VSS
F37
VSS
F38
VSS
F4
VSS
F40
VSS
F42
VSS
BA41
VSS
PDC
?
AA65
AA68
AB15
AB16
AB18
AB21
AD13
AD16
AD19
AD20
AD21
AD62
AE64
AE65
AE66
AE67
AE68
AE69
AF10
AF15
AF17
AF63
AG16
AG17
AG18
AG19
AG20
AG21
AG71
AH13
AH63
AH64
AH67
AJ15
AJ18
AJ20
AK11
AK16
AK18
AK21
AK22
AK27
AK63
AK68
AK69
AL28
AL32
AL35
AL38
AL45
AL48
AL52
AL55
AL58
AL64
A67
A70
AA2
AA4
AB8
AD8
AF1
AF2
AF4
AH6
AJ4
AK8
AL2
AL4
U11P
A5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
*SKL_ULT
REV = 1
SKL_ULT
GND 1 OF 3
Need apply PN
?
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
16 OF 20
?
AL65
AL66
AM13
AM21
AM25
AM27
AM43
AM45
AM46
AM55
AM60
AM61
AM68
AM71
AM8
AN20
AN23
AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48
AR5
AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58
U11R
?
D D
C C
B B
SKL_ULT
GND 3 OF 3
F8
VSS
G10
VSS
G22
VSS
G43
VSS
G45
VSS
G48
VSS
G5
VSS
G52
VSS
G55
VSS
G58
VSS
G6
VSS
G60
VSS
G63
VSS
G66
VSS
H15
VSS
H18
VSS
H71
VSS
J11
VSS
J13
VSS
J25
VSS
J28
VSS
J32
VSS
J35
VSS
J38
VSS
J42
VSS
J8
VSS
K16
VSS
K18
VSS
K22
VSS
K61
VSS
K63
VSS
K64
VSS
K65
VSS
K66
VSS
K67
VSS
K68
VSS
K70
VSS
K71
VSS
L11
VSS
L16
VSS
L17
VSS
18 OF 20
*SKL_ULT
REV = 1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21
?
A A
PROJECT : Y0DD
PROJECT : Y0DD
PROJECT : Y0DD
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
NB5
NB5
NB5
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
SKL U (7/14)
SKL U (7/14)
SKL U (7/14)
1
8 41Tuesday, May 26, 2015
8 41Tuesday, May 26, 2015
8 41Tuesday, May 26, 2015
1A
1A
1A
I'm from VIETNAM sualaptop365
5
4
3
2
1
09
?
U11S
CFG0-19 need Reserve TP
D D
+1.0V_DEEP_SUS
C C
CFG0<16>
CFG1<16>
CFG2<16>
CFG3<16>
CFG4<16>
CFG5<16>
CFG6<16>
CFG7<16>
CFG8<16>
CFG9<16>
CFG10<16>
CFG11<16>
CFG12<16>
CFG13<16>
CFG14<16>
CFG15<16>
CFG16<16>
CFG17<16>
CFG18<16>
CFG19<16>
R46 49.9/F_2
R183 *1K_2
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG_RCOMP
G69
G68
G71
G70
AY2
AY1
AL25
AL27
BA70
BA68
G65
E68
B67
D65
D67
E70
C68
D68
C67
F71
F70
H70
H69
E63
F63
E66
F66
E60
E8
D1
D3
K46
K45
C71
B70
F60
A52
J71
J68
F65
F61
E61
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
CFG[18]
CFG[19]
CFG_RCOMP
ITP_PMODE
RSVD_AY2
RSVD_AY1
RSVD_D1
RSVD_D3
RSVD_K46
RSVD_K45
RSVD_AL25
RSVD_AL27
RSVD_C71
RSVD_B70
RSVD_F60
RSVD_A52
RSVD_TP_BA70
RSVD_TP_BA68
RSVD_J71
RSVD_J68
VSS_F65
VSS_G65
RSVD_F61
RSVD_E61
SKL_ULT
RESERVED SIGNALS-1
PDC
B B
*SKL_ULT
REV = 1
19 OF 20
Need apply PN
RSVD_TP_BB68
RSVD_TP_BB69
RSVD_TP_AK13
RSVD_TP_AK12
RSVD_BB2
RSVD_BA3
RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2
RSVD_B3
RSVD_A3
RSVD_AW1
RSVD_E1
RSVD_E2
RSVD_BA4
RSVD_BB4
RSVD_A4
RSVD_C4
RSVD_A69
RSVD_B69
RSVD_AY3
RSVD_D71
RSVD_C70
RSVD_C54
RSVD_D54
VSS_AY71
RSVD_TP_AW71
RSVD_TP_AW70
PROC_SELECT#
ZVM#
MSM#
TP5
TP6
TP4
TP1
TP2
?
BB68
BB69
AK13
AK12
BB2
BA3
AU5
AT5
D5
D4
B2
C2
B3
A3
AW1
E1
E2
BA4
BB4
A4
C4
BB5
A69
B69
AY3
R375 *0_2/S
D71
C70
C54
D54
AY4
BB3
AY71
R385 *0_2/S
AR56
AW71
AW70
AP56
C64
R159 *100K_2
0112 unmount
+1.8V_DEEP_SUS
SI
+VCCSTPLL
R556 *0_2
C559
*1uF/6.3_2
AW69
AW68
AU56
AW48
C7
U12
U11
H11
U11T
RSVD_AW69
RSVD_AW68
RSVD_AU56
RSVD_AW48
RSVD_C7
RSVD_U12
RSVD_U11
RSVD_H11
*SKL_ULT
REV = 1
SKL_ULT
?
SPARE
20 OF 20
Need apply PN
F6
RSVD_F6
E3
RSVD_E3
C11
RSVD_C11
B11
RSVD_B11
A11
RSVD_A11
D12
RSVD_D12
C12
RSVD_C12
F52
RSVD_F52
?
Processor Strapping
CFG3
(Physcial Debug Enable)
DFX Privacy
CFG4
(DP Presence Strap)
A A
5
The CFG signals have a default value of '1' if not terminated on the board.
1 0
Disable: Enable: Set DFX Enable in DFX interface MSR
Disable; No physical DP attached to eDP
4
Enable; An ext DP device is connected to eDP
3
CFG3
CFG4
Circuit
R143 *1K_2
R42 *1K_2
PROJECT : Y0DD
PROJECT : Y0DD
PROJECT : Y0DD
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
NB5
NB5
NB5
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
SKL U (8/14)
SKL U (8/14)
SKL U (8/14)
1
9 41Tuesday, May 26, 2015
9 41Tuesday, May 26, 2015
9 41Tuesday, May 26, 2015
1A
1A
1A
I'm from VIETNAM sualaptop365
5
+3V_DEEP_SUS <4,11,12,14,15,16>
+3V <2,4,11,12,13,14,15,16,20,21,22,23,25,26,27,29,30,31,37,38>
+5V <22,23,24,27,37,38>
+1.0V <2,4,6,16,30,36>
+3VS5 <4,15,16,22,28,30,31,33,35,36,37>
D D
C C
4
3
2
1
10
?
U11E
SPI - FLASH
PCH_SPI1_CLK
PCH_SPI1_SO
PCH_SPI1_SI
PCH_SPI_IO2
PCH_SPI_IO3
PCH_SPI_CS0#
Support Vpro
CL_CLK<28>
CL_DAT<28>
CL_RST#<28>
SERIRQ<26,30>
GPP_D1
SIO_EXT_SMI#
PCI_SERR#
GPP_D21
GPP_D22
GPP_D0
GPP_D1<21>
SIO_EXT_SMI#<30>
PCI_SERR#<30>
GPP_D21<24>
GPP_D22<24>
GPP_D0<24>
EC_RCIN#<30>
AW3
AW2
AW13
AY11
AV2
AV3
AU4
AU3
AU2
AU1
M2
M3
J4
V1
V2
M1
G3
G2
G1
SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_IO2
SPI0_IO3
SPI0_CS0#
SPI0_CS1#
SPI0_CS2#
SPI - TOUCH
GPP_D1/SPI1_CLK
GPP_D2/SPI1_MISO
GPP_D3/SPI1_MOSI
GPP_D21/SPI1_IO2
GPP_D22/SPI1_IO3
GPP_D0/SPI1_CS#
C LINK
CL_CLK
CL_DATA
CL_RST#
GPP_A0/RCIN#
GPP_A6/SERIRQ
*SKL_ULT
REV = 1
SKL_ULT
LPC
PDC
5 OF 20
Need apply PN
SMBUS, SMLINK
GPP_A14/SUS_STAT#/ESPI_RESET#
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C2/SMBALERT#
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C5/SML0ALERT#
GPP_C6/SML1CLK
GPP_C7/SML1DATA
GPP_B23/SML1ALERT#/PCHHOT#
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
GPP_A5/LFRAME#/ESPI_CS#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
GPP_A10/CLKOUT_LPC1
GPP_A8/CLKRUN#
?
R7
R8
R10
R9
W2
W1
W3
V3
AM7
AY13
BA13
BB13
AY12
BA12
BA11
AW9
AY9
AW11
SMB_PCH_CLK
SMB_PCH_DAT
SML0ALERT#
SMB_ME0_CLK
SMB_ME0_DAT
SML1ALERT#
SMB_ME1_CLK
SMB_ME1_DAT
GPP_B23
CLK_PCI_EC_R
CLK_PCI_LPC_R
CLKRUN#
SML0ALERT# <11>
SML1ALERT# <11>
TP15
LAD0 <26,28,30>
LAD1 <26,28,30>
LAD2 <26,28,30>
LAD3 <26,28,30>
LFRAME# <26,28,30>
R408 22/F_4
CLKRUN# <30>
R404 22/F_4
R405 22/F_4
EC25 18P/50V_4
EC24 18P/50V_4
EC23
18P/50V_4
CLK_24M_KBC <30>
CLK_24M_DEBUG <28>
EMI(near PCH)
CLK_PCI_TPM <26>
EMI(near PCH)
GPIO Pull UP
+3V +3V_DEEP_SUS
SERIRQ
CLKRUN#
SIO_EXT_SMI#
EC_RCIN#
PCI_SERR#
B B
R377 10K_2
R380 8.2K/F_4
R205 10K_2
R378 10K_2
R202 10K_2
SMBus/Pull-up(CLG)
SI 2
DEL Q20
A A
R356 4.7K_2
+3V
SMB_RUN_DAT<16,27>
R364 4.7K_2
+3V
SMB_RUN_CLK<16,27>
I'm from VIETNAM sualaptop365
5
Q21
4 3
1
2N7002KDW
+3V
5
2
6
ACC_LED#<12>
SMB_PCH_DAT
SMB_PCH_CLK
SMB_PCH_CLK
SMB_PCH_DAT
SMB_ME0_CLK
SMB_ME0_DAT
SMB_ME1_CLK
SMB_ME1_DAT
Touch Pad
XDP
LPDDR3 thermal sensor
4
R360 2.2K_2
R366 2.2K_2
R232 499/F_4
R257 499/F_4
R341 1K_2
R333 1K_2
R173 10K_2
SI
PCH SPI ROM(CLG)
Vender P/N
EON
Winbond
GigaDevice
Socket
TP66-71 need place to TOP
3
Size
8MB
8MB
TP65
TP68
TP71
TP67
TP70
TP66
R457/R453/R450/R451/R546/R548 close to U15 pin
C376 1U/10V_4
AKE3EZN0Q01 (EN25QH64-104HIP)8MB
AKE3EFP0N07 (W25Q64FVSSIQ)
AKE3EGN0Q01 (GD25B64BSIGR)
DFHS08FS023
U23&U24 footprint
PCH_SPI_CS0#_R
PCH_SPI1_CLK_R
PCH_SPI1_SI_R
PCH_SPI1_SO_R
BIOS_WP#
HOLD#
R340 15/F_4
R361 15/F_4
R367 15/F_4
R354 15/F_4
PCH_SPI_CS0#_R
PCH_SPI1_CLK_R
PCH_SPI1_SI_RPCH_SPI1_SI
PCH_SPI1_SO_RPCH_SPI1_SO
C373
22P/50V_4
PCH_SPI_CS0#
PCH_SPI1_CLK
+3VSPI
PCH_SPI_IO2
R359 1K_4
R365 15/F_4
PCH_SPI_CS0#_R<30>
PCH_SPI1_CLK_R<30>
PCH_SPI1_SI_R<30>
PCH_SPI1_SO_R<30>
PCH SPI ROM(CLG)
+3V_M
U17
1
CE#
VDD
6
SCK
5
SI
2
SO
HOLD#
3
WP#
VSS
GD25B64BSIGR
AKE3EFP0N07
BIOS_WP#
2
4M SPI ROM Socket
PCH_SPI_CS0#_R
PCH_SPI1_CLK_R
PCH_SPI1_SI_R
PCH_SPI1_SO_R
BIOS_WP#
8
+3VSPI
R343 1K_4
7
HOLD#
R342 15/F_4
4
C346
0.1U/10V_4
PCH_SPI_IO3
PROJECT : Y0DD
PROJECT : Y0DD
PROJECT : Y0DD
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
NB5
NB5
NB5
Date: Sheet of
Date: Sheet of
Date: Sheet of
+3VSPI
SI
HOLD#
+3V_M<15>
SKL U (9/14)
SKL U (9/14)
SKL U (9/14)
1
1A
1A
10 41Tuesday, May 26, 2015
10 41Tuesday, May 26, 2015
10 41Tuesday, May 26, 2015
1A
5
4
3
2
1
11
D D
DESIGN NOTE:
WEAK PULL UP RESISTOR PRESENT ON THIS NET
ACZ_SPKR<14,23>
C C
1212 change R95 pull-high from
+3V to +3V_DEEP_SUS
B B
GSPI1_MOSI<14>
ACZ_SPKR
GSPI1_MOSI
R381
*20K/F_2
+3V_DEEP_SUS
R231
1K_2
R233
*20K/F_2
R63
*20K/F_2
Functional Strap Definitions
TOP SWAP OVERRIDE
HIGH - TOP SWAP ENABLE
LOW-DISABLED
HIGH: LPC SELECTED FOR SYSTEM FLASH
WEAK INTERNAL PD
No Boot:
The signal has a weak internal pull-down.
0 = Disable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (no confidentiality).
1 = Enable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (with confidentiality). Must be
pulled up to support Intel AMT with TLS and Intel
SBA (Small Business Advantage) with TLS.
No Boot:
The signal has a weak internal pull-down.
This field determines the destination of accesses to the
BIOS memory range. Also controllable using Boot BIOS
Destination bit (Chipset Configuration Registers: Offset
3410h:Bit 10). This strap is used in conjunction with Boot
BIOS Destination Selection 0 strap.
Bit 10 Boot BIOS Destination
0 SPI
1 LPC
ACZ_SDOUT<14>
GPIO33_EC<30>
GPP_B18<14>SML0ALERT#<10>
SML1ALERT#<10>
ACZ_SDOUT
R401 1K_2
GPP_B18SML0ALERT#
+3V_DEEP_SUS
SML1ALERT#
+3V_DEEP_SUS
R397
*4.7K_2
ACZ_SDOUT
+3V
R363
*4.7K_2
R362
10K_2
R260
*10K_2
R267
20K/F_2
No Boot:
The signal has a weak internal pull-down.
0 = Enable security measures defined in the Flash
Descriptor.
1 = Disable Flash Descriptor Security (override). This
strap should only be asserted high using external
pull-up in manufacturing/debug environments ONLY.
This function is useful when running ITP/XDP.
No Boot:
The signal has a weak internal pull-down.
0 = Disable No Reboot mode.
1 = Enable No Reboot mode
(PCH will disable the TCO
Timer system reboot feature).
This function is useful when running ITP/XDP.
No Boot:
The signal has a weak internal pull-down.
0 = LPC Is selected for EC.
1 = eSPI Is selected for EC.
A A
PROJECT : Y0DD
PROJECT : Y0DD
PROJECT : Y0DD
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
NB5
NB5
NB5
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
SKL U (10/14)
SKL U (10/14)
SKL U (10/14)
1
11 41Tuesday, May 26, 2015
11 41Tuesday, May 26, 2015
11 41Tuesday, May 26, 2015
1A
1A
1A
I'm from VIETNAM sualaptop365
5
+3V <2,4,10,11,13,14,15,16,20,21,22,23,25,26,27,29,30,31,37,38>
+3VS5 <4,15,16,22,28,30,31,33,35,36,37>
+3V_DEEP_SUS <4,10,11,14,15,16>
BB11
H13
G13
B17
A17
G11
F11
D16
C16
H16
G16
D17
C17
G15
F15
B19
A19
F16
E16
C19
D19
G18
F18
D20
C20
F20
E20
B21
A21
G21
F21
D21
C21
E22
E23
B23
A23
F25
E25
D23
C23
F5
E5
D56
D61
E28
E27
D24
C24
E30
F30
A25
B25
PCIE_RXN5_CARD<26>
PCIE_RXP5_CARD<26>
D D
C C
B B
WLAN
HDD
Cardreader
PCIE_TXN5_CARD<26>
PCIE_TXP5_CARD<26>
PCIE_RXN6_WLAN<28>
PCIE_RXP6_WLAN<28>
PCIE_TXN6_WLAN<28>
PCIE_TXP6_WLAN<28>
SATA_RXN3<26>
SATA_RXP3<26>
SATA_TXN3<26>
SATA_TXP3<26>
SATA_RXN2<26>
SATA_RXP2<26>
SATA_TXN2<26>
SATA_TXP2<26>
SATA_RXN1<26>
SATA_RXP1<26>
SATA_TXN1<26>
SATA_TXP1<26>
SATA_RXN0<26>
SATA_RXP0<26>
SATA_TXN0<26>
SATA_TXP0<26>
XDP_PRDY#_CPU<16>
XDP_PREQ#_CPU<16>
+3V_DEEP_SUS
C176 0.1U/16V_4
C177 0.1U/16V_4
C216 0.1U/16V_4
C215 0.1U/16V_4
R379 10K_2
PCIE_TXN5_CARD_C
PCIE_TXP5_CARD_C
PCIE_TXN6_WLAN_C
PCIE_TXP6_WLAN_C
R44 100/F_2
PIRQA#
PCI-E Port Mapping Table
PCI-E Port
Port1
Port2
Port3
Port4
Port5
A A
5
Port6
Port7
Port8
Port9
Port10 Un-used
4
U11H
PCIE/USB3/SATA
PCIE1_RXN/USB3_5_RXN
PCIE1_RXP/USB3_5_RXP
PCIE1_TXN/USB3_5_TXN
PCIE1_TXP/USB3_5_TXP
PCIE2_RXN/USB3_6_RXN
PCIE2_RXP/USB3_6_RXP
PCIE2_TXN/USB3_6_TXN
PCIE2_TXP/USB3_6_TXP
PCIE3_RXN
PCIE3_RXP
PCIE3_TXN
PCIE3_TXP
PCIE4_RXN
PCIE4_RXP
PCIE4_TXN
PCIE4_TXP
PCIE5_RXN
PCIE5_RXP
PCIE5_TXN
PCIE5_TXP
PCIE6_RXN
PCIE6_RXP
PCIE6_TXN
PCIE6_TXP
PCIE7_RXN/SATA0_RXN
PCIE7_RXP/SATA0_RXP
PCIE7_TXN/SATA0_TXN
PCIE7_TXP/SATA0_TXP
PCIE8_RXN/SATA1A_RXN
PCIE8_RXP/SATA1A_RXP
PCIE8_TXN/SATA1A_TXN
PCIE8_TXP/SATA1A_TXP
PCIE9_RXN
PCIE9_RXP
PCIE9_TXN
PCIE9_TXP
PCIE10_RXN
PCIE10_RXP
PCIE10_TXN
PCIE10_TXP
PCIE_RCOMPN
PCIE_RCOMPP
PROC_PRDY#
PROC_PREQ#
GPP_A7/PIRQA#
PCIE11_RXN/SATA1B_RXN
PCIE11_RXP/SATA1B_RXP
PCIE11_TXN/SATA1B_TXN
PCIE11_TXP/SATA1B_TXP
PCIE12_RXN/SATA2_RXN
PCIE12_RXP/SATA2_RXP
PCIE12_TXN/SATA2_TXN
PCIE12_TXP/SATA2_TXP
*SKL_ULT
REV = 1
Function
CardReader
WLAN
Un-used
Un-used
SSD
SSD
SSD
SSD
Un-used
4
SKL_ULT
CLK RQ Port
Port0
Port1
Port2
Port3
Port4
Port5
?
USB2
PDC
8 OF 20
Function
Un-used
CardReader
WLAN
Un-used
Un-used
SSD
Need apply PN
SSIC / USB3
GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
USB3_1_RXN
USB3_1_RXP
USB3_1_TXN
USB3_1_TXP
USB3_2_RXN/SSIC_1_RXN
USB3_2_RXP/SSIC_1_RXP
USB3_2_TXN/SSIC_1_TXN
USB3_2_TXP/SSIC_1_TXP
USB3_3_RXN/SSIC_2_RXN
USB3_3_RXP/SSIC_2_RXP
USB3_3_TXN/SSIC_2_TXN
USB3_3_TXP/SSIC_2_TXP
USB3_4_RXN
USB3_4_RXP
USB3_4_TXN
USB3_4_TXP
USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9
USB2P_9
USB2N_10
USB2P_10
USB2_COMP
USB2_ID
USB2_VBUSSENSE
GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2
GPP_E8/SATALED#
?
3
H8
G8
C13
D13
J6
H6
B13
A13
J10
H10
B15
A15
E10
F10
C15
D15
AB9
AB10
AD6
AD7
AH3
AJ3
AD9
AD10
AJ1
AJ2
AF6
AF7
AH1
AH2
AF8
AF9
AG1
AG2
AH7
AH8
AB6
AG3
AG4
A9
C9
D9
B9
J1
J2
J3
H2
H3
G4
H1
USB2_COMP
TS_OFF
TS_INT#
TS_RST
DEVSLP1
DEVSLP2
SATAGP0
SATAGP1
SATAGP2
SATA_LED#
USB30_RX1USB30_RX1+
USB30_TX1USB30_TX1+
USB30_RX2USB30_RX2+
USB30_TX2USB30_TX2+
USB30_RX3USB30_RX3+
USB30_TX3USB30_TX3+
USBP1USBP1+
USBP2USBP2+
USBP3USBP3+
USBP4USBP4+
USBP6USBP6+
USBP7USBP7+
USBP8USBP8+
R326 113/F_4
DEVSLP1 <26>
TP52
USB30_RX1- <25>
USB30_RX1+ <25>
USB30_TX1- <25>
USB30_TX1+ <25>
USB30_RX2- <25>
USB30_RX2+ <25>
USB30_TX2- <25>
USB30_TX2+ <25>
USB30_RX3- <25>
USB30_RX3+ <25>
USB30_TX3- <25>
USB30_TX3+ <25>
USBP1- <25>
USBP1+ <25>
USBP2- <25>
USBP2+ <25>
USBP3- <25>
USBP3+ <25>
USBP4- <29>
USBP4+ <29>
USBP6- <20>
USBP6+ <20>
USBP7- <28>
USBP7+ <28>
USBP8- <20>
USBP8+ <20>
ACC_LED# <10>
TS_OFF <20>
TS_INT# <20>
TS_RST <20>
TP53
USB3.0 Port Mapping Table
USB3.0 Function
PORT-1
PORT-2
PORT-3
USB3.0 MB-1
USB3.0 MB-2
USB3.0 MB-3
PORT-4 NC
3
2
USB3.0 (M/B-1)
USB3.0 (M/B-2)
USB3.0 (M/B-3)
Combo USB3.0 MB-1
Combo USB3.0 MB-2
Combo USB3.0 MB-3
Sensor Hub
Camera
BT
Touch Screen
PLACE 'R10387' WITHIN 500 MILS
FROM USB2_COMP PIN WITH
TRACE IMPEDANCE LESS THAN 0.5 OHMS
SI
2
TS_OFF
TS_INT#
TS_RST
SATA_LED#
SATAGP0
SATAGP1
SATAGP2
GPIO34 <26>
GPIO35 <26>
GPIO36 <26>
USB2.0 Port Mapping Table
USB2.0 Function
PORT-1
PORT-2
PORT-3
PORT-4
PORT-5
PORT-6
PORT-7
PORT-8
PORT-9
PORT-10
USB3.0 MB-1
USB3.0 MB-2
USB3.0 MB-3
Sensor Hub
NC
Camera
WLAN
Touch Screen
NC
NC
NB5
NB5
NB5
1
12
+3V
R171 *10K_2
R148 10K_2
R172 10K_2
R194 *10K_2
R126 10K_2
R15 10K_2
R14 10K_2
R16 *10K_2
R17 *10K_2
R131 *10K_2
PROJECT : Y0DD
PROJECT : Y0DD
PROJECT : Y0DD
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
SKL U (11/14)
SKL U (11/14)
SKL U (11/14)
1
12 41Tuesday, May 26, 2015
12 41Tuesday, May 26, 2015
12 41Tuesday, May 26, 2015
1A
1A
1A
I'm from VIETNAM sualaptop365
5
4
3
2
1
+1.8V_DEEP_SUS <9,15,35,37>
+3V <2,4,10,11,12,14,15,16,20,21,22,23,25,26,27,29,30,31,37,38>
?
10 OF 20
?
PDC
9 OF 20
Need apply PN
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
GPD8/SUSCLK
XCLK_BIASREF
TBT
Need apply PN
CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3
CSI2_COMP
GPP_D4/FLASHTRIG
EMMC
GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7
GPP_F21/EMMC_RCLK
GPP_F22/EMMC_CLK
GPP_F12/EMMC_CMD
EMMC_RCOMP
?
XTAL24_IN
XTAL24_OUT
RTCX1
RTCX2
SRTCRST#
RTCRST#
C37
D37
C32
D32
C29
D29
B26
A26
E13
B7
AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1
AM2
AM3
AP4
AT1
?
F43
E43
BA17
PCH_SUSCLK
E37
XTAL24_IN
E35
XTAL24_OUT
E42
XCLK_BIASREF
AM18
RTC_X1
AM20
RTC_X2
AN18
SRTC_RST#PCIE_CLKREQ_VGA#
AM16
RTC_RST#
GPP_D4
EMMC_RCOMP
R168 2.7K/F_4
R166 *60.4/F_4
TP69
R144 100/F_2
TP49
R337 200/F_4
RTC_RST# <16>
CK_XDP_N <16>
CK_XDP_P <16>
PCH_SUSCLK <26,28>
+1.0V_DEEP_SUS
CLK_REQ/Strap Pin(CLG)
PCIE_CLKREQ_VGA#
PCIE_CLKREQ_WLAN#
PCIE_CLKREQ_LAN#
PCIE_CLKREQ_CR#
PCIE_CLKREQ_SSD#
PCIE_CLKREQ0#
R371 10K_2
R372 10K_2
R68 10K_2
R369 10K_2
R386 10K_2
R67 10K_2
U11J
D42
CLKOUT_PCIE_N0
C42
CLKOUT_PCIE_P0
D D
Cardreader
WLAN
SSD
C C
B B
CLK_PCIE_SSDN<26>
CLK_PCIE_SSDP<26>
PCIE_CLKREQ_SSD#<26>
CLK_PCIE_CRN<26>
CLK_PCIE_CRP<26>
PCIE_CLKREQ_CR#<26>
CLK_PCIE_WLANN<28>
CLK_PCIE_WLANP<28>
PCIE_CLKREQ_WLAN#<28>
PCIE_CLKREQ_SSD#
PCIE_CLKREQ0#
CLK_PCIE_CRN
CLK_PCIE_CRP
PCIE_CLKREQ_CR#
CLK_PCIE_WLANN
CLK_PCIE_WLANP
PCIE_CLKREQ_WLAN#
PCIE_CLKREQ_LAN#
AR10
GPP_B5/SRCCLKREQ0#
B42
CLKOUT_PCIE_N1
A42
CLKOUT_PCIE_P1
AT7
GPP_B6/SRCCLKREQ1#
D41
CLKOUT_PCIE_N2
C41
CLKOUT_PCIE_P2
AT8
GPP_B7/SRCCLKREQ2#
D40
CLKOUT_PCIE_N3
C40
CLKOUT_PCIE_P3
AT10
GPP_B8/SRCCLKREQ3#
B40
CLKOUT_PCIE_N4
A40
CLKOUT_PCIE_P4
AU8
GPP_B9/SRCCLKREQ4#
E40
CLKOUT_PCIE_N5
E38
CLKOUT_PCIE_P5
AU7
GPP_B10/SRCCLKREQ5#
*SKL_ULT
REV = 1
A36
B36
C38
D38
C36
D36
A38
B38
C31
D31
C33
D33
A31
B31
A33
B33
A29
B29
C28
D28
A27
B27
C27
D27
U11I
CSI-2
CSI2_DN0
CSI2_DP0
CSI2_DN1
CSI2_DP1
CSI2_DN2
CSI2_DP2
CSI2_DN3
CSI2_DP3
CSI2_DN4
CSI2_DP4
CSI2_DN5
CSI2_DP5
CSI2_DN6
CSI2_DP6
CSI2_DN7
CSI2_DP7
CSI2_DN8
CSI2_DP8
CSI2_DN9
CSI2_DP9
CSI2_DN10
CSI2_DP10
CSI2_DN11
CSI2_DP11
*SKL_ULT
SKL_ULT
CLOCK SIGNALS
SKL_ULT
REV = 1
13
+3V
RTC Clock 32.768KHz
C357 15P/50V_4
Y2
32.768KHz
A A
SI
RTC_X1
12
R350
10M_4
RTC_X2
I'm from VIETNAM sualaptop365
5
RTC Circuitry(RTC)
RTC Power trace width 20mils.
+3VPCU
4
D7
MEK500V-40
1U/6.3V_4
+3V_RTC <4,15,27,31,32>
+3VPCU <6,15,27,28,30,31,32,33,41>
30mils
+3V_RTC
C306
R286
20K/F_2
R301
20K/F_2C362 15P/50V_4
R304 *0_6
C293
1U/6.3V_4
C341
1U/6.3V_4
R302 *0_6
RTC_RST#
SRTC_RST#
SRTC_RST#RTC_RST#
3
RTC_RST#
3
2
Q18
2N7002K
1
R282
10K_2
EC_RTC_RST <30>
External Crystal
2
XTAL24_IN
XTAL24_OUT
TP50
C207 33P/50V_4
1
2
R176
24MHZ +-30PPM
1M_2
Y1
4
3
C208 33P/50V_4
TP51
SI 2
PROJECT : Y0DD
PROJECT : Y0DD
PROJECT : Y0DD
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
SKL U (12/14)
SKL U (12/14)
NB5
NB5
NB5
SKL U (12/14)
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
1A
1A
13 41Tuesday, May 26, 2015
13 41Tuesday, May 26, 2015
13 41Tuesday, May 26, 2015
1A
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