Quanta Y01 Schematic Timing Diagram
5
4
3
2
1
A23 - Intel Shark Bay ULT mainly Power On Sequence(G3 to S0)
From Coin Cell BAT
D D
From AC,BATT
3V/5V (TPS51225RUKR)
EC to PCH
EC to PCH
PCH to EC
From PW On Button to EC
EC to PCH
C C
VDDQ Power GOOD
MainOn Power Rail
MainOn Power Rail
B B
MainOn Power Rail
EC to PCH
CPU to Power IC
PP3300_RTC
VIN
PP3300_DSW
PCH_DPWROK
PCH_RSMRST_L
PCH_SLP_SUS_L
PWR_BTN_L
PCH_PWRBTN_L
PCH_SLP_S5_LPCH to EC
PCH_SLP_S3_LPCH to EC
PP3300_PCH_SUSSUSON Power Rail
PP1050_PCH_SUSSUSON Power Rail
PP1350VDDQ
PP1350_PGOOD
PP1050_PCH
PP3300_PCH
PP1500_PCH_TS
PCH_PWROK
VCCST_PWRGDEC to CPU
VRON_CPU
EC assert PP3300_DSW_EN to 3V/5V (TPS51225RUKR)
10ms
For a non-DeepSx system DPWROK and RSMRST# go
high at the same time (connected on board)
Minimum duration of PCH_PWRBTN_L assertion = 16 mS.
PCH_PWRBTN_L can assert before or after PCH_RSMRST_L
60uS
PCH_SLP_S5_L enable TPS22930
EC assert SUSP_VR_EN to AOZ1237QI
EC assert PP1350_EN to TPS51216RUKR
100nS
Power IC to EC
PCH_SLP_S3_L enable TPS22964
PCH_SLP_S3_L enable TPS22930
PCH_SLP_S3_L enable APW8824CTI
1mS
PCH_PWROK and APWROK are strapped together
PCH_PWROK to CPU via power buffer
01
CPU Core Power +VCCIN
Power IC to CPU VCORE_PGOOD
SYS_PWROKEC to PCH
CPU SVID BUSCPU SVID BUS
A A
PLTRST#PCH Assert PLTRST#
5~99mS
CPU drives SVID
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Monday, April 29, 2013
Date: Sheet of
Monday, April 29, 2013
Date: Sheet of
5
4
3
2
Monday, April 29, 2013
PROJECT :
Power Sequence
Power Sequence
Power Sequence
1
A23
A23
A23
1 1
1 1
1 1
1A
1A
1A
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