QUANTA X31 Schematics
5
4
3
2
1
Monster Intel KABY LAKE ULT Platform Block Diagram
SPI Interface
D D
13.3 QHD AG Panel 2560 x 2160
PAGE 20
LPDDR3 1600MHz
16Gb x64 2PCS
eDP x 1 Port, 4Lanes13.3 FHD 1920 x 1080,
LPDDR3L x1866MHz 1.2V
DDI x 2 Port 8 Lans
PAGE 17
LPDDR3 1600MHz
16Gb x64 2PCS
LPDDR3L x1866MHz 1.2V
PAGE 18
SATA - 1st NGFF SSD
256/512GB/1TB or
>1TB SSD in M.2 2280-D3
C C
PAGE 24
SATA0/PCIE 4XLANE
KABY LAKE - U
Processor
PCIE x 4
Thunderbolt
Intel Alpine Ridge
I2C/I2S
Speaker
Speaker Amplifier
ALC1004-CG
PAGE 21
Headphone amplifier
HPA0022642RTJR
Speaker
PAGE 21
B B
PAGE 20
Digital MIC
PAGE 22
Combo Jack
System BIOS
SPI ROM
PAGE 10
AUDIO CODEC
ALC3258-CG
HDA
PAGE 20
SPI Interface
Processor : Daul Core GT3e
Power : 15 (Watt)
Package : BGA1356
Size : 40 X 24 (mm)
HP
PG.2~16
USB3.0 Interface
USB2.0 Interface
I2C
Touch Screen
ISH
PAGE 29,30
Camera
Full HD + IR front camera
Alpine Rideg EEPROM
SPI ROM
DP AUX /TBT LS
USB2.0
USB2.0
DP AUX /TBT LS
PORT5,6
PORT1
SPI and Connect to TI TPS65982
CIO_TX_RX (DP/USB3.1)
USB type C PD
TI TPS65982
PAGE 31
USB type C PD
TI TPS65982
PAGE 32
CIO_TX_RX (DP/USB3.1)
USB Charger
TI TPS2546
PORT7
USB2.0 B/T
CC1/CC2
SBU1/SBU2
USB2.0
CC1/CC2
SBU1/SBU2
USB 3.0*
USB2.0
USB2.0 B/T
USB TypeC A
PAGE 34
USB Charger
TI TPS2546
BC 1.2
PG 33
USB Charger
TI TPS2546
BC 1.2
PG 33
USB TypeC B
PAGE 34
USB3.0 Port x 1
(total 3.5A)
PAGE 23
USB TypeC Adapter
20V, 75W
01
TPM 2.0 SLB9665TT2.0
(OPTION)
PAGE 24
LPC
ITE 8987
Embedded Controller
Package : BGA128
Keyboard
A A
Touch Pad
Synaptics
PAGE 25
PS2
SMBUS
Size : 7x 7 (mm)
PAGE 28PAGE 25
FAN1
FAN2
SMBUS
Battery
3-cell 64.5W 3S1P
PAGE 22 PAGE 22
5
4
G-Sensor
ST Micro HP2DCTR
PAGE 27
PCIE Gen 1 x 1 Lane
Accelerometer +e-Compass+Gyro
HP9DS1TR TS Board
Wireless LAN via M.2 card
Snowfield Peak
WiFi / BT Combo
PAGE 26
PROJECT : X31
PROJECT : X31
PROJECT : X31
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
NB5
NB5
NB5
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
Block Diagram
Block Diagram
Block Diagram
for ERD check
1
1 50Friday, August 05, 2016
1 50Friday, August 05, 2016
1 50Friday, August 05, 2016
I'm from VIETNAM sualaptop365
5
+3V
INT_DP_SCL
R194 2.2K_2
INT_DP_SDA
D D
DDPB_CTRLDATA/ GPP_E19
Display Port B Detected
This signal has a weak internal pull-down.
0 = Port B is not detected.
1 = Port B is detected.
This signal has a weak internal
pull-down.
0 = Port C and D is not detected.
1 = Port C and D is detected.
C C
SDVO_CLK
SDVO_DATA
DDPD_CTRLDATA
R195 2.2K_2
R191 2.2K_2
R192 2.2K_2
R197 10K_2
eDP_COMPIO and ICOMPO signals should be shorted near
balls and routed with typical impedance <25 mohms
+VCCIO
4
DDI1_TX0_DN29
DDI1_TX0_DP29
DDI1_TX1_DN29
DDI1_TX1_DP29
DDI1_TX2_DN29
DDI1_TX2_DP29
DDI1_TX3_DN29
DDI1_TX3_DP29
DDI2_TX0_DN29
DDI2_TX0_DP29
DDI2_TX1_DN29
DDI2_TX1_DP29
DDI2_TX2_DN29
DDI2_TX2_DP29
DDI2_TX3_DN29
DDI2_TX3_DP29
R220 24.9/F_2
SDVO_CLK
SDVO_DATA
INT_DP_SCL
INT_DP_SDA
DDPD_CTRLDATA
EDP_RCOMP
U1A
E55
DDI1_TXN[0]
F55
DDI1_TXP[0]
E58
DDI1_TXN[1]
F58
DDI1_TXP[1]
F53
DDI1_TXN[2]
G53
DDI1_TXP[2]
F56
DDI1_TXN[3]
G56
DDI1_TXP[3]
C50
DDI2_TXN[0]
D50
DDI2_TXP[0]
C52
DDI2_TXN[1]
D52
DDI2_TXP[1]
A50
DDI2_TXN[2]
B50
DDI2_TXP[2]
D51
DDI2_TXN[3]
C51
DDI2_TXP[3]
L13
GPP_E18/DDPB_CTRLCLK
L12
GPP_E19/DDPB_CTRLDATA
N7
GPP_E20/DDPC_CTRLCLK
N8
GPP_E21/DDPC_CTRLDATA
N11
GPP_E22/DDPD_CTRLCLK
N12
GPP_E23/DDPD_CTRLDATA
E52
EDP_RCOMP
*SKL_ULT
REV = 1
SKL_ULT
DDI
DISPLAY SIDEBANDS
3
?
Need apply PN
C47
EDP_TXN[0]
C46
EDP_TXP[0]
D46
EDP_TXN[1]
C45
EDP_TXP[1]
A45
EDP_TXN[2]
B45
EDP_TXP[2]
A47
EDP_TXN[3]
B47
EDP_TXP[3]
E45
EDP
EDP_AUXN
F45
EDP_AUXP
DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
DDI3_AUXN
DDI3_AUXP
B52
G50
F50
E48
F48
G46
F46
L9
L7
L6
N9
L10
R12
R11
U13
?1 OF 20
EDP_DISP_UTIL
GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3
GPP_E17/EDP_HPD
EDP_BKLTEN
EDP_BKLTCTL
EDP_VDDEN
+3V 4,10,11,12,13,14,15,19,20,21,22,24,25,27,28,29,33,42,46
+1.0V 4,6,28,41
+VCCIO 6,41
+VCCSTPLL 5,6,9,41,42
INT_EDP_TXN0
INT_EDP_TXP0
INT_EDP_TXN1
INT_EDP_TXP1
INT_EDP_TXN2
INT_EDP_TXP2
INT_EDP_TXN3
INT_EDP_TXP3
INT_EDP_AUXN
INT_EDP_AUXP
ULT_EDP_HPD
PCH_LVDS_BLON
PCH_DPST_PWM
PCH_DISP_ON
2
INT_EDP_TXN0 19
INT_EDP_TXP0 19
INT_EDP_TXN1 19
INT_EDP_TXP1 19
INT_EDP_TXN2 19
INT_EDP_TXP2 19
INT_EDP_TXN3 19
INT_EDP_TXP3 19
INT_EDP_AUXN 19
INT_EDP_AUXP 19
DDI1_AUX_DN 29
DDI1_AUX_DP 29
DDI2_AUX_DN 29
DDI2_AUX_DP 29
DDI1_HPD0 29
DDI2_HPD0 29
ULT_EDP_HPD 19
PCH_LVDS_BLON 19
PCH_DPST_PWM 19
PCH_DISP_ON 19
1
Reserve EDP_HPD opposites circuit!
+3V
R35
*10K_2
ULT_EDP_HPD
R31
100K_2
02
+VCCSTPLL
R170 *49.9/F_2
H_PROCHOT#28,37,42
+1.0V
R166 1K_2
B B
A A
H_PROCHOT#
5
R188 499/F_4
4
EC_PECI28
PM_THRMTRIP#28
R248 49.9/F_2
R249 49.9/F_2
R210 49.9/F_2
R208 49.9/F_2
CATERR#
EC_PECI
PROCHOT#
PM_THRMTRIP#
PROC_POPIRCOMP
PCH_OPI_RCOMP
EDRAM_OPIO_RCOMP
EOPIO_RCOMP
D63
CATERR#
A54
PECI
C65
PROCHOT#
C63
THERMTRIP#
A65
SKTOCC#
C55
BPM#[0]
D55
BPM#[1]
B54
BPM#[2]
C56
BPM#[3]
A6
GPP_E3/CPU_GP0
A7
GPP_E7/CPU_GP1
BA5
GPP_B3/CPU_GP2
AY5
GPP_B4/CPU_GP3
AT16
PROC_POPIRCOMP
AU16
PCH_OPIRCOMP
H66
OPCE_RCOMP
H65
OPC_RCOMP
U1D
*SKL_ULT
REV = 1
SKL_ULT
CPU MISC
3
?
4 OF 20
Need apply PN
JTAG
PROC_TCK
PROC_TDI
PROC_TDO
PROC_TMS
PROC_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_TRST#
JTAGX
PDC
B61
XDP_TCK0
D60
XDP_TDI_CPU
A61
XDP_TDO_CPU
C60
XDP_TMS_CPU
B59
XDP_TRST#
B56
JTAG_TCK_PCH
D59
JTAG_TDI_PCH XDP_TDI_CPU
A56
JTAG_TDO_PCH XDP_TDO_CPU
C59
JTAG_TMS_PCH XDP_TMS_CPU
C61
XDP_TRST#_CPU XDP_TRST#
A59
JTAGX_PCH XDP_TCK0
R182 *0_2/S
R16 *0_2/S
R181 *0_2/S
R177 *0_2/S
R187 *0_2/S
2
Close to EC
PM_THRMTRIP#
Processor pull-up (CPU)
TO BE REPLACED WITH 1K OHMS FOR SKL .
470 OHM IS FOR I/P
JTAG_TMS_PCH
JTAG_TDI_PCH
JTAG_TDO_PCH
JTAG_TCK_PCH
XDP_TCK0
XDP_TRST#_CPU
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
NB5
NB5
NB5
Date: Sheet of
Date: Sheet of
Date: Sheet of
R553 1K_2
R172 51_2
R171 51_2
R10 100_2
R14 51_2
R176 51_2
R175 51_2
Close to Chipset
PROJECT : X31
PROJECT : X31
PROJECT : X31
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
SKLU (1/14)
SKLU (1/14)
SKLU (1/14)
1
+VCCSTPLL
+1.0V
PVR Change
2 49Friday, August 05, 2016
2 49Friday, August 05, 2016
2 49Friday, August 05, 2016
I'm from VIETNAM sualaptop365
5
M_A_DQSN[7:0]16
M_A_DQSP[7:0]16
M_B_DQSN[7:0]17
M_B_DQSP[7:0]17
M_A_DQ[63:0]16
M_B_DQ[63:0]17
4
3
2
1
03
KABYLAKE ULT Processor LPDDR3 x32
D D
Need apply PN
?
U1B
AL71
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
C C
B B
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
DDR0_DQ[0]
AL68
DDR0_DQ[1]
AN68
DDR0_DQ[2]
AN69
DDR0_DQ[3]
AL70
DDR0_DQ[4]
AL69
DDR0_DQ[5]
AN70
DDR0_DQ[6]
AN71
DDR0_DQ[7]
AR70
DDR0_DQ[8]
AR68
DDR0_DQ[9]
AU71
DDR0_DQ[10]
AU68
DDR0_DQ[11]
AR71
DDR0_DQ[12]
AR69
DDR0_DQ[13]
AU70
DDR0_DQ[14]
AU69
DDR0_DQ[15]
AF65
DDR1_DQ[0]/DDR0_DQ[16]
AF64
DDR1_DQ[1]/DDR0_DQ[17]
AK65
DDR1_DQ[2]/DDR0_DQ[18]
AK64
DDR1_DQ[3]/DDR0_DQ[19]
AF66
DDR1_DQ[4]/DDR0_DQ[20]
AF67
DDR1_DQ[5]/DDR0_DQ[21]
AK67
DDR1_DQ[6]/DDR0_DQ[22]
AK66
DDR1_DQ[7]/DDR0_DQ[23]
AF70
DDR1_DQ[8]/DDR0_DQ[24]
AF68
DDR1_DQ[9]/DDR0_DQ[25]
AH71
DDR1_DQ[10]/DDR0_DQ[26]
AH68
DDR1_DQ[11]/DDR0_DQ[27]
AF71
DDR1_DQ[12]/DDR0_DQ[28]
AF69
DDR1_DQ[13]/DDR0_DQ[29]
AH70
DDR1_DQ[14]/DDR0_DQ[30]
AH69
DDR1_DQ[15]/DDR0_DQ[31]
BB65
DDR0_DQ[16]/DDR0_DQ[32]
AW65
DDR0_DQ[17]/DDR0_DQ[33]
AW63
DDR0_DQ[18]/DDR0_DQ[34]
AY63
DDR0_DQ[19]/DDR0_DQ[35]
BA65
DDR0_DQ[20]/DDR0_DQ[36]
AY65
DDR0_DQ[21]/DDR0_DQ[37]
BA63
DDR0_DQ[22]/DDR0_DQ[38]
BB63
DDR0_DQ[23]/DDR0_DQ[39]
BA61
DDR0_DQ[24]/DDR0_DQ[40]
AW61
DDR0_DQ[25]/DDR0_DQ[41]
BB59
DDR0_DQ[26]/DDR0_DQ[42]
AW59
DDR0_DQ[27]/DDR0_DQ[43]
BB61
DDR0_DQ[28]/DDR0_DQ[44]
AY61
DDR0_DQ[29]/DDR0_DQ[45]
BA59
DDR0_DQ[30]/DDR0_DQ[46]
AY59
DDR0_DQ[31]/DDR0_DQ[47]
AT66
DDR1_DQ[16]/DDR0_DQ[48]
AU66
DDR1_DQ[17]/DDR0_DQ[49]
AP65
DDR1_DQ[18]/DDR0_DQ[50]
AN65
DDR1_DQ[19]/DDR0_DQ[51]
AN66
DDR1_DQ[20]/DDR0_DQ[52]
AP66
DDR1_DQ[21]/DDR0_DQ[53]
AT65
DDR1_DQ[22]/DDR0_DQ[54]
AU65
DDR1_DQ[23]/DDR0_DQ[55]
AT61
DDR1_DQ[24]/DDR0_DQ[56]
AU61
DDR1_DQ[25]/DDR0_DQ[57]
AP60
DDR1_DQ[26]/DDR0_DQ[58]
AN60
DDR1_DQ[27]/DDR0_DQ[59]
AN61
DDR1_DQ[28]/DDR0_DQ[60]
AP61
DDR1_DQ[29]/DDR0_DQ[61]
AT60
DDR1_DQ[30]/DDR0_DQ[62]
AU60
DDR1_DQ[31]/DDR0_DQ[63]
*SKL_ULT
REV = 1
SKL_ULT
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]
DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]
DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]
DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7]
NIL-DDR CH A
2 OF 20
DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]
DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]
DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]
DDR0_ODT[1]
DDR0_MA[3]
DDR0_MA[4]
DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSP[1]
DDR0_ALERT#
DDR0_PAR
DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ
DDR_VTT_CNTL
AU53
AT53
AU55
AT55
BA56
BB56
AW56
AY56
AU45
AU43
AT45
AT43
BA51
BB54
BA52
AY52
AW52
AY55
AW54
BA54
BA55
AY54
AU46
AU48
AT46
AU50
AU52
AY51
AT48
AT50
BB50
AY50
BA50
BB52
AM70
M_A_DQSN0
AM69
M_A_DQSP0
AT69
M_A_DQSN1
AT70
M_A_DQSP1
AH66
M_A_DQSN2
AH65
M_A_DQSP2
AG69
M_A_DQSN3
AG70
M_A_DQSP3
BA64
M_A_DQSN4
AY64
M_A_DQSP4
AY60
M_A_DQSN5
BA60
M_A_DQSP5
AR66
M_A_DQSN6
AR65
M_A_DQSP6
AR61
M_A_DQSN7
AR60
M_A_DQSP7
AW50
AT52
AY67
AY68
BA67
AW67
DDR_VTT_CNTL_R
M_A_CKE2
M_A_CKE3
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_B0
M_A_B1
M_A_B2
M_A_B3
M_A_B4
M_A_B5
M_A_B6
M_A_B7
M_A_B8
M_A_B9
M_A_A0 16,18
M_A_A1 16,18
M_A_A2 16,18
M_A_A3 16,18
M_A_A4 16,18
M_A_A5 16,18
M_A_A6 16,18
M_A_A7 16,18
M_A_A8 16,18
M_A_A9 16,18
M_A_B0 16,18
M_A_B1 16,18
M_A_B2 16,18
M_A_B3 16,18
M_A_B4 16,18
M_A_B5 16,18
M_A_B6 16,18
M_A_B7 16,18
M_A_B8 16,18
M_A_B9 16,18
R80 *0_2
Place near CPU
M_A_CLKN0 16,18
M_A_CLKP0 16,18
M_A_CLKN1 16,18
M_A_CLKP1 16,18
M_A_CKE0 16,18
M_A_CKE1 16,18
M_A_CKE2 16,18
M_A_CKE3 16,18
M_A_CS#0 16,18
M_A_CS#1 16,18
M_A_ODT0 16,18
SM_VREF_CA 16
SM_VREF_DQ0 16
SM_VREF_DQ1 17
DDR_VTT_CNTL 4
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
U1C
AY39
DDR0_DQ[32]/DDR1_DQ[0]
AW39
DDR0_DQ[33]/DDR1_DQ[1]
AY37
DDR0_DQ[34]/DDR1_DQ[2]
AW37
DDR0_DQ[35]/DDR1_DQ[3]
BB39
DDR0_DQ[36]/DDR1_DQ[4]
BA39
DDR0_DQ[37]/DDR1_DQ[5]
BA37
DDR0_DQ[38]/DDR1_DQ[6]
BB37
DDR0_DQ[39]/DDR1_DQ[7]
AY35
DDR0_DQ[40]/DDR1_DQ[8]
AW35
DDR0_DQ[41]/DDR1_DQ[9]
AY33
DDR0_DQ[42]/DDR1_DQ[10]
AW33
DDR0_DQ[43]/DDR1_DQ[11]
BB35
DDR0_DQ[44]/DDR1_DQ[12]
BA35
DDR0_DQ[45]/DDR1_DQ[13]
BA33
DDR0_DQ[46]/DDR1_DQ[14]
BB33
DDR0_DQ[47]/DDR1_DQ[15]
AU40
DDR1_DQ[32]/DDR1_DQ[16]
AT40
DDR1_DQ[33]/DDR1_DQ[17]
AT37
DDR1_DQ[34]/DDR1_DQ[18]
AU37
DDR1_DQ[35]/DDR1_DQ[19]
AR40
DDR1_DQ[36]/DDR1_DQ[20]
AP40
DDR1_DQ[37]/DDR1_DQ[21]
AP37
DDR1_DQ[38]/DDR1_DQ[22]
AR37
DDR1_DQ[39]/DDR1_DQ[23]
AT33
DDR1_DQ[40]/DDR1_DQ[24]
AU33
DDR1_DQ[41]/DDR1_DQ[25]
AU30
DDR1_DQ[42]/DDR1_DQ[26]
AT30
DDR1_DQ[43]/DDR1_DQ[27]
AR33
DDR1_DQ[44]/DDR1_DQ[28]
AP33
DDR1_DQ[45]/DDR1_DQ[29]
AR30
DDR1_DQ[46]/DDR1_DQ[30]
AP30
DDR1_DQ[47]/DDR1_DQ[31]
AY31
DDR0_DQ[48]/DDR1_DQ[32]
AW31
DDR0_DQ[49]/DDR1_DQ[33]
AY29
DDR0_DQ[50]/DDR1_DQ[34]
AW29
DDR0_DQ[51]/DDR1_DQ[35]
BB31
DDR0_DQ[52]/DDR1_DQ[36]
BA31
DDR0_DQ[53]/DDR1_DQ[37]
BA29
DDR0_DQ[54]/DDR1_DQ[38]
BB29
DDR0_DQ[55]/DDR1_DQ[39]
AY27
DDR0_DQ[56]/DDR1_DQ[40]
AW27
DDR0_DQ[57]/DDR1_DQ[41]
AY25
DDR0_DQ[58]/DDR1_DQ[42]
AW25
DDR0_DQ[59]/DDR1_DQ[43]
BB27
DDR0_DQ[60]/DDR1_DQ[44]
BA27
DDR0_DQ[61]/DDR1_DQ[45]
BA25
DDR0_DQ[62]/DDR1_DQ[46]
BB25
DDR0_DQ[63]/DDR1_DQ[47]
AU27
DDR1_DQ[48]
AT27
DDR1_DQ[49]
AT25
DDR1_DQ[50]
AU25
DDR1_DQ[51]
AP27
DDR1_DQ[52]
AN27
DDR1_DQ[53]
AN25
DDR1_DQ[54]
AP25
DDR1_DQ[55]
AT22
DDR1_DQ[56]
AU22
DDR1_DQ[57]
AU21
DDR1_DQ[58]
AT21
DDR1_DQ[59]
AN22
DDR1_DQ[60]
AP22
DDR1_DQ[61]
AP21
DDR1_DQ[62]
AN21
DDR1_DQ[63]
*SKL_ULT
REV = 1
?
SKL_ULT
Need apply PN
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
NIL-DDR CH B
3 OF 20
DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]
DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]
DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]
DDR1_ODT[1]
DDR1_MA[3]
DDR1_MA[4]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSP[5]/DDR1_DQSP[3]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSP[7]/DDR1_DQSP[5]
DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]
DDR1_ALERT#
DDR1_PAR
DRAM_RESET#
DDR_RCOMP[0]
DDR_RCOMP[1]
DDR_RCOMP[2]
PDC
AN45
AN46
AP45
AP46
AN56
AP55
AN55
M_B_CKE2
AP53
M_B_CKE3
BB42
AY42
BA42
AW42
AY48
M_B_A0
AP50
M_B_A1
BA48
M_B_A2
BB48
M_B_A3
AP48
M_B_A4
AP52
M_B_A5
AN50
M_B_A6
AN48
M_B_A7
AN53
M_B_A8
AN52
M_B_A9
BA43
M_B_B0
AY43
M_B_B1
AY44
M_B_B2
AW44
M_B_B3
BB44
M_B_B4
AY47
M_B_B5
BA44
M_B_B6
AW46
M_B_B7
AY46
M_B_B8
BA46
M_B_B9
BB46
BA47
BA38
M_B_DQSN0
AY38
M_B_DQSP0
AY34
M_B_DQSN1
BA34
M_B_DQSP1
AT38
M_B_DQSN2
AR38
M_B_DQSP2
AT32
M_B_DQSN3
AR32
M_B_DQSP3
BA30
M_B_DQSN4
AY30
M_B_DQSP4
AY26
M_B_DQSN5
BA26
M_B_DQSP5
AR25
M_B_DQSN6
AR27
M_B_DQSP6
AR22
M_B_DQSN7
AR21
M_B_DQSP7
AN43
AP43
AT13
SM_DRAMRST#
AR18
AT18
AU18
DDR Rcomp need follow Intel Spec
12-15 min trance length
M_B_CLKN0 17,18
M_B_CLKN1 17,18
M_B_CLKP0 17,18
M_B_CLKP1 17,18
M_B_CKE0 17,18
M_B_CKE1 17,18
M_B_CKE2 17,18
M_B_CKE3 17,18
M_B_CS#0 17,18
M_B_CS#1 17,18
M_B_ODT0 17,18
M_B_A0 17,18
M_B_A1 17,18
M_B_A2 17,18
M_B_A3 17,18
M_B_A4 17,18
M_B_A5 17,18
M_B_A6 17,18
M_B_A7 17,18
M_B_A8 17,18
M_B_A9 17,18
M_B_B0 17,18
M_B_B1 17,18
M_B_B2 17,18
M_B_B3 17,18
M_B_B4 17,18
M_B_B5 17,18
M_B_B6 17,18
M_B_B7 17,18
M_B_B8 17,18
M_B_B9 17,18
Need change to 0ohm open
SM_RCOMP_0
R253 200/F_2
SM_RCOMP_1
R252 80.6/F_2
SM_RCOMP_2
R251 162/F_2
+1.2VSUS
R304
*0_2
+1.2VSUS 6,16,17,18,39,41
A A
PROJECT : X31
PROJECT : X31
PROJECT : X31
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
SKL U (2/14)
SKL U (2/14)
NB5
NB5
5
4
3
2
NB5
SKL U (2/14)
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
3 49Friday, August 05, 2016
3 49Friday, August 05, 2016
3 49Friday, August 05, 2016
I'm from VIETNAM sualaptop365
5
4
3
2
1
04
?
U1K
D D
C C
RSMRST#28
EC19
*220P/50V_2
EC_PWROK28
PCIE_WAKE#26,28,29
RF_OFF_PCH26
DDR_VTT_CNTL3
R198 *10K_2
C19 *0.1U/10V_2
R263 *0_2
R247 *0_2/S
PLTRST#
SYS_RESET#
RSMRST#
PROCPWRGD
H_VCCST_PWRGD
SYS_PWROK
EC_PWROK
DSWROK_EC_R
SUSWARN#SUSWARN#_EC
SUSACK#SUSWARN#
PCIE_WAKE#
RF_OFF_PCH
AN10
GPP_B13/PLTRST#
B5
SYS_RESET#
AY17
RSMRST#
A68
PROCPWRGD
B65
VCCST_PWRGD
B6
SYS_PWROK
BA20
PCH_PWROK
BB20
DSW_PW ROK
AR13
GPP_A13/SUSW ARN#/SUSPWRDNACK
AP11
GPP_A15/SUSACK#
BB15
WAKE#
AM15
GPD2/LAN_WAKE#
AW17
GPD11/LANPHYPC
AT15
GPD7/RSVD
*SKL_ULT
REV = 1
SKL_ULT
SYSTEM POWER MANAGEMENT
Need apply PN
SLP_SUS#
SLP_LAN#
INTRUDER#
AT11
AP15
BA16
AY16
AN15
AW15
BB17
AN16
BA15
AY15
AU13
AU11
AP16
AM10
AM11
?
GPP_B12/SLP_S0#
GPD4/SLP_S3#
GPD5/SLP_S4#
GPD10/SLP_S5#
GPD9/SLP_WLAN#
GPD6/SLP_A#
GPD3/PWRBTN#
GPD1/ACPRESENT
GPD0/BATLOW #
GPP_A11/PME#
GPP_B11/EXT_PW R_GATE#
GPP_B2/VRALERT#
11 OF 20
+3V 2,10,11,12,13,14,15,19,20,21,22,24,25,27,28,29,33,42,46
+1.0V 2,6,28,41
+3VS5 15,26,27,28,29,30,37,38,39,40,41,45,46
+5VS5 20,23,31,32,33,38,39,40,41,42,43,44,46
+BAT_RTC 13,15,25,37,47
+3V_RTC_2 13,15
+3V_DEEP_SUS 10,11,12,14,15,30
SLP_SUS#_EC
PCH_SLP_WLAN#
DNBSWON#
AC_PRESENT_EC
BATLOW#
INTRUDER#_R
Rb
R250 1M_2
Ra
R298 *1M_2
SUSB# 28
SUSC# 28
SLP_SUS#_EC 28
PCH_SLP_WLAN# 28
SLP_A# 28
DNBSWON# 28
AC_PRESENT_EC 28
BATLOW# 29
+3V_RTC_2
+BAT_RTC
Main BAT -->Ra
Coin BAT -->Rb (default)
PCH Pull-high/low(CLG)
SUSWARN#
SUSACK#
BATLOW#
PCIE_WAKE#
AC_PRESENT_EC
SYS_RESET#
RSMRST#
DSWROK_EC_R
R278 *10K_2
R290 10K_2
R291 *10K_2
PV Change
R258 1K_2
R262 *10K_2
R19 10K_2
R100 10K_2
R106 100K_2
+3V_DEEP_SUS
+3VS5
+3V
For DS3 Sequence
For DS3 -->Ra
Non-DS3 -->Rb
RSMRST#
DPWROK_EC28
B B
PLTRST#(CLG)
R72
100K/F_2
Rb
R94 *0_2
R89 0_2
Ra
PLTRST# 24,26,28,29,31,33
DSWROK_EC_R
HW Power Good Circuit
R10479 close to CPU side
H_VCCST_PWRGD trace 0.3" - 1.5"
HWPG28,31,38,39,40
D1 MEK500V-40
21
+1.0V
R5
1K_2
H_VCCST_PWRGD_R
C10
*10P/50V_2
H_VCCST_PWRGD
+1.0V +3VS5+5VS5
R2
15K/F_4
R1
100K_2
2
1 3
+1.0V_PWRGD_G1
C1
0.1U/10V_2
R3
100K_2
+1.0V_PWRGD_G2
Q1
MMBT3904T-7-F
SI Change
R168
10K_2
R167
100K_2R4 60.4_4
HWPG
3
2
Q2
DMG1012T-7
1
System PWR_OK(CLG)
A A
R15 *0_2/S
5
EC_PWROKSYS_PWROK
R18
10K/F_2
PROJECT : X31
PROJECT : X31
PROJECT : X31
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
NB5
NB5
NB5
Date: Sheet of
Date: Sheet of
4
3
2
Date: Sheet of
SKL U (3/14)
SKL U (3/14)
SKL U (3/14)
1
4 49Friday, August 05, 2016
4 49Friday, August 05, 2016
4 49Friday, August 05, 2016
I'm from VIETNAM sualaptop365
5
4
3
2
1
?
SKL_ULT
+VCC_CORE
Under U1
C108
C82
47U/6.3V_6
D D
22U/6.3V_6
C129
47U/6.3V_6
22U/6.3V_6
47U/6.3V_6
C142
47U/6.3V_6
C107
47U/6.3V_6
C119
47U/6.3V_6
47U/6.3V_6
C117
47U/6.3V_6
C158
47U/6.3V_6
C590
47U/6.3V_6
DB2 Add
+VCC_EDRAM
C162
C180
*1uF/6.3_2
C181
*1uF/6.3_2
C141
*1uF/6.3_2
C137
*1uF/6.3_2
C154
*1uF/6.3_2
C163
*1uF/6.3_2
*1uF/6.3_2
C C
For IRIS CPU
Reserved +vcc_edram,+vcc_eopio,+1.8v_deep_sus Power Plan
B B
+VCC_EOPIO
+VCC_EDRAM
C146
*1uF/6.3_2
C151
*1uF/6.3_2
C152
*1uF/6.3_2
C164
*1uF/6.3_2
+1.8V
R206 *0_4
C88
*1uF/6.3_2
C160
*1uF/6.3_2
C150
*1uF/6.3_2
VID0_VCC_EDRAM45
VID1_VCC_EDRAM45
50mA
3A
+V1.8S_EDRAM
VID0_VCC_EDRAM
VID1_VCC_EDRAM
3A
Del TP24,TP28
U1L
A30
VCC_A30
A34
VCC_A34
A39
VCC_A39
A44
VCC_A44
AK33
VCC_AK33
AK35
VCC_AK35
AK37
VCC_AK37
AK38
VCC_AK38
AK40
VCC_AK40
AL33
VCC_AL33
AL37
VCC_AL37
AL40
VCC_AL40
AM32
VCC_AM32
AM33
VCC_AM33
AM35
VCC_AM35
AM37
VCC_AM37
AM38
VCC_AM38
G30
VCC_G30
K32
RSVD_K32
AK32
RSVD_AK32
AB62
VCCOPC_AB62
P62
VCCOPC_P62
V62
VCCOPC_V62
H63
VCC_OPC_1P8_H63
G61
VCC_OPC_1P8_G61
AC63
VCCOPC_SENSE
AE63
VSSOPC_SENSE
AE62
VCCEOPIO
AG62
VCCEOPIO
AL63
VCCEOPIO_SENSE
AJ62
VSSEOPIO_SENSE
*SKL_ULT
REV = 1
Close U11
+VCC_CORE
C89
47U/6.3V_6
CPU POWER 1 OF 4
3A
3A
C83
47U/6.3V_6
28A
50mA
12 OF 20
C81
47U/6.3V_6
VCC_SENSE
VSS_SENSE
VIDALERT#
VCCSTG_G20
VCC_G32
VCC_G33
VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42
VCC_J30
VCC_J33
VCC_J37
VCC_J40
VCC_K33
VCC_K35
VCC_K37
VCC_K38
VCC_K40
VCC_K42
VCC_K43
VIDSCK
VIDSOUT
PDC
C84
47U/6.3V_6
?
+VCC_CORE
G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43
E32
E33
B63
H_CPU_SVIDALRT#
A63
VR_SVID_CLK_R
D64
H_CPU_SVIDDAT
G20
C186
1uF/6.3_2
C116
1uF/6.3_2
C98
1uF/6.3_2
C85
1uF/6.3_2
R215 100/F_2
R211 100/F_2
+VCCSTG
+1.8V 20,21,46
+VCCSTG 6
+VCCSTPLL 2,6,9,41,42
+VCC_CORE 44
+VCC_EOPIO 45
+VCC_EDRAM 45
C120
1uF/6.3_2
C97
1uF/6.3_2
100- ±1%
pull-up to VCC
near processor.
C182
1uF/6.3_2C112
C101
1uF/6.3_2
+VCC_CORE
VCC_SENSE 42
VSS_SENSE 42
C86
1uF/6.3_2
C95
1uF/6.3_2
C168
C133
1uF/6.3_2
1uF/6.3_2C109
C96
1uF/6.3_2C90
Layout Note:
Sense resistor should be placed within 2 inches
(50.8mm) of the processor Trace Impedance 50ohm
C87
1uF/6.3_2
C184
1uF/6.3_2
Layout note: need routing together and ALERT need between CLK and DATA.
+VCCSTPLL
CLOSE TO CPU
PLACE THE PU RESISTORS
H_CPU_SVIDALRT#
PLACE THE PU RESISTORS
CLOSE TO VR
PULL UP IS IN THE VR MODULE
VR_SVID_CLK_R
R180 220/F_4
R173 *0_4/S
+VCCSTPLL
R179
56.2/F_4
C76
*0.1U/10V_2
+VCCSTPLL
R178
*54.9/F_4
SVID ALERT
VR_SVID_ALERT# 42
SVID CLK
VR_SVID_CLK 42
05
R183
CLOSE TO CPU
PLACE THE PU RESISTORS
H_CPU_SVIDDAT
A A
5
4
3
2
100/F_4
R185 *0_4/S
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
NB5
NB5
NB5
Date: Sheet of
Date: Sheet of
Date: Sheet of
SVID DATA
VR_SVID_DATA 42
PROJECT : X31
PROJECT : X31
PROJECT : X31
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
SKL U (4/14)
SKL U (4/14)
SKL U (4/14)
1
5 49Friday, August 05, 2016
5 49Friday, August 05, 2016
5 49Friday, August 05, 2016
I'm from VIETNAM sualaptop365
5
4
3
2
1
06
C172
1uF/6.3_2
C118
1uF/6.3_2
C14
22U/6.3V_6
R236 100/F_4
R237 100/F_4
+VCCIO
C171
1uF/6.3_2
C155
22U/6.3V_6
C9
22U/6.3V_6
+VCCIO
C11
22U/6.3V_6
+1.2VSUS
D D
C213
10U/6.3V_4
+VCCSTPLL
R8 0_4
+1.0V
R7 *0_2
C C
+1.2V_VCCPLL_OC
R311 *0_4/S
Under U11
+VCCSTG +VCCPLL_OC
C218
10U/6.3V_4
C232
10U/6.3V_4
C248
10U/6.3V_4
C228
10U/6.3V_4
+VCCSTG
+VCCPLL_OC
C199
1uF/6.3_2
C278
10U/6.3V_4
C230
1uF/6.3_2
C231
1uF/6.3_2
C286
10U/6.3V_4
Close U11 Under U11
Close to CPU
+1.2VSUS
C203
1U/6.3V_2
C205
1uF/6.3_2
+VCCSTPLL
+VCCSTG
+VCCPLL_OC
+VCCPLL
+VCCPLL+VCCSTPLL
AU23
AU28
AU35
AU42
BB23
BB32
BB41
BB47
BB51
AM40
AL23
A18
A22
K20
K21
U1N
VDDQ_AU23
VDDQ_AU28
VDDQ_AU35
VDDQ_AU42
VDDQ_BB23
VDDQ_BB32
VDDQ_BB41
VDDQ_BB47
VDDQ_BB51
VDDQC
VCCST
VCCSTG_A22
VCCPLL_OC
VCCPLL_K20
VCCPLL_K21
*SKL_ULT
REV = 1
SKL_ULT
CPU POWER 3 OF 4
2A
0.12A
0.04A
0.12A
?
3.1A
GT2 4.5A
GT3 5.1A
VCCIO_SENSE
VSSIO_SENSE
VSSSA_SENSE
VCCSA_SENSE
14 OF 20
AK28
VCCIO
AK30
VCCIO
AL30
VCCIO
AL42
VCCIO
VCCIO
VCCIO
VCCIO
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
C176
AM28
1uF/6.3_2
AM30
AM42
AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30
AM23
AM22
H21
H20
+1.0V 2,4,28,41
+VCCIO 2,41
+3VPCU 13,23,25,26,28,31,37,38,45,47
+VCCSA 42,44
+VCCSTG 5
+1.2VSUS 3,16,17,18,39,41
+VCCSTPLL 2,5,9,41,42
+1.2V_VCCPLL_OC 41
+VCCSA
C140
1uF/6.3_2
VCCIO_VCCSENSE
VCCIO_VSSSENSE
C175
1uF/6.3_2
C114
1uF/6.3_2
C179
C174
47U/6.3V_6
1uF/6.3_2
C123
C135
1U/6.3V_2
1uF/6.3_2
C2
22U/6.3V_6
VSSSA_SENSE 42
VCCSA_SENSE 42
C170
1uF/6.3_2
C147
1U/6.3V_2
C139
22U/6.3V_6
C173
1uF/6.3_2
C130
1U/6.3V_2
VCCIO_VCCSENSE
VCCIO_VSSSENSE
C20
1U/6.3V_2
C243
1uF/6.3_2
C273
10U/6.3V_4
C274
10U/6.3V_4
C264
10U/6.3V_4
C271
10U/6.3V_4
C252
10U/6.3V_4
C250
10U/6.3V_4
C210
1uF/6.3_2
C197
1uF/6.3_2
C226
1uF/6.3_2
C196
1uF/6.3_2
Close A18 Ball
+VCCSTPLL
B B
C67
C77
22U/6.3V_6
1U/6.3V_2
Close U11
+VCCPLL+VCCSTPLL
C72
1U/6.3V_2
A A
C73
1uF/6.3_2
5
For 65 degree, 1.8v limit, (SW)
R155
20K/F_2
R25
100K_4 NTC
C63
0.1U/10V_2
+3VPCU +3VPCU+3VPCU
R147
20K/F_2
For 75 degree, 1.2v limit, (HW) For 75 degree, 1.2v limit, (HW)For 75 degree, 1.2v limit, (HW)
THRM_MOINTOR2 28 THRM_MOINTOR3 28THRM_MOINTOR1 28
R241
100K_4 NTC
4
C58
0.1U/10V_2
SSD Ther ProtectCHOCK Ther Protect DDR Ther Protect
R154
20K/F_2
R507
100K_4 NTC
C66
0.1U/10V_2
PROJECT : X31
PROJECT : X31
PROJECT : X31
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
NB5
NB5
NB5
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
SKL U (5/14)
SKL U (5/14)
SKL U (5/14)
1
6 49Friday, August 05, 2016
6 49Friday, August 05, 2016
6 49Friday, August 05, 2016
I'm from VIETNAM sualaptop365
5
4
3
2
1
?
SKL_ULT
57A
PDC
13 OF 20
Need apply PN
VCCGTX_AK42
VCCGTX_AK43
VCCGTX_AK45
VCCGTX_AK46
7A
VCCGTX_AK48
VCCGTX_AK50
VCCGTX_AK52
VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60
VCCGTX_AK70
VCCGTX_AL43
VCCGTX_AL46
VCCGTX_AL50
VCCGTX_AL53
VCCGTX_AL56
VCCGTX_AL60
VCCGTX_AM48
VCCGTX_AM50
VCCGTX_AM52
VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58
VCCGTX_AU58
VCCGTX_AU63
VCCGTX_BB57
VCCGTX_BB66
VCCGTX_SENSE
VSSGTX_SENSE
AA63
AA64
AA66
AA67
AA69
AA70
AA71
AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71
M62
N63
N64
N66
N67
N69
A48
A53
A58
A62
A66
J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60
K48
K50
K52
K53
K55
K56
K58
K60
L62
L63
L64
L65
L66
L67
L68
L69
L70
L71
J70
J69
U1M
CPU POWER 2 OF 4
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT_SENSE
VSSGT_SENSE
*SKL_ULT
REV = 1
+VCCGT
C161
1uF/6.3_2
C148
47U/6.3V_6
D D
C C
B B
47U/6.3V_6
C111
22U/6.3V_6
C131
1uF/6.3_2
C125
1uF/6.3_2
47U/6.3V_6
C103
22U/6.3V_6
C127
1uF/6.3_2
VCCGT_SENSE42
VSSGT_SENSE42
C128
1uF/6.3_2
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62
AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66
AK62
AL61
+VCCGT
C143
47U/6.3V_6C102
C591
47U/6.3V_6C149
C144
47U/6.3V_6
DB2 Add
C138
47U/6.3V_6
+VCC_GTX
C191
47U/6.3V_6
C183
*47U/6.3V_6
+VCC_GTX +VCCGT
C106
47U/6.3V_6
C177
*47U/6.3V_6
C110
47U/6.3V_6
Close U11
R238 *0_8
R232 *0_8
C190
47U/6.3V_6
C178
*22U/6.3V_6
C122
47U/6.3V_6
C189
47U/6.3V_6
For IRIS CPU
Reserved +VCC_GTX
+VCCGT 42,43
07
A A
PROJECT : X31
PROJECT : X31
PROJECT : X31
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
NB5
NB5
NB5
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
SKL U (6/14)
SKL U (6/14)
SKL U (6/14)
1
7 49Friday, August 05, 2016
7 49Friday, August 05, 2016
7 49Friday, August 05, 2016
I'm from VIETNAM sualaptop365
5
4
3
2
1
08
AT63
AT68
AT71
AU10
AU15
AU20
AU32
AU38
AV68
AV69
AV70
AV71
AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57
AW6
AW60
AW62
AW64
AW66
AW8
AY66
BA10
BA14
BA18
BA23
BA28
BA32
BA36
BA45
U1Q
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AV1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B10
VSS
B14
VSS
B18
VSS
B22
VSS
B30
VSS
B34
VSS
B39
VSS
B44
VSS
B48
VSS
B53
VSS
B58
VSS
B62
VSS
B66
VSS
B71
VSS
BA1
VSS
VSS
VSS
VSS
BA2
VSS
VSS
VSS
VSS
VSS
F68
VSS
VSS
*SKL_ULT
REV = 1
SKL_ULT
GND 2 OF 3
?
17 OF 20
Need apply PNNeed apply PN
BA49
VSS
BA53
VSS
BA57
VSS
BA6
VSS
BA62
VSS
BA66
VSS
BA71
VSS
BB18
VSS
BB26
VSS
BB30
VSS
BB34
VSS
BB38
VSS
BB43
VSS
BB55
VSS
BB6
VSS
BB60
VSS
BB64
VSS
BB67
VSS
BB70
VSS
C1
VSS
C25
VSS
C5
VSS
D10
VSS
D11
VSS
D14
VSS
D18
VSS
D22
VSS
D25
VSS
D26
VSS
D30
VSS
D34
VSS
D39
VSS
D44
VSS
D45
VSS
D47
VSS
D48
VSS
D53
VSS
D58
VSS
D6
VSS
D62
VSS
D66
VSS
D69
VSS
E11
VSS
E15
VSS
E18
VSS
E21
VSS
E46
VSS
E50
VSS
E53
VSS
E56
VSS
E6
VSS
E65
VSS
E71
VSS
F1
VSS
F13
VSS
F2
VSS
F22
VSS
F23
VSS
F27
VSS
F28
VSS
F32
VSS
F33
VSS
F35
VSS
F37
VSS
F38
VSS
F4
VSS
F40
VSS
F42
VSS
BA41
VSS
PDC
?
AA65
AA68
AB15
AB16
AB18
AB21
AD13
AD16
AD19
AD20
AD21
AD62
AE64
AE65
AE66
AE67
AE68
AE69
AF10
AF15
AF17
AF63
AG16
AG17
AG18
AG19
AG20
AG21
AG71
AH13
AH63
AH64
AH67
AJ15
AJ18
AJ20
AK11
AK16
AK18
AK21
AK22
AK27
AK63
AK68
AK69
AL28
AL32
AL35
AL38
AL45
AL48
AL52
AL55
AL58
AL64
A67
A70
AA2
AA4
AB8
AD8
AF1
AF2
AF4
AH6
AJ4
AK8
AL2
AL4
U1P
A5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
*SKL_ULT
REV = 1
SKL_ULT
GND 1 OF 3
Need apply PN
?
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
16 OF 20
?
AL65
AL66
AM13
AM21
AM25
AM27
AM43
AM45
AM46
AM55
AM60
AM61
AM68
AM71
AM8
AN20
AN23
AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48
AR5
AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58
U1R
?
D D
C C
B B
SKL_ULT
GND 3 OF 3
F8
VSS
G10
VSS
G22
VSS
G43
VSS
G45
VSS
G48
VSS
G5
VSS
G52
VSS
G55
VSS
G58
VSS
G6
VSS
G60
VSS
G63
VSS
G66
VSS
H15
VSS
H18
VSS
H71
VSS
J11
VSS
J13
VSS
J25
VSS
J28
VSS
J32
VSS
J35
VSS
J38
VSS
J42
VSS
J8
VSS
K16
VSS
K18
VSS
K22
VSS
K61
VSS
K63
VSS
K64
VSS
K65
VSS
K66
VSS
K67
VSS
K68
VSS
K70
VSS
K71
VSS
L11
VSS
L16
VSS
L17
VSS
18 OF 20
*SKL_ULT
REV = 1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21
?
A A
PROJECT : X31
PROJECT : X31
PROJECT : X31
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
NB5
NB5
NB5
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
SKL U (7/14)
SKL U (7/14)
SKL U (7/14)
1
8 49Friday, August 05, 2016
8 49Friday, August 05, 2016
8 49Friday, August 05, 2016
I'm from VIETNAM sualaptop365
5
4
3
2
1
09
?
U1S
E68
D D
+1.0V_DEEP_SUS
C C
B B
R214 49.9/F_2
R193 *1K_2
CFG_RCOMP
CFG3
CFG4
AL25
AL27
BA70
BA68
B67
D65
D67
E70
C68
D68
C67
F71
G69
F70
G68
H70
G71
H69
G70
E63
F63
E66
F66
E60
E8
AY2
AY1
D1
D3
K46
K45
C71
B70
F60
A52
J71
J68
F65
G65
F61
E61
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
CFG[18]
CFG[19]
CFG_RCOMP
ITP_PMODE
RSVD_AY2
RSVD_AY1
RSVD_D1
RSVD_D3
RSVD_K46
RSVD_K45
RSVD_AL25
RSVD_AL27
RSVD_C71
RSVD_B70
RSVD_F60
RSVD_A52
RSVD_TP_BA70
RSVD_TP_BA68
RSVD_J71
RSVD_J68
VSS_F65
VSS_G65
RSVD_F61
RSVD_E61
*SKL_ULT
REV = 1
SKL_ULT
RESERVED SIGNALS-1
PDC
19 OF 20
RSVD_TP_BB68
RSVD_TP_BB69
RSVD_TP_AK13
RSVD_TP_AK12
RSVD_BB2
RSVD_BA3
RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2
RSVD_B3
RSVD_A3
RSVD_AW1
RSVD_E1
RSVD_E2
RSVD_BA4
RSVD_BB4
RSVD_A4
RSVD_C4
RSVD_A69
RSVD_B69
RSVD_AY3
RSVD_D71
RSVD_C70
RSVD_C54
RSVD_D54
VSS_AY71
ZVM#
RSVD_TP_AW71
RSVD_TP_AW70
MSM#
PROC_SELECT#
TP5
TP6
TP4
TP1
TP2
?
BB68
BB69
AK13
AK12
BB2
BA3
AU5
AT5
D5
D4
B2
C2
B3
A3
AW1
E1
E2
BA4
BB4
A4
C4
BB5
A69
B69
AY3
R255 *0_2/S
D71
C70
C54
D54
AY4
BB3
AY71
R243 *0_2/S
AR56
AW71
AW70
AP56
C64
R169 *100K_2
0112 unmount
Co-lay for
Cannonlake
+1.8V_DEEP_SUS
LP# 45
DB2 Add
+VCCSTPLL
R221 *0_2
C104
*1uF/6.3_2
AW69
AW68
AU56
AW48
C7
U12
U11
H11
?
SKL_ULT
U1T
SPARE
RSVD_AW69
RSVD_AW68
RSVD_AU56
RSVD_AW48
RSVD_C7
RSVD_U12
RSVD_U11
RSVD_H11
*SKL_ULT
REV = 1
+VCCSTPLL 2,5,6,41,42
+1.0V_DEEP_SUS 13,15,40,41
+1.8V_DEEP_SUS 15,37,40,46
20 OF 20
RSVD_F6
RSVD_E3
RSVD_C11
RSVD_B11
RSVD_A11
RSVD_D12
RSVD_C12
RSVD_F52
F6
E3
C11
B11
A11
D12
C12
F52
?
Processor Strapping
CFG3
(Physcial Debug Enable)
DFX Privacy
CFG4
(DP Presence Strap)
A A
5
The CFG signals have a default value of '1' if not terminated on the board.
1 0
Disable: Enable: Set DFX Enable in DFX interface MSR
Disable; No physical DP attached to eDP
4
Enable; An ext DP device is connected to eDP
3
CFG3
CFG4
Circuit
R199 *1K_2
R204 1K_2
PROJECT : X31
PROJECT : X31
PROJECT : X31
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
NB5
NB5
NB5
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
SKL U (8/14)
SKL U (8/14)
SKL U (8/14)
1
9 49Friday, August 05, 2016
9 49Friday, August 05, 2016
9 49Friday, August 05, 2016
I'm from VIETNAM sualaptop365
5
4
3
2
1
10
?
U1E
SPI - FLASH
AW3
AW2
AW13
AY11
AV2
AV3
AU4
AU3
AU2
AU1
M2
M3
J4
V1
V2
M1
G3
G2
G1
SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_IO2
SPI0_IO3
SPI0_CS0#
SPI0_CS1#
SPI0_CS2#
SPI - TOUCH
GPP_D1/SPI1_CLK
GPP_D2/SPI1_MISO
GPP_D3/SPI1_MOSI
GPP_D21/SPI1_IO2
GPP_D22/SPI1_IO3
GPP_D0/SPI1_CS#
C LINK
CL_CLK
CL_DATA
CL_RST#
GPP_A0/RCIN#
GPP_A6/SERIRQ
*SKL_ULT
TP1
TP4
TP3
TP2
Support Vpro
EC_RCIN#28
SERIRQ24,28
PCH_SPI1_CLK
PCH_SPI1_SO
PCH_SPI1_SI
PCH_SPI_IO2
PCH_SPI_IO3
PCH_SPI_CS0#
SPI1_CLK
SPI1_MISO
PCI_SERR#
SPI1_IO2
SPI1_IO3
SPI1_CS#
CL_CLK26
CL_DAT26
CL_RST#26
D D
PCI_SERR#28
C C
SKL_ULT
+3V 2,4,11,12,13,14,15,19,20,21,22,24,25,27,28,29,33,42,46
+3V_DEEP_SUS 4,11,12,14,15,30
LPC
PDC
5 OF 20REV = 1
Need apply PN
SMBUS, SMLINK
GPP_A14/SUS_STAT#/ESPI_RESET#
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C2/SMBALERT#
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C5/SML0ALERT#
GPP_C6/SML1CLK
GPP_C7/SML1DATA
GPP_B23/SML1ALERT#/PCHHOT#
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
GPP_A5/LFRAME#/ESPI_CS#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
GPP_A10/CLKOUT_LPC1
GPP_A8/CLKRUN#
?
R7
SMB_PCH_CLK
R8
SMB_PCH_DAT
R10
SML0ALERT#
R9
SMB_ME0_CLK
W2
SMB_ME0_DAT
W1
SML1ALERT#
W3
SMB_ME1_CLK
V3
SMB_ME1_DAT
AM7
AY13
BA13
BB13
AY12
BA12
BA11
AW9
CLK_PCI_EC_R
AY9
CLK_PCI_LPC_R
AW11
CLKRUN#
SML0ALERT# 11
SML1ALERT# 11
LAD0 24,26,28
LAD1 24,26,28
LAD2 24,26,28
LAD3 24,26,28
LFRAME# 24,26,28
CLKRUN# 28
R99 22/F_2
R92 22/F_2
R91 22/F_2
EC4 18P/50V_4
EC3 18P/50V_4
EC2
18P/50V_4
CLK_24M_KBC 28
CLK_24M_DEBUG 26
EMI(near PCH)
CLK_PCI_TPM 24
EMI(near PCH)
GPIO Pull UP
PCH SPI ROM(CLG)
P/NVender Size
+3V
SERIRQ
CLKRUN#
SPI1_MISO
EC_RCIN#
PCI_SERR#
B B
R270 10K_2
R284 8.2K/F_4
R22 10K_2
R257 10K_2
R21 10K_2
SMB_PCH_CLK
SMB_PCH_DAT
SMB_ME0_CLK
SMB_ME0_DAT
SMB_ME1_CLK
SMB_ME1_DAT
R190 2.2K_2
R189 2.2K_2
R28 2.2K_2
R46 2.2K_2
R33 1K_2
R37 1K_2
+3V_DEEP_SUS
GigaDevice
Socket
SMBus/Pull-up(CLG)
R184 4.7K_4
+3V
SMB_RUN_DAT25
R174 4.7K_4
+3V
SMB_RUN_CLK25
A A
I'm from VIETNAM sualaptop365
5
Q5
4 3
1
2N7002KDW
+3V
5
SMB_PCH_DAT
2
6
SMB_PCH_CLK
Touch Pad
XDP
LPDDR3 thermal sensor
4
3
8MB
AKE3EFP0N07 (W25Q64FVSSIQ)Winbond
8MB
AKE2EZN0Q00 (GD25B64CSIGR)
8MB
Mxic 8MB AKE3EZ-0Z00 (MX25L6473FM2I-08G)
DFHS08FS023
PCH_SPI_CS0#_R
TP15
PCH_SPI1_CLK_R
TP21
PCH_SPI1_SI_R
TP15-24 need place to BOT
R364/R330/R341/R374/R323/R380 close to U11
TP23
TP17
TP24
TP22
C288 1uF/6.3_2
PCH_SPI1_SO_R
BIOS_WP#
HOLD#
PCH_SPI_CS0#
PCH_SPI1_CLK
+3V_DEEP_SUS
PCH_SPI_IO2
R364 15/F_2
R330 15/F_2
R341 15/F_2
R374 15/F_2
R380 1K_2
R382 15/F_2
2
PCH_SPI_CS0#_R
PCH_SPI1_CLK_R
PCH_SPI1_SI_RPCH_SPI1_SI
PCH_SPI1_SO_RPCH_SPI1_SO
C297
22P/25V_2
BIOS_WP#
PCH_SPI_CS0#_R28
PCH_SPI1_CLK_R28
PCH_SPI1_SI_R28
PCH_SPI1_SO_R28
+3V_DEEP_SUS
U11
1
CE#
6
SCK
5
SI
2
SO
3
WP#
GD25B64BSIGR
AKE3EFP0N07
PCH_SPI_CS0#_R
PCH_SPI1_CLK_R
PCH_SPI1_SI_R
PCH_SPI1_SO_R
8
+3V_DEEP_SUS
VDD
HOLD#
VSS
NB5
NB5
NB5
R323 1K_2
7
HOLD#
R326 15/F_2
4
PCH_SPI_IO3
PROJECT : X31
PROJECT : X31
PROJECT : X31
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
SKL U (9/14)
SKL U (9/14)
SKL U (9/14)
1
C298
0.1U/10V_2
10 49Tuesday, August 09, 2016
10 49Tuesday, August 09, 2016
10 49Tuesday, August 09, 2016
5
4
3
2
1
11
D D
DESIGN NOTE:
WEAK PULL UP RESISTOR PRESENT ON THIS NET
ACZ_SPKR14,20
C C
B B
GSPI1_MOSI14
ACZ_SPKR
GSPI1_MOSI
R95
*20K/F_2
+3V_DEEP_SUS
R200
1K_2
R209
*20K/F_2
R226
*20K/F_2
Functional Strap Definitions
TOP SWAP OVERRIDE
HIGH - TOP SWAP ENABLE
LOW-DISABLED
HIGH: LPC SELECTED FOR SYSTEM FLASH
WEAK INTERNAL PD
No Boot:
The signal has a weak internal pull-down.
0 = Disable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (no confidentiality).
1 = Enable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (with confidentiality). Must be
pulled up to support Intel AMT with TLS and Intel
SBA (Small Business Advantage) with TLS.
+3V 2,4,10,12,13,14,15,19,20,21,22,24,25,27,28,29,33,42,46
+3V_DEEP_SUS 4,10,12,14,15,30
No Boot:
The signal has a weak internal pull-down.
This field determines the destination of accesses to the
BIOS memory range. Also controllable using Boot BIOS
Destination bit (Chipset Configuration Registers: Offset
3410h:Bit 10). This strap is used in conjunction with Boot
BIOS Destination Selection 0 strap.
Bit 10 Boot BIOS Destination
0 SPI
1 LPC
ACZ_SDOUT14
GPIO33_EC28
GPP_B1814SML0ALERT#10
SML1ALERT#10
ACZ_SDOUT
R90 1K_2
GPP_B18SML0ALERT#
SML1ALERT#
+3V_DEEP_SUS
R85
*4.7K_2
ACZ_SDOUT
+3V
R70
*4.7K_2
R71
10K_2
+3V_DEEP_SUS
R39
*10K_2
R40
20K/F_2
No Boot:
The signal has a weak internal pull-down.
0 = Enable security measures defined in the Flash
Descriptor.
1 = Disable Flash Descriptor Security (override). This
strap should only be asserted high using external
pull-up in manufacturing/debug environments ONLY.
This function is useful when running ITP/XDP.
No Boot:
The signal has a weak internal pull-down.
0 = Disable No Reboot mode.
1 = Enable No Reboot mode
(PCH will disable the TCO
Timer system reboot feature).
This function is useful when running ITP/XDP.
No Boot:
The signal has a weak internal pull-down.
0 = LPC Is selected for EC.
1 = eSPI Is selected for EC.
A A
PROJECT : X31
PROJECT : X31
PROJECT : X31
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
NB5
NB5
NB5
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
SKL U (10/14)
SKL U (10/14)
SKL U (10/14)
1
11 49Friday, August 05, 2016
11 49Friday, August 05, 2016
11 49Friday, August 05, 2016
I'm from VIETNAM sualaptop365
5
D D
WLAN
Thunderbolt
C C
PCIE_SSD
PCIE_SSD
B B
PCIE_RXN2_WLAN26
PCIE_RXP2_WLAN26
PCIE_TXN2_WLAN26
PCIE_TXP2_WLAN26
PCIE_RXN5_TBT29
PCIE_RXP5_TBT29
PCIE_TXN5_TBT29
PCIE_TXP5_TBT29
PCIE_RXN6_TBT29
PCIE_RXP6_TBT29
PCIE_TXN6_TBT29
PCIE_TXP6_TBT29
PCIE_RXN7_TBT29
PCIE_RXP7_TBT29
PCIE_TXN7_TBT29
PCIE_TXP7_TBT29
PCIE_RXN8_TBT29
PCIE_RXP8_TBT29
PCIE_TXN8_TBT29
PCIE_TXP8_TBT29
PCIE_RXN9_SSD24
PCIE_RXP9_SSD24
PCIE_TXN9_SSD24
PCIE_TXP9_SSD24
PCIE_RXN10_SSD24
PCIE_RXP10_SSD24
PCIE_TXN10_SSD24
PCIE_TXP10_SSD24
+3V_DEEP_SUS
PCIE11_SATA1B_RXN24
PCIE11_SATA1B_RXP24
PCIE11_SATA1B_TXN24
PCIE11_SATA1B_TXP24
PCIE12_SATA2_RXN24
PCIE12_SATA2_RXP24
PCIE12_SATA2_TXN24
PCIE12_SATA2_TXP24
C15 0.1U/10V_2
C16 0.1U/10V_2
C4 0.22uF/10V_2
C3 0.22uF/10V_2
C18 0.22uF/10V_2 R20 *10K_2
C17 0.22uF/10V_2
C5 0.22uF/10V_2
C6 0.22uF/10V_2
C8 0.22uF/10V_2
C7 0.22uF/10V_2
R292 10K_2
PCI-E Port Mapping Table
PCI-E Port
Port1
Port2
Port3
Port4
Port5
Port6
Port7
A A
Port8
Port9
Port10
Port11
Port12
5
Function
Un-used
WLAN
Un-used
Un-used Un-used
Thunderbolt
Thunderbolt
Thunderbolt
Thunderbolt
SSD HDD
SSD HDD
SSD HDD
SSD HDD
CLK RQ Port
Port0
Port1
Port2
Port3
Port4
Port5
Function
Un-used
Un-used
WLAN
Thunderbolt
SSD HDD
4
PCIE_TXN2_WLAN_C
PCIE_TXP2_WLAN_C
PCIE_TXN5_TBT_C
PCIE_TXP5_TBT_C
PCIE_TXN6_TBT_C
PCIE_TXP6_TBT_C
PCIE_TXN7_TBT_C
PCIE_TXP7_TBT_C
PCIE_TXN8_TBT_C
PCIE_TXP8_TBT_C
R202 100/F_2
PIRQA#
4
U1H
PCIE/USB3/SATA
H13
PCIE1_RXN/USB3_5_RXN
G13
PCIE1_RXP/USB3_5_RXP
B17
PCIE1_TXN/USB3_5_TXN
A17
PCIE1_TXP/USB3_5_TXP
G11
PCIE2_RXN/USB3_6_RXN
F11
PCIE2_RXP/USB3_6_RXP
D16
PCIE2_TXN/USB3_6_TXN
C16
PCIE2_TXP/USB3_6_TXP
H16
PCIE3_RXN
G16
PCIE3_RXP
D17
PCIE3_TXN
C17
PCIE3_TXP
G15
PCIE4_RXN
F15
PCIE4_RXP
B19
PCIE4_TXN
A19
PCIE4_TXP
F16
PCIE5_RXN
E16
PCIE5_RXP
C19
PCIE5_TXN
D19
PCIE5_TXP
G18
PCIE6_RXN
F18
PCIE6_RXP
D20
PCIE6_TXN
C20
PCIE6_TXP
F20
PCIE7_RXN/SATA0_RXN
E20
PCIE7_RXP/SATA0_RXP
B21
PCIE7_TXN/SATA0_TXN
A21
PCIE7_TXP/SATA0_TXP
G21
PCIE8_RXN/SATA1A_RXN
F21
PCIE8_RXP/SATA1A_RXP
D21
PCIE8_TXN/SATA1A_TXN
C21
PCIE8_TXP/SATA1A_TXP
E22
PCIE9_RXN
E23
PCIE9_RXP
B23
PCIE9_TXN
A23
PCIE9_TXP
F25
PCIE10_RXN
E25
PCIE10_RXP
D23
PCIE10_TXN
C23
PCIE10_TXP
F5
PCIE_RCOMPN
E5
PCIE_RCOMPP
D56
PROC_PRDY#
D61
PROC_PREQ#
BB11
GPP_A7/PIRQA#
E28
PCIE11_RXN/SATA1B_RXN
E27
PCIE11_RXP/SATA1B_RXP
D24
PCIE11_TXN/SATA1B_TXN
C24
PCIE11_TXP/SATA1B_TXP
E30
PCIE12_RXN/SATA2_RXN
F30
PCIE12_RXP/SATA2_RXP
A25
PCIE12_TXN/SATA2_TXN
B25
PCIE12_TXP/SATA2_TXP
*SKL_ULT
REV = 1
?
SKL_ULT
SSIC / USB3
USB2
GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
PDC
8 OF 20
+3V 2,4,10,11,13,14,15,19,20,21,22,24,25,27,28,29,33,42,46
+3V_DEEP_SUS 4,10,11,14,15,30
USB3.0 Port Mapping Table
USB3.0 Function
PORT-1
PORT-2
USB3.0 MB-1
NC
PORT-3
PORT-4 NC
3
USB3_1_RXN
USB3_1_RXP
USB3_1_TXN
USB3_1_TXP
USB3_2_RXN/SSIC_1_RXN
USB3_2_RXP/SSIC_1_RXP
USB3_2_TXN/SSIC_1_TXN
USB3_2_TXP/SSIC_1_TXP
USB3_3_RXN/SSIC_2_RXN
USB3_3_RXP/SSIC_2_RXP
USB3_3_TXN/SSIC_2_TXN
USB3_3_TXP/SSIC_2_TXP
USB3_4_RXN
USB3_4_RXP
USB3_4_TXN
USB3_4_TXP
USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9
USB2P_9
USB2N_10
USB2P_10
USB2_COMP
USB2_VBUSSENSE
GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2
GPP_E8/SATALED#
?
3
USB2_ID
H8
G8
C13
D13
J6
H6
B13
A13
J10
H10
B15
A15
E10
F10
C15
D15
AB9
AB10
AD6
AD7
AH3
AJ3
AD9
AD10
AJ1
AJ2
AF6
AF7
AH1
AH2
AF8
AF9
AG1
AG2
AH7
AH8
AB6
USB2_COMP
AG3
AG4
A9
OC0#
C9
TS_OFF
D9
TS_INT#
B9
J1
TBT_FORCE_PWR
J2
DEVSLP1
J3
H2
GPIO34
H3
GPIO35
G4
GPIO36
H1
SATA_LED#
USB30_RX1USB30_RX1+
USB30_TX1USB30_TX1+
USBP1USBP1+
USBP5USBP5+
USBP6USBP6+
USBP7USBP7+
USBP8USBP8+
R47 113/F_2
R79 *0_2/S
2
USB30_RX1- 23
USB30_RX1+ 23
USB30_TX1- 23
USB30_TX1+ 23
USBP1- 23
USBP1+ 23
USBP5- 24
USBP5+ 24
USBP6- 24
USBP6+ 24
USBP7- 26
USBP7+ 26
USBP8- 19
USBP8+ 19
Daughter Board
Daughter Board
HD Camera
IR Camera
BT
OLED Touch Screen
SI Change
PLACE 'R326' WITHIN 500 MILS
FROM USB2_COMP PIN WITH
TRACE IMPEDANCE LESS THAN 0.5 OHMS
TS_OFF 19
TS_INT# 19
TS_RST 19
TBT_FORCE_PWR 29
DEVSLP1 24
GPIO34 24
GPIO35 24
GPIO36 24
USB2.0 Port Mapping Table
USB2.0 Function
2
USB3.0 MB-1
NC
NC
NC
HD Camera
IR Camera
WLAN
OLED Touch ScreenNC
NC
NC
NB5
NB5
NB5
PORT-1
PORT-2
PORT-3
PORT-4
PORT-5
PORT-6
PORT-7
PORT-8
PORT-9
PORT-10
1
12
+3V
TS_OFF
TS_INT#
TS_RST
SATA_LED#
GPIO34
GPIO35
GPIO36
GPIO34
GPIO35
GPIO36
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
R6 *10K_2
R17 10K_2
R13 10K_2
R205 10K_2
R216 10K_2
R203 10K_2
R207 *10K_2
R213 *10K_2
R201 *10K_2
+3V_DEEP_SUS
OC0#
R186 10K_2
Un-used OC# need add pull high
PROJECT : X31
PROJECT : X31
PROJECT : X31
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
1
for ERD check
12 49Friday, August 05, 2016
12 49Friday, August 05, 2016
12 49Friday, August 05, 2016
SKL U (11/14)
SKL U (11/14)
SKL U (11/14)
I'm from VIETNAM sualaptop365
5
4
3
2
1
13
?
U1J
D42
CLKOUT_PCIE_N0
C42
CLKOUT_PCIE_P0
D D
WLAN
Thunderbolt
SSD
CLK_PCIE_WLANN26
CLK_PCIE_WLANP26
PCIE_CLKREQ_WLAN#26
CLK_PCIE_TBTN29
CLK_PCIE_TBTP29
PCIE_CLKREQ_TBT#29
CLK_PCIE_SSDN24
CLK_PCIE_SSDP24
PCIE_CLKREQ_SSD#24
PCIE_CLKREQ0#
PCIE_CLKREQ1#
CLK_PCIE_WLANN
CLK_PCIE_WLANP
PCIE_CLKREQ_WLAN#
PCIE_CLKREQ3#
PCIE_CLKREQ_TBT#
PCIE_CLKREQ_SSD#
AR10
GPP_B5/SRCCLKREQ0#
B42
CLKOUT_PCIE_N1
A42
CLKOUT_PCIE_P1
AT7
GPP_B6/SRCCLKREQ1#
D41
CLKOUT_PCIE_N2
C41
CLKOUT_PCIE_P2
AT8
GPP_B7/SRCCLKREQ2#
D40
CLKOUT_PCIE_N3
C40
CLKOUT_PCIE_P3
AT10
GPP_B8/SRCCLKREQ3#
B40
CLKOUT_PCIE_N4
A40
CLKOUT_PCIE_P4
AU8
GPP_B9/SRCCLKREQ4#
E40
CLKOUT_PCIE_N5
E38
CLKOUT_PCIE_P5
AU7
GPP_B10/SRCCLKREQ5#
*SKL_ULT
REV = 1
SKL_ULT
CLOCK SIGNALS
10 OF 20
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
GPD8/SUSCLK
XTAL24_IN
XTAL24_OUT
XCLK_BIASREF
RTCX1
RTCX2
SRTCRST#
RTCRST#
TBT
+1.0V_DEEP_SUS
F43
E43
BA17
E37
E35
E42
AM18
AM20
AN18
AM16
PCH_SUSCLK
XTAL24_IN
XTAL24_OUT
XCLK_BIASREF
RTC_X1
RTC_X2
SRTC_RST#
RTC_RST#
PCH_SUSCLK 24,26
XCLK_BIASREF
R12
2.7K/F_2
R9
*60.4/F_2
Cannonlake-U Stuff R376.
?
SKL_ULT
U1I
CSI-2
+3VPCU
+3V_RTC_1
A36
B36
C38
D38
C36
D36
A38
B38
C31
D31
C33
D33
A31
B31
A33
B33
A29
B29
C28
D28
A27
B27
C27
D27
20mils
CSI2_DN0
CSI2_DP0
CSI2_DN1
CSI2_DP1
CSI2_DN2
CSI2_DP2
CSI2_DN3
CSI2_DP3
CSI2_DN4
CSI2_DP4
CSI2_DN5
CSI2_DP5
CSI2_DN6
CSI2_DP6
CSI2_DN7
CSI2_DP7
CSI2_DN8
CSI2_DP8
CSI2_DN9
CSI2_DP9
CSI2_DN10
CSI2_DP10
CSI2_DN11
CSI2_DP11
*SKL_ULT
+BAT_RTC+3V_RTC_2
R419
0_4
D45
BAT54CW-7-F
+3V_RTC_D
REV = 1
C C
B B
RTC Clock 32.768KHz
RTC Circuitry(RTC)
Coin BAT -->Rb (default)
C35 15P/50V_4
Y2
32.768KHz
C31 15P/50V_4
A A
RTC_X1
12
R75
10M_4
RTC_X2
I'm from VIETNAM sualaptop365
5
RTC Power trace width 20mils.
+3V_RTC_0
+3V_RTC_0
R509 1K_2
CN20
1
23
RTC_CONN_2P
4
DFHD02MS223
4
?
CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3
CSI2_COMP
GPP_D4/FLASHTRIG
EMMC
GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7
GPP_F21/EMMC_RCLK
GPP_F22/EMMC_CLK
GPP_F12/EMMC_CMD
PDC
+3V 2,4,10,11,12,14,15,19,20,21,22,24,25,27,28,29,33,42,46
+3VPCU 6,23,25,26,28,31,37,38,45,47
+BAT_RTC 4,15,25,37,47
+3V_RTC_2 4,15
+1.0V_DEEP_SUS 9,15,40,41
RaRbMain BAT -->Ra
R418
*0_4
R431 20K/F_2
R490 20K/F_2
C403
1U/6.3V_2
R501 *0_2/S
9 OF 20
SRTC_RST#RTC_RST#
EMMC_RCOMP
?
C471
1U/6.3V_4
C466
1U/6.3V_2
3
RTC_RST#
SRTC_RST#
C37
D37
C32
D32
C29
D29
B26
A26
E13
B7
AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1
AM2
AM3
AP4
AT1
EMMC_RCOMP
R196 100/F_2
R81 200/F_2
RTC_RST#
3
Q17
DMG1012T-7
2
1
SI2 Del R532,Q24
R420
10K_2
External Crystal
EC_RTC_RST 28
2
CLK_REQ/Strap Pin(CLG)
PCIE_CLKREQ_TBT#
PCIE_CLKREQ_WLAN#
PCIE_CLKREQ3#
PCIE_CLKREQ1#
PCIE_CLKREQ_SSD#
PCIE_CLKREQ0#
XTAL24_IN
XTAL24_OUT
R231 10K_2
R261 10K_2
R244 10K_2
R227 10K_2
R234 10K_2
R230 10K_2
C13 27P/50V_4
1
2
R11
1M_4
4
3
C12 27P/50V_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
NB5
NB5
NB5
Date: Sheet of
Date: Sheet of
Date: Sheet of
+3V
24MHZ +-30PPM
Y1
PROJECT : X31
PROJECT : X31
PROJECT : X31
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
SKL U (12/14)
SKL U (12/14)
SKL U (12/14)
1
13 49Friday, August 05, 2016
13 49Friday, August 05, 2016
13 49Friday, August 05, 2016
5
4
3
2
1
BT_OFF
PCH_TEMPALERT#
D D
C C
KBL-U
B B
SIO_EXT_SCI#
UART2_RXD
UART2_TXD
SPK_ID_CODEC
SPK_ID_AMP
R65 10K_2
R63 *10K_2
R54 10K_2
R55 10K_2
R43 10K_2
R45 *10K_2
R51 *10K_2
R57 10K_2
R272 *10K_2
BOARD_ID8
R26 10K_2
R27 10K_2
R48 10K_2 R271 *10K_2
R52 49.9K/F_4
R60 49.9K/F_4
R225 10K_2
R224 10K_2
BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4
BOARD_ID5
BOARD_ID6
BOARD_ID7
BOARD_ID8
Model
0 VPRO
X31
1 Non VPRO
A A
0 2+2 CPU
1 2+3E CPU
5
+3V_DEEP_SUS
R59 *10K_2
R66 10K_2
R61 *10K_2
R58 *10K_2
R42 *10K_2
R44 10K_2
R53 10K_2
R50 *10K_2
R289 10K_2
BOARD_ID6
ID6ID7ID8
0 OLED
1 Nomal
DB2 Change Footprint
Touch Screen
+3V_DEEP_SUS
BOARD_ID5 BOARD_ID4
ID5 ID4
0 Normal PD
1 D Version PD
Reserve
(Default 0)
GPP_B1811
GSPI1_MOSI11
TBT_HTPLG29
SIO_EXT_SCI#28
I2C0_SDA19
I2C0_SCL19
SPK_ID_CODEC20
SPK_ID_AMP21
GPP_B18
GSPI1_MOSI
UART2_RXD
UART2_TXD
TBT_HTPLG
SIO_EXT_SCI#
I2C0_SDA
I2C0_SCL
BOARD_ID[3:0]BOARD_ID7
ID3 ID2 ID1 ID0
0
0 0
0
0 0
0
0
0
0
0
0
1
10
0 1
1 0
1 0
1 1
1 1
0 0
1 0 0
1 10
1 10
4
0
1
0
1
0
1
0
1
0
1
0
1
U1F
AN8
GPP_B15/GSPI0_CS#
AP7
GPP_B16/GSPI0_CLK
AP8
GPP_B17/GSPI0_MISO
AR7
GPP_B18/GSPI0_MOSI
AM5
GPP_B19/GSPI1_CS#
AN7
GPP_B20/GSPI1_CLK
AP5
GPP_B21/GSPI1_MISO
AN5
GPP_B22/GSPI1_MOSI
AB1
GPP_C8/UART0_RXD
AB2
GPP_C9/UART0_TXD
W4
GPP_C10/UART0_RTS#
AB3
GPP_C11/UART0_CTS#
AD1
GPP_C20/UART2_RXD
AD2
GPP_C21/UART2_TXD
AD3
GPP_C22/UART2_RTS#
AD4
GPP_C23/UART2_CTS#
U7
GPP_C16/I2C0_SDA
U6
GPP_C17/I2C0_SCL
U8
GPP_C18/I2C1_SDA
U9
GPP_C19/I2C1_SCL
AH9
GPP_F4/I2C2_SDA
AH10
GPP_F5/I2C2_SCL
AH11
GPP_F6/I2C3_SDA
AH12
GPP_F7/I2C3_SCL
AF11
GPP_F8/I2C4_SDA
AF12
GPP_F9/I2C4_SCL
*SKL_ULT
REV = 1
Hynix 8G
Samsung 8G
Micron 8G
Hynix 16G
Samsung 16G
Micron 16G
Hynix 4G
Samsung 4G
Micron 4G
LPSS ISH
Skylake (GPIO)
?
SKL_ULT
+3V 2,4,10,11,12,13,15,19,20,21,22,24,25,27,28,29,33,42,46
+3V_DEEP_SUS 4,10,11,12,15,30
+3V_DEEP_SUS
ACZ_SYNC_AUDIO20
ACZ_RST#_AUDIO20
ACZ_SDOUT_AUDIO20
BIT_CLK_AUDIO20
ACZ_SYNC
ACZ_BCLK
ACZ_SDOUT11
ACZ_SDIN020
ACZ_SPKR11,20
ACZ_SDOUT
ACZ_SDIN0
ACZ_RST#
ACZ_SPKR
3
Need apply PN
GPP_D9
GPP_D10
GPP_D11
GPP_D12
GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL
GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL
GPP_F10/I2C5_SDA/ISH_I2C2_SDA
GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
GPP_D15/ISH_UART0_RTS#
GPP_D16/ISH_UART0_CTS#/SML0BALERT#
GPP_C12/UART1_RXD/ISH_UART1_RXD
GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#
GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5
GPP_A12/BM_BUSY#/ISH_GP6
HDA Bus(CLG)
ACZ_SYNC
ACZ_SYNC
ACZ_RST#
ACZ_SDOUT
ACZ_BCLK
U1G
BA22
HDA_SYNC/I2S0_SFRM
AY22
HDA_BLK/I2S0_SCLK
BB22
HDA_SDO/I2S0_TXD
BA21
HDA_SDI0/I2S0_RXD
AY21
HDA_SDI1/I2S1_RXD
AW22
HDA_RST#/I2S1_SCLK
J5
GPP_D23/I2S_MCLK
AY20
I2S1_SFRM
AW20
I2S1_TXD
AK7
GPP_F1/I2S2_SFRM
AK6
GPP_F0/I2S2_SCLK
AK9
GPP_F2/I2S2_TXD
AK10
GPP_F3/I2S2_RXD
H5
GPP_D19/DMIC_CLK0
D7
GPP_D20/DMIC_DATA0
D8
GPP_D17/DMIC_CLK1
C8
GPP_D18/DMIC_DATA1
AW5
GPP_B14/SPKR
*SKL_ULT
R93 *1K_2
R88 33_2
R103 33_2
R111 33_2
R107 33_2
C528
*10P/50V_2
AUDIO
?6 OF 20
SKL_ULT
P2
P3
P4
P1
M4
N3
N1
N2
AD11
AD12
U1
U2
U3
U4
AC1
AC2
AC3
AB4
AY8
BA8
BB7
BA7
AY7
AW7
AP13
BT_OFF
ISH_I2C0_SDA
ISH_I2C0_SCL
ISH_I2C1_SDA
ISH_I2C1_SCL
ISH_I2C2_SDA
ISH_I2C2_SCL
PCH_TEMPALERT#
ISH_AE_INT_K
ISH_GYRO_DRDY_K
ISH_GYRO_INT_K
ISH_GP3
ISH_ACC_INT_K
DISABLE KB
EMU_LID_D
Need apply PN
?
SDIO/SDXC
GPP_A17/SD_PWR_EN#/ISH_GP7
7 OF 20REV = 1
2
BT_OFF 26
ISH_I2C0_SDA 27
ISH_I2C0_SCL 27
TP5
TP6
R266 *0_2
R260 *0_2
DISABLE KB 28
GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3
GPP_G5/SD_CD#
GPP_G6/SD_CLK
GPP_G7/SD_WP
GPP_A16/SD_1P8_SEL
SD_RCOMP
GPP_F23
?
EMU_LID_D
AB11
AB13
AB12
W12
W11
W10
W8
W7
BA9
BB9
AB7
AF13
EMU_LID_D
ISH_GYRO_DRDY
R274 *10K_2
R254 *10K_2
R288 *10K_2
ISH_AE_INT_K
ISH_GP3
ISH_GYRO_DRDY 27
ISH_GYRO_INT 27
ISH_GYRO_INT_K
ISH_ACC_INT_K
ISH_GYRO_INT
ISH_AE_INT
ISH_ACC_INT
DISABLE KB
ISH_I2C0_SDA
ISH_I2C0_SCL
ISH_I2C2_SDA
ISH_I2C2_SCL
ISH_I2C1_SDA
ISH_I2C1_SCL
I2C0_SDA
I2C0_SCL
R259 0_2
R268 *0_2
R296 0_2
R279 *0_2
R280 *10K_2
D37 MEK500V-40
Sensors Debug CONN
CN3
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
*ACES_88511-180N
BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4
BOARD_ID5
BOARD_ID6
BOARD_ID7
BOARD_ID8
R222 200/F_2
PROJECT : X31
PROJECT : X31
PROJECT : X31
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
NB5
NB5
NB5
Date: Sheet of
Date: Sheet of
Date: Sheet of
+3V_DEEP_SUS
ISH_I2C0_SCL
ISH_I2C0_SDA
ISH_I2C1_SCL
ISH_I2C1_SDA
ISH_GYRO_DRDY
ISH_GYRO_INT
ISH_AE_INT
ISH_ACC_INT
EMU_LID_D
DISABLE KB
SKL U (13/14)
SKL U (13/14)
SKL U (13/14)
1
R264 *10K_2
R283 10K_2
R273 10K_2
R299 10K_2
R256 10K_2
R23 10K_2
R24 10K_2
R62 10K_2
R64 10K_2
R217 10K_2
R212 10K_2
R218 10K_2
R219 10K_2
ISH_AE_INT 27
ISH_ACC_INT 27
EMU_LID 19,28
TP7
TP8
TP9
+3V
TP10
14 49Friday, August 05, 2016
14 49Friday, August 05, 2016
14 49Friday, August 05, 2016
14
+3V
I'm from VIETNAM sualaptop365
5
4
3
2
1
?
SKL_ULT
U1O
C145 1uF/6.3_2
+3VS5
+3V
+1.0V_DEEP_SUS
+VCCDSW_1.0V
+1.0V_DEEP_SUS
+1.0V_DEEP_SUS
+1.0V_DEEP_SUS
C166 *0.1U/10V_2
+1.0V_DEEP_SUS
+1.0V_DEEP_SUS
R78 *0_2/S
C537 *0.1U/10V_2
+3V_DEEP_SUS
+1.0V_DEEP_SUS
+3V_DEEP_SUS
+1.0V_DEEP_SUS
+1.0V_DEEP_SUS
C136 1uF/6.3_2
C29 1uF/6.3_2
C74 1uF/6.3_2
C157 1uF/6.3_2
C71 22U/6.3V_6
C78 1U/6.3V_2
R223 *0_4/S
C36 1uF/6.3_2
R233 BLM03BD601SN1
C187 0.1U/10V_2
DB2 Change
C169 1uF/6.3_2
R235 *0_4/S
C80 1uF/6.3_2
D D
PCH Internal VRM
C C
+VCCPRIM
+VCCMPHYAON_1P0
+VCCAMPHYPLL_1P0
C153 *0.1U/10V_2
+VCCAPLL_1.0V
+VCCPRIM
+V3.3DX_1.5DX_ADO
+3V_DEEP_SUS
+VCCSRAM_1.0V
+VCCPRIM_3.3V
+VCCPRIM_1.0V
+VCCAPLLEBB
AB19
AB20
AF18
AF19
AB17
AD17
AD18
AJ17
AJ19
AJ16
AF20
AF21
AJ21
AK20
P18
V20
V21
AL1
K17
L1
N15
N16
N17
P15
P16
K15
L15
V15
Y18
T19
T20
N18
REV = 1
CPU POWER 4 OF 4
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_1P0
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
VCCPRIM_CORE
DCPDSW_1P0
VCCMPHYAON_1P0
VCCMPHYAON_1P0
VCCMPHYGT_1P0_N15
VCCMPHYGT_1P0_N16
VCCMPHYGT_1P0_N17
VCCMPHYGT_1P0_P15
VCCMPHYGT_1P0_P16
VCCAMPHYPLL_1P0
VCCAMPHYPLL_1P0
VCCAPLL_1P0
VCCPRIM_1P0_AB17
VCCPRIM_1P0_Y18
VCCDSW_3P3_AD17
VCCDSW_3P3_AD18
VCCDSW_3P3_AJ17
VCCHDA
VCCSPI
VCCSRAM_1P0
VCCSRAM_1P0
VCCSRAM_1P0
VCCSRAM_1P0
VCCPRIM_3P3_AJ21
VCCPRIM_1P0_AK20
VCCAPLLEBB
*SKL_ULT
2.899A
0.03A
2.57A
1.714A
0.09A
15 OF 20
VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE
VCCPGPPF
VCCPGPPG
VCCPRIM_3P3_V19
VCCPRIM_1P0_T1
VCCATS_1P8
VCCRTCPRIM_3P3
VCCRTC_AK19
VCCRTC_BB14
DCPRTC
VCCCLK1
VCCCLK2
VCCCLK3
VCCCLK4
VCCCLK5
VCCCLK6
GPP_B0/CORE_VID0
GPP_B1/CORE_VID1
?
AK15
AG15
Y16
Y15
T16
AF16
AD15
V19
T1
AA1
AK17
AK19
BB14
BB10
A14
K19
L21
N20
L19
A10
AN11
AN13
+VCCPGPPA
+VCCPGPPB
+VCCPGPPC
+VCCPGPPD
+VCCPGPPE
+VCCPGPPF
+VCCPGPPG
+VCCPRIM_1.0V_T1
+VCCATS_1.8V
+VCCRTCPRIM_3.3V
VCCRTC
DCPRTC
+VCCCLK1
+VCCCLK2
+VCCCLK3
+VCCCLK4
+VCCCLK5
+VCCCLK6
CORE_VID0
CORE_VID1
C156 1uF/6.3_2
R285 0_4
R286 *0_4
C198 0.1U/10V_2
C79 1uF/6.3_2
TP19
TP20
Rb
Ra
+3V_DEEP_SUS
+1.0V_DEEP_SUS
+1.8V_DEEP_SUS
+3V_DEEP_SUS
+3V_RTC_2
+BAT_RTC
+1.0V_DEEP_SUS
Main BAT -->Ra
Coin BAT -->Rb (default)
+VCCPGPPB +VCCPGPPC +VCCPGPPE
+VCCATS_1.8V
C188
1uF/6.3_2
C124
1uF/6.3_2
+VCCPGPPA
+VCCPGPPB
+VCCPGPPC
+VCCPGPPD
+VCCPGPPE
+VCCPGPPG
+VCCPGPPF
C202
0.1U/10V_2
C185
1uF/6.3_2
C195
1uF/6.3_2
+VCCRTCPRIM_3.3VVCCRTC
15
+3V_DEEP_SUS
+1.8V_DEEP_SUS
C165
1uF/6.3_2
C159
1uF/6.3_2
C167
0.1U/10V_2
+1.0V_DEEP_SUS
C34
1uF/6.3_2
+3VS5
6
3
U3
OUT
IN
SET
FLAG
EN4GND
GND
G517AL
1
2
GSET
5
7
+3V_DEEP_SUS
C30 0.1U/10V_2
R591 11K/F_2
RSET
B B
C132
*1U/6.3V_2
C70
*22U/6.3V_6
PVR Change
R69
10K/F_2
SLP_SUS_ON28,40,41
R592
*100K/F_2
+3V 2,4,10,11,12,13,14,19,20,21,22,24,25,27,28,29,33,42,46
+3VS5 4,26,27,28,29,30,37,38,39,40,41,45,46
+BAT_RTC 4,13,25,37,47
+3V_RTC_2 4,13
+3V_DEEP_SUS 4,10,11,12,14,30
+1.0V_DEEP_SUS 9,13,40,41
+1.8V_DEEP_SUS 9,37,40,46
SI Change
G517AL
RSET(KΩ) Current Limit(A)
A A
9.76
11
24.9
37.4
49.9
100
5
4
2.87
2.5
1.0
0.7
0.5
0.25
PROJECT : X31
PROJECT : X31
PROJECT : X31
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
NB5
NB5
NB5
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
SKL U (14/14)
SKL U (14/14)
SKL U (14/14)
1
15 49Friday, August 05, 2016
15 49Friday, August 05, 2016
15 49Friday, August 05, 2016
I'm from VIETNAM sualaptop365
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