QUANTA X1B-10L Schematics
5
www.vinafix.com
4
3
2
1
DIS (14" / 15" / 17")
D D
C C
System BIOS
SPI ROM
B B
Intel SKYLAKE ULT Platform Block Diagram
DDR3L SODIMM1
Maxima 8GBs
PAGE 17
DDR3L SODIMM2
Maxima 8GBs
PAGE 18
SATA0 - 1st HDD
Package : 9.5 (mm)
Power :
SATA ODD
Package : 12.7 (mm)
Power :
PAGE 10
DDR3L
DDR3L
PAGE 34
PAGE 34
SPI Interface
SKYLAKE U
Processor
Processor : Daul Core
Power : 15 (Watt)
SATA0 6GB/s
SATA1 3GB/s
SLB9665TT2.0 FW 5
PAGE 32TPM
LPC Interface PCIE Gen 1 x 1 Lane
Package : BGA1356
Size : 40 X 24 (mm)
HP
PAGE 2~16
Azalia
PCI-E
X4 Lane
eDP X 2
DP Port 1
USB3.0 Interface
USB2.0 Interface
Chocolate
NVIDIA N16S-GT
Package 23*23mm
25W
USB 3.0 Port 1,2,3(USB 2.0 Port 0,1,5)
27MHz
PAGE 16
PAGE 19~22
Camera
Port2
PAGE 28
VRAM DDR3 x 8
256M X 16 X 8
900Mhz
RTD2136
Package : QFN-32
Port7
Elan EKTH3915 for 14",15"
Elan EKTH3918 for 17"
PAGE 23~26
PAGE 27
Touch Screen
PAGE 32
LVDS (2CH)
eDP
HDMI Conn
USB3.0 Port x 1
Port 1
PAGE 28
PAGE 28
PAGE 28
PAGE 33
PCB 10L STACK UP
LAYER 1 : TOP
LAYER 2 : SGND
LAYER 3 : IN1(High)
LAYER 4 : IN2(Low)
LAYER 5 : SVCC
LAYER 6 : SGND1
LAYER 7 : IN3
LAYER 8 : IN4
LAYER 9 : SGND2
LAYER 10 : BOT
01
iTE 8987
Embedded Controller
Power :
Package : LQPF128
Size : 14 x 14 (mm)
PAGE 35
FAN
PAGE 31
5
H.P
PAGE32
PAGE 31
PAGE 31
SM BUS
G-Sensor
HP3DC2TR
Keyboard
Touch Pad
A A
Audio Codec
ALC3241
Power :
Package : MQFN
Size : 6 x 6 (mm)
PAGE 29
4
Card Reader
RTS5237S-GRT
Power :
Package : LQPF48
Size : 7 x 7 (mm)
DB
Head Phone AMP
HPA022642RTJR PAGE 30
LAN Controller
RTL8111HSH(Giga)
RTL8107EH(10/100)
Power :
Package : OFN32
DB
Speaker
Combo Jack
Digital MIC
3
M2 Card
Intel Rambo Peak
WLAN / BT Combo
Port6
PAGE 34
PAGE 29
PAGE 29
PAGE 28
PROJECT : X1B-10L
PROJECT : X1B-10L
PROJECT : X1B-10L
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
NB5
NB5
NB5
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Block Diagram
Block Diagram
Block Diagram
1
for ICT Review
1A
1A
1A
1 49Wednesday, May 06, 2015
1 49Wednesday, May 06, 2015
1 49Wednesday, May 06, 2015
5
HDMI
D D
DDPB_CTRLDATA/ GPP_E19
Display Port B Detected
This signal has a weak internal pull-down.
0 = Port B is not detected.
1 = Port B is detected.
This signal has a weak internal pull-down.
0 = Port C and D is not detected.
1 = Port C and D is detected.
C C
DB Del R98, R110
eDP_COMPIO and ICOMPO signals should be shorted near
balls and routed with typical impedance <25 mohms
SDVO_CLK28
SDVO_DATA28
+VCCIO
IN_D2#28
IN_D228
IN_D1#28
IN_D128
IN_D0#28
IN_D028
IN_CLK#28
IN_CLK28
4
TP113
TP114
IN_D2#
IN_D2
IN_D1#
IN_D1
IN_D0#
IN_D0
IN_CLK#
IN_CLK
DDPC_CTRLDATA
DDPD_CTRLDATA
R100 24.9/F_4
EDP_RCOMP
U20A
E55
DDI1_TXN[0]
F55
DDI1_TXP[0]
E58
DDI1_TXN[1]
F58
DDI1_TXP[1]
F53
DDI1_TXN[2]
G53
DDI1_TXP[2]
F56
DDI1_TXN[3]
G56
DDI1_TXP[3]
C50
DDI2_TXN[0]
D50
DDI2_TXP[0]
C52
DDI2_TXN[1]
D52
DDI2_TXP[1]
A50
DDI2_TXN[2]
B50
DDI2_TXP[2]
D51
DDI2_TXN[3]
C51
DDI2_TXP[3]
L13
GPP_E18/DDPB_CTRLCLK
L12
GPP_E19/DDPB_CTRLDATA
N7
GPP_E20/DDPC_CTRLCLK
N8
GPP_E21/DDPC_CTRLDATA
N11
GPP_E22/DDPD_CTRLCLK
N12
GPP_E23/DDPD_CTRLDATA
E52
EDP_RCOMP
*SKL_ULT
REV = 1
SKL_ULT
DDI
DISPLAY SIDEBANDS
3
C47
C46
D46
C45
A45
B45
A47
B47
E45
F45
B52
G50
F50
E48
F48
G46
F46
L9
L7
L6
N9
L10
R12
R11
U13
INT_EDP_TXN0
INT_EDP_TXP0
INT_EDP_TXN1
INT_EDP_TXP1
INT_EDP_AUXN
INT_EDP_AUXP
EDP_DISP_UTIL
HDMI_HPD_CON
ULT_EDP_HPD
PCH_LVDS_BLON
PCH_DPST_PWM
PCH_DISP_ON
EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]
EDP
1 OF 20
+3V 4,10,11,12,13,14,15,16,17,18,20,27,28,29,30,31,32,33,34,35,41,43,44
+1.0V 4,6,16,32,35,40
+VCCIO 6,16,40
+VCCSTPLL 4,5,6,9,40,41
EDP_AUXN
EDP_AUXP
EDP_DISP_UTIL
DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
DDI3_AUXN
DDI3_AUXP
GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3
GPP_E17/EDP_HPD
EDP_BKLTEN
EDP_BKLTCTL
EDP_VDDEN
2
INT_EDP_TXN0 27
INT_EDP_TXP0 27
INT_EDP_TXN1 27
INT_EDP_TXP1 27
INT_EDP_AUXN 27
INT_EDP_AUXP 27
TP52
HDMI_HPD_CON 28
ULT_EDP_HPD 27,28
PCH_LVDS_BLON 28
PCH_DPST_PWM 27
PCH_DISP_ON 28
1
Reserve EDP_HPD opposites circuit!
+3V
R93
ULT_EDP_HPD
*10K/F_4
R96
100K_4
Close to EC
PM_THRMTRIP#
Processor pull-up (CPU)
TO BE REPLACED WITH 1K OHMS FOR SKL .
470 OHM IS FOR I/P
R420 1K_4
02
+VCCSTPLL
CPU MISC
3
SKL_ULT
4 OF 20
JTAG
PROC_TCK
PROC_TDI
PROC_TDO
PROC_TMS
PROC_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_TRST#
PDC
JTAGX
B61
XDP_TCK0
D60
XDP_TDI_CPU
A61
XDP_TDO_CPU
C60
XDP_TMS_CPU
B59
XDP_TRST#_CPU
B56
JTAG_TCK_PCH
D59
JTAG_TDI_PCH
A56
JTAG_TDO_PCH
C59
JTAG_TMS_PCH
C61
XDP_TRST#_CPU
A59
JTAGX_PCH
XDP_TCK0 16
XDP_TDI_CPU 16
XDP_TDO_CPU 16
XDP_TMS_CPU 16
XDP_TRST#_CPU 16
JTAG_TCK_PCH 16
JTAG_TDI_PCH 16
JTAG_TDO_PCH 16
JTAG_TMS_PCH 16
JTAGX_PCH 16
2
PLACE NEAR CPU
XDP_TMS_CPU
XDP_TDI_CPU
XDP_TDO_CPU
H_PROCHOT#
XDP_TCK0
XDP_TRST#_CPU
PROJECT : X1B-10L
PROJECT : X1B-10L
PROJECT : X1B-10L
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
NB5
NB5
NB5
Date: Sheet of
Date: Sheet of
Date: Sheet of
R408 *51_4
R407 *51_4
R393 *51_4
R49 1K_4
R417 51_4
R399 51_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
SKYPAKE 1/20(eDP/DDI)
SKYPAKE 1/20(eDP/DDI)
SKYPAKE 1/20(eDP/DDI)
1
+1.0V
+1.0V
for ICT Review
2 49Wednesday, May 06, 2015
2 49Wednesday, May 06, 2015
2 49Wednesday, May 06, 2015
1A
1A
1A
+VCCSTPLL
R421 *49.9/F_4
EC_PECI35
H_PROCHOT#35,36,41
PM_THRMTRIP#35
XDP_BPM016
XDP_BPM116
3D_FW_GPIO33
+1.0V
B B
A A
R78 *0_4/S
5
R403 *51_4
R404 51_4
R418 51_4
R419 51_4
R405 51_4
Close to Chipset
JTAGX_PCH
JTAG_TMS_PCH
JTAG_TDI_PCH
JTAG_TDO_PCH
JTAG_TCK_PCH
SI Add
4
R395 499/F_4
R608 *0_4
R206 49.9/F_4
R201 49.9/F_4
R114 49.9/F_4
R106 49.9/F_4
TP46
TP105
TP103
CATERR#
EC_PECI
PROCHOT#
PM_THRMTRIP#
3D_FW_GPIO_R
CPU_GP1
CPU_GP2
CPU_GP3
PROC_POPIRCOMP
PCH_OPI_RCOMP
EDRAM_OPIO_RCOMP
EOPIO_RCOMP
D63
A54
C65
C63
A65
C55
D55
B54
C56
BA5
AY5
AT16
AU16
H66
H65
A6
A7
U20D
CATERR#
PECI
PROCHOT#
THERMTRIP#
SKTOCC#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3
PROC_POPIRCOMP
PCH_OPIRCOMP
OPCE_RCOMP
OPC_RCOMP
*SKL_ULT
REV = 1
5
M_A_DQSN[7:0]17
M_A_DQSP[7:0]17
M_B_DQSN[7:0]18
M_B_DQSP[7:0]18
M_A_DQ[63:0]17
M_B_DQ[63:0]18
4
3
2
1
03
SkyLake ULT Processor (DDR3L)
D D
U20B
AL71
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_B_DQ0
M_B_DQ1
M_B_DQ2
C C
B B
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
DDR0_DQ[0]
AL68
DDR0_DQ[1]
AN68
DDR0_DQ[2]
AN69
DDR0_DQ[3]
AL70
DDR0_DQ[4]
AL69
DDR0_DQ[5]
AN70
DDR0_DQ[6]
AN71
DDR0_DQ[7]
AR70
DDR0_DQ[8]
AR68
DDR0_DQ[9]
AU71
DDR0_DQ[10]
AU68
DDR0_DQ[11]
AR71
DDR0_DQ[12]
AR69
DDR0_DQ[13]
AU70
DDR0_DQ[14]
AU69
DDR0_DQ[15]
AF65
DDR1_DQ[0]/DDR0_DQ[16]
AF64
DDR1_DQ[1]/DDR0_DQ[17]
AK65
DDR1_DQ[2]/DDR0_DQ[18]
AK64
DDR1_DQ[3]/DDR0_DQ[19]
AF66
DDR1_DQ[4]/DDR0_DQ[20]
AF67
DDR1_DQ[5]/DDR0_DQ[21]
AK67
DDR1_DQ[6]/DDR0_DQ[22]
AK66
DDR1_DQ[7]/DDR0_DQ[23]
AF70
DDR1_DQ[8]/DDR0_DQ[24]
AF68
DDR1_DQ[9]/DDR0_DQ[25]
AH71
DDR1_DQ[10]/DDR0_DQ[26]
AH68
DDR1_DQ[11]/DDR0_DQ[27]
AF71
DDR1_DQ[12]/DDR0_DQ[28]
AF69
DDR1_DQ[13]/DDR0_DQ[29]
AH70
DDR1_DQ[14]/DDR0_DQ[30]
AH69
DDR1_DQ[15]/DDR0_DQ[31]
BB65
DDR0_DQ[16]/DDR0_DQ[32]
AW65
DDR0_DQ[17]/DDR0_DQ[33]
AW63
DDR0_DQ[18]/DDR0_DQ[34]
AY63
DDR0_DQ[19]/DDR0_DQ[35]
BA65
DDR0_DQ[20]/DDR0_DQ[36]
AY65
DDR0_DQ[21]/DDR0_DQ[37]
BA63
DDR0_DQ[22]/DDR0_DQ[38]
BB63
DDR0_DQ[23]/DDR0_DQ[39]
BA61
DDR0_DQ[24]/DDR0_DQ[40]
AW61
DDR0_DQ[25]/DDR0_DQ[41]
BB59
DDR0_DQ[26]/DDR0_DQ[42]
AW59
DDR0_DQ[27]/DDR0_DQ[43]
BB61
DDR0_DQ[28]/DDR0_DQ[44]
AY61
DDR0_DQ[29]/DDR0_DQ[45]
BA59
DDR0_DQ[30]/DDR0_DQ[46]
AY59
DDR0_DQ[31]/DDR0_DQ[47]
AT66
DDR1_DQ[16]/DDR0_DQ[48]
AU66
DDR1_DQ[17]/DDR0_DQ[49]
AP65
DDR1_DQ[18]/DDR0_DQ[50]
AN65
DDR1_DQ[19]/DDR0_DQ[51]
AN66
DDR1_DQ[20]/DDR0_DQ[52]
AP66
DDR1_DQ[21]/DDR0_DQ[53]
AT65
DDR1_DQ[22]/DDR0_DQ[54]
AU65
DDR1_DQ[23]/DDR0_DQ[55]
AT61
DDR1_DQ[24]/DDR0_DQ[56]
AU61
DDR1_DQ[25]/DDR0_DQ[57]
AP60
DDR1_DQ[26]/DDR0_DQ[58]
AN60
DDR1_DQ[27]/DDR0_DQ[59]
AN61
DDR1_DQ[28]/DDR0_DQ[60]
AP61
DDR1_DQ[29]/DDR0_DQ[61]
AT60
DDR1_DQ[30]/DDR0_DQ[62]
AU60
DDR1_DQ[31]/DDR0_DQ[63]
*SKL_ULT
REV = 1
SKL_ULT
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]
DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]
DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]
DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7]
NIL-DDR CH A
2 OF 20
DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]
DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]
DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]
DDR0_ODT[1]
DDR0_MA[3]
DDR0_MA[4]
DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSP[1]
DDR0_ALERT#
DDR0_PAR
DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ
DDR_VTT_CNTL
AU53
AT53
AU55
AT55
BA56
BB56
AW56
AY56
AU45
AU43
AT45
AT43
BA51
M_A_A5
BB54
M_A_A9
BA52
M_A_A6
AY52
M_A_A8
AW52
M_A_A7
AY55
M_A_BS#2
AW54
M_A_A12
BA54
M_A_A11
BA55
M_A_A15
AY54
M_A_A14
AU46
M_A_A13
AU48
AT46
AU50
AU52
AY51
M_A_A2
AT48
AT50
M_A_A10
BB50
M_A_A1
AY50
M_A_A0
BA50
M_A_A3
BB52
M_A_A4
AM70
M_A_DQSN0
AM69
M_A_DQSP0
AT69
M_A_DQSN1
AT70
M_A_DQSP1
AH66
M_B_DQSN0
AH65
M_B_DQSP0
AG69
M_B_DQSN1
AG70
M_B_DQSP1
BA64
M_A_DQSN2
AY64
M_A_DQSP2
AY60
M_A_DQSN3
BA60
M_A_DQSP3
AR66
M_B_DQSN2
AR65
M_B_DQSP2
AR61
M_B_DQSN3
AR60
M_B_DQSP3
AW50
AT52
DDR0_PAR
AY67
SM_VREF
AY68
SMDDR_VREF_DQ0_M3
BA67
SMDDR_VREF_DQ1_M3
AW67
DDR_VTT_CNTL
M_A_CLKN0 17
M_A_CLKP0 17
M_A_CLKN1 17
M_A_CLKP1 17
M_A_CKE0 17
M_A_CKE1 17
M_A_CS#0 17
M_A_CS#1 17
M_A_DIM0_ODT0 17
M_A_DIM0_ODT1 17
M_A_A5 17
M_A_A9 17
M_A_A6 17
M_A_A8 17
M_A_A7 17
M_A_BS#2 17
M_A_A12 17
M_A_A11 17
M_A_A15 17
M_A_A14 17
M_A_A13 17
M_A_CAS# 17
M_A_WE# 17
M_A_RAS# 17
M_A_BS#0 17
M_A_A2 17
M_A_BS#1 17
M_A_A10 17
M_A_A1 17
M_A_A0 17
M_A_A3 17
M_A_A4 17
TP17
SM_VREF 17
SMDDR_VREF_DQ0_M3 17
SMDDR_VREF_DQ1_M3 18
DDR_VTT_CNTL 4,18
20mils width
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
U20C
AY39
DDR0_DQ[32]/DDR1_DQ[0]
AW39
DDR0_DQ[33]/DDR1_DQ[1]
AY37
DDR0_DQ[34]/DDR1_DQ[2]
AW37
DDR0_DQ[35]/DDR1_DQ[3]
BB39
DDR0_DQ[36]/DDR1_DQ[4]
BA39
DDR0_DQ[37]/DDR1_DQ[5]
BA37
DDR0_DQ[38]/DDR1_DQ[6]
BB37
DDR0_DQ[39]/DDR1_DQ[7]
AY35
DDR0_DQ[40]/DDR1_DQ[8]
AW35
DDR0_DQ[41]/DDR1_DQ[9]
AY33
DDR0_DQ[42]/DDR1_DQ[10]
AW33
DDR0_DQ[43]/DDR1_DQ[11]
BB35
DDR0_DQ[44]/DDR1_DQ[12]
BA35
DDR0_DQ[45]/DDR1_DQ[13]
BA33
DDR0_DQ[46]/DDR1_DQ[14]
BB33
DDR0_DQ[47]/DDR1_DQ[15]
AU40
DDR1_DQ[32]/DDR1_DQ[16]
AT40
DDR1_DQ[33]/DDR1_DQ[17]
AT37
DDR1_DQ[34]/DDR1_DQ[18]
AU37
DDR1_DQ[35]/DDR1_DQ[19]
AR40
DDR1_DQ[36]/DDR1_DQ[20]
AP40
DDR1_DQ[37]/DDR1_DQ[21]
AP37
DDR1_DQ[38]/DDR1_DQ[22]
AR37
DDR1_DQ[39]/DDR1_DQ[23]
AT33
DDR1_DQ[40]/DDR1_DQ[24]
AU33
DDR1_DQ[41]/DDR1_DQ[25]
AU30
DDR1_DQ[42]/DDR1_DQ[26]
AT30
DDR1_DQ[43]/DDR1_DQ[27]
AR33
DDR1_DQ[44]/DDR1_DQ[28]
AP33
DDR1_DQ[45]/DDR1_DQ[29]
AR30
DDR1_DQ[46]/DDR1_DQ[30]
AP30
DDR1_DQ[47]/DDR1_DQ[31]
AY31
DDR0_DQ[48]/DDR1_DQ[32]
AW31
DDR0_DQ[49]/DDR1_DQ[33]
AY29
DDR0_DQ[50]/DDR1_DQ[34]
AW29
DDR0_DQ[51]/DDR1_DQ[35]
BB31
DDR0_DQ[52]/DDR1_DQ[36]
BA31
DDR0_DQ[53]/DDR1_DQ[37]
BA29
DDR0_DQ[54]/DDR1_DQ[38]
BB29
DDR0_DQ[55]/DDR1_DQ[39]
AY27
DDR0_DQ[56]/DDR1_DQ[40]
AW27
DDR0_DQ[57]/DDR1_DQ[41]
AY25
DDR0_DQ[58]/DDR1_DQ[42]
AW25
DDR0_DQ[59]/DDR1_DQ[43]
BB27
DDR0_DQ[60]/DDR1_DQ[44]
BA27
DDR0_DQ[61]/DDR1_DQ[45]
BA25
DDR0_DQ[62]/DDR1_DQ[46]
BB25
DDR0_DQ[63]/DDR1_DQ[47]
AU27
DDR1_DQ[48]
AT27
DDR1_DQ[49]
AT25
DDR1_DQ[50]
AU25
DDR1_DQ[51]
AP27
DDR1_DQ[52]
AN27
DDR1_DQ[53]
AN25
DDR1_DQ[54]
AP25
DDR1_DQ[55]
AT22
DDR1_DQ[56]
AU22
DDR1_DQ[57]
AU21
DDR1_DQ[58]
AT21
DDR1_DQ[59]
AN22
DDR1_DQ[60]
AP22
DDR1_DQ[61]
AP21
DDR1_DQ[62]
AN21
DDR1_DQ[63]
*SKL_ULT
REV = 1
SKL_ULT
DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]
DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]
DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
NIL-DDR CH B
3 OF 20
DDR1_ODT[1]
DDR1_MA[3]
DDR1_MA[4]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSP[5]/DDR1_DQSP[3]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSP[7]/DDR1_DQSP[5]
DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]
DDR1_ALERT#
DRAM_RESET#
DDR_RCOMP[0]
DDR_RCOMP[1]
DDR_RCOMP[2]
PDC
DDR1_PAR
AN45
AN46
AP45
AP46
AN56
AP55
AN55
AP53
BB42
AY42
BA42
AW42
AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52
BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47
BA38
AY38
AY34
BA34
AT38
AR38
AT32
AR32
BA30
AY30
AY26
BA26
AR25
AR27
AR22
AR21
AN43
AP43
AT13
AR18
AT18
AU18
M_B_A5
M_B_A9
M_B_A6
M_B_A8
M_B_A7
M_B_A12
M_B_A11
M_B_A15
M_B_A14
M_B_A13
M_B_A2
M_B_A10
M_B_A1
M_B_A0
M_B_A3
M_B_A4
M_A_DQSN4
M_A_DQSP4
M_A_DQSN5
M_A_DQSP5
M_B_DQSN4
M_B_DQSP4
M_B_DQSN5
M_B_DQSP5
M_A_DQSN6
M_A_DQSP6
M_A_DQSN7
M_A_DQSP7
M_B_DQSN6
M_B_DQSP6
M_B_DQSN7
M_B_DQSP7
DDR1_PAR
SM_DRAMRST#
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
TP29
R180 121/F_4
R175 80.6/F_4
R179 100/F_4
M_B_CLKN0 18
M_B_CLKN1 18
M_B_CLKP0 18
M_B_CLKP1 18
M_B_CKE0 18
M_B_CKE1 18
M_B_CS#0 18
M_B_CS#1 18
M_B_DIM0_ODT0 18
M_B_DIM0_ODT1 18
M_B_A5 18
M_B_A9 18
M_B_A6 18
M_B_A8 18
M_B_A7 18
M_B_BS#2 18
M_B_A12 18
M_B_A11 18
M_B_A15 18
M_B_A14 18
M_B_A13 18
M_B_CAS# 18
M_B_WE# 18
M_B_RAS# 18
M_B_BS#0 18
M_B_A2 18
M_B_BS#1 18
M_B_A10 18
M_B_A1 18
M_B_A0 18
M_B_A3 18
M_B_A4 18
+1.35VSUS
R301
470_4
DDR3_DRAMRST# 17,18
A A
5
4
+1.35VSUS 6,17,18,38,40,46
3
PROJECT : X1B-10L
PROJECT : X1B-10L
PROJECT : X1B-10L
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
NB5
NB5
NB5
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
SKYPAKE 3/20(DDR3-A I/F)
SKYPAKE 3/20(DDR3-A I/F)
SKYPAKE 3/20(DDR3-A I/F)
1
1A
1A
1A
3 49Tuesday, May 05, 2015
3 49Tuesday, May 05, 2015
3 49Tuesday, May 05, 2015
5
4
3
2
1
04
U20K
D D
SUSACK#_EC35
RSMRST#35
SUSWARN#
EC27
*220P/50V_4
R204 *0_4
R207 0_4
PCIE_WAKE#30,34,35
DDR_VTT_CNTL3,18
SYS_RESET#16
SYS_PWROK16
EC_PWROK16,35
SUSWARN#_EC35
Need check circuit!!!!
Should be delete
R402 *10K_4
R202 *0_4/S
PLTRST#
SYS_RESET#
RSMRST#
PROCPWRGD
H_VCCST_PWRGD
C593 *0.1U/16V_4
SYS_PWROK
PCH_PWROK
DSWROK_EC_R
SUSWARN#
SUSACK#
PCIE_WAKE#
DDR_VTT_CNTL PCIE_WAKE#
AN10
GPP_B13/PLTRST#
B5
SYS_RESET#
AY17
RSMRST#
A68
PROCPWRGD
B65
VCCST_PWRGD
B6
SYS_PWROK
BA20
PCH_PWROK
BB20
DSW_PW ROK
AR13
GPP_A13/SUSW ARN#/SUSPWRDNACK
AP11
GPP_A15/SUSACK#
BB15
WAKE#
AM15
GPD2/LAN_WAKE#
AW17
GPD11/LANPHYPC
AT15
GPD7/RSVD
*SKL_ULT
REV = 1
SKL_ULT
SYSTEM POWER MANAGEMENT
11 OF 20
GPP_B12/SLP_S0#
GPD4/SLP_S3#
GPD5/SLP_S4#
GPD10/SLP_S5#
SLP_SUS#
SLP_LAN#
GPD9/SLP_WLAN#
GPD6/SLP_A#
GPD3/PWRBTN#
GPD1/ACPRESENT
GPD0/BATLOW #
GPP_A11/PME#
GPP_B11/EXT_PW R_GATE#
INTRUDER#
GPP_B2/VRALERT#
PCH_SLP_S0_N
AP15
BA16
AY16
AN15
SLP_SUS#_EC
AW15
BB17
AN16
BA15
AY15
AU13
AU11
AP16
AM10
AM11
?
SI Del TP111
DNBSWON#
AC_PRESENT_EC
RF_OFF_PCH
INTRUDER#_R
GPP_B2
R181 1M_4
TP15
PCH_SLP_S0_N 16,35
SUSB# 16,35
SUSC# 16,35
SLP_S5# 16
SLP_SUS#_EC 35
SLP_A# 16
DNBSWON# 35
AC_PRESENT_EC 35
RF_OFF_PCH 34
+3V_RTC
SUSWARN#
SUSACK#
RF_OFF_PCH
AC_PRESENT_EC
+3V_DEEP_SUS
R197 10K_4
R205 10K_4
R196 10K_4
+3VS5
R214 1K_4
R212 *10K_4
+3V
AT11
PCH Pull-high/low(CLG)
SYS_RESET#
C C
+3V 2,10,11,12,13,14,15,16,17,18,20,27,28,29,30,31,32,33,34,35,41,43,44
+1.0V 2,6,16,32,35,40
+3VS5 10,15,16,32,34,35,37,39,40,43,46
+5VS5 30,32,33,37,38,39,40,41,42,43,44,45,46
+3V_RTC 13,15,32
+VCCSTPLL 2,5,6,9,40,41
+3V_DEEP_SUS 10,11,12,14,15,16,18
RSMRST#
DSWROK_EC
R429 10K_4
R217 10K_4
R227 100K/F_4
For DS3 Sequence
For DS3 -->Ra
Non-DS3 -->Rb
RSMRST#
DSWROK_EC35
B B
PLTRST#(CLG)
Check Q2010 Rise/Fall time less than 100ns
R18
100K/F_4
System PWR_OK(CLG)
Rb
R220 *0_4
R222 0_4
Ra
PLTRST# 16,19,30,32,34,35
R425 0_4
EC_PWROKSYS_PWROK
DSWROK_EC_R
1216 Change R409 and R394 from
+VCCSTPLL or +1.0V co-layout.
+1.0V
+VCCSTPLL
R394
1K_4
HWPG16,35,37,38,39
D13 RB501V-40
21
R10479 close to CPU side
H_VCCST_PWRGD trace 0.3" - 1.5"
H_VCCST_PWRGD_R
C577
*10P/50V_4
R409
*1K_4
R396 60.4_4
H_VCCST_PWRGD
+1.0V +3VS5+5VS5
R22
15K_4
+1.0V_PWRGD_G1
C38
0.1U/16V_4
R26
100K_4
2
R35
100K_4
+1.0V_PWRGD_G2
Q10
METR3904-G
1 3
R48
10K_4
3
Q11
2
DMN601K-7
1
1110 Add Citcuit for +1.0V Power Good
R43
100K_4
HWPG
A A
5
R426
10K/F_4
PROJECT : X1B-10L
PROJECT : X1B-10L
PROJECT : X1B-10L
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
NB5
NB5
NB5
Date: Sheet of
Date: Sheet of
4
3
2
Date: Sheet of
SKYPAKE 5/20(Power Manger)
SKYPAKE 5/20(Power Manger)
SKYPAKE 5/20(Power Manger)
1
1A
1A
1A
4 49Tuesday, May 05, 2015
4 49Tuesday, May 05, 2015
4 49Tuesday, May 05, 2015
5
4
3
2
1
SKL_ULT
A30
A34
A39
A44
AK33
AK35
AK37
AK38
AK40
AL33
AL37
AL40
AM32
AM33
AM35
AM37
AM38
G30
K32
AK32
AB62
P62
V62
H63
G61
AC63
AE63
AE62
AG62
AL63
AJ62
C555
47U/6.3VS_6
U20L
CPU POWER 1 OF 4
VCC_A30
VCC_A34
33A
VCC_A39
VCC_A44
VCC_AK33
VCC_AK35
VCC_AK37
VCC_AK38
VCC_AK40
VCC_AL33
VCC_AL37
VCC_AL40
VCC_AM32
VCC_AM33
VCC_AM35
VCC_AM37
VCC_AM38
VCC_G30
RSVD_K32
RSVD_AK32
VCCOPC_AB62
VCCOPC_P62
VCCOPC_V62
VCC_OPC_1P8_H63
VCC_OPC_1P8_G61
VCCOPC_SENSE
VSSOPC_SENSE
VCCEOPIO
VCCEOPIO
VCCEOPIO_SENSE
VSSEOPIO_SENSE
*SKL_ULT
REV = 1
C173
47U/6.3VS_6
12 OF 20
C139
47U/6.3VS_6
C140
47U/6.3VS_6
VCC_G32
VCC_G33
VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42
VCC_J30
VCC_J33
VCC_J37
VCC_J40
VCC_K33
VCC_K35
VCC_K37
VCC_K38
VCC_K40
VCC_K42
VCC_K43
VCC_SENSE
VSS_SENSE
VIDALERT#
VIDSCK
VIDSOUT
VCCSTG_G20
PDC
C172
47U/6.3VS_6
G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43
E32
E33
B63
H_CPU_SVIDALRT#
A63
VR_SVID_CLK_R
D64
H_CPU_SVIDDAT
G20
C157
47U/6.3VS_6
C600
1U/6.3V_4
C602
1U/6.3V_4
C160
1U/6.3V_4
C137
1U/6.3V_4
R103 *100/F_4
R104 *100/F_4
+VCCSTG
C177
C601
1U/6.3V_4
1U/6.3V_4
C152
C144
1U/6.3V_4
1U/6.3V_4
+VCC_CORE
VCC_SENSE 41
VSS_SENSE 41
C563
1U/6.3V_4
C201
1U/6.3V_4
C200
1U/6.3V_4
C190
1U/6.3V_4
C169
1U/6.3V_4
C126
1U/6.3V_4
C116
1U/6.3V_4
100- ±1%
pull-up to VCC
near processor.
Layout note: need routing together and ALERT need between CLK and DATA.
+VCCSTPLL
CLOSE TO CPU
PLACE THE PU RESISTORS
H_CPU_SVIDALRT#
R412 220/F_4
R400
56.2/F_4
C569
*0.1U/16V_4
SVID ALERT
VR_SVID_ALERT# 41
Under U20 Under U20
C55
C61
22U/6.3V_6
D D
C C
10U/6.3V_6
C98
10U/6.3V_4
C557
22U/6.3V_6
C199
10U/6.3V_4
C65
22U/6.3V_6
22U/6.3V_6
C127
10U/6.3V_4
C84
22U/6.3V_6
22U/6.3V_6
C188
10U/6.3V_4
C70
22U/6.3V_6
C551
47U/6.3VS_6
C189
10U/6.3V_4
C554
22U/6.3V_6
C553
22U/6.3V_6
C125
10U/6.3V_4
C58
22U/6.3V_6
C552
C48
TP18
TP11
+VCC_CORE
+VCC_CORE
C63
22U/6.3V_6
C579
10U/6.3V_4
VCCEOPIO_SENSE
VSSEOPIO_SENSE
C156
47U/6.3VS_6
Close U20
+VCC_CORE +VCC_CORE
C558
22U/6.3V_6
C556
47U/6.3VS_6
05
R411
100/F_4
+VCCSTPLL
R398
*54.9/F_4
SVID CLK
VR_SVID_CLK 41
SVID DATA
R397 *0_4/S
PROJECT : X1B-10L
PROJECT : X1B-10L
PROJECT : X1B-10L
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
NB5
NB5
NB5
Date: Sheet of
Date: Sheet of
Date: Sheet of
VR_SVID_DATA 41
SKYPAKE 6/20 (POWER-1)
SKYPAKE 6/20 (POWER-1)
SKYPAKE 6/20 (POWER-1)
1
1A
1A
1A
5 49Tuesday, May 05, 2015
5 49Tuesday, May 05, 2015
5 49Tuesday, May 05, 2015
C124
B B
A A
5
10U/6.3V_4
C90
10U/6.3V_4
4
C96
10U/6.3V_4
C117
10U/6.3V_4
C570
10U/6.3V_4
C599
C572
10U/6.3V_4
10U/6.3V_4
+VCCSTG 6
+VCCSTPLL 2,4,6,9,40,41
+VCC_CORE 41
C596
10U/6.3V_4
3
PLACE THE PU RESISTORS
CLOSE TO VR
PULL UP IS IN THE VR MODULE
CLOSE TO CPU
PLACE THE PU RESISTORS
VR_SVID_CLK_R
H_CPU_SVIDDAT
2
R416 *0_4/S
+VCCSTPLL
5
4
3
2
1
06
Under U20
D D
10U/6.3V_4
C269
C289
10U/6.3V_4
C291
10U/6.3V_4
C318
10U/6.3V_4
C293
10U/6.3V_4
C294
1U/6.3V_4
C280
10U/6.3V_4
Close U20
+VCCSTPLL
R586 0_4
+1.0V
R79 *0_4
+VCCIO
C C
Add R621 NI for Modern Stand By
R621 *0_4
R75 0_6
+VCCSTG
+VCCPLL+VCCSTPLL
+1.35VSUS
TBD
C287
C288
1U/6.3V_4
1U/6.3V_4
C206
*10U/6.3V_4
Close U20 Under U20
+1.35V_VCCPLL_OC
Add R620 NI for Modern Stand By
C278
1U/6.3V_4
C202
1U/6.3V_4
R187 0_6
R620 *0_6
+VCCSTPLL
+VCCSTG
+VCCPLL_OC
+VCCPLL
+VCCPLL_OC+1.35VSUS
+VCCSTPLL
C100
*1U/6.3V_4
120mA
AU23
AU28
AU35
AU42
BB23
BB32
BB41
BB47
BB51
AM40
A18
A22
AL23
K20
K21
C86
*22U/6.3V_6
U20N
CPU POWER 3 OF 4
VDDQ_AU23
VDDQ_AU28
VDDQ_AU35
VDDQ_AU42
VDDQ_BB23
VDDQ_BB32
VDDQ_BB41
VDDQ_BB47
VDDQ_BB51
VDDQC
VCCST
VCCSTG_A22
VCCPLL_OC
VCCPLL_K20
VCCPLL_K21
*SKL_ULT
REV = 1
SKL_ULT
2A
0.12A
0.04A
0.12A
Need apply PN
VCCIO
3.1A
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCSA
4.5A
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCIO_SENSE
VSSIO_SENSE
VSSSA_SENSE
VCCSA_SENSE
14 OF 20
+1.0V 2,4,16,32,35,40
+VCCIO 2,16,40
+3VPCU 13,30,31,32,33,34,35,36,37
+VCCSA 41,42
+VCCSTG 5
+1.35VSUS 3,17,18,38,40,46
+VCCSTPLL 2,4,5,9,40,41
+1.35V_VCCPLL_OC 40
AK28
AK30
AL30
AL42
AM28
AM30
AM42
AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30
AM23
AM22
H21
H20
C167
1U/6.3V_4
+VCCSA
C578
1U/6.3V_4
VCCIO_VCCSENSE
VCCIO_VSSSENSE
Under U20 Close U20
C195
1U/6.3V_4
C197
1U/6.3V_4
C158
10U/6.3V_4
C141
10U/6.3V_4
C149
10U/6.3V_4
C196
1U/6.3V_4
Under U20
C97
C564
1U/6.3V_4
C129
10U/6.3V_4
C71
C566
1U/6.3V_4
1U/6.3V_4
C112
C168
10U/6.3V_4
10U/6.3V_4
VSSSA_SENSE 41
VCCSA_SENSE 41
C81
1U/6.3V_4
C186
10U/6.3V_4
1U/6.3V_4
C44
10U/6.3V_4
VCCIO_VCCSENSE
VCCIO_VSSSENSE
C175
1U/6.3V_4
C94
10U/6.3V_4
C185
1U/6.3V_4
C111
10U/6.3V_4
Close U20
R149 100/F_4
R142 100/F_4
Close A18 Ball
+VCCSTG +VCCPLL_OC +VCCPLL +1.35VSUS+VCCSTPLL
C198
1U/6.3V_4
C135
10U/6.3V_4
+VCCIO
C174
1U/6.3V_4
C576
10U/6.3V_4
+VCCIO
C585
10U/6.3V_4
C586
10U/6.3V_4
C89
10U/6.3V_4
C571
10U/6.3V_4
C99
1U/6.3V_4
Under U20 Close U20
B B
C263
1U/6.3V_4
IO Ther Protect
+3VPCU
A A
5
R157
20K/F_4
C72
1U/6.3V_4
C138
1U/6.3V_4
For 75 degree, 1.2v limit, (HW)
THRM_MOINTOR1 35
R156
100K_4 NTC
C211
0.1U/16V_4
1 2
C246
10U/6.3V_6
C256
10U/6.3V_6
C252
10U/6.3V_6
C333
10U/6.3V_6
C245
10U/6.3V_6
C254
10U/6.3V_6
Close to CPU
CHOCK Ther Protect DDR Ther Protect
+3VPCU +3VPCU
R580
20K/F_4
For 75 degree, 1.2v limit, (HW) For 75 degree, 1.2v limit, (HW)
THRM_MOINTOR2 35 THRM_MOINTOR3 35
R578
100K_4 NTC
C728
0.1U/16V_4
1 2
4
R581
*20K/F_4
R579
*100K_4 NTC
1 2
R579 Close to U15
C277
1U/6.3V_4
C729
*0.1U/16V_4
C307
1U/6.3V_4
3
C292
1U/6.3V_4
C323
1U/6.3V_4
PROJECT : X1B-10L
PROJECT : X1B-10L
PROJECT : X1B-10L
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
NB5
NB5
NB5
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
SKYPAKE 7/20 (POWER-2)
SKYPAKE 7/20 (POWER-2)
SKYPAKE 7/20 (POWER-2)
1
1A
1A
1A
6 49Tuesday, May 05, 2015
6 49Tuesday, May 05, 2015
6 49Tuesday, May 05, 2015
5
4
3
2
1
SKL_ULT
AA63
AA64
AA66
AA67
AA69
AA70
AA71
AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71
M62
N63
N64
N66
N67
N69
A48
A53
A58
A62
A66
J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60
K48
K50
K52
K53
K55
K56
K58
K60
L62
L63
L64
L65
L66
L67
L68
L69
L70
L71
J70
J69
U20M
CPU POWER 2 OF 4
VCCGT
VCCGT
40A
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT_SENSE
VSSGT_SENSE
*SKL_ULT
REV = 1
PDC
13 OF 20
VCCGTX_AK42
VCCGTX_AK43
VCCGTX_AK45
VCCGTX_AK46
VCCGTX_AK48
VCCGTX_AK50
VCCGTX_AK52
VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60
VCCGTX_AK70
VCCGTX_AL43
VCCGTX_AL46
VCCGTX_AL50
VCCGTX_AL53
VCCGTX_AL56
VCCGTX_AL60
VCCGTX_AM48
VCCGTX_AM50
VCCGTX_AM52
VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58
VCCGTX_AU58
VCCGTX_AU63
VCCGTX_BB57
VCCGTX_BB66
VCCGTX_SENSE
VSSGTX_SENSE
+VCCGT
C123
1U/6.3V_4
C88
1U/6.3V_4
C122
10U/6.3V_4
C132
10U/6.3V_4
C615
1U/6.3V_4
C68
1U/6.3V_4
C610
10U/6.3V_4
C164
10U/6.3V_4
C113
1U/6.3V_4
C597
1U/6.3V_4
C121
10U/6.3V_4
C133
10U/6.3V_4
C114
1U/6.3V_4
C134
1U/6.3V_4
VCCGT_SENSE41
VSSGT_SENSE41
D D
C C
B B
C77
10U/6.3V_4
C115
10U/6.3V_4
C145
1U/6.3V_4
C165
1U/6.3V_4
C192
10U/6.3V_4
C147
10U/6.3V_4
C118
1U/6.3V_4
C95
1U/6.3V_4
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62
AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66
AK62
AL61
+VCCGT
Close U20Under U20
C182
47U/6.3VS_6
C194
22U/6.3V_6
C153
22U/6.3V_6
C161
47U/6.3VS_6
C191
22U/6.3V_6
C130
22U/6.3V_6
C146
47U/6.3VS_6
C180
22U/6.3V_6
C119
22U/6.3V_6
C128
47U/6.3VS_6
C179
22U/6.3V_6
C193
22U/6.3V_6
C154
47U/6.3VS_6
C181
22U/6.3V_6
C162
22U/6.3V_6
C155
47U/6.3VS_6
C142
22U/6.3V_6
C171
22U/6.3V_6
07
+VCCGT 41
A A
PROJECT : X1B-10L
PROJECT : X1B-10L
PROJECT : X1B-10L
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
NB5
NB5
NB5
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
SKYPAKE 8/20 (POWER-3)
SKYPAKE 8/20 (POWER-3)
SKYPAKE 8/20 (POWER-3)
1
1A
1A
1A
7 49Tuesday, May 05, 2015
7 49Tuesday, May 05, 2015
7 49Tuesday, May 05, 2015
5
4
3
2
1
08
AT63
AT68
AT71
AU10
AU15
AU20
AU32
AU38
AV68
AV69
AV70
AV71
AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57
AW6
AW60
AW62
AW64
AW66
AW8
AY66
BA10
BA14
BA18
BA23
BA28
BA32
BA36
BA45
AV1
B10
B14
B18
B22
B30
B34
B39
B44
B48
B53
B58
B62
B66
B71
BA1
BA2
F68
SKL_ULT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
*SKL_ULT
REV = 1
GND 2 OF 3
AA2
AA4
AA65
AA68
AB15
AB16
AB18
AB21
AB8
AD13
AD16
AD19
AD20
AD21
AD62
AD8
AE64
AE65
AE66
AE67
AE68
AE69
AF10
AF15
AF17
AF63
AG16
AG17
AG18
AG19
AG20
AG21
AG71
AH13
AH6
AH63
AH64
AH67
AJ15
AJ18
AJ20
AK11
AK16
AK18
AK21
AK22
AK27
AK63
AK68
AK69
AK8
AL28
AL32
AL35
AL38
AL45
AL48
AL52
AL55
AL58
AL64
A67
A70
AF1
AF2
AF4
AJ4
AL2
AL4
A5
SKL_ULT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
*SKL_ULT
REV = 1
GND 1 OF 3
16 OF 20
U20P
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AL65
AL66
AM13
AM21
AM25
AM27
AM43
AM45
AM46
AM55
AM60
AM61
AM68
AM71
AM8
AN20
AN23
AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48
AR5
AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58
D D
C C
B B
G10
G22
G43
G45
G48
G52
G55
G58
G60
G63
G66
H15
H18
H71
K16
K18
K22
K61
K63
K64
K65
K66
K67
K68
K70
K71
F8
G5
G6
J11
J13
J25
J28
J32
J35
J38
J42
J8
L11
L16
L17
SKL_ULT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
*SKL_ULT
REV = 1
GND 3 OF 3
18 OF 20
U20R
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21
17 OF 20
U20Q
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PDC
BA49
BA53
BA57
BA6
BA62
BA66
BA71
BB18
BB26
BB30
BB34
BB38
BB43
BB55
BB6
BB60
BB64
BB67
BB70
C1
C25
C5
D10
D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58
D6
D62
D66
D69
E11
E15
E18
E21
E46
E50
E53
E56
E6
E65
E71
F1
F13
F2
F22
F23
F27
F28
F32
F33
F35
F37
F38
F4
F40
F42
BA41
A A
PROJECT : X1B-10L
PROJECT : X1B-10L
PROJECT : X1B-10L
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
NB5
NB5
NB5
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
SKYPAKE 9/20 (GND-1)
SKYPAKE 9/20 (GND-1)
SKYPAKE 9/20 (GND-1)
1
1A
1A
1A
8 49Tuesday, May 05, 2015
8 49Tuesday, May 05, 2015
8 49Tuesday, May 05, 2015
5
4
3
2
1
09
U20S
CFG0-19 need Reserve TP
D D
+1.0V_DEEP_SUS
C C
CFG016
CFG116
CFG216
CFG316
CFG416
CFG516
CFG616
CFG716
CFG816
CFG916
CFG1016
CFG1116
CFG1216
CFG1316
CFG1416
CFG1516
CFG1616
CFG1716
CFG1816
CFG1916
R101 49.9/F_4
R76 *1K_4
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG_RCOMP
AL25
AL27
BA70
BA68
E68
B67
D65
D67
E70
C68
D68
C67
F71
G69
F70
G68
H70
G71
H69
G70
E63
F63
E66
F66
E60
E8
AY2
AY1
D1
D3
K46
K45
C71
B70
F60
A52
J71
J68
F65
G65
F61
E61
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
CFG[18]
CFG[19]
CFG_RCOMP
ITP_PMODE
RSVD_AY2
RSVD_AY1
RSVD_D1
RSVD_D3
RSVD_K46
RSVD_K45
RSVD_AL25
RSVD_AL27
RSVD_C71
RSVD_B70
RSVD_F60
RSVD_A52
RSVD_TP_BA70
RSVD_TP_BA68
RSVD_J71
RSVD_J68
VSS_F65
VSS_G65
RSVD_F61
RSVD_E61
SKL_ULT
RESERVED SIGNALS-1
RSVD_TP_BB68
RSVD_TP_BB69
RSVD_TP_AK13
RSVD_TP_AK12
RSVD_BB2
RSVD_BA3
RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2
RSVD_B3
RSVD_A3
RSVD_AW1
RSVD_E1
RSVD_E2
RSVD_BA4
RSVD_BB4
RSVD_A4
RSVD_C4
RSVD_A69
RSVD_B69
RSVD_AY3
RSVD_D71
RSVD_C70
RSVD_C54
RSVD_D54
VSS_AY71
ZVM#
RSVD_TP_AW71
RSVD_TP_AW70
MSM#
PROC_SELECT#
BB68
BB69
AK13
AK12
BB2
BA3
AU5
TP5
AT5
TP6
D5
D4
B2
C2
B3
A3
AW1
E1
E2
BA4
BB4
A4
C4
BB5
TP4
A69
B69
AY3
R500 *0_4/S
D71
C70
C54
D54
AY4
TP1
BB3
TP2
AY71
R531 *0_4/S
AR56
AW71
AW70
AP56
C64
R410 *100K_4
+1.8V_DEEP_SUS
R583 *0_4
SKL-U un-install R583,C732.
Cannonlake-U Stuff R583,C732.
+VCCSTPLL
AW69
AW68
AW48
C732
*1U/6.3V_4
AU56
C7
U12
U11
H11
SKL_ULT
U20T
RSVD_AW69
RSVD_AW68
RSVD_AU56
RSVD_AW48
RSVD_C7
RSVD_U12
RSVD_U11
RSVD_H11
*SKL_ULT
REV = 1
SPARE
20 OF 20
RSVD_F6
RSVD_E3
RSVD_C11
RSVD_B11
RSVD_A11
RSVD_D12
RSVD_C12
RSVD_F52
F6
E3
C11
B11
A11
D12
C12
F52
PDC
B B
*SKL_ULT
REV = 1
19 OF 20
+VCCSTPLL 2,4,5,6,40,41
+1.0V_DEEP_SUS 13,15,16,39,40
+1.8V_DEEP_SUS 15,39
Processor Strapping
CFG3
(Physcial Debug Enable)
DFX Privacy
CFG4
(DP Presence Strap)
A A
5
The CFG signals have a default value of '1' if not terminated on the board.
1 0
Disable: Enable: Set DFX Enable in DFX interface MSR
Disable; No physical DP attached to eDP
4
Enable; An ext DP device is connected to eDP
3
CFG3
CFG4
SI Change
Circuit
R430 *1K_4
R443 1K_4
PROJECT : X1B-10L
PROJECT : X1B-10L
PROJECT : X1B-10L
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
NB5
NB5
NB5
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
SKYPAKE 12/20 (RSV-1)
SKYPAKE 12/20 (RSV-1)
SKYPAKE 12/20 (RSV-1)
1
1A
1A
1A
9 49Tuesday, May 05, 2015
9 49Tuesday, May 05, 2015
9 49Tuesday, May 05, 2015
5
4
3
2
1
U20E
SPI - FLASH
PCH_SPI1_CLK
PCH_SPI1_SO
PCH_SPI1_SI
PCH_SPI_IO2
PCH_SPI_IO3
D D
SIO_EXT_SMI#35
PCI_SERR#35
C C
PCH_SPI_CS0#
SPI1_CLK
TP59
SIO_EXT_SMI#
PCI_SERR#
SPI1_IO2
SPI1_IO3
TP75
TP73
SPI1_CS#
TP57
EC_RCIN#35
SERIRQ32,35
AW3
AW2
AW13
AY11
AV2
AV3
AU4
AU3
AU2
AU1
M2
M3
J4
V1
V2
M1
G3
G2
G1
SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_IO2
SPI0_IO3
SPI0_CS0#
SPI0_CS1#
SPI0_CS2#
SPI - TOUCH
GPP_D1/SPI1_CLK
GPP_D2/SPI1_MISO
GPP_D3/SPI1_MOSI
GPP_D21/SPI1_IO2
GPP_D22/SPI1_IO3
GPP_D0/SPI1_CS#
C LINK
CL_CLK
CL_DATA
CL_RST#
GPP_A0/RCIN#
GPP_A6/SERIRQ
*SKL_ULT
REV = 1
GPIO Pull UP
SERIRQ
CLKRUN#
SIO_EXT_SMI#
EC_RCIN#
PCI_SERR#
+3V
R532 10K_4
R528 8.2K/F_4 R107 499/F_4
R444 10K_4
R218 10K_4
R446 10K_4
SMB_PCH_CLK
SMB_PCH_DAT
SMB_ME0_CLK
SMB_ME0_DAT
SMB_ME1_CLK
SMB_ME1_DAT
R94 2.2K_4
R92 2.2K_4
R464 499/F_4
R457 1K_4
R455 1K_4
SKL_ULT
SMBUS, SMLINK
GPP_B23/SML1ALERT#/PCHHOT#
LPC
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
GPP_A5/LFRAME#/ESPI_CS#
GPP_A14/SUS_STAT#/ESPI_RESET#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
GPP_A10/CLKOUT_LPC1
PDC
5 OF 20
+3V 2,4,11,12,13,14,15,16,17,18,20,27,28,29,30,31,32,33,34,35,41,43,44
+3VS5 4,15,16,32,34,35,37,39,40,43,46
+3V_DEEP_SUS 4,11,12,14,15,16,18
PCH SPI ROM(CLG)
+3V_DEEP_SUS
Vender P/N
EON
Winbond
GigaDevice
Socket
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C2/SMBALERT#
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C5/SML0ALERT#
GPP_C6/SML1CLK
GPP_C7/SML1DATA
GPP_A8/CLKRUN#
Size
8MB
8MB
R7
SMB_PCH_CLK
R8
SMB_PCH_DAT
R10
R9
W2
W1
W3
V3
AM7
AY13
BA13
BB13
AY12
BA12
BA11
AW9
AY9
AW11
SML0ALERT#
SMB_ME0_CLK
SMB_ME0_DAT
SML1ALERT#
SMB_ME1_CLK
SMB_ME1_DAT
GPP_B23
CLK_PCI_EC_R
CLK_PCI_LPC_R
CLKRUN#
SML0ALERT# 11
SML1ALERT# 11
LAD0 32,34,35
LAD1 32,34,35
LAD2 32,34,35
LAD3 32,34,35
LFRAME# 32,34,35
R186 22/F_4
R182 22/F_4
CLKRUN# 35
R185 *22/F_4
TP22
SI Change
AKE3EZN0Q01 (EN25QH64-104HIP)8MB
AKE3EFP0N07 (W25Q64FVSSIQ)
AKE2EZN0Q00 (GD25B64CSIGR)
DFHS08FS023 (HOUSING 8P 2R FS)
EC26 18P/50V_4
EC22 18P/50V_4
EC23
*18P/50V_4
CLK_24M_KBC 35
CLK_24M_DEBUG 34
EMI(near PCH)
CLK_PCI_TPM 32
EMI(near PCH)
4M SPI ROM Socket
+3VSPI
10
U18
1
6
5
2
3
W25Q64FVSSIQ
AKE3EFP0N07
soic8-7_9-1_27-2_16h
R489 *0_4
R490 0_4
+3VSPI
R453 1K/F_4
R452 15/F_4
PCH_SPI_IO3
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
NB5
NB5
NB5
Date: Sheet of
Date: Sheet of
Date: Sheet of
+3V_DEEP_SUS
CE#
SCK
SI
SO
WP#
VDD
HOLD#
VSS
PCH_SPI_CS0#_R
PCH_SPI1_CLK_R
PCH_SPI1_SI_R
PCH_SPI1_SO_R
BIOS_WP#
+3VS5
8
7
HOLD#
4
PCH_SPI_CS0#_R35
PCH_SPI1_CLK_R35
PCH_SPI1_SI_R35
B B
SMBus/Pull-up(CLG)
PCH_SPI_CS0#_R
TP53
PCH_SPI1_CLK_R
Q35
MBCLK218,27,35
MBDATA218,27,35
R95 4.7K_4
+3V
SMB_RUN_DAT16,17,18,27,31
R91 4.7K_4
A A
+3V
SMB_RUN_CLK16,17,18,27,31
5
4 3
1
*2N7002DW
Q13
4 3
1
2N7002KDW
+3V
5
SMB_ME1_CLK
2
6
SMB_ME1_DAT
+3V
5
SMB_PCH_DAT
2
6
SMB_PCH_CLK
CPU heat pipe local thermal sensor
DDR thermal sensor
RTD2136
EC
Touch Pad
XDP
DDR3-L
4
TP66-71 need place to TOP
3
TP79
PCH_SPI1_SI_R
TP72
PCH_SPI1_SO_R
TP50
BIOS_WP#
TP45
HOLD#
TP69
PCH_SPI_CS0#
PCH_SPI1_CLK
R457/R453/R450/R451/R546/R548 close to U15 pin
C620 1U/10V_4
+3VSPI
PCH_SPI_IO2
U18&U19 footprint
R424 15/F_4
R461 15/F_4
R454 15/F_4
R415 15/F_4
R422 1K/F_4
R423 15/F_4
Change to 1K for CRB
PCH_SPI1_SO_R35
PCH SPI ROM(CLG)
U19
PCH_SPI_CS0#_R
PCH_SPI1_CLK_R
PCH_SPI1_SI_RPCH_SPI1_SI
PCH_SPI1_SO_RPCH_SPI1_SO
C616
22P/50V_4
BIOS_WP#
1
6
5
2
3
*EN25QH64-104HIP
AKE3EZN0Q01
2
8
CE#
VDD
SCK
SI
7
HOLD#
HOLD#
4
VSS
SO
WP#
Change to 1K for CRB
C626
0.1U/16V_4
PROJECT : X1B-10L
PROJECT : X1B-10L
PROJECT : X1B-10L
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
SKYPAKE 14/20(SPI/LPC/SMBUS)
SKYPAKE 14/20(SPI/LPC/SMBUS)
SKYPAKE 14/20(SPI/LPC/SMBUS)
1
1A
1A
1A
10 49Tuesday, May 05, 2015
10 49Tuesday, May 05, 2015
10 49Tuesday, May 05, 2015
5
4
3
2
1
11
D D
DESIGN NOTE:
WEAK PULL UP RESISTOR PRESENT ON THIS NET
ACZ_SPKR14,29
C C
SML0ALERT#10
B B
GSPI1_MOSI14
ACZ_SPKR
SML0ALERT#
GSPI1_MOSI
R507
*20K/F_4
+3V_DEEP_SUS
R99
1K_4
R102
*20K/F_4
R152
*20K/F_4
Functional Strap Definitions
+3V_DEEP_SUS
TOP SWAP OVERRIDE
HIGH - TOP SWAP ENABLE
LOW-DISABLED
HIGH: LPC SELECTED FOR SYSTEM FLASH
WEAK INTERNAL PD
No Boot:
The signal has a weak internal pull-down.
0 = Disable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (no confidentiality).
1 = Enable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (with confidentiality). Must be
pulled up to support Intel AMT with TLS and Intel
SBA (Small Business Advantage) with TLS.
+3V 2,4,10,12,13,14,15,16,17,18,20,27,28,29,30,31,32,33,34,35,41,43,44
+3V_DEEP_SUS 4,10,12,14,15,16,18
No Boot:
The signal has a weak internal pull-down.
This field determines the destination of accesses to the
BIOS memory range. Also controllable using Boot BIOS
Destination bit (Chipset Configuration Registers: Offset
3410h:Bit 10). This strap is used in conjunction with Boot
BIOS Destination Selection 0 strap.
Bit 10 Boot BIOS Destination
0 SPI
1 LPC
ACZ_SDOUT14
GPP_B1814
SML1ALERT#10
ACZ_SDOUT
GPIO33_EC35
GPP_B18
SML1ALERT#
R533
*4.7K_4
R311 1K_4
+3V_DEEP_SUS
No Boot:
The signal has a weak internal pull-down.
0 = Enable security measures defined in the Flash
Descriptor.
1 = Disable Flash Descriptor Security (override). This
strap should only be asserted high using external
pull-up in manufacturing/debug environments ONLY.
This function is useful when running ITP/XDP.
ACZ_SDOUT
+3V
R159
*4.7K_4
R462
20K/F_4
No Boot:
The signal has a weak internal pull-down.
0 = Disable No Reboot mode.
1 = Enable No Reboot mode
(PCH will disable the TCO
Timer system reboot feature).
This function is useful when running ITP/XDP.
R162
10K_4
No Boot:
The signal has a weak internal pull-down.
0 = LPC Is selected for EC.
R463
*10K_4
1 = eSPI Is selected for EC.
A A
PROJECT : X1B-10L
PROJECT : X1B-10L
PROJECT : X1B-10L
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
NB5
NB5
NB5
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
SKYPAKE 15/20(HDA)
SKYPAKE 15/20(HDA)
SKYPAKE 15/20(HDA)
1
1A
1A
1A
11 49Tuesday, May 05, 2015
11 49Tuesday, May 05, 2015
11 49Tuesday, May 05, 2015
5
4
3
2
1
Port0
Port1
Port2
Port3
Port4
Port5
SKL_ULT
PDC
Function
Un-used
CardReader
WLAN
LAN
VGA
Un-used
SSIC / USB3
USB3_2_RXN/SSIC_1_RXN
USB3_2_RXP/SSIC_1_RXP
USB3_2_TXN/SSIC_1_TXN
USB3_3_RXN/SSIC_2_RXN
USB3_3_RXP/SSIC_2_RXP
USB3_3_TXN/SSIC_2_TXN
USB2
GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
8 OF 20
USB3_1_RXN
USB3_1_RXP
USB3_1_TXN
USB3_1_TXP
USB3_2_TXP/SSIC_1_TXP
USB3_3_TXP/SSIC_2_TXP
USB3_4_RXN
USB3_4_RXP
USB3_4_TXN
USB3_4_TXP
USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9
USB2P_9
USB2N_10
USB2P_10
USB2_COMP
USB2_ID
USB2_VBUSSENSE
GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2
GPP_E8/SATALED#
H8
G8
C13
D13
J6
H6
B13
A13
J10
H10
B15
A15
E10
F10
C15
D15
AB9
AB10
AD6
AD7
AH3
AJ3
AD9
AD10
AJ1
AJ2
AF6
AF7
AH1
AH2
AF8
AF9
AG1
AG2
AH7
AH8
AB6
AG3
AG4
A9
C9
D9
B9
J1
J2
J3
H2
H3
G4
H1
USB30_RX1USB30_RX1+
USB30_TX1USB30_TX1+
USB30_RX2USB30_RX2+
USB30_TX2USB30_TX2+
USB30_RX3USB30_RX3+
USB30_TX3USB30_TX3+
USB2_COMP
R136 113/F_4
DGPU_HOLD_RST#
GPU_EVENT#
DGPU_PWR_EN
DGPU_PWROK
GC6_FB_EN
DEVSLP1
OCP_OC#
ACC_LED#
ODD_PRSNT#_R
SATAGP2
R436 *0_4/S
USBP1USBP1+
USBP2USBP2+
USBP3USBP3+
USBP6USBP6+
USBP7USBP7+
USBP8USBP8+
DGPU_HOLD_RST# 19
GPU_EVENT# 22
DGPU_PWR_EN 20,46
ACC_LED# 34
USB30_RX1- 33
USB30_RX1+ 33
USB30_TX1- 33
USB30_TX1+ 33
USB30_RX2- 33
USB30_RX2+ 33
USB30_TX2- 33
USB30_TX2+ 33
USB30_RX3- 30
USB30_RX3+ 30
USB30_TX3- 30
USB30_TX3+ 30
USBP1- 33
USBP1+ 33
USBP2- 30
USBP2+ 30
USBP3- 28
USBP3+ 28
USBP6- 30
USBP6+ 30
USBP7- 34
USBP7+ 34
USBP8- 32
USBP8+ 32
PLACE 'R10387' WITHIN 500 MILS
FROM USB2_COMP PIN WITH
TRACE IMPEDANCE LESS THAN 0.5 OHMS
DGPU_PWROK 21,35,45
GC6_FB_EN 20,22
TP55
TP54
R431 *0_4
TP40
SATA_LED#SATA_LED#_R
USB3.0 Port Mapping Table
USB3.0 Function
PORT-1
PORT-2
PORT-3
USB3.0 MB-1
USB3.0 3D CAMERA
Cobime USB3.0 Smaii Board
PORT-4 NC
+3V 2,4,10,11,13,14,15,16,17,18,20,27,28,29,30,31,32,33,34,35,41,43,44
+3V_DEEP_SUS 4,10,11,14,15,16,18
3
USB3.0 (M/B-1)
USB3.0 (3D CAMERA)
SI Add
USB3.0 Small Board
Combo USB3.0 MB-1
Combo USB3.0 Small Board
Camera
Combo USB3.0 Small Board
WLAN
Touch Screen
ZERO_ODD_DP# 34
SATA_LED# 34
2
GPU_EVENT#
DGPU_HOLD_RST#
DGPU_PWR_EN
DGPU_PWROK
SATA_LED#
GC6_FB_EN
ODD_PRSNT#_R
DGPU_HOLD_RST#
R427 *10K_4
R414 *10K_4
R77 10K_4
R428 10K_4
R439 10K_4
R440 *10K_4
R433 10K_4
R587 100K_4
SI Add
SI Change +3V to +3V_DEEP_SUS
ACC_LED#
R441 10K_4
USB2.0 Port Mapping Table
USB2.0 Function
PORT-1
PORT-2
PORT-3
PORT-4
PORT-5
PORT-6
PORT-7
PORT-8
PORT-9
PORT-10
Cobime USB3.0 MB-1
Cobime USB3.0 Smaii Board
Camera
NC
NC
Cobime USB3.0 Smaii Board
WLAN
Touch Screen
NC
NC
PROJECT : X1B-10L
PROJECT : X1B-10L
PROJECT : X1B-10L
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
NB5
NB5
NB5
Date: Sheet of
Date: Sheet of
Date: Sheet of
+3V
+3V_DEEP_SUS
SKYPAKE 16/20 (PCIE/USB)
SKYPAKE 16/20 (PCIE/USB)
SKYPAKE 16/20 (PCIE/USB)
1
12
12 49Tuesday, May 05, 2015
12 49Tuesday, May 05, 2015
12 49Tuesday, May 05, 2015
1A
1A
1A
U20H
PCIE/USB3/SATA
PEG_RXN119
PEG_RXP119
PEG_TXN119
PCIE_RXN5_CARD30
PCIE_RXP5_CARD30
PCIE_TXN5_CARD30
PCIE_TXP5_CARD30
PCIE_RXN6_WLAN34
PCIE_RXP6_WLAN34
PCIE_TXN6_WLAN34
PCIE_TXP6_WLAN34
PCIE_RXN9_LAN30
PCIE_RXP9_LAN30
PCIE_TXN9_LAN30
PCIE_TXP9_LAN30
PEG_TXP119
PEG_RXN219
PEG_RXP219
PEG_TXN219
PEG_TXP219
PEG_RXN319
PEG_RXP319
PEG_TXN319
PEG_TXP319
PEG_RXN419
PEG_RXP419
PEG_TXN419
PEG_TXP419
SATA_RXN034
SATA_RXP034
SATA_TXN034
SATA_TXP034
SATA_RXN134
SATA_RXP134
SATA_TXN134
SATA_TXP134
+3V_DEEP_SUS
D D
dGPU
Cardreader
WLAN
HDD
C C
ODD
LAN
B B
XDP_PRDY#_CPU16
XDP_PREQ#_CPU16
C608 0.22U/10V_4
C607 0.22U/10V_4
C592 0.22U/10V_4
C591 0.22U/10V_4
C589 0.22U/10V_4
C590 0.22U/10V_4
C587 0.22U/10V_4
C588 0.22U/10V_4
C605 0.1U/16V_4
C606 0.1U/16V_4
C603 0.1U/16V_4
C604 0.1U/16V_4
C609 0.1U/16V_4
C598 0.1U/16V_4
R105 100/F_4
R193 10K_4
PCIE_TXN5_CARD_C
PCIE_TXP5_CARD_C
PCIE_TXN6_WLAN_C
PCIE_TXP6_WLAN_C
PCIE_TXN9_LAN_C
PCIE_TXP9_LAN_C
PCIE_RCOMPN
PCIE_RCOMPP
PIRQA#
PEG_TXN1_C
PEG_TXP1_C
PEG_TXN2_C
PEG_TXP2_C
PEG_TXN3_C
PEG_TXP3_C
PEG_TXN4_C
PEG_TXP4_C
H13
PCIE1_RXN/USB3_5_RXN
G13
PCIE1_RXP/USB3_5_RXP
B17
PCIE1_TXN/USB3_5_TXN
A17
PCIE1_TXP/USB3_5_TXP
G11
PCIE2_RXN/USB3_6_RXN
F11
PCIE2_RXP/USB3_6_RXP
D16
PCIE2_TXN/USB3_6_TXN
C16
PCIE2_TXP/USB3_6_TXP
H16
PCIE3_RXN
G16
PCIE3_RXP
D17
PCIE3_TXN
C17
PCIE3_TXP
G15
PCIE4_RXN
F15
PCIE4_RXP
B19
PCIE4_TXN
A19
PCIE4_TXP
F16
PCIE5_RXN
E16
PCIE5_RXP
C19
PCIE5_TXN
D19
PCIE5_TXP
G18
PCIE6_RXN
F18
PCIE6_RXP
D20
PCIE6_TXN
C20
PCIE6_TXP
F20
PCIE7_RXN/SATA0_RXN
E20
PCIE7_RXP/SATA0_RXP
B21
PCIE7_TXN/SATA0_TXN
A21
PCIE7_TXP/SATA0_TXP
G21
PCIE8_RXN/SATA1A_RXN
F21
PCIE8_RXP/SATA1A_RXP
D21
PCIE8_TXN/SATA1A_TXN
C21
PCIE8_TXP/SATA1A_TXP
E22
PCIE9_RXN
E23
PCIE9_RXP
B23
PCIE9_TXN
A23
PCIE9_TXP
F25
PCIE10_RXN
E25
PCIE10_RXP
D23
PCIE10_TXN
C23
PCIE10_TXP
F5
PCIE_RCOMPN
E5
PCIE_RCOMPP
D56
PROC_PRDY#
D61
PROC_PREQ#
BB11
GPP_A7/PIRQA#
E28
PCIE11_RXN/SATA1B_RXN
E27
PCIE11_RXP/SATA1B_RXP
D24
PCIE11_TXN/SATA1B_TXN
C24
PCIE11_TXP/SATA1B_TXP
E30
PCIE12_RXN/SATA2_RXN
F30
PCIE12_RXP/SATA2_RXP
A25
PCIE12_TXN/SATA2_TXN
B25
PCIE12_TXP/SATA2_TXP
*SKL_ULT
REV = 1
PCI-E Port Mapping Table
PCI-E Port
Port1
Port2
Port3
Port4
Port5
A A
Port6
Port7
Port8
Port9
Port10
5
Function
dGPU
dGPU
dGPU
dGPU
CardReader
WLAN
HDD
ODD
LAN
Un-used
CLK RQ Port
4
5
4
3
2
1
13
REV = 1
SKL_ULT
SKL_ULT
CLOCK SIGNALS
10 OF 20
PDC
9 OF 20
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
GPD8/SUSCLK
XCLK_BIASREF
TBT
CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3
CSI2_COMP
GPP_D4/FLASHTRIG
EMMC
GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7
GPP_F21/EMMC_RCLK
GPP_F22/EMMC_CLK
GPP_F12/EMMC_CMD
EMMC_RCOMP
XTAL24_IN
XTAL24_OUT
RTCX1
RTCX2
SRTCRST#
RTCRST#
C37
D37
C32
D32
C29
D29
B26
A26
E13
B7
AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1
AM2
AM3
AP4
AT1
F43
CK_XDP_N_R
E43
CK_XDP_P_R
BA17
E37
XTAL24_IN
E35
XTAL24_OUT
E42
XCLK_BIASREF
AM18
RTC_X1
AM20
RTC_X2
AN18
SRTC_RST#
AM16
RTC_RST#
GPP_D4
GPP_F13
GPP_F14
GPP_F15
GPP_F16
GPP_F17
GPP_F18
GPP_F19
GPP_F20
EMMC_RCLK
EMMC_CLK
EMMC_CMD
EMMC_RCOMP
RP1 install for XDP
RP3 *0_4P2R_4
2
4
TP74
RTC_RST# 16
TP42
TP99
TP102
TP100
TP95
TP98
TP96
TP94
TP97
TP93
TP92
TP101
R501 200/F_4
R86
100/F_4
1
3
CK_XDP_N 16
CK_XDP_P 16
CLK_REQ/Strap Pin(CLG)
+1.0V_DEEP_SUS
R406
2.7K/F_4
XCLK_BIASREF
R582
*60.4/F_4
Cannonlake-U Stuff R582.
PCIE_CLKREQ_VGA#
PCIE_CLKREQ_WLAN#
PCIE_CLKREQ_LAN#
PCIE_CLKREQ_CR#
PCIE_CLKREQ5#
PCIE_CLKREQ0#
R155 10K_4
R167 10K_4
R176 10K_4
R165 10K_4
R170 10K_4
R174 10K_4
+3V
SI Modify port 4 Change to port 0
VGA
D D
Cardreader
WLAN
LAN
CLK_VGA_N19
CLK_VGA_P19
PCIE_CLKREQ_VGA#19
CLK_PCIE_CRN30
CLK_PCIE_CRP30
PCIE_CLKREQ_CR#30
CLK_PCIE_WLANN34
CLK_PCIE_WLANP34
PCIE_CLKREQ_WLAN#34
CLK_PCIE_LANN30
CLK_PCIE_LANP30
PCIE_CLKREQ_LAN#30
SI Modify port 0 Change to port 4
C C
CLK_VGA_N
CLK_VGA_P
PCIE_CLKREQ_VGA#
CLK_PCIE_CRN
CLK_PCIE_CRP
PCIE_CLKREQ_CR#
CLK_PCIE_WLANN
CLK_PCIE_WLANP
PCIE_CLKREQ_WLAN#
CLK_PCIE_LANN
CLK_PCIE_LANP
PCIE_CLKREQ_LAN#
PCIE_CLKREQ0#
PCIE_CLKREQ5#
U20J
D42
CLKOUT_PCIE_N0
C42
CLKOUT_PCIE_P0
AR10
GPP_B5/SRCCLKREQ0#
B42
CLKOUT_PCIE_N1
A42
CLKOUT_PCIE_P1
AT7
GPP_B6/SRCCLKREQ1#
D41
CLKOUT_PCIE_N2
C41
CLKOUT_PCIE_P2
AT8
GPP_B7/SRCCLKREQ2#
D40
CLKOUT_PCIE_N3
C40
CLKOUT_PCIE_P3
AT10
GPP_B8/SRCCLKREQ3#
B40
CLKOUT_PCIE_N4
A40
CLKOUT_PCIE_P4
AU8
GPP_B9/SRCCLKREQ4#
E40
CLKOUT_PCIE_N5
E38
CLKOUT_PCIE_P5
AU7
GPP_B10/SRCCLKREQ5#
*SKL_ULT
REV = 1
A36
B36
C38
D38
C36
D36
A38
B38
C31
D31
C33
D33
A31
B31
A33
B33
A29
B29
C28
D28
A27
B27
C27
D27
U20I
CSI-2
CSI2_DN0
CSI2_DP0
CSI2_DN1
CSI2_DP1
CSI2_DN2
CSI2_DP2
CSI2_DN3
CSI2_DP3
CSI2_DN4
CSI2_DP4
CSI2_DN5
CSI2_DP5
CSI2_DN6
CSI2_DP6
CSI2_DN7
CSI2_DP7
CSI2_DN8
CSI2_DP8
CSI2_DN9
CSI2_DP9
CSI2_DN10
CSI2_DP10
CSI2_DN11
CSI2_DP11
*SKL_ULT
B B
RTC Clock 32.768KHz RTC Circuitry(RTC)
R456 *0_4
C614 18P/50V_4
Y3
32.768KHZ
C611 18P/50V_4
A A
RTC_X1
23
R451
10M_4
4 1
RTC_X2
5
CLKGEN_RTC_X1 32
+3V_RTC_0
+3V_RTC_0
12
RTC Power trace width 20mils.
+3VPCU
R380 1K_4
CN9
BAT_CONN
DFHS02FS058
Uninstall for Green-CLK
BAT-23_2-4_2
4
+3V_RTC_1
D12
BAT54CW-7-F
+3V 2,4,10,11,12,14,15,16,17,18,20,27,28,29,30,31,32,33,34,35,41,43,44
+3V_RTC 4,15,32
+3V_RTC_0 32
+1.0V_DEEP_SUS 9,15,16,39,40
R376
20K/F_4
R379
20K/F_4
DB Change to Pad
J1 *0_4
RTC_RST#
C543
1U/6.3V_4
SRTC_RST#
C545
1U/6.3V_4
R377 *0_4
3
30mils
+3V_RTC
C544
1U/6.3V_4
External Crystal and Green Clock
R401 *0_4
TP44
C594 10P/50V_4
1
XTAL24_IN
RTC_RST#
3
Q34
DMN601K-7
SRTC_RST#RTC_RST#
2
1
R378
10K_4
EC_RTC_RST 35
XTAL24_OUT
2
R413
1M_4
2
Y2
24MHZ +-30PPM
4
3
C595 10P/50V_4
TP43
PCH_XTAL24_IN 32
The 24 MHz (50 Ohm ESR)
XTAL used for Skylake-U needs
to be replaced by 38.4MHz
(30 OhmESR) XTAL for Cannonlake-U
SI Change
PROJECT : X1B-10L
PROJECT : X1B-10L
PROJECT : X1B-10L
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
NB5
NB5
NB5
Date: Sheet of
Date: Sheet of
Date: Sheet of
SKYPAKE 17/20 (CLK)
SKYPAKE 17/20 (CLK)
SKYPAKE 17/20 (CLK)
1
1A
1A
1A
13 49Tuesday, May 05, 2015
13 49Tuesday, May 05, 2015
13 49Tuesday, May 05, 2015
5
4
3
2
1
Skylake (GPIO)
BA22
HDA_SYNC/I2S0_SFRM
AY22
HDA_BLK/I2S0_SCLK
BB22
HDA_SDO/I2S0_TXD
BA21
HDA_SDI0/I2S0_RXD
AY21
HDA_SDI1/I2S1_RXD
AW22
HDA_RST#/I2S1_SCLK
J5
GPP_D23/I2S_MCLK
AY20
I2S1_SFRM
AW20
I2S1_TXD
AK7
GPP_F1/I2S2_SFRM
AK6
GPP_F0/I2S2_SCLK
AK9
GPP_F2/I2S2_TXD
AK10
GPP_F3/I2S2_RXD
H5
GPP_D19/DMIC_CLK0
D7
GPP_D20/DMIC_DATA0
D8
GPP_D17/DMIC_CLK1
C8
GPP_D18/DMIC_DATA1
AW5
GPP_B14/SPKR
3
ACZ_SYNC_AUDIO29
ACZ_RST#_AUDIO29
ACZ_SDOUT_AUDIO29
U20G
*SKL_ULT
REV = 1
SKL_ULT
+3V_DEEP_SUS
BIT_CLK_AUDIO29
AUDIO
GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL
GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL
GPP_F10/I2C5_SDA/ISH_I2C2_SDA
GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
6 OF 20
GPP_D15/ISH_UART0_RTS#
GPP_D16/ISH_UART0_CTS#/SML0BALERT#
GPP_C12/UART1_RXD/ISH_UART1_RXD
GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#
GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5
GPP_A12/BM_BUSY#/ISH_GP6
HDA Bus(CLG)
R525 *1K_4
R224 33_4
R534 33_4
R225 33_4
R524 33_4
*10P/50V_4
SKL_ULT
ACZ_SYNC
ACZ_SYNC
ACZ_RST#
ACZ_SDOUT
ACZ_BCLK
SDIO/SDXC
GPP_A17/SD_PWR_EN#/ISH_GP7
7 OF 20
P2
GPP_D9
P3
GPP_D10
P4
GPP_D11
P1
GPP_D12
M4
N3
N1
N2
AD11
AD12
U1
U2
U3
U4
AC1
AC2
AC3
AB4
AY8
BA8
BB7
BA7
AY7
AW7
AP13
GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3
GPP_G5/SD_CD#
GPP_G6/SD_CLK
GPP_G7/SD_WP
GPP_A16/SD_1P8_SEL
SD_RCOMP
2
GPP_D9
3D_CAM_EN_PCH 3D_CAM_EN
GPP_D11
BT_OFF
ISH_I2C0_SDA
ISH_I2C0_SCL
ISH_I2C1_SDA
ISH_I2C1_SCL
ISH_I2C2_SDA
ISH_I2C2_SCL
PCH_TEMPALERT#
SML0BDATA
SML0BCLK
SML0BALERT#
UART1_RXD
UART1_TXD
UART1_RTS
UART1_CTS
GPP_A19
GPP_A20
GPP_A21
GPP_A22
GPP_A23
GPP_A12
AB11
AB13
AB12
W12
W11
W10
W8
W7
BA9
BB9
AB7
AF13
GPP_F23
TP65
R609 *0_4
TP66
TP60
TP61
TP62
TP58
TP3
TP2TP76
TP67
TP70
TP68
TP71
TP84
TP83
TP85
TP81
TP108
TP109
TP106
TP107
TP104
TP12
BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4
BOARD_ID5
BOARD_ID6
BOARD_ID7
BOARD_ID8
GPP_A16
GPP_F23
BT_OFF 34
SI Del TP110
R135 200/F_4
GPP_A16 33
TP9
NB5
NB5
NB5
SI Add
3D_CAM_EN 35,43
SI Add
PROJECT : X1B-10L
PROJECT : X1B-10L
PROJECT : X1B-10L
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
SKYPAKE 19/20 (GPIO)
SKYPAKE 19/20 (GPIO)
SKYPAKE 19/20 (GPIO)
1
ACZ_SPKR11,29
U20F
AN8
GPP_B15/GSPI0_CS#
AP7
GPP_B16/GSPI0_CLK
AP8
GPP_B17/GSPI0_MISO
AR7
GPP_B18/GSPI0_MOSI
AM5
GPP_B19/GSPI1_CS#
AN7
GPP_B20/GSPI1_CLK
AP5
GPP_B21/GSPI1_MISO
AN5
GPP_B22/GSPI1_MOSI
AB1
GPP_C8/UART0_RXD
AB2
GPP_C9/UART0_TXD
W4
GPP_C10/UART0_RTS#
AB3
GPP_C11/UART0_CTS#
AD1
GPP_C20/UART2_RXD
AD2
GPP_C21/UART2_TXD
AD3
GPP_C22/UART2_RTS#
AD4
GPP_C23/UART2_CTS#
U7
GPP_C16/I2C0_SDA
U6
GPP_C17/I2C0_SCL
U8
GPP_C18/I2C1_SDA
U9
GPP_C19/I2C1_SCL
AH9
GPP_F4/I2C2_SDA
AH10
GPP_F5/I2C2_SCL
AH11
GPP_F6/I2C3_SDA
AH12
GPP_F7/I2C3_SCL
AF11
GPP_F8/I2C4_SDA
AF12
GPP_F9/I2C4_SCL
*SKL_ULT
TP14
TP13
TP21
TP20
TP1
TP49
TP41
TP48
LPSS ISH
REV = 1
ACZ_SYNC
ACZ_BCLK
ACZ_SDOUT
ACZ_SDIN0
ACZ_RST#
SSP2_SFRM
SSP2_SCLK
SSP2_TXD
SSP2_RXD
GPP_D19
GPP_D20
GPP_D17
GPP_D18
ACZ_SPKR
+3V_DEEP_SUS
R448 10K_4
D D
C C
B B
Skylake
U
R449 10K_4
R154 10K_4
+3V
R491 10K_4
R130 *10K_4
R140 10K_4
R116 *10K_4
R113 10K_4
R126 10K_4
R138 10K_4
R118 10K_4
R523 10K_4
BOARD_ID[8:7]
Model
A A
Definition
00 Non 3D SKU
01 3D SKU
00 1.1
01 2.0
5
BT_OFF
PCH_TEMPALERT#
SIO_EXT_SCI#
ACCEL_INTA#
BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4
BOARD_ID5
BOARD_ID6
BOARD_ID7
BOARD_ID8
00 Single Rank (X1B)
01 Dual Rank (X1B)
10 Meso-AMD (X1A)
11 Reserve
GPP_B15
TP25
GPP_B16
TP30
GPP_B17
+3V_DEEP_SUS
R585
R584
49.9K/F_4
49.9K/F_4
UART2_RXD33
UART2_TXD33
R131 10K_4
R150 10K_4R146 *10K_4
R147 *10K_4 C645
R115 10K_4
R111 *10K_4
R125 *10K_4
R141 *10K_4
R119 *10K_4
R519 *10K_4
+3V_DEEP_SUS
TP31
TP19
TP26
TP27
TP82
TP78
TP77
TP63
TP80
TP5
TP6
TP10
TP8
TP7
TP4
GPP_B18
GPP_B19
GPP_B20
GPP_B21
GSPI1_MOSI
GPP_C8
GPP_C9
GPP_C10
GPP_C11
GPP_C20
GPP_C21
ACCEL_INTA#
SIO_EXT_SCI#
I2C1_SDA
I2C1_SCL
I2C2_SDA
I2C2_SCL
I2C3_SDA
I2C3_SCL
I2C4_SDA
I2C4_SCL
ACZ_SDOUT11
ACZ_SDIN029
GPP_B1811
GSPI1_MOSI11
ACCEL_INTA#32
SIO_EXT_SCI#35
+3V 2,4,10,11,12,13,15,16,17,18,20,27,28,29,30,31,32,33,34,35,41,43,44
+3V_DEEP_SUS 4,10,11,12,15,16,18
BOARD_ID[2:1]BOARD_ID[6:5] BOARD_ID0Board ID [4:3]
ID0ID2 ID1ID4 ID3ID6 ID5ID8 ID7
00 14"
01 15"
0UMA
1DIS
10 17"
11 Reserve
4
14
14 49Tuesday, May 05, 2015
14 49Tuesday, May 05, 2015
14 49Tuesday, May 05, 2015
1A
1A
1A
5
4
3
2
1
15
D D
AB19
VCCPRIM_1P0
AB20
VCCPRIM_1P0
P18
VCCPRIM_1P0
AF18
VCCPRIM_CORE
AF19
VCCPRIM_CORE
V20
VCCPRIM_CORE
V21
VCCPRIM_CORE
AL1
DCPDSW_1P0
K17
VCCMPHYAON_1P0
L1
VCCMPHYAON_1P0
N15
VCCMPHYGT_1P0_N15
N16
VCCMPHYGT_1P0_N16
N17
VCCMPHYGT_1P0_N17
P15
VCCMPHYGT_1P0_P15
P16
VCCMPHYGT_1P0_P16
K15
VCCAMPHYPLL_1P0
L15
VCCAMPHYPLL_1P0
V15
VCCAPLL_1P0
AB17
VCCPRIM_1P0_AB17
Y18
VCCPRIM_1P0_Y18
AD17
VCCDSW_3P3_AD17
AD18
VCCDSW_3P3_AD18
AJ17
VCCDSW_3P3_AJ17
AJ19
VCCHDA
AJ16
VCCSPI
AF20
VCCSRAM_1P0
AF21
VCCSRAM_1P0
T19
VCCSRAM_1P0
T20
VCCSRAM_1P0
AJ21
VCCPRIM_3P3_AJ21
AK20
VCCPRIM_1P0_AK20
N18
VCCAPLLEBB
C62
*22U/6.3V_6
+VCCPRIM
+VCCDSW_1.0V
+VCCMPHYAON_1P0
+VCCAMPHYPLL_1P0
+VCCAPLL_1.0V
+VCCPRIM
+VCCDSW_3P3
+VCCSPI
+VCCSRAM_1.0V
+VCCPRIM_3.3V
+VCCPRIM_1.0V_AK20
+VCCAPLLEBB
C163 1U/6.3V_4
+1.0V_DEEP_SUS
PCH Internal VRM
C C
+V3.3DX_1.5DX_ADO +1.0V_DEEP_SUS
B B
+1.0V_DEEP_SUS
+1.0V_DEEP_SUS
+1.0V_DEEP_SUS
+1.0V_DEEP_SUS
+1.0V_DEEP_SUS
R200 0_4
+3VS5
DB Del R199
+V3.3DX_1.5DX_ADO
+3V_DEEP_SUS
+1.0V_DEEP_SUS
+3V_DEEP_SUS
+1.0V_DEEP_SUS
+1.0V_DEEP_SUS
R194 0_4
C159 1U/6.3V_4
C627 1U/6.3V_4
R445 0_6
C150 1U/6.3V_4
C87 1U/6.3V_4
C66 47U/6.3VS_6
C69 1U/6.3V_4
C178 1U/6.3V_4
C295 1U/6.3V_4
C120 1U/6.3V_4
C143 1U/6.3V_4
+3V
R72 0_6
R74 0_6
R121 0_6
R190 0_6
R124 0_6
R189 0_6
R450 0_6
R82 0_6
C78
*1U/6.3V_4
U20O
*SKL_ULT
REV = 1
SKL_ULT
CPU POWER 4 OF 4
2.899A
2.57A
1.714A
0.03A
0.09A
VCCPRIM_3P3_V19
VCCRTCPRIM_3P3
GPP_B0/CORE_VID0
GPP_B1/CORE_VID1
15 OF 20
for DS3
VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE
VCCPGPPF
VCCPGPPG
VCCPRIM_1P0_T1
VCCATS_1P8
VCCRTC_AK19
VCCRTC_BB14
DCPRTC
VCCCLK1
VCCCLK2
VCCCLK3
VCCCLK4
VCCCLK5
VCCCLK6
AK15
AG15
Y16
Y15
T16
AF16
AD15
V19
T1
AA1
AK17
AK19
BB14
BB10
A14
K19
L21
N20
L19
A10
AN11
AN13
+VCCPGPPA
+VCCPGPPB
+VCCPGPPC
+VCCPGPPD
+VCCPGPPE
+VCCPGPPF
+VCCPGPPG
+VCCPRIM_1.0V_T1
+VCCATS_1.8V
+VCCRTCPRIM_3.3V
DCPRTC
C248 0.1U/16V_4
+VCCCLK1
+VCCCLK2
+VCCCLK3
+VCCCLK4
+VCCCLK5
+VCCCLK6
CORE_VID0
CORE_VID1
+3V_DEEP_SUS+3VS5
+VCCPGPPA
C170
1U/6.3V_4
+VCCPGPPB
+VCCPGPPC
+VCCPGPPD
+VCCPGPPE
+VCCPGPPG
+VCCPGPPF
C208 1U/6.3V_4 R137 0_6
R143 0_6
R488 0_6
R139 0_6
R83 0_6
R58 0_6
R61 0_6
R80 0_6
R81 0_6
R73 0_6
C101 1U/6.3V_4
TP23
TP16
1U/6.3V_4
+3V_DEEP_SUS
+1.0V_DEEP_SUS
+1.8V_DEEP_SUS
+3V_DEEP_SUS
+3V_RTC
+1.0V_DEEP_SUS
+VCCATS_1.8V +3V_RTC +VCCPGPPB
C619
C314
0.1U/16V_4
C321
1U/6.3V_4
R145 0_6
R123 0_6
R129 0_6
R117 0_6
R132 0_6
R487 0_6
+3V_DEEP_SUS
+1.8V_DEEP_SUS
R97
100K_4
SLP_SUS_ON35,39,40
A A
5
4
C108
1U/6.3V_4
C109
*10P/50V_4
U6
5
IN
4
IN
3
ON/OFF
IC(5P) G5243AT11U-Lay
+3V 2,4,10,11,12,13,14,16,17,18,20,27,28,29,30,31,32,33,34,35,41,43,44
+3VS5 4,10,16,32,34,35,37,39,40,43,46
+3V_RTC 4,13,32
+3V_DEEP_SUS 4,10,11,12,14,16,18
+1.0V_DEEP_SUS 9,13,16,39,40
+1.8V_DEEP_SUS 9,39
3
OUT
GND
1
2
C110
0.1U/16V_4
+VCCPGPPC +VCCPGPPE
C151
1U/6.3V_4
1U/6.3V_4
2
C131
+VCCRTCPRIM_3.3V
C203
1U/6.3V_4
NB5
NB5
NB5
C184
0.1U/16V_4
PROJECT : X1B-10L
PROJECT : X1B-10L
PROJECT : X1B-10L
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
SKYPAKE 20/20(PCH POWER)
SKYPAKE 20/20(PCH POWER)
SKYPAKE 20/20(PCH POWER)
1
15 49Tuesday, May 05, 2015
15 49Tuesday, May 05, 2015
15 49Tuesday, May 05, 2015
1A
1A
1A
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