QUANTA W Mainboard Series S210-MBT2W Technical Manual

W Mainboard Series

S210-MBT2W

Model Name

Short Description

Technical Guide

Date Modified: August 10, 2012 4:09 pm Document Version: 1.0.0

TABLE OF CONTENTS

I

TABLE OF CONTENTS

About the Server

Overview 1-1

S210-MBT2W Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1

Package Contents 1-5

Functional Architecture 1-6

Processor 1-7

Overview of the Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7

Processor Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7

Turbo Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-8

Processor C-State Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-8

Memory 1-10

General Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-10

DIMM Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-15

DIMM Population Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-16

Memory Error LED and Beep Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-18

TABLE OF CONTENTS

II

Memory Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-18

Suspend to RAM (S3) Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-23

VREF Calibration Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-24

PCI-Express 1-25

Processor PCIe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25

Processor PCIe Port Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-25

PCIe Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25

GPGPU Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25

Slot Power for High Power PCIe Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-27

Nvidia SLI Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-27

ATI CROSSFIREX/PRO Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-27

SMBUS Address MUX for GPGPU Sensor Monitoring Support . . . . . . . . . . . . . . . . . . . . 1-28

Patsburg PCIe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-28

Patsburg PCIe Port Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28

Oversubscription of DMI2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-29

SAS Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29

Riser Support for 3rd Party Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-29

LPC Bus 1-32

Trusted Platform Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-32

TPM Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-32

TABLE OF CONTENTS

III

TPM Clock Requirement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-32

TPM Header Pinout and Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-33

USB 1-34

BIOS USB Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-34

Wake-on-USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-34

USB Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-35

Front Panel USB2.0 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-35

Internal USB2.0 Type-A Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-35

eUSB (Zepher) Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-35

IEEE 1394b 1-37

IEEE 1394b Port Cable and Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-37

Serial Attached SCSI/Serial ATA 1-38

Serial Attached SCSI / Serial ATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-38

Patsburg Dynamic SKU'ing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-38

Baseboard Routing of SAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-39

SAS/SATA Connector Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-39

SATA DOM Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-40

SATA/SAS Connector Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-41

Romley Keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-42

HDD Backplane Support 1-43

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IV

SATA/SAS SGPIO Header. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-43

HSBP I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-43

LAN on Motherboard 1-45

Powerville Thermal Sensor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-45

NIC Status LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-45

MAC Address Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-46

LAN Manageability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-46

LAN Connector Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-46

Wake-on-LAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-46

Video 1-47

Video Connector Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-47

Serial Port 1-49

Wake-On-Ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-49

Front Panel 1-50

Front Panel Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-50

Front Panel LED Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-50

S210-MBT2W IEEE 1394 (Extreme Server SKU Only) . . . . . . . . . . . . . . . . . . . . . . . . .1-51

Clocks 1-54

TABLE OF CONTENTS

V

SMBus 1-55

SMBus Voltage Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-55

SMBus Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-55

General Purpose I/O 1-57

GPIO List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-58

Baseboard SKU and Revision ID 1-75

Error Propagation 1-76

BIOS MICROSOFT WHEA SUPPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-76

PROCHOT#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-76

MEMHOT# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-77

THERMTRIP# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-78

CATERR# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-79

WAKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-80

Power Sequencing and Reset Distribution 1-81

Power Subsystem 1-83

AC Power Supplies (to be updated) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-83

PSU SMBUS Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-83

PSU Redundancy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-84

PSU Signal Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-84

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VI

PWOK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-84

System PSU Bulk Caps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-84

PSU Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-84

SmaRT (Smart Ride Through) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-85

CLST (Closed Loop System Throttle) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-86

PMBUS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-87

System Power Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-87

DC-DC Power Sub-system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-91

Efficiency Targets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-94

VR Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-94

Debug 1-95

XDP SUPPORT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-95

BIOS

BIOS Setup Utility 2-1

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1

Setup Page Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1

Entering BIOS Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2

Keyboard Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2

TABLE OF CONTENTS

VII

Menu Selection Bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4

Server Platform Setup Utility Screens . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5

Main Screen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6

Advanced Screen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-7

PCI Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9

TPM Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-11

WHEA Support Screen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-12

Processor Configuration Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-13

Runtime Error Logging Screen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-18

SATA Controller Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-19

Intel TXT(LT-SX) Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-21

USB Configuration Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-22

Super I/O Configuration Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-23

Onboard Device Configuration Screen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-25

Console Redirection Screen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-26

Chipset Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-29

North Bridge Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-30

South Bridge Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-32

ME Subsystem Screen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-34

TABLE OF CONTENTS

VIII

Server Management Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-35

System Event Log Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-37

FRU Information Screen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-38

BMC Network Configuration Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-40

Boot Option Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-41

Network Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-43

Security Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-44

Image Execution Policy Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-46

Key Management Screen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-47

Exit Screen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-49

Loading BIOS Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-51

BIOS Update Utility 2-52

BIOS Update Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-52

Recovery Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-52

Recovery Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53

Clear CMOS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-54

Clear Password . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-54

Server Management 2-56

Console Redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-56

Serial Configuration Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-56

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IX

Keystroke Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-56

Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57

Interface to Server Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57

PXE Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-57

Checkpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-58

Checkpoint Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-58

Standard Checkpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-59

DXE Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62

ACPI/ASL Checkpoints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-64

OEM-Reserved Checkpoint Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-65

BMC

BMC Web Graphical User Interface for ESMS 3-1

Using the Web GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1

Login . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1

Dashboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3

Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-3

Network Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-4

Sensor Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-4

Event Logs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-5

TABLE OF CONTENTS

X

Server Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-5

FRU Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-6

Server Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-7

Server identify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-8

Server Health Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-9

Sensor Readings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-9

Event Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-11

Configuration Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-12

Active Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-12

DNS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-15

LDAP/E-Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-18

Mouse Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-21

Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-22

PEF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24

RADIUS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32

Remote Session . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-33

SMTP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-34

SOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-37

SSL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-37

User Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-42

TABLE OF CONTENTS

XI

Virtual Media . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-45

Remote Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-46

Console Redirection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-46

Server Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-52

Maintenance Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-53

Firmware Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-54

Preserve Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-55

Restore Factory Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-55

System Administrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-56

Log Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-57

User Privilege . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-57

BMC Server Management Software 3-59

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-59

BMC Key Features and Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-59

Power System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-59

Front Panel User Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-60

Power Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-60

ID Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-60

LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-60

TABLE OF CONTENTS

XII

LAN Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-62

Session and User . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-62

RMCP+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-62

Serial Over LAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-62

Time Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-63

SEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-63

Platform Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-63

Platform Event Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-63

BMC Firmware Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-63

DOS Recovery Utility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-64

WebUI Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-64

Temperature Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-64

Voltage Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-66

Fan Speed Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-67

Processor Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-67

Thermal Trip / Processor Hot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-67

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-67

Watchdog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-67

Pre-Timeout Interrupt Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-67

Timeout Action Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-68

TABLE OF CONTENTS

XIII

IPMI 1.5 / 2.0 Command Support List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-68

BMC Device and Messaging Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-68

BMC Watchdog Timer Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-70

Chassis Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-71

Event Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-71

SEL Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-72

SDR Repository Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-72

FRU Inventory Device Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-73

Sensor Device Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-73

LAN Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-74

SOL Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-75

PEF/PET Alerting Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-75

OEM Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-75

BMC Recovery Process 3-77

Recovery Process in DOS System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-77

Recovery Process in Linux System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-77

Recovery Process in Windows System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-77

TABLE OF CONTENTS

XIV

Jumpers and Connectors

Mainboard Jumpers and Connectors 4-1

Troubleshooting

Troubleshooting 5-1

System does not Boot after Initial Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1

System does not boot after Configuration Changes. . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3

Installation Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-4

Installation and Assembly Safety Instructions

Installation and Assembly Safety Instructions 6-1

Safety Information

Server Safety Information 7-1

Safety Warnings and Cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1

Intended Application Uses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-2

Site Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3

TABLE OF CONTENTS

XV

Equipment Handling Practices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3

Power and Electrical Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-3

Power Cord Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-4

System Access Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-5

Rack Mount Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-6

Electrostatic Discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-7

Other Hazards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-7

Battery Replacement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-7

Cooling and Airflow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-8

Laser Peripherals or Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-8

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-8

Regulatory and Compliance Information

Product Regulatory Compliance Markings 8-1

Electromagnetic Compatibility Notices 8-2

FCC Verification Statement (USA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-2

Europe (CE Declaration of Conformity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-3

VCCI (Japan) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-3

BSMI (Taiwan) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-3

TABLE OF CONTENTS

XVI

Regulated Specified Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-3

Restriction of Hazardous Substances (RoHS) Compliance . . . . . . . . . . . . . . . . . . . . . . . . .8-4

End of Life / Product Recycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-4

CONVENTIONS

XVII

[0.2.1] Conventions

[0.2.2] Several different typographic conventions are used
throughout this manual. Refer to the following examples for
common usage.

[0.2.3] Bold type face denotes menu items, buttons and appli­cation names.

[0.2.4] Italic type face denotes references to other sections, and
the names of the folders, menus, programs, and files.

[0.2.5] <Enter> type face denotes keyboard keys.

[0.2.9]

WARNING!

[0.2.6] Warning information appears before the text it refer-

ences and should not be ignored as the content may prevent
damage to the device.

CAUTION!

[0.2.7] CAUTIONS APPEAR BEFORE THE TEXT IT REFERENCES, SIMI-

LAR TO NOTES AND WARNINGS. CAUTIONS, HOWEVER, APPEAR IN
CAPITAL LETTERS AND CONTAIN VITAL HEALTH AND SAFETY INFOR-
MATION.

Note:

[0.2.8] Highlights general or useful information and tips.

!

!

ACRONYMS

XVIII

[0.3.10] Acronyms

[0.3.11] TERM [0.3.12] DEFINITION

[0.3.13] A/D [0.3.14] Analog to Digital

[0.3.15] ACPI [0.3.16] Advanced Configuration and Power Interface

[0.3.17] ASF [0.3.18] Alerting Standard Forum

[0.3.19] Asserte

d

[0.3.20] Active-high (positive true) signals are
asserted when in the high electrical state (near power
potential). Active-low (negative true) signals are
asserted when in the low electrical state (near ground
potential).

[0.3.21] BIOS [0.3.22] Basic Input/Output System

[0.3.23] BIST [0.3.24] Built-In Self Test

[0.3.25] BMC

[0.3.26] At the heart of the IPMI architecture is a

microcontroller called the Baseboard management
controller (BMC)

[0.3.27] Bridge

[0.3.28] Circuitry connecting one computer bus to

another, allowing an agent on one to access the other

[0.3.29] BSP [0.3.30] Bootstrap processor

[0.3.31] Byte [0.3.32] 8-bit quantity

[0.3.33] CLI [0.3.34] Command Line Interface

[0.3.35] CMOS

[0.3.36] In terms of this specification, this describes

the PC-AT compatible region of battery-backed 128
bytes of memory, which normally resides on the
baseboard

[0.3.37] CPU [0.3.38] Central Processing Unit

[0.3.39] Deasser

ted

[0.3.40] A signal is deasserted when in the inactive
state. Active-low signal names have “_L” appended
to the end of the signal mnemonic. Active-high signal
names have no “_L” suffix. To reduce confusion when
referring to active-high and active-low signals, the
terms one/zero, high/low, and true/false are not used
when describing signal states.

[0.3.41] DTC [0.3.42] Data Transfer Controller

[0.3.43] EEPROM[0.3.44] Electrically Erasable Programmable Read-

Only Memory

[0.3.45] EMP [0.3.46] Emergency Management Port

[0.3.47] FRU [0.3.48] Field Replaceable Unit

[0.3.49] GB [0.3.50] 1024 MB.

[0.3.51] GPIO [0.3.52] General Purpose Input/Out

[0.3.53] HSC [0.3.54] Hot-Swap Controller

[0.3.55] Hz [0.3.56] Hertz (1 cycle/second)

[0.3.57] I

2

C

[0.3.58] Inter-Integrated Circuit bus

[0.3.59] IANA [0.3.60] Internet Assigned Numbers Authority

[0.3.61] IBF [0.3.62] Input buffer

[0.3.63] ICH [0.3.64] I/O Controller Hub

[0.3.65] ICMB [0.3.66] Intelligent Chassis Management Bus

ACRONYMS

XIX

[0.3.67] IERR [0.3.68] Internal Error

[0.3.69] IP [0.3.70] Internet Protocol

[0.3.71] IPMB [0.3.72] Intelligent Platform Management Bus

[0.3.73] IPMI [0.3.74] Intelligent Platform Management Interface

[0.3.75] ITP [0.3.76] In-Target Probe

[0.3.77] KB [0.3.78] 1024 bytes.

[0.3.79] KCS [0.3.80] Keyboard Controller Style

[0.3.81] KVM [0.3.82] Keyboard, Video, Mouse

[0.3.83] LAN [0.3.84] Local Area Network

[0.3.85] LCD [0.3.86] Liquid Crystal Display

[0.3.87] LCT [0.3.88] Lower Critical Threshold

[0.3.89] LED [0.3.90] Light Emitting Diode

[0.3.91] LNCT [0.3.92] Lower Non-Critical Threshold

[0.3.93] LNRT [0.3.94] Lower Non-Recoverable Threshold

[0.3.95] LPC [0.3.96] Low Pin Count

[0.3.97] LSI [0.3.98] Large Scale Integration

[0.3.99] LUN [0.3.100] Logical Unit Number

[0.3.101] MAC [0.3.102] Media Access Control

[0.3.103] MB [0.3.104] 1024 KB

[0.3.105] MD2 [0.3.106] Message Digest 2 – Hashing Algorithm

[0.3.107] MD5

[0.3.108] Message Digest 5 – Hashing Algorithm –

Higher Security

[0.3.109] Ms [0.3.110] Milliseconds

[0.3.111] Mux [0.3.112] Multiplexer

[0.3.113] NIC [0.3.114] Network Interface Card

[0.3.115] NMI [0.3.116] Non-maskable Interrupt

[0.3.117] NM [0.3.118] Node Management

[0.3.119] OBF [0.3.120] Output buffer

[0.3.121] OEM [0.3.122] Original Equipment Manufacturer

[0.3.123] Ohm [0.3.124] Unit of electrical resistance

[0.3.125] PDB [0.3.126] Power Distribution Board

[0.3.127] PEF [0.3.128] Platform Event Filtering

[0.3.129] PEP [0.3.130] Platform Event Paging

[0.3.131] PERR [0.3.132] Parity Error

[0.3.133] POH [0.3.134] Power-On Hours

[0.3.135] POST [0.3.136] Power-On Self Test

[0.3.137] PWM [0.3.138] Pulse Width Modulation

[0.3.139] RAC [0.3.140] Remote Access Card

[0.3.141] RAM [0.3.142] Random Access Memory

[0.3.143] RMCP [0.3.144] Remote Management Control Protocol

[0.3.145] ROM [0.3.146] Read Only Memory

[0.3.147] RTC

[0.3.148] Real-Time Clock. Component of the chipset

on the baseboard.

[0.3.149] RTOS [0.3.150] Real Time Operation System

[0.3.151] SCI [0.3.152] Serial Communication Interface

[0.3.153] SDC [0.3.154] SCSI Daughter Card

ACRONYMS

XX

[0.3.155] SDR [0.3.156] Sensor Data Record

[0.3.157] SEEP

ROM

[0.3.158] Serial Electrically Erasable Programmable
Read-Only Memory

[0.3.159] SEL [0.3.160] System Event Log

[0.3.161] SERR [0.3.162] System Error

[0.3.163] SMBus

[0.3.164] A two-wire interface based on the I

2

C proto­col. The SMBus is a low-speed bus that provides
positive addressing for devices, as well as bus arbi­tration

[0.3.165] SMI

[0.3.166] Server Management Interrupt. SMI is the

highest priority non-maskable interrupt

[0.3.167] SMM [0.3.168] Server Management Mode

[0.3.169] SMS [0.3.170] Server Management Software

[0.3.171] SNMP [0.3.172] Simple Network Management Protocol

[0.3.173] SOL [0.3.174] Serial Over LAN

[0.3.175] UART

[0.3.176] Universal Asynchronous Receiver/Trans-

mitter

[0.3.177] UCT [0.3.178] Upper Critical Threshold

[0.3.179] UDP [0.3.180] User Datagram Protocol

[0.3.181] UNCT [0.3.182] Upper Non-Critical Threshold

[0.3.183] UNRT [0.3.184] Upper Non-Recoverable Threshold

[0.3.185] WDT [0.3.186] Watchdog Timer

[0.3.187] Word [0.3.188] 16-bit quantity

SAFETY INFORMATION

XXI

[0.4.189] Safety Information

[0.4.190] Important Safety
Instructions

[0.4.191] Read all caution and safety statements in this docu­ment before performing any of the instructions.

[0.4.192] Warnings

[0.4.193] Heed safety instructions: Before working with the
server, whether using this manual or any other resource as a
reference, pay close attention to the safety instructions. Adhere
to the assembly instructions in this manual to ensure and main­tain compliance with existing product certifications and approv­als. Use only the described, regulated components specified in
this manual. Use of other products / components will void the
UL listing and other regulatory approvals of the product and will
most likely result in non-compliance with product regulations in
the region(s) in which the product is sold.

[0.4.194] System power on/off: The power button DOES NOT
turn off the system AC power. To remove power from system,
you must unplug the AC power cord from the wall outlet. Make
sure the AC power cord is unplugged before opening the chas­sis, adding, or removing any components.

[0.4.195] Hazardous conditions, devices and cables: Haz­ardous electrical conditions may be present on power, tele­phone, and communication cables. Turn off the server and
disconnect the power cord, telecommunications systems, net­works, and modems attached to the server before opening it.
Otherwise, personal injury or equipment damage can result.

[0.4.196] Electrostatic discharge (ESD) and ESD protection:

ESD can damage drives, boards, and other parts. We recom­mend that you perform all procedures in this chapter only at an
ESD workstation. If one is not available, provide some ESD pro­tection by wearing an antistatic wrist strap attached to chassis
ground any unpainted metal surface on the server when han­dling parts.

[0.4.197] ESD and handling boards: Always handle boards
carefully. They can be extremely sensitive to electrostatic dis­charge (ESD). Hold boards only by their edges. After removing
a board from its protective wrapper or from the server, place the
board component side up on a grounded, static free surface.
Use a conductive foam pad if available but not the board wrap­per. Do not slide board over any surface.

[0.4.198] Installing or removing jumpers: A jumper is a small
plastic encased conductor that slips over two jumper pins.
Some jumpers have a small tab on top that can be gripped with
fingertips or with a pair of fine needle nosed pliers. If the jump­ers do not have such a tab, take care when using needle nosed

SAFETY INFORMATION

XXII

pliers to remove or install a jumper; grip the narrow sides of the
jumper with the pliers, never the wide sides. Gripping the wide
sides can damage the contacts inside the jumper, causing inter­mittent problems with the function controlled by that jumper.
Take care to grip with, but not squeeze, the pliers or other tool
used to remove a jumper, or the pins on the board may bend or
break.

[0.4.199]

REVISION HISTORY

XXIII

[0.5.200] Revision History

Refer to the table below for the updates made to this manual.

[0.5.210] Copyright

[0.5.211] Copyright © 2012 Quanta Computer Inc. This publica­tion, including all photographs, illustrations and software, is pro­tected under international copyright laws, with all rights
reserved. Neither this manual, nor any of the material contained
herein, may be reproduced without the express written consent
of the manufacturer. All trademarks and logos are copyrights of
their respective owners.

[0.5.212] Version 1.0 / August, 2012

[0.5.213] Disclaimer

[0.5.214] The information in this document is subject to change
without notice. The manufacturer makes no representations or
warranties with respect to the contents hereof and specifically
disclaims any implied warranties of merchantability or fitness for
any particular purpose. Furthermore, the manufacturer reserves
the right to revise this publication and to make changes from
time to time in the content hereof without obligation of the man­ufacturer to notify any person of such revision or changes.

[0.5.215] For the latest information and updates please refer to

www.QuantaQCT.com

[0.5.216] All the illustrations in this technical guide are for refer­ence only and are subject to change without prior notice.

[0.5.201] DATE [0.5.202] CHAPTER [0.5.203] UPDATES

[0.5.204] [0.5.205] [0.5.206]

[0.5.207] [0.5.208] [0.5.209]

[1.0.1] About the Server

Chapter 1

ABOUT THE SERVER OVERVIEW

1-1

[1.1.1] Overview

[1.1.2] The S210-MBT2W Pedestal products are IA-64 based
dual-socket platforms that support the Sandy Bridge –EP (8
Core) and the Ivy Bridge –EP (10 Core) processors in combina­tion with the Patsburg Server South Bridge (SSB).

[1.1.3] S210-MBT2W Features

[1.1.4] The major components of the platform are featured as
follows:

 Chipset: Patsburg -A with upgrade capability.

 Processors: Socket -R based SNB -EP and IVB -EP inte-

grated processors.

 PCI-Express (PCIe) x16/8/4: (4) PCIe x16 G3 slots, (1)

PCIe x8 G3 slot, and (1) PCIe x 4 G2 slot.

 Memory: Up to sixteen DIMM slots are available. DDR3

800/1067/1333/1600 MHz RDIMM, UDIMM with ECC, LR­DIMM, and LV-DIMM are supported.

 HDD Interface: (4) or (8) SATA 6G ports with LSI SW

RAID5 availability, 4 or 8 SAS 6G ports with LSI SW
RAID5 availability. (2) SATA 6G ports (ODD).

[1.1.5] The following table provides detailed information on
Romley-EP product features.

[1.1.6] S210-MBT2W Feature Set

[1.1.7] FEATURE [1.1.8] DESCRIPTION

[1.1.9] Processor

[1.1.10] SNB-EP (8 Cores):

 TDP up to 135W (Servers)

 TDP 150W (Extreme Server SKU Only)

 Package: 52.5 x 45 mm FC-LGA package

(LGA2011)

[1.1.11] IVB-EP (10 Cores):

 TDP up to 135W (Servers)

 TDP 150W (Extreme Server SKU Only)

 Package: 52.5 x 45 mm FC-LGA package

(LGA2011)

[1.1.12] CPU
Memory Configura­tion

[1.1.13] 4 DDR3 Memory Channels

ABOUT THE SERVER S210-MBT2W FEATURES

1-2

[1.1.14] CPU PCI
Express Configura­tion

[1.1.15] Integrated I/O Configuration:

 PCI Express Gen3: 40 lanes

 PCIe Master controllers: 10 Full peer-to-peer

support between PCI-Express interfaces

 PCI-Express Base Specification: Revision 2 and

3 compliant

 IOAT4 Support: PCIe Gen3 caching hints I/O

Virtualization: VT-d 2 Supported

 Crystal Beach Supported

 PCIe Master Controller configuration:

 IOU 0: 4 Master Controllers

 IOU 1: 4 Master Controllers

 IOU 2: 2 Master Controllers

 Supported configurations:

 IOU 2 Port 0: 1 x4 ESI/DMI port in Gen2

mode

 Independent logic operation from x8. Can be

strapped to operate in PCIe-mode

 IOU 2 Port 1: 2 x4, or 1x8 (IOU to connect to

Patsburg)

 IOU 0 Port 2: 4 x4, or 1 x8 and 2 x4, or 2 x8,

or 1 x16

 IOU 1 Port 3: 4 x4, or 1 x8 and 2 x4, or 2x8,

or 1 x16

[1.1.6] S210-MBT2W Feature Set (Continued)

[1.1.7] FEATURE [1.1.8] DESCRIPTION

[1.1.16] CPU PCI

Express Configura­tion

 IOU to Port Mapping

 Port 0 x4 = IOU2 = xxESI_xx_ [3:0]

 Port 1 x8 = IOU2 = xxPE2_xx_ [7:0]

 Port 2 x16 = IOU0 = xxPE0_xx_ [15:0]

 Port 3 x16 = IOU1 = xxPE1_xx_ [15:0]

[1.1.17] Server
South Bridge

[1.1.18] Patsburg SSB:

 Patsburg –A: TDP 8.0W

 Patsburg –A with 8 Drive Upgrade Options: TDP

11.50W

[1.1.19] I/O Architecture: Upstream Interfaces:

 DMI/ESI x4 Gen2 interface

 PCI-E x4 Gen3 interface:

 Connect to SNB-EP / IVB-EP IOU2 Port 0:

x4 link: SNB-EP / IVB-EP Interface:
xxPE2_xx_[3:0]

 Downstream Interfaces:

 PCI Express Gen2: 8 Lanes

 PCIe Master Controllers: 8

 Supported Configurations: 8 x1, or 4 x2, or 2

x4

 Non-Supported Configuration: 1 x8

[1.1.6] S210-MBT2W Feature Set (Continued)

[1.1.7] FEATURE [1.1.8] DESCRIPTION

ABOUT THE SERVER S210-MBT2W FEATURES

1-3

[1.1.20] Server
South Bridge

 SATA Gen2 (3 Gbps) LHS AHCI Ports 2 through

5. Total: 4 ports

 Support for 3.0Gbps and 1.5Gbps transfer

rates

 SATA Gen 3 (6 Gbps) LHS AHCI Ports 0 and 1:

Total: 2 ports

 Support for 6.0Gbps, 3.0Gbps, and 1.5Gbps

transfer rates

 SATA SW RAID Configurations: RAID 0, 1, 5,

10, and 50 capable

 SAS Gen 2 (6 Gbps) RHS SCU Ports: 8

 Support for 6.0Gbps and 3.0Gbps transfer

rates

 Support for SATA 6Gbps, 3.0Gbps, and

1.5Gbps rates

 Fuse available to disable SATA feature sup-

port

[1.1.6] S210-MBT2W Feature Set (Continued)

[1.1.7] FEATURE [1.1.8] DESCRIPTION

[1.1.21] Server

South Bridge

 SAS SW RAID Configurations: RAID 0, 1, 5, 10,

and 50 capable

 SAS “RAID ON LOAD” HW RAID (CB DMA

engine enabled): Capable NVSRAM Interface:
33MHz 20-pin interface for ROL NVSRAM
device

 USB 2.0 Ports: 14

 USB 3.0 Ports: 0 (de-featured on Romley)

 SMBUS Ports:

 1 Host SMBus: Resume power well

 1 ME/ SMLink 0: (Connect to BMC) :

Resume power well

 1 ME/ SMLink 1: (Power Supply PMBus

Interface): Resume power well

 1 Storage SES SMBus (Primary SMBUS):

Main power well

 1 Storage SES SMBus (Secondary SMBUS):

Main power well

[1.1.6] S210-MBT2W Feature Set (Continued)

[1.1.7] FEATURE [1.1.8] DESCRIPTION

ABOUT THE SERVER S210-MBT2W FEATURES

1-4

[1.1.28]

[1.1.22] Network

Controllers

[1.1.23] INTEL I350 Powerville Network Control­ler:

 Dual or Quad 10/100/1000 Ethernet MAC with

quad PHY ports integrated.

 PCIe x4 Gen2 interface upstream (4GBps

aggregate)

 MSI-X support

 High speed sideband management port: Node

Controller-Sideband Interface

 (NC-SI) also known as multi-drop RMII link

 Package: PBGA 17mm x 17mm 1.0 mm ball

pitch

 Controller TDP: 4.2W (2.7W for Dual Powerville

Option)

[1.1.24] BIOS

[1.1.25] AMI Aptio v 4.x “One-Core”, using 8 MB

SPI Flash module connected to Patsburg SPI inter­face

[1.1.6] S210-MBT2W Feature Set (Continued)

[1.1.7] FEATURE [1.1.8] DESCRIPTION

[1.1.26] Server

Management

[1.1.27] ASPEED 2300 Integrated BMC Basic
Logic Block Configuration:

 Provides one serial port that could be switched

to DB9 on the rear panel

 Provides VGA, standard VGA DB15 on the rear

panel

 Provides a dedicated 10/100M NIC for manage-

ment, on the rear panel

 Connects to a x1 PCIe Gen 2 lane that origi-

nates from Patsburg

 Connects to the LPC bus (for system manage-

ment commands)

 Connects to the USB2.0x1 and USB1.1x1 from

Patsburg

[1.1.6] S210-MBT2W Feature Set (Continued)

[1.1.7] FEATURE [1.1.8] DESCRIPTION

ABOUT THE SERVER PACKAGE CONTENTS

1-5

[1.2.29] Package Contents

[1.2.30] The following items are included to the package con­tent:

 Serverboard

 CD (technical guide included)

[1.3.31] Functional Architecture

ABOUT THE SERVER PROCESSOR

1-7

[1.3.32] Processor

[1.3.33] The S210-MBT2W baseboard supports Sandy Bridge
–EP Processor (SNB-EP) and Ivy Bridge –EP Processor (IVB­EP). The board include dual Socket –Rs and EVRD 12.0s that
support up to 150W TDP Processors for the S210-MBT2W.
This is accomplished by using a 6-phase VR12 design to sup­port 150W on S210-MBT2W Server SKU.

[1.3.34] Overview of the Proces­sors

[1.3.35] The SNB –EP and IVB –EP are composed of up to 8
cores and 10 cores respectively. The microprocessors include
an integrated DDR3 memory controller (IMC) with four memory
channels which can support up to three ECC Registered
DIMMs or three Un-buffered DIMMs (ECC or non-ECC) per
memory channel, an integrated I/O controller with 40 PCI
Express Gen3 lanes controlled by ten PCI Express Master Con­trollers. The target TDPs are: 50W, 60W, 70, 80W, 95W and
135W for servers.

[1.3.37] The S210-MBT2W baseboards must support the IVB –
EP processor as a drop in. Board designers must be aware that
the IVB –EP controller has a lower Processor VTT and VPLL
rail voltage set point than SNB –EP. To dynamically adjust the
Processor VTT and VPLL output voltages, a pin has been
defined on Socket –R to identify IVB –EP processors. The sig­nal: IVB_PRESENT_N is pulled up to Processor VTT when a
SNB –EP controller is present and it is grounded when an IVB –
EP controller is placed on the board. Socket –R sideband sig­nals that operate from the VTT power well and are connected to
other parts of the baseboard must be translated taking into
account the lower processor VTT voltage level set point (i.e. V
(typical) = 1.0V, V(max) = 1.03V, V(low) = 0.95V). It must also
be noted that the IVB_PRESENT_N signal cannot be pulled up
to 3.3V but must be kept at a maximum voltage level of 1.05V
due to signal integrity requirements of signals adjacent to
IVB_PRESENT_N. This is accomplished by using a voltage
divider from the 3.3V voltage rail.

[1.3.38] Processor Mismatch

[1.3.39] The S210-MBT2W baseboard must prevent the base­board from booting if SNB –EP and IVB-EP processors are
mixed into the system. The BMC will log an error in the SEL.

Note:

[1.3.36] 150W SKU is for Extreme Server SKUs.

ABOUT THE SERVER TURBO MODE

1-8

[1.3.40] Turbo Mode

[1.3.41] This product must be designed to exploit SNB/IVB
Turbo Mode. The development team will need to meet the ther­mal and VR solution requirements to get the performance
upside. Some background information:

 IMON was modified by Cisco to improve platform perfor-

mance (by default Cisco set it always on). Google fol­lowed similar implementation.

 The Turbo Working Group is changing the nomenclature

to SNB Turbo and refraining from using Dynamic Turbo.

 An investigation has been done, to find out if Turbo gener-

ates PROCHOT# more often.

[1.3.42] In the Romley generation, the SNB -EP and IVB –EP
processors will support Turbo Mode in which the processor can
exceed the TDP power for short period of time. It is a require­ment to support this feature on this product.

[1.3.43] Processor C-State
Power Consumption

[1.3.44] Preliminary numbers C-state power guidance (iMOW
ww26 2010) is based on pre-silicon model and is subject to
change based on post-silicon validation results. The processor
case temperature is assumed at 50°C for all C-states. See the
following table for details on 8/6 core SKUs and 4 core SKU:

[1.3.70] The C-state power guidance (iMOW ww26 2010) is
based on pre-silicon model and is subject to change based on
post-silicon validation results. The processor case temperature
is assumed at 50°C for all C-states. The post-silicon C-state
power specifications will be based on ES2 characterization
work that beings in Q4'10. See the following table for details:

[1.3.45] Processor C-State Details

[1.3.46]
S

TATE

[1.3.47]

T

HREADS

[1.3.48] L

1/MLC

[1.3.49]

PLL

[1.3.50] VCC[1.3.51] CON

TEXT

[1.3.52]

C1(E)

[1.3.53]

Both at
least in
C1 (E)

[1.3.54] V
alid

[1.3.55]

N/A

[1.3.56] R
equest
LFM

[1.3.57] Valid

[1.3.58]

C3

[1.3.59]

Both at
least in
C3

[1.3.60] Fl
ushed &
disabled

[1.3.61]

N/A

[1.3.62] R
equest
retention

[1.3.63] Valid

[1.3.64]

C6/7

[1.3.65]

Both at
least in
C6/7

[1.3.66] Fl
ushed &
disabled

[1.3.67]

N/A

[1.3.68] P
ower
gated

[1.3.69] Save
d (Way0)

[1.3.71] SNB Post Silicon C-State Power Consumption

[1.3.72] SNB -

EP/EX 8/6

C

ORE SKUS

[1.3.73] C1E

(W)

[1.3.74] C3 (W) [1.3.75] C6 (W)

[1.3.76] 150W

WS (8-core)

[1.3.77] 58 [1.3.78] 27 [1.3.79] 16

ABOUT THE SERVER PROCESSOR C-STATE POWER CONSUMPTION

1-9

[1.3.80] 130W
1U (8-core)

[1.3.81] 47 [1.3.82] 22 [1.3.83] 15

[1.3.84] 130W

1U (6-core)

[1.3.85] 53 [1.3.86] 25 [1.3.87] 16

[1.3.88] 95W

1U (8 core)

[1.3.89] 47 [1.3.90] 22 [1.3.91] 15

[1.3.92] 95W

1U (6 core)

[1.3.93] 48 [1.3.94] 22 [1.3.95] 15

[1.3.96] 70W

1U (8 core)

[1.3.97] 39 [1.3.98] 17 [1.3.99] 12

[1.3.100] 60W

1U (6 core)

[1.3.101] 38 [1.3.102] 16 [1.3.103] 13

[1.3.104] SNB -EP/EX 4 core SKU

[1.3.105] SNB -

EP/EX 4 C

ORE

SKU

S

[1.3.106] C1E

(W)

[1.3.107] C3

(W)

[1.3.108] C6

(W)

[1.3.109] 130W

2U (4-core)

[1.3.110] 53 [1.3.111] 28 [1.3.112] 16

[1.3.113] 95W

1U (4-core)

[1.3.114] 43 [1.3.115] 18 [1.3.116] 14

[1.3.117] 80W

1U (4-core)

[1.3.118] 42 [1.3.119] 21 [1.3.120] 16

[1.3.71] SNB Post Silicon C-State Power Consumption

[1.3.72] SNB -

EP/EX 8/6

C

ORE SKUS

[1.3.73] C1E

(W)

[1.3.74] C3 (W) [1.3.75] C6 (W)

[1.3.121] 50W

1U (4 core)

[1.3.122] 34 [1.3.123] 17 [1.3.124] 13

[1.3.104] SNB -EP/EX 4 core SKU

[1.3.105] SNB -

EP/EX 4 C

ORE

SKU

S

[1.3.106] C1E

(W)

[1.3.107] C3

(W)

[1.3.108] C6

(W)

ABOUT THE SERVER MEMORY

1-10

1.3.2 Memory

General Guidelines

This section discusses the requested memory configurations
and capacities that need to be supported for SNB –EP and IVB
–EP. The memory EVRD 12.0 and memory VTT VRD should be
sized to support ~90% peak bandwidth for the integrated mem­ory controller 256 clock thermal window, this is approximately

11.5GB/sec/channel at DDR3 1600. For TDP purposes, an
active DIMM can be assumed to consume 18W.

Note:

IVB is scoping DDR3U (Ultra Low Power = 1.25V). DDR3U is
evolving and is being tracked by PMO and reported in the
Romley PXT, the direction for Intel is now on DDR3U enable­ment and rather push for earlier DDR4 adoption (DDR4 will
not be supported on Romley products).

ABOUT THE SERVER GENERAL GUIDELINES

1-11

DDR3 for SNB -EP

The following table includes information on supported DDR3 for SNB -EP platform.

DDR3 Support for SNB -EP

RDIMM / LR-DIMM JAKETOWN SOCKET R

S

LOTS /

C

HANNEL

DPC DDR TYPE

RANKS /

D

IMM

STANDARD VOLTAGE -1.5V LOW VOLTAGE -1.35V

1866 1600 1333 1066 800 1866 1600 1333 1066 800

11

RDIMM SR POR POR POR POR POR

RDIMM DR POR POR POR POR POR

RDIMM QR POR POR

LR-DIMM QR POR POR POR POR

UDIMM SR POR POR POR POR POR

UDIMM DR POR POR POR POR POR

21

RDIMM SR POR POR POR POR

RDIMM DR POR POR POR POR

RDIMM QR POR POR

LR-DIMM QR POR POR POR

UDIMM SR POR POR POR POR

UDIMM DR POR POR POR POR

ABOUT THE SERVER GENERAL GUIDELINES

1-12

22

RDIMM SR POR POR POR POR POR

RDIMM DR POR POR POR POR POR

RDIMM QR POR POR

LR-DIMM QR POR POR POR

UDIMM SR POR POR POR

UDIMM DR POR POR POR

31

RDIMM SR POR POR POR POR POR

RDIMM DR POR POR POR POR POR

RDIMM QR

POR

POR

LR-DIMM QR POR POR POR

UDIMM SR POR POR POR

UDIMM DR POR POR POR

DDR3 Support for SNB -EP (Continued)

RDIMM / LR-DIMM JAKETOWN SOCKET R

S

LOTS /

C

HANNEL

DPC DDR TYPE

RANKS /

D

IMM

STANDARD VOLTAGE -1.5V LOW VOLTAGE -1.35V

1866 1600 1333 1066 800 1866 1600 1333 1066 800

ABOUT THE SERVER GENERAL GUIDELINES

1-13

32

RDIMM SR POR POR POR POR POR

RDIMM DR POR POR POR POR POR

RDIMM QR POR POR

LR-DIMM QR POR POR POR

UDIMM SR POR POR POR

UDIMM DR POR POR POR

33

RDIMM POR POR

RDIMM POR POR

RDIMM

LR-DIMM POR POR

UDIMM

UDIMM

DDR3 Support for SNB -EP (Continued)

RDIMM / LR-DIMM JAKETOWN SOCKET R

S

LOTS /

C

HANNEL

DPC DDR TYPE

RANKS /

D

IMM

STANDARD VOLTAGE -1.5V LOW VOLTAGE -1.35V

1866 1600 1333 1066 800 1866 1600 1333 1066 800

ABOUT THE SERVER GENERAL GUIDELINES

1-14

DDR3 for IVB -EP

The following table includes information on supported DDR3 for IVB -EP platform.

DDR3 Support for IVB -EP

RDIMM / LR-DIMM JAKETOWN SOCKET R

S

LOTS /

C

HANNEL

DPC DDR TYPE

RANKS /

D

IMM

STANDARD VOLTAGE -1.5V LOW VOLTAGE -1.35V

1866 1600 1333 1066 800 1866 1600 1333 1066

21

RDIMM SR STR X* POR POR POR POR

RDIMM DR STR X* POR POR POR POR

RDIMM QR POR POR POR

LR-DIMM QR STR X* POR POR POR POR

UDIMM SR POR POR POR POR

UDIMM DR POR POR POR POR

22

RDIMM SR STR 2* POR POR POR

RDIMM DR STR 2* POR POR POR

RDIMM QR STR 10* POR POR

LR-DIMM QR POR POR POR POR

UDIMM SR STR 9* POR POR POR

UDIMM DR STR 9* POR POR POR

Note:

* indicates recent changes.

ABOUT THE SERVER DIMM NOMENCLATURE

1-15

DIMM Nomenclature

DIMMs are organized into physical slots on DDR3 memory
channels that belong to processor sockets. The memory chan­nels from Socket 0 are identified as Channel A, B, C, D. The
memory channels from Socket 1 are identified as Channel E, F,
G and H. The DIMM identifiers on the silk screen on the board
provide information about the channel, and therefore the pro­cessor, to which they belong. For example, DIMM_A1 is the first
slot on Channel A on Processor 0; DIMM_E1 is the first DIMM
socket on Channel E on Processor 1. Space must be provided
to attach labels to the Baseboard (and any other board in the
system).

See the following illustration for details on processor and DIMM
labeling and placement.

CPU and DIMM Labeling and Placement

DIMM_G1 (0XA0) Channel 2 1

st

DIMM

DIMM_G2 (0XA2) Channel 2 2

nd

DIMM

DIMM_G3 (0XA4) Channel 2 3

rd

DIMM

DIMM_H1 (0XA6) Channel 3 1

st

DIMM

DIMM_H2 (0XA8) Channel 3 2

nd

DIMM

DIMM_H3 (0XAA) Channel 3 3

rd

DIMM

DIMM_A1 (0XA0) Channel 0 1

st

DIMM

DIMM_A2 (0XA2) Channel 0 2

nd

DIMM

DIMM_A3 (0XA4) Channel 0 3

rd

DIMM

DIMM_B1 (0XA6) Channel 1 1

st

DIMM

DIMM_B2 (0XA8) Channel 1 2

nd

DIMM

DIMM_B3 (0XAA) Channel 1 3

rd

DIMM

DIMM_F3 (0XAA) Channel 1 3

rd

DIMM

DIMM_F2 (0XA8) Channel 1 2

nd

DIMM

DIMM_F1 (0XA6) Channel 1 1

st

DIMM

DIMM_D3 (0XAA) Channel 3 3

rd

DIMM

DIMM_D2 (0XA8) Channel 3 2

nd

DIMM

DIMM_D1 (0XA6) Channel 3 1

st

DIMM

QPI PORT 0

QPI PORT 0

QPI PORT 1

QPI PORT 1

SNB-EP

SOCKET 1

SNB-EP

SOCKET 0

ABOUT THE SERVER DIMM POPULATION RULES

1-16

DIMM Population Rules

The memory slots of DDR3 channels from the "SNB/IVB –EP
processor" should be populated on a farthest first fashion. This
means that A2 cannot be populated/used if A1 is empty. See
the following illustrations for instructions on RDIMM, UDIMM,
and LR-DIMM population.

RDIMM Population Rules

SLOT

S

PER

C

HAN

NEL

DIMM

S PER

C

HAN

NEL

SLOT2SLOT1

S

LOT

0

POR

?

V

AL POR?

11

xx xx SR Yes Yes

xx xx DR Yes Yes

xx xx QR Yes NOT Val POR

21

xx Empty SR Yes Yes

xx Empty DR Yes Yes

xx Empty QR Yes NOT Val POR

22

xx SR SR Yes Yes

xx SR DR Yes Yes

xx SR QR Yes NOT Val POR

xx DR DR Yes Yes

xx DR QR Yes NOT Val POR

xx QR QR Yes NOT Val POR

31

Empty Empty SR Yes Yes

Empty empty DR Yes Yes

Empty empty QR Yes NOT Val POR

32

Empty SR SR Yes Yes

Empty SR DR Yes Yes

Empty SR QR Yes NOT Val POR

Empty DR DR Yes Yes

Empty DR QR Yes NOT Val POR

Empty QR QR Yes NOT Val POR

33

SR SR SR Yes Yes

SR SR DR Yes Yes

SR DR DR Yes Yes

DR DR DR Yes Yes

RDIMM Population Rules (Continued)

SLOT

S

PER

C

HAN

NEL

DIMM

S PER

C

HAN

NEL

SLOT2SLOT1

S

LOT

0

POR

?

V

AL POR?

ABOUT THE SERVER DIMM POPULATION RULES

1-17

UDIMM Population Rules

SLOT

S

PER

C

HAN

NEL

DIMM

S PER

C

HAN

NEL

SLOT2SLOT1

S

LOT

0

POR

?

V

AL POR?

11

xx xx SR Yes Yes

xx xx SR Yes Yes

21

xx Empty SR Yes Yes

xx Empty DR Yes Yes

22

xx SR SR Yes Yes

xx SR DR Yes Yes

xx DR DR Yes Yes

31

Empty Empty SR Yes Yes

Empty Empty DR Yes Yes

32

Empty SR SR Yes Yes

Empty SR DR Yes Yes

Empty DR DR Yes Yes

Note:

LR-DIMM can only be populated with other LR-DIMMs, not
UDIMM or RDIMM.

Note:

There is no limitation on numbers of LR-DIMMs per channel.

Note:

Only LR-DIMM R/C-B and R/C-C are validation POR.

Note:

"LR-Dir" is direct mapped mode; "LR-2xRM" is rank multipli­cation mode.

Note:

Only quad rank (4R) LR-DIMM is POR. Octal rank (8R) is not
POR.

LR-DIMM Population Rules

SLOT

S

PER

C

HAN

NEL

DIMM

S PER

C

HAN

NEL

SLOT2SLOT1SLOT0

POR

?

V

AL

P

OR?

1 1 xx xx LR-Dir Yes Yes

2 1 xx empty LR-Dir Yes Yes

2 2 xx LR-Dir LR-Dir Yes Yes

3 1 Empty Empty LR-Dir Yes Yes

3 2 Empty LR-Dir LR-Dir Yes Yes

3 3 LR-2xRM LR-2xRM LR-2xRM Yes Yes

ABOUT THE SERVER MEMORY ERROR LED AND BEEP CODES

1-18

Memory Error LED and Beep
Codes

BIOS identifies problematic DIMMs during the boot process.
BIOS will send a message to the BMC to indicate which DIMM
LED needs to be turned on.

If no functional DIMM can be found, then the Buzzer will indi­cate this condition by a beep code that is defined in the FW
EAS.

Memory Power Consumption

The following tables list the power consumption for the DIMM
Vddq VR. The VR current (A/VR in table) assumes 2 channels
per VR plus 3A of CPU Idd current. In addition, the step loading
uses worst case and 3 sigma Idd. The author of the table is Ed

Payton WW31 ’10.

Note:

Vtt current is not presented.

RDIMM/RRDIMM Power Consumption 1876 2GB

RDIMM/LRDIMM

S

OCKET R

1867 2G

B

SLOT

S

/

C

HAN

NEL

DPC

DD

R

T

YP

E

A/

DIM

M

PK/
DIM

M

A/

C

H

A/

V

R

WC
S

TE

P

A/

V

R

3-

S

IGM

A

S

TEP

A/

VR

11

RDI
MM

SR 4.5 8.5 4.5 12.7 N/A N/A

RDI
MM

DR 6.6 9.8 6.6 16.9 N/A N/A

RDI
MM

QR N/A N/A N/A N/A N/A N/A

LR­DIMMQR 11.0 15,1 11.0 23.8 26.7 24.3

22

RDI
MM

SR N/A N/A N/A N/A N/A N/A

RDI
MM

DR N/A N/A N/A N/A N/A N/A

RDI
MM

QR N/A N/A N/A N/A N/A N/A

LR­DIMMQR N/A N/A N/A N/A N/A N/A

ABOUT THE SERVER MEMORY POWER CONSUMPTION

1-19

33

RDI
MM

SR N/A N/A N/A N/A N/A N/A

RDI
MM

DR N/A N/A N/A N/A N/A N/A

RDI
MM

QR N/A N/A N/A N/A N/A N/A

LR­RDIMMQR N/A N/A N/A N/A N/A N/A

RDIMM/RRDIMM Power Consumption 1876 2GB (Continued)

RDIMM/LRDIMM

S

OCKET R

1867 2G

B

SLOT

S

/

C

HAN

NEL

DPC

DD

R

T

YP

E

A/

DIM

M

PK/
DIM

M

A/

C

H

A/

V

R

WC
S

TE

P

A/

V

R

3-

S

IGM

A

S

TEP

A/

VR

RDIMM/RRDIMM Power Consumption 1600 4GB

RDIMM/LRDIMM

S

OCKET R

1600 4G

B

SLOT

S

/

C

HAN

NEL

DPC

DD

R

T

YP

E

A/

DIM

M

PK/
DIM

M

A/

C

H

A/

V

R

WC

S

TE

P

A/

V

R

3-

S

IGM

A

S

TEP

A/

VR

11

RDI
MM

SR 4.8 6.9 4.8 13.3 13.6 12.2

RDI
MM

DR 5.8 8.1 5.8 15.3 14.8 13.3

RDI
MM

QR N/A N/A N/A N/A N/A N/A

LR­DIMMQR 10.2 13.2

10.
2

24.6 21.9 20.3

22

RDI
MM

SR N/A N/A N/A N/A N/A N/A

RDI
MM

DR 5.1 6.6

10.
2

25.9 21.1 19.4

RDI
MM

QR N/A N/A N/A N/A N/A N/A

LR­DIMMQR 8.3 10.4

16.
6

38.6 30.1 28.2

ABOUT THE SERVER MEMORY POWER CONSUMPTION

1-20

33

RDI
MM

SR N/A N/A N/A N/A N/A N/A

RDI
MM

DR N/A N/A N/A N/A N/A N/A

RDI
MM

QR N/A N/A N/A N/A N/A N/A

LR­RDIMMQR N/A N/A N/A N/A N/A N/A

RDIMM/RRDIMM Power Consumption 1600 4GB (Continued)

RDIMM/LRDIMM

S

OCKET R

1600 4G

B

SLOT

S

/

C

HAN

NEL

DPC

DD

R

T

YP

E

A/

DIM

M

PK/
DIM

M

A/

C

H

A/

V

R

WC
S

TE

P

A/

V

R

3-

S

IGM

A

S

TEP

A/

VR

RDIMM/RRDIMM Power Consumption 1333 4Gb

RDIMM/LRDIMM

S

OCKET R

1333 4G

B

SLOT

S

/

C

HAN

NEL

DPC

DD

R

T

YP

E

A/

DIM

M

PK/
DIM

M

A/

C

H

A/

V

R

WC

S

TE

P

A/

V

R

3-

S

IGM

A

S

TEP

A/

VR

11

RDI
MM

SR N/A N/A N/A N/A N/A N/A

RDI
MM

DR N/A N/A N/A N/A N/A N/A

RDI
MM

QR 7.4 9.2 7.4 19 14.4 13.2

LR­DIMMQR 9.3 11.3 9.3 22.8 19.4 18.2

22

RDI
MM

SR N/A N/A N/A N/A N/A N/A

RDI
MM

DR N/A N/A N/A N/A N/A N/A

RDI
MM

QR N/A N/A N/A N/A N/A N/A

LR­DIMMQR 7.8 9.2

15.
6

36.6 26.8 25.4

ABOUT THE SERVER MEMORY POWER CONSUMPTION

1-21

33

RDI
MM

SR N/A N/A N/A N/A N/A N/A

RDI
MM

DR N/A N/A N/A N/A N/A N/A

RDI
MM

QR N/A N/A N/A N/A N/A N/A

LR­RDIMMQR N/A N/A N/A N/A N/A N/A

RDIMM/RRDIMM Power Consumption 1333 4Gb (Continued)

RDIMM/LRDIMM

S

OCKET R

1333 4G

B

SLOT

S

/

C

HAN

NEL

DPC

DD

R

T

YP

E

A/

DIM

M

PK/
DIM

M

A/

C

H

A/

V

R

WC
S

TE

P

A/

V

R

3-

S

IGM

A

S

TEP

A/

VR

RDIMM/RRDIMM Power Consumption 1067 4Gb

RDIMM/LRDIMM

S

OCKET R

1067 4G

B

SLOT

S

/

C

HAN

NEL

DPC

DD

R

T

YP

E

A/

DIM

M

PK/
DIM

M

A/

C

H

A/

V

R

WC

S

TE

P

A/

V

R

3-

S

IGM

A

S

TEP

A/

VR

11

RDI
MM

SR N/A N/A N/A N/A N/A N/A

RDI
MM

DR N/A N/A N/A N/A N/A N/A

RDI
MM

QR N/A N/A N/A N/A N/A N/A

LR­DIMMQR 8.6 10.4 8.6 21.4 17.0 16.1

22

RDI
MM

SR N/A N/A N/A N/A N/A N/A

RDI
MM

DR N/A N/A N/A N/A N/A N/A

RDI
MM

QR 6.0 7.1

12.
0

29.5 18.7 17.8

LR­DIMMQR 7.0 8.1

14.
1

33.6 21.8 22.7

ABOUT THE SERVER MEMORY POWER CONSUMPTION

1-22

33

RDI
MM

SR 2.5 3.0 7.5 21.7 10.3 9.7

RDI
MM

DR 3.1 3.9 9.3 25.4 11.8 11.2

RDI
MM

QR N/A N/A N/A N/A N/A N/A

LR­RDIMMQR 5.7 7.0

17.
1

40.9 18.5 17.9

RDIMM/RRDIMM Power Consumption 1067 4Gb (Continued)

RDIMM/LRDIMM

S

OCKET R

1067 4G

B

SLOT

S

/

C

HAN

NEL

DPC

DD

R

T

YP

E

A/

DIM

M

PK/
DIM

M

A/

C

H

A/

V

R

WC
S

TE

P

A/

V

R

3-

S

IGM

A

S

TEP

A/

VR

RDIMM/RRDIMM Power Consumption 800 4Gb

RDIMM/LRDIMM

S

OCKET R

800 4G

B

SLOT

S

/

C

HAN

NEL

DPC

DD

R

T

YP

E

A/

DIM

M

PK/
DIM

M

A/

C

H

A/

V

R

WC

S

TE

P

A/

V

R

3-

S

IGM

A

S

TEP

A/

VR

11

RDI
MM

SR N/A N/A N/A N/A N/A N/A

RDI
MM

DR N/A N/A N/A N/A N/A N/A

RDI
MM

QR N/A N/A N/A N/A N/A N/A

LR­DIMMQR 8.6 10.4 8.6 21.4 17.0 16.1

22

RDI
MM

SR N/A N/A N/A N/A N/A N/A

RDI
MM

DR N/A N/A N/A N/A N/A N/A

RDI
MM

QR 5.5 6.2 11.0 27.5 14.9 14.4

LR­DIMMQR N/A N/A N/A N/A N/A N/A

ABOUT THE SERVER SUSPEND TO RAM (S3) SUPPORT

1-23

Suspend to RAM (S3) Support

The S210-MBT2W Extreme Server SKU must support Suspend
to RAM (ACPI S3) in order to qualify for the Windows Logo Cer­tification. The recommendation from Architecture is to support
the Shady Cove (Thurley Extreme Server SKU) S3 switching
circuits. Reviewing the P-FET circuit below:

When DC is off, Vgs > 0, the P-FET is off, and

P12V_P5V_AUX comes from P5V_STBY.

When DC is on, Vgs < -4.5V, the P-FET is on, and

P12V_P5V_AUX comes from P12V3A.

When in S3, the CPLD will enable the memory VDDQ VRs to
support the DDR3 DRAM power. When in S4 or S5, the CPLD
will disable the memory VDDQ VRs thereby shutting down
DDR3 DRAM power.

See the following schema for details on S3 switch circuit.

33

RDI
MM

SR 2.2 2.5 6.7 20.2 8.9 8.5

RDI
MM

DR 3.0 3.4 9.0 24.7 9.8 9.5

RDI
MM

QR N/A N/A N/A N/A N/A N/A

LR­RDIMMQR 5.1 6.2

15.
2

37.2 15.6 15.3

RDIMM/RRDIMM Power Consumption 800 4Gb

RDIMM/LRDIMM

S

OCKET R

800 4G

B

SLOT

S

/

C

HAN

NEL

DPC

DD

R

T

YP

E

A/

DIM

M

PK/
DIM

M

A/

C

H

A/

V

R

WC
S

TE

P

A/

V

R

3-

S

IGM

A

S

TEP

A/

VR

ABOUT THE SERVER VREF CALIBRATION CIRCUIT

1-24

S210-MBT2W S3 Switch Circuit

S3 will be required to supported all SKUs. So, the build option
(two zero resistors unstuffed) are removed from board design.

All external USB ports must be capable of waking up the sys­tem from the S3 state.

VREF Calibration Circuit

The Romley Platform requires the use of “Digitally Controlled
Potentiometers” to allow BIOS to program the memory VREF
voltage level for optimized memory interface timings and guard­band.

The S210-MBT2W Server products, require the use of four of
these “Digitally Controlled Potentiometer” circuits, one circuit
per memory quadrant.

The recommended circuit is illustrated below for reference:

DDR3 VREF Circuit Implementation

ABOUT THE SERVER PCI-EXPRESS

1-25

[1.3.3] PCI-Express

[1.3.4] Processor PCIe

[1.3.5] PCIe Gen1, Gen2 and Gen 3 are dual-simplex point-to
point serial differential low-voltage interconnects. The signaling
bit rate is 2.5 Gbit/s one direction per lane for Gen1 (8b/10b
encoding), 5.0 Gbit/s one direction per lane for Gen2 (8b/10b
encoding) and 8.0 Gbit/s one direction per lane for Gen3 (128b/
130b encoding). Each port consists of a transmitter and
receiver pair. A link between the ports of two devices is a collec­tion of lanes (x1, x2, x4, x8, x16, etc.). All lanes within a port
must transmit data using the same frequency. 8.0 Gbit/s trans­lates to 1.0 GB/s (one way), which corresponds to 2GB/s, 4GB/
s, 8GB/s and 16GB/s for x2, x4, x8, and x16 lanes respectively.
Since a given lane is simultaneously transmitting and receiving
data though separate Tx and Rx pairs, the effective, theoretical
data transfer rate is doubled (ie. 4GB/s, 8GB/s, 16GB/s and
32GB/s).

[1.3.6] Processor PCIe Port Connec­tivity

[1.3.7] The following table includes information on processor
PCIe port connectivity:

[1.3.9] PCIe Power Management

[1.3.10] L0 and L3 power management states are supported on
all PCIe slots and embedded end points.

[1.3.11] GPGPU Support

[1.3.12] S210-MBT2W Server Platforms must support up to 2 x
full length, full height, double-wide, 300W GPGPUs (General

[1.3.8] CPU PCIe Connectivity

CPU# DEVICE

PHYSICAL

C

ONN

IOU# PORT

ELECTRIC

AL

WIDTH

CPU0 Slot 2 x16 1 3A-3D x16

CPU1 Slot 3 x16 1 3A-3D x16

CPU0 LAN N/A 2 1A x4

CPU0 PGB N/A 2 1B x4

CPU0 PGB N/A DMI2 0 x4 Gen2

CPU1 Slot 4 x8 2 1A-1B x8

CPU0 Slot 5 x16 0 2A-2D x16

CPU1 Slot 6 x16 0 2A-2B x16

ABOUT THE SERVER GPGPU SUPPORT

1-26

Purpose Graphics Processing Units) and/or high end GPUs
(Graphics Processing Units; a.k.a. Graphics Cards). A sample
list of these cards is below. For the official listing of required
cards, the OIV Master AP List should be used by the Develop­ment Teams. For reference see the following web page:

[1.3.13] http://epgeroom.intel.com/eRoom/SPD-Process-Tasks/
AdaptPeriphList

 Intel GPGPU/Graphic Cards

 Intel Knights Ferry – 300W (SDV support only)

 Intel Knighs Corner – 225W & 300W SKUs

 Nvidia GPGPU/Graphics Cards

 GFX480 – 250W

 GFX470 – 215W

 GTX295 – 289W

 GTX285 – 204W

 GTX280 – 236W

 GTX275 – 219W

 GTX260 – 182W

 Tesla C2070 – 247W*

 Tesla C2050 – 247W

 Tesla C1060 – 187W

 Tesla M2050/M2070 (fermi based GPGPU cards - pas-

sive solution) – 247W (may be removed from Master
AP List)

Note:

[1.3.14] Power envelope of future GPGPU cards per

NVidia are ~300W.

 ATI GPGPU/Graphics Cards

 ATI Firepro V8750 - 154W

 ATI 5970 - 294W

 ATI 5870 - 188W

 ATI 5870 E6 - 228W

 ATI 5850 - 151W

 ATI 5830 - 175W

ABOUT THE SERVER SLOT POWER FOR HIGH POWER PCIE CARDS

1-27

[1.3.15] Slot Power for High
Power PCIe Cards

[1.3.16] Standard PCIe Slots can provide up to 25W of power.
In order to support the additional power required by GPGPU
and high end graphic cards, 75W needs to come from each
designated high powered PCIe slot (regardless of 150W/225W/
300W Cards) in addition to supplemental power directly from
the Power Supply. For this reason, an additional 12V 2x2
power "plus" connector (12A per pin) will be required on the
baseboard (sourced from the PSU/PDB) to provide the needed
power to designated high powered PCIe slots. Below is a list of
possible power configurations supporting different high power
PCIe cards.

 X16 150W card

 75W from PCIe slot + 75W from PSU direct cable

attach: 75W (2x3 connector)

 X16 225W card

 75W from PCIe slot + 150W from PSU direct cable

attach: 75W (2x3 conn) + 75W (2x3 conn)

[1.3.17] OR

 75W from PCIe slot + 150W from PSU direct cable

attach: 75W (2x3 conn) + 75W (2x4 conn)

[1.3.18] OR

 75W from PCIe slot + 150W from PSU direct cable

attach: 150W (2x4 conn)

 X16 300W card

 75W from PCIe slot + 225W from PSU direct cable

attach: 75W (2x3 conn) + 150W (2x4 conn)

[1.3.19] OR

 75W from PCIe slot + 225W from PSU direct cable

attach: 75W (2x3 conn) + 75W (2x3 conn) + 75W (2x3
conn) - Not preferred

[1.3.20] Nvidia SLI Support

[1.3.21] Due to licensing issues, S210-MBT2W Extreme Server
SKU is not allowed to support NVidia SLI configurations.
Although this has no affect on the hardware design, it would
have required additional BIOS support.

[1.3.22] ATI CROSSFIREX/PRO Sup­port

[1.3.23] S210-MBT2W Extreme Server SKU must support up to
4-way multi-GPU configs connected through CrossFireX/Pro
flex cables. Maximum performance would have both GPGPUs
from a single processor. However, S210-MBT2W supports the
double-wide GPGUs from x16 slots on different processors. No
additional BIOS support is required to support CrossFireX/Pro
configurations.

ABOUT THE SERVER PATSBURG PCIE

1-28

[1.3.24] SMBUS Address MUX for
GPGPU Sensor Monitoring Support

[1.3.25] Some high end NVIDIA GPGPU cards have on-board
sensors that allow monitoring of power consumption and ther­mal data via the PCIe sideband SMBUS interface. S210­MBT2W must support GPGPU sensor monitoring from desig­nated GPGPU PCIe slots. Unfortunately since the sensor
devices on all NVIDIA GPGPU cards have the same SMBUS
address, this will create address conflicts when trying to acquire
sensor data from different cards. An SMBus MUX (PCA9545 or
PCA9546) will be required to support Address isolation
between the different cards. Connect the SMBus MUX
between the designated GPGPU slots and BMC SMBus 2.

[1.3.26] SMBus Address Isolation for GPGPU Cards

[1.3.27] The recommended components for the SMBus MUX

are as follows:

 PCA9545A: IPN G10822-001

 PCA9546: IPN E50300-001 (Preferred)

[1.3.28] Patsburg PCIe

[1.3.29] Patsburg SSB supports 8 x1 Gen2 downstream ports,
1 x4 Gen3 upstream port, and 1 x4 Gen2 upstream DMI2 port.

[1.3.30] Patsburg PCIe Port Connec­tivity

[1.3.31] See table below for S210-MBT2W Server PCIe Port
connectivity.

[1.3.32] Patsburg PCIe Connectivity

SSB DEVICE PORT

E

LECTRIC

AL

WIDTH

MODE COMMENT

PBG Slot 1 1-4 x4 Gen 2

PBG

ASPEED
AST2300
BMC

8x1Gen 1

PBG

IEEE139
4b

6x1Gen2

Extreme
Server
SKU SKU

PBG

Not in
use

5,7 x1 Gen 2

ABOUT THE SERVER SAS MODULE

1-29

[1.3.33] Oversubscription of DMI2

[1.3.34] Architecture is aware that the Patsburg DMI2 link will
be oversubscribed when there is max use of IO without the
Gen3 uplink connected. The PBG/CPT team indicated that
they have a bug on their arbitration logic where the PCIe Gen 2
Ports 1 and 5 are the only ones that get a Grant Count value of
4 and the PCIe Gen 2 Ports 2, 3, 4, 6, 7, 8 get Grant Count val­ues of 1.

[1.3.35] SAS Module

[1.3.36] The S210-MBT2W Server will support the Intel
designed Romley SAS ROC Module in PCIe slot 4. A special
bulkhead for the module will be needed for the "Rack" configu­ration designed by 3rd party (Kontron).

[1.3.37] Riser Support for 3rd Party
Chassis

[1.3.38] S210-MBT2W can support PCIe I/O risers in slots 2, 5,
and 6. GPIOs on the PCH will need to be used so that different
riser types can be identified according to the following tables.
Slot 2 has two clocks, slot 5 has three clocks, and slot 6 has
three clocks for supporting riser slots. Note: The I/O Riser
Boards for slots 5&6 will need to have pin B31 grounded.

[1.3.39] Riser ID Definition

LAN­PHYPC/
GPIO12
FM_RISE
R_ID4

SUS_ST
AT# /
GPIO61
FM_RISE
R_ID3

GPIO66
FM_RISE
R_ID2

GPIO65
FM_RISE
R_ID1

GPIO64
FM_RISE
R_ID0

Riser Slot
Usage

Riser
Slot5 pin
B31 ID2

Riser
Slot5&6
pin A50
ID1

Riser
Slot5&6
pin B48
ID0

Riser
Slot2 pin
A50 ID1

Riser
Slot2 pin
B48 ID0

[1.3.40] Riser IDs

SOCKET 2

ID4 ID3 ID2 ID1

ID0

SOCKET 1

3

D 3C 3B 3A 2D 2C 2B 2A 1B 1A 3D 3C 3B 3A 2D 2C 2B 2A 1B 1A

Riser
SLT2

xxxx

ABOUT THE SERVER SAS MODULE

1-30

Riser
SLT5

xxxx

Riser
SLT6

xxxx

Riser
SLT2

xxx11

x1
6

configs xxx10 x8 x8

xxx01 x8 x4 x4

Riser
SLT5

111xx x16

configs 010xx x8 x8

001xx x8 x4x4

Riser
SLT6

x1
6

111
xx

configs x8 x8

110
xx

x8 x4 x4

10
1xx

[1.3.40] Riser IDs (Continued)

SOCKET 2

ID4 ID3 ID2 ID1

ID0

SOCKET 1

3

D 3C 3B 3A 2D 2C 2B 2A 1B 1A 3D 3C 3B 3A 2D 2C 2B 2A 1B 1A

ABOUT THE SERVER SAS MODULE

1-31

[1.3.41]

S210­MBT2W
Riser
IDs

[1.3.40] Riser IDs (Continued)

SOCKET 2

ID4 ID3 ID2 ID1

ID0

SOCKET 1

3

D 3C 3B 3A 2D 2C 2B 2A 1B 1A 3D 3C 3B 3A 2D 2C 2B 2A 1B 1A

ABOUT THE SERVER LPC BUS

1-32

[1.3.42] LPC Bus

[1.3.43] The Patsburg SSB implements a Low Pin Count (LPC)
interface as described in the Low Pin Count Interface Specifica­tion, Revision 1.1. The LPC interface consists of a 4-bit data
bus, a control frame and a clock input. The LPC interface sup­ports only 8-bit I/O read and write cycles. The LPC interface
also includes sideband signal SERIRQ and SMI. The Patsburg
SSB LPC interface on S210-MBT2W supports the ASPEED
AST2300 BMC as well as the TPM/TCM security connector.

[1.3.44] Trusted Platform Mod­ule

[1.3.45] TPM Module

[1.3.46] Trusted Platform Module (TPM) is a chip that provides
platform security functions such as hash, encryption and secure
storage. The Romley platform should support a TCG Client
specification 1.2 compliant TPM device in order to support the
LT-SX/TXT feature. BIOS should implement support for TPM

1.2 device appropriately.

[1.3.47] TPM Clock Requirement

[1.3.48] The 33Mhz clock going to Patsburg needs to also be
connected to the TPM clock in order to comply with security
requirements. This ensures that malicious code does not by­pass security mechanisms and attempt to disable the TPM by
shutting off the 33Mhz clock. If the 33Mhz TPM clock is some­how shut off it will disable Patsburg, which will halt the system,
thus preventing any further security intrusion.

ABOUT THE SERVER TRUSTED PLATFORM MODULE

1-33

[1.3.49] TPM Header Pinout and Con­nector

[1.3.51] Baseboard Header: FCI MPN 87832-1420

[1.3.50] Romley TPM Module Connector Pin Assignment

PIN NAME PIN NAME

1 CLK_33M_TPM 2 IRQ_INIT3_3V_N

3

RST_IBMC_NIC_N_R
2

4P3V3

5 LPC_LAD<0> 6 TP_SERIAL

7 LPC_LAD<1> 8 P5V

9 LPC_LAD<2> 10 IRQ_SERIAL

11 LPC_LAD<3> 12 GND

13 LPC_FRAME_N 14 GND

ABOUT THE SERVER USB

1-34

[1.3.52] USB

[1.3.53] There are 14 USB 2.0 ports available from Patsburg.
All ports are high-speed, full-speed and low-speed capable. A
total of 10 USB 2.0 dedicated ports are required in order to sup­port the S210-MBT2W Enterprise Server and Extreme Server
SKU products.

[1.3.54] USB 2.0 port distribution is as follows; ASPEED
AST2300 BMC and the Zepher module consume 3 USB 2.0
ports, an internal 1x4 Type-A USB connector consumes 1 USB

2.0 port and 6 external USB 2.0 ports are needed (2 at front and
4 at rear).

Note:

[1.3.55] USB ports on the Romley-EP S210-MBT2W

board are required to be powered from STBY.

Note:

[1.3.56] USB Port 0 must be assigned to one of the rear I/

O panel ports for Microsoft Kernel Debug.

Note:

[1.3.57] There are 14 USB 2.0 per the Patsburg SSB C-

spec 1.0 document.

[1.3.58] There are 14 USB 2.0 per the Patsburg SSB C-spec

1.0 document.

[1.3.59] BIOS USB Debug Sup­port

[1.3.60] USB 2.0 UHCI Port#1 or Port#9 (assuming 0-based
numbering) MUST be connected to one of the external USB
connectors for BIOS Debug and Microsoft Kernel Debug. Refer
to Romley WW52 2009 MOW for details.

[1.3.61] Wake-on-USB

[1.3.62] S210-MBT2W Server shall support Wake on USB on
the rear and front panel USB ports for S1. S210-MBT2W will
also support Wake on USB from S3/S4/S5. As a result,
Standby power on USB ports is required.

ABOUT THE SERVER USB CONNECTORS

1-35

[1.3.63] USB Connectors

[1.3.64] Front Panel USB2.0 Connec­tor

[1.3.66] Internal USB2.0 Type-A
Connector

[1.3.68] eUSB (Zepher) Module

[1.3.69] Intel's Z-U130 Value Solid State Drive (SSD) is a USB

2.0 storage solution built around high performance Intel®
NAND flash memory. This module uses single-level cell Intel
NAND flash memory with cache programming and dual plane
feature set designed to improve overall module performance.
Additionally each module has two TSOP packages attached to
the printed circuit board with densities varied by the number of
die within each package (i.e. 2 GB = 2 X 512 MB die per pack­age and 4 GB = 4 X 512 MB die per package). The Intel Z­U130 Value SSD supports the Universal Serial Bus (USB) spec­ification v2.0 and is backward compatible with v1.1. The mod­ule uses industry standard connectors which are available in
two sizes. This device can be used with operating systems
compatible with the USB Mass Storage Class specification
v1.0.

[1.3.70] The LP version of eUSB (Zepher) will be used to
increase gap between PCIe cards and the eUSB (Zepher)
device for the 2U rack and to try to use only one type across all
Romley products (customer won't then need to stock two
types). The eUSB (Zepher) LED signal will be hooked up so
that it shows on FP HDD activity LED.

[1.3.65] USB2.0 Baseboard Front-Panel Connector Definition

PIN SIGNAL NAME SIGNAL NAME PIN

1+5V+5V2

3 USB_N USB_N 4

5 USB_P USB_P 6

7GNDGND8

9 Key_Pin NC 10

[1.3.67] Internal USB2.0 Type A Connector Definition

PIN SIGNAL NAME

1+5V

2 USB_N

3 USB_P

4GND

[1.3.71] eUSB (Zepher) Connector Definition

PIN SIGNAL NAME PIN SIGNAL NAME

1+5V2NC

3 USB_N 4 NC

ABOUT THE SERVER EUSB (ZEPHER) MODULE

1-36

[1.3.72] eUSB (Zepher) Pin Assignment 2x5 Connector

(Bottom View)

[1.3.73] MECHANICAL STANDOFF: The eUSB (Zepher) mod-

ule requires one plastic standoff to mount to the baseboard.
Below is the standoff used on Thurley and is recommended for
the Romley-EP platform. The standoff height dimension 'A' is

6.4mm and the INTEL part number is iP/N E54719-001.

[1.3.74] eUSB (Zepher) Mechanical Standoff

Note:

[1.3.75] (Zepher) is no longer sold by Intel. Instead, com-

panies like Smart Modular are offering "eUSB (Zepher)­compatible" eUSB (Embedded USB) devices that can be
used in Romley Platforms.

5 USB_P 6 NC

7GND8NC

9 Key Pin 10 LED#

[1.3.71] eUSB (Zepher) Connector Definition

PIN SIGNAL NAME PIN SIGNAL NAME

ABOUT THE SERVER IEEE 1394B

1-37

[1.3.76] IEEE 1394b

[1.3.77] S210-MBT2W Extreme Server SKU offers two front
panel IEEE 1394b ports via a discrete controller (LSI FW643E-

02). The FW643E-02 uses a PCIe x1 Gen 1 upstream interface
from Patsburg PCH. When connected to 1394b compliant
devices, the FW643E-02 can transfer data at speeds of up to
800 Mbps. The S210-MBT2W baseboard includes two internal
1394b connectors that allows for front panel 1394b cable
attachments.

[1.3.78] IEEE 1394b Discrete Host Controller Block Dia-

gram

[1.3.79] IEEE 1394b Port Cable
and Connector

[1.3.80] See S210-MBT2W Extreme Server SKU Front Panel
Section for details on the 1394b Cable, Connector, and pinout.

ABOUT THE SERVER SERIAL ATTACHED SCSI/SERIAL ATA

1-38

[1.3.81] Serial Attached SCSI/Serial ATA

[1.3.82] Serial Attached SCSI /
Serial ATA

[1.3.83] The Thurley platform had 6 SATA 3Gbps ports from
ICH10. For Romley with Patsburg -A, 4 SATA 6Gbps ports is
available as the base SKU from PBG RHS SCU0 (ports3:0).
An upgrade option is available through Dynamic SKU'ing Key to
support 4 additional SATA 6Gbps ports from PBG RHS SCU1
(ports7:4), providing a total of 8 SATA 6Gbps ports. There are
additional SATA Ports from the PBG LHS AHCI (ports 5:0).
Four of the 3Gbps SATA ports (ports 5:2) from PBG LHS are
currently unused. The two remaining SATA ports (ports1:0) are
6Gbps and need to connect to 7-pin SATA Gen3 connectors.
Other upgrade options are also available that provide either 4
or 8 SAS 6Gbps ports from the PBG RHS SCU[1:0]. Refer to
for details on the SATA ports available with the different Pats­burg SKUs.

[1.3.84] Patsburg Dynamic SKU'ing

[1.3.85] In general for all 7 keys as well as the "no key" case,
"basic" SW RAID is enabled in all cases. "Basic SW RAID"
includes RAID 0/1/10 from both LSI and RSTe for all SATA ports
(4 or 8 from the SCU and 2 from the ACHI - although RAID10 is
not supported on the ACHI ports since there are only 2 ports
and RAID 10 requires more than 2 ports) and for all 8 SAS ports

from the SCU. In addition Basic SW RAID also includes RSTe
SW RAID 5 for the first 4 SATA only ports from the SCU and
support for the second 4 SCU SATA only ports is expected to
be confirmed as supported soon. The user has to choose to
use either LSI or RSTe on the ACHI ports (can't mix w/in the
ACHI) and the user has to choose to use either LSI or RSTe on
the SCU ports (can't mix w/in the SCU). Currently our BIOS
would allow the user to choose a different RAID vendor on the
ACHI vs. on the SCU, but we are working to modify BIOS so
that it forces the user to chose a single RAID vendor (LSI or
RSTe) for all ports that originate in Patsburg (ACHI + SCU).
Below are the 8 SKU's (1xNoKey and 7xkey) that are POR
today:

 NoKey - 4 SCU based SATA only Ports (No PSB ROM, No

LSI ROM)

 Key #1 - 4 SCU based SATA only Ports w/ LSI SW RAID5

added (No PSB ROM, Yes LSI ROM)

 Key #2 - 8 SCU based SATA only Ports (Yes PSB ROM

#9, No LSI ROM)

 Key #3 - 8 SCU based SATA only Ports w/ LSI SW RAID5

added (Yes PSB ROM #9, Yes LSI ROM)

 Key #4 - 4 SCU based SAS/SATA Ports (Yes PSB ROM

#1, No LSI ROM)

 Key #5 - 4 SCU based SAS/SATA Ports w/ LSI SW RAID5

added (Yes PSB ROM #1, Yes LSI ROM)

ABOUT THE SERVER SERIAL ATTACHED SCSI / SERIAL ATA

1-39

 Key #6 - 8 SCU based SAS/SATA Ports (Yes PSB ROM

#5, No LSI ROM)

 Key #7 - 8 SCU based SAS/SATA Ports w/ LSI SW RAID5

added (Yes PSB ROM #5, Yes LSI ROM)

[1.3.86] Still TBD and not currently official POR:

 Potential Key #8 version a - 8 SCU based SAS/SATA

Ports w/ XOR enabled and LSI SW RAID5 supported (Yes
PSB ROM #7, Yes LSI ROM)

 Potential Key #8 version b - 8 SCU based SAS/SATA

ports w/ XOR enabled and both LSI SW RAID5 and RSTe
SW RAID5 (if adding RSTe SW RAID5 adds no incremen­tal cost over just the XOR or if RSTe SW RAID5 shows
compelling superior performance over LSI SW RAID5).
(Yes PSB ROM #8, Yes LSI ROM)

 Potential Key #9 (only if #8a above is POR and #8b is

NOT POR and RSTe is either "free" with XOR and/or if
RSTe shows significant performance improvement over
LSI SW RAID5) - 8 SCU based SAS/STAT ports w/ XOR
enabled and RSTe SW RAID5 supported. (Yes PSB ROM
#8, No LSI ROM). TBD scenarios are:

 #8a only or …

 #8a with #9 or …

 #8b only

 New Key#10 that is like Key #5 but w/ RSTe SW RAID5

instead of LSI SW RAID5 (would use PSB ROM#2)

 New Key#11 that is like Key #7 but w/ RSTe SW RAID5

instead of LSI SW RAID5 (would use PSB ROM#6)

[1.3.87] Baseboard Routing of SAS

[1.3.88] The SAS 6Gbps interface on the baseboard be routed
using 85 Ohm differential impedance in order to increase the
overall trace length in the baseboard. The 85 Ohm differential
routing is a deviation of the SAS 6Gbps specification which
calls for routing the SAS interface using 100 Ohm differential
impedance. We understand that this trade off allows for
increased routing length between the Patsburg SAS interface
and the baseboard SAS connectors. We also understand that
the rest of the topology will have to meet SAS specification and
utilize SAS cables, connectors, and backplanes that meet 100
Ohm differential impedance. This is a requirement since multi­ple SAS adapters must be supported on this platform.

[1.3.89] SAS/SATA Connector Place­ment

[1.3.90] For the S210-MBT2W Server Pedestal Products, there
is a desire from Marketing to support miniSAS (SFF-8087) con­nectors for the various SAS/SATA ports going to HSBPs (Hot
Swap Backplanes) instead of the standard 7pin connectors.
Since most of the HSBPs are moving to miniSAS (for future
12G support), this would minimize the number of 7pin to SFF­8087 conversion cables required to be shipped with the system.
In addition, there are potential layout advantages to going with
miniSAS connectors. However, evaluations show that mini-

ABOUT THE SERVER SERIAL ATTACHED SCSI / SERIAL ATA

1-40

SAS connectors cannot be used on S210-MBT2W. Since
Quad miniSAS connectors can support 4 SAS/SATA ports, this
allows removal of 4 individual 7pin connectors, which take up
more area. T22W needs to support 10 SATA/SAS ports. 8 of
these ports need to go to HSBPs and 2 are reserved for ODDs
(Optical Device Drives) as well as a few other SATA device
options (See Table below).

Table 21:

[1.3.92] SATA DOM Support

[1.3.93] The S210-MBT2W does not have the necessary
design hooks in place to support a SATA DOM (Disk on Mod­ule) with a special pin on the 7-pin connector dedicated for
power (see NOTE below). However, it can support a SATA
DOM where power is provided through an external 4 pin HDD
power cable connected to the power supply. It can also support
a cabled SATA SSD in a DIMM form-factor; provided an empty
DIMM slot is available.

[1.3.91] S210-MBT2W SATA/SAS Port Mapping

PORT TYPE CONNECTOR DEVICE

PBG RHS
SCU0/SCU1:
PORT[7:0]

SATA 6G
SAS 6G

8 x 7-pin HSBP

PBG LHS
AHCI:
PORT[1:0]

SATA 6G 2 x 7-pin

Opt1: ODD
Opt2: SSD
direct connect

Note:

[1.3.94] There is a Common Core CCB proposing additional

circuits to be added to existing 7pin SATA connectors for sup­porting the Pin7 Power option SATA DOM. Whether or not
this can be supported on certain Romley Products will be
decided by each PDT.

Note:

[1.3.95] S210-MBT2W also support On board Power on

SATA DOM as Alternative.

ABOUT THE SERVER SERIAL ATTACHED SCSI / SERIAL ATA

1-41

[1.3.97] SATA DOM with External Power Cable

[1.3.98] Viking SATA DIMM

[1.3.99] SATA/SAS Connector Pin­outs

Note:

[1.3.96] S210-MBT2W Only support vertical/high profile

SATA DOM module.

[1.3.100] 7-pin SATA Connector

PIN SIGNAL NAME

1GND

2SATA_TX_P

3SATA_TX_N

4GND

5SATA_RX_N

6SATA_RX_P

7GND

[1.3.101] SATA/SAS Connector Colors

PIN

CONNECTOR

C

OLOR

CABLE CONNECTOR IPN

3G SATA BLACK BLACK C92545-003

6G SATA WHITE BLACK E82125-006

6G SAS BLUE BLACK E82125-002

12G SAS ORANGE BLACK TBD

MINI-SAS METAL

BLACK
SLEEVE

D37394-001
(PLACE­HOLDER)

ABOUT THE SERVER SERIAL ATTACHED SCSI / SERIAL ATA

1-42

[1.3.102] The SATA active LED output of the Patsburg PCH
should be WIRE-OR'd via zero ohm resistors with the add-in
card LED DRIVE ACTIVE_N signal that is connected to the
baseboard via 2-pin header.

[1.3.104] It is important to note that the AHCI SATA3 ports do
not communicate with the AHCI SATA3 ports from a RAID stack
perspective.

[1.3.105] Romley Keys

[1.3.106] Single 3pin header on baseboard that covers S210­MBT2W key combinations.

[1.3.107] Romley Baseboard Activation Key Connector: Molex
p/n 53290-0380

[1.3.103] SATA/SAS LED

PIN SIGNAL NAME

1 LED_HD_ACTIVE_L

2NC

[1.3.108] Baseboard SAK/SRAK/RAK Connector Pinout

PIN SIGNAL NAME

1GND

2 FM_PBG_DYN_SKU_KEY

5 FM_SSB_SAS_SATA_RAID_KEY

ABOUT THE SERVER HDD BACKPLANE SUPPORT

1-43

[1.3.109] HDD Backplane Support

[1.3.110] SATA/SAS SGPIO Header

[1.3. 111] The HSBPs will support SGPIO interface (SFF-8485).
On S210-MBT2W the SGPIO signals are passed through the
sideband signal pins on the SFF-8087 connectors and do not
require individual SGPIO headers.

[1.3.113] HSBP I2C Bus

[1.3.114] The baseboard must add a 3pin I2C header to base­board for a bus to the HSBP. The 3-pin header on the board
must implement MLX 22-43-6030 (white housing). This header
does not contain any addressing wires since the circuits on the
HSBP will handle the addressing. The proposal is to daisy
chain the I2C for up to 3 HSBPs in a single server.

[1.3.115] This same I2C bus will also go to a 4-pin header with

3.3V STBY that is intended to be used for third party fan control
circuits using a Maxim 72408 controller. The 4-pin connector
will use FOX HF4504E and must have 30u gold plating. This is
in addition to maintaining the typical IPMB header in case we
want to offer this for 3rd party chassis HSBPs.

[1.3.112] SATA SGPIO Connector

PIN SIGNAL NAME

1SCLK

2SLOAD

3GND

4SDATAOUT0

5SDATAOUT1

[1.3.116] HSBP 3-pin Bus Connector

PIN SIGNAL NAME

1 SMB_3V3SB_DAT

2GND

3 SMB_3V3SB_CLK

[1.3.117] HSBP 4-pin IPMB Bus Connector for Maxim 72408 fan
controller

PIN SIGNAL NAME

1 SMB_3V3SB_DAT

2GND

3 SMB_3V3SB_CLK

4P3V_STBY

ABOUT THE SERVER HDD BACKPLANE SUPPORT

1-44

[1.3.118] IPMB HSBP Connector

PIN SIGNAL NAME

1 SMB_5VSB_DAT

2GND

3 SMB_5VSB_CLK

4 P5V_STBY

ABOUT THE SERVER LAN ON MOTHERBOARD

1-45

[1.3.119] LAN on Motherboard

[1.3.120] The S210-MBT2W Server will use the Intel® I350
code named Powerville Quad 10/100/1000 integrated MAC and
PHY controller. The Powerville LOM requires a PCIe x4 Gen2
upstream interface. When connected to a CPU Gen3 interface,
the Gen3 will downshift to Gen2.

[1.3.121] The Powerville LAN controller will be on standby
power so that Wake on LAN and manageability functions can
be supported.

[1.3.122] It is expected that Powerville support the normal
LINK/Activity speed LEDS as well as the Proset ID function,
and that should connect the Powerville LAN port LED signals to
the corresponding RJ45 connector LEDs. These LEDs should
be powered from a standby voltage rail.

[1.3.123] Powerville will be used in conjunction with the
ASPEED AST2300 BMC for out of band Management traffic.
The BMC will communicate with Powerville over a NC-SI inter­face (RMII physical). Powerville will be on standby power so
that the IBMC can send management traffic over the NC-SI
interface to the network during sleep states, S3, S4 and S5.

[1.3.124] Powerville Thermal Sensor

[1.3.125] Powerville will have a integrated digital thermal sen­sor accessible through CSR and manageability registers. The

thermal sensor can be programmed to trigger digital pins and
thermal throttling with hysteresis. There will also be thermal
diode. The thermal diode is primarily designed for lab usage.
The development team should use the Powerville thermal sen­sor in the FSC (fan speed algorithm).

[1.3.126] NIC Status LED

[1.3.127] The S210-MBT2W design needs to ensure that the
following scheme for the NIC Speed is incorporated into the
EEPROM.

[1.3.128] NIC LED Behavior

LED COLOR LED STATE NIC STAT E

Green/Amber (Right)

Off

3rd Fastest (10 Mbps
for Powerville)

Amber

2nd Fastest (100
Mbps for Powerville)

Green

Fastest (1000 Mbps
for Powerville)

Green (Left)

On Active Connection

Blinking

Transmit / Receive
activity

ABOUT THE SERVER LAN ON MOTHERBOARD

1-46

[1.3.129] MAC Address Definition

[1.3.130] The S210-MBT2W products have the following 3
MAC addresses assigned to it.

 NIC 1 MAC address

 NIC 2 MAC address - Assigned the NIC 1 MAC address

+1 (Server Management & WOL)

 Dedicated NIC MAC address - Assigned the NIC 1 MAC

address +2

[1.3.131] LAN Manageability

[1.3.132] Port 2 (assuming 1 based numbering) will be used by
the BMC firmware to send management traffic. In standby in
order to save power, Port2 (assuming 1 based numbering); will
be the only port to support Wake on LAN. The EEPROM must
be programmed to turn off this feature from the other ports in
order to maximize power savings during sleep states.

[1.3.133] LAN Connector Ordering

[1.3.134] When looking in at the I/O panel the NIC 1 should be
wired to the left most RJ45 connector.

[1.3.135] MDI Flip Capability

[1.3.136] Powerville has MDI flip capability. This feature must
NOT be used because it will conflict with the LAN ordering.

[1.3.137] Wake-on-LAN

[1.3.138] WOL shall be supported on the Powerville LAN con­troller for all supported Sleep states.

ABOUT THE SERVER VIDEO

1-47

[1.3.139] Video

[1.3.140] Video Engine supports high performance video com­pressions with a wide range of video quality and compression
ratio options. The adopted compressing algorithm is a mixed
one including JPEG and Vector Quantization

[1.3.141] Features:

 Directly connected to AHB bus interface for register pro-

gramming

 Directly access video data through M-Bus

 Maximum operation frequency: 266MHz

 Video source can be from internal VGA output or from

external DVO input

 Support two video compression formats

 YUV420: for lower video quality but higher compression

ratio

 YUV444: for higher video quality but lower compression

ratio

 Support high resolution video compression up to

1920x1200x32bpp@60Hz

 Target frame rate: 60 frame/sec for 1280x1024@60Hz

under YUV420 compression format

 Support intelligent scene change detection by comparing

CRC code of each video scan line, signifcantly reducing
memory bandwidth requirement

 Support smart video mode detection functions

 Support video mode watch dog interrupt when source

video mode change

 Support programmable bit resolution truncation to input

video data

 Support 12 selectable JPEG quality levels

 Support VQ compression mode

 Support video auto stream mode and single frame trigger

mode.

[1.3.142] Video Connector Pinouts

[1.3.143] Rear VGA Video Connector Pinout

PIN SIGNAL NAME

1RED

2GREEN

3BLUE

4N/C

ABOUT THE SERVER VIDEO

1-48

5GND

6GND

7GND

8GND

9 P5V (fuse not populated)

10 GND

11 N/C

12 DDC_SDA

13 HSYNC

14 VSYNC

15 DDC_SCL

[1.3.143] Rear VGA Video Connector Pinout (Continued)

PIN SIGNAL NAME

ABOUT THE SERVER SERIAL PORT

1-49

[1.3.144] Serial Port

[1.3.147] Wake-On-Ring

[1.3.148] Wake on Ring support is not required on the external
Serial port.

[1.3.145] Serial Port A (COM1, external on rear panel DB9
connector)

PIN SIGNAL NAME PIN SIGNAL NAME

1SPA_DCD 2SPA_SIN_N

3 SPA_SOUT_N 4 SPA_DTR

5GND 6SPA_DSR

7SPA_RTS 8SPA_CTS

9 SPA_RI (Not Required)

[1.3.146] Serial Port B (COM2, on internal header)

PIN SIGNAL NAME PIN SIGNAL NAME

1SPA_DCD 2SPA_DSR

3 SPA_SIN_N 4 SPA_RTS

5 SPA_SOUT_N 6 SPA_CTS

7SPA_DTR 8SPA_RI

9GND

ABOUT THE SERVER FRONT PANEL

1-50

[1.3.149] Front Panel

[1.3.150] The S210-MBT2W Server products will use a com­mon front panel.

[1.3.151] Front Panel Connector

[1.3.152] The common front panel feature set conforms to the
industry standard SSI 2x12 connector specification.

[1.3.155] Front Panel LED Overview

[1.3.153] SSI Common Front-Panel Connector Pinout
(Baseboard)

PIN SSI SIG NAME PIN SSI SIG NAME

1 SB3.3V 2 SB3.3V

3 Key 4 SB5V

5 Power LED Cathode 6

System ID LED Cath­ode

73.3V 8

System Fault LED
Anode

9

HDD Activity LED
Cathode

10

System Fault LED
Cathode

11 Power Switch 12 NIC#1 Activity LED

13 GND (Power Switch) 14 NIC#1 Link LED

15 Reset Switch 16 I2C SDA

17

GND (Reset/ID/NMI
Switch)

18 I2C SCL

17 System ID Switch 18 Chassis Intrusion

21 Pull Down 22 NIC#2 Activity LED

23 NMI to CPU Switch 24 NIC#2 Link LED

Note:

[1.3.154] The presence of current limiting resistors on the

base board is an important part of the Front panel definition.

[1.3.156] Front Panel LED Functionality

LED COLOR

CONDIT

ION

DESCRIPTION

POWER /
SLEEP

Green On Power on or S0 sleep

Green Blink

S1 sleep or S3 standby only for
workstation baseboards

Off Off (also sleep S4 / S5 modes)

[1.3.153] SSI Common Front-Panel Connector Pinout
(Baseboard)

PIN SSI SIG NAME PIN SSI SIG NAME

ABOUT THE SERVER FRONT PANEL

1-51

[1.3.157] S210-MBT2W IEEE 1394
(Extreme Server SKU Only)

[1.3.158] The 1394b on board connector is a 2x5 (No Shrouded
Header with Pin 2 pulled). Color is red. See the following table
for details on Pin definition.

STATUS

Green On System ready/No alarm

Green Blink

System ready, but degraded:
redundancy lost such as PS or fan
failure; non-critical temp/voltage
threshold; battery failure; or pre­dictive PS failure.

Amber On

Critical alarm: Voltage, thermal, or
power fault; CPU0 missing; insuffi­cient power unit redundancy
resource offset asserted

Amber Blink

Non-Critical failure: Critical temp/
voltage threshold; VDR hot
asserted; min number fans not
present or failed

Off

AC power off: System unplugged
AC power on: System powered off
and in standby, no prior
degraded\non-critical\critical state

HDD

Green Blink HDD access

Amber

Not Sup­ported

HDD fault

Amber

Not Sup­ported

Predictive failure, rebuild, identify

Off No access and no fault

[1.3.156] Front Panel LED Functionality

LED COLOR

CONDIT

ION

DESCRIPTION

LAN #1
ACTIVITY

Green On LAN link/ no access

Green Blink LAN access

Off Idle

LAN #2
ACTIVITY

Green On LAN link/ no access

Green Blink LAN access

Off Idle

IDENTFI­CATION

Blue

Not Sup­ported

Front panel chassis ID button
pressed

Blue

Not Sup­ported

Unit selected for identification via
software

Off No identification

[1.3.156] Front Panel LED Functionality

LED COLOR

CONDIT

ION

DESCRIPTION

ABOUT THE SERVER FRONT PANEL

1-52

[1.3.161] 1394b On Board Connector

[1.3.162] IEEE 1394b Socket and Connector/Cable

[1.3.159] 1394b Connector Pinout

PIN SIGNAL NAME PIN

1 Ground 6 TPB+

2 Key (no pin) 7 TPB_REF

3 +12V (fused) 8 TPA_REF

4 +12V (fused) 9 TPA-

5TPB-10TPA+

Note:

[1.3.160] IEEE-1394 ports may be assigned as needed.

[1.3.163] IEEE 1394b Socket and Connector/Cable

ITEM NO.ITEM

1 Beta 1394B Jack

2 Bilingual 1394B Jack

3 1394B Cable

12 3

ABOUT THE SERVER FRONT PANEL

1-53

[1.3.164] An internal IEEE 1394b with a Bilingual Socket on
one side and a 2x5 connector on the other.

[1.3.165] Internal USB to Flash Card Reader (Example)

ABOUT THE SERVER CLOCKS

1-54

[1.3.166] Clocks

[1.3.167] As an EMI reduction requirement all unused clocks
shall be turned off during BIOS setup for the CK420BQ,
DB1900Z, and CKMNG+. This is accomplished by using the
Clock SMBus interface.

[1.3.168] All root and end points for SNB –EP / IVB -EP PCIe
should be from the same clock source. This is a requirement
put forth by the SNB-EP and IVB-EP Silicon Teams.

[1.3.169] All SNB–EP and IVB-EP processors BCLK and
PCIE_CLK should be from the same clock source.

[1.3.170] S210-MBT2W Product System Clock Diagram

Note:

[1.3.171] Please see the CK420BQ Vendor Data sheet for

specific resistor values on single and dual load topologies.

ABOUT THE SERVER SMBUS

1-55

[1.3.172] SMBus

[1.3.173] The S210-MBT2W products must comply with the
Romley Platform common-core SMBUS architecture in order to
maximize BIOS, Patsburg ME Firmware, and ASPEED
AST2300 BMC firmware. This is a requirement in order to mini­mize BIOS and Firmware code development efforts and
improve validation and product board stability and debugging.

[1.3.174] SMBus Voltage Trans­lation

[1.3.175] The SNB-EP SMBUS Master Controller voltage trans­lation devices required for use on the Romley platforms are:
PCA9517A. PCA9517A must be pulled up to the Vcc(b) –high
voltage side.

[1.3.176] SMBus Architecture

[1.3.177] The S210-MBT2W Management SMBus Architecture:
This section outlines the platform management SMBUS topolo­gies and interconnects. It is expected that this architecture will

vary depending on the manageability solution utilized for each
of the various Romley designs.

[1.3.178] S210-MBT2W Product System SMBus

ABOUT THE SERVER SMBUS ARCHITECTURE

1-56

[1.3.179] S210-MBT2W Product Management SMBus

[1.3.180] IPMB Header 4 pin

[1.3.181] PIN [1.3.182] SIGNAL NAME

[1.3.183] 1 [1.3.184] SMB_IPMB_5VSB_DAT

[1.3.185] 2 [1.3.186] GND

[1.3.187] 3 [1.3.188] SMB_IPMB_5VSB_CLK

[1.3.189] 4

[1.3.190] P5V_STBY (P3V_STBY for Kontron Fan

Connector)

ABOUT THE SERVER GENERAL PURPOSE I/O

1-57

[1.3.191] General Purpose I/O

[1.3.192] Two devices on the Romley -EP Pedestal platform
have GPIO’s available for design customization:

 Patsburg SSB Controller

 ASPEED AST2300 BMC

Note:

[1.3.193] All unused GPIO pins that default to native input or

GPI must be properly terminated, so that they are at a pre­defined level and do not cause undue side effects.

ABOUT THE SERVER GPIO LIST

1-58

[1.3.194] GPIO List

[1.3.195] GPIO List

ITEM PIN #PIN NAME

IO

TYPE

POWER

WELL

PU/PD

V

ENDOR

R

ECOMMENDATIONS

(

REFERENCE DESIGN)

A

LTERNATE

FUNCTION

(D

EFAULT)

USED

FUNCTION

NET

NAME

STATE
AFTER

RESET

NET

CONNECT

TO

1 E24 BMBUSY_N_GPIO0 O P1V1_SSB PU

"In Main Power Well.
Muxed with BM_BUSY#.
Defaults to GPI. If not
used, require a weak pull­up (8.2kohm to 10kohm) to
Vcc3_3"

BMBUSY_N
(GPI)

GPO

IRQ_SSB
_SCI_WH
EA_N

high

pull up
P3V3 via
10Kohm

P3V3

2 AL19 TACH1_GPIO1 I P1V1_SSB PU

"In Main Power Well.
Muxed with TACH1.
Defaults to GPI. If not
used, require a weak pull­up (8.2kohm to 10kohm) to
Vcc3_3"

TACH1
(GPI)

GPI

BOARD_S
KU1

high

PU to
P3V3 via
10K (NI)
and PD
via 10K

board
SKU ID

3 AF32 PIRQE_N_GPIO2 I P1V1_SSB PU

"In Main Power Well.
Muxed with PIRQ[H:E]#.
Defaults to GPI. If not
used, require a weak pull­up (8.2kohm to 10kohm) to
Vcc3_3"

PIRQE_N
(GPI)

GPI

FM_ERR0
_N

high

GTL to
LVT TL
conver­sion

P3V3

4 AL22 PIRQF_N_GPIO3 I P1V1_SSB PU

"In Main Power Well.
Muxed with PIRQ[H:E]#.
Defaults to GPI. If not
used, require a weak pull­up (8.2kohm to 10kohm) to
Vcc3_3"

PIRQF_N
(GPI)

GPI

FM_ERR1
_DLY_N

high

pull up
10k to
P3V3
and con­nect to
CPLD

P3V3

5 AA32 PIRQG_N_GPIO4 I P1V1_SSB PU

"In Main Power Well.
Muxed with PIRQ[H:E]#.
Defaults to GPI. If not
used, require a weak pull­up (8.2kohm to 10kohm) to
Vcc3_3"

PIRQG_N
(GPI)

GPI

FM_IBMC
_SSB_SM
I_LPC_N

high

BMC via

37.4ohm
and pull
up P3V3
via
10Kohm

P3V3

ABOUT THE SERVER GPIO LIST

1-59

6 AR16 PIRQH_N_GPIO5 I P1V1_SSB PU

"In Main Power Well.
Muxed with PIRQ[H:E]#.
Defaults to GPI. If not
used, require a weak pull­up (8.2kohm to 10kohm) to
Vcc3_3"

PIRQH_N
(GPI)

GPI

IRQ_IBMC
_SSB_NMIhigh

BMC via
level shift
and pull
up P3V3
via
10Kohm

P3V3

7 Y31 TACH2_GPIO6 I P1V1_SSB PU

"In Main Power Well.
Muxed with TACH[3:2].
Defaults to GPI. If not
used, require a weak pull­up (8.2kohm to 10kohm) to
Vcc3_3"

TACH2
(GPI)

GPI

BOARD_S
KU2

high

PU to
P3V3 via
10K (NI)
and PD
via 10K

board
SKU ID

8 AJ35 TACH3_GPIO7 I P1V1_SSB PU

"In Main Power Well.
Muxed with TACH[3:2].
Defaults to GPI. If not
used, require a weak pull­up (8.2kohm to 10kohm) to
Vcc3_3"

TACH3
(GPI)

GPI

BOARD_R
EVISION0

high

PU to
P3V3 via
10K and
PD via
10K (NI)

board
revi­sion ID

9 F38 GPIO8 I P3V3_AUX PU

"In Suspend Power Well.
Unmuxed. Defaults to
GPO. "

IRQ_CATE
RR_DLY_B
UF_N
(GPO)

GPI

IRQ_CAT
ERR_DLY
_BUF_N

high

CPU via
GTL/
LVT TL
transla­tor, D flip
flop, buf­fer and
pull up
P3V3_A
UX via

4.7Kohm

P3V3
_AUX

10 L39 OC5_N_GPIO9 I P3V3_AUX PU

"In Suspend Power Well.
Muxed with OC5#.
Defaults to OC5#. If not
used, require a weak pull­up (8.2kohm to 10kohm) to
Vcc3_3"

OC5_N
(GPI)

GPI

PU_USB_
OC5_N

high

pull up
P3V3_A
UX via
10Kohm

[1.3.195] GPIO List (Continued)

ITEM PIN #PIN NAME

IO

TYPE

POWER

WELL

PU/PD

V

ENDOR

R

ECOMMENDATIONS

(

REFERENCE DESIGN)

A

LTERNATE

FUNCTION

(D

EFAULT)

USED

FUNCTION

NET

NAME

STATE
AFTER

RESET

NET

CONNECT

TO

ABOUT THE SERVER GPIO LIST

1-60

11 K30 OC6_N_GPIO10 I P3V3_AUX PU

"In Suspend Power Well.
Muxed with OC6#.
Defaults to OC6#. If not
used, require a weak pull­up (8.2kohm to 10kohm) to
Vcc3_3"

OC6_N
(GPI)

GPI

PU_USB_
OC6_N

high

Pull up
P3V3_A
UX via
10Kohm

P3V3
_AUX

12 J31

SMBALERT_N_GPIO

11

I P3V3_AUX PU

"In Suspend Power Well.
Muxed with SMBALERT#.
Defaults to SMBALERT#.
If not used, require a weak
pull-up (8.2kohm to
10kohm) to Vcc3_3"

SMBALERT
_N (GPI)

GPI

PU_SMB_
ALERT_N

high

Pull up
P3V3_A
UX via
10Kohm

P3V3
_AUX

SMBus
Alert

13 F39 LANPHYPC_GPIO12 I P3V3_AUX PU

"In Suspend Power Well.
Muxed with
LAN_PHY_PWR_CTRL#.
The default for this signal
is determined by soft strap
configuration and the
GPIO_USE_SEL bit is
ignored. "

LAN_PHY_
PWR_CTRL
_N (GPO)

GPI

FM_RISE
R_ID4

high

Connect
to PCIE
SLOT5
and pull
up 10k to
P3V3_A
UX

i350
LAN
device
control

14 AV24 GPIO13 I P3V3_AUX PU

"In Suspend Power Well.
Unmuxed. Defaults to GPI.
If not used, require a weak
pull-up (8.2kohm to
10kohm) to VccSus3_3"

GPIO13
(GPI)

GPI

FM_IBMC
_SSB_SCI
_LPC_N

high

Connect
to BMC
and pull
up
P3V3_A
UX via
10Kohm

P3V3
_AUX

BMC
SCI to
PCH

[1.3.195] GPIO List (Continued)

ITEM PIN #PIN NAME

IO

TYPE

POWER

WELL

PU/PD

V

ENDOR

R

ECOMMENDATIONS

(

REFERENCE DESIGN)

A

LTERNATE

FUNCTION

(D

EFAULT)

USED

FUNCTION

NET

NAME

STATE
AFTER

RESET

NET

CONNECT

TO

ABOUT THE SERVER GPIO LIST

1-61

15 K38 OC7_N_GPIO14 I P3V3_AUX PU

"In Suspend Power Well.
Muxed with OC7#.
Defaults to OC7#. If not
used, require a weak pull­up (8.2kohm to 10kohm) to
Vcc3_3"

OC7_N
(GPI)

GPI

PU_USB_
OC7_N

high

pull up
P3V3_A
UX via
10Kohm
and con­nect to
FM_ERR
2_N via
0ohm
(EMPTY)
resistor

P3V3
_AUX

16 E30 GPIO15 O P3V3_AUX NA

"In Suspend Power Well.
Unmuxed. Defaults to
GPO. "

GPIO15
(GPO)

GPO

FM_SSB_
SAS_SAT
A_RAID_K
EY

N/A

connect
to pin 3
of JP3
(RAID
Key con­nector)
via

33.2ohm,
pull

2.21k to
P3V3_A
UX

P3V3
_AUX

Upgrad
e KEY

17 H22 SATA4GP_GPIO16 I P1V1_SSB PU

"In Main Power Well.
Muxed with SATA4GP.
Defaults to GPI. If not
used, require a weak pull­up (8.2kohm to 10kohm) to
Vcc3_3"

SATA4GP
(GPI)

GPI

FM_THRO
TTLE_N

high

pull up
P3V3 via
10Kohm,
and con­nect to
CPU

P3V3

THROT
TLE

18 AV21 TACH0_GPIO17 I P1V1_SSB PU

"In Main Power Well.
Muxed with TACH0.
Defaults to GPI. If not
used, require a weak pull­up (8.2kohm to 10kohm) to
Vcc3_3"

TACH0
(GPI)

GPI

BOARD_S
KU0

high

PU to
P3V3 via
10K and
PD via
10K (NI)

board
SKU ID

[1.3.195] GPIO List (Continued)

ITEM PIN #PIN NAME

IO

TYPE

POWER

WELL

PU/PD

V

ENDOR

R

ECOMMENDATIONS

(

REFERENCE DESIGN)

A

LTERNATE

FUNCTION

(D

EFAULT)

USED

FUNCTION

NET

NAME

STATE
AFTER

RESET

NET

CONNECT

TO

ABOUT THE SERVER GPIO LIST

1-62

19 B29 GPIO18 I/O P1V1_SSB NA

"In Main Power Well.
Unmuxed. Defaults to
GPO. "

GPIO18
(GPO)

GPO

TP_SSB_
GPIO18

N/A NC

20 A25 SATA1GP_GPIO19 O P1V1_SSB PU

"In Main Power Well.
Muxed with SATA1GP.
Defaults to GPI. If not
used, require a weak pull­up (8.2kohm to 10kohm) to
Vcc3_3"

SATA1GP
(GPI)

GPO

FM_BIOS
_SPI_WP_Nhigh

connect
to WP
pin of
SPI
BIOS
and pull
up P3V3
via

4.75Koh
m

P3V3

BIOS
SPI
flash
write
pro­tected

21 F24 GPIO20_SMI_N O P1V1_SSB PU

"In Main Power Well.
Muxed with SMI#. Defaults
to SMI#. "

SMI_N
(GPO)

GPO

FM_SMI_
ACTIVE_Nhigh

BMC and
pull up
P3V3 via

4.7Kohm

P3V3

SMI
signal

22 J24 SATA0GP_GPIO21 I P1V1_SSB PU

"In Main Power Well.
Muxed with SATA0GP.
Defaults to GPI. If not
used, require a weak pull­up (8.2kohm to 10kohm) to
Vcc3_3"

SATA0GP
(GPI)

GPI

PCIE_SL
OT1_PRE
SENT_N

N/A

Connect
to PCIE
slot1 and
PU to
P3V3 via
10K

P3V3

PCIE
slot1
pres­ent pin

23 F27 SCLOCK_GPIO22 O P1V1_SSB PU

"In Main Power Well.
Muxed with SCLOCK.
Defaults to GPI. If not
used, require a weak pull­up (8.2kohm to 10kohm) to
Vcc3_3"

SCLOCK
(GPI)

GPO

SGPIO_S
ATA_ CLO
CK_R

high

connect
to pin1 of
J1H1 via

49.9 ohm
and pull
up P3V3
via

2.0Kohm

P3V3

SGPIO
CLOCK

24 AR37 LDRQ1_N_GPIO23 I P1V1_SSB NA

"In Main Power Well.
Muxed with LDRQ1#.
Defaults to LDRQ1#. "

LDRQ1_N
(GPI)

GPI

PU_LPC_
LDRQ_N

N/A

pull 10k
to P3V3

P3V3

[1.3.195] GPIO List (Continued)

ITEM PIN #PIN NAME

IO

TYPE

POWER

WELL

PU/PD

V

ENDOR

R

ECOMMENDATIONS

(

REFERENCE DESIGN)

A

LTERNATE

FUNCTION

(D

EFAULT)

USED

FUNCTION

NET

NAME

STATE
AFTER

RESET

NET

CONNECT

TO

ABOUT THE SERVER GPIO LIST

1-63

25 F34 GPIO24 I P3V3_AUX PU

"In Suspend Power Well.
Unmuxed. Defaults to
GPO. This GPIO is not
cleared by a CF9 reset
event."

GPIO24
(GPO)

GPI

FM_PBG_
DYN_SKU
_KEY

high

connect
to pin2 of
JP3
(RAID
Key con­nector)
and pull
up
P3V3_A
UX via
750 ohm

P3V3
_AUX

Upgrad
e KEY

26 J38 GPIO25 O P3V3_AUX PU

"In Suspend Power Well.
Unmuxed. Defaults to
GPO. "

GPIO25
(GPO)

GPO

JTAG_PB
G_PLD_TDIhigh

Connect
to CPLD
TDI

P3V3
_AUX

JTAG

27 F31 GPIO26 O P3V3_AUX PU

"In Suspend Power Well.
Unmuxed. Defaults to
GPO. "

GPIO26
(GPO)

GPO

JTAG_PB
G_PLD_TCKhigh

"1. con­nect to
pin2 of
J1E7
and
JTAG_P
LD_TCK
via a
475ohm(
empty) 2.
Connect
to CPLD
TCK"

P3V3
_AUX

Reserv
ed for
JTAG
for
CPLD
on-line
update

28 M35 GPIO27 O P3V3_AUX PU

"In Deep Sleep Power
Well. Unmuxed. Defaults
to GPI. If not used, require
a weak pull-up (8.2kohm to
10kohm) to VccDSW3_3"

GPIO27
(GPI)

GPO

FP_PWR_
LED_N

high

Connect
to Front
Panel via
a buffer

P3V3
_AUX

Power
LED
control

[1.3.195] GPIO List (Continued)

ITEM PIN #PIN NAME

IO

TYPE

POWER

WELL

PU/PD

V

ENDOR

R

ECOMMENDATIONS

(

REFERENCE DESIGN)

A

LTERNATE

FUNCTION

(D

EFAULT)

USED

FUNCTION

NET

NAME

STATE
AFTER

RESET

NET

CONNECT

TO

ABOUT THE SERVER GPIO LIST

1-64

29 A33 GPIO28 I P3V3_AUX NA

"In Suspend Power Well.
Unmuxed. Defaults to
GPO. "

GPIO28
(GPO)

GPO

FM_PASS
WORD_C
LEAR_N

high

Connect
to 3 pin
header
and PU
to P3V3
via 1K

P3V3
_AUX

PASS­WORD
func­tion

30 H28 SLP_LAN_N_GPIO29 I P3V3_AUX PU

"In Suspend Power Well.
Muxed with SLP_LAN#.
Defaults to GPI. If not
used, require a weak pull­up (8.2kohm to 10kohm) to
VccSus3_3"

SLP_LAN_
N (GPI)

GPI

PU_PBG_
GPIO29

NA

Pull up
P3V3_A
UX via
10Kohm

P3V3
_AUX

31 N38

SUSWARN_N_SUSP

WRDNACK_GPIO30

I P3V3_AUX PU

"In Deep Sleep Power
Well. Muxed with
SUS_PWRDN_ACK/
SUS_WARN#. Defaults to
GPI. If not used, require a
weak pull-up (8.2kohm to
10kohm) to VccDSW3_3"

SUSWARN
_N_SUSPW
RDNACK
(GPI)

GPI

PU_SUS_
WARN_N

high

Pull up
P3V3_A
UX via
10Kohm

P3V3
_AUX

32 K33 GPIO31_MGPIO2 I P3V3_AUX PU

"In Deep Sleep Power
Well. Unmuxed. Defaults
to GPI. If not used, require
a weak pull-up (8.2kohm to
10kohm) to VccDSW3_3"

MGPIO2
(GPI)

GPI

IRQ_SML
1_PMBUS
_ALERT_
N

high

CPU,
BMC,
CPLD,
pin3 of
J1K2
(PMBus
CONN)
and pull
up
P3V3_A
UX via
10Kohm

P3V3
_AUX

PMBus
Alert

[1.3.195] GPIO List (Continued)

ITEM PIN #PIN NAME

IO

TYPE

POWER

WELL

PU/PD

V

ENDOR

R

ECOMMENDATIONS

(

REFERENCE DESIGN)

A

LTERNATE

FUNCTION

(D

EFAULT)

USED

FUNCTION

NET

NAME

STATE
AFTER

RESET

NET

CONNECT

TO

ABOUT THE SERVER GPIO LIST

1-65

33 B24 GPIO32 I P1V1_SSB PU

"In Main Power Well.
Unmuxed. Defaults to
Native. "

GPIO32
(Native)

GPI

PCIE_SL
OT2_PRE
SENT_N

high

Connect
to PCIE
slot2 and
PU to
P3V3 via
10K

PCIE
slot2
pres­ent pin

34 F25 GPIO33 I P1V1_SSB PU

"In Main Power Well.
Unmuxed. Defaults to
GPO."

GPIO33
(GPO)

GPI

TP_PBG_
GPIO33

high

Connect
to PCIE
slot3 and
PU to
P3V3 via
10K

P3V3

PCIE
slot3
pres­ent pin

35 F25 GPIO34 O P1V1_SSB NA

"In Main Power Well.
Muxed with STP_PCI.
Defaults to GPI. If not
used, require a weak pull­up (8.2kohm to 10kohm) to
Vcc3_3"

GPIO34
(GPI)

GPO

FM_VIDE
O_DISAB
LE_N

N/A BMC N/A

BMC
Video
disable

36 B31 GPIO35_NMI_N O P1V1_SSB PU

"In Main Power Well.
Muxed with NMI#. Defaults
to GPO. "

NMI_N
(GPO)

GPO

FM_NMI_
EVENT_N

N/A

BMC,
and pull
up P3V3
via

4.7Kohm

P3V3

SYS­TEM
NMI
EVENT

37 C25 SATA2GP_GPIO36 I P1V1_SSB PU

"In Main Power Well. Can
instead be used as
SATA[3:2]GP. Defaults to
GPI. If not used, require a
weak pull-up (8.2kohm to
10kohm) to Vcc3_3"

SATA2GP GPI

PU_PBG_
GPIO36

high

Pull up
P3V3 via
330Koh
m

P3V3

[1.3.195] GPIO List (Continued)

ITEM PIN #PIN NAME

IO

TYPE

POWER

WELL

PU/PD

V

ENDOR

R

ECOMMENDATIONS

(

REFERENCE DESIGN)

A

LTERNATE

FUNCTION

(D

EFAULT)

USED

FUNCTION

NET

NAME

STATE
AFTER

RESET

NET

CONNECT

TO

ABOUT THE SERVER GPIO LIST

1-66

38 C28 SATA3GP_GPIO37 I P1V1_SSB PU

"In Main Power Well. Can
instead be used as
SATA[3:2]GP. Defaults to
GPI. If not used, require a
weak pull-up (8.2kohm to
10kohm) to Vcc3_3"

SATA3GP
(GPI)

GPI

PU_PBG_
GPIO37

high

Pull up
P3V3 via
330Koh
m

P3V3

39 A30 SLOAD_GPIO38 O P1V1_SSB PU

"In Main Power Well.
Muxed with SLOAD.
Defaults to GPI. If not
used, require a weak pull­up (8.2kohm to 10kohm) to
Vcc3_3"

SATA_LOA
D (GPI)

GPO

SGPIO_S
ATA_ LOA
D_R

high

connect
to pin2 of
J1H1 via

49.9 ohm
and pull
up P3V3
via

2.0Kohm

P3V3

SGPIO
SATA
LOAD

40 K25

SDATAOUT0_GPIO3

9

O P1V1_SSB PU

"In Main Power Well.
Muxed with SDATAOUT0.
Defaults to GPI. If not
used, require a weak pull­up (8.2kohm to 10kohm) to
Vcc3_3"

SATA_DATA
OUT0 (GPI)

GPO

SGPIO_S
ATA_ DATA
OUT0_R

high

connect
to pin4 of
J1H1 via

49.9 ohm
and pull
up P3V3
via

2.0Kohm

P3V3

SGPIO
SATA
DATAO
UT

41 M37 OC1_N_GPIO40 I P3V3_AUX NA

"In Suspend Power Well.
Muxed with OC1#.
Defaults to OC1#. If not
used, require a weak pull­up (8.2kohm to 10kohm) to
VccSus3_3"

OC1_N
(GPI)

GPI

FM_USB_
OC_BP1_NN/A

USB
Fuse

N/A

42 M38 OC2_N_GPIO41 O P3V3_AUX NA

"In Suspend Power Well.
Muxed with OC2#.
Defaults to OC2#. If not
used, require a weak pull­up (8.2kohm to 10kohm) to
VccSus3_3"

OC2_N
(GPI)

GPO

FM_USB_
OC_BP2_NN/A

USB
Fuse

N/A

[1.3.195] GPIO List (Continued)

ITEM PIN #PIN NAME

IO

TYPE

POWER

WELL

PU/PD

V

ENDOR

R

ECOMMENDATIONS

(

REFERENCE DESIGN)

A

LTERNATE

FUNCTION

(D

EFAULT)

USED

FUNCTION

NET

NAME

STATE
AFTER

RESET

NET

CONNECT

TO

ABOUT THE SERVER GPIO LIST

1-67

43 K36 OC3_N_GPIO42 O P3V3_AUX PU

"In Suspend Power Well.
Muxed with OC3#.
Defaults to OC3#. If not
used, require a weak pull­up (8.2kohm to 10kohm) to
VccSus3_3"

OC3_N
(GPI)

GPO

PU_USB_
OC3_N

high

pull up
P3V3_A
UX via
10Kohm

P3V3
_AUX

44 J30 OC4_N_GPIO43 O P3V3_AUX NA

"In Suspend Power Well.
Muxed with OC4#.
Defaults to OC4#. If not
used, require a weak pull­up (8.2kohm to 10kohm) to
VccSus3_3"

OC4_N
(GPI)

GPO

FM_USB_
OC_FP_N

N/A

USB
Fuse

N/A

45 J25 GPIO44 O P3V3_AUX NA

"In Suspend Power Well.
Unmuxed. Defaults to GPI.
If not used, require a weak
pull-up (8.2kohm to
10kohm) to VccSus3_3"

GPIO44
(GPI)

GPI

FM_LAN0
_DISABLE_Nhigh

i350, pull
up 10k to
P3V3_A
UX

P3V3
_AUX

i350
port
disable
control

46 E25 GPIO45 O P3V3_AUX PU

"In Suspend Power Well.
Unmuxed. Defaults to GPI.
If not used, require a weak
pull-up (8.2kohm to
10kohm) to VccSus3_3"

GPIO45
(GPI)

GPI

FM_LAN1
_DISABLE_Nhigh

i350, pull
up 10k to
P3V3_A
UX

P3V3
_AUX

i350
port
disable
control

47 D37 GPIO46 I P3V3_AUX PU

"In Suspend Power Well.
Unmuxed. Defaults to GPI.
If not used, require a weak
pull-up (8.2kohm to
10kohm) to VccSus3_3"

GPIO46
(GPI)

GPI

PU_SSB_
GPIO46

high

pull-up to
P3V3_A
UX via
10Kohm

P3V3
_AUX

48 B32 GPIO47 I P3V3_AUX PU

"In Suspend Power Well.
Unmuxed. Defaults to GPI.
If not used, require a weak
pull-up (8.2kohm to
10kohm) to VccSus3_3"

GPIO47
(GPI)

GPI

BMC_REA
DY_N

high

connect
to BMC
and pull
up to
P3V3_A
UX via

4.7Kohm

P3V3
_AUX

BMC
ready
signal

[1.3.195] GPIO List (Continued)

ITEM PIN #PIN NAME

IO

TYPE

POWER

WELL

PU/PD

V

ENDOR

R

ECOMMENDATIONS

(

REFERENCE DESIGN)

A

LTERNATE

FUNCTION

(D

EFAULT)

USED

FUNCTION

NET

NAME

STATE
AFTER

RESET

NET

CONNECT

TO

ABOUT THE SERVER GPIO LIST

1-68

49 E27

SDATAOUT1_GPIO4

8

O P1V1_SSB PU

"In Main Power Well.
Muxed with SDATAOUT1.
Defaults to GPI. If not
used, require a weak pull­up (8.2kohm to 10kohm) to
Vcc3_3"

SATA_DATA
OUT1 (GPI)

GPI

SGPIO_S
ATA_ DATA
OUT1_R

high

connect
to pin5 of
J1H1 via

49.9ohm
and pull
up P3V3
via

2.0Kohm

P3V3

SGPIO
SATA
DATAO
UT

50 H21 SATA5GP_GPIO49 O P1V1_SSB NA

"In Main Power Well.
Muxed with SATA5GP and
TEMP_ALERT#. Defaults
to GPI. If not used, require
a weak pull-up (8.2kohm to
10kohm) to Vcc3_3"

SATA5GP
(GPI)

GPO

FM_BIOS
_POST_C
MPLT_N

N/A

connect
to BMC
and pull
up to
P3V3 via
10Kohm

N/A

For
BIOS
to indi­cate
POST
status
to
BMC.

51 AR34

REQ1_N_GPIO50_G

SXCLK

I P1V1_SSB PU

"In Main Power Well.
Muxed with REQ1#/GSX­CLK. Defaults to REQ1#. If
not used, require a weak
pull-up (8.2kohm to
10kohm) to Vcc3_3"

REQ1_N/
GSXCLK
(GPI)

GPI

PU_SGPI
O_GSX_CLKN/A

Pull up
P3V3 via

8.25Koh
m

P3V3

52 AU15

GNT_1_N_GPIO51_

GSXDOUT

I P1V1_SSB NA

"In Main Power Well.
Muxed with GNT1#/GSXD­OUT. Defaults to GNT1#.
Do not pull low."

GNT1_N/
GSX_DOUT
(GPO)

GPI

TP_SGPI
O_GSX_D
OUT

N/A TP

53 AK34

REQ2_N_GPIO52_G

SXLOAD

I P1V1_SSB PU

"In Main Power Well.
Muxed with REQ2#/GSXS­LOAD. Defaults to REQ2#.
If not used, require a weak
pull-up (8.2kohm to
10kohm) to Vcc3_3"

REQ2_N/
GSX_LOAD
(GPI)

GPI

PU_SGPI
O_GSX_L
OAD

N/A

Pull up
P3V3 via

8.25Koh
m

P3V3

[1.3.195] GPIO List (Continued)

ITEM PIN #PIN NAME

IO

TYPE

POWER

WELL

PU/PD

V

ENDOR

R

ECOMMENDATIONS

(

REFERENCE DESIGN)

A

LTERNATE

FUNCTION

(D

EFAULT)

USED

FUNCTION

NET

NAME

STATE
AFTER

RESET

NET

CONNECT

TO

ABOUT THE SERVER GPIO LIST

1-69

54 AJ34

GNT_2_N_GPIO53_

GSXDIN

I P1V1_SSB PD

"In Main Power Well.
Muxed with GNT2#/GSX­DIN. Defaults to GNT2#. "

GNT2_N/
GSX_DIN
(GPO)

GPI

SGPIO_M
UX_GSX_
DIN

N/A

Pull
down
1Kohm

N/A

55 AK21

REQ3_N_GPIO54_G

SXSRESET_N

I P1V1_SSB PU

"In Main Power Well.
Muxed with REQ3#/
GSXRESET. Defaults to
REQ3#. If not used,
require a weak pull-up
(8.2kohm to 10kohm) to
Vcc3_3"

REQ3_N/
GSX_SRES
ET (GPI)

GPI

PU_SGPI
O_GSX_R
ESET

high

Pull up
P3V3 via

8.25Koh
m

P3V3

56 AF30 GNT_3_N_GPIO55 I P1V1_SSB PU

"In Main Power Well.
Muxed with GNT3#.
Defaults to GNT3#. "

GNT3_N
(GPO)

GPI

FM_BIOS
_RCVR_B
OOT_N

NC

Connect
to 3 pin
header
and PU
to P3V3
via 10K

BIOS
recov­ery
func­tion

57 H27 GPIO56 I P3V3_AUX PU

"In Suspend Power Well.
Unmuxed. Defaults to GPI.
"

GPIO56
(GPI)

GPI

JTAG_PB
G_PLD_TDOhigh

connect
to PLD
via a
0hm and
pull up
P3V3_A
UX via
10Kohm

P3V3
_AUX

Reserv
ed for
JTAG
for
CPLD
on-line
update

[1.3.195] GPIO List (Continued)

ITEM PIN #PIN NAME

IO

TYPE

POWER

WELL

PU/PD

V

ENDOR

R

ECOMMENDATIONS

(

REFERENCE DESIGN)

A

LTERNATE

FUNCTION

(D

EFAULT)

USED

FUNCTION

NET

NAME

STATE
AFTER

RESET

NET

CONNECT

TO

ABOUT THE SERVER GPIO LIST

1-70

58 J27 GPIO57 I P3V3_AUX PU

"In Suspend Power Well.
Unmuxed. Defaults to GPI.
"

ME_RCVR_
N (GPI)

GPI

FM_ME_R
CVR_N

high

pin2 of
J1J3
(ME
FIRM­WARE
UPDATE
HEADER
) and Pull
up
P3V3_A
UX via
10Kohm

P3V3
_AUX

59 K34 SML1CLK_GPIO58 O P3V3_AUX PU

"In Suspend Power Well.
Muxed with SML1CLK#.
Defaults to SML1CLK#. "

SML1CLK
(GPO)

GPO

SMB_PM
BUS_CLK

high

BMC,
pin1 of
J1K2
(SSI
PSU
AUX
CONN)
and Pull
up
P3V3_A
UX via

3.32Koh
m

P3V3
_AUX

PMBus
CLK

60 H34 OC0_N_GPIO59 I P3V3_AUX

"In Suspend Power Well.
Muxed with OC0#.
Defaults to OC0#. If not
used, require a weak pull­up (8.2kohm to 10kohm) to
Vcc3_3"

OC0_N
(GPI)

GPI

FM_USB_
OC_INT_NN/A

USB
Fuse

N/A

61 H34

SML0ALERT_N_GPI

O60

I P3V3_AUX PU

"In Suspend Power Well.
Muxed with SML0ALERT#.
Defaults to SML0ALERT#.
"

SML0_ALE
RT (GPI)

GPI

IRQ_SML
0_ALERT_Nhigh

BMC,
pull up
10k to
P3V3_A
UX

P3V3
_AUX

SMLink
0 Alert

[1.3.195] GPIO List (Continued)

ITEM PIN #PIN NAME

IO

TYPE

POWER

WELL

PU/PD

V

ENDOR

R

ECOMMENDATIONS

(

REFERENCE DESIGN)

A

LTERNATE

FUNCTION

(D

EFAULT)

USED

FUNCTION

NET

NAME

STATE
AFTER

RESET

NET

CONNECT

TO

ABOUT THE SERVER GPIO LIST

1-71

62 E36

SUS_STAT_N_GPIO

61

O P3V3_AUX NA

"In Suspend Power Well.
Muxed with SUS_STAT#.
Defaults to SUS_STAT#. "

SUS_STAT_
N (GPO)

GPO

FM_RISE
R_ID3_R3

high

connect
to PCIE
SLOT5
and
SLOT6
and pull
up 4.75k
to
P3V3_A
UX

Reserv
ed for
JTAG
for
CPLD
on-line
update

63 C35 SUSCLK_GPIO62 O P3V3_AUX NA

"In Suspend Power Well.
Muxed with SUSCLK.
Defaults to SUSCLK. "

SUSCLK
(GPO)

GPO

CLK_33K_
SUSCLK_
PLD

N/A

CPLD
via a
10ohm
resistor

N/A

CLK to
PLD

64 B35 SLP_S5_N_GPIO63 O P3V3_AUX NA

"In Suspend Power Well.
Muxed with SLP_S5#.
Defaults to SLP_S5#. "

SLPS5_N
(GPO)

GPO

FM_SLPS
5_N

N/A

connect
to BMC
and
NCT301
2S

N/A

S5
Sleep
Control

65 AL16 GPIO64 I P1V1_SSB PU

"In Core Power Well.
Unmuxed. Defaults to
GPO. "

GPIO64
(GPO)

GPO

FM_RISE
R_ID0

high

connect
to Slot2
and pull
up P3V3
via
1Kohm

P3V3

PCIE
slot6
riser

66 AK16 GPIO65 I P1V1_SSB NA

"In Core Power Well.
Unmuxed. Defaults to
GPO. "

GPIO65
(GPO)

GPO

FM_RISE
R_ID1

N/A

connect
to Slot6
and pull
up P3V3
via
1Kohm

P3V3

PCIE
slot6
riser

[1.3.195] GPIO List (Continued)

ITEM PIN #PIN NAME

IO

TYPE

POWER

WELL

PU/PD

V

ENDOR

R

ECOMMENDATIONS

(

REFERENCE DESIGN)

A

LTERNATE

FUNCTION

(D

EFAULT)

USED

FUNCTION

NET

NAME

STATE
AFTER

RESET

NET

CONNECT

TO

ABOUT THE SERVER GPIO LIST

1-72

67 AL15 GPIO66 I P1V1_SSB NA

"In Core Power Well.
Unmuxed. Defaults to
GPO. "

GPIO66
(GPO)

GPO

FM_RISE
R_ID2

high

connect
to
Slot5and
Slot6
and pull
up P3V3
via
1Kohm

P3V3

PCIE
slot6
riser

68 AK15 GPIO67 I P1V1_SSB NA

"In Core Power Well.
Unmuxed. Defaults to
GPO. "

GPIO67
(GPO)

GPO

FW_1394
_DISABLE
_N

Board
1394 dis­able pin

P3V3

1394
disable
pin

69 AG34 TACH4_GPIO68 I P1V1_SSB PU

"In Core Power Well.
Muxed with TACH4.
Defaults to GPI. If not
used, require a weak pull­up (8.2kohm to 10kohm) to
Vcc3_3"

TACH4
(GPI)

GPI

BOARD_R
EVISION1

high

PU to
P3V3 via
10K (NI)
and PD
via 10K

P3V3

board
revi­sion ID

70 Y32 TACH5_GPIO69 I P1V1_SSB PU

"In Core Power Well.
Muxed with TACH5.
Defaults to GPI. If not
used, require a weak pull­up (8.2kohm to 10kohm) to
Vcc3_3"

TACH5
(GPI)

GPI

"PCIE_SL
OT4_PRE
SENT_N"

high

Connect
to PCIE
slot4 and
PU to
P3V3 via
10K

P3V3

PCIE
slot4
pres­ent pin

71 AF34 TACH6_GPIO70 I P1V1_SSB PU

"In Core Power Well.
Muxed with TACH6.
Defaults to GPI. If not
used, require a weak pull­up (8.2kohm to 10kohm) to
Vcc3_3"

TACH6
(GPI)

GPI

PCIE_SL
OT5_PRE
SENT_N

high

Connect
to PCIE
slot5 and
PU to
P3V3 via
10K

P3V3

PCIE
slot5
pres­ent pin

[1.3.195] GPIO List (Continued)

ITEM PIN #PIN NAME

IO

TYPE

POWER

WELL

PU/PD

V

ENDOR

R

ECOMMENDATIONS

(

REFERENCE DESIGN)

A

LTERNATE

FUNCTION

(D

EFAULT)

USED

FUNCTION

NET

NAME

STATE
AFTER

RESET

NET

CONNECT

TO

ABOUT THE SERVER GPIO LIST

1-73

72 AM36 TACH7_GPIO71 I P1V1_SSB PU

"In Core Power Well.
Muxed with TACH7.
Defaults to GPI. If not
used, require a weak pull­up (8.2kohm to 10kohm) to
Vcc3_3"

TACH7
(GPI)

GPI

PCIE_SL
OT6_PRE
SENT_N

high

Connect
to PCIE
slot6 and
PU to
P3V3 via
10K

P3V3

PCIE
slot6
pres­ent pin

73 E38 GPIO72 O P3V3_AUX PU

"In Suspend Power Well.
Unmuxed. Defaults to
Native. If not used, require
a weak pull-up (8.2kohm to
10kohm) to VccSus3_3"

GPIO72
(Native)

Native

FM_LOM_
DEV_OFF_Nhigh

i350, and
Pull up
P3V3_A
UX via
10Kohm
(empty)

P3V3
_AUX

i350
LAN
device
control

74 B33 GPIO73 I P3V3_AUX PU

"In Suspend Power Well.
Unmuxed. Defaults to GPI.
If not used, require a weak
pull-up (8.2kohm to
10kohm) to VccSus3_3"

GPIO73
(GPI)

GPI

JTAG_PB
G_PLD_TMShigh

connect
to PLD
via a
0hm

P3V3
_AUX

Reserv
ed for
JTAG
for
CPLD
on-line
update

75 J33

SML1ALERT_N_PCH

HOT_N_GPIO74

O P3V3_AUX PU

"In Suspend Power Well.
Muxed with SML1ALERT#/
PCHHOT#. Defaults to
Native. "

SML1ALER
T_N\PCHH
OT_N
(Native)

GPO

FM_SSB_I
BMC_THE
RMTRIP_
N

high

BMC and
pull up
P3V3_A
UX via
10Kohm

P3V3
_AUX

PCH
HOT
indicate

[1.3.195] GPIO List (Continued)

ITEM PIN #PIN NAME

IO

TYPE

POWER

WELL

PU/PD

V

ENDOR

R

ECOMMENDATIONS

(

REFERENCE DESIGN)

A

LTERNATE

FUNCTION

(D

EFAULT)

USED

FUNCTION

NET

NAME

STATE
AFTER

RESET

NET

CONNECT

TO

ABOUT THE SERVER GPIO LIST

1-74

76 K39 SML1DATA_GPIO75 I/O P3V3_AUX PU

"In Suspend Power Well.
Muxed with SML1DATA.
Defaults to SML1DATA. If
not used, require a weak
pull-up (8.2kohm to
10kohm) to Vcc3_3"

SML1DATA
(GPIO)

GPIO

SMB_PM
BUS_DATAhigh

BMC,
pin2 of
J2J9
(SSI
PSU
AUX
CONN)
and Pull
up
P3V3_A
UX via

4.7Kohm

P3V3
_AUX

PMBus
DATA

[1.3.195] GPIO List (Continued)

ITEM PIN #PIN NAME

IO

TYPE

POWER

WELL

PU/PD

V

ENDOR

R

ECOMMENDATIONS

(

REFERENCE DESIGN)

A

LTERNATE

FUNCTION

(D

EFAULT)

USED

FUNCTION

NET

NAME

STATE
AFTER

RESET

NET

CONNECT

TO

ABOUT THE SERVER BASEBOARD SKU AND REVISION ID

1-75

[1.3.196] Baseboard SKU and Revision ID

[1.3.197] On the Romley Product design a copy of the base­board SKU and revision ID’s is stored in BIOS and FW flash
devices without any HW strapping requirements. Thurley was
the first platform to implement board SKU and revision ID in the
BIOS and firmware SPI flash devices. Historically, SKU and
revision ID’s were strapped by HW and read by BIOS via
GPIO’s.

[1.3.198] Product BIOS uses the Platform Data Region of the
SPI flash to store the 3-bit SKU and 3-bit revision ID’s. These
IDs reside in the PIT (Platform Interface Table), along with
UUID, and is only programmable when in manufacturing mode.
Firmware uses a location in the Boot Block of the SPI flash to
store the 3-bit SKU and 2-bit revision ID’s. Since SKU and revi­sion ID’s are programmed in a secure region in the BIOS flash,
BIOS is required to update a byte in an BMC Mailbox register
during each boot to ensure that Firmware has the most current
copy of the ID’s in case the Firmware Boot Block is corrupted,
or the Firmware Boot Block is being updated.