Quanta U83 Discrete Ultra, Pavilion 15 Schematic
5
4
3
2
1
U83 DIS (14"/15.6")
D D
C C
System BIOS
SPI ROM
B B
Intel Shark Bay ULT Platform Block Diagram
DDR3L SODIMM1
Maxima 8GBs
PAGE 12
DDR3L SODIMM2
Maxima 8GBs
PAGE 13
SATA - 1st HDD
Package : 9.5 (mm)
Power :
mSATA
Package : 12.7 (mm)
Power :
SATA ODD
Package : (mm)
Power :
PAGE 7
PAGE 24
PAGE 24
PAGE 24
DDR3L
DDR3L
SATA0 6GB/s
SATA1 6GB/s
SATA2 6GB/s
SPI Interface
Intel Shark Bay ULT
Processor : Daul Core
Power : 15 (Watt)
Package : BGA1168
Size : 40 X 24 (mm)
ICT
PAGE 2~10
Azalia
PCI-E Gen3
X4 Lane
eDP X1
DP Port 1
USB3.0 Interface
USB2.0 Interface
USB2.0 Port x 1(Left side)
Port1 Port2
PCIE Gen 1 x 1 LaneLPC Interface
PAGE 21
Ultra/Slim
AMD Sun XT
Power : 25 (Watt)
Package : S3
Size : 23 x 23 (mm)
PAGE 14-18
USB 3.0 Port 1,2(USB 2.0 Port 0,5)
Camera
PAGE 20
VRAM DDR3 x 4 (900 MHz)
128 x 16 x 4, 64 bit
256 x 16 x 4, 64 bit
Max 1GBs PAGE 19
27MHz
PAGE 16
RTD2132R
Package : QFN-32
PAGE 19
PCB 6L STACK UP
LAYER 1 : TOP
LAYER 2 : SGND
LAYER 3 : IN1(High)
LAYER 4 : IN2(Low)
LAYER 5 : SVCC
LAYER 6 : BOT
LVDS (1CH)
PAGE 20
eDP
PAGE 20
HDMI Conn
PAGE 20
USB3.0 Port x 2
PAGE 25
01
G-Sensor
HP3DC2TR
Keyboard
Touch Pad
PAGE 26
PAGE 25
SM BUS
EnE KB9010QF A1
Embedded Controller
Power :
Package : LQPF128
Size : 14 x 14 (mm)
PAGE 27
Audio Codec
ALC3227-GR
Power :
Package : MQFN
Size : 6 x 6 (mm)
PAGE 21
Card Reader
RTS5237-GR
Power :
Package : LQPF48
Size : 7 x 7 (mm)
PAGE 23
LAN Controller
10/100 RTL8176EH-CG
Power :
Package : OFN48
Size : 6 x 6 (mm)
Int
PAGE 22
Halt Mini Card
Intel Rambo Peak
WLAN / BT Combo
PAGE 26
TCP-15G24
PAGE 24 FAN
Speaker
PAGE 24
PAGE 21
Combo Jack
A A
5
4
iPHONE type
Digital MIC
PAGE 21
PAGE 21
PROJECT :U83
PROJECT :U83
PROJECT :U83
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Block Diagram
Block Diagram
Block Diagram
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
1
1A
1A
1A
1 41Monday, March 18, 2013
1 41Monday, March 18, 2013
1 41Monday, March 18, 2013
5
4
3
2
1
U19A
IN_D2#<21>
IN_D1#<21>
IN_D0#<21>
IN_CLK#<21>
IN_D2<21>
IN_D1<21>
IN_D0<21>
D D
eDP_COMPIO and ICOMPO signals should be shorted
near balls and routed with typical impedance <25 mohms
C C
IN_CLK<21>
EDP_DISP_UTIL<6>
INT_eDP_AUXP<20>
INT_eDP_AUXN<20>
INT_eDP_TXP0<20>
INT_eDP_TXN0<20>
DPB_LANE0_N
DPB_LANE1_N
DPB_LANE2_N
DPB_LANE3_N
DPB_LANE0_P
DPB_LANE1_P
DPB_LANE2_P
DPB_LANE3_P
eDP_RCOMP
EDP_DISP_UTIL
INT_eDP_AUXP
INT_eDP_AUXN
INT_eDP_TXP0
INT_eDP_TXN0
+VCCIOA_OUT
eDP_COMPIO and ICOMPO signals should be shorted
near balls and routed with typical impedance <25 mohms
C54
DDI1_TXN0
B58
DDI1_TXN1
B55
DDI1_TXN2
A57
DDI1_TXN3
C55
DDI1_TXP0
C58
DDI1_TXP1
A55
DDI1_TXP2
B57
DDI1_TXP3
C51
DDI2_TXN0
C53
DDI2_TXN1
C49
DDI2_TXN2
A53
DDI2_TXN3
C50
DDI2_TXP0
B54
DDI2_TXP1
B50
DDI2_TXP2
B53
DDI2_TXP3
D20
EDP_RCOMP
A43
EDP_DISP_UTIL
B45
EDP_AUXP
A45
EDP_AUXN
B46
eDP_TXP0
B47
eDP_TXP1
C46
eDP_TXP2
B49
eDP_TXP3
C45
eDP_TXN0
A47
eDP_TXN1
C47
eDP_TXN2
A49
eDP_TXN3
*HSW_ULT_DDR3L
R109 24.9/F_4
eDP_RCOMP
EC_PECI<28>
H_PROCHOT#<28,33>
eDP
R415 56.2/F_4
TP86
PCI EXPRESS* - GRAPHICS
TP89
TP91
R397 10K/F_4
PROC_DETECT#
CATERR#
EC_PECI
PROCHOT#
PROCPWRGD
U19B
D61
PROC_DETECT#
K61
CATERR#
N62
PECI
K63
PROCHOT#
C61
PROCPWRGD
*HSW_ULT_DDR3L
02
MISCTHERMALPWR MANAGEMENT
AV15
DDR3JTAG & BPM
SM_DRAMRST#
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
SM_PG_CNTL1
PRDY#
PREQ#
PROC_TCK
PROC_TMS
PROC_TRST#
PROC_TDI
PROC_TDO
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7
AU60
AV60
AU61
AV61
J62
K62
E60
E61
E59
F63
F62
J60
H60
H61
H62
K59
H63
K60
J61
SM_DRAMRST#
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
XDP_TCK0
XDP_TMS_CPU
XDP_TRST#_CPU
XDP_TDI_CPU
XDP_TDO_CPU
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7
R184 0_4
R527 200/F_4
R528 121/F_4
R526 100/F_4
+1.35VSUS
R183
470_4
DDR_PG_CNTL <13>
TP21
XDP_PRDY#_CPU <11>
XDP_PREQ#_CPU <11>
TP25
XDP_TCK0 <11>
XDP_TMS_CPU <11>
XDP_TRST#_CPU <7,11>
XDP_TDI_CPU <11>
XDP_TDO_CPU <11>
XDP_BPM0 <11>
XDP_BPM1 <11>
TP90
TP17
TP24
TP20
TP28
TP22
DDR3_DRAMRST# <12,13>
Processor pull-up (CPU)
H_PROCHOT#
XDP_TDO_CPU
B B
DEL or not?
XDP_TMS_CPU
XDP_TDI_CPU
R419 62_4
+V1.05S_VCCST
R411 51_4
R410 *51_4
R412 *51_4
+V1.05S_VCCST
XDP_TRST#_CPU
XDP_TCK0
A A
5
4
3
R539 *51_4
R101 51_4
PROJECT :U83
PROJECT :U83
PROJECT :U83
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
ULT 1/9(eDP/DDI)
ULT 1/9(eDP/DDI)
ULT 1/9(eDP/DDI)
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
1
1A
1A
1A
2 41Thursday, March 14, 2013
2 41Thursday, March 14, 2013
2 41Thursday, March 14, 2013
5
M_A_DQ[63:0]<12>
M_B_DQ[63:0]<13>
M_A_DQSN[7:0]<12>
M_A_DQSP[7:0]<12>
M_B_DQSN[7:0]<13>
M_B_DQSP[7:0]<13>
4
3
2
1
03
Haswell ULT Processor (DDR3L)
D D
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
C C
B B
M_A_BS#0<12>
M_A_BS#1<12>
M_A_BS#2<12>
M_A_CAS#<12>
M_A_RAS#<12>
M_A_WE#<12>
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
AH62
AK63
AK62
AH61
AH60
AK61
AK60
AM63
AM62
AP63
AP62
AM61
AM60
AP61
AP60
AP58
AR58
AM57
AK57
AL58
AK58
AR57
AN57
AP55
AR55
AM54
AK54
AL55
AK55
AR54
AN54
AY58
AW58
AY56
AW56
AV58
AU58
AV56
AU56
AY54
AW54
AY52
AW52
AV54
AU54
AV52
AU52
AK40
AK42
AM43
AM45
AK45
AK43
AM40
AM42
AM46
AK46
AM49
AK49
AM48
AK48
AM51
AK51
AU35
AV35
AY41
AU34
AY34
AW34
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
SA_BA0
SA_BA1
SA_BA2
SA_CAS#
SA_RAS#
SA_WE#
*HSW_ULT_DDR3L
DDR SYSTEM MEMORY A
SA_CLK0
SA_CLK#0
SA_CKE0
SA_CLK1
SA_CLK#1
SA_CKE1
SA_CKE2
SA_CKE3
SA_CS#0
SA_CS#1
SA_ODT0
SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7
SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
SM_VREF_CA
SM_VREF_DQ0
SM_VREF_DQ1
AV37
AU37
AU43
AY36
AW36
AW43
AY42
AY43
AP33
AR32
AP32
AJ61
M_A_DQSN0
AN62
M_A_DQSN1
AM58
M_B_DQSN0
AM55
M_B_DQSN1
AV57
M_A_DQSN2
AV53
M_A_DQSN3
AL43
M_B_DQSN2
AL48
M_B_DQSN3
AJ62
M_A_DQSP0
AN61
M_A_DQSP1
AN58
M_B_DQSP0
AN55
M_B_DQSP1
AW57
M_A_DQSP2
AW53
M_A_DQSP3
AL42
M_B_DQSP2
AL49
M_B_DQSP3
AU36
M_A_A0
AY37
M_A_A1
AR38
M_A_A2
AP36
M_A_A3
AU39
M_A_A4
AR36
M_A_A5
AV40
M_A_A6
AW39
M_A_A7
AY39
M_A_A8
AU40
M_A_A9
AP35
M_A_A10
AW41
M_A_A11
AU41
M_A_A12
AR35
M_A_A13
AV42
M_A_A14
AU42
M_A_A15
AP49
SM_VREF
AR51
SMDDR_VREF_DQ0_M3
AP51
SMDDR_VREF_DQ1_M3
20mils width
M_A_CLKP0 <12>
M_A_CLKN0 <12>
M_A_CKE0 <12>
M_A_CLKP1 <12>
M_A_CLKN1 <12>
M_A_CKE1 <12>
M_A_CS#0 <12>
M_A_CS#1 <12>
TP61
M_A_A[15:0] <12>
SM_VREF <12>
SMDDR_VREF_DQ0_M3 <12>
SMDDR_VREF_DQ1_M3 <13>
M_B_BS#0<13>
M_B_BS#1<13>
M_B_BS#2<13>
M_B_CAS#<13>
M_B_RAS#<13>
M_B_WE#<13>
U19C
AH63
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
AY31
AW31
AY29
AW29
AV31
AU31
AV29
AU29
AY27
AW27
AY25
AW25
AV27
AU27
AV25
AU25
AM29
AK29
AL28
AK28
AR29
AN29
AR28
AP28
AN26
AR26
AR25
AP25
AK26
AM26
AK25
AL25
AY23
AW23
AY21
AW21
AV23
AU23
AV21
AU21
AY19
AW19
AY17
AW17
AV19
AU19
AV17
AU17
AR21
AR22
AL21
AM22
AN22
AP21
AK21
AK22
AN20
AR20
AK18
AL18
AK20
AM20
AR18
AP18
AL35
AM36
AU49
AM33
AM35
AK35
U19D
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
SB_BA0
SB_BA1
SB_BA2
SB_CAS#
SB_RAS#
SB_WE#
ICT
*HSW_ULT_DDR3L
AN38
SB_CLK0
AM38
SB_CLK#0
AY49
SB_CKE0
AL38
SB_CLK1
AK38
SB_CLK#1
AU50
SB_CKE1
AW49
SB_CKE2
AV50
SB_CKE3
AM32
SB_CS#0
AK32
SB_CS#1
AL32
SB_ODT0
AW30
AV26
AN28
AN25
AW22
AV18
AN21
AN18
AV30
AW26
AM28
AM25
AV22
AW18
AM21
AM18
AP40
AR40
AP42
AR42
AR45
AP45
AW46
AY46
AY47
AU46
AK36
AV47
AU47
AK33
AR46
AP46
M_A_DQSN4
M_A_DQSN5
M_B_DQSN4
M_B_DQSN5
M_A_DQSN6
M_A_DQSN7
M_B_DQSN6
M_B_DQSN7
M_A_DQSP4
M_A_DQSP5
M_B_DQSP4
M_B_DQSP5
M_A_DQSP6
M_A_DQSP7
M_B_DQSP6
M_B_DQSP7
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7
SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7
SB_MA0
SB_MA1
SB_MA2
SB_MA3
DDR SYSTEM MEMORY B
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
M_B_CLKP0 <13>
M_B_CLKN0 <13>
M_B_CKE0 <13>
M_B_CLKP1 <13>
M_B_CLKN1 <13>
M_B_CKE1 <13>
M_B_CS#0 <13>
M_B_CS#1 <13>
TP59
M_B_A[15:0] <13>
A A
PROJECT :U83
PROJECT :U83
PROJECT :U83
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
ULT 2/9 (DDR3 I/F)
ULT 2/9 (DDR3 I/F)
ULT 2/9 (DDR3 I/F)
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
1
1A
1A
1A
3 41Monday, March 18, 2013
3 41Monday, March 18, 2013
3 41Monday, March 18, 2013
5
32A
+VCC_CORE
C224
C469
22U/6.3VT_8
22U/6.3VT_8
D D
C234
22U/6.3VT_8
C223
22U/6.3VT_8
C212
22U/6.3VT_8
C236
22U/6.3VT_8
C245
22U/6.3VT_8
C C
C178
22U/6.3VT_8
C486
*22U/6.3VS_8
B B
A A
22U/6.3VT_8
C199
22U/6.3VT_8
C214
22U/6.3VT_8
22U/6.3VT_8
C237
22U/6.3VT_8
22U/6.3VT_8
C213
22U/6.3VT_8
22U/6.3VT_8
C187
22U/6.3VT_8
22U/6.3VT_8
C179
22U/6.3VT_8
22U/6.3VT_8
C467
*22U/6.3VS_8
+VCCIOA_OUT <2>
+VCCIO_OUT <6>
+1.5V <10,22,25,27,31>
+1.35VSUS <2,12,13,25,32>
+1.05V <7,10,11,27,28,31,34>
+VCC_CORE <33>
C221
C222
22U/6.3VT_8
C235
C475
C200
C198
C182
C468
*22U/6.3VS_8
C201
22U/6.3VT_8
C471
22U/6.3VT_8
C466
22U/6.3VT_8
C492
22U/6.3VT_8
C211
22U/6.3VT_8
C502
*22U/6.3VS_8
5
U19F
C36
C40
C44
C48
C52
C56
E23
E25
E27
E29
E31
E33
E35
E37
E39
E41
E43
E45
E47
E49
E51
E53
E55
E57
F24
F28
F32
F36
F40
F44
F48
F52
F56
G23
G25
G27
G29
G31
G33
G35
G37
G39
G41
G43
G45
G47
G49
G51
G53
G55
G57
H23
J23
K23
K57
L22
M23
M57
P57
U57
W57
AB57
AD57
AG57
C24
C28
C32
F59
L59
J58
N58
AC58
AB23
AD23
AA23
AE59
AT2
AU44
AV44
D15
F22
H22
J21
N23
R23
T23
U10
AL1
AM11
AP7
AU10
AU15
*HSW_ULT_DDR3L
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
POWER
HSW ULT POWER
PWR_DEBUG#
VCCST_PWRGD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VCCIO_OUT
VCCIOA_OUT
VIDALERT#
VIDSCLK
VIDSOUT
VR_EN
VR_READY
VCCST
VCCST
VCCST
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
VCC_SENSE
VSS_SENSE
RSVD
RSVD
VSS
VSS
4
1.4A
+1.35VSUS
C561
10U/6.3V_6
C550
2.2U/6.3V_4
R458 *0_8
R105 0_4
R399 0_4
+VCC_CORE
VCC_SENSE <33>
VSS_SENSE <33>
Close to CPU
C559
10U/6.3V_6
IMVP_PWRGD_R
AH26
AJ31
AJ33
AJ37
C560
AN33
10U/6.3V_6
AP43
AR48
AY35
AY40
AY44
Direct tie to CPU VCC/VSS-Ball
AY50
C552
2.2U/6.3V_4
D63
P62
T59
AD60
AD59
AA59
AE60
AC59
AG58
U59
V59
A59
E20
L62
H_CPU_SVIDALRT#
N63
VR_SVID_CLK
L63
H_CPU_SVIDDAT
H59
PWR_DEBUG
F60
C59
R398 10K_4
AC22
AE22
AE23
B59
P60
P61
N59
N61
E63
E62
AW14
AY14
+V1.05S_VCCST
H_VCCST_PWRGD_R
TP44
TP40
TP32
TP38
R408 100/F_4
R413 100/F_4
TP111
TP110
100- ±1% pull-up to VCC near processor.
Processor Strapping
CFG3
(Physcial Debug Enable)
DFX Privacy
CFG4
(DP Presence Strap)
4
3
CFG0-19 need Reserve TP
CFG0<11>
CFG1<11>
CFG2<11>
CFG3<11>
+V1.05S_VCCST
R431
75/F_4
C518 *0.1U/10V_4
+V1.05S_VCCST
Place PU resistor
close to VR
R414
130/F_4
CFG4<11>
CFG5<11>
CFG6<11>
CFG7<11>
CFG8<11>
CFG9<11>
CFG10<11>
CFG11<11>
CFG12<11>
CFG13<11>
CFG14<11>
CFG15<11>
CFG16<11>
CFG17<11>
CFG18<11>
CFG19<11>
+V1.05S_VCCST
R402
10K_4
C508
*10P/50V_4
C562
10U/6.3V_6
C554
2.2U/6.3V_4
+VCCIO_OUT+1.05V
C516
4.7U/6.3V_6
+VCCIO_OUT
+VCCIOA_OUT
TP14
D1 *RB501V-40
2 1
H_VCCST_PWRGD
C551
2.2U/6.3V_4
PWR_DEBUG <11>
H_VR_ENABLE_MCP <33>
C563
C556
10U/6.3V_6
10U/6.3V_6
IMVP_PWRGD_R <28>
IMVP_PWRGD <6,33>
Layout note: need routing
together and ALERT need
between CLK and DATA.
H_CPU_SVIDALRT#
VR_SVID_CLK
H_CPU_SVIDDAT
HWPG<11,28,30,31,32> H_VCCST_PWRGD <11>
R422 43_4
R421 *0_4/S
21
D14 RB501V-40
The CFG signals have a default value of '1' if not terminated on the board.
1 0
Disable: Enable: Set DFX Enable in DFX interface MSR
Disable; No physical DP attached to eDP
Enable; An ext DP device is connected to eDP
3
SVID ALERT
VR_SVID_ALERT# <33>
SVID CLK
VR_SVID_CLK <33>
SVID DATA
VR_SVID_DATA <33>
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG3
CFG4
TP53
TP51
TP63
TP96
TP58
TP48
TP54
TP41
TP35
TP34
TP49
TP43
TP36
TP31
TP30
TP42
TP16
TP15
TP37
TP39
2
TP88
TP87
2
TP108
TP104
R448
CFG_RCOMP
49.9/F_4
TD_IREF
R385
8.2K/F_4
Circuit
R452 *1K_4
R143 1K_4
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
U19E
AC60
AC62
AC63
AA63
AA60
Y62
Y61
Y60
V62
V61
V60
U60
T63
T62
T61
T60
AA62
AA61
U63
U62
V63
A5
E1
D1
J20
H18
B12
AV63
AU63
C63
C62
B43
*HSW_ULT_DDR3L
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG_RCOMP
RSVD
RSVD
RSVD
RSVD
RSVD
TD_IREF
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
PROC_OPI_RCOMP
RESERVED
IO Thrm Protect
+3VPCU
For 65 degree, 1.8v limit, (SW)
R78
16.5K/F_4
R76
3.3K/F_4
For 75 degree, 1.2v limit, (HW)
R509
0_4
THER_CPU
R504
100K_4 NTC
+V1.05S_VCCST+1.05V
R459 0_8
+V1.05S_VCCST
1
A51
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
C145
0.1U/10V_4
1 2
C135
0.1U/10V_4
1 2
C514
*1U/6.3V_4
R401
150/F_4
PWR_DEBUG
R400
*10K_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
TP80
B51
TP83
L60
TP27
N60
W23
Y22
AY15
PROC_OPI_RCOMP
AV62
R523
D58
49.9/F_4
P22
VSS
N21
VSS
P20
R20
THRM_MOINTOR <28>
THRM_MOINTOR1 <28>
C513
*22U/6.3V_8
PROJECT :U83
PROJECT :U83
PROJECT :U83
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
04 -- ULT 3/9 (POWER-1)
04 -- ULT 3/9 (POWER-1)
04 -- ULT 3/9 (POWER-1)
1
04
1A
1A
1A
4 41Thursday, March 14, 2013
4 41Thursday, March 14, 2013
4 41Thursday, March 14, 2013
5
U19G
A11
VSS
A14
VSS
A18
VSS
A24
VSS
A28
VSS
A32
VSS
A36
VSS
A40
VSS
A44
VSS
A48
D D
C C
B B
VSS
A52
VSS
A56
VSS
AA1
VSS
AA58
VSS
AB10
VSS
AB20
VSS
AB22
VSS
AB7
VSS
AC61
VSS
AD21
VSS
AD3
VSS
AD63
VSS
AE10
VSS
AE5
VSS
AE58
VSS
AF11
VSS
AF12
VSS
AF14
VSS
AF15
VSS
AF17
VSS
AF18
VSS
AG1
VSS
AG11
VSS
AG21
VSS
AG23
VSS
AG60
VSS
AG61
VSS
AG62
VSS
AG63
VSS
AH17
VSS
AH19
VSS
AH20
VSS
AH22
VSS
AH24
VSS
AH28
VSS
AH30
VSS
AH32
VSS
AH34
VSS
AH36
VSS
AH38
VSS
AH40
VSS
AH42
VSS
AH44
VSS
AH49
VSS
AH51
VSS
AH53
VSS
AH55
VSS
AH57
VSS
AJ13
VSS
AJ14
VSS
AJ23
VSS
AJ25
VSS
AJ27
VSS
AJ29
VSS
*HSW_ULT_DDR3L
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AP10
AP17
AP20
4
U19H
AP22
VSS
AP23
VSS
AP26
VSS
AP29
VSS
AP3
VSS
AP31
VSS
AP38
VSS
AP39
VSS
AP48
VSS
AP52
VSS
AP54
VSS
AP57
VSS
AR11
VSS
AR15
VSS
AR17
VSS
AR23
VSS
AR31
VSS
AR33
VSS
AR39
VSS
AR43
VSS
AR49
VSS
AR5
VSS
AR52
VSS
AT13
VSS
AT35
VSS
AT37
VSS
AT40
VSS
AT42
VSS
AT43
VSS
AT46
VSS
AT49
VSS
AT61
VSS
AT62
VSS
AT63
VSS
AU1
VSS
AU16
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU33
AU51
AU53
AU55
AU57
AU59
AV14
AV16
AV20
AV24
AV28
AV33
AV34
AV36
AV39
AV41
AV43
AV46
AV49
AV51
AV55
*HSW_ULT_DDR3L
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
ICT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
3
AV59
AV8
AW16
AW24
AW33
AW35
AW37
AW4
AW40
AW42
AW44
AW47
AW50
AW51
AW59
AW60
AY11
AY16
AY18
AY22
AY24
AY26
AY30
AY33
AY4
AY51
AY53
AY57
AY59
AY6
B20
B24
B26
B28
B32
B36
B4
B40
B44
B48
B52
B56
B60
C11
C14
C18
C20
C25
C27
C38
C39
C57
D12
D14
D18
D2
D21
D23
D25
D26
D27
D29
D30
D31
DC_TEST_AY2_AW2
DC_TEST_AY3_AW3
TP109
DC_TEST_AY61_AW61
DC_TEST_AY62_AW62
DC_TEST_A3_B3
TP78
DC_TEST_A61_B61
DC_TEST_B62_B63
DC_TEST_C1_C2
TEST_AY60
TEST_B2
2
U19I
D33
VSS
D34
VSS
D35
VSS
D37
VSS
D38
VSS
D39
VSS
D41
VSS
D42
VSS
D43
VSS
D45
VSS
D46
VSS
D47
VSS
D49
VSS
D5
VSS
D50
VSS
D51
VSS
D53
VSS
D54
VSS
D55
VSS
D57
VSS
D59
VSS
D62
VSS
D8
VSS
E11
VSS
E17
VSS
F20
VSS
F26
VSS
F30
VSS
F34
VSS
F38
VSS
F42
VSS
F46
VSS
F50
VSS
F54
VSS
F58
VSS
F61
VSS
G18
VSS
G22
VSS
G3
VSS
G5
VSS
G6
VSS
G8
VSS
H13
VSS
AY2
DAISY_CHAIN_NTCF_AY2
AY3
DAISY_CHAIN_NTCF_AY3
AY60
DAISY_CHAIN_NTCF_AY60
AY61
DAISY_CHAIN_NTCF_AY61
AY62
DAISY_CHAIN_NTCF_AY62
B2
DAISY_CHAIN_NTCF_B2
B3
DAISY_CHAIN_NTCF_B3
B61
DAISY_CHAIN_NTCF_B61
B62
DAISY_CHAIN_NTCF_B62
B63
DAISY_CHAIN_NTCF_B63
C1
DAISY_CHAIN_NTCF_C1
C2
DAISY_CHAIN_NTCF_C2
*HSW_ULT_DDR3L
VSS
DAISY_CHAIN_NTCF_A3
DAISY_CHAIN_NTCF_A4
DAISY_CHAIN_NTCF_A60
DAISY_CHAIN_NTCF_A61
DAISY_CHAIN_NTCF_A62
DAISY_CHAIN_NTCF_AV1
DAISY_CHAIN_NTCF_AW 1
DAISY_CHAIN_NTCF_AW 2
DAISY_CHAIN_NTCF_AW 3
DAISY_CHAIN_NTCF_AW 61
DAISY_CHAIN_NTCF_AW 62
DAISY_CHAIN_NTCF_AW 63
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H17
H57
J10
J22
J59
J63
K1
K12
L13
L15
L17
L18
L20
L58
L61
L7
M22
N10
N3
P59
P63
R10
R22
R8
T1
T58
U20
U22
U61
U9
V10
V3
V7
W20
W22
Y10
Y59
Y63
V58
AH46
V23
AH16
A3
DC_TEST_A3_B3
A4
TEST_A4
A60
TEST_A60
A61
DC_TEST_A61_B61
A62
TEST_A62
AV1
TEST_AV1
AW1
TEST_AW1
AW2
DC_TEST_AY2_AW2
AW3
DC_TEST_AY3_AW3
AW61
DC_TEST_AY61_AW61
AW62
DC_TEST_AY62_AW62
AW63
TEST_AW63
1
05
TP79
TP85
TP84
TP102
TP105
TP107
A A
PROJECT :U83
PROJECT :U83
PROJECT :U83
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
ULT 4/9 (RSV,GND)
ULT 4/9 (RSV,GND)
ULT 4/9 (RSV,GND)
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
1
1A
1A
1A
5 41Monday, March 18, 2013
5 41Monday, March 18, 2013
5 41Monday, March 18, 2013
5
4
3
2
1
Lynx Point-LP Platform Controller Hub (LVDS,DDI)
U19M
PCH_LVDS_BLON<20>
PCH_DISP_ON<20>
D D
SUSACK#SUSWARN#
SUSACK#
SYS_RESET#
C531 *0.1U/10V_4
TP62
EC_PWROK
EC_PWROK
PLTRST#
RSMRST#
SUSWARN#
DNBSWON#_R
AC_PRESENT_R
PM_BATLOW#
PCH_SLP_S0_N
PCH_SLP_WLAN_N
SYS_RESET#<11>
R480 *0_4
R472 0_4
RSMRST#<28>
R479 0_4
R164 0_4
R138 0_4
PCH_SLP_S0_N<11,28>
for DS3
SUSACK#_EC<28>
SYS_PWROK<11>
C C
EC_PWROK<28>
for DS3
SUSWARN#_EC<28>
DNBSWON#<11,28>
U19L
AK2
SUSACK#
AC3
SYS_RESET#
AG2
SYS_PWROK
AY7
PCH_PWROK
AB5
APWROK
AG7
PLTRST#
AW6
RSMRST#
AV4
SUSWARN#/SUSPWRDNACK/GPIO30(SUS)
AL7
PWRBTN#
AJ8
ACPRESENT / GPIO31(DSW)
AN4
BATLOW# / GPIO72(DSW )
AF3
SLP_S0#
AM5
SLP_WLAN#/ GPIO29(DSW )
*HSW_ULT_DDR3L
System Power Management
DSWVRMEN
DPWROK
WAKE#
CLKRUN#/ GPIO32
SUS_STAT# / GPIO61 (SUS)
SUSCLK / GPIO62 (SUS)
SLP_S5# / GPIO63 ( DSW)
SLP_S4#
SLP_S3#
SLP_A#
SLP_SUS#
SLP_LAN#
AW7
DSWVRMEN
AV5
DPWROK RSMRST#
AJ5
PCIE_WAKE#
V5
CLKRUN#
AG4
SUS_STAT#
AE6
PCH_SUSCLK_L
AP5
AJ6
AT4
AL5
AP4
SLP_SUS#
AJ7
SLP_LAN#
DSWVRMEN <7>
Ra
R543 0_4
R542 *0_4
Rb
PCIE_WAKE# <23,24,27,28>
CLKRUN# <25,28>
TP50
R116 *0_4/S
SLP_S5# <11>
SUSC# <11,28>
SUSB# <11,28>
TP55
SLP_A# <11>
R142 0_4
TP69
For DS3 -->Ra
Non-DS3 -->Rb
DPWROK_EC
SLP_SUS#_EC
PCH_DPST_PWM<20>
EDP_DISP_UTIL<2>
Need Check!
DPWROK_EC <28>
PCH_SUSCLK <28>
TP26
for DS3
SLP_SUS#_EC <28>AC_PRESENT_EC<28>
PCH_LVDS_BLON
PCH_DISP_ON
PCH_DPST_PWM
R379 *0_4
A9
EDP_BKLEN
C6
EDP_VDDEN
B8
EDP_BKLCTL
*HSW_ULT_DDR3L
EDP SIDEBAND
DDPB_CTRLCLK
DDPB_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA
DISPLAY
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
EDP_HPD
B9
C9
C5
B5
C8
D9
D11
B6
A6
A8
D6
SDVO_CLK
SDVO_DATA
HDMI_HPD_CON
INT_eDP_HPD_Q
SDVO_CLK <21>
SDVO_DATA <21>
HDMI_HPD_CON <21>
06
INT. HDMI
B B
PCH Pull-high/low(CLG)
PM_BATLOW#
PCIE_WAKE#
Change to 1k for LAN wake from OBFF state issue
SUSACK#
SUSWARN#
Check SUSWARN# need PU?
PWRBTN# internally PU in PCH to 3.3V_DSW
DNBSWON#_R
AC_PRESENT_R
A A
SYS_PWROK
CLKRUN#
SYS_RESET#
RSMRST#
DPWROK_EC
R156 10K_4
R131 1K_4
R471 10K_4
R478 10K_4
R163 *10K_4
R137 *10K_4
R481 *1K_4
R121 8.2K/F_4
R119 10K_4
R123 *1K_4 Q36
R541 10K_4
R544 100K_4
+3VS5
+3V_DEEP_SUS
+3V
5
for DS3
+3VS5
PLTRST#(CLG)
R453 100K_4
INT_eDP_HPD_Q
PLTRST#
R449 0_4
Q33 *2N7002
1
R442
*100K_4
PLTRST# <11,14,23,24,25,27,28>
Check Q2010 Rise/Fall time less than 100ns
Reserve EDP_HPD opposites circuit!
+VCCIO_OUT
R468
DG V0.7 -> 10K
*10K/F_4
SCH V0.7 -> 1K
3
INT_eDP_HPD
2
+5V
R500
*100K_4
*2N7002
4
R497 0_4
3
2
1
R501
100K_4
RTD2132R Vender request PD 100kohm
ULT_EDP_HPD <20,21>
3
System PWR_OK(CLG)
+3VS5
SYS_PWROK
4
U17
*TC7SH08FU
C522 *0.1U/10V_4
2
1
3 5
R447 0_4
EC_PWROK
R430
10K_4
2
IMVP_PWRGD <4,33>
+3V<7,8,9,10,11,12,13,14,20,21,22,23,24,25,26,27,28,33,34,35>
+3VS5<9,10,11,25,27,30,31,34,35,36>
PROJECT :U83
PROJECT :U83
PROJECT :U83
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
ULT 5/9(Power Manger)
ULT 5/9(Power Manger)
ULT 5/9(Power Manger)
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
6 41Thursday, March 14, 2013
6 41Thursday, March 14, 2013
6 41Thursday, March 14, 2013
1A
1A
1A
5
4
3
2
1
Lynx Point-LP Platform Controller Hub
(HDA,JTAG,SATA)
U19J
TP70
PCH_SPI1_CLK
PCH_SPI_CS0#
PCH_SPI1_SI
PCH_SPI1_SO
PCH_SPI_IO2
PCH_SPI_IO3
AW5
RTCX1
AY5
RTCX2
AU7
RTCRST#
AV6
SRTCRST#
AU6
INTRUDER#
AV7
INTVRMEN
AW8
HDA_BCLK / I2S0_SCLK
AV11
HDA_SYNC/ I2S0_SFRM
AU8
HDA_RST#/ I2S_MCLK
AY10
HDA_SDIN0/ I2S0_RXD
AU12
HDA_SDIN1/ I2S1_RXD
AU11
HDA_SDO/ I2S0_TXD
AW10
HDA_DOCK_EN# / I2S1_TXD
AV10
HDA_DOCK_RST/ I2S1_SFRM
AY8
I2S1_SCLK
AU62
PCH_TRST#
AE62
PCH_TCK
AD61
PCH_TDI
AE61
PCH_TDO
AD62
PCH_TMS
AL11
RSVD
AC4
RSVD
AE63
JTAGX
AV2
RSVD
AA3
SPI_CLK
Y7
SPI_CS0#
Y4
SPI_CS1#
AC2
SPI_CS2#
AA2
SPI_MOSI
AA4
SPI_MISO
Y6
SPI_IO2
AF1
SPI_IO3
*HSW_ULT_DDR3L
RTC
SPI JTAG
PWROK
LPC
SATA_RN0/ PERN6_L3
SATA_RP0/ PERP6_L3
SATA_TN0/ PETN6_L3
SATA_TP0/ PETP6_L3
SATA_RN1/ PERN6_L2
SATA_RP1/ PERP6_L2
SATA_TN1/ PETN6_L2
SATA_TP1/ PETP6_L2
SATA_RN2/ PERN6_L1
SATA_RP2/ PERP6_L1
SATA_TN2/ PETN6_L1
SATA_TP2/ PETP6_L1
SATA_RN3/ PERN6_L0
AUDIO
SATA_RP3/ PERP6_L0
SATA_TN3/ PETN6_L0
SATA_TP3/ PETP6_L0
SATA0GP/ GPIO34
SATA1GP/ GPIO35
SATA2GP/ GPIO36
SATA3GP/ GPIO37
SATA_RCOMP
SATA
0 = Default (weak pull-down 20K)
1 = Setting to No-Reboot mode
0 = "top-block swap" mode
1 = Default (weak pull-up 20K)
RTC_X1
RTC_X2
RTC_RST#<11>
D D
C C
B B
+3V_RTC
PCH Strap Table
R521 1M_4
ACZ_SDIN0<22>
XDP_TRST#_CPU<2,11>
JTAG_TCK_PCH<11>
JTAG_TDI_PCH<11>
JTAG_TDO_PCH<11>
JTAG_TMS_PCH<11>
JTAGX_PCH<11>
Pin Name Strap description Sampled Configuration
SPKR
RTC_RST#
SRTC_RST#
SM_INTRUDER#
PCH_INVRMEN
ACZ_BCLK
ACZ_SYNC
ACZ_RST#
ACZ_SDOUT
XDP_TRST#_CPU
JTAG_TCK_PCH
JTAG_TDI_PCH
JTAG_TDO_PCH
JTAG_TMS_PCH
JTAGX_PCH
No reboot mode setting PWROK
SDIO_D0 /GPIO66 Top-Block Swap
LAD0
LAD1
LAD2
LAD3
LFRAME#
SATA_IREF
SATALED#
RSVD
RSVD
AU14
AW12
AY12
AW11
AV12
J5
H5
B15
A15
J8
H8
A17
B17
J6
H6
B14
C15
F5
E5
C17
D17
V1
U1
V6
AC1
C12
A12
U3
L11
K10
SATA_RXN0
SATA_RXP0
SATA_TXN0
SATA_TXP0
SATA_RXN1
SATA_RXP1
SATA_TXN1
SATA_TXP1
SATA_RXN2
SATA_RXP2
SATA_TXN2
SATA_TXP2
ACC_LED#
SIO_EXT_SMI#
PCI_SERR#
SATA3GP
SATA_RCOMP
SATA_IREF
LAD0 <25,27,28>
LAD1 <25,27,28>
LAD2 <25,27,28>
LAD3 <25,27,28>
LFRAME# <25,27,28>
SATA_RXN0 <25>
SATA_RXP0 <25>
SATA_TXN0 <25>
SATA_TXP0 <25>
SATA_RXN1 <25>
SATA_RXP1 <25>
SATA_TXN1 <25>
SATA_TXP1 <25>
SATA_RXN2 <24>
SATA_RXP2 <24>
SATA_TXN2 <24>
SATA_TXP2 <24>
TP97
ACC_LED# <22>
TP95
SIO_EXT_SMI# <28>
PCI_SERR# <28>
TP93
TP101
R391 3.01K/F_4
R362 0_6
R450 10K_4
INTVRMEN Integrated 1.05V VRM enable ALWAYS Should be always pull-up
HDA_SDO /I2S0_TXD
GSPI0_MOSI /GPIO86 PWROK
GPIO15
DSWVRMEN
A A
5
Flash Descriptor Security
Only for Interposer
Boot BIOS Selection
TLS Confidentiality PWROK
Deep Sx Well
On-Die Voltage
Regulator Enable
PWROK
ALWAYS Should be always pull-up
0 = Default (weak pull-down 20K)
1 = Can be Overridden
GNT0#
Boot Location
1
LPC
0
SPI(Default)
0 = ME Crypto Transport Layer Security
cipher suite with no confidentiality(Default)
1 = Intel ME Crypto TLS cipher suite with
confidentiality
4
+3V_DEEP_SUS
+1.05V
R476 *0_4
HDD0 (SATA3 6.0Gb/s)
mSATA (SATA4 6Gb/s)
ODD (SATA3 6.0Gb/s)
+V1.05S_ASATA3PLL
DG recommended that SATA AC coupling capacitors should be
close to the connector (<100 mils) for optimal signal quality.
+3V
SATA_LED# <22>
Circuit
+3V
+3V_RTC
R125 *1K_4
+3V_RTC
R455 *1K_4
R376 *1K_4
R375 *1K_4
R519 330K_4
GPIO33_EC<28>
R520 330K_4
PCH_SPI_CS0#_R<28>
PCH_SPI1_CLK_R<28>
PCH_SPI1_SI_R<28>
PCH_SPI1_SO_R<28>
3
+1.05VS5
R473 *51_4
R469 51_4
R460 51_4
R487 51_4
R477 *51_4
Close to Chipset
SPKR
PCH_INVRMEN
R182 1K_4
GPIO15_ULT <9>
JTAGX_PCH
JTAG_TMS_PCH
JTAG_TDI_PCH
JTAG_TDO_PCH
JTAG_TCK_PCH
SPKR <9>
GPIO66_ULT <9>
ACZ_SDOUT
DSWVRMEN <6>
PCH_SPI_CS0#_R
PCH_SPI1_CLK_R
PCH_SPI1_SI_R
PCH_SPI1_SO_R
RTC Clock 32.768KHz
C530 *18P/50V_4
C534 *18P/50V_4
23
Y4
*32.768KHZ
4 1
no stuff If use green Clock
RTC Circuitry(RTC)
+3V_RTC_0
+3V_RTC_0
12
CN18
BAT_CONN
RTC Power trace width 20mils.
+3VPCU
R346
*1K_4
+3V_RTC_1
Uninstall for Green-CLK
HDA Bus(CLG)
ACZ_SYNC_AUDIO<22>
ACZ_RST#_AUDIO<22>
ACZ_SDOUT_AUDIO<22>
BIT_CLK_AUDIO<22>
*10P/50V_4
+3V_DEEP_SUS
Vender
AMIC
Winbond
GigaDevice
Size
8MB AKE3EFN0800 (A25LQ64M-F)
8MB
8MB
Socket
TP66-71 need place to TOP
R457/R453/R450/R451/R546/R548 close to U15 pin
PCH_SPI_IO2
+3V <6,8,9,10,11,12,13,14,20,21,22,23,24,25,26,27,28,33,34,35>
+5V <6,21,22,24,25,26,27,34>
+1.05V <4,10,11,27,28,31,34>
+3VS5 <6,9,10,11,25,27,30,31,34,35,36>
+3VPCU <4,22,25,26,27,28,29,30>
+3V_RTC <10,27>
+V1.05S_ASATA3PLL <10>
2
R533 33_4
R535 33_4
R530 33_4
R532 33_4
C553
R181 *1K_4
P/N
AKE3EFP0N07 (W25Q64FVSSIQ)
AKE3EGN0Q01 (GD25B64BSIGR)
DFHS08FS023
TP12
TP19
TP11
TP10
TP13
TP18
PCH_SPI_CS0#
PCH_SPI1_SI PCH_SPI1_SI_R
PCH_SPI1_SO PCH_SPI1_SO_R
+3VSPI
R389 3.3K/F_4C620 1U/10V_4
PCH_SPI_CS0#_R
PCH_SPI1_CLK_R
PCH_SPI1_SI_R
PCH_SPI1_SO_R
BIOS_WP#
HOLD#
R386 15/F_4
R441 15/F_4
R436 15/F_4
R387 15/F_4
R494 0_4
RTC_X1
R483
*10M_4
RTC_X2
D9
*BAT54C
*1U/6.3V_4
C464
30mils
+3V_RTC
CLKGEN_RTC_X1 <27>
R341
20K/F_4
R347
20K/F_4
R345 *0_6
GPIO Pull UP
ACC_LED#
ACZ_SYNC
ACZ_RST#
ACZ_SDOUT
ACZ_BCLK
ACZ_SYNC
SIO_EXT_SMI#
PCI_SERR#
SATA3GP
PCH SPI ROM(CLG)
+3V_DEEP_SUS
U15
PCH_SPI_CS0#_R
PCH_SPI1_CLK_RPCH_SPI1_CLK
C521
22P/50V_4
R388 15/F_4
1
CE#
VDD
6
SCK
5
SI
2
SO
HOLD#
3
WP#
VSS
A25LQ64M-F
AKE3EFN0800
BIOS_WP#
SI modify
PROJECT :U83
PROJECT :U83
PROJECT :U83
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
ULT 6/9(SATA/HDA)
ULT 6/9(SATA/HDA)
ULT 6/9(SATA/HDA)
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
C462
1U/6.3V_4
C463
1U/6.3V_4
SRTC_RST#RTC_RST#
R454 10K_4
R106 10K_4
R420 10K_4
R474 10K_4
R438 0_4
8
+3VSPI
R451 3.3K/F_4
7
HOLD#
R440 15/F_4
4
PCH_SPI_IO3
07
RTC_RST#
SRTC_RST#
C520
0.1U/10V_4
7 41Thursday, March 14, 2013
7 41Thursday, March 14, 2013
7 41Thursday, March 14, 2013
+3V
1A
1A
1A
5
PCI/USBOC# Pull-up(CLG)
DGPU_PR_EN
TS_INTB#
PIRQC#
PIRQD#
GPIO77_ULT
GPIO52_ULT
GPIO53_ULT
GPIO55_ULT
DGPU_HOLD_RST#
D D
DGPU_HOLD_RST#
SMBALERT#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB3.0
C C
R428 *10K_4
R432 10K_4
R103 10K_4
R423 10K_4
R403 10K_4
R418 10K_4
R416 10K_4
R111 10K_4
R104 10K_4
R102 *100K_4
R498 10K_4
R171 10K_4
R172 10K_4
R173 10K_4
R484 10K_4
USB30_RX1-<26>
USB30_RX1+<26>
USB30_TX1-<26>
USB30_TX1+<26>
USB30_RX2-<26>
USB30_RX2+<26>
USB30_TX2-<26>
USB30_TX2+<26>
Lynx Point-LP Platform Controller Hub
(HDA,JTAG,SATA)
+3V
+3V_DEEP_SUS
for DS3
U19N
G20
USB3RN1
H20
USB3RP1
C33
USB3TN1
B34
USB3TP1
E18
USB3RN2
F18
USB3RP2
B33
USB3TN2
A33
USB3TP2
20111130 Modify USB3.0 for HM70
GPIO77_ULT
TS_INTB#
PIRQC#
PIRQD#
GPIO52_ULT
DGPU_PR_EN<35,36,37>
DGPU_HOLD_RST#<14>
B B
R417 0_4
TP46
DGPU_PWR_EN_R
DGPU_HOLD_RST#
GPIO53_ULT
GPIO55_ULT
PCI_PME#
U6
P4
N4
N2
L1
L3
R5
L4
U7
AD4
PIRQA#/ GPIO77
PIRQB#/ GPIO78
PIRQC#/ GPIO79
PIRQD#/ GPIO80
GPIO52
GPIO54
GPIO51
GPIO53
GPIO55
PME#
PCI
C- Link
USBRBIAS#
USB
OC0# / GPIO40(SUS)
OC1# / GPIO41(SUS)
OC2# / GPIO42(SUS)
OC3# / GPIO43(SUS)
4
AF2
CL_CLK
AD2
CL_DATA
AF4
CL_RST#
USB2.0(M/B-1)
USB2.0/USB3.0 COMBO 1st
USB2.0 Small board
USB2.0/USB3.0 COMBO 2nd
AN8
USB2N0
AM8
USB2P0
AR7
USB2N1
AT7
USB2P1
AR8
USB2N2
AP8
USB2P2
AR10
USB2N3
AT10
USB2P3
AM15
USB2N4
AL15
USB2P4
AM13
USB2N5
AN13
USB2P5
AP11
USB2N6
AN11
USB2P6
AR13
USB2N7
AP13
USB2P7
AJ10
AJ11
USBRBIAS
AN10
RSVD
AM10
RSVD
AL3
AT1
AH2
AV3
Cardreader
WLAN
LAN
(USBP0)
(USBP1)
USBP0- <26>
USBP0+ <26>
USBP1- <22>
USBP1+ <22>
USBP2- <21>
USBP2+ <21>
Camera
(USBP2)
USB2.0(M/B-2)
SI modify
TIE TRACES TOGETHER
CLOSE TO PINS WITH LENGTH
TO RESISTOR
USB_BIAS
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
(USBP5)
USBP5- <26>
USBP5+ <26>
USBP6- <27>
USBP6+ <27>
Cardreader
R140
22.6/F_4
TP65
TP66
TP64
TP100
PCIE_RXN2_CARD<24>
PCIE_RXP2_CARD<24>
PCIE_TXN2_CARD<24>
PCIE_TXP2_CARD<24>
PCIE_RXN3_WLAN<27>
PCIE_RXP3_WLAN<27>
PCIE_TXN3_WLAN<27>
PCIE_TXP3_WLAN<27>
PCIE_RXN4_LAN<23>
PCIE_RXP4_LAN<23>
PCIE_TXN4_LAN<23>
PCIE_TXP4_LAN<23>
+V1.05S_AUSB3PLL<10>
WLAN
Touch Screen
WLAN
LAN
PEG_RXN0<14>
PEG_RXP0<14>
PEG_TXN0<14>
PEG_TXP0<14>
PEG_RXN1<14>
PEG_RXP1<14>
PEG_TXN1<14>
PEG_TXP1<14>
PEG_RXN2<14>
PEG_RXP2<14>
PEG_TXN2<14>
PEG_TXP2<14>
PEG_RXN3<14>
PEG_RXP3<14>
PEG_TXN3<14>
PEG_TXP3<14>
USBP7- <27>
USBP7+ <27>
PCIE_CLKREQ_CR#<24>
CLK_PCIE_CRN<24>
CLK_PCIE_CRP<24>
VGA
CLK_PCIE_WLANN<27>
CLK_PCIE_WLANP<27>
PCIE_CLKREQ_WLAN#<27>
PCIE_CLKREQ_LAN#<23>
PCIE_CLKREQ_VGA#<15>
3
C192 0.1U/10V_4
C193 0.1U/10V_4
C494 0.1U/10V_4
C493 0.1U/10V_4
C496 0.1U/10V_4
C495 0.1U/10V_4
C183 0.22U/10V_4
C184 0.22U/10V_4
C188 0.22U/10V_4
C189 0.22U/10V_4
C190 0.22U/10V_4
C191 0.22U/10V_4
C185 0.22U/10V_4
C186 0.22U/10V_4
CLK_PCIE_LANN<23>
CLK_PCIE_LANP<23>
CLK_VGA_N<14>
CLK_VGA_P<14>
SI modify
PCIE_TXN2_CARD_C
PCIE_TXP2_CARD_C
PCIE_TXN3_WLAN_C
PCIE_TXP3_WLAN_C
PEG_TXN0_C
PEG_TXP0_C
PEG_TXN1_C
PEG_TXP1_C
PEG_TXN2_C
PEG_TXP2_C
PEG_TXN3_C
PEG_TXP3_C
R98 0_4
R99 3.01K/F_4
PCIE_CLKREQ_CR#
PCIE_CLKREQ1#
CLK_PCIE_WLANN
CLK_PCIE_WLANP
PCIE_CLKREQ_WLAN#
CLK_PCIE_LANN
CLK_PCIE_LANP
PCIE_CLKREQ_LAN#
CLK_VGA_N
CLK_VGA_P
PCIE_CLKREQ_VGA#
PCIE_CLKREQ0#
PCIE_RXN4_LAN
PCIE_RXP4_LAN
PCIE_TXN4_LAN_C
PCIE_TXP4_LAN_C
PCIE_IREF
PCIE_RCOMP
CLK_PCIE_CRN
CLK_PCIE_CRP
U19K
G17
PERN1 / USB3RN3
F17
PERP1 / USB3RP3
C30
PETN1 / USB3TN3
C31
PETP1 / USB3TP3
F15
PERN2/ USB3RN4
G15
PERP2/ USB3RP4
B31
PETN2/ USB3TN4
A31
PETP2/ USB3TP4
G11
PERN3
F11
PERP3
C29
PETN3
B30
PETP3
F13
PERN4
G13
PERP4
B29
PETN4
A29
PETP4
F10
PERN5_L0
E10
PERP5_L0
C23
PETN5_L0
C22
PETP5_L0
F8
PERN5_L1
E8
PERP5_L1
B23
PETN5_L1
A23
PETP5_L1
H10
PERN5_L2
G10
PERP5_L2
B21
PETN5_L2
C21
PETP5_L2
E6
PERN5_L3
F6
PERP5_L3
B22
PETN5_L3
A21
PETP5_L3
B27
PCIE_IREF
A27
PCIE_RCOMP
E15
RSVD
E13
RSVD
C43
CLKOUT_PCIE0N
C42
CLKOUT_PCIE0P
U2
PCIECLKRQ0# / GPIO18
B41
CLKOUT_PCIE_N1
A41
CLKOUT_PCIE_P1
Y5
PCIECLKRQ1# / GPIO19
C41
CLKOUT_PCIE_N2
B42
CLKOUT_PCIE_P2
AD1
PCIECLKRQ2# / GPIO20
B38
CLKOUT_PCIE_N3
C37
CLKOUT_PCI_P3
N1
PCIECLKRQ3# / GPIO21
A39
CLKOUT_PCIE_N4
B39
CLKOUT_PCIE_P4
U5
PCIECLKRQ4# / GPIO22
B37
CLKOUT_PCIE_N5
A37
CLKOUT_PCIE_P5
T2
PCIECLKRQ5# / GPIO23
*HSW_ULT_DDR3L
2
SMBALERT# / GPIO11(SUS)
SMBUS
SML0ALERT# / GPIO60(SUS)
SML1ALERT# / PCHHOT# / GPIO73(SUS)
SML1DATA / GPIO74(SUS)
PCI-E*
CLOCK SIGNALS
SMBCLK
SMBDATA
SML0CLK
SML0DATA
SML1CLK / GPIO75(SUS)
XTAL24_IN
XTAL24_OUT
CLKOUT_ITPXDP#
CLKOUT_ITPXDP_P
CLKOUT_LPC_0
CLKOUT_LPC_1
DIFFCLK_BIASREF
RSVD
RSVD
TESTLOW_C35
TESTLOW_C34
TESTLOW_AK8
TESTLOW_AL8
AN2
SMBALERT#
AP2
SMB_PCH_CLK
AH1
SMB_PCH_DAT
AL2
SML0ALERT#
AN1
SMB_ME0_CLK
AK1
SMB_ME0_DAT
AU4
SML1ALERT#
AU3
SMB_ME1_CLK
AH3
SMB_ME1_DAT
A25
XTAL24_IN
B25
XTAL24_OUT
B35
CK_XDP_N_R
A35
CK_XDP_P_R
RP1 install for XDP
AN15
CLK_PCI_EC_R
AP15
CLK_PCI_LPC_R
C26
XCLK_BIASREF
K21
M21
C35
R380 10K/F_4
C34
R381 10K/F_4
AK8
R531 10K/F_4
AL8
R141 10K/F_4
RP1
*0_4P2R_4
R369 0_4
R392
*1M_4
2
4
R525 22_4
R524 22_4
R5103 22_4
R384
3.01K/F_4
1
TP68
TP82
C501 *12P/50V_4
1
2
*24MHZ +-30PPM
Y3
4
3
C500 *12P/50V_4
TP81
1
3
EC34 18P/50V_4
EMI(near PCH)
EC33 18P/50V_4
EMI(near PCH)
EC44 *18P/50V_4
08
PCH_XTAL24_IN <27>
CK_XDP_N <11>
CK_XDP_P <11>
CLK_24M_KBC <28>
CLK_24M_DEBUG <27>
CLK_PCI_TPM <25>
+V1.05S_AXCK_LCPLL <10>
*HSW_ULT_DDR3L
SMBus/Pull-up(CLG) CLK_REQ/Strap Pin(CLG)
Q34
MBCLK2<13,20,28>
MBDATA2<13,20,28>
A A
R495 4.7K_4
+3V
SMB_RUN_DAT<11,12,13,20,25>
R461 4.7K_4
+3V
SMB_RUN_CLK<11,12,13,20,25>
5
4 3
1
*2N7002DW
Q35
4 3
1
2N7002DW
+3V
5
SMB_ME1_CLK
2
6
SMB_ME1_DAT
+3V
5
SMB_PCH_DAT
2
6
SMB_PCH_CLK
4
PCIE_CLKREQ0#
PCIE_CLKREQ1#
PCIE_CLKREQ_WLAN#
PCIE_CLKREQ_LAN#
PCIE_CLKREQ_CR#
PCIE_CLKREQ_VGA#
R443 10K_4
R115 10K_4
R482 10K_4
R425 10K_4
R445 10K_4
R114 10K_4
+3V
for DS3
+3V_DEEP_SUS
+3V<6,7,9,10,11,12,13,14,20,21,22,23,24,25,26,27,28,33,34,35>
3
+3V_DEEP_SUS<6,7,9,10,11>
2
SMBus/Pull-up(CLG)
R499 2.2K_4
R486 2.2K_4
R168 2.2K_4
R493 2.2K_4
R178 2.2K_4
R485 2.2K_4
R179 10K_4
R492 1K_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
SMB_PCH_CLK
SMB_PCH_DAT
SMB_ME0_CLK
SMB_ME0_DAT
SMB_ME1_CLK
SMB_ME1_DAT
SML1ALERT#
SML0ALERT#
PROJECT :U83
PROJECT :U83
PROJECT :U83
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
ULT 7/9 (PCIE/USB/CLK)
ULT 7/9 (PCIE/USB/CLK)
ULT 7/9 (PCIE/USB/CLK)
1
8 41Thursday, March 14, 2013
8 41Thursday, March 14, 2013
8 41Thursday, March 14, 2013
1A
1A
1A
5
SIO_EXT_SCI#<28>
BT_OFF<27>
RF_OFF<27>
for DS3
D D
+3V_DEEP_SUS
SI modify
DEVSLP1<25>
C C
BT_COMBO_EN#<27>
B B
Reserve
R175 10K_4
ZERO_ODD_DP#<24>
TP for DG
TP29
TP67
TP57
TP52
GPIO15_ULT<7>
DGPU_PWROK<28,35,36,37>
TP5038
ACCEL_INTA#<27>
BT_COMBO_EN#
MPHY_PWREN<34>
ACZ_SPKR<22>
SPKR<7>
RF_OFF
R631 *0_4
TP92
GPIO27_ULT
TP106
GPIO70_ULT
TP94
R456 0_4
BT_OFF
LAN_DISABLE#
GPIO13_ULT
GPIO14_ULT
TP103
ODD_PRSNT#_R
GPIO24_ULT
GPIO25_ULT
GPIO26_ULT
GPIO28_ULT
DEVSLP0
DEVSLP1
DEVSLP2
GPIO44_ULT
BOARD_ID4
ACCEL_INTA#
BOARD_ID5
GPIO49_ULT
GPIO50_ULT
BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3
MPHY_PWREN
GPIO76_ULT
SPKR
Lynx Point-LP Platform Controller Hub
Lynx Point-LP Platform Controller Hub
Lynx Point-LP Platform Controller HubLynx Point-LP Platform Controller Hub
(HDA,JTAG,SATA)
(HDA,JTAG,SATA)
(HDA,JTAG,SATA)(HDA,JTAG,SATA)
U19O
AU2
AM3
AM2
AM7
AT3
AH4
AD6
Y1
T3
AD5
AM4
AN3
AN5
AD7
P2
L2
N5
AK4
AG5
AG3
AB6
U4
Y3
P3
AG6
AP1
AL4
AT5
C4
Y2
P1
V2
*HSW_ULT_DDR3L
4
GPIO8(SUS)
GPIO9(SUS)
GPIO10(SUS)
LAN_PHY_PWR_CTRL / GPIO12(DSW)
GPIO13(SUS)
GPIO14(SUS)
GPIO15(SUS)
GPIO16
GPIO17
GPIO24 (SUS)
GPIO25(DSW)
GPIO26(SUS)
GPIO27(DSW)
GPIO28(SUS)
DEVSLP0/ GPIO33
DEVSLP1/ GPIO38
DEVSLP2/ GPIO39
GPIO44(SUS)
GPIO45(SUS)
GPIO46(SUS)
GPIO47(SUS)
GPIO48
GPIO49
GPIO50
GPIO56(SUS)
GPIO57(SUS)
GPIO58(SUS)
GPIO59(SUS)
SDIO_POWER_EN/ GPIO70
HSIOPC/ GPIO71
BMBUSY# / GPIO76
SPKR/ GPIO81
GPIO
Haswell (GPIO)
D60
RSVD
RSVD
PCH_THRMTRIP#
V4
T4
AW15
AF20
AB21
R6
L6
N6
L8
R7
L5
N7
K2
J1
K3
J2
G1
K4
G2
J3
J4
F2
F3
G4
F1
E3
F4
D3
E4
C3
E2
EC_RCIN#
SERIRQ
PCH_OPI_RCOMP
GSPI0_CS
GSPI0_CLK
GSPI0_MISO
GPIO86_ULT
GSPI1_CS
GSPI1_CLK
GSPI1_MISO
GSPI1_MOSI
UART0_RXD
UART0_TXD
UART0_RTS
UART0_CTS
UART1_RXD
UART1_TXD
UART1_RST
UART1_CTS
I2C0_SDA
I2C0_SCL
I2C1_SDA
I2C1_SCL
SDIO_CLK
SDIO_CMD
SDIO_D1
SDIO_D2
SDIO_D3
THRMTRIP#
RCIN#/ GPIO82
PCH_OPI_RCOMP
CPU/MISC
GSPI0_CS/ GPIO83
GSPI0_CLK/ GPIO84
GSPI0_MISO/ GPIO85
GSPI0_MOSI/ GPIO86
GSPI1_CS/ GPIO87
GSPI1_CLK/ GPIO88
GSPI1_MISO/ GPIO89
GSPI1_MOSI/ GPIO90
UART0_RXD/ GPIO91
UART0_TXD/ GPIO92
UART0_RTS/ GPIO93
UART0_CTS/ GPIO94
UART1_RXD/ GPIO0
SERIAL IO
UART1_TXD/ GPIO1
UART1_RST/ GPIO2
UART1_CTS/ GPIO3
I2C0_SDA/ GPIO4
I2C0_SCL/ GPIO5
I2C1_SDA/ GPIO6
I2C1_SCL/ GPIO7
SDIO_CLK/ GPIO64
SDIO_CMD/ GPIO65
SDIO_D0/ GPIO66
SDIO_D1/ GPIO67
SDIO_D2/ GPIO68
SDIO_D3/ GPIO69
SERIRQ
3
R405 0_4
R113 10K_4
R522
49.9/F_4
TP33
GPIO66_ULT <7>
PM_THRMTRIP# <28>
EC_RCIN# <28>
+3V
SERIRQ <25,28>
2
UART1_RXD
I2C1_SDA
GSPI0_CLK
GSPI1_CLKSIO_EXT_SCI#
UART0_RXD
UART1_CTS
GSPI0_CS
GSPI1_CS
RP7
10
9
8
7 4
10K_10P8R_6
RP5
10
9
8
7 4
10K_10P8R_6
1
2
3
56
1
2
3
56
SDIO_D2
SDIO_D1
SDIO_CMD
SDIO_CLK
+3V
UART1_RST
UART0_RTS
UART0_CTS
UART1_TXD
+3V
GSPI1_MOSI
GSPI0_MISO
GSPI1_MISO
UART0_TXD
GPIO Pull-up/Pull-down(CLG)
SI modify
GPIO12 LAN_DISABLE#
SUS -->Check list
+3V -->Datasheet
Close to EC
PM_THRMTRIP#
RP6
10
9
8
7 4
10K_10P8R_6
SIO_EXT_SCI#
BT_OFF
RF_OFF
GPIO13_ULT
GPIO14_ULT
GPIO24_ULT
GPIO26_ULT
GPIO28_ULT
GPIO44_ULT
ACCEL_INTA#
GPIO49_ULT
GPIO50_ULT
ODD_PRSNT#_R
DGPU_PWROK
DEVSLP0
DEVSLP1
DEVSLP2
BT_COMBO_EN#
GPIO70_ULT
EC_RCIN#
GPIO76_ULT
MPHY_PWREN
MPHY_PWREN
GPIO25_ULT
GPIO27_ULT
LAN_DISABLE#
1
1
I2C0_SCL
2
I2C1_SCL
3
I2C0_SDA
SDIO_D3
56
+3V
R134 10K_4
R161 10K_4
R136 10K_4
R135 1K_4
09
+3V_DEEP_SUS
R174 10K_4
R177 10K_4
R139 10K_4
R176 10K_4
R489 10K_4
R488 10K_4
R180 10K_4
R126 10K_4
R491 10K_4
R490 10K_4
R475 10K_4
R433 10K_4
R470 10K_4
R424 10K_4
R407 10K_4
R429 10K_4
R396 10K_4TP99
R112 10K_4
R383 10K_4
R444 10K_4
R434 10K_4
R465 100K_4
R464 *10K_4
+V1.05S_VCCST
+3V
+3VS5
BOARD_ID4
BOARD_ID5
14": 0
Model
U83 DIS-14
U83 UMA-15
A A
UMA: 0
DIS: 1
1
0
0
0
0
0 0
5
15": 1
0
1
0
0
0
0
0
0
0
BOARD_ID1BOARD_ID2BOARD_ID3
BOARD_ID0
0
0
0
0
0
0
0
0
0 0 0
00000
0
0
0
0
R132 10K_4
R158 10K_4
R155 10K_4
R160 10K_4
R463 10K_4
Rb
R128 *10K_4
4
BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4
BOARD_ID5
R133 *10K_4
R159 *10K_4
R154 *10K_4
R167 *10K_4
R466 *10K_4
R127 10K_4
Ra
+3V_DEEP_SUS
DIS
Ra
Stuff
Rb
NC
3
UMA
Rb
Ra
+3V<6,7,8,10,11,12,13,14,20,21,22,23,24,25,26,27,28,33,34,35>
+3VS5<6,10,11,25,27,30,31,34,35,36>
PROJECT :U83
PROJECT :U83
PROJECT :U83
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
ULT 8/9 (GPIO/MISC)
ULT 8/9 (GPIO/MISC)
ULT 8/9 (GPIO/MISC)
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
1
1A
1A
1A
9 41Thursday, March 14, 2013
9 41Thursday, March 14, 2013
9 41Thursday, March 14, 2013
5
+1.05V
D D
C249
1U/6.3V_4
+1.05V
+1.05V
VCCASW=658mA
TP47
+1.05V
C C
TP23
+V3.3DX_1.5DX_ADO
B B
+3V_DEEP_SUS
+3VS5
+3V
A A
VCC1_05=1.741A
DcpSus1=109mA
C206 1U/6.3V_4
C197 1U/6.3V_4
C208 *1U/6.3V_4
C225 *1U/6.3V_4
C499 1U/6.3V_4
C489 22U/6.3VS_8
C484 22U/6.3VS_8
C504 1U/6.3V_4
C498 22U/6.3VST_8
C490 22U/6.3VS_8
SI Change to 22uF for Intel recommend
DcpSus3=10mA
+V3.3DX_1.5DX_PAZSUS_PCH
DcpSus2=25mA
TP60
+V1.05S_CORE_PCH
TP56
C244 1U/6.3V_4
C528 *22U/6.3VS_8
+V1.05A_SUS_PCH
+V1.05DX_MODPHY_PCH
VCCHSIO=1.838A
+V1.05S_AIDLE
+V1.05S_AUSB3PLL
VCCSATA3PLL=42mA
+V1.05S_ASATA3PLL
+V1.05A_VCCUSB3SUS
C243 1U/6.3V_4
+V1.05A_USB2SUS
VCCSUS3_3=63mA
C242 22U/6.3VST_8
VCCDSW3_3=114mA
+3.3V_A_DSW_P
C250 *1U/6.3V_4
C205 22U/6.3VST_8
C2481U/6.3V_4
C2411U/6.3V_4
C20410U/6.3VS_6
+PCH_VCCDSW
+V1.05M_ASW
+V1.05M_FHV0
+V1.05M_FHV1
VCCHDA=11mA
+V3.3A_PSUS
+V3.3S_PCORE
U19P
J11
VCC1_05
H11
VCC1_05
H15
VCC1_05
AE8
VCC1_05
AF22
VCC1_05
AG19
DCPSUSBYP
AG20
DCPSUSBYP
AE9
VCCASW
AF9
VCCASW
AG8
VCCASW
AG14
VCCASW
AG13
VCCASW
AD10
DCPSUS1
AD8
DCPSUS1
K9
VCCHSIO
L10
VCCHSIO
M9
VCCHSIO
N8
VCC1_05
P9
VCC1_05
B18
VCCUSB3PLL
B11
VCCSATA3PLL
J13
DCPSUS3
AH14
VCCHDA
AH13
DCPSUS2
AC9
VCCSUS3_3
AA9
VCCSUS3_3
AH10
VCCDSW3_3
V8
VCC3_3
W9
VCC3_3
ICT
*HSW_ULT_DDR3L
+V3.3DX_1.5DX_ADO
POWER
CORE
VCCMPHY
USB3
HDA
VRM
GPIO/ LCC
R129 0_4
R5105 *0_4
4
RTC
SPI
ICC
THERMAL SENSOR
OPI
SERIAL IO
SUS OSCILLATOR
USB2
+1.5V
+3V
VCCSUS3_3
VCCRTC
DCPRTC
VCCSPI
VCCCLK
VCCCLK
VCCACLKPLL
VCCCLK
VCCCLK
VCCCLK
RSVD
RSVD
RSVD
VCCSUS3_3
VCCSUS3_3
VCCTS1_5
VCC3_3
VCC3_3
RSVD
VCCAPLL
VCCAPLL
VCCSDIO
VCCSDIO
DCPSUS4
RSVD
VCC1_05
VCC1_05
3
Lynx Point-LP Platform Controller Hub
(HDA,JTAG,SATA)(POWER)
+V3.3A_DSW_PRTCSUS
AH11
VCCRTC < 1mA
AG10
AE7
+VCCRTCEXT
VCCSPI=18mA
Y8
+V3.3M_PSPI
+V1.05S_AXCK_DCB
J18
K19
A20
+V1.05S_AXCK_LCPLL
J17
+V1.05S_SSCF100
R21
T21
+V1.05S_SSCFF
K18
M20
V21
AE20
+V3.3A_PSUS
AE21
VCCTS1_5=3mA
J15
+V1.5S_ATS
+V3.3S_PTS
K14
VCC3_3=41mA
K16
VCCAPLL=57mA
Y20
AA21
W21
+V1.05S_APLLOPI
VCCSDIO=17mA
U8
T9
+V3.3S_1.8S_SDIO_PCH
AB8
+V1.05A_AOSCSUS
AC20
AG16
+V1.05S_DUSB
AG17
C258 1U/6.3V_4
C233 0.1U/10V_4 L26 2.2uH/500mA_6
C227 *0.1U/10V_4
R117 0_4
R118 *0_4
2.2uH/500mA_6
L4
C209 1U/6.3V_4
C217 47U/6.3VST_8
C216 47U/6.3VST_8
L27 2.2uH/500mA_6
C503 1U/6.3V_4
C488 47U/6.3VST_8
C483 47U/6.3VS_8
C202 1U/6.3V_4
C210 1U/6.3V_4
R110 0_6
R122 0_6
C203 0.1U/10V_4
2.2uH PN CV-2205JZ00
L5 0_6
C229 1U/6.3V_4
C231 *47U/6.3VST_8
C232 *47U/6.3VST_8
C218 1U/6.3V_4
DcpSus4=1mA
C239 1U/6.3V_4
C246 1U/6.3V_4
+3V_DEEP_SUS
+3V_RTC
C564 1U/6.3V_4
C565 0.1U/10V_4
C247 0.1U/10V_4
+3V_DEEP_SUS
+3V
+1.05V
+1.05V
+1.05V
+1.05V
+V3.3A_PSUS
+1.5V
+3V
+1.05V
+3V
TP45
+1.05V
+1.05V_MODPHY
VCCACLKPLL=31mA
VCCCLK=200mA
2
1
10
20mil
+V1.05S_ASATA3PLL
L25 2.2uH/500mA_6
R446
100K_4
SLP_SUS_ON<28>
R426 0_4
C524
1U/6.3V_4
C517
*10P/50V_4
20mil
for DS3
R462 *0_6
U18
5
IN
4
IN
3
ON/OFF
IC(5P) G5243AT11U
+V1.05S_AUSB3PLL
+V1.05DX_MODPHY_PCH
1
OUT
2
GND
+3V_DEEP_SUS+3VS5
C526
0.1U/10V_4
+5V<6,21,22,24,25,26,27,34>
+1.05V<4,7,11,27,28,31,34>
+3VS5<6,9,11,25,27,30,31,34,35,36>
+5VS5<13,22,25,26,30,32,33,34,35,36,37>
5
+V1.05S_AUSB3PLL<8>
+V1.05S_ASATA3PLL<7>
+V1.05S_AXCK_LCPLL<8>
+3V<6,7,8,9,11,12,13,14,20,21,22,23,24,25,26,27,28,33,34,35>
+3V_RTC<7,27>
+1.35VSUS<2,4,12,13,25,32>
4
3
2
PROJECT :U83
PROJECT :U83
PROJECT :U83
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
ULT 9/9(POWER-2)
ULT 9/9(POWER-2)
ULT 9/9(POWER-2)
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
10 41Monday, March 18, 2013
10 41Monday, March 18, 2013
10 41Monday, March 18, 2013
1A
1A
1A
5
D D
H_VCCST_PWRGD<4>
+1.05V
C C
H_VCCST_PWRGD VCCST_PWRGD_XDP
C228 0.1U/10V_4
4
XDP_PREQ#_CPU<2>
XDP_PRDY#_CPU<2>
CFG0<4>
CFG1<4>
CFG2<4>
CFG3<4>
XDP_BPM0<2>
XDP_BPM1<2>
CFG4<4>
CFG5<4>
CFG6<4>
R406 1K_4
CFG7<4>
PWR_DEBUG<4>
SMB_RUN_DAT<8,12,13,20,25>
SMB_RUN_CLK<8,12,13,20,25>
XDP_TCK0<2>
R496 1K_4
CFG1
CFG2
CFG3
OBSFN_B0
OBSFN_B1
CFG4
CFG5
CFG6
CFG7
DNBSWON#
H_SYS_PWROK_XDP
XDP_TCK1
XDP_TCK0
3
CN6
31
31
323229
333328
343427
353526
363625
373724
383823
393922
404021
414120
424219
434318
444417
454516
464615
474714
484813
494912
505011
515110
52529
53538
54547
55556
56565
57574
58583
59592
60601
*SEC_BSH-030-01-L-D-A-TR
30
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
OBSFN_C0
OBSFN_C1
CFG8
CFG9
CFG10
CFG11
OBSFN_D0
OBSFN_D1
CFG12
CFG13
CFG14
CFG15
XDP_RST
XDP_DBRESET_N
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
R100 1K_4
CFG17 <4>
CFG16 <4>
CFG8 <4>
CFG9 <4>
CFG10 <4>
CFG11 <4>
CFG19 <4>
CFG18 <4>
CFG12 <4>
CFG13 <4>
CFG14 <4>
CFG15 <4>
CK_XDP_P <8>
CK_XDP_N <8>
CFG3
2
C238 0.1U/10V_4
1
11
+1.05V
XDP_DBRESET_N
B B
A A
5
APS
+3V_DEEP_SUS
CN8
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
*ACES_88511-180N
+3VS5
R145 0_4
R146 0_4
R147 0_4
R148 0_4
R149 0_4
R150 0_4
R151 0_4
R152 *0_4
R153 0_4
SUSB# <6,11,28>
SLP_S5# <6>
SUSC# <6,28>
SLP_A# <6>
RTC_RST# <7>
DNBSWON# <6,28>
SYS_RESET# <6>
PCH_SLP_S0_N <6,28>
SUSB# <6,11,28>
4
R157 0_4
R144 *0_4
+3V_DEEP_SUS
+3VS5
R120 1K_4
C215
0.1U/10V_4
+V1.05S_VCCST
JTAGX_PCH<7>
JTAG_TMS_PCH<7>
JTAG_TDI_PCH<7>
JTAG_TDO_PCH<7>
XDP_TDI_R
JTAG_TCK_PCH<7>
3
HWPG<4,28,30,31,32>
R513 *0_4
H_SYS_PWROK_XDP
+3V
+3V
XDP_TDO
XDP_TDI_R
XDP_TMS
XDP_TRST#
R515 0_4
R511 *51_4
R510 *0_4
R505 0_4 R166 0_4
R538 0_4
R516 0_4
R512 0_4
R506 *0_4
R502 0_4
R170 *1K_4
C255
0.1U/10V_4
C566
0.1U/10V_4
U22
14
VCC
2
1A
1
1OE
5
2A
4
2OE
9
3A
10
3OE
12
4A
13
4OE
*SN74CBTLV3126RGYR
XDP_TDI_RXDP_TDI
XDP_TDO
XDP_TCK0
XDP_TMS
XDP_TDI
XDP_TDO
XDP_TCK0
XDP_TCK1
+3V_DEEP_SUS
3
1B
6
2B
8
3B
11
4B
15
DPAD
7
GND
SYS_PWROK<6>
PLTRST#<6,14,23,24,25,27,28>
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
XDP_TDO_CPU <2>
XDP_TDI_CPU <2>
XDP_TMS_CPU <2>
XDP_TRST#_CPU <2,7>
H_SYS_PWROK_XDP
R124 1K_4
PROJECT :U83
PROJECT :U83
PROJECT :U83
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
HSW XDP & APS
HSW XDP & APS
HSW XDP & APS
XDP_RST
ULT
ULT
ULT
1
11 41Thursday, March 14, 2013
11 41Thursday, March 14, 2013
11 41Thursday, March 14, 2013
1A
1A
1A
5
4
3
2
1
M_A_A[15:0]<3>
D D
M_A_BS#0<3>
M_A_BS#1<3>
M_A_BS#2<3>
M_A_CS#0<3>
M_A_CS#1<3>
M_A_CLKP0<3>
M_A_CLKN0<3>
M_A_CLKP1<3>
M_A_CLKN1<3>
M_A_CKE0<3>
M_A_CKE1<3>
M_A_CAS#<3>
M_A_RAS#<3>
R207 10K/F_4
R208 10K/F_4
C C
M_A_WE#<3>
SMB_RUN_CLK<8,11,13,20,25>
SMB_RUN_DAT<8,11,13,20,25>
M_A_ODT0<13>
M_A_ODT1<13>
M_A_DQSP[7:0]<3>
M_A_DQSN[7:0]<3>
CPU Bracket
B B
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
DIMM0_SA0
DIMM0_SA1
SMB_RUN_CLK
SMB_RUN_DAT
M_A_DQSP0
M_A_DQSP1
M_A_DQSP2
M_A_DQSP3
M_A_DQSP4
M_A_DQSP5
M_A_DQSP6
M_A_DQSP7
M_A_DQSN0
M_A_DQSN1
M_A_DQSN2
M_A_DQSN3
M_A_DQSN4
M_A_DQSN5
M_A_DQSN6
M_A_DQSN7
JDIM2A
98
A0
97
A1
96
A2
95
A3
92
A4
91
A5
90
A6
86
A7
89
A8
85
A9
107
A10/AP
84
A11
83
A12/BC#
119
A13
80
A14
78
A15
109
BA0
108
BA1
79
BA2
114
S0#
121
S1#
101
CK0
103
CK0#
102
CK1
104
CK1#
73
CKE0
74
CKE1
115
CAS#
110
RAS#
113
WE#
197
SA0
201
SA1
202
SCL
200
SDA
116
ODT0
120
ODT1
11
DM0
28
DM1
46
DM2
63
DM3
136
DM4
153
DM5
170
DM6
187
DM7
12
DQS0
29
DQS1
47
DQS2
64
DQS3
137
DQS4
154
DQS5
171
DQS6
188
DQS7
10
DQS#0
27
DQS#1
45
DQS#2
62
DQS#3
135
DQS#4
152
DQS#5
169
DQS#6
186
DQS#7
DDR3-DIMM0_H=4.0_STD
ddr-ddrsk-20401-tp4b-204p-ldv
DGMK4000326
IC SOCKET DDR3 SODIMM(204P,H4.0,STD)
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
(204P)
PC2100 DDR3 SDRAM SO-DIMM
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
EZIW
5
M_A_DQ5
7
M_A_DQ4
15
M_A_DQ6
17
M_A_DQ2
4
M_A_DQ1
6
M_A_DQ0
16
M_A_DQ7
18
M_A_DQ3
21
M_A_DQ13
23
M_A_DQ12
33
M_A_DQ14
35
M_A_DQ15
22
M_A_DQ9
24
M_A_DQ8
34
M_A_DQ11
36
M_A_DQ10
39
M_A_DQ21
41
M_A_DQ20
51
M_A_DQ19
53
M_A_DQ23
40
M_A_DQ17
42
M_A_DQ16
50
M_A_DQ18
52
M_A_DQ22
57
M_A_DQ24
59
M_A_DQ25
67
M_A_DQ31
69
M_A_DQ27
56
M_A_DQ28
58
M_A_DQ29
68
M_A_DQ30
70
M_A_DQ26
129
M_A_DQ36
131
M_A_DQ33
141
M_A_DQ34
143
M_A_DQ35
130
M_A_DQ32
132
M_A_DQ37
140
M_A_DQ38
142
M_A_DQ39
147
M_A_DQ44
149
M_A_DQ45
157
M_A_DQ46
159
M_A_DQ42
146
M_A_DQ40
148
M_A_DQ41
158
M_A_DQ47
160
M_A_DQ43
163
M_A_DQ49
165
M_A_DQ52
175
M_A_DQ50
177
M_A_DQ51
164
M_A_DQ55
166
M_A_DQ48
174
M_A_DQ54
176
M_A_DQ53
181
M_A_DQ59
183
M_A_DQ56
191
M_A_DQ63
193
M_A_DQ58
180
M_A_DQ57
182
M_A_DQ60
192
M_A_DQ62
194
M_A_DQ61
M_A_DQ[63:0] <3>
+SMDDR_VREF_DIMM<12,13>
DDR3_DRAMRST#<2,13>
R204 0_6
+3V
PM_EXTTS#0<13>
+1.35VSUS
2.48A
+3V
R198 10K/F_4
PM_EXTTS#0
C320 *0.1U/10V_4
+SMDDR_VREF_DQ0SMDDR_VREF_DQ0_M1
+SMDDR_VREF_DIMM
JDIM2B
75
VDD1
76
VDD2
81
VDD3
82
VDD4
87
VDD5
88
VDD6
93
VDD7
94
VDD8
99
VDD9
100
VDD10
105
VDD11
106
VDD12
111
VDD13
112
VDD14
117
VDD15
118
VDD16
123
VDD17
124
VDD18
199
VDDSPD
77
NC1
122
NC2
125
NCTEST
198
EVENT#
30
RESET#
1
VREF_DQ
126
VREF_CA
2
VSS1
3
VSS2
8
VSS3
9
VSS4
13
VSS5
14
VSS6
19
VSS7
20
VSS8
25
VSS9
26
VSS10
31
VSS11
32
VSS12
37
VSS13
38
VSS14
43
VSS15
DDR3-DIMM0_H=4.0_STD
ddr-ddrsk-20401-tp4b-204p-ldv
DGMK4000326
IC SOCKET DDR3 SODIMM(204P,H4.0,STD)
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
(204P)
PC2100 DDR3 SDRAM SO-DIMM
VTT1
VTT2
GND
GND
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
203
204
205
206
+SMDDR_VREF_DIMM<12,13>
+0.75V_DDR_VTT
+1.35VSUS<2,4,13,25,32>
+0.75V_DDR_VTT<13,32>
+3V<6,7,8,9,10,11,13,14,20,21,22,23,24,25,26,27,28,33,34,35>
12
1uF/10uF 4pcs on each side of connector
Place these Caps near So-Dimm0.
For EMI RESERVE
+1.35VSUS
EC5 *120P/50V_4
EC6 *120P/50V_4
EC7 *120P/50V_4
EC35 120P/50V_4
EC10 *120P/50V_4
EC9 *120P/50V_4
A A
5
+0.75V_DDR_VTT
EC12 *120P/50V_4
EC11 *120P/50V_4
+1.35VSUS
EC14 *120P/50V_4
EC15 *120P/50V_4
EC16 *120P/50V_4
EC4 *0.1U/10V_4
EC13 *0.1U/10V_4
EC43 *0.1U/10V_4EC8 *120P/50V_4
EC42 *0.1U/10V_4
4
+1.35VSUS +0.75V_DDR_VTT
C324 1U/6.3V_4
C330 1U/6.3V_4
C325 1U/6.3V_4
C311 1U/6.3V_4
C313 1U/6.3V_4
C312 1U/6.3V_4
C310 1U/6.3V_4
C309 1U/6.3V_4
C329 10U/6.3V_6
C327 10U/6.3V_6
C326 10U/6.3V_6
C314 10U/6.3V_6
C315 10U/6.3V_6
C340 10U/6.3V_6
C323 10U/6.3V_6
C343 10U/6.3V_6
+SMDDR_VREF_DIMM
+SMDDR_VREF_DQ0
3
C333 1U/6.3V_4
C328 1U/6.3V_4
C318 1U/6.3V_4
C322 1U/6.3V_4
C319 10U/6.3V_6
C335 *0.1U/10V_4
C332 *2.2U/6.3V_6
C307 *0.1U/10V_4
C316 *2.2U/6.3V_6
+3V
C302 0.1U/10V_4
C308 2.2U/6.3V_6
DDR_VTTREF<13,32>
SMDDR_VREF_DQ0_M3<3>
2
DDR_VTTREF
SMDDR_VREF_DQ0_M3
R205
24.9/F_4
DDR_VTTREF
R200 *0_6
R203 2/F_6
C317
0.022U/25V_4
2 1
SM_VREF<3>
+1.35VSUS
VREF DQ0 M1 Solution
R202
1.8K/F_4
SMDDR_VREF_DQ0_M1
R201
1.8K/F_4
R214 *0_6
R217 2/F_6
C347
0.022U/25V_4
2 1
R220
24.9/F_4
PROJECT :U83
PROJECT :U83
PROJECT :U83
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
DDR3 DIMM0-STD(4.0H)
DDR3 DIMM0-STD(4.0H)
DDR3 DIMM0-STD(4.0H)
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
+1.35VSUS
R215
1.8K/F_4
+SMDDR_VREF_DIMM
R213
1.8K/F_4
12 41Thursday, March 14, 2013
12 41Thursday, March 14, 2013
12 41Thursday, March 14, 2013
1A
1A
1A
5
M_B_A[15:0]<3>
D D
M_B_BS#0<3>
M_B_BS#1<3>
M_B_BS#2<3>
M_B_CS#0<3>
M_B_CS#1<3>
M_B_CLKP0<3>
M_B_CLKN0<3>
M_B_CLKP1<3>
M_B_CLKN1<3>
M_B_CKE0<3>
M_B_CKE1<3>
M_B_CAS#<3>
M_B_RAS#<3>
R189 10K/F_4
R190 10K/F_4
+3V
C C
B B
M_B_WE#<3>
SMB_RUN_CLK<8,11,12,20,25>
SMB_RUN_DAT<8,11,12,20,25>
M_B_DQSP[7:0]<3>
M_B_DQSN[7:0]<3>
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
DIMM1_SA0
DIMM1_SA1
M_B_ODT0
M_B_ODT1
M_B_DQSP2
M_B_DQSP0
M_B_DQSP1
M_B_DQSP3
M_B_DQSP4
M_B_DQSP5
M_B_DQSP6
M_B_DQSP7
M_B_DQSN2
M_B_DQSN0
M_B_DQSN1
M_B_DQSN3
M_B_DQSN4
M_B_DQSN5
M_B_DQSN6
M_B_DQSN7
98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
109
108
79
114
121
101
103
102
104
73
74
115
110
113
197
201
202
200
116
120
11
28
46
63
136
153
170
187
12
29
47
64
137
154
171
188
10
27
45
62
135
152
169
186
4
JDIM1A
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15
BA0
BA1
BA2
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE#
SA0
SA1
SCL
SDA
ODT0
ODT1
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
PC2100 DDR3 SDRAM SO-DIMM
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7
DDR3-DIMM1_H=4.0_RVS
ddr-ddrrk-20401-tp4b-204p-ruv
DGMK4000263
IC SOCKET DDR3 SODIMM (204P, H4.0, RVS)
5
DQ0
7
DQ1
15
DQ2
17
DQ3
4
DQ4
6
DQ5
16
DQ6
18
DQ7
21
DQ8
23
DQ9
33
DQ10
35
DQ11
22
DQ12
24
DQ13
34
DQ14
36
DQ15
39
DQ16
41
DQ17
51
DQ18
53
DQ19
40
DQ20
42
DQ21
50
DQ22
52
DQ23
57
DQ24
59
DQ25
67
DQ26
69
DQ27
56
DQ28
58
DQ29
68
DQ30
70
DQ31
129
DQ32
131
DQ33
141
DQ34
143
DQ35
130
DQ36
132
DQ37
140
DQ38
142
DQ39
147
DQ40
149
DQ41
157
DQ42
159
DQ43
146
DQ44
148
DQ45
158
DQ46
160
(204P)
DQ47
163
DQ48
165
DQ49
175
DQ50
177
DQ51
164
DQ52
166
DQ53
174
DQ54
176
DQ55
181
DQ56
183
DQ57
191
DQ58
193
DQ59
180
DQ60
182
DQ61
192
DQ62
194
DQ63
M_B_DQ22
M_B_DQ23
M_B_DQ21
M_B_DQ18
M_B_DQ16
M_B_DQ17
M_B_DQ20
M_B_DQ19
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ2
M_B_DQ3
M_B_DQ1
M_B_DQ0
M_B_DQ9
M_B_DQ8
M_B_DQ11
M_B_DQ10
M_B_DQ12
M_B_DQ13
M_B_DQ15
M_B_DQ14
M_B_DQ26
M_B_DQ27
M_B_DQ29
M_B_DQ28
M_B_DQ30
M_B_DQ31
M_B_DQ24
M_B_DQ25
M_B_DQ32
M_B_DQ33
M_B_DQ38
M_B_DQ34
M_B_DQ36
M_B_DQ37
M_B_DQ35
M_B_DQ39
M_B_DQ40
M_B_DQ43
M_B_DQ47
M_B_DQ46
M_B_DQ41
M_B_DQ42
M_B_DQ44
M_B_DQ45
M_B_DQ52
M_B_DQ51
M_B_DQ54
M_B_DQ48
M_B_DQ49
M_B_DQ55
M_B_DQ50
M_B_DQ53
M_B_DQ63
M_B_DQ62
M_B_DQ59
M_B_DQ60
M_B_DQ56
M_B_DQ57
M_B_DQ61
M_B_DQ58
3
M_B_DQ[63:0] <3>
2
2.48A
PM_EXTTS#0<12>
DDR3_DRAMRST#<2,12>
SMDDR_VREF_DQ1_M1 +SMDDR_VREF_DQ1
+SMDDR_VREF_DIMM<12>
R199 0_6
C321 *0.1U/10V_4
Local Thermal Sensor
R185 *10K/F_4
+3V
MBCLK2
MBDATA2
PM_EXTTS#0
MBCLK2<8,20,28>
MBDATA2<8,20,28>
+1.35VSUS
+3V
PM_EXTTS#0
8
7
6
4
JDIM1B
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
199
77
122
125
198
30
1
126
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
DDR3-DIMM1_H=4.0_RVS
ddr-ddrrk-20401-tp4b-204p-ruv
DGMK4000263
IC SOCKET DDR3 SODIMM (204P, H4.0, RVS)
U3
VCC
SCLK
DXP
SDA
DXN
ALERT#
GND
OVERT#
*EMC1412-1-ACZL-TR
Need Check PN(EOD)
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDDSPD
NC1
NC2
NCTEST
EVENT#
RESET#
VREF_DQ
VREF_CA
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
1
2
3
5
1
44
VSS16
48
VSS17
49
VSS18
54
VSS19
55
VSS20
60
VSS21
61
VSS22
65
VSS23
66
VSS24
71
VSS25
72
VSS26
127
VSS27
128
VSS28
133
VSS29
134
VSS30
138
VSS31
139
VSS32
144
VSS33
145
VSS34
150
VSS35
151
VSS36
155
VSS37
156
VSS38
161
VSS39
162
VSS40
167
VSS41
168
VSS42
172
VSS43
173
VSS44
178
VSS45
179
VSS46
184
VSS47
185
VSS48
189
VSS49
190
VSS50
195
VSS51
196
VSS52
(204P)
PC2100 DDR3 SDRAM SO-DIMM
C271 *0.01U/16V_4
203
VTT1
204
VTT2
205
GND
206
GND
DDR_THERMDA
C272
*2200P/50V_4
DDR_THERMDC
+0.75V_DDR_VTT
+3V
DDR3 Thermal Sensor
2
Q2
*METR3904-G
1 3
Main:AL001412003 EMC1412-1-ACZL-TR(98h)
13
2nd:AL000431014 TMP431ADGKR(98h)
+5VPCU
R212
100K_4
DTC144EUA
2
A A
DDR_PG_CNTL
1 3
C336
0.1U/10V_4
2
1
Q4
2N7002K
DDR_PG_CNTL <2>
5
3
+1.35VSUS+5VS5
R218
220K_4
DDR_VTT_PG_CTRL
R216 *0_4
R219
*2M/F_4
2N7002
Q3
3
51216S3 <32>
2
1
R209 66.5/F_4
R210 66.5/F_4
R195 66.5/F_4
R194 66.5/F_4
+0.75V_DDR_VTT<12,32>
4
M_A_ODT0 <12>
M_A_ODT1 <12>
M_B_ODT0
M_B_ODT1
+1.35VSUS<2,4,12,25,32>
+3V<6,7,8,9,10,11,12,14,20,21,22,23,24,25,26,27,28,33,34,35>
+1.35VSUS
Place these Caps near So-Dimm1.
1uF/10uF 4pcs on each side of connector
C303 1U/6.3V_4
C306 1U/6.3V_4
C341 1U/6.3V_4
C304 1U/6.3V_4
C301 1U/6.3V_4
C300 1U/6.3V_4
C305 1U/6.3V_4
C299 1U/6.3V_4
C287 10U/6.3V_6
C292 10U/6.3V_6
C284 10U/6.3V_6
C283 10U/6.3V_6
C286 10U/6.3V_6
C285 10U/6.3V_6
C291 10U/6.3V_6
C294 10U/6.3V_6
+0.75V_DDR_VTT
C293 1U/6.3V_4Q5
C297 1U/6.3V_4
C289 1U/6.3V_4
C295 1U/6.3V_4
C288 10U/6.3V_6
+3V
C281 0.1U/10V_4
C282 2.2U/6.3V_6
3
+SMDDR_VREF_DIMM
C280 *0.1U/10V_4
C279 *2.2U/6.3V_6
+SMDDR_VREF_DQ1
C296 *0.1U/10V_4
C298 *2.2U/6.3V_6
1
+1.35VSUS
R187
1.8K/F_4
SMDDR_VREF_DQ1_M1DDR_VTTREF
R188
1.8K/F_4
1A
1A
1A
13 41Thursday, March 14, 2013
13 41Thursday, March 14, 2013
13 41Thursday, March 14, 2013
VREF DQ1 M1 Solution
DDR_VTTREF<12,32>
SMDDR_VREF_DQ1_M3<3>
2
SMDDR_VREF_DQ1_M3
R193 24.9/F_4
R192 *0_6
R191 2/F_6
C290
0.022U/25V_4
2 1
PROJECT :U83
PROJECT :U83
PROJECT :U83
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
DDR3 DIMM1-RVS(4.0H)
DDR3 DIMM1-RVS(4.0H)
DDR3 DIMM1-RVS(4.0H)
Date: Sheet of
Date: Sheet of
Date: Sheet of
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