Quanta TWL Schematic
5
www.schematic-x.blogspot.com
4
3
2
1
01
TWL + JWL Intel SKYLAKE-U Platform Block Diagram
D D
DDR3L SO-DIMM-0
Maxima 8GBs
Front Side / REV Type
DDR3L SO-DIMM-1
Maxima 8GBs
Rear Side / STD Type
SATA HDD
Package : 9.5 (mm)
TWL
SATA ODD Board
C C
USB3.0 Port
Left / Front Side
PAGE 33
PAGE 32
SATA ODD
Package : 12.7 (mm)
NGFF SSD
Package : 2280 & 2242
Full mini-PCIe Card - SSD
TPS2546
Package : QFN-16
PAGE 32
PAGE 17
PAGE 18
PAGE 33
PAGE 33
PAGE 31
USB3.0 Port-1 & USB2.0 Port-1
DDR3L CH-A
DDR3L CH-B
SATA0 6GB/s Port-0
SATA1 3GB/s Port-1
SATA2 6GB/s Port-2
Skylake-U
ES sample
QHMF - AJ0QHMFUT03
CPU(1356P)ULV 2.3G
QHMF(BGA)
QHMG - AJ0QHMGVT03
CPU(1356P)ULV 1.6G
QHMG(BGA)
Processor : Daul Core
TDP : 15 (Watt)
Package : BGA, 1356-PIN
BGA1356
Size : 42 X 24 X 1.213 (mm)
PCI-e
X4 Lane
Port-1~4
eDP X 2
eDP Port-0 & 1
DDI Port-1
DDI Port-2
NVIDIA
N16V-GM / GT920M
N16S-GT / GT940M
Power : 25 (Watt)
Package : S3
Size : 23 x 23 (mm)
PAGE-19~22
27MHz
RTD2136
Package : QFN-32
eDP
ANX6210
Package : QFN-40
27MHz
1-Channel
64Bit
PAGE 24
PAGE 24
PAGE 26
Graphics 4Gb/2Gb
DDR3L SDRAM
1.0GHz / 16-Bit
PAGE-23
JWL Panel
TWL
Panel (2-CH)
PAGE 25
Camera
USB2.0 Port-3
PAGE 25
HDMI
PAGE 25
CRT
PAGE 26
JWL
USB3.0 Port
Left / Rear Side
PAGE 32
USB Board
B B
USB2.0 Port USB2.0 Port-6
Right Side
PAGE 27
Combo Jack
Ext. Headphone & MIC
PAGE 27
Speaker
4Ω , Normal 1.5W
PAGE 27
Digital MIC
with Camera
A A
PAGE 25
USB3.0 Port-2 & USB2.0 Port-2
Audio Codec
ALC255-CG
Package : MQFN48
Size : 6 x 6 (mm)
w w w . c h i n a f i x . c o m
PAGE 27
Azalia
SPI
System BIOS
& EC F/W
PAGE 10
PCIE Gen 1 x 1 Lane Port-5
PCIE Gen 1 x 1 Lane Port-9
PCIE Gen 1 x 1 Lane Port-6
PAGE-2~16
LPC
Embedded ControllerSPI ROM 16MByte
IC CTRL(128P) IT8987E/BX(LQFP)
Package : LQFP Size : 16 x 16 (mm)
PAGE 35
Card Reader
Package : QFN32 Size : 4 x 4 (mm)
LAN Controller
Package : OFN32
NGFF WLAN
Half mini-PCIe Card
WLAN & BT Combo Card
USB2.0 Port-5
JWL Power Button Board
TWL Power Button Board
LID Switch
RTS5227S-GRT
PAGE 29
RTL8111H-CG(Giga)
PAGE 28
Package : 2230
PAGE 30
PAGE 33
TWL
Card Slot
SD Card
MMC Card
RJ45
PCB 6L STACK UP
LAYER-1 : TOP
LAYER-2 : SGND
LAYER-3 : IN1(High)
LAYER-4 : IN2(Low)
LAYER-5 : SVCC
LAYER-6 : BOT
5
JWL
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Keyboard
PAGE 34
4
Touch Pad
PAGE 34
3
FAN
PAGE 33
TWL
BATTERY
PAGE 37
C
C
C
Date:
Date:
Date:
2
Quanta Computer Inc.Quanta Computer Inc.
PROJECT : TWL & JWL ( MB )
PROJECT : TWL & JWL ( MB )
PROJECT : TWL & JWL ( MB )
Document Number
Document Number
Document Number
Block Diagram
Block Diagram
Block Diagram
Wednesday, July 29, 2015
Wednesday, July 29, 2015
Wednesday, July 29, 2015
Sheet :
Sheet :
Sheet :
1
of
of
of
1 51
1 51
1 51
Rev.Size
Rev.Size
Rev.Size
3C
3C
3C
5
4
3
2
1
U25A
IN_D2#[25]
IN_D2[25]
IN_D1#[25]
IN_D1[25]
HDMI
D D
CRT
+3V
IN_D0#[25]
IN_D0[25]
IN_CLK#[25]
IN_CLK[25]
DDI2_CRT_TX0N[26]
DDI2_CRT_TX0P[26]
20150309A-DDPC_CTRLDATA
This signal needs to be pulled up
through a 2.2 KΩ ±5% pull-up to
3.3V to enable Port -C.
R125
2.2K_4
R123
*2.2K_4
+VCCIO
R173 24.9/F_4
TP20
SDVO_CLK[25]
SDVO_DATA[25]
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPD_CTRLDATA
EDP_RCOMP
X1B 1218 change connection from +1.0V to +VCCIO.
E55
DDI1_TXN[0]
F55
DDI1_TXP[0]
E58
DDI1_TXN[1]
F58
DDI1_TXP[1]
F53
DDI1_TXN[2]
G53
DDI1_TXP[2]
F56
DDI1_TXN[3]
G56
DDI1_TXP[3]
C50
DDI2_TXN[0]
D50
DDI2_TXP[0]
C52
DDI2_TXN[1]
D52
DDI2_TXP[1]
A50
DDI2_TXN[2]
B50
DDI2_TXP[2]
D51
DDI2_TXN[3]
C51
DDI2_TXP[3]
L13
GPP_E18/DDPB_CTRLCLK
L12
GPP_E19/DDPB_CTRLDATA
N7
GPP_E20/DDPC_CTRLCLK
N8
GPP_E21/DDPC_CTRLDATA
N11
GPP_E22/DDPD_CTRLCLK
N12
GPP_E23/DDPD_CTRLDATA
E52
EDP_RCOMP
*SKL_ULT
SKL_ULT
DDI
CRT
DISPLAY SIDEBANDS
eDP/LVDSHDMI
EDP
GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3
EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]
EDP_AUXN
EDP_AUXP
EDP_DISP_UTIL
DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
DDI3_AUXN
DDI3_AUXP
GPP_E17/EDP_HPD
EDP_BKLTEN
EDP_BKLTCTL
EDP_VDDEN
1 OF 20REV = 1
C47
C46
D46
C45
A45
B45
A47
B47
E45
F45
B52
G50
F50
E48
F48
G46
F46
L9
L7
L6
N9
L10
R12
R11
U13
EDP_DISP_UTIL
DDI2_CRT_HPD_Q [26]
INT_EDP_TXN0 [24]
INT_EDP_TXP0 [24]
INT_EDP_TXN1 [24]
INT_EDP_TXP1 [24]
INT_EDP_AUXN [24]
INT_EDP_AUXP [24]
TP88
DDI2_CRT_AUXN [26]
DDI2_CRT_AUXP [26]
HDMI_HPD_CON [25]
PCH_LVDS_BLON [25]
PCH_DPST_PWM [24,25]
PCH_DISP_ON [25]
eDP or LVDS
+3V
R163
*10K/F_4
ULT_EDP_HPD [24,25]
R162
100K_4
02
Reserve EDP_HPD opposites circuit !
EDP_HPD need pull down via 100KΩ.
eDP_COMPIO and ICOMPO signals should be shorted near
C C
balls and routed with typical impedance < 25 mΩ.
PLACE NEAR CPU
R489 51_4
R143 *51_4
R497 *51_4
1218 Unmount R380, R367
+VCCSTPLL
B B
H_PROCHOT#[35,37,42]
Close to EC
Processor pull-up (CPU)
TO BE REPLACED WITH 1K OHMS
FOR SKL . 470 OHM IS FOR I/P
PM_THRMTRIP#[35]
+1.0V
R479
1K_4
+VCCSTPLL
R453
1K_4
R485 499/F_4
TP13
EC_PECI[35]
XDP_BPM0[16]
XDP_BPM1[16]
TP86
TP87
TP132
TP129
R262 49.9/F_4
R259 49.9/F_4
R520 49.9/F_4
R519 49.9/F_4
X1B-1223 change to un-mount.
R137
*49.9/F_4
CATERR#
EC_PECI
PROCHOT#
PM_THRMTRIP#
3D_FW_GPIO_R
CPU_GP1
CPU_GP2
CPU_GP3
PROC_POPIRCOMP
PCH_OPI_RCOMP
EDRAM_OPIO_RCOMP
EOPIO_RCOMP
D63
CATERR#
A54
PECI
C65
PROCHOT#
C63
THERMTRIP#
A65
SKTOCC#
C55
BPM#[0]
D55
BPM#[1]
B54
BPM#[2]
C56
BPM#[3]
A6
GPP_E3/CPU_GP0
A7
GPP_E7/CPU_GP1
BA5
GPP_B3/CPU_GP2
AY5
GPP_B4/CPU_GP3
AT16
PROC_POPIRCOMP
AU16
PCH_OPIRCOMP
H66
OPCE_RCOMP
H65
OPC_RCOMP
*SKL_ULT
U25D
SKL_ULT
CPU MISC
JTAG
PROC_TCK
PROC_TDI
PROC_TDO
PROC_TMS
PROC_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_TRST#
BOM
4 OF 20REV = 1
JTAGX
B61
D60
A61
C60
B59
B56
D59
A56
C59
C61
A59
R493 *51_4
R492 51_4
R488 51_4
R144 51_4
R487 51_4
R450 51_4
R451 *51_4
+1.0V
+1.0V
+1.0V
XDP_TCK0 [16]
XDP_TDI_CPU [16]
XDP_TDO_CPU [16]
XDP_TMS_CPU [16]
XDP_TRST#_CPU [16]
JTAG_TCK_PCH [16]
JTAG_TDI_PCH [16]
JTAG_TDO_PCH [16]
JTAG_TMS_PCH [16]
JTAGX_PCH [16]
+1.0V
R449 0_4
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
+1.0V
+3V
+VCCIO
+VCCSTPLL
+1.0V [4,6,16,32,35,41]
+3V [4,10,11,12,13,14,15,16,17,18,19,21,22,24,25,26,27,28,29,30,31,33,34,35,36,42,44,45,46]
+VCCIO [6,16,41]
+VCCSTPLL [4,5,6,9,41,42]
5
PROJECT : TWL & JWL ( MB )
PROJECT : TWL & JWL ( MB )
PROJECT : TWL & JWL ( MB )
Document Number
Document Number
Document Number
SKL-01 (eDP/DDI/MISC)
SKL-01 (eDP/DDI/MISC)
Custom
Custom
Custom
Date:
Date:
Date:
4
3
2
SKL-01 (eDP/DDI/MISC)
Wednesday, July 29, 2015
Wednesday, July 29, 2015
Wednesday, July 29, 2015
Sheet :
Sheet :
Sheet :
1
of
of
of
2 51
2 51
2 51
Rev.Size
Rev.Size
Rev.Size
3C
3C
3C
5
M_A_DQSN[7:0][17]
M_A_DQSP[7:0][17]
M_B_DQSN[7:0][18]
M_B_DQSP[7:0][18]
M_A_DQ[63:0][17]
M_B_DQ[63:0][18]
4
3
2
1
03
D D
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
A0
A1
C C
B0
B1
A2
A3
B B
B2
B3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
SkyLake ULT Processor (DDR3L)
U25B
AL71
DDR0_DQ[0]
AL68
DDR0_DQ[1]
AN68
DDR0_DQ[2]
AN69
DDR0_DQ[3]
AL70
DDR0_DQ[4]
AL69
DDR0_DQ[5]
AN70
DDR0_DQ[6]
AN71
DDR0_DQ[7]
AR70
DDR0_DQ[8]
AR68
DDR0_DQ[9]
AU71
DDR0_DQ[10]
AU68
DDR0_DQ[11]
AR71
DDR0_DQ[12]
AR69
DDR0_DQ[13]
AU70
DDR0_DQ[14]
AU69
DDR0_DQ[15]
AF65
DDR1_DQ[0]/DDR0_DQ[16]
AF64
DDR1_DQ[1]/DDR0_DQ[17]
AK65
DDR1_DQ[2]/DDR0_DQ[18]
AK64
DDR1_DQ[3]/DDR0_DQ[19]
AF66
DDR1_DQ[4]/DDR0_DQ[20]
AF67
DDR1_DQ[5]/DDR0_DQ[21]
AK67
DDR1_DQ[6]/DDR0_DQ[22]
AK66
DDR1_DQ[7]/DDR0_DQ[23]
AF70
DDR1_DQ[8]/DDR0_DQ[24]
AF68
DDR1_DQ[9]/DDR0_DQ[25]
AH71
DDR1_DQ[10]/DDR0_DQ[26]
AH68
DDR1_DQ[11]/DDR0_DQ[27]
AF71
DDR1_DQ[12]/DDR0_DQ[28]
AF69
DDR1_DQ[13]/DDR0_DQ[29]
AH70
DDR1_DQ[14]/DDR0_DQ[30]
AH69
DDR1_DQ[15]/DDR0_DQ[31]
BB65
DDR0_DQ[16]/DDR0_DQ[32]
AW65
DDR0_DQ[17]/DDR0_DQ[33]
AW63
DDR0_DQ[18]/DDR0_DQ[34]
AY63
DDR0_DQ[19]/DDR0_DQ[35]
BA65
DDR0_DQ[20]/DDR0_DQ[36]
AY65
DDR0_DQ[21]/DDR0_DQ[37]
BA63
DDR0_DQ[22]/DDR0_DQ[38]
BB63
DDR0_DQ[23]/DDR0_DQ[39]
BA61
DDR0_DQ[24]/DDR0_DQ[40]
AW61
DDR0_DQ[25]/DDR0_DQ[41]
BB59
DDR0_DQ[26]/DDR0_DQ[42]
AW59
DDR0_DQ[27]/DDR0_DQ[43]
BB61
DDR0_DQ[28]/DDR0_DQ[44]
AY61
DDR0_DQ[29]/DDR0_DQ[45]
BA59
DDR0_DQ[30]/DDR0_DQ[46]
AY59
DDR0_DQ[31]/DDR0_DQ[47]
AT66
DDR1_DQ[16]/DDR0_DQ[48]
AU66
DDR1_DQ[17]/DDR0_DQ[49]
AP65
DDR1_DQ[18]/DDR0_DQ[50]
AN65
DDR1_DQ[19]/DDR0_DQ[51]
AN66
DDR1_DQ[20]/DDR0_DQ[52]
AP66
DDR1_DQ[21]/DDR0_DQ[53]
AT65
DDR1_DQ[22]/DDR0_DQ[54]
AU65
DDR1_DQ[23]/DDR0_DQ[55]
AT61
DDR1_DQ[24]/DDR0_DQ[56]
AU61
DDR1_DQ[25]/DDR0_DQ[57]
AP60
DDR1_DQ[26]/DDR0_DQ[58]
AN60
DDR1_DQ[27]/DDR0_DQ[59]
AN61
DDR1_DQ[28]/DDR0_DQ[60]
AP61
DDR1_DQ[29]/DDR0_DQ[61]
AT60
DDR1_DQ[30]/DDR0_DQ[62]
AU60
DDR1_DQ[31]/DDR0_DQ[63]
*SKL_ULT
SKL_ULT
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]
DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]
DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]
DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSP[2]/DDR0_DQSP[4]
DDR0_DQSN[3]/DDR0_DQSN[5]
DDR0_DQSP[3]/DDR0_DQSP[5]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSP[3]/DDR0_DQSP[7]
NIL-DDR CH A
DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]
DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]
DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]
DDR0_ODT[1]
DDR0_MA[3]
DDR0_MA[4]
DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSP[1]
DDR0_ALERT#
DDR0_PAR
DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ
DDR_VTT_CNTL
2 OF 20REV = 1
AU53
AT53
AU55
AT55
BA56
BB56
AW56
AY56
AU45
AU43
AT45
AT43
BA51
BB54
BA52
AY52
AW52
AY55
AW54
BA54
BA55
AY54
AU46
AU48
AT46
AU50
AU52
AY51
AT48
AT50
BB50
AY50
BA50
BB52
AM70
AM69
AT69
AT70
AH66
AH65
AG69
AG70
BA64
AY64
AY60
BA60
AR66
AR65
AR61
AR60
AW50
AT52
AY67
AY68
BA67
AW67
M_A_DQSN0
M_A_DQSP0
M_A_DQSN1
M_A_DQSP1
M_B_DQSN0
M_B_DQSP0
M_B_DQSN1
M_B_DQSP1
M_A_DQSN2
M_A_DQSP2
M_A_DQSN3
M_A_DQSP3
M_B_DQSN2
M_B_DQSP2
M_B_DQSN3
M_B_DQSP3
DDR0_PAR
M_A_CLKN0 [17]
M_A_CLKP0 [17]
M_A_CLKN1 [17]
M_A_CLKP1 [17]
M_A_CKE0 [17]
M_A_CKE1 [17]
M_A_CS#0 [17]
M_A_CS#1 [17]
M_A_DIM0_ODT0 [17]
M_A_DIM0_ODT1 [17] M_B_DIM0_ODT0 [18]
M_A_A5 [17]
M_A_A9 [17]
M_A_A6 [17]
M_A_A8 [17]
M_A_A7 [17]
M_A_BS#2 [17]
M_A_A12 [17]
M_A_A11 [17]
M_A_A15 [17]
M_A_A14 [17]
M_A_A13 [17]
M_A_CAS# [17]
M_A_WE# [17]
M_A_RAS# [17]
M_A_BS#0 [17]
M_A_A2 [17]
M_A_BS#1 [17]
M_A_A10 [17]
M_A_A1 [17]
M_A_A0 [17]
M_A_A3 [17]
M_A_A4 [17]
TP47
SMDDR_VREF_DQ0_M3 [3,17]
SMDDR_VREF_DQ1_M3 [3,18]
SM_VREF [3,17]
DDR_VTT_CNTL [4,18]
20mils width
A4
A5
B4
B5
A6
A7
B6
B7
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
U25C
AY39
DDR0_DQ[32]/DDR1_DQ[0]
AW39
DDR0_DQ[33]/DDR1_DQ[1]
AY37
DDR0_DQ[34]/DDR1_DQ[2]
AW37
DDR0_DQ[35]/DDR1_DQ[3]
BB39
DDR0_DQ[36]/DDR1_DQ[4]
BA39
DDR0_DQ[37]/DDR1_DQ[5]
BA37
DDR0_DQ[38]/DDR1_DQ[6]
BB37
DDR0_DQ[39]/DDR1_DQ[7]
AY35
DDR0_DQ[40]/DDR1_DQ[8]
AW35
DDR0_DQ[41]/DDR1_DQ[9]
AY33
DDR0_DQ[42]/DDR1_DQ[10]
AW33
DDR0_DQ[43]/DDR1_DQ[11]
BB35
DDR0_DQ[44]/DDR1_DQ[12]
BA35
DDR0_DQ[45]/DDR1_DQ[13]
BA33
DDR0_DQ[46]/DDR1_DQ[14]
BB33
DDR0_DQ[47]/DDR1_DQ[15]
AU40
DDR1_DQ[32]/DDR1_DQ[16]
AT40
DDR1_DQ[33]/DDR1_DQ[17]
AT37
DDR1_DQ[34]/DDR1_DQ[18]
AU37
DDR1_DQ[35]/DDR1_DQ[19]
AR40
DDR1_DQ[36]/DDR1_DQ[20]
AP40
DDR1_DQ[37]/DDR1_DQ[21]
AP37
DDR1_DQ[38]/DDR1_DQ[22]
AR37
DDR1_DQ[39]/DDR1_DQ[23]
AT33
DDR1_DQ[40]/DDR1_DQ[24]
AU33
DDR1_DQ[41]/DDR1_DQ[25]
AU30
DDR1_DQ[42]/DDR1_DQ[26]
AT30
DDR1_DQ[43]/DDR1_DQ[27]
AR33
DDR1_DQ[44]/DDR1_DQ[28]
AP33
DDR1_DQ[45]/DDR1_DQ[29]
AR30
DDR1_DQ[46]/DDR1_DQ[30]
AP30
DDR1_DQ[47]/DDR1_DQ[31]
AY31
DDR0_DQ[48]/DDR1_DQ[32]
AW31
DDR0_DQ[49]/DDR1_DQ[33]
AY29
DDR0_DQ[50]/DDR1_DQ[34]
AW29
DDR0_DQ[51]/DDR1_DQ[35]
BB31
DDR0_DQ[52]/DDR1_DQ[36]
BA31
DDR0_DQ[53]/DDR1_DQ[37]
BA29
DDR0_DQ[54]/DDR1_DQ[38]
BB29
DDR0_DQ[55]/DDR1_DQ[39]
AY27
DDR0_DQ[56]/DDR1_DQ[40]
AW27
DDR0_DQ[57]/DDR1_DQ[41]
AY25
DDR0_DQ[58]/DDR1_DQ[42]
AW25
DDR0_DQ[59]/DDR1_DQ[43]
BB27
DDR0_DQ[60]/DDR1_DQ[44]
BA27
DDR0_DQ[61]/DDR1_DQ[45]
BA25
DDR0_DQ[62]/DDR1_DQ[46]
BB25
DDR0_DQ[63]/DDR1_DQ[47]
AU27
DDR1_DQ[48]
AT27
DDR1_DQ[49]
AT25
DDR1_DQ[50]
AU25
DDR1_DQ[51]
AP27
DDR1_DQ[52]
AN27
DDR1_DQ[53]
AN25
DDR1_DQ[54]
AP25
DDR1_DQ[55]
AT22
DDR1_DQ[56]
AU22
DDR1_DQ[57]
AU21
DDR1_DQ[58]
AT21
DDR1_DQ[59]
AN22
DDR1_DQ[60]
AP22
DDR1_DQ[61]
AP21
DDR1_DQ[62]
AN21
DDR1_DQ[63]
*SKL_ULT
SKL_ULT
DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]
DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]
DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]
DDR1_ODT[1]
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]
DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSN[5]/DDR1_DQSN[3]
DDR1_DQSP[5]/DDR1_DQSP[3]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSN[7]/DDR1_DQSN[5]
DDR0_DQSP[7]/DDR1_DQSP[5]
NIL-DDR CH B
BOM
DDR1_MA[3]
DDR1_MA[4]
DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]
DDR1_ALERT#
DDR1_PAR
DRAM_RESET#
DDR_RCOMP[0]
DDR_RCOMP[1]
DDR_RCOMP[2]
AN45
AN46
AP45
AP46
AN56
AP55
AN55
AP53
BB42
AY42
BA42
AW42
AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52
BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47
BA38
AY38
AY34
BA34
AT38
AR38
AT32
AR32
BA30
AY30
AY26
BA26
AR25
AR27
AR22
AR21
AN43
AP43
DDR1_PAR
AT13
AR18
SM_RCOMP_0
AT18
SM_RCOMP_1
AU18
SM_RCOMP_2
3 OF 20REV = 1
M_B_CLKN0 [18]
M_B_CLKN1 [18]
M_B_CLKP0 [18]
M_B_CLKP1 [18]
M_A_DQSN4
M_A_DQSP4
M_A_DQSN5
M_A_DQSP5
M_B_DQSN4
M_B_DQSP4
M_B_DQSN5
M_B_DQSP5
M_A_DQSN6
M_A_DQSP6
M_A_DQSN7
M_A_DQSP7
M_B_DQSN6
M_B_DQSP6
M_B_DQSN7
M_B_DQSP7
M_B_CKE0 [18]
M_B_CKE1 [18]
M_B_CS#0 [18]
M_B_CS#1 [18]
M_B_CAS# [18]
M_B_RAS# [18]
M_B_DIM0_ODT1 [18]
M_B_A5 [18]
M_B_A9 [18]
M_B_A6 [18]
M_B_A8 [18]
M_B_A7 [18]
M_B_BS#2 [18]
M_B_A12 [18]
M_B_A11 [18]
M_B_A15 [18]
M_B_A14 [18]
M_B_A13 [18]
M_B_WE# [18]
M_B_BS#0 [18]
M_B_A2 [18]
M_B_BS#1 [18]
M_B_A10 [18]
M_B_A1 [18]
M_B_A0 [18]
M_B_A3 [18]
M_B_A4 [18]
TP45
R244 121/F_4
R257 80.6/F_4
R247 100/F_4
+1.35VSUS
R346
470_4
DDR3_DRAMRST# [17,18]
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
+1.35VSUS
SM_VREF
SMDDR_VREF_DQ0_M3
SMDDR_VREF_DQ1_M3
+1.35VSUS [6,17,18,36,39,41,47]
SMDDR_VREF_DQ0_M3 [3,17]
SMDDR_VREF_DQ1_M3 [3,18]
5
SM_VREF [3,17]
Custom
Custom
Custom
Date:
Date:
Date:
4
3
2
Quanta Computer Inc.Quanta Computer Inc.
PROJECT : TWL & JWL ( MB )
PROJECT : TWL & JWL ( MB )
PROJECT : TWL & JWL ( MB )
Document Number
Document Number
Document Number
SKL-02 (DDR3L)
SKL-02 (DDR3L)
SKL-02 (DDR3L)
Wednesday, July 29, 2015
Wednesday, July 29, 2015
Wednesday, July 29, 2015
Sheet :
Sheet :
Sheet :
1
of
of
of
3 51
3 51
3 51
Rev.Size
Rev.Size
Rev.Size
3C
3C
3C
5
4
3
2
1
PLTRST#(CLG)
Check Q2010 Rise/Fall time less than 100ns
PLTRST#[16,19,26,28,29,30,33,35]
R264
100K/F_4
SYS_RESET#[16]
+1.0V
21
RSMRST#[35]
R459
1K_4
X1B-1218 Reserve
PU with +VCCSTPLL.
+VCCSTPLL
R458
*1K_4
H_VCCST_PWRGD_R
C703
*10P/50V_4
Close to CPU side
H_VCCST_PWRGD
trace length 0.3" - 1.5"
C717
*0.1U/16V_4
EC72
*220P/50V_4
R499 *10K_4
R457 60.4_4
R462
0_4
R461
10K/F_4
PLTRST#
SYS_RESET#
RSMRST#
PROCPWRGD
H_VCCST_PWRGD
SYS_PWROK
EC_PWROK
DSWROK_EC_R
SUSWARN#
SUSACK#
PCIE_WAKE#
LAN_WAKE#
DDR_VTT_CNTL
U25K
AN10
GPP_B13/PLTRST#
B5
SYS_RESET#
AY17
RSMRST#
A68
PROCPWRGD
B65
VCCST_PWRGD
B6
SYS_PWROK
BA20
PCH_PWROK
BB20
DSW_PWROK
AR13
GPP_A13/SUSWARN#/SUSPWRDNACK
AP11
GPP_A15/SUSACK#
BB15
WAKE#
AM15
GPD2/LAN_WAKE#
AW17
GPD11/LANPHYPC
AT15
GPD7/RSVD
*SKL_ULT
SYSTEM POWER MANAGEMENT
SKL_ULT
200 mS
GPP_B12/SLP_S0#
GPD4/SLP_S3#
GPD5/SLP_S4#
GPD10/SLP_S5#
SLP_SUS#
SLP_LAN#
GPD9/SLP_WLAN#
GPD6/SLP_A#
GPD3/PWRBTN#
GPD1/ACPRESENT
GPD0/BATLOW#
GPP_A11/PME#
INTRUDER#
GPP_B11/EXT_PWR_GATE#
GPP_B2/VRALERT#
11 OF 20REV = 1
AT11
AP15
BA16
AY16
AN15
AW15
BB17
AN16
BA15
AY15
AU13
AU11
AP16
AM10
AM11
PCH_SLP_S0_N
SLP_SUS#_EC
GPD9
DNBSWON#
AC_PRESENT_EC
WLAN_OFF_PCH
INTRUDER#_R
GPP_B2
TP133
R269 1M_4
TP40
PCH_SLP_S0_N [16,35]
AC_PRESENT_EC [35]
WLAN_OFF_PCH [30]
PCH Pull-high/low(CLG)
SUSWARN#
SUSACK#
WLAN_OFF_PCH
PCIE_WAKE#
AC_PRESENT_EC
LAN_WAKE#
SYS_RESET#
RSMRST#
DSWROK_EC
R285 *10K_4
R281 10K_4
R258 10K_4
R563 1K_4
R564 *10K_4
R606 *10K_4
R443 10K_4
R569 10K_4
R570 100K/F_4
SUSB# [16,35]
SUSC# [16,35]
SLP_S5# [16]
SLP_SUS#_EC [35]
SLP_A# [16]
DNBSWON# [35]
+3V_RTC
+3V_DEEP_SUS
+3VS5
SLP_SUS# : For platforms supporting Deep Sx state.
20150521A-X1B SUSWARN# abnormal waveform.
SUSWARN# isn't OD. Remove pull high resistor.
X1B-1127 PU resistor for SUSACK# change to stuff .
20150520A-X61 auto-wake issue.
LAN_WAKE# need to be pull high +3VPCU or +3VS5.
( LAN_WAKE# need pull high DSW power plane.
+3V
Commercial is +3VPCU, but consumer is +3VS5. )
D D
D8
RB500V-40
HWPG[16,35,38,39,40]
R177
100K_4
Q16
METR3904-G
+3VS5+1.0V
R175
10K_4
HWPG
3
Q15
2
2N7002K
1
R176
100K_4
+5VS5
R182
15K/F_4
C C
+1.0V_PWRGD_G2
2
1 3
C293
0.1U/16V_4
+1.0V_PWRGD_G1
R185
100K_4
System PWR_OK(CLG)
SYS_PWROK[16]
EC_PWROK[16,35]
B B
For DS3 Sequence
Support DS3 --> Ra
Non-DS3 --> Rb
RSMRST#
DSWROK_EC[35]
Rb
R560 *0_4
Ra
R565 0_4
04
SUSWARN#_EC[35]
SUSACK#_EC[35]
PCIE_WAKE#[28,29,30,35]
DDR_VTT_CNTL[3,18]
R293 0_4
R283 0_4
R282
*0_4
Need check circuit!!!!
Should be delete
A A
+1.0V
+3V
+3V_DEEP_SUS
+3V_RTC
+3VS5
+5VS5
+VCCSTPLL
5
+1.0V [2,6,16,32,35,41]
+3V [2,10,11,12,13,14,15,16,17,18,19,21,22,24,25,26,27,28,29,30,31,33,34,35,36,42,44,45,46]
+3V_DEEP_SUS [10,11,12,14,15,16,18]
+3V_RTC [13,15,32]
+3VS5 [10,15,16,27,30,33,35,36,38,40,41,44,47]
+5VS5 [27,32,36,38,39,40,41,42,43,44,45,46,47]
+VCCSTPLL [2,5,6,9,41,42]
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
PROJECT : TWL & JWL ( MB )
PROJECT : TWL & JWL ( MB )
PROJECT : TWL & JWL ( MB )
Document Number
Document Number
Document Number
SKL-03 (PowerManger)
SKL-03 (PowerManger)
C
C
C
Date:
Date:
Date:
4
3
2
SKL-03 (PowerManger)
Wednesday, July 29, 2015
Wednesday, July 29, 2015
Wednesday, July 29, 2015
Sheet :
Sheet :
Sheet :
1
of
of
of
4 51
4 51
4 51
Rev.Size
Rev.Size
Rev.Size
3C
3C
3C
5
4
3
2
1
05
SKL_ULT
CPU POWER 1 OF 4
VCC
VCC
VCC VCC
0.55~1.5V
0.55~1.5V
0.55~1.5V0.55~1.5V
29A
29A
29A 29A
VCC_G32
VCC_G33
VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42
VCC_J30
VCC_J33
VCC_J37
VCC_J40
VCC_K33
VCC_K35
VCC_K37
VCC_K38
VCC_K40
VCC_K42
VCC_K43
VCC_SENSE
VSS_SENSE
VIDALERT#
VIDSCK
VIDSOUT
VCCSTG_G20
BOM
12 OF 20REV = 1
G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43
E32
E33
B63
A63
D64
G20
+VCC_CORE
+VCCSTG
+1.0V
C185 47U/6.3V_8
C286 47U/6.3V_8
C690 47U/6.3V_8
C326 47U/6.3V_8
C193 47U/6.3V_8
C304 47U/6.3V_8
C184 47U/6.3V_8
C692 47U/6.3V_8
C256 10U/6.3V_4
C265 10U/6.3V_4
C257 10U/6.3V_4
C693 10U/6.3V_4
C705 10U/6.3V_4
C311 10U/6.3V_4
C246 10U/6.3V_4
C278 10U/6.3V_4
100Ω ±1% pull-up to VCC near processor.
20150519A-VCC_SENSE & VSS_SENSE has pull up resistor
at CPU & Power side. Because need add more
+VCC_CORE shape, so delete PU on CPU side.
VCC_SENSE [42]
VSS_SENSE [42]
+VCCSTPLL
CLOSE TO CPU
A30
A34
A39
A44
AK33
AK35
AK37
AK38
AK40
AL33
AL37
AL40
AM32
AM33
AM35
AM37
AM38
G30
K32
AK32
AB62
P62
V62
H63
G61
AC63
AE63
AE62
AG62
AL63
AJ62
*SKL_ULT
U25L
VCC_A30
VCC_A34
VCC_A39
VCC_A44
VCC_AK33
VCC_AK35
VCC_AK37
VCC_AK38
VCC_AK40
VCC_AL33
VCC_AL37
VCC_AL40
VCC_AM32
VCC_AM33
VCC_AM35
VCC_AM37
VCC_AM38
VCC_G30
RSVD_K32
RSVD_AK32
VCCOPC_AB62
VCCOPC_P62
VCCOPC_V62
VCC_OPC_1P8_H63
VCC_OPC_1P8_G61
VCCOPC_SENSE
VSSOPC_SENSE
VCCEOPIO
VCCEOPIO
VCCEOPIO_SENSE
VSSEOPIO_SENSE
Under CPU. Close CPU.
C295 1U/6.3V_4
D D
C C
C319 1U/6.3V_4
C330 1U/6.3V_4
C312 1U/6.3V_4
C329 1U/6.3V_4
C200 22U/6.3V_6
C186 47U/6.3V_Y8
C288 1U/6.3V_4
C267 1U/6.3V_4 C214 22U/6.3V_6
C694 22U/6.3V_6
C189 22U/6.3V_6
C345 1U/6.3V_4
C355 1U/6.3V_4
C259 1U/6.3V_4
C287 10U/6.3V_4
C203 10U/6.3V_6
C277 10U/6.3V_4
C704 22U/6.3V_6
C308 22U/6.3V_6
C211 22U/6.3V_6
+VCC_CORE
C354 1U/6.3V_4
C266 1U/6.3V_4
C294 10U/6.3V_4
C291 22U/6.3V_6
C344 1U/6.3V_4
C318 1U/6.3V_4
C258 10U/6.3V_4
C247 10U/6.3V_4C697 1U/6.3V_4
C702 10U/6.3V_4
C264 10U/6.3V_4
C281 22U/6.3V_6
C691 22U/6.3V_6
C316 22U/6.3V_6
C333 22U/6.3V_6
PLACE THE PU RESISTORS
R455
TP42
TP34
VCCEOPIO_SENSE
VSSEOPIO_SENSE
H_CPU_SVIDALRT#
R498 220/F_4
56.2/F_4
C714
*0.1U/16V_4
SVID ALERT
VR_SVID_ALERT# [42]
+VCCSTPLL
PLACE THE PU RESISTORS
CLOSE TO VR
R454
PULL UP IS IN THE VR MODULE
*54.9/F_4
VR_SVID_CLK_R
B B
H_CPU_SVIDDAT
R482 *0_4/S
+VCCSTPLL
R483
100/F_4
CLOSE TO CPU
PLACE THE PU RESISTORS
R484 *0_4/S
SVID CLK
VR_SVID_CLK [42]
SVID DATA
VR_SVID_DATA [42]
Layout note:
need routing together and ALERT
need between CLK and DATA.
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
PROJECT : TWL & JWL ( MB )
PROJECT : TWL & JWL ( MB )
+VCC_CORE
+VCCSTG
+VCCSTPLL
5
4
3
+VCC_CORE [42]
+VCCSTG [6]
+VCCSTPLL [2,4,6,9,41,42]
C
C
C
Date:
Date:
Date:
2
PROJECT : TWL & JWL ( MB )
Document Number
Document Number
Document Number
SKL-04 (POWER-1)
SKL-04 (POWER-1)
SKL-04 (POWER-1)
Wednesday, July 29, 2015
Wednesday, July 29, 2015
Wednesday, July 29, 2015
Sheet :
Sheet :
Sheet :
1
of
of
of
5 51
5 51
5 51
Rev.Size
Rev.Size
Rev.Size
3C
3C
3C
5
4
3
2
1
X1B-1218 change from +1.0V to +VCCIO.
C413 10U/6.3V_4
+1.35VSUS
C403 10U/6.3V_4
+VCCPLL_OC
C405 1U/6.3V_4
C399 1U/6.3V_4
C404 1U/6.3V_4
C414 1U/6.3V_4
SKL_ULT
C426 1U/6.3V_4
C356 1U/6.3V_4
AU23
AU28
AU35
AU42
BB23
BB32
BB41
BB47
BB51
AM40
A18
A22
AL23
K20
K21
U25N
CPU POWER 3 OF 4
VDDQ_AU23
VDDQ_AU28
VDDQ_AU35
VDDQ_AU42
VDDQ_BB23
VDDQ_BB32
VDDQ_BB41
VDDQ_BB47
VDDQ_BB51
VDDQC
VCCST
VCCSTG_A22
VCCPLL_OC
VCCPLL_K20
VCCPLL_K21
*SKL_ULT
VDDQ
VDDQ
VDDQVDDQ
1.35V
1.35V
1.35V1.35V
2A
2A
2A 2A
1.0V
1.0V
1.0V 1.0V
120mA
120mA
120mA120mA
0.04A
1.0V
1.0V
1.0V 1.0V
120mA
120mA
120mA120mA
VCCIO
VCCIO
VCCIOVCCIO
0.95V
0.95V
0.95V0.95V
3.1A
3.1A
3.1A 3.1A
VCCSA
VCCSA
VCCSA VCCSA
0.55~1.5V
0.55~1.5V
0.55~1.5V0.55~1.5V
4.5A
4.5A
4.5A 4.5A
VCCIO_SENSE
VSSIO_SENSE
VSSSA_SENSE
VCCSA_SENSE
14 OF 20REV = 1
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
AK28
AK30
AL30
AL42
AM28
AM30
AM42
AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30
AM23
AM22
H21
H20
Under CPU Close CPU
C368 10U/6.3V_4
C351 1U/6.3V_4
C352 1U/6.3V_4
C369 1U/6.3V_4
C289 1U/6.3V_4
C279 1U/6.3V_4
C225 1U/6.3V_4
VCCIO_VCCSENSE
VCCIO_VSSSENSE
C360 10U/6.3V_4
C350 10U/6.3V_4
+VCCSA
C320 1U/6.3V_4
C321 1U/6.3V_4
C280 1U/6.3V_4
R215 100/F_4
R203 100/F_4
VSSSA_SENSE [42]
VCCSA_SENSE [42]
C347 1U/6.3V_4
C346 1U/6.3V_4
Under CPU Close CPU
C313 10U/6.3V_4
C290 1U/6.3V_4
C359 1U/6.3V_4
C297 10U/6.3V_4
Close CPU Close CPU Under CPU
C431 10U/6.3V_6
C432 10U/6.3V_6
C434 10U/6.3V_6
D D
+1.0V_DEEP_SUS
+VCCSTPLL
C216 *1U/6.3V_4
C215 *22U/6.3V_6
+1.0V
C C
20150729A-VCCSTG change source by +VCCSTPLL.
Close CPU A18 Ball
20150518A-Modern Standby.
+VCCIO
X1B-0106 Reserve RES to +VCCSTPLL.
20150319A-Folllow X1B
change Power Source from
+1.0V to +VCCSTPLL.
R141 0_4
R151 *0_4
R600 *0_4
C429 10U/6.3V_6
C427 10U/6.3V_6
C433 10U/6.3V_6
+VCCSTG
C430 1U/6.3V_4
C415 1U/6.3V_4
C428 1U/6.3V_4
C228 1U/6.3V_4
C421 1U/6.3V_4
+1.35V_VCCPLL_OC
+1.35VSUS
C425 10U/6.3V_4
C424 10U/6.3V_4
C416 10U/6.3V_4
C419 10U/6.3V_4
C420 *10U/6.3V_4
Close CPU Under CPU
+VCCSTPLL → VCCSTG/S3=1.0V
+1.0V → VCCSTG/S3=42mV
+1.35VSUS
20150518A-Modern Standby.
20150518B-Mail from Hermann at 5/14 16:27.
+VCCPLL_OC change power source from
+1.35VSUS to +1.35V_VCCPLL_OC.
R243 *0_6
R601 0_6
C353 1U/6.3V_4
C269 10U/6.3V_4
+VCCIO
+VCCIO+1.35VSUS
C260 10U/6.3V_4
C270 10U/6.3V_4
C314 10U/6.3V_4
C298 10U/6.3V_4
X1B-1218 change from
+1.0V to +VCCIO.
C248 10U/6.3V_4
C332 10U/6.3V_4
C230 10U/6.3V_4
C261 10U/6.3V_4
C331 10U/6.3V_4
C249 10U/6.3V_4
06
Under CPU
+VCCSTPLL
R142 0_6
C217
1U/6.3V_4
+VCCPLL
C227
1U/6.3V_4
Under CPU
120mA
+1.0V
+1.35VSUS
+3VPCU
+VCCIO
+VCCPLL
+VCCPLL_OC
+VCCSA
+VCCSTG
+VCCSTPLL
+1.0V [2,4,16,32,35,41]
+1.35VSUS [3,17,18,36,39,41,47]
+3VPCU [13,30,32,33,34,35,37,38]
+VCCIO [2,16,41]
+VCCPLL
+VCCPLL_OC
+VCCSA [42,43]
+VCCSTG [5]
+VCCSTPLL [2,4,5,9,41,42]
Close CPU Close CPU
B B
IO Thrm Protect
Top Side for FAN output.
+3VPCU
R153
20K/F_4
THRM_MOINTOR1 [35]
THER_CPU
R152
100K_4 NTC
C233
0.1U/16V_4
1 2
A A
For 75 degree, 1.2v limit, (HW)
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
PROJECT : TWL & JWL ( MB )
PROJECT : TWL & JWL ( MB )
PROJECT : TWL & JWL ( MB )
Document Number
Document Number
Document Number
SKL-05 (POWER-2)
SKL-05 (POWER-2)
C
C
C
Date:
Date:
Date:
5
4
3
2
SKL-05 (POWER-2)
Wednesday, July 29, 2015
Wednesday, July 29, 2015
Wednesday, July 29, 2015
Sheet :
Sheet :
Sheet :
1
of
of
of
6 51
6 51
6 51
Rev.Size
Rev.Size
Rev.Size
3C
3C
3C
5
4
3
2
1
SKL_ULT
A48
A53
A58
A62
A66
AA63
AA64
AA66
AA67
AA69
AA70
AA71
AC64
AC65
AC66
AC67
AC68
AC69
AC70
AC71
J43
J45
J46
J48
J50
J52
J53
J55
J56
J58
J60
K48
K50
K52
K53
K55
K56
K58
K60
L62
L63
L64
L65
L66
L67
L68
L69
L70
L71
M62
N63
N64
N66
N67
N69
J70
J69
U25M
CPU POWER 2 OF 4
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT_SENSE
VSSGT_SENSE
*SKL_ULT
VCCGT
VCCGT
VCCGT VCCGT
0.55~1.5V
0.55~1.5V
0.55~1.5V0.55~1.5V
31A
31A
31A 31A
BOM
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGTX_AK42
VCCGTX_AK43
VCCGTX_AK45
VCCGTX_AK46
VCCGTX_AK48
VCCGTX_AK50
VCCGTX_AK52
VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60
VCCGTX_AK70
VCCGTX_AL43
VCCGTX_AL46
VCCGTX_AL50
VCCGTX_AL53
VCCGTX_AL56
VCCGTX_AL60
VCCGTX_AM48
VCCGTX_AM50
VCCGTX_AM52
VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58
VCCGTX_AU58
VCCGTX_AU63
VCCGTX_BB57
VCCGTX_BB66
VCCGTX_SENSE
VSSGTX_SENSE
13 OF 20REV = 1
+VCCGT
C245 10U/6.3V_4
C732 10U/6.3V_4
C271 10U/6.3V_4
C339 10U/6.3V_4
D D
C263 1U/6.3V_4
C242 1U/6.3V_4
C255 1U/6.3V_4
C C
Under CPU
C244 1U/6.3V_4
C253 1U/6.3V_4
C340 1U/6.3V_4
VCCGT_SENSE[42]
VSSGT_SENSE[42]
C224 10U/6.3V_4
C222 10U/6.3V_4
C226 10U/6.3V_4
C243 1U/6.3V_4
C262 1U/6.3V_4
C252 1U/6.3V_4
C737 10U/6.3V_4
C272 10U/6.3V_4
C250 10U/6.3V_4
C251 1U/6.3V_4
C223 1U/6.3V_4
C254 1U/6.3V_4
N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62
AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66
AK62
AL61
+VCCGT
C325 47U/6.3V_Y8
C310 47U/6.3V_Y8
C285 47U/6.3V_Y8
C349 47U/6.3V_Y8
C739 22U/6.3V_6
C728 22U/6.3V_6
C276 22U/6.3V_6
C303 47U/6.3V_Y8
C309 47U/6.3V_Y8
C342 22U/6.3V_6
C729 22U/6.3V_6
Close CPU
C274 22U/6.3V_6
C273 22U/6.3V_6
C733 22U/6.3V_6
C738 22U/6.3V_6
C734 22U/6.3V_6
C275 22U/6.3V_6
C727 22U/6.3V_6
07
B B
+VCCGT
A A
5
4
+VCCGT [42]
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
PROJECT : TWL & JWL ( MB )
PROJECT : TWL & JWL ( MB )
PROJECT : TWL & JWL ( MB )
Document Number
Document Number
Document Number
SKL-06 (POWER-3)
SKL-06 (POWER-3)
Custom
Custom
Custom
Date:
Date:
Date:
3
2
SKL-06 (POWER-3)
Wednesday, July 29, 2015
Wednesday, July 29, 2015
Wednesday, July 29, 2015
Sheet :
Sheet :
Sheet :
1
of
of
of
7 51
7 51
7 51
Rev.Size
Rev.Size
Rev.Size
3C
3C
3C
5
4
3
2
1
08
A67
A70
AA2
AA4
AA65
AA68
AB15
AB16
AB18
AB21
AB8
AD13
AD16
AD19
AD20
AD21
AD62
AD8
AE64
AE65
AE66
AE67
AE68
AE69
AF1
AF10
AF15
AF17
AF2
AF4
AF63
AG16
AG17
AG18
AG19
AG20
AG21
AG71
AH13
AH6
AH63
AH64
AH67
AJ15
AJ18
AJ20
AJ4
AK11
AK16
AK18
AK21
AK22
AK27
AK63
AK68
AK69
AK8
AL2
AL28
AL32
AL35
AL38
AL4
AL45
AL48
AL52
AL55
AL58
AL64
A5
U25P
SKL_ULT
GND 1 OF 3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
*SKL_ULT
AL65
VSS
AL66
VSS
AM13
VSS
AM21
VSS
AM25
VSS
AM27
VSS
AM43
VSS
AM45
VSS
AM46
VSS
AM55
VSS
AM60
VSS
AM61
VSS
AM68
VSS
AM71
VSS
AM8
VSS
AN20
VSS
AN23
VSS
AN28
VSS
AN30
VSS
AN32
VSS
AN33
VSS
AN35
VSS
AN37
VSS
AN38
VSS
AN40
VSS
AN42
VSS
AN58
VSS
AN63
VSS
AP10
VSS
AP18
VSS
AP20
VSS
AP23
VSS
AP28
VSS
AP32
VSS
AP35
VSS
AP38
VSS
AP42
VSS
AP58
VSS
AP63
VSS
AP68
VSS
AP70
VSS
AR11
VSS
AR15
VSS
AR16
VSS
AR20
VSS
AR23
VSS
AR28
VSS
AR35
VSS
AR42
VSS
AR43
VSS
AR45
VSS
AR46
VSS
AR48
VSS
AR5
VSS
AR50
VSS
AR52
VSS
AR53
VSS
AR55
VSS
AR58
VSS
AR63
VSS
AR8
VSS
AT2
VSS
AT20
VSS
AT23
VSS
AT28
VSS
AT35
VSS
AT4
VSS
AT42
VSS
AT56
VSS
AT58
VSS
16 OF 20REV = 1
U25R
G10
G22
G43
G45
G48
G52
G55
G58
G60
G63
G66
H15
H18
H71
J11
J13
J25
J28
J32
J35
J38
J42
K16
K18
K22
K61
K63
K64
K65
K66
K67
K68
K70
K71
L11
L16
L17
G5
G6
F8
J8
SKL_ULT
GND 3 OF 3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
*SKL_ULT
L18
VSS
L2
VSS
L20
VSS
L4
VSS
L8
VSS
N10
VSS
N13
VSS
N19
VSS
N21
VSS
N6
VSS
N65
VSS
N68
VSS
P17
VSS
P19
VSS
P20
VSS
P21
VSS
R13
VSS
R6
VSS
T15
VSS
T17
VSS
T18
VSS
T2
VSS
T21
VSS
T4
VSS
U10
VSS
U63
VSS
U64
VSS
U66
VSS
U67
VSS
U69
VSS
U70
VSS
V16
VSS
V17
VSS
V18
VSS
W13
VSS
W6
VSS
W9
VSS
Y17
VSS
Y19
VSS
Y20
VSS
Y21
VSS
18 OF 20REV = 1
D D
C C
B B
AT63
AT68
AT71
AU10
AU15
AU20
AU32
AU38
AV1
AV68
AV69
AV70
AV71
AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57
AW6
AW60
AW62
AW64
AW66
AW8
AY66
B10
B14
B18
B22
B30
B34
B39
B44
B48
B53
B58
B62
B66
B71
BA1
BA10
BA14
BA18
BA2
BA23
BA28
BA32
BA36
F68
BA45
U25Q
SKL_ULT
GND 2 OF 3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
*SKL_ULT
BOM
17 OF 20REV = 1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BA49
BA53
BA57
BA6
BA62
BA66
BA71
BB18
BB26
BB30
BB34
BB38
BB43
BB55
BB6
BB60
BB64
BB67
BB70
C1
C25
C5
D10
D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58
D6
D62
D66
D69
E11
E15
E18
E21
E46
E50
E53
E56
E6
E65
E71
F1
F13
F2
F22
F23
F27
F28
F32
F33
F35
F37
F38
F4
F40
F42
BA41
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
PROJECT : TWL & JWL ( MB )
PROJECT : TWL & JWL ( MB )
PROJECT : TWL & JWL ( MB )
Document Number
Document Number
Document Number
SKL-07 (GND)
SKL-07 (GND)
Custom
Custom
Custom
Date:
Date:
Date:
5
4
3
2
SKL-07 (GND)
Wednesday, July 29, 2015
Wednesday, July 29, 2015
Wednesday, July 29, 2015
Sheet :
Sheet :
Sheet :
1
of
of
of
8 51
8 51
8 51
Rev.Size
Rev.Size
Rev.Size
3C
3C
3C
5
4
3
2
1
09
U25S
CFG0-19 need Reserve TP
D D
+1.0V_DEEP_SUS
C C
B B
CFG0[16]
CFG1[16]
CFG2[16]
CFG3[16]
CFG4[16]
CFG5[16]
CFG6[16]
CFG7[16]
CFG8[16]
CFG9[16]
CFG10[16]
CFG11[16]
CFG12[16]
CFG13[16]
CFG14[16]
CFG15[16]
CFG16[16]
CFG17[16]
CFG18[16]
CFG19[16]
R145 49.9/F_4
R442 *1K_4
CFG3
CFG4
CFG_RCOMP
E68
B67
D65
D67
E70
C68
D68
C67
F71
G69
F70
G68
H70
G71
H69
G70
E63
F63
E66
F66
E60
AY2
AY1
K46
K45
AL25
AL27
C71
B70
F60
A52
BA70
BA68
J71
J68
F65
G65
F61
E61
E8
D1
D3
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
CFG[18]
CFG[19]
CFG_RCOMP
ITP_PMODE
RSVD_AY2
RSVD_AY1
RSVD_D1
RSVD_D3
RSVD_K46
RSVD_K45
RSVD_AL25
RSVD_AL27
RSVD_C71
RSVD_B70
RSVD_F60
RSVD_A52
RSVD_TP_BA70
RSVD_TP_BA68
RSVD_J71
RSVD_J68
VSS_F65
VSS_G65
RSVD_F61
RSVD_E61
*SKL_ULT
SKL_ULT
RESERVED SIGNALS-1
BOM
RSVD_TP_BB68
RSVD_TP_BB69
RSVD_TP_AK13
RSVD_TP_AK12
RSVD_BB2
RSVD_BA3
TP5
TP6
RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2
RSVD_B3
RSVD_A3
RSVD_AW1
RSVD_E1
RSVD_E2
RSVD_BA4
RSVD_BB4
RSVD_A4
RSVD_C4
TP4
RSVD_A69
RSVD_B69
RSVD_AY3
RSVD_D71
RSVD_C70
RSVD_C54
RSVD_D54
TP1
TP2
VSS_AY71
ZVM#
RSVD_TP_AW71
RSVD_TP_AW70
MSM#
PROC_SELECT#
19 OF 20REV = 1
BB68
BB69
AK13
AK12
BB2
BA3
AU5
AT5
D5
D4
B2
C2
B3
A3
AW1
E1
E2
BA4
BB4
A4
C4
BB5
A69
B69
AY3
R265 *0_4/S
D71
C70
C54
D54
AY4
BB3
AY71
R256 *0_4/S
AR56
AW71
AW70
AP56
C64
R456 *100K_4
0105 R384 unmount
1226 Add R538, C677 reserved
+1.8V_DEEP_SUS
R160 *0_4
+VCCSTPLL
C234
*1U/6.3V_4
Close to CPU
within 100mil
AW69
AW68
AU56
AW48
U12
U11
H11
C7
*SKL_ULT
SKL_ULT
U25T
RSVD_AW69
RSVD_AW68
RSVD_AU56
RSVD_AW48
RSVD_C7
RSVD_U12
RSVD_U11
RSVD_H11
SPARE
RSVD_F6
RSVD_E3
RSVD_C11
RSVD_B11
RSVD_A11
RSVD_D12
RSVD_C12
RSVD_F52
20 OF 20REV = 1
F6
E3
C11
B11
A11
D12
C12
F52
Processor Strapping
CFG3
(Physcial Debug Enable)
Disable: Enable: Set DFX Enable in DFX interface MSR
The CFG signals have a default value of '1' if not terminated on the board.
1 0
CFG3
Circuit
R494 *1K_4
DFX Privacy
CFG4
(DP Presence Strap)
A A
+1.0V_DEEP_SUS
+1.8V_DEEP_SUS
+VCCSTPLL
5
Disable; No physical DP attached to eDP
+1.0V_DEEP_SUS [13,15,16,40,41]
+1.8V_DEEP_SUS [15,40]
+VCCSTPLL [2,4,5,6,41,42]
4
Enable; An ext DP device is connected to eDP
3
CFG4
R512 1K_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
PROJECT : TWL & JWL ( MB )
PROJECT : TWL & JWL ( MB )
PROJECT : TWL & JWL ( MB )
Document Number
Document Number
Document Number
SKL-08 (RSV)
SKL-08 (RSV)
Custom
Custom
Custom
Date:
Date:
Date:
2
SKL-08 (RSV)
Wednesday, July 29, 2015
Wednesday, July 29, 2015
Wednesday, July 29, 2015
Sheet :
Sheet :
Sheet :
1
of
of
of
9 51
9 51
9 51
Rev.Size
Rev.Size
Rev.Size
3C
3C
3C
5
4
3
2
1
10
D D
+3VSPI
+3VS5
R537 *0_4/S
R536 *0_4
C736 0.1U/16V_4
R538 1K_4
+3VSPI
HOLD#
TP51/TP38/TP44/TP43/TP50/TP18 need place to TOP
PCH_SPI1_SI_R[35]
PCH_SPI_CS0#_R[35]
PCH_SPI1_CLK_R[35]
PCH_SPI1_SO_R[35]
U26
8
VDD
7
HOLD#
4
VSS
W25Q128FVSIQ
AKE3DZN0N01
PCH SPI ROM(CLG)
8
VDD
7
HOLD#
4
VSS
*A25LQ32AM-F/Q
DFHS08FS023
91960-0084L-8P-SOCKET
CE#
SCK
WP#
CE#
SCK
WP#
SO
U27
SO
SI
SI
1
PCH_SPI_CS0#_R
6
PCH_SPI1_CLK_R
5
PCH_SPI1_SI_R
2
PCH_SPI1_SO_R
3
1
PCH_SPI_CS0#_R
6
PCH_SPI1_CLK_R
5
PCH_SPI1_SI_R
2
PCH_SPI1_SO_R
3
BIOS_WP#
TP51
TP38
TP44
TP43
C735
22P/50V_4
1224 Change R427 R397 to 1K
BIOS_WP#
HOLD#
TP50
TP18
16MB SPI ROM Socket
U26 & U27 footprint at same location for co-layout.
20150511A-BOM change, stuff ROM SOCKET / no stuff ROM CHIP by DB.
Stuff ROM CHIP / no stuff ROM SOCKET by PV.
R551/R539/R541/R552/R553/R535 close to U26 pin.
R551 15/F_4
R539 15/F_4
R541 15/F_4
R552 15/F_4
+3VSPI
PCH_SPI1_CLK
TP17
TP106
TP105
TP97
PCH_SPI1_SO
PCH_SPI1_SI
PCH_SPI_IO2
PCH_SPI_IO3
PCH_SPI_CS0#
SPI1_CLK
SIO_EXT_SMI#
PCI_SERR#
SPI1_IO2
SPI1_IO3
SPI1_CS#
R554
1K_4
R553 15/F_4
R535 15/F_4
C748
1U/10V_4
SIO_EXT_SMI#[35]
PCI_SERR#[35]
EC_RCIN#[35]
SERIRQ[33,35]
AV2
AW3
AV3
AW2
AU4
AU3
AU2
AU1
AW13
AY11
M2
M3
J4
V1
V2
M1
G3
G2
G1
*SKL_ULT
U25E
SPI - FLASH
SPI0_CLK
SPI0_MISO
SPI0_MOSI
SPI0_IO2
SPI0_IO3
SPI0_CS0#
SPI0_CS1#
SPI0_CS2#
SPI - TOUCH
GPP_D1/SPI1_CLK
GPP_D2/SPI1_MISO
GPP_D3/SPI1_MOSI
GPP_D21/SPI1_IO2
GPP_D22/SPI1_IO3
GPP_D0/SPI1_CS#
C LINK
CL_CLK
CL_DATA
CL_RST#
GPP_A0/RCIN#
GPP_A6/SERIRQ
SKL_ULT
+3V_DEEP_SUS
R174 1K_4
R164 499/F_4
R161 2.2K_4
R165 2.2K_4
SMBUS, SMLINK
GPP_B23/SML1ALERT#/PCHHOT#
LPC
GPP_A14/SUS_STAT#/ESPI_RESET#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
PDC
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C2/SMBALERT#
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C5/SML0ALERT#
GPP_C6/SML1CLK
GPP_C7/SML1DATA
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
GPP_A5/LFRAME#/ESPI_CS#
GPP_A10/CLKOUT_LPC1
GPP_A8/CLKRUN#
R7
R8
R10
R9
W2
W1
W3
V3
AM7
AY13
BA13
BB13
AY12
BA12
BA11
AW9
AY9
AW11
5 OF 20REV = 1
SMB_PCH_CLK
SMB_PCH_DAT
SML0ALERT# [11]
SMB_ME0_CLK
SMB_ME0_DAT
SML1ALERT# [11]
SMB_ME1_CLK
SMB_ME1_DAT
GPP_B23
CLK_PCI_EC_R
CLK_PCI_LPC_R
LAD0 [30,33,35]
LAD1 [30,33,35]
LAD2 [30,33,35]
LAD3 [30,33,35]
LFRAME# [30,33,35]
R272 22/F_4
R273 22/F_4
R274 *22/F_4
20150319A-Folllow X1B
Change to NU.
R534 499/F_4
TP41
+3V_DEEP_SUS
C C
PCH SPI ROM(CLG)
B B
Vender P/N
SOCKET
Size
16MB
16MBGigaDevice ( GGD )
AKE3DZN0N01 - IC FLASH(8P) W25Q128FVSIQ(SOIC)WINBOND ( WND )
AKE3DF00Q00 - IC FLASH(8P)GD25B128CSIGR(SOP)
DFHS08FS023 - CONN SMD HOUSING 8P 2R FS(P1.27,H5.0)
SMBus/Pull-up(CLG)
CPU heat pipe local thermal sensor
DDR thermal sensor
RTD2136
EC
Touch Pad
XDP
DDR3-L
R171 1K_4
Q13
2N7002KDW
+3V
EC29
18P/50V_4
EMI(near PCH)
EC30
*18P/50V_4
EMI(near PCH)
6
2
5
5
2
6
Q14
*2N7002DW
EC27
18P/50V_4
+3V
1
43
43
1
R275
8.2K/F_4
+3V
R167 4.7K_4
R166 4.7K_4
MBCLK2 [24,35]
MBDATA2 [24,35]
CLK_24M_KBC [35]
CLK_24M_DEBUG [30]
CLK_PCI_TPM [33]
CLKRUN# [33,35]
SMB_RUN_CLK [16,17,18,24,34]
SMB_RUN_DAT [16,17,18,24,34]
+3V
GPIO Pull UP
SERIRQ
+3V
+3V_DEEP_SUS
+3VS5
+3VSPI
A A
5
+3V [2,4,11,12,13,14,15,16,17,18,19,21,22,24,25,26,27,28,29,30,31,33,34,35,36,42,44,45,46]
+3V_DEEP_SUS [4,11,12,14,15,16,18]
+3VS5 [4,15,16,27,30,33,35,36,38,40,41,44,47]
+3VSPI
4
SIO_EXT_SMI#
EC_RCIN#
PCI_SERR#
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
PROJECT : TWL & JWL ( MB )
PROJECT : TWL & JWL ( MB )
PROJECT : TWL & JWL ( MB )
Document Number
Document Number
Document Number
SKL-09 (SPI/LPC/SM)
SKL-09 (SPI/LPC/SM)
C
C
C
Date:
Date:
Date:
3
2
SKL-09 (SPI/LPC/SM)
Wednesday, July 29, 2015
Wednesday, July 29, 2015
Wednesday, July 29, 2015
R567 10K_4
R511 10K_4
R562 10K_4
R502 10K_4
Sheet :
Sheet :
Sheet :
1
of
of
of
10 51
10 51
10 51
Rev.Size
Rev.Size
Rev.Size
3C
3C
3C
5
4
3
2
1
11
D D
Functional Strap Definitions
DESIGN NOTE:
WEAK PULL UP RESISTOR PRESENT ON THIS NET
ACZ_SPKR[14,27]
ACZ_SPKR
TOP SWAP OVERRIDE
R550
*20K/F_4
HIGH - TOP SWAP ENABLE
LOW-DISABLED
HIGH: LPC SELECTED FOR SYSTEM FLASH
WEAK INTERNAL PD
ACZ_SDOUT[14]
+3V_DEEP_SUS
ACZ_SDOUT
R566
*4.7K_4
No Boot:
The signal has a weak internal pull-down.
0 = Enable security measures defined in the Flash
Descriptor.
1 = Disable Flash Descriptor Security (override). This
strap should only be asserted high using external
pull-up in manufacturing/debug environments ONLY.
This function is useful when running ITP/XDP.
C C
+3V_DEEP_SUS
X1B-1212 change R95 pull-high from
+3V to +3V_DEEP_SUS
R510
1K_4
No Boot:
GPIO33_EC[35]
R568 1K_4
The signal has a weak internal pull-down.
0 = Disable Intel ME Crypto Transport Layer Security
R505
*20K/F_4
(TLS) cipher suite (no confidentiality).
1 = Enable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (with confidentiality). Must be
pulled up to support Intel AMT with TLS and Intel
GPP_B18[14]SML0ALERT#[10]
SBA (Small Business Advantage) with TLS.
ACZ_SDOUT
+3V
R261
*4.7K_4
No Boot:
The signal has a weak internal pull-down.
GPP_B18SML0ALERT#
0 = Disable No Reboot mode.
1 = Enable No Reboot mode
R268
10K_4
(PCH will disable the TCO
Timer system reboot feature).
This function is useful when running ITP/XDP.
+3V_DEEP_SUS
B B
R532
GSPI1_MOSI[14]
GSPI1_MOSI
No Boot:
The signal has a weak internal pull-down.
*10K_4
This field determines the destination of accesses to the
R207
*20K/F_4
BIOS memory range. Also controllable using Boot BIOS
Destination bit (Chipset Configuration Registers: Offset
3410h:Bit 10). This strap is used in conjunction with Boot
BIOS Destination Selection 0 strap.
Bit 10 Boot BIOS Destination
0 SPI
SML1ALERT#[10]
SML1ALERT#
R531
20K/F_4
No Boot:
The signal has a weak internal pull-down.
0 = LPC Is selected for EC.
1 = eSPI Is selected for EC.
1 LPC
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
+3V
+3V_DEEP_SUS
5
+3V_DEEP_SUS [4,10,12,14,15,16,18]
+3V [2,4,10,12,13,14,15,16,17,18,19,21,22,24,25,26,27,28,29,30,31,33,34,35,36,42,44,45,46]
4
Custom
Custom
Custom
Date:
Date:
Date:
3
2
Quanta Computer Inc.Quanta Computer Inc.
PROJECT : TWL & JWL ( MB )
PROJECT : TWL & JWL ( MB )
PROJECT : TWL & JWL ( MB )
Document Number
Document Number
Document Number
SKL-10 (HDA/STRAP)
SKL-10 (HDA/STRAP)
SKL-10 (HDA/STRAP)
Wednesday, July 29, 2015
Wednesday, July 29, 2015
Wednesday, July 29, 2015
Sheet :
Sheet :
Sheet :
1
of
of
of
11 51
11 51
11 51
Rev.Size
Rev.Size
Rev.Size
3C
3C
3C
5
4
3
2
1
U25H
DIS only
PEG_RXN1[19]
PEG_RXP1[19]
PEG_TXN1[19]
PEG_TXP1[19]
D D
dGPU
Card
Reader
WLAN
HDD
C C
ODD
LAN
SSD
B B
PEG_RXN2[19]
PEG_RXP2[19]
PEG_TXN2[19]
PEG_TXP2[19]
PEG_RXN3[19]
PEG_RXP3[19]
PEG_TXN3[19]
PEG_TXP3[19]
PEG_RXN4[19]
PEG_RXP4[19]
PEG_TXN4[19]
PEG_TXP4[19]
PCIE_RXN5_CARD[29]
PCIE_RXP5_CARD[29]
PCIE_TXN5_CARD[29]
PCIE_TXP5_CARD[29]
PCIE_RXN6_WLAN[30]
PCIE_RXP6_WLAN[30]
PCIE_TXN6_WLAN[30]
PCIE_TXP6_WLAN[30]
SATA_RXN0[33]
SATA_RXP0[33]
SATA_TXN0[33]
SATA_TXP0[33]
SATA_RXN1[33]
SATA_RXP1[33]
SATA_TXN1[33]
SATA_TXP1[33]
PCIE_RXN9_LAN[28]
PCIE_RXP9_LAN[28]
PCIE_TXN9_LAN[28]
PCIE_TXP9_LAN[28]
XDP_PRDY#_CPU[16]
XDP_PREQ#_CPU[16]
+3V_DEEP_SUS
SATA_RXN2[31]
SATA_RXP2[31]
SATA_TXN2[31]
SATA_TXP2[31]
C698 0.22U/10V_4
C699 0.22U/10V_4
C711 0.22U/10V_4
C710 0.22U/10V_4
C713 0.22U/10V_4
C712 0.22U/10V_4
C708 0.22U/10V_4
C707 0.22U/10V_4
C701 0.1U/16V_4
C700 0.1U/16V_4
C695 0.1U/16V_4
C696 0.1U/16V_4
C716 0.1U/16V_4
C715 0.1U/16V_4
R248 10K_4
PEG_TXN1_C
PEG_TXP1_C
PEG_TXN2_C
PEG_TXP2_C
PEG_TXN3_C
PEG_TXP3_C
PEG_TXN4_C
PEG_TXP4_C
PCIE_TXN5_CARD_C
PCIE_TXP5_CARD_C
PCIE_TXN6_WLAN_C
PCIE_TXP6_WLAN_C
PCIE_TXN9_LAN_C
PCIE_TXP9_LAN_C
R496 100/F_4
PIRQA#
PCIE/USB3/SATA
H13
PCIE1_RXN/USB3_5_RXN
G13
PCIE1_RXP/USB3_5_RXP
B17
PCIE1_TXN/USB3_5_TXN
A17
PCIE1_TXP/USB3_5_TXP
G11
PCIE2_RXN/USB3_6_RXN
F11
PCIE2_RXP/USB3_6_RXP
D16
PCIE2_TXN/USB3_6_TXN
C16
PCIE2_TXP/USB3_6_TXP
H16
PCIE3_RXN
G16
PCIE3_RXP
D17
PCIE3_TXN
C17
PCIE3_TXP
G15
PCIE4_RXN
F15
PCIE4_RXP
B19
PCIE4_TXN
A19
PCIE4_TXP
F16
PCIE5_RXN
E16
PCIE5_RXP
C19
PCIE5_TXN
D19
PCIE5_TXP
G18
PCIE6_RXN
F18
PCIE6_RXP
D20
PCIE6_TXN
C20
PCIE6_TXP
F20
PCIE7_RXN/SATA0_RXN
E20
PCIE7_RXP/SATA0_RXP
B21
PCIE7_TXN/SATA0_TXN
A21
PCIE7_TXP/SATA0_TXP
G21
PCIE8_RXN/SATA1A_RXN
F21
PCIE8_RXP/SATA1A_RXP
D21
PCIE8_TXN/SATA1A_TXN
C21
PCIE8_TXP/SATA1A_TXP
E22
PCIE9_RXN
E23
PCIE9_RXP
B23
PCIE9_TXN
A23
PCIE9_TXP
F25
PCIE10_RXN
E25
PCIE10_RXP
D23
PCIE10_TXN
C23
PCIE10_TXP
F5
PCIE_RCOMPN
E5
PCIE_RCOMPP
D56
PROC_PRDY#
D61
PROC_PREQ#
BB11
GPP_A7/PIRQA#
E28
PCIE11_RXN/SATA1B_RXN
E27
PCIE11_RXP/SATA1B_RXP
D24
PCIE11_TXN/SATA1B_TXN
C24
PCIE11_TXP/SATA1B_TXP
E30
PCIE12_RXN/SATA2_RXN
F30
PCIE12_RXP/SATA2_RXP
A25
PCIE12_TXN/SATA2_TXN
B25
PCIE12_TXP/SATA2_TXP
*SKL_ULT
SKL_ULT
PDC
SSIC / USB3
USB3_1_RXN
USB3_1_RXP
USB3_2_RXN/SSIC_1_RXN
USB3_2_RXP/SSIC_1_RXP
USB3_2_TXN/SSIC_1_TXN
USB3_2_TXP/SSIC_1_TXP
USB3_3_RXN/SSIC_2_RXN
USB3_3_RXP/SSIC_2_RXP
USB3_3_TXN/SSIC_2_TXN
USB3_3_TXP/SSIC_2_TXP
USB3_4_RXN
USB3_4_RXP
USB2
USB2_VBUSSENSE
GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#
GPP_E4/DEVSLP0
GPP_E5/DEVSLP1
GPP_E6/DEVSLP2
GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
GPP_E8/SATALED#
USB3_1_TXN
USB3_1_TXP
USB3_4_TXN
USB3_4_TXP
USB2N_1
USB2P_1
USB2N_2
USB2P_2
USB2N_3
USB2P_3
USB2N_4
USB2P_4
USB2N_5
USB2P_5
USB2N_6
USB2P_6
USB2N_7
USB2P_7
USB2N_8
USB2P_8
USB2N_9
USB2P_9
USB2N_10
USB2P_10
USB2_COMP
USB2_ID
8 OF 20REV = 1
H8
G8
C13
D13
J6
H6
B13
A13
J10
H10
B15
A15
E10
F10
C15
D15
AB9
AB10
AD6
AD7
AH3
AJ3
AD9
AD10
AJ1
AJ2
AF6
AF7
AH1
AH2
AF8
AF9
AG1
AG2
AH7
AH8
AB6
USB2_COMP
AG3
AG4
A9
DGPU_HOLD_RST#
C9
GPU_EVENT#
D9
DGPU_PWR_EN
B9
DGPU_PWROK
J1
GC6_FB_EN
J2
DEVSLP1
J3
OCP_OC#
H2
H3
ODD_PRSNT#_R
G4
SATAGP2
H1
SATA_LED#_R
USB30_RX1USB30_RX1+
USB30_TX1USB30_TX1+
USB30_RX2USB30_RX2+
USB30_TX2USB30_TX2+
USBP1USBP1+
USBP2USBP2+
USBP3USBP3+
USBP5USBP5+
USBP6USBP6+
USBP7USBP7+
USBP8USBP8+
R184 113/F_4
TP96
TP93
R500 *0_4
TP81
R495 *0_4/S
USB30_RX1- [32]
USB30_RX1+ [32]
USB30_TX1- [32]
USB30_TX1+ [32]
USB30_RX2- [32]
USB30_RX2+ [32]
USB30_TX2- [32]
USB30_TX2+ [32]
USBP1- [32]
USBP1+ [32]
USBP2- [32]
USBP2+ [32]
USBP3- [25]
USBP3+ [25]
USBP5- [30]
USBP5+ [30]
USBP6- [27]
USBP6+ [27]
USBP7- [31]
USBP7+ [31]
USBP8- [33]
USBP8+ [33]
PLACE 'R123' WITHIN 500 MILS
FROM USB2_COMP PIN WITH
TRACE IMPEDANCE LESS THAN 0.5 OHMS
DGPU_HOLD_RST# [19]
GPU_EVENT# [22]
DGPU_PWR_EN [22,47]
DGPU_PWROK [21,35,46]
GC6_FB_EN [22]
SATA_LED#
USB3.0 (M/B-Right Front, Charger)
USB3.0 (M/B-Right Rear)
USB3.0 (M/B-Right Front, Charger)
USB3.0 (M/B-Right Rear)
CCD
WLAN
USB2.0 (USB/B-Left Rear)
SSD
Finger Printer
+3V_DEEP_SUS
ZERO_ODD_DP# [33]
SATA_LED# [34]
R478
10K_4
20150319A-Folllow X1B change PU
from +3V to +3V_DEEP_SUS.
ACC_LED#
12
+3V
PCI-e Port Mapping Table
PCI-E Port
Port-01
Port-02
Port-03
Port-04
Port-05
Port-06
A A
Port-07
Port-08
Port-09
Port-10
5
Function
dGPU
dGPU
dGPU
dGPU
CardReader
WLAN
HDD
ODD
LAN
Un-used
CLK RQ Port
Port-0
Port-1
Port-2
Port-3
Port-4
Port-5
Function
dGPU
CardReader
WLAN
LAN
Un-used
Un-used
USB3.0 Port Mapping Table
USB3.0 Function
PORT-1
PORT-2
PORT-3
PORT-4
4
+3V
+3V_DEEP_SUS
USB3.0 (M/B-Right Front, Charger)
USB3.0 (M/B-Right Rear)
NC
NC
+3V_DEEP_SUS [4,10,11,14,15,16,18]
+3V [2,4,10,11,13,14,15,16,17,18,19,21,22,24,25,26,27,28,29,30,31,33,34,35,36,42,44,45,46]
USB2.0 Port Mapping Table
USB2.0 Function
PORT-1
PORT-2
PORT-3
PORT-4
PORT-5
PORT-6
PORT-7
PORT-8
PORT-9
PORT-10
3
USB3.0 (M/B-Right Front, Charger)
USB3.0 (M/B-Right Rear)
CCD
NC
WLAN
USB2.0 (USB/B-Left Rear)
SSD
Finger Printer
NC
NC
GPU_EVENT#
DGPU_PWR_EN
DGPU_PWROK
SATA_LED#
GC6_FB_EN
ODD_PRSNT#_R
DGPU_HOLD_RST#
20150319A-Folllow X1B change PU for NU & stuff PD.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
PROJECT : TWL & JWL ( MB )
PROJECT : TWL & JWL ( MB )
PROJECT : TWL & JWL ( MB )
Document Number
Document Number
Document Number
SKL-11 (PCIe/USB)
SKL-11 (PCIe/USB)
Custom
Custom
Custom
Date:
Date:
Date:
2
SKL-11 (PCIe/USB)
Wednesday, July 29, 2015
Wednesday, July 29, 2015
Wednesday, July 29, 2015
R444 *10K_4
R437 10K_4
R438 10K_4
R486 10K_4
R503 *10K_4
R501 10K_4
R445 *10K_4
R441 100K_4
Sheet :
Sheet :
Sheet :
1
of
of
of
12 51
12 51
12 51
Rev.Size
Rev.Size
Rev.Size
3C
3C
3C
5
4
3
2
1
13
RP3 install for XDP
RP15 *0_4P2R_4
XTAL24_IN
XTAL24_OUT
RTC_X1
TP126
2
4
+1.0V_DEEP_SUS
CK_XDP_N_R
CK_XDP_P_R
D D
20150319A-Folllow X1B
Change VGA CLK from Port-4 to Port-0.
VGA
Card
Reader
WLAN
LAN
C C
CLK_REQ/Strap Pin(CLG)
+3V
R263 10K_4
R251 10K_4
R249 10K_4
R267 10K_4
R260 10K_4
R250 10K_4
CLK_VGA_N[19]
CLK_VGA_P[19]
PCIE_CLKREQ_VGA#[19]
CLK_PCIE_CRN[29]
CLK_PCIE_CRP[29]
PCIE_CLKREQ_CR#[29]
CLK_PCIE_WLANN[30]
CLK_PCIE_WLANP[30]
PCIE_CLKREQ_WLAN#[30]
CLK_PCIE_LANN[28]
CLK_PCIE_LANP[28]
PCIE_CLKREQ_LAN#[28]
PCIE_CLKREQ_VGA#
PCIE_CLKREQ_WLAN#
PCIE_CLKREQ_LAN#
PCIE_CLKREQ_CR#
PCIE_CLKREQ5#
PCIE_CLKREQ4#
PCIE_CLKREQ_VGA#
PCIE_CLKREQ_CR#
PCIE_CLKREQ_WLAN#
PCIE_CLKREQ_LAN#
PCIE_CLKREQ4#
PCIE_CLKREQ5#
U25J
D42
CLKOUT_PCIE_N0
C42
CLKOUT_PCIE_P0
AR10
GPP_B5/SRCCLKREQ0#
B42
CLKOUT_PCIE_N1
A42
CLKOUT_PCIE_P1
AT7
GPP_B6/SRCCLKREQ1#
D41
CLKOUT_PCIE_N2
C41
CLKOUT_PCIE_P2
AT8
GPP_B7/SRCCLKREQ2#
D40
CLKOUT_PCIE_N3
C40
CLKOUT_PCIE_P3
AT10
GPP_B8/SRCCLKREQ3#
B40
CLKOUT_PCIE_N4
A40
CLKOUT_PCIE_P4
AU8
GPP_B9/SRCCLKREQ4#
E40
CLKOUT_PCIE_N5
E38
CLKOUT_PCIE_P5
AU7
GPP_B10/SRCCLKREQ5#
*SKL_ULT
SKL_ULT
CLOCK SIGNALS
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
GPD8/SUSCLK
XTAL24_IN
XTAL24_OUT
XCLK_BIASREF
RTCX1
RTCX2
SRTCRST#
RTCRST#
10 OF 20REV = 1
F43
E43
BA17
E37
E35
E42
AM18
AM20
AN18
AM16
XCLK_BIASREF
RTC_RST#
RTC_X2
SRTC_RST#
1
3
R460
2.7K/F_4
R448
*60.4/F_4
R549 0_4
R548
*10M_4
CK_XDP_N [16]
CK_XDP_P [16]
PCH_SUSCLK [31]
20150713A3-PV-R
20150727A1-PV-R change for crystal.
R440 *0_4
TP91
C719 12P/50V_4
1
2
4
3
C718 12P/50V_4
R439 *0_4
C745 *10P/50V_4
23
Y7
*32.768KHZ
4 1
C744 *10P/50V_4
Y6
24MHZ +-30PPM
R480
1M_4
TP90
20150312A-ADD
PCH_XTAL24_IN [32]
20150601A-Change C719 to NU. R440 change from
0Ω to 22Ω for terminal resistor.
20150525A-BOM change to same with DB stage.
20150518A-XTAL24_IN from G-CLK. Screen has flicker
when all CPU workload on 100%. Root-cause is
PCH_XTAL24_IN too close +VCC_CORE. Vender
recommand to add CAP 10pF on C719.
External Crystal and Green Clock
The 24 MHz (50 Ohm ESR) XTAL used for Skylake-U
needs to be replaced by 38.4 MHz (30 Ohm ESR) XTAL
for Cannonlake-U.
20150319A-Folllow X1B change to 10pF CAP.
CLKGEN_RTC_X1 [32]
RTC Clock 32.768KHz
20150518A-Change RTC 32.768KHz from G-CLK since PV stage.
20150520A-Change C744, C745 to 10pF base on EPSON test result.
+3V_RTC +3V_RTC_0
3.206VPass by Diode = 3.079V
+3V_RTC can't pass by G-CLK
U25I
CSI-2
A36
CSI2_DN0
B36
CSI2_DP0
B B
A A
+1.0V_DEEP_SUS
+3V
+3V_RTC
+3V_RTC_0
+3VPCU
5
C38
D38
C36
D36
A38
B38
C31
D31
C33
D33
A31
B31
A33
B33
A29
B29
C28
D28
A27
B27
C27
D27
CSI2_DN1
CSI2_DP1
CSI2_DN2
CSI2_DP2
CSI2_DN3
CSI2_DP3
CSI2_DN4
CSI2_DP4
CSI2_DN5
CSI2_DP5
CSI2_DN6
CSI2_DP6
CSI2_DN7
CSI2_DP7
CSI2_DN8
CSI2_DP8
CSI2_DN9
CSI2_DP9
CSI2_DN10
CSI2_DP10
CSI2_DN11
CSI2_DP11
*SKL_ULT
SKL_ULT
PDC
+1.0V_DEEP_SUS [9,15,16,40,41]
+3V [2,4,10,11,12,14,15,16,17,18,19,21,22,24,25,26,27,28,29,30,31,33,34,35,36,42,44,45,46]
+3V_RTC [4,15,32]
+3V_RTC_0 [32]
+3VPCU [6,30,32,33,34,35,37,38]
CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3
CSI2_COMP
GPP_D4/FLASHTRIG
EMMC
GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7
GPP_F21/EMMC_RCLK
GPP_F22/EMMC_CLK
GPP_F12/EMMC_CMD
EMMC_RCOMP
9 OF 20REV = 1
C37
D37
C32
D32
C29
D29
B26
A26
E13
B7
AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1
AM2
AM3
AP4
AT1
GPP_D4
GPP_F13
GPP_F14
GPP_F15
GPP_F16
GPP_F17
GPP_F18
GPP_F19
GPP_F20
EMMC_RCLK
EMMC_CLK
EMMC_CMD
EMMC_RCOMP
4
R481 100/F_4
TP84
TP124
TP123
TP122
TP121
TP120
TP119
TP115
TP116
TP117
TP118
TP125
R547 200/F_4
R279
20K/F_4
R280
20K/F_4
+3V_RTC +3VPCU +3V_RTC_0
30mils
C521
1U/6.3V_4
D6
BAT54CW-7-F
+3V_RTC_1
RTC Power trace width 20mils.
R291
*0_6
3
C446
1U/6.3V_4
C447
1U/6.3V_4
3
1
Q18
2N7002K
2
R292
*0_6
1223 change J1 to R524 unmount
Function for RESET.
R289
10K_4
2
3.135VPass by G-CLK = 2.712V
IC because G-CLK has more ΔV.
R332
1K_4
12
CN9
BAT_CONN
RTC_RST# [16]
EC_RTC_RST [35]
RTC Circuitry(RTC)
EC_RTC_RST:
Watch Dog for system can't boot and
need remove RTC battery & clear CMOS.
C
C
C
Date:
Date:
Date:
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
PROJECT : TWL & JWL ( MB )
PROJECT : TWL & JWL ( MB )
PROJECT : TWL & JWL ( MB )
Document Number
Document Number
Document Number
SKL-12 (CLK/eMMC)
SKL-12 (CLK/eMMC)
SKL-12 (CLK/eMMC)
Wednesday, July 29, 2015
Wednesday, July 29, 2015
Wednesday, July 29, 2015
Sheet :
Sheet :
Sheet :
1
of
of
of
13 51
13 51
13 51
Rev.Size
Rev.Size
Rev.Size
3C
3C
3C
5
4
3
2
1
Skylake (GPIO)
U25F
AN8
GPP_B15/GSPI0_CS#
AP7
GPP_B16/GSPI0_CLK
AP8
GPP_B17/GSPI0_MISO
AR7
GPP_B18/GSPI0_MOSI
AM5
GPP_B19/GSPI1_CS#
AN7
GPP_B20/GSPI1_CLK
AP5
GPP_B21/GSPI1_MISO
AN5
GPP_B22/GSPI1_MOSI
AB1
GPP_C8/UART0_RXD
AB2
GPP_C9/UART0_TXD
W4
GPP_C10/UART0_RTS#
AB3
GPP_C11/UART0_CTS#
AD1
GPP_C20/UART2_RXD
AD2
GPP_C21/UART2_TXD
AD3
GPP_C22/UART2_RTS#
AD4
GPP_C23/UART2_CTS#
U7
GPP_C16/I2C0_SDA
U6
GPP_C17/I2C0_SCL
U8
GPP_C18/I2C1_SDA
U9
GPP_C19/I2C1_SCL
AH9
GPP_F4/I2C2_SDA
AH10
GPP_F5/I2C2_SCL
AH11
GPP_F6/I2C3_SDA
AH12
GPP_F7/I2C3_SCL
AF11
GPP_F8/I2C4_SDA
AF12
GPP_F9/I2C4_SCL
*SKL_ULT
BA22
AY22
BB22
BA21
AY21
AW22
J5
AY20
AW20
AK7
AK6
AK9
AK10
H5
D7
D8
C8
AW5
TP31
TP32
TP33
TP27
TP83
TP89
TP85
TP92
GPP_B15
GPP_B16
GPP_B17
GPP_B18
GPP_B19
GPP_B20
GPP_B21
GSPI1_MOSI
GPP_C8
GPP_C9
GPP_C10
GPP_C11
UART2_RXD
UART2_TXD
ACCEL_INTA#
SIO_EXT_SCI#
I2C1_SDA
I2C1_SCL
I2C2_SDA
I2C2_SCL
I2C3_SDA
I2C3_SCL
I2C4_SDA
I2C4_SCL
ACZ_SYNC
ACZ_BCLK
ACZ_SDOUT
ACZ_SDIN0
ACZ_RST#
SSP2_SFRM
SSP2_SCLK
SSP2_TXD
SSP2_RXD
GPP_D19
GPP_D20
GPP_D17
GPP_D18
TP49
TP48
R557
*1K_4
TP56
TP36
TP46
TP39
TP108
TP107
TP109
TP19
TP21
TP28
TP26
TP29
TP35
TP22
TP30
+3V_DEEP_SUS
D D
BT_OFF_PCH
PCH_TEMPALERT#
SIO_EXT_SCI#
UART2_RXD
UART2_TXD
1227 Add R536 and R537 for
UART2 function reserved
ACCEL_INTA#
R516 10K_4
R523 10K_4
R544 10K_4
R543 49.9K/F_4
R542 49.9K/F_4
R545 10K_4
20150320A-ACCEL_INTA#, X1B connect with G-sensor.
20150518A-Add UART2_RXD & UART2_TXD for USB debug.
20150720A-Remove UART switch circiut to same with DB.
+3V
GPP_B18[11]
GSPI1_MOSI[11]
ACCEL_INTA#
SIO_EXT_SCI#[35]
1223 Add R525
C C
+3V_DEEP_SUS
HDA Bus(CLG)
ACZ_SYNC_AUDIO[27]
BIT_CLK_AUDIO[27]
ACZ_SDOUT[11]
ACZ_SDOUT_AUDIO[27]
ACZ_SDIN0[27]
ACZ_RST#_AUDIO[27]
B B
ACZ_SPKR[11,27]
R556 33_4
R558 33_4
C749
*10P/50V_4
R559 33_4
R555 33_4
ACZ_SPKR
LPSS ISH
U25G
AUDIO
HDA_SYNC/I2S0_SFRM
HDA_BLK/I2S0_SCLK
HDA_SDO/I2S0_TXD
HDA_SDI0/I2S0_RXD
HDA_SDI1/I2S1_RXD
HDA_RST#/I2S1_SCLK
GPP_D23/I2S_MCLK
I2S1_SFRM
I2S1_TXD
GPP_F1/I2S2_SFRM
GPP_F0/I2S2_SCLK
GPP_F2/I2S2_TXD
GPP_F3/I2S2_RXD
GPP_D19/DMIC_CLK0
GPP_D20/DMIC_DATA0
GPP_D17/DMIC_CLK1
GPP_D18/DMIC_DATA1
GPP_B14/SPKR
SKL_ULT
SKL_ULT
GPP_D9
GPP_D10
GPP_D11
GPP_D12
GPP_D5/ISH_I2C0_SDA
GPP_D6/ISH_I2C0_SCL
GPP_D7/ISH_I2C1_SDA
GPP_D8/ISH_I2C1_SCL
GPP_F10/I2C5_SDA/ISH_I2C2_SDA
GPP_F11/I2C5_SCL/ISH_I2C2_SCL
GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA
GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL
GPP_D16/ISH_UART0_CTS#/SML0BALERT#
GPP_C14/UART1_RTS#/ISH_UART1_RTS#
GPP_C15/UART1_CTS#/ISH_UART1_CTS#
SDIO/SDXC
GPP_A17/SD_PWR_EN#/ISH_GP7
GPP_D15/ISH_UART0_RTS#
GPP_C12/UART1_RXD/ISH_UART1_RXD
GPP_C13/UART1_TXD/ISH_UART1_TXD
GPP_A18/ISH_GP0
GPP_A19/ISH_GP1
GPP_A20/ISH_GP2
GPP_A21/ISH_GP3
GPP_A22/ISH_GP4
GPP_A23/ISH_GP5
GPP_A12/BM_BUSY#/ISH_GP6
6 OF 20REV = 1
GPP_F23
AB11
AB13
AB12
W12
W11
W10
W8
W7
BA9
BB9
AB7
AF13
GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3
GPP_G5/SD_CD#
GPP_G6/SD_CLK
GPP_G7/SD_WP
GPP_A16/SD_1P8_SEL
SD_RCOMP
P2
P3
P4
P1
M4
N3
N1
N2
AD11
AD12
U1
U2
U3
U4
AC1
AC2
AC3
AB4
AY8
BA8
BB7
BA7
AY7
AW7
AP13
BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4
BOARD_ID5
BOARD_ID6
BOARD_ID7
BOARD_ID8
R180
200/F_4
GPP_D9
3D_CAM_EN_PCH
GPP_D11
BT_OFF_PCH
ISH_I2C0_SDA
ISH_I2C0_SCL
ISH_I2C1_SDA
ISH_I2C1_SCL
ISH_I2C2_SDA
ISH_I2C2_SCL
PCH_TEMPALERT#
SML0BDATA
SML0BCLK
SML0BALERT#
UART1_RXD
UART1_TXD
UART1_RTS
UART1_CTS
GPP_A18
GPP_A19
GPP_A20
GPP_A21
GPP_A22
GPP_A23
GPP_A12
TP128
0114
Del TP57, Add R547 with 0ohm
TP100
unmount for 3D camera
TP99
TP94
TP14
TP15
TP95
TP98
TP24TP110
TP23
TP103
TP104
TP102
TP101
TP113
TP114
TP112
TP111
TP127
TP131
TP135
TP134
TP130
TP53
TP54
R529 *10K_4
R530 10K_4
BT_OFF_PCH [30]
+3V_DEEP_SUS
R525 *10K_4
R526 10K_4
R514 *10K_4
R517 10K_4
R508 *10K_4
R515 10K_4
R509 10K_4
R518 *10K_4
R506 *10K_4
R521 10K_4
R522 *10K_4
R571 *10K_4
R527 *10K_4
R561 10K_4
R528 10K_4
R507 10K_4
14
*SKL_ULT
BOARD_ID0
Model
TWL + UMA
TWL + dGPU + N16S
A A
JWL + UMA
JWL + dGPU + N16S
JWL + dGPU + N16V
TWL : 0
JWL : 1
0
0 0 0 0
0
1
1 1
1 1
BOARD_ID1 BOARD_ID2 BOARD_ID3 BOARD_ID4 BOARD_ID5
GPP_G1 GPP_G2 GPP_G3 GPP_G4 GPP_G5GPP_G0
No Define N16V : 0
N16S : 1
No Define No Define
UMA : 0
dGPU : 1
00000
11
1
0 0 0 0
0000TWL + dGPU + N16V
000
1
00000
BOARD_ID6
GPP_G6
No Define
0
0
0
0
0
0
BOARD_ID7
GPP_G7
No Define
0
0
0
0
0
0
BOARD_ID8
GPP_G8
No Define
0
0
0
0
0
0
20141008A-BIOS request for SVID, N16S-GT need PU GPIO58 ( BOARD_ID2 ).
+3V
+3V_DEEP_SUS
5
4
+3V [2,4,10,11,12,13,15,16,17,18,19,21,22,24,25,26,27,28,29,30,31,33,34,35,36,42,44,45,46]
+3V_DEEP_SUS [4,10,11,12,15,16,18]
3
7 OF 20REV = 1
GPP_F23
TP25
20150518A-Add GPP_A16 for USB debug.
20150720A-Remove UART switch circiut to same with DB.
2
Document Number
Document Number
C
C
C
Date:
Date:
Date:
Document Number
Wednesday, July 29, 2015
Wednesday, July 29, 2015
Wednesday, July 29, 2015
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
PROJECT : TWL & JWL ( MB )
PROJECT : TWL & JWL ( MB )
PROJECT : TWL & JWL ( MB )
SKL-13 (GPIO)
SKL-13 (GPIO)
SKL-13 (GPIO)
Sheet :
Sheet :
Sheet :
1
of
of
of
14 51
14 51
14 51
Rev.Size
Rev.Size
Rev.Size
3C
3C
3C
5
PCH Internal VRM
C820 and C690 close to cpu less then 100 mils
4
3
0107 Change R129 connection from
+VCCPRIM_1.0V to +VCCPRIM_1.0V_T1
2
1
15
C296 1U/6.3V_4
+1.0V_DEEP_SUS
D D
C C
C724 1U/6.3V_4
+3VS5
R513 100K_4
C229 *22U/6.3V_6
+3V_DEEP_SUS
C221 *1U/6.3V_4
+VCCDSW_1.0V
C218 1U/6.3V_4
C317 1U/6.3V_4
C213 47U/6.3V_Y8
C284 1U/6.3V_4
+3VS5
for DS3
U24
5
IN
4
IN
SLP_SUS_ON[35,40,41]
C721
*10P/50V_4
3
ON/OFF
G5243AT11U
OUT
GND
1
2
C725
0.1U/16V_4
C283 1U/6.3V_4
C210 1U/6.3V_4
C337 1U/6.3V_4
C741 1U/6.3V_4
R156 *0_6/S
R181 0_6
1223 R185 mount,R184 unmount
0106 Del R184
R266 *0_4/S
C301 1U/6.3V_4
+3V
R206 *0_4/S
C335 1U/6.3V_4
R201 *0_6/S
R188 0_6
R209 *0_6/S
R205 *0_6/S
R127 *0_6/S
R157 *0_6/S
R178 *0_6/S
+V3.3DX_1.5DX_ADO
+VCCPRIM
+VCCMPHYAON_1P0
+VCCAMPHYPLL_1P0
+VCCAPLL_1.0V
+VCCPRIM
+VCCSPI
+VCCSRAM_1.0V
+VCCPRIM_3.3V
+VCCPRIM_1.0V
+VCCAPLLEBB
U25O
AB19
VCCPRIM_1P0
AB20
VCCPRIM_1P0
P18
VCCPRIM_1P0
AF18
VCCPRIM_CORE
AF19
VCCPRIM_CORE
V20
VCCPRIM_CORE
V21
VCCPRIM_CORE
AL1
DCPDSW_1P0
K17
VCCMPHYAON_1P0
L1
VCCMPHYAON_1P0
N15
VCCMPHYGT_1P0_N15
N16
VCCMPHYGT_1P0_N16
N17
VCCMPHYGT_1P0_N17
P15
VCCMPHYGT_1P0_P15
P16
VCCMPHYGT_1P0_P16
K15
VCCAMPHYPLL_1P0
L15
VCCAMPHYPLL_1P0
V15
VCCAPLL_1P0
AB17
VCCPRIM_1P0_AB17
Y18
VCCPRIM_1P0_Y18
AD17
VCCDSW_3P3_AD17
AD18
VCCDSW_3P3_AD18
AJ17
VCCDSW_3P3_AJ17
AJ19
VCCHDA
AJ16
VCCSPI
AF20
VCCSRAM_1P0
AF21
VCCSRAM_1P0
T19
VCCSRAM_1P0
T20
VCCSRAM_1P0
AJ21
VCCPRIM_3P3_AJ21
AK20
VCCPRIM_1P0_AK20
N18
VCCAPLLEBB
*SKL_ULT
SKL_ULT
CPU POWER 4 OF 4
2.899A
2.57A
1.714A
0.03A
0.09A
VCCPGPPA
VCCPGPPB
VCCPGPPC
VCCPGPPD
VCCPGPPE
VCCPGPPF
VCCPGPPG
VCCPRIM_3P3_V19
VCCPRIM_1P0_T1
VCCATS_1P8
VCCRTCPRIM_3P3
VCCRTC_AK19
VCCRTC_BB14
DCPRTC
VCCCLK1
VCCCLK2
VCCCLK3
VCCCLK4
VCCCLK5
VCCCLK6
GPP_B0/CORE_VID0
GPP_B1/CORE_VID1
15 OF 20REV = 1
AK15
AG15
Y16
Y15
T16
AF16
AD15
V19
T1
+VCCPRIM_1.0V_T1
AA1
+VCCATS_1.8V
AK17
+VCCRTCPRIM_3.3V
AK19
BB14
BB10
DCPRTC
A14
+VCCCLK1
K19
+VCCCLK2
L21
+VCCCLK3
N20
+VCCCLK4
L19
+VCCCLK5
A10
+VCCCLK6
AN11
AN13
+VCCPGPPA
+VCCPGPPB
+VCCPGPPC
+VCCPGPPD
+VCCPGPPE
+VCCPGPPF
+VCCPGPPG
CORE_VID0
CORE_VID1
+3V_DEEP_SUS
R218 *0_6/S
R199 *0_6/S
R179 *0_6/S
R187 *0_6/S
R183 *0_6/S
R197 *0_6/S
R524 *0_6/S
R533 *0_6/S
R222 *0_6/S
C750 0.1U/16V_4
R447 *0_6/S
R148 *0_6/S
R133 *0_6/S
R134 *0_6/S
R149 *0_6/S
R446 *0_6/S
C709 1U/6.3V_4
TP37
TP52
+VCCRTCPRIM_3.3V +VCCATS_1.8V+3V_RTC +VCCPGPPB+VCCPGPPC+VCCPGPPE
C401 1U/6.3V_4
C363 0.1U/16V_4
C380 0.1U/16V_4
C381 1U/6.3V_4
R186 *0_6/S
+1.8V_DEEP_SUS
+3V_RTC
C731 1U/6.3V_4
+1.8V_DEEP_SUS
C282 1U/6.3V_4
+3V_DEEP_SUS
C302
1U/6.3V_4
+1.0V_DEEP_SUS
C268 1U/6.3V_4
C327 1U/6.3V_4
B B
+1.0V_DEEP_SUS
+1.8V_DEEP_SUS
+3V
A A
+3V_DEEP_SUS
+3V_RTC
+3VS5
+V3.3DX_1.5DX_ADO
+VCCATS_1.8V
+VCCDSW_1.0V
+VCCPGPPB
+VCCPGPPC
+VCCPGPPE
+VCCRTCPRIM_3.3V
5
+1.0V_DEEP_SUS [9,13,16,40,41]
+1.8V_DEEP_SUS [9,40]
+3V_DEEP_SUS [4,10,11,12,14,16,18]
+V3.3DX_1.5DX_ADO
+VCCDSW_1.0V
+VCCRTCPRIM_3.3V
+3V [2,4,10,11,12,13,14,16,17,18,19,21,22,24,25,26,27,28,29,30,31,33,34,35,36,42,44,45,46]
+3V_RTC [4,13,32]
+3VS5 [4,10,16,27,30,33,35,36,38,40,41,44,47]
+VCCATS_1.8V
+VCCPGPPB
+VCCPGPPC
+VCCPGPPE
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
PROJECT : TWL & JWL ( MB )
PROJECT : TWL & JWL ( MB )
PROJECT : TWL & JWL ( MB )
Document Number
Document Number
Document Number
SKL-14 (PCH POWER)
SKL-14 (PCH POWER)
C
C
C
Date:
Date:
Date:
4
3
2
SKL-14 (PCH POWER)
Wednesday, July 29, 2015
Wednesday, July 29, 2015
Wednesday, July 29, 2015
Sheet :
Sheet :
Sheet :
1
of
of
of
15 51
15 51
15 51
Rev.Size
Rev.Size
Rev.Size
3C
3C
3C
5
4
3
2
1
JTAG_TCK_PCH[2]
D D
C C
XDP_TCK1
CFG0[9]
+3V
R220
1K_4
C383
0.1U/16V_4
R225 *0_4
XDP_TCK0[2]
JTAGX_PCH[2]
1218 Change R86
connection from +1.0V
to +VCCIO
R230
150/F_4
R229
*10K_4
R452 *0_4
R231 1K_4
XDP_PREQ#_CPU[12]
XDP_PRDY#_CPU[12]
CFG1[9]
CFG2[9]
CFG3[9]
CFG4[9]
CFG5[9]
CFG6[9]
CFG7[9]
ON/OFFBTN_KBC#[16]
CK_XDP_P[13]
CK_XDP_N[13]
SMB_RUN_DAT[10,17,18,24,34]
SMB_RUN_CLK[10,17,18,24,34]
R224 *0_4
+1.0V
R228 *0_4
R227 *0_4
0116 Change CN2 footprint
R233 1K_4
R232 1K_4
PWR_DEBUG
XDP_DBRESET_N
SMB_RUN_DAT_XDP
SMB_RUN_CLK_XDP
XDP_TCK0
16
+1.0V_DEEP_SUS+VCCIO
C411 0.1U/16V_4
C412 0.1U/16V_4
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25
25
26
26
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
525253
53
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
TP55
XDP_TCK1
XDP_RST
CN7
*FH26W-51S-0.3SHW(05)
+3V
XDP_BPM0 [2]
XDP_BPM1 [2]
CFG17 [9]
CFG16 [9]
CFG8 [9]
CFG9 [9]
CFG10 [9]
CFG11 [9]
CFG19 [9]
CFG18 [9]
CFG12 [9]
CFG13 [9]
CFG14 [9]
CFG15 [9]
EC_PWROK [4,35]
+3V_DEEP_SUS
R235
*1K_4
C384
0.1U/16V_4
R2341K_4
SYS_PWROK [4]
PLTRST# [4,19,26,28,29,30,33,35]
R221
51_4
JTAG_TDO_PCH[2]
R226
*0_4
B B
APS
CN6
A A
*ACES_88511-180N
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
5
+3VS5+3V_DEEP_SUS
R168 *0_4
SUSB# [4,16,35]
SLP_S5# [4]
SUSC# [4,35]
SLP_A# [4]
RTC_RST# [13]
ON/OFFBTN_KBC# [16]
SYS_RESET# [4]
PCH_SLP_S0_N [4,35]
SUSB# [4,16,35]
4
JTAG_TDI_PCH[2]
JTAG_TMS_PCH[2]
+1.0V
+1.0V_DEEP_SUS
+3V
+3V_DEEP_SUS
+3VS5
+VCCIO
+1.0V_DEEP_SUS [9,13,15,40,41]
+3V_DEEP_SUS [4,10,11,12,14,15,18]
+1.0V [2,4,6,32,35,41]
+3V [2,4,10,11,12,13,14,15,17,18,19,21,22,24,25,26,27,28,29,30,31,33,34,35,36,42,44,45,46]
+3VS5 [4,10,15,27,30,33,35,36,38,40,41,44,47]
+VCCIO [2,6,41]
3
HWPG[4,35,38,39,40]
C307
0.1U/16V_4
XDP_TDO
XDP_TDI
XDP_TMS
XDP_TRST#
2
U9
14
VCC
2
1A
1
1OE
5
2A
4
2OE
9
3A
10
3OE
12
4A
13
4OE
*SN74CBTLV3126RGYR
Document Number
Document Number
Document Number
B
B
B
Date:
Date:
Date:
Wednesday, July 29, 2015
Wednesday, July 29, 2015
Wednesday, July 29, 2015
3
1B
6
2B
8
3B
11
4B
15
DPAD
7
GND
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
Quanta Computer Inc.Quanta Computer Inc.
PROJECT : TWL & JWL ( MB )
PROJECT : TWL & JWL ( MB )
PROJECT : TWL & JWL ( MB )
SKL-15 (XDP & APS)
SKL-15 (XDP & APS)
SKL-15 (XDP & APS)
Sheet :
Sheet :
Sheet :
XDP_TDO_CPU [2]
XDP_TDI_CPU [2]
XDP_TMS_CPU [2]
XDP_TRST#_CPU [2]
of
of
of
16 51
16 51
16 51
1
Rev.Size
Rev.Size
Rev.Size
3C
3C
3C
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