Quanta TWL Schematic

5

www.schematic-x.blogspot.com

4

3

2

1

01

TWL + JWL Intel SKYLAKE-U Platform Block Diagram

D D

DDR3L SO-DIMM-0 Maxima 8GBs

Front Side / REV Type

DDR3L SO-DIMM-1 Maxima 8GBs

Rear Side / STD Type

SATA HDD Package : 9.5 (mm)

TWL SATA ODD Board

C C

USB3.0 Port

Left / Front Side

PAGE 33

PAGE 32

SATA ODD Package : 12.7 (mm)

NGFF SSD

Package : 2280 & 2242

Full mini-PCIe Card - SSD

TPS2546

Package : QFN-16

PAGE 32

PAGE 17

PAGE 18

PAGE 33

PAGE 31

USB3.0 Port-1 & USB2.0 Port-1

DDR3L CH-A

DDR3L CH-B

SATA0 6GB/s Port-0

SATA1 3GB/s Port-1

SATA2 6GB/s Port-2

Skylake-U ES sample

QHMF - AJ0QHMFUT03 CPU(1356P)ULV 2.3G QHMF(BGA)

QHMG - AJ0QHMGVT03 CPU(1356P)ULV 1.6G QHMG(BGA)

Processor : Daul Core

TDP : 15 (Watt)

Package : BGA, 1356-PIN BGA1356

Size : 42 X 24 X 1.213 (mm)

PCI-e X4 Lane

Port-1~4

eDP X 2

eDP Port-0 & 1

DDI Port-1

DDI Port-2

NVIDIA N16V-GM / GT920M N16S-GT / GT940M

Power : 25 (Watt)

Package : S3 Size : 23 x 23 (mm)

PAGE-19~22

27MHz

RTD2136

Package : QFN-32

eDP

ANX6210

Package : QFN-40

27MHz

1-Channel 64Bit

PAGE 24

PAGE 26

Graphics 4Gb/2Gb DDR3L SDRAM

1.0GHz / 16-Bit

PAGE-23

JWL Panel

TWL Panel (2-CH)

PAGE 25

Camera

USB2.0 Port-3

PAGE 25

HDMI

PAGE 25

CRT

PAGE 26

JWL

USB3.0 Port

Left / Rear Side

PAGE 32

USB Board

B B

USB2.0 Port USB2.0 Port-6

Right Side

PAGE 27

Combo Jack Ext. Headphone & MIC

PAGE 27

Speaker 4Ω , Normal 1.5W

PAGE 27

Digital MIC with Camera

A A

PAGE 25

USB3.0 Port-2 & USB2.0 Port-2

Audio Codec

ALC255-CG

Package : MQFN48 Size : 6 x 6 (mm)

w w w . c h i n a f i x . c o m

PAGE 27

Azalia

SPI

System BIOS & EC F/W

PAGE 10

PCIE Gen 1 x 1 Lane Port-5

PCIE Gen 1 x 1 Lane Port-9

PCIE Gen 1 x 1 Lane Port-6

PAGE-2~16

LPC

Embedded ControllerSPI ROM 16MByte

IC CTRL(128P) IT8987E/BX(LQFP)

Package : LQFP Size : 16 x 16 (mm)

PAGE 35

Card Reader

Package : QFN32 Size : 4 x 4 (mm)

LAN Controller

Package : OFN32

NGFF WLAN

Half mini-PCIe Card WLAN & BT Combo Card

USB2.0 Port-5

JWL Power Button Board TWL Power Button Board LID Switch

RTS5227S-GRT

PAGE 29

RTL8111H-CG(Giga)

PAGE 28

Package : 2230

PAGE 30

PAGE 33

TWL

Card Slot SD Card MMC Card

RJ45

PCB 6L STACK UP

LAYER-1 : TOP LAYER-2 : SGND LAYER-3 : IN1(High) LAYER-4 : IN2(Low) LAYER-5 : SVCC LAYER-6 : BOT

5

JWL

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

Keyboard

PAGE 34

4

Touch Pad

PAGE 34

3

FAN

PAGE 33

TWL BATTERY

PAGE 37

C

Date:

2

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

Block Diagram

Wednesday, July 29, 2015

Sheet :

1

of

1 51

Rev.Size

3C

5

4

3

2

1

U25A

IN_D2#[25] IN_D2[25] IN_D1#[25] IN_D1[25]

HDMI

D D

CRT

+3V

IN_D0#[25] IN_D0[25] IN_CLK#[25] IN_CLK[25]

DDI2_CRT_TX0N[26] DDI2_CRT_TX0P[26]

20150309A-DDPC_CTRLDATA This signal needs to be pulled up through a 2.2 KΩ ±5% pull-up to

3.3V to enable Port -C.

R125

2.2K_4

R123 *2.2K_4

+VCCIO

R173 24.9/F_4

TP20

SDVO_CLK[25] SDVO_DATA[25]

DDPC_CTRLCLK DDPC_CTRLDATA

DDPD_CTRLDATA

EDP_RCOMP

X1B 1218 change connection from +1.0V to +VCCIO.

E55

DDI1_TXN[0]

F55

DDI1_TXP[0]

E58

DDI1_TXN[1]

F58

DDI1_TXP[1]

F53

DDI1_TXN[2]

G53

DDI1_TXP[2]

F56

DDI1_TXN[3]

G56

DDI1_TXP[3]

C50

DDI2_TXN[0]

D50

DDI2_TXP[0]

C52

DDI2_TXN[1]

D52

DDI2_TXP[1]

A50

DDI2_TXN[2]

B50

DDI2_TXP[2]

D51

DDI2_TXN[3]

C51

DDI2_TXP[3]

L13

GPP_E18/DDPB_CTRLCLK

L12

GPP_E19/DDPB_CTRLDATA

N7

GPP_E20/DDPC_CTRLCLK

N8

GPP_E21/DDPC_CTRLDATA

N11

GPP_E22/DDPD_CTRLCLK

N12

GPP_E23/DDPD_CTRLDATA

E52

EDP_RCOMP

*SKL_ULT

SKL_ULT

DDI

CRT

DISPLAY SIDEBANDS

eDP/LVDSHDMI

EDP

GPP_E13/DDPB_HPD0 GPP_E14/DDPC_HPD1 GPP_E15/DDPD_HPD2 GPP_E16/DDPE_HPD3

EDP_TXN[0] EDP_TXP[0] EDP_TXN[1] EDP_TXP[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]

EDP_AUXN EDP_AUXP

EDP_DISP_UTIL

DDI1_AUXN DDI1_AUXP DDI2_AUXN DDI2_AUXP DDI3_AUXN DDI3_AUXP

GPP_E17/EDP_HPD

EDP_BKLTEN

EDP_BKLTCTL

EDP_VDDEN

1 OF 20REV = 1

C47 C46 D46 C45 A45 B45 A47 B47

E45 F45

B52 G50

F50 E48 F48 G46 F46

L9 L7 L6 N9 L10

R12 R11 U13

EDP_DISP_UTIL

DDI2_CRT_HPD_Q [26]

INT_EDP_TXN0 [24] INT_EDP_TXP0 [24] INT_EDP_TXN1 [24] INT_EDP_TXP1 [24]

INT_EDP_AUXN [24]

INT_EDP_AUXP [24]

TP88

DDI2_CRT_AUXN [26] DDI2_CRT_AUXP [26]

HDMI_HPD_CON [25]

PCH_LVDS_BLON [25]

PCH_DPST_PWM [24,25]

PCH_DISP_ON [25]

eDP or LVDS

+3V

R163 *10K/F_4

ULT_EDP_HPD [24,25]

R162 100K_4

02

Reserve EDP_HPD opposites circuit ! EDP_HPD need pull down via 100KΩ.

eDP_COMPIO and ICOMPO signals should be shorted near

C C

balls and routed with typical impedance < 25 mΩ.

PLACE NEAR CPU

R489 51_4 R143 *51_4

R497 *51_4

1218 Unmount R380, R367

+VCCSTPLL

B B

H_PROCHOT#[35,37,42]

Close to EC Processor pull-up (CPU) TO BE REPLACED WITH 1K OHMS FOR SKL . 470 OHM IS FOR I/P

PM_THRMTRIP#[35]

+1.0V

R479 1K_4

+VCCSTPLL

R453 1K_4

R485 499/F_4

TP13

EC_PECI[35]

XDP_BPM0[16] XDP_BPM1[16]

TP86 TP87 TP132 TP129

R262 49.9/F_4 R259 49.9/F_4 R520 49.9/F_4 R519 49.9/F_4

X1B-1223 change to un-mount.

R137 *49.9/F_4

CATERR# EC_PECI PROCHOT# PM_THRMTRIP#

3D_FW_GPIO_R CPU_GP1 CPU_GP2 CPU_GP3

PROC_POPIRCOMP PCH_OPI_RCOMP EDRAM_OPIO_RCOMP EOPIO_RCOMP

D63

CATERR#

A54

PECI

C65

PROCHOT#

C63

THERMTRIP#

A65

SKTOCC#

C55

BPM#[0]

D55

BPM#[1]

B54

BPM#[2]

C56

BPM#[3]

A6

GPP_E3/CPU_GP0

A7

GPP_E7/CPU_GP1

BA5

GPP_B3/CPU_GP2

AY5

GPP_B4/CPU_GP3

AT16

PROC_POPIRCOMP

AU16

PCH_OPIRCOMP

H66

OPCE_RCOMP

H65

OPC_RCOMP

*SKL_ULT

U25D

SKL_ULT

CPU MISC

JTAG

PROC_TCK

PROC_TDI

PROC_TDO

PROC_TMS

PROC_TRST#

PCH_JTAG_TCK

PCH_JTAG_TDI

PCH_JTAG_TDO

PCH_JTAG_TMS

PCH_TRST#

BOM

4 OF 20REV = 1

JTAGX

B61 D60 A61 C60 B59

B56 D59 A56 C59 C61 A59

R493 *51_4

R492 51_4

R488 51_4

R144 51_4

R487 51_4

R450 51_4

R451 *51_4

+1.0V

XDP_TCK0 [16]

XDP_TDI_CPU [16]

XDP_TDO_CPU [16]

XDP_TMS_CPU [16]

XDP_TRST#_CPU [16]

JTAG_TCK_PCH [16]

JTAG_TDI_PCH [16]

JTAG_TDO_PCH [16]

JTAG_TMS_PCH [16]

JTAGX_PCH [16]

+1.0V

R449 0_4

A A

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

+1.0V +3V +VCCIO +VCCSTPLL

+1.0V [4,6,16,32,35,41]

+3V [4,10,11,12,13,14,15,16,17,18,19,21,22,24,25,26,27,28,29,30,31,33,34,35,36,42,44,45,46]

+VCCIO [6,16,41]

+VCCSTPLL [4,5,6,9,41,42]

5

PROJECT : TWL & JWL ( MB )

Document Number

SKL-01 (eDP/DDI/MISC)

Custom

Date:

4

3

2

SKL-01 (eDP/DDI/MISC)

Wednesday, July 29, 2015

Sheet :

1

of

2 51

Rev.Size

3C

5

M_A_DQSN[7:0][17] M_A_DQSP[7:0][17] M_B_DQSN[7:0][18] M_B_DQSP[7:0][18] M_A_DQ[63:0][17] M_B_DQ[63:0][18]

4

3

2

1

03

D D

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3

A0

A1

C C

B0

B1

A2

A3

B B

B2

B3

M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7

M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7

M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15

M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23

M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31

M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23

M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31

SkyLake ULT Processor (DDR3L)

U25B

AL71

DDR0_DQ[0]

AL68

DDR0_DQ[1]

AN68

DDR0_DQ[2]

AN69

DDR0_DQ[3]

AL70

DDR0_DQ[4]

AL69

DDR0_DQ[5]

AN70

DDR0_DQ[6]

AN71

DDR0_DQ[7]

AR70

DDR0_DQ[8]

AR68

DDR0_DQ[9]

AU71

DDR0_DQ[10]

AU68

DDR0_DQ[11]

AR71

DDR0_DQ[12]

AR69

DDR0_DQ[13]

AU70

DDR0_DQ[14]

AU69

DDR0_DQ[15]

AF65

DDR1_DQ[0]/DDR0_DQ[16]

AF64

DDR1_DQ[1]/DDR0_DQ[17]

AK65

DDR1_DQ[2]/DDR0_DQ[18]

AK64

DDR1_DQ[3]/DDR0_DQ[19]

AF66

DDR1_DQ[4]/DDR0_DQ[20]

AF67

DDR1_DQ[5]/DDR0_DQ[21]

AK67

DDR1_DQ[6]/DDR0_DQ[22]

AK66

DDR1_DQ[7]/DDR0_DQ[23]

AF70

DDR1_DQ[8]/DDR0_DQ[24]

AF68

DDR1_DQ[9]/DDR0_DQ[25]

AH71

DDR1_DQ[10]/DDR0_DQ[26]

AH68

DDR1_DQ[11]/DDR0_DQ[27]

AF71

DDR1_DQ[12]/DDR0_DQ[28]

AF69

DDR1_DQ[13]/DDR0_DQ[29]

AH70

DDR1_DQ[14]/DDR0_DQ[30]

AH69

DDR1_DQ[15]/DDR0_DQ[31]

BB65

DDR0_DQ[16]/DDR0_DQ[32]

AW65

DDR0_DQ[17]/DDR0_DQ[33]

AW63

DDR0_DQ[18]/DDR0_DQ[34]

AY63

DDR0_DQ[19]/DDR0_DQ[35]

BA65

DDR0_DQ[20]/DDR0_DQ[36]

AY65

DDR0_DQ[21]/DDR0_DQ[37]

BA63

DDR0_DQ[22]/DDR0_DQ[38]

BB63

DDR0_DQ[23]/DDR0_DQ[39]

BA61

DDR0_DQ[24]/DDR0_DQ[40]

AW61

DDR0_DQ[25]/DDR0_DQ[41]

BB59

DDR0_DQ[26]/DDR0_DQ[42]

AW59

DDR0_DQ[27]/DDR0_DQ[43]

BB61

DDR0_DQ[28]/DDR0_DQ[44]

AY61

DDR0_DQ[29]/DDR0_DQ[45]

BA59

DDR0_DQ[30]/DDR0_DQ[46]

AY59

DDR0_DQ[31]/DDR0_DQ[47]

AT66

DDR1_DQ[16]/DDR0_DQ[48]

AU66

DDR1_DQ[17]/DDR0_DQ[49]

AP65

DDR1_DQ[18]/DDR0_DQ[50]

AN65

DDR1_DQ[19]/DDR0_DQ[51]

AN66

DDR1_DQ[20]/DDR0_DQ[52]

AP66

DDR1_DQ[21]/DDR0_DQ[53]

AT65

DDR1_DQ[22]/DDR0_DQ[54]

AU65

DDR1_DQ[23]/DDR0_DQ[55]

AT61

DDR1_DQ[24]/DDR0_DQ[56]

AU61

DDR1_DQ[25]/DDR0_DQ[57]

AP60

DDR1_DQ[26]/DDR0_DQ[58]

AN60

DDR1_DQ[27]/DDR0_DQ[59]

AN61

DDR1_DQ[28]/DDR0_DQ[60]

AP61

DDR1_DQ[29]/DDR0_DQ[61]

AT60

DDR1_DQ[30]/DDR0_DQ[62]

AU60

DDR1_DQ[31]/DDR0_DQ[63]

*SKL_ULT

SKL_ULT

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]

DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]

DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]

DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]

DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]

DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSP[1]/DDR0_DQSP[3] DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[3]/DDR0_DQSP[5] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSP[3]/DDR0_DQSP[7]

NIL-DDR CH A

DDR0_CKN[0] DDR0_CKP[0] DDR0_CKN[1] DDR0_CKP[1]

DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3]

DDR0_CS#[0] DDR0_CS#[1] DDR0_ODT[0] DDR0_ODT[1]

DDR0_MA[3] DDR0_MA[4]

DDR0_DQSN[0] DDR0_DQSP[0] DDR0_DQSN[1] DDR0_DQSP[1]

DDR0_ALERT#

DDR0_PAR

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

DDR_VTT_CNTL

2 OF 20REV = 1

AU53 AT53 AU55 AT55

BA56 BB56 AW56 AY56

AU45 AU43 AT45 AT43

BA51 BB54 BA52 AY52 AW52 AY55 AW54 BA54 BA55 AY54

AU46 AU48 AT46 AU50 AU52 AY51 AT48 AT50 BB50 AY50 BA50 BB52

AM70 AM69 AT69 AT70 AH66 AH65 AG69 AG70 BA64 AY64 AY60 BA60 AR66 AR65 AR61 AR60

AW50 AT52

AY67 AY68 BA67

AW67

M_A_DQSN0

M_A_DQSP0

M_A_DQSN1

M_A_DQSP1

M_B_DQSN0

M_B_DQSP0

M_B_DQSN1

M_B_DQSP1

M_A_DQSN2

M_A_DQSP2

M_A_DQSN3

M_A_DQSP3

M_B_DQSN2

M_B_DQSP2

M_B_DQSN3

M_B_DQSP3

DDR0_PAR

M_A_CLKN0 [17]

M_A_CLKP0 [17]

M_A_CLKN1 [17]

M_A_CLKP1 [17]

M_A_CKE0 [17]

M_A_CKE1 [17]

M_A_CS#0 [17]

M_A_CS#1 [17]

M_A_DIM0_ODT0 [17]

M_A_DIM0_ODT1 [17] M_B_DIM0_ODT0 [18]

M_A_A5 [17] M_A_A9 [17] M_A_A6 [17] M_A_A8 [17] M_A_A7 [17]

M_A_BS#2 [17]

M_A_A12 [17] M_A_A11 [17] M_A_A15 [17] M_A_A14 [17]

M_A_A13 [17]

M_A_CAS# [17]

M_A_WE# [17]

M_A_RAS# [17]

M_A_BS#0 [17]

M_A_A2 [17]

M_A_BS#1 [17]

M_A_A10 [17]

M_A_A1 [17] M_A_A0 [17] M_A_A3 [17] M_A_A4 [17]

TP47

SMDDR_VREF_DQ0_M3 [3,17] SMDDR_VREF_DQ1_M3 [3,18]

SM_VREF [3,17]

DDR_VTT_CNTL [4,18]

20mils width

A4

A5

B4

B5

A6

A7

B6

B7

M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39

M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47

M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39

M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47

M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55

M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55

M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

U25C

AY39

DDR0_DQ[32]/DDR1_DQ[0]

AW39

DDR0_DQ[33]/DDR1_DQ[1]

AY37

DDR0_DQ[34]/DDR1_DQ[2]

AW37

DDR0_DQ[35]/DDR1_DQ[3]

BB39

DDR0_DQ[36]/DDR1_DQ[4]

BA39

DDR0_DQ[37]/DDR1_DQ[5]

BA37

DDR0_DQ[38]/DDR1_DQ[6]

BB37

DDR0_DQ[39]/DDR1_DQ[7]

AY35

DDR0_DQ[40]/DDR1_DQ[8]

AW35

DDR0_DQ[41]/DDR1_DQ[9]

AY33

DDR0_DQ[42]/DDR1_DQ[10]

AW33

DDR0_DQ[43]/DDR1_DQ[11]

BB35

DDR0_DQ[44]/DDR1_DQ[12]

BA35

DDR0_DQ[45]/DDR1_DQ[13]

BA33

DDR0_DQ[46]/DDR1_DQ[14]

BB33

DDR0_DQ[47]/DDR1_DQ[15]

AU40

DDR1_DQ[32]/DDR1_DQ[16]

AT40

DDR1_DQ[33]/DDR1_DQ[17]

AT37

DDR1_DQ[34]/DDR1_DQ[18]

AU37

DDR1_DQ[35]/DDR1_DQ[19]

AR40

DDR1_DQ[36]/DDR1_DQ[20]

AP40

DDR1_DQ[37]/DDR1_DQ[21]

AP37

DDR1_DQ[38]/DDR1_DQ[22]

AR37

DDR1_DQ[39]/DDR1_DQ[23]

AT33

DDR1_DQ[40]/DDR1_DQ[24]

AU33

DDR1_DQ[41]/DDR1_DQ[25]

AU30

DDR1_DQ[42]/DDR1_DQ[26]

AT30

DDR1_DQ[43]/DDR1_DQ[27]

AR33

DDR1_DQ[44]/DDR1_DQ[28]

AP33

DDR1_DQ[45]/DDR1_DQ[29]

AR30

DDR1_DQ[46]/DDR1_DQ[30]

AP30

DDR1_DQ[47]/DDR1_DQ[31]

AY31

DDR0_DQ[48]/DDR1_DQ[32]

AW31

DDR0_DQ[49]/DDR1_DQ[33]

AY29

DDR0_DQ[50]/DDR1_DQ[34]

AW29

DDR0_DQ[51]/DDR1_DQ[35]

BB31

DDR0_DQ[52]/DDR1_DQ[36]

BA31

DDR0_DQ[53]/DDR1_DQ[37]

BA29

DDR0_DQ[54]/DDR1_DQ[38]

BB29

DDR0_DQ[55]/DDR1_DQ[39]

AY27

DDR0_DQ[56]/DDR1_DQ[40]

AW27

DDR0_DQ[57]/DDR1_DQ[41]

AY25

DDR0_DQ[58]/DDR1_DQ[42]

AW25

DDR0_DQ[59]/DDR1_DQ[43]

BB27

DDR0_DQ[60]/DDR1_DQ[44]

BA27

DDR0_DQ[61]/DDR1_DQ[45]

BA25

DDR0_DQ[62]/DDR1_DQ[46]

BB25

DDR0_DQ[63]/DDR1_DQ[47]

AU27

DDR1_DQ[48]

AT27

DDR1_DQ[49]

AT25

DDR1_DQ[50]

AU25

DDR1_DQ[51]

AP27

DDR1_DQ[52]

AN27

DDR1_DQ[53]

AN25

DDR1_DQ[54]

AP25

DDR1_DQ[55]

AT22

DDR1_DQ[56]

AU22

DDR1_DQ[57]

AU21

DDR1_DQ[58]

AT21

DDR1_DQ[59]

AN22

DDR1_DQ[60]

AP22

DDR1_DQ[61]

AP21

DDR1_DQ[62]

AN21

DDR1_DQ[63]

*SKL_ULT

SKL_ULT

DDR1_CKN[0] DDR1_CKN[1] DDR1_CKP[0] DDR1_CKP[1]

DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3]

DDR1_CS#[0] DDR1_CS#[1] DDR1_ODT[0] DDR1_ODT[1]

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]

DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]

DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]

DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSP[5]/DDR1_DQSP[1] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQSP[5]/DDR1_DQSP[3] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSN[7]/DDR1_DQSN[5] DDR0_DQSP[7]/DDR1_DQSP[5]

NIL-DDR CH B

BOM

DDR1_MA[3] DDR1_MA[4]

DDR1_DQSN[6] DDR1_DQSP[6] DDR1_DQSN[7] DDR1_DQSP[7]

DDR1_ALERT#

DDR1_PAR

DRAM_RESET# DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2]

AN45 AN46 AP45 AP46

AN56 AP55 AN55 AP53

BB42 AY42 BA42 AW42

AY48 AP50 BA48 BB48 AP48 AP52 AN50 AN48 AN53 AN52

BA43 AY43 AY44 AW44 BB44 AY47 BA44 AW46 AY46 BA46 BB46 BA47

BA38 AY38 AY34 BA34 AT38 AR38 AT32 AR32 BA30 AY30 AY26 BA26 AR25 AR27 AR22 AR21

AN43 AP43

DDR1_PAR

AT13 AR18

SM_RCOMP_0

AT18

SM_RCOMP_1

AU18

SM_RCOMP_2

3 OF 20REV = 1

M_B_CLKN0 [18]

M_B_CLKN1 [18]

M_B_CLKP0 [18]

M_B_CLKP1 [18]

M_A_DQSN4

M_A_DQSP4

M_A_DQSN5

M_A_DQSP5

M_B_DQSN4

M_B_DQSP4

M_B_DQSN5

M_B_DQSP5

M_A_DQSN6

M_A_DQSP6

M_A_DQSN7

M_A_DQSP7

M_B_DQSN6

M_B_DQSP6

M_B_DQSN7

M_B_DQSP7

M_B_CKE0 [18]

M_B_CKE1 [18]

M_B_CS#0 [18]

M_B_CS#1 [18]

M_B_CAS# [18] M_B_RAS# [18]

M_B_DIM0_ODT1 [18]

M_B_A5 [18] M_B_A9 [18] M_B_A6 [18] M_B_A8 [18] M_B_A7 [18]

M_B_BS#2 [18]

M_B_A12 [18] M_B_A11 [18] M_B_A15 [18] M_B_A14 [18]

M_B_A13 [18]

M_B_WE# [18]

M_B_BS#0 [18]

M_B_A2 [18]

M_B_BS#1 [18]

M_B_A10 [18]

M_B_A1 [18] M_B_A0 [18] M_B_A3 [18] M_B_A4 [18]

TP45

R244 121/F_4 R257 80.6/F_4 R247 100/F_4

+1.35VSUS

R346 470_4

DDR3_DRAMRST# [17,18]

A A

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

+1.35VSUS SM_VREF SMDDR_VREF_DQ0_M3 SMDDR_VREF_DQ1_M3

+1.35VSUS [6,17,18,36,39,41,47]

SMDDR_VREF_DQ0_M3 [3,17] SMDDR_VREF_DQ1_M3 [3,18]

5

SM_VREF [3,17]

Custom

Date:

4

3

2

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

SKL-02 (DDR3L)

Wednesday, July 29, 2015

Sheet :

1

of

3 51

Rev.Size

3C

5

4

3

2

1

PLTRST#(CLG)

Check Q2010 Rise/Fall time less than 100ns

PLTRST#[16,19,26,28,29,30,33,35]

R264 100K/F_4

SYS_RESET#[16]

+1.0V

21

RSMRST#[35]

R459 1K_4

X1B-1218 Reserve PU with +VCCSTPLL.

+VCCSTPLL

R458 *1K_4

H_VCCST_PWRGD_R

C703 *10P/50V_4

Close to CPU side H_VCCST_PWRGD trace length 0.3" - 1.5"

C717 *0.1U/16V_4

EC72 *220P/50V_4

R499 *10K_4

R457 60.4_4

R462 0_4

R461 10K/F_4

PLTRST# SYS_RESET# RSMRST#

PROCPWRGD H_VCCST_PWRGD

SYS_PWROK EC_PWROK

DSWROK_EC_R

SUSWARN# SUSACK#

PCIE_WAKE#

LAN_WAKE#

DDR_VTT_CNTL

U25K

AN10

GPP_B13/PLTRST#

B5

SYS_RESET#

AY17

RSMRST#

A68

PROCPWRGD

B65

VCCST_PWRGD

B6

SYS_PWROK

BA20

PCH_PWROK

BB20

DSW_PWROK

AR13

GPP_A13/SUSWARN#/SUSPWRDNACK

AP11

GPP_A15/SUSACK#

BB15

WAKE#

AM15

GPD2/LAN_WAKE#

AW17

GPD11/LANPHYPC

AT15

GPD7/RSVD

*SKL_ULT

SYSTEM POWER MANAGEMENT

SKL_ULT

200 mS

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

SLP_SUS# SLP_LAN#

GPD9/SLP_WLAN#

GPD6/SLP_A#

GPD3/PWRBTN#

GPD1/ACPRESENT

GPD0/BATLOW#

GPP_A11/PME#

INTRUDER#

GPP_B11/EXT_PWR_GATE#

GPP_B2/VRALERT#

11 OF 20REV = 1

AT11 AP15 BA16 AY16

AN15 AW15 BB17 AN16

BA15 AY15 AU13

AU11 AP16

AM10 AM11

PCH_SLP_S0_N

SLP_SUS#_EC GPD9

DNBSWON# AC_PRESENT_EC

WLAN_OFF_PCH

INTRUDER#_R

GPP_B2

TP133

R269 1M_4

TP40

PCH_SLP_S0_N [16,35]

AC_PRESENT_EC [35]

WLAN_OFF_PCH [30]

PCH Pull-high/low(CLG)

SUSWARN#

SUSACK#

WLAN_OFF_PCH

PCIE_WAKE# AC_PRESENT_EC

LAN_WAKE#

SYS_RESET# RSMRST# DSWROK_EC

R285 *10K_4 R281 10K_4 R258 10K_4

R563 1K_4 R564 *10K_4

R606 *10K_4

R443 10K_4 R569 10K_4 R570 100K/F_4

SUSB# [16,35] SUSC# [16,35]

SLP_S5# [16]

SLP_SUS#_EC [35]

SLP_A# [16]

DNBSWON# [35]

+3V_RTC

+3V_DEEP_SUS

+3VS5

SLP_SUS# : For platforms supporting Deep Sx state.

20150521A-X1B SUSWARN# abnormal waveform. SUSWARN# isn't OD. Remove pull high resistor.

X1B-1127 PU resistor for SUSACK# change to stuff .

20150520A-X61 auto-wake issue. LAN_WAKE# need to be pull high +3VPCU or +3VS5. ( LAN_WAKE# need pull high DSW power plane.

+3V

Commercial is +3VPCU, but consumer is +3VS5. )

D D

D8 RB500V-40

HWPG[16,35,38,39,40]

R177 100K_4

Q16

METR3904-G

+3VS5+1.0V

R175 10K_4

HWPG

3

Q15

2

2N7002K

1

R176 100K_4

+5VS5

R182 15K/F_4

C C

+1.0V_PWRGD_G2

2

1 3

C293

0.1U/16V_4

+1.0V_PWRGD_G1

R185 100K_4

System PWR_OK(CLG)

SYS_PWROK[16]

EC_PWROK[16,35]

B B

For DS3 Sequence Support DS3 --> Ra Non-DS3 --> Rb

RSMRST#

DSWROK_EC[35]

Rb

R560 *0_4

Ra

R565 0_4

04

SUSWARN#_EC[35]

SUSACK#_EC[35]

PCIE_WAKE#[28,29,30,35]

DDR_VTT_CNTL[3,18]

R293 0_4

R283 0_4

R282 *0_4

Need check circuit!!!! Should be delete

A A

+1.0V +3V +3V_DEEP_SUS +3V_RTC +3VS5 +5VS5 +VCCSTPLL

5

+1.0V [2,6,16,32,35,41]

+3V [2,10,11,12,13,14,15,16,17,18,19,21,22,24,25,26,27,28,29,30,31,33,34,35,36,42,44,45,46]

+3V_DEEP_SUS [10,11,12,14,15,16,18]

+3V_RTC [13,15,32]

+3VS5 [10,15,16,27,30,33,35,36,38,40,41,44,47] +5VS5 [27,32,36,38,39,40,41,42,43,44,45,46,47]

+VCCSTPLL [2,5,6,9,41,42]

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

SKL-03 (PowerManger)

C

Date:

4

3

2

SKL-03 (PowerManger)

Wednesday, July 29, 2015

Sheet :

1

of

4 51

Rev.Size

3C

5

4

3

2

1

05

SKL_ULT

CPU POWER 1 OF 4

VCC

VCC VCC

0.55~1.5V

0.55~1.5V0.55~1.5V 29A

29A

29A 29A

VCC_G32 VCC_G33 VCC_G35 VCC_G37 VCC_G38 VCC_G40 VCC_G42

VCC_J30 VCC_J33 VCC_J37

VCC_J40 VCC_K33 VCC_K35 VCC_K37 VCC_K38 VCC_K40 VCC_K42 VCC_K43

VCC_SENSE

VSS_SENSE

VIDALERT#

VIDSCK

VIDSOUT

VCCSTG_G20

BOM

12 OF 20REV = 1

G32 G33 G35 G37 G38 G40 G42 J30 J33 J37 J40 K33 K35 K37 K38 K40 K42 K43

E32 E33

B63 A63 D64

G20

+VCC_CORE

+VCCSTG

+1.0V

C185 47U/6.3V_8

C286 47U/6.3V_8

C690 47U/6.3V_8

C326 47U/6.3V_8

C193 47U/6.3V_8

C304 47U/6.3V_8

C184 47U/6.3V_8

C692 47U/6.3V_8

C256 10U/6.3V_4

C265 10U/6.3V_4

C257 10U/6.3V_4

C693 10U/6.3V_4

C705 10U/6.3V_4

C311 10U/6.3V_4

C246 10U/6.3V_4

C278 10U/6.3V_4

100Ω ±1% pull-up to VCC near processor.

20150519A-VCC_SENSE & VSS_SENSE has pull up resistor at CPU & Power side. Because need add more +VCC_CORE shape, so delete PU on CPU side.

VCC_SENSE [42]

VSS_SENSE [42]

+VCCSTPLL

CLOSE TO CPU

A30 A34 A39

A44 AK33 AK35 AK37 AK38 AK40 AL33 AL37 AL40

AM32 AM33 AM35 AM37 AM38

G30

K32 AK32 AB62

P62

V62

H63

G61

AC63

AE63 AE62

AG62

AL63

AJ62

*SKL_ULT

U25L

VCC_A30 VCC_A34 VCC_A39 VCC_A44 VCC_AK33 VCC_AK35 VCC_AK37 VCC_AK38 VCC_AK40 VCC_AL33 VCC_AL37 VCC_AL40 VCC_AM32 VCC_AM33 VCC_AM35 VCC_AM37 VCC_AM38 VCC_G30

RSVD_K32 RSVD_AK32 VCCOPC_AB62

VCCOPC_P62 VCCOPC_V62

VCC_OPC_1P8_H63 VCC_OPC_1P8_G61 VCCOPC_SENSE

VSSOPC_SENSE VCCEOPIO

VCCEOPIO VCCEOPIO_SENSE

VSSEOPIO_SENSE

Under CPU. Close CPU.

C295 1U/6.3V_4

D D

C C

C319 1U/6.3V_4

C330 1U/6.3V_4

C312 1U/6.3V_4

C329 1U/6.3V_4

C200 22U/6.3V_6

C186 47U/6.3V_Y8

C288 1U/6.3V_4

C267 1U/6.3V_4 C214 22U/6.3V_6

C694 22U/6.3V_6

C189 22U/6.3V_6

C345 1U/6.3V_4

C355 1U/6.3V_4

C259 1U/6.3V_4

C287 10U/6.3V_4

C203 10U/6.3V_6

C277 10U/6.3V_4

C704 22U/6.3V_6

C308 22U/6.3V_6

C211 22U/6.3V_6

+VCC_CORE

C354 1U/6.3V_4

C266 1U/6.3V_4

C294 10U/6.3V_4

C291 22U/6.3V_6

C344 1U/6.3V_4

C318 1U/6.3V_4

C258 10U/6.3V_4

C247 10U/6.3V_4C697 1U/6.3V_4

C702 10U/6.3V_4

C264 10U/6.3V_4

C281 22U/6.3V_6

C691 22U/6.3V_6

C316 22U/6.3V_6

C333 22U/6.3V_6

PLACE THE PU RESISTORS

R455

TP42 TP34

VCCEOPIO_SENSE VSSEOPIO_SENSE

H_CPU_SVIDALRT#

R498 220/F_4

56.2/F_4

C714 *0.1U/16V_4

SVID ALERT

VR_SVID_ALERT# [42]

+VCCSTPLL

PLACE THE PU RESISTORS CLOSE TO VR

R454

PULL UP IS IN THE VR MODULE

*54.9/F_4

VR_SVID_CLK_R

B B

H_CPU_SVIDDAT

R482 *0_4/S

+VCCSTPLL

R483 100/F_4

CLOSE TO CPU PLACE THE PU RESISTORS

R484 *0_4/S

SVID CLK

VR_SVID_CLK [42]

SVID DATA

VR_SVID_DATA [42]

Layout note: need routing together and ALERT need between CLK and DATA.

A A

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

+VCC_CORE +VCCSTG +VCCSTPLL

5

4

3

+VCC_CORE [42]

+VCCSTG [6]

+VCCSTPLL [2,4,6,9,41,42]

C

Date:

2

PROJECT : TWL & JWL ( MB )

Document Number

SKL-04 (POWER-1)

Wednesday, July 29, 2015

Sheet :

1

of

5 51

Rev.Size

3C

5

4

3

2

1

X1B-1218 change from +1.0V to +VCCIO.

C413 10U/6.3V_4

+1.35VSUS

C403 10U/6.3V_4

+VCCPLL_OC

C405 1U/6.3V_4

C399 1U/6.3V_4

C404 1U/6.3V_4

C414 1U/6.3V_4

SKL_ULT

C426 1U/6.3V_4

C356 1U/6.3V_4

AU23 AU28 AU35 AU42 BB23 BB32 BB41 BB47 BB51

AM40

A18 A22

AL23

K20 K21

U25N

CPU POWER 3 OF 4

VDDQ_AU23 VDDQ_AU28 VDDQ_AU35 VDDQ_AU42 VDDQ_BB23 VDDQ_BB32 VDDQ_BB41 VDDQ_BB47 VDDQ_BB51

VDDQC VCCST VCCSTG_A22 VCCPLL_OC VCCPLL_K20

VCCPLL_K21

*SKL_ULT

VDDQ

VDDQVDDQ

1.35V

1.35V1.35V 2A

2A

2A 2A

1.0V

1.0V 1.0V 120mA

120mA

120mA120mA

0.04A

1.0V

1.0V 1.0V 120mA

120mA

120mA120mA

VCCIO

VCCIOVCCIO

0.95V

0.95V0.95V

3.1A

3.1A 3.1A

VCCSA

VCCSA VCCSA

0.55~1.5V

0.55~1.5V0.55~1.5V

4.5A

4.5A 4.5A

VCCIO_SENSE

VSSIO_SENSE

VSSSA_SENSE

VCCSA_SENSE

14 OF 20REV = 1

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

AK28 AK30 AL30 AL42 AM28 AM30 AM42

AK23 AK25 G23 G25 G27 G28 J22 J23 J27 K23 K25 K27 K28 K30

AM23 AM22

H21 H20

Under CPU Close CPU

C368 10U/6.3V_4

C351 1U/6.3V_4

C352 1U/6.3V_4

C369 1U/6.3V_4

C289 1U/6.3V_4

C279 1U/6.3V_4

C225 1U/6.3V_4

VCCIO_VCCSENSE

VCCIO_VSSSENSE

C360 10U/6.3V_4

C350 10U/6.3V_4

+VCCSA

C320 1U/6.3V_4

C321 1U/6.3V_4

C280 1U/6.3V_4

R215 100/F_4

R203 100/F_4

VSSSA_SENSE [42] VCCSA_SENSE [42]

C347 1U/6.3V_4

C346 1U/6.3V_4

Under CPU Close CPU

C313 10U/6.3V_4

C290 1U/6.3V_4

C359 1U/6.3V_4

C297 10U/6.3V_4

Close CPU Close CPU Under CPU

C431 10U/6.3V_6

C432 10U/6.3V_6

C434 10U/6.3V_6

D D

+1.0V_DEEP_SUS

+VCCSTPLL

C216 *1U/6.3V_4

C215 *22U/6.3V_6

+1.0V

C C

20150729A-VCCSTG change source by +VCCSTPLL.

Close CPU A18 Ball

20150518A-Modern Standby.

+VCCIO

X1B-0106 Reserve RES to +VCCSTPLL.

20150319A-Folllow X1B change Power Source from +1.0V to +VCCSTPLL.

R141 0_4

R151 *0_4

R600 *0_4

C429 10U/6.3V_6

C427 10U/6.3V_6

C433 10U/6.3V_6

+VCCSTG

C430 1U/6.3V_4

C415 1U/6.3V_4

C428 1U/6.3V_4

C228 1U/6.3V_4

C421 1U/6.3V_4

+1.35V_VCCPLL_OC

+1.35VSUS

C425 10U/6.3V_4

C424 10U/6.3V_4

C416 10U/6.3V_4

C419 10U/6.3V_4

C420 *10U/6.3V_4

Close CPU Under CPU

+VCCSTPLL → VCCSTG/S3=1.0V +1.0V → VCCSTG/S3=42mV

+1.35VSUS

20150518A-Modern Standby. 20150518B-Mail from Hermann at 5/14 16:27. +VCCPLL_OC change power source from +1.35VSUS to +1.35V_VCCPLL_OC.

R243 *0_6

R601 0_6

C353 1U/6.3V_4

C269 10U/6.3V_4

+VCCIO

+VCCIO+1.35VSUS

C260 10U/6.3V_4

C270 10U/6.3V_4

C314 10U/6.3V_4

C298 10U/6.3V_4

X1B-1218 change from +1.0V to +VCCIO.

C248 10U/6.3V_4

C332 10U/6.3V_4

C230 10U/6.3V_4

C261 10U/6.3V_4

C331 10U/6.3V_4

C249 10U/6.3V_4

06

Under CPU

+VCCSTPLL

R142 0_6

C217 1U/6.3V_4

+VCCPLL

C227 1U/6.3V_4

Under CPU

120mA

+1.0V +1.35VSUS +3VPCU +VCCIO +VCCPLL +VCCPLL_OC +VCCSA +VCCSTG +VCCSTPLL

+1.0V [2,4,16,32,35,41]

+1.35VSUS [3,17,18,36,39,41,47]

+3VPCU [13,30,32,33,34,35,37,38] +VCCIO [2,16,41]

+VCCPLL

+VCCPLL_OC

+VCCSA [42,43]

+VCCSTG [5]

+VCCSTPLL [2,4,5,9,41,42]

Close CPU Close CPU

B B

IO Thrm Protect Top Side for FAN output.

+3VPCU

R153 20K/F_4

THRM_MOINTOR1 [35]

THER_CPU

R152 100K_4 NTC

C233

0.1U/16V_4

1 2

A A

For 75 degree, 1.2v limit, (HW)

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

SKL-05 (POWER-2)

C

Date:

5

4

3

2

SKL-05 (POWER-2)

Wednesday, July 29, 2015

Sheet :

1

of

6 51

Rev.Size

3C

5

4

3

2

1

SKL_ULT

A48 A53 A58 A62

A66 AA63 AA64 AA66 AA67 AA69 AA70 AA71 AC64 AC65 AC66 AC67 AC68 AC69 AC70 AC71

J43 J45 J46 J48 J50 J52 J53 J55 J56 J58

J60 K48 K50 K52 K53 K55 K56 K58 K60

L62

L63

L64

L65

L66

L67

L68

L69

L70

L71

M62

N63 N64 N66 N67 N69

J70

J69

U25M

CPU POWER 2 OF 4

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGT_SENSE VSSGT_SENSE

*SKL_ULT

VCCGT

VCCGT VCCGT

0.55~1.5V

0.55~1.5V0.55~1.5V 31A

31A

31A 31A

BOM

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

VCCGTX_AK42 VCCGTX_AK43 VCCGTX_AK45 VCCGTX_AK46 VCCGTX_AK48 VCCGTX_AK50 VCCGTX_AK52 VCCGTX_AK53 VCCGTX_AK55 VCCGTX_AK56 VCCGTX_AK58 VCCGTX_AK60 VCCGTX_AK70

VCCGTX_AL43 VCCGTX_AL46 VCCGTX_AL50 VCCGTX_AL53 VCCGTX_AL56

VCCGTX_AL60 VCCGTX_AM48 VCCGTX_AM50 VCCGTX_AM52 VCCGTX_AM53 VCCGTX_AM56 VCCGTX_AM58 VCCGTX_AU58 VCCGTX_AU63

VCCGTX_BB57 VCCGTX_BB66

VCCGTX_SENSE VSSGTX_SENSE

13 OF 20REV = 1

+VCCGT

C245 10U/6.3V_4

C732 10U/6.3V_4

C271 10U/6.3V_4

C339 10U/6.3V_4

D D

C263 1U/6.3V_4

C242 1U/6.3V_4

C255 1U/6.3V_4

C C

Under CPU

C244 1U/6.3V_4

C253 1U/6.3V_4

C340 1U/6.3V_4

VCCGT_SENSE[42] VSSGT_SENSE[42]

C224 10U/6.3V_4

C222 10U/6.3V_4

C226 10U/6.3V_4

C243 1U/6.3V_4

C262 1U/6.3V_4

C252 1U/6.3V_4

C737 10U/6.3V_4

C272 10U/6.3V_4

C250 10U/6.3V_4

C251 1U/6.3V_4

C223 1U/6.3V_4

C254 1U/6.3V_4

N70 N71 R63 R64 R65 R66 R67 R68 R69 R70 R71 T62 U65 U68 U71 W63 W64 W65 W66 W67 W68 W69 W70 W71 Y62

AK42 AK43 AK45 AK46 AK48 AK50 AK52 AK53 AK55 AK56 AK58 AK60 AK70 AL43 AL46 AL50 AL53 AL56 AL60 AM48 AM50 AM52 AM53 AM56 AM58 AU58 AU63 BB57 BB66

AK62 AL61

+VCCGT

C325 47U/6.3V_Y8

C310 47U/6.3V_Y8

C285 47U/6.3V_Y8

C349 47U/6.3V_Y8

C739 22U/6.3V_6

C728 22U/6.3V_6

C276 22U/6.3V_6

C303 47U/6.3V_Y8

C309 47U/6.3V_Y8

C342 22U/6.3V_6

C729 22U/6.3V_6

Close CPU

C274 22U/6.3V_6

C273 22U/6.3V_6

C733 22U/6.3V_6

C738 22U/6.3V_6

C734 22U/6.3V_6

C275 22U/6.3V_6

C727 22U/6.3V_6

07

B B

+VCCGT

A A

5

4

+VCCGT [42]

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

SKL-06 (POWER-3)

Custom

Date:

3

2

SKL-06 (POWER-3)

Wednesday, July 29, 2015

Sheet :

1

of

7 51

Rev.Size

3C

5

4

3

2

1

08

A67

A70 AA2 AA4

AA65 AA68 AB15 AB16 AB18 AB21

AB8

AD13 AD16 AD19 AD20 AD21 AD62

AD8

AE64 AE65 AE66 AE67 AE68 AE69

AF1

AF10 AF15 AF17

AF2 AF4

AF63 AG16 AG17 AG18 AG19 AG20 AG21 AG71 AH13

AH6

AH63 AH64 AH67

AJ15 AJ18 AJ20

AJ4

AK11 AK16 AK18 AK21 AK22 AK27 AK63 AK68 AK69

AK8

AL2

AL28 AL32 AL35 AL38

AL4

AL45 AL48 AL52 AL55 AL58 AL64

A5

U25P

SKL_ULT

GND 1 OF 3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

*SKL_ULT

AL65

VSS

AL66

VSS

AM13

VSS

AM21

VSS

AM25

VSS

AM27

VSS

AM43

VSS

AM45

VSS

AM46

VSS

AM55

VSS

AM60

VSS

AM61

VSS

AM68

VSS

AM71

VSS

AM8

VSS

AN20

VSS

AN23

VSS

AN28

VSS

AN30

VSS

AN32

VSS

AN33

VSS

AN35

VSS

AN37

VSS

AN38

VSS

AN40

VSS

AN42

VSS

AN58

VSS

AN63

VSS

AP10

VSS

AP18

VSS

AP20

VSS

AP23

VSS

AP28

VSS

AP32

VSS

AP35

VSS

AP38

VSS

AP42

VSS

AP58

VSS

AP63

VSS

AP68

VSS

AP70

VSS

AR11

VSS

AR15

VSS

AR16

VSS

AR20

VSS

AR23

VSS

AR28

VSS

AR35

VSS

AR42

VSS

AR43

VSS

AR45

VSS

AR46

VSS

AR48

VSS

AR5

VSS

AR50

VSS

AR52

VSS

AR53

VSS

AR55

VSS

AR58

VSS

AR63

VSS

AR8

VSS

AT2

VSS

AT20

VSS

AT23

VSS

AT28

VSS

AT35

VSS

AT4

VSS

AT42

VSS

AT56

VSS

AT58

VSS

16 OF 20REV = 1

U25R

G10 G22 G43 G45 G48

G52 G55 G58

G60 G63 G66 H15 H18 H71

J11 J13 J25 J28 J32 J35 J38 J42

K16 K18 K22 K61 K63 K64 K65 K66 K67 K68 K70 K71

L11 L16 L17

G5

G6

F8

J8

SKL_ULT

GND 3 OF 3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

*SKL_ULT

L18

VSS

L2

VSS

L20

VSS

L4

VSS

L8

VSS

N10

VSS

N13

VSS

N19

VSS

N21

VSS

N6

VSS

N65

VSS

N68

VSS

P17

VSS

P19

VSS

P20

VSS

P21

VSS

R13

VSS

R6

VSS

T15

VSS

T17

VSS

T18

VSS

T2

VSS

T21

VSS

T4

VSS

U10

VSS

U63

VSS

U64

VSS

U66

VSS

U67

VSS

U69

VSS

U70

VSS

V16

VSS

V17

VSS

V18

VSS

W13

VSS

W6

VSS

W9

VSS

Y17

VSS

Y19

VSS

Y20

VSS

Y21

VSS

18 OF 20REV = 1

D D

C C

B B

AT63 AT68 AT71 AU10 AU15 AU20 AU32 AU38

AV1 AV68 AV69 AV70 AV71

AW10 AW12 AW14 AW16 AW18 AW21 AW23 AW26 AW28 AW30 AW32 AW34 AW36 AW38 AW41 AW43 AW45 AW47 AW49 AW51 AW53 AW55 AW57

AW6 AW60 AW62 AW64 AW66

AW8

AY66

B10 B14 B18 B22 B30 B34 B39 B44 B48 B53 B58 B62 B66 B71

BA1 BA10 BA14 BA18

BA2 BA23 BA28 BA32 BA36

F68

BA45

U25Q

SKL_ULT

GND 2 OF 3

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

*SKL_ULT

BOM

17 OF 20REV = 1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

BA49 BA53 BA57 BA6 BA62 BA66 BA71 BB18 BB26 BB30 BB34 BB38 BB43 BB55 BB6 BB60 BB64 BB67 BB70 C1 C25 C5 D10 D11 D14 D18 D22 D25 D26 D30 D34 D39 D44 D45 D47 D48 D53 D58 D6 D62 D66 D69 E11 E15 E18 E21 E46 E50 E53 E56 E6 E65 E71 F1 F13 F2 F22 F23 F27 F28 F32 F33 F35 F37 F38 F4 F40 F42 BA41

A A

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

SKL-07 (GND)

Custom

Date:

5

4

3

2

SKL-07 (GND)

Wednesday, July 29, 2015

Sheet :

1

of

8 51

Rev.Size

3C

5

4

3

2

1

09

U25S

CFG0-19 need Reserve TP

D D

+1.0V_DEEP_SUS

C C

B B

CFG0[16] CFG1[16] CFG2[16] CFG3[16] CFG4[16] CFG5[16] CFG6[16] CFG7[16] CFG8[16] CFG9[16] CFG10[16] CFG11[16] CFG12[16] CFG13[16] CFG14[16] CFG15[16]

CFG16[16] CFG17[16]

CFG18[16] CFG19[16]

R145 49.9/F_4 R442 *1K_4

CFG3 CFG4

CFG_RCOMP

E68 B67 D65 D67 E70 C68 D68 C67 F71

G69

F70

G68

H70

G71

H69

G70

E63 F63

E66 F66

E60

AY2 AY1

K46 K45

AL25 AL27

C71 B70

F60 A52

BA70 BA68

J71 J68

F65

G65

F61 E61

E8

D1 D3

CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15]

CFG[16] CFG[17]

CFG[18] CFG[19]

CFG_RCOMP ITP_PMODE RSVD_AY2

RSVD_AY1 RSVD_D1

RSVD_D3 RSVD_K46

RSVD_K45 RSVD_AL25

RSVD_AL27 RSVD_C71

RSVD_B70 RSVD_F60 RSVD_A52 RSVD_TP_BA70

RSVD_TP_BA68 RSVD_J71

RSVD_J68 VSS_F65

VSS_G65 RSVD_F61

RSVD_E61

*SKL_ULT

SKL_ULT

RESERVED SIGNALS-1

BOM

RSVD_TP_BB68 RSVD_TP_BB69

RSVD_TP_AK13 RSVD_TP_AK12

RSVD_BB2 RSVD_BA3

TP5 TP6

RSVD_D5 RSVD_D4 RSVD_B2 RSVD_C2

RSVD_B3 RSVD_A3

RSVD_AW1

RSVD_E1 RSVD_E2

RSVD_BA4 RSVD_BB4

RSVD_A4 RSVD_C4

TP4

RSVD_A69

RSVD_B69 RSVD_AY3 RSVD_D71

RSVD_C70 RSVD_C54

RSVD_D54

TP1 TP2

VSS_AY71

ZVM#

RSVD_TP_AW71 RSVD_TP_AW70

MSM#

PROC_SELECT#

19 OF 20REV = 1

BB68 BB69

AK13 AK12

BB2 BA3

AU5 AT5

D5 D4 B2 C2

B3 A3

AW1 E1

E2 BA4

BB4 A4

C4 BB5 A69

B69 AY3

R265 *0_4/S

D71 C70

C54 D54

AY4 BB3

AY71

R256 *0_4/S

AR56 AW71

AW70 AP56

C64

R456 *100K_4

0105 R384 unmount

1226 Add R538, C677 reserved

+1.8V_DEEP_SUS

R160 *0_4

+VCCSTPLL

C234 *1U/6.3V_4

Close to CPU within 100mil

AW69 AW68

AU56

AW48

U12 U11 H11

C7

*SKL_ULT

SKL_ULT

U25T

RSVD_AW69 RSVD_AW68 RSVD_AU56 RSVD_AW48 RSVD_C7 RSVD_U12 RSVD_U11 RSVD_H11

SPARE

RSVD_F6

RSVD_E3 RSVD_C11 RSVD_B11 RSVD_A11 RSVD_D12 RSVD_C12 RSVD_F52

20 OF 20REV = 1

F6 E3 C11 B11 A11 D12 C12 F52

Processor Strapping

CFG3 (Physcial Debug Enable)

Disable: Enable: Set DFX Enable in DFX interface MSR

The CFG signals have a default value of '1' if not terminated on the board.

1 0

CFG3

Circuit

R494 *1K_4

DFX Privacy

CFG4 (DP Presence Strap)

A A

+1.0V_DEEP_SUS +1.8V_DEEP_SUS +VCCSTPLL

5

Disable; No physical DP attached to eDP

+1.0V_DEEP_SUS [13,15,16,40,41] +1.8V_DEEP_SUS [15,40]

+VCCSTPLL [2,4,5,6,41,42]

4

Enable; An ext DP device is connected to eDP

3

CFG4

R512 1K_4

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

SKL-08 (RSV)

Custom

Date:

2

SKL-08 (RSV)

Wednesday, July 29, 2015

Sheet :

1

of

9 51

Rev.Size

3C

5

4

3

2

1

10

D D

+3VSPI

+3VS5

R537 *0_4/S R536 *0_4

C736 0.1U/16V_4

R538 1K_4

+3VSPI

HOLD#

TP51/TP38/TP44/TP43/TP50/TP18 need place to TOP

PCH_SPI1_SI_R[35] PCH_SPI_CS0#_R[35] PCH_SPI1_CLK_R[35] PCH_SPI1_SO_R[35]

U26

8

VDD

7

HOLD#

4

VSS

W25Q128FVSIQ

AKE3DZN0N01

PCH SPI ROM(CLG)

8

VDD

7

HOLD#

4

VSS

*A25LQ32AM-F/Q

DFHS08FS023

91960-0084L-8P-SOCKET

CE# SCK

WP#

CE# SCK

WP#

SO

U27

SO

SI

1

PCH_SPI_CS0#_R

6

PCH_SPI1_CLK_R

5

PCH_SPI1_SI_R

2

PCH_SPI1_SO_R

3

1

PCH_SPI_CS0#_R

6

PCH_SPI1_CLK_R

5

PCH_SPI1_SI_R

2

PCH_SPI1_SO_R

3

BIOS_WP#

TP51 TP38 TP44 TP43

C735 22P/50V_4

1224 Change R427 R397 to 1K

BIOS_WP# HOLD#

TP50 TP18

16MB SPI ROM Socket U26 & U27 footprint at same location for co-layout.

20150511A-BOM change, stuff ROM SOCKET / no stuff ROM CHIP by DB. Stuff ROM CHIP / no stuff ROM SOCKET by PV.

R551/R539/R541/R552/R553/R535 close to U26 pin.

R551 15/F_4 R539 15/F_4 R541 15/F_4 R552 15/F_4

+3VSPI

PCH_SPI1_CLK

TP17

TP106 TP105 TP97

PCH_SPI1_SO PCH_SPI1_SI PCH_SPI_IO2 PCH_SPI_IO3 PCH_SPI_CS0#

SPI1_CLK SIO_EXT_SMI# PCI_SERR# SPI1_IO2 SPI1_IO3 SPI1_CS#

R554 1K_4

R553 15/F_4 R535 15/F_4

C748 1U/10V_4

SIO_EXT_SMI#[35] PCI_SERR#[35]

EC_RCIN#[35] SERIRQ[33,35]

AV2

AW3

AV3

AW2

AU4 AU3 AU2 AU1

AW13

AY11

M2 M3

J4 V1 V2

M1

G3 G2 G1

*SKL_ULT

U25E

SPI - FLASH

SPI0_CLK SPI0_MISO SPI0_MOSI SPI0_IO2 SPI0_IO3 SPI0_CS0# SPI0_CS1# SPI0_CS2#

SPI - TOUCH

GPP_D1/SPI1_CLK GPP_D2/SPI1_MISO GPP_D3/SPI1_MOSI GPP_D21/SPI1_IO2 GPP_D22/SPI1_IO3 GPP_D0/SPI1_CS#

C LINK

CL_CLK CL_DATA CL_RST#

GPP_A0/RCIN# GPP_A6/SERIRQ

SKL_ULT

+3V_DEEP_SUS

R174 1K_4

R164 499/F_4

R161 2.2K_4

R165 2.2K_4

SMBUS, SMLINK

GPP_B23/SML1ALERT#/PCHHOT#

LPC

GPP_A14/SUS_STAT#/ESPI_RESET#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

PDC

GPP_C0/SMBCLK

GPP_C1/SMBDATA

GPP_C2/SMBALERT#

GPP_C3/SML0CLK

GPP_C4/SML0DATA

GPP_C5/SML0ALERT#

GPP_C6/SML1CLK

GPP_C7/SML1DATA

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS#

GPP_A10/CLKOUT_LPC1

GPP_A8/CLKRUN#

R7 R8 R10

R9 W2 W1

W3 V3 AM7

AY13 BA13 BB13 AY12 BA12 BA11

AW9 AY9 AW11

5 OF 20REV = 1

SMB_PCH_CLK

SMB_PCH_DAT

SML0ALERT# [11]

SMB_ME0_CLK SMB_ME0_DAT

SML1ALERT# [11]

SMB_ME1_CLK SMB_ME1_DAT GPP_B23

CLK_PCI_EC_R CLK_PCI_LPC_R

LAD0 [30,33,35] LAD1 [30,33,35] LAD2 [30,33,35] LAD3 [30,33,35]

LFRAME# [30,33,35]

R272 22/F_4 R273 22/F_4

R274 *22/F_4

20150319A-Folllow X1B Change to NU.

R534 499/F_4

TP41

+3V_DEEP_SUS

C C

PCH SPI ROM(CLG)

B B

Vender P/N

SOCKET

Size

16MB

16MBGigaDevice ( GGD )

AKE3DZN0N01 - IC FLASH(8P) W25Q128FVSIQ(SOIC)WINBOND ( WND )

AKE3DF00Q00 - IC FLASH(8P)GD25B128CSIGR(SOP)

DFHS08FS023 - CONN SMD HOUSING 8P 2R FS(P1.27,H5.0)

SMBus/Pull-up(CLG)

CPU heat pipe local thermal sensor DDR thermal sensor RTD2136 EC

Touch Pad XDP DDR3-L

R171 1K_4

Q13 2N7002KDW

+3V

EC29 18P/50V_4

EMI(near PCH)

EC30 *18P/50V_4

EMI(near PCH)

6 2

5

2 6

Q14 *2N7002DW

EC27 18P/50V_4

+3V

1

43

1

R275

8.2K/F_4

+3V

R167 4.7K_4

R166 4.7K_4

MBCLK2 [24,35]

MBDATA2 [24,35]

CLK_24M_KBC [35]

CLK_24M_DEBUG [30]

CLK_PCI_TPM [33]

CLKRUN# [33,35]

SMB_RUN_CLK [16,17,18,24,34]

SMB_RUN_DAT [16,17,18,24,34]

+3V

GPIO Pull UP

SERIRQ

+3V +3V_DEEP_SUS +3VS5 +3VSPI

A A

5

+3V [2,4,11,12,13,14,15,16,17,18,19,21,22,24,25,26,27,28,29,30,31,33,34,35,36,42,44,45,46]

+3V_DEEP_SUS [4,11,12,14,15,16,18]

+3VS5 [4,15,16,27,30,33,35,36,38,40,41,44,47]

+3VSPI

4

SIO_EXT_SMI# EC_RCIN# PCI_SERR#

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

SKL-09 (SPI/LPC/SM)

C

Date:

3

2

SKL-09 (SPI/LPC/SM)

Wednesday, July 29, 2015

R567 10K_4

R511 10K_4 R562 10K_4 R502 10K_4

Sheet :

1

of

10 51

Rev.Size

3C

5

4

3

2

1

11

D D

Functional Strap Definitions

DESIGN NOTE: WEAK PULL UP RESISTOR PRESENT ON THIS NET

ACZ_SPKR[14,27]

ACZ_SPKR

TOP SWAP OVERRIDE

R550 *20K/F_4

HIGH - TOP SWAP ENABLE LOW-DISABLED HIGH: LPC SELECTED FOR SYSTEM FLASH WEAK INTERNAL PD

ACZ_SDOUT[14]

+3V_DEEP_SUS

ACZ_SDOUT

R566 *4.7K_4

No Boot: The signal has a weak internal pull-down. 0 = Enable security measures defined in the Flash Descriptor. 1 = Disable Flash Descriptor Security (override). This strap should only be asserted high using external pull-up in manufacturing/debug environments ONLY. This function is useful when running ITP/XDP.

C C

+3V_DEEP_SUS

X1B-1212 change R95 pull-high from +3V to +3V_DEEP_SUS

R510 1K_4

No Boot:

GPIO33_EC[35]

R568 1K_4

The signal has a weak internal pull-down. 0 = Disable Intel ME Crypto Transport Layer Security

R505 *20K/F_4

(TLS) cipher suite (no confidentiality). 1 = Enable Intel ME Crypto Transport Layer Security (TLS) cipher suite (with confidentiality). Must be pulled up to support Intel AMT with TLS and Intel

GPP_B18[14]SML0ALERT#[10]

SBA (Small Business Advantage) with TLS.

ACZ_SDOUT

+3V

R261 *4.7K_4

No Boot: The signal has a weak internal pull-down.

GPP_B18SML0ALERT#

0 = Disable No Reboot mode. 1 = Enable No Reboot mode

R268 10K_4

(PCH will disable the TCO Timer system reboot feature). This function is useful when running ITP/XDP.

+3V_DEEP_SUS

B B

R532

GSPI1_MOSI[14]

GSPI1_MOSI

No Boot: The signal has a weak internal pull-down.

*10K_4

This field determines the destination of accesses to the

R207 *20K/F_4

BIOS memory range. Also controllable using Boot BIOS Destination bit (Chipset Configuration Registers: Offset 3410h:Bit 10). This strap is used in conjunction with Boot BIOS Destination Selection 0 strap. Bit 10 Boot BIOS Destination 0 SPI

SML1ALERT#[10]

SML1ALERT#

R531 20K/F_4

No Boot: The signal has a weak internal pull-down. 0 = LPC Is selected for EC. 1 = eSPI Is selected for EC.

1 LPC

A A

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

+3V +3V_DEEP_SUS

5

+3V_DEEP_SUS [4,10,12,14,15,16,18]

+3V [2,4,10,12,13,14,15,16,17,18,19,21,22,24,25,26,27,28,29,30,31,33,34,35,36,42,44,45,46]

4

Custom

Date:

3

2

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

SKL-10 (HDA/STRAP)

Wednesday, July 29, 2015

Sheet :

1

of

11 51

Rev.Size

3C

5

4

3

2

1

U25H

DIS only

PEG_RXN1[19] PEG_RXP1[19] PEG_TXN1[19] PEG_TXP1[19]

D D

dGPU

Card Reader

WLAN

HDD

C C

ODD

LAN

SSD

B B

PEG_RXN2[19] PEG_RXP2[19] PEG_TXN2[19] PEG_TXP2[19]

PEG_RXN3[19] PEG_RXP3[19] PEG_TXN3[19] PEG_TXP3[19]

PEG_RXN4[19] PEG_RXP4[19] PEG_TXN4[19] PEG_TXP4[19]

PCIE_RXN5_CARD[29] PCIE_RXP5_CARD[29] PCIE_TXN5_CARD[29] PCIE_TXP5_CARD[29]

PCIE_RXN6_WLAN[30] PCIE_RXP6_WLAN[30] PCIE_TXN6_WLAN[30] PCIE_TXP6_WLAN[30]

SATA_RXN0[33] SATA_RXP0[33] SATA_TXN0[33] SATA_TXP0[33]

SATA_RXN1[33] SATA_RXP1[33] SATA_TXN1[33] SATA_TXP1[33]

PCIE_RXN9_LAN[28] PCIE_RXP9_LAN[28] PCIE_TXN9_LAN[28] PCIE_TXP9_LAN[28]

XDP_PRDY#_CPU[16] XDP_PREQ#_CPU[16]

+3V_DEEP_SUS

SATA_RXN2[31] SATA_RXP2[31] SATA_TXN2[31] SATA_TXP2[31]

C698 0.22U/10V_4 C699 0.22U/10V_4

C711 0.22U/10V_4 C710 0.22U/10V_4

C713 0.22U/10V_4 C712 0.22U/10V_4

C708 0.22U/10V_4 C707 0.22U/10V_4

C701 0.1U/16V_4 C700 0.1U/16V_4

C695 0.1U/16V_4 C696 0.1U/16V_4

C716 0.1U/16V_4 C715 0.1U/16V_4

R248 10K_4

PEG_TXN1_C PEG_TXP1_C

PEG_TXN2_C PEG_TXP2_C

PEG_TXN3_C PEG_TXP3_C

PEG_TXN4_C PEG_TXP4_C

PCIE_TXN5_CARD_C PCIE_TXP5_CARD_C

PCIE_TXN6_WLAN_C PCIE_TXP6_WLAN_C

PCIE_TXN9_LAN_C PCIE_TXP9_LAN_C

R496 100/F_4

PIRQA#

PCIE/USB3/SATA

H13

PCIE1_RXN/USB3_5_RXN

G13

PCIE1_RXP/USB3_5_RXP

B17

PCIE1_TXN/USB3_5_TXN

A17

PCIE1_TXP/USB3_5_TXP

G11

PCIE2_RXN/USB3_6_RXN

F11

PCIE2_RXP/USB3_6_RXP

D16

PCIE2_TXN/USB3_6_TXN

C16

PCIE2_TXP/USB3_6_TXP

H16

PCIE3_RXN

G16

PCIE3_RXP

D17

PCIE3_TXN

C17

PCIE3_TXP

G15

PCIE4_RXN

F15

PCIE4_RXP

B19

PCIE4_TXN

A19

PCIE4_TXP

F16

PCIE5_RXN

E16

PCIE5_RXP

C19

PCIE5_TXN

D19

PCIE5_TXP

G18

PCIE6_RXN

F18

PCIE6_RXP

D20

PCIE6_TXN

C20

PCIE6_TXP

F20

PCIE7_RXN/SATA0_RXN

E20

PCIE7_RXP/SATA0_RXP

B21

PCIE7_TXN/SATA0_TXN

A21

PCIE7_TXP/SATA0_TXP

G21

PCIE8_RXN/SATA1A_RXN

F21

PCIE8_RXP/SATA1A_RXP

D21

PCIE8_TXN/SATA1A_TXN

C21

PCIE8_TXP/SATA1A_TXP

E22

PCIE9_RXN

E23

PCIE9_RXP

B23

PCIE9_TXN

A23

PCIE9_TXP

F25

PCIE10_RXN

E25

PCIE10_RXP

D23

PCIE10_TXN

C23

PCIE10_TXP

F5

PCIE_RCOMPN

E5

PCIE_RCOMPP

D56

PROC_PRDY#

D61

PROC_PREQ#

BB11

GPP_A7/PIRQA#

E28

PCIE11_RXN/SATA1B_RXN

E27

PCIE11_RXP/SATA1B_RXP

D24

PCIE11_TXN/SATA1B_TXN

C24

PCIE11_TXP/SATA1B_TXP

E30

PCIE12_RXN/SATA2_RXN

F30

PCIE12_RXP/SATA2_RXP

A25

PCIE12_TXN/SATA2_TXN

B25

PCIE12_TXP/SATA2_TXP

*SKL_ULT

SKL_ULT

PDC

SSIC / USB3

USB3_1_RXN USB3_1_RXP

USB3_2_RXN/SSIC_1_RXN USB3_2_RXP/SSIC_1_RXP

USB3_2_TXN/SSIC_1_TXN USB3_2_TXP/SSIC_1_TXP

USB3_3_RXN/SSIC_2_RXN USB3_3_RXP/SSIC_2_RXP

USB3_3_TXN/SSIC_2_TXN USB3_3_TXP/SSIC_2_TXP

USB3_4_RXN USB3_4_RXP

USB2

USB2_VBUSSENSE

GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_E4/DEVSLP0 GPP_E5/DEVSLP1 GPP_E6/DEVSLP2

GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2

GPP_E8/SATALED#

USB3_1_TXN USB3_1_TXP

USB3_4_TXN USB3_4_TXP

USB2N_1

USB2P_1

USB2N_2

USB2P_2

USB2N_3

USB2P_3

USB2N_4

USB2P_4

USB2N_5

USB2P_5

USB2N_6

USB2P_6

USB2N_7

USB2P_7

USB2N_8

USB2P_8

USB2N_9

USB2P_9

USB2N_10 USB2P_10

USB2_COMP

USB2_ID

8 OF 20REV = 1

H8 G8 C13 D13

J6 H6 B13 A13

J10 H10 B15 A15

E10 F10 C15 D15

AB9 AB10

AD6 AD7

AH3 AJ3

AD9 AD10

AJ1 AJ2

AF6 AF7

AH1 AH2

AF8 AF9

AG1 AG2

AH7 AH8

AB6

USB2_COMP

AG3 AG4

A9

DGPU_HOLD_RST#

C9

GPU_EVENT#

D9

DGPU_PWR_EN

B9

DGPU_PWROK

J1

GC6_FB_EN

J2

DEVSLP1

J3

OCP_OC#

H2 H3

ODD_PRSNT#_R

G4

SATAGP2

H1

SATA_LED#_R

USB30_RX1USB30_RX1+ USB30_TX1USB30_TX1+

USB30_RX2USB30_RX2+ USB30_TX2USB30_TX2+

USBP1USBP1+

USBP2USBP2+

USBP3USBP3+

USBP5USBP5+

USBP6USBP6+

USBP7USBP7+

USBP8USBP8+

R184 113/F_4

TP96 TP93

R500 *0_4

TP81

R495 *0_4/S

USB30_RX1- [32]

USB30_RX1+ [32]

USB30_TX1- [32]

USB30_TX1+ [32] USB30_RX2- [32]

USB30_RX2+ [32]

USB30_TX2- [32]

USB30_TX2+ [32]

USBP1- [32]

USBP1+ [32]

USBP2- [32]

USBP2+ [32]

USBP3- [25]

USBP3+ [25]

USBP5- [30]

USBP5+ [30]

USBP6- [27]

USBP6+ [27]

USBP7- [31]

USBP7+ [31]

USBP8- [33]

USBP8+ [33]

PLACE 'R123' WITHIN 500 MILS FROM USB2_COMP PIN WITH TRACE IMPEDANCE LESS THAN 0.5 OHMS

DGPU_HOLD_RST# [19]

GPU_EVENT# [22]

DGPU_PWR_EN [22,47]

DGPU_PWROK [21,35,46]

GC6_FB_EN [22]

SATA_LED#

USB3.0 (M/B-Right Front, Charger)

USB3.0 (M/B-Right Rear)

USB3.0 (M/B-Right Front, Charger)

USB3.0 (M/B-Right Rear)

CCD

WLAN

USB2.0 (USB/B-Left Rear)

SSD

Finger Printer

+3V_DEEP_SUS

ZERO_ODD_DP# [33]

SATA_LED# [34]

R478 10K_4

20150319A-Folllow X1B change PU from +3V to +3V_DEEP_SUS.

ACC_LED#

12

+3V

PCI-e Port Mapping Table

PCI-E Port

Port-01

Port-02

Port-03

Port-04

Port-05

Port-06

A A

Port-07

Port-08

Port-09

Port-10

5

Function

dGPU

CardReader

WLAN

HDD

ODD

LAN

Un-used

CLK RQ Port

Port-0

Port-1

Port-2

Port-3

Port-4

Port-5

Function

dGPU

CardReader

WLAN

LAN

Un-used

USB3.0 Port Mapping Table

USB3.0 Function PORT-1 PORT-2 PORT-3 PORT-4

4

+3V +3V_DEEP_SUS

USB3.0 (M/B-Right Front, Charger) USB3.0 (M/B-Right Rear) NC NC

+3V_DEEP_SUS [4,10,11,14,15,16,18]

+3V [2,4,10,11,13,14,15,16,17,18,19,21,22,24,25,26,27,28,29,30,31,33,34,35,36,42,44,45,46]

USB2.0 Port Mapping Table

USB2.0 Function PORT-1 PORT-2 PORT-3 PORT-4 PORT-5 PORT-6 PORT-7 PORT-8 PORT-9 PORT-10

3

USB3.0 (M/B-Right Front, Charger) USB3.0 (M/B-Right Rear) CCD NC WLAN USB2.0 (USB/B-Left Rear) SSD Finger Printer NC NC

GPU_EVENT#

DGPU_PWR_EN DGPU_PWROK

SATA_LED# GC6_FB_EN ODD_PRSNT#_R

DGPU_HOLD_RST#

20150319A-Folllow X1B change PU for NU & stuff PD.

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

SKL-11 (PCIe/USB)

Custom

Date:

2

SKL-11 (PCIe/USB)

Wednesday, July 29, 2015

R444 *10K_4

R437 10K_4 R438 10K_4

R486 10K_4 R503 *10K_4 R501 10K_4

R445 *10K_4 R441 100K_4

Sheet :

1

of

12 51

Rev.Size

3C

5

4

3

2

1

13

RP3 install for XDP

RP15 *0_4P2R_4

XTAL24_IN XTAL24_OUT

RTC_X1

TP126

2 4

+1.0V_DEEP_SUS

CK_XDP_N_R CK_XDP_P_R

D D

20150319A-Folllow X1B Change VGA CLK from Port-4 to Port-0.

VGA

Card Reader

WLAN

LAN

C C

CLK_REQ/Strap Pin(CLG)

+3V

R263 10K_4 R251 10K_4 R249 10K_4 R267 10K_4 R260 10K_4 R250 10K_4

CLK_VGA_N[19] CLK_VGA_P[19] PCIE_CLKREQ_VGA#[19]

CLK_PCIE_CRN[29] CLK_PCIE_CRP[29] PCIE_CLKREQ_CR#[29]

CLK_PCIE_WLANN[30] CLK_PCIE_WLANP[30] PCIE_CLKREQ_WLAN#[30]

CLK_PCIE_LANN[28] CLK_PCIE_LANP[28] PCIE_CLKREQ_LAN#[28]

PCIE_CLKREQ_VGA# PCIE_CLKREQ_WLAN# PCIE_CLKREQ_LAN# PCIE_CLKREQ_CR# PCIE_CLKREQ5#

PCIE_CLKREQ4#

PCIE_CLKREQ_VGA#

PCIE_CLKREQ_CR#

PCIE_CLKREQ_WLAN#

PCIE_CLKREQ_LAN#

PCIE_CLKREQ4#

PCIE_CLKREQ5#

U25J

D42

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

AR10

GPP_B5/SRCCLKREQ0#

B42

CLKOUT_PCIE_N1

A42

CLKOUT_PCIE_P1

AT7

GPP_B6/SRCCLKREQ1#

D41

CLKOUT_PCIE_N2

C41

CLKOUT_PCIE_P2

AT8

GPP_B7/SRCCLKREQ2#

D40

CLKOUT_PCIE_N3

C40

CLKOUT_PCIE_P3

AT10

GPP_B8/SRCCLKREQ3#

B40

CLKOUT_PCIE_N4

A40

CLKOUT_PCIE_P4

AU8

GPP_B9/SRCCLKREQ4#

E40

CLKOUT_PCIE_N5

E38

CLKOUT_PCIE_P5

AU7

GPP_B10/SRCCLKREQ5#

*SKL_ULT

SKL_ULT

CLOCK SIGNALS

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

GPD8/SUSCLK

XTAL24_IN

XTAL24_OUT

XCLK_BIASREF

RTCX1 RTCX2

SRTCRST#

RTCRST#

10 OF 20REV = 1

F43 E43

BA17 E37

E35 E42 AM18

AM20 AN18

AM16

XCLK_BIASREF

RTC_RST#

RTC_X2

SRTC_RST#

1 3

R460

2.7K/F_4

R448 *60.4/F_4

R549 0_4

R548 *10M_4

CK_XDP_N [16] CK_XDP_P [16]

PCH_SUSCLK [31]

20150713A3-PV-R 20150727A1-PV-R change for crystal.

R440 *0_4

TP91

C719 12P/50V_4

1

2

4

3

C718 12P/50V_4

R439 *0_4

C745 *10P/50V_4

23

Y7

*32.768KHZ

4 1

C744 *10P/50V_4

Y6 24MHZ +-30PPM

R480 1M_4

TP90

20150312A-ADD

PCH_XTAL24_IN [32]

20150601A-Change C719 to NU. R440 change from 0Ω to 22Ω for terminal resistor.

20150525A-BOM change to same with DB stage.

20150518A-XTAL24_IN from G-CLK. Screen has flicker when all CPU workload on 100%. Root-cause is PCH_XTAL24_IN too close +VCC_CORE. Vender recommand to add CAP 10pF on C719.

External Crystal and Green Clock

The 24 MHz (50 Ohm ESR) XTAL used for Skylake-U needs to be replaced by 38.4 MHz (30 Ohm ESR) XTAL for Cannonlake-U.

20150319A-Folllow X1B change to 10pF CAP.

CLKGEN_RTC_X1 [32]

RTC Clock 32.768KHz

20150518A-Change RTC 32.768KHz from G-CLK since PV stage. 20150520A-Change C744, C745 to 10pF base on EPSON test result.

+3V_RTC +3V_RTC_0

3.206VPass by Diode = 3.079V

+3V_RTC can't pass by G-CLK

U25I

CSI-2

A36

CSI2_DN0

B36

CSI2_DP0

B B

A A

+1.0V_DEEP_SUS +3V +3V_RTC +3V_RTC_0 +3VPCU

5

C38 D38 C36 D36

A38 B38

C31 D31 C33 D33

A31 B31 A33 B33

A29

B29 C28 D28

A27

B27 C27 D27

CSI2_DN1 CSI2_DP1 CSI2_DN2 CSI2_DP2 CSI2_DN3 CSI2_DP3

CSI2_DN4 CSI2_DP4 CSI2_DN5 CSI2_DP5 CSI2_DN6 CSI2_DP6 CSI2_DN7 CSI2_DP7

CSI2_DN8 CSI2_DP8 CSI2_DN9 CSI2_DP9 CSI2_DN10 CSI2_DP10 CSI2_DN11 CSI2_DP11

*SKL_ULT

SKL_ULT

PDC

+1.0V_DEEP_SUS [9,15,16,40,41]

+3V [2,4,10,11,12,14,15,16,17,18,19,21,22,24,25,26,27,28,29,30,31,33,34,35,36,42,44,45,46]

+3V_RTC [4,15,32]

+3V_RTC_0 [32]

+3VPCU [6,30,32,33,34,35,37,38]

CSI2_CLKN0

CSI2_CLKP0

CSI2_CLKN1

CSI2_CLKP1

CSI2_CLKN2

CSI2_CLKP2

CSI2_CLKN3

CSI2_CLKP3

CSI2_COMP

GPP_D4/FLASHTRIG

EMMC

GPP_F13/EMMC_DATA0 GPP_F14/EMMC_DATA1 GPP_F15/EMMC_DATA2 GPP_F16/EMMC_DATA3 GPP_F17/EMMC_DATA4 GPP_F18/EMMC_DATA5 GPP_F19/EMMC_DATA6 GPP_F20/EMMC_DATA7

GPP_F21/EMMC_RCLK

GPP_F22/EMMC_CLK

GPP_F12/EMMC_CMD

EMMC_RCOMP

9 OF 20REV = 1

C37 D37 C32 D32 C29 D29 B26 A26

E13 B7

AP2 AP1 AP3 AN3 AN1 AN2 AM4 AM1

AM2 AM3 AP4

AT1

GPP_D4

GPP_F13 GPP_F14 GPP_F15 GPP_F16 GPP_F17 GPP_F18 GPP_F19 GPP_F20

EMMC_RCLK EMMC_CLK EMMC_CMD

EMMC_RCOMP

4

R481 100/F_4

TP84

TP124 TP123 TP122 TP121 TP120 TP119 TP115 TP116

TP117 TP118 TP125

R547 200/F_4

R279 20K/F_4

R280 20K/F_4

+3V_RTC +3VPCU +3V_RTC_0

30mils

C521 1U/6.3V_4

D6 BAT54CW-7-F

+3V_RTC_1

RTC Power trace width 20mils.

R291 *0_6

3

C446 1U/6.3V_4

C447 1U/6.3V_4

3

1

Q18 2N7002K

2

R292 *0_6

1223 change J1 to R524 unmount Function for RESET.

R289 10K_4

2

3.135VPass by G-CLK = 2.712V

IC because G-CLK has more ΔV.

R332 1K_4

12

CN9 BAT_CONN

RTC_RST# [16]

EC_RTC_RST [35]

RTC Circuitry(RTC)

EC_RTC_RST: Watch Dog for system can't boot and need remove RTC battery & clear CMOS.

C

Date:

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

SKL-12 (CLK/eMMC)

Wednesday, July 29, 2015

Sheet :

1

of

13 51

Rev.Size

3C

5

4

3

2

1

Skylake (GPIO)

U25F

AN8

GPP_B15/GSPI0_CS#

AP7

GPP_B16/GSPI0_CLK

AP8

GPP_B17/GSPI0_MISO

AR7

GPP_B18/GSPI0_MOSI

AM5

GPP_B19/GSPI1_CS#

AN7

GPP_B20/GSPI1_CLK

AP5

GPP_B21/GSPI1_MISO

AN5

GPP_B22/GSPI1_MOSI

AB1

GPP_C8/UART0_RXD

AB2

GPP_C9/UART0_TXD

W4

GPP_C10/UART0_RTS#

AB3

GPP_C11/UART0_CTS#

AD1

GPP_C20/UART2_RXD

AD2

GPP_C21/UART2_TXD

AD3

GPP_C22/UART2_RTS#

AD4

GPP_C23/UART2_CTS#

U7

GPP_C16/I2C0_SDA

U6

GPP_C17/I2C0_SCL

U8

GPP_C18/I2C1_SDA

U9

GPP_C19/I2C1_SCL

AH9

GPP_F4/I2C2_SDA

AH10

GPP_F5/I2C2_SCL

AH11

GPP_F6/I2C3_SDA

AH12

GPP_F7/I2C3_SCL

AF11

GPP_F8/I2C4_SDA

AF12

GPP_F9/I2C4_SCL

*SKL_ULT

BA22 AY22 BB22 BA21 AY21

AW22

J5

AY20

AW20

AK7 AK6 AK9

AK10

H5 D7

D8 C8

AW5

TP31 TP32 TP33 TP27

TP83 TP89

TP85 TP92

GPP_B15 GPP_B16 GPP_B17 GPP_B18

GPP_B19 GPP_B20 GPP_B21 GSPI1_MOSI

GPP_C8 GPP_C9 GPP_C10 GPP_C11

UART2_RXD UART2_TXD ACCEL_INTA# SIO_EXT_SCI#

I2C1_SDA I2C1_SCL

I2C2_SDA I2C2_SCL

I2C3_SDA I2C3_SCL

I2C4_SDA I2C4_SCL

ACZ_SYNC ACZ_BCLK ACZ_SDOUT ACZ_SDIN0

ACZ_RST#

SSP2_SFRM SSP2_SCLK SSP2_TXD SSP2_RXD

GPP_D19 GPP_D20

GPP_D17 GPP_D18

TP49 TP48

R557 *1K_4

TP56

TP36 TP46 TP39

TP108 TP107

TP109

TP19 TP21

TP28 TP26

TP29 TP35

TP22 TP30

+3V_DEEP_SUS

D D

BT_OFF_PCH

PCH_TEMPALERT#

SIO_EXT_SCI#

UART2_RXD

UART2_TXD

1227 Add R536 and R537 for UART2 function reserved

ACCEL_INTA#

R516 10K_4

R523 10K_4

R544 10K_4

R543 49.9K/F_4

R542 49.9K/F_4

R545 10K_4

20150320A-ACCEL_INTA#, X1B connect with G-sensor.

20150518A-Add UART2_RXD & UART2_TXD for USB debug. 20150720A-Remove UART switch circiut to same with DB.

+3V

GPP_B18[11]

GSPI1_MOSI[11]

ACCEL_INTA# SIO_EXT_SCI#[35]

1223 Add R525

C C

+3V_DEEP_SUS

HDA Bus(CLG)

ACZ_SYNC_AUDIO[27] BIT_CLK_AUDIO[27]

ACZ_SDOUT[11] ACZ_SDOUT_AUDIO[27] ACZ_SDIN0[27]

ACZ_RST#_AUDIO[27]

B B

ACZ_SPKR[11,27]

R556 33_4 R558 33_4

C749 *10P/50V_4

R559 33_4

R555 33_4

ACZ_SPKR

LPSS ISH

U25G

AUDIO

HDA_SYNC/I2S0_SFRM HDA_BLK/I2S0_SCLK HDA_SDO/I2S0_TXD HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_RST#/I2S1_SCLK GPP_D23/I2S_MCLK I2S1_SFRM I2S1_TXD

GPP_F1/I2S2_SFRM GPP_F0/I2S2_SCLK GPP_F2/I2S2_TXD GPP_F3/I2S2_RXD

GPP_D19/DMIC_CLK0 GPP_D20/DMIC_DATA0

GPP_D17/DMIC_CLK1 GPP_D18/DMIC_DATA1

GPP_B14/SPKR

SKL_ULT

GPP_D9 GPP_D10 GPP_D11 GPP_D12

GPP_D5/ISH_I2C0_SDA

GPP_D6/ISH_I2C0_SCL

GPP_D7/ISH_I2C1_SDA

GPP_D8/ISH_I2C1_SCL

GPP_F10/I2C5_SDA/ISH_I2C2_SDA

GPP_F11/I2C5_SCL/ISH_I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C4B_SDA

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C4B_SCL

GPP_D16/ISH_UART0_CTS#/SML0BALERT#

GPP_C14/UART1_RTS#/ISH_UART1_RTS# GPP_C15/UART1_CTS#/ISH_UART1_CTS#

SDIO/SDXC

GPP_A17/SD_PWR_EN#/ISH_GP7

GPP_D15/ISH_UART0_RTS#

GPP_C12/UART1_RXD/ISH_UART1_RXD

GPP_C13/UART1_TXD/ISH_UART1_TXD

GPP_A18/ISH_GP0 GPP_A19/ISH_GP1 GPP_A20/ISH_GP2 GPP_A21/ISH_GP3 GPP_A22/ISH_GP4 GPP_A23/ISH_GP5

GPP_A12/BM_BUSY#/ISH_GP6

6 OF 20REV = 1

GPP_F23

AB11 AB13 AB12 W12 W11 W10 W8 W7

BA9 BB9

AB7

AF13

GPP_G0/SD_CMD GPP_G1/SD_DATA0 GPP_G2/SD_DATA1 GPP_G3/SD_DATA2 GPP_G4/SD_DATA3

GPP_G5/SD_CD#

GPP_G6/SD_CLK

GPP_G7/SD_WP

GPP_A16/SD_1P8_SEL

SD_RCOMP

P2 P3 P4 P1

M4 N3

N1 N2

AD11 AD12

U1 U2 U3 U4

AC1 AC2 AC3 AB4

AY8 BA8 BB7 BA7 AY7 AW7 AP13

BOARD_ID0 BOARD_ID1 BOARD_ID2 BOARD_ID3 BOARD_ID4 BOARD_ID5 BOARD_ID6 BOARD_ID7

BOARD_ID8

R180 200/F_4

GPP_D9 3D_CAM_EN_PCH GPP_D11

BT_OFF_PCH

ISH_I2C0_SDA ISH_I2C0_SCL

ISH_I2C1_SDA ISH_I2C1_SCL

ISH_I2C2_SDA ISH_I2C2_SCL

PCH_TEMPALERT# SML0BDATA SML0BCLK SML0BALERT#

UART1_RXD UART1_TXD UART1_RTS UART1_CTS

GPP_A18 GPP_A19 GPP_A20 GPP_A21 GPP_A22 GPP_A23 GPP_A12

TP128

0114 Del TP57, Add R547 with 0ohm

TP100

unmount for 3D camera

TP99 TP94

TP14 TP15

TP95 TP98

TP24TP110 TP23

TP103 TP104 TP102 TP101

TP113 TP114 TP112 TP111

TP127 TP131 TP135 TP134 TP130 TP53 TP54

R529 *10K_4

R530 10K_4

BT_OFF_PCH [30]

+3V_DEEP_SUS

R525 *10K_4

R526 10K_4

R514 *10K_4

R517 10K_4

R508 *10K_4

R515 10K_4

R509 10K_4

R518 *10K_4

R506 *10K_4

R521 10K_4

R522 *10K_4

R571 *10K_4

R527 *10K_4

R561 10K_4

R528 10K_4

R507 10K_4

14

*SKL_ULT

BOARD_ID0

Model

TWL + UMA

TWL + dGPU + N16S

A A

JWL + UMA

JWL + dGPU + N16S

JWL + dGPU + N16V

TWL : 0 JWL : 1

0

0 0 0 0

0

1 1 1 1 1

BOARD_ID1 BOARD_ID2 BOARD_ID3 BOARD_ID4 BOARD_ID5

GPP_G1 GPP_G2 GPP_G3 GPP_G4 GPP_G5GPP_G0

No Define N16V : 0

N16S : 1

No Define No Define

UMA : 0 dGPU : 1

00000

11

1

0 0 0 0

0000TWL + dGPU + N16V

000

1

00000

BOARD_ID6

GPP_G6

No Define

0

BOARD_ID7

GPP_G7

No Define

0

BOARD_ID8

GPP_G8

No Define

0

20141008A-BIOS request for SVID, N16S-GT need PU GPIO58 ( BOARD_ID2 ).

+3V +3V_DEEP_SUS

5

4

+3V [2,4,10,11,12,13,15,16,17,18,19,21,22,24,25,26,27,28,29,30,31,33,34,35,36,42,44,45,46]

+3V_DEEP_SUS [4,10,11,12,15,16,18]

3

7 OF 20REV = 1

GPP_F23

TP25

20150518A-Add GPP_A16 for USB debug. 20150720A-Remove UART switch circiut to same with DB.

2

Document Number

C

Date:

Document Number

Wednesday, July 29, 2015

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

SKL-13 (GPIO)

Sheet :

1

of

14 51

Rev.Size

3C

5

PCH Internal VRM

C820 and C690 close to cpu less then 100 mils

4

3

0107 Change R129 connection from +VCCPRIM_1.0V to +VCCPRIM_1.0V_T1

2

1

15

C296 1U/6.3V_4

+1.0V_DEEP_SUS

D D

C C

C724 1U/6.3V_4

+3VS5

R513 100K_4

C229 *22U/6.3V_6

+3V_DEEP_SUS

C221 *1U/6.3V_4

+VCCDSW_1.0V

C218 1U/6.3V_4

C317 1U/6.3V_4 C213 47U/6.3V_Y8

C284 1U/6.3V_4

+3VS5

for DS3

U24

5

IN

4

IN

SLP_SUS_ON[35,40,41]

C721 *10P/50V_4

3

ON/OFF

G5243AT11U

OUT

GND

1 2

C725

0.1U/16V_4

C283 1U/6.3V_4

C210 1U/6.3V_4

C337 1U/6.3V_4

C741 1U/6.3V_4

R156 *0_6/S R181 0_6

1223 R185 mount,R184 unmount 0106 Del R184

R266 *0_4/S

C301 1U/6.3V_4

+3V

R206 *0_4/S

C335 1U/6.3V_4

R201 *0_6/S

R188 0_6

R209 *0_6/S

R205 *0_6/S

R127 *0_6/S

R157 *0_6/S

R178 *0_6/S

+V3.3DX_1.5DX_ADO

+VCCPRIM

+VCCMPHYAON_1P0

+VCCAMPHYPLL_1P0

+VCCAPLL_1.0V

+VCCPRIM

+VCCSPI

+VCCSRAM_1.0V

+VCCPRIM_3.3V

+VCCPRIM_1.0V

+VCCAPLLEBB

U25O

AB19

VCCPRIM_1P0

AB20

VCCPRIM_1P0

P18

VCCPRIM_1P0

AF18

VCCPRIM_CORE

AF19

VCCPRIM_CORE

V20

VCCPRIM_CORE

V21

VCCPRIM_CORE

AL1

DCPDSW_1P0

K17

VCCMPHYAON_1P0

L1

VCCMPHYAON_1P0

N15

VCCMPHYGT_1P0_N15

N16

VCCMPHYGT_1P0_N16

N17

VCCMPHYGT_1P0_N17

P15

VCCMPHYGT_1P0_P15

P16

VCCMPHYGT_1P0_P16

K15

VCCAMPHYPLL_1P0

L15

VCCAMPHYPLL_1P0

V15

VCCAPLL_1P0

AB17

VCCPRIM_1P0_AB17

Y18

VCCPRIM_1P0_Y18

AD17

VCCDSW_3P3_AD17

AD18

VCCDSW_3P3_AD18

AJ17

VCCDSW_3P3_AJ17

AJ19

VCCHDA

AJ16

VCCSPI

AF20

VCCSRAM_1P0

AF21

VCCSRAM_1P0

T19

VCCSRAM_1P0

T20

VCCSRAM_1P0

AJ21

VCCPRIM_3P3_AJ21

AK20

VCCPRIM_1P0_AK20

N18

VCCAPLLEBB

*SKL_ULT

SKL_ULT

CPU POWER 4 OF 4

2.899A

2.57A

1.714A

0.03A

0.09A

VCCPGPPA VCCPGPPB VCCPGPPC VCCPGPPD VCCPGPPE

VCCPGPPF

VCCPGPPG

VCCPRIM_3P3_V19

VCCPRIM_1P0_T1

VCCATS_1P8

VCCRTCPRIM_3P3

VCCRTC_AK19 VCCRTC_BB14

DCPRTC VCCCLK1 VCCCLK2 VCCCLK3 VCCCLK4 VCCCLK5 VCCCLK6

GPP_B0/CORE_VID0 GPP_B1/CORE_VID1

15 OF 20REV = 1

AK15 AG15 Y16 Y15 T16 AF16 AD15

V19 T1

+VCCPRIM_1.0V_T1

AA1

+VCCATS_1.8V

AK17

+VCCRTCPRIM_3.3V

AK19 BB14

BB10

DCPRTC

A14

+VCCCLK1

K19

+VCCCLK2

L21

+VCCCLK3

N20

+VCCCLK4

L19

+VCCCLK5

A10

+VCCCLK6

AN11 AN13

+VCCPGPPA +VCCPGPPB +VCCPGPPC +VCCPGPPD +VCCPGPPE +VCCPGPPF +VCCPGPPG

CORE_VID0 CORE_VID1

+3V_DEEP_SUS

R218 *0_6/S R199 *0_6/S R179 *0_6/S R187 *0_6/S R183 *0_6/S

R197 *0_6/S

R524 *0_6/S R533 *0_6/S R222 *0_6/S

C750 0.1U/16V_4 R447 *0_6/S R148 *0_6/S R133 *0_6/S R134 *0_6/S R149 *0_6/S R446 *0_6/S C709 1U/6.3V_4

TP37 TP52

+VCCRTCPRIM_3.3V +VCCATS_1.8V+3V_RTC +VCCPGPPB+VCCPGPPC+VCCPGPPE

C401 1U/6.3V_4

C363 0.1U/16V_4

C380 0.1U/16V_4

C381 1U/6.3V_4

R186 *0_6/S

+1.8V_DEEP_SUS

+3V_RTC

C731 1U/6.3V_4

+1.8V_DEEP_SUS

C282 1U/6.3V_4

+3V_DEEP_SUS

C302 1U/6.3V_4

+1.0V_DEEP_SUS

C268 1U/6.3V_4

C327 1U/6.3V_4

B B

+1.0V_DEEP_SUS +1.8V_DEEP_SUS

+3V

A A

+3V_DEEP_SUS +3V_RTC

+3VS5 +V3.3DX_1.5DX_ADO

+VCCATS_1.8V +VCCDSW_1.0V

+VCCPGPPB +VCCPGPPC

+VCCPGPPE +VCCRTCPRIM_3.3V

5

+1.0V_DEEP_SUS [9,13,16,40,41] +1.8V_DEEP_SUS [9,40]

+3V_DEEP_SUS [4,10,11,12,14,16,18]

+V3.3DX_1.5DX_ADO

+VCCDSW_1.0V

+VCCRTCPRIM_3.3V

+3V [2,4,10,11,12,13,14,16,17,18,19,21,22,24,25,26,27,28,29,30,31,33,34,35,36,42,44,45,46]

+3V_RTC [4,13,32]

+3VS5 [4,10,16,27,30,33,35,36,38,40,41,44,47]

+VCCATS_1.8V

+VCCPGPPB +VCCPGPPC

+VCCPGPPE

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

SKL-14 (PCH POWER)

C

Date:

4

3

2

SKL-14 (PCH POWER)

Wednesday, July 29, 2015

Sheet :

1

of

15 51

Rev.Size

3C

5

4

3

2

1

JTAG_TCK_PCH[2]

D D

C C

XDP_TCK1

CFG0[9]

+3V

R220 1K_4

C383

0.1U/16V_4

R225 *0_4

XDP_TCK0[2] JTAGX_PCH[2]

1218 Change R86 connection from +1.0V to +VCCIO

R230 150/F_4

R229 *10K_4

R452 *0_4

R231 1K_4

XDP_PREQ#_CPU[12] XDP_PRDY#_CPU[12]

CFG1[9] CFG2[9] CFG3[9] CFG4[9]

CFG5[9]

CFG6[9] CFG7[9] ON/OFFBTN_KBC#[16]

CK_XDP_P[13] CK_XDP_N[13]

SMB_RUN_DAT[10,17,18,24,34] SMB_RUN_CLK[10,17,18,24,34]

R224 *0_4

+1.0V

R228 *0_4 R227 *0_4

0116 Change CN2 footprint

R233 1K_4

R232 1K_4

PWR_DEBUG

XDP_DBRESET_N SMB_RUN_DAT_XDP SMB_RUN_CLK_XDP

XDP_TCK0

16

+1.0V_DEEP_SUS+VCCIO

C411 0.1U/16V_4 C412 0.1U/16V_4

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27

525253

53

51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27

TP55

XDP_TCK1 XDP_RST

CN7 *FH26W-51S-0.3SHW(05)

+3V

XDP_BPM0 [2] XDP_BPM1 [2]

CFG17 [9] CFG16 [9]

CFG8 [9]

CFG9 [9] CFG10 [9] CFG11 [9] CFG19 [9] CFG18 [9] CFG12 [9] CFG13 [9] CFG14 [9] CFG15 [9]

EC_PWROK [4,35]

+3V_DEEP_SUS

R235 *1K_4

C384

0.1U/16V_4

R2341K_4

SYS_PWROK [4]

PLTRST# [4,19,26,28,29,30,33,35]

R221 51_4

JTAG_TDO_PCH[2]

R226 *0_4

B B

APS

CN6

A A

*ACES_88511-180N

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

5

+3VS5+3V_DEEP_SUS

R168 *0_4

SUSB# [4,16,35]

SLP_S5# [4]

SUSC# [4,35]

SLP_A# [4]

RTC_RST# [13]

ON/OFFBTN_KBC# [16]

SYS_RESET# [4]

PCH_SLP_S0_N [4,35]

SUSB# [4,16,35]

4

JTAG_TDI_PCH[2]

JTAG_TMS_PCH[2]

+1.0V +1.0V_DEEP_SUS +3V +3V_DEEP_SUS +3VS5 +VCCIO

+1.0V_DEEP_SUS [9,13,15,40,41]

+3V_DEEP_SUS [4,10,11,12,14,15,18]

+1.0V [2,4,6,32,35,41]

+3V [2,4,10,11,12,13,14,15,17,18,19,21,22,24,25,26,27,28,29,30,31,33,34,35,36,42,44,45,46]

+3VS5 [4,10,15,27,30,33,35,36,38,40,41,44,47]

+VCCIO [2,6,41]

3

HWPG[4,35,38,39,40]

C307

0.1U/16V_4

XDP_TDO

XDP_TDI

XDP_TMS

XDP_TRST#

2

U9

14

VCC

2

1A

1

1OE

5

2A

4

2OE

9

3A

10

3OE

12

4A

13

4OE

*SN74CBTLV3126RGYR

Document Number

B

Date:

Wednesday, July 29, 2015

3

1B

6

2B

8

3B

11

4B

15

DPAD

7

GND

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

SKL-15 (XDP & APS)

Sheet :

XDP_TDO_CPU [2]

XDP_TDI_CPU [2]

XDP_TMS_CPU [2]

XDP_TRST#_CPU [2]

of

16 51

1

Rev.Size

3C

5

4

3

2

1

M_A_A[15:0][3]

D D

M_A_BS#0[3] M_A_BS#1[3] M_A_BS#2[3] M_A_CS#0[3] M_A_CS#1[3] M_A_CLKP0[3] M_A_CLKN0[3] M_A_CLKP1[3] M_A_CLKN1[3] M_A_CKE0[3] M_A_CKE1[3] M_A_CAS#[3] M_A_RAS#[3]

R287 10K/F_4 R288 10K/F_4

C C

M_A_WE#[3]

SMB_RUN_CLK[10,16,18,24,34] SMB_RUN_DAT[10,16,18,24,34]

M_A_DIM0_ODT0[3] M_A_DIM0_ODT1[3]

M_A_DQSP[7:0][3]

M_A_DQSN[7:0][3]

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

DIMM0_SA0 DIMM0_SA1 SMB_RUN_CLK SMB_RUN_DAT

M_A_DQSP0 M_A_DQSP1 M_A_DQSP2 M_A_DQSP3 M_A_DQSP4 M_A_DQSP5 M_A_DQSP6 M_A_DQSP7 M_A_DQSN0 M_A_DQSN1 M_A_DQSN2 M_A_DQSN3 M_A_DQSN4 M_A_DQSN5 M_A_DQSN6 M_A_DQSN7

CN23A

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12/BC#

119

A13

80

A14

78

A15

109

BA0

108

BA1

79

BA2

114

S0#

121

S1#

101

CK0

103

CK0#

102

CK1

104

CK1#

73

CKE0

74

CKE1

115

CAS#

110

RAS#

113

WE#

197

SA0

201

SA1

202

SCL

200

SDA

116

ODT0

120

ODT1

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

10

DQS#0

27

DQS#1

45

DQS#2

62

DQS#3

135

DQS#4

152

DQS#5

169

DQS#6

186

DQS#7

DDR3-DIMM1_H=5.15_RVS

ddr-ds1rk-20401-tp5b-204p-smt

DGMK4000425

IC SOCKET DDRIII SO-DIMM(204P,H5.15,RVS)

PC2100 DDR3 SDRAM SO-DIMM

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46

(204P)

DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

EZIW

5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194

M_A_DQ4 M_A_DQ0 M_A_DQ7 M_A_DQ3 M_A_DQ1 M_A_DQ5 M_A_DQ2 M_A_DQ6 M_A_DQ9 M_A_DQ12 M_A_DQ10 M_A_DQ14 M_A_DQ8 M_A_DQ13 M_A_DQ15 M_A_DQ11 M_A_DQ17 M_A_DQ21 M_A_DQ22 M_A_DQ18 M_A_DQ20 M_A_DQ16 M_A_DQ23 M_A_DQ19 M_A_DQ28 M_A_DQ24 M_A_DQ31 M_A_DQ27 M_A_DQ25 M_A_DQ29 M_A_DQ26 M_A_DQ30 M_A_DQ37 M_A_DQ33 M_A_DQ38 M_A_DQ35 M_A_DQ32 M_A_DQ36 M_A_DQ34 M_A_DQ39 M_A_DQ40 M_A_DQ43 M_A_DQ41 M_A_DQ47 M_A_DQ45 M_A_DQ44 M_A_DQ42 M_A_DQ46 M_A_DQ53 M_A_DQ52 M_A_DQ55 M_A_DQ50 M_A_DQ49 M_A_DQ48 M_A_DQ54 M_A_DQ51 M_A_DQ56 M_A_DQ60 M_A_DQ59 M_A_DQ63 M_A_DQ57 M_A_DQ61 M_A_DQ62 M_A_DQ58

M_A_DQ[63:0] [3]

VREF DQ0 M1 Solution

SMDDR_VREF_DQ0_M3[3,17]

2 1

SM_VREF[3,17]

2 1

R320 2/F_6

C481

0.022U/25V_4

R315

24.9/F_4

R377 2/F_6

C593

0.022U/25V_4

R374

24.9/F_4

+1.35VSUS

+3V

R290 10K/F_4

PM_EXTTS#0[18] DDR3_DRAMRST#[3,18]

C532 *0.1U/16V_4

+1.35VSUS

R318

1.8K/F_4 R321 *0_6/S

PV modify to short pad

R317

1.8K/F_4

+1.35VSUS

R337

1.8K/F_4

R367

1.8K/F_4

+SMDDR_VREF_DIMM

+3V

+SMDDR_VREF_DQ0SMDDR_VREF_DQ0_M1 +SMDDR_VREF_DIMM

2.48A

CN23B

75

VDD1

76

VDD2

81

VDD3

82

VDD4

87

VDD5

88

VDD6

93

VDD7

94

VDD8

99

VDD9

100

VDD10

105

VDD11

106

VDD12

111

VDD13

112

VDD14

117

VDD15

118

VDD16

123

VDD17

124

VDD18

199

VDDSPD

77

NC1

122

NC2

125

NCTEST

198

EVENT#

30

RESET#

1

VREF_DQ

126

VREF_CA

2

VSS1

3

VSS2

8

VSS3

9

VSS4

13

VSS5

14

VSS6

19

VSS7

20

VSS8

25

VSS9

26

VSS10

31

VSS11

32

VSS12

37

VSS13

38

VSS14

43

VSS15

DDR3-DIMM1_H=5.15_RVS

ddr-ds1rk-20401-tp5b-204p-smt

DGMK4000425

IC SOCKET DDRIII SO-DIMM(204P,H5.15,RVS)

PC2100 DDR3 SDRAM SO-DIMM

(204P)

VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52

VTT1 VTT2

GND GND

44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196

203 204

205 206

+0.65V_DDR_VTT

17

+0.65V_DDR_VTT +1.35VSUS +3V +SMDDR_VREF_DIMM +SMDDR_VREF_DQ0 SM_VREF SMDDR_VREF_DQ0_M3

B B

+0.65V_DDR_VTT [18,39]

+1.35VSUS [3,6,18,36,39,41,47]

+SMDDR_VREF_DIMM [18]

+SMDDR_VREF_DQ0

SMDDR_VREF_DQ0_M3 [3,17]

+3V [2,4,10,11,12,13,14,15,16,18,19,21,22,24,25,26,27,28,29,30,31,33,34,35,36,42,44,45,46]

SM_VREF [3,17]

Place these CAPS near SO-DIMM-0.

For EMI RESERVE

20150331A-EMI request to stuff for DB.

+1.35VSUS +0.65V_DDR_VTT+1.35VSUS

EC40 120P/50V_4 EC25 120P/50V_4 EC26 120P/50V_4 EC41 *120P/50V_4 EC47 120P/50V_4 EC60 120P/50V_4 EC55 120P/50V_4 EC36 120P/50V_4

A A

5

EC31 120P/50V_4 EC46 120P/50V_4 EC48 0.1U/16V_4 EC45 *0.1U/16V_4 EC52 *0.1U/16V_4 EC38 0.1U/16V_4

EC32 *120P/50V_4 EC33 *120P/50V_4

4

1uF/10uF 4pcs on each side of connector

C512 1U/6.3V_4 C513 1U/6.3V_4 C514 1U/6.3V_4 C515 1U/6.3V_4 C493 1U/6.3V_4 C492 1U/6.3V_4 C494 1U/6.3V_4 C495 1U/6.3V_4

C496 10U/6.3V_6 C499 10U/6.3V_6 C498 10U/6.3V_6 C497 10U/6.3V_6 C517 10U/6.3V_6 C511 10U/6.3V_6 C510 10U/6.3V_6 C509 10U/6.3V_6

3

+SMDDR_VREF_DIMM +3V+1.35VSUS +0.65V_DDR_VTT +SMDDR_VREF_DQ0

C445 1U/6.3V_4 C448 0.1U/16V_4C501 *0.1U/16V_4 C452 1U/6.3V_4 C462 1U/6.3V_4 C449 1U/6.3V_4 C461 1U/6.3V_4

C538 *0.1U/16V_4 C588 *2.2U/6.3V_6

2

C491 *2.2U/6.3V_6

C

Date:

C444 2.2U/6.3V_6

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

DDR3L DIMM-A-RVS(H5.15)

Wednesday, July 29, 2015

Sheet :

1

of

17 51

Rev.Size

3C

5

M_B_A[15:0][3]

D D

M_B_BS#0[3] M_B_BS#1[3] M_B_BS#2[3] M_B_CS#0[3] M_B_CS#1[3] M_B_CLKP0[3] M_B_CLKN0[3] M_B_CLKP1[3] M_B_CLKN1[3] M_B_CKE0[3] M_B_CKE1[3] M_B_CAS#[3] M_B_RAS#[3]

R361 10K/F_4 R362 10K/F_4

+3V

C C

M_B_WE#[3]

SMB_RUN_CLK[10,16,17,24,34] SMB_RUN_DAT[10,16,17,24,34]

M_B_DIM0_ODT0[3] M_B_DIM0_ODT1[3]

M_B_DQSP[7:0][3]

M_B_DQSN[7:0][3]

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

DIMM1_SA0 DIMM1_SA1

M_B_ODT0 M_B_ODT1

M_B_DQSP1 M_B_DQSP0 M_B_DQSP2 M_B_DQSP3 M_B_DQSP4 M_B_DQSP5 M_B_DQSP6 M_B_DQSP7 M_B_DQSN1 M_B_DQSN0 M_B_DQSN2 M_B_DQSN3 M_B_DQSN4 M_B_DQSN5 M_B_DQSN6 M_B_DQSN7

CN27A

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12/BC#

119

A13

80

A14

78

A15

109

BA0

108

BA1

79

BA2

114

S0#

121

S1#

101

CK0

103

CK0#

102

CK1

104

CK1#

73

CKE0

74

CKE1

115

CAS#

110

RAS#

113

WE#

197

SA0

201

SA1

202

SCL

200

SDA

116

ODT0

120

ODT1

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

10

DQS#0

27

DQS#1

45

DQS#2

62

DQS#3

135

DQS#4

152

DQS#5

169

DQS#6

186

DQS#7

DDR3-DIMM0_H=5.2_STD

ddr-ds1sk-20401-std-204p-smt

DGMK4000406

PC2100 DDR3 SDRAM SO-DIMM

4

M_B_DQ[63:0] [3]

5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194

M_B_DQ12 M_B_DQ8 M_B_DQ11 M_B_DQ10 M_B_DQ9 M_B_DQ13 M_B_DQ15 M_B_DQ14 M_B_DQ4 M_B_DQ0 M_B_DQ3 M_B_DQ6 M_B_DQ5 M_B_DQ1 M_B_DQ2 M_B_DQ7 M_B_DQ17 M_B_DQ16 M_B_DQ18 M_B_DQ19 M_B_DQ21 M_B_DQ20 M_B_DQ22 M_B_DQ23 M_B_DQ25 M_B_DQ24 M_B_DQ30 M_B_DQ31 M_B_DQ28 M_B_DQ29 M_B_DQ26 M_B_DQ27 M_B_DQ36 M_B_DQ37 M_B_DQ39 M_B_DQ35 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ38 M_B_DQ44 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ45 M_B_DQ40 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ52 M_B_DQ55 M_B_DQ54 M_B_DQ49 M_B_DQ53 M_B_DQ50 M_B_DQ51 M_B_DQ57 M_B_DQ56 M_B_DQ58 M_B_DQ62 M_B_DQ61 M_B_DQ60 M_B_DQ59 M_B_DQ63

VREF DQ1 M1 Solution

SMDDR_VREF_DQ1_M3[3,18]

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47

(204P)

DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

3

R376 2/F_6

C592

0.022U/25V_4

2 1

R372

24.9/F_4

PM_EXTTS#0[17] DDR3_DRAMRST#[3,17]

+1.35VSUS

R370

1.8K/F_4

SMDDR_VREF_DQ1_M1 +SMDDR_VREF_DQ1

R373

1.8K/F_4

PM_EXTTS#0

C554 *0.1U/16V_4

PV modify to short pad

R342 *0_6/S

+SMDDR_VREF_DIMM

+3V

2

+1.35VSUS

2.48A

CN27B

75

VDD1

76

VDD2

81

VDD3

82

VDD4

87

VDD5

88

VDD6

93

VDD7

94

VDD8

99

VDD9

100

VDD10

105

VDD11

106

VDD12

111

VDD13

112

VDD14

117

VDD15

118

VDD16

123

VDD17

124

VDD18

199

VDDSPD

77

NC1

122

NC2

125

NCTEST

198

EVENT#

30

RESET#

1

VREF_DQ

126

VREF_CA

2

VSS1

3

VSS2

8

VSS3

9

VSS4

13

VSS5

14

VSS6

19

VSS7

20

VSS8

25

VSS9

26

VSS10

31

VSS11

32

VSS12

37

VSS13

38

VSS14

43

VSS15

DDR3-DIMM0_H=5.2_STD

ddr-ds1sk-20401-std-204p-smt

DGMK4000406

PC2100 DDR3 SDRAM SO-DIMM

(204P)

VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52

VTT1 VTT2

HOLE1 HOLE2

PAD1 PAD2

44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196

203 204

205 206

207 208

1

18

+0.65V_DDR_VTT

+0.65V_DDR_VTT +1.35VSUS +3V +3V_DEEP_SUS +SMDDR_VREF_DIMM +SMDDR_VREF_DQ1 SMDDR_VREF_DQ1_M3

B B

+0.65V_DDR_VTT [17,39]

+1.35VSUS [3,6,17,36,39,41,47]

+3V [2,4,10,11,12,13,14,15,16,17,19,21,22,24,25,26,27,28,29,30,31,33,34,35,36,42,44,45,46]

+3V_DEEP_SUS [4,10,11,12,14,15,16]

+SMDDR_VREF_DIMM [17]

+SMDDR_VREF_DQ1

SMDDR_VREF_DQ1_M3 [3,18]

Place these CAPS near SO-DIMM-1.Co-lay for ODT

From Intel MOW, ODT directly connection to CPU

+1.35VSUS +3V_DEEP_SUS

1223 R205,R244 unmount

R310 *47K/F_4

A A

R309 *47K/F_4

2

1 3

Q22 *LTC044

R298 *47K/F_4

DDR_VTT_PG_CTRL

R304 *0_4

DDR_VTT_PG_CTRL_R [39]DDR_VTT_CNTL[3,4]

1uF/10uF 4pcs on each side of connector

C574 1U/6.3V_4

C570 1U/6.3V_4 C568 1U/6.3V_4 C528 1U/6.3V_4 C529 1U/6.3V_4 C530 1U/6.3V_4 C531 1U/6.3V_4 C535 10U/6.3V_6

C534 10U/6.3V_6 C536 10U/6.3V_6

C533 10U/6.3V_6 C567 10U/6.3V_6

C569 10U/6.3V_6 C571 10U/6.3V_6

C573 10U/6.3V_6

C556 1U/6.3V_4

C566 1U/6.3V_4 C580 1U/6.3V_4 C587 10U/6.3V_6

+SMDDR_VREF_DIMM +SMDDR_VREF_DQ1

C561 *0.1U/16V_4 C578 *2.2U/6.3V_6C558 1U/6.3V_4

C526 *0.1U/16V_4 C537 *2.2U/6.3V_6C572 1U/6.3V_4

+3V+1.35VSUS +0.65V_DDR_VTT

C555 0.1U/16V_4 C562 2.2U/6.3V_6

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

DDR3L DIMM-B-STD(H5.2)

C

Date:

5

4

3

2

DDR3L DIMM-B-STD(H5.2)

Wednesday, July 29, 2015

Sheet :

1

of

18 51

Rev.Size

3C

1

2

3

4

5

6

7

8

+3V_AON

BOM Default by N16S-GT for Support GC6 2.0.

+3V

C654

0.1U/16V_4

A A

PLTRST#[4,16,26,28,29,30,33,35] DGPU_HOLD_RST#[12]

2 1

3 5

U21 MC74VHC1G08DFT2G

4

R419 0_4

GPU_PEX_RST_HOLD#[22] DGPU_OVT# [35]VGA_OVT#[22]

GC6 2.0

R420 *0_4

N16S-GT support GC6 function

+3V

C655 0.1U/16V_4 U22

MC74VHC1G08DFT2G

2 1

3 5

4

PEX_IOVDD + PEX_IOVDDQ = 1.042A

+1.05V_GFX

Near GPU

C138 22U/6.3VS_6_T100 C126 *22U/6.3VS_6_T100 C127 10U/6.3VS_6_T47 C139 *10U/6.3VS_6_T47 C164 4.7U/6.3V_6

C120 1U/6.3V_4 C121 *1U/6.3V_4

Under GPU

+1.05V_GFX

C122 22U/6.3VS_6_T100 C137 *22U/6.3VS_6_T100 C135 10U/6.3VS_6_T47 C123 *10U/6.3VS_6_T47 C136 4.7U/6.3V_6

B B

C112 1U/6.3V_4 C116 *1U/6.3V_4

Near GPU

Under GPU

PEX_PLL_HVDD + PEX_SVDD_3V3 = 143mA

+3V_AON

C C

+1.05V_GFX

CX300T30001 Change to 0ohm

D D

1

C109 0.1U/16V_4 C105 4.7U/6.3V_6 C106 4.7U/6.3V_6

VGPU_CORE_SENSE[45]

VSS_GPU_SENSE[45]

R422 *200/F_4

R101 *0_6/S

Near GPU

C155 4.7U/6.3V_6 C140 1U/6.3V_4

Under GPU

C113 0.1U/16V_4

PEX_PLLVDD = 130mA

R424 10K/F_4

R423 2.49K/F_4

Near GPU

PEX_TSTCLK PEX_TSTCLK#

PEX_PLLVDD

TESTMODE

PEX_TERMP

2

AA22 AB23 AC24 AD25 AE26 AE27

AA10 AA12 AA13 AA16 AA18 AA19 AA20 AA21 AB22 AC23 AD24 AE25

AF26 AF27

AA8 AA9

AB8

AF22

AE22

AA14 AA15

AD9

AF25

U19A

PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD PEX_IOVDD

PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ PEX_IOVDDQ

PEX_PLL_HVDD PEX_PLL_HVDD

PEX_SVDD_3V3

F2

VDD_SENSE

F1

GND_SENSE

PEX_TSTCLK_OUT PEX_TSTCLK_OUT

PEX_PLLVDD PEX_PLLVDD

TESTMODE

PEX_TERMP

NC NC

1/14 PCI_EXPRESS

PEX_WAKE

PEX_RST

PEX_CLKREQ

PEX_REFCLK PEX_REFCLK

PEX_TX0 PEX_TX0

PEX_RX0 PEX_RX0

PEX_TX1 PEX_TX1

PEX_RX1 PEX_RX1

PEX_TX2 PEX_TX2

PEX_RX2 PEX_RX2

PEX_TX3 PEX_TX3

PEX_RX3 PEX_RX3

PEX_TX4 PEX_TX4

PEX_RX4 PEX_RX4

PEX_TX5 PEX_TX5

PEX_RX5 PEX_RX5

PEX_TX6 PEX_TX6

PEX_RX6 PEX_RX6

PEX_TX7 PEX_TX7

PEX_RX7 PEX_RX7

PEX_TX8 PEX_TX8

PEX_RX8 PEX_RX8

PEX_TX9 PEX_TX9

PEX_RX9 PEX_RX9

PEX_TX10 PEX_TX10

PEX_RX10 PEX_RX10

PEX_TX11 PEX_TX11

PEX_RX11 PEX_RX11

PEX_TX12 PEX_TX12

PEX_RX12 PEX_RX12

PEX_TX13 PEX_TX13

PEX_RX13 PEX_RX13

PEX_TX14 PEX_TX14

PEX_RX14 PEX_RX14

PEX_TX15 PEX_TX15

PEX_RX15 PEX_RX15

GF119GF117

COMMONbga595-nvidia-n13p-gv2-s-a2

3

N16V-GM not support GC6 function

AB6

AC7

VGA_RST#

AC6

PEX_CLKREQ#

AE8 AD8

AC9 AB9

AG6 AG7

AB10 AC10

AF7 AE7

AD11 AC11

AE9 AF9

AC12 AB12

AG9 AG10

AB13 AC13

AF10 AE10

AD14 AC14

AE12 AF12

AC15 AB15

AG12 AG13

AB16 AC16

AF13 AE13

AD17 AC17

AE15 AF15

AC18 AB18

AG15 AG16

AB19 AC19

AF16 AE16

AD20 AC20

AE18 AF18

AC21 AB21

AG18 AG19

AD23 AE23

AF19 AE19

AF24 AE24

AE21 AF21

AG24 AG25

AG21 AG22

PEG_RXP1_C PEG_RXN1_C

PEG_RXP2_C PEG_RXN2_C

PEG_RXP3_C PEG_RXN3_C

PEG_RXP4_C PEG_RXN4_C

C149 0.22U/10V_4 C150 0.22U/10V_4

C158 0.22U/10V_4 C159 0.22U/10V_4

C147 0.22U/10V_4 C148 0.22U/10V_4

C156 0.22U/10V_4 C157 0.22U/10V_4

NVDD = 32.22 ~ 26.66 A

C72 22U/6.3VS_6_T100 C633 47U/10VS_8_T100

C80 4.7U/6.3V_6 C73 4.7U/6.3V_6 C634 4.7U/6.3V_6 C635 4.7U/6.3V_6 C71 4.7U/6.3V_6

Near GPU

+1.05V_GFX +3V +3V_AON +3V_GFX +VGACORE

4

GC6 2.0

R428 10K/F_4

GC6 2.0

PEGX_RST#

R427 100K/F_4

CLK_VGA_P [13] CLK_VGA_N [13]

PEG_RXP1 [12] PEG_RXN1 [12]

PEG_TXP1 [12]

PEG_TXN1 [12]

PEG_RXP2 [12] PEG_RXN2 [12]

PEG_TXP2 [12]

PEG_TXN2 [12] PEG_RXP3 [12]

PEG_RXN3 [12]

PEG_TXP3 [12]

PEG_TXN3 [12]

PEG_RXP4 [12] PEG_RXN4 [12]

PEG_TXP4 [12]

PEG_TXN4 [12]

Under GPU

C108 0.1U/16V_4 C629 0.1U/16V_4 C107 0.1U/16V_4 C632 0.1U/16V_4 C98 4.7U/6.3V_6 C114 4.7U/6.3V_6 C643 4.7U/6.3V_6 C111 4.7U/6.3V_6 C641 4.7U/6.3V_6 C630 4.7U/6.3V_6 C631 4.7U/6.3V_6 C640 4.7U/6.3V_6 C642 4.7U/6.3V_6 C81 4.7U/6.3V_6 C79 4.7U/6.3V_6

12

+

C99 330U_2.5V_3528

+1.05V_GFX [20,21,47]

+VGACORE [45]

This GPIO monitors the PCIe reset assertion from the system side during GC6 residency.

SYS_PEX_RST_MON# [22]

+3V_AON

R98 10K/F_4

R426 0_4

C660 *0.1U/16V_4

+3V_AON

R87 10K/F_4

2

+VGACORE

U19E

11/14 NVVDD

K10

VDD

K12

VDD

K14

VDD

K16

VDD

K18

VDD

L11

VDD

L13

VDD

L15

VDD

L17

VDD

M10

VDD

M12

VDD

M14

VDD

M16

VDD

M18

VDD

N11

VDD

N13

VDD

N15

VDD

N17

VDD

P10

VDD

P12

VDD

P14

VDD

P16

VDD

P18

VDD

R11

VDD

R13

VDD

R15

VDD

R17

VDD

T10

VDD

T12

VDD

T14

VDD

T16

VDD

T18

VDD

U11

VDD

U13

VDD

U15

VDD

U17

VDD

V10

VDD

V12

VDD

V14

VDD

V16

VDD

V18

VDD

bga595-nvidia-n13p-gv2-s-a2 COMMON

+3V [2,4,10,11,12,13,14,15,16,17,18,21,22,24,25,26,27,28,29,30,31,33,34,35,36,42,44,45,46] +3V_AON [22,32,47] +3V_GFX [21,22,45,47]

5

1

+3V_GFX

1 3

Q7 *2N7002K

3

2

R91

4.7K_4

CLKREQ_C1

Q6 LTC044

2

U19C

14/14 XVDD/VDD33

AD10

NC

AD7

NC

B19

NC

3V3AUX_NC

F11

V5

FERMI_RSVD1_NC

V6

FERMI_RSVD2_NC

CONFIGURABLE POWER CHANNELS * nc on substrat e

G1

XPWR_G1

G2

XPWR_G2

G3

XPWR_G3

G4

XPWR_G4

G5

XPWR_G5

G6

XPWR_G6

G7

XPWR_G7

V1

XPWR_V1

V2

XPWR_V2

W1

XPWR_W1

W2

XPWR_W2

W3

XPWR_W3

W4

XPWR_W4

bga595-nvidia-n13p-gv2-s-a2 COMMON

Q8 LTC044

1 3

VDD33 = 56mA

6

PCIE_CLKREQ_VGA# [13]

G10

VDD33

G12

VDD33

G8

VDD33

G9

VDD33

Power Up Sequence

VDD33 +3.3V_GFX

+VCC_DGFX_CORE

FBVDDQ +1.5V_GFX

PEX_VDD +1.05V_GFX

IFP(CDEF)_IOVDD +1.05V_GFX

Power Down Sequence

C60 0.1U/16V_4

PLACE NEAR BALLS

1 2

C56 1U/10V_6 C58 4.7U/6.3V_6

PLACE NEAR BGA

PLACE NEAR BALLS

C61 0.1U/16V_4 C59 0.1U/16V_4

1 2

C54 1U/10V_6 C53 4.7U/6.3V_6

PLACE NEAR BGA

C

Date:

7

t>0NVVDD

t>0

t>=0

BOM Default by N16S-GT for Support GC6 2.0.

N16S-GT support GC6 function

R36 0_4

R37 *0_4

R44 0_4

+3V_AON

+3V_GFX

N16V-GM not support GC6 function

N16S-GT support GC6 function

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

N16x (PCIe, PWR-1)

Wednesday, July 29, 2015

Sheet :

19 51

8

19

of

Rev.Size

3C

1

2

3

4

5

6

7

8

20140804A-NV recommand ball : F3 keep NC.

20

20140919A-NV recommancd add 10KΩ PD on ball-F3 to avoid GPU entry GC6 1.0 state when floating. Some S3/S4 long run test fail is due bo ball-F3 floating.

U19B

C27 C26

E24

F24 D27 D26

F25

F26

F23 G22 G23 G24

F27 G25 G27 G26 M24 M23

K24

K23 M27 M26 M25

K26

K22

J23

J25

J24

K27

K25

J27

J26

F3

FB_CLAMP

FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31

GF119NC

GF117

FBA_CMD2 FBA_CMD18 FBA_CMD5 FBA_CMD3 FBA_CMD19

FBA_CMD0[23] FBA_CMD2[23]

FBA_CMD3[23] FBA_CMD4[23] FBA_CMD5[23] FBA_CMD6[23] FBA_CMD7[23] FBA_CMD8[23] FBA_CMD9[23] FBA_CMD10[23] FBA_CMD11[23] FBA_CMD12[23] FBA_CMD13[23] FBA_CMD14[23] FBA_CMD15[23] FBA_CMD16[23]

FBA_CMD18[23] FBA_CMD19[23] FBA_CMD20[23] FBA_CMD21[23] FBA_CMD22[23] FBA_CMD23[23] FBA_CMD24[23] FBA_CMD25[23] FBA_CMD26[23] FBA_CMD27[23] FBA_CMD28[23] FBA_CMD29[23] FBA_CMD30[23]

PS_FB_CLAMP

R417 10K_4

TP64

A A

FBA_ODT_L FBA_ODT_H FBA_RST# FBA_CKE_L FBA_CKE_H

B B

R32 10K/F_4 R90 10K/F_4 R75 10K/F_4 R33 10K/F_4 R93 10K/F_4

TP63

TP8

TP65

FBA_CMD1

FBA_CMD17

FBA_CMD31

+1.35V_GFX

R3 *10K/F_4 R4 *10K/F_4

VMA_CLK0[23]

C C

VMA_CLK0#[23] VMA_CLK1[23] VMA_CLK1#[23]

FB_PLLAVDD = 55mA

+1.05V_GFX

L6 UPB100505T-330Y-N

C78 22U/6.3V_Y6 C90 0.1U/16V_4 C62 0.1U/16V_4 C95 0.1U/16V_4

+FB_PLLAVDD

FB_DLLAVDD = 15mA

F22

J22

D24 D25 N22 M22

D18

C18

D17

D16

T24

U24

V24

V25

F16

P22

H22

FBA_DEBUG0 FBA_DEBUG1

FBA_CLK0 FBA_CLK0 FBA_CLK1 FBA_CLK1

FBA_WCK01 FBA_WCK01 FBA_WCK23 FBA_WCK23 FBA_WCK45 FBA_WCK45 FBA_WCK67 FBA_WCK67

FB_PLLAVDD

FB_DLLAVDD

GF119

GF117FB_PLLAVDD

2/14 FBA

FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8

FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63

FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7

FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7

FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7

E18 F18 E16 F17 D20 D21 F20 E21 E15 D15 F15 F13 C13 B13 E13 D13 B15 C16 A13 A15 B18 A18 A19 C19 B24 C23 A25 A24 A21 B21 C20 C21 R22 R24 T22 R23 N25 N26 N23 N24 V23 V22 T23 U22 Y24 AA24 Y22 AA23 AD27 AB25 AD26 AC25 AA27 AA26 W26 Y25 R26 T25 N27 R27 V26 V27 W27 W25

D19 D14 C17 C22 P24 W24 AA25 U25

E19 C15 B16 B22 R25 W23 AB26 T26

F19 C14 A16 A22 P25 W22 AB27 T27

VMA_DQ0 VMA_DQ1 VMA_DQ2 VMA_DQ3 VMA_DQ4 VMA_DQ5 VMA_DQ6 VMA_DQ7

VMA_DQ8 VMA_DQ9 VMA_DQ10 VMA_DQ11 VMA_DQ12 VMA_DQ13 VMA_DQ14 VMA_DQ15

VMA_DQ16 VMA_DQ17 VMA_DQ18 VMA_DQ19 VMA_DQ20 VMA_DQ21 VMA_DQ22 VMA_DQ23

VMA_DQ24 VMA_DQ25 VMA_DQ26 VMA_DQ27 VMA_DQ28 VMA_DQ29 VMA_DQ30 VMA_DQ31

VMA_DQ32 VMA_DQ33 VMA_DQ34 VMA_DQ35 VMA_DQ36 VMA_DQ37 VMA_DQ38 VMA_DQ39

VMA_DQ40 VMA_DQ41 VMA_DQ42 VMA_DQ43 VMA_DQ44 VMA_DQ45 VMA_DQ46 VMA_DQ47

VMA_DQ48 VMA_DQ49 VMA_DQ50 VMA_DQ51 VMA_DQ52 VMA_DQ53 VMA_DQ54 VMA_DQ55

VMA_DQ56 VMA_DQ57 VMA_DQ58 VMA_DQ59 VMA_DQ60 VMA_DQ61 VMA_DQ62 VMA_DQ63

VMA_DM0 VMA_DM1 VMA_DM2 VMA_DM3 VMA_DM4 VMA_DM5 VMA_DM6 VMA_DM7

VMA_WDQS0 VMA_WDQS1 VMA_WDQS2 VMA_WDQS3 VMA_WDQS4 VMA_WDQS5 VMA_WDQS6 VMA_WDQS7

VMA_RDQS0 VMA_RDQS1 VMA_RDQS2 VMA_RDQS3 VMA_RDQS4 VMA_RDQS5 VMA_RDQS6 VMA_RDQS7

VMA_DQ[63:0] [23]

VMA_DM[7:0] [23]

VMA_WDQS[7:0] [23]

VMA_RDQS[7:0] [23]

C96 0.1U/16V_4 C104 0.1U/16V_4

1 2

C74 1U/10V_6

1 2

C94 1U/10V_6 C92 4.7U/6.3V_6 C618 4.7U/6.3V_6 C32 10U/6.3V_6 C628 22U/6.3V_Y6

FBVDDQ + FBVDD = 3.116A

+1.35V_GFX

U19D

12/14 FBVDDQ

B26

FBVDDQ

C25

FBVDDQ

E23

FBVDDQ

E26

FBVDDQ

F14

FBVDDQ

F21

FBVDDQ

G13

FBVDDQ

G14

FBVDDQ

G15

FBVDDQ

G16

FBVDDQ

G18

FBVDDQ

G19

FBVDDQ

G20

FBVDDQ

G21

FBVDDQ

H24

FBVDDQ

H26

FBVDDQ

J21

FBVDDQ

K21

FBVDDQ

L22

FBVDDQ

L24

FBVDDQ

L26

FBVDDQ

M21

FBVDDQ

N21

FBVDDQ

R21

FBVDDQ

T21

FBVDDQ

V21

FBVDDQ

W21

FBVDDQ

bga595-nvidia-n13p-gv2-s-a2 COMMON

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_CALTERM_GND

D22

FB_CAL_PD_VDDQ

C24

FB_CAL_PU_GND

B25

FB_CAL_TERM_GND

+1.35V_GFX

R73 40.2/F_4

R70 42.2/F_4

R69 51.1/F_4

U19F

13/14 GND

A2

GND

AB17

GND

AB20

GND

AB24

GND

AC2

GND

AC22

GND

AC26

GND

AC5

GND

AC8

GND

AD12

GND

AD13

GND

A26

GND

AD15

GND

AD16

GND

AD18

GND

AD19

GND

AD21

GND

AD22

GND

AE11

GND

AE14

GND

AE17

GND

AE20

GND

AB11

GND

AF1

GND

AF11

GND

AF14

GND

AF17

GND

AF20

GND

AF23

GND

AF5

GND

AF8

GND

AG2

GND

AG26

GND

AB14

GND

B1

GND

B11

GND

B14

GND

B17

GND

B20

GND

B23

GND

B27

GND

B5

GND

B8

GND

E11

GND

E14

GND

E17

GND

E2

GND

E20

GND

E22

GND

E25

GND

E5

GND

E8

GND

H2

GND

H23

GND

H25

GND

H5

GND

K11

GND

K13

GND

K15

GND

K17

GND

L10

GND

L12

GND

L14

GND

L16

GND

L18

GND

L2

GND

L23

GND

L25

GND

L5

GND

M11

GND

bga595-nvidia-n13p-gv2-s-a2 COMMON

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

GND GND

M13 M15 M17 N10 N12 N14 N16 N18 P11 P13 P15 P17 P2 P23 P26 P5 R10 R12 R14 R16 R18 T11 T13 T15 T17 U10 U12 U14 U16 U18 U2 U23 U26 U5 V11 V13 V15 V17 Y2 Y23 Y26 Y5

AA7 AB7

COMMON

D23

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

N16x (VRAM,PWR-2)

C

Date:

4

5

6

7

N16x (VRAM,PWR-2)

Wednesday, July 29, 2015

Sheet :

of

20 51

8

Rev.Size

3C

INT

bga595-nvidia-n13p-gv2-s-a2

D D

1

+1.05V_GFX [19,21,47] +1.35V_GFX [21,23,36,46]

2

3

+1.05V_GFX +1.35V_GFX

FB_VREF_PROBE

1

2

3

4

5

6

7

8

0319 : Change I2CA_SCL/SDA from +3V_GFX to GND for nVdia suggest

GF119

DACA_HSYNC

DACA_VSYNC

DACA_GREEN

DACA_BLUE

I2CA_SCL I2CA_SDA

DACA_RED

COMMON

B7 A7

AE3 AE4

AG3 AF4 AF3

I2CA_SCL I2CA_SDA

R20 2.2K_4 R19 2.2K_4

USAGE FB Clamp monitor

Memory VDD VID Panel Backlight PWM PANEL POWER ENABLE PANEL BACKLIGHT ENABLE

-Active low FB Clamp toggle request 3D VISION LEFT/RIGHT signal ACTIVE LOW THERMAL OVER TEMP ACTIVE LOW THERMAL ALERT MEMMORY VREF CONTROL GPU CORE_VDD PWM Control signal AC Power detect or power supply overdraw input

+3V

R85

4.7K_4

Low

R89

4.7K_4

DGPU_POK4

C130 *1000P/50V_4

R92

4.7K_4

DGPU_POK2

C131 *1000P/50V_4

2

1 3

High ON

2

1 3

High ON

DGPU_PGOK-1

Q4 METR3904-G

Q5 METR3904-G

2

C125 1000P/50V_4

+3V_GFX

1 3

R81 *4.7K_4

High

OFF

Q3 LTC044

DGPU_PWROK [12,35,46]

R82 100K/F_4

Discharge

W5 AE2 AF2

XTALOUTBUFF

XTALOUT

COMMON

U19K

3/14 DACA

GF119

DACA_VDD

DACA_VREF

DACA_RSET

bga595-nvidia-n13p-gv2-s-a2

GF117

NC

TSEN_VREF

NC

GF117

NC NC

NC

NC NC

GPIO ASSIGNMENTS

GPIO

0 1

3 4 5 6 7 8

9 10 11 12 13

C10

B10

I/O IN

OUT OUT OUT2LCD_VCC OUT OUT OUT OUT I/O I/O OUT OUT IN

BXTALOUTXTAL_SSIN

FB_CLAMP_MON MEM_VDD_CTL LCD_BL_PWM

LCD_BLEN Reserved FB_CLAMP_TGL_REQ 3D VISION OVERT ALERT MEM VREF_CTL PWR_VID PWR_LEVEL PSI Phase SheddingOUT

+1.05V_GFX

R401 10K/F_4

+1.35V_GFX

U19G

4/14 IFPAB

GF117GF119

GF117

NC

GF117

NC

NC NC

NC

AA6

A A

B B

C C

V7

W7

W6

Y6

T6

M7 N7

P6

U6

T7 R7

GF119

IFPAB_RSET

IFPAB_PLLVDD

IFPA_IOVDD

IFPB_IOVDD

IFPAB

bga595-nvidia-n13p-gv2-s-a2

U19H

5/14 IFPC

GF119

IFPC_RSET

IFPC_PLLVDD IFPC_PLLVDD

IFPC_IOVDD

bga595-nvidia-n13p-gv2-s-a2

U19I

6/14 IFPD

GF119

IFPD_RSET

IFPD_PLLVDD

GF117

IFPD

R6

D D

IFPD_IOVDD

NC

GF119 GF117

GF119

NC NC

NC

NC NC

NC

GF117

IFPA_TXC IFPA_TXC

IFPA_TXD0 IFPA_TXD0

IFPA_TXD1 IFPA_TXD1

IFPA_TXD2 IFPA_TXD2

IFPA_TXD3 IFPA_TXD3

IFPB_TXC IFPB_TXC

IFPB_TXD4 IFPB_TXD4

IFPB_TXD5 IFPB_TXD5

IFPB_TXD6 IFPB_TXD6

IFPB_TXD7 IFPB_TXD7

DVI/HDMI DP

I2CW_SDA I2CW_SCL

TXD0 TXD0

TXD1 TXD1

TXD2 TXD2

I2CX_SDA

NC

I2CX_SCL

NC

NC NC

NC

GPIO14

TXC TXC

COMMON

GF119GF117

TXC TXC

TXD0 TXD0

TXD1 TXD1

TXD2 TXD2

GF119

AC4 AC3

Y3 Y4

AA2 AA3

AA1 AB1

AA5 AA4

AB4 AB5

AB2 AB3

AD2 AD3

AD1 AE1

AD5 AD4

B3

IFPC

IFPC_AUX IFPC_AUX

IFPC_L3 IFPC_L3

IFPC_L2 IFPC_L2

IFPC_L1 IFPC_L1

IFPC_L0 IFPC_L0

GPIO15

COMMON

DPDVI/HDMI

IFPD_AUX IFPD_AUX

IFPD_L3 IFPD_L3

IFPD_L2 IFPD_L2

IFPD_L1 IFPD_L1

IFPD_L0 IFPD_L0

GPIO17

N5 N4

N3 N2

R3 R2

R1 T1

T3 T2

C3

P4 P3

R5 R4

T5 T4

U4 U3

V4 V3

D4

J7

K7

K6

H6

J6

+1.05V_GFX

U19J

7/14 IFPEF

GF119

IFPEF_PLLVDD

IFPEF_RSET

IFPE

GF119

IFPE_IOVDD

IFPF_IOVDD

IFPF

bga595-nvidia-n13p-gv2-s-a2

L4 UPB100505T-330Y-N C70 0.1U/16V_4 C68 22U/6.3V_Y6

L5 HCB1005KF-181T15_4 C75 0.1U/16V_4 C82 0.1U/16V_4 C76 10U/6.3V_6 C77 47U/6.3V_Y8

CLK_27M_XTAL_IN[32]

GF117

NC NC

NC

NC NC

NC

NC NC

NC

NC NC

NC

GF117

NC

NC NC

NC

R394 10K/F_4

R389 *0_4

DVI-DL

I2CY_SDA I2CY_SCL

TXC TXC

TXD0 TXD0

TXD1 TXD1

TXD2 TXD2

HPD_ENC

DVI-DL

TXD3 TXD3

TXD4 TXD4

TXD5 TXD5

NV_PLLVDD

SP_PLLVDD

GF119

DVI-SL/HDMI

I2CY_SDA I2CY_SCL

TXC TXC

TXD0 TXD0

TXD1 TXD1

TXD2 TXD2

HPD_E

GF119

DVI-SL/HDMI

I2CZ_SDA I2CZ_SCL

TXC TXC

TXD0 TXD0

TXD1 TXD1

TXD2 TXD2

HPD_F

DP

IFPE_AUX IFPE_AUX

IFPE_L3 IFPE_L3

IFPE_L2 IFPE_L2

IFPE_L1 IFPE_L1

IFPE_L0 IFPE_L0

GPIO18

DP

IFPF_AUX IFPF_AUX

IFPF_L3 IFPF_L3

IFPF_L2 IFPF_L2

IFPF_L1 IFPF_L1

IFPF_L0 IFPF_L0

GPIO19

COMMON

J3 J2

J1 K1

K3 K2

M3 M2

M1 N1

C2

H4 H3

J5 J4

K5 K4

L4 L3

M5 M4

F7

PLLVDD = 38mA SP_PLLVDD = 17mA VID_PLLVDD = 41mA

U19M

9/14 XTAL_PLL

L6

PLLVDD

M6

SP_PLLVDD

N6

VID_PLLVDD

A10

XTALSSIN

C11

XTALIN

bga595-nvidia-n13p-gv2-s-a2

CLK_27M_XTAL_IN_C CLK_27M_XTAL_OUT

NC

C621 12P/50V_4

GF119

GF117

Y5 27MHZ +-10PPM

4 1

23

C620 12P/50V_4

21

COMMONbga595-nvidia-n13p-gv2-s-a2

1

2

+1.05V_GFX +1.35V_GFX +3V +3V_GFX

3

+1.05V_GFX [19,20,47] +1.35V_GFX [20,23,36,46]

+3V [2,4,10,11,12,13,14,15,16,17,18,19,22,24,25,26,27,28,29,30,31,33,34,35,36,42,44,45,46]

+3V_GFX [19,22,45,47]

4

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

N16x (DISPLAY, PWROK)

C

Date:

5

6

7

N16x (DISPLAY, PWROK)

Wednesday, July 29, 2015

Sheet :

of

21 51

8

Rev.Size

3C

1

2

3

4

5

6

7

8

N16V-GM not support GC6 function

R47 *0_4

BOM Default by N16S-GT

GPU_GPIO0

A A

GPU_GPIO5

GPU_GPIO6

TP7 TP6

TP66 TP69 TP68 TP67

B B

THERMTHERM+

JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO

+3V_AON

JTAG_TRST#

R51

R410

R409

R408

R407 STUFF STUFF

U19N

E12 F12

AE5 AD6 AE6

AF6

AG4

R425 10K/F_4

bga595-nvidia-n13p-gv2-s-a2

8/14 MISC1

THERMDN

THERMDP

JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO JTAG_TRST

GC6 ( O )

STUFF

STUFF STUFF

STUFF

N16V-GMN16S-GT

GC6 ( X )

NO STUFF

GF117

NC NC

GF117

+3V_AON

R16 4.7K_4

R13 4.7K_4

R1 *0_4

Q1 2N7002KDW

4 3

1

GPUT_DATA_R

GPUT_CLK_R

D9

I2CS_SCL

D8

I2CS_SDA

A9

I2CC_SCL I2CC_SDA

GF119

I2CB_SCL I2CB_SDA

GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8

GPIO9 GPIO10 GPIO11 GPIO12 GPIO13

GF119

NC NC

NC

GPIO16 GPIO20 GPIO21

COMMON

DGPU_EDIDCLK

B9

DGPU_EDIDDATA

C9

N12E_SCL

C8

N12E_SDA

C6

GPU_GPIO0

B2

GPU_GPIO1

D6

FB_CLAMP_TGL_REQ#

C7 F9 A3

GPU_GPIO5

A4

GPU_GPIO6

B6 A6

VGA_OVT#

F8

ALERT

C5 E7 D7

PWR_LEVEL

B4

PSI

D5

GPU_GPIO16

E6 C4

R8 *0_4

R393 2.2K_4 R390 2.2K_4

R400 2.2K_4 R397 2.2K_4

R51 0_4

R410 0_4 R408 0_4

R72 10K/F_4

TP1

5

2 6

TP62 TP2

+3V_AON

R60 0_4

From PGOOD of NVVDD (+VGACORE)

DGPU_VC_EN[45,47]

DGPU_PWR_EN[12,47]

GPUT_CLK [35]

+3V_GFX

GPUT_DATA [35]

N16S-GT support GC6 function

20140811A-Remove GC6 V1.0 function net of FB_CLAMP_TGL_REQ#_EC ( connect with EC ).

+3V_AON

R62 10K/F_4

+3V_AON

R406 10K/F_4

+3V_AON

+3V_GFX

R61 10K/F_4

R45 0_4

R54 *0_4

GC6_FB_EN

+3V_AON

R409 10K/F_4

D2 RB500V-40

2 1

R407 10K/F_4

+3V

C51

0.1U/16V_4

2 1

+3V_MAIN_EN: W/ Support GC6 enable by GPU_GPIO5. W/O support GC6 enable by +3V_AON.

+3V_MAIN_EN to enable : +VGACORE, +3V_GFX, +1.05V_GFX

+3V_MAIN_EN [45,47]

GPU_EVENT# [12]

VGA_OVT# [19]

GPU_VID [45]

DGPU_PROCHOT_EC# [35,45]

GPU_PEX_RST_HOLD# [19]

U1

3 5

NL17SZ32DFT2G

+3V

Inform CPU.

PSI [45]

4

R53 *10K/F_4

R52 10K/F_4

GC6 2.0

DGPU_FB_EN [46]

To enable VRAM POWER :

R55 *100K/F_4

+1.35V_GFX

GC6_FB_EN [12]

Inform PCH to enable GC6 2.0.

ROM_SI (Memory strap setting)

* Both for 940M ( N16S-GT ) & 920M ( N16V-GM )

V

V V

V

1001

1011

0011

0101

0010

22

PU 10.0KΩ

PU 20.0KΩ

PD 20.0KΩ

PD 30.1KΩ

PD 15.0KΩ

N13P-GV2 NVDD HW BOOT Voltage = 0.875V

R412 *10K/F_4

R66 *10K/F_4

R64 *10K/F_4

R414 *10K/F_4

R416 49.9K/F_4

VID = 110010

R395 *4.99K/F_4

R398 *4.99K/F_4

R399 *10K/F_4

DEL VID pin for NVD request

U19L

C C

TP5 TP4

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

R65 *10K/F_4

R63 *4.99K/F_4

R411 *45.3K/F_4

BOM Default by N16S-GT

D D

R413 *45.3K/F_4

R415 *10K/F_4

Location

PU PD

+3V_AON

R68 *10K/F_4

R67

40.2K/F_4

N16S-GT N16V-GM GC6 ( O ) GC6 (X)

ROM_SI RVL RVLR399 R403

ROM_SO

ROM_SCLK

STRAP0

STRAP1

STRAP2

STRAP3

STRAP4

R398 R402

R416 R415

R414 R413

R66 R65

R64 R63

R412 R411

1

PD 4.99KΩ

PD 4.99KΩ PU 4.99KΩR395 R396

PU 49.9KΩ

NU

10/14 MISC2

E10

VMON_IN0

F10

VMON_IN1

D1

STRAP0

D2

STRAP1

E4

STRAP2

E3

STRAP3

D3

STRAP4

GF119

C1

STRAP5_NC

F6

MULTISTRAP_REF0_GND

F4

MULTISTRAP_REF1_GND

F5

MULTISTRAP_REF2_GND

bga595-nvidia-n13p-gv2-s-a2 COMMON

GF119

GF117

NC

GF117

NC

20141106A-NV suggestion to reserve a pull up resistor to +3V_AON on ball F6 that just follow design guide recommend.

PU 4.99KΩ

PU 45.3KΩ

PD 45.3KΩ

PU 10KΩ

PD 4.99KΩ

PD 45.3KΩ

2

+3V +3V_AON +3V_GFX

D12

ROM_CS

ROM_SI

ROM_SO

ROM_SCLK

BUFRST

PGOOD

CEC

+3V [2,4,10,11,12,13,14,15,16,17,18,19,21,24,25,26,27,28,29,30,31,33,34,35,36,42,44,45,46] +3V_AON [19,32,47] +3V_GFX [19,21,45,47]

B12 A12 C12

D11 D10

E9

3

ROM_CS ROM_SI

ROM_SO ROM_SCLK

NV_PWG

R71 *0_4/S

TP3

R31 *10K/F_4

GC6 2.0 Follow JW5.

SYS_PEX_RST_MON# [19]

R396 4.99K/F_4

R402 4.99K/F_4

R403 30K/F_4

4

ROM_SI (Memory strap setting) BOM Default by 30.1KΩ PD for Samsung K4W4G1646D-BC1A for N16S-GT.

N16S-GT

Quanta P/N VRAM Part Description Value Resistor

0*3

AKD5PGWTW05 Hynix H5TC4G63AFR-11C

AKD5PGWT500 Samsung K4W4G1646D-BC1A

AKD5PZDTW00 Hynix H5TC4G63CFR-N0C

AKD5MZDTW04 Hynix H5TC2G63FFR-11C

AKD5MGST511 PU 20.0KΩ (R399)

K4W2G1646Q-BC1ASamsung

0011

0*5 0101

0*2 0010

0*9 1001

0*B 1011

PD 20.0KΩ (R403)

PD 30.1KΩ (R403)

PD 15.0Ω (R403)

PU 10.0KΩ (R399)

N16V-GM

VRAM Part Description Value ResistorQuanta P/N

AKD5PGWTW05 Hynix H5TC4G63AFR-11C

AKD5PGWT500 Samsung K4W4G1646D-BC1A

AKD5MZDTW04 Hynix H5TC2G63FFR-11C

AKD5MGST511 K4W2G1646Q-BC1A

AKD5PZDTW00 Hynix H5TC4G63CFR-N0C

5

0*E 1110

0*5 0101

0*B 1011

0*7 0111

0*0 0000

PU 34.8KΩ (R399)

PD 30.1KΩ (R403)

PU 20.0KΩ (R399)

PD 45.3KΩ (R403)Samsung

PD 4.99KΩ (R403)

6

V

V V

V

C

Date:

Wednesday, July 29, 2015

7

1011

PU 20.0KΩ

0111

PD 45.3KΩ

1110

PU 34.8KΩ

0101

PD 30.1KΩ

0000

PD 4.99KΩ

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

N16x (GPIO/STRAPS)

Sheet :

of

22 51

8

Rev.Size

3C

5

4

3

2

1

CHANNEL A: 256MB/512MB DDR3L

VMA_DQ[63..0][20]

VMA_DM[7..0][20]

D D

R18

1.33K/F_4

C43 0.1U/16V_4

R35 1.33K/F_4

+1.35V_GFX +1.35V_GFX+1.35V_GFX +1.35V_GFX

R404

1.33K/F_4

C619 0.1U/16V_4

R405 1.33K/F_4

VMA_WDQS[7..0][20]

VMA_RDQS[7..0][20]

R96

1.33K/F_4

R95 1.33K/F_4

C132 0.1U/16V_4

R86

1.33K/F_4

R88 1.33K/F_4

C129 0.1U/16V_4

23

TOP REAR BOT REAR TOP FRONT BOT FRONT

U3

VREFC_VMA1 VREFD_VMA1

FBA_CMD9[20] FBA_CMD11[20] FBA_CMD8[20] FBA_CMD25[20] FBA_CMD10[20] FBA_CMD24[20] FBA_CMD22[20] FBA_CMD7[20] FBA_CMD21[20] FBA_CMD6[20] FBA_CMD29[20]

C C

VMA_CLK0[20] VMA_CLK0#[20]

FBA_CMD3[20]

B B

FBA_CMD23[20] FBA_CMD28[20] FBA_CMD20[20] FBA_CMD4[20] FBA_CMD14[20]

FBA_CMD12[20] FBA_CMD27[20] FBA_CMD26[20]

R34 160/F_4

FBA_CMD2[20] FBA_CMD0[20]

FBA_CMD30[20] FBA_CMD15[20] FBA_CMD13[20]

FBA_CMD5[20]

Should be 240 Ohms +-1%

VMA_WDQS1 VMA_RDQS1

VMA_DM1 VMA_DM0

VMA_WDQS0 VMA_RDQS0

VMA_ZQ1

R76 243/F_4

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

G3

DQSL

E7

DML

D3

DMU

C7

DQSU

B7

DQSU

T2

RESET

L8

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

96-BALL SDRAM DDR3

VRAM _DDR3_SAMSUNG_256MX16

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9

VDDQ#A1

VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9

VSS#A9 VSS#B3 VSS#E1

VSS#G8

VSS#J2

VSS#J8 VSS#M1 VSS#M9

VSS#P1

VSS#P9

VSS#T1

VSS#T9

VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8

VSSQ#F9 VSSQ#G1 VSSQ#G9

E3

VMA_DQ11

F7

VMA_DQ9

F2

VMA_DQ14

F8

VMA_DQ8

H3

VMA_DQ12

H8

VMA_DQ10

G2

VMA_DQ15

H7

VMA_DQ13

D7

VMA_DQ5 VMA_DQ16

C3

VMA_DQ1

C8

VMA_DQ6

C2

VMA_DQ2

A7

VMA_DQ4

A2

VMA_DQ3

B8

VMA_DQ7

A3

VMA_DQ0

+1.35V_GFX +1.35V_GFX +1.35V_GFX

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

Should be 240 Ohms +-1%

VREFC_VMA1 VREFD_VMA1

FBA_CMD9 FBA_CMD11 FBA_CMD8 FBA_CMD25 FBA_CMD10 FBA_CMD24 FBA_CMD22 FBA_CMD7 FBA_CMD21 FBA_CMD6 FBA_CMD29 FBA_CMD23 FBA_CMD28 FBA_CMD20 FBA_CMD4 FBA_CMD14

FBA_CMD12 FBA_CMD27 FBA_CMD26

VMA_CLK0 VMA_CLK0# FBA_CMD3

FBA_CMD2 FBA_CMD0

FBA_CMD30 FBA_CMD15 FBA_CMD13

VMA_WDQS3 VMA_RDQS3

VMA_DM3 VMA_DM2

VMA_WDQS2 VMA_RDQS2

FBA_CMD5

VMA_ZQ2 VMA_ZQ3

R30 243/F_4

U18

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

G3

DQSL

E7

DML

D3

DMU

C7

DQSU

B7

DQSU

T2

RESET

L8

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

96-BALL SDRAM DDR3

VRAM _DDR3_SAMSUNG_256MX16

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD#B2 VDD#D9 VDD#G7

VDD#K2

VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9

VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9 VDDQ#F1 VDDQ#H2 VDDQ#H9

VSS#A9

VSS#B3

VSS#E1

VSS#G8

VSS#J2

VSS#J8 VSS#M1 VSS#M9 VSS#P1 VSS#P9

VSS#T1

VSS#T9

VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8

VSSQ#F9 VSSQ#G1 VSSQ#G9

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

VMA_DQ25 VMA_DQ28 VMA_DQ27 VMA_DQ29 VMA_DQ26 VMA_DQ31 VMA_DQ24 VMA_DQ30

VMA_DQ23 VMA_DQ18 VMA_DQ21 VMA_DQ19 VMA_DQ22 VMA_DQ17 VMA_DQ20

+1.35V_GFX

VREFC_VMA3 VREFD_VMA3

FBA_CMD9 FBA_CMD11 FBA_CMD8 FBA_CMD25 FBA_CMD10 FBA_CMD24 FBA_CMD22 FBA_CMD7 FBA_CMD21 FBA_CMD6 FBA_CMD29 FBA_CMD23 FBA_CMD28 FBA_CMD20 FBA_CMD4 FBA_CMD14

FBA_CMD12 FBA_CMD27 FBA_CMD26

VMA_CLK1[20] VMA_CLK1#[20]

FBA_CMD19[20]

FBA_CMD18[20] FBA_CMD16[20]

Should be 240 Ohms +-1%

R421 160/F_4

FBA_CMD30 FBA_CMD15 FBA_CMD13

VMA_WDQS5 VMA_RDQS5

VMA_DM5 VMA_DM4

VMA_WDQS4 VMA_RDQS4

FBA_CMD5

R94 243/F_4

U4

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

G3

DQSL

E7

DML

D3

DMU

C7

DQSU

B7

DQSU

T2

RESET

L8

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

96-BALL SDRAM DDR3

VRAM _DDR3_SAMSUNG_256MX16

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9

VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9

VDDQ#F1 VDDQ#H2 VDDQ#H9

VSS#A9 VSS#B3 VSS#E1 VSS#G8

VSS#J2

VSS#J8 VSS#M1 VSS#M9

VSS#P1 VSS#P9

VSS#T1

VSS#T9

VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8

VSSQ#F9 VSSQ#G1 VSSQ#G9

E3

VMA_DQ40

F7

VMA_DQ45

F2

VMA_DQ42

F8

VMA_DQ46

H3

VMA_DQ43

H8

VMA_DQ47

G2

VMA_DQ41

H7

VMA_DQ44

D7

VMA_DQ34

C3

VMA_DQ36

C8

VMA_DQ32

C2

VMA_DQ38

A7

VMA_DQ33

A2

VMA_DQ37

B8

VMA_DQ35

A3

VMA_DQ39

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

Should be 240 Ohms +-1%

VREFC_VMA3 VREFD_VMA3

FBA_CMD9 FBA_CMD11 FBA_CMD8 FBA_CMD25 FBA_CMD10 FBA_CMD24 FBA_CMD22 FBA_CMD7 FBA_CMD21 FBA_CMD6 FBA_CMD29 FBA_CMD23 FBA_CMD28 FBA_CMD20 FBA_CMD4 FBA_CMD14

FBA_CMD12 FBA_CMD27 FBA_CMD26

VMA_CLK1 VMA_CLK1# FBA_CMD19

FBA_CMD18 FBA_CMD16

FBA_CMD30 FBA_CMD15 FBA_CMD13

VMA_WDQS7 VMA_RDQS7

VMA_DM7 VMA_DM6

VMA_WDQS6 VMA_RDQS6

FBA_CMD5

VMA_ZQ4

R418 243/F_4

U20

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

A15

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

K1

ODT

L2

CS

J3

RAS

K3

CAS

L3

WE

F3

DQSL

G3

DQSL

E7

DML

D3

DMU

C7

DQSU

B7

DQSU

T2

RESET

L8

ZQ

J1

NC#J1

L1

NC#L1

J9

NC#J9

L9

NC#L9

96-BALL SDRAM DDR3

VRAM _DDR3_SAMSUNG_256MX16

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD#B2 VDD#D9 VDD#G7 VDD#K2 VDD#K8 VDD#N1 VDD#N9 VDD#R1 VDD#R9

VDDQ#A1 VDDQ#A8 VDDQ#C1 VDDQ#C9 VDDQ#D2 VDDQ#E9

VDDQ#F1 VDDQ#H2 VDDQ#H9

VSS#A9 VSS#B3 VSS#E1

VSS#G8

VSS#J2

VSS#J8 VSS#M1 VSS#M9

VSS#P1

VSS#P9

VSS#T1

VSS#T9

VSSQ#B1 VSSQ#B9 VSSQ#D1 VSSQ#D8 VSSQ#E2 VSSQ#E8

VSSQ#F9 VSSQ#G1 VSSQ#G9

E3

VMA_DQ62

F7

VMA_DQ59

F2

VMA_DQ60

F8

VMA_DQ56

H3

VMA_DQ61

H8

VMA_DQ58

G2

VMA_DQ63

H7

VMA_DQ57

D7

VMA_DQ54

C3

VMA_DQ48

C8

VMA_DQ55

C2

VMA_DQ51

A7

VMA_DQ53

A2

VMA_DQ50

B8

VMA_DQ52

A3

VMA_DQ49

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

+1.35V_GFX

C69 1U/6.3V_4

C124 1U/6.3V_4

C626 0.1U/16V_4

C624 0.1U/16V_4

A A

5

4

C615 0.1U/16V_4

C638 0.1U/16V_4

C87 0.1U/16V_4

C88 0.1U/16V_4

C67 0.1U/16V_4

C97 0.1U/16V_4

C659 1U/6.3V_4

C614 1U/6.3V_4

C623 1U/6.3V_4

C47 1U/6.3V_4

C46 1U/6.3V_4

C637 1U/6.3V_4

C639 1U/6.3V_4

C117 1U/6.3V_4

C625 1U/6.3V_4

3

C636 1U/6.3V_4

C650 1U/6.3V_4

+1.35V_GFX

C658 1U/6.3V_4

C617 10U/6.3V_6

C627 10U/6.3V_6

C622 1U/6.3V_4

C91 1U/6.3V_4

C102 10U/6.3V_6

+1.35V_GFX [20,21,36,46]

C616 10U/6.3V_6

C110 10U/6.3V_6

C115 10U/6.3V_6

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

dGPU Memory (DDR3L)

C

Date:

2

dGPU Memory (DDR3L)

Wednesday, July 29, 2015

Sheet :

1

of

23 51

Rev.Size

3C

5

4

3

2

1

TWL/JWL default by eDP circuit.

24

L11: need use CV-4709MN00 for Vendor suggestion

D D

SWR MODE

LDO MODE

Stuff Inductance Stuff Resister

+SWR_LX +1.2V_2136

L11 *4.7UH_1A

R135 *0_6

Rated current 1A.

X5R

Close to Pin15

20mil

C201 *10U/6.3V_Y6

C194 *0.1U/16V_4

Close to Pin43

Close to Pin15

C197 *0.1U/16V_4

C177 *0.1U/16V_4

Close to Pin11

C181 *0.1U/16V_4

C182 *0.1U/16V_4

20mil

L8 *PBY160808T-600Y-N

C183 *10U/6.3V_6

USING 60R 1A

C180 *0.1U/16V_4

For EMI

+3V+3.3V_2136_A

keep 80 Mile Trace

RTD2136S Power Up Sequence

EDDID EEPROM VCC

DP2LVDS VCC

HPD

<=100ms

C C

Reserve for co layout EDP CON, EDP only please stuff

R113 0_4 R114 0_4 R115 0_4 R116 0_4 R118 0_4 R122 0_4

ULT_EDP_HPD[2,25]

Stuff on CPU side.

AUX Channel : 6inch/85Ω

Main Link : 6inch/85Ω

INT_eDP_AUXN[2] INT_eDP_AUXP[2]

INT_eDP_TXP0[2] INT_eDP_TXN0[2]

INT_eDP_TXP1[2] INT_eDP_TXN1[2] TXUOUT0- [25]

MBCLK2[10,35] MBDATA2[10,35]

SMB_RUN_CLK[10,16,17,18,34] SMB_RUN_DAT[10,16,17,18,34]

R146 *0_4 R147 *0_4

Default

R139 *0_4 R140 *0_4

C178 *0.1U/16V_4 C179 *0.1U/16V_4

C187 *0.1U/16V_4 C188 *0.1U/16V_4 C190 *0.1U/16V_4 C192 *0.1U/16V_4

Reserve

B B

20mil/0.5A/<400mil

INT_eDP_AUXN_R [25]

INT_eDP_AUXP_R [25]

INT_eDP_TXP0_R [25] INT_eDP_TXN0_R [25] INT_eDP_TXP1_R [25] INT_eDP_TXN1_R [25]

Noise Filter

R111 *1K/F_4

R108 *100K_4

R110 *100k/F_4

INT_eDP_AUXN_2136 INT_eDP_AUXP_2136

INT_eDP_TXP0_2136 INT_eDP_TXN0_2136 INT_eDP_TXP1_2136 INT_eDP_TXN1_2136

20mil

LDO mode Pin-15 : LDO output Pin-11 & 43 : VDD input Pin-17 : LDO feedback

EDP_HPD_2136

Avoid Floating

SCL1_2136 SDA1_2136

SDAT_2136 SCLK_2136

IC thermal pad connect with GND.

ROM Mode

R109 *4.7K_4 R112 *4.7K_4

EDIDCLK_2136 [25]

EDIDDATA_2136 [25]

1 2 3 4

7 8 9

10

13 14

45 46 47 48

49

+3V

U7

DP_HPD TESTMODE AUX-CH_N AUX-CH_P

LANE0P LANE0N LANE1P LANE1N

CIICSCL1 CIICSDA1

MIICSDA1 MIICSCL1 MIICSDA0 MIICSCL0

NC

17

DP_GND

6

SWR_LX

RTD2136R

DP_REXT

GND

12

16

11

43

15

VCCK

DP_V12

SWR_VCCK

Level Shifter

R128 *12K/F_4

5

DP_V33

PWMOUT19PANEL_VCC20PWMIN

21

R138 *100K/F_4

18

22

SWR_VDD

PIN-18 : 80mil/<200mil

TXO0-

PVCC

TXO0+

TXO1-

TXO1+

TXO2-

TXO2+

TXOC-

TXOC+

TXO3-

TXO3+

TXE0-

TXE0+

TXE1-

TXE1+

TXE2TXE2+ TXEC-

TXEC+

TXE3TXE3+

BL_EN

EC20

*0.1U/25V_4

C209 *22U/6.3V_Y6

+3.3V_2136_D

CLOSE TO Pin22

10uF/X5R

C202 *0.1U/16V_4

Close to Pin18

Close to Pin18Close to Pin5

42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23

44

R126 *100K/F_4

PANEL_VCC : Output 1A / 80mil

EC14 *0.1U/25V_4

20141007A-EMI request.

C204 *0.1U/16V_4

C212 *0.1U/16V_4

L10

USING 60R 2A

*PBY160808T-600Y-N

C220 *10U/6.3V_Y6

TXLOUT0-_2136 [25]

TXLOUT0+_2136 [25]

TXLOUT1-_2136 [25]

TXLOUT1+_2136 [25]

TXLOUT2- [25] TXLOUT2+ [25]

TXLCLKOUT- [25]

TXLCLKOUT+ [25]

TXUOUT0+ [25]

TXUOUT1- [25]

TXUOUT1+ [25]

TXUOUT2- [25]

TXUOUT2+ [25]

TXUCLKOUT- [25]

TXUCLKOUT+ [25]

LVDS_BLON_2136 [25]

PCH_DPST_PWM [2,25]

2136_DISP_ON [25]

2136_DPST_PWM [25]

LVDS (RTD2136~CNN) : 7inch/90~100Ω

PIN-20 PANEL_VCC The switch can support any panel resolution with the maximum current consumption below 1-A, and can endure panel inrush current up to 2-A.

Input & output need PD, avoid on floating status while RD2136 booting.

+1.2V_2136 +3.3V_2136_A +3.3V_2136_D

A A

5

4

3

+3V +SWR_LX

+1.2V_2136

+3.3V_2136_A

+3.3V_2136_D

+3V [2,4,10,11,12,13,14,15,16,17,18,19,21,22,25,26,27,28,29,30,31,33,34,35,36,42,44,45,46]

+SWR_LX

Document Number

C

Date:

2

Document Number

Wednesday, July 29, 2015

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

IC-LVDS RTD2136

Sheet :

1

of

24 51

Rev.Size

3C

1

2

3

4

5

6

7

8

25

RTD2136R PANEL_VCC : Output 1A / 80mil / <2inch Add 4.7uF & 100KΩ close panel connector

R41

+3V

U2

5 4 3

AP2821KTR-G1

C30 *4.7U/6.3V_6

DIGITAL_CLK[27]

DIGITAL_D1[27]

R2 1K/F_4

PN_BLON

D1 RB500V-40

R48 1K/F_4

*100K/F_4

Power Switch Reserve

OUT

IN

GND

IN ON/OFF

INT_eDP_AUXP_R[24]

eDP

LVDS

EDIDCLK_2136[24]

LVDS

EDIDDATA_2136[24]

eDP

INT_eDP_AUXN_R[24]

eDP

INT_eDP_TXN1_R[24]

LVDS

TXLOUT0-_2136[24]

LVDS

TXLOUT0+_2136[24]

eDP

INT_eDP_TXP1_R[24]

eDP

INT_eDP_TXN0_R[24]

LVDS

TXLOUT1-_2136[24]

LVDS

TXLOUT1+_2136[24]

eDP

INT_eDP_TXP0_R[24]

TXLOUT2-[24]

LVDS

TXLOUT2+[24]

TXLCLKOUT-[24]

LVDS

TXLCLKOUT+[24] TXUOUT0-[24]

LVDS

TXUOUT0+[24] TXUOUT1-[24]

LVDS

TXUOUT1+[24] TXUOUT2-[24]

LVDS

TXUOUT2+[24] TXUCLKOUT-[24]

LVDS

TXUCLKOUT+[24]

L1 MCM2012B900GBE

1

2

4 3

C19 *Clamp-Diode

12

C20

12

ESD

L2 FILTER FCM1005KF-121T05

R9 *0_4/S

20150312A-EMI

C23 33P/50V_4

For LVDS Only: stuff Ra,Rb,Rc

Rc

A A

2136_DISP_ON[24]

PCH_DISP_ON[2]

For eDP Only: stuff Rd,Re,Rf

B B

VHPD (eDP panel) : 2.25V ~ 3.6V (LVDS panel) : N/A (W/O this pin define)

C C

PCH_DPST_PWM[2,24]

2136_DPST_PWM[24]

LID Switch

D D

1

EMU_LID[ 35]

LVDS_BLON_2136[24]

PCH_LVDS_BLON[2]

R50 *0_8

R46 0_4

For eDP Only: Stuff Re

For LVDS Only: Stuff Rf

For eDP Only: Stuff Rd

ULT_EDP_HPD[2,24]

For LVDS Only: Stuff Rc

+3V

R22 10_4

R14 *0_4

R49 *0_4/S

R56 *0_4

R57 0_4

LVDS

DISP_ON_L

Rf

eDP

For EDP Only: stuff

For eDP Only: stuff Cap

For LVDS only stuff Resistor

+3VLCD_CON

R42

Re

0_6

eDP eDP

R23

Rf

*0_6

LVDS

R38 0_4

eDP

R21 *0_4

LVDS

R17 *0_6/S

20141212AL1 change from RES 0ohm to EMI FILTER SBY100505T-121Y-N(120,300MA) for EMI request.

+3V

R5 1K_4

+3V

eDP

R58 1K_4

eDP

LVDS_BLON1

LVDS

eDP

LVDS

Rb

Rd

Ra

Re

eDP

R59 100K/F_4

Avoid Floating

2

C64 1U/6.3V_4

BRIGHT

R43 0_6

R24 *0_6

LVDS

Rd

Rc

C18 *0.01U/50V_4

USBP3-[12] USBP3+[12]

C50 *4.7U/6.3V_4

1

L3 PBY160808T-600Y-N

2

*Clamp-Diode

C21 *10P/50V_4

C22 *10P/50V_4

VADJ1

C49

R39

22P/50V_4

100K/F_4

2 1

3

C29

0.01U/50V_4

eDP

LVDS

eDP

LVDS

eDP

LVDS LVDS

R40 *0_8

C35

0.1U/16V_4

2 1

C34 0.1U/16V_4

eDP

+3V

C42 0.1U/16V_4

C25 0.1U/16V_4

R6 *0_4 R7 *0_4

C26 0.1U/16V_4

C37 0.1U/16V_4

R25 *0_4 R26 *0_4

C38 0.1U/16V_4

+VIN

R10 *4.7K_4

LVDS

C33 *10P/50V_4

RF

+3V

C41 *10P/50V_4

RF

C52 *4.7U/25V_8

C40 10U/6.3V_6

+3V

R11 *0_4

LVDS

R27 *4.7K_4

LVDS

R28 *0_4

LVDS

100mA

C36 0.1U/25V_4

C24 0.1U/25V_4

C45 *4.7U/25V_8

C31 0.1U/25V_4

Rb

R391 *0_6

+3V

R29 100K_4

eDP

+VIN_BLIGHT

C17 0.1U/25V_4

C55 0.1U/25V_4

C44 0.01U/50V_4

R12 100K_4

eDP

C48 0.1U/25V_4

+3VLCD_CON

C28 *0.047U/25V_4

C27 *0.047U/25V_4

1 2

C15 *1000P/50V_4

TWL LVDS

+3VLCD_CON

+3V_VEDID

CN1 CONN SMD FFC 40P 1R FR(H2.0, P0.5)

DFFC40FR036

lvds-51519-04001-001-40p-l

40 39

EDIDCLK_R EDIDDATA_R TXLOUT0TXLOUT0+

TXLOUT1TXLOUT1+

TXLOUT2TXLOUT2+

PANEL_ID0

TXLCLKOUTTXLCLKOUT+

PANEL_ID1

TXUOUT0TXUOUT0+

TXUOUT1TXUOUT1+

ULT_EDP_HPD_R

TXUOUT2TXUOUT2+

TXUCLKOUTTXUCLKOUT+

+3V_CAM USBP3-_C USBP3+_C

DIGITAL_CLK_L DIGITAL_D2 VADJ1 BLON_CON

+VIN_BLIGHT

38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

20140811A-Modify base on CY's Y14 pin define.

4

12

R316 100K/F_4

Q28

4 3

1

2N7002KDW

C471 0.1U/16V_4 C466 0.1U/16V_4

C465 0.1U/16V_4 C464 0.1U/16V_4

C476 0.1U/16V_4 C480 0.1U/16V_4

C463 0.1U/16V_4 C457 0.1U/16V_4

R307 470/F_4 R303 470/F_4

R300 470/F_4 R296 470/F_4

R311 470/F_4 R314 470/F_4

DGPU_CL_HDMIP

R295 470/F_4 R286 470/F_4

3

Q24 2N7002K

2

1

+3V

5

2 6

+5V_HDMI_CRT

21

D11 RB500V-40

5V_HSMBDT

R574

2.2K_4

C754 *10P/50V_4

R294 121/F_4

D10 RB500V-40

5V_HSMBCK

R312 121/F_4

HDMI_SCLK HDMI_SDATA

EMI Solution

21

R306 121/F_4

R299 121/F_4

CN21 HDMI CONN

20

SHELL1

21

SHELL2

10 11 12 13 14 15 16 17 18 19

1 2 3 4 5 6 7 8 9

D2+ D2 Shield D2D1+ D1 Shield D1D0+ D0 Shield D0CK+ CK Shield CKCE Remote NC DDC CLK DDC DATA GND +5V HP DET

SHELL3 SHELL4

22 23

C_TX2_HDMI+ C_TX2_HDMI-

C_TX1_HDMI+ C_TX1_HDMI-

C_TX0_HDMI+ C_TX0_HDMI-

C_TXC_HDMI+ C_TXC_HDMI-

HDMI Conn.

R573

2.2K_4

C753 *10P/50V_4

IN_D2[2] IN_D2#[2]

IN_D1[2] IN_D1#[2]

IN_D0[2] IN_D0#[2]

IN_CLK[2] IN_CLK#[2]

+3V

Close to Q24

C477

0.1U/16V_4

JWV LVDS

CN2

+3VLCD_CON

+3V_VEDID

*HOUSING 40P 2R FS

DFHS40FS104

lvds-50406-04071-001-40p-r

4142 1 2

EDIDCLK_R EDIDDATA_R TXLOUT0TXLOUT0+

TXLOUT1TXLOUT1+

TXLOUT2TXLOUT2+

PANEL_ID0

TXLCLKOUTTXLCLKOUT+

PANEL_ID1

TXUOUT0TXUOUT0+

TXUOUT1TXUOUT1+

ULT_EDP_HPD_R

TXUOUT2TXUOUT2+

TXUCLKOUTTXUCLKOUT+

+3V_CAM USBP3-_C USBP3+_C

DIGITAL_CLK_L DIGITAL_D2 VADJ1 BLON_CON

+VIN_BLIGHT

41 42

+VIN_BLIGHT

3 4 5

43 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

44 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

45 37 38 39 40

SDVO_CLK[2]

SDVO_DATA[2]

+3V

R575 2.2K_4

R572 2.2K_4

HDMI SMBus Isolation Close to HDMI connector

40 MIL

C752

0.1U/16V_4

+5V_HDMI_CRT

C751

0.01U/50V_4

20140821A-EMI request.

HDMI_DET_CHDMI_HPD

VC1 *TVM0G5R5M220R

7

C438 220P/50V_4

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

CN-LCD & HDMI

D

Date:

Wednesday, July 29, 2015

8

Sheet :

of

25 51

Rev.Size

3C

40 mils

+5V

VC6 *TVM0G5R5M220R

SSM14 spec is 40V 1A

+3V

R284 1M_4

6

1

Q19 2N7002K

+3V [ 2,4,10,11,12,13,14,15,16,17,18,19,21,22,24,26,27,28,29,30,31,33,34,35,36,42,44,45,46]

+3VLCD_CON

+5V [ 27,33,36,44]

+5V_HDMI_CRT [26]

+VIN [36,37,38,39,40,42,43,45,46,47]

HDMI_HPD_CON[ 2]

+3V +3VLCD_CON +5V +5V_HDMI_CRT +VIN

5

12

F1 FUSE SMD 1.5A 6V POLY

2

3

L21 *0_6/S

R277 20K/F_4

A

B

C

D

E

ESD PROTECTION

U13

VGA_CON_GREEN VGA_HSYNC_R VGA_SDA

+3V

4 4

DDI2_CRT_AUXN[2] DDI2_CRT_AUXP[2]

C422 0.1U/16V_4 C423 0.1U/16V_4

100 ohm differential impedance

DDI2_CRT_TX0P[2] DDI2_CRT_TX0N[2]

DDI2_CRT_HPD_Q[2]

3 3

C387 0.1U/16V_4 C382 0.1U/16V_4

R213 *0_4/S

R254 *100K/F_4

DDI2_CRT_AUXN_C DDI2_CRT_AUXP_C

R255 *100K/F_4

DDI2_CRT_TX0P_C DDI2_CRT_TX0N_C

DDI2_CRT_HPD

R214 100K/F_4

U12A

28

DP_RX_AUXN

29

DP_RX_AUXP

34

DP_RX_L0P

35

DP_RX_L0N

7

DP_RX_HPD

ANX6210FN-AB-R/QFN40

VGA_SDA VGA_SCL

RED_L

RED

GRN_L

GRN

BLUE_L

BLUE

HSYNC VSYNC

25 23

20 19

18 17

16 15

9 8

VGA_SDA VGA_SCL

VGA_RED_L VGA_RED

VGA_GREEN_L VGA_GREEN

VGA_BLUE_L VGA_BLUE

VGA_HSYNC VGA_VSYNC

R236 37.4/F_4

R239 37.4/F_4

Re

Rd

Rc

+5V_HDMI_CRT

R271

4.7K_4

R270

4.7K_4

Layout Note : Refer chip spec page-20 ~ 23.

It is strongly recommended to shield RGB with ground.

R223 75/F_4

R238 75/F_4

R241 75/F_4

R242 37.4/F_4

Rz

Ry

Rx

C392 4.7P/50V_4

C385 4.7P/50V_4

VGA_VSYNC_R VGA_SCL VGA_CON_BLUE

L18 BLM15BA470SN1D

L17 BLM15BA470SN1D

L15 BLM15BA470SN1D

C396 4.7P/50V_4

1

IO1

2

GND IO23IO3

*SP0504SHTG

U11

1

IO1

2

GND IO23IO3

*SP0504SHTG

IO4

REF

IO4

REF

6

VGA_CON_RED

5 4

+5V_HDMI_CRT

6 5 4

CRT CONN CN20

dsub-10327-00001-15p DFDS15FR276

VGA_CON_RED

VGA_CON_GREEN

VGA_CON_BLUE

C386 2.2P/50V_4

C395 2.2P/50V_4

C391 2.2P/50V_4

+5V_HDMI_CRT

C371 *0.1U/16V_4

1617

6 7

2 8 3 9 4

10

5

111 12 13 14 15

26

Place Rc,Rd,Re as close as possible to relative pins of ANX6210.

+1.05V_CRTLDO

40 mil ( Max. 470mW )

1.05V_CRT_DVDD

L19 *0_6/S

C348 0.1U/16V_4

C408 4.7U/6.3V_4 C372 0.1U/16V_4

1.05V_CRT_AVDD

2 2

+3V

1 1

L16 *0_6/S

L14 *0_4/S

L20 *0_4/S

A

C366 4.7U/6.3V_4

C389 0.1U/16V_4

3V_CRT_AVDD

C378 4.7U/6.3V_4

C373 1000P/50V_4

3V_CRT_DVDD

C338 4.7U/6.3V_4

C322 0.1U/16V_4

C334 1000P/50V_4

C364 0.1U/16V_4

C365 1000P/50V_4

C377 0.1U/16V_4

C376 0.1U/16V_4

C362 0.1U/16V_4

C418 1000P/50V_4

40 mil

C417 0.01U/50V_4

C400 1000P/50V_4

Pin-26 / LDO LDO 1.05V output, can be connected to AVDD10/DVDD10 input.

40 mil

C390 0.01U/50V_4

C388 1000P/50V_4

C375 0.01U/50V_4

C374 1000P/50V_4

C410 0.1U/16V_4

C402 0.01U/50V_4

U12C

5

DVDD10

22

DVDD10

DVDD10:

1.0V*29.83mA

DVSS_PLL

AVDD10:

1.0V*21.62mA

12

AVDD10

31

AVDD10

33

AVDD10

38

AVDD33

37

AVDD33

27

AVDD33

14

AVDD33

AVDD33:

3.3V*80.9mA

24

DVDD33

6

DVDD33

DVDD33:

3.3V*0.19mA

ANX6210FN-AB-R/QFN40

B

LDO

AVSS AVSS AVSS AVSS

26

39

40 36 32 13

41

EP

C407 1U/6.3V_4

Case 1: Keep Ra and remove Rb; ANX6210 in HPD process mode; Case 2: Keep Rb and remove Ra; ANX6210 in IRQ process mode.

Place Rx,Ry,Rz as close as possible to the R/G/B pins of VGA header.

3V_CRT_DVDD

R202

4.7K_4

Ra

R198 *10K_4

Rb

Pin-4 / CFG_SDA High : Pass VGA cable detect to DP HPD

PLTRST#[4,16,19,28,29,30,33,35]

+1.05V_CRTLDO +3V +5V_HDMI_CRT

1.05V_CRT_DVDD

1.05V_CRT_AVDD 3V_CRT_AVDD 3V_CRT_DVDD

C

R252 *0_4/S

R237 15/F_4 R217 15/F_4

Route the VGA_RED, VEA_BLUE, VGA_GREEN, VGA_CON_RED, VGA_CON_BLUE, VGA_CON_GREEN by 75 Ohm impendance.

Place Rf as close to the R_BIAS pin as possible.

R210

4.7K_4

3V_CRT_DVDD

+1.05V_CRTLDO

1.05V_CRT_DVDD

1.05V_CRT_AVDD

+3V [2,4,10,11,12,13,14,15,16,17,18,19,21,22,24,25,27,28,29,30,31,33,34,35,36,42,44,45,46]

+5V_HDMI_CRT [25]

3V_CRT_AVDD 3V_CRT_DVDD

Rf

R253 *6.2K_4

C406 *0.1U/16V_4

R245 12K/F_4

C394 *0.1U/16V_4

R212 10K_4

D

VGA_HSYNC_R VGA_VSYNC_R

C379

0.1U/16V_4

U12B

30

R_BIAS

3

CFG_SCL

4

CFG_SDA

10

TEST_EN

21

RESETN

ANX6210FN-AB-R/QFN40

1

XTAL_IN

XTAL_OUT

GPIO

Pin-11 / GPIO LOW : 4.7KΩ resistor to pull down, I2C Address is 0x52 and 0x8E

CRT_XIN

2

CRT_XOUT

11

R211

4.7K_4

C

Date:

Wednesday, July 29, 2015

R216 1M_4

Y4

1

3 4

2

27MHZ +-10PPM

C357 18P/50V_4

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

IC-CRT ANX6210

Sheet :

E

C358 15P/50V_4

of

26 51

Rev.Size

3C

A

B

C

D

E

C590

0.047U/25V_4

AGND

+5V+5V_AVDD

C589 1U/6.3V_4

USB 2.0 & AUDIO COMBO JACK

20140821A-EMI request.

C565 1000P/50V_4 C557 1000P/50V_4 C544 1000P/50V_4

HPOUT_L HPOUT_R

SENSE_A

+5VS5

C539

0.1U/25V_4

L22

4 3 1

2

MCM2012B900GBE

place to near Audio Chip or under Audio Chip.

C522 1000P/50V_4

C520 10U/10V_8

20140821A-EMI request.

USBP6-_C USBP6+_C

EC79 1000P/50V_4 EC65 1000P/50V_4 EC77 1000P/50V_4 EC54 1000P/50V_4 EC73 1000P/50V_4

AGND

Close to CODEC

R385 *0_8/S

AGND

Custom

Date:

Wednesday, July 29, 2015

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

IC-AUDIO ALC255-CG

27

AGND

CN10 Audio CONN

1 2 3 4 5

AGND

6 7 8

DGND

9 10 11 12 13 14 15

20140821A-EMI request.

16 17 18 19 20

Rev.Size

3C

Sheet :

E

of

27 51

3C

U17 *TPS793475DBVR

5

Vout

4

C763 *2.2U/6.3V_6

+3V

L36 HCB1005KF-181T15_4

C791 1U/6.3V_4

C796 10U/6.3V_Y6

C795

0.1U/16V_4

+3V_DVDD

3.3Vx0.51mA 20mil

Close to PIN1

C792 10P/50V_4

TO Digital MIC

20150209A-Change POWER from +1.5V to +3V.

+5V_AVDD

R580 10K_4

C767 0.1U/16V_4

3

ACZ_SPKR[11,14]

1 1

2

Q29 2N7002K

1

AGND

+1.5V

AMP_BEEP_R2

DIGITAL_D1[25] DIGITAL_CLK[25]

ACZ_SDOUT_AUDIO[14] BIT_CLK_AUDIO[14] ACZ_SDIN0[14]

L34 *HCB1005KF-181T15_4

L35 HCB1005KF-181T15_4

+3V

ACZ_SYNC_AUDIO[14] ACZ_RST#_AUDIO[14]

R576 10K/F_4

R579 2K/F_4

INT. Speaker

CN12 INT SPEAKER CONN

L_SPK+_R

1

L_SPK-_R

2

R_SPK-_R

3

R_SPK+_R

4

+1.5V +1.5V_AUDIO +1.5V_AVDD +3V +3V_DVDD +3V_DVDD-IO +3VS5 +5V +5V_AVDD +5V_DVDD +5VS5

FOR EMI

ACZ_SDIN0

ACZ_SDOUT_AUDIO

ACZ_SYNC_AUDIO

BIT_CLK_AUDIO

+1.5V_AUDIO

+1.5V_AVDD

+3V_DVDD

+3V_DVDD-IO

+5V_AVDD +5V_DVDD

A

EC75 *33P/50V_4

EC78 *10P/50V_4

EC74 *10P/50V_4

EC76 *33P/50V_4

+1.5V [30,31,40]

+3V [2,4,10,11,12,13,14,15,16,17,18,19,21,22,24,25,26,28,29,30,31,33,34,35,36,42,44,45,46]

+3VS5 [4,10,15,16,30,33,35,36,38,40,41,44,47]

+5V [25,33,36,44]

+5VS5 [4,32,36,38,39,40,41,42,43,44,45,46,47]

R593 *0_4/S R592 100/F_4 C788 10P/50V_4

R591 *0_4/S R587 33_4

+3V_DVDD-IO

C780

0.1U/16V_4

C773

0.1U/16V_4

AGND

Close to Pin 34,35,36

C604 1000P/50V_4

C602 1000P/50V_4

C603 1000P/50V_4

Digital power for HDA link. (Digital VCC (3.3V or 1.5V)

C782 10U/6.3V_Y6

C777 *0.1U/16V_4

AMP_BEEP_L

+3V_DVDD

C787 1U/6.3V_4

C789

4.7U/6.3V_6

Close to PIN7

3.3Vx0.51mA 15~20mil

C774 0.1U/16V_4

C790 1U/6.3V_4

3.3Vx0.0012mA 20mil

DMIC0 DMIC_CLK_R

ACZ_SDOUT_AUDIO

C785 10U/6.3V_Y6

ACZ_SYNC_AUDIO

AMP_BEEP

Close to Speaker

L28 PBY160808T-600Y-N L27 PBY160808T-600Y-N L26 PBY160808T-600Y-N L25 PBY160808T-600Y-N

C605 1000P/50V_4

Speaker P/N : DN003009000 ( 4Ω , Normal 1.5W, Max 2W ) 8Ω , 10mil < Trace Width < 20mil. 4Ω , 20mil < Trace Width < 40mil.

Make the trace length/ Speaker wire length of SPKL+/L-/R+/R- be the same as possible as you can.

+5V

40mil30mil

+5V_DVDD

L37 HCB1005KF-181T15_4

Class-D power supply

for intel HSW ULT

Q7 BA039040000 BA039040020

ACZ_RST#_AUDIO

VOLMUTE#[35]

B

+1.5V

R594 *2.2K_4

2

Q30 *METR3904-G

1 3

21

D12 RB500V-40

HD_BCLK

HD_SDIN0

10 11 12 34

CAPCAP+

+3V_DVDD

L_SPK+ L_SPKR_SPKR_SPK+

+5V_DVDD

C800 0.1U/16V_4 C798 10U/6.3V_Y6

C801 0.1U/16V_4 C797 10U/6.3V_Y6

35 37 36

42 43 44 45

25mil

Close to Pin 41

25mil

Close to Pin 46

+3V_DVDD

U29 ALC255-CG

1

DVDD

D0@3.3Vx0.51mW

2

GPIO0/ DMIC-DATA

3

GPIO1 / DMIC-CLK

4

DVSS

5

SDATA-OUT

6

BCLK

7

LDO3-CAP

8

SDATA-IN

9

DVDD-IO

D0@1.5Vx0.005mW

SYNC RESETB PCBEEP CPVEE

CBN CBP CPVDD

D0@3.3Vx0.0012mW

SPK-L+ SPK-LSPK-RSPK-R+

NC

49

5Vx0.001mA

R595 *1K/F_4

R597 *10K_4

Digital

D0@5Vx0.0012mW

PVDD1

PVDD246SPDIF-OUT/GPIO2

PDB

41

47

PD#

48

>40mils trace

D0@5Vx4.81mW D0@1.5Vx13.42mW

Analog

LINE1-VREFO-L

LINE1-VREFO-R

MIC2-R (PORTF)

MIC2-L (PORTF)

MIC2-VREFO

MONO-OUT

JD1

13

COMBO_GPI

+3VS5

C758 *2.2U/6.3V_4

+3V

C

26

AVDD1

40

AVDD2

25

AVSS1

38

AVSS2

27

LDO1-CAP

39

LDO2-CAP

28

VREF

32

HPOUT-L

33

HPOUT-R

24

LINE2-L

23

LINE2-R

22

LINE1-L

21

LINE1-R

20

VD33 STB

19

MIC CAP

31 30

18 17

29 16

JD3/GPIO3

JD2

15

14

SENSE_A_1

2013/07/05 Reserve for 1.5V power supply

AGND

5Vx4.81mA 8~20mil

1.5Vx13.42mA

AGND

C783 0.1U/16V_4

C784 2.2U/6.3V_6

HPOUT_L HPOUT_R

C768 4.7U/6.3V_6 C769 4.7U/6.3V_6

C770 10U/6.3V_Y6 R588 4.7K_4

R590 4.7K_4

MIC_R1 MIC_L1

+3V

AGND

U28

1

VIN

2

GND

3

ON/OFF

*G9090-150T11U

Close to PIN26

8mil

VREFOUT_C

0309 CQ Del Pin 30 MUTE_LED_CNTL Del Pin 15 R637 20K

R581 100K/F_4

R582 200K_4 R583 *39.2K/F_4

R596 *22K/F_4

C799 *10U/6.3V_6

C766 *0.1U/16V_4

C775 10U/6.3V_Y6

AGND

+1.5V_AVDD

AGND

R586 100K_4 C781 10U/6.3V_Y6

C793 10U/6.3V_Y6

Close to PIN28

C771 0_6 C772 *2.2U/6.3V_6

R578 0_4

Close to codec

5

VOUT

4

NC

C601 *1U/6.3V_4

L33 HCB1005KF-181T15_4

C776

0.1U/16V_4

L38 HCB1005KF-181T15_4

C794 10U/6.3V_Y6

AGND DGND

AGND

+3VS5

AGND

+1.5V_AUDIO +1.5V_AVDD

20mil

C757 *0.1U/16V_4

BYP GND2EN

HPA01091DBVR

Close to PIN40

0309 CQ New add

20150713A-PV-R for record issue.

R577 0_4

R589 2.2K_4

C786 *1U/6.3V_4

SENSE_A

EXT_MIC_L

GND AGND

L31

*HCB1005KF-181T15_4

L32

*HCB1005KF-181T15_4

C765 *1U/6.3V_4

1

Vin

3

R379 *10K_4

C591

0.1U/16V_4

Vset=1.242V

20150604A-R379 change to NU.

+5V

12

C764 *AZ2015-01H

20150216AAVDD2 must connect with +1.5V,

+1.5V

so cancel power source of +3V.

0319 CQ : Change MIC_R1 from PIN 20 to PIN 18 for ALC255-CG suggest Change MIC_L1 from PIN 19 to PIN 17 for ALC255-CG suggest Change VREFOUT_C from PIN 31 to PIN 29 for ALC255-CG suggest

AGND

Close to PIN27 & 39

AGND SHIELD AGND SHIELD AGND SHIELD

R341 *22K/F_4

AGND

+3V_DVDD-IO

D

USBPW_ON#[32,35]

USBP6-[12] USBP6+[12]

For USB2.0 Port on Right Side

5

4

3

2

1

TX_D1+

TX_D1-

28

TX_D2+

TX_D3+

TX_D3-

TX_D2-

TX_D4+

D D

TX_D4-

Place Cc,Cd,Ce,Cf close to each VDD10 pin-- 3,8,22,30 Place Cg & Ch close to each VDD10 pin22

RTL8111GS stuff Lx,Cy, Cz

+1.0V_LAN

C173 1U/6.3V_4

C134 0.1U/16V_4

Cg

Ch

Close Pin-3

Close Pin-22

C C

+3VLANVCC

RTL8111GS stuff Cc, Cd Remove For Not Using SWR mode Stuff Ca and Cb only, close to each VDD33 pin-- 11, 32

B B

Place Cc and Cd close to each VDD33 pin-- 23

(SWR mode need stuff Cx & Cz)

C142 0.1U/16V_4

C169 0.1U/16V_4

Ce

Cf

Close Pin-8

Close Pin-22

Ca

C141 *4.7U/6.3V_6

C143 *4.7U/6.3V_6

Close Pin-32

Close Pin-11

Close Pin-32

0306 CQ RTL8111H unstuff (or remove) Cc , Cd for LDO mode

>60mil

C151 0.1U/16V_4

C172 0.1U/16V_4

Cd

Close Pin-22

CbCdCc

C152 0.1U/16V_4

C146 0.1U/16V_4

Close Pin-11

C171 *0.1U/16V_4

Cc

Cz

Close Pin-30

SWR, Close Lx SWR, Close Pin-23

C174 *4.7U/6.3V_6

C170 *0.1U/16V_4

SWR, Close Pin-23

Differential Impedance : 100Ω

A A

Trace<30 mil Width > 60 mil

Lx : SWR

L7 *4.7UH,+-20%,650MA_1210

C166 *4.7U/6.3V_6

Cy

SWR, Close Lx

20150316ARich Power recommend to change power for S0 state.

if ISOLATEB pin pull-low,the LAN chip will not drive it's PCI-E outputs ( excluding PCIE_WAKE# pin )

PLTRST#[4,16,19,26,29,30,33,35]

PCIE_RXN9_LAN[12] PCIE_RXP9_LAN[12]

R105 0_8

Rx : LDO

LDO Mode:Stuff Rx Switch Mode:Stuff Lx

0306 CQ RTL8111H stuff C1017 (LDO mode) Unstuff C132 , C133

+1.0V_LAN

Pin-21 LANWAKEB : O/D, Low Active, PU via 1KΩ to +3VS5 on CPU side.

PCIE_WAKE#[4,29,30,35]

C168 0.1U/16V_4 C167 0.1U/16V_4

CLK_PCIE_LANN[13] CLK_PCIE_LANP[13]

PCIE_TXN9_LAN[12] PCIE_TXP9_LAN[12]

PCIE_CLKREQ_LAN#[13]

Pin-12 CLKREQB : O/D, PU via 10KΩ to +3V on CPU side.

+3V

1 2

R104 1K_4

R103 15K/F_4

C175 0.1U/16V_4

ISOLATEB

PCIE_RXN9_LAN_C PCIE_RXP9_LAN_C

RTL8111HS (SWR Mode) Pin-24 REGOUT : Switching Regulator 1.0V Output.

RTL8111H (LDO Mode) Pin-24 REGOUT : LDO Regulator 1.0V Output.

+1.0V_LAN_REGOUT

>60mil

R100 *0_4/S

TP9

TP11

TP10

LAN_AMBLED#

LAN_WLED#

24

REGOUT(NC)

23

VDDREG(VDD33)

22

DVDD10(NC)

21

LANWAKEB

20

ISOLATEB

19

PERSTB

18

HSON

17

HSOP

LAN_CLKRQ

LAN_XTAL25_IN[32]

For EMI 0 ~ 22 ohm

25

27

26

LED0

LED1/GPO

LED2(LED1)

RTL8111H-CG

16

LAN_XTAL1

R102 *0_4

XTAL2

XTAL1

28

30

CKXTAL229CKXTAL1

HSIP13HSIN14REFCLK_P15REFCLK_N

CLKREQB

12

11

RSET

31

AVDD10

AVDD33(NC)

10

R99 *0_4/S

C165 *10P/50V_4

1

2

Y1 *25MHZ +-10PPM

4

3

C160 *10P/50V_4

R97 2.49K/F_4

Please add 9 GND VIAs connection with thermal PAD

32

GND

RSET

AVDD33

MDIP0 MDIN0

AVDD10(NC)

MDIP1

MDIN1 MDIP2(NC) MDIN2(NC)

AVDD10

MDIP3(NC)9MDIN3(NC)

U6 RTL8111H-CG

+3VLANVCC

R392 330_4

+1.0V_LAN

+3VLANVCC

33

1 2 3 4 5 6 7 8

+1.0V_LAN

20140930A-Transformer must H<2.5mm, so change source & pin define.

MDI0+

MDI0-

MDI1+

MDI1-

MDI2+

MDI2-

MDI3+

MDI3-

TRA_V_DAC

C133

0.01U/50V_4

1 2

5 6

7 8

11 12

3 4 9

10

U5

TD1+ TD1-

TD2+ TD2-

TD3+ TD3-

TD4+ TD4-

TCT1 TCT2 TCT3 TCT4

NA0069R

MX1+

MX1-

MX2+

MX2-

MX3+

MX3-

MX4+

MX4-

MCT1 MCT2 MCT3 MCT4

24 23

20 19

18 17

14 13

22 21 16 15

MDI0+_1

MDI0-_1

MDI1+_1

MDI1-_1

MDI2+_1

MDI2-_1

MDI3+_1

MDI3-_1

LAN_MCTG3

R79 75/F_4

C100 *0.01U/100V_06

C613 1000P/50V_4

(Amber)

LAN_AMBLED#

LAN_AMBLED

MDI0+_1

MDI0-_1

MDI1+_1

MDI2+_1

MDI2-_1

MDI1-_1

MDI3+_1

MDI3-_1

(White)

LAN_WLED#

LAN_WLED

LAN_MCTG1

LAN_MCTG2

R83 75/F_4

R80 75/F_4

C101 *0.01U/100V_06

LAN_MCTG0

C118 *0.01U/100V_06

R84 75/F_4

C119 *0.01U/100V_06

LAN_MCTG

LAN CONN

CN17 RJ45_CONN

12

LED_AMB#

11

LED_AMB

10

MDI0+

9

MDI0-

8

MDI1+

7

MDI2+

6

MDI2-

5

MDI1-

4

MDI3+

3

MDI3-

2

LED_WIT#

1

LED_WIT

+3VLANVCC

R74 330_4

C89 1000P/50V_4

C128 10P/3KV_1808

14

GND1

13

GND2

EC13

0.1U/25V_4

20141007A-EMI request.

R15 *0_6/S

R77 *0_6/S

Power trace Layout W > 60mil

+1.0V_LAN +1.0V_LAN_REGOUT +3V +3VLANVCC

5

+1.0V_LAN

+1.0V_LAN_REGOUT

+3V [2,4,10,11,12,13,14,15,16,17,18,19,21,22,24,25,26,27,29,30,31,33,34,35,36,42,44,45,46]

+3VLANVCC [32,44]

RTL8111GS : Switching Regulater RTL8111G : LDO Regulater

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

IC-LAN RTL8111GS-CG/RJ45

C

Date:

4

3

2

IC-LAN RTL8111GS-CG/RJ45

Wednesday, July 29, 2015

1

Sheet :

of

28 51

Rev.Size

3C

5

4

3

2

1

29

D D

+3VCARD

SD_D2 SD_D3 SD_CMD SD_CD#

RTS5237_GPIO

RTS5237_3Vaux

PCIE_WAKE#[4,28,30,35]

PLTRST#[4,16,19,26,28,30,33,35]

PCIE_CLKREQ_CR#[13] PCIE_TXP5_CARD[12]

PCIE_TXN5_CARD[12] CLK_PCIE_CRP[13]

CLK_PCIE_CRN[13]

PCIE_RXP5_CARD[12]

C C

PCIE_RXN5_CARD[12]

R339 *0_4/S

C545 0.1U/16V_4 C551 0.1U/16V_4

Zdiff = 100 ohm

RTS5237_RREF : W > 12mil, L < 200mil.

PCIE_CLKREQ_CR#_R

PCIE_RXP5_CARD_C PCIE_RXN5_CARD_C

Please add 9 GND VIAs connection with thermal PAD

Colse to Chip

R352

6.2K/F_4

+3V +3VCARD

C553 *100P/50V_4

1 2

Power Budget ~ 1.2A ( W > 40mil )

C577 10U/10V_8

C579

0.1U/16V_4

U15 RTS5227S-GRT

1 2 3 4 5 6 7 8

33

RTS5237_RREF

R356 *0_6/S

PERST# CLKREQ# HSIP HSIN REFCLKP REFCLKN HSOP HSON

GND

29

31

27

26

30

32

28

NC25NC

SP7

GPIO

3V3aux

WAKE#

SD_CD#

MS_INS#

RTS5227S-GRT

RREF93V3_IN11DV12S14SP115SP2

AV1210CARD_3V312NC

16

13

RTS5237_DV12SRTS5237_AV12

SP6 SP5 SP4

DV33_18

SP3

NC NC NC

24 23 22 21 20 19 18 17

SD_D0_R SD_D1_R

R331 10K_4

R333 *0_6/S C525 0.1U/16V_4R330 *0_4/S C524 4.7U/6.3V_6

Resister close to chip.

SD_D2_R SD_D3_R SD_CMD_R DV33_18

SD_CLK_R

R338 33_4 R340 33_4 R343 *0_4/S

DV33_18 : W > 20mil, L < 200mil.

R350 22_4

R353 33_4 R363 33_4

Output capability is 800mA. Current protection is 950mA. ( W > 40mil )

C550 1U/10V_4

20140821A-EMI request.

RTS5237_GPIO Imax = 15mA

+3V

RTS5237_3Vaux : Power Budget ~ 375mA ( W > 30mil )

C575

5.6P/16V_4

SD_D3

SD_D2

EC59 *5.6P/16V_4

C564 *0.1U/16V_4

C563 0.1U/16V_4

C576 4.7U/6.3V_6

EC58 *5.6P/16V_4

CLOSE CONN

SD_CLK SD_D0

SD_D1 SD_WP

SD_D2 SD_D3 SD_CMD SD_CD#

SD_CLK SD_D0

SD_D1 SD_WP

SD_D1

SD_D0

Reserve for EMI

EC61 *5.6P/16V_4

EC62 *5.6P/16V_4

W > 20mil

R360 *0_4/S

CARD READER For JWL 14".

CN13 *CARDREADER CONN

1

DAT2

2

DAT3

3

CMD

4

C/D

5

VSS1

6

VDD

7

CLK

8

VSS2

9

DAT0

10

DAT1

11

W/P

12

GND

13

GND

14

GND

15

GND

CARD READER For TWL 15".

CN11 CARDREADER CONN

1

DAT2

2

DAT3

3

CMD

4

C/D

5

VSS1

6

VDD

7

CLK

8

VSS2

9

DAT0

10

DAT1

11

W/P

12

GND

13

GND

14

GND

15

GND

20141127A-TWB CN11--Vender inform : DFHD11MR029, DFHS11FR153 has same footprint / pin define / dimenstion , only different for coating. Change P/N for DFHS11FR153.

DFHS11FR153 : TWL (15") DFHD11MR052 : JWL (14")

C582

0.1U/16V_4

B B

C584 *4.7U/6.3V_6

20140811A-Realtek recommand to remove C454 4.7uF. Base on Rev:A test result to discuss on Rev:B.

C583

0.1U/16V_4

C585

4.7U/6.3V_6

Share Pin

+3V +3VCARD

+3V [2,4,10,11,12,13,14,15,16,17,18,19,21,22,24,25,26,27,28,30,31,33,34,35,36,42,44,45,46]

+3VCARD

PIN-15

PIN-16

PIN-17

PIN-19

PIN-20

PIN-21

PIN-29

PIN-30

A A

5

4

3

2

SP1

SP2

SP3

SP4

SP5

SP6

SP7

SD_CD#

SD_D1

SD_D0

SD_CLK

SD_CMD

SD_D3

SD_D2

SD_WP

SD_CD#

C

Date:

---

MS_D1

MS_D0

MS_D2

MS_D3

MS_CLK

MS_BS

---

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

IC-CR RTS5227S-GRT

Wednesday, July 29, 2015

SD Data 1 (SD_D1)

I/O

SD Data 0 (SD_D0)

I/O

SD Clock signal (SD_CLK)

I/O

SD CMD signal (SD_CMD)

I/O

SD Data 3 (SD_D3)

I/O

SD Data 2 (SD_D2)

I/O

SD Write Protect signal

I

SD Card Detection signal

I

Sheet :

1

of

29 51

Rev.Size

3C

A

B

C

D

E

No Function.

30

24mil

C472 *0.1U/16V_4

2 4

+3V

1

R313 *0_8

Q25 AO3409

3

30V, 2.6A

2

20150407A-Delet double net name for +3V_AOCS.

1 3

USBP5+ USBP5-PCIE_TXP6_WLAN_HMC

C490

0.1U/16V_4 R322 200K_4

C516 *0.022U/25V_4

RF_LINK# [35]

USBP5+ [12]

USBP5- [12]

3

1

R308 10K_4

2

Q23 2N7002K

EC_AOCS# [35]

+1.5V +3VS5 +3VPCU+3V_WLAN_P

HMC/WLAN

C487 *10U/6.3V_Y6

C508 *0.1U/16V_4

C489 *0.01U/50V_4

4 4

CN26

DFHS52FR044

*MINI PCIE H=5.2

6

+1.5V

28

+1.5V

48

+1.5V

BT_OFF#

20150305A-EC_DEBUG reserve for TP.

CLK_24M_DEBUG[10,30]

4

PCIE_TXP6_WLAN[12] PCIE_TXN6_WLAN[12] PCIE_RXP6_WLAN[12] PCIE_RXN6_WLAN[12]

CLK_PCIE_WLANP[13] CLK_PCIE_WLANN[13]

RP8 *0_4P2R_4

2 2

RP10 *0_4P2R_4

4 2

RP5 *0_4P2R_4

4

3 1 1 3 1 3

PCIE_CLKREQ_WLAN#[13]

PCIE_TXN6_WLAN_HMC PCIE_RXP6_WLAN_HMC PCIE_RXN6_WLAN_HMC CLK_PCIE_WLANP_HMC CLK_PCIE_WLANN_HMC

TP58

R319 *0_4/S

TP57

20150330A-Change to TP.

+3V_WLAN_P

2

Q20 *LTC044

3 3

PCIE_WAKE#[4,28,29,35]

+3V_WLAN_P

S0~3.357V S4~0.142V

EC_PCIE_WAKE#[35]

S0~3.261V S4~3.308V

13

2

Q21 LTC044

13

R302 10K/F_4

Intel 7260 BGN + BT WLAN/combo Wake up from WLAN for iSCT (AOAC) Output / OD

S0~3.355V S4~0.168V

EC_DEBUG PLTRST#

CLKREQ_WLAN#

BT_COMBO_EN#

MINICAR_PME# LFRAME#

51

Reserved

49

Reserved

47

Reserved

45

Reserved

19

Reserved

17

Reserved

33

PETp0

31

PETn0

25

PERp0

23

PERn0

13

REFCLK+

11

REFCLK-

7

CLKREQ#

5

BT_CHCLK

3

BT_DATA

1

WAKE#

43

Reserved

37

Reserved

35

GND

29

GND

27

GND

21

GND

15

GND

H=5.2

minipci-aaa-pci-092-p05-52p-smt

ph

+3.3V

+3.3V +3.3Vaux Reserved Reserved

LED_WLAN# LED_WPAN#

LED_WWAN#

USB_D+

USB_D-

SMB_DATA

SMB_CLK

PERST#

W_DISABLE#

Reserved Reserved Reserved Reserved Reserved

GND GND GND GND GND GND GND

PAD54PAD53HOLE55HOLE

56

52 2 24 41 39 44 46 42 38 36 32 30 22 20 16 14 12 10 8 50 40 34 26 18 4 9

PLTRST#

WLAN_DISABLE#

LAD0 LAD1 LAD2 LAD3

R328 *10K_4

R327 *10K_4

HMC_LED_WLAN# HMC_LED_BT#

C467 *0.1U/16V_4

C479 *0.1U/16V_4

USBP5+_HMC USBP5-_HMC

C470 *10U/6.3V_Y6

C475 *0.1U/16V_4

R326 *0_4 R325 *0_4

RP7 *0_4P2R_4

PLTRST# [4,16,19,26,28,29,33,35]

Support Wake Function(Reserve)

(Low Active)

WLAN_OFF_L POWER DOWN LAN CHIP from EC? WIFI_DISABLE_L disable Antenna from PCH?

WLAN_OFF_L : Follow Y07 control by EC.

+3V_WLAN_P

R349 10K_4

R368 10K_4

2 2

Q26 2N7002DW

WLAN_OFF_PCH[4]

BT_OFF_PCH[14]

1 1

+1.5V +3V +3V_WLAN_P +3VPCU +3VS5

A

+1.5V [27,31,40]

+3V [2,4,10,11,12,13,14,15,16,17,18,19,21,22,24,25,26,27,28,29,31,33,34,35,36,42,44,45,46]

+3V_WLAN_P

+3VPCU [6,13,32,33,34,35,37,38]

+3VS5 [4,10,15,16,27,33,35,36,38,40,41,44,47]

5

2

3

4

6

1

+3V_WLAN_P

R347 10K_4

R355 *0_4/S

RF_LINK#

R348 *0_4/S

B

+3V_WLAN_P

C598 0.1U/16V_4

C599 0.1U/16V_4

C597 10U/6.3V_6

TP60

WLAN_DISABLE# BT_OFF#

PLTRST#

TP59

20150305A-Remove PCH_SUSCLK circuit for NGFF.

R354 10K_4

C600 0.1U/16V_4

LAD3[10,33,35] LAD2[10,33,35] LAD1[10,33,35] LAD0[10,33,35]

+WL_VIO

WIFI_SUSCLK

NGFF_LED_BT#

NGFF_LED_WLAN#

+3V_WLAN_P

WIFI/BT COMBO (NGFF E KEY)

CN29 WLAN_NGFF_CONN_75P_E-KEY

74 72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32

30 28 26 24

22 20 18 16 14 12 10

8 6 4 2

C

NGFF

3.3Vaux

3.3Vaux NC NFC_ANT_N NFC_ANT_P NFC_VDDANT ALERT I2C_CLK I2C_DATA W_DISABLE PDN# PERST0# SUSCLK_32KHz LTE_SOUT LTE_SIN NC NFC_WI_IN NFC_SWP2_IO NC UART_CTS UART_RTS UART_Rx

SLOT A-SD

KEY KEY KEY KEY

UART_Tx UART_Wake GND LED#2 PCM_IN PCM_OUT PCM_SYNC PCM_CLK LED#1

3.3Vaux

E

SDIO_RESET

SDIO_WAKE

GND76GND

77

RESERVED RESERVED

PEWake0#

CLKREQ0# REFCLKN0

REFCLKP0

SDIO_DAT3 SDIO_DAT2 SDIO_DAT1 SDIO_DAT0

SDIO_CMD

SDIO_CLK

GND

GND PETn1 PETp1

GND PERn1 PERp1

GND

GND PETn0 PETp0

GND PERn0 PERp0

GND

KEY KEY KEY KEY

GND

USB_D-

USB_D+

GND

75 73 71 69 67 65 63 61 59 57 55 53 51 49 47 45 43 41 39 37 35 33

31 29 27 25

23 21 19 17 15 13 11 9 7 5 3 1

WAKE/REQ 53, 55 OD

MINICAR_PME# CLKREQ_WLAN#

CLK_PCIE_WLANN_NGFF CLK_PCIE_WLANP_NGFF

PCIE_RXN6_WLAN_NGFF PCIE_RXP6_WLAN_NGFF

PCIE_TXN6_WLAN_NGFF PCIE_TXP6_WLAN_NGFF

USBP5-_NGFF USBP5+_NGFF

EC53

R344

*33P/50V_4

*0_4

RP6 0_4P2R_4

RP12 0_4P2R_4

RP11 0_4P2R_4

BT

2

RP9 0_4P2R_4

4

CLK_24M_DEBUG [10,30]

For EMI Suggestion

4 2

2 4

D

3 1

1 3

LFRAME# [10,33,35]

CLK_PCIE_WLANN CLK_PCIE_WLANP

PCIE_RXN6_WLAN PCIE_RXP6_WLAN

PCIE_TXN6_WLAN PCIE_TXP6_WLAN

USBP5USBP5+

Document Number

C

Date:

Document Number

Wednesday, July 29, 2015

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

CN-WLAN & BT/HMC & NGFF

Sheet :

E

of

30 51

Rev.Size

3C

1

2

3

4

5

6

7

8

31

FMC/iSATA

A A

Mini PCI-E Card 2- Full size

C460 *0.1U/16V_4

C459 *0.1U/16V_4

C450 *4.7U/6.3V_6

C473 *0.1U/16V_4

C451 *4.7U/6.3V_6

mSATA

2

SATA_TXP2[12] SATA_TXN2[12]

SATA_RXN2[12] SATA_RXP2[12]

B B

RP2 *0_4P2R_4

4

2

RP1 *0_4P2R_4

4

1 3

SATA_TXP2_HMC1 SATA_TXN2_HMC1

SATA_RXN2_HMC1 SATA_RXP2_HMC1

C454 *0.01U/50V_4 C453 *0.01U/50V_4

C456 *0.01U/50V_4 C455 *0.01U/50V_4

SATA_TXP2_HMC2 SATA_TXN2_HMC2

SATA_RXN2_HMC2 SATA_RXP2_HMC2

Place Cap close to conn within 100mils

+3V

C478 *4.7U/6.3V_6

CN22 *MINI PCIE H=5.2

51

Reserved

49

Reserved

47

Reserved

45

Reserved

43

Reserved

41

Reserved

39

Reserved

37

Reserved

35

GND

33

PETp0

31

PETn0

29

GND

27

GND

25

PERp0

23

PERn0

21

GND

19

Reserved

17

Reserved

15

GND

13

REFCLK+

11

REFCLK-

9

GND

7

CLKREQ#

5

BT_CHCLK

3

BT_DATA

1

WAKE#

DFHS52FR044

H=5.2

LED_WPAN# LED_WLAN#

LED_WWAN#

USB_D+

USB_D-

SMB_DATA

SMB_CLK

+3.3Vaux

PERST#

W_DISABLE#

Reserved Reserved Reserved Reserved Reserved

GND53GND

54

+3.3V

GND

+1.5V

GND

+1.5V

GND

+1.5V

GND

+3.3V

52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18

16 14 12 10 8 6 4 2

USBP7+_C USBP7-_C

C469 *0.01U/50V_4

+1.5V

C474 *0.1U/16V_4

R305 *0_4

R297 *0_4/S R301 *0_4/S

C458 *4.7U/6.3V_6

DEVSLP1 [31]

USBP7+ [12] USBP7- [12]

CN28

1 3 5 7

9 11 13

Pin--21 / OC SSD : GND = SSD

Place Cap close to conn within 100mils

SATA_RXP2 SATA_RXN2

SATA_TXN2

C C

SATA_TXP2

2

RP3 0_4P2R_4

4 2

RP4 0_4P2R_4

4

1 3

SATA_RXP2_NGFF1 SATA_RXN2_NGFF1

SATA_TXN2_NGFF1 SATA_TXP2_NGFF1

C552 0.01U/50V_4 C546 0.01U/50V_4

C541 0.01U/50V_4 C540 0.01U/50V_4

SATA_RXP2_NGFF2 SATA_RXN2_NGFF2

SATA_TXN2_NGFF2 SATA_TXP2_NGFF2

Pin--69 / PEDET : GND = SATA

15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75

NGFF

PRESERVE GND N/A N/A N/A N/A B-KEY_13 B-KEY_15 B-KEY_17 B-KEY_19 WWAN/SSDIND_N N/A N/A GND N/A N/A GND N/A N/A GND SATA RX+ SATA RXGND SATA TXSATA TX+ GND REFCLKN REFCLKP GND M-KEY_59 M-KEY_61 M-KEY_63 M-KEY_65 N/A IFDET GND GND GND

SSD_NGFF_CONN_75P_B-KEY

ngff-12-0002-01-75p-kb

B

M

3.3Vaux

B-KEY_12 B-KEY_14 B-KEY_16 B-KEY_18

Device sleep

M-KEY_60 M-KEY_62 M-KEY_64 M-KEY_66

SUSCLK

3.3Vaux

DAS#

MFG1 MFG2

N/A N/A

N/A N/A N/A N/A N/A N/A N/A N/A N/A

N/A N/A N/A N/A N/A N/A N/A N/A

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74

R371 *0_6/S

TP61

Pin--10 / DAS & DSS# : Device Activity

R351 *0_4/S

R329 *0_4/S

check power consumption

R335 *0_8/S

+3V

EC63 *10U/6.3V_Y6

Reserve for RF

+3V

R357 10K_4

Device Sleep Signal H : SSD enter sleep mode. Device Sleep Signal L : SSD exit sleep mode.

Added in MV stage (8/13)

20150312A-ADD

EC51 *10U/6.3V_Y6

DEVSLP1 [31]

PCH_SUSCLK [13]

+3V

Max. 1.8A, W > 100mil

EC49 *470P/50V_4

Reserve for RF

+1.5V +3V

D D

Follow TWE 2280/2242

1

2

3

4

5

+1.5V [27,30,40]

+3V [2,4,10,11,12,13,14,15,16,17,18,19,21,22,24,25,26,27,28,29,30,33,34,35,36,42,44,45,46]

6

C

Date:

Wednesday, July 29, 2015

7

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

CN-SSD/FMC & NGFF

Sheet :

of

31 51

8

Rev.Size

3C

5

4

3

2

1

USB 2.0/3.0 Combo

+5VS5+5VS5

32

Follow TWE

USB_CHARGER_ON[35]

MAINON[35,39,40,41,44] EC_USB_CTRL2[35]

D D

EC_USB_CTRL3[35]

USBP1-[12] USBP1+[12]

R359 *0_4/S

EC_USB_CTRL2 EC_USB_CTRL3

R365 *10K/F_4

U16

5

EN

6

CTL1

7

CTL2

8

CTL3

11

DM_IN

10

DP_IN

2

DM_OUT

3

DP_OUT

TPS2546

High Active

OUT

GND /STATUS PADGND

ILIM_HI

ILIMI_LO

ILIM_SEL

/FAULT

R375 10K/F_4

1

IN

12 14 9 17 16 15 4 13

R378 *0_4

R345 10K/F_4

R358

80.6K/F_4

IC current limit is 2A Ios = 48000/RILIM0

DB2 modify: EMI stuff L40

L24 MCM2012B900GBE

1

USBP1-_CHA USBP1+_CHA

C596 *Clamp-Diode C594 *Clamp-Diode

C C

USB30_RX1-[12] USB30_RX1+[12]

USB30_TX1-[12] USB30_TX1+[12]

C586 0.1U/16V_4 C581 0.1U/16V_4

USB3_1USB3_1+

R381 *0_4/S R380 *0_4/S

R369 *0_4/S R366 *0_4/S

4 3

2

12 12

C595 4.7U/6.3V_6 C549 0.1U/16V_4

C559 470P/50V_4

C543 150U/6.3V(H1.9)

12

+

R364 22K/F_4

12

+

+5V_USBP1

C542 *150U/6.3V(H1.9)

80 mils (Iout=2A)

C548 0.1U/16V_4 C547 470P/50V_4 VC4 *AVLC 5S_4 C560 1000P/50V_4

+5V_USBP1 USBP1-_C USBP1+_C

USB30_RX1-_C USB30_RX1+_C

USB30_TX1-_C USB30_TX1+_C

USB 3.0

CN30 USB3.0 CONN

1

VBUS

1

2

D-

2

3

D+

4

GND

5

SSRX-

6

SSRX+

7

GND

8

SSTX-

9

SSTX+

9

12

DFHS09FR436 usb-2ub4029-200601f-9p

D7

2

10

1

*SP3010-04UTG

3

11111010131312

79 4

USB30_TX1-_CUSB30_RX1+_C

6 5

USB30_TX1+_CUSB30_RX1-_C

LAN_XTAL25_IN[28]

+5VS5

VC3 *AVLC 5S_4

B B

USBPW_ON#[27,35]

C502 1U/6.3V_4

Active Low 150 mils (Iout=3.7A)

U14 AP2501M8-13

2

VIN1

3

VIN2

4

EN

1

GND

OUT3 OUT2 OUT1

8 7 6 5

OC

+5V_USBP0

USB 3.0

C500 150U/6.3V(H1.9)

C503 0.1U/16V_4

C483 1000P/50V_4

C484 470P/50V_4

VC2 *AVLC 5S_4

C486 *150U/6.3V(H1.9)

12

+

LAN

PCH_XTAL24_IN[13]

PCH

CLKGEN_RTC_X1[13]

R208 33_4

C367 *10P/50V_4

20150713A3-PV-R 20150727A1-PV-R change for crystal.

R204 *22/F_4

C341 *10P/50V_4

LAN_XTAL25_IN_R

PCH_XTAL24_IN_R

20140922A-For SLG3NB3455V, R209 change to 0Ω.

Green CLK Circuitry

+3VPCU

C292 0.1U/16V_4

+3V_RTC voltage has 3V when current from RTC battery through D6. But voltage down around 2.5V when current from G-CLK. So has more ΔV for G-CLK. Doesn't recommand +3V_RTC through G-CLK.

+3V_RTC_0+3VLANVCC +3V_RTC

R219 360/F_4

C370 0.1U/16V_4

C361 22U/10V_Y8

R196 *0_6

C315 2.2U/6.3V_6

RTC

CLK_27M_XTAL_IN[21]

GPU

20150518A-Add UART2 & USB switch IC for USB debug. 20150720A-Remove UART switch circiut to same with DB.

4 3

USBP2-[12] USBP2+[12]

USB30_RX2-[12] USB30_RX2+[12]

USB30_TX2-[12] USB30_TX2+[12]

A A

+1.0V +3V_AON +3V_RTC +3V_RTC_0 +3VLANVCC +3VPCU +5V_USBP0 +5V_USBP1 +5VS5

+3V_RTC_0 [13]

+3VLANVCC [28,44]

+5V_USBP0 +5V_USBP1

C506 0.1U/16V_4 C505 0.1U/16V_4

+1.0V [2,4,6,16,35,41]

+3V_AON [19,22,47]

+3V_RTC [4,13,15]

+3VPCU [6,13,30,33,34,35,37,38]

+5VS5 [4,27,36,38,39,40,41,42,43,44,45,46,47]

5

L23 MCM2012B900GBE

1

2

R336 *0_4/S R334 *0_4/S

USB3_2USB3_2+

R324 *0_4/S R323 *0_4/S

USBP2-_C USBP2+_C

USB30_RX2-_C USB30_RX2+_C

USB30_TX2-_C USB30_TX2+_C

C504 *Clamp-Diode

C507 *Clamp-Diode

12

4

C527 *Clamp-Diode

C523 *Clamp-Diode

12

C518 *Clamp-Diode

C519 *Clamp-Diode

12

CN24 USB3.0 CONN

1A

1

VBUS

1

2

D-

2

3

D+

4

GND

5

SSRX-

6

SSRX+

7

GND

8

SSTX-

9

SSTX+

12

DFHS09FR436 usb-2ub4029-200601f-9p

20150209A-Change POWER from +1.05V to +1.0V.

11111010131312

3

R200 *22_4

C328 *10P/50V_4

+3VLANVCC

+1.0V

+3V_AON

C306 15P/50V_4

C305 12P/50V_4

4

3

1

2

CLK_27M_XTAL_IN_R

20141002A-Without clock output by PIN-12.

C323 0.1U/16V_4

C336 0.1U/16V_4

C343 *0.1U/16V_4

GEN_XTAL25_OUT

Y3 25MHZ +-10PPM

GEN_XTAL25_IN

U10 SLG3NB3455

6

25M

5

24M

9

32Khz

12

27Mhz/NC

VDD_RTC_OUT

8

VDDIO_25M VDDIO_24M3GND

11

VDDIO_27/NC

16

XTAL_OUT

1

XTAL_IN

2

+V3.3A

VDD

VBAT

GND GND GND

15 2 10

14 7

13 4 17

+3V_RTC_R

+3V_RTC_G

20mils width(min)

+3V_RTC_0,+3V_RTC_R,+3V_RTC..

P/N

UMA

DIS

AL003455002

AL003454000

AL003455002 IC OTHER(16P) SLG3NB3455(TQFN)

SLG3NB3455 : Pin-11 & 12 --> NC.

AL003454000 IC OTHER(16P) SLG3NB3454(TQFN)

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

IC-USB3.0/G-CLK

C

Date:

IC-USB3.0/G-CLK

Wednesday, July 29, 2015

Iout : 2.5 ~ 6uA

R202 C300

No Stuff No Stuff

Stuff

Sheet :

1

of

32 51

Rev.Size

3C

A

0327 : DEL Touch Pad Connector CN7 for U83 0927 Change CN4 PIN2 from +3V to DEEP_PWRLED# for Power LED

+3VPCU

B

C

D

E

33

Power Botton Connector

R78 10K/F_4

S0~0.078V

4 4

PWR_LED#[35]

DEEP_PWRLED#[34]

3 3

2 2

S0~3.262V

LAD0[10,30,35] LAD1[10,30,35] LAD2[10,30,35] LAD3[10,30,35] CLK_PCI_TPM[10]

C324 *10P/50V_4

2

C93

0.1U/16V_4

FOR EMI

LFRAME#[10,30,35] PLTRST#[4,16,19,26,28,29,30,35]

R195 *4.7K/F_4

+3V

SERIRQ[10,35]

R154 *4.7K/F_4

+3V

CLKRUN#[10,35]

Q2 LTC044

1 3

LID_EC#[35]

NBSWON1#[35]

Address

R194 *0_4 R193 *0_4 R190 *0_4 R189 *0_4

R191 *33_4

R192 *0_4

USBP8+[12] USBP8-[12]

BADD 4EH/4FHIGH

LPCPD#_TPM

+3VPCU

C86

0.1U/16V_4

DEEP_PWRLED#

C85

0.1U/16V_4

C84

0.1U/16V_4

C83

0.1U/16V_4

20140821A-EMI request.

LAD0_T LAD1_T LAD2_T LAD3_T

LFRAME#_T

Pin1 : +3VPCU(LIDSWITCH PWR) Pin2 : +3V POWER LED Pin3 : LIDSWITCH Pin4 : GND Pin5 : GND Pin6 : POWERON#

1 2 3 4 5 6

CN3 POWER BTN CONN

DFFC06FR062

50503-0060n-001-6p-l

Fingerprint Conn

R278 *0_4/S R276 *0_4/S

C439 *Clamp-Diode

12

TPM (1.2)

(default)

U8 *SLB9635TT1.2-FW3.17

26

LAD0

23

LAD1

20

LAD2

17

LAD3

21

LCLK

22

LFRAME#

16

LRESET#

28

LPCPD#

27

9

15

1 3

12

SERIRQ TEST/BADD CLKRUN# NC

NC NC

GPIO

GPIO2

TESTI

XTALI/32K IN

XTALO

VDD VDD VDD VSB

GND GND GND GND

C662

0.1U/16V_4

FAN1_PWM[35]

C652 *220P/50V_4

FAN1SIG[35]

+3V

20140821A-EMI request.

C441 *0.1U/16V_4

88513-0601-6p-l-smt

DFFC06FR162

*FINGER PRINT CONN

USBP8+_C USBP8-_C

C440 *Clamp-Diode

12

+3V

C299 *0.1U/16V_4 C235 *0.1U/16V_4 C300 *0.1U/16V_4

10 19 24 5

4 11 18 25

6 2

7

PP

8 13

14

+3VS5

TPM_XOUT

R158 *10M_4

+5V

C437 *0.1U/16V_4

C236 *0.1U/16V_4

TPM_PP

TPM_XIN

6 5 4 3 2 1

CN8

SI..Add C610 for FR +5v bypass cap...11/25

+3V

R155 *4.7K/F_4

R150 *0_4

+5V

SATA HDD Connector

C657 10U/6.3V_Y6 CN25

+3V

R429

4.7K_4

Close EC

C671 *220P/50V_4

FAN

CN18 FAN Connect

1

5 2 3 46

5

6

SATA_TXP1[12] SATA_TXN1[12]

SATA_RXN1[12] SATA_RXP1[12]

ZERO_ODD_DP#[12]

CONN DIP SATA 22P 1R FR(P1.27,H3.65)

1

GND1

2

A1+

3

A1-

4

GND2

5

B1-

6

B1+

7

GND3

8

3.3V

9

3.3V

10

3.3V

11

GND

12

GND

13

GND

14

5V

15

5V

16

5V

17

GND

18

RSVD

19

GND

20

12V

21

12V

22

CGND1 CGND2

12V

23 24

Gnd : (5 Pin)

20141212ATWB HDD modify from H=7.5mm to H=9mm. ( JWV still keep original design for HDD H=7.5mm ) Footprint are different for HDD connector & can't co-layout. So separate schematic & PCB by TWB & JWV.

Bypass CAP close conn

C747 0.01U/50V_4 C746 0.01U/50V_4

C743 0.01U/50V_4 C742 0.01U/50V_4

+5V +5V_ODD

R540 *0_8/S

C740 *0.1U/16V_4

TP16

20150212A- Remove ZERO POWER CIRCUIT. HLDS GUB0N * DA : (MD pin) Keep DA pin to be pull-up for ZPO or external eject support. * DP : Keep DP pin to be open state in host side if no need HOT SWAP.

SATA_TXP0_C SATA_TXN0_C

SATA_RXN0_C SATA_RXP0_C

+3V

C755 10U/10V_8 C756 0.1U/16V_4

+5V

C468 *10U/10V_8 C482 *10U/6.3V_Y6 C485 4.7U/6.3V_6 C488 0.1U/16V_4

+3V

R172 *10K_4

Bypass CAP close conn

C762 0.01U/50V_4 C761 0.01U/50V_4

C760 0.01U/50V_4 C759 0.01U/50V_4

SATA_TXP14_C SATA_TXN14_C

SATA_RXN14_C SATA_RXP14_C

12

R546 1K_4

120 mils

C720 0.1U/16V_4

C726 0.1U/16V_4

C730 10U/6.3V_8

C723 0.1U/16V_4

C722 0.1U/16V_4

ODD_EJECT#_CN

SATA_TXP0 [12]

SATA_TXN0 [12]

SATA_RXN0 [12] SATA_RXP0 [12]

+3V: 2 A (4-Pin)

+5V: 2 A (4-Pin)

CN19

14 SATA ODD

S1

2

TXP

3

TXN

5

RXN

6

RXP

8

DP

9

+5V

10

+5V

11

MD

1

GND1

4

GND2

7

GND3

12

GND

13

GND

14

16

S7 P1

17

15

P6

SATA ODD CONNECTOR

14'' SATA ODD

1 1

JWV remove G-sensor/Touch Screen function.

A

B

Y2 *32.768KHz

1 2

C231 *12P/50V_4

C232 *12P/50V_4

+3V +3VPCU +3VS5 +5V +5V_ODD

C

+3V [2,4,10,11,12,13,14,15,16,17,18,19,21,22,24,25,26,27,28,29,30,31,34,35,36,42,44,45,46]

+3VPCU [6,13,30,32,34,35,37,38]

+3VS5 [4,10,15,16,27,30,35,36,38,40,41,44,47]

+5V [25,27,36,44]

+5V_ODD

D

Document Number

C

Date:

Document Number

Wednesday, July 29, 2015

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

CN-HDD/ODD/PWR/FAN/TPM

Sheet :

E

of

33 51

Rev.Size

3C

A

B

C

D

E

34

LED Status

2013/07/05 Reserve for BATTERY LED

MBATLED0#[35]

TWL 15" Left SW

JWL 14" Left SW

1 1

TWL 15" Right SW

JWL 14" Right SW

+3VSUS

R170

4.7K_4

TPCLK[35] TPDATA[35]

A

+3VPCU

R382 *10K_4

2

34

5

Q27A *2N7002KDW

R384 *0_4/S

SW3

3 4

5 6

sw-tme-533b-q-tr-6p

SW2

3 4

5 6

*sw-tme-533b-q-tr-6p

SW4

3 4

5 6

sw-tme-533b-q-tr-6p

SW1

3 4

5 6

*sw-tme-533b-q-tr-6p

R169

4.7K_4

L12 BLM15BB470SN1D L13 BLM15BB470SN1D

SMB_RUN_DAT[10,16,17,18,24]

SMB_RUN_CLK[10,16,17,18,24]

61

Q27B *2N7002KDW

+3V

R383 *10K_4

BATLOW#_L

1 2

Q17B 2N7002KDW

61

2

Dual

5

34

Q17A 2N7002KDW

BAT LED

LED2 3P WHITE LED

C607 *AVLC 5S_4

R585 1K_4

R584 1K_4

C241 10P/50V_4

C240 10P/50V_4

+3VSUS

R246

4.7K_4

C397 *10P/50V_4

21

25 mils

C398

0.1U/16V_4

+3VSUS

B

R387 330_6

C779

0.1U/16V_4

C778

0.1U/16V_4

TPCLK-1 TPDATA-1

R240

4.7K_4

C393 *10P/50V_4

TP_L

TP_R

TP_SMB_DATA TP_SMB_CLK

SATA_LED#[12]

+3VPCU

DEEP_PWRLED#[33]

CN5

50503-0080n-001-8p-l

DFFC08FR026

1 2 3 4 5 6 7 8

TOUCH PAD CONN

Touch Pad Connector

+3V +3VPCU +3VSUS

+3V [2,4,10,11,12,13,14,15,16,17,18,19,21,22,24,25,26,27,28,29,30,31,33,35,36,42,44,45,46]

+3VPCU [6,13,30,32,33,35,37,38]

+3VSUS [44]

C

SATA LED

C608 *AVLC 5S_4

PWR LED

C606 *AVLC 5S_4

21

LED3 3P WHITE LED

21

LED1 3P WHITE LED

1 2

R388 330_6

R386 330_6

MY[0..17][35] MX[0..7][35]

KEYBOARD PULL-UP

+3VPCU

MY13 MY12 MY3 MY6

+3VPCU

MY1 MY4 MY5 MY0 MY9

+3VPCU

D

RP14 *10P8R-8.2K

10

9 8 7 4

10

9 8 7 4

R431 *8.2K/F_4 R430 *8.2K/F_4

RP13 *10P8R-8.2K

1 2 3

56

1 2 3

56

20150216ACancel CAPSLED, MUTELED, WLAN ON/OFF control for meet K/B function & reduce EC GPIO.

MY5 MY6 MY3 MY7

MY8 MY9 MY10 MY11

MY1 MY2 MY4 MY0

MX4 MX6 MX3 MX2

+3V

+3VPCU

MY[0..17] MX[0..7]

MY14 MY11 MY10 MY15

MY2 MY7

MY8

MY16 MY17

C661 220P/50V_4 C669 220P/50V_4 C670 220P/50V_4 C667 220P/50V_4

C668 220P/50V_4 C647 220P/50V_4 C677 220P/50V_4 C676 220P/50V_4

C663 220P/50V_4 C665 220P/50V_4 C666 220P/50V_4 C651 220P/50V_4

C648 220P/50V_4 C646 220P/50V_4 C656 220P/50V_4 C653 220P/50V_4

KEYBOARD CONN

0503 : Change pin define and M/B keyboard connector follow R33

CN4 KB CONN

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

DFFC32FR025

196319-32021-3-32p-l

C645 220P/50V_4 C664 220P/50V_4 C649 220P/50V_4 C644 220P/50V_4

C672 220P/50V_4 C673 220P/50V_4 C675 220P/50V_4 C678 220P/50V_4

C680 220P/50V_4 C679 220P/50V_4

E

Document Number

C

Date:

Document Number

Wednesday, July 29, 2015

MX1 MX7 MX6 MY9 MX4 MX5 MY0 MX2 MX3 MY5 MY1 MX0 MY2 MY4 MY7 MY8 MY6 MY3 MY12 MY13 MY14 MY11 MY10 MY15 MY16 MY17

MX7 MX0 MX5 MX1

MY12 MY13 MY14 MY15

MY16 MY17

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

CN-LED/KB/TP Button

Sheet :

of

34 51

Rev.Size

3C

5

D D

+3V_EC

R436 *0_6/S

For EC power consumption measure.

C689 0.1U/16V_4

4

C674 0.1U/16V_4

C684 0.1U/16V_4

C196 0.1U/16V_4

C191 0.1U/16V_4

C195 0.1U/16V_4

C198 0.1U/16V_4

C686 1U/6.3V_4

C205

0.1U/16V_4

+3V_VSTBY

+3V_ECACC

L29 HCB1608KF-181T15_S0_6

C685 1000P/50V_4

L9 HCB1608KF-181T15_S0_6

3

R121 *0_6/S

For EC power consumption measure.

2

+3VPCU_EC

3

+1.0V

Q11 *2N7002K

R159

4.7K_4

R130

100K_4

C207

R120 10K_4

+3V_EC

+3VPCU_EC

EC_WRST

Q12 METR3904-G

1 3

2

Open Drain need PU

THRM_ALERT_HW#1

+3VPCU+3VPCU_EC+3V

EC_PWROK OVT_DETC

EC_WRST

D4 RB500V-40

21

1U/10V_4

R131

4.7K_4

Q9

2

METR3904-G

13

2

1

C208 220P/50V_4

1

35

PM_THRMTRIP# [2]

DGPU_OVT# [19]

DGPU_PWROK [12,21,46]

11

U23

LAD0[10,30,33] LAD1[10,30,33] LAD2[10,30,33] LAD3[10,30,33]

C C

CLK_24M_KBC[10]

R435 *10_4

C687 *10P/50V_4

For Touch-Pad

GPIO33_EC[11] RF_LINK#[30]

USBPW_ON#[27,32] PCH_SPI1_CLK_R[10]

B B

A A

PCH_SPI1_SO_R[10] PCH_SPI1_SI_R[10] PCH_SPI_CS0#_R[10] S5_ON[38]

PLTRST#[4,16,19,26,28,29,30,33] LFRAME#[10,30,33] PCIE_WAKE#[4,28,29,30] AC_PRESENT_EC [4]

EC_WRST

GPUT_CLK

LID_EC#

MAINON

BIOS_SPI_CLK BIOS_RD#

BIOS_WR# BIOS_CS# S5_ON

MY0[34] MY1[34] MY2[34] MY3[34] MY4[34] MY5[34] MY6[34] MY7[34] MY8[34] MY9[34] MY10[34] MY11[34] MY12[34] MY13[34] MY14[34] MY15[34] MX0[34] MX1[34] MX2[34] MX3[34] MX4[34] MX5[34] MX6[34] MX7[34]

ZERO_PWR_ODD

TP82

SERIRQ[10,33] SIO_EXT_SMI#[10] SIO_EXT_SCI#[14]

EC_RCIN#[10] GPUT_CLK[22]

BATSHIP[37] LID_EC#[33]

TPDATA[34] TPCLK[34]

DSWROK_EC[4] SLP_SUS#_EC[4] SLP_SUS_ON[15,40,41]

RSMRST#[4] MAINON[32,39,40,41,44]

D9 RB500V-40

R468 15/F_4

Close to BIOS

R467 15/F_4 R466 15/F_4 R465 15/F_4

5VS5_ON[38]

TP79

10

LAD0

9

LAD1

8

LAD2

7

LAD3

22

LPCRST#/WUI4/GPD2

13

LPCCLK

6

LFRAME#

17

LPCPD#/WUI6/GPE6

126

GA20/GPB5

5

SERIRQ

15

ECSMI#/GPD4

23

ECSCI#/GPD3

14

WRST#

4

KBRST#/GPB6

16

PWUREQ#/BBO/GPC7

113

CRX0/GPC0

123

TMA0/GPB2

86

PS2DAT0/TMB1/GPF1

85

PS2CLK0/TMB0/GPF0

88

PS2DAT1/RTS0#/GPF3

87

PS2CLK1/DTR0#/GPF2

90

PS2DAT2/WUI21/GPF5

89

PS2CLK2/WUI20/GPF4

119

DSR0#/GPG6

33

GINT/CTS0#/GPD5

108

RXD/SIN0/GPB0

109

TXD/SOUT0/GPB1

125

SSCE1#/GPG0

105

FSCK/GPG7

103

FMISO/GPG5

102

FMOSI/GPG4

101

FSCE#/GPG3

100

SSCE0#/GPG2

36

KSO0/PD0

37

KSO1/PD1

38

KSO2/PD2

39

KSO3/PD3

40

KSO4/PD4

41

KSO5/PD5

42

KSO6/PD6

43

KSO7/PD7

44

KSO8/ACK#

45

KSO9/BUSY

46

KSO10/PE

51

KSO11/ERR#

52

KSO12/SLCT

53

KSO13

54

KSO14

55

KSO15

58

KSI0/STB#

59

KSI1/AFD#

60

KSI2/INIT#

61

KSI3/SLIN#

62

KSI4

63

KSI5

64

KSI6

65

KSI7

128

GPJ6

2

GPJ7

AJ089870F01

IT8987E/BX

VCC

VSTBY26VSTBY50VSTBY92VSTBY

106

114

121

VSTBY

LPC

IT8987

PS/2

UART

FLASH

KBMX

RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7

CLOCK

VSS

VSS27VSS

1

49

74

127

AVCC

VSTBY_FSPI

L80HLAT/BAO/WUI24/GPE0

GPIO

CTX1/WUI18/GPH2/SMDAT3/ID2 CRX1/WUI17/GPH1/SMCLK3/ID1

CLKRUN#/WUI16/GPH0/ID0

SMCLK2/WUI22/GPF6/PECI

SM_BUS

PWM

WAKE UP

A/D D/A

VSS

AVSS

VSS

12

75

91

104

EGCLK/WUI27/GPE3 EGCS#/WUI26/GPE2

VSTBY

EGAD/WUI25/GPE1

KSO16/SMOSI/GPC3 KSO17/SMISO/GPC5

L80LLAT/WUI7/GPE7

DTR1/SBUSY/GPG1/ID7

HMOSIGPH6/ID6

HMISO/GPH5/ID5

HSCK/GPH4/ID4

HSCE#/WUI19/GPH3/ID3

GPH7

SMDAT2/WUI23/GPF7

SMCLK0/GPB3 SMDAT0/GPB4 SMCLK1/GPC1 SMDAT1/GPC2

PWM0/GPA0 PWM1/GPA1 PWM2/GPA2 PWM3/GPA3 PWM4/GPA4 PWM5/GPA5

PWM6/SSCK/GPA6

PWM7/GPA7

TACH0/GPD6

TACH1/TMA1/GPD7

DAC1/GPJ1 DAC0/GPJ0

TMR0/WUI2/GPC4 TMR1/WUI3/GPC6

PWRSW/GPE4 RI1#/WUI0/GPD0 RI2#/WUI1/GPD1

WUI5/GPE5

ADC0/GPI0 ADC1/GPI1 ADC2/GPI2

ADC3/GPI3 ADC4/WUI28/GPI4 ADC5/WUI29/GPI5 ADC6/WUI30/GPI6 ADC7/WUI31/GPI7

DAC5/RIG0#/GPJ5

DAC4/DCD0#/GPJ4

DAC3/GPJ3 DAC2/GPJ2

VCORE

84 83

VRON

82 56

57 19

CRY1

20

EC_PWROK

122 99 98

HWPG

97 96

DGPU_PROCHOT_EC#

95

MBDATA3

94

MBCLK3

93 3

117

EC_PECI_R

118

GPUT_DATA

110 111 115 116

24 25 28

AC_LED_ON#

29

TS_ON

30 31 32 34

CAPSLED#

47 48

77 76

120 124

107

NBSWON1#

18 21

DNBSWON#

35

SUSON

112

66 67 68 69 70

THRM_MOINTOR2

71

THRM_MOINTOR3

72 73

81 80

THRM_ALERT_HW#1

79

EC_PCIE_WAKE#

78

R433 *0_4/S

TP78 TP77

R474 43_4

TP73 TP72

TP136 TP71

TP70

TP74 TP75

TP76

EC_AOCS# [30]

VRON [42]

SUSACK#_EC [4]

MY16 [34] MY17 [34]

EC_PWROK [4,16]

PCI_SERR# [10]

DGPU_PROCHOT_EC# [22,45]

CLKRUN# [10,33]

SUSWARN#_EC [4]

EC_PECI [2]

GPUT_DATA [22]SUSB#[4,16]

MBCLK [37] MBDATA [37] MBCLK2 [10,24]

MBDATA2 [10,24]

PWR_LED# [33]

MBATLED0# [34]

FAN1_PWM [33]

VOLMUTE# [27]

FAN1SIG [33]

DGPU_PROCHOT# [45]

EC_USB_CTRL3 [32]

TEMP_MBAT [37]

NBSWON1# [33]

SUSC# [4,16]

SUSON [39,41,44]

LAN_POWER [44]

BAT_I [37]

EC_RTC_RST [13]

SYS_I [37]

AD_AIR [37]

THRM_MOINTOR1 [6]

EC_USB_CTRL2 [32]

EMU_LID [25]

EC_PCIE_WAKE# [30]

USB_CHARGER_ON [32]

R476 *0_4

C706

0.1U/16V_4

VC5 *AVLC 5S_4

H_PECI (50ohm) Route on microstrip only Spacing >18 mils Trace Length: 0.4~6.125 iches

PCH_SLP_S0_N [4,16] HWPG [4,16,38,39,40]

For Battery Charge For PCH & LVDS Converter

3

H_PROCHOT#_EC

+3VS5

R432 10K_4

20150511A-EC request to remove adapter type circuit & EC_RTC_RST change from PIN-31 to PIN-67.

2

Q10

R129

2N7002K

1

*10K_4

20150319A-Folllow X1B change PU from NU to stuff.

ACIN [37]

H_PROCHOT# [2,37,42]

C206 *47P/50V_4

DNBSWON# [4]

+3V_EC

+3VPCU_EC

R504 *10K_4 R434 4.7K_4 R475 4.7K_4 R463 4.7K_4 R472 4.7K_4 R473 4.7K_4

R469 10K_4 R470 4.7K_4TP80 R471 4.7K_4 R119 10K_4 R477 47K/F_4 R464 10K_4

THRM_MOINTOR1 THRM_MOINTOR2 THRM_MOINTOR3

0105 Add C680, C681 with 0.1uF

20150511A-THRM_MOINTOR2/3 are NC pin, C681 & C683 change to NU.

VRON

SUSON

MAINON

20150319A-Folllow X1B to add PD for signal blink issue.

GPIO33_EC GPUT_CLK GPUT_DATA DGPU_PROCHOT_EC# MBCLK2 MBDATA2

NBSWON1# MBCLK MBDATA EC_PCIE_WAKE# LID_EC# S5_ON

C682 0.1U/16V_4 C681 *0.1U/16V_4 C683 *0.1U/16V_4

R117 100K_4

R107 100K_4

R106 100K_4

L30 HCB1608KF-181T15_S0_6

IT8502_AGND

5

4

C688

0.1U/16V_4

+1.0V +3V +3V_EC +3VPCU +3VPCU_EC +3VS5

+1.0V [2,4,6,16,32,41]

+3V [2,4,10,11,12,13,14,15,16,17,18,19,21,22,24,25,26,27,28,29,30,31,33,34,36,42,44,45,46]

+3V_EC

+3VPCU [6,13,30,32,33,34,37,38]

+3VPCU_EC

+3VS5 [4,10,15,16,27,30,33,36,38,40,41,44,47]

C

Date:

3

2

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

EC (IT8987)

Wednesday, July 29, 2015

Sheet :

1

of

35 51

Rev.Size

3C

5

4

3

2

1

36

20140826A-EMI request.20140829A-EMI request.

EC23 0.01U/50V_4

+5V

EC44 0.01U/50V_4

+5V

EC64 0.01U/50V_4

D D

+5V +5V

+3V +3V +3V +3V +3V

+5VS5 +5VS5 +5VS5 +5VS5 +5VS5

EC34 0.01U/50V_4

EC6 0.01U/50V_4 EC22 0.01U/50V_4 EC39 0.01U/50V_4 EC37 0.01U/50V_4 EC50 0.01U/50V_4

EC7 0.01U/50V_4 EC24 0.01U/50V_4 EC43 0.01U/50V_4 EC66 0.01U/50V_4 EC57 0.01U/50V_4

+1.35V_GFX +1.35V_GFX +1.35V_GFX +1.35V_GFX +1.35V_GFX

+1.35VSUS +1.35VSUS +1.35VSUS +1.35VSUS

1 2

EC11 100P/50V_4

1 2 1 2

EC15 100P/50V_4

1 2

EC9 100P/50V_4

1 2

EC5 100P/50V_4

EC10 120P/50V_4 EC21 120P/50V_4 EC28 120P/50V_4 EC42 120P/50V_4

+VIN +VIN +VIN +VIN +VIN +VIN +VIN +VIN +VIN +VIN +VIN +VIN

+VIN +VIN +VIN +VIN +VIN +VIN +VIN +VIN +VIN +VIN +VIN +VIN +VIN +VIN

C237 *0.1U/25V_4 C435 *0.1U/25V_4 C12 0.1U/25V_4

C153 *0.1U/25V_4 C57 *0.1U/25V_4 C8 *0.1U/25V_4 C5 *0.1U/25V_4 C442 *0.1U/25V_4 C7 *0.1U/25V_4 C144 *0.1U/25V_4 C66 *0.1U/25V_4 C3 *0.1U/25V_4

C14 0.1U/25V_4 C161 0.1U/25V_4 C63 0.1U/25V_4 C4 0.1U/25V_4 C103 0.1U/25V_4 C145 0.1U/25V_4 C436 0.1U/25V_4 C163 0.1U/25V_4 C6 0.1U/25V_4 C65 0.1U/25V_4 C39 0.1U/25V_4 C16 0.1U/25V_4 C612 0.1U/25V_4 C162 0.1U/25V_4

+PRWSRC +PRWSRC +PRWSRC +PRWSRC

+1.35VSUS

+5VS5

+PRWSRC +PRWSRC

BATT+ BATT+ BATT+ BATT+

C13 0.1U/25V_4 C11 0.1U/25V_4C154 *0.1U/25V_4

C610 0.1U/25V_4EC17 100P/50V_4

C2 *0.1U/25V_4 C611 *0.1U/25V_4 C609 *150P/50V_4 C1 *150P/50V_4

C239 *0.1U/25V_4 C443 *0.1U/25V_4 C409 *0.1U/25V_4

C238 *0.1U/25V_4 C176 *0.1U/25V_4

C10 *0.1U/25V_4 C9 *0.1U/25V_4

EC19 0.01U/50V_4

+3VS5

EC56 0.01U/50V_4

+3VS5

EC35 0.01U/50V_4

+3VS5

C C

+1.35V_GFX +1.35VSUS +3V +3VS5 +5V +5VS5 +PRWSRC +VIN +VIN_VGACORE BATT+ +VIN_VCCGT

+1.35V_GFX [20,21,23,46]

+1.35VSUS [3,6,17,18,39,41,47]

+3V [2,4,10,11,12,13,14,15,16,17,18,19,21,22,24,25,26,27,28,29,30,31,33,34,35,42,44,45,46]

+3VS5 [4,10,15,16,27,30,33,35,38,40,41,44,47]

+5V [25,27,33,44]

+5VS5 [4,27,32,38,39,40,41,42,43,44,45,46,47]

+PRWSRC [37]

+VIN [25,37,38,39,40,42,43,45,46,47]

+VIN_VGACORE [45]

BATT+ [37]

+VIN_VCCGT [42]

Hole

CPU Backet

CPU BRACKET P/N : FBU86017010

B B

H9 *INTEL-BKT-SKL-NSTD

top

BRACKET

342

1

20141008A-EMI request for PV.

+VIN +VIN

+VIN_VGACORE +VIN_VGACORE

EC18 0.1U/25V_4 EC2 2200P/50V_4

EC16 0.1U/25V_4 EC12 2200P/50V_4

20150520A-EMI request for PV.

+VIN_VCCGT +VIN_VCCGT

Thermal Module

H7 *O-U6X-2

top

NO-NUT

1

EC80 0.1U/25V_4 EC81 2200P/50V_4

H2 *H-C315D102P2

1

H6 *H-C315D118P2

1

H1 *H-C236D118P2

toptop

1

FIX-HOLESCREW

H3 *H-C315D118P2

toptop

1

SCREWSCREW

toptop toptop bot

SCREWSCREW SCREWSCREW

H10 *H-c394I198D118P2

toptop top

1

SCREWSCREW SCREW

H13 *H-C236D118P2

1

H17 *H-C394D118P2

1

C

Date:

20150521A-Change H10 footprinter for UART routing.

PAD2

PAD1

1

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

EMI / SCREW HOLE

Wednesday, July 29, 2015

Sheet :

1

36 51

PAD3

1

of

Rev.Size

3C

GPU Backet

GPU BRACKET P/N : FBR62021010

NGFF NUT P/N : MBY01001010

A A

FAN NUT P/N : MBFF4001010

5

H4 *H-TC279BC216D141P2

H5 *H-TC279BC216D141P2

H8 *H-TC279BC216D141P2

top top top

BRACKET BRACKET BRACKET

1

NGFF WLAN 2230 NGFF SSD 2240 for JWL 14" NGFF SSD 2280 for TWL 15"

H21 H-TC197BC157D106P2 for NGFF WLAN

bot bot bot

NUT-BOT NUT-BOT NUT-BOT

1

H19 H-TC236BC315D145P2 for FAN

bot

1

NUT-BOT NUT-BOT

H22 H-TC197BC157D106P2 for JWL NGFF SSD

1

H20 H-TC236BC315D145P2 for FAN

top

1

4

H23 H-TC197BC157D106P2 for TWL NGFF SSD

1

3

H11 *H-C394D118P2

1

H14 *H-C197D118P2

top top

1

FIX-HOLE SCREW

??

H16 *H-C394D118P2

1

2

H18 *H-C394D118P2

1

H24 *SPAD-C236NP

bot

1

H25 *SPAD-C197NP

1

H12 *H-C394D118P2

1

H15 *H-C236D98P2

1

5

4

3

2

1

Do Not add test pad on BATDIS_G signal

37

follow TWB location and footprint

+BATCHG

PC191

0.1U/25V_4

EC69 *1U/25V_4

PC205

3.3uH/6A(PCMC063T-3R3MN)

PR45

2.2_6

PC26 2200P/50V_4

EC70 *1U/25V_4

+VIN

PC211

4.7U/25V_8 2200P/50V_4

PL13

PV Change

CSOP CSON

follow TWB location and footprint

BATTE RY 8P 1R MR(P2.0,H5.2)

BATT+ SMD

SMC

B_TEMP_MBAT

5

PR214

For EMI

0.1U/25V_4

PQ16 FDMS7698

D

G

EC68 *1U/25V_4

PQ15

EMB20N03V

PQ12

EMB20N03V

PC32

PC31

+BAT_DIS

3

S

2 1

4

+PRWSRC

PC30

0.1U/25V_4

PC214

0.01U/50V_4

EC67 *1U/25V_4

678

35241

678

35241

PC212 2200P/50V_4

BATDIS_G

PR9 *430K/F_4

PR10 82K/F_4

H_PROCHOT#[2,35,42]

+3VPCU

PC258

PC254

PQ14 AP0203GMT-HF

3

D

S

5

2 1

G

4

+VAD

ACDET=14.985V

MBDATA BQDATA MBCLK BQCLK

PR49 *100K/F_4

PV Change

PR52 *100K/F_4

PR19 10/F_4

PR21 10/F_4

PC207

0.1U/50V_6

PR11

4.02K/F_4

PR17 10/F_8

PR36 *0_4/S PR31 *0_4/S

REGN6V

ACIN[35]

PC13 100P/50V_4

PC15 100P/50V_4

+PRWSRC +VIN

PC1

1U/25V_6

PR34 *0_4/S

100K/F_4

PC14

PR42 *0_4/S

PR28

PR183

PR12

4.02K/F_4

BQCMSRC

BQACDRV

BQVCC

BQACDET

PC3 *1000P/50V_4

BQPROCHOT BQBATPRES

BQTB_STAT

ACIN

BQIADP

BQIBAT

+3VPCU

1U/25V_6

PU1

3

CMSRC

4

ACDRV

28

VCC

6

ACDET

11

SDA

12

SCL

10

PROCHOT

15

BATPRES

16

TB_STAT

5

ACOK

7

IADP

8

IDCHG

PR53 100K/F_4

PR2

PR207

RC1206-R010

PR206 *0_2/S

*0_4/S

BQACP_N

PC4

0.1U/25V_4 PR13

BQACP

2

ACP

*0_4/S

BQACN_N

BQACN

1

21

PR210 *0_2/S

0.1U/25V_4

ACN

BQ24780SRUYR

20141218 updated

BATSRC

BATDRV

CMPOUT

ILIM

CMPIN

PMON

9

14

21

BQILIM

PR43

43.2K/F_4

13

PR35 *0_2/S

38

PR26 *0_4/P

PR Change

PD3

*P4SMAFJ20A

2 1

Place this ZVS close to Far-Far away +VIN

PC5

PV Change

REGN

HIDRV

BTST

PHASE

LODRV

GND PAD

SRP

SRN

PAD PAD PAD PAD PAD PAD

PAD36PAD37PAD

REGN6V

24

26

25

27

23 22 29

17

20

19

18 30 31 32 33 34 35

PD2

*PDZ8.2B

PC21

2.2U/10V_6

BQHIDRV

PR25

BQB_2 BQB_1

BQPHASE

BQLODRV

BQBATSRC

BQSRP

BQSRN

BQBATDRV

PC18 *100P/50V_4

BQBATDRV

PR Change

21

PC16

0_6

PR46 10/F_6

0.047U/25V_4

PR Change

PR48 0_6

PR47 0_6

PR Change

PMON [42]

4.02K/F_4

DC_JACK DIP

D D

CN16

1 2

3 4

50300-00441-001-4p-l

45W/ 65W

+VA_AC +VA

PL10 *0_8/S

PL9 *0_8/S

PC181

0.1U/25V_4

PV2 Change

+VAD

4

PR184 220K_4 PR186

220K_4

C C

B B

A A

+3VPCU [6,13,30,32,33,34,35,38] +5VPCU

2 1

AD_AIR[35]

PC261

0.1U/16V_4

Place this cap close to EC

VIDCHG = 8 or 16 × (VSRN – VSRP)

PQ13

6 7 8

PC206

0.1U/25V_4

PQ2

Q2

Q1

MMDT2907A

+VA_AIR

EMB20P03V

3 65

15 2 3

4

PR23

IDEA_G

1M_4

PR14

1K_6

+VA +VAD

21

PD1

1N4448WS-7-F

PR7

PV Change

75K/F_4

PR6

12.4K/F_4

+VAD

PC202

Place this ZVS close to Diode away +VIN

0.1U/25V_4

+VA

2 1

PR185 1M_4

PR8 430K/F_4

PD9

P4SMAFJ20A

SYS_I[35]

0.01U/50V_4

Place this cap close to EC

BAT_I[35]

0.01U/50V_4

Place this cap close to EC

PL8 *0_8/S

PL11 *0_8/S

PC210

1000P/50V_4

+BAT_DIS

15"

1 2 3 4

5 6 7 8

BATT+

PC192

0.1U/25V_4

MBDATA[35]

MBCLK[35]

*100P/50V_4

PC213

0.1U/25V_4

CN14

1 2 3 4

5 6 7

10

8

9

follow TWB location and footprint

PR194 330_4

PC188

*100P/50V_4

PD6

2 1

PDZ5.6B

PC189

PD7 PDZ5.6B

PR195 330_4

For ISN

EC3

10U/25V_8

PR203

RC1206-R010

PR202

*0_2/S

10 9

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

EC71

10U/25V_8

PR201 *0_2/S

EC1

10U/25V_8

21

BATSHIP[35]

SMD SMC

EC4

PC197

10U/25V_8

BATT+

B_TEMP_MBAT

PC187

0.01U/50V_4

10U/25V_8

PR193 200K/J_4

PR192 1K/F_4

PC198

10U/25V_8

2

14"

CN15

*MPCRA-08MLBS1ZZ4H4

1

2

3

4

5

6

7

10

8

9

+3VPCU

TEMP_MBAT [35]

PC186

0.01U/50V_4

Place this cap close to EC

+BATCHG

PC190

PR Change

+BATCHG

3

1

2 1

0.1U/25V_4

PR Change

PR27 *470_8

PQ1 *2N7002K

PD8

10 9

PD11 SX34F

*RB500V-40

PROJECT : TWL & JWL ( MB )

Document Number

Charger (BQ24780S)_65W

Custom

Date:

5

4

3

2

Charger (BQ24780S)_65W

Wednesday, July 29, 2015

Sheet :

1

of

37 51

Rev.Size

3C

5

DC/DC +3VS5/+5VS5

4

3

2

1

38

Do Not add test pad on VCC & LDO pin

+3VPCU

D D

PR148 10K/F_4

PR150 *0_4/S

PC275

2.2U/6.3V_4

SY8208BPGHWPG

+3VS5

HWPG[4,16,35,39,40]

PV Change

S5_ON SY8208BEN

+3VPCU

PD4

C C

*UDZVTE-173.6B

PR152

*4.99K/F_4

PR154

*4.02K/F_4

2 1

2

SY8208CEN

PQ11 *METR3904-G

1 3

+VIN

PR151 *0_4/S

PR145 499K/F_4

PR153 1M_4

PR146 150K/F_4

PC283 *0.1U/16V_4

PU17

5

2

1

7

SY8208B

LDO

PGOOD

EN1

EN2

VIN

GND

BST

SW

VOUT

FB

8

9

6

SY8208BBST

10

SY8208BSW

4

3

PC138

0.1U/25V_4

SY8208BVOUT

SY8208BFBSY8208BLDOEN

PC278

4.7U/25V_8

PR149

0_6

+VIN_3VS5

PC139

4.7U/25V_8

SY8208BBST_S

PR262

1K/F_4

PC137

2200P/50V_4

PC141

0.1U/25V_4

PL7 *0_8/S

+VIN

PC135

0.1U/25V_4

PL24

2.2uH/8A(PCMC063T-2R2MN)

PR157 *2.2_6

PC147 *2200P/50V_4

EC8

*1000P/50V_4

PR164 *0_2/S

PC277

0.01U/50V_4

+3.3VS5_S

12

+

PC292

PC161

0.1U/16V_4

*150U/6.3V_5X3.8 ESR20

+3.3 Volt +/- 5% TDC:8A EDP:9A

+3VS5

PJP3 *POWER_JP/S

1 2

PC157

PC150

*22U/6.3V_8

PC149

22U/6.3V_8

PC154

22U/6.3V_8

+3VS5 [4,10,15,16,27,30,33,35,36,40,41,44,47] +5VS5 [4,27,32,36,39,40,41,42,43,44,45,46,47]

2014/12/18 updated

Do Not add test pad on VCC & LDO pin

+5VPCU

PC284

2.2U/6.3V_4

B B

PV Change

PR160 1K/F_4

5VS5_ON[35]

S5_ON[35]

USB Charge Support

A A

VINE (No support)

ENVY (Support)

Rb

Ra

PR159 *1K/F_4

Stuff NA

NA Stuff

PR158 *0_4/S

PV2 Change

PC145 PR264 1M_4

RbRa

*0.1U/16V_4

2.2U/6.3V_4

SY8208CPGHWPG

SY8208CEN

PC286

Do Not add test pad on VCC & LDO pin

PU18

7

2

1

5

SY8208C

LDO

PGOOD

EN

VCC

VIN

GND

BST

SW

VOUT

8

9

6

SY8208CBST

10

SY8208CSW

4

SY8208CVOUT

3

FB

SY8208CFB

PC288

PR156

0_6

0.1U/25V_4

SY8208CBST_S

PC276

PR263 1K/F_4

4.7U/25V_8

+VIN_5VS5

PC281

4.7U/25V_8

PC146

0.1U/25V_4

PL22 *0_8/S

PC285

2200P/50V_4

PR155 *2.2_6

PC142 *2200P/50V_4

+VIN

PC280

0.1U/25V_4

PL26

2.2uH/8A(PCMC063T-2R2MN)

PR167 *0_2/S

PC287

6800P/50V_4

+5VS5_S

12

+

PC291

*150U/6.3V_5X3.8 ESR20

PC159

0.1U/16V_4

+5 Volt +/- 5% TDC:8A EDP:9A

+5VS5

PJP4 *POWER_JP/S

1 2

PC155

PC167

*22U/6.3V_8

PC168

22U/6.3V_8

PC158

22U/6.3V_8

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

3/5VS5 (SY8208B/SY8208C)

Custom

Date:

5

4

3

2

3/5VS5 (SY8208B/SY8208C)

Wednesday, July 29, 2015

Sheet :

1

of

38 51

Rev.Size

3C

1

2

3

4

5

39

PR162

HWPG[4,16,35,38,40]

A A

DDR_VTT_PG_CTRL_R[18]

( 3mA )

B B

DDR_VTTREF

SUSON[35,41,44]

MAINON[32,35,40,41,44]

PV Change

+0.75V_DDR_VTT

PR173

100/F_4

PC174

0.1U/16V_4

PR176 *0_4

PR172 *0_4/S

*0_4/S PR168

*0_4/S

+0.65V_DDR_VTT

PC170 10U/6.3V_6

PC173

0.033U/10V_4

+1.35VSUS

PC163 *0.1U/16V_4

PV Change

PC160 *0.1U/16V_4

20

VTT

2

VTTSNS

1

VTTGND

4

VTTREF

19

VLDOIN

PC169

*10U/6.3V_6

+5VS5

PR175 *0_2/S

PR166 *0_2/S

1P35V_S5

1P35V_S3

7

S58S3

PU11

RT8231BGQW

LPMB

VID

3

11

1P35V_VID

1P35V_PGOOD

10

14

PGOOD

PGND

Ilimit=10.5A

PR165 243K/F_4

1P35V_TON

1P35V_CS

13

9

CS

TON

VDDQ

FB

5

6

1P35V_FB

1P35V_VDDQ

PR174

10.2K/F_4

PR178 10K/F_4

21

UGATE

BOOT1

PHASE

LGATE

PAD

VDD

2014/12/18 updated

Fsw=500KHz

PR163 499K/F_4

17

1P35V_UGATE

18

1P35V_BOOT

16

1P35V_PHASE

15

1P35V_LGATE

12

PC156 1U/6.3V_4

PR171

2.2_6

+5VS5

PC162

0.1U/25V_4

PQ31

EMB20N03V

PQ32

MDV1595SURH

Rds(on) 13m ohm

678

35241

678

35241

PC152

0.1U/25V_4

PR161

2.2_6

PC153 2200P/50V_4

PC290

1uH/11A(PCMC063T-1R0MN)

PC289

4.7U/25V_8

PL25

PC151

4.7U/25V_8 2200P/50V_4

PV Change

PL23 *0_8/S

+VIN+VIN_DDR

+1.35V +/- 5% Countinue current:6A

PC282

Peak current:8A OCP minimum:10.5A

PC143

22U/6.3V_8

+1.35VSUS

1 2

PC148

PJP2 *POWER_JP/S

PC144

22U/6.3V_8

20150525 updated

12

+

PC140

*22U/6.3V_8

PC279

*22U/6.3V_8

*330U/2.5V_3528

0.1U/25V_4

+1.35VSUS_S

PR147 *0_2/S

PC136

0.1U/16V_4

C C

+VIN [25,36,37,38,40,42,43,45,46,47]

D D

Custom

Date:

1

2

3

4

+5VS5 [4,27,32,36,38,40,41,42,43,44,45,46,47]

+0.65V_DDR_VTT [17,18]

+1.35VSUS [3,6,17,18,36,41,47]

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

DDR3 (RT8231B)

Wednesday, July 29, 2015

Sheet :

5

of

39 51

Rev.Size

3C

5

+VIN [25,36,37,38,39,42,43,45,46,47] +5VS5 [4,27,32,36,38,39,41,42,43,44,45,46,47] +3VS5 [4,10,15,16,27,30,33,35,36,38,41,44,47] +1.8V_DEEP_SUS [9,15] +1.0V_DEEP_SUS [9,13,15,16,41]

4

3

2

1

40

D D

PV Change

+5VS5

PC260 1U/6.3V_4

PV Change

HWPG[4,16,35,38,39]

SLP_SUS_ON[15,35,40,41]

C C

HWPG

PR94 *0_4/S

PR96 *0_4/S

PR232 *0_2/S

PR85

*0_4

1237PGPCH

1237PFMPCH

1237ENPCH

PC257 *0.1U/16V_4

1237SSPCH

PC78

0.1U/16V_4

PU16

7

NC

21

VCC

1

PGOOD

3

PFM

2

EN

23

SS

AOZ1267QI-3

PR227

84.5K/F_4

6

TON

BST

PGND PGND PGND PGND PGND AGND

IN IN IN

LX LX LX LX LX

FB

8 9 22

20

1237BSTPCH

10

1237LX

11 16 17 18

12 13 14 15 19 4

5

1237FBPCH

R2

PC246

PR97

0_6

PR88

2.61K/F_4

PR231 10K/F_4

PC238

0.1U/25V_4

4.7U/25V_8

1237BSTPCH_S

R1

1237FBPCH_S

Vout1=(1+R1/R2)*0.8

+VIN_1.0V +VIN

PC242

4.7U/25V_8

PC79

0.1U/25V_4

PL16 *0_8/S

PC241

2200P/50V_4

PR241 *2.2_6

PC255 *2200P/50V_4

PC236

0.1U/25V_4

PL19

1uH/11A (PCMC063T-1R0MN)

+1.0VS5_S2

PR91 *0_2/S

(V1.00A+V1.00_MODPHY+VccPRIM_CORE)

+1.0VS5 Volt +/- 5%

Countinue current:6A

Peak current:9A

+1.0V_DEEP_SUS

PJP1 *POWER_JP/S

1 2

PC271

0.1U/16V_4

PC100

22U/6.3V_8

PC101

22U/6.3V_8

PC85

PC95

22U/6.3V_8

PV ChangePV Change

+

PC268

*220u/2V_7343

PR133

+3VS5

B B

PV Change

PR134

HWPG

SLP_SUS_ON[15,35,40,41]

*0_4/S

PR138 *0_4/S

PC122

0.1U/16V_4

*0_6/S

4

PU9

5

PG

G5719CTB1U

1

EN

6

PV2 Change

R2

VIN

GND

FB

PR135 10K/F_4

PC116

4.7U/6.3V_6

3

LX

2

PR136 20K/F_4

R1

PL6

1uH/2.6A_2520

PR141

*0_2/S

+1.8V +/- 5% TDC:1A EDP:2A

+1.8V_DEEP_SUS

PC132

0.1U/16V_4

PC129 10U/6.3V_6

PV Change

MAINON[32,35,39,41,44]

PC117

1U/6.3V_4

PR132 *0_4/S

PC118

*0.1U/16V_4

+5VS5

PU8

1

VBIAS

2

GND

3

EN

G9183-12TP1U

+1.8V_DEEP_SUS

6

VIN

5

VOUT

4

VADJ

PC128

4.7U/6.3V_4

R1

R2

+1.5V Volt +/- 5% Countinue current:150mA

+1.5V

PC127

PR142

88.7K/F_4

Vout=0.8(1+R1/R2)

PR140 100K/F_4

4.7U/6.3V_4

VO=(0.6(R1+R2)/R2)

A A

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

+1.0/+1.8V_DEEP_SUS

Custom

Date:

5

4

3

2

+1.0/+1.8V_DEEP_SUS

Wednesday, July 29, 2015

Sheet :

1

of

40 51

Rev.Size

3C

5

+1.0V_DEEP_SUS [9,13,15,16,40,41] +1.0V [2,4,6,16,32,35,41] +5VS5 [4,27,32,36,38,39,40,41,42,43,44,45,46,47] +VCCSTPLL [2,4,5,6,9,41,42] +VCCIO [2,6,16,41]

+3VS5

PR84

D D

SUSON[35,39,41,44]

SLP_SUS_ON[15,35,40,41]

*0_4

PR74 *0_4

1 2

3 5

4

+VCCSTG_ON

PU4 *17SZ08DFT2G

PR66 *47K/F_4

PC55

*1000P/50V_4

4

PC232

0.1U/16V_4

*DMG3414U-7

+1.0V_DEEP_SUS

2

PQ25

+VCCSTPLL

20150106 updated

3

1

PC247

0.1U/16V_4

PV Change

PR223 *0_4/S

<= 65usec full load ready

TDC:0.16A

PR228 *0_6/S

PC248 *10U/6.3V_6

+VCCSTPLL

3

2

1

41

<= 65usec full

+1.0V_DEEP_SUS

PC231 1U/6.3V_4

+3VS5

PC229

PV Update

PR266

MAINON[32,35,39,40,41,44]

0_4

PV Update

PR267

0_4

0.1U/16V_4

PU15 AOZ1335DI

1

VIN

2

VIN

9

VIN

3

VBIAS

4

ON

PC228 *0.1U/16V_4

VOUT

GND

8

5

PC240

0.1U/16V_4

PC245 *10U/6.3V_6

PR Update

load ready

TDC:0.04A

PV Update

PR224 0_6

PR226 *0_6/S

+1.0V

TDC:3A

+VCCIO

+1.0V_MODERN

PR265

*0_6

PV Update

+5VS5

PR124

C C

34

5

PQ10A *2N7002KDW

*1M_4

PR125 *2M_4

PR106 *22_8

61

2

PQ10B *2N7002KDW

PR Update

PR268 *0_4

Rd

PR Update

MODERNSTB_EN

Support Modern standby mode

1. Remove Ra/Rc & stuff Rb/Rd

2. stuff block C & D

Reserve for Modern StandBy

PR Update

Block C

PR282

MAINON[32,35,39,40,41,44]

Reserve for Modern StandBy

Block D

B B

MAINON[32,35,39,40,41,44]

A A

5

PV Update

PR273 *47K/F_4

PC299

*1000P/50V_4

*2N7002KDW

+1.0V_DEEP_SUS

2

PQ36B

4

2

61

3

1

+5VS5

PC296

0.1U/16V_4

PQ34

*DMG3414U-7

PC300 *0.1U/16V_4

+1.0V_MODERN

PR280

*1M_4

5

PR281 *2M_4

PR275 *0_6/S

PC301 *10U/6.3V_6

PR278 *22_8

34

PQ36A

*2N7002KDW

<= 65usec full load ready

TDC:0.3A

+1.0V_MODERN

SUSON[35,39,41,44]

SLP_SUS_ON[15,35,40,41]

PCH_SLP_S0_EC[41]

Reserve for debug

+1.0V [2,4,6,16,32,35,41] +3VS5 [4,10,15,16,27,30,33,35,36,38,40,44,47] +5VS5 [4,27,32,36,38,39,40,41,42,43,44,45,46,47] +VCCIO [2,6,16,41] +1.35VSUS [3,6,17,18,36,39,47] +VCCSTPLL [2,4,5,6,9,41,42] +1.0V_MODERN +1.0V_DEEP_SUS [9,13,15,16,40,41] +1.35V_VCCPLL_OC [6]

3

*0_4

PR270 0_4

PR272 0_4

PR283 *0_4

+3VS5

+1.35VSUS

PC293

0.1U/16V_4

1 2

3 5

PCH_SLP_S0_EC[41]

4

PU19

MC74VHC1G08DFT2G

PR271 47K/F_4

PR269 *47K/F_4

PC295

*1000P/50V_4

2

PR Update

2

PQ35B

*2N7002KDW

2

PC294

3

0.1U/16V_4

PQ33

DMG3414U-7

1

PC297

0.1U/16V_4

+5VS5

61

Custom

Date:

Wednesday, July 29, 2015

<= 65usec full load ready

TDC:0.26A

PR274 *0_6/S

PC298 *10U/6.3V_6

+1.35V_VCCPLL_OC

PR277

*1M_4

5

PR279 *2M_4

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

+1.0V/+VCCSTPLL

+1.35V_VCCPLL_OC

PR Update

PR276 *22_8

34

PQ35A

*2N7002KDW

Sheet :

1

of

41 51

Rev.Size

3C

1

PC62

1000P/50V_4

PC61

1000P/50V_4

+VCCSTPLL

+VCC_CORE

VCC_SENSE[5] VSS_SENSE[5]

PR127

100/F_4

PR126

100/F_4

PR65 *0_4/S

PR64 *0_4/S

PV Change

A A

PR71

100/F_4

PR70 *110/F_4

PR69

45.3/F_4

PR72 *75/F_4

VR_SVID_DATA

VR_SVID_ALERT#

VR_SVID_CLK

H_PROCHOT#

PV Change

PR100

+VCCSA

VCCSA_SENSE[6] VSSSA_SENSE[6]

B B

C C

Place close to VCCSA Inductor

SWN_SA[43]

H_PROCHOT#[2,35,37]

VR_SVID_DATA[5]

VR_SVID_ALERT#[5]

VR_SVID_CLK[5]

PR260

100/F_4

PR261

100/F_4

PR92

14K/F_4

PR89

7.5K/F_4

PR95 1K/F_4

PV2 Change

PWM_SA[43]

DRON[43]

+VIN_VCC_CORE

IMVP_PWRGD

VRON[35] PMON[37]

CSN_SA[43]

PV2 Change

+VCCGT

VCCGT_SENSE[7] VSSGT_SENSE[7]

TSENSE_GT TSENSE_CORE

PR120

PV Change PV Change

D D

*0_4/S

PR121

15K/F_4

1

*0_4/S

PC80

1000P/50V_4

PR98 *0_4/S

1 2

PR256 100K/F_4 NTC

PC69

0.022U/25V_4

PC75 180P/50V_4

PC72

0.01U/50V_4 PR236 105K/F_4

PR67 *0_4/S PR68 51.1K/F_4 PR76 *0_4/S

PR80 75/F_4 PR79 10/F_4 PR78 0_4 PR77 49.9/F_4 PR114 1K/F_4

PR86 10K/F_4

+3V

PR105 19.6K/F_4 PC83 *100P/50V_4

PR257

100/F_4

PR259

100/F_4

PR229

1 2

100K/F_4 NTC

place close to GT MOSFET

PC57

0.1U/16V_4

PV2 Change

PC82

1000P/50V_4

PR101

2.61K/F_4

PR99

1K/F_4

PC76

1000P/50V_4

PC70

*390P/50V_4

PR243 34K/F_4

PC262 1000P/50V_4

PC259 470P/50V_4

PV Change PV Change

PV Change

PR110 *0_4/S

PR112 *0_4/S

PV Change

PR233 *0_4/S

PR230

15K/F_4

PC253

470P/50V_4

VSP_SA VSN_SA CSN_SA CSP_SA ILIM_SA COMP_SA

IOUT_SA

VR_HOT# SDIO ALERT# SCLK VRMP

PC92

0.01U/50V_4

PR87 *0_4/S PR75 *0_4/S PR108 *0_4/S

PC89

1000P/50V_4

PR237

1 2

100K/F_4 NTC

place close to VCORE MOSFET

PR225 1K/F_4

PC249 15P/50V_4

PV2 Change

PR235 140K/F_4

IOUT_CORE

49

VSP_1b

48

VSN_1b

45

CSN_1b

44

CSP_1b

46

ILIM_1b

47

COMP_1b

43

IOUT_1b

40

PWM/ADDR_VBOOT

39

DRON

35

VR_HOT#

36

SDIO

37

ALERT#

38

SCLK

12

VRMP

PR111 1K/F_4

PC90

2200P/50V_4

PV2 Change

1000P/50V_4

PC252 1000P/50V_4

34

IOUT_1a

VR_RDY42EN

41

VR_EN

VR_RDY

PC264

0.1U/16V_4

2

PR83

2K/F_4

PR82

5.23K/F_4

PR81

1K/F_4

PC65

PC250

0.01U/50V_4

PC256 0.1U/16V_4

PR234 63.4K/F_4

VSP_CORE

VSN_CORE

COMP_CORE

TSENSE_CORE

ILIM_CORE

27

31

ILIM_1a

50

29

28

30

VSP_1a

VSN_1a

COMP_1a

TSENSE_1ph

PU6

NCP81206

VSP_2ph

PSYS

PR248 28K/F_4

49.9/F_4

PR118 1K/F_4 PR247 100K/F_4

TSENSE_2ph

11

TSENSE_GT

PR113

51

VSP_GT

VSN_2ph

1

52

VSN_GT

PC98

330P/50V_4

IOUT_GT

program IccMax_2ph

2

3

Place close to

12

PR240 11K/F_4

HG_GT1

15

HG1

BST1

SW1

LG1/ROSC

LG3/ICCMAX_1b

HG2

BST2

SW2

CSP1_2ph

CSREF_2ph

CSP2_2ph

PVCC

EPAD

VCC

53

13

PR254

PC266

1U/6.3V_4

2.2_6

VCORE Inductor

14K/F_4

PR63

SWN_CORE

7.5K/F_4 PC68

0.22U/25V_6

14

BST_GT1

16

SW_GT1

0.22U/25V_6

17

LG_GT1

21 22 20 19

LG_GT2

10

CSP_GT1

8

CSREF_GT

9

CSP_GT2

7

CSSUM_GT

18

+5VS5

PC263

2.2U/6.3V_4

PR93

1_6

PR107

1_6

PC86

PR246

14K/F_4

PR242

22.6K/F_4

+5VS5

3

HG_CORE_L

FDMS7698

PQ9

FDMS0308AS

HG_GT1_L

PV Change

IccMax=28A

PV Change

PC87

0.01U/50V_4

PR252 *0_4/S

PV Change

PR249

PC66

CSP_CORE

CSN_CORE

33

32

CSP_1a

CSN_1a

DIFFOUT_2ph/IccMax_2ph2FB_2ph

IOUT_2ph

DIFFOUT_GT

PC265 470P/50V_4

100K/F_4 NTC PC64

0.033U/10V_4

0.018U/16V_4

SW_CORE

BST_CORE

HG_CORE

25

24

26

HG3

SW3

BST3

LG2/ICCMAX_1a

ILIM_2ph5CSCOMP_2ph

COMP_2ph

3

4

ILIM_GT

COMP_GT

FB_GT

PR109

14.3K/F_4

PC96 15P/50V_4

PR119 2K/F_4

LG_CORE

23

CSSUM_2ph

6

CSCOMP_GT

PC99

2200P/50V_4

PQ28

HG_GT1_L

SW_GT1

LG_GT1

PR116

7.15K/F_4

PC88

0.047U/25V_4

+VIN_VCC_CORE

5

D

G

4

S

213

5

D

G

S

213

PQ26

FDMS3664S

PQ8

*FDMS3664S

SWN_GT1

PR115 10/F_4

PC53

4.7U/25V_8

DEL PQ21 (20141216)

4

PQ30

FDMS0308AS

1

2

D1

G1

S1/D2

9

G2

8

1

G1

S1/D2

9

G2

8

CSN_GT1

+VIN_VCCGT

S2

7

6

2

D1

S2

7

6

PR122 34K/F_4

PC91 1800P/50V_4

D1

S2

5

D1

S2

5

PC237

4.7U/25V_8

5

G

213

PV Change

PV2 Change

4

PC233

4.7U/25V_8

PR250

2.2_6

D

S

PC267 2200P/50V_4

PV Change

4.7U/25V_8

PR123

165K/F_4

PC97 *390P/50V_4

4

PC235

4.7U/25V_8

PC63

SW_GT1

PR103

2.2_6

PC81 2200P/50V_4

PL4 *0_8/S

PC52

0.15uH/40A(PCMB104T-R15MS0R487)

PR117 75K/F_4

PC60

*4.7U/25V_8

DCR=0.48m ohm

PR245 *0_2/S

PC67

4.7U/25V_8

DCR=0.48m ohm

PR238 *0_2/S

Place close to GT1 Inductor

1 2

PC56 2200P/50V_4

0.1U/25V_4

PL21

PR258 *0_2/S

CSN_CORE SWN_CORE

PC234

PL18

Watt Resistor(PR105)

90 22.1K

65 30.9K

40

PR253

PC71

*4.7U/25V_8

skylake Psys setting (NCP81206) table

100K/F_4 NTC

0.1U/25V_4

PR251 *0_2/S

CSN_GT1 SWN_GT1

Custom

Date:

+VIN

PC51

0.1U/25V_4PR73

12

+

PC272 390U/2.5V_5X5.8ESR10

PL5 *0_8/S

PC73

2200P/50V_4

12

+

PC274 390U/2.5V_5X5.8ESR10

49.9K CS34992FB10

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

Document Number

CPU VR IC (NCP81206)

Wednesday, July 29, 2015

PC54

0.1U/25V_4

part number

CS32212FB12

CS33092FB06

PROJECT : TWL & JWL ( MB )

5

+VCC_CORE

TDC=21[A]

IccMax=28[A]

+VIN+VIN_VCCGT

12

For Acoustic

+

12

+

PC208

*100U/25V

12

PC273 390U/2.5V_5X5.8ESR10

Sheet :

5

42

+VCC_CORE

+

PC104 *220u/2V_7343

+VCCGT

PC239

TDC=18[A]

IccMax=31[A]

100U/25V

+VCCGT

+

of

42 51

PC93 *220u/2V_7343

Rev.Size

3C

1

2

3

4

5

43

A A

+VIN_VCCSA +VIN

PC244

678

VCCSA

PU5

+5VS5

PR102 *0_4/S

PR104 *0_4/S

2 3

4

PC74

2.2U/6.3V_6

PWM EN

VCC

PV Change

B B

PWM_SA[42] DRON[42]

PV Change

8

NCP81253

GND6PAD

9

DRVH

BST

SW

DRVL

1

VGTA_BST1

7

SW_SA

5

LG_SA

PR90

1_6

PC77

0.22U/25V_6

HG_SA_LHG_SA

PQ29

MDV1595SURH

35241

678

35241

4.7U/25V_8

PQ27 EMB20N03V

PR239 *2.2_6

PC251 *2200P/50V_4

PC243 *4.7U/25V_8

DCR=4.2m ohm

0.47uH/17.5A(PCMC063T-R47MN)

PR244 *0_2/S

PL20

PC58

0.1U/25V_4

PR255 *0_2/S

PL17 *0_8/S

PC59 2200P/50V_4

PC84

*22U/6.3V_8

CSN_SA [42] SWN_SA [42]

PC269

22U/6.3V_8

PC230

0.1U/25V_4

PC102

22U/6.3V_8

+VCCSA

TDC=4[A]

IccMax current=5[A]

+VCCSA

PC103

22U/6.3V_8

PC270

PC94

22U/6.3V_8

*22U/6.3V_8

C C

D D

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

+VCCSA (NCP81253)

Custom

Date:

1

2

3

4

+VCCSA (NCP81253)

Wednesday, July 29, 2015

Sheet :

5

of

43 51

Rev.Size

3C

5

4

3

2

1

44

D D

+3VS5

C C

PC134

0.1U/16V_4

PR144 *0_8/S

+3V_S2

PC130 *10U/6.3V_6

+5VS5

PR143 *0_4/S

PC133

0.1U/16V_4

PC125

0.1U/16V_4

PC131 *0.1U/16V_4

+3V +3VLANVCC

MAINON[32,35,39,40,41]

PV Change

B B

13

VOUT1

14

VOUT1

4

VBIAS

3

ON1

PC126

220P/50V_4

1

APL3523A

VIN12VIN1

PU10

CT1

12

VIN26VIN2

10

7

OUT2 OUT2

GND GND

ON2

CT2

PC124 1000P/50V_4

+3VS5

8 9

11 15

5

PC120

0.1U/16V_4

PC123 *0.1U/16V_4

+3VLANVCC_S2

PC119

0.1U/16V_4

PR139 *0_4/S

PV Change

0.67A5.2A

PR137

*0_6/S

PC121 *10U/6.3V_6

LAN_POWER [35]

+5V +3VSUS

PR179 *0_8/S

+5V_S2

MAINON

PC175 *10U/6.3V_6

+5VS5

PR170 *0_4/S

PV Change

+5VS5

PC180

0.1U/16V_4

PC165

0.1U/16V_4

PC172

0.1U/16V_4

13

VOUT1

14

VOUT1

4

VBIAS

3

ON1

PC166 *0.1U/16V_4

PC179

220P/50V_4

1

APL3523A

PU12

12

VIN12VIN1

CT1

VIN26VIN2

CT2

10

1000P/50V_4

7

PC178

OUT2 OUT2

GND GND

ON2

+3VS5

8 9

11 15

5

PC171

0.1U/16V_4

PR169 *0_4/S

PC164 *0.1U/16V_4

+3VSUS_S2

PC177

0.1U/16V_4

PV Change

PR177 *0_6/S

PC176 *10U/6.3V_6

SUSON [35,39,41]

0.04A5.1A

+3V[2,4,10,11,12,13,14,15,16,17,18,19,21,22,24,25,26,27,28,29,30,31,33,34,35,36,42,45,46] +5V[25,27,33,36]

+VIN[25,36,37,38,39,40,42,43,45,46,47] +3VS5[4,10,15,16,27,30,33,35,36,38,40,41,47] +5VS5[4,27,32,36,38,39,40,41,42,43,45,46,47]

A A

Document Number

Custom

Date:

Wednesday, July 29, 2015

5

4

3

2

Wednesday, July 29, 2015

+3VLANVCC[28,32]

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Load switch IC (APL3523A)

Sheet :

1

of

44 51

Rev.Size

3C

5

4

3

2

1

VGA Core

PC48

PC47

2200P/50V_4

+

PC33

PL3 *0_8/S

PL2 *0_8/S

PC34

0.1U/25V_4

2200P/50V_4

+VIN

12

+

PC227 *100U/25V

For Acoustic

12

+

N16S-GT (23/18W)

EDP: 26A

EDP peak: 51A

OCP minimum 56A

+VGACORE

12

*330u_2V_7343

+

PC50

*330u_2V_7343

12

+

PC215

390U/2.5V_5X5.8ESR10

12

+

PC224

390U/2.5V_5X5.8ESR10

12

+

PC225

*390U/2.5V_5X5.8ESR10

12

+

PU2

D D

+5VS5

+VIN_VGACORE

1U/25V_6

+3V

DGPU_VC_EN[22,47]

+3V_GFX

+3V_MAIN_EN[22,47]

C C

for VGA sequence

PSI[22]

GPU_VID[22]

PV Change

Open VR config=B

2700P/50V_4

B B

8813VREF

PC2

8813VREF

PR213

1 2

10K/F_4 NTC

PR200 *0_6/S

PR1 1_6

PC6

PR33

10K/F_4

RB500V-40

PD5

PR197 47K/F_4

PR30 *0_4/S

PR24 *0_4/S

PR5 20K/F_4

PR180

20K/F_4

PR16 2K/F_4

PR181 18K/F_4

PR182 0_4

PR15 324/F_4

PR20 0_4/P

PR18

499K/F_4

PR196 *10K/F_4

21

8813PVCC

PC204

2.2U/6.3V_4

8813TON

8813EN

PC22 *2200P/50V_4

8813PSI

8813VID

8813VREF

PC9

0.1U/16V_4

8813REFADJ

8813REFIN

PC10

*0.01U/50V_4

8813ISEN3

PC17 100P/50V_4

21

9

16

3

4

5

8

6

7

13

PVCC

RT8813CGQW

TON

PGOOD

EN

PSI

VID

VREF

REFADJ

TALERT/ISEN2

REFIN

TSNS/ISEN3

UGATE1

BOOT1

PHASE1

LGATE1

VCC/ISEN1

UGATE2

BOOT2

PHASE2

LGATE2

VSNS

RGND

SS

GND/PWM3

GND

2

1

24

23

15

17

18

19

20

14

11

10

12

22

25

8813UGATE1

8813BOOT1

8813PHASE1

8813LGAT1

8813ISEN1

8813UGATE2

8813BOOT2

8813PHASE2

8813LGAT2

PR32 *0_4

8813ISEN2

PR29 *0_4/S

8813VOUT1

PC11

56P/50V_4

8813RGN

PC12

56P/50V_4

8813SS

8813PWM3

PV Change

PR41 1_6

PC28

0.22U/25V_6

PR40

1_6

PC27

0.22U/25V_6

PR22 30K/F_4

PC8

56P/50V_4

PR50 *0_4/S

8813UGATE1_1

PR191 10K/F_4

PC199

0.22U/10V_4

8813UGATE2_1

DGPU_PROCHOT_EC# [22,35]

+3V

+5VS5

DGPU_PROCHOT# [35]

PV Change

*FDMS0308AS

Ra

*FDMS0308AS

PQ17

PR51

10.5K/F_4

PQ23

PC7 *100P/50V_4

5

D

G

4

S

213

5

D

G

S

213

5

D

G

S

213

5

D

G

S

213

PR3 *0_4/S

PR4 *0_4/S

PV Change

8813UGATE1_1

PQ19 *FDMS7698

8813UGATE2_1

PQ21 *FDMS7698

4

PQ18

FDMS0308AS

4

PQ24

FDMS0308AS

PR212

100/F_4

PR211

100/F_4

PC37

4.7U/25V_8

PQ20 FDMS7698

PR217

2.2_6

PC43

5

D

G

S

213

5

D

G

PC36

4.7U/25V_8

0.36U28A(PCME104T-R36MS0R765)

S

213

5

G

213

5

G

D

S

D

PC218 2200P/50V_4

PC44

PQ22 FDMS7698

PR221

2.2_6

PV Change

+VIN_VGACORE

PC42

4.7U/25V_8

PC45

4.7U/25V_8

*4.7U/25V_8

0.36U28A(PCME104T-R36MS0R765)

DCR=0.76mohm

S

213

PC226 2200P/50V_4

+VGACORE

VGPU_CORE_SENSE [19] VSS_GPU_SENSE [19]

PV Change

+VIN_VGACORE

PC46

4.7U/25V_8

*4.7U/25V_8

PL14

DCR=0.76mohm

PC38

PL15

PC49

4.7U/25V_8

PC35

0.1U/25V_4

12

PC201 100U/25V

PC220

390U/2.5V_5X5.8ESR10

45

A A

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

+VGACORE (RT8813C)

Custom

Date:

5

4

3

2

+VGACORE (RT8813C)

Wednesday, July 29, 2015

Sheet :

1

of

45 51

Rev.Size

3C

5

4

3

2

1

46

+VIN[25,36,37,38,39,40,42,43,45,47]

+5VS5[4,27,32,36,38,39,40,41,42,43,44,45,47]

+1.35V_GFX[20,21,23,36]

D D

PC184

1U/6.3V_4

+5VS5

PR39 *0_4

PR209 113K/F_4

6

PU13

7

NC

21

VCC

IN IN

TON

IN

PV Change

8 9 22

PC20

PC23

+VIN_1.5VGA +VIN

PC25

PL1 *0_8/S

PC29 2200P/50V_4

PC19

0.1U/25V_4

+1.35V Volt +/- 5% Countinue current:3.82A

0.1U/25V_4

20

PR188 *10K/F_4

+3V

PR198 *0_2/S

1237EN1.5V

PC182

0.47U/6.3V_4

1237SS1.5V

PC183 2200P/50V_4

1237PG1.5V

1237PFM1.5V

DGPU_PWROK[12,21,35]

C C

DGPU_FB_EN[22]

PV Change

DGPU_FB_EN

PR189 *0_4/S

PR187 1K/F_4

1

PGOOD

3

PFM

2

EN

23

SS

AOZ1236QI-2

PGND PGND PGND PGND PGND AGND

BST

LX LX LX LX LX

FB

1237BST1.5V

10

1237LX1.5V

11 16 17 18

12 13 14 15 19 4

5

1237FB1.5V

PR190

0_6

PR204

32.4K/F_4

4.7U/25V_8

1237BST1.5V_S

PR199 22K/F_4

4.7U/25V_8

PC185

0.1U/25V_4

1237FB1.5V_S

1uH/11A(PCMC063T-1R0MN)

PR208 *2.2_6

PC209 *2200P/50V_4

PL12

PR205 *0_2/S

PC203

0.1U/16V_4

PC194

*22U/6.3V_8

PC196

*22U/6.3V_8

Peak current:6A OCP minimum:8A

+1.35V_GFX

12

+

PC193

22U/6.3V_8

PC195

PC200 *390U/2.5V_5X5.8ESR10

*22U/6.3V_8

+1.35V_GFX

B B

3

1237EN1.5V

PC24

*0.47U/6.3V_4

A A

5

2

1

4

PQ4 2N7002K

+VIN

PR38 1M_4

PR44 1M_4

PR37 22_8

3

2

PQ3 2N7002K

1

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

+1.35V_GFX (AOZ1267QI)

Custom

Date:

3

2

+1.35V_GFX (AOZ1267QI)

Wednesday, July 29, 2015

Sheet :

1

of

46 51

Rev.Size

3C

1

+VIN[25,36,37,38,39,40,42,43,45,46] +3VS5[4,10,15,16,27,30,33,35,36,38,40,41,44] +5VS5[4,27,32,36,38,39,40,41,42,43,44,45,46]

+1.35VSUS[3,6,17,18,36,39,41]

+3V_GFX[19,21,22,45] +3V_AON[19,22,32]

+1.05V_GFX[19,20,21]

2

3

4

5

6

7

8

47

+3VS5

A A

PC110

0.1U/16V_4

PC108 *0.1U/16V_4

PC105

0.1U/16V_4

13

VOUT1

14

VOUT1

4

VBIAS

3

ON1

*1000P/50V_4

PC109

1

APL3523A

12

VIN12VIN1

PU7

CT1

VIN26VIN2

CT2

10

+3V_MAIN_EN

0.3A

+3V_MAIN_EN[22,45]

PR128 *0_6/S

+3V_GFX_S2+3V_GFX

PC107

*10U/6.3V_6

PR129 *0_4/S

PV Change

PC106

0.1U/16V_4

+5VS5

7

OUT2 OUT2

GND GND

ON2

PC111 *1000P/50V_4

+3VS5

8 9

11 15

5

PC114

0.1U/16V_4

PR130 *0_4/S

PC112 *0.1U/16V_4

+3V_AON_S2

PC115

0.1U/16V_4

PV Change

0.5A

PR131 *0_6/S

PC113 *10U/6.3V_6

DGPU_PWR_EN [12,22]

+3V_AON

+3V_GFX

B B

+VGA_CORE

DGPU_VC_ENVGACORE PGD -->

+1.05V_GFX

+1.05V_GFX +/- 5% Countinue current:0.79A

DGPU_VC_EN GC6_FB_EN

DGPU_FB_EN

+1.35V_GFX

Peak current:2.09A

+1.05V_GFX

PQ7

PD10

5 6 7 8

6

5

EMB20N03V

4

R2

PR57 110/F_4

PR56 100/F_4

1 2 3

PC221

10U/6.3V_6

20150116 updated

PC216

0.01U/50V_4

10U/6.3V_6

PR218 47/F_4

PC222

R1

Vout1=(1+R1/R2)*0.5

PC39

0.1U/16V_4

+1.35VSUS +1.05V_GFX_S

PC40

0.1U/16V_4

C C

+3VS5

PV Change

PR220

PV Change

DGPU_VC_EN[22,45]

PR216 *0_4/S

20141218 updated

D D

GFXPGD

PC217 *0.1U/16V_4

*0_4/S

PR219 10K/F_4

+5VS5

PC219

0.1U/16V_4

PC41

10U/6.3V_6

PR215 10K/F_4

PV Change

PU14

3

PGD

4

EN

1

VCC

G9336

GND

2

2 1

1SS355

DRV

ADJ

PR59 *POWER_JP/S

1 2

+

PC223

+VIN

PR58 22_8

3

*330U_2.5V_3528

PQ6 2N7002K

1

PR54 1M_4

2

PR55 1M_4

3

1

PQ5 2N7002K

2

PR Change

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

3V_GFX/1.05V_GFX(APL3523)

Custom

Date:

1

2

3

4

5

6

3V_GFX/1.05V_GFX(APL3523)

Wednesday, July 29, 2015

7

Sheet :

of

47 51

8

Rev.Size

3C

5

4

3

2

1

+3VS5

S5 PWR MOS SW

D D

+3VS5

S5 PWR MOS SW

+5VS5

+3VLANVCC

16

LAN_POWER

+3VSUS

14

SUSON

+5V

19

13

15

+3VS5

S5 PWR MOS SW

+3V

MAINON

19

18

SUSON

MAINON

LAN_POWER

+3VPCU

3

+5VPUC

BTN

LATCH (NBSWON1#)

13 18

15

3

S5_ON

4

RSMRST#

9

DNBSWON#

9

+VIN

3V/5VPWR

VR

PG

S5 PWR MOS SW

C C

+VIN

MAINON

+0.65V_DDR_VTT

MAINON

19

18

27

VRON

SLP_SUS_ON

IMVP_PWRGD

23

7

GPH5

EC

GPIO55

EC_PWROK

IMVP_PWROK

30

27

5

+3VS5

+5VS5

HWPG

12

17

9 6

12

CHARGER

SUSC# SUSB#

PLTRST#

31

DSWROK_EC

SLP_SUS#_EC

+VIN+PWR_SRC

RSMRST#

PWRBTN# SLP_S4# SLP_S3#

PLTRST#

SYS_PWROK

PCH_PWROK

DSW_PWROK

SLP_SUS#

48

Battery

PCH

1.35V VR

PG

+VIN

B B

+1.0V_DEEP_SUS VR

18

MAINON

PCH_SLP_S0_N

20

+1.35VSUS

14

SUSON

HWPG

+1.0V_DEEP_SUS

PG

13

SLP_SUS_ON

HWPG

+1.0V_DEEP_SUS

+1.0V_EN

8

7

DS3 PWR MOS SW

22

+1.0V

HWPG

21

+VIN

IMVP VR

SUSWARN#_EC

+VCC_CORE

IMVP_PWRGD

26

+VIN

28

+VCCSA

11

10

SUSACK#_EC

SUSWARN#

SUSACK#

IMVP VR

24

PG

EN

+VCCGT

DRON

VRON

25

23

+3VS5

PG

EN

DRON

25

8

+1.8V_DEEP_SUS

CPU

14

A A

+1.0V_DEEP_SUS

+VCCSTPLL

PW8824

13

SUSON

SLP_SUS_ON

7

5

VCCSTPLL_EN

DS3 PWR MOS SW

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PG

EN

INTEL POWER UP SEQUENCE

4

3

SLP_SUS_ON

HWPG

2

7

Custom

Date:

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

Power sequencce diagram

Wednesday, July 29, 2015

Sheet :

1

of

48 51

Rev.Size

3C

Adapter

5

PU3

(+VAD)

+PRWSRC

4

3

2

1

49

VRON MAINONSUSON

PU0001 PU11

NCP81206

+VCC_CORE

DGPU_VC_EN

+1.35VSUS

GMT

PU10

RT8231BGQW

+0.65V_DDR_VTT+VCCGT

PU8

PU2

(+VIN)

PU11

Battery

D D

+3VPCU +5VPCU

SY8208B SY8208C

S5_ON

DRON

NCP81253

+VCCSA

G9336

+3V_MAIN_EN

RT8813CGQW

+VGACORE

PU9

DGPU_FB_EN

AOZ1267QI-03

+1.35V_GFX

PU21

+1.0V_EN

SLP_SUS_ON

PU12

AOZ1267QI-03

+1.0V_DEEP_SUS

PU23 PR11161

AOZ1335DI

+5VS5+3VS5

+1.0V

+1.05V_GFX

C C

VCCIO

+VCCSTPLL

PU7 PU6

Power switch IC

APL3523A

LAN_POWER

B B

(+3VS5)

+3VLANVCC +5V+3VSUS+3V

Power switch IC

APL3523A

SUSONMAINON

(+3VS5)

MAINON

(+5VS5)

Power switch IC

APL3523A

(+3VS5)

DGPU_PWR_EN+3V_MAIN_EN

(+3VS5)

+3V_AON+3V_GFX

PU13

SLP_SUS_ON

PU15

SY8002B

+1.8V_DEEP_SUS

MAINON

PU24

G9183-12TP1U

SLP_SUS_ON

U34

G5243AT11U

+3V_DEEP_SUS

USBPW_ON#

AP2501M8-13

+5V_USBP0

U13

USB_CHARGER_ON

U15

TPS2546

+5V_USBP1

+1.5V

A A

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

Data-Power Block Diagram

C

Date:

5

4

3

2

Data-Power Block Diagram

Wednesday, July 29, 2015

Sheet :

1

of

49 51

Rev.Size

3C

5

4

3

2

1

G3 to S0 S0 S0 to S3 S4/S5

50

+3V_RTC

SRTC_RST#

RTC_RST#

D D

S5_ON

+3VS5

+5VS5

PWR_BTN

SLP_SUS_ON

+3V_DEEP_SUS

+1.8V_DEEP_SUS

T1

9 ms

+1.0V_DEEP_SUS

tPCH03 10 us

RSMRST#

C C

SUS_ON

+1.35VSUS

+3VSUS

+VCCSTPLL

MAINON

tPCH28 30 us

+3V +5V +0.65V_DDR_VTT

+1.0V

HWPG

B B

VRON

+VCORE

+VCCGT

IMVP_PWRGD

EC_PWROK

tPCH33

PLTRST#

A A

5

4

99 ms

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

Intel POWER UP SEQUENCE

3

2

C

Date:

Document Number

Power sequence-2

Wednesday, July 29, 2015

Sheet :

1

of

50 51

Rev.Size

3C

5

4

3

TWL+JWL SYSTEM POWER BLOCK DIAGRAM

2

1

51

DC Jack

D D

CN14

CHARGER PU3 BQ24780

S.W MOS-FET PQ23, PQ24

S.W MOS-FET PQ3

VIN

+BATCHG

BATTERY

NCP81206 PU0001

+VCC_CORE

+VCCGT

SY8208B PU2

+3VPCU

EC, RESET, ALS/Hall IC, CPU

+3VS5

C C

B B

S5_ON

Power IC, Pull High.

APL3523A PU6

SUSON

APL3523A PU7

MAINON

APL3523A PU7

LAN_POWER

APL3523A PU13

+3V_MAIN_EN

APL3523A PU13

DGPU_PWR_EN

G5243AT11U PU34

SLP_SUS_ON

+3V_SUS

CAM, LVDS converter

+3V

CAM, LVDS converter

+3VLANVCC

CPU

+3V_GFX

WLAN

+3V_AON

HMC, Audio

+3V_DEEP_SUS

VRON

RT8231BGQW PU10

SUSON MAINON

NCP81253 PU11

DRON

RT8813CGQW PU9

+3V_MAIN_EN

AOZ1267QI-03 PU21

DGPU_FB_EN

AOZ1267QI-03 PU12

SLP_SUS_ON

+1.35VSUS

RAM, CPU

+0.65V_DRR_VTT

+VCCSA

+VGACORE

CPU

+1.35V_GFX

CPU

+1.0V_DEEP_SUS

CPU

AOZ1335DI PU23

+1.0V_EN

PR11161

+1.0V

CPU

VCCIO

CPU

+VCCSTPLL

CPU

SY8002B PU15

SLP_SUS_ON

+1.8V_DEEP_SUS

SY8208C PU11

G9183-12TP1U PU24

MAINON

A A

S5_ON

+1.5V

5

4

3

+5VPCU

EC, RESET, ALS/Hall IC, CPU

+5VS5

Power IC, Pull High.

AP2501M8-13 U13

USBPW_ON#

TPS2546 U15

USB_CHARGER_ON

2

APL3523A PU6

MAINON

+5V_USBP0

CPU

+5V_USBP1

CPU

+5V

CAM, LVDS converter

Quanta Computer Inc.

Quanta Computer Inc.Quanta Computer Inc.

PROJECT : TWL & JWL ( MB )

Document Number

POWER_Power Diagram

D

Date:

Wednesday, July 29, 2015

1

Sheet :

of

51 51

Rev.Size

3C

Quanta TWL Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual