QUANTA TWH Schematics

TWH (15.6") Intel Huron River Platform Block Diagram

D D

VRAM DDR3 x 8

Max 1GBs/2GBs

DDR3 SODIMM1 Maxima 4GBs

DDR3 800 ~ 1333 MT/s

PAGE 12

https://t.me/biosarchive

DDR3 SO-DIMM2 Maxima 4GBs

DDR3 800 ~ 1333 MT/s

PAGE 13

DMI x 4

C C

SATA - 1st HDD Power : Package : 9.5 (mm)

https://t.me/biosarchive

PAGE 29

SATA0 300MB/s

SATA1 300MB/sSATA - CD-ROM Power : Package : 12.7 (mm)

B B

PAGE 29

SPI Interface

Intel Sandy Bridge

Processor : Daul / Quad Core

Power : 35 / 45 (Watt)

Package : rPGA998B

PCI-E Gen2 x 16 Lane

Nvidia N12P-GS/N12E-GE (Ventura)

Power : 25 / 35 (Watt)

Size : 37.5 x 37.5 (mm) Package : FCBGA973/1005

PAGE 2~5

Size : 29 x 29 (mm)

FDI x 8

BCLK133M DMI100M DP120M

Intel Cougar Point

Platform Controller Hub

32.768KHz

LVDS Interface

HDMI Interface

Power : 3.5 Watt

Package : FCBG989

Size : 25 x 25 (mm)

PAGE 6~11

Azalia

CRT Interface

USB2.0 Interface

USB2.0 Port x 3

(Co-Layout With USB3.0 x 2)

Camera

Power :

Package :

PCIE Gen 1 x 1 LaneLPC Interface

https://t.me/biosarchive

System BIOS SPI ROM

PAGE 25

Keyboard & Touch Pad

PAGE 29

IT8158E

Embedded Controller

Power :

Package : LQPF128

Size : 14 x 14 (mm)

PAGE 32

FAN Controller

Realtek ALC269

Audio Codec

Power :

Package : LQPF48

Size : 7 x 7 (mm)

PAGE 25

Morden Conn

(Option)

A A

PAGE 25

PAGE 26

VIA VL801

USB3.0 Controller

Power :

Package : QFN88

Size : 9.15 x 9.15 (mm)

PAGE 24

USB3.0 Port x 3

(Co-Layout With USB2.0)

PAGE 24

Atheros AR8151

LAN Controller

Power :

Package : OFN48

Size : 6 x 6 (mm)

PAGE 19~20

PAGE 14~18

27MHz

Bluetooth

Power :

Package :

PAGE 27

25MHz

Intel Rambo Peak

Halt Mini Card

WLAN / BT Combo

Power :

Package :

Size :

PAGE 31

LCD Conn (15.6") Dual Channel 1366 x 768

PAGE 21

CRT Conn 2048 x 1536

PAGE 22

HDMI Conn 1920 x 1080

PAGE 23

Realtek RTS5138

Card Reader

Power :

Package : LQPF48

Size : 7 x 7 (mm)

PAGE 28

PCB 6L STACK UP

LAYER 1 : TOP LAYER 2 : SGND LAYER 3 : IN1(High) LAYER 4 : IN2(Low) LAYER 5 : SVCC LAYER 6 : BOT

Power Source

O2Micro OZ8681

System Charge Power (+BATCHG)

P2806

System Discharge Power (+1.5V/+3V/+5V)

Ricktek RT8205

System Power (+3VPCU/+5VPCU/ +3VS5/+5VS5)

NCP6131/NCP5911/RT8209/G9334

Processor Power (+VCC_CORE/ +1.05_VTT/+VCCSA)

Richtek RT8207

System Memory Power (+1.5VSUS/ +0.75V_DDR_VTT)

Richtek RT8209/RT9025

PCH Power (+1.05/+1.8V)

O2Micro OZ8122

DGPU Power (+VGACORE/+3.3V_GFX/ +1.8_VGA/+1.5_GFX/+1.05_GFX)

PCB 8L STACK UP

LAYER 1 : TOP LAYER 2 : SGND LAYER 3 : IN1(High) LAYER 4 : IN2(Low) LAYER 5 : SGND1 LAYER 6 : SVCC LAYER 7 : SGND2 LAYER 8 : BOT

PROJECT : TWH

PROJECT : TWH Quanta Computer Inc.

Quanta Computer Inc.

https://t.me/biosarchive

NB5

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev A3

Block Diagram

Date: Sheet

1 40Tuesday, December 14, 2010

Sandy Bridge Processor (DMI,PEG,FDI) Sandy Bridge Processor (CLK,MISC,JTAG)

CPU_DRAMRST#

R40

4.99K/F_4

+1.5V_CPU[4,10,27] +1.05V_VTT[4,29,33,34,38,39]

+3V[6,7,8,9,10,12,13,14,21,22,23,24,25,26,27,28,29,34,36,37,39]

+3VS5[6,7,8,9,10,14,24,29,31,33,35,36,38]

U15B

U15A

DMI_TXN0[6] DMI_TXN1[6] DMI_TXN2[6] DMI_TXN3[6]

D D

C C

B B

DMI_TXP0[6] DMI_TXP1[6] DMI_TXP2[6] DMI_TXP3[6]

DMI_RXN0[6] DMI_RXN1[6] DMI_RXN2[6] DMI_RXN3[6]

DMI_RXP0[6] DMI_RXP1[6] DMI_RXP2[6] DMI_RXP3[6]

FDI_TXN0[6] FDI_TXN1[6] FDI_TXN2[6] FDI_TXN3[6] FDI_TXN4[6] FDI_TXN5[6] FDI_TXN6[6] FDI_TXN7[6]

FDI_TXP0[6] FDI_TXP1[6] FDI_TXP2[6] FDI_TXP3[6] FDI_TXP4[6] FDI_TXP5[6] FDI_TXP6[6] FDI_TXP7[6]

FDI_FSYNC0[6] FDI_FSYNC1[6]

FDI_INT[6]

FDI_LSYNC0[6] FDI_LSYNC1[6]

eDP_COMP INT_eDP_HPD_Q

eDP_COMP connect to PIN A18 W:4mils/S:15mils/L: 500mils. eDP_COMP connect to PIN A17 W:12mils/S:15mils/L: 500mils.

B27

DMI_RX#[0]

B25

DMI_RX#[1]

A25

DMI_RX#[2]

B24

DMI_RX#[3]

B28

DMI_RX[0]

B26

DMI_RX[1]

A24

DMI_RX[2]

B23

DMI_RX[3]

G21

DMI_TX#[0]

E22

DMI_TX#[1]

F21

DMI_TX#[2]

D21

DMI_TX#[3]

G22

DMI_TX[0]

D22

DMI_TX[1]

F20

DMI_TX[2]

C21

DMI_TX[3]

A21

FDI0_TX#[0]

H19

FDI0_TX#[1]

E19

FDI0_TX#[2]

F18

FDI0_TX#[3]

B21

FDI1_TX#[0]

C20

FDI1_TX#[1]

D18

FDI1_TX#[2]

E17

FDI1_TX#[3]

A22

FDI0_TX[0]

G19

FDI0_TX[1]

E20

FDI0_TX[2]

G18

FDI0_TX[3]

B20

FDI1_TX[0]

C19

FDI1_TX[1]

D19

FDI1_TX[2]

F17

FDI1_TX[3]

J18

FDI0_FSYNC

J17

FDI1_FSYNC

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

eDP_COMPIO

A17

eDP_ICOMPO

B16

eDP_HPD

C15

eDP_AUX

D15

eDP_AUX#

C17

eDP_TX[0]

F16

eDP_TX[1]

C16

eDP_TX[2]

G15

eDP_TX[3]

C18

eDP_TX#[0]

E16

eDP_TX#[1]

D16

eDP_TX#[2]

F15

eDP_TX#[3]

Sandy Bridge_rPGA_Rev0p61

rpga989-47989-socket

DGG^9000014

IC SOCKET RPGA 989P(P1.0,M/H3.0)

DMI

Intel(R) FDI

eDP

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]

PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]

PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]

PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9]

PEG_TX#[10] PEG_TX#[11] PEG_TX#[12]

PCI EXPRESS* - GRAPHICS

PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

J22 J21 H22

K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32

J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32

M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25

M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25

PEG_COMP

PEG_RX#0 PEG_RX#1 PEG_RX#2 PEG_RX#3 PEG_RX#4 PEG_RX#5 PEG_RX#6 PEG_RX#7 PEG_RX#8 PEG_RX#9 PEG_RX#10 PEG_RX#11 PEG_RX#12 PEG_RX#13 PEG_RX#14 PEG_RX#15

PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8 PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15

C_PEG_TX#0 C_PEG_TX#1 C_PEG_TX#2 C_PEG_TX#3 C_PEG_TX#4 C_PEG_TX#5 C_PEG_TX#6 C_PEG_TX#7 C_PEG_TX#8 C_PEG_TX#9 C_PEG_TX#10 C_PEG_TX#11 C_PEG_TX#12 C_PEG_TX#13 C_PEG_TX#14 C_PEG_TX#15

C_PEG_TX0 C_PEG_TX1 C_PEG_TX2 C_PEG_TX3 C_PEG_TX4 C_PEG_TX5 C_PEG_TX6 C_PEG_TX7 C_PEG_TX8 C_PEG_TX9 C_PEG_TX10 C_PEG_TX11 C_PEG_TX12 C_PEG_TX13 C_PEG_TX14 C_PEG_TX15

PEG_COMP connect to PIN H22&J22 W:4mils/S:15mils/L: 500mils. PEG_COMP connect to PIN J21 W:12mils/S:15mils/L: 500mils.

H_SNB_IVB#[7]

SNB_IVB# N.A at SNB EDS #27637 0.7v1

Placement close to EC.

PEG_RX[0..15] [14]

EC_PECI[29]

H_PROCHOT#[29,39]

PM_THRMTRIP#[9,29]

C1016

43P/50V_4

R276 43_4R276 43_4

R167 56.2/F_4R167 56.2/F_4

R462 *0_4/SR462 *0_4/S

12/13 short

11/12 short

R454 *0_4/S

8/31 reserved for "boot hang 47" issue

PM_SYNC[6]

H_PWRGOOD[9]

R454 *0_4/S

C1001 *0.1U/10V_4C1001 *0.1U/10V_4 R457 *0_4/SR457 *0_4/S R456 10K_4R456 10K_4

3/26 DB del for DG update.

8/26 A-->B modify

C502

*0.1U/10V_4

1 2

10/11 change

PM_DRAM_PWRGD_C

R120

R120 *3K/F_4

*3K/F_4

R470 *75_4R470 *75_4 R460 *43_4R460 *43_4

CPU RESET#

PLTRST#[8,14,24,26,27,29]

8/26 A-->B modify

SM_DRAMPWROK Processor Input.

3/26 DB del for DG update.

8/31 change to 0 ohm

+1.05V_VTT

U18

GND3OUT

*74LVC1G07GW

R463 1.5K/F_4R463 1.5K/F_4

+3VS5 +3VS5

CPU_PLTRST# CPU_PLTRST#_RCPU_PLTRST#_R

+3VS5

VCC5NC

R491

R491 *10K_4

*10K_4

PM_DRAM_PWRGD_PU

R495

R495 *0_4

*0_4

PM_DRAM_PWRGD [6]

R127 *0_4/SR127 *0_4/S

12/13 short

SKTOCC#

TP22TP22

TP_CATERR#

TP23TP23

H_PECI

H_PROCHOT#_R

9/9 add for PDG update

PM_THRMTRIP#_R

PM_SYNC_R

short0402

H_PWRGOOD_R

PM_DRAM_PWRGD_R

8/26 A-->B modify

U19

VCC5NC IN GND3OUT

*74LVC1G07GW

PM_DRAM_PWRGD_C

R459

R459 750/F_4

750/F_4

C522

C522 *0.1U/10V_4

*0.1U/10V_4

Q17

Q17 2N7002

2N7002

U15B

C26

SNB_IVB#

AN34

SKTOCC#

AL33

CATERR#

AN33

PECI

AL32

PROCHOT#

AN32

THERMTRIP#

AM34

PM_SYNC

AP33

UNCOREPWRGOOD

SM_DRAMPW ROK

AR33

RESET#

Sandy Bridge_rPGA_Rev0p61

rpga989-47989-socket

DGG^9000014

IC SOCKET RPGA 989P(P1.0,M/H3.0)

+1.5V_CPU

R488

R488 200/F_4

200/F_4 R123 130/F_4R123 130/F_4

R125

8/26 A-->B modify

39_4

MAIN_ONG [4,36]

11/8 add

MISCTHERMALPWR MANAGEMENT

PM_DRAM_PWRGD_R

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLOCKS

DDR3

MISC

DDR3

MISC

JTAG & BPM

BCLK

BCLK#

SM_DRAMRST#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

PRDY# PREQ#

TCK TMS

TRST#

TDO

DBR#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

DDR3_DRAMRST#[12,13]

DRAMRST_CNTRL_PCH[8]

3/26 DB for H/W modify.

A28 A27

A16 A15

AK1 A5 A4

SM_RCOMP[0] W:20mils/S:20mils/L: 500mils, SM_RCOMP[1] W:20mils/S:20mils/L: 500mils, SM_RCOMP[2] W:15mils/S:20mils/L: 500mils,

AP29 AP27

AR26 AR27 AP30

AR28

TDI

AP26

AL35

AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32

CLK_CPU_BCLKP [8]PEG_RX#[0..15] [14] CLK_CPU_BCLKN [8]

CLK_DPLL_SSCLKP_R CLK_DPLL_SSCLKN_R

CPU_DRAMRST#

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

XDP_PRDY# XDP_PREQ#

XDP_TCLK XDP_TMS XDP_TRST#

XDP_TDI_R XDP_TDO

XDP_DBRST#

XDP_BPM0 XDP_BPM1 XDP_BPM2 XDP_BPM3 XDP_BPM4 XDP_BPM5 XDP_BPM6 XDP_BPM7

R134 140/F_4R134 140/F_4 R396 26.1/F_4R396 26.1/F_4 R395 200/F_4R395 200/F_4

R453 *1K_4R453 *1K_4

TP72TP72 TP28TP28

TP68TP68 TP73TP73 TP71TP71

TP27TP27 TP74TP74

TP30TP30 TP31TP31 TP67TP67 TP69TP69 TP25TP25 TP66TP66 TP70TP70 TP65TP65

DDR3 DRAM RESET

+1.5VSUS

R41 1K_4R41 1K_4

R43 1K_4R43 1K_4

CPU_DRAMRST#_R

R39 *0_4/S

11/12 short

short0402

0.047U/10V_4

CPU XDP

+3V

XDP_DBRST# [6]

R42 *0_4R42 *0_4

2N7002Q92N7002

C37

8/26 A-->B modify

FDI disable (DIS only stuff)

FDI_INT

R71 *0_4R71 *0_4 R69 *0_4R69 *0_4

A A

R70 *0_4R70 *0_4

R68 *1K_4R68 *1K_4 R72 *1K_4R72 *1K_4

FDI_FSYNC can gang all these 4 signals together and tie them with only one 1K resistor to GND (DG V0.5 Ch2.2.9).

FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

PEG x16 disable (UMA only remove)

PEG_TX[0..15][14] PEG_TX#[0..15][14]

C_PEG_TX0 C_PEG_TX1 C_PEG_TX2 C_PEG_TX3 C_PEG_TX4 C_PEG_TX5 C_PEG_TX6 C_PEG_TX7 C_PEG_TX8 C_PEG_TX9 C_PEG_TX10 C_PEG_TX11 C_PEG_TX12 C_PEG_TX13 C_PEG_TX14 C_PEG_TX15

C500 0.1U/10V_4C500 0.1U/10V_4 C499 0.1U/10V_4C499 0.1U/10V_4 C497 0.1U/10V_4C497 0.1U/10V_4 C493 0.1U/10V_4C493 0.1U/10V_4 C495 0.1U/10V_4C495 0.1U/10V_4 C488 0.1U/10V_4C488 0.1U/10V_4 C489 0.1U/10V_4C489 0.1U/10V_4 C483 0.1U/10V_4C483 0.1U/10V_4 C486 0.1U/10V_4C486 0.1U/10V_4 C478 0.1U/10V_4C478 0.1U/10V_4 C480 0.1U/10V_4C480 0.1U/10V_4 C479 0.1U/10V_4C479 0.1U/10V_4 C474 0.1U/10V_4C474 0.1U/10V_4 C465 0.1U/10V_4C465 0.1U/10V_4 C466 0.1U/10V_4C466 0.1U/10V_4

0.22uF AC coupling Caps for PCIE GEN1/2/3

PEG_TX0 PEG_TX1 PEG_TX2 PEG_TX3 PEG_TX4 PEG_TX5 PEG_TX6 PEG_TX7 PEG_TX8 PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15

C_PEG_TX#0 C_PEG_TX#1 C_PEG_TX#2 C_PEG_TX#3 C_PEG_TX#4 C_PEG_TX#5 C_PEG_TX#6 C_PEG_TX#7 C_PEG_TX#8 C_PEG_TX#9 C_PEG_TX#10 C_PEG_TX#11 C_PEG_TX#12 C_PEG_TX#13 C_PEG_TX#14 C_PEG_TX#15

C505 0.1U/10V_4C505 0.1U/10V_4C504 0.1U/10V_4C504 0.1U/10V_4 C503 0.1U/10V_4C503 0.1U/10V_4 C501 0.1U/10V_4C501 0.1U/10V_4 C498 0.1U/10V_4C498 0.1U/10V_4 C494 0.1U/10V_4C494 0.1U/10V_4 C496 0.1U/10V_4C496 0.1U/10V_4 C490 0.1U/10V_4C490 0.1U/10V_4 C492 0.1U/10V_4C492 0.1U/10V_4 C485 0.1U/10V_4C485 0.1U/10V_4 C487 0.1U/10V_4C487 0.1U/10V_4 C481 0.1U/10V_4C481 0.1U/10V_4 C482 0.1U/10V_4C482 0.1U/10V_4 C475 0.1U/10V_4C475 0.1U/10V_4 C476 0.1U/10V_4C476 0.1U/10V_4 C468 0.1U/10V_4C468 0.1U/10V_4 C469 0.1U/10V_4C469 0.1U/10V_4

PEG_TX#0 PEG_TX#1 PEG_TX#2 PEG_TX#3 PEG_TX#4 PEG_TX#5 PEG_TX#6 PEG_TX#7 PEG_TX#8 PEG_TX#9 PEG_TX#10 PEG_TX#11 PEG_TX#12 PEG_TX#13 PEG_TX#14 PEG_TX#15

0.22uF AC coupling Caps for PCIE GEN1/2/3

Embedded Display PLL Clock

3/26 DB change

Part reference.

RP11

CLK_DPLL_SSCLKP_R CLK_DPLL_SSCLKN_R

SG/UMA

RP11

0_4P2R_04

R398 *0_4R398 *0_4

R397 *0_4R397 *0_4

Ra Rb Rc NCDIS

Stuff Stuff

Stuff

NC NC

CLK_DPLL_SSCLKP [8] CLK_DPLL_SSCLKN [8]

DP & PEG Compensation

+1.05V_VTT

eDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance <25 mohms

+1.05V_VTT

PEG_ICOMPI and RCOMPO signals should be routed within 500 mils typical impedance = 43 mohms PEG_ICOMPO signals should be routed within 500 mils typical impedance = 14.5 mohms

R389 10K_4R389 10K_4

R390 24.9/F_4R390 24.9/F_4

R67 24.9/F_4R67 24.9/F_4

INT_eDP_HPD_Q

eDP_COMP

PEG_COMP

NB5

Processor pull-up (CPU)

H_PROCHOT# XDP_TDO XDP_TMS XDP_TDI_R XDP_PREQ# XDP_TCLK XDP_TRST#

PROJECT : TWH

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev Custom

Custom

Processor 1/4 (Host/GPU)

Date: Sheet

R168 62_4R168 62_4 R476 51_4R476 51_4 R474 51_4R474 51_4 R159 51_4R159 51_4 R162 *51_4R162 *51_4 R163 51_4R163 51_4 R475 51_4R475 51_4

+1.05V_VTT

2 40Tuesday, December 14, 2010

Sandy Bridge Processor (DDR3)

U15D

D10

K10

AM5 AM6 AR3

AP3 AN3 AN2 AN1

AP2

AP5 AN9

AT5

AT6

AP6 AN8 AR6 AR5 AR9

AJ11

AT8

AT9

AH11

AR8

AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15

AA9

AA7

AA10

AB8

AB9

J10

C9 A7

C8 A9 A8 D9 D8 G4 F4 F1 G1 G5 F5 F2 G2

J7 J8

K8 K7 M5 N4 N2 N1 M4 N5 M2 M1

U15D

SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]

SB_BS[0] SB_BS[1] SB_BS[2]

SB_CAS# SB_RAS# SB_WE#

AE2

SB_CLK[0]

AD2

SB_CLK#[0]

SB_CKE[0]

AE1

SB_CLK[1]

AD1

SB_CLK#[1]

R10

SB_CKE[1]

AB2

SB_CLK[2]

AA2

SB_CLK#[2]

SB_CKE[2]

AA1

SB_CLK[3]

AB1

SB_CLK#[3]

T10

SB_CKE[3]

AD3

SB_CS#[0]

AE3

SB_CS#[1]

AD6

SB_CS#[2]

AE6

SB_CS#[3]

AE4

SB_ODT[0]

AD4

SB_ODT[1]

AD5

SB_ODT[2]

AE5

SB_ODT[3]

M_B_DQSN0

SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]

SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6]

DDR SYSTEM MEMORY B

SB_DQS[7]

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8]

SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

F3 K6 N3 AN5 AP9 AK12 AP15

C7 G3 J6 M3 AN6 AP8 AK11 AP14

AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4

M_B_DQSN1 M_B_DQSN2 M_B_DQSN3 M_B_DQSN4 M_B_DQSN5 M_B_DQSN6 M_B_DQSN7

M_B_DQSP0 M_B_DQSP1 M_B_DQSP2 M_B_DQSP3 M_B_DQSP4 M_B_DQSP5 M_B_DQSP6 M_B_DQSP7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15

M_B_CLKP0 [13] M_B_CLKN0 [13] M_B_CKE0 [13]

M_B_CLKP1 [13] M_B_CLKN1 [13] M_B_CKE1 [13]

M_B_CS#0 [13] M_B_CS#1 [13]

M_B_ODT0 [13] M_B_ODT1 [13]

M_B_DQSN[7:0] [13]

M_B_DQSP[7:0] [13]

M_B_A[15:0] [13]

U15C

D D

M_A_DQ[63:0][12]

C C

B B

M_A_BS#0[12] M_A_BS#1[12] M_A_BS#2[12]

M_A_CAS#[12] M_A_RAS#[12] M_A_WE#[12]

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

G10

N10

M10

AG6 AG5 AK6 AK5 AH5 AH6 AJ5 AJ6 AJ8 AK8 AJ9 AK9 AH8 AH9 AL9

AL8 AP11 AN11

AL12 AM12 AM11

AL11 AP12 AN12

AJ14 AH14

AL15 AK15

AL14 AK14

AJ15 AH15

AE10 AF10

AE8 AD9 AF9

F10

C5 D5 D3 D2 D6 C6 C2 C3

F7 G8 G7

K2 M8

N7 M9

N9 M7

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE#

DDR SYSTEM MEMORY A

SA_CLK[0]

SA_CLK#[0]

SA_CKE[0]

SA_CLK[1]

SA_CLK#[1]

SA_CKE[1]

SA_CLK[2]

SA_CLK#[2]

SA_CKE[2]

SA_CLK[3]

SA_CLK#[3]

SA_CKE[3]

SA_CS#[0] SA_CS#[1] SA_CS#[2] SA_CS#[3]

SA_ODT[0] SA_ODT[1] SA_ODT[2] SA_ODT[3]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

AB6 AA6 V9

AA5 AB5 V10

AB4 AA4 W9

AB3 AA3 W10

AK3 AL3 AG1 AH1

AH3 AG3 AG2 AH2

C4 G6 J3 M6 AL6 AM8 AR12 AM15

D4 F6 K3 N6 AL5 AM9 AR11 AM14

AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7

M_A_DQSN0 M_A_DQSN1 M_A_DQSN2 M_A_DQSN3 M_A_DQSN4 M_A_DQSN5 M_A_DQSN6 M_A_DQSN7

M_A_DQSP0 M_A_DQSP1 M_A_DQSP2 M_A_DQSP3 M_A_DQSP4 M_A_DQSP5 M_A_DQSP6 M_A_DQSP7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

M_A_CLKP0 [12] M_A_CLKN0 [12] M_A_CKE0 [12]

M_A_CLKP1 [12] M_A_CLKN1 [12] M_A_CKE1 [12]

M_A_CS#0 [12] M_A_CS#1 [12]

M_A_ODT0 [12] M_A_ODT1 [12]

M_A_DQSN[7:0] [12]

M_A_DQSP[7:0] [12]

M_A_A[15:0] [12]

M_B_DQ[63:0][13]

M_B_BS#0[13] M_B_BS#1[13] M_B_BS#2[13]

M_B_CAS#[13] M_B_RAS#[13] M_B_WE#[13]

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

Sandy Bridge_rPGA_Rev0p61

rpga989-47989-socket

DGG^9000014

IC SOCKET RPGA 989P(P1.0,M/H3.0)

A A

IC SOCKET RPGA 989P(P1.0,M/H3.0)

Sandy Bridge_rPGA_Rev0p61

rpga989-47989-socket

DGG^9000014

IC SOCKET RPGA 989P(P1.0,M/H3.0)

PROJECT : TWH

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev Custom

Custom

Processor 2/4 (Memory)

NB5

Processor 2/4 (Memory)

Date: Sheet

3 40Tuesday, December 14, 2010

9/4 all of these 22uF/6.3V capacitors are repleaced by 10uF/6.3V in BOM

SNB: 55A

C473

C48

D D

22U/6.3VS_8

C108

C108 22U/6.3VS_8

22U/6.3VS_8

C51

C51 22U/6.3VS_8

22U/6.3VS_8

C206

C206 22U/6.3VS_8

22U/6.3VS_8

C C

C125

C125 22U/6.3VS_8

22U/6.3VS_8

C144

C144 22U/6.3VS_8

22U/6.3VS_8

C157

C157 22U/6.3VS_8

22U/6.3VS_8

C46

C46 *22U/6.3VS_8

*22U/6.3VS_8

B B

C461

C461 22U/6.3VS_8

22U/6.3VS_8

C41

C41 22U/6.3VS_8

22U/6.3VS_8

22uF_8 x8 Socket TOP cavity 22uF_8 x10 Socket BOT cavity 22uF_8 x8 Socket TOP edge 470uF_7343 x4

3/26 DB change 10U FP to 0805.

A A

C473 22U/6.3VS_8

22U/6.3VS_8

C92

C92 22U/6.3VS_8

22U/6.3VS_8

C28

C28 22U/6.3VS_8

22U/6.3VS_8

C165

C165 22U/6.3VS_8

22U/6.3VS_8

C477

C477 *22U/6.3VS_8

*22U/6.3VS_8

C147

C147 22U/6.3VS_8

22U/6.3VS_8

C107

C107 22U/6.3VS_8

22U/6.3VS_8

C467

C467 *22U/6.3VS_8

*22U/6.3VS_8

C29

C29 22U/6.3VS_8

22U/6.3VS_8

C431

C431 22U/6.3VS_8

22U/6.3VS_8

Sandy Bridge Processor (POWER) Sandy Bridge Processor (GRAPHIC POWER)

U15F

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

Sandy Bridge_rPGA_Rev0p61

rpga989-47989-socket

DGG^9000014

IC SOCKET RPGA 989P(P1.0,M/H3.0)

AH13

VCCIO1

AH10

VCCIO2

AG10

VCCIO3

AC10

VCCIO4

Y10

VCCIO5

U10

VCCIO6

P10

VCCIO7

L10

VCCIO8

J14

VCCIO9

J13

VCCIO10

J12

VCCIO11

J11

VCCIO12

H14

VCCIO13

H12

VCCIO14

H11

VCCIO15

G14

VCCIO16

G13

VCCIO17

G12

VCCIO18

F14

VCCIO19

F13

VCCIO20

F12

VCCIO21

F11

VCCIO22

E14

VCCIO23

E12

VCCIO24

E11

VCCIO25

D14

VCCIO26

D13

VCCIO27

D12

VCCIO28

D11

VCCIO29

C14

VCCIO30

C13

VCCIO31

C12

VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39

VCCIO40

VIDALERT#

VIDSCLK

VIDSOUT

C11 B14 B12 A14 A13 A12 A11

J23

AJ29 AJ30 AJ28

PEG AND DDR

CORE SUPPLY

3/26 DB Modify.

AJ35 AJ34

B10 A10

SENSE LINES SVID

VCC_SENSE VSS_SENSE

VCCIO_SENSE

VSSIO_SENSE

C127

C127 22U/6.3VS_8

22U/6.3VS_8

C58

C58 22U/6.3VS_8

22U/6.3VS_8

C178

C178 22U/6.3VS_8

22U/6.3VS_8

C49

C49 22U/6.3VS_8

22U/6.3VS_8

C141

C141 22U/6.3VS_8

22U/6.3VS_8

C197

C197 22U/6.3VS_8

22U/6.3VS_8

C151

C151 22U/6.3VS_8

22U/6.3VS_8

C430

C430 22U/6.3VS_8

22U/6.3VS_8

C53

C53 22U/6.3VS_8

22U/6.3VS_8

C47

C47 *22U/6.3VS_8

*22U/6.3VS_8

+VCC_CORE

9/4 all of these 22uF/6.3V capacitors are repleaced by 10uF/6.3V in BOM

SNB: 8.5A

C135

C135 22U/6.3VS_8

22U/6.3VS_8

C179

C179 22U/6.3VS_8

22U/6.3VS_8

C136

C136 *22U/6.3VS_8

*22U/6.3VS_8

C470

C470 *22U/6.3VS_8

*22U/6.3VS_8

C445

C445 22U/6.3VS_8

22U/6.3VS_8

C446

C446 *22U/6.3VS_8

*22U/6.3VS_8

C460

C460 *22U/6.3VS_8

*22U/6.3VS_8

22uF_8 x7 Socket TOP cavity 22uF_8 x5 Socket BOT cavity 22uF_8 x2 Socket TOP cavity (no stuff) 22uF_8 x5 Socket BOT cavity (no stuff) 330uF_7343 x2

+1.05V_VTT_40

H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT

R66 *0_4/SR66 *0_4/S

R128 100_4R128 100_4

R133 100_4R133 100_4

VSSP_SENSE

+1.05V_VTT

C137

C137 22U/6.3VS_8

22U/6.3VS_8

C138

C138 22U/6.3VS_8

22U/6.3VS_8

C148

C148 22U/6.3VS_8

22U/6.3VS_8

C142

C142 *22U/6.3VS_8

*22U/6.3VS_8

5/14 modify

C120

*22U/6.3VS_8

C454

C454 22U/6.3VS_8

22U/6.3VS_8

C457

C457 22U/6.3VS_8

22U/6.3VS_8

+1.05V_VTT

VCC_SENSE [39] VSS_SENSE [39]

VCCP_SENSE [34]

Trace Route to Power IC area.

C450

C450 22U/6.3VS_8

22U/6.3VS_8

C209

C209 22U/6.3VS_8

22U/6.3VS_8

C464

C464 22U/6.3VS_8

22U/6.3VS_8

C121

C121 *22U/6.3VS_8

*22U/6.3VS_8

C198

C198 *22U/6.3VS_8

*22U/6.3VS_8

C158

C158 *22U/6.3VS_8

*22U/6.3VS_8

C101

C101 22U/6.3VS_8

22U/6.3VS_8

5/4: add C8260/ C8322

+VCC_CORE

TP53TP53

+1.5VSUS[2,10,12,13,32,33,38] +1.5V_CPU[2,10,27] +1.05V_VTT[2,29,33,34,38,39]

+VCCSA[33]

+VCC_GFX[39,40]

+VCC_CORE[39,40]

22uF_8 x2 Socket TOP cavity 22uF_8 x2 Socket BOT cavity 22uF_8 x4 Socket TOP edge 22uF_8 x4 Socket BOT edge 470uF_7343 x2

+VCC_GFX

+1.8V

SNB: 1.5A

C42

C45

10U/6.3V_8

1U/6.3V_4

330uF x1, 10uF_8 x1, 1uF_4 x2 Socket BOT edge.

3/26 DB change 10U FP to 0805.

Layout note: need routing together and ALERT need between CLK and DATA.

H_CPU_SVIDCLK

Place PU resistor close to CPU

H_CPU_SVIDDAT

Place PU resistor close to CPU

H_CPU_SVIDALRT#

SNB: 21.5A

C472

C472 22U/6.3V_8

22U/6.3V_8

C193

C193 22U/6.3V_8

22U/6.3V_8

C192

C192 22U/6.3V_8

22U/6.3V_8

C207

C207 22U/6.3V_8

22U/6.3V_8

C512

C512 22U/6.3V_8

22U/6.3V_8

C168

C168 22U/6.3V_8

22U/6.3V_8

R473 *0_4R473 *0_4

C167

C167 22U/6.3V_8

22U/6.3V_8

C208

C208 22U/6.3V_8

22U/6.3V_8

C511

C511 22U/6.3V_8

22U/6.3V_8

C166

C166 22U/6.3V_8

22U/6.3V_8

C169

C169 22U/6.3V_8

22U/6.3V_8

C471

C471 22U/6.3V_8

22U/6.3V_8

DISNCSG/UMA

Ra Stuff

C44

C44 1U/6.3V_4

1U/6.3V_4

3/26 DB Modify.

+1.05V_VTT +1.05V_VTT

+1.05V_VTT

C432

330U/2V_7343

R121

R121 130/F_4

130/F_4

3/26 DB Modify.

R158 75_4R158 75_4

R166 43_4R166 43_4

U15G

AT24

VAXG1

AT23

VAXG2

AT21

VAXG3

AT20

VAXG4

AT18

VAXG5

AT17

VAXG6

AR24

VAXG7

AR23

VAXG8

AR21

VAXG9

AR20

VAXG10

AR18

VAXG11

AR17

VAXG12

AP24

VAXG13

AP23

VAXG14

AP21

VAXG15

AP20

VAXG16

AP18

VAXG17

AP17

VAXG18

AN24

VAXG19

AN23

VAXG20

AN21

VAXG21

AN20

VAXG22

AN18

VAXG23

AN17

VAXG24

AM24

VAXG25

AM23

VAXG26

AM21

VAXG27

AM20

VAXG28

AM18

VAXG29

AM17

VAXG30

AL24

VAXG31

AL23

VAXG32

AL21

VAXG33

AL20

VAXG34

AL18

VAXG35

AL17

VAXG36

AK24

VAXG37

AK23

VAXG38

AK21

VAXG39

AK20

VAXG40

AK18

VAXG41

AK17

VAXG42

AJ24

VAXG43

AJ23

VAXG44

AJ21

VAXG45

AJ20

VAXG46

AJ18

VAXG47

AJ17

VAXG48

AH24

VAXG49

AH23

VAXG50

AH21

VAXG51

AH20

VAXG52

AH18

VAXG53

AH17

VAXG54

VCCPLL1

VCCPLL2

VCCPLL3

Sandy Bridge_rPGA_Rev0p61

rpga989-47989-socket

DGG^9000014

IC SOCKET RPGA 989P(P1.0,M/H3.0)

Place PU resistor close to VR

R124 *54.9/F_4R124 *54.9/F_4

Place PU resistor

R118

close to VR

*130/F_4

5/12: modify

3/26 DB Modify.

SENSE

GRAPHICS

1.8V RAIL

SVID CLK

+1.05V_VTT

VR_SVID_CLK [39]

SVID DATA

VR_SVID_DATA [39]

SVID ALERT

VR_SVID_ALERT# [39]

VSSAXG_SENSE

LINES

VREFMISC

DDR3 -1.5V RAILS

SA RAIL

VCCSA_SENSE

VAXG_SENSE

SM_VREF

VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8

VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8

FC_C22

VCCSA_VID1

3/26 DB Modify.

AK35 AK34

+VDDR_REF_CPU

AL1

AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1

R136 100_4R136 100_4

VCC_AXG_SENSE [39] VSS_AXG_SENSE [39]

R138 100_4R138 100_4

CAD Note: +VDDR_REF_CPU should have 10 mil trace width

R157 *0_8R157 *0_8

R165

R165 100K_4

100K_4

11/13 C516 mount for S3 black screen issue

5/14 modify

C134

C134 10U/6.3V_6

10U/6.3V_6

C173

C173 10U/6.3V_6

10U/6.3V_6

3/26 DB change 10U FP to 0805.

Q19

Q19 2N7002

2N7002

MAIND

SNB: 5A

C152

C152 10U/6.3V_8

10U/6.3V_8

4/27: layout modify

330uF x1, 10uF_8 x6 Socket BOT edge.

C213

C213 10U/6.3V_6

10U/6.3V_6

8/31 C516 FP changed from 330U_2.5V_5.0x5.9ESR10m to 220U/6.3V_6x4.5ESR18

SNB: 6A

M27 M26 L26 J26 J25 J24 H26 H25

VCCUSA_SENSE_R

H23

11/12 short

H_FC_C22

C22 C24

C31

C447

10U/6.3V_8

330uF x1, 10uF_8 x1 Socket BOT edge, 10uF_8 x2 Socket BOT cavity.

3/26 DB change 10U FP to 0805.

R388 *0_4/S

short0402

R392 10K_4R392 10K_4

R393 10K_4R393 10K_4

5/11: Add for intel CRB

9/8 delete JP1

5 2

MAIND

NB5

Q40

Q40 AON7410

AON7410

+1.5V_CPU+1.5VSUS

R170

220_8

3/26 DB add for Intel.

C262

C262 *470P/50V_4

*470P/50V_4

PROJECT : TWH

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev Custom

Custom

Processor 3/4 (Power)

Date: Sheet

Placement close to CPU.

Q20

2N7002

+VCC_GFX

DDR_VTTREF [12,13,32]

MAIND [36]

+1.5V_CPU

C153

C204

10U/6.3V_6

C516

C516 100U 16V(+-20%,6.3*5.8)

100U 16V(+-20%,6.3*5.8)

+VCCSA

C97

C24

10U/6.3V_8

*10U/6.3V_8

VCCUSA_SENSE [33]

VCCSA_SEL [33]

+1.5VSUS

C515 0.1U/10V_4C515 0.1U/10V_4 C517 0.1U/10V_4C517 0.1U/10V_4 C518 0.1U/10V_4C518 0.1U/10V_4 C514 0.1U/10V_4C514 0.1U/10V_4

MAIN_ONG [2,36]

5/6: modify

CPU VDDQ

4 40Tuesday, December 14, 2010

Sandy Bridge Processor (GND)

U15I

M34

H33 H30 H27 H24 H21 H18 H15 H13 H10

G35 G32 G29 G26 G23 G20 G17 G11

U15I

T35

VSS161

T34

VSS162

T33

VSS163

T32

VSS164

T31

VSS165

T30

VSS166

T29

VSS167

T28

VSS168

T27

VSS169

T26

VSS170

VSS171

VSS172

VSS173

VSS174

VSS175

VSS176

N35

VSS177

N34

VSS178

N33

VSS179

N32

VSS180

N31

VSS181

N30

VSS182

N29

VSS183

N28

VSS184

N27

VSS185

N26

VSS186 VSS187

L33

VSS188

L30

VSS189

L27

VSS190

VSS191

VSS192

VSS193

VSS194

VSS195

VSS196

VSS197

VSS198

K35

VSS199

K32

VSS200

K29

VSS201

K26

VSS202

J34

VSS203

J31

VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213

VSS214

VSS215

VSS216

VSS217

VSS218

VSS219

VSS220

VSS221

VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230

F34

VSS231

F31

VSS232

F29

VSS233

VSS

VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285

F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3

SMDDR_VREF_DQ0_M3[12] SMDDR_VREF_DQ1_M3[13]

H_VTTVID1[34]

U15H

AT35

VSS1

AT32

VSS2

AT29

VSS3

AT27

VSS4

AT25

VSS5

AT22

VSS6

AT19

D D

C C

B B

AT16 AT13 AT10

AR25 AR22 AR19 AR16 AR13 AR10

AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10

AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10

AM29 AM25 AM22 AM19 AM16 AM13 AM10

AM7 AM4 AM3 AM2

AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10

AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10

AJ25

AT7 AT4 AT3

AR7 AR4 AR2

AP7 AP4 AP1

AN7 AN4

AL7 AL4 AL2

AK7 AK4

VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80

VSS

VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98

VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160

AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH26 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2

Sandy Bridge Processor (RESERVED, CFG)

U15E

For CPU debug.

TP20TP20 TP19TP19

TP24TP24

R394

R394 *1K_4

*1K_4

R391 *0_4/S

11/12 short

CFG0 CFG2 CFG4

CFG5 CFG6 CFG7CFG7

R387

R387 *1K_4

*1K_4

short0402

AK28

CFG[0]

AK29

CFG[1]

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30

CFG[9]

AM28

CFG[10]

AM26

CFG[11]

AN28

CFG[12]

AN31

CFG[13]

AN26

CFG[14]

AM27

CFG[15]

AK31

CFG[16]

AN29

CFG[17]

AJ31

RSVD1

AH31

RSVD2

AJ33

RSVD3

AH33

RSVD4

AJ26

RSVD5

RSVD6

RSVD7

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

A19

RSVD26

J15

RSVD27

Sandy Bridge_rPGA_Rev0p61

rpga989-47989-socket

DGG^9000014

IC SOCKET RPGA 989P(P1.0,M/H3.0)

RESERVED

RSVD28

AG7

RSVD29

AE7

RSVD30

AK2

RSVD31

RSVD32

AT26

RSVD33

AM33

RSVD34

AJ27

RSVD35

RSVD37

J16

RSVD38

H16

RSVD39

G16

RSVD40

AR35

RSVD41

AT34

RSVD42

AT33

RSVD43

AP35

RSVD44

AR34

RSVD45

B34

RSVD46

A33

RSVD47

A34

RSVD48

B35

RSVD49

C35

RSVD50

AJ32

RSVD51

AK32

RSVD52

AH27

RSVD53

AN35

RSVD54

AM35

RSVD55

#27636 SNB EDS0.7v1 no function.

AT2

RSVD56

AT1

RSVD57

AR1

RSVD58

For rPGA socket, RSVD59 pin should be left NC.

KEY

TP63TP63 TP64TP64

Sandy Bridge_rPGA_Rev0p61

rpga989-47989-socket

DGG^9000014

IC SOCKET RPGA 989P(P1.0,M/H3.0)

Processor Strapping

The CFG signals have a default value of '1' if not terminated on the board.

1 0

A A

CFG2 (PEG Static Lane Reversal)

CFG4 (DP Presence Strap)

CFG7 (PEG Defer Training)

Normal Operation Lane Reversed

Disable; No physical DP attached to eDP

PEG train immediately following xxRESETB de assertion

Sandy Bridge_rPGA_Rev0p61

rpga989-47989-socket

DGG^9000014

IC SOCKET RPGA 989P(P1.0,M/H3.0)

Enable; An ext DP device is connected to eDP

PEG wait for BIOS training

CFG[6:5] (PCIE Port Bifurcation Straps)

11: (Default) x16 - Device 1 functions 1 and 2 disabled 10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled

(hh) TWH PEG bus is Lane Reversed

CFG2

R155 1K_4R155 1K_4

CFG4

R156 *1K_4R156 *1K_4

CFG7

R153 *1K_4R153 *1K_4

CFG5

R141 *1K_4R141 *1K_4

CFG6

R152 *1K_4R152 *1K_4

01: Reserved - (Device 1 function 1 disabled ; function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

PROJECT : TWH

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev Custom

Custom

Processor 4/4 (Ground)

NB5

Processor 4/4 (Ground)

Date: Sheet

5 40Tuesday, December 14, 2010

Cougar Point (DMI,FDI,PM)

U24C

DMI_RXN0[2] DMI_RXN1[2] DMI_RXN2[2] DMI_RXN3[2]

DMI_RXP0[2]

+1.05V

DMI_RXP1[2] DMI_RXP2[2] DMI_RXP3[2]

DMI_TXN0[2] DMI_TXN1[2] DMI_TXN2[2] DMI_TXN3[2]

DMI_TXP0[2] DMI_TXP1[2] DMI_TXP2[2] DMI_TXP3[2]

R563 49.9/F_4R563 49.9/F_4 R284 750/F_4R284 750/F_4

DMI_COMP DMI_RBIAS

D D

11/12 short

SUS_PWR_ACK_R

SUSACK#[29]

C C

B B

XDP_DBRST#[2]

10/11 add

EC_PWROK[29]

12/13 short

PM_DRAM_PWRGD[2]

11/12 short

SUS_PWR_ACK[29]

DNBSWON#[29]

AC_PRESENT[29]

SYS_PWROK

EC_PWROK_R

RSMRST#[29]

R584 *0_4/S

short0402

SUSACK#_R XDP_DBRST#

SYS_PWROK_R

EC_PWROK_R

APWROK_R

PM_DRAM_PWRGD

RSMRST#

SUS_PWR_ACK_R

DNBSWON#_R

AC_PRESENT_R

PM_BATLOW#

PM_RI#

R590 *0_4R590 *0_4

C2003 1U/10V_4C2003 1U/10V_4

R630 *0_4/S

R312 *0_4R312 *0_4 R336 *0_4/SR336 *0_4/S

R334 *0_4/SR334 *0_4/S R294 *0_4/S

R578 *0_4/S

R570 *0_4/S

R269 *0_4R269 *0_4

8/26 A-->B modify

PCH Pull-high/low(CLG)

PM_RI# PM_BATLOW# PCIE_WAKE# SLP_LAN# SUS_PWR_ACK AC_PRESENT_R

A A

CLKRUN# XDP_DBRST#

RSMRST# SYS_PWROK

R610 10K_4R610 10K_4 R350 *8.2K_4R350 *8.2K_4 R613 10K_4R613 10K_4 R268 *10K_4R268 *10K_4 R577 10K_4R577 10K_4 R270 10K_4R270 10K_4

R639 8.2K_4R639 8.2K_4 R624 10K_4R624 10K_4 R599 *1K_4R599 *1K_4 R547 10K_4R547 10K_4 R313 *100K_4R313 *100K_4

9/10 change from 10K to 100K

9/28 change to NC

+3VS5 +3VPCU

+3V

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

(+3VS5)

K16

SUSWARN#/SUSPWRDNACK/GPIO30

E20

PWRBTN#

(DSW)

H20

ACPRESENT / GPIO31

(+3VS5)

E10

BATLOW# / GPIO72

A10

RI#

CougarPoint_Rev_0p7

fcbga989-intel-cougarpoint

AJSLH9D0T13

IC CTRL(989P)COUGARPOINT QMVY TOP B/S

PCH PS - AJSLH9D0T13

DMI

FDI

DMI

FDI

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

System Power Management

SLP_LAN# / GPIO29

FDI_FSYNC0 FDI_FSYNC1

DSWVRMEN

INT LVDS & CRT disable (DIS only remove)

+3V

PCH_HSYNC[22] PCH_VSYNC[22]

PD Res place close to PCH PCH to Res routeing 50 ohm Impedance.

Res to connector filter routeing 37.5ohm Impedance.

R202 150/F_4R202 150/F_4 R201 150/F_4R201 150/F_4 R200 150/F_4R200 150/F_4

3/26 DB change net name.

R209 2.2K_4R209 2.2K_4 R197 2.2K_4R197 2.2K_4

R235 2.37K/F_4R235 2.37K/F_4

R204 33_4R204 33_4 R203 33_4R203 33_4

CTRL_CLK CTRL_DATA

LVD_IBG

PCH_HSYNC_R PCH_VSYNC_R

4/29 modify

PCH_CRT_B PCH_CRT_G PCH_CRT_R

FDI_LSYNC0 FDI_LSYNC1

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7

FDI_INT

DPWROK

WAKE#

(+3V)

(+3VS5)

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

(+3VS5)

BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9

BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

AW16 AV12 BC10 AV14 BB10

DSWVREN

A18

R545 *0_4/SR545 *0_4/S

E22

PCIE_WAKE#

CLKRUN#

N14

D10

G10

G16

AP14

K14

PCH_SUSCLK_L

R330 *0_4/SR330 *0_4/S

R620 *0_4/SR620 *0_4/S

R308 *0_4R308 *0_4

R574 *0_4R574 *0_4

SLP_LAN#

DPB_LANE0_N DPB_LANE0_P DPB_LANE1_N DPB_LANE1_P DPB_LANE2_N DPB_LANE2_P DPB_LANE3_N DPB_LANE3_P

R294 *0_4/S

INT HDMI Detect Function

R506 0_4R506 0_4 R320 0_4R320 0_4

DPB_HPD_Q

R511

R511 *100K_4

*100K_4

FDI_TXN0 [2] FDI_TXN1 [2] FDI_TXN2 [2] FDI_TXN3 [2] FDI_TXN4 [2] FDI_TXN5 [2] FDI_TXN6 [2] FDI_TXN7 [2]

FDI_TXP0 [2] FDI_TXP1 [2] FDI_TXP2 [2] FDI_TXP3 [2] FDI_TXP4 [2] FDI_TXP5 [2] FDI_TXP6 [2] FDI_TXP7 [2]

FDI_INT [2] FDI_FSYNC0 [2] FDI_FSYNC1 [2] FDI_LSYNC0 [2] FDI_LSYNC1 [2]

R546 *0_4/SR546 *0_4/S

DPWROK

9/9 remove in BOM

+5V

12/13 short

PCIE_WAKE# [24,26,27]

CLKRUN# [29]

TP44TP44

11/12 short

short0402

SLP_S5 [29]

SUSC# [29]

SUSB# [29]

SLP_A# [29]

SLP_SUS# [29]

PM_SYNC [2]

Q45

Q45 *2N7002

*2N7002

R496

R496 *100K_4

*100K_4

RSMRST#

5/12: modify

PCH_SUSCLK [29]

TP39TP39

IN_D2# [22] IN_D2 [22] IN_D1# [22] IN_D1 [22] IN_D0# [22] IN_D0 [22] IN_CLK# [22] IN_CLK [22]

HDMI_HPD_CON [22]

PCH_LVDS_BLON[21]

PCH_DISP_ON[21]

PCH_DPST_PWM[21]

PCH_EDIDCLK[21] PCH_EDIDDATA[21]

3/26 DB change net name.

PCH_LA_CLK#[21]

PCH_LA_CLK[21]

PCH_LA_DATAN0[21] PCH_LA_DATAN1[21] PCH_LA_DATAN2[21]

PCH_LA_DATAP0[21] PCH_LA_DATAP1[21] PCH_LA_DATAP2[21]

PCH_LB_CLK#[21] PCH_LB_CLK[21]

PCH_LB_DATAN0[21] PCH_LB_DATAN1[21] PCH_LB_DATAN2[21]

PCH_LB_DATAP0[21] PCH_LB_DATAP1[21] PCH_LB_DATAP2[21]

PCH_CRT_B[22] PCH_CRT_G[22] PCH_CRT_R[22]

PCH_DDCCLK[22] PCH_DDCDATA[22]

C1013 6.8P/50V_4C1013 6.8P/50V_4 C1014 6.8P/50V_4C1014 6.8P/50V_4 C1015 6.8P/50V_4C1015 6.8P/50V_4

PCH_EDIDCLK PCH_EDIDDAT

CTRL_CLK CTRL_DATA

LVD_IBG

PCH_LA_CLK# PCH_LA_CLK

PCH_LA_DATAN0 PCH_LA_DATAN1 PCH_LA_DATAN2

PCH_LA_DATAP0 PCH_LA_DATAP1 PCH_LA_DATAP2

PCH_LB_CLK# PCH_LB_CLK

PCH_LB_DATAN0 PCH_LB_DATAN1 PCH_LB_DATAN2

PCH_LB_DATAP0 PCH_LB_DATAP1 PCH_LB_DATAP2

R670 0_6R670 0_6 R669 0_6R669 0_6 R671 0_6R671 0_6

R673 0_6R673 0_6 R672 0_6R672 0_6

PCH_HSYNC_R PCH_VSYNC_R

PCH_CRT_B PCH_CRT_G PCH_CRT_R

9/8 EMI(near PCH)

System PWR_OK(CLG)

SYS_PWROK

U8 *TC7SH08FU

*TC7SH08FU

+3VS5

C399 *0.1U/10V_4C399 *0.1U/10V_4

3 5

8/26 A-->B modify

9/6 delete a short net in"EC_PWROK"

R565 330K_4R565 330K_4

+3V_RTC

On Die DSW VR Enable High = Enable (Default)

Low = Disable

PCH_CRT_B PCH_CRT_G PCH_CRT_R

2 1

DSWVREN

TP35TP35

R675 0_6R675 0_6 R674 0_6R674 0_6

EC_PWROK

R319

R319 100K_4

100K_4

Cougar Point (LVDS,DDI)

U24D

J47

M45

P45 T40

K47 T45

P39

AF37 AF36

AE48 AE47

AK39 AK40

AN48 AM47 AK47

AJ48

AN47 AM49 AK49

AJ47

AF40 AF39

AH45 AH47 AF49 AF45

AH43 AH49 AF47 AF43

N48 P49 T49

T39

M40

M47 M49

DAC_IREF

T43 T42

R227

R227 1K/F_4

1K/F_4

R568 *330K_4R568 *330K_4

L_BKLTEN L_VDD_EN

L_BKLTCTL L_DDC_CLK

L_DDC_DATA L_CTRL_CLK

L_CTRL_DATA LVD_IBG

LVD_VBG LVD_VREFH

LVD_VREFL

LVDSA_CLK# LVDSA_CLK

LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3

LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3

LVDSB_CLK# LVDSB_CLK

LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3

LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3

CRT_BLUE CRT_GREEN CRT_RED

CRT_DDC_CLK CRT_DDC_DATA

CRT_HSYNC CRT_VSYNC

DAC_IREF CRT_IRTN

CougarPoint_Rev_0p7

fcbga989-intel-cougarpoint

AJSLH9D0T13

IC CTRL(989P)COUGARPOINT QMVY TOP B/S

PCH PS - AJSLH9D0T13

LVDS

CRT

DPWROK FOR DSWINT HDMI disable (DIS only remove)

IMVP_PWRGD [39]

+3VS5

+3VPCU

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

5/12: modify

D21

*RB500V-40

*RB500V-40 D20

D20

*RB500V-40

NB5

SDVO_STALLN

SDVO_STALLP

AP43

AP45 AM42

AM40 AP39

SDVO_INTN

AP40

SDVO_INTP

P38 M39

DDPB_AUXN DDPB_AUXP

DDPC_AUXN DDPC_AUXP

DDPD_AUXN DDPD_AUXP

AT49 AT47 AT40

DDPB_HPD

AV42

DDPB_0N

AV40

DDPB_0P

AV45

DDPB_1N

AV46

DDPB_1P

AU48

DDPB_2N

AU47

DDPB_2P

AV47

DDPB_3N

AV49

DDPB_3P

P46 P42

AP47 AP49 AT38

DDPC_HPD

AY47

DDPC_0N

AY49

DDPC_0P

AY43

DDPC_1N

AY45

DDPC_1P

BA47

DDPC_2N

BA48

DDPC_2P

BB47

DDPC_3N

BB49

DDPC_3P

M43 M36

AT45 AT43 BH41

DDPD_HPD

BB43

DDPD_0N

BB45

DDPD_0P

BF44

DDPD_1N

BE44

DDPD_1P

BF42

DDPD_2N

BE42

DDPD_2P

BJ42

DDPD_3N

BG42

DDPD_3P

+3V_DSW

Q48

Q48 *PDTC144EU

*PDTC144EU

PROJECT : TWH

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev Custom

Custom

PCH 1/6 (Host/Display)

Date: Sheet

SDVO_CLK [22] SDVO_DATA [22]

DPB_HPD_Q DPB_LANE0_N

DPB_LANE0_P DPB_LANE1_N DPB_LANE1_P DPB_LANE2_N DPB_LANE2_P DPB_LANE3_N DPB_LANE3_P

+3VPCU

R554

R554 *10K_4

*10K_4

1 3

R553

R553 *10K_4

*10K_4

Q49

Q49 *2N7002

*2N7002

+3VS5[2,7,8,9,10,14,24,29,31,33,35,36,38]

+3VPCU[7,21,27,28,29,30,31]

+3V_DSW[7,10]

+3V_RTC[7,10,29]

+5V[7,10,21,22,23,27,28,36] +3V[2,7,8,9,10,12,13,14,21,22,23,24,25,26,27,28,29,34,36,37,39]

DPWROK

C595

C595 *0.1U/10V_4

*0.1U/10V_4

add cap to timing tune

6 40Tuesday, December 14, 2010

INT. HDMI

Cougar Point (HDA,JTAG,SATA)

U24A

RTC_X1 RTC_X2 RTC_RST# SRTC_RST#

R281 1M_4R281 1M_4

D D

+3V_RTC

SPKR[23]

ACZ_SDIN0[23]

TP1004TP1004

SM_INTRUDER# PCH_INVRMEN

ACZ_BCLK ACZ_SYNC SPKR ACZ_RST#

9/3 delete net "ACZ_SDIN1"

+3VSUS

R5001 10K/F_4R5001 10K/F_4

USB3_SMI#[26]

C C

+3VPCU

B B

PCH Strap Table

Pin Name Strap description Sampled Configuration

SPKR

12/13 moved from p.26

11/12 short

TP47TP47 TP50TP50 TP51TP51 TP52TP52

PCH_SPI_CLK[29]

PCH_SPI_CS0#[29]

R641 *10K_4R641 *10K_4

PCH_SPI_SI[29]

PCH_SPI_SO[29]

Different from Calpella

ACZ_SDOUT

GPIO33

R652 *0_4/SR652 *0_4/S

PCH_JTAG_TCK_R PCH_JTAG_TMS PCH_JTAG_TDI_R PCH_JTAG_TDO_R

PCH_SPI_CLK PCH_SPI_CS0# PCH_SPI_CS1#

PCH_SPI_SI PCH_SPI_SO

No reboot mode setting PWROK

GNT3# / GPIO55 Top-Block Swap Override INTVRMEN Integrated 1.05V VRM enable ALWAYS

Flash Descriptor Security

HDA_DOCK_EN#/GPIO33 GNT1# / GPIO51

GPIO19

Different from Calpella

GNT2# / GPIO53 NV_ALE

NV_CLE

A A

HDA_SYNC On-Die PLL VR Voltage Select RSMRST

Only for Interposer

Boot BIOS Selection 1 [bit-1] Boot BIOS Selection 0 [bit-0] ESI strap (Server only)

Intel Anti-Theft HDD protection

Only for Interposer

DMI Termination voltage

HDA_SDO PWROKFlash Descriptor Security

GPIO8

GPIO28

Different from Calpella

Integrated Clock Chip Enable Should be pull-down (weak pull-up 20K)RSMRST# On-die PLL Voltage Regulator RSMRST#

SPI_MOSI iTPM function Disable APWROK

U24A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

(+3V)

C36

HDA_DOCK_EN# / GPIO33

(+3VS5)

N32

HDA_DOCK_RST# / GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

SPI_CLK

Y14

SPI_CS0#

SPI_CS1#

SPI_MOSI

SPI_MISO

CougarPoint_Rev_0p7

fcbga989-intel-cougarpoint

AJSLH9D0T13

IC CTRL(989P)COUGARPOINT QMVY TOP B/S

PWROK

PWROK PWROK PWROK PWROK PWROK 0 = Disable (Internal pull-down 20kohm)

PWROK

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

LPC

FWH4 / LFRAME#

RTCIHDA

SPI JTAG

LDRQ0#

LDRQ1# / GPIO23

(+3V)

SERIRQ

SATA0RXN SATA0RXP SATA0TXN

SATA0TXP

SATA1RXN SATA1RXP

SATA 6G

SATA1TXN

SATA1TXP

SATA2RXN SATA2RXP SATA2TXN

SATA2TXP

SATA3RXN SATA3RXP SATA3TXN

SATA3TXP

SATA

SATA4RXN SATA4RXP SATA4TXN

SATA4TXP

SATA5RXN SATA5RXP SATA5TXN

SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED#

(+3V)

SATA0GP / GPIO21

(+3V)

SATA1GP / GPIO19

PCH PS - AJSLH9D0T13

0 = Default (weak pull-down 20K)

1 = Setting to No-Reboot mode

0 = "top-block swap" mode

1 = Default (weak pull-up 20K) Should be always pull-up

0 = Override

1 = Default (weak pull-up 20K)

GNT0#GNT1#

11 00

Should not be pull-down (weak pull-up 20K)

weak pull-down 20kohm

0 = Support by 1.8V (weak pull-down) 1 = Support by 1.5V

0 = Override

1 = Default (weak pull-up 20K)

0 = Disable

1 = Enable (Default) 0 = Default (weak pull-down 20K)

1 = Enable

4/29 DB change net name.

C38 A38 B37 C37

D36 E36

K36 V5

AM3 AM1 AP7 AP5

AM10 AM8 AP11 AP10

AD7 AD5 AH5 AH4

AB8 AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11 Y10

AB12 AB13

AH1

P3 V14 P1

Boot Location

3/26 DB change net name.

LAD0 [27,29] LAD1 [27,29] LAD2 [27,29] LAD3 [27,29]

PCH_DRQ#0 PCH_DRQ#1

SERIRQ

SATA_RXN0_C SATA_RXP0_C SATA_TXN0_C SATA_TXP0_C

SATA_RXN1_C SATA_RXP1_C SATA_TXN1_C SATA_TXP1_C

LFRAME# [27,29]

TP37TP37 TP36TP36

R324 8.2K_4R324 8.2K_4

8/26 A-->B modify

8/31 delete excess AC coupling C C635,C634,C409,C410 C404,C405,C633,C632

DG recommended that AC coupling capacitors should be close to the connector (<100 mils) for optimal signal quality.

3/26 DB modify for placement.

SATA_COMP

SATA3_COMP

SATA3_RBIAS

BBS_BIT0

SPI

LPC

R302 37.4/F_4R302 37.4/F_4

R303 49.9/F_4R303 49.9/F_4

R606 750/F_4R606 750/F_4

R640 10K_4R640 10K_4 R321 10K_4R321 10K_4

+3V

SPKR

R518 *1K_4R518 *1K_4 R514 10K_4R514 10K_4

PCH_INVRMEN

GPIO33

[Need external pull-down for LPC BIOS] Default weak pull-up on GNT0/1#

USE GPIO PIN

+1.8V

4/29 modify

8/26 A-->B modify

+1.8V

+3VS5

PCH_SPI_SI

R616 2.2K_4R616 2.2K_4

GPIO33_E[29]

+3V SERIRQ [29]

SATA_RXN0 [28] SATA_RXP0 [28] SATA_TXN0 [28] SATA_TXP0 [28]

SATA_RXN1 [28] SATA_RXP1 [28] SATA_TXN1 [28] SATA_TXP1 [28]

HDD0 (SATA3 6.0Gb/s)

ODD (SATA1 1.5Gb/s)

10/8 add for EMI

+1.05V

SATA_LED# [27]

BIT_CLK_AUDIO[23]

ACZ_SYNC_AUDIO[23]

10/8 Intel PDG

Circuit

R636 *1K_4R636 *1K_4

R566 330K_4R566 330K_4

R540 *1K_4R540 *1K_4

R602 *1K_4R602 *1K_4 R513 *1K_4R513 *1K_4

R608 *1K_4R608 *1K_4

R215 1K_4R215 1K_4

R611 *1K_4R611 *1K_4

R617 *1K_4R617 *1K_4

R604 1K_4R604 1K_4

+3V

PCI_GNT3# [8]

Bios request, for can't boot Capella 4/23.

+3V_RTC

8/26 A-->B modify

GPIO33_E [29]

BBS_BIT0

BBS_BIT1 [8]

R607 4.7K_4R607 4.7K_4

ACZ_SDOUT

NV_ALE [8]

ACZ_SYNC

R544 *1K_4R544 *1K_4

4/29 reserve.

ICC_EN# [9]

PLL_ODVR_EN [9]

+3V

NV_CLE [8] H_SNB_IVB# [2]

C2001

10P/50V_4

R520 33_4R520 33_4

R2005

1M_4

N.A at CPT EDS 0.7

+V3.3A_1.5A_HDA_IO

RTC Circuitry(RTC)

5/12: modify

R273 *0_6R273 *0_6

+3V_DSW

R286 *0_6/SR286 *0_6/S

+3VPCU

+3V_RTC_0

R275 1K_4R275 1K_4

CN17

CN17 BAT_CONN

BAT_CONN

11/12 short

RTC Power trace width 20mils.

R242 33_4R242 33_4

+5V

ACZ_SDOUT_AUDIO[23]

Vender EON Winbond

ACZ_BCLK

R503 10K_4R503 10K_4

ACZ_RST#_AUDIO[23]

9/3 delete MDC function support "ACZ_BCLK"-R246-"BIT_CLK_MDC" "ACZ_SYNC"-R214-"ACZ_SYNC_MDC" "ACZ_RST#"-R527-"ACZ_RST#_MDC" "ACZ_SDOUT"-R539-"ACZ_SDOUT_MDC"

Size 4MB 4MB

Socket

PCH_SPI_CS0# PCH_SPI_CLK PCH_SPI_SI PCH_SPI1_SI_R PCH_SPI_SO

R603 *0_4R603 *0_4 R628 *0_4R628 *0_4 R548 *0_4R548 *0_4

FOR DSW

+3V_RTC_2 +3V_RTC_1

10P/50V_4

C557

R522 33_4R522 33_4 R535 33_4R535 33_4

P/N AKE39FN0Q00 (EN25F32-100HIP)

AKE391P0N00 (W25Q32BVSSIG)

DG008000031

R549 *3.3K_4R549 *3.3K_4

+3V

RTC Clock 32.768KHz

C602 18P/50V_4C602 18P/50V_4

C601 18P/50V_4C601 18P/50V_4

30mils

+3V_RTC

D10

D10 BAT54C

BAT54C

32.768KHZ

4 1

R298

20K/F_4

R297

R297 20K/F_4

20K/F_4

C389

C389 1U/6.3V_4

1U/6.3V_4

4/20 DB add.

RTC_X1

R567

R567 10M_4

10M_4

RTC_X2

C390

C390 1U/6.3V_4

1U/6.3V_4

C387

C387 1U/6.3V_4

1U/6.3V_4

R280 *0_6R280 *0_6

SRTC_RST#RTC_RST#

PCH JTAG Debug(CLG)HDA Bus(CLG)

R343

R343 *210/F_4

*210/F_4

R327

R327 *100/F_4

*100/F_4

5/3 : modify

4/29: modify

R358

R358 *210/F_4

*210/F_4

PCH_JTAG_TMS PCH_JTAG_TDO_R

R346

R346 *100/F_4

*100/F_4

R347

R347 *210/F_4

*210/F_4

R331

R331 *100/F_4

*100/F_4

+3VS5

Q46

Q46 2N7002K

2N7002K

ACZ_SYNC

ACZ_RST# ACZ_SDOUT PCH_JTAG_TDI_R

10/13 remove all R (Intel confirmed)

PCH SPI ROM(CLG)

U22

PCH_SPI1_CLK_R PCH_SPI1_SO_R

C645

C645 *22P/50V_4

*22P/50V_4

NB5

CE#

SCK

WP#

*SPI Flash Socket

PROJECT : TWH

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev Custom

Custom

PCH 2/6 (HDA/RTC/SATA/SPI)

Date: Sheet

VDD

HOLD#

VSS

R517 *3.3K_4R517 *3.3K_4

7 4

+V3.3A_1.5A_HDA_IO[10]

*0.1U/10V_4

RTC_RST#

J2 *SOLDERJUMPER-2

*SOLDERJUMPER-2

SRTC_RST#

J1 *SOLDERJUMPER-2

*SOLDERJUMPER-2

PCH_JTAG_TCK_R

R329

R329 *51_4

*51_4

+3V

C559

+3V[2,6,8,9,10,12,13,14,21,22,23,24,25,26,27,28,29,34,36,37,39]

+3VPCU[6,21,27,28,29,30,31]

+3V_DSW[6,10]

+3V_RTC[6,10,29]

+1.8V[4,10,36,38]

7 40Wednesday, December 15, 2010

R198 8.2K_4R198 8.2K_4 R531 8.2K_4R531 8.2K_4 R234 8.2K_4R234 8.2K_4 R238 8.2K_4R238 8.2K_4

+3V

RP12

9 8 7 4

10K_10P8R_6

RP13

9 8 7 4

10K_10P8R_6

Low = MPC ON High = MPC OFF (Default)

R521 *1K_4R521 *1K_4

BBS_BIT1[7]

PCI_GNT3#[7]

LCD_BK[21]

DGPU_IDLE_INT#

TP76TP76 TP34TP34

CLK_PCI_FB

R213 22_4R213 22_4

R225 22_4R225 22_4

C1012

C1012 18P/50V_4

18P/50V_4

+3VS5

C406 *0.1U/10V_4C406 *0.1U/10V_4

3 5

*TC7SH08FU

PLTRST# [2,14,24,26,27,29]

+3V

3/26 DB change Part reference.

PCH_GPIO4

1 2

BT_COMBO_EN#

3 56

3/26 DB change Part reference.

USB_OC6#

USB_OC0#

USB_OC7#

USB_OC5#USB_OC2#

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

BT_COMBO_EN#

BBS_BIT1 PCI_GNT3# MPC_PWR_CTRL#

LCD_BK

PCH_GPIO4

11/8 delete R2001

TP46TP46

PCI_PLTRST#

CLK_PCI_TPM_R CLK_PCI_CARD_R

R230 22_4R230 22_4

CLK_PCI_FB_R

CLK_PCI_LPC_R

CLK_PCI_EC_R

9/8 EMI(near PCH)

PLTRST#

4/29 modify

R338

R338 100K_4

100K_4

Cougar Point-M (PCI,USB,NVRAM)

U24E

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

B21

PCI_PME#

TP21

M20

TP22

AY16

TP23

BG46

TP24

BE28

TP25

BC30

TP26

BE32

TP27

BJ32

TP28

BC28

TP29

BE30

TP30

BF32

TP31

BG32

TP32

AV26

TP33

BB26

TP34

AU28

TP35

AY30

TP36

AU26

TP37

AY26

TP38

AV28

TP39

AW30

TP40

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1# / GPIO50

C44

REQ2# / GPIO52

E40

REQ3# / GPIO54

D47

GNT1# / GPIO51

E42

GNT2# / GPIO53

F46

GNT3# / GPIO55

G42

PIRQE# / GPIO2

G40

PIRQF# / GPIO3

C42

PIRQG# / GPIO4

D44

PIRQH# / GPIO5

K10

PME#

PLTRST#

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

CougarPoint_Rev_0p7

fcbga989-intel-cougarpoint

AJSLH9D0T13

IC CTRL(989P)COUGARPOINT QMVY TOP B/S

PCH PS - AJSLH9D0T13

4/20 modify

MBDATA2[13,17,29]

SMB_PCH_DAT

Q44

Q44 2N7002

2N7002

SMB_PCH_CLK

RSVD

PCI

(+3V) (+3V) (+3V)

(+3V) (+3V) (+3V) (+3V)

(+3VS5) (+3VS5) (+3VS5) (+3VS5) (+3VS5) (+3VS5) (+3VS5) (+3VS5)

SMBus/Pull-up(CLG)

2N7002

MBCLK2[13,17,29]

Q50

+3V

Q51

2N7002

+3V

2 2

Q43

Q43 2N7002

2N7002

R487 4.7K_4R487 4.7K_4 R486 4.7K_4R486 4.7K_4

11/8 change net name to "PCH_GPIO4" delete "DGPU_IDLE_INT#" pull-hi

PCI/USBOC# Pull-up(CLG)

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

D D

MPC_PWR_CTRL#

LCD_BK

+3VS5

USB_OC4# USB_OC1#

USB_OC3#

MPC Switch Control

MPC_PWR_CTRL#

C C

BT_COMBO_EN#[27]

DGPU_IDLE_INT#[17]

B B

9/5 remove R213 in BOM

CLK_33M_KBC[29]

C1011

18P/50V_4

PLTRST#(CLG)

A A

PCI_PLTRST#

R352

R352 0_4

0_4

2 1

PLTRST#

NV_DQ0 / NV_IO0 NV_DQ1 / NV_IO1 NV_DQ2 / NV_IO2 NV_DQ3 / NV_IO3 NV_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8

NV_DQ9 / NV_IO9 NV_DQ10 / NV_IO10 NV_DQ11 / NV_IO11

NVRAM

NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15

NV_RCOMP

NV_RE#_WRB0 NV_RE#_WRB1

NV_WE#_CK0 NV_WE#_CK1

USB

USBRBIAS#

USBRBIAS

OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43

OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14

SMB_ME1_CLK

R586 2.2K_4R586 2.2K_4

R587 2.2K_4R587 2.2K_4

SMB_ME1_DAT

SMB_RUN_DAT [12,13]

SMB_RUN_CLK [12,13]

NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3

NV_DQS0 NV_DQS1

NV_ALE NV_CLE

NV_RB#

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P

USBP10N

USBP10P

USBP11N

USBP11P

USBP12N

USBP12P

USBP13N

USBP13P

+3VS5

AY7 AV7 AU3 BG4

AT10 BC8

AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6

NV_ALE

AV5

NV_CLE

AY1 AV10 AT8 AY5

BA2 AT12

BF3

C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29

HM65 Port6 & Port7

N28

are disable

M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32

USB_BIAS

C33

B33

USB_OC0#

A14

USB_OC1#

K20

USB_OC2#

B17

USB_OC3#

C16

USB_OC4#

L16

USB_OC5#

A16

USB_OC6#

D14

USB_OC7#

C14

PCIE_RXN1[27] PCIE_RXP1[27]

WLAN

LAN

USB3.0

NV_ALE [7] NV_CLE [7]

PCIE_TXN1[27] PCIE_TXP1[27]

PCIE_RXN2_LAN[24]

PCIE_RXP2_LAN[24] PCIE_TXN2_LAN[24] PCIE_TXP2_LAN[24]

PCIE_RXN3_USB3[26] PCIE_RXP3_USB3[26]

PCIE_TXN3_USB3[26] PCIE_TXP3_USB3[26]

8/26 A-->B modify

USBP1- [23] USBP1+ [23] USBP2- [26] USBP2+ [26]

USBP4- [26] USBP4+ [26]

TP1001TP1001

TP1002TP1002

USBP9- [21] USBP9+ [21] USBP10- [27] USBP10+ [27]

USBP12- [25] USBP12+ [25]

R541

22.6/F_4

9/4 Change net name "BOARD_ID1" to "INT_BT_COMBO_EN#"

CLK_REQ/Strap Pin(CLG)

10/10 R638 mount

CLK_PCIE_REQ1# CLK_PCIE_REQ2#

CLK_PCIE_REQ0# CLK_PCIE_REQ3# CLK_PCIE_REQ4#

CLK_PEGB_REQ# CLK_PEGA_REQ#

SG : Rb ; UMA : Ra

CLK_PEGA_REQ# CLK_PEGB_REQ#

CLK_BUF_BCLK_N CLK_BUF_BCLK_P

CLK_BUF_PCIE_3GPLL# CLK_BUF_PCIE_3GPLL CLK_BUF_DREFCLK# CLK_BUF_DREFCLK CLK_BUF_DREFSSCLK# CLK_BUF_DREFSSCLK CLK_PCH_14M

USB2.0 USB2.0

USB2.0

Bluetooth Camera WLAN

Card Reader

R638 10K_4R638 10K_4 R323 10K_4R323 10K_4

R597 10K_4R597 10K_4 R612 10K_4R612 10K_4 R287 10K_4R287 10K_4

R360 *10K_4R360 *10K_4 R344 *10K_4R344 *10K_4

R328 *10K_4R328 *10K_4

R1111 10K_4R1111 10K_4 R556 10K_4R556 10K_4

R558 10K_4R558 10K_4 R291 10K_4R291 10K_4

R295 10K_4R295 10K_4 R258 10K_4R258 10K_4 R262 10K_4R262 10K_4 R315 10K_4R315 10K_4 R314 10K_4R314 10K_4 R216 10K_4R216 10K_4

EXTERNAL USB2.0 USB2.0/USB3.0 COMBO

USB2.0/USB3.0 COMBO

9/3 delete BT function (USB) delete net "USB8+/-"

CLOCK TERMINATION for FCIM

C385 0.1U/10V_4C385 0.1U/10V_4 C379 0.1U/10V_4C379 0.1U/10V_4

C345 0.1U/10V_4C345 0.1U/10V_4 C353 0.1U/10V_4C353 0.1U/10V_4

C355 0.1U/10V_4C355 0.1U/10V_4 C358 0.1U/10V_4C358 0.1U/10V_4

8/26 A-->B modify

Bios swap GPIO 4/23.Bios swap GPIO 4/23.

INT_BT_COMBO_EN#[27]CLK_33M_DEBUG[27]

+3V

+3VS5

Cougar Point-M (PCI-E,SMBUS,CLK)

PCIE_TXN1_C PCIE_TXP1_C

PCIE_TXN2_LAN_C PCIE_TXP2_LAN_C

PCIE_TXN3_USB3_C PCIE_TXP3_USB3_C

CLK_PCH_SRC0N CLK_PCH_SRC0P

CLK_PCIE_REQ0#

CLK_PCH_SRC2N CLK_PCH_SRC2P

CLK_PCIE_REQ1#

CLK_PCIE_REQ2#

CLK_PCIE_REQ3#

CLK_PCIE_REQ4#

BOARD_ID0[9]

CLK_PCH_PEGBN CLK_PCH_PEGBP

CLK_PEGB_REQ#

BOARD_ID2[9]

TP41TP41 TP38TP38

CLK_PCH_ITPN CLK_PCH_ITPP

PCH PS - AJSLH9D0T13

PCIE Clock

WLAN

LAN

GPU

USB3.0

CLK_PCIE_WLANN[27] CLK_PCIE_WLANP[27]

PCIE_CLKREQ_WLAN#[27]

CLK_PCIE_LANN[24]

CLK_PCIE_LANP[24]

PCIE_CLKREQ_LAN#[24]

CLK_PCIE_VGA#[14]

PCIE_CLKREQ_VGA#[14]

CLK_PCIE_USB3N[26] CLK_PCIE_USB3P[26]

11/11 delete R359

CLK_PCIE_VGA[14]

U24B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

PCIECLKRQ0# / GPIO73

(+3VS5)

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

PCIECLKRQ1# / GPIO18

(+3V)

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GPIO20

(+3V)

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

PCIECLKRQ3# / GPIO25

(+3VS5)

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GPIO26

(+3VS5)

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GPIO44

(+3VS5)

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

PEG_B_CLKRQ# / GPIO56

(+3VS5)

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GPIO45

(+3VS5)

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GPIO46

(+3VS5)

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

CougarPoint_Rev_0p7

fcbga989-intel-cougarpoint

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

PCI-E*

CLOCKS

AJSLH9D0T13

IC CTRL(989P)COUGARPOINT QMVY TOP B/S

3/26 DB change Part reference.

R621 *0_4/SR621 *0_4/S

3/26 DB change Part reference.

RP6

0_4P2R_04

R637 *0_4/SR637 *0_4/S

3/26 DB change Part reference.

RP5

0_4P2R_04

R345 *0_4/SR345 *0_4/S

RP8

0_4P2R_04

IC CTRL(989P)COUGARPOINT QMVY TOP B/S

CLK_PCH_SRC0N CLK_PCH_SRC0P CLK_PCIE_REQ0#

CLK_PCH_SRC2N

CLK_PCH_SRC2P

CLK_PCIE_REQ1#

CLK_PCH_PEGAN

CLK_PCH_PEGAP

CLK_PEGA_REQ#

CLK_PCH_PEGBN

CLK_PCH_PEGBP

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML1CLK / GPIO58

SML1DATA / GPIO75

Link

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N CLKOUT_DP_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_GND1_N CLKIN_GND1_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_SATA_N CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64 CLKOUTFLEX1 / GPIO65 CLKOUTFLEX2 / GPIO66 CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

12/13 delete RP7

12/13 short

+3V[2,6,7,9,10,12,13,14,21,22,23,24,25,26,27,28,29,34,36,37,39]

+3VS5[2,6,7,9,10,14,24,29,31,33,35,36,38]

(+3VS5)

SMBCLK

SMBDATA

(+3VS5)

SML0CLK

SML0DATA

(+3VS5) (+3VS5)

(+3VS5)

CL_CLK1

CL_DATA1

CL_RST1#

(+3VS5)

XTAL25_IN

(+3V) (+3V)

SMBALERT#

E12

SMB_PCH_CLK

H14

SMB_PCH_DAT

DRAMRST_CNTRL_PCH

A12

SMB_ME0_CLK

SMB_ME0_DAT

G12

SML1ALERT#_R

C13

SMB_ME1_CLK

E14

SMB_ME1_DAT

M16

CL_CLK_R

CL_DAT_R

T11

CL_RST#_R

P10

CLK_PEGA_REQ#

M10

CLK_PCH_PEGAN

AB37

CLK_PCH_PEGAP

AB38

AV22 AU22

AM12 AM13

CLK_BUF_PCIE_3GPLL#

BF18

CLK_BUF_PCIE_3GPLL

BE18

CLK_BUF_BCLK_N

BJ30

CLK_BUF_BCLK_P

BG30

CLK_BUF_DREFCLK#

G24

CLK_BUF_DREFCLK

E24

CLK_BUF_DREFSSCLK#

AK7

CLK_BUF_DREFSSCLK

AK5

CLK_PCH_14M

K45

CLK_PCI_FB

H45

XTAL25_IN

V47

XTAL25_OUT

V49

XCLK_RCOMP

Y47

CLK_FLEX0

K43

CLK_FLEX1

F47

CLK_FLEX2

H47

CLK_FLEX3

K49

DRAMRST_CNTRL_PCH [2]

TP40TP40

TP43TP43

TP48TP48

TP49TP49

CLK_CPU_BCLKN [2] CLK_CPU_BCLKP [2]

CLK_DPLL_SSCLKN [2] CLK_DPLL_SSCLKP [2]

3/26 DB del external clock generator.

C311

C311 18P/50V_4

18P/50V_4

R206

R206 1M_4

1M_4

R502 90.9/F_4R502 90.9/F_4

R211 22_4R211 22_4 R205 22_4R205 22_4

R3025 *22_4R3025 *22_4

TP2002TP2002

Remove Ra, Rb for UMA & SG. 27MHz support DIS only.

SMBus/Pull-up(CLG)

+3VS5

R333 1K_4R333 1K_4 R282 10K_4R282 10K_4

R351 2.2K_4R351 2.2K_4 R337 2.2K_4R337 2.2K_4 R634 2.2K_4R634 2.2K_4 R292 2.2K_4R292 2.2K_4 R289 10K_4R289 10K_4

Size Document Number Rev

Size Document Number Rev Custom

Custom

NB5

Date: Sheet

8/26 A-->B modify change FP

25MHZY125MHZ

C312

C312 18P/50V_4

18P/50V_4

+1.05V

CLK_48M_CR [25]

C2002

C2002 10P/50V_4

10P/50V_4

9/11 add R1015, exchange 27M net

10/8 remove 27M circuit

DRAMRST_CNTRL_PCH SMBALERT#

SMB_PCH_CLK SMB_PCH_DAT SMB_ME0_CLK SMB_ME0_DAT SML1ALERT#_R

PROJECT : TWH

Quanta Computer Inc.

PCH 3/6 (Clock/PCI/PCIE/USB)

CLK_25M_USB3.0 [26]

10/8 add for EMI

8 40Tuesday, December 14, 2010

Cougar Point (GPIO,VSS_NCTF,RSVD)

Cougar Point (GPIO,VSS_NCTF,RSVD)Cougar Point (GPIO,VSS_NCTF,RSVD)

U24F

S_GPIO

R363 100_4R363 100_4

SIO_EXT_SMI#[29]

9/3 delete net "BT_OFF#"

D D

Reserve

SIO_EXT_SCI#[29]

ICC_EN#[7]

RF_OFF#[27]

ODD_PRSNT#[28]

DGPU_PWROK[14,29,37]

4/29 modify

TP1003TP1003

R627 *0_4R627 *0_4

R676 0_4R676 0_4

8/26 A-->B modify

DGPU_HOLD_RST#[14,29]

PLL_ODVR_EN[7]

DGPU_PWR_EN[29,37,38]

C C

SATA5GP[29]

R677 0_4R677 0_4

R618 0_4R618 0_4

R353 0_4R353 0_4

SIO_EXT_SMI# SIO_EXT_SCI# BT_OFF# ICC_EN#ICC_EN#ICC_EN#ICC_EN#ICC_EN#ICC_EN#ICC_EN#ICC_EN#ICC_EN#ICC_EN# LAN_DISABLE#_R RF_OFF#

ODD_PRSNT#_R

BIOS_REC BOARD_ID5 GPIO27 PLL_ODVR_EN_R BOARD_ID3 BOARD_ID4 DGPU_PWR_EN_R FDI_OVRVLTG MFG_MODE DGPU_PRSNT# TEST_SET_UP SATA5GP SV_DET

OPTIMUS POWER control pin DGPU_PWROK DGPU_HOLD_RST# DGPU_PWR_EN

B B

GPIO17 GPIO24 GPIO36

U24F

BMBUSY# / GPIO0

(+3V)

A42

TACH1 / GPIO1

(+3V)

H36

TACH2 / GPIO6

(+3V)

E38

TACH3 / GPIO7

(+3V)

C10

GPIO8

(+3VS5)

LAN_PHY_PWR_CTRL / GPIO12

(+3VS5)

GPIO15

(+3VS5)

SATA4GP / GPIO16

(+3V)

D40

TACH0 / GPIO17

(+3V)

SCLOCK / GPIO22

(+3V)

GPIO24 / MEM_LED

(+3VS5)

E16

GPIO27

(DSW)

GPIO28

(+3VS5)

STP_PCI# / GPIO34

(+3V)

GPIO35

(+3V)

SATA2GP / GPIO36

(+3V)

SATA3GP / GPIO37

(+3V)

SLOAD / GPIO38

(+3V)

SDATAOUT0 / GPIO39

(+3V)

V13

SDATAOUT1 / GPIO48

(+3V)

SATA5GP / GPIO49

(+3V)

GPIO57

(+3VS5)

VSS_NCTF_1

A44

VSS_NCTF_2

A45

VSS_NCTF_3

A46

VSS_NCTF_4

VSS_NCTF_5

VSS_NCTF_6

VSS_NCTF_7

B47

VSS_NCTF_8

BD1

VSS_NCTF_9

BD49

VSS_NCTF_10

BE1

VSS_NCTF_11

BE49

VSS_NCTF_12

BF1

VSS_NCTF_13

BF49

VSS_NCTF_14

CougarPoint_Rev_0p7

fcbga989-intel-cougarpoint

AJSLH9D0T13

BOARD ID SETTING

0=QLH/TWH 1=QLC/SWH

ID2

ID3 ID4

0=NO 1=YES

ID5

0=UMA 1=Dis.

0=YES 1=NO

1=YES 0=NO

Board ID

ID0

0=LG 1=CB

ID1

UMA/Dis.

15.6"/ 14"

A A

MDC

Dobly

Optiums

TACH4 / GPIO68

(+3V)

TACH5 / GPIO69

(+3V)

TACH6 / GPIO70

(+3V)

TACH7 / GPIO71

(+3V)

A20GATE

PECI

RCIN#

PROCPWRGD

NCTF

CPU/MISC

VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23 VSS_NCTF_24 VSS_NCTF_25 VSS_NCTF_26 VSS_NCTF_27 VSS_NCTF_28 VSS_NCTF_29 VSS_NCTF_30 VSS_NCTF_31 VSS_NCTF_32

THRMTRIP#

INIT3_3V#

NC_1 NC_2 NC_3 NC_4 NC_5

GPIO

IC CTRL(989P)COUGARPOINT QMVY TOP B/S

PCH PS - AJSLH9D0T13

BOARD_ID0[8] BOARD_ID2[8]

R632 *10K_4R632 *10K_4

R356 *10K_4R356 *10K_4

R589 10K_4R589 10K_4

R598 *10K_4R598 *10K_4

R622 10K_4R622 10K_4

R348 *10K_4R348 *10K_4

10/11 correct board ID

RF_PWR_OFF# [27]

9/6 add "RF_PWR_OFF#" control from PCH

C40 B41 C41 A40

P4 AU16 P5 AY11 AY10 T14

AH8 AK11 AH10 AK10 P37

GPIO68 GPIO69

GPIO71

EC_RCIN#

PCH_THRMTRIP#

R529 *10K_4R529 *10K_4 R3017 R525 1.5K/F_4R525 1.5K/F_4

R524 *1.5K/F_4R524 *1.5K/F_4

DGPU_OPT_DIS#

R311 390_4R311 390_4

20101012 modify:

1. Delete TACH0.

2. GPIO70 connect DGPU optimus / discrete setting.

R307 0_4R307 0_4

+3V

11/12 modify Delete net "GPIO70",connect DGPU optimus / discrete circuit

EC_A20GATE [29]

EC_RCIN# [29] H_PWRGOOD [2] PM_THRMTRIP# [2,29]

DG rev0.9 suggest to TS_VSS connect to GND 4/23.

BG2 BG48 BH3 BH47 BJ4 BJ44 BJ45 BJ46 BJ5 BJ6 C2 C48 D1 D49 E1 E49 F1 F49

BOARD_ID0 BOARD_ID2

BOARD_ID0

BOARD_ID1

BOARD_ID2

BOARD_ID3

BOARD_ID4

BOARD_ID5

9/6 delete net "BOARD_ID1"

R631 10K_4R631 10K_4

R357 *10K_4R357 *10K_4

R609 *10K_4R609 *10K_4

R623 *10K_4R623 *10K_4

R635 *10K_4R635 *10K_4

R349 *10K_4R349 *10K_4

4/29 modify

+3VS5

+3V

+3VS5

5/11 stuff R9144

Intel ME Crypto Transport Layer Security (TLS) cipher suite

Low = Disable (Default) High = Enable

R339 *0_4R339 *0_4

SV_SET_UP High = Strong (Default)

10/11 no need pull high

DMI TERMINATION VOLTAGE OVERRIDE

R600 *100K_4R600 *100K_4

Clock Gen Power OK (CLG)

3/26 DB del external clock generator.

MFG-TEST

MFG_MODE

Bios swap GPIO 4/23.

S_GPIO

RF_OFF#

TEST_SET_UP

Low = Tx, Rx terminated to same voltage (DC Coupling Mode) (DEFAULT)

R626 10K_4R626 10K_4 R601 *0_4R601 *0_4

R365 10K_4R365 10K_4 R217 *10K_4R217 *10K_4 R364 *0_4R364 *0_4

R596 1K_4R596 1K_4

R322 10K_4R322 10K_4

R340 *200K/F_4R340 *200K/F_4

GFX Present

SG Ra Rb

RaRb

R625 10K_4R625 10K_4

UMA Rb Ra

DGPU_PRSNT#

Stuff NC

+3V

R3017 10K/F_4

10K/F_4

DGPU_OPT_DIS#

DGPU_OPT_DIS#: High : Optimus. Low: Discrete.

R3018

R3018 *10K/F_4

*10K/F_4

GPIO Pull-up/Pull-down(CLG)

+3V

+3VS5

+3V

LAN_DISABLE#_R

SIO_EXT_SCI# SIO_EXT_SMI# BT_OFF# EC_A20GATE EC_RCIN#

+3V

9/3 update net name from "DGPU_VC_EN" to "DGPU_PWROK"

SATA5GP GPIO71

ODD_PRSNT#_R DGPU_PWROK

DGPU_PWROK GPIO27

R341 *0_4R341 *0_4

BIOS RECOVERY High = Disable (Default)

R594 100K_4R594 100K_4

R595 10K_4R595 10K_4

R228 10K_4R228 10K_4 R523 10K_4R523 10K_4 R512 10K_4R512 10K_4 R325 10K_4R325 10K_4 R355 10K_4R355 10K_4 R605 10K_4R605 10K_4

R530 1.5K/F_4R530 1.5K/F_4 R642 10K_4R642 10K_4

R226 *10K_4R226 *10K_4 R296 10K_4R296 10K_4

4/29 modify

BIOS_REC

Low = Enable

SV_DET

TEST DETECT Low = Default

+3V +3V

R326 100K_4R326 100K_4

FDI TERMINATION VOLTAGE OVERRIDE

+3V

NB5

FDI_OVRVLTGDGPU_PWR_EN_R

LOW - Tx, Rx terminated to same voltage

PROJECT : TWH

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev Custom

Custom

PCH 4/6 (GPIO)

Date: Sheet

+3VS5

+3V

10/10 double pull high

R354 10K_4R354 10K_4

R619 *10K_4R619 *10K_4

R342 *1K_4R342 *1K_4

+3V[2,6,7,8,10,12,13,14,21,22,23,24,25,26,27,28,29,34,36,37,39]

+3VS5[2,6,7,8,10,14,24,29,31,33,35,36,38]

11/13 delete "GPIO70" and R528

+3V

+3VS5

9 40Wednesday, December 15, 2010

Cougar Point-M (POWER)

12/13 short

R508 *0_8R508 *0_8

+1.05V

R283 *0_4/SR283 *0_4/S

+3VS5

R288 *0_4R288 *0_4

+3V_DSW

C383

5/12: modify

D D

C383

0.1U/10V_4

10/8 remove for leakage

+1.05V

+1.05V +1.05V_VCCEPW

C C

+VCCAPLL_CPY_PCH

L30

*10uH/100mA_8

R569 *0_6/SR569 *0_6/S

R249

0.002/F_1206

C603

C603 *10U/6.3V_6

*10U/6.3V_6

C351

C351 1U/6.3V_4

1U/6.3V_4

1.01A (60mils)

+VCCACLK

+VCCPDSW

3mA (10mils)

C408

PCH_VCCDSW

*0.1U/10V_4

+3V_SUS_CLKF33

4/29: modify

+VCCDPLL_CPY

+VCCSUS1

C367

C367 *1U/6.3V_4

*1U/6.3V_4

C369

C352

1U/6.3V_4

C340

C340 22U/6.3VS_8

22U/6.3VS_8

C341

C341 22U/6.3VS_8

22U/6.3VS_8

11/12 short

R335 *0_6/SR335 *0_6/S

+1.05V

C407

1U/6.3V_4

R504 *0_6/SR504 *0_6/S

+1.05V

B B

+1.05V

V_PROC_IO=1mA (10mils)

A A

VCCRTC<1mA (10mils)

C542

1U/6.3V_4

R557 *0_6/SR557 *0_6/S

C592

1U/6.3V_4

R293 *0_6R293 *0_6

C374

*1U/6.3V_4

R588 *0_4/S

short0402

+3V_RTC

C621

4.7U/6.3V_6

C386

C386 1U/6.3V_4

1U/6.3V_4

+VCCRTCEXT

C388

0.1U/10V_4

+VCCAFDI_VRM

160mA (20mils)

+1.05V_VCCA_A_DPL

65mA (10mils)

+1.05V_VCCA_B_DPL

8mA (10mils)

+VCCDIFFCLK +VCCDIFFCLKN

55mA (10mils)

+V1.05V_SSCVCC

95mA (10mils)

C384

0.1U/10V_4

+V1.05M_VCCSUS +VTT_VCCPCPU

C617

C613

0.1U/10V_4

C382

C375

0.1U/10V_4

+VCCSST

U24J

AD49

VCCACLK

T16

VCCDSW3_3

V12

DCPSUSBYP

T38

VCC3_3[5]

BH23

VCCAPLLDMI2

AL29

VCCIO[14]

AL24

DCPSUS[3]

AA19

VCCASW[1]

AA21

VCCASW[2]

AA24

VCCASW[3]

AA26

VCCASW[4]

AA27

VCCASW[5]

AA29

VCCASW[6]

AA31

VCCASW[7]

AC26

VCCASW[8]

AC27

VCCASW[9]

AC29

VCCASW[10]

AC31

VCCASW[11]

AD29

VCCASW[12]

AD31

VCCASW[13]

W21

VCCASW[14]

W23

VCCASW[15]

W24

VCCASW[16]

W26

VCCASW[17]

W29

VCCASW[18]

W31

VCCASW[19]

W33

VCCASW[20]

N16

DCPRTC

Y49

VCCVRM[4]

BD47

VCCADPLLA

BF47

VCCADPLLB

AF17

VCCIO[7]

AF33

VCCDIFFCLKN[1]

AF34

VCCDIFFCLKN[2]

AG34

VCCDIFFCLKN[3]

AG33

VCCSSC

V16

DCPSST

T17

DCPSUS[1]

V19

DCPSUS[2]

BJ8

V_PROC_IO

A22

VCCRTC

CougarPoint_Rev_0p7

fcbga989-intel-cougarpoint

AJSLH9D0T13

IC CTRL(989P)COUGARPOINT QMVY TOP B/S

PCH PS - AJSLH9D0T13

+1.8V[4,7,36,38]

+1.5VSUS[2,4,12,13,32,33,38]

+1.05V[6,7,8,26,35]

+3V

R550 *0_4R550 *0_4 R552 *0_4/SR552 *0_4/S

C575

C575 *1U/6.3V_4

*1U/6.3V_4

+3V_DSW[6,7]

+3V_RTC[6,7,29]

R543 *0_8/SR543 *0_8/S

C571

C571 1U/6.3V_4

1U/6.3V_4

119mA (20mils)

R267 *0_6/SR267 *0_6/S

C360

0.1U/10V_4

R264 *0_6/SR264 *0_6/S

C346

0.1U/10V_4

R259 *0_6/SR259 *0_6/S

C365 *1U/6.3V_4C365 *1U/6.3V_4

R290 *0_6/SR290 *0_6/S

C366

C366 1U/6.3V_4

1U/6.3V_4

R332 *0_6/SR332 *0_6/S

C403

0.1U/10V_4

+3V

C338

0.1U/10V_4

R318 *0_8/SR318 *0_8/S

C402

C402 1U/6.3V_4

1U/6.3V_4

L35

L35 *10uH/100mA_8

*10uH/100mA_8 C652

C652 *10U/6.3V_6

*10U/6.3V_6

R362 *0_6/SR362 *0_6/S

C412

C412 1U/6.3V_4

1U/6.3V_4

12/13 short

+5V[6,7,21,22,23,27,28,36]

+5VS5[21,23,26,31,32,33,34,35,36,37,38,39,40]

+3V[2,6,7,8,9,12,13,14,21,22,23,24,25,26,27,28,29,34,36,37,39]

+3VS5[2,6,7,8,9,14,24,29,31,33,35,36,38]

N26

VCCIO[29]

P26

VCCIO[30]

P28

VCCIO[31]

T27

VCCIO[32]

T29

VCCIO[33]

+3V_VCCPUSB

VCCIO[34]

DCPSUS[4]

V5REF

VCC3_3[1] VCC3_3[8] VCC3_3[4]

VCC3_3[2]

VCCIO[5] VCCIO[12] VCCIO[13]

VCCIO[6]

VCCVRM[1]

VCCIO[2]

VCCIO[3]

VCCIO[4]

T23 T24 V23 V24

+3V_VCCAUBG

P24

+VCCAUPLL

T26

+5V_PCH_VCC5REFSUS

M26

+VCCA_USBSUS

AN23

+3V_VCCPSUS

AN24

+5V_PCH_VCC5REF

P34

N20 N22

119mA (15mils)

+3V_VCCPSUS

P20 P22

AA16

266mA (20mils)

+3V_VCCPCORE

W16 T34

AJ2

AF13 AH13 AH14 AF14

+V1.1LAN_VCCAPLL

AK1

+VCCAFDI_VRM

AF11

AC16

+1.05V_VCCIO1

AC17 AD17

1.01A (60mils)

+1.05V_VCCEPW

T21

V21

T19

P32

C400

0.1U/10V_4

+V1.05S_SATA3

10mA (10mils)

+V3.3A_1.5A_HDA_IO

C580

0.1U/10V_4

VCCSUS3_3[7] VCCSUS3_3[8] VCCSUS3_3[9]

VCCSUS3_3[10]

VCCSUS3_3[6]

V5REF_SUS

VCCSUS3_3[1]

VCCSUS3_3[2] VCCSUS3_3[3] VCCSUS3_3[4] VCCSUS3_3[5]

PCI/GPIO/LPCMISC

Clock and Miscellaneous

VCCAPLLSATA

SATA USB

VCCASW[22]

VCCASW[23]

CPURTC

VCCASW[21]

VCCSUSHDA

HDA

+1.05V+1.05V_VCCUSBCORE

+3VS5

+1.05V

11/12 short

+3VS5

+3V

+1.05V

+1.5VSUS +3VS5

+1.05V +1.05V_PCH_VCC

+1.05V +1.05V_VCCAPLL_EXP

+1.05V +1.05V_VCCIO

(Mobile 1.5V)

+1.5V_CPU

+1.05V

12/13 short

+1.05V +VCC_DMI_CCI +1.1V_VCC_DMI_CCI

12/13 short

1.3 A (60mils)

R301

0.002/F_1206

+1.05V_PCH_VCCDPLL_EXP+1.05V

R274

*0_6/S

L31

*1uH/25mA_6

R257

0.002/F_1206

C329

C329 10U/6.3VS_6

10U/6.3VS_6

R564 0_8R564 0_8

R500 *0_6/SR500 *0_6/S R501 *0_6R501 *0_6

+1.05V

L25

L25 10uH/100MA_8

10uH/100MA_8

C350

C350 1U/6.3V_4

1U/6.3V_4

C370

C370 10U/6.3VS_6

10U/6.3VS_6

C604

C604 *10U/6.3V_6

*10U/6.3V_6

2.925 A (140mils)

C330

C330 1U/6.3V_4

1U/6.3V_4

C356

C356 1U/6.3V_4

1U/6.3V_4

+3V_VCC_EXP+3V

160mA (15mils)

+VCCAFDI_VRM

+1.05V

C361

C361 1U/6.3V_4

1U/6.3V_4

C349

C349 1U/6.3V_4

1U/6.3V_4

C334

C334 1U/6.3V_4

1U/6.3V_4

C344

C344 1U/6.3V_4

1U/6.3V_4

C600

0.1U/10V_4

+VCCAFDI_VRM +1.05V_VCCAPLL_FDI

R316 *0_8R316 *0_8 R304 *0_8/SR304 *0_8/S

+1.05V_VCCDPLL_FDI

65mA (10mils)

+1.05V_VCCA_A_DPL

8mA (10mils)

L27

L27 10uH/100MA_8

10uH/100MA_8

+3V

R536 *0_6R536 *0_6 R537 1/F_4R537 1/F_4 C567 10U/6.3VS_6C567 10U/6.3VS_6

+1.05V_VCCA_B_DPL

20mA (10mils)

+3V_SUS_CLKF33 +3V_SUS_CLKF33_R

20mA (10mils)

R591 *1/F_4R591 *1/F_4 R592 *0_4/SR592 *0_4/S

L33

L33 *10uH/100mA_8

*10uH/100mA_8

COUGAR POINT (POWER)

U24G

AA23

VCCCORE[1]

AC23

VCCCORE[2]

AD21

VCCCORE[3]

AD23

VCCCORE[4]

AF21

VCCCORE[5]

AF23

VCCCORE[6]

AG21

VCCCORE[7]

AG23

VCCCORE[8]

AG24

VCCCORE[9]

AG26

VCCCORE[10]

AG27

VCCCORE[11]

AG29

VCCCORE[12]

AJ23

VCCCORE[13]

AJ26

VCCCORE[14]

AJ27

VCCCORE[15]

AJ29

VCCCORE[16]

AJ31

VCCCORE[17]

AN19

VCCIO[28]

BJ22

VCCAPLLEXP

AN16

VCCIO[15]

AN17

VCCIO[16]

AN21

VCCIO[17]

AN26

VCCIO[18]

AN27

VCCIO[19]

AP21

VCCIO[20]

AP23

VCCIO[21]

AP24

VCCIO[22]

AP26

VCCIO[23]

AT24

VCCIO[24]

AN33

VCCIO[25]

AN34

VCCIO[26]

BH29

VCC3_3[3]

AP16

VCCVRM[2]

BG6

VccAFDIPLL

AP17

VCCIO[27]

AU20

VCCDMI[2]

CougarPoint_Rev_0p7

fcbga989-intel-cougarpoint

AJSLH9D0T13

IC CTRL(989P)COUGARPOINT QMVY TOP B/S

C543 1U/6.3V_4C543 1U/6.3V_4

C540 *220U/2.5V_3528

C586 1U/6.3V_4C586 1U/6.3V_4

C576 *220U/2.5V_3528

5/14 modify

C568 1U/6.3V_4C568 1U/6.3V_4

L28

L28 10uH/100MA_8

10uH/100MA_8

11/12 add for CRT wave noise

CRTLVDS

VCC CORE

VCCIO

DMI

NAND / SPI HVCMOS

FDI

PCH PS - AJSLH9D0T13

VCCADAC

VSSADAC

VCCALVDS VSSALVDS

VCCTX_LVDS[1] VCCTX_LVDS[2] VCCTX_LVDS[3] VCCTX_LVDS[4]

VCC3_3[6] VCC3_3[7]

VCCVRM[3]

VCCDMI[1]

VCCCLKDMI

VCCPNAND[1]

VCCPNAND[2]

VCCPNAND[3]

VCCPNAND[4]

VCCSPI

NB5

U3001

+5V +3V_LDO

+VCCA_DAC_1_2

U48

U47

1mA (10mils)

AK36 AK37

AM37 AM38 AP36 AP37

SG & UMA : Ra DIS : Rb

V33 V34

U3001

*G910T21U

Vin3Vout

+3V_LDO

GND

C3009

C3009 *1U/6.3V_4

*1U/6.3V_4

1mA (10mils)

HCB1608KF-181T15/1.5A_6

C523 10U/6.3VS_6C523 10U/6.3VS_6 C525 0.1U/10V_4C525 0.1U/10V_4 C524 0.01U/25V_4C524 0.01U/25V_4 R489 *0_8R489 *0_8

+VCCALVDS +3V

R561 *0_4/SR561 *0_4/S

R562 *0_4R562 *0_4

60mA (10mils)

0.1uH/250mA_8

R551 *0_4R551 *0_4 C584 22U/6.3VS_8C584 22U/6.3VS_8 C581 0.01U/25V_4C581 0.01U/25V_4 C582 0.01U/25V_4C582 0.01U/25V_4

R243 *0_6/SR243 *0_6/S

C333

0.1U/10V_4

L24

L29

+3V+3V_VCC_GIO

42mA (10mils)

+VCCAFDI_VRM

AT16 AT20

+1.1V_VCC_DMI_CCI

AB36

C616

C616 1U/6.3V_4

1U/6.3V_4

190 mA (15mils)

AG16

AG17

AJ16

AJ17

R317 *0_8/SR317 *0_8/S

C401

0.1U/10V_4

20mA (10mils)

+5V_PCH_VCC5REF

V5REF= 1mA

+5V_PCH_VCC5REFSUS

VCC5REFSUS=1mA

Size Document Number Rev

Size Document Number Rev Custom

Custom

Custom Date: Sheet

Date: Sheet

R643 *0_6/SR643 *0_6/S

C646

C646 1U/6.3V_4

1U/6.3V_4

C332

C332 1U/6.3V_4

1U/6.3V_4

C589

0.1U/10V_4

PROJECT : TWH

Quanta Computer Inc.

PCH 5/6 (Power)

C619

C619 *10U/6.3V_6

*10U/6.3V_6

+1.8V+VCCP_NAND

+3V+3V_VCCME_SPI

R241 10_4R241 10_4 D9 RB500V-40D9 RB500V-40

R560 10_4R560 10_4 D22 RB500V-40D22 RB500V-40

R279 *0_4/SR279 *0_4/S

C376

C376 1U/6.3V_4

1U/6.3V_4

+3V

12/9 0805 FP

12/13 short

+1.8V+VCC_TX_LVDS

+1.05V+1.1V_VCC_DMI

11/12 short

+5V +3V

+5VS5 +3VS5

10 40Tuesday, December 14, 2010

IBEX PEAK-M (GND)

U24I

AY4

VSS[159]

AY42

VSS[160]

AY46

VSS[161]

AY8

VSS[162]

B11

VSS[163]

B15

D D

C C

B B

A A

VSS[164]

B19

VSS[165]

B23

VSS[166]

B27

VSS[167]

B31

VSS[168]

B35

VSS[169]

B39

VSS[170]

VSS[171]

F45

VSS[172]

BB12

VSS[173]

BB16

VSS[174]

BB20

VSS[175]

BB22

VSS[176]

BB24

VSS[177]

BB28

VSS[178]

BB30

VSS[179]

BB38

VSS[180]

BB4

VSS[181]

BB46

VSS[182]

BC14

VSS[183]

BC18

VSS[184]

BC2

VSS[185]

BC22

VSS[186]

BC26

VSS[187]

BC32

VSS[188]

BC34

VSS[189]

BC36

VSS[190]

BC40

VSS[191]

BC42

VSS[192]

BC48

VSS[193]

BD46

VSS[194]

BD5

VSS[195]

BE22

VSS[196]

BE26

VSS[197]

BE40

VSS[198]

BF10

VSS[199]

BF12

VSS[200]

BF16

VSS[201]

BF20

VSS[202]

BF22

VSS[203]

BF24

VSS[204]

BF26

VSS[205]

BF28

VSS[206]

BD3

VSS[207]

BF30

VSS[208]

BF38

VSS[209]

BF40

VSS[210]

BF8

VSS[211]

BG17

VSS[212]

BG21

VSS[213]

BG33

VSS[214]

BG44

VSS[215]

BG8

VSS[216]

BH11

VSS[217]

BH15

VSS[218]

BH17

VSS[219]

BH19

VSS[220]

H10

VSS[221]

BH27

VSS[222]

BH31

VSS[223]

BH33

VSS[224]

BH35

VSS[225]

BH39

VSS[226]

BH43

VSS[227]

BH7

VSS[228]

VSS[229]

D12

VSS[230]

D16

VSS[231]

D18

VSS[232]

D22

VSS[233]

D24

VSS[234]

D26

VSS[235]

D30

VSS[236]

D32

VSS[237]

D34

VSS[238]

D38

VSS[239]

D42

VSS[240]

VSS[241]

E18

VSS[242]

E26

VSS[243]

G18

VSS[244]

G20

VSS[245]

G26

VSS[246]

G28

VSS[247]

G36

VSS[248]

G48

VSS[249]

H12

VSS[250]

H18

VSS[251]

H22

VSS[252]

H24

VSS[253]

H26

VSS[254]

H30

VSS[255]

H32

VSS[256]

H34

VSS[257]

VSS[258]

CougarPoint_Rev_0p7

PCH PS - AJSLH9D0T13

VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[328] VSS[329] VSS[330] VSS[331] VSS[333] VSS[334] VSS[335] VSS[337] VSS[338] VSS[340] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352]

H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28

IBEX PEAK-M (GND)

U24H

VSS[0]

AA17

VSS[1]

AA2

VSS[2]

AA3

VSS[3]

AA33

VSS[4]

AA34

VSS[5]

AB11

VSS[6]

AB14

VSS[7]

AB39

VSS[8]

AB4

VSS[9]

AB43

VSS[10]

AB5

VSS[11]

AB7

VSS[12]

AC19

VSS[13]

AC2

VSS[14]

AC21

VSS[15]

AC24

VSS[16]

AC33

VSS[17]

AC34

VSS[18]

AC48

VSS[19]

AD10

VSS[20]

AD11

VSS[21]

AD12

VSS[22]

AD13

VSS[23]

AD19

VSS[24]

AD24

VSS[25]

AD26

VSS[26]

AD27

VSS[27]

AD33

VSS[28]

AD34

VSS[29]

AD36

VSS[30]

AD37

VSS[31]

AD38

VSS[32]

AD39

VSS[33]

AD4

VSS[34]

AD40

VSS[35]

AD42

VSS[36]

AD43

VSS[37]

AD45

VSS[38]

AD46

VSS[39]

AD8

VSS[40]

AE2

VSS[41]

AE3

VSS[42]

AF10

VSS[43]

AF12

VSS[44]

AD14

VSS[45]

AD16

VSS[46]

AF16

VSS[47]

AF19

VSS[48]

AF24

VSS[49]

AF26

VSS[50]

AF27

VSS[51]

AF29

VSS[52]

AF31

VSS[53]

AF38

VSS[54]

AF4

VSS[55]

AF42

VSS[56]

AF46

VSS[57]

AF5

VSS[58]

AF7

VSS[59]

AF8

VSS[60]

AG19

VSS[61]

AG2

VSS[62]

AG31

VSS[63]

AG48

VSS[64]

AH11

VSS[65]

AH3

VSS[66]

AH36

VSS[67]

AH39

VSS[68]

AH40

VSS[69]

AH42

VSS[70]

AH46

VSS[71]

AH7

VSS[72]

AJ19

VSS[73]

AJ21

VSS[74]

AJ24

VSS[75]

AJ33

VSS[76]

AJ34

VSS[77]

AK12

VSS[78]

AK3

VSS[79]

CougarPoint_Rev_0p7

PCH PS - AJSLH9D0T13

VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98]

VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158]

AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28

PROJECT : TWH

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev Custom

Custom

PCH 6/6 (Ground)

NB5

PCH 6/6 (Ground)

Date: Sheet

11 40Tuesday, December 14, 2010

JDIM1A

M_A_A[15:0][3]

D D

M_A_BS#0[3] M_A_BS#1[3] M_A_BS#2[3] M_A_CS#0[3] M_A_CS#1[3] M_A_CLKP0[3] M_A_CLKN0[3] M_A_CLKP1[3] M_A_CLKN1[3] M_A_CKE0[3] M_A_CKE1[3] M_A_CAS#[3] M_A_RAS#[3]

R160 10K_4R160 10K_4 R164 10K_4R164 10K_4

C C

B B

M_A_WE#[3]

SMB_RUN_CLK[8,13] SMB_RUN_DAT[8,13]

M_A_ODT0[3] M_A_ODT1[3]

M_A_DQSP[7:0][3]

M_A_DQSN[7:0][3]

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15

DIMM0_SA0 DIMM0_SA1 SMB_RUN_CLK SMB_RUN_DAT

M_A_DM1

M_A_DM2

M_A_DQSP0 M_A_DQSP1 M_A_DQSP2 M_A_DQSP3 M_A_DQSP4 M_A_DQSP5 M_A_DQSP6 M_A_DQSP7 M_A_DQSN0 M_A_DQSN1 M_A_DQSN2 M_A_DQSN3 M_A_DQSN4 M_A_DQSN5 M_A_DQSN6 M_A_DQSN7

JDIM1A

107

A10/AP

A11

A12/BC#

119

A13

A14

A15

109

BA0

108

BA1

BA2

114

S0#

121

S1#

101

CK0

103

CK0#

102

CK1

104

CK1#

CKE0

CKE1

115

CAS#

110

RAS#

113

WE#

197

SA0

201

SA1

202

SCL

200

SDA

116

ODT0

120

ODT1

DM0

DM1

DM2

DM3

136

DM4

153

DM5

170

DM6

187

DM7

DQS0

DQS1

DQS2

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

DQS#0

DQS#1

DQS#2

DQS#3

135

DQS#4

152

DQS#5

169

DQS#6

186

DQS#7

DDR3-DIMM0_H=5.2_RVS

DDR-78279-001-RVS-204P

DGMK4000028

IC SOCKET DDRIII SO-DIMM(204P,H5.2,RVS)

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46

(204P)

PC2100 DDR3 SDRAM SO-DIMM

DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

M_A_DQ4

M_A_DQ5

M_A_DQ7

M_A_DQ6

M_A_DQ1

M_A_DQ0

M_A_DQ3

M_A_DQ2

M_A_DQ9

M_A_DQ8

M_A_DQ15

M_A_DQ10

M_A_DQ12

M_A_DQ13

M_A_DQ14

M_A_DQ11

M_A_DQ21

M_A_DQ16

M_A_DQ19

M_A_DQ18

M_A_DQ20

M_A_DQ17

M_A_DQ23

M_A_DQ22

M_A_DQ25

M_A_DQ24

M_A_DQ30

M_A_DQ26

M_A_DQ28

M_A_DQ29

M_A_DQ31

M_A_DQ27

M_A_DQ36

129

M_A_DQ37

131

M_A_DQ34

141

M_A_DQ38

143

M_A_DQ32

130

M_A_DQ33

132

M_A_DQ35

140

M_A_DQ39

142

M_A_DQ41

147

M_A_DQ45

149

M_A_DQ47

157

M_A_DQ46

159

M_A_DQ40

146

M_A_DQ44

148

M_A_DQ42

158

M_A_DQ43

160

M_A_DQ49

163

M_A_DQ48

165

M_A_DQ54

175

M_A_DQ55

177

M_A_DQ53

164

M_A_DQ52

166

M_A_DQ50

174

M_A_DQ51

176

M_A_DQ61

181

M_A_DQ60

183

M_A_DQ62

191

M_A_DQ63

193

M_A_DQ56

180

M_A_DQ57

182

M_A_DQ59

192

M_A_DQ58

194

M_A_DQ[63:0] [3]

+3V

PM_EXTTS#0[13]

DDR3_DRAMRST#[2,13]

SMDDR_VREF_DQ0_M3[5]

SMDDR_VREF_DQ0_M3

R36 *0_6/SR36 *0_6/S R32 *0_6R32 *0_6

12/13 short

2.48A

+3V

R177 10K_4R177 10K_4

PM_EXTTS#0

+SMDDR_VREF_DQ0SMDDR_VREF_DQ0_M1 +SMDDR_VREF_DIMM

+1.5VSUS

JDIM1B

VDD1

VDD2

VDD3

VDD4

VDD5

VDD6

VDD7

VDD8

VDD9

100

VDD10

105

VDD11

106

VDD12

111

VDD13

112

VDD14

117

VDD15

118

VDD16

123

VDD17

124

VDD18

199

VDDSPD

NC1

122

NC2

125

NCTEST

198

EVENT#

RESET#

VREF_DQ

126

VREF_CA

VSS1

VSS2

VSS3

VSS4

VSS5

VSS6

VSS7

VSS8

VSS9

VSS10

VSS11

VSS12

VSS13

VSS14

VSS15

DDR3-DIMM0_H=5.2_RVS

DDR-78279-001-RVS-204P

DGMK4000028

IC SOCKET DDRIII SO-DIMM(204P,H5.2,RVS)

VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52

(204P)

PC2100 DDR3 SDRAM SO-DIMM

VTT1 VTT2

GND GND

44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196

203 204

205 206

+0.75V_DDR_VTT

+1.5VSUS

VREF DQ0 M1 SolutionPlace these Caps near So-Dimm0.

Remove M2 Solution (Intel 436996 Doc)

A A

8/31 C513 FP changed from 330U_2.5V_5.0x5.9ESR10m to 220U/6.3V_6x4.5ESR18

11/13 delete C513

+1.5VSUS +0.75V_DDR_VTT

C126 1U/6.3V_4C126 1U/6.3V_4 C171 1U/6.3V_4C171 1U/6.3V_4 C177 1U/6.3V_4C177 1U/6.3V_4 C163 1U/6.3V_4C163 1U/6.3V_4 C155 10U/6.3VS_6C155 10U/6.3VS_6 C139 10U/6.3VS_6C139 10U/6.3VS_6 C119 10U/6.3VS_6C119 10U/6.3VS_6 C124 10U/6.3VS_6C124 10U/6.3VS_6 C61 10U/6.3VS_6C61 10U/6.3VS_6 C123 10U/6.3VS_6C123 10U/6.3VS_6 C146 *10U/6.3V_6C146 *10U/6.3V_6

C149 10U/6.3V_8C149 10U/6.3V_8

+SMDDR_VREF_DIMM

+SMDDR_VREF_DQ0

4/27: layout modify

C287 1U/6.3V_4C287 1U/6.3V_4 C288 1U/6.3V_4C288 1U/6.3V_4 C286 1U/6.3V_4C286 1U/6.3V_4 C285 1U/6.3V_4C285 1U/6.3V_4 C284 10U/6.3V_6C284 10U/6.3V_6 C289 *10U/6.3V_6C289 *10U/6.3V_6

C181 0.1U/10V_4C181 0.1U/10V_4 C164 2.2U/6.3V_6C164 2.2U/6.3V_6

C26 0.1U/10V_4C26 0.1U/10V_4C140 10U/6.3V_8C140 10U/6.3V_8 C23 2.2U/6.3V_6C23 2.2U/6.3V_6

+3V

C273 0.1U/10V_4C273 0.1U/10V_4 C265 2.2U/6.3V_6C265 2.2U/6.3V_6

R34

R34 1K/F_4

DDR_VTTREF SMDDR_VREF_DQ0_M1

R33 *0_6R33 *0_6

1K/F_4

R35

R35 1K/F_4

1K/F_4

DDR_VTTREF[4,13,32]

NB5

+1.5VSUS

R115

R115 10K_4

10K_4

R119 *0_6R119 *0_6

PROJECT : TWH

Quanta Computer Inc.

Size Document Number Rev

Size Document Number Rev Custom

Custom

System Memory 1/2 (5.2H)

Date: Sheet

+SMDDR_VREF_DIMM

R111

R111 10K_4

10K_4

+0.75V_DDR_VTT[13,32,36]

C180

C180 470P/50V_4

470P/50V_4

+3V[2,6,7,8,9,10,13,14,21,22,23,24,25,26,27,28,29,34,36,37,39]

+3VPCU[6,7,21,27,28,29,30,31]

+1.5VSUS[2,4,10,13,32,33,38]

12 40Tuesday, December 14, 2010

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