Quanta TT9, Pavilion tx2000, Pavilion tx2500, Pavilion tx2640, Pavilion tx2650 Schematic
1
2
3
4
5
6
7
8
PCB STACK UP
LAYER 1 : TOP
LAYER 2 : SGND1
LAYER 3 : IN1
A A
LAYER 4 : IN2
LAYER 5 : VCC
LAYER 6 : IN3
LAYER 7 : SGND2
LAYER 8 : BOT
Soyuz 2.0 SYSTEM DIAGRAM
DDRII-SODIMM1
PAGE 8,9
DDRII-SODIMM2
PAGE 8,9
DDRII 667/800 MHz
DDRII 667/800 MHz
PCI-E
AMD
Griffin
S1G2 Processor
Lion
Sabie
638P (uPGA)/35W
PAGE 5,6,7
HT3
CPU THERMAL
SENSOR
PAGE 7
CRT
CPU_CLK
NBGFX_CLK
NBGPP_CLK
SBLINK_CLK
14.318MHz
CLOCK GEN
ICS9LPRS476AKLFT-->HP
SLG8SP626VTR-->HP
RTM880N-795 -->HP
PAGE 4
01
PAGE 20
NORTH BRIDGE
Cable
Docking
B B
VGA
RJ-45
CIR/Pwr btn
SPDIF Out
Stereo MIC
TV_OUT
LAN
Realtek
PCIE-LAN
RTL8111C
(10/100/GagaLAN)
PAGE 26,27
Express
Card
(NEW CARD)
PAGE 28
Headphone Jack
USB Port
PAGE 32
VOL Cntr
SYSTEM CHARGER(ISL6251A)
RJ45
PAGE 26
SATA - HDD
PAGE 28
PAGE 39
SYSTEM POWER MAX1631A
C C
DDR II SMDDR_VTERM
1.8V/1.8VSUS
VCCP +1.1V AND +1.2V(RT8204)
PAGE 33
PAGE 36
PAGE 34
CPU CORE ISL6265A
PAGE 35
SATA - CD-ROM
PAGE 28
Keyboard
PAGE 29
CIR X2
PAGE 30
Mini PCI-E
Card
(Wireless
LAN/ROBSON/TV)
PAGE 31
SATA0 150MB
SATA0 150MB
ENE KBC
KB3926 Bx
RS780M
21mm X 21mm, 528pin BGA
PAGE 10,11,12,13
PCIE X4
SOUTH BRIDGE
SB700
21mm X 21mm, 528pin BGA
4.5W(Ext)
4.3W(Int)
PAGE 14,15.16.17.18
LPC
MDC DAA
PAGE 24
Side port
256mb RAM
PAGE 10
USB2.0
0,1,6
USB2.0 Ports
X3
PAGE 25
(2.0/1.1)
Azalia
ALC268
PAGE 22
AUDIO
Amplifier
LVDS
PAGE 19
S-Vidio
PAGE 20
7
Camera
PAGE 19
(2.0)
SBSRC_CLK
Fingerprint
PAGE 19
(1.1)
1312
Touch
Screen
PAGE 19
(1.1)
Express Card x1
Cable Docking x1
WLAN X1
9
Bluetooth
PAGE 25
(2.0)
(2.0/1.1)
PAGE 28,32
2,4,8
Card Reader
RTS5158
(2.0)
Memory
CardReader
PAGE 21
3
PAGE 21
Touch Pad
D D
1
2
PAGE 30
3
FAN
PAGE 32
PAGE 30
SPI
PAGE 30
4
AUDIO CONNDigital MIC
(Phone/ MIC)
PAGE 22PAGE 22
5
PAGE 23
SPEAKER
Conn
PAGE 23
PROJECT : TT9
Quanta Computer Inc.
Size Document Number Rev
Custom
6
NB5/RD2/HW1
Block Diagram
Date: Sheet
7
141Wednesday, January 23, 2008
8
1A
of
5
4
3
2
1
INDEX Power & Ground
Description
1
Schematic Block Diagram
2
D D
C C
B B
A A
System Information
3
Power sequence chart
4
CLOCL GENERATOR
5-7
AMD CPU S1G2 Griffin
8-9
DDR II SO-DIMM
10-13
RS780M
14-18
SB700
19
LCD CONNECTOR / LCD PWR / LID
20
20--CRT,TV_OUT
21
RTS5158E & CR SOCKET
22
Azalia ALC268
23
JACK/AMP_TPA0312
24
Si3080 and MDC1.5 Connector
25
Blue Tooth / USBX3 / TPM
26
RTL8111C/RJ45
27
LAN Power
28
NEW CARD/SATA ODD/SATA HDD
29
LED/KEYBOARD/SW
30
KB3926/ROM/TP
31
Mini CARD/Hole
32
CABLE DOCKING/FAN
33
3V/5V(MAX1631A)
34
+1.2V/+1.1V (RT8204)
35
+CPU_CORE ISL6265
36
+1.8VSUS/+1.8V/+2.5V
37
+1.1V/+1.2V_S5/+1.5V
38
DISCHARGE
39
Charger (ISL6251)
* --> Un-stuff (ex. *1K/04)
04-- 0402 footprint
06-- 0603 footprint
08-- 0805 footprint
12-- 1206 footprint
F-- 1% tolerance
5
NOTEPg#
Label
+VIN
+BATT
+AVBAT
+12VALW
+VCORE
+CPUVDDNB S0 CPU CORE POWER (1.375-1.5V)
+1.1V_NB
+1.1V S0 +1.1V
+1.2VS5 S0, S3, S4, S5 S5_ON
+1.2V S0 +1.2V VRON
+3V
+3VSUS
+3VS5 S5_ONS0, S3, S4, S5
+3VPCU
+5V
+5VSUS
+5VPCU
+1.5V S0
+1.8VSUS
+1.8V S0 MAINON
+2.5V
+0.9VSMVREF_DIMM
+AVDD
+3VLANVCC S0, S3, S4, S5 LAN Power LAN_ON
GND
AGND
SMBUS
SMBCLK0
SMBDAT0
SMBCLK1
SMBDAT1
SMBCLK2
SMBDAT2
4
3
ACTIVE
S0, S3, S4, S5
S0, S3, S4, S5
S0, S3, S4, S5
S0, S3, S4, S5
S0
S0
S0
S0, S3
S0, S3, S4, S5
S0
S0, S3
S0, S3, S4, S5
S0, S3 SUSON
S0 VR2.5_ON
S0
S0, S3
S0 MAINON
ALL PAGES
AC ADAPTER (18.5V)
MAIN BATTERY + (6.2V-8.4V)
RTC & KBC POWER
+12V
CPU CORE POWER (0.375-1.5V)
+1.1 to +1.0 DYN
ALWAYS POWER (3V)
ALWAYS POWER (5V)
DDR CORE POWER
CPU VDDA
DDR COMMAND & CONTROL PULL UP POWER
DDR REF POWER
AUDIO ANALOG POWER (5V)
DIGITAL GROUND
AUDIO GND
Description
(3.3V)
SMBUS function define
DDR / DDR THER / CLOCK GEN (+3V)
Mini Card (+3VS5)
New CARD (+3VS5)
2
NB5/RD2/HW1
Control
Signal
VRON
VRON
VRON
VRON
MAINON
SUSON
MAIND
SUSON
MAIND
MAINON+0.9VSMVTT
SUSON
02
PROJECT : TT9
Quanta Computer Inc.
Size Document Number Rev
Custom
System Information
Date: Sheet
241Wednesday, January 23, 2008
1
of
1A
5
4
3
2
1
03
CPU Power Group A CPU Power Group B
D D
EC Pin98
SUSON
+1.8VSUS
HWPG
EC Pin33
VR_ON
+VCORE0
VRM_PWRGD
+VCORE1
3VPCU/5VPCU
NBSWON1#
DNBSWON#
S5_ON
RSMRST#
+0.9VSMVTT
SUSC
+CPUVDDNB
EC Pin102
SUSB
VR2.5_ON
+2.5V
+1.2V
C C
EC Pin101
S5_ON
Delay
S5_OND
+3VS5
EC Pin101
S5_ON
EC Pin33
VR_ON
EC Pin33
VR_ON
+1.1V
+1.1V DYN+1.2VS5
HWPG
HWPG
HWPG
SUSON
MAINON
VR_ON
VR2.5_ON
HWPG
VRM_PWRGD
ECPWROK
+5VSUS
B B
EC Pin98
SUSON
Delay
SUSD
+3VSUS
EC Pin99
MAINON
+1.5V
HWPG
NB_PWRGD_IN
SB_PWRGD_IN
CPU CLK IN
CPU RESET
EC Pin99
+5V
MAINON
Delay
1.8V_OND
+1.8V
CPU POWER OK
CPU_LDTSTOP#
EC Pin99
MAINON
Delay
MAIND
+3V
EC Pin100
LAN_POWER
Delay
LAN_ON
+3VLANVCC
A A
PROJECT : TT9
Quanta Computer Inc.
Size Document Number Rev
Custom
5
4
3
2
NB5/RD2/HW1
Power control
Date: Sheet
1
341Wednesday, January 23, 2008
1A
of
5
0.2A
L29 FBM-11-160808
+1.2V
600 ohms@100Mhz
60 ohm, 0.5A
C273
22U/6.3VC_8
C542
0.1U/10VC_4
C539
0.1U/10VC_4
0.1U/10VC_4
0.5A
D D
+3V
DCR: 0.5 ohm
600 ohms@100Mhz
L30 FBM-11-160808
60 ohm, 0.5A
22U/6.3VC_8
+3V_CLKVDD
C276
2.2U/6.3VC_6
C284
C567
0.1U/10VC_4
C565
0.1U/10VC_4
C541
+3V_CLKVDD
0.1U/10VC_4
4
+1.2V_CLKVDDIO
C269
0.1U/10VC_4
C547
0.1U/10VC_4
C544
0.1U/10VC_4
C563
0.1U/10VC_4
C540
0.1U/10VC_4
C548
C545
0.1U/10VC_4
C569
0.1U/10VC_4
3
C557
0.1U/10VC_4
Clock chip has internal serial
terminations
for differencial pairs, external resistors
are
reserved for debug purpose.
2
NB CLOCK INPUT TABLE
NB CLOCKS
HT_REFCLKP
HT_REFCLKN
REFCLK_P
REFCLK_N
GFX_REFCLK
GPP_REFCLK
GPPSB_REFCLK
RX780 RS780
100M DIFF
100M DIFF
14M SE (1.8V) 14M SE (1.1V)
NC vref
100M DIFF
100M DIFF
100M DIFF 100M DIFF
1
100M DIFF
100M DIFF
100M DIFF(IN/OUT)*
NC or 100M DIFF OUTPUT
04
+3V_CLKVDD
L31
BLM18PG221SN1D
C C
PV Modify for RTC problem
C299 22P/50VA_4
Y3
14.318MHZ
C300 22P/50VA_4
B B
when driven low
A A
* RS780 can be used as clock buffer to output two PCIE referecence clocks
By deault, chip will configured as input mode, BIOS can program it to output
mode.
CG_XIN CG_XIN
1 2
CG_XOUT
CHIPSET_PCIE_SLOW_SB#16
SB_SRC clocks slow
to reduced setpoint
+1.2V 5,13,14,16,17,34,37
+3V 5,7,8,9,12,13,14,15,16,17,18,19,20,22,23,26,28,29,30,31,33,34,38
5
C295
22U/6.3VC_8
Place very
close to
C/G
PCLK_SMB8,9,15
PDAT_SMB8,9,15
D10 *CH501H-40PT L-F
+3V_CLK_VDDA
2.2U/6.3VC_6
+3V_CLK_VDDA
2.2U/6.3VC_6
21
only supported with
custom CG IC
C551
C570
+3V_CLKVDD
+1.2V_CLKVDDIO
CG_XOUT
CLK_PD#
PCLK_SMB
PDAT_SMB
SB_SRC_SLOW#
4
U31A
49
VDDA
48
GNDA
62
VDDREF
66
GNDREF
69
VDD48
29
VDDATIG
54
VDDCPU
61
VDDHTT
38
VDDSB_SRC
17
VDDSRC
44
VDDSATA
3
VDDDOT
28
VDDATIG_IO
53
VDDCPU_IO
37
VDDSB_SRC_IO
12
VDDSRC_IO1
18
VDDSRC_IO2
72
GND48
27
GNDATIG1
6
GNDDOT
52
GNDCPU
58
GNDHTT
47
GNDSATA
36
GNDSB_SRC
11
GNDSRC1
19
GNDSRC2
67
X1
68
X2
57
PD#
1
SMBCLK
2
SMBDAT
41
SB_SRC_SLOW#
RTM880N-795-VB-GR
73
eGND73
74
eGND74
75
eGND75
U31B
RTM880N-795-VB-GR
* default
SEL_HTT66
SEL_SATA
SEL_27 1
CPUKG0T_LPRS
CPUKG0C_LPRS
ATIG0T_LPRS
ATIG0C_LPRS
ATIG1T_LPRS
ATIG1C_LPRS
ATIG2T_LPRS
ATIG2C_LPRS
SB_SRC0T_LPRS
SB_SRC0C_LPRS
SB_SRC1T_LPRS
SB_SRC1C_LPRS
SRC0T_LPRS
SRC0C_LPRS
SRC1T_LPRS
SRC1C_LPRS
SRC2T_LPRS
SRC2C_LPRS
SRC3T_LPRS
SRC3C_LPRS
SRC4T_LPRS
SRC4C_LPRS
SRC5T_LPRS
SRC5C_LPRS
SRC6T/SATAT_LPRS
SRC6C/SATAC_LPRS
SRC7T_LPRS/27Mhz_SS
SRC7C_LPRS/27Mhz_NS
HTT0T/66M_LPRS
HTT0C/66M_LPRS
48MHz_0
48MHz_1
REF0/SEL_HTT66
REF1/SEL_SATA
REF2/SEL_27
CLKREQ0#
CLKREQ1#
CLKREQ2#
CLKREQ3#
CLKREQ4#
THERMAL GND
1
*0
*
1
0
*
0
eGND77
eGND76
eGND78
66 MHz 3.3V single ended HTT clock
100 MHz differential HTT clock
100 MHz non-spreading differential SRC clock
100 MHz spreading differential SRC clock
27MHz non-spreading singled clock
100 MHz spreading differential SRC clock
3
Place within 0.5"
of CLKGEN
CPUCLK0P
56
CPUCLK0N
55
NBGFXCLK0P
33
NBGFXCLK0N
32
31
30
26
25
40
39
35
34
23
22
PCIENEWCLK0P
21
PCIENEWCLK0N
20
PCIEMINICLK1P
16
PCIEMINICLK1N
15
PCILANCLK0P
14
13
10
9
8
7
SBSRCCLK0P SBSRC_CLKP
46
SBSRCCLK0N SBSRC_CLKN
45
5
4
NBHTREFCLK0P
60
NBHTREFCLK0N
59
CLK48MUSBCR
71
70
SEL_HT66
65
SEL_SATA
64
SEL_27
63
CLKREQ0#
24
EXT_NWD_CLK_REQ#
51
CLK_MINI_OE#
50
CLKREQ3#
43
CLKREQ4#
42
77
76
78
RP37 0X2_4P2R_4
4
3
2
4
2
4
2
4
2
4
2
4
2
4
2
1 2
For RS780
1
3
1
3
1
3
1
3
1
3
1
3
1
1.1V
R414
*8.2K_4
R160
8.2K_4
RP32 0X2_4P2R_4
RP31 0X2_4P2R_4
RP33 0X2_4P2R_4
RP34 0X2_4P2R_4
RP36 0X2_4P2R_4
RP35 0X2_4P2R_4
R416 0_4
R417 0_4
R405 33_4
R412 33_4
R415 158/F_4
R165 90.9/F_4
+3V_CLKVDD
R164
*8.2K_4
EXT
R163
8.2K_4
R418 *261/F_4
CPUCLKP
CPUCLKN
NBGFX_CLKP
NBGFX_CLKN
PCIE_NEW_CLKP
PCIE_NEW_CLKN
PCIE_MINI1_CLKP
PCIE_MINI1_CLKN
PCIE_LAN_CLKP
PCIE_LAN_CLKNPCILANCLK0N
SBLINK_CLKPSBLINKCLK0P
SBLINK_CLKNSBLINKCLK0N
NBHT_REFCLKP
NBHT_REFCLKN
CLK_48M_USB_CR
CLK_48M_USBCLK48MUSB
SI Fix SRC signal use
SI Fix bios can not write
SEL_27
SEL_SATA
SEL_HT66
2
CPUCLKP 5
CPUCLKN 5
NBGFX_CLKP 12
NBGFX_CLKN 12
PCIE_NEW_CLKP 28
PCIE_NEW_CLKN 28
PCIE_MINI1_CLKP 31
PCIE_MINI1_CLKN 31
PCIE_LAN_CLKP 26
PCIE_LAN_CLKN 26
SBLINK_CLKP 12
SBLINK_CLKN 12
SBSRC_CLKP 14
SBSRC_CLKN 14
NBHT_REFCLKP 12
NBHT_REFCLKN 12
CLK_48M_USB_CR 21
CLK_48M_USB 15
EXT_NB_OSC 12
EXT_NWD_CLK_REQ# 28
CLK_MINI_OE# 31
NB5/RD2/HW1
SI EMI request
+3V
CLKREQ0#
CLKREQ3#
CLKREQ4#
CLK_MINI_OE#
SI Modified -- add clock
request pin pull Hi for new
version clock gen
note : if pull Hi will
disable SRC clock output
EXT_NWD_CLK_REQ#
CLK_PD#
SB_SRC_SLOW#
R4968.2K_4
R497*8.2K_4
R498*8.2K_4
R4998.2K_4
+3V
R4028.2K_4
R1558.2K_4
R3918.2K_4
PROJECT : TT9
Quanta Computer Inc.
Size Document Number Rev
Custom
Clock gererator
Date: Sheet
441Wednesday, January 23, 2008
1
of
1A
5
+1.2V 4,13,14,16,17,34,37
+1.8V 10,12,13,14,15,18,36,38
+1.8VSUS 6,7,8,9,31,35,36,37
+2.5V 37
+3V 4,7,8,9,12,13,14,15,16,17,18,19,20,22,23,26,28,29,30,31,33,34,38
C130 4.7U/6.3VC_6
C121 4.7U/6.3VC_6
D D
HT_NB_CPU_CAD_H[15..0]10
HT_NB_CPU_CAD_L[15..0]10
HT_NB_CPU_CLK_H[1..0]10
HT_NB_CPU_CLK_L[1..0]10
HT_NB_CPU_CTL_H[1..0]10
HT_NB_CPU_CTL_L[1..0]10
HT_CPU_NB_CAD_H[15..0]10
HT_CPU_NB_CAD_L[15..0]10
HT_CPU_NB_CLK_H[1..0]10
HT_CPU_NB_CLK_L[1..0]10
HT_CPU_NB_CTL_H[1..0]10
C C
HT_CPU_NB_CTL_L[1..0]10
HT_NB_CPU_CAD_H[15..0]
HT_NB_CPU_CAD_L[15..0]
HT_NB_CPU_CLK_H[1..0]
HT_NB_CPU_CLK_L[1..0]
HT_NB_CPU_CTL_H[1..0]
HT_NB_CPU_CTL_L[1..0]
HT_CPU_NB_CAD_H[15..0]
HT_CPU_NB_CAD_L[15..0]
HT_CPU_NB_CLK_H[1..0]
HT_CPU_NB_CLK_L[1..0]
HT_CPU_NB_CTL_H[1..0]
HT_CPU_NB_CTL_L[1..0]
C129 0.22U/6.3VC_4
180P/50VA_4
1.5A
+1.2V +1.2V_VLDT
R336 0_8
R337 0_8
+1.2V_VLDT
+1.2V_VLDT
+1.2V_VLDT
+1.2V_VLDT
+1.2V_VLDT
HT_NB_CPU_CAD_H0
HT_NB_CPU_CAD_L0
HT_NB_CPU_CAD_H1
HT_NB_CPU_CAD_L1
HT_NB_CPU_CAD_H2
HT_NB_CPU_CAD_L2
HT_NB_CPU_CAD_H3
HT_NB_CPU_CAD_L3
HT_NB_CPU_CAD_H4
HT_NB_CPU_CAD_L4
HT_NB_CPU_CAD_H5
HT_NB_CPU_CAD_L5
HT_NB_CPU_CAD_H6
HT_NB_CPU_CAD_L6
HT_NB_CPU_CAD_H7
HT_NB_CPU_CAD_L7
HT_NB_CPU_CAD_H8
HT_NB_CPU_CAD_L8
HT_NB_CPU_CAD_H9
HT_NB_CPU_CAD_L9
HT_NB_CPU_CAD_H10
HT_NB_CPU_CAD_L10
HT_NB_CPU_CAD_H11
HT_NB_CPU_CAD_L11
HT_NB_CPU_CAD_H12
HT_NB_CPU_CAD_L12
HT_NB_CPU_CAD_H13
HT_NB_CPU_CAD_L13
HT_NB_CPU_CAD_H14
HT_NB_CPU_CAD_L14
HT_NB_CPU_CAD_H15
HT_NB_CPU_CAD_L15
HT_NB_CPU_CLK_H0
HT_NB_CPU_CLK_L0
HT_NB_CPU_CLK_H1
HT_NB_CPU_CLK_L1
HT_NB_CPU_CTL_H0
HT_NB_CPU_CTL_L0
HT_NB_CPU_CTL_H1
HT_NB_CPU_CTL_L1
4
U27A
D1
VLDT_A0
D2
VLDT_A1
D3
VLDT_A2
D4
VLDT_A3
E3
L0_CADIN_H0
E2
L0_CADIN_L0
E1
L0_CADIN_H1
F1
L0_CADIN_L1
G3
L0_CADIN_H2
G2
L0_CADIN_L2
G1
L0_CADIN_H3
H1
L0_CADIN_L3
J1
L0_CADIN_H4
K1
L0_CADIN_L4
L3
L0_CADIN_H5
L2
L0_CADIN_L5
L1
L0_CADIN_H6
M1
L0_CADIN_L6
N3
L0_CADIN_H7
N2
L0_CADIN_L7
E5
L0_CADIN_H8
F5
L0_CADIN_L8
F3
L0_CADIN_H9
F4
L0_CADIN_L9
G5
L0_CADIN_H10
H5
L0_CADIN_L10
H3
L0_CADIN_H11
H4
L0_CADIN_L11
K3
L0_CADIN_H12
K4
L0_CADIN_L12
L5
L0_CADIN_H13
M5
L0_CADIN_L13
M3
L0_CADIN_H14
M4
L0_CADIN_L14
N5
L0_CADIN_H15
P5
L0_CADIN_L15
J3
L0_CLKIN_H0
J2
L0_CLKIN_L0
J5
L0_CLKIN_H1
K5
L0_CLKIN_L1
N1
L0_CTLIN_H0
P1
L0_CTLIN_L0
P3
L0_CTLIN_H1
P4
L0_CTLIN_L1
SOCKET_638_PIN
HT LINK
C484
VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3
L0_CADOUT_H0
L0_CADOUT_L0
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H15
L0_CADOUT_L15
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
+1.2V_VLDT
AE2
+1.2V_VLDT
AE3
+1.2V_VLDT
AE4
+1.2V_VLDT
AE5
HT_CPU_NB_CAD_H0
AD1
HT_CPU_NB_CAD_L0
AC1
HT_CPU_NB_CAD_H1
AC2
HT_CPU_NB_CAD_L1
AC3
HT_CPU_NB_CAD_H2
AB1
HT_CPU_NB_CAD_L2
AA1
HT_CPU_NB_CAD_H3
AA2
HT_CPU_NB_CAD_L3
AA3
HT_CPU_NB_CAD_H4
W2
HT_CPU_NB_CAD_L4
W3
HT_CPU_NB_CAD_H5
V1
HT_CPU_NB_CAD_L5
U1
HT_CPU_NB_CAD_H6
U2
HT_CPU_NB_CAD_L6
U3
HT_CPU_NB_CAD_H7
T1
HT_CPU_NB_CAD_L7
R1
HT_CPU_NB_CAD_H8
AD4
HT_CPU_NB_CAD_L8
AD3
HT_CPU_NB_CAD_H9
AD5
HT_CPU_NB_CAD_L9
AC5
HT_CPU_NB_CAD_H10
AB4
HT_CPU_NB_CAD_L10
AB3
HT_CPU_NB_CAD_H11
AB5
HT_CPU_NB_CAD_L11
AA5
HT_CPU_NB_CAD_H12
Y5
HT_CPU_NB_CAD_L12
W5
HT_CPU_NB_CAD_H13
V4
HT_CPU_NB_CAD_L13
V3
HT_CPU_NB_CAD_H14
V5
HT_CPU_NB_CAD_L14
U5
HT_CPU_NB_CAD_H15
T4
HT_CPU_NB_CAD_L15
T3
HT_CPU_NB_CLK_H0
Y1
HT_CPU_NB_CLK_L0
W1
HT_CPU_NB_CLK_H1
Y4
HT_CPU_NB_CLK_L1
Y3
HT_CPU_NB_CTL_H0
R2
HT_CPU_NB_CTL_L0
R3
HT_CPU_NB_CTL_H1
T5
HT_CPU_NB_CTL_L1
R5
+2.5V
3
L8
BLM21PG221SN1D
LS0805-100M-N
C74
10U/6.3VC_8
W/S= 15 mil/20mil
C2234.7U/6.3VC_6
C2260.22U/6.3VC_4
C224180P/50VA_4
SideBand Temp sense I2C
+1.2V_VLDT
PV modified for
AMD sighting
update
PV modified for
AMD sighting
update
C80
4.7U/6.3VC_6
CPU_LDT_RST#14
CPU_PWRGD14
CPU_LDT_STOP#12,14
CPU_SIC7
CPU_SID7
CPU_ALERT7
R127 44.2/F_4
R121 44.2/F_4
CPU_VDD0_RUN_FB_H35
CPU_VDD0_RUN_FB_L35
CPU_VDD1_RUN_FB_H35
CPU_VDD1_RUN_FB_L35
+1.8VSUS
R504 300/F_4
R505 300/F_4
+CPUVDDA
C86
0.22U/6.3VC_4
250mA
+CPUVDDA
+CPUVDDA
CPUCLKIN
CPUCLKIN#
CPU_LDT_RST#
CPU_PWRGD
CPU_LDT_STOP#
CPU_LDT_REQ#_CPU
CPU_SIC
CPU_SID
CPU_ALERT
CPU_HTREF0
place them to CPU within 1.5"
CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI
R353 *510/F_4
R354 *510/F_4
R351 0_4
CPU_HTREF1
T41
T16
T21
CPUTEST21
CPUTEST20
T95
CPUTEST24
CPUTEST22
T42
CPUTEST12
T45
CPUTEST27
T43
Need check
3300P/25VB_4
CPUTEST23
CPUTEST18
CPUTEST19
CPUTEST25H
CPUTEST25L
C94
F10
AF4
AF5
AE6
AB6
G10
AA9
AC9
AD9
AF9
AD7
H10
AB8
AF7
AE7
AE8
AC8
AF8
AA6
2
U27D
F8
VDDA1
F9
VDDA2
A9
CLKIN_H
A8
CLKIN_L
B7
RESET_L
A7
PWROK
LDTSTOP_L
C6
LDTREQ_L
SIC
SID
ALERT_L
R6
HT_REF0
P6
HT_REF1
F6
VDD0_FB_H
E6
VDD0_FB_L
Y6
VDD1_FB_H
VDD1_FB_L
DBRDY
TMS
TCK
TRST_L
TDI
TEST23
TEST18
G9
TEST19
E9
TEST25_H
E8
TEST25_L
TEST21
TEST20
TEST24
TEST22
TEST12
TEST27
C2
TEST9
TEST6
A3
RSVD1
A5
RSVD2
B3
RSVD3
B5
RSVD4
C1
RSVD5
SOCKET_638_PIN
KEY1
KEY2
SVC
SVD
THERMTRIP_L
PROCHOT_L
MEMHOT_L
THERMDC
THERMDA
VDDIO_FB_H
VDDIO_FB_L
VDDNB_FB_H
VDDNB_FB_L
DBREQ_L
TDO
TEST28_H
TEST28_L
TEST17
TEST16
TEST15
TEST14
TEST7
TEST10
TEST8
TEST29_H
TEST29_L
RSVD10
RSVD9
RSVD8
RSVD7
RSVD6
M11
W18
CPU_SVC_R
A6
CPU_SVD_R
A4
CPU_THERMTRIP_L#
AF6
CPU_PROCHOT_L#
AC7
CPU_MEMHOT_L#
AA8
H_THRMDC
W7
H_THRMDA
W8
VDDIO_FB_H
W9
VDDIO_FB_L
Y9
H6
G6
CPU_DBREQ#
E10
CPU_TDO
AE9
CPUTEST28H
J7
CPUTEST28L
H8
CPUTEST17
D7
CPUTEST16
E7
CPUTEST15
F7
CPUTEST14
C7
C3
K8
C4
CPUTEST29H
C9
CPUTEST29L
C8
H18
H19
AA7
D5
C5
1
CPU_PROCHOT_L# 32
H_THRMDC 7
H_THRMDA 7
VDDIO_FB_H 36
VDDIO_FB_L 36
CPU_VDDNB_RUN_FB_H 35
CPU_VDDNB_RUN_FB_L 35
R503 300/F_4
T20
T17
T12
T13
T14
T11
T3
T2
PV modified for
AMD sighting
update
05
+1.8VSUS
CNTR_VREF
B B
A A
+3V
+1.8VSUS
+1.8VSUS
CPU_PROCHOT_L#
+1.8VSUS
+1.8VSUS
CPU_THERMTRIP_L#
R358 20K_4
Q33 *BSS138_NL/SOT23
1
R355 0_4
R136 10K/F_4
R132 300_4
R118 10K/F_4
R119 300_4
C499 0.1U/10VC_4
R357 34.8K/F_4
CNTR_VREF
2
3
2
Q17
1 3
MMBT3904
2
Q12
MMBT3904
1 3
5
CPU_LDT_REQ# 12
CPU_PROCHOT# 14
CPU_THERMTRIP# 15
CNTR_VREF 7
CPU_LDT_RST# CPU_LDT_RST_HTPA#CPU_LDT_REQ#_CPU
+1.8VSUS
+1.8VSUS
CPU CLK
R339
0_4
R112 10K/F_4
R114 300_4
CPU_MEMHOT_L#
CPUCLKP4
CPUCLKN4
2
1
4
3
Q32
BSS138_NL/SOT23
2
Q11
MMBT3904
13
CPUCLKIN
C477 3900P/25VB_4
CPUCLKN
C475 3900P/25VB_4
Keep trace from resisor to CPU within 0.6"
keep trace from caps to CPU within 1.2"
R340 1K/F_4
CPU_MEMHOT# 9,15
R332 169/F_4
+3V
CPUCLKIN#
CPUCLKINCPUCLKP
CPUCLKIN#
R63 *2.2K_4
R72 1K/F_4
+1.8VSUS
CPU_SVC_R
CPU_SVD_R CPU_SVD
CPU_PWRGD
R331 1K/F_4
R330 0_4
R73 0_4
R75 0_4
R329 *220_4
R71 *220_4
R76 *0.1U/10VC_4
Add 0.1u
PV Remove for Power up seq
CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO
C275 *0.1U/10VC_4
3
Serial VID
CPU_SVC
CPU_PWRGD_SVID_REG
VFIX MODE
SVC SVD Voltage Output
00
0
1
11
HDT Connector
+1.8VSUS
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
KEY
CN6 *HDT CONN
VID Override Circuit
1
0
25
CPU_SVC 35
CPU_SVD 35
CPU_PWRGD_SVID_REG 35
1.4V
1.2V
1.0V
0.8V
CPU_LDT_RST_HTPA#
2
+1.8VSUS +3VPCU
CPU_LDT_RST#
CPU_LDT_STOP#
CPU_PWRGD
CPU_LDT_REQ#_CPU
Size Document Number Rev
NB5/RD2/HW1
Custom
Date: Sheet
C682 *0.1U/10VC_4
C683 *0.1U/10VC_4
Change from +1.8VSUS to +1.8
+1.8V
R349300_4
R352300_4
R74300_4
G3
12
*SHORT_ PAD1
R356300_4
CPU_LDT_RST#
PROJECT : TT9
Quanta Computer Inc.
S1G2 HT,CTL I/F 1/3
1
541Wednesday, January 23, 2008
of
1A
A
B
C
D
E
+0.9VSMVTT +0.9VSMVTT
PLACE THEM CLOSE TO
CPU WITHIN 1"
R367 39.2/F_4
MEM_MA0_ODT08,9
MEM_MA0_ODT18,9
MEM_MA0_CS#08,9
MEM_MA0_CS#18,9
MEM_MA_CLK1_P8
MEM_MA_CLK1_N8
MEM_MA_CLK7_P8
MEM_MA_CLK7_N8
MEM_MA_BANK08,9
MEM_MA_BANK18,9
MEM_MA_BANK28,9
MEM_MA_RAS#8,9
MEM_MA_CAS#8,9
MEM_MA_WE#8,9
MEM_MA_CKE08,9
MEM_MA_CKE18,9
R368 39.2/F_4
T18
T27
T32
T34
T35
T22
T23
T26
T25
A
+1.8VSUS
4 4
MEM_MA_ADD[0..15]8,9
3 3
2 2
1 1
M_ZP
M_ZN
MEM_MA_RESET#
MEM_MA1_ODT0
MEM_MA1_ODT1
CPU_MA1_CS_L0
CPU_MA1_CS_L1
CPU_MA_CLK_H5
CPU_MA_CLK_L5
CPU_MA_CLK_H4
CPU_MA_CLK_L4
MEM_MA_ADD0
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD3
MEM_MA_ADD4
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD9
MEM_MA_ADD10
MEM_MA_ADD11
MEM_MA_ADD12
MEM_MA_ADD13
MEM_MA_ADD14
MEM_MA_ADD15
+0.9VSMVTT
+0.9VSMVTT
MEM_MB_CLK7_P
MEM_MB_CLK7_N
MEM_MB_CLK1_P
MEM_MB_CLK1_N
U27B
D10
C10
B10
AD10
AF10
AE10
H16
T19
V22
U21
V19
T20
U19
U20
V20
J22
J20
N19
N20
E16
F16
Y16
AA16
P19
P20
N21
M20
N22
M19
M22
L20
M24
L21
L19
K22
R21
L22
K20
V24
K24
K19
R20
R23
J21
R19
T22
T24
SOCKET_638_PIN
C232
4.7U/6.3VC_6
C89
1000P/50VB_4
VTT1
MEM:CMD/CTRL/CLK
VTT2
VTT3
VTT4
MEMZP
MEMZN
RSVD_M1
MA0_ODT0
MA0_ODT1
MA1_ODT0
MA1_ODT1
MA0_CS_L0
MA0_CS_L1
MA1_CS_L0
MA1_CS_L1
MA_CKE0
MA_CKE1
MA_CLK_H5
MA_CLK_L5
MA_CLK_H1
MA_CLK_L1
MA_CLK_H7
MA_CLK_L7
MA_CLK_H4
MA_CLK_L4
MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15
MA_BANK0
MA_BANK1
MA_BANK2
MA_RAS_L
MA_CAS_L
MA_WE_L
C233
4.7U/6.3VC_6
C88
1000P/50VB_4
C524
1.5P/50VA_4
C476
1.5P/50VA_4
W10
VTT5
AC10
VTT6
AB10
VTT7
AA10
VTT8
A10
VTT9
CPU_VTT_SENSE
MEMVREF
RSVD_M2
MB0_ODT0
MB0_ODT1
MB1_ODT0
MB_CKE0
MB_CKE1
MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15
MB_BANK0
MB_BANK1
MB_BANK2
MB_RAS_L
MB_CAS_L
MB_WE_L
Y10
MEMVREF_CPU
W17
MEM_MB_RESET#
B18
W26
W23
MEM_MB1_ODT0
Y26
V26
W25
U22
J25
H26
CPU_MB_CLK_H5
P22
CPU_MB_CLK_L5
R22
A17
A18
AF18
AF17
CPU_MB_CLK_H4
R26
CPU_MB_CLK_L4
R25
MEM_MB_ADD0
P24
MEM_MB_ADD1
N24
MEM_MB_ADD2
P26
MEM_MB_ADD3
N23
MEM_MB_ADD4
N26
MEM_MB_ADD5
L23
MEM_MB_ADD6
N25
MEM_MB_ADD7
L24
MEM_MB_ADD8
M26
MEM_MB_ADD9
K26
MEM_MB_ADD10
T26
MEM_MB_ADD11
L26
MEM_MB_ADD12
L25
MEM_MB_ADD13
W24
MEM_MB_ADD14
J23
MEM_MB_ADD15
J24
R24
U26
J26
U25
U24
U23
VTT_SENSE
MB0_CS_L0
MB0_CS_L1
MB1_CS_L0
MB_CLK_H5
MB_CLK_L5
MB_CLK_H1
MB_CLK_L1
MB_CLK_H7
MB_CLK_L7
MB_CLK_H4
MB_CLK_L4
Place close to socket
C84
4.7U/6.3VC_6
C229
1000P/50VB_4
Close to CPU within 1500 mils
C83
4.7U/6.3VC_6
C238
1000P/50VB_4
MEM_MA_CLK7_P
MEM_MA_CLK7_N
MEM_MA_CLK1_P
MEM_MA_CLK1_N
B
750mA
CPU_VTT_SENSE 36
T4
MEM_MB0_ODT0 8,9
MEM_MB0_ODT1 8,9
T38
MEM_MB0_CS#0 8,9
MEM_MB0_CS#1 8,9
T31
MEM_MB_CKE0 8,9
MEM_MB_CKE1 8,9
T28
T24
MEM_MB_CLK1_P 8
MEM_MB_CLK1_N 8
MEM_MB_CLK7_P 8
MEM_MB_CLK7_N 8
T29
T30
MEM_MB_BANK0 8,9
MEM_MB_BANK1 8,9
MEM_MB_BANK2 8,9
MEM_MB_RAS# 8,9
MEM_MB_CAS# 8,9
MEM_MB_WE# 8,9
C230
0.22U/6.3VC_4
C234
180P/50VA_4
MEM_MB_ADD[0..15] 8,9
C81
0.22U/6.3VC_4
C90
180P/50VA_4
C523
1.5P/50VA_4
C95
1.5P/50VA_4
R365
1K/F_4
C82
0.22U/6.3VC_4
C91
180P/50VA_4
MEM_MB_DATA[0..63]8
R366 1K/F_4
C526
0.1U/10VC_4
MEM_MB_DM[0..7]8
C231
0.22U/6.3VC_4
C92
180P/50VA_4
C
+1.8VSUS
C525
1000P/50VB_4
MEM_MB_DQS0_P8
MEM_MB_DQS0_N8
MEM_MB_DQS1_P8
MEM_MB_DQS1_N8
MEM_MB_DQS2_P8
MEM_MB_DQS2_N8
MEM_MB_DQS3_P8
MEM_MB_DQS3_N8
MEM_MB_DQS4_P8
MEM_MB_DQS4_N8
MEM_MB_DQS5_P8
MEM_MB_DQS5_N8
MEM_MB_DQS6_P8
MEM_MB_DQS6_N8
MEM_MB_DQS7_P8
MEM_MB_DQS7_N8
Processor Memory Interface
MEM_MB_DATA0
MEM_MB_DATA1
MEM_MB_DATA2
MEM_MB_DATA3
MEM_MB_DATA4
MEM_MB_DATA5
MEM_MB_DATA6
MEM_MB_DATA7
MEM_MB_DATA8
MEM_MB_DATA9
MEM_MB_DATA10
MEM_MB_DATA11
MEM_MB_DATA12
MEM_MB_DATA13
MEM_MB_DATA14
MEM_MB_DATA15
MEM_MB_DATA16
MEM_MB_DATA17
MEM_MB_DATA18
MEM_MB_DATA19
MEM_MB_DATA20
MEM_MB_DATA21
MEM_MB_DATA22
MEM_MB_DATA23
MEM_MB_DATA24
MEM_MB_DATA25
MEM_MB_DATA26
MEM_MB_DATA27
MEM_MB_DATA28
MEM_MB_DATA29
MEM_MB_DATA30
MEM_MB_DATA31
MEM_MB_DATA32
MEM_MB_DATA33
MEM_MB_DATA34
MEM_MB_DATA35
MEM_MB_DATA36
MEM_MB_DATA37
MEM_MB_DATA38
MEM_MB_DATA39
MEM_MB_DATA40
MEM_MB_DATA41
MEM_MB_DATA42
MEM_MB_DATA43
MEM_MB_DATA44
MEM_MB_DATA45
MEM_MB_DATA46
MEM_MB_DATA47
MEM_MB_DATA48
MEM_MB_DATA49
MEM_MB_DATA50
MEM_MB_DATA51
MEM_MB_DATA52
MEM_MB_DATA53
MEM_MB_DATA54
MEM_MB_DATA55
MEM_MB_DATA56
MEM_MB_DATA57
MEM_MB_DATA58
MEM_MB_DATA59
MEM_MB_DATA60
MEM_MB_DATA61
MEM_MB_DATA62
MEM_MB_DATA63
MEM_MB_DM0
MEM_MB_DM1
MEM_MB_DM2
MEM_MB_DM3
MEM_MB_DM4
MEM_MB_DM5
MEM_MB_DM6
MEM_MB_DM7
+0.9VSMVTT 9,31,36
+1.8VSUS 5,7,8,9,31,35,36,37
U27C
C11
A11
A14
B14
G11
E11
D12
A13
A15
A16
A19
A20
C14
D14
C18
D18
D20
A21
D24
C25
B20
C20
B24
C24
E23
E24
G25
G26
C26
D26
G23
G24
AA24
AA23
AD24
AE24
AA26
AA25
AD26
AE25
AC22
AD22
AE20
AF20
AF24
AF23
AC20
AD20
AD18
AE18
AC14
AD14
AF19
AC18
AF16
AF15
AF13
AC12
AB11
Y11
AE14
AF14
AF11
AD11
A12
B16
A22
E25
AB26
AE22
AC16
AD12
C12
B12
D16
C16
A24
A23
F26
E26
AC25
AC26
AF21
AF22
AE16
AD16
AF12
AE12
SOCKET_638_PIN
MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63
MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7
MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7
D
MEM:DATA
MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63
MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7
MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7
MEM_MA_DATA0
G12
MEM_MA_DATA1
F12
MEM_MA_DATA2
H14
MEM_MA_DATA3
G14
MEM_MA_DATA4
H11
MEM_MA_DATA5
H12
MEM_MA_DATA6
C13
MEM_MA_DATA7
E13
MEM_MA_DATA8
H15
MEM_MA_DATA9
E15
MEM_MA_DATA10
E17
MEM_MA_DATA11
H17
MEM_MA_DATA12
E14
MEM_MA_DATA13
F14
MEM_MA_DATA14
C17
MEM_MA_DATA15
G17
MEM_MA_DATA16
G18
MEM_MA_DATA17
C19
MEM_MA_DATA18
D22
MEM_MA_DATA19
E20
MEM_MA_DATA20
E18
MEM_MA_DATA21
F18
MEM_MA_DATA22
B22
MEM_MA_DATA23
C23
MEM_MA_DATA24
F20
MEM_MA_DATA25
F22
MEM_MA_DATA26
H24
MEM_MA_DATA27
J19
MEM_MA_DATA28
E21
MEM_MA_DATA29
E22
MEM_MA_DATA30
H20
MEM_MA_DATA31
H22
MEM_MA_DATA32
Y24
MEM_MA_DATA33
AB24
MEM_MA_DATA34
AB22
MEM_MA_DATA35
AA21
MEM_MA_DATA36
W22
MEM_MA_DATA37
W21
MEM_MA_DATA38
Y22
MEM_MA_DATA39
AA22
MEM_MA_DATA40
Y20
MEM_MA_DATA41
AA20
MEM_MA_DATA42
AA18
MEM_MA_DATA43
AB18
MEM_MA_DATA44
AB21
MEM_MA_DATA45
AD21
MEM_MA_DATA46
AD19
MEM_MA_DATA47
Y18
MEM_MA_DATA48
AD17
MEM_MA_DATA49
W16
MEM_MA_DATA50
W14
MEM_MA_DATA51
Y14
MEM_MA_DATA52
Y17
MEM_MA_DATA53
AB17
MEM_MA_DATA54
AB15
MEM_MA_DATA55
AD15
MEM_MA_DATA56
AB13
MEM_MA_DATA57
AD13
MEM_MA_DATA58
Y12
MEM_MA_DATA59
W11
MEM_MA_DATA60
AB14
MEM_MA_DATA61
AA14
MEM_MA_DATA62
AB12
MEM_MA_DATA63
AA12
E12
C15
E19
F24
AC24
Y19
AB16
Y13
G13
H13
G16
G15
C22
C21
G22
G21
AD23
AC23
AB19
AB20
Y15
W15
W12
W13
NB5/RD2/HW1
06
MEM_MA_DM0
MEM_MA_DM1
MEM_MA_DM2
MEM_MA_DM3
MEM_MA_DM4
MEM_MA_DM5
MEM_MA_DM6
MEM_MA_DM7
MEM_MA_DATA[0..63] 8
MEM_MA_DM[0..7] 8
MEM_MA_DQS0_P 8
MEM_MA_DQS0_N 8
MEM_MA_DQS1_P 8
MEM_MA_DQS1_N 8
MEM_MA_DQS2_P 8
MEM_MA_DQS2_N 8
MEM_MA_DQS3_P 8
MEM_MA_DQS3_N 8
MEM_MA_DQS4_P 8
MEM_MA_DQS4_N 8
MEM_MA_DQS5_P 8
MEM_MA_DQS5_N 8
MEM_MA_DQS6_P 8
MEM_MA_DQS6_N 8
MEM_MA_DQS7_P 8
MEM_MA_DQS7_N 8
PROJECT : TT9
Quanta Computer Inc.
Size Document Number Rev
Custom
S1G2 DDRII MEMORY I/F 2/3
Date: Sheet
E
641Wednesday, January 23, 2008
of
1A
5
4
3
2
1
U27F
AA4
VSS1
AA11
U27E
G4
VDD0_1
H2
VDD0_2
J9
VDD0_3
J11
VDD0_4
J13
VDD0_5
D D
+CPUVDDNB
3A
+1.8VSUS
2A
C C
CNTR_VREF5
MBCLK_CPU30
*BSS138_NL/SOT23
MBDATA_CPU30
B B
MBCLK_CPU30
MBDATA_CPU30
A A
SMBALERT# CPU_ALERT
J15
K6
K10
K12
K14
L4
L7
L9
L11
L13
L15
M2
M6
M8
M10
N7
N9
N11
K16
M16
P16
T16
V16
H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17
3
*BSS138_NL/SOT23
R137
10K/F_4
R139 0_4
SMBALERT#
5
VDD0_6
VDD0_7
VDD0_8
VDD0_9
VDD0_10
VDD0_11
VDD0_12
VDD0_13
VDD0_14
VDD0_15
VDD0_16
VDD0_17
VDD0_18
VDD0_19
VDD0_20
VDD0_21
VDD0_22
VDD0_23
VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
SOCKET_638_PIN
2
3
*BSS138_NL/SOT23
PM_THERM# 15
Q15
1
2
R138
10K/F_4
3
VDD1_1
VDD1_2
VDD1_3
VDD1_4
VDD1_5
VDD1_6
VDD1_7
VDD1_8
VDD1_9
VDD1_10
VDD1_11
VDD1_12
VDD1_13
VDD1_14
VDD1_15
VDD1_16
VDD1_17
VDD1_18
VDD1_19
VDD1_20
VDD1_21
VDD1_22
VDD1_23
VDD1_24
VDD1_25
VDD1_26
VDDIO27
VDDIO26
VDDIO25
VDDIO24
VDDIO23
VDDIO22
VDDIO21
VDDIO20
VDDIO19
VDDIO18
VDDIO17
VDDIO16
VDDIO15
VDDIO14
VDDIO13
Q14
1
+3V
+VCORE1+VCORE0 +VCORE0
P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
U15
V6
V8
V10
V12
V14
W4
Y2
2
AC4
AD2
Y25
V25
V23
V21
V18
U17
T25
T23
T21
T18
R17
P25
P23
P21
P18
R131
390_4
CPU_SIC
Q16
1
+1.8VSUS
CPU_SID
+1.8VSUS
R129
390_4
R128
1K/F_4
CPU_SIC 5
CPU_SID 5
CPU_ALERT 5
PROCESSOR POWER AND GROUND
+3V
R140
10K/F_4
U6
8
SCLK
7
SDA
6
ALERT#
4
OVERT#
G781P8
AL007421001
AL000780000 IC OTHER(8P) G780P81U(MSOP-8)
R153
200_4
3V_G781
1
VCC
2
DXP
3
DXN
5
GND
MSOP
IC OTHER(8P) ADT7421ARMZ-REEL(MSOP)
C282
2200P/50VB_4
4
C286
0.1U/10VC_4
H_THRMDA 5
H_THRMDC 5
AA13
AA15
AA17
AA19
AB2
AB7
AB9
AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21
AD6
AD8
AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23
B4
B6
B8
B9
B11
B13
B15
B17
B19
B21
B23
B25
D6
D8
D9
D11
D13
D15
D17
D19
D21
D23
D25
E4
F2
F11
F13
F15
F17
F19
F21
F23
F25
H7
H9
H21
H23
J4
SOCKET_638_PIN
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
R389 *0_6
reserve for
power shutdown
( if can )
R143 0_4
Q37
MMBT3904
2
1 3
+VCORE035
+VCORE135
+CPUVDDNB35
+1.8VSUS 5,6,8,9,31,35,36,37
+3V 4,5,8,9,12,13,14,15,16,17,18,19,20,22,23,26,28,29,30,31,33,34,38
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
R146 1M/F_6
3
J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
AC6
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6
D9
2 1
CH500H
2 1
SYS_SHDN#
D8
*CH500H
3920_RST#
ECPWROK
BOTTOM SIDE DECOUPLING
C169
22U/6.3VC_8
C186
22U/6.3VC_8
C195
22U/6.3VC_8
C151
22U/6.3VC_8
C187
22U/6.3VC_8
C181
22U/6.3VC_8
C168
22U/6.3VC_8
C206
22U/6.3VC_8
+1.8VSUS
C152
22U/6.3VC_8
0.22U/6.3VC_4
C188
0.22U/6.3VC_4
C180
22U/6.3VC_8
C156
C155
0.01U/16VB_4
C197
0.01U/16VB_4
C200
0.22U/6.3VC_4
C174
180P/50VA_4
C183
180P/50VA_4
C203
0.22U/6.3VC_4
0.01U/16VB_4
+VCORE1
22U/6.3VC_8
+CPUVDDNB
22U/6.3VC_8
C166
22U/6.3VC_8
C196
C69
DECOUPLING BETWEEN PROCESSOR AND DIMMs
PLACE CLOSE TO PROCESSOR AS POSSIBLE
+1.8VSUS
C144
4.7U/6.3VC_6
C205
0.22U/6.3VC_4
3920_RST# 30,39
C208
4.7U/6.3VC_6
C204
0.01U/16VB_4
Q35
2N7002E
2
C207
4.7U/6.3VC_6
R390 *0_6
+3V
2
C495
0.22U/6.3VC_4
C146
0.01U/16VB_4
R381
1M/F_6
3
1
C496
180P/50VA_4
2
C538
0.1U/16VB_6
add hardware protect
NB5/RD2/HW1
C147
0.22U/6.3VC_4
1631RESET# 33,39
3
Q34
*2N7002E
1
PROJECT : TT9
Quanta Computer Inc.
Size Document Number Rev
Custom
S1G2 PWR & GND 3/3
Date: Sheet
1
+1.8VSUS
+3V
C143
4.7U/6.3VC_6
C202
0.22U/6.3VC_4
ECPWROK 18,30
C198
C148
180P/50VA_4
07
C145
180P/50VA_4
741Wednesday, January 23, 2008
of
1A
5
+1.8VSUS +1.8VSUS
117
103
111
104
MEM_MA_ADD[0..15]6,9
D D
MEM_MA_BANK[0..2]6,9
MEM_MA_DQS0_P6
MEM_MA_DQS1_P6
MEM_MA_DQS2_P6
MEM_MA_DQS3_P6
MEM_MA_DQS4_P6
MEM_MA_DQS5_P6
MEM_MA_DQS6_P6
C C
B B
A A
MEM_MA_DQS7_P6
MEM_MA_DQS0_N6
MEM_MA_DQS1_N6
MEM_MA_DQS2_N6
MEM_MA_DQS3_N6
MEM_MA_DQS4_N6
MEM_MA_DQS5_N6
MEM_MA_DQS6_N6
MEM_MA_DQS7_N6
MEM_MA_CLK1_P6
MEM_MA_CLK1_N6
MEM_MA_CLK7_P6
MEM_MA_CLK7_N6
MEM_MA_CKE06,9
MEM_MA_CKE16,9
MEM_MA_RAS#6,9
MEM_MA_CAS#6,9
MEM_MA_WE#6,9
MEM_MA0_CS#06,9
MEM_MA0_CS#16,9
MEM_MA0_ODT06,9
MEM_MA0_ODT16,9
PDAT_SMB4,9,15
PCLK_SMB4,9,15
+3V
MEM_MA_ADD0
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD3
MEM_MA_ADD4
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD9
MEM_MA_ADD10
MEM_MA_ADD11
MEM_MA_ADD12
MEM_MA_ADD13
MEM_MA_ADD14
MEM_MA_ADD15
PDAT_SMB
PCLK_SMB
C44
1000P/50VB_4
5
MEM_MA_BANK0
MEM_MA_BANK1
MEM_MA_BANK2
MEM_MA_DM0
MEM_MA_DM1
MEM_MA_DM2
MEM_MA_DM3
MEM_MA_DM4
MEM_MA_DM5
MEM_MA_DM6
MEM_MA_DM7
DIM1_SA0
DIM1_SA1
C214
0.1U/10VC_4
102
A0
101
A1
100
105
116
107
106
130
147
170
185
131
148
169
188
129
146
167
186
164
166
108
113
109
110
115
114
119
198
200
195
197
199
VDD081VDD182VDD287VDD388VDD495VDD596VDD6
A2
99
A3
98
A4
97
A5
94
A6
92
A7
93
A8
91
A9
A10
90
A11
89
A12
A13
86
A14
84
A15
BA0
BA1
85
BA2
10
DM0
26
DM1
52
DM2
67
DM3
DM4
DM5
DM6
DM7
13
DQS0
31
DQS1
51
DQS2
70
DQS3
DQS4
DQS5
DQS6
DQS7
11
DQS0
29
DQS1
49
DQS2
68
DQS3
DQS4
DQS5
DQS6
DQS7
30
CK0
32
CK0
CK1
CK1
79
CKE0
80
CKE1
RAS
CAS
WE
S0
S1
ODT0
ODT1
SA0
SA1
SDA
SCL
VDDspd
1
VREF
2
VSS0
3
VSS1
8
VSS2
9
VSS3
12
VSS4
15
VSS5
18
VSS6
21
VSS7
24
VSS8
27
VSS9
28
VSS10
33
VSS11
34
VSS12
39
VSS13
40
VSS14
41
VSS15
42
VSS16
47
VSS17
48
VSS18
53
VSS19
54
VSS20
59
DDR SO-DIMM SOCKET 1.8V
H=5.2 H=9.2
R125 10K/F_4
R124 10K/F_4
112
VDD8
VDD7
VDD9
VDD10
SO-DIMM
(REVERSE)
VSS31
VSS30
VSS29
VSS2878VSS2777VSS2672VSS2571VSS2466VSS2365VSS2260VSS21
127
122
121
DIM1_SA0
DIM1_SA1
118
VDD11
NC/TEST
VSS33
VSS32
132
128
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
NC1
NC2
NC3
NC4
VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
CN23
4
5
7
17
19
4
6
14
16
23
25
35
37
20
22
36
38
43
45
55
57
44
46
56
58
61
63
73
75
62
64
74
76
123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194
50
69
83
120
163
196
193
190
187
184
183
178
177
172
171
168
165
162
161
156
155
150
149
145
144
139
138
133
4
MEM_MA_DATA5
MEM_MA_DATA4
MEM_MA_DATA2
MEM_MA_DATA3
MEM_MA_DATA0
MEM_MA_DATA1
MEM_MA_DATA6
MEM_MA_DATA7
MEM_MA_DATA9
MEM_MA_DATA8
MEM_MA_DATA10
MEM_MA_DATA14
MEM_MA_DATA13
MEM_MA_DATA12
MEM_MA_DATA15
MEM_MA_DATA11
MEM_MA_DATA19
MEM_MA_DATA21
MEM_MA_DATA18
MEM_MA_DATA16
MEM_MA_DATA20
MEM_MA_DATA17
MEM_MA_DATA22
MEM_MA_DATA23
MEM_MA_DATA24
MEM_MA_DATA25
MEM_MA_DATA31
MEM_MA_DATA26
MEM_MA_DATA28
MEM_MA_DATA29
MEM_MA_DATA27
MEM_MA_DATA30
MEM_MA_DATA32
MEM_MA_DATA38
MEM_MA_DATA36
MEM_MA_DATA37
MEM_MA_DATA33
MEM_MA_DATA39
MEM_MA_DATA34
MEM_MA_DATA35
MEM_MA_DATA44
MEM_MA_DATA40
MEM_MA_DATA46
MEM_MA_DATA42
MEM_MA_DATA45
MEM_MA_DATA41
MEM_MA_DATA43
MEM_MA_DATA47
MEM_MA_DATA53
MEM_MA_DATA49
MEM_MA_DATA55
MEM_MA_DATA50
MEM_MA_DATA48
MEM_MA_DATA52
MEM_MA_DATA54
MEM_MA_DATA51
MEM_MA_DATA60
MEM_MA_DATA56
MEM_MA_DATA63
MEM_MA_DATA62
MEM_MA_DATA57
MEM_MA_DATA61
MEM_MA_DATA58
MEM_MA_DATA59
MEMHOT_SODIMM#_1
MEM_MA_RESET#1
MEM_MA_NC5
+1.8VSUS 5,6,7,9,31,35,36,37
+3V 4,5,7,9,12,13,14,15,16,17,18,19,20,22,23,26,28,29,30,31,33,34,38
MEM_MA_DATA[0..63] 6
R68 0_4
T6
+0.9VSMVREF36
R27 2K/F_4
C34 0.1U/10VC_4
C32 2.2U/6.3VC_6
MEM_MB_ADD[0..15]6,9 MEM_MB_DATA[0..63] 6
MEM_MB_BANK[0..2]6,9
MEMHOT_SODIMM# 9
+0.9VSMVREF_DIMM+0.9VSMVREF_DIMM
+0.9VSMVREF_DIMM
R29 2K/F_4
+0.9VSMVREF_DIMM
+0.9VSMVREF_DIMM
3
MEM_MB_DM[0..7]6MEM_MA_DM[0..7]6
MEM_MB_DQS0_P6
MEM_MB_DQS1_P6
MEM_MB_DQS2_P6
MEM_MB_DQS3_P6
MEM_MB_DQS4_P6
MEM_MB_DQS5_P6
MEM_MB_DQS6_P6
MEM_MB_DQS7_P6
MEM_MB_DQS0_N6
MEM_MB_DQS1_N6
MEM_MB_DQS2_N6
MEM_MB_DQS3_N6
MEM_MB_DQS4_N6
MEM_MB_DQS5_N6
MEM_MB_DQS6_N6
MEM_MB_DQS7_N6
MEM_MB_CLK1_P6
MEM_MB_CLK1_N6
MEM_MB_CLK7_P6
MEM_MB_CLK7_N6
MEM_MB_CKE06,9
MEM_MB_CKE16,9
MEM_MB_RAS#6,9
MEM_MB_CAS#6,9
MEM_MB_WE#6,9
MEM_MB0_CS#06,9
MEM_MB0_CS#16,9
MEM_MB0_ODT06,9
MEM_MB0_ODT16,9
+3V
R28 *0_4
C35 0.1U/10VC_4
C39 2.2U/6.3VC_6
3
MEM_MB_ADD0
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MB_ADD3
MEM_MB_ADD4
MEM_MB_ADD5
MEM_MB_ADD6
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MB_ADD9
MEM_MB_ADD10
MEM_MB_ADD11
MEM_MB_ADD12
MEM_MB_ADD13
MEM_MB_ADD14
MEM_MB_ADD15
MEM_MB_BANK0
MEM_MB_BANK1
MEM_MB_BANK2
MEM_MB_DM0
MEM_MB_DM1
MEM_MB_DM2
MEM_MB_DM3
MEM_MB_DM4
MEM_MB_DM5
MEM_MB_DM6
MEM_MB_DM7
DIM2_SA0
DIM2_SA1
PDAT_SMB
PCLK_SMB
C31
1000P/50VB_4
+1.8VSUS
C219
0.1U/10VC_4
102
A0
101
A1
100
105
116
107
106
130
147
170
185
131
148
169
188
129
146
167
186
164
166
108
113
109
110
115
114
119
198
200
195
197
199
VDD081VDD182VDD287VDD388VDD495VDD596VDD6
A2
99
A3
98
A4
97
A5
94
A6
92
A7
93
A8
91
A9
A10
90
A11
89
A12
A13
86
A14
84
A15
BA0
BA1
85
BA2
10
DM0
26
DM1
52
DM2
67
DM3
DM4
DM5
DM6
DM7
13
DQS0
31
DQS1
51
DQS2
70
DQS3
DQS4
DQS5
DQS6
DQS7
11
DQS0
29
DQS1
49
DQS2
68
DQS3
DQS4
DQS5
DQS6
DQS7
30
CK0
32
CK0
CK1
CK1
79
CKE0
80
CKE1
RAS
CAS
WE
S0
S1
ODT0
ODT1
SA0
SA1
SDA
SCL
VDDspd
1
VREF
2
VSS0
o
3
VSS1
8
VSS2
o
9
VSS3
12
VSS4
15
VSS5
18
VSS6
21
VSS7
24
VSS8
27
VSS9
28
VSS10
33
VSS11
34
VSS12
39
VSS13
40
VSS14
41
VSS15
42
VSS16
47
VSS17
48
VSS18
53
VSS19
54
VSS20
59
DDR SO-DIMM SOCKET 1.8V
DIM2_SA0
R123 10K/F_4
DIM2_SA1
R126 10K/F_4
SMbus address A2SMbus address A0
2
117
118
103
111
104
112
CN22
DQ0
DQ1
VDD8
VDD7
VDD9
VDD10
VDD11
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
NC1
NC2
NC3
NC4
NC/TEST
VSS56
SO-DIMM
(REVERSE)
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
VSS29
VSS2878VSS2777VSS2672VSS2571VSS2466VSS2365VSS2260VSS21
132
128
127
122
121
+3V
2
MEM_MB_DATA1
5
MEM_MB_DATA4
7
MEM_MB_DATA3
17
MEM_MB_DATA2
19
MEM_MB_DATA5
4
MEM_MB_DATA0
6
MEM_MB_DATA7
14
MEM_MB_DATA6
16
MEM_MB_DATA9
23
MEM_MB_DATA13
25
MEM_MB_DATA14
35
MEM_MB_DATA10
37
MEM_MB_DATA8
20
MEM_MB_DATA12
22
MEM_MB_DATA15
36
MEM_MB_DATA11
38
MEM_MB_DATA16
43
MEM_MB_DATA17
45
MEM_MB_DATA18
55
MEM_MB_DATA23
57
MEM_MB_DATA20
44
MEM_MB_DATA21
46
MEM_MB_DATA22
56
MEM_MB_DATA19
58
MEM_MB_DATA24
61
MEM_MB_DATA29
63
MEM_MB_DATA30
73
MEM_MB_DATA31
75
MEM_MB_DATA28
62
MEM_MB_DATA25
64
MEM_MB_DATA27
74
MEM_MB_DATA26
76
MEM_MB_DATA36
123
MEM_MB_DATA37
125
MEM_MB_DATA35
135
MEM_MB_DATA34
137
MEM_MB_DATA32
124
MEM_MB_DATA33
126
MEM_MB_DATA38
134
MEM_MB_DATA39
136
MEM_MB_DATA44
141
MEM_MB_DATA41
143
MEM_MB_DATA47
151
MEM_MB_DATA46
153
MEM_MB_DATA40
140
MEM_MB_DATA45
142
MEM_MB_DATA42
152
MEM_MB_DATA43
154
MEM_MB_DATA52
157
MEM_MB_DATA54
159
MEM_MB_DATA50
173
MEM_MB_DATA53
175
MEM_MB_DATA48
158
MEM_MB_DATA49
160
MEM_MB_DATA55
174
MEM_MB_DATA51
176
MEM_MB_DATA60
179
MEM_MB_DATA61
181
MEM_MB_DATA62
189
MEM_MB_DATA59
191
MEM_MB_DATA57
180
MEM_MB_DATA56
182
MEM_MB_DATA58
192
MEM_MB_DATA63
194
MEMHOT_SODIMM#_2
50
MEM_MB_RESET#2
69
83
120
MEM_MB_NC5
163
196
193
190
187
184
183
178
177
172
171
168
165
162
161
156
155
150
149
145
144
139
138
133
NB5/RD2/HW1
1
08
R67 0_4
T5
T36T37
Size Document Number Rev
Custom
Date: Sheet
MEMHOT_SODIMM#
PROJECT : TT9
Quanta Computer Inc.
DDR2 SODIMMS: A/B CHANNEL
1
841Wednesday, January 23, 2008
of
1A
5
4
3
2
1
MEM_MA_ADD[0..15]6,8
MEM_MA_BANK[0..2]6,8
MEM_MA_CKE06,8
D D
MEM_MA_WE#6,8
MEM_MA0_CS#16,8
MEM_MA_CAS#6,8
MEM_MA0_ODT16,8
MEM_MA_CKE16,8
MEM_MA0_ODT06,8
MEM_MA0_CS#06,8
MEM_MA_RAS#6,8
C C
MEM_MA_CKE0
MEM_MA_BANK2
MEM_MA_ADD12
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD5
MEM_MA_ADD3
MEM_MA_ADD1
MEM_MA_BANK0
MEM_MA_ADD10
MEM_MA_WE#
MEM_MA0_CS#1
MEM_MA_CAS#
MEM_MA0_ODT1
MEM_MA_ADD15
MEM_MA_CKE1
MEM_MA_ADD14
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD11
MEM_MA_ADD2
MEM_MA_ADD4
MEM_MA0_ODT0
MEM_MA0_CS#0
MEM_MA_RAS#
MEM_MA_ADD0
MEM_MA_ADD13
MEM_MA_BANK1
RP5 47RX2_4P2R_4
4
2
RP9 47RX2_4P2R_4
4
2
RP12 47RX2_4P2R_4
4
2
RP16 47RX2_4P2R_4
4
2
RP18 47RX2_4P2R_4
4
2
RP22 47RX2_4P2R_4
4
2
RP27 47RX2_4P2R_4
4
2
RP2 47RX2_4P2R_4
4
2
RP6 47RX2_4P2R_4
4
2
RP10 47RX2_4P2R_4
4
2
RP14 47RX2_4P2R_4
4
2
RP26 47RX2_4P2R_4
4
2
RP19 47RX2_4P2R_4
4
2
RP23 47RX2_4P2R_4
4
2
MEM_MA_ADD[0..15]
MEM_MA_BANK[0..2]
+0.9VSMVTT
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
3
1
C115 0.1U/10VC_4
C107 0.1U/10VC_4
C116 0.1U/10VC_4
C135 0.1U/10VC_4
C157 0.1U/10VC_4
C104 0.1U/10VC_4
C128 0.1U/10VC_4
C150 0.1U/10VC_4
C110 0.1U/10VC_4
C106 0.1U/10VC_4
C100 0.1U/10VC_4
C158 0.1U/10VC_4
C141 0.1U/10VC_4
C160 0.1U/10VC_4
C138 0.1U/10VC_4
C108 0.1U/10VC_4
+1.8VSUS
+1.8VSUS
+1.8VSUS
+1.8VSUS
+1.8VSUS
+1.8VSUS
+1.8VSUS
+1.8VSUS
MEM_MB_ADD[0..15]6,8
MEM_MB_BANK[0..2]6,8
MEM_MB_CKE06,8
MEM_MB_WE#6,8
MEM_MB_CAS#6,8
MEM_MB0_ODT16,8
MEM_MB0_CS#16,8
MEM_MB_CKE16,8
MEM_MB0_CS#06,8
MEM_MB_RAS#6,8
MEM_MB0_ODT06,8
MEM_MB_CKE0
MEM_MB_BANK2
MEM_MB_ADD9
MEM_MB_ADD12
MEM_MB_ADD8
MEM_MB_ADD5
MEM_MB_ADD3
MEM_MB_ADD1
MEM_MB_BANK0
MEM_MB_ADD10
MEM_MB_WE#
MEM_MB_CAS#
MEM_MB0_ODT1
MEM_MB0_CS#1
MEM_MB_ADD7
MEM_MB_ADD14
MEM_MB_CKE1
MEM_MB_ADD15
MEM_MB_ADD4
MEM_MB_ADD11
MEM_MB_ADD2
MEM_MB_ADD6
MEM_MB_BANK1
MEM_MB_ADD0
MEM_MB0_CS#0
MEM_MB_RAS#
MEM_MB_ADD13
MEM_MB0_ODT0
MEM_MB_ADD[0..15]
MEM_MB_BANK[0..2]
+0.9VSMVTT
RP3 47RX2_4P2R_4
4
3
2
RP7 47RX2_4P2R_4
RP11 47RX2_4P2R_4
RP15 47RX2_4P2R_4
RP20 47RX2_4P2R_4
RP24 47RX2_4P2R_4
RP28 47RX2_4P2R_4
RP4 47RX2_4P2R_4
RP1 47RX2_4P2R_4
RP8 47RX2_4P2R_4
RP13 47RX2_4P2R_4
RP17 47RX2_4P2R_4
RP21 47RX2_4P2R_4
RP25 47RX2_4P2R_4
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
C132 0.1U/10VC_4
C490 0.1U/10VC_4
C140 0.1U/10VC_4
C120 0.1U/10VC_4
C131 0.1U/10VC_4
C109 0.1U/10VC_4
C118 0.1U/10VC_4
C111 0.1U/10VC_4
C102 0.1U/10VC_4
C123 0.1U/10VC_4
C153 0.1U/10VC_4
C98 0.1U/10VC_4
C134 0.1U/10VC_4
C119 0.1U/10VC_4
C165 0.1U/10VC_4
09
+1.8VSUS
+1.8VSUS
+1.8VSUS
+1.8VSUS
+1.8VSUS
+1.8VSUS
+1.8VSUS
Emi request
+0.9VSMVTT
C220
100P/50VA_4
C79
*1200P/50VB_4
C222
*2200P/50VB_4
C77
100P/50VA_4
C221
0.1U/10VC_4
C78
0.1U/10VC_4
PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH
PLACE CLOSE TO PROCESSOR
PV fix +3VS5 leakage to +3V
B B
+3VS5
Remove
Close DDR2 socket
U28
A07+VS
+3V
PDAT_SMB4,8,15
A A
PCLK_SMB4,8,15
+3V
6
A1
5
A2
PDAT_SMB
1
PCLK_SMB
R117 10K/F_4
SDA
2
SCL
*DS75U+T&R
+3V
8
MEMHOT_SODIMM#
3
O.S
4
GND
Address:92h
MEMHOT_SODIMM#
C215 *0.1U/10VC_4
MEMHOT_SODIMM# 8
2
Q13
*2N7002E-G
+3V
R116
*10K/F_4
MEMHOT_1#
3
1
R113 *33_4
MEMHOT_2#
2
Q10
*2N7002E-G
3
1
R115
10K/F_4
CPU_MEMHOT# 5,15
+1.8VSUS
+1.8VSUS
C498
0.1U/10VC_4
C489
0.1U/10VC_4
WITHIN 1.5 INCH
C137
0.1U/10VC_4
C494
0.1U/10VC_4
C105
0.1U/10VC_4
PLACE CLOSE TO SOCKET( PER EMI/EMC)
C486
0.1U/10VC_4
C501
0.1U/10VC_4
C125
0.1U/10VC_4
PLACE CLOSE TO SOCKET( PER EMI/EMC)
C482
0.1U/10VC_4
C491
0.1U/10VC_4
C488
0.1U/10VC_4
C112
0.1U/10VC_4
PROJECT : TT9
Quanta Computer Inc.
+0.9VSMVTT 6,31,36
+1.8VSUS 5,6,7,8,31,35,36,37
+3V 4,5,7,8,12,13,14,15,16,17,18,19,20,22,23,26,28,29,30,31,33,34,38
5
4
3
2
NB5/RD2/HW1
Size Document Number Rev
Custom
DDR2 SODIMMS TERMINATIONS
Date: Sheet
941Wednesday, January 23, 2008
1
of
1A
5
HT_CPU_NB_CAD_H0
HT_CPU_NB_CAD_L0
HT_CPU_NB_CAD_H1
HT_CPU_NB_CAD_L1
HT_CPU_NB_CAD_H2
HT_CPU_NB_CAD_L2
HT_CPU_NB_CAD_H3
HT_CPU_NB_CAD_L3
HT_CPU_NB_CAD_H4
HT_CPU_NB_CAD_L4
D D
C C
PV modified -Âfollow AMD
check list to
change part
number 300 ohm
to 301 ohm
B B
+1.8V_MEM_VDDQ
A A
HT_CPU_NB_CAD_H5
HT_CPU_NB_CAD_L5
HT_CPU_NB_CAD_H6
HT_CPU_NB_CAD_L6
HT_CPU_NB_CAD_H7
HT_CPU_NB_CAD_L7
HT_CPU_NB_CAD_H8
HT_CPU_NB_CAD_L8
HT_CPU_NB_CAD_H9
HT_CPU_NB_CAD_L9
HT_CPU_NB_CAD_H10
HT_CPU_NB_CAD_L10
HT_CPU_NB_CAD_H11
HT_CPU_NB_CAD_L11
HT_CPU_NB_CAD_H12
HT_CPU_NB_CAD_L12
HT_CPU_NB_CAD_H13
HT_CPU_NB_CAD_L13
HT_CPU_NB_CAD_H14
HT_CPU_NB_CAD_L14
HT_CPU_NB_CAD_H15
HT_CPU_NB_CAD_L15
HT_CPU_NB_CLK_H0
HT_CPU_NB_CLK_L0
HT_CPU_NB_CLK_H1
HT_CPU_NB_CLK_L1
HT_CPU_NB_CTL_H0
HT_CPU_NB_CTL_L0
HT_CPU_NB_CTL_H1
HT_CPU_NB_CTL_L1
R350 301/F_4
SPM_A0
SPM_A1
SPM_A2
SPM_A3
SPM_A4
SPM_A5
SPM_A6
SPM_A7
SPM_A8
SPM_A9
SPM_A10
SPM_A11
T33
SPM_A12
SPM_A13
SPM_BA0
SPM_BA1
SPM_BA2
SPM_RAS#
SPM_CAS#
SPM_WE#
SPM_CS#
SPM_CKE
SPM_ODT
SPM_CLKP
SPM_CLKN
R361 40.2/F_4
R362 40.2/F_4
HT_RXCALP
HT_RXCALN
SPM_COMPP
SPM_COMPN
All external components connected to
SPMEM signals must be removed
for RX780
Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25
AC24
AC25
AB25
AB24
AA24
AA25
Y22
Y23
W21
W20
V21
V20
U20
U21
U19
U18
T22
T23
AB23
AA22
M22
M23
R21
R20
C23
A24
AB12
AE16
V11
AE15
AA12
AB16
AB14
AD14
AD13
AD15
AC16
AE13
AC14
Y14
AD16
AE17
AD17
W12
Y12
AD18
AB13
AB18
V14
V15
W14
AE12
AD12
U26A
HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N
HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N
HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N
HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N
HT_RXCALP
HT_RXCALN
RS780M
U26D
MEM_A0(NC)
MEM_A1(NC)
MEM_A2(NC)
MEM_A3(NC)
MEM_A4(NC)
MEM_A5(NC)
MEM_A6(NC)
MEM_A7(NC)
MEM_A8(NC)
MEM_A9(NC)
MEM_A10(NC)
MEM_A11(NC)
MEM_A12(NC)
MEM_A13(NC)
MEM_BA0(NC)
MEM_BA1(NC)
MEM_BA2(NC)
MEM_RASb(NC)
MEM_CASb(NC)
MEM_WEb(NC)
MEM_CSb(NC)
MEM_CKE(NC)
MEM_ODT(NC)
MEM_CKP(NC)
MEM_CKN(NC)
MEM_COMPP(NC)
MEM_COMPN(NC)
RS780M
PART 1 OF 6
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N
HYPER TRANSPORT CPU I/F
PAR 4 OF 6
MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC)
MEM_DQ3/DVO_D0(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)
MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)
MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)
MEM_DQS1P(NC)
MEM_DQS1N(NC)
MEM_DM1/DVO_D8(NC)
SBD_MEM/DVO_I/F
IOPLLVDD18(NC)
HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N
HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N
HT_TXCALP
HT_TXCALN
MEM_DQ4(NC)
MEM_DQ12(NC)
MEM_DM0(NC)
IOPLLVDD(NC)
IOPLLVSS(NC)
MEM_VREF(NC)
4
HT_NB_CPU_CAD_H0
D24
HT_NB_CPU_CAD_L0
D25
HT_NB_CPU_CAD_H1
E24
HT_NB_CPU_CAD_L1
E25
HT_NB_CPU_CAD_H2
F24
HT_NB_CPU_CAD_L2
F25
HT_NB_CPU_CAD_H3
F23
HT_NB_CPU_CAD_L3
F22
HT_NB_CPU_CAD_H4
H23
HT_NB_CPU_CAD_L4
H22
HT_NB_CPU_CAD_H5
J25
HT_NB_CPU_CAD_L5
J24
HT_NB_CPU_CAD_H6
K24
HT_NB_CPU_CAD_L6
K25
HT_NB_CPU_CAD_H7
K23
HT_NB_CPU_CAD_L7
K22
HT_NB_CPU_CAD_H8
F21
HT_NB_CPU_CAD_L8
G21
HT_NB_CPU_CAD_H9
G20
HT_NB_CPU_CAD_L9
H21
HT_NB_CPU_CAD_H10
J20
HT_NB_CPU_CAD_L10
J21
HT_NB_CPU_CAD_H11
J18
HT_NB_CPU_CAD_L11
K17
HT_NB_CPU_CAD_H12
L19
HT_NB_CPU_CAD_L12
J19
HT_NB_CPU_CAD_H13
M19
HT_NB_CPU_CAD_L13
L18
HT_NB_CPU_CAD_H14
M21
HT_NB_CPU_CAD_L14
P21
HT_NB_CPU_CAD_H15
P18
HT_NB_CPU_CAD_L15
M18
HT_NB_CPU_CLK_H0
H24
HT_NB_CPU_CLK_L0
H25
HT_NB_CPU_CLK_H1
L21
HT_NB_CPU_CLK_L1
L20
HT_NB_CPU_CTL_H0
M24
HT_NB_CPU_CTL_L0
M25
HT_NB_CPU_CTL_H1
P19
HT_NB_CPU_CTL_L1
R18
HT_TXCALP
B24
HT_TXCALN
B25
AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21
Y17
W18
AD20
AE21
W17
AE19
AE23
AE24
AD23
AE18
R359 1K/F_4
C518 0.1U/10VC_4
R341 301/F_4
PV modified -Âfollow AMD
check list to
change part
number 300 ohm
to 301 ohm
SPM_DQ0
SPM_DQ1
SPM_DQ2
SPM_DQ3
SPM_DQ4
SPM_DQ5
SPM_DQ6
SPM_DQ7
SPM_DQ8
SPM_DQ9
SPM_DQ10
SPM_DQ11
SPM_DQ12
SPM_DQ13
SPM_DQ14
SPM_DQ15
SPM_DQS0P
SPM_DQS0N
SPM_DQS1P
SPM_DQS1N
SPM_DM0
SPM_DM1
+1.8_IOPLLVDD18_NB
+1.1V_IOPLLVDD
SPM_VREF1
C522
2.2U/6.3VC_6
R360 1K/F_4
C517 0.1U/10VC_4
BLM18PG221SN1D
L50
L49
BLM18PG221SN1D
C521
2.2U/6.3VC_6
3
HT_CPU_NB_CAD_H[15..0]
HT_CPU_NB_CAD_L[15..0]
HT_CPU_NB_CLK_H[1..0]
HT_CPU_NB_CLK_L[1..0]
HT_CPU_NB_CTL_H[1..0]
HT_CPU_NB_CTL_L[1..0]
HT_NB_CPU_CAD_H[15..0]
HT_NB_CPU_CAD_L[15..0]
HT_NB_CPU_CLK_H[1..0]
HT_NB_CPU_CLK_L[1..0]
HT_NB_CPU_CTL_H[1..0]
HT_NB_CPU_CTL_L[1..0]
+1.8V
+1.1V
+1.8V_MEM_VDDQ
HT_CPU_NB_CAD_H[15..0] 5
HT_CPU_NB_CAD_L[15..0] 5
HT_CPU_NB_CLK_H[1..0] 5
HT_CPU_NB_CLK_L[1..0] 5
HT_CPU_NB_CTL_H[1..0] 5
HT_CPU_NB_CTL_L[1..0] 5
HT_NB_CPU_CAD_H[15..0] 5
HT_NB_CPU_CAD_L[15..0] 5
HT_NB_CPU_CLK_H[1..0] 5
HT_NB_CPU_CLK_L[1..0] 5
HT_NB_CPU_CTL_H[1..0] 5
HT_NB_CPU_CTL_L[1..0] 5
+1.8V_MEM_VDDQ
C271
0.1U/10VC_4
C270
0.1U/10VC_4
R383
1K/F_4
R386
1K/F_4
2
C529
0.1U/10VC_4
C246
0.1U/10VC_4
SPM_CLKN
R135
100_4
Within 200mils
SPM_CLKP
Close to U23
SPM_BA0
SPM_BA1
SPM_A12
SPM_A11
SPM_A10
SPM_A9
SPM_A8
SPM_A7
SPM_A6
SPM_A5
SPM_A4
SPM_A3
SPM_A2
SPM_A1
SPM_A0
SPM_CLKN
SPM_CLKP
SPM_CKE
SPM_CS#
SPM_WE#
SPM_RAS#
SPM_CAS#
SPM_DM0
SPM_DM1
SPM_ODT
SPM_DQS0P
SPM_DQS0N
SPM_DQS1P
SPM_DQS1N
SPM_VREF
SPM_BA2
C532
1U/10VC_4
L2
L3
R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8
K8
J8
K2
L8
K3
K7
L7
F3
B3
K9
F7
E8
B7
A8
J2
A2
E2
L1
R3
R7
R8
U29
BA0
BA1
A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CK
CK
CKE
CS
WE
RAS
CAS
LDM
UDM
ODT
LDQS
LDQS
UDQS
UDQS
VREF
NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8
64M*16*4
C536
1U/10VC_4
VDDQ10
VSSQ10
40mils wdith or more
+1.8V_MEM_VDDQ
C535
10U/6.3VC_8
B9
DQ15
B1
DQ14
D9
DQ13
D1
DQ12
D3
DQ11
D7
DQ10
C2
DQ9
C8
DQ8
F9
DQ7
F1
DQ6
H9
DQ5
H1
DQ4
H3
DQ3
H7
DQ2
G2
DQ1
G8
DQ0
A9
VDDQ1
C1
VDDQ2
C3
VDDQ3
C7
VDDQ4
C9
VDDQ5
E9
VDDQ6
G1
VDDQ7
G3
VDDQ8
G7
VDDQ9
G9
A1
VDD1
E1
VDD2
J9
VDD3
M9
VDD4
R1
VDD5
J1
VDDL
J7
VSSDL
A7
VSSQ1
B2
VSSQ2
B8
VSSQ3
D2
VSSQ4
D8
VSSQ5
E7
VSSQ6
F2
VSSQ7
F8
VSSQ8
H2
VSSQ9
H8
A3
VSS1
E3
VSS2
J3
VSS3
N1
VSS4
P9
VSS5
1
C528
10U/6.3VC_8
40mils wdith or more
SPM_DQ15
SPM_DQ14
SPM_DQ9
SPM_DQ12
SPM_DQ8
SPM_DQ10
SPM_DQ13
SPM_DQ11
SPM_DQ5
SPM_DQ3
SPM_DQ4
SPM_DQ1
SPM_DQ0
SPM_DQ7
SPM_DQ2
SPM_DQ6
+1.8V_MEM_VDDQ
MEM_VDDQ_VDDL
10
R377 0_6
L53
BLM18PG221SN1D
C537
1U/10VC_4
+1.8V
PROJECT : TT9
Quanta Computer Inc.
+0.9VSMVTT 6,9,31,36
+1.1V 11,12,13,37
+1.8V 5,12,13,14,15,18,36,38
5
4
3
2
NB5/RD2/HW1
Size Document Number Rev
Custom
RS780M-HT LINK I/F 1/4
Date: Sheet
1
10 41Wednesday, January 23, 2008
of
1A
5
D4
C4
A3
B3
AE3
AD4
AE2
AD3
AD1
AD2
AA8
AA7
AA5
AA6
C2
C1
E5
F5
G5
G6
H5
H6
J6
J5
J7
J8
L5
L6
M8
L8
P7
M7
P5
M5
R8
P8
R6
R5
P4
P3
T4
T3
V5
W6
U5
U6
U8
U7
Y8
Y7
W5
Y5
D D
C C
PCIE_RXP028
PCIE_RXN028
PCIE_RXP131
PCIE_RXN131
PCIE_RXP2_LAN26
PCIE_SB_NB_RX0P14
PCIE_SB_NB_RX0N14
PCIE_SB_NB_RX1P14
PCIE_SB_NB_RX1N14
PCIE_SB_NB_RX2P14
B B
PCIE_SB_NB_RX2N14
PCIE_SB_NB_RX3P14
PCIE_SB_NB_RX3N14
PCIE_RXP0
PCIE_RXN0
PCIE_RXP1
PCIE_RXN1
PCIE_RXP2_LAN
PCIE_RXN2_LAN PCIE_TXN2_C
U26B
GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N
GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
GPP_RX4P
GPP_RX4N
GPP_RX5P
GPP_RX5N
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
RS780M
4
PART 2 OF 6
PCIE I/F GFX
PCIE I/F GPP
PCIE I/F SB
PCE_CALRP(PCE_BCALRP)
PCE_CALRN(PCE_BCALRN)
GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2
AC1
AC2
AB4
AB3
AA2
AA1
Y1
Y2
Y4
Y3
V1
V2
AD7
AE7
AE6
AD6
AB6
AC6
AD5
AE5
AC8
AB8
PCIE_TXP0_C
PCIE_TXN0_C
PCIE_TXP1_C
PCIE_TXN1_C
PCIE_TXP2_C
A_TX0P_C
A_TX0N_C
A_TX1P_C
A_TX1N_C
A_TX2P_C
A_TX2N_C
A_TX3P_C
A_TX3N_C
NB_PCIECALRP
NB_PCIECALRN
3
C510 0.1U/10VC_4
C509 0.1U/10VC_4
C507 0.1U/10VC_4
C508 0.1U/10VC_4
C505 0.1U/10VC_4
C506 0.1U/10VC_4
C520 0.1U/10VC_4
C519 0.1U/10VC_4
C513 0.1U/10VC_4
C514 0.1U/10VC_4
C511 0.1U/10VC_4
C512 0.1U/10VC_4
C516 0.1U/10VC_4
C515 0.1U/10VC_4
R364 1.27K/F_4
R363 2K/F_4
Fixed to RS780M
PCIE_TXP0 28
PCIE_TXN0 28
PCIE_TXP1 31
PCIE_TXN1 31
PCIE_TXP2_LAN 26
PCIE_TXN2_LAN 26PCIE_RXN2_LAN26
PCIE_NB_SB_TX0P 14
PCIE_NB_SB_TX0N 14
PCIE_NB_SB_TX1P 14
PCIE_NB_SB_TX1N 14
PCIE_NB_SB_TX2P 14
PCIE_NB_SB_TX2N 14
PCIE_NB_SB_TX3P 14
PCIE_NB_SB_TX3N 14
+1.1V
2
GPP0
GPP1
GPP2
1
11
EXPRESS CARD (NEW CARD)
Wireless Lan
PCIE LAN(Realtek)
+1.1V 10,12,13,37
A A
PROJECT : TT9
Quanta Computer Inc.
Size Document Number Rev
B
NB5/RD2/HW1
5
4
3
2
RS780M-PCIE I/F 2/4
Date: Sheet
1
11 41Wednesday, January 23, 2008
1A
of
5
Enables the Test Debug Bus using GPIO.
0 : Enable
1 : Disable
(RS780 use VSYNC#)
D D
Enables Side port memory
0: Enable (RS780)
1: Disable(RS780)
( RS780 use HSYNC#)
default values if not connected
RS780:SUS_STAT
S-CD1
C C
R88 *3K_4
AUX CAL Value need update
VSYNC_COM
HSYNC_COM
RS780_AUX_CAL
DYN_1.1_NB
R344 3K_4
R345 *3K_4
R95 *3K_4
R96 3K_4
R100 3K_4
R91 *4.7K_4
R90 2.2K_4
+3V
+3V
+3V
PV modified for
AMD sighting
update
4
R87 150/F_4
R86 150/F_4
R89 150/F_4
R347 150/F_4
R346 150/F_4
R343 150/F_4
S-CD1
S-YD1
S-CVBS1
0.5"~1"
CRT_R
CRT_G
CRT_B
EXT_NB_OSC4
+1.1V
As output to the voltage
regulator for PWM of
RS780M core voitage.
NB_PWRGD_IN18
HSYNC_COM20
VSYNC_COM20
R105
4.7K_4
DYN_1.1_NB34
3
+3V_AVDD_NB
+1.8V_AVDDDI_NB
+1.8V_AVDDQ_NB
+3V
R106
4.7K_4
S-CD1
S-YD1
S-CVBS1
CRT_R
CRT_G
CRT_B
HSYNC_COM
VSYNC_COM
DDCDATA
DDCCLK
R98 715/F_6
R102 0_4
R94 *4.7K_4
T10
T8
T7
T19
DAC_RSET_NB
+1.1V_PLLVDD
+1.8V_PLLVDD18
+1.8V_VDDA18HTPLL
+1.8V_VDDA18PCIEPLL
NB_RST#_IN
NB_PWRGD_IN
NB_LDT_STOP#
NB_ALLOW_LDTSTOP
NBHT_REFCLKP
NBHT_REFCLKN
NBGFX_CLKP
NBGFX_CLKN
SBLINK_CLKP
SBLINK_CLKN
EDIDDATA
EDIDCLK
HDTV_DET
RS740_DFT_GPIO1
DYN_1.1_NB
RS780_AUX_CAL
S-CD120
S-YD120
S-CVBS120
CRT_R20
CRT_G20
CRT_B20
DDCDATA20
DDCCLK20
PLTRST#14
EDIDDATA19
EDIDCLK19
U26C
F12
AVDD1(NC)
E12
AVDD2(NC)
F14
AVDDDI(NC)
G15
AVSSDI(NC)
H15
AVDDQ(NC)
H14
AVSSQ(NC)
E17
C_Pr(DFT_GPIO5)
F17
Y(DFT_GPIO2)
F15
COMP_Pb(DFT_GPIO4)
G18
RED(DFT_GPIO0)
G17
REDb(NC)
E18
GREEN(DFT_GPIO1)
F18
GREENb(NC)
E19
BLUE(DFT_GPIO3)
F19
BLUEb(NC)
A11
DAC_HSYNC(PWM_GPIO4)
B11
DAC_VSYNC(PWM_GPIO6)
E8
DAC_SDA(PCE_TCALRN)
F8
DAC_SCL(PCE_RCALRN)
G14
DAC_RSET(PWM_GPIO1)
A12
PLLVDD(NC)
D14
PLLVDD18(NC)
B12
PLLVSS(NC)
H17
VDDA18HTPLL
D7
VDDA18PCIEPLL1
E7
VDDA18PCIEPLL2
D8
SYSRESETb
A10
POWERGOOD
C10
LDTSTOPb
C12
ALLOW_LDTSTOP
C25
HT_REFCLKP
C24
HT_REFCLKN
E11
REFCLK_P/OSCIN(OSCIN)
F11
REFCLK_N(PWM_GPIO3)
T2
GFX_REFCLKP
T1
GFX_REFCLKN
U1
GPP_REFCLKP
U2
GPP_REFCLKN
V4
GPPSB_REFCLKP(SB_REFCLKP)
V3
GPPSB_REFCLKN(SB_REFCLKN)
A9
I2C_DATA
B9
I2C_CLK
B8
DDC_DATA/AUX0N(NC)
A8
DDC_CLK/AUX0P(NC)
B7
AUX1P(NC)
A7
AUX1N(NC)
B10
STRP_DATA
G11
RSVD
C8
AUX_CAL(NC)
RS780M
I
I/O
I/O
2
PART 3 OF 6
TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U3P(PCIE_RESET_GPIO5)
CRT/TVOUT
TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)
LVTM
PM
I
LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PWM_GPIO2)
CLOCKs PLL PWR
MIS.
TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)
TXOUT_L2N(DBG_GPIO0)
TXOUT_L3P(NC)
TXOUT_L3N(DBG_GPIO2)
TXOUT_U0P(NC)
TXOUT_U0N(NC)
TXOUT_U2P(NC)
TXOUT_U2N(NC)
TXOUT_U3N(NC)
TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)
VDDLTP18(NC)
VSSLTP18(NC)
VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)
VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)
TMDS_HPD(NC)
HPD(NC)
TVCLKIN(PWM_GPIO5)
THERMALDIODE_P
THERMALDIODE_N
TESTMODE
A22
B22
A21
B21
B20
A20
A19
B19
B18
A18
A17
B17
D20
D21
D18
D19
B16
A16
D16
D17
A13
B13
A15
B15
A14
B14
C14
D15
C16
C18
C20
E20
C22
E9
F7
G12
D9
D10
D12
AE8
AD8
TEST_EN
D13
LA_DATAP0
LA_DATAN0
LA_DATAP1
LA_DATAN1
LA_DATAP2
LA_DATAN2
LA_CLK
LA_CLK#
+1.8V_VDDLTP18_NB
+1.8V_VDDLT_18_NB
DISP_ON
LVDS_BLON
DPST_PWM
TMDS_HPD0
TMDS_HPD1
SUS_STAT_1#
T40
T39
R348
1.82K/F_4
T9
T15
R99 0_4
LA_DATAP0 19
LA_DATAN0 19
LA_DATAP1 19
LA_DATAN1 19
LA_DATAP2 19
LA_DATAN2 19
LA_CLK 19
LA_CLK# 19
DISP_ON 19
LVDS_BLON 19
DPST_PWM 19
SUS_STAT# 15
1
12
0.135A for AVDD
L42
+3V
+1.8V
3
Q29
BSS138_NL/SOT23
+3V
NB_ALLOW_LDTSTOP
3
Q30
BSS138_NL/SOT23
R338
4.7K_4
NB_LDT_STOP#
R334
4.7K_4
NBHT_REFCLKP
NBHT_REFCLKN
SBLINK_CLKP
SBLINK_CLKN
NBGFX_CLKP
NBGFX_CLKN
2
R66 0_4
5
1
R511 *0_4
1
R512 *0_4
NBHT_REFCLKP4
NBHT_REFCLKN4
SBLINK_CLKP4
SBLINK_CLKN4
NBGFX_CLKP4
NBGFX_CLKN4
+1.8V
2
CPU_LDT_STOP#5,14
B B
PV modified for
AMD sighting
update
CPU_LDT_REQ#5
ALLOW_LDTSTOP14
A A
+3V
+1.8V
BLM18PG221SN1D
R333 0_6
L45
BLM18PG221SN1D
+3V_AVDD_NB
C480
2.2U/6.3VC_6
+1.8V_AVDDDI_NB
C478
0.1U/16VB_6
+1.8V_AVDDQ_NB +1.8V_VDDLT_18_NB
C485
2.2U/6.3VC_6
PV modified for
AMD sighting
update
4
+1.1V
+1.8V
+1.8V
0.15A for PLLs 1.1V
L41
BLM18PG221SN1D
L13
BLM18PG221SN1D
L44
BLM18PG221SN1D
L10
BLM18PG221SN1D
C93
10U/6.3VC_8
+1.1V_PLLVDD
C479
2.2U/6.3VC_6
20mils width
+1.8V_VDDA18PCIEPLL
C127
2.2U/6.3VC_6
20mils width
+1.8V_VDDA18HTPLL
C154
2.2U/6.3VC_6
+1.8V_PLLVDD18
C136
2.2U/6.3VC_6
0.08A for VDDLT180.1A for PLLs 1.8V
+1.8V
L43
BLM18PG221SN1D
L9
BLM21PG221SN1D
3
+1.8V_VDDLTP18_NB
C483
2.2U/6.3VC_6
C99
4.7U/6.3VC_6
C103
0.1U/10VC_4
+1.1V 10,11,13,37
+1.8V 5,10,13,14,15,18,36,38
+3V 4,5,7,8,9,13,14,15,16,17,18,19,20,22,23,26,28,29,30,31,33,34,38
+12VALW 19,28,31,33,38
PROJECT : TT9
Quanta Computer Inc.
Size Document Number Rev
C
2
NB5/RD2/HW1
RS780M-SYSTEM I/F 3/4
Date: Sheet
1
12 41Wednesday, January 23, 2008
1A
of
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