Quanta TE1, Satellite M300, Satellite M305 Schematic
1
2
3
4
5
6
7
8
PCB STACK UP
HDMI
CRT
Page 20
LCD PANEL
Page 19
Transmitter
Sil1392
Page 21
LED
Driver IC
Page 19
LAYER 1 : TOP
LAYER 2 : SGND
LAYER 3 : IN1
LAYER 4 : VCC
A A
LAYER 5 : IN2
LAYER 6 : IN3
LAYER 7 : SGND2
LAYER 8 : BOT
VCC_CORE
HDMI
Page 21
LED PANEL
Page 19
Azalia
+1.5V
SATA - HDD
DAUGHTER
BOARD
DAUGHTER
BOARD
DAUGHTER
BOARD
Page 22
IDE - ODD
Page 22
LAN/B USB
Page 26
Camera
Page 19
WLAN
Page 25
Finger Printer
Page 26
Bluetooth
Page 26
New Card
Page 27
M/B USB 2
Page 27
Felica
Page 26
(FTB)
(FTB)
(FTB)
+1.05V
B B
+1.25V
+1.8VSUS
+1.8V
+3VPCU
+3V_S5
+3VSUS
+3V
+5VPCU
+5V_S5
+5V
+SMDDR_VTERM
+SMDDR_VREF
C C
M/B USB
Page 27
TV/ROBSON
Page 25
2
Port-A
Port-B
AUDIO CODEC
(CX20561)
Page 29
FM TUNER
& MDC
Page 30
MDC Board RJ11
Port-C
HP
Page 30
MIC JACK
Page 30
D D
INT SPK
Page 29
Reserve MIC
Page 19
Reserve MIC
Page 29
1
SPK AMP
Page 29
SATA
PATA
USB-0
USB-3
USB-5
USB-1
USB-2
USB-9
USB-7
USB-4
USB-6
USB-8
Reserve FM
Page 29
3
TE1 Block Diagram
Intel
Merom
(35W)
Page 3,4
FSB(667/800MHZ)
SDVO
CRT
LVDS
USB 2.0
Azalia
Page 28
Page 30
Crestline GM
Page 5,7,8,9,10,11
ICH8M
Page 14,15,16,17
WPCE775C
Kill SW
FANVR
Page 27Page 3
4
DMI(x2/x4)
LPC
Key FLASH
Board
Page 26 Page 28 Page 28
PCI-E 16X Lan
533/ 667 MHZ DDR II
32.768KHz
ROM
CLOCK GENERATOR
CK505
ICS9LPR363
Page 2
Azalia
VGA CONNECTOR
(FOX)
Page 18
DDRII-SODIMM1
DDRII-SODIMM2
Page 12,13
MINI CARD-3
U 9H_HD-DVD
Page 25
PCI-Express
PCIE-6 PCIE-5
MINI CARD-1
U&D 5.6H_WLAN
Page 25
PCI Bus
PCIE-2
MINI CARD-2
U 6.75H_TV/ROBSON
D 7.5H_HD-DVD
Page 25
PCMCIA
Controller
(CB 1410)
Page 23 Page 24
PCMCIA
CIR
PCI ROUTING
TABLE
REQ0# / GNT0# OZ129T
REQ1# / GNT1# CB1410AD18 INTC#
G-Sensor
Page 22
5
IDSEL
AD17
6
INTERUPT
INTA#
MINI CARD-4
D ROBSON
Page 25
Card
Reader/1394
(OZ129T)
5 IN 1 1394
LCD/LED
(FTB)
PCIE-4
PCIE-1PCIE-3
NEW CARD
Page 27
DEVICE
BTO BOM OPTION
IV@ : UMA
EV@ : VGA/B
CB@ : CARD BUS
GS@ : G-SENSOR
NEW@ : NEW CARD
LCD@ : LCD TYPE PANEL
LED@ : LED TYPE PANEL
CIR@ : CIR
CRT
HDMI
Connector
Page 26
LAN/RJ11/RJ45/USB/RF DAUGHTER BOARD
Marvell LAN
10/100/Giga
88E8040T/88E8072
Transformer
RJ45 RJ11 USB
LED Board
Low Cost Board
Page 26
MMB Board
Page 26
Power Board
Page 26
Touch Pad
Board
Page 26
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Block Diagram
Block Diagram
Block Diagram
Date: Sheet
Date: Sheet
Date: Sheet
7
PROJECT :
DAUGHTER
BOARD
TE1
TE1
TE1
8
RF
1A
1A
141Saturday, January 19, 2008
141Saturday, January 19, 2008
141Saturday, January 19, 2008
1A
of
of
of
5
4
3
2
1
Clock Generator
+1.25V_VDD
L44 PBY160808T-301Y-N_6L44 PBY160808T-301Y-N_6
+3V
C541
C541
*10u/10V_8
D D
*10u/10V_8
VDD :0.25A, 0.106A(Typ)
VDD_CK_VDD_PCI
C536 0.1u/10V_4C536 0.1u/10V_4
C533 0.1u/10V_4C533 0.1u/10V_4
C547 10u/10V_8C547 10u/10V_8
C211
C211
*10u/10V_8
*10u/10V_8
C212
C212
10u/10V_8
10u/10V_8
C519
C519
0.1u/10V_4
0.1u/10V_4
C213
C213
0.1u/10V_4
0.1u/10V_4
C214
C214
0.1u/10V_4
0.1u/10V_4
C509
C509
0.1u/10V_4
0.1u/10V_4
C218
C218
0.1u/10V_4
0.1u/10V_4
C215
C215
0.1u/10V_4
0.1u/10V_4
L21PBY160808T-301Y-N_6 L21PBY160808T-301Y-N_6
+1.25V
B2A
C231 30p/50V_4C231 30p/50V_4
CL=20p
C234 30p/50V_4C234 30p/50V_4
To Debug Card
To PCMCIA
To OZ129
C C
To EC
To SB
To SB
To SB
+3V +3V
ICS9LPRS365
(ALPRS365K13)
Pin 4
PCI2/TME
Pin 5
Pin 6
Pin 7
PCI-3
PCI-4/27M_SEL
PCIF-5/ITP_EN
B B
RTM875T-606
(AL000875K06)
PCI2/TME
internal PD
PCI-3/SRC5_EN
internal PD
PCI-4/27M_SEL
internal PD
PCIF-5/ITP_EN
internal PD
CG_XIN
21
Y3
Y3
14.318MHZ
14.318MHZ
CG_XOUT
Realtek FAE PCI3: Int PD driven issue. Add Ext PD for Realtek
PCLK_DEBUG(25)
B2A
PCLK_PCM(23)
PCLK_OZ129(24)
PCLK_591(28)
PCLK_ICH(15)
CLKUSB_48(16)
R217 10K_4R217 10K_4
NO OVERCLOCKING NORMAL RUN
PIN37/38 IS SRC5
PIN 17/18 IS 27MHz
PIN 46/47 IS CPUITP PIN 46/47 IS SRC8
+3V
CLK_BSEL0
CLK_BSEL1
CLK_BSEL2 FSC
14M_ICH(16)
PULL HIGH PULL DOWN
14M_ICH
PCLK_591
(default)
C529 0.1u/10V_4C529 0.1u/10V_4
C508 0.1u/10V_4C508 0.1u/10V_4
C475 0.1u/10V_4C475 0.1u/10V_4
C534 0.1u/10V_4C534 0.1u/10V_4
PCLK_DEBUG
PCLK_PCM
PCLK_OZ129
R208 *10K_4R208 *10K_4
PCLK_ICH
R207 10K_4R207 10K_4
CLKUSB_48
R210 2.2K_4R210 2.2K_4
R219 10K_4R219 10K_4
R213 33_4R213 33_4
PIN37/38 IS
PCI_STOP/CPU_STOP
PIN 17/18
IS SRC/DOT
R228 33_4R228 33_4
R226 *CB@33_4R226 *CB@33_4
R223 33_4R223 33_4
R220 10K_4R220 10K_4
R214 47_4R214 47_4
B2A
R211 47_4R211 47_4
R205 33_4R205 33_4
R227 10K_4R227 10K_4
R222 *10K_4R222 *10K_4
(default)
(default)
(default)
VDDIO : 0.08A, 0.032A(Typ)
+1.25V_VDD
PCLK_DEBUG_R
PCLK_PCM_R
PCLK_OZ129_R
PCI_CLK_SIO_R
PCLK_591_RPCLK_591
PCLK_ICH_R
CG_XIN
CG_XOUT
FSA
PCLK_OZ129
PCLK_PCM
PCLK_591
CLKUSB_48
14M_ICH
PCLK_ICH
PCLK_DEBUG
U13
U13
2
VDD_PCI
9
VDD_48
16
VDD_PLL3
61
VDD_REF
CK505
39
55
12
20
26
45
36
49
1
3
4
5
6
7
60
59
10
57
62
8
11
15
19
52
23
29
42
58
ICS9LPRS365BGLFT
ICS9LPRS365BGLFT
CK505
VDD_SRC
VDD_CPU
VDD_96_IO
VDD_PLL3_IO
VDD_SRC_IO_1
VDD_SRC_IO_3
VDD_SRC_IO_2
VDD_CPU_IO
PCI0/CR#_A
PCI1/CR#_B
PCI2/TME
PCI3
PCI4/SRC5_EN
PCIF5/ITP_EN
XTAL_IN
XTAL_OUT
USB_48/FSA
FSB/TEST/MODE
REF0/FSC/TESTSEL
VSS_PCI
VSS_48
VSS_IO
VSS_PLL3
VSS_CPU
VSS_SRC1
VSS_SRC2
VSS_SRC3
VSS_REF
D3A
Change C221 to 15p/50V_4
C230 *33p/50V_4C230 *33p/50V_4
C225 *33p/50V_4C225 *33p/50V_4
C221 15p/50V_4C221 15p/50V_4
C223 *33p/50V_4C223 *33p/50V_4
C222 *33p/50V_4C222 *33p/50V_4
C229 *33p/50V_4C229 *33p/50V_4
IO_VOUT
SCLK
SDA
SRC5/PCI_STOP#
SRC5#/CPU_STOP#
CPU0
CPU0#
CPU1
CPU1#
SRC8/ITP
SRC8#/ITP#
SRC10#
SRC10
SRC11/CR#_H
SRC11#/CR#_G
SRC9
SRC9#
SRC7/CR#_F
SRC7#/CR#_E
SRC6
SRC6#
SRC4
SRC4#
SRC3/CR#_C
SRC3#/CR#_D
SRC2/SATA
SRC2#/SATA#
SRC1/SE1
SRC1#/SE2
SRC0/DOT96
SRC0#/DOT96#
CKPWRGD/PWRDWN#
48
CGCLK_SMB
64
CGDAT_SMB
63
38
37
CLK_CPU_BCLK_R
54
CLK_CPU_BCLK#_R
53
CLK_MCH_BCLK_R
51
CLK_MCH_BCLK#_R
50
CLK_PCIE_MINI3&4_R
47
CLK_PCIE_MINI3&4#_R
46
CLK_PCIE_3GPLL#_R
35
CLK_PCIE_3GPLL_R
34
CLK_MCH_OE#_R
33
NEW_CLKREQ#_R
32
CLK_PCIE_NEW_R
30
CLK_PCIE_NEW_R#
31
CLK_PCIE_MINI2_R
44
CLK_PCIE_MINI2#_R
43
CLK_PCIE_MINI_R
41
CLK_PCIE_MINI#_R
40
CLK_PCIE_LAN_R
27
CLK_PCIE_LAN#_R
28
CLK_PCIE_ICH_R
24
CLK_PCIE_ICH#_R
25
CLK_PCIE_SATA_R
21
CLK_PCIE_SATA#_R
22
DREFSSCLK_R
17
DREFSSCLK#_R
18
DREFCLK_R
13
DREFCLK#_R
14
56
CLK_PCIE_MINI3&4_R
CLK_PCIE_MINI3&4#_R
DREFSSCLK_R
DREFSSCLK#_R
RP54 0X2RP54 0X2
RP52 0X2RP52 0X2
RP44 0X2RP44 0X2
R195 475/F_4R195 475/F_4
R196 475/F_4R196 475/F_4
RP45 NEW@0X2RP45 NEW@0X2
RP49 0X2RP49 0X2
RP47 0X2RP47 0X2
RP46 0X2RP46 0X2
RP48 0X2RP48 0X2
RP50 0X2RP50 0X2
RP55 *IV@0X2RP55 *IV@0X2R218 *10K_4R218 *10K_4
RP51 *IV@0X2RP51 *IV@0X2
RP72 EV@0X2RP72 EV@0X2
RP70 *IV@0X2RP70 *IV@0X2
RP53 EV@0X2RP53 EV@0X2
2
1
4
3
2
1
4
3
2
1
4
3
4
3
2
1
2
1
4
3
2
1
4
3
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
2
1
4
3
4
3
2
1
2
1
4
3
4
3
2
1
PM_STPPCI# (16)
PM_STPCPU# (16)
CLK_CPU_BCLK (3)
CLK_CPU_BCLK# (3)
CLK_MCH_BCLK (5)
CLK_MCH_BCLK# (5)
CLK_PCIE_3GPLL# (6)
CLK_PCIE_3GPLL (6)
CLK_MCH_OE# (6)
NEW_CLKREQ# (27)
CLK_PCIE_NEW (27)
CLK_PCIE_NEW# (27)
CLK_PCIE_MINI2 (25)
CLK_PCIE_MINI2# (25)
CLK_PCIE_MINI (25)
CLK_PCIE_MINI# (25)
CLK_PCIE_LAN (26)
CLK_PCIE_LAN# (26)
CLK_PCIE_ICH (15)
CLK_PCIE_ICH# (15)
CLK_PCIE_SATA (14)
CLK_PCIE_SATA# (14)
DREFCLK (6)
DREFCLK# (6)
CK_PWRGD (16)
CLK_PCIE_MINI3 (25)
CLK_PCIE_MINI3# (25)
CLK_PCIE_MINI4 (25)
CLK_PCIE_MINI4# (25)
DREFSSCLK (6)
DREFSSCLK# (6)
CLK_MXM (18)
CLK_MXM# (18)
To CPU
To NB
To NB
To New Card
To MINI2
To MINI1
To LAN
To SB
To SB
To NB
To MINI3
To MINI4
To NB
To VGA Card
B2A
Clock Gen I2CBSEL Frequency Select Table
FSC FSB FSA Frequency
0
0
0
0
0
0
A A
1
1
1
1
1
1
0
1
011
1
1
1
0
0
0
266Mhz0
133Mhz
166Mhz
200Mhz
400Mhz
Reserved
100Mhz
333Mhz
5
CPU_BSEL0(3)
+1.05V
CPU_BSEL1(3)
+1.05V
CPU_BSEL2(3) MCH_BSEL2 (6)
+1.05V
R464 0_4R464 0_4
R463 *56_4R463 *56_4
R465 *1K_4R465 *1K_4
R206 0_4R206 0_4
R204 *0_4R204 *0_4
R203 *1K_4R203 *1K_4
R460 0_4R460 0_4
R209 *0_4R209 *0_4
R454 *1K_4R454 *1K_4
4
CLK_BSEL0
CLK_BSEL1
CLK_BSEL2
MCH_BSEL0 (6)
MCH_BSEL1 (6)
3
+3V
SDATA(16,21,25,27)
SCLK(16,21,25,27)
R197 10K_4R197 10K_4
2
+3V
2
3
+3V
2
3
NEW_CLKREQ#_R
Q35
Q35
RHU002N06
RHU002N06
1
Q37
Q37
RHU002N06
RHU002N06
1
R221
R221
10K_4
10K_4
CGDAT_SMB
R225
R225
10K_4
10K_4
CGCLK_SMB
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
CLK. GEN./ CK505
CLK. GEN./ CK505
CLK. GEN./ CK505
Date: Sheet
Date: Sheet
Date: Sheet
CGDAT_SMB (13)
CGCLK_SMB (13)
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
TE1
TE1
TE1
241Wednesday, January 23, 2008
241Wednesday, January 23, 2008
241Wednesday, January 23, 2008
1
1A
1A
1A
of
of
of
5
CPU(HOST)
D D
C C
B B
+1.05V
R68
R68
1K/F_4
1K/F_4
A A
<Check list & CRB>
Layout note: Z=55 ohm
H_GTLREF<0.5"
R64
R64
2K/F_4
2K/F_4
H_A#[16:3](5)
H_ADSTB0#(5)
H_REQ#[4:0](5)
H_A#[35:17](5)
H_ADSTB1#(5)
H_A20M#(14)
H_FERR#(14)
H_IGNNE#(14)
H_STPCLK#(14)
H_INTR(14)
H_NMI(14)
H_SMI#(14)
H_D#[15:0](5)
H_DSTBN#0(5)
H_DSTBP#0(5)
H_DINV#0(5)
H_D#[31:16](5)
H_DSTBN#1(5)
H_DSTBP#1(5)
H_DINV#1(5)
R48 *1K_4R48 *1K_4 R31 *0_4R31 *0_4
R59 *1K_4R59 *1K_4
T9T9
T11T11
T3T3
T10T10
CPU_BSEL0(2)
CPU_BSEL1(2)
CPU_BSEL2(2)
5
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_GTLREF
CPU_TEST1
CPU_TEST2
CPU_TEST3
CPU_TEST4
CPU_TEST5
CPU_TEST6
U26A
U26A
J4
A[3]#
L5
A[4]#
L4
A[5]#
K5
A[6]#
M3
A[7]#
N2
A[8]#
J1
A[9]#
N3
A[10]#
P5
A[11]#
P2
A[12]#
L2
A[13]#
P4
A[14]#
P1
A[15]#
R1
A[16]#
M1
ADSTB[0]#
K3
REQ[0]#
H2
REQ[1]#
K2
REQ[2]#
J3
REQ[3]#
L1
REQ[4]#
Y2
A[17]#
U5
A[18]#
R3
A[19]#
W6
A[20]#
U4
A[21]#
Y5
A[22]#
U1
A[23]#
R4
A[24]#
T5
A[25]#
T3
A[26]#
W2
A[27]#
W5
A[28]#
Y4
A[29]#
U2
A[30]#
V4
A[31]#
W3
A[32]#
AA4
A[33]#
AB2
A[34]#
AA3
A[35]#
V1
ADSTB[1]#
A6
A20M#
A5
FERR#
C4
IGNNE#
D5
STPCLK#
C6
LINT0
B4
LINT1
A3
SMI#
M4
RSVD[01]
N5
RSVD[02]
T2
RSVD[03]
V3
RSVD[04]
B2
RSVD[05]
C3
RSVD[06]
D2
RSVD[07]
D22
RSVD[08]
D3
RSVD[09]
F6
RSVD[10]
Merom Ball-out Rev 1a
Merom Ball-out Rev 1a
U26B
U26B
E22
D[0]#
F24
D[1]#
E26
D[2]#
G22
D[3]#
F23
D[4]#
G25
D[5]#
E25
D[6]#
E23
D[7]#
K24
D[8]#
G24
D[9]#
J24
D[10]#
J23
D[11]#
H22
D[12]#
F26
D[13]#
K22
D[14]#
H23
D[15]#
J26
DSTBN[0]#
H26
DSTBP[0]#
H25
DINV[0]#
N22
D[16]#
K25
D[17]#
P26
D[18]#
R23
D[19]#
L23
D[20]#
M24
D[21]#
L22
D[22]#
M23
D[23]#
P25
D[24]#
P23
D[25]#
P22
D[26]#
T24
D[27]#
R24
D[28]#
L25
D[29]#
T25
D[30]#
N25
D[31]#
L26
DSTBN[1]#
M26
DSTBP[1]#
N24
DINV[1]#
AD26
GTLREF
C23
TEST1
D25
TEST2
C24
TEST3
AF26
TEST4
AF1
TEST5
A26
TEST6
B22
BSEL[0]
B23
BSEL[1]
C21
BSEL[2]
Merom Ball-out Rev 1a
Merom Ball-out Rev 1a
ADDR GROUP 0 ADDR GROUP 1
ADDR GROUP 0 ADDR GROUP 1
ICH
ICH
DATA GRP 1
DATA GRP 1
MISC
MISC
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
CONTROL
CONTROL
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
HIT#
HITM#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDO
TMS
TRST#
XDP/ITP SIGNALS
XDP/ITP SIGNALS
DBR#
THERMAL
THERMAL
PROCHOT#
THERMDA
THERMDC
THERMTRIP#
H CLK
H CLK
BCLK[0]
BCLK[1]
RESERVED
RESERVED
DATA GRP 0
DATA GRP 0
DATA GRP 2DATA GRP 3
DATA GRP 2DATA GRP 3
DSTBN[2]#
DSTBP[2]#
DSTBN[3]#
DSTBP[3]#
DPRSTP#
PWRGOOD
TDI
DINV[2]#
DINV[3]#
COMP[0]
COMP[1]
COMP[2]
COMP[3]
DPSLP#
DPWR#
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
SLP#
PSI#
H1
E2
G5
H5
F21
E1
F1
D20
B3
H4
C1
F3
F4
G3
G2
G6
E4
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
D21
A24
B25
C7
A22
A21
4
H_IERR#
CPURESET#
XDP_TCK
XDP_TDI
XDP_TMS
XDP_TRST#
XDP_DBRESET#
H_PROCHOT_R#
H_THERMDA
H_THERMDC
THERMTRIP#_PWR
H_D#32
Y22
H_D#33
AB24
H_D#34
V24
H_D#35
V26
H_D#36
V23
H_D#37
T22
H_D#38
U25
H_D#39
U23
H_D#40
Y25
H_D#41
W22
H_D#42
Y23
H_D#43
W24
H_D#44
W25
H_D#45
AA23
H_D#46
AA24
H_D#47
AB25
Y26
AA26
U22
H_D#48
AE24
H_D#49
AD24
H_D#50
AA21
H_D#51
AB22
H_D#52
AB21
H_D#53
AC26
H_D#54
AD20
H_D#55
AE22
H_D#56
AF23
H_D#57
AC25
H_D#58
AE21
H_D#59
AD21
H_D#60
AC22
H_D#61
AD23
H_D#62
AF22
H_D#63
AC23
AE25
AF24
AC20
COMP0
R26
COMP1
U26
COMP2
AA1
COMP3
Y1
E5
B5
D24
D6
D7
AE6
4
R35 56.2/F_4R35 56.2/F_4
L54 BK1608LM252-T_6L54 BK1608LM252-T_6
T7T7
T6T6
T4T4
T8T8
T2T2
T1T1
T5T5
<check list>
Default PU 56ohm if no use.
Serial R NC, If connect to power side PU 68ohm. Serial R 2.2K
CLK_CPU_BCLK (2)
CLK_CPU_BCLK# (2)
R67 27.4/F_6R67 27.4/F_6
R63 54.9/F_4R63 54.9/F_4
R20 27.4/F_6R20 27.4/F_6
R19 54.9/F_4R19 54.9/F_4
+1.05V
R33 0_4R33 0_4
R43 56.2/F_4R43 56.2/F_4
R45 *2.2K_4R45 *2.2K_4
H_D#[47:32] (5)
H_DSTBN#2 (5)
H_DSTBP#2 (5)
H_DINV#2 (5)
H_D#[63:48] (5)
H_DSTBN#3 (5)
H_DSTBP#3 (5)
H_DINV#3 (5)
ICH_DPRSTP# (6,14,33)
H_DPSLP# (14)
H_DPWR# (5)
H_PWRGD (14)
H_CPUSLP# (5)
PSI# (33)
H_ADS# (5)
H_BNR# (5)
H_BPRI# (5)
H_DEFER# (5)
H_DRDY# (5)
H_DBSY# (5)
H_BREQ#0 (5)
H_INIT# (14)
H_LOCK# (5)
H_RS#0 (5)
H_RS#1 (5)
H_RS#2 (5)
H_TRDY# (5)
H_HIT# (5)
H_HITM# (5)
SYS_RST# (16)
+1.05V
H_PROCHOT# (33)
<Check list & CRB>
Layout note: L<0.5"
COMP0/2 Z=27.4ohm
COMP1/3 Z=54.9
3
D3A
H_CPURST# (5)
3
2
CPU Thermal monitor
+3V
Q10
Q10
2
RHU002N06
2ND_MBCLK(22,28)
2ND_MBDATA(22,28)
3
3
B2A
+3V
THERM_ALERT#(16)
+3V
RHU002N06
1
+3V
Q11
Q11
2
RHU002N06
RHU002N06
1
R81 10K_4R81 10K_4
R80 *0_4R80 *0_4
R39 10K_4R39 10K_4
CPU FAN
+5V
C68 2.2u/6.3V_6C68 2.2u/6.3V_6
SYSFANON#(18)
VFAN(28)
R84 0_4R84 0_4
PU/PD (ITP700) Thermal Trip
+1.05V
R17 39/F_4R17 39/F_4
XDP_TMS
R21 150_4R21 150_4
XDP_TDI
R22 27_4R22 27_4
XDP_TCK
XDP_TRST# THERMTRIP#_PWR
R18 680/F_4R18 680/F_4
DELAY_VR_PWRGOOD(6,16,33)
2
THERM_ALERT#_R
THER_SHD#
U27
U27
VIN2VO
GND
1
/FON
GND
GND
4
VSET
GND
G995
G995
FANPWR = 1.6*VSET
1
+3V
R83
R83
R42
10K_4
10K_4
U28
U28
8
SCLK
7
SDA
6
ALERT#
4
OVERT#
LM95245
LM95245
ADDRESS: 98H
B2A
FANSIG(28)
TH_FAN_POWER
C70
C70
0.01u/16V_4
0.01u/16V_4
R42
200_6
200_6
+3V
2
1 3
VCC
DXP
DXN
GND
LM86VCC
1
2
3
5
R92
R92
330_4
330_4
Q9
MMBT3904Q9MMBT3904
C71
C71
*0.01u/16V_4
*0.01u/16V_4
C52
C52
0.1u/10V_4
0.1u/10V_4
C402
C402
2200p/50V_4
2200p/50V_4
SYS_SHDN# (32)
+3V
R86
R86
10K_4
10K_4
R79
R79
10K_4
10K_4
3
5
6
C65
C65
7
8
10u/10V_8
10u/10V_8
D3A
+1.05V
3
R34
R34
*10K_4
*10K_4
SYS_SHDN# (32)
PM_THRMTRIP# (6,14)
1
D3
*BAS316D3*BAS316
R116 100K_4R116 100K_4
TE1
TE1
TE1
341Wednesday, January 23, 2008
341Wednesday, January 23, 2008
341Wednesday, January 23, 2008
Q5
2
FDV301NQ5FDV301N
+1.05V
R30
R30
56.2/F_4
56.2/F_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
1
R115
R115
B2A
1K_4
1K_4
Q6
2
B2A
MMBT3904Q6MMBT3904
1 3
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
CPU(1 of 2)/FAN/Thermal
CPU(1 of 2)/FAN/Thermal
CPU(1 of 2)/FAN/Thermal
H_THERMDA
H_THERMDC
CN22
CN22
1
2
3
FAN_CON
FAN_CON
of
of
of
1A
1A
1A
5
4
3
2
1
CPU(Power)
VCC_CORE
U26D
<REV.NO. 0.5/REF.NO.19343>
Ivcc Max 52A
U26C
C390
C394
C376
C376
C33
10u/6.3V_8
10u/6.3V_8
C389
C389
10u/6.3V_8
10u/6.3V_8
C29
*10u/6.3V_8
*10u/6.3V_8
C375
C375
*10u/6.3V_8
*10u/6.3V_8
C2A
C33
10u/6.3V_8
10u/6.3V_8
C391
C391
10u/6.3V_8
10u/6.3V_8
C32
C32
*10u/6.3V_8
*10u/6.3V_8
C37
C37
*10u/6.3V_8
*10u/6.3V_8
+
+
PC147
PC147
330u/2.5V_7343
330u/2.5V_7343
D D
C C
+
+
PC146
PC146
330u/2.5V_7343
330u/2.5V_7343
B B
A A
C392
C392
10u/6.3V_8
10u/6.3V_8
C393
C393
*10u/6.3V_8
*10u/6.3V_8
C383
C383
*10u/6.3V_8
*10u/6.3V_8
C387
C387
*10u/6.3V_8
*10u/6.3V_8
C394
10u/6.3V_8
10u/6.3V_8
C373
C373
*10u/6.3V_8
*10u/6.3V_8
C386
C386
*10u/6.3V_8
*10u/6.3V_8
C38
C38
*10u/6.3V_8
*10u/6.3V_8
C382
C382
10u/6.3V_8
10u/6.3V_8
C385
C385
*10u/6.3V_8
*10u/6.3V_8
C30
C30
*10u/6.3V_8
*10u/6.3V_8
C43
C43
*10u/6.3V_8
*10u/6.3V_8
C390
10u/6.3V_8
10u/6.3V_8
C45
C45
*10u/6.3V_8
*10u/6.3V_8
C384
C384
*10u/6.3V_8
*10u/6.3V_8
C395
C395
*10u/6.3V_8
*10u/6.3V_8
C372
C372
10u/6.3V_8
10u/6.3V_8
C39
C39
*10u/6.3V_8
*10u/6.3V_8
C374
C374
10u/6.3V_8
10u/6.3V_8
C44
C44
*10u/6.3V_8
*10u/6.3V_8
C34
C34
10u/6.3V_8
10u/6.3V_8
C378
C378
*10u/6.3V_8
*10u/6.3V_8
C381
C381
10u/6.3V_8
10u/6.3V_8
C371
C371
*10u/6.3V_8
*10u/6.3V_8
U26C
A7
VCC[001]
A9
VCC[002]
A10
VCC[003]
A12
VCC[004]
A13
VCC[005]
A15
VCC[006]
A17
VCC[007]
A18
VCC[008]
A20
VCC[009]
B7
VCC[010]
B9
VCC[011]
B10
VCC[012]
B12
VCC[013]
B14
VCC[014]
B15
VCC[015]
B17
VCC[016]
B18
VCC[017]
B20
VCC[018]
C9
VCC[019]
C10
VCC[020]
C12
VCC[021]
C13
VCC[022]
C15
VCC[023]
C17
VCC[024]
C18
VCC[025]
D9
VCC[026]
D10
VCC[027]
D12
VCC[028]
D14
VCC[029]
D15
VCC[030]
D17
VCC[031]
D18
VCC[032]
E7
VCC[033]
E9
VCC[034]
E10
VCC[035]
E12
VCC[036]
E13
VCC[037]
E15
VCC[038]
E17
VCC[039]
E18
VCC[040]
E20
VCC[041]
F7
VCC[042]
F9
VCC[043]
F10
VCC[044]
F12
VCC[045]
F14
VCC[046]
F15
VCC[047]
F17
VCC[048]
F18
VCC[049]
F20
VCC[050]
AA7
VCC[051]
AA9
VCC[052]
AA10
VCC[053]
AA12
VCC[054]
AA13
VCC[055]
AA15
VCC[056]
AA17
VCC[057]
AA18
VCC[058]
AA20
VCC[059]
AB9
VCC[060]
AC10
VCC[061]
AB10
VCC[062]
AB12
VCC[063]
AB14
VCC[064]
AB15
VCC[065]
AB17
VCC[066]
AB18
VCC[067]
Merom Ball-out Rev 1a
Merom Ball-out Rev 1a
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
VCCA[01]
VCCA[02]
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VCCSENSE
VSSSENSE
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
+VCCA_PROC
B26
C26
AD6
AF5
AE5
AF4
AE3
AF3
AE2
AF7
AE7
.
.
Ivccp Max 6A(VCCP supply before Vcc stable)
Max 2A(VCCP supply after Vcc stable)
Ivcca Max 130mA
+1.05V
C28
C28
0.1u/16V_6
0.1u/16V_6
+
+
C35
C35
330u/2V_7343
330u/2V_7343
H_VID0 (33)
H_VID1 (33)
H_VID2 (33)
H_VID3 (33)
H_VID4 (33)
H_VID5 (33)
H_VID6 (33)
VCC_CORE
C26
C26
0.1u/16V_6
0.1u/16V_6C29
<Check list>
ESR=12m ohm
<CRB>
.01U near to B26 ball
R391
R391
100/F_6
100/F_6
R390
R390
100/F_6
100/F_6
C47
C47
0.1u/16V_6
0.1u/16V_6
C25
C25
C48
C48
0.1u/16V_6
0.1u/16V_6
0.1u/16V_6
0.1u/16V_6
R73 0_6R73 0_6
C64
C64
C62
C62
10u/10V_8
10u/10V_8
0.01u/16V_4
0.01u/16V_4
VCCSENSE (33)
<CRB>
Routing 27.4ohm with 50mils spacing
PU/PD near to CPU 1"
VSSSENSE (33)
+1.5V
C46
C46
0.1u/16V_6
0.1u/16V_6
U26D
A4
VSS[001]
A8
VSS[002]
A11
VSS[003]
A14
VSS[004]
A16
VSS[005]
A19
VSS[006]
A23
VSS[007]
AF2
VSS[008]
B6
VSS[009]
B8
VSS[010]
B11
VSS[011]
B13
VSS[012]
B16
VSS[013]
B19
VSS[014]
B21
VSS[015]
B24
VSS[016]
C5
VSS[017]
C8
VSS[018]
C11
VSS[019]
C14
VSS[020]
C16
VSS[021]
C19
VSS[022]
C2
VSS[023]
C22
VSS[024]
C25
VSS[025]
D1
VSS[026]
D4
VSS[027]
D8
VSS[028]
D11
VSS[029]
D13
VSS[030]
D16
VSS[031]
D19
VSS[032]
D23
VSS[033]
D26
VSS[034]
E3
VSS[035]
E6
VSS[036]
E8
VSS[037]
E11
VSS[038]
E14
VSS[039]
E16
VSS[040]
E19
VSS[041]
E21
VSS[042]
E24
VSS[043]
F5
VSS[044]
F8
VSS[045]
F11
VSS[046]
F13
VSS[047]
F16
VSS[048]
F19
VSS[049]
F2
VSS[050]
F22
VSS[051]
F25
VSS[052]
G4
VSS[053]
G1
VSS[054]
G23
VSS[055]
G26
VSS[056]
H3
VSS[057]
H6
VSS[058]
H21
VSS[059]
H24
VSS[060]
J2
VSS[061]
J5
VSS[062]
J22
VSS[063]
J25
VSS[064]
K1
VSS[065]
K4
VSS[066]
K23
VSS[067]
K26
VSS[068]
L3
VSS[069]
L6
VSS[070]
L21
VSS[071]
L24
VSS[072]
M2
VSS[073]
M5
VSS[074]
M22
VSS[075]
M25
VSS[076]
N1
VSS[077]
N4
VSS[078]
N23
VSS[079]
N26
VSS[080]
VSS[081]P3VSS[162]
Merom Ball-out Rev 1a
Merom Ball-out Rev 1a
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[163]
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
.
.
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
CPU(2 of 2)
CPU(2 of 2)
CPU(2 of 2)
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
PROJECT :
TE1
TE1
TE1
441Wednesday, January 23, 2008
441Wednesday, January 23, 2008
441Wednesday, January 23, 2008
1
1A
1A
1A
of
of
of
5
4
3
2
1
NB(HOST)
H_D#[63:0](3)
+1.05V
R411
+1.05V
+1.05V
H_CPURST#(3)
C406
C406
0.1u/10V_4
0.1u/10V_4
R411
221/F_4
221/F_4
R410
R410
100/F_4
100/F_4
R409
R409
24.9/F_4
24.9/F_4
R97
R97
54.9/F_4
54.9/F_4
R98
R98
54.9/F_4
54.9/F_4
H_SWING
H_RCOMP
H_SCOMP
H_SCOMP#
C404
C404
0.1u/10V_4
0.1u/10V_4
10:20 mils(Width:Spacing)
Impedance 55ohm
Impedance 55ohm
0.1U close to B9,L<100mils
H_CPURST#
D3A
C666
C666
*0.1u/10V_4
*0.1u/10V_4
4
D D
C C
B B
+1.05V
R413
R413
1K/F_4
1K/F_4
A A
R412
R412
2K/F_4
2K/F_4
5
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_SWING
H_RCOMP
H_SCOMP
H_SCOMP#
H_CPURST#
H_AVREF
U29A
U29A
E2
H_D#_0
G2
H_D#_1
G7
H_D#_2
M6
H_D#_3
H7
H_D#_4
H3
H_D#_5
G4
H_D#_6
F3
H_D#_7
N8
H_D#_8
H2
H_D#_9
M10
H_D#_10
N12
H_D#_11
N9
H_D#_12
H5
H_D#_13
P13
H_D#_14
K9
H_D#_15
M2
H_D#_16
W10
H_D#_17
Y8
H_D#_18
V4
H_D#_19
M3
H_D#_20
J1
H_D#_21
N5
H_D#_22
N3
H_D#_23
W6
H_D#_24
W9
H_D#_25
N2
H_D#_26
Y7
H_D#_27
Y9
H_D#_28
P4
H_D#_29
W3
H_D#_30
N1
H_D#_31
AD12
H_D#_32
AE3
H_D#_33
AD9
AC9
AC7
AC14
AD11
AC11
AB2
AD7
AB1
AC6
AE2
AC5
AG3
AH8
AJ14
AE9
AE11
AH12
AH5
AE7
AE5
AH2
AH13
Y3
AJ9
AJ5
AJ6
AJ7
AJ2
AJ3
B3
C2
W1
W2
B6
E5
B9
A9
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
H_SWING
H_RCOMP
H_SCOMP
H_SCOMP#
H_CPURST#
H_CPUSLP#
H_AVREF
H_DVREF
CRESTLINE_1p0
CRESTLINE_1p0
HOST
HOST
H_ADSTB#_0
H_ADSTB#_1
HPLL_CLK#
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
965GM : AJSLA5T0T20
965PM : AJSLA5U0T25
960GML : AJSLA5V0T09
3
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
H_ADS#
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
H_RS#_0
H_RS#_1
H_RS#_2
J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19
G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7
K5
L2
AD13
AE13
M7
K3
AD2
AH11
L7
K2
AC2
AJ10
M14
E13
A11
H13
B12
E12
D7
D8
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
H_A#[35:3] (3)
H_ADS# (3)
H_ADSTB0# (3)
H_ADSTB1# (3)
H_BNR# (3)
H_BPRI# (3)
H_BREQ#0 (3)
H_DEFER# (3)
H_DBSY# (3)
CLK_MCH_BCLK (2)
CLK_MCH_BCLK# (2)
H_DPWR# (3)
H_DRDY# (3)
H_HIT# (3)
H_HITM# (3)
H_LOCK# (3)
H_TRDY# (3)
H_DINV#[3:0] (3)
H_DSTBN#[3:0] (3)
H_DSTBP#[3:0] (3)
H_REQ#[4:0] (3)
H_RS#[2:0] (3)H_CPUSLP#(3)
2
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
GMCH HOST(1 of 7)
GMCH HOST(1 of 7)
GMCH HOST(1 of 7)
Date: Sheet
Date: Sheet
Date: Sheet
PROJECT :
TE1
TE1
TE1
of
of
of
541Wednesday, January 23, 2008
541Wednesday, January 23, 2008
541Wednesday, January 23, 2008
1
1A
1A
1A
5
)
D D
M_A_A14(12,13)
M_B_A14(12,13)
C C
MCH_BSEL0(2)
MCH_BSEL1(2)
MCH_BSEL2(2)
MCH_CFG_5(11)
MCH_CFG_9(11)
MCH_CFG_12(11)
MCH_CFG_13(11)
MCH_CFG_16(11)
MCH_CFG_19(11)
MCH_CFG_20(11)
B B
A A
PM_BMBUSY#(16)
ICH_DPRSTP#(3,14,33)
PM_EXTTS#0(13)
PM_EXTTS#1(13)
DELAY_VR_PWRGOOD3,16,33
PLTRST#_NB(15)
PM_THRMTRIP#(3,14)
PM_DPRSLPVR(16,33)
R117 100_4R117 100_4
R113 *0_4R113 *0_4
M_RCOMP#
T19T19
T25T25
T17T17
T21T21
T16T16
T20T20
T23T23
T15T15
T22T22
T18T18
T26T26
5
MCH_CFG_3
MCH_CFG_4
MCH_CFG_6
MCH_CFG_7
MCH_CFG_8
MCH_CFG_10
MCH_CFG_11
MCH_CFG_14
MCH_CFG_15
MCH_CFG_17
MCH_CFG_18
PM_EXTTS#0
PM_EXTTS#1
RST_IN#_MCH
PM_THRMTRIP#_GMCH
R415
R415
20/F_4
20/F_4
M_RCOMP
+1.8VSUS
AW20
AW49
R417
R417
20/F_4
20/F_4
AR12
AR13
AM12
AN13
AR37
AM36
AL36
AM37
BJ20
BK22
BF19
BH20
BK18
BJ18
BF23
BG23
BC23
BD24
BJ29
BE24
BH39
BK20
AV20
BJ51
BK51
BK50
BL50
BL49
P36
P37
R35
N35
J12
D20
H10
B51
C48
D47
B44
C44
A35
B37
B36
B34
C34
P27
N27
N24
C21
C23
F23
N23
G23
J20
C20
R24
L23
J23
E23
E20
K23
M20
M24
L32
N33
L35
G41
L39
L36
J36
N20
G36
BL3
BL2
BK1
BJ1
C51
B50
A50
A49
BK2
U29B
U29B
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
PM_BM_BUSY#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
E1
NC_10
A5
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
CRESTLINE_1p0
CRESTLINE_1p0
+3V
4
SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3
SM_RCOMP
SM_RCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_VREF_0
DDR MUXINGCLK
DDR MUXINGCLK
SM_VREF_1
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
CFGRSVD
CFGRSVD
DMI_TXP_0
DMI_TXP_1
DMI
DMI
DMI_TXP_2
DMI_TXP_3
GFX_VID_0
GFX_VID_1
GFX_VID_2
PM
PM
GFX_VID_3
GFX_VR_EN
GRAPHICS VID
GRAPHICS VID
CL_PWROK
ME
ME
NC
NC
SDVO_CTRL_CLK
SDVO_CTRL_DATA
ICH_SYNC#
MISC
MISC
R163 10K_4R163 10K_4
R162 10K_4R162 10K_4
R146 10K_4R146 10K_4
4
SM_CK_0
SM_CK_1
SM_CK_3
SM_CK_4
SM_CK#_0
SM_CK#_1
SM_CK#_3
SM_CK#_4
SM_CKE_0
SM_CKE_1
SM_CKE_3
SM_CKE_4
SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3
PEG_CLK
PEG_CLK#
CL_CLK
CL_DATA
CL_RST#
CL_VREF
CLK_REQ#
TEST_1
TEST_2
CLK_MCH_OE#
PM_EXTTS#0
PM_EXTTS#1
AV29
BB23
BA25
AV23
AW30
BA23
AW25
AW23
BE29
AY32
BD39
BG37
BG20
BK16
BG16
BE13
BH18
BJ15
BJ14
BE16
BL15
BK14
BK31
BL31
AR49
AW4
B42
C42
H48
H47
K44
K45
AN47
AJ38
AN42
AN46
AM47
AJ39
AN41
AN45
DMI_RXN0
AJ46
DMI_RXN1
AJ41
DMI_RXN2
AM40
DMI_RXN3
AM44
DMI_RXP0
AJ47
DMI_RXP1
AJ42
DMI_RXP2
AM39
DMI_RXP3
AM43
E35
A39
C38
B39
E36
AM49
AK50
AT43
AN49
+1.25V_CL_VREF
AM50
H35
K36
CLK_MCH_OE#
G39
G40
GMCH_TEST1
A37
GMCH_TEST2
R32
+1.8VSUS
M_RCOMP
M_RCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
SMDDR_VREF_MCH
DREFCLK
DREFCLK#
DREFSSCLK
DREFSSCLK#
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
M_CLK_DDR0 (13)
M_CLK_DDR1 (13)
M_CLK_DDR3 (13)
M_CLK_DDR4 (13)
M_CLK_DDR#0 (13)
M_CLK_DDR#1 (13)
M_CLK_DDR#3 (13)
M_CLK_DDR#4 (13)
M_CKE0 (12,13)
M_CKE1 (12,13)
M_CKE3 (12,13)
M_CKE4 (12,13)
M_CS#0 (12,13)
M_CS#1 (12,13)
M_CS#2 (12,13)
M_CS#3 (12,13)
M_ODT0 (12,13)
M_ODT1 (12,13)
M_ODT2 (12,13)
M_ODT3 (12,13)
R96 *10K_6R96 *10K_6
R100 *10K_6R100 *10K_6
DREFCLK (2)
DREFCLK# (2)
DREFSSCLK (2)
DREFSSCLK# (2)
CLK_PCIE_3GPLL (2)
CLK_PCIE_3GPLL# (2)
DMI_TXN[3:0] (15)
DMI_TXP[3:0] (15)
DMI_RXN[3:0] (15)
DMI_RXP[3:0] (15)
INT_CRT_DDCCLK(20)
INT_CRT_DDCDAT(20)
CL_CLK0 (16)
CL_DATA0 (16)
MPWROK (16)
CL_RST#0 (16)
SDVO_CTRLCLK (21)
SDVO_CTRLDATA (21)
CLK_MCH_OE# (2)
MCH_ICH_SYNC# (16)
R166 0_4R166 0_4
R152 20K_4R152 20K_4
R422 1K/F_4R422 1K/F_4
INT_LVDS_PWM(19)
INT_LVDS_BLON(19)
R93 0_6R93 0_6
INT_HSYNC(20)
INT_VSYNC(20)
R423
R423
3.01K/F_4
3.01K/F_4
R421
R421
1K/F_4
1K/F_4
+3V
+3V
INT_LVDS_EDIDCLK(19)
INT_LVDS_EDIDDATA(19)
INT_LVDS_DIGON(19)
+SMDDR_VREF
+1.8VSUS
INT_CRT_BLU(20)
INT_CRT_GRN(20)
INT_CRT_RED(20)
R149 *IV@30/F_4R149 *IV@30/F_4
R154 *IV@30/F_4R154 *IV@30/F_4
+1.25V_AXD
C210
C210
0.1u/10V_4
0.1u/10V_4
SM_RCOMP_VOH
C431
C431
0.01u/16V_4
0.01u/16V_4
SM_RCOMP_VOL
C425
C425
0.01u/16V_4
0.01u/16V_4
3
R147 *IV@10K_4R147 *IV@10K_4
R170 EV@0_4R170 EV@0_4
R145 EV@0_4R145 EV@0_4
R161 *IV@10K_4R161 *IV@10K_4
R175 *IV@2.4K/F_4R175 *IV@2.4K/F_4
R177 *IV@0_4R177 *IV@0_4
INT_TXLCLKOUT-(19)
INT_TXLCLKOUT+(19)
INT_TXLOUT0-(19)
INT_TXLOUT1-(19)
INT_TXLOUT2-(19)
INT_TXLOUT0+(19)
INT_TXLOUT1+(19)
INT_TXLOUT2+(19)
R127 EV@0_4R127 EV@0_4
R124 EV@0_4R124 EV@0_4
R105 EV@0_4R105 EV@0_4
For EV@
TV A/B/C
use 0 ohm R
R159 0_4R159 0_4
R169 0_4R169 0_4
INT_CRT_BLU
INT_CRT_GRN
INT_CRT_RED
INT_CRT_DDCCLK
INT_CRT_DDCDAT
R190
R190
1K/F_4
1K/F_4
R192
R192
392/F_6
392/F_6
C428
C428
2.2u/6.3V_6
2.2u/6.3V_6
C419
C419
2.2u/6.3V_6
2.2u/6.3V_6
3
L_CTRL_CLK
L_CTRL_DATA
LVDS_IBG
T31T31
T29T29
T30T30
T28T28
T34T34
T32T32
T27T27
T35T35
T33T33
NB_TVA
NB_TVB
NB_TVC
For IV@
TV A/B/C
use 75 ohm R
NB_TV_DCONSEL_0
NB_TV_DCONSEL_1
HSYNC_A
CRTIREF
VSYNC_A
U29C
U29C
J40
L_BKLT_CTRL
H39
L_BKLT_EN
E39
L_CTRL_CLK
E40
L_CTRL_DATA
C37
L_DDC_CLK
D35
L_DDC_DATA
K40
L_VDD_EN
L41
LVDS_IBG
L43
LVDS_VBG
N41
LVDS_VREFH
N40
LVDS_VREFL
D46
LVDSA_CLK#
C45
LVDSA_CLK
D44
LVDSB_CLK#
E42
LVDSB_CLK
G51
LVDSA_DATA#_0
E51
LVDSA_DATA#_1
F49
LVDSA_DATA#_2
G50
LVDSA_DATA_0
E50
LVDSA_DATA_1
F48
LVDSA_DATA_2
G44
LVDSB_DATA#_0
B47
LVDSB_DATA#_1
B45
LVDSB_DATA#_2
E44
LVDSB_DATA_0
A47
LVDSB_DATA_1
A45
LVDSB_DATA_2
E27
TVA_DAC
G27
TVB_DAC
K27
TVC_DAC
F27
TVA_RTN
J27
TVB_RTN
L27
TVC_RTN
M35
TV_DCONSEL_0
P33
TV_DCONSEL_1
H32
CRT_BLUE
G32
CRT_BLUE#
K29
CRT_GREEN
J29
CRT_GREEN#
F29
CRT_RED
E29
CRT_RED#
K33
CRT_DDC_CLK
G35
CRT_DDC_DATA
F33
CRT_HSYNC
C32
CRT_TVO_IREF
E33
CRT_VSYNC
CRESTLINE_1p0
CRESTLINE_1p0
For EV@
CRT R/G/B
use 0 ohm R
R132 EV@0_4R132 EV@0_4
R133 EV@0_4R133 EV@0_4
R131 EV@0_4R131 EV@0_4
R137 EV@0_6R137 EV@0_6
For IV@ USE 1.3K ohm R
For EV@ USE 0 ohm R
RP30 EV@0X2RP30 EV@0X2
3
1
RP39 EV@0X2RP39 EV@0X2
1
3
4
2
2
4
For IV@
CRT R/G/B
use 150 ohm R
INT_CRT_BLU
INT_CRT_GRN
INT_CRT_RED
CRTIREF
DREFSSCLK
DREFSSCLK#
2
LVDS
LVDS
TV VGA
TV VGA
PCI-EXPRESS GRAPHICS
PCI-EXPRESS GRAPHICS
DREFCLK
DREFCLK#
2
PEG_COMPI
PEG_COMPO
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
N43
M43
J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
AD44
AD40
AG46
AH49
AG45
AG41
J50
L50
M47
U44
T49
T41
W45
W41
AB50
Y48
AC45
AC41
AH47
AG49
AH45
AG42
N45
U39
U47
N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44
M45
T38
T46
N50
R51
U43
W42
Y47
Y39
AC38
AD47
AC50
AD43
AG39
AE50
AH43
C_PEG_TXP0
C_PEG_TXN0
C_PEG_TXP1
C_PEG_TXN1
C_PEG_TXP2
C_PEG_TXN2
C_PEG_TXP3
C_PEG_TXN3
1
+VCC_PEG
EXP_A_COMPX
R173 24.9/F_4R173 24.9/F_4
PEG_RXN0 (18)
PEG_RXN1 (18,21)
PEG_RXN2 (18)
PEG_RXN3 (18)
PEG_RXN4 (18)
PEG_RXN5 (18)
PEG_RXN6 (18)
PEG_RXN7 (18)
PEG_RXN8 (18)
PEG_RXN9 (18)
PEG_RXN10 (18)
PEG_RXN11 (18)
PEG_RXN12 (18)
PEG_RXN13 (18)
PEG_RXN14 (18)
PEG_RXN15 (18)
PEG_RXP0 (18)
PEG_RXP1 (18,21)
PEG_RXP2 (18)
PEG_RXP3 (18)
PEG_RXP4 (18)
PEG_RXP5 (18)
PEG_RXP6 (18)
PEG_RXP7 (18)
PEG_RXP8 (18)
PEG_RXP9 (18)
PEG_RXP10 (18)
PEG_RXP11 (18)
PEG_RXP12 (18)
PEG_RXP13 (18)
PEG_RXP14 (18)
C_PEG_TXN0
C_PEG_TXN1
C_PEG_TXN2
C_PEG_TXN3
C_PEG_TXN4
C_PEG_TXN5
C_PEG_TXN6
C_PEG_TXN7
C_PEG_TXN8
C_PEG_TXN9
C_PEG_TXN10
C_PEG_TXN11
C_PEG_TXN12
C_PEG_TXN13
C_PEG_TXN14
C_PEG_TXN15
C_PEG_TXP0
C_PEG_TXP1
C_PEG_TXP2
C_PEG_TXP3
C_PEG_TXP4
C_PEG_TXP5
C_PEG_TXP6
C_PEG_TXP7
C_PEG_TXP8
C_PEG_TXP9
C_PEG_TXP10
C_PEG_TXP11
C_PEG_TXP12
C_PEG_TXP13
C_PEG_TXP14
C_PEG_TXP15
PEG_RXP15 (18)
C526 EV@0.1u/10V_4C526 EV@0.1u/10V_4
C524 EV@0.1u/10V_4C524 EV@0.1u/10V_4
C522 EV@0.1u/10V_4C522 EV@0.1u/10V_4
C520 EV@0.1u/10V_4C520 EV@0.1u/10V_4
C487 EV@0.1u/10V_4C487 EV@0.1u/10V_4
C511 EV@0.1u/10V_4C511 EV@0.1u/10V_4
C499 EV@0.1u/10V_4C499 EV@0.1u/10V_4
C489 EV@0.1u/10V_4C489 EV@0.1u/10V_4
C479 EV@0.1u/10V_4C479 EV@0.1u/10V_4
C483 EV@0.1u/10V_4C483 EV@0.1u/10V_4
C493 EV@0.1u/10V_4C493 EV@0.1u/10V_4
C515 EV@0.1u/10V_4C515 EV@0.1u/10V_4
C497 EV@0.1u/10V_4C497 EV@0.1u/10V_4
C513 EV@0.1u/10V_4C513 EV@0.1u/10V_4
C495 EV@0.1u/10V_4C495 EV@0.1u/10V_4
C517 EV@0.1u/10V_4C517 EV@0.1u/10V_4
C527 EV@0.1u/10V_4C527 EV@0.1u/10V_4
C525 EV@0.1u/10V_4C525 EV@0.1u/10V_4
C523 EV@0.1u/10V_4C523 EV@0.1u/10V_4
C521 EV@0.1u/10V_4C521 EV@0.1u/10V_4
C488 EV@0.1u/10V_4C488 EV@0.1u/10V_4
C512 EV@0.1u/10V_4C512 EV@0.1u/10V_4
C500 EV@0.1u/10V_4C500 EV@0.1u/10V_4
C490 EV@0.1u/10V_4C490 EV@0.1u/10V_4
C480 EV@0.1u/10V_4C480 EV@0.1u/10V_4
C484 EV@0.1u/10V_4C484 EV@0.1u/10V_4
C494 EV@0.1u/10V_4C494 EV@0.1u/10V_4
C516 EV@0.1u/10V_4C516 EV@0.1u/10V_4
C498 EV@0.1u/10V_4C498 EV@0.1u/10V_4
C514 EV@0.1u/10V_4C514 EV@0.1u/10V_4
C496 EV@0.1u/10V_4C496 EV@0.1u/10V_4
C518 EV@0.1u/10V_4C518 EV@0.1u/10V_4
C510 *IV@0.1u/10V_4C510 *IV@0.1u/10V_4
C507 *IV@0.1u/10V_4C507 *IV@0.1u/10V_4
C506 *IV@0.1u/10V_4C506 *IV@0.1u/10V_4
C505 *IV@0.1u/10V_4C505 *IV@0.1u/10V_4
C504 *IV@0.1u/10V_4C504 *IV@0.1u/10V_4
C503 *IV@0.1u/10V_4C503 *IV@0.1u/10V_4
C502 *IV@0.1u/10V_4C502 *IV@0.1u/10V_4
C501 *IV@0.1u/10V_4C501 *IV@0.1u/10V_4
R150 EV@0_4R150 EV@0_4
R156 EV@0_4R156 EV@0_4
R158 EV@0_4R158 EV@0_4
R157 EV@0_4R157 EV@0_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
GMCH DMI/VIDEO(2 of 7)
GMCH DMI/VIDEO(2 of 7)
GMCH DMI/VIDEO(2 of 7)
Date: Sheet
Date: Sheet
Date: Sheet
PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15
PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15
HSYNC_A
VSYNC_A
INT_CRT_DDCCLK
INT_CRT_DDCDAT
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
1
PEG_TXN0 (18)
PEG_TXN1 (18)
PEG_TXN2 (18)
PEG_TXN3 (18)
PEG_TXN4 (18)
PEG_TXN5 (18)
PEG_TXN6 (18)
PEG_TXN7 (18)
PEG_TXN8 (18)
PEG_TXN9 (18)
PEG_TXN10 (18)
PEG_TXN11 (18)
PEG_TXN12 (18)
PEG_TXN13 (18)
PEG_TXN14 (18)
PEG_TXN15 (18)
PEG_TXP0 (18)
PEG_TXP1 (18)
PEG_TXP2 (18)
PEG_TXP3 (18)
PEG_TXP4 (18)
PEG_TXP5 (18)
PEG_TXP6 (18)
PEG_TXP7 (18)
PEG_TXP8 (18)
PEG_TXP9 (18)
PEG_TXP10 (18)
PEG_TXP11 (18)
PEG_TXP12 (18)
PEG_TXP13 (18)
PEG_TXP14 (18)
PEG_TXP15 (18)
SDVOB_RED+ (21)
SDVOB_RED- (21)
SDVOB_GREEN+ (21)
SDVOB_GREEN- (21)
SDVOB_BLUE+ (21)
SDVOB_BLUE- (21)
SDVOB_CLK+ (21)
SDVOB_CLK- (21)
TE1
TE1
TE1
641Wednesday, January 23, 2008
641Wednesday, January 23, 2008
641Wednesday, January 23, 2008
of
of
of
1A
1A
1A
5
NB(Memory controller)
4
3
2
1
M_A_DQ[63:0](13)
D D
C C
B B
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
AR43
AW44
BA45
AY46
AR41
AR45
AT42
AW47
BB45
BF48
BG47
BJ45
BB47
BG50
BH49
BE45
AW43
BE44
BG42
BE40
BF44
BH45
BG40
BF40
AR40
AW40
AT39
AW36
AW41
AY41
AV38
AT38
AV13
AT13
AW11
AV11
AU15
AT11
BA13
BA11
BE10
BD10
BD8
AY9
BG10
AW9
BD7
BB9
BB5
AY7
AT5
AT7
AY6
BB7
AR5
AR8
AR9
AN3
AM8
AN10
AT9
AN9
AM9
AN11
U29D
U29D
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
CRESTLINE_1p0
CRESTLINE_1p0
BB19
SA_BS_0
BK19
SA_BS_1
BF29
SA_BS_2
BL17
SA_CAS#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_RAS#
SA_RCVEN#
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
SA_WE#
AT45
BD44
BD42
AW38
AW13
BG8
AY5
AN6
AT46
BE48
BB43
BC37
BB16
BH6
BB2
AP3
AT47
BD47
BC41
BA37
BA16
BH7
BC1
AP2
BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16
BE18
AY20
BA19
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
TP_SA_RCVEN#
M_A_BS#0 (12,13)
M_A_BS#1 (12,13)
M_A_BS#2 (12,13)
M_A_CAS# (12,13)
M_A_DM[7:0] (13)
M_A_DQS[7:0] (13)
M_A_DQS#[7:0] (13)
M_A_A[13:0] (12,13)
M_A_RAS# (12,13)
T24T24
M_A_WE# (12,13)
M_B_DQ[63:0](13)
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
AP49
AR51
AW50
AW51
AN51
AN50
AV50
AV49
BA50
BB50
BA49
BE50
BA51
AY49
BF50
BF49
BJ50
BJ44
BJ43
BL43
BK47
BK49
BK43
BK42
BJ41
BL41
BJ37
BJ36
BK41
BJ40
BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12
BJ10
BK10
BH5
BG1
BC2
BK3
BE4
BD3
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2
BL9
BK5
BL5
BK9
BJ8
BJ6
BF4
BJ2
U29E
U29E
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
CRESTLINE_1p0
CRESTLINE_1p0
AY17
SB_BS_0
BG18
SB_BS_1
BG36
SB_BS_2
BE17
SB_CAS#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_RAS#
SB_RCVEN#
SB_WE#
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
AR50
BD49
BK45
BL39
BH12
BJ7
BF3
AW2
AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3
BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13
AV16
AY18
BC17
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
TP_SB_RCVEN#
M_B_BS#0 (12,13)
M_B_BS#1 (12,13)
M_B_BS#2 (12,13)
M_B_CAS# (12,13)
M_B_DM[7:0] (13)
M_B_DQS[7:0] (13)
M_B_DQS#[7:0] (13)
M_B_A[13:0] (12,13)
M_B_RAS# (12,13)
T14T14
M_B_WE# (12,13)
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
MCH DDR(3 of 7)
MCH DDR(3 of 7)
MCH DDR(3 of 7)
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
PROJECT :
TE1
TE1
TE1
1A
1A
741Wednesday, January 23, 2008
741Wednesday, January 23, 2008
741Wednesday, January 23, 2008
1
1A
of
of
of
5
4
3
2
1
NB(Power-1)
+1.05V
D D
+1.8VSUS
C151
C151
0.1u/10V_4
0.1u/10V_4
C C
+1.05_VCC_AXG_NCTF
B B
A A
C443
C443
10u/10V_8
10u/10V_8
GM:1572.62mA
PM:1310mA
533MHz:2700mA
667MHz:3300mA
C436
C436
10u/10V_8
10u/10V_8
5
7700mA
AT35
AT34
AH28
AC32
AC31
AK32
AJ31
AJ28
AH32
AH31
AH29
AF32
AU32
AU33
AU35
AV33
AW33
AW35
AY35
BA32
BA33
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35
BJ32
BJ33
BJ34
BK32
BK33
BK34
BK35
BL33
AU30
W13
W14
AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31
AJ20
AN14
R30
R20
T14
Y12
U29G
U29G
VCC_1
VCC_2
VCC_3
VCC_5
VCC_4
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36
VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
CRESTLINE_1p0
CRESTLINE_1p0
VCC CORE
VCC CORE
POWER
POWER
VCC SMVCC GFX
VCC SMVCC GFX
VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC GFX NCTF
VCC GFX NCTF
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
VCC SM LF
VCC SM LF
4
T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31
AW45
BC39
BE39
BD17
BD4
AW8
AT6
+1.05_VCC_AXG_NCTF
+1.05_VCC_AXG_NCTF
VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7
C93
C93
0.1u/10V_4
0.1u/10V_4
C114
C114
*IV@0.47u/10V_6
*IV@0.47u/10V_6
C94
C94
0.1u/10V_4
0.1u/10V_4
C97
C97
*IV@1u/10V_6
*IV@1u/10V_6
C88
C88
0.22u/6.3V_4
0.22u/6.3V_4
+1.05V
3
C98
C98
*IV@10u/10V_8
*IV@10u/10V_8
+1.05V
C155
C155
10u/10V_8
10u/10V_8
C96
C96
0.22u/6.3V_4
0.22u/6.3V_4
+
+
C403
C403
*330u/2.5V_3528
*330u/2.5V_3528
C100
C100
*IV@22u/6.3V_8
*IV@22u/6.3V_8
C141
C141
0.22u/6.3V_4
0.22u/6.3V_4
C161
C161
0.47u/10V_6
0.47u/10V_6
C149
C149
10u/10V_8
10u/10V_8
R107
R107
*IV@0_8
*IV@0_8
C109
C109
*IV@0.1u/10V_4
*IV@0.1u/10V_4
C159
C159
0.22u/6.3V_4
0.22u/6.3V_4
C163
C163
1u/10V_6
1u/10V_6
C115
C115
0.22u/6.3V_4
0.22u/6.3V_4
R130
R130
*IV@0_8
*IV@0_8
C104
C104
*IV@0.1u/10V_4
*IV@0.1u/10V_4
C127
C127
0.1u/10V_4
0.1u/10V_4
C176
C176
1u/10V_6
1u/10V_6
C140
C140
0.22u/6.3V_4
0.22u/6.3V_4
+1.05V
C158
C158
0.1u/10V_4
0.1u/10V_4
2
R138
R138
*IV@0_8
*IV@0_8
R125
R125
EV@0_4
EV@0_4
C154
C154
0.1u/10V_4
0.1u/10V_4
U29F
U29F
AB33
VCC_NCTF_1
AB36
VCC_NCTF_2
AB37
C137
C137
0.1u/10V_4
0.1u/10V_4
AC33
AC35
AC36
AD35
AD36
AF33
AF36
AH33
AH35
AH36
AH37
AJ33
AJ35
AK33
AK35
AK36
AK37
AD33
AJ36
AM35
AL33
AL35
AA33
AA35
AA36
AP35
AP36
AR35
AR36
Y32
Y33
Y35
Y36
Y37
T30
T34
T35
U29
U31
U32
U33
U35
U36
V32
V33
V36
V37
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
VCC_NCTF_45
VCC_NCTF_46
VCC_NCTF_47
VCC_NCTF_48
VCC_NCTF_49
VCC_NCTF_50
VCC NCTF
VCC NCTF
POWER
POWER
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS NCTF
VSS NCTF
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS SCBVCC AXM
VSS SCBVCC AXM
540mA
AL24
VCC_AXM_NCTF_1
AL26
VCC_AXM_NCTF_2
AL28
VCC_AXM_NCTF_3
AM26
VCC_AXM_NCTF_4
AM28
VCC_AXM_NCTF_5
AM29
VCC_AXM_NCTF_6
AM31
VCC_AXM_NCTF_7
AM32
VCC_AXM_NCTF_8
AM33
VCC_AXM_NCTF_9
AP29
VCC_AXM_NCTF_10
AP31
VCC_AXM_NCTF_11
AP32
VCC_AXM_NCTF_12
AP33
VCC_AXM_NCTF_13
AL29
VCC_AXM_NCTF_14
AL31
VCC_AXM_NCTF_15
AL32
VCC_AXM_NCTF_16
AR31
VCC_AXM_NCTF_17
AR32
VCC_AXM_NCTF_18
AR33
VCC_AXM_NCTF_19
CRESTLINE_1p0
CRESTLINE_1p0
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
GMCH Power-1(4 of 7)
GMCH Power-1(4 of 7)
GMCH Power-1(4 of 7)
Date: Sheet
Date: Sheet
Date: Sheet
VCC AXM NCTF
VCC AXM NCTF
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
1
VSS_SCB1
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6
VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_5
VCC_AXM_6
VCC_AXM_7
TE1
TE1
TE1
T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28
A3
B2
C1
BL1
BL51
A51
+1.05V
AT33
AT31
AK29
AK24
AK23
AJ26
AJ23
1A
1A
1A
of
of
of
841Wednesday, January 23, 2008
841Wednesday, January 23, 2008
841Wednesday, January 23, 2008
NB(Power-2)
5
+1.25V
L17
L17
*IV@10uh_8
*IV@10uh_8
C466
C466
+
+
*IV@220u/6.3V_7343
*IV@220u/6.3V_7343
D D
+1.25V
L19
L19
*IV@10uh_8
*IV@10uh_8
C464
C464
+
+
*IV@220u/6.3V_7343
*IV@220u/6.3V_7343
+1.25V_VCCA_DPLLA
+1.25V_VCCA_DPLLB
R180
R180
R183
R183
EV@0_4
EV@0_4
EV@0_4
C C
+3V
B B
A A
EV@0_4
C67 22u/6.3vV_8C67 22u/6.3vV_8
L31 *IV@PBY160808T-301Y-N_6L31 *IV@PBY160808T-301Y-N_6
C411
C411
*IV@22u/6.3V_8
*IV@22u/6.3V_8
+1.5V
C420
C420
*IV@10u/10V_8
*IV@10u/10V_8
R118 0_6R118 0_6
C185
C185
*IV@0.1u/10V_4
*IV@0.1u/10V_4
100mA
C181
C181
*IV@0.1u/10V_4
*IV@0.1u/10V_4
L10 PBY160808T-301Y-N_6L10 PBY160808T-301Y-N_6
+1.25V
L9 PBY160808T-301Y-N_6L9 PBY160808T-301Y-N_6
V1.25M_MPLL_RC
+1.25V
+3V_TV_DAC
C415
C415
*IV@0.1u/10V_4
*IV@0.1u/10V_4
C413
C413
*IV@0.1u/10V_4
*IV@0.1u/10V_4
C421
C421
*IV@0.1u/10V_4
*IV@0.1u/10V_4
C128
C128
0.1u/10V_4
0.1u/10V_4
R109 *IV@100/F_6R109 *IV@100/F_6
C126
C126
*IV@0.1u/10V_4
*IV@0.1u/10V_4
5
50mA
150mA
+
+
C69
C69
*100u/6.3V_3528
*100u/6.3V_3528
+1.25V
C416
C416
*IV@22n/16V_4
*IV@22n/16V_4
C422
C422
*IV@22n/16V_4
*IV@22n/16V_4
C414
C414
*IV@22n/16V_4
*IV@22n/16V_4
R167 *IV@0_6R167 *IV@0_6
+3V
L36 *IV@PBY160808T-301Y-N_6L36 *IV@PBY160808T-301Y-N_6
+3V
+3V_TV_DAC
R76
R76
0.5/F_6
0.5/F_6
R102 0_6R102 0_6
R430 0_6R430 0_6
R420
R420
EV@0_4
EV@0_4
C427
C427
**IV@22u/6.3V_8
**IV@22u/6.3V_8
R120 *IV@0_6R120 *IV@0_6
C75
C75
22u/6.3vV_8
22u/6.3vV_8
C79
C79
0.1u/10V_4
0.1u/10V_4
C105
C105
*22u/6.3V_8
*22u/6.3V_8
C452
C452
*1u/16V_6
*1u/16V_6
60mA
60mA 0.5mA
C107
C107
22n/16V_4
22n/16V_4
C108
C112
C112
*IV@22n/16V_4
*IV@22n/16V_4
C108
*IV@1u/10V_6
*IV@1u/10V_6
4
+3V_VCCSYNC
C143
C143
*IV@0.1u/10V_4
*IV@0.1u/10V_4
C433
C433
*IV@0.1u/10V_4
*IV@0.1u/10V_4
C120
C120
*IV@0.1u/10V_4
*IV@0.1u/10V_4
C85
C85
0.1u/10V_4
0.1u/10V_4
R187 0_8R187 0_8
+3V
C177 0.1u/10V_4C177 0.1u/10V_4
C102
C102
4.7u/6.3V_6
4.7u/6.3V_6
C453
C453
*1u/16V_6
*1u/16V_6
R143 EV@0_4R143 EV@0_4
R126 *IV@0_6R126 *IV@0_6
R99 0_6R99 0_6
+1.25V
250mA
90mA
L20 PBY160808T-301Y-N_6L20 PBY160808T-301Y-N_6
+1.25V
+V1.25S_PEGPLL_FB
C209
C209
10u/10V_8
10u/10V_8
R176 *IV@0_6R176 *IV@0_6
+1.8VSUS
R122
R122
EV@0_4
EV@0_4
4
10mA
+3V_VCCA_CRT_DAC
+3V_VCCA_DAC_BG
C123
C123
*IV@22n/16V_4
*IV@22n/16V_4
C458
C458
10u/10V_8
10u/10V_8
R165
R165
EV@0_4
EV@0_4
C432
C432
*IV@22n/16V_4
*IV@22n/16V_4
C449
C449
*IV@1000p/50V_4
*IV@1000p/50V_4
C192
C192
Share VCCD_PEG_PLL
0.1u/10V_4
0.1u/10V_4
C99
C99
22u/6.3vV_8
22u/6.3vV_8
C133
C133
0.1u/10V_4
0.1u/10V_4
+1.25VM_MCH_VCCD_HPLL
C86
C86
0.1u/10V_4
0.1u/10V_4
R185
R185
1_8
1_8
C167
C167
*IV@1u/10V_6
*IV@1u/10V_6
70mA
R424
R424
EV@0_4
EV@0_4
5mA
R139
R139
EV@0_4
EV@0_4
+1.25V_VCCA_DPLLA
+1.25V_VCCA_DPLLB
+1.25VM_VCCA_HPLL
+1.25VM_VCCA_MPLL
10mA
+1.8VSUS_VCC_TX_LVDS
0.4mA
+3V_VCCA_PEG_BG
+1.25V_VCCD_PEG_PLL
DDR2:550mA
+1.25VM_VCCA_SM
C101
C101
1u/10V_6
1u/10V_6
35mA
+1.25VM_VCCA_SM_CK
40mA
40mA
40mA
+1.5V_VCCD_CRT
+1.5V_VCCD_TVDAC
+1.5V_VCCD_QDAC
+1.25V_VCCD_PEG_PLL
C190
C190
0.1u/10V_4
0.1u/10V_4
150mA
+1.8V_VCCD_LVDS
C172
C172
**IV@10u/10V_8
**IV@10u/10V_8
3
EnableBall EnableDisable DisableBall
VCCA_CRT
3.3V GND
VCCD_CRT
1.5V
VCCDQ_CRT
3.3V
VCCA_A_TVO
3.3V
VCCA_B_TVO VCC_SYNC
U29H
U29H
J32
VCCSYNC
A33
VCCA_CRT_DAC_1
B33
VCCA_CRT_DAC_2
A30
VCCA_DAC_BG
B32
VSSA_DAC_BG
B49
VCCA_DPLLA
H49
VCCA_DPLLB
AL2
VCCA_HPLL
AM2
VCCA_MPLL
A41
VCCA_LVDS
B41
VSSA_LVDS
K50
VCCA_PEG_BG
K49
VSSA_PEG_BG
U51
VCCA_PEG_PLL
AW18
VCCA_SM_1
AV19
VCCA_SM_2
AU19
VCCA_SM_3
AU18
VCCA_SM_4
AU17
VCCA_SM_5
AT22
VCCA_SM_7
AT21
VCCA_SM_8
AT19
VCCA_SM_9
AT18
VCCA_SM_10
AT17
VCCA_SM_11
AR17
VCCA_SM_NCTF_1
AR16
VCCA_SM_NCTF_2
BC29
VCCA_SM_CK_1
BB29
VCCA_SM_CK_2
C25
VCCA_TVA_DAC_1
B25
VCCA_TVA_DAC_2
C27
VCCA_TVB_DAC_1
B27
VCCA_TVB_DAC_2
B28
VCCA_TVC_DAC_1
A28
VCCA_TVC_DAC_2
M32
VCCD_CRT
L29
VCCD_TVDAC
N28
VCCD_QDAC
AN2
VCCD_HPLL
U48
VCCD_PEG_PLL
J41
VCCD_LVDS_1
H42
VCCD_LVDS_2
CRESTLINE_1p0
CRESTLINE_1p0
+1.05V
R172
R172
EV@0_4
EV@0_4
+3V
3
VCCA_C_TVO
GND
VCCD_TVO
GND
VCCABG_DAC
GND
VSSABG_DAC
GND
CRTPLLAPEGASMTV
CRTPLLAPEGASMTV
VCC_AXD_1
VCC_AXD_2
VCC_AXD_3
VCC_AXD_4
VCC_AXD_5
AXD
AXD
VCC_AXD_6
VCC_AXD_NCTF
VCC_AXF_1
POWER
POWER
A CK A LVDS
A CK A LVDS
D TV/CRTLVDS
D TV/CRTLVDS
D18 PDZ5.6BD18 PDZ5.6B
2 1
VCC_AXF_2
VCC_AXF_3
AXF
AXF
VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4
SM CK
SM CK
VCC_TX_LVDS
HV
HV
VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
PEG
PEG
VCC_PEG_5
VCC_RXR_DMI_1
VCC_RXR_DMI_2
DMI
DMI
3.3V
1.5V1.5V
3.3V
GND
3.3V
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT
VTT
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VCC_DMI
VCC_HV_1
VCC_HV_2
VTTLF1
VTTLF2
VTTLF3
VTTLF
VTTLF
U13
U12
U11
U9
U8
U7
U5
U3
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1
AT23
AU28
AU24
AT29
AT25
AT30
AR29
B23
B21
A21
AJ50
BK24
BK23
BJ24
BJ23
A43
C40
B40
AD51
W50
W51
V49
V50
AH50
AH51
A7
F2
AH1
+1.05V_SD
GND
1.5V
GND
GND
GND
2
850mA
+1.05V
+1.25V_AXD
515mA
+1.25V_VCC_AXF
+1.25V_VCC_DMI
+1.8VSUS_VCC_SM_CK
+1.8VSUS_VCC_TX_LVDS
+3V_VCC_HV
C81
C81
0.47u/6.3V_4
0.47u/6.3V_4
R191
R191
10_4
10_4
R425 0_4R425 0_4
2
LVDS Disable/Enable guidelineCRT/TV Disable/Enable guideline
External VGA with EV@part,Internal VGA with IV@ part
Signal
VCCD_LVDS
VCCA_LVDS
VCCTX_LVDS
495mA
100mA
200mA
C89
C89
4.7u/10V_8
4.7u/10V_8
C119
C119
1u/10V_6
1u/10V_6
C106
C106
0.1u/10V_4
0.1u/10V_4
If SDVO Disable
LVDS Disable
GND
GND
EXTERNAL INTERNAL
C73
C73
4.7u/10V_8
4.7u/10V_8
R140 0_6R140 0_6
C116
C116
*22u/6.3V_8
*22u/6.3V_8
C407
C407
1u/10V_6
1u/10V_6
C205
C205
0.1u/10V_4
0.1u/10V_4
C118
C118
10u/10V_8
10u/10V_8
If SDVO enable
LVDS Disable
1.8V
GND
GNDGND
C95
C95
2.2u/10V_8
2.2u/10V_8
R414 0_6R414 0_6
C410
C410
10u/10V_8
10u/10V_8
R188 0_6R188 0_6
L14 1uh_8L14 1uh_8
R419 1_6R419 1_6
C82
C82
0.47u/10V_6
0.47u/10V_6
100mA
C448
C448
R428
100mA
1310mA
R428
EV@0_4
EV@0_4
+VCC_PEG
*IV@1000p/50V_4
*IV@1000p/50V_4
260mA
+
+
C467
C467
10u/10V_8
10u/10V_8
C83
C83
0.47u/6.3V_4
0.47u/6.3V_4
C405
C405
0.47u/6.3V_4
0.47u/6.3V_4
R151 *IV@10_4R151 *IV@10_4
+3V_VCC_HV
C441
C441
0.1u/10V_4
0.1u/10V_4
D15 *IV@PDZ5.6BD15 *IV@PDZ5.6B
VCCGFPLLOW
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
GMCH Power-2(5 of 7)
GMCH Power-2(5 of 7)
GMCH Power-2(5 of 7)
Date: Sheet
Date: Sheet
Date: Sheet
PROJECT :
1
If SDVO enable
LVDS enable
1.8V
1.8V
1.8V
+1.25V
+1.25V
+1.25V
+V1.8_SMCK_RC
L37 *IV@1uh_8L37 *IV@1uh_8
+
+
C444
C444
*IV@220u/6.3V_7343
*IV@220u/6.3V_7343
L38 91nh_L32L38 91nh_L32
C463
C463
220u/6.3V_7343
220u/6.3V_7343
21
1
+1.05V
+1.8VSUS
C412 22u/6.3vV_8C412 22u/6.3vV_8
+1.8VSUS
+1.05V
+1.05V+3V_VCCSYNC
TE1
TE1
TE1
of
of
of
941Wednesday, January 23, 2008
941Wednesday, January 23, 2008
941Wednesday, January 23, 2008
1A
1A
1A
5
4
3
2
1
NB(Power-3)
U29I
U29I
A13
VSS_1
A15
VSS_2
A17
VSS_3
A24
VSS_4
AA21
VSS_5
AA24
VSS_6
AA29
VSS_7
AB20
D D
C C
B B
A A
5
AB23
AB26
AB28
AB31
AC10
AC13
AC3
AC39
AC43
AC47
AD1
AD21
AD26
AD29
AD3
AD41
AD45
AD49
AD5
AD50
AD8
AE10
AE14
AE6
AF20
AF23
AF24
AF31
AG2
AG38
AG43
AG47
AG50
AH3
AH40
AH41
AH7
AH9
AJ11
AJ13
AJ21
AJ24
AJ29
AJ32
AJ43
AJ45
AJ49
AK20
AK21
AK26
AK28
AK31
AK51
AL1
AM11
AM13
AM3
AM4
AM41
AM45
AN1
AN38
AN39
AN43
AN5
AN7
AP4
AP48
AP50
AR11
AR2
AR39
AR44
AR47
AR7
AT10
AT14
AT41
AT49
AU1
AU23
AU29
AU3
AU36
AU49
AU51
AV39
AV48
AW1
AW12
AW16
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
CRESTLINE_1p0
CRESTLINE_1p0
VSS
VSS
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41
4
3
U29J
U29J
C46
C50
C7
D13
D24
D3
D32
D39
D45
D49
E10
E16
E24
E28
E32
E47
F19
F36
F4
F40
F50
G1
G13
G16
G19
G24
G28
G29
G33
G42
G45
G48
G8
H24
H28
H4
H45
J11
J16
J2
J24
J28
J33
J35
J39
K12
K47
K8
L1
L17
L20
L24
L28
L3
L33
L49
M28
M42
M46
M49
M5
M50
M9
N11
N14
N17
N29
N32
N36
N39
N44
N49
N7
P19
P2
P23
P3
P50
R49
T39
T43
T47
U41
U45
U50
V2
V3
CRESTLINE_1p0
CRESTLINE_1p0
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS
VSS
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28
AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
GMCH Power-3(6 of 7)
GMCH Power-3(6 of 7)
GMCH Power-3(6 of 7)
Date: Sheet
Date: Sheet
2
Date: Sheet
PROJECT :
TE1
TE1
TE1
1A
1A
of
of
of
10 41Wednesday, January 23, 2008
10 41Wednesday, January 23, 2008
10 41Wednesday, January 23, 2008
1
1A
5
4
3
2
1
Strap table(base on checklist Ver1.6)
All strap are sampled with respect to the leading edge of the GMCH Power OK(PWROK) Signal
CFG[17:3] Have internal Pull-up
CFG[18:19] Have internal Pull-down
Any CFG signal strapping option not list below should be left NC Pin
Pin Name Strap description
D D
CFG[2:0]
CFG[4:3]
CFG5
CFG6
CFG7
CFG8
FSB Frequency Select
Reserved
DMI X2 Select
Reserved
Intel? Management Engine Crypto strap
Reserved
Configuration
010 = FSB 800MHz
011 = FSB 667MHz
0 = DMI X2
1 = DMI X4(Default)
0 = Intel? Management Engine Crypto Transport Layer.Security (TLS) cipher suite with no confidentiality
1= Intel Management Engine Crypto TLS Cipher Suite with confidentiality (default)
CFG9
CFG[11:10]
C C
CFG[13:12]
CFG[15:14]
CFG16
CFG[18:17]
SDVO_CTRLDATA
CFG19
CFG20
B B
DMI X2 Select
MCH_CFG_5 Low = DMIX2
High = IDMIX4(Default)
FSB Dynamic ODT
MCH_CFG_16 Low = ODT Disable
A A
MCH_CFG_16(6)
High = ODT Enable(Default)
5
PCI Express Graphics Lane Reversal
Reserved
XOR/ALLZ
Reserved
FSB Dynamic ODT
Reserved
SDVO Present
DMI Lane Reversal
SDVO/PCIe concurrent
DMI Lane Reversal
MCH_CFG_19 Low = Normal operation(Default)
R114
R114
*4.02K_4
*4.02K_4
MCH_CFG_19(6)
SDVO/PCIE Concurrent operation
MCH_CFG_20
R108
R108
*4.02K_4
*4.02K_4
MCH_CFG_20(6)
High = Reverse Lane
+3V
R164
R164
*4.02K_4
*4.02K_4
Low = Only SDVO or PCIE is
operational(Default)
High = SDVO andPCIE are operating
simultaneously via the PEG port
+3V
R148
R148
*4.02K_4
*4.02K_4
4
0 = Reverse Lanes
1 = Normal operation(Default)
00 = Reserved
01 = XOR Mode Enable
10 = All-Z Mode Enabled
11 = Normal operation(Default)
0 = Dynamic ODT disable
1 = Dynamic ODT Enable(Default)
0 = No SDVO Card present(Default)
1 = SDVO Card Present
0 = Normal operation(Default)
1 = Reverse Lanes
0 = Only SDVO or PCIE is operation(Default)
1 = SDVO and PCIE are operating simultaneously via the PEG port
XOR /ALLz /Clock Un-gating
MCH_CFG_12 MCH_CFG_13 Configuration
0
0
1
1
MCH_CFG_12(6)
MCH_CFG_13(6)
0
1
0
1
Clock gating disable
XOR Mode Enable
ALL-z Mode Enable
Normal operation(Default)
3
R123
R123
*4.02K_4
*4.02K_4
PCI Express Graphics
MCH_CFG_9 Low = Reverse Lane
MCH_CFG_9(6)MCH_CFG_5(6)
R112
R112
*4.02K_4
*4.02K_4
High = Normal operation(Default)
SDVO Present
Strap define at External
HDMI control page
R111
R111
*4.02K_4
*4.02K_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
GMCH Strap(7 of 7)
GMCH Strap(7 of 7)
GMCH Strap(7 of 7)
Date: Sheet
Date: Sheet
2
Date: Sheet
PROJECT :
TE1
TE1
TE1
1A
1A
1A
of
of
of
11 41Wednesday, January 23, 2008
11 41Wednesday, January 23, 2008
11 41Wednesday, January 23, 2008
1
1
DDR2 Dual channel A/B PU
2
3
4
5
6
7
8
A A
DDRII A CHANNEL DDRII B CHANNEL
+SMDDR_VTERM +SMDDR_VTERM
C132
C148
C148
C165
C165
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
B B
M_CKE0(6,13)
M_A_BS#2(7,13)
M_A_BS#1(7,13)
C C
M_B_WE#(7,13) M_B_CAS#(7,13)
M_B_BS#1(7,13)
D D
C121
C121
0.1u/10V_4
0.1u/10V_4
M_CKE1(6,13)
C132
0.1u/10V_4
0.1u/10V_4
M_A_A3
M_A_A1
M_A_A9
M_A_A5
M_A_A2
M_A_A4
M_A_A11
M_A_A8
M_A_A12
M_A_A0
M_B_A10
M_B_A3
M_B_A1
M_B_A0
M_B_A7
M_B_A11
M_B_A8
M_B_A5
M_B_A2
M_B_A4
M_B_A9
M_B_A12
C183
C183
C174
C174
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
RP28 56X2RP28 56X2
1
3
RP34 56X2RP34 56X2
1
3
RP32 56X2RP32 56X2
1
3
RP40 56X2RP40 56X2
1
3
RP38 56X2RP38 56X2
1
3
RP41 56X2RP41 56X2
1
3
RP25 56X2RP25 56X2
1
3
RP26 56X2RP26 56X2
1
3
RP29 56X2RP29 56X2
1
3
RP27 56X2RP27 56X2
1
3
RP35 56X2RP35 56X2
1
3
RP33 56X2RP33 56X2
1
3
RP31 56X2RP31 56X2
1
3
RP36 56X2RP36 56X2
1
3
C162
C162
0.1u/10V_4
0.1u/10V_4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
C147
C147
0.1u/10V_4
0.1u/10V_4
C142
C142
C194
C194
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
Place one cap close to every 2 pull-up resistor terminated to SMDDR_VTERM
+SMDDR_VTERM
+SMDDR_VTERM
M_A_A[13..0]
M_B_A[13..0]
C193
C193
0.1u/10V_4
0.1u/10V_4
C195
C195
0.1u/10V_4
0.1u/10V_4
M_A_A[13..0] (7,13)
M_B_A[13..0] (7,13)
C134
C134
0.1u/10V_4
0.1u/10V_4
C152
C199
C199
0.1u/10V_4
0.1u/10V_4
C152
0.1u/10V_4
0.1u/10V_4
C178
C203
C202
C202
C171
C171
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
M_A_A7
M_A_A6
M_CKE3(6,13)
M_B_BS#2(7,13)
M_ODT1(6,13)
M_CS#1(6,13)
M_ODT3(6,13)
M_B_BS#0(7,13)
M_A_BS#0(7,13)
M_A_CAS#(7,13)
M_A_WE#(7,13)
M_CS#0(6,13)
M_A_RAS#(7,13)
M_CS#3(6,13)
M_CKE4(6,13)
M_ODT2(6,13)
M_B_RAS#(7,13)
M_ODT0(6,13)
M_CS#2(6,13)
M_A_A10
M_B_A6
M_A_A13
M_B_A13
C139
C139
C124
C124
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
RP37 56X2RP37 56X2
RP43 56X2RP43 56X2
RP18 56X2RP18 56X2
RP19 56X2RP19 56X2
RP24 56X2RP24 56X2
RP21 56X2RP21 56X2
RP23 56X2RP23 56X2
RP22 56X2RP22 56X2
RP42 56X2RP42 56X2
RP20 56X2RP20 56X2
RP16 56X2RP16 56X2
RP17 56X2RP17 56X2
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
C125
C125
0.1u/10V_4
0.1u/10V_4
C196
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
0.1u/10V_4
+SMDDR_VTERM
C203
C196
C169
C169
0.1u/10V_4
0.1u/10V_4
C160
C160
0.1u/10V_4
0.1u/10V_4
C144
C144
0.1u/10V_4
0.1u/10V_4
C178
0.1u/10V_4
0.1u/10V_4
Quanta Computer Inc.
Quanta Computer Inc.
M_A_A14(6,13)
M_B_A14(6,13)
1
R181 56_4R181 56_4
R178 56_4R178 56_4
2
+SMDDR_VTERM
3
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
DDR RES. ARRAY
DDR RES. ARRAY
DDR RES. ARRAY
Date: Sheet
Date: Sheet
4
5
6
Date: Sheet
7
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
TE1
TE1
TE1
12 41Wednesday, January 23, 2008
12 41Wednesday, January 23, 2008
12 41Wednesday, January 23, 2008
of
of
of
8
1A
1A
1A
DDR2 Dual channel A/B CONN
DDR2 VCC(SUS)
DDR2-800 each dimm is 2.8A
DDR2-667 EACH DIMM IS 2.6A
VTERM(SUS)
3A
A A
B B
C C
D D
1
SMDDR_VREF_DIMM
+1.8VSUS
CN25
CN25
1
VREF
3
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
VSS47
DQ0
DQ1
VSS37
DQS#0
DQS0
VSS48
DQ2
DQ3
VSS38
DQ8
DQ9
VSS49
DQS#1
DQS1
VSS39
DQ10
DQ11
VSS50
VSS18
DQ16
DQ17
VSS1
DQS#2
DQS2
VSS19
DQ18
DQ19
VSS22
DQ24
DQ25
VSS23
DM3
NC4
VSS9
DQ26
DQ27
VSS4
CKE0
VDD7
NC1
A16_BA2
VDD9
A12
A9
A8
VDD5
A5
A3
A1
VDD10
A10/AP
BA0
WE#
VDD2
CAS#
S1#
VDD3
ODT1
VSS11
DQ32
DQ33
VSS26
DQS#4
DQS4
VSS2
DQ34
DQ35
VSS27
DQ40
DQ41
VSS29
DM5
VSS51
DQ42
DQ43
VSS40
DQ48
DQ49
VSS52
NCTEST
VSS30
DQS#6
DQS6
VSS31
DQ50
DQ51
VSS33
DQ56
DQ57
VSS3
DM7
VSS34
DQ58
DQ59
VSS14
SDA
SCL
VDD(SPD)
DDR2_6H
DDR2_6H
M_A_DQ6
M_A_DQ5
M_A_DQS#0
M_A_DQS0
M_A_DQ2
M_A_DQ3
M_A_DQ9
M_A_DQ8 M_A_DM1
M_A_DQS#1
M_A_DQS1
M_A_DQ11 M_A_DQ15
M_A_DQ17
M_A_DQ20
M_A_DQS#2
M_A_DQS2
M_A_DQ23
M_A_DQ19
M_A_DQ28
M_A_DQ25
M_A_DM3
M_A_DQ26
M_A_DQ27
M_CKE0(6,12)
M_A_BS#2(7,12)
M_A_BS#0(7,12)
M_A_WE#(7,12)
M_A_CAS#(7,12)
M_CS#1(6,12)
M_ODT1(6,12)
+3V
M_A_A12
M_A_A9
M_A_A5
M_A_A3
M_A_A1
M_A_A10
M_A_DQ36 M_B_DQ36
M_A_DQ37
M_A_DQS#4
M_A_DQS4
M_A_DQ39
M_A_DQ34
M_A_DQ40
M_A_DQ41
M_A_DM5
M_A_DQ42
M_A_DQ46
M_A_DQ53
M_A_DQ49
M_A_DQS#6
M_A_DQS6
M_A_DQ50
M_A_DQ56
M_A_DQ60
M_A_DM7
M_A_DQ62
M_A_DQ63
CGDAT_SMB
CGCLK_SMB
H: 6mm
2
VSS46
DQ4
DQ5
VSS15
DM0
VSS5
DQ6
DQ7
VSS16
DQ12
DQ13
VSS17
DM1
VSS53
CK0
CK0#
VSS41
DQ14
DQ15
VSS54
VSS20
DQ20
DQ21
VSS6
NC3
DM2
VSS21
DQ22
DQ23
VSS24
DQ28
DQ29
VSS25
DQS#3
DQS3
VSS10
DQ30
DQ31
VSS8
CKE1
PC4800 DDR2 SDRAM
SO-DIMM (200P)
PC4800 DDR2 SDRAM
SO-DIMM (200P)
VDD8
A15
A14
VDD11
A11
A7
A6
VDD4
A4
A2
A0
VDD12
BA1
RAS#
S0#
VDD1
ODT0
A13
VDD6
NC2
VSS12
DQ36
DQ37
VSS28
DM4
VSS42
DQ38
DQ39
VSS55
DQ44
DQ45
VSS43
DQS#5
DQS5
VSS56
DQ46
DQ47
VSS44
DQ52
DQ53
VSS57
CK1
CK1#
VSS45
DM6
VSS32
DQ54
DQ55
VSS35
DQ60
DQ61
VSS7
DQS#7
DQS7
VSS36
DQ62
DQ63
VSS13
SA0
SA1
3
M_A_DM[0..7] (7)
M_A_DQ[0..63] (7)
+1.8VSUS +1.8VSUS +1.8VSUS
2
M_A_DQ4
4
M_A_DQ0
6
8
M_A_DM0
10
12
M_A_DQ7
14
M_A_DQ1
16
18
M_A_DQ13
20
M_A_DQ12
22
24
26
28
30
32
34
M_A_DQ10M_A_DQ14
36
38
40
42
M_A_DQ16
44
M_A_DQ21
46
48
50
M_A_DM2
52
54
M_A_DQ18
56
M_A_DQ22
58
60
M_A_DQ29
62
M_A_DQ24
64
66
M_A_DQS#3
68
M_A_DQS3
70
72
M_A_DQ30
74
M_A_DQ31
76
78
80
82
84
86
88
M_A_A11
90
M_A_A7
92
M_A_A6M_A_A8
94
96
M_A_A4
98
M_A_A2
100
M_A_A0
102
104
106
108
110
112
114
M_A_A13
116
118
120
122
M_A_DQ32
124
M_A_DQ33
126
128
M_A_DM4
130
132
M_A_DQ35
134
M_A_DQ38
136
138
M_A_DQ44
140
M_A_DQ45
142
144
M_A_DQS#5
146
M_A_DQS5
148
150
M_A_DQ43
152
M_A_DQ47
154
156
M_A_DQ48
158
M_A_DQ52
160
162
164
166
168
M_A_DM6
170
172
M_A_DQ54
174
M_A_DQ55M_A_DQ51
176
178
M_A_DQ61
180
M_A_DQ57
182
184
M_A_DQS#7
186
M_A_DQS7
188
190
M_A_DQ58
192
M_A_DQ59
194
196
R89 10K_4R89 10K_4
198
R87 10K_4R87 10K_4
200
SO-DIMM0 SPD Address is 0xA0
SO-DIMM0 TS Address is 0x30
M_A_DQS[0..7] (7)
M_A_DQS#[0..7] (7)
M_CLK_DDR0 (6)
M_CLK_DDR#0 (6)
PM_EXTTS#0 (6)
M_CKE1 (6,12)
M_A_A14 (6,12)
M_A_BS#1 (7,12)
M_A_RAS# (7,12)
M_CS#0 (6,12)
M_ODT0 (6,12)
M_CLK_DDR1 (6) M_CLK_DDR#4 (6)
M_CLK_DDR#1 (6)
M_CKE3(6,12) M_CKE4 (6,12)
M_B_BS#2(7,12)
M_B_BS#0(7,12)
M_B_WE#(7,12)
M_B_CAS#(7,12)
M_CS#3(6,12)
M_ODT3(6,12)
CGDAT_SMB(2)
CGCLK_SMB(2)
4
SMDDR_VREF_DIMM
CN24
CN24
1
VREF
3
M_B_DQ0
M_B_DQ5
M_B_DQS#0
M_B_DQS0
M_B_DQ7
M_B_DQ3
M_B_DQ9
M_B_DQ8 M_B_DM1
M_B_DQS#1
M_B_DQS1
M_B_DQ11
M_B_DQ10
M_B_DQ20
M_B_DQ17
M_B_DQS#2
M_B_DQS2
M_B_DQ22
M_B_DQ23
M_B_DQ29
M_B_DQ28
M_B_DM3
M_B_DQ26
M_B_DQ27
M_B_A12
M_B_A9
M_B_A8
M_B_A5
M_B_A3
M_B_A1
M_B_A10
M_B_DQ37
M_B_DQ38
M_B_DQS#4
M_B_DQS4
M_B_DQ34
M_B_DQ35
M_B_DQ40
M_B_DQ41
M_B_DM5
M_B_DQ46
M_B_DQ43
M_B_DQS#6
M_B_DQS6
M_B_DQ54
M_B_DQ56
M_B_DQ57 M_B_DQ61
M_B_DM7
M_B_DQ59
M_B_DQ62
CGDAT_SMB
CGCLK_SMB
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
VSS47
DQ0
DQ1
VSS37
DQS#0
DQS0
VSS48
DQ2
DQ3
VSS38
DQ8
DQ9
VSS49
DQS#1
DQS1
VSS39
DQ10
DQ11
VSS50
VSS18
DQ16
DQ17
VSS1
DQS#2
DQS2
VSS19
DQ18
DQ19
VSS22
DQ24
DQ25
VSS23
DM3
NC4
VSS9
DQ26
DQ27
VSS4
CKE0
VDD7
NC1
A16_BA2
VDD9
A12
A9
A8
VDD5
A5
A3
A1
VDD10
A10/AP
BA0
WE#
VDD2
CAS#
S1#
VDD3
ODT1
VSS11
DQ32
DQ33
VSS26
DQS#4
DQS4
VSS2
DQ34
DQ35
VSS27
DQ40
DQ41
VSS29
DM5
VSS51
DQ42
DQ43
VSS40
DQ48
DQ49
VSS52
NCTEST
VSS30
DQS#6
DQS6
VSS31
DQ50
DQ51
VSS33
DQ56
DQ57
VSS3
DM7
VSS34
DQ58
DQ59
VSS14
SDA
SCL
VDD(SPD)
DDR2_10.1H
DDR2_10.1H
VSS46
DQ4
DQ5
VSS15
DM0
VSS5
DQ6
DQ7
VSS16
DQ12
DQ13
VSS17
DM1
VSS53
CK0
CK0#
VSS41
DQ14
DQ15
VSS54
VSS20
DQ20
DQ21
VSS6
NC3
DM2
VSS21
DQ22
DQ23
VSS24
DQ28
DQ29
VSS25
DQS#3
DQS3
VSS10
DQ30
DQ31
VSS8
CKE1
VDD8
A15
A14
VDD11
PC4800 DDR2 SDRAM
SO-DIMM (200P)
PC4800 DDR2 SDRAM
SO-DIMM (200P)
A11
A7
A6
VDD4
A4
A2
A0
VDD12
BA1
RAS#
S0#
VDD1
ODT0
A13
VDD6
NC2
VSS12
DQ36
DQ37
VSS28
DM4
VSS42
DQ38
DQ39
VSS55
DQ44
DQ45
VSS43
DQS#5
DQS5
VSS56
DQ46
DQ47
VSS44
DQ52
DQ53
VSS57
CK1
CK1#
VSS45
DM6
VSS32
DQ54
DQ55
VSS35
DQ60
DQ61
VSS7
DQS#7
DQS7
VSS36
DQ62
DQ63
VSS13
SA0
SA1
H: 10.1mm
5
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
R408 10K_4R408 10K_4
198
R407 10K_4R407 10K_4
200
SO-DIMM1 SPD Address is 0xA4
SO-DIMM1 TS Address is 0x34
M_B_DQ4
M_B_DQ1
M_B_DM0
M_B_DQ2
M_B_DQ6
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ21
M_B_DM2
M_B_DQ18
M_B_DQ19
M_B_DQ24
M_B_DQ25
M_B_DQS#3
M_B_DQS3
M_B_DQ30
M_B_DQ31
M_B_A11
M_B_A7
M_B_A6
M_B_A4
M_B_A2
M_B_A0
M_B_A13
M_B_DQ32
M_B_DM4
M_B_DQ39
M_B_DQ33
M_B_DQ44
M_B_DQ45
M_B_DQS#5
M_B_DQS5
M_B_DQ42
M_B_DQ47
M_B_DQ52M_B_DQ53
M_B_DQ48M_B_DQ49
M_B_DM6
M_B_DQ55M_B_DQ51
M_B_DQ50
M_B_DQ60
M_B_DQS#7
M_B_DQS7
M_B_DQ63
M_B_DQ58
+3V
M_B_DM[0..7] (7)
M_B_DQ[0..63] (7)
M_B_DQS[0..7] (7)
M_B_DQS#[0..7] (7)
M_B_A[0..13] (7,12)M_A_A[0..13] (7,12)
M_CLK_DDR3 (6)
M_CLK_DDR#3 (6)
PM_EXTTS#1 (6)
M_B_A14 (6,12)
M_B_BS#1 (7,12)
M_B_RAS# (7,12)
M_CS#2 (6,12)
M_ODT2 (6,12)
M_CLK_DDR4 (6)
6
Close to DIMM0
+1.8VSUS
+
+
C461
C461
*330u/2.5V_3528
*330u/2.5V_3528
+1.8VSUS
C136
C136
0.1u/10V_4
0.1u/10V_4
SMDDR_VREF_DIMM
C217
C217
0.1u/10V_4
0.1u/10V_4
Close to DIMM1
+1.8VSUS
+
+
C138
C138
*330u/2.5V_3528
*330u/2.5V_3528
+1.8VSUS
C191
C191
0.1u/10V_4
0.1u/10V_4
SMDDR_VREF_DIMM
C216
C216
0.1u/10V_4
0.1u/10V_4
7
C447
C447
2.2u/6.3V_6
2.2u/6.3V_6
C180
C180
0.1u/10V_4
0.1u/10V_4
C220
C220
2.2u/6.3V_6
2.2u/6.3V_6
C435
C435
2.2u/6.3V_6
2.2u/6.3V_6
C157
C157
0.1u/10V_4
0.1u/10V_4
C219
C219
2.2u/6.3V_6
2.2u/6.3V_6
SMDDR_VREF_DIMM
R202 *10K_4R202 *10K_4
C459
C459
2.2u/6.3V_6
2.2u/6.3V_6
C450
C450
0.1u/10V_4
0.1u/10V_4
C456
C456
2.2u/6.3V_6
2.2u/6.3V_6
C164
C164
0.1u/10V_4
0.1u/10V_4
C438
C438
2.2u/6.3V_6
2.2u/6.3V_6
C168
C168
0.1u/10V_4
0.1u/10V_4
C451
C451
2.2u/6.3V_6
2.2u/6.3V_6
C150
C150
0.1u/10V_4
0.1u/10V_4
R199 0_6R199 0_6
R201 *10K_4R201 *10K_4
+3V
+3V
C446
C446
2.2u/6.3V_6
2.2u/6.3V_6
C74
C74
2.2u/6.3V_6
2.2u/6.3V_6
C429
C429
2.2u/6.3V_6
2.2u/6.3V_6
C76
C76
2.2u/6.3V_6
2.2u/6.3V_6
+SMDDR_VREF+3V
+1.8VSUS
8
C440
C440
2.2u/6.3V_6
2.2u/6.3V_6
C78
C78
0.1u/10V_4
0.1u/10V_4
C457
C457
2.2u/6.3V_6
2.2u/6.3V_6
C80
C80
0.1u/10V_4
0.1u/10V_4
CLOCK 0,1 CLOCK 3,4
CKE 2,3CKE 0,1
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
DDR SO-DIMM(200P)
DDR SO-DIMM(200P)
DDR SO-DIMM(200P)
Date: Sheet
Date: Sheet
1
2
3
4
5
6
Date: Sheet
7
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
TE1
TE1
TE1
of
of
of
13 41Wednesday, January 23, 2008
13 41Wednesday, January 23, 2008
13 41Wednesday, January 23, 2008
8
1A
1A
1A
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