QUANTA TA7 Schematics

5

4

3

14.318MHz

2

1

TA7 BLOCK DIAGRAM

Cable Docking CON.

RJ45
IEEE 1394

D D

CRT
Headphone
USB 2.0
Power Jack

PG 38

667/800 MHz

DDRII-SODIMM1

DDRII-SODIMM2

C C

FINGER PRINT

USB8

Bluetooth

USB6

USB PORT X 3

USB0~1
USB2~3

PATA ODD
AUX Battery

PG12, 13

PG 12,13

Internal HDD

B B

DDRII 533/667 MHz

DDRII 533/667 MHz

PG 36

PG 38

PG 34

PG 33

PG 33

32.768KHz

USB 2.0

PATA

SATA

Merom

(478 Micro-FCPGA)

FSB

Crestline

1299 uFCBGA

PG 5,6,7,8,9,10,11

DMI LINK

4X PCI-E

ICH8-M

676 BGA

PG14,15,16,17

PG 3,4

PCI-EXPRESS

MDC Module 1.5

CLOCK GEN

ICS9LPRS365
64pins

CPU THERMAL
SENSOR

VIDEO RAM *2

DDRIII

64bit/256MB

PG 23

ATI

M71S

PG 18,19,20,21,22

FOR Crestline (LCD/CRT)

33MHZ, 3.3V PCI

PCI-E
Azalia

Azalia

STAC9200

PG 30

PG 2

PG 3

PG 30

LCD Panel

CRT

Intel 82566

25MHz

Merom / Crestline / ICH8-M

MAX1993 VGACORE
(1.1V/1.2V)

2.5V

SYSTEM POWER(3/5V)

CPU CORE POWER ISL6262A

+1.5V

PG 24

PG 25

MINI PCI-E Card * 2

USB7
USB9

PG 26

PG 32

+1.05V/+1.25V

+1.8VSUS/+0.9V

CHARGER MAX8724 &
SELECTER

DISCHARGE

CARDBUS / IEEE 1394
CONTROLLER/CF

R5C843

PG 49

PG 48

PG 48

PG 47

PG 46

PG 45

PG 44

PG 41,42

PG 40

24.576MHz

PG 28

32.768KHz

LPC

Amplifier

MAX9789A

PG 31

SIM Card

PG 32

4 IN 1

CARD READER
SD/MMC, MS,XD

PG 29

CARDBUS
SLOT X1

PG 28

1394
CONN

PG 28

WIRE

PCI DEVICES IRQ ROUTING

IDSEL #

DEVICE

CardBus/1394

<OrgName>

<OrgName>

<OrgName>
<OrgAddr1>

<OrgAddr1>

<OrgAddr1>
<OrgAddr2>

<OrgAddr2>

<OrgAddr2>
<OrgAddr3>

<OrgAddr3>

<OrgAddr3>
<OrgAddr4>

<OrgAddr4>

<OrgAddr4>
Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Block Diagram

Block Diagram

Block Diagram

Date: Sheet

Date: Sheet

Date: Sheet

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

REQ/GNT #

AD25

PROJECT : TA7

PROJECT : TA7

PROJECT : TA7

1

PCI_INT

0

A,B,C

of

of

of

149Friday, March 02, 2007

149Friday, March 02, 2007

149Friday, March 02, 2007

1A

1A

1A

PG 37

RJ11
JACK

JACK

HEADPHONE,
2ND HEADPHONE,
MIC

3

PG 31

RJ45
JACK

PG 27

2

TPM

PG 38

A A

FAN

5

Touchpad

PG 36

LQFP 128

PG 36

IT8512

PG 35

Keyboard

PG 36

4

SIO PC87381

Digitizer

SPI FLASH

PG 35

5

L88

L88

+3.3V_M

BLM21PG600SN1D

BLM21PG600SN1D

iAMT

D D

SATA_CLKREQ#16

MINI1CLK_REQ#32

CLK_PCI_TPM38

PCLK_LPC_DEBUG32

PCI_CLK_851235

PCLK_741228

PCI_CLK_SIO37

PCI4/27_Select: 1=27MHz,0=SRC_100MHz
of Pin17 & Pin18.

C C

CLK_PCI_ICH15

PCIF5/ITP_EN: PU be used, the CK505 will
be configured to use Pin46/47 to CPU ITP
clock.If PD be detect at powe-on,the CK505
will setting Pin 46/47 to SRC8(Default is
setting to SRC8)

B B

CPU_MCH_BSEL03,6
CPU_MCH_BSEL13,6

CPU_MCH_BSEL23,6
CLK_ICH_14M16
CLK_SIO_14M37

C757

C757

10U/6.3V/X5R_8

10U/6.3V/X5R_8

+3.3V

+3.3V

+3.3V

C454 33P/50V_4C454 33P/50V_4

Layout Note:
XTAL length < 500mils

C455 33P/50V_4C455 33P/50V_4

CLK48_741229

CLK_ICH_48M16

R357 10K_4@EVR357 10K_4@EV
R355 *10K_4@IVR355 *10K_4@IV

R642 10K_4R642 10K_4
R640 *10K_4@NCR640 *10K_4@NC

C775 0.1U/10V/X5R_4C775 0.1U/10V/X5R_4

+CK_VDD_MAIN2

C758 0.1U/10V/X5R_4C758 0.1U/10V/X5R_4
C443

C443

C760 0.1U/10V/X5R_4C760 0.1U/10V/X5R_4
C764 0.1U/10V/X5R_4C764 0.1U/10V/X5R_4

C768 0.1U/10V/X5R_4C768 0.1U/10V/X5R_4

C762 0.1U/10V/X5R_4C762 0.1U/10V/X5R_4

R343 10K_4R343 10K_4

21

4.7U/10V/X5R_8

4.7U/10V/X5R_8

Y10

Y10

14.318MHZ

14.318MHZ

R770 22/F_4R770 22/F_4
R712 22/F_4R712 22/F_4
R359 2.2K_4R359 2.2K_4

R631 10K_4R631 10K_4
R625 15_4R625 15_4
R624 15_4R624 15_4

+CK_VDD_MAIN

R623

R623

475/F_4

475/F_4

R636

R636

475/F_4

475/F_4

R346 22_4R346 22_4
R344 22_4R344 22_4
R637 22_4R637 22_4
R352 12.1/F_4R352 12.1/F_4
R351 12.1/F_4R351 12.1/F_4

R639 22_4R639 22_4

add R712 and R770
remove R363
for TI7412 change

4

C783

C783

4.7U/10V/X5R_8

4.7U/10V/X5R_8

Clock Gen

U37

U37

2

VDD_PCI

9

VDD_48

16

VDD_PLL3

61

VDD_REF

CK505

CK505

VDD_SRC
VDD_CPU

VDD_96_IO
VDD_PLL3_IO
VDD_SRC_IO_1

VDD_SRC_IO_2
VDD_CPU_IO
VDD_SRC_IO_3

PCI0/CR#_A
PCI1/CR#_B
PCI2/TME
PCI3
PCI4/27MHz_Select
PCIF5/ITP_EN
XTAL_IN
XTAL_OUT
USB_48/FSA
FSB/TEST/MODE
REF0/FSC/TESTSEL
VSS_PCI

VSS_48
VSS_IO
VSS_PLL3
VSS_CPU
VSS_SRC1
VSS_SRC2
VSS_SRC3
VSS_REF

SRC1/SE1/27MHz_NonSS

SRC1#/SE2/27MHz_SS

CKPWRGD/PWRDWN#

SATACLKREQ#_R

PCI_CLK_R5C843_R

PCLK_8512_R
FCTSEL1
PCI_ICH
CG_XIN
CG_XOUT

FSA

FSC

39
55

12
20
26

36
49
45

1
3
4
5
6

7
60
59
10
57
62

8
11
15
19
52
23
29
42
58

Add capacitor pads for improving WWAN.

C462 *27P/50V_4@NCC462 *27P/50V_4@NC
C755 *27P/50V_4@NCC755 *27P/50V_4@NC
C756 *27P/50V_4@NCC756 *27P/50V_4@NC

C759 *27P/50V_4@NCC759 *27P/50V_4@NC
C459 *27P/50V_4@NCC459 *27P/50V_4@NC
C450 *27P/50V_4@NCC450 *27P/50V_4@NC
C453 *27P/50V_4@NCC453 *27P/50V_4@NC
C761 *27P/50V_4@NCC761 *27P/50V_4@NC

CLK_ICH_48M
CLK_SIO_14M
CLK_ICH_14M

PCI_CLK_8512
PCLK_7412
PCLK_LPC_DEBUG
CLK_PCI_TPM
CLK_PCI_ICH

0.1U/10V/X5R_4

0.1U/10V/X5R_4

SCLK

SDA

PCI_STOP#

CPU_STOP#

CPU0

CPU0#

CPU1

CPU1#

SRC8/ITP

SRC8#/ITP#

SRC10#

SRC10

SRC11/CR#_H

SRC11#/CR#_G

SRC9

SRC9#

SRC7/CR#_F

SRC7#/CR#_E

SRC6

SRC6#

SRC4

SRC4#

SRC3/CR#_C

SRC3#/CR#_D

SRC2/SATA

SRC2#/SATA#

SRC0/DOT96

SRC0#/DOT96#

ICS9LPRS365BGLFT

ICS9LPRS365BGLFT

C771

C771

NC

C779

C779

0.1U/10V/X5R_4

0.1U/10V/X5R_4

48

T159T159

CGCLK_SMB_M

64

CGDAT_SMB_M

63
38

37

CPU_BCLK

54

CPU_BCLK#

53

MCH_BCLK

51

MCH_BCLK#

50

CPU_ITP

47

CPU_ITP#

46

MCH_3GPLL#

35

MCH_3GPLL

34

CLK_3GPLLREQ#_R

33

MINI2CLK_REQ#_RPCLK_TPM_R

32

PCIE_MINI2

30

PCIE_MINI2#

31

PECLK_VGA_R

44

PECLK_VGA#_R

43

PCIE_ICH

41

PCIE_ICH#

40

PCIE_MINI1

27

PCIE_MINI1#

28
24

25

PCIE_SATA

21

PCIE_SATA#

22

DREFSSCLK_R

17

DREFSSCLK#_R

18

DREFCLK_R

13

DREFCLK#_R

14
56

3

0.1U/10V/X5R_4

0.1U/10V/X5R_4

+CK_VDD_MAIN +3.3V

C770

C770

C774

C774

C765

C765

0.1U/10V/X5R_4

0.1U/10V/X5R_4

0.1U/10V/X5R_4

0.1U/10V/X5R_4

CGCLK_SMB_M 12,13
CGDAT_SMB_M 12,13

UMA & Discrete Dis/Enable setting

CPU Clock select

2

L90

L90

12

H_STP_PCI# 16
H_STP_CPU# 16

CLK_CPU_BCLK 3
CLK_CPU_BCLK# 3

CLK_MCH_BCLK 5
CLK_MCH_BCLK# 5

CLK_MCH_3GPLL# 6
CLK_MCH_3GPLL 6

CLK_3GPLLREQ# 6
MINI2CLK_REQ# 32

CLK_PCIE_MINI2 32
CLK_PCIE_MINI2# 32

CLK_PCIE_VGA 18
CLK_PCIE_VGA# 18

CLK_PCIE_ICH 15
CLK_PCIE_ICH# 15

CLK_PCIE_MINI1 32
CLK_PCIE_MINI1# 32

CLK_PCIE_SATA 14
CLK_PCIE_SATA# 14

DREF_SSCLK 6
DREF_SSCLK# 6

MCH_DREFCLK 6
MCH_DREFCLK# 6

CLK_VGA_27M_NSS 19
CLK_VGA_27M_SS 19

CLK_PWRGD 16

100

33

100

33

100

33

100

33

100
100
100

33

100

33

+3.3V_M

iAMT

T160T160
T161T161

BLM21PG600SN1D

BLM21PG600SN1D

C767

C767

C776

C776

0.1U/10V/X5R_4

0.1U/10V/X5R_4

10U/6.3V/X5R_8

10U/6.3V/X5R_8

RP43

4
2

4
2

4
2

4
2

R648 475/F_4R648 475/F_4
R651 475/F_4R651 475/F_4

2
4

4
2

2
4

4
2

4
2

2
4

4
2

4
2

FSC FSB
1330
0
0
0
00
1
1
1

RP43

3

0X2

0X2

1

RP44

RP44

3

0X2

0X2

1

CLK_CPU_ITP

RP45

RP45

3

CLK_CPU_ITP#

*0X2

*0X2

1

RP49

RP49

3

0X2

0X2

1

RP48

RP48

1

0X2

0X2

3

RP47

RP47

3

0X2

0X2

1

RP37

RP37

1

0X2

0X2

3

RP38

RP38

3

0X2

0X2

1

RP36

RP36

3

0X2

0X2

1

RP46

RP46

1

*0X2@IV

*0X2@IV

3

RP34

RP34

3

*0X2@IV

*0X2@IV

1

RP35

RP35

3

0X2

0X2

1

FSA CPU SRC PCI
1 100
10

133
166

1

1
1

033
1
1

200

0

266

0

333

0

400

0
1

RSVD

iAMT

Discrete

MINI1CLK_REQ#
MINI2CLK_REQ#
CLK_3GPLLREQ#
SATA_CLKREQ#

R632 10K_4R632 10K_4
R650 10K_4R650 10K_4
R649 10K_4R649 10K_4
R622 10K_4R622 10K_4

2N7002W-7-F

2N7002W-7-F

ICH_SMBDATA16,32

2N7002W-7-F

2N7002W-7-F

ICH_SMBCLK16,32

UMA & Discrete setting

CLK Discrete / UMA

--------------------­RP47 0 NC
RP46 NC 0
RP34 NC 0
RP35 0 NC

1

Clock Gen I2C

+3.3V_M

R627

R627
10K_4

10K_4

2

Q49

Q49

3 1

+3.3V_M

2

Q50

Q50

3 1

R628

R628
10K_4

10K_4

CGDAT_SMB_M

CGCLK_SMB_M

Mika 2006/11/30
R770 R712 change value from 15 to 12.1

(CS01212FB14)
Mika 2007/01/05

R770 R712 change value from 12.1 to 22

A A

(CS02202FB12)
Mika 2007/03/02

GCLK_SEL = FCTSEL1

FCTSEL1
(PIN6)

0=UMA
1 = External

VGA

PIN13 PIN18PIN14

SRCT0 SRCC0 27Mout-NSS 27Mout-SS

PIN17

SRCT1/LCDT_100DOT96C

SRCC1/LCDT_100DOT96T

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Clock Gen

Clock Gen

Clock Gen

Friday, March 02, 2007

Friday, March 02, 2007

Friday, March 02, 2007

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

PROJECT : TA7

PROJECT : TA7

PROJECT : TA7

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

249

249

249

of

of

1

of

2A

2A

2A

5

CPU(HOST)

H_A#[3..16]5

D D

C C

B B

+1.05V_VCCP

A A

H_ADSTB#05
H_REQ#[0..4]5

H_A#[17..35]5

H_ADSTB#15

H_A20M#14

H_FERR#14

H_IGNNE#14
H_STPCLK#14

H_INTR14
H_NMI14
H_SMI#14

H_D#[0..63]5

H_DSTBN#05
H_DSTBP#05
H_DINV#05

H_D#[0..63]5

Layout Note:
Place voltage divider within

0.5" of GTLREF pin

R550

R550
1K/F_4

1K/F_4

R544

R544
2K/F_4

2K/F_4

H_DSTBN#15
H_DSTBP#15
H_DINV#15

R184 *1K_4@NCR184 *1K_4@NC
R185 *1K_4@NCR185 *1K_4@NC

T45T45

T11T11

R547 *0_4@NCR547 *0_4@NC

CPU_MCH_BSEL02,6
CPU_MCH_BSEL12,6
CPU_MCH_BSEL22,6

Layout Note:
Place C close to the CPU_TEST4 pin. Make sure
CPU_TEST4 routing is reference to GND and away
from other noisy signal.

H_A#[3..16]

H_REQ#[0..4]

H_A#[17..35]

H_D#[0..63] H_D#[0..63]

H_D#[0..63]

C682 *0.1U/10V/X5R_4@NCC682 *0.1U/10V/X5R_4@NC

5

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31

H_GTLREF
CPU_TEST1
CPU_TEST2
CPU_TEST3
CPU_TEST4
CPU_TEST5
CPU_TEST6

U30A

U30A

J4

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]#

W3

A[32]#

AA4

A[33]#

AB2

A[34]#

AA3

A[35]#

V1

ADSTB[1]#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD[01]

N5

RSVD[02]

T2

RSVD[03]

V3

RSVD[04]

B2

RSVD[05]

C3

RSVD[06]

D2

RSVD[07]

D22

RSVD[08]

D3

RSVD[09]

F6

RSVD[10]

Merom Ball-out Rev 1a

Merom Ball-out Rev 1a
U30B

U30B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

Merom Ball-out Rev 1a

Merom Ball-out Rev 1a

ADDR GROUP 0 ADDR GROUP 1

ADDR GROUP 0 ADDR GROUP 1

ADS#
BNR#

BPRI#

DEFER#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

CONTROL

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TCK

TDI
TDO
TMS

TRST#

XDP/ITP SIGNALS

XDP/ITP SIGNALS

DBR#

THERMAL

THERMAL

PROCHOT#

THERMDA
THERMDC

ICH

ICH

THERMTRIP#

H CLK

H CLK

BCLK[0]
BCLK[1]

RESERVED

RESERVED

DATA GRP 0

DATA GRP 0

DATA GRP 2DATA GRP 3

DATA GRP 2DATA GRP 3

DSTBN[2]#
DSTBP[2]#

DINV[2]#

DATA GRP 1

DATA GRP 1

DSTBN[3]#
DSTBP[3]#

DINV[3]#

COMP[0]

MISC

MISC

COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#

PWRGOOD

DPWR#

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#

D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#

SLP#

PSI#

H1
E2
G5

H5
F21
E1

F1
D20

B3
H4
C1

F3
F4
G3
G2

G6
E4

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20

D21
A24
B25

C7

A22
A21

4

H_IERR#

H_RESET#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
ITP_DBRESET#

H_PROCHOT#H_PROCHOT#
H_THERMDA
H_THERMDC

H_THERMTRIP_R#

H_D#32

Y22

H_D#33

AB24

H_D#34

V24

H_D#35

V26

H_D#36

V23

H_D#37

T22

H_D#38

U25

H_D#39

U23

H_D#40

Y25

H_D#41

W22

H_D#42

Y23

H_D#43

W24

H_D#44

W25

H_D#45

AA23

H_D#46

AA24

H_D#47

AB25
Y26
AA26
U22

H_D#48

AE24

H_D#49

AD24

H_D#50

AA21

H_D#51

AB22

H_D#52

AB21

H_D#53

AC26

H_D#54

AD20

H_D#55

AE22

H_D#56

AF23

H_D#57

AC25

H_D#58

AE21

H_D#59

AD21

H_D#60

AC22

H_D#61

AD23

H_D#62

AF22

H_D#63

AC23
AE25
AF24
AC20

COMP0

R26

COMP1

U26

COMP2

AA1

COMP3

Y1
E5

B5
D24
D6
D7
AE6

4

R187 56.2/F_4R187 56.2/F_4

T12T12
T10T10
T13T13
T9T9
T8T8
T7T7

R186 56.2/F_4R186 56.2/F_4

R511 0_4R511 0_4
R508 *56.2/F_4R508 *56.2/F_4

CLK_CPU_BCLK 2
CLK_CPU_BCLK# 2

H_D#[0..63]

R548 27.4/F_4R548 27.4/F_4
R549 54.9/F_4R549 54.9/F_4
R31 27.4/F_4R31 27.4/F_4
R30 54.9/F_4R30 54.9/F_4

H_DPRSTP# 6,14,47
H_DPSLP# 14
H_DPWR# 5
H_PWRGOOD 14
H_CPUSLP# 5
H_PSI# 47

H_ADS# 5
H_BNR# 5
H_BPRI# 5

H_DEFER# 5
H_DRDY# 5
H_DBSY# 5

H_BR0# 5

+1.05V_VCCP

H_INIT# 14
H_LOCK# 5
H_RESET# 5

H_RS#0 5
H_RS#1 5
H_RS#2 5
H_TRDY# 5

H_HIT# 5
H_HITM# 5

ITP_DBRESET# 16

H_D#[0..63] 5

H_DSTBN#2 5
H_DSTBP#2 5
H_DINV#2 5

H_D#[0..63] 5

Layout Note:
Comp0,2 connect with Zo=27.4ohm,Comp1,3
connect with Zo=55ohm, make those traces
length shorter than 0.5".Trace should be at
least 25 mils away from any other toggling
signal.

H_DSTBN#3 5
H_DSTBP#3 5
H_DINV#3 5

<check list>
Default PU 56ohm if no
use.Serial R NC
If connect to power side
PU 75ohm.Serial R 2.2K

R191 *330_4@NCR191 *330_4@NC

+1.05V_VCCP

H_THERMTRIP# 6,14

+1.05V_VCCP

Layout Note:
ICH_DPRSTP# need to daisy chain
from ICH8 to IMVP6 to CPU.

2

1 3

Q18

Q18

*MMBT3904_NL@NC

*MMBT3904_NL@NC

3

3

CPU Thermal monitor

THCLK_SMB19
THDAT_SMB19

2N7002W-7-F

2N7002W-7-F

ABCLK16,35,42

2N7002W-7-F

2N7002W-7-F

ABDATA16,35,42

THERM_ALERT#16

2N7002W-7-F

SYS_SHDN#43

+1.05V_VCCP

IMVP6_PROCHOT# 47

2N7002W-7-F

Populate ITP700Flex for bringup

H_RESET#

ITP_TMS

ITP_TDI

ITP_TDO
ITP_TCK
ITP_TRST#

ITP_DBRESET#

R27 *51/F_4R27 *51/F_4

R32 39/F_4R32 39/F_4

R29 150/F_4R29 150/F_4

R33 *51_4@NCR33 *51_4@NC
R35 27/F_4R35 27/F_4
R34 649/F_4R34 649/F_4

R183 150/F_4R183 150/F_4

2

Q47

Q47

2

ABCLK THCLK_SMB

3 1

+3.3V

Q45

Q45

2

ABDATA THDAT_SMB

3 1

+3.3V

2

Q46

Q46

+1.05V_VCCP

3 1

Signal

6648OVERT#

Resistor Value

TDI

39 ohm ± 1%

TMS

500 to 680

TRST#

ohm ± 5%

TCK

27 ohm ± 1%

51 ohm ± 5%

TDO

+3.3V_S5

RESET#

2

22.6 ohm ± 1%
series resistor
and pullup 51
ohm ± 1%.

+3.3V+3.3V

R563

R563

R566

R566

10K_4

10K_4

10K_4

10K_4

R554 *0_4@NCR554 *0_4@NC

Layout Note:
Layout Note:Routing 10:10 mils and
away from noise source with ground
gard

ITP700 layout guidelines

Connect To

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

1

VCC

DXP
DXN
GND

G781P8

G781P8

ADDRESS: 98H

6648VCC

R553

R553

10K_4

10K_4

R565 220_6R565 220_6

R558

R558

*10K_4@NC

*10K_4@NC

8
7
6
4

U34

U34

SCLK
SDA
ALERT#
OVERT#

Resistor Placement

VCCP150 ohm ± 5%

Place the pull-up near CPU

VCCP

Within 200ps of ITP connector

Place the pull-up near CPU

GND

Connect to TCK pin of CPU and then
connect it to FBO pin of ITP connector

GND

in daisy chain. Place the pull-down
near TCK0 pin of ITP connector

Place the pull-up near CPU

VCCP

Connect to CPURST# pin of GMCH through
the series resistor placed within
200ps of ITP connector. Place the

VCCP

pull-up after the series resistor from
ITP connector.

PROJECT : TA7

PROJECT : TA7

PROJECT : TA7

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

CPU(1 of 2)/FAN/Thermal

CPU(1 of 2)/FAN/Thermal

CPU(1 of 2)/FAN/Thermal

Friday, March 02, 2007

Friday, March 02, 2007

Friday, March 02, 2007

1

C693

C693

0.1U/10V/X5R_4

0.1U/10V/X5R_4

1
2
3
5

H_THERMDA

C248

C248
2200P/50V/X7R_6

2200P/50V/X7R_6

H_THERMDC

349

349

349

of

of

of

1A

1A

1A

5

CPU(Power)

All use 10U 4V(+-20%,X6S,0805)Pb-Free.

+VCC_CORE

C107

C107
10U/4V/X6S_8

10U/4V/X6S_8

D D

+VCC_CORE

C169

C169
10U/4V/X6S_8

10U/4V/X6S_8

C621

C621
10U/4V/X6S_8

10U/4V/X6S_8

C153

C153
10U/4V/X6S_8

10U/4V/X6S_8

C626

C626
10U/4V/X6S_8

10U/4V/X6S_8

C640

C640
10U/4V/X6S_8

10U/4V/X6S_8

8 inside cavity, north side, secondary layer.

+VCC_CORE

C132

C84

C84
10U/4V/X6S_8

10U/4V/X6S_8

+VCC_CORE

C131

C C

C131
10U/4V/X6S_8

10U/4V/X6S_8

C75

C75
10U/4V/X6S_8

10U/4V/X6S_8

C120

C120
10U/4V/X6S_8

10U/4V/X6S_8

C132
10U/4V/X6S_8

10U/4V/X6S_8

C58

C58
10U/4V/X6S_8

10U/4V/X6S_8

8 inside cavity, south side, secondary layer.

+VCC_CORE

C110

C108

C108
10U/4V/X6S_8

10U/4V/X6S_8

C110
10U/4V/X6S_8

10U/4V/X6S_8

C57

C57
10U/4V/X6S_8

10U/4V/X6S_8

6 inside cavity, north side, primary layer.

+VCC_CORE

C625

C620

C620
10U/4V/X6S_8

10U/4V/X6S_8

B B

6 inside cavity, south side, primary layer.

C625
10U/4V/X6S_8

10U/4V/X6S_8

C629

C629
10U/4V/X6S_8

10U/4V/X6S_8

C630

C630
10U/4V/X6S_8

10U/4V/X6S_8

C645

C645
10U/4V/X6S_8

10U/4V/X6S_8

C121

C121
10U/4V/X6S_8

10U/4V/X6S_8

C168

C168
10U/4V/X6S_8

10U/4V/X6S_8

C74

C74
10U/4V/X6S_8

10U/4V/X6S_8

C633

C633
10U/4V/X6S_8

10U/4V/X6S_8

C83

C83
10U/4V/X6S_8

10U/4V/X6S_8

C639

C639
10U/4V/X6S_8

10U/4V/X6S_8

C634

C634
10U/4V/X6S_8

10U/4V/X6S_8

C111

C111
10U/4V/X6S_8

10U/4V/X6S_8

C99

C99
10U/4V/X6S_8

10U/4V/X6S_8

C152

C152
10U/4V/X6S_8

10U/4V/X6S_8

C98

C98
10U/4V/X6S_8

10U/4V/X6S_8

C644

C644
10U/4V/X6S_8

10U/4V/X6S_8

4

+VCC_CORE

U30C

U30C

A7

VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[01]
VCCA[02]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

A9
A10
A12
A13
A15
A17
A18
A20

B7

B9
B10
B12
B14
B15
B17
B18
B20

C9
C10
C12
C13
C15
C17
C18

D9
D10
D12
D14
D15
D17
D18

E7

E9
E10
E12
E13
E15
E17
E18
E20

F7

F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9

AA10
AA12
AA13
AA15
AA17
AA18
AA20

AB9

AC10
AB10
AB12
AB14
AB15
AB17
AB18

Merom Ball-out Rev 1a

Merom Ball-out Rev 1a

3

<REV.NO. 0.5/REF.NO.19343>
Ivcc Max 52A
Ivccp Max 6A(VCCP supply before Vcc stable)
Max 2A(VCCP supply after Vcc stable)
Ivcca Max 130mA

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

AF7

AE7

.

.

Layout Note:
Route VCCSENSE and VSSSENSE
traces at 27.4ohms and length
matched to within 25 mil. Place PU
and PD within 2 inch of CPU.

+1.05V_VCCP

C56

C56

C173

C173

C55

0.1U/10V/X5R_4

0.1U/10V/X5R_4

+VCC_CORE

C55

0.1U/10V/X5R_4

0.1U/10V/X5R_4

+1.05V_VCCP

12

+

+

C31

C31
220U/4V_7343

220U/4V_7343

0.01U/16V/X7R_4

0.01U/16V/X7R_4

R497

R497
100/F_6

100/F_6

R490

R490
100/F_6

100/F_6

0.1U/10V/X5R_4

0.1U/10V/X5R_4

Layout out:
Place these inside socket cavity on North side secondary.

VID0 47
VID1 47
VID2 47
VID3 47
VID4 47
VID5 47
VID6 47

C175

C175

0.1U/10V/X5R_4

0.1U/10V/X5R_4

C683

C683

2

C54

C54

0.1U/10V/X5R_4

0.1U/10V/X5R_4

+1.5V

C681

C681
10U/6.3V/X5R_8

10U/6.3V/X5R_8

C176

C176

0.1U/10V/X5R_4

0.1U/10V/X5R_4

Layout Note:
Place C2549 near PIN B26.

VCCSENSE 47

VSSSENSE 47

1

U30D

U30D

A4

VSS[001]

A8

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

B6

VSS[009]

B8

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

C5

VSS[017]

C8

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

C2

VSS[023]

C22

VSS[024]

C25

VSS[025]

D1

VSS[026]

D4

VSS[027]

D8

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

E3

VSS[035]

E6

VSS[036]

E8

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

F5

VSS[044]

F8

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

F2

VSS[050]

F22

VSS[051]

F25

VSS[052]

G4

VSS[053]

G1

VSS[054]

G23

VSS[055]

G26

VSS[056]

H3

VSS[057]

H6

VSS[058]

H21

VSS[059]

H24

VSS[060]

J2

VSS[061]

J5

VSS[062]

J22

VSS[063]

J25

VSS[064]

K1

VSS[065]

K4

VSS[066]

K23

VSS[067]

K26

VSS[068]

L3

VSS[069]

L6

VSS[070]

L21

VSS[071]

L24

VSS[072]

M2

VSS[073]

M5

VSS[074]

M22

VSS[075]

M25

VSS[076]

N1

VSS[077]

N4

VSS[078]

N23

VSS[079]

N26

VSS[080]
VSS[081]P3VSS[162]

Merom Ball-out Rev 1a

Merom Ball-out Rev 1a

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]

VSS[163]

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

.

.

A A

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

CPU(2 of 2)

CPU(2 of 2)

CPU(2 of 2)

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

PROJECT : TA7

PROJECT : TA7

PROJECT : TA7

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

449Friday, March 02, 2007

449Friday, March 02, 2007

449Friday, March 02, 2007

of

of

1

of

1A

1A

1A

NB(HOST)

5

4

3

2

1

D D

H_D#[0..63]3

+1.05V_VCCP

R74

R74

221/F_4

221/F_4

H_SWING

C73

+1.05V_VCCP

R530

R530

54.9/F_4

54.9/F_4

H_SCOMP
H_SCOMP#

H_RCOMP

R83

R83

24.9/F_4

24.9/F_4

C73

Layout Note:

0.1U close to B3

0.1U/10V/X5R_4

0.1U/10V/X5R_4

Layout Note:
Impedance 55ohm

Layout Note:
10:20 mils(Width:Spacing)

+1.05V_VCCP

R62

R62
1K/F_4

1K/F_4

R61

R61

C48

C48

2K/F_4

2K/F_4

0.1U/10V/X5R_4

0.1U/10V/X5R_4

H_RESET#3
H_CPUSLP#3

H_REF

Layout Note:
Place the 0.1 uF
decoupling capacitor
within 100 mils from
GMCH pins.

R80

R80

100/F_4

100/F_4

C C

R531

R531

54.9/F_4

54.9/F_4

B B

H_D#[0..63]

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_SWING
H_RCOMP

H_SCOMP
H_SCOMP#

U32A

U32A

E2

H_D#_0

G2

H_D#_1

G7

H_D#_2

M6

H_D#_3

H7

H_D#_4

H3

H_D#_5

G4

H_D#_6

F3

H_D#_7

N8

H_D#_8

H2

H_D#_9

M10

H_D#_10

N12

H_D#_11

N9

H_D#_12

H5

H_D#_13

P13

H_D#_14

K9

H_D#_15

M2

H_D#_16

W10

H_D#_17

Y8

H_D#_18

V4

H_D#_19

M3

H_D#_20

J1

H_D#_21

N5

H_D#_22

N3

H_D#_23

W6

H_D#_24

W9

H_D#_25

N2

H_D#_26

Y7

H_D#_27

Y9

H_D#_28

P4

H_D#_29

W3

H_D#_30

N1

H_D#_31

AD12

H_D#_32

AE3

H_D#_33

AD9

H_D#_34

AC9

H_D#_35

AC7

H_D#_36

AC14

H_D#_37

AD11

H_D#_38

AC11

H_D#_39

AB2

H_D#_40

AD7

H_D#_41

AB1

H_D#_42

Y3

H_D#_43

AC6

H_D#_44

AE2

H_D#_45

AC5

H_D#_46

AG3

H_D#_47

AJ9

H_D#_48

AH8

H_D#_49

AJ14

H_D#_50

AE9

H_D#_51

AE11

H_D#_52

AH12

H_D#_53

AJ5

H_D#_54

AH5

H_D#_55

AJ6

H_D#_56

AE7

H_D#_57

AJ7

H_D#_58

AJ2

H_D#_59

AE5

H_D#_60

AJ3

H_D#_61

AH2

H_D#_62

AH13

H_D#_63

B3

H_SWING

C2

H_RCOMP

W1

H_SCOMP

W2

H_SCOMP#

B6

H_CPURST#

E5

H_CPUSLP#

B9

H_AVREF

A9

H_DVREF

IC(1299P) PM965 QN14 B0(UFCBGA)

IC(1299P) PM965 QN14 B0(UFCBGA)

HOST

HOST

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#
H_ADSTB#_0
H_ADSTB#_1

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HIT#

H_HITM#
H_LOCK#
H_TRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1

H_REQ#_2
H_REQ#_3

H_REQ#_4

H_RS#_0

H_RS#_1

H_RS#_2

J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19

G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7

K5
L2
AD13
AE13

M7
K3
AD2
AH11

L7
K2
AC2
AJ10

M14
E13
A11
H13
B12

E12
D7
D8

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_A#[3..35]

H_ADS# 3
H_ADSTB#0 3
H_ADSTB#1 3
H_BNR# 3
H_BPRI# 3
H_BR0# 3
H_DEFER# 3
H_DBSY# 3
CLK_MCH_BCLK 2
CLK_MCH_BCLK# 2
H_DPWR# 3
H_DRDY# 3
H_HIT# 3
H_HITM# 3
H_LOCK# 3
H_TRDY# 3

H_DINV#0 3
H_DINV#1 3
H_DINV#2 3
H_DINV#3 3

H_DSTBN#0 3
H_DSTBN#1 3
H_DSTBN#2 3
H_DSTBN#3 3

H_DSTBP#0 3
H_DSTBP#1 3
H_DSTBP#2 3
H_DSTBP#3 3

H_REQ#0 3
H_REQ#1 3
H_REQ#2 3
H_REQ#3 3
H_REQ#4 3

H_RS#0 3
H_RS#1 3
H_RS#2 3

H_A#[3..35] 3

A A

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

GMCH HOST(1 of 6)

GMCH HOST(1 of 6)

GMCH HOST(1 of 6)

Friday, March 02, 2007

Friday, March 02, 2007

Friday, March 02, 2007

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

PROJECT : TA7

PROJECT : TA7

PROJECT : TA7

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

549

549

549

of

of

1

of

1A

1A

1A

+1.8V_SUS

SM_RCOMP_VOH

R199

R199

3.01K/F_4

3.01K/F_4

0.01U/16V/X7R_4

0.01U/16V/X7R_4

D D

C C

B B

A A

SM_RCOMP_VOL

R200

R200
1K/F_4

1K/F_4

0.01U/16V/X7R_4

0.01U/16V/X7R_4

+3.3V

R489 10K_4R489 10K_4
R51 10K_4R51 10K_4

+1.05V_VCCP

CPU_MCH_BSEL02,3
CPU_MCH_BSEL12,3
CPU_MCH_BSEL22,3

MCH_CFG_511

MCH_CFG_911

MCH_CFG_1211
MCH_CFG_1311

MCH_CFG_1611

MCH_CFG_1911
MCH_CFG_2011

PM_BMBUSY#16
H_DPRSTP#3,14,47
PM_EXTTS#012,13
PM_EXTTS#112,13
DELAY_VR_PG16,47
PLTRST#_NB15
H_THERMTRIP#3,14
PM_DPRSLPVR16,47

DREF_SSCLK
DREF_SSCLK#

MCH_DREFCLK
MCH_DREFCLK#

<design guide>
If no use DREFCLK and DREFCLK# PD

5

R198

R198
1K/F_4

1K/F_4

12

C272

C272

C276

C276

Santa Rosa Platform MOW WW15
For 4Gb DRAM support,
change Pin-BJ29 to DDR_A_MA14,
change Pin-BE24 to DDR_B_MA14.

R146

R146

R189 0_4@EVR189 0_4@EV
R188 10K_4R188 10K_4

R265 0_4@EVR265 0_4@EV
R264 10K_4R264 10K_4

12

CRESTLINE
new pin
define

PM_EXTTS#0
PM_EXTTS#1

THRMTRIP#_GMCH

*56.2/F_4@NC

*56.2/F_4@NC

R552 0_4R552 0_4
R192 100_4R192 100_4
R150 0_4R150 0_4
R116 0_4R116 0_4

5

C275

C275

2.2U/10V/X5R_8

2.2U/10V/X5R_8

C286

C286

2.2U/10V/X5R_8

2.2U/10V/X5R_8

T125T125
T19T19

T20T20
T119T119

T37T37
T16T16
T23T23

T38T38
T27T27

T17T17
T30T30

T36T36
T29T29

T143T143
T145T145
T151T151
T150T150
T149T149
T146T146
T147T147
T142T142
T141T141
T128T128
T118T118
T129T129
T124T124
T99T99
T100T100
T144T144

+1.05V_VCCP

MCH_CFG_3
MCH_CFG_4

MCH_CFG_6
MCH_CFG_7
MCH_CFG_8

MCH_CFG_10
MCH_CFG_11

MCH_CFG_14
MCH_CFG_15

MCH_CFG_17
MCH_CFG_18

PM_BMBUSY#
PM_EXTTS#0

PM_EXTTS#1

PLTRST#_R

THRMTRIP#_GMCH
PM_DPRSLPVR_GMCH

UMA & Discrete setting

CRT Discrete / UMA

--------------------­R189 0 NC
R188 10K NC
R265 0 NC
R264 10K NC

TP_NC1
TP_NC2
TP_NC3
TP_NC4
TP_NC5
TP_NC6
TP_NC7
TP_NC8
TP_NC9
TP_NC10
TP_NC11
TP_NC12
TP_NC13
TP_NC14
TP_NC15
TP_NC16

U32B

U32B

P36

RSVD1

P37

RSVD2

R35

RSVD3

N35

RSVD4

AR12

RSVD5

AR13

RSVD6

AM12

RSVD7

AN13

RSVD8

J12

RSVD9

AR37

RSVD10

AM36

RSVD11

AL36

RSVD12

AM37

RSVD13

D20

RSVD14

H10

RSVD20

B51

RSVD21

BJ20

RSVD22

BK22

RSVD23

BF19

RSVD24

BH20

RSVD25

BK18

RSVD26

BJ18

RSVD27

BF23

RSVD28

BG23

RSVD29

BC23

RSVD30

BD24

RSVD31

BJ29

RSVD32

BE24

RSVD33

BH39

RSVD34

AW20

RSVD35

BK20

RSVD36

C48

RSVD37

D47

RSVD38

B44

RSVD39

C44

RSVD40

A35

RSVD41

B37

RSVD42

B36

RSVD43

B34

RSVD44

C34

RSVD45

P27

CFG_0

N27

CFG_1

N24

CFG_2

C21

CFG_3

C23

CFG_4

F23

CFG_5

N23

CFG_6

G23

CFG_7

J20

CFG_8

C20

CFG_9

R24

CFG_10

L23

CFG_11

J23

CFG_12

E23

CFG_13

E20

CFG_14

K23

CFG_15

M20

CFG_16

M24

CFG_17

L32

CFG_18

N33

CFG_19

L35

CFG_20

G41

PM_BM_BUSY#

L39

PM_DPRSTP#

L36

PM_EXT_TS#_0

J36

PM_EXT_TS#_1

AW49

PWROK

AV20

RSTIN#

N20

THERMTRIP#

G36

DPRSLPVR

BJ51

NC_1

BK51

NC_2

BK50

NC_3

BL50

NC_4

BL49

NC_5

BL3

NC_6

BL2

NC_7

BK1

NC_8

BJ1

NC_9

E1

NC_10

A5

NC_11

C51

NC_12

B50

NC_13

A50

NC_14

A49

NC_15

BK2

NC_16

IC(1299P) PM965 QN14 B0(UFCBGA)

IC(1299P) PM965 QN14 B0(UFCBGA)

4

SM_CK_0
SM_CK_1
SM_CK_3
SM_CK_4

SM_CK#_0
SM_CK#_1
SM_CK#_3

SM_CK#_4
SM_CKE_0

SM_CKE_1
SM_CKE_3
SM_CKE_4

SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3

SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3

SM_RCOMP

SM_RCOMP#

SM_RCOMP_VOH
SM_RCOMP_VOL

SM_VREF_0

DDR MUXINGCLK

DDR MUXINGCLK

SM_VREF_1

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK

PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2

CFGRSVD

CFGRSVD

PM

PM

NC

NC

DMI_TXN_3
DMI_TXP_0

DMI_TXP_1

DMI

DMI

DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3

GFX_VR_EN

GRAPHICS VID

GRAPHICS VID

CL_CLK

CL_DATA

CL_PWROK

CL_RST#

CL_VREF

ME

ME

SDVO_CTRL_CLK

SDVO_CTRL_DATA

CLK_REQ#

ICH_SYNC#

MISC

MISC

TEST_1
TEST_2

4

UMA & Discrete setting

AV29
BB23
BA25
AV23

AW30
BA23
AW25
AW23

BE29
AY32
BD39
BG37

BG20
BK16
BG16
BE13

BH18
BJ15
BJ14
BE16

SMRCOMPP

BL15

SMRCOMPN

BK14

SM_RCOMP_VOH

BK31

SM_RCOMP_VOL

BL31
AR49

AW4

C244 0.1U/10V/X7R_4C244 0.1U/10V/X7R_4
C252 0.1U/10V/X7R_4C252 0.1U/10V/X7R_4

MCH_DREFCLK

B42

MCH_DREFCLK#

C42

DREF_SSCLK

H48

DREF_SSCLK#

H47
K44

K45

AN47
AJ38
AN42
AN46

AM47
AJ39
AN41
AN45

AJ46
AJ41
AM40
AM44

AJ47
AJ42
AM39
AM43

E35

T15T15

A39

T105T105

C38

T116T116

B39

T115T115

E36

T108T108

AM49
AK50
AT43
AN49

MCH_CLVREF

AM50

SDVO_CTRLCLK

H35

SDVO_CTRLDATA

K36

CLK_3GPLLREQ#

G39
G40

GMCH_TEST1

A37

GMCH_TEST2

R32

M_CLK_DDR0 13
M_CLK_DDR1 13
M_CLK_DDR3 13
M_CLK_DDR4 13

M_CLK_DDR#0 13
M_CLK_DDR#1 13
M_CLK_DDR#3 13
M_CLK_DDR#4 13

DDR_CKE0_DIMMA 12,13
DDR_CKE1_DIMMA 12,13
DDR_CKE3_DIMMB 12,13
DDR_CKE4_DIMMB 12,13

DDR_CS0_DIMMA# 12,13
DDR_CS1_DIMMA# 12,13
DDR_CS2_DIMMB# 12,13
DDR_CS3_DIMMB# 12,13

M_ODT0 12,13
M_ODT1 12,13
M_ODT2 12,13
M_ODT3 12,13

V_DDR_MCH_REF

MCH_DREFCLK 2
MCH_DREFCLK# 2
DREF_SSCLK 2
DREF_SSCLK# 2

CLK_MCH_3GPLL 2
CLK_MCH_3GPLL# 2

DMI_MRX_ITX_N0 15
DMI_MRX_ITX_N1 15
DMI_MRX_ITX_N2 15
DMI_MRX_ITX_N3 15

DMI_MRX_ITX_P0 15
DMI_MRX_ITX_P1 15
DMI_MRX_ITX_P2 15
DMI_MRX_ITX_P3 15

DMI_MTX_IRX_N0 15
DMI_MTX_IRX_N1 15
DMI_MTX_IRX_N2 15
DMI_MTX_IRX_N3 15

DMI_MTX_IRX_P0 15
DMI_MTX_IRX_P1 15
DMI_MTX_IRX_P2 15
DMI_MTX_IRX_P3 15

HSYNC_COM19,25
VSYNC_COM19,25

CL_CLK0 16

CL_DATA0 16
ICH_CL_PWROK 16,40
ICH_CL_RST0# 16

R132 0_4R132 0_4
R127 0_4R127 0_4

CLK_3GPLLREQ# 2

MCH_ICH_SYNC# 16

R506 0_4R506 0_4
R156 20K_4R156 20K_4

L_CTRL_CLK
L_CTRL_DATA
INT_CRT_DDCCLK
INT_CRT_DDCDAT
INT_LVDS_EDIDCLK
INT_LVDS_EDIDDATA

3

LVDS Discrete / UMA
R49 NC 10K
R48 NC 10K

INT_LVDS_BLON24

+1.8V_SUS

R194

R194
20/F_4

20/F_4

R195

R195
20/F_4

20/F_4

+3.3V

DDCCLK_COM19,25
DDCDATA_COM19,25

R484 *0_4@IVR484 *0_4@IV
R485 *0_4@IVR485 *0_4@IV

Layout Note:
HSYNC/VSYNC serial R
place close to NB

C674

C674

0.1U/10V/X5R_4

0.1U/10V/X5R_4

UMA & Discrete setting

LVDS/CRT Discrete / UMA

--------------------------­R488 0 NC
R487 0 NC
R64 0 NC
R65 0 NC
R50 0 NC
R96 0 NC

R488 0_4@EVR488 0_4@EV
R487 0_4@EVR487 0_4@EV
R64 0_4@EVR64 0_4@EV
R65 0_4@EVR65 0_4@EV
R50 0_4@EVR50 0_4@EV
R96 0_4@EVR96 0_4@EV

3

INT_BKLT_CTRL24

*10K_4@IV

*10K_4@IV

R49

R49

+3.3V

R48 *10K_4@IVR48 *10K_4@IV

INT_LVDS_EDIDCLK24
INT_LVDS_EDIDDATA24

INT_LVDS_DIGON24

R142 *2.4K_4@IVR142 *2.4K_4@IV
R140 *0_4@IVR140 *0_4@IV

INT_TXLCLKOUT-24
INT_TXLCLKOUT+24

INT_TXLOUT0-24
INT_TXLOUT1-24
INT_TXLOUT2-24

INT_TXLOUT0+24
INT_TXLOUT1+24
INT_TXLOUT2+24

UMA & Discrete setting

LVDS Discrete / UMA

-------------------------­R142 NC 2.4K
R140 NC 0

CRT Discrete / UMA

---------------------­L73 NC STUFF
L72 NC STUFF
L74 NC STUFF

R43 *2.2K_4R43 *2.2K_4
R46 *2.2K_4R46 *2.2K_4

R44 0_4@EVR44 0_4@EV
R45 0_4@EVR45 0_4@EV

L73

L73
*LQG18HN68NJ00D@IV

*LQG18HN68NJ00D@IV
L72

L72
*LQG18HN68NJ00D@IV

*LQG18HN68NJ00D@IV
L74

L74
*LQG18HN68NJ00D@IV

*LQG18HN68NJ00D@IV

R81 *0_4@IVR81 *0_4@IV
R82 *0_4@IVR82 *0_4@IV

HSYNC2

R77 *30_4@IVR77 *30_4@IV

R105 0_4@EVR105 0_4@EV

VSYNC2

R78 *30_4@IVR78 *30_4@IV

iAMT

+1.25V_M

R545

R545
1K/F_4

1K/F_4

add R773 R774 R775

12

Mika 2006/11/30

R540

R540
392/F_4

392/F_4

L_CTRL_CLK

L_CTRL_DATA
INT_LVDS_EDIDCLK
INT_LVDS_EDIDDATA

LVDS_IBG

T31T31

T14T14
T26T26

T25T25
T117T117
T120T120

T21T21
T106T106
T107T107

R774

R774
75/F_4

75/F_4

R773

R773
75/F_4

75/F_4

R775

R775
75/F_4

75/F_4

TV_DCONSEL_0

TV_DCONSEL_1

INT_CRT_BLU_1INT_CRT_BLU_2
INT_CRT_GRN_1INT_CRT_GRN_2
INT_CRT_RED_1INT_CRT_RED_2

INT_CRT_DDCCLKINT_CRT_DDCCLK
INT_CRT_DDCDATINT_CRT_DDCDAT

HSYNC1

CRTIREF

VSYNC1

UMA & Discrete setting

CRT Discrete / UMA

--------------------­R105 0 1.3K/F
R77 NC 30
R78 NC 30
R81 NC 0
R82 NC 0
R484 NC 0
R485 NC 0

External VGA with @EV part,
Internal VGA with @IV part.

Layout Note:
Place 150 ohm
termination resistors
close to GMCH.

R111 0_4@EVR111 0_4@EV
R101 0_4@EVR101 0_4@EV

R117 0_4@EVR117 0_4@EV
R125 0_4@EVR125 0_4@EV
R110 0_4@EVR110 0_4@EV

2

U32C

U32C

J40

L_BKLT_CTRL

H39

L_BKLT_EN

E39

L_CTRL_CLK

E40

L_CTRL_DATA

C37

L_DDC_CLK

D35

L_DDC_DATA

K40

L_VDD_EN

L41

LVDS_IBG

L43

LVDS_VBG

N41

LVDS_VREFH

N40

LVDS_VREFL

D46

LVDSA_CLK#

C45

LVDSA_CLK

D44

LVDSB_CLK#

E42

LVDSB_CLK

G51

LVDSA_DATA#_0

E51

LVDSA_DATA#_1

F49

LVDSA_DATA#_2

G50

LVDSA_DATA_0

E50

LVDSA_DATA_1

F48

LVDSA_DATA_2

G44

LVDSB_DATA#_0

B47

LVDSB_DATA#_1

B45

LVDSB_DATA#_2

E44

LVDSB_DATA_0

A47

LVDSB_DATA_1

A45

LVDSB_DATA_2

E27

TVA_DAC

G27

TVB_DAC

K27

TVC_DAC

F27

TVA_RTN

J27

TVB_RTN

L27

TVC_RTN

M35

TV_DCONSEL_0

P33

TV_DCONSEL_1

H32

CRT_BLUE

G32

CRT_BLUE#

K29

CRT_GREEN

J29

CRT_GREEN#

F29

CRT_RED

E29

CRT_RED#

K33

CRT_DDC_CLK

G35

CRT_DDC_DATA

F33

CRT_HSYNC

C32

CRT_TVO_IREF

E33

CRT_VSYNC

IC(1299P) PM965 QN14 B0(UFCBGA)

IC(1299P) PM965 QN14 B0(UFCBGA)

CRT_B_COM19,25
CRT_G_COM19,25
CRT_R_COM19,25

UMA & Discrete setting

CRT Discrete / UMA

--------------------­R111 0 NC
R101 0 NC
R117 0 150
R125 0 150
R110 0 150

HSYNC1
VSYNC1

INT_CRT_BLU_1
INT_CRT_GRN_1
INT_CRT_RED_1

2

EXP_A_COMPX

N43

PEG_COMPI

PEG_COMPO

LVDS

LVDS

TV VGA

TV VGA

CRT Discrete / UMA

---------------------­R52 NC 0
R53 NC 0
R54 NC 0

PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PCI-EXPRESS GRAPHICS

PCI-EXPRESS GRAPHICS

R52 *0_4@IVR52 *0_4@IV
R53 *0_4@IVR53 *0_4@IV
R54 *0_4@IVR54 *0_4@IV

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

M43

PEG_RXN0

J51

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9

PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

GMCH DMI/VIDEO(2 of 6)

GMCH DMI/VIDEO(2 of 6)

GMCH DMI/VIDEO(2 of 6)

Friday, March 02, 2007

Friday, March 02, 2007

Friday, March 02, 2007

PEG_RXN1

L51

PEG_RXN2

N47

PEG_RXN3

T45

PEG_RXN4

T50

PEG_RXN5

U40

PEG_RXN6

Y44

PEG_RXN7

Y40

PEG_RXN8

AB51

PEG_RXN9

W49

PEG_RXN10

AD44

PEG_RXN11

AD40

PEG_RXN12

AG46

PEG_RXN13

AH49

PEG_RXN14

AG45

PEG_RXN15

AG41

PEG_RXP0

J50

PEG_RXP1

L50

PEG_RXP2

M47

PEG_RXP3

U44

PEG_RXP4

T49

PEG_RXP5

T41

PEG_RXP6

W45

PEG_RXP7

W41

PEG_RXP8

AB50

PEG_RXP9

Y48

PEG_RXP10

AC45

PEG_RXP11

AC41

PEG_RXP12

AH47

PEG_RXP13

AG49

PEG_RXP14

AH45

PEG_RXP15

AG42

C_PEG_TXN0

N45

C_PEG_TXN1

U39

C_PEG_TXN2

U47

C_PEG_TXN3

N51

C_PEG_TXN4

R50

C_PEG_TXN5

T42

C_PEG_TXN6

Y43

C_PEG_TXN7

W46

C_PEG_TXN8

W38

C_PEG_TXN9

AD39

C_PEG_TXN10

AC46

C_PEG_TXN11

AC49

C_PEG_TXN12

AC42

C_PEG_TXN13

AH39

C_PEG_TXN14

AE49

C_PEG_TXN15

AH44

C_PEG_TXP0

M45

C_PEG_TXP1

T38

C_PEG_TXP2

T46

C_PEG_TXP3

N50

C_PEG_TXP4

R51

C_PEG_TXP5

U43

C_PEG_TXP6

W42

C_PEG_TXP7

Y47

C_PEG_TXP8

Y39

C_PEG_TXP9

AC38

C_PEG_TXP10

AD47

C_PEG_TXP11

AC50

C_PEG_TXP12

AD43

C_PEG_TXP13

AG39

C_PEG_TXP14

AE50

C_PEG_TXP15

AH43

INT_CRT_BLU_2
INT_CRT_GRN_2
INT_CRT_RED_2

PEG_TXN[15:0]18

PROJECT : TA7

PROJECT : TA7

PROJECT : TA7

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

1

R147 24.9/F_4R147 24.9/F_4

PEG_RXN[15:0] 18

PEG_RXP[15:0] 18

C123 0.1U/10V/X5R_4@EVC123 0.1U/10V/X5R_4@EV
C635 0.1U/10V/X5R_4@EVC635 0.1U/10V/X5R_4@EV
C133 0.1U/10V/X5R_4@EVC133 0.1U/10V/X5R_4@EV
C641 0.1U/10V/X5R_4@EVC641 0.1U/10V/X5R_4@EV
C154 0.1U/10V/X5R_4@EVC154 0.1U/10V/X5R_4@EV
C646 0.1U/10V/X5R_4@EVC646 0.1U/10V/X5R_4@EV
C188 0.1U/10V/X5R_4@EVC188 0.1U/10V/X5R_4@EV
C651 0.1U/10V/X5R_4@EVC651 0.1U/10V/X5R_4@EV
C165 0.1U/10V/X5R_4@EVC165 0.1U/10V/X5R_4@EV
C656 0.1U/10V/X5R_4@EVC656 0.1U/10V/X5R_4@EV
C218 0.1U/10V/X5R_4@EVC218 0.1U/10V/X5R_4@EV
C660 0.1U/10V/X5R_4@EVC660 0.1U/10V/X5R_4@EV
C207 0.1U/10V/X5R_4@EVC207 0.1U/10V/X5R_4@EV
C667 0.1U/10V/X5R_4@EVC667 0.1U/10V/X5R_4@EV
C225 0.1U/10V/X5R_4@EVC225 0.1U/10V/X5R_4@EV
C672 0.1U/10V/X5R_4@EVC672 0.1U/10V/X5R_4@EV

C112 0.1U/10V/X5R_4@EVC112 0.1U/10V/X5R_4@EV
C631 0.1U/10V/X5R_4@EVC631 0.1U/10V/X5R_4@EV
C129 0.1U/10V/X5R_4@EVC129 0.1U/10V/X5R_4@EV
C637 0.1U/10V/X5R_4@EVC637 0.1U/10V/X5R_4@EV
C145 0.1U/10V/X5R_4@EVC145 0.1U/10V/X5R_4@EV
C642 0.1U/10V/X5R_4@EVC642 0.1U/10V/X5R_4@EV
C185 0.1U/10V/X5R_4@EVC185 0.1U/10V/X5R_4@EV
C648 0.1U/10V/X5R_4@EVC648 0.1U/10V/X5R_4@EV
C171 0.1U/10V/X5R_4@EVC171 0.1U/10V/X5R_4@EV
C654 0.1U/10V/X5R_4@EVC654 0.1U/10V/X5R_4@EV
C215 0.1U/10V/X5R_4@EVC215 0.1U/10V/X5R_4@EV
C659 0.1U/10V/X5R_4@EVC659 0.1U/10V/X5R_4@EV
C198 0.1U/10V/X5R_4@EVC198 0.1U/10V/X5R_4@EV
C664 0.1U/10V/X5R_4@EVC664 0.1U/10V/X5R_4@EV
C231 0.1U/10V/X5R_4@EVC231 0.1U/10V/X5R_4@EV
C668 0.1U/10V/X5R_4@EVC668 0.1U/10V/X5R_4@EV

UMA & Discrete setting
UMA NC

PEG_TXP[15:0]18

PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15

649

649

649

1

+VCC_PEG

PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15

of

of

of

2A

2A

2A

5

4

3

2

1

NB(Memory controller)

D D

DDR_A_D[0..63]13 DDR_B_D[0..63]13

C C

B B

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

U32D

U32D

AR43

SA_DQ_0

AW44

SA_DQ_1

BA45

SA_DQ_2

AY46

SA_DQ_3

AR41

SA_DQ_4

AR45

SA_DQ_5

AT42

SA_DQ_6

AW47

SA_DQ_7

BB45

SA_DQ_8

BF48

SA_DQ_9

BG47

SA_DQ_10

BJ45

SA_DQ_11

BB47

SA_DQ_12

BG50

SA_DQ_13

BH49

SA_DQ_14

BE45

SA_DQ_15

AW43

SA_DQ_16

BE44

SA_DQ_17

BG42

SA_DQ_18

BE40

SA_DQ_19

BF44

SA_DQ_20

BH45

SA_DQ_21

BG40

SA_DQ_22

BF40

SA_DQ_23

AR40

SA_DQ_24

AW40

SA_DQ_25

AT39

SA_DQ_26

AW36

SA_DQ_27

AW41

SA_DQ_28

AY41

SA_DQ_29

AV38

SA_DQ_30

AT38

SA_DQ_31

AV13

SA_DQ_32

AT13

SA_DQ_33

AW11

SA_DQ_34

AV11

SA_DQ_35

AU15

SA_DQ_36

AT11

SA_DQ_37

BA13

SA_DQ_38

BA11

SA_DQ_39

BE10

SA_DQ_40

BD10

SA_DQ_41

BD8

SA_DQ_42

AY9

SA_DQ_43

BG10

SA_DQ_44

AW9

SA_DQ_45

BD7

SA_DQ_46

BB9

SA_DQ_47

BB5

SA_DQ_48

AY7

SA_DQ_49

AT5

SA_DQ_50

AT7

SA_DQ_51

AY6

SA_DQ_52

BB7

SA_DQ_53

AR5

SA_DQ_54

AR8

SA_DQ_55

AR9

SA_DQ_56

AN3

SA_DQ_57

AM8

SA_DQ_58

AN10

SA_DQ_59

AT9

SA_DQ_60

AN9

SA_DQ_61

AM9

SA_DQ_62

AN11

SA_DQ_63

IC(1299P) PM965 QN14 B0(UFCBGA)

IC(1299P) PM965 QN14 B0(UFCBGA)

DDR_A_BS0

BB19

SA_BS_0
SA_BS_1
SA_BS_2

SA_CAS#

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6

SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13

SA_RAS#

SA_RCVEN#

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_WE#

BK19
BF29

BL17
AT45

BD44
BD42
AW38
AW13
BG8
AY5
AN6

AT46
BE48
BB43
BC37
BB16
BH6
BB2
AP3
AT47
BD47
BC41
BA37
BA16
BH7
BC1
AP2

BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16

BE18
AY20

BA19

DDR_A_BS1
DDR_A_BS2

DDR_A_CAS#
DDR_A_DM0

DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

DDR_A_RAS#

DDR_A_WE#

DDR_A_BS0 12,13
DDR_A_BS1 12,13
DDR_A_BS2 12,13

DDR_A_CAS# 12,13 DDR_B_CAS# 12,13
DDR_A_DM[0..7] 13

DDR_A_DQS[0..7] 13

DDR_A_DQS#[0..7] 13

DDR_A_MA[0..13] 12,13 DDR_B_MA[0..13] 12,13

DDR_A_RAS# 12,13

T47T47

DDR_A_WE# 12,13

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

U32E

U32E

AP49

SB_DQ_0

AR51

SB_DQ_1

AW50

SB_DQ_2

AW51

SB_DQ_3

AN51

SB_DQ_4

AN50

SB_DQ_5

AV50

SB_DQ_6

AV49

SB_DQ_7

BA50

SB_DQ_8

BB50

SB_DQ_9

BA49

SB_DQ_10

BE50

SB_DQ_11

BA51

SB_DQ_12

AY49

SB_DQ_13

BF50

SB_DQ_14

BF49

SB_DQ_15

BJ50

SB_DQ_16

BJ44

SB_DQ_17

BJ43

SB_DQ_18

BL43

SB_DQ_19

BK47

SB_DQ_20

BK49

SB_DQ_21

BK43

SB_DQ_22

BK42

SB_DQ_23

BJ41

SB_DQ_24

BL41

SB_DQ_25

BJ37

SB_DQ_26

BJ36

SB_DQ_27

BK41

SB_DQ_28

BJ40

SB_DQ_29

BL35

SB_DQ_30

BK37

SB_DQ_31

BK13

SB_DQ_32

BE11

SB_DQ_33

BK11

SB_DQ_34

BC11

SB_DQ_35

BC13

SB_DQ_36

BE12

SB_DQ_37

BC12

SB_DQ_38

BG12

SB_DQ_39

BJ10

SB_DQ_40

BL9

SB_DQ_41

BK5

SB_DQ_42

BL5

SB_DQ_43

BK9

SB_DQ_44

BK10

SB_DQ_45

BJ8

SB_DQ_46

BJ6

SB_DQ_47

BF4

SB_DQ_48

BH5

SB_DQ_49

BG1

SB_DQ_50

BC2

SB_DQ_51

BK3

SB_DQ_52

BE4

SB_DQ_53

BD3

SB_DQ_54

BJ2

SB_DQ_55

BA3

SB_DQ_56

BB3

SB_DQ_57

AR1

SB_DQ_58

AT3

SB_DQ_59

AY2

SB_DQ_60

AY3

SB_DQ_61

AU2

SB_DQ_62

AT2

SB_DQ_63

IC(1299P) PM965 QN14 B0(UFCBGA)

IC(1299P) PM965 QN14 B0(UFCBGA)

DDR_B_BS0

AY17

SB_BS_0
SB_BS_1
SB_BS_2

SB_CAS#

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6

SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13

SB_RAS#

SB_RCVEN#

SB_WE#

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

BG18
BG36

BE17
AR50

BD49
BK45
BL39
BH12
BJ7
BF3
AW2

AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3

BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13

AV16
AY18

BC17

DDR_B_BS1
DDR_B_BS2

DDR_B_CAS#
DDR_B_DM0

DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

DDR_B_RAS#

DDR_B_WE#

T46T46

DDR_B_BS0 12,13
DDR_B_BS1 12,13
DDR_B_BS2 12,13

DDR_B_DM[0..7] 13

DDR_B_DQS[0..7] 13

DDR_B_DQS#[0..7] 13

DDR_B_RAS# 12,13

DDR_B_WE# 12,13

A A

<OrgName>

<OrgName>

<OrgName>
<OrgAddr1>

<OrgAddr1>

<OrgAddr1>
<OrgAddr2>

<OrgAddr2>

<OrgAddr2>
<OrgAddr3>

<OrgAddr3>

<OrgAddr3>
<OrgAddr4>

<OrgAddr4>

<OrgAddr4>
Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

GMCH DDR/Strap(3 of 6)

GMCH DDR/Strap(3 of 6)

GMCH DDR/Strap(3 of 6)

Date: Sheet

Date: Sheet of

5

4

3

2

Date: Sheet of

PROJECT : TA7

PROJECT : TA7

PROJECT : TA7

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

of

749Friday, March 02, 2007

749Friday, March 02, 2007

749Friday, March 02, 2007

1

1A

1A

1A

5

GMCH 1.05V

VCC Core

VCC_AXG

VCC_AXD

VTT

D D

VCC_PEG

VCC_AXM

VCCR_RX_DMI

current(A)

1.573

7.7

0.2

0.85

1.2

0.54

0.25

12.313SUM

+1.8V_SUS

Remark

( 1.3A for
external GFX )

for integrated
Gfx

FSB VCCP

for PCIEG

for IAMT
function

DMI

+1.05V_VCCP

AT35
AT34
AH28
AC32
AC31
AK32

AJ31

AJ28
AH32
AH31
AH29
AF32

U32G

U32G

VCC_1
VCC_2
VCC_3
VCC_5
VCC_4
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

R30

VCC_13

IVCCSM supply current 1 channel 1.615A 2 channel 3.138A

AU32

VCC_SM_1

AU33

VCC_SM_2

AU35

VCC_SM_3

AV33

C266

C266

+

C309

+

C309
220U/4V_7343

C246

C246

0.1U/10V/X5R_4

0.1U/10V/X5R_4

C C

Layout Note:
Place C125 where
LVDS and DDR2
taps.

220U/4V_7343

22U/4V/X6S_8

22U/4V/X6S_8

C258

C258
22U/4V/X6S_8

22U/4V/X6S_8

change C309 value
from 330U/2V to 220U/4V
Mika 2006/12/26

+VCC_AXG

B B

A A

AW33
AW35

AY35
BA32
BA33
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35

BJ32

BJ33

BJ34
BK32
BK33
BK34
BK35

BL33

AU30

W13

W14
AA20

AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31

AJ20

AN14

R20
T14

Y12

VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34

4

VCC CORE

VCC CORE

POWER

POWER

VCC SMVCC GFX

VCC SMVCC GFX

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8

VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54

VCC GFX NCTF

VCC GFX NCTF

VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

VCC SM LF

VCC SM LF

T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31

AW45
BC39
BE39
BD17
BD4
AW8
AT6

3

+VCC_AXG

+1.05V_VCCP

Layout Note:
370 mils
from edge.

Ivcc_AXG Graphics core supply current 7.7A

C139

C139

+

*330U/2V_7343@NC

*330U/2V_7343@NC

+

*330U/2V_7343@NC

*330U/2V_7343@NC

C196

C196

*0.1U/10V/X5R_4@IV

*0.1U/10V/X5R_4@IV

Layout Note:
Inside GMCH cavity for VCC_AXG.

UMA & Discrete setting

VCC_AXG Discrete / UMA

----------------------­R84 NC STUFF
R85 NC STUFF
C104 NC NC
C249 NC NC
C181 NC 330U
C139 NC 330U
C196 NC 0.1U
C187 NC 0.1U
C228 NC 0.47U
C163 NC 1U
C156 NC 22U
C223 0 10U

External VGA with @EV part,
Internal VGA with @IV part.

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6

VCCSM_LF7

C241

C241

0.1U/10V/X5R_4

0.1U/10V/X5R_4

C254

C254

0.1U/10V/X5R_4

0.1U/10V/X5R_4

12

+3.3V

C604

C604

220U/2.5V_7343

220U/2.5V_7343

C181

C181

+

+

*330U/2V_7343@NC

*330U/2V_7343@NC

C187

C187

*0.1U/10V/X5R_4@IV

*0.1U/10V/X5R_4@IV

*0.47U/10V/X7R_6@IV

*0.47U/10V/X7R_6@IV

C261

C261

0.22U/10V/X7R_6

0.22U/10V/X7R_6

2

R496 10_4R496 10_4

1 2

+VCC_GMCH_L

21

D26 CH751H-40PTD26 CH751H-40PT

Ivcc (External GFX 1.310 A, integrate 1.572 A)

12

+

+

C249

C249

+

+

C228

C228

C650

C650

22U/4V/X6S_8

22U/4V/X6S_8

0.22U/6.3V/X5R_4

0.22U/6.3V/X5R_4

+VCC_AXG

C104

C104

+

+

*330U/2V_7343@NC

*330U/2V_7343@NC

C163

C163

*1U/6.3V/X5R_6@IV

*1U/6.3V/X5R_6@IV

C653

C653

0.22U/6.3V/X5R_4

0.22U/6.3V/X5R_4

Layout Note:
370 mils from edge.

*22U/4V/X6S_8@IV

*22U/4V/X6S_8@IV

C164

C164

0.1U/10V/X5R_4

0.1U/10V/X5R_4

C172

C172

Layout Note:
Inside GMCH
cavity.

R84 *HI0805R800R-5AR84 *HI0805R800R-5A
R85 *HI0805R800R-5AR85 *HI0805R800R-5A

UMA & Discrete setting

C156

C156

C223

C223
0_8@EV

0_8@EV

UMA & Discrete setting

Ivcc_AXM Controller supply current 540mA

Layout Note:
Inside GMCH cavity
for VCC_AXG.

C234

12

C240

C240

0.22U/10V/X7R_6

0.22U/10V/X7R_6

C234

0.1U/10V/X5R_4

0.1U/10V/X5R_4

C251

C251
1U/6.3V/X5R_6

1U/6.3V/X5R_6

C222

C222

0.1U/10V/X5R_4

0.1U/10V/X5R_4

Layout Note:
Place close to GMCH edge.

C269

C269

0.47U/10V/X7R_6

0.47U/10V/X7R_6

22U/4V/X6S_8

22U/4V/X6S_8

C262

C262

0.22U/6.3V/X5R_4

0.22U/6.3V/X5R_4

iAMT

+1.05V_M

C235

C235

12

+1.05V_VCCP

C210

C210

0.1U/10V/X5R_4

0.1U/10V/X5R_4

12

C220

C220

0.22U/10V/X7R_6

0.22U/10V/X7R_6

C256

C256
1U/6.3V/X5R_6

1U/6.3V/X5R_6

U32F

U32F

AB33

VCC_NCTF_1

AB36

VCC_NCTF_2

AB37

VCC_NCTF_3

AC33

VCC_NCTF_4

AC35

VCC_NCTF_5

AC36

VCC_NCTF_6

AD35

VCC_NCTF_7

AD36

VCC_NCTF_8

AF33

VCC_NCTF_9

AF36

VCC_NCTF_10

AH33

VCC_NCTF_11

AH35

VCC_NCTF_12

AH36

VCC_NCTF_13

AH37

VCC_NCTF_14

AJ33

VCC_NCTF_15

AJ35

VCC_NCTF_16

AK33

VCC_NCTF_17

AK35

VCC_NCTF_18

AK36

VCC_NCTF_19

AK37

VCC_NCTF_20

AD33

VCC_NCTF_21

AJ36

VCC_NCTF_22

AM35

VCC_NCTF_23

AL33

VCC_NCTF_24

AL35

VCC_NCTF_25

AA33

VCC_NCTF_26

AA35

VCC_NCTF_27

AA36

VCC_NCTF_28

AP35

VCC_NCTF_29

AP36

VCC_NCTF_30

AR35

VCC_NCTF_31

AR36

VCC_NCTF_32

Y32

VCC_NCTF_33

Y33

VCC_NCTF_34

Y35

VCC_NCTF_35

Y36

VCC_NCTF_36

Y37

VCC_NCTF_37

T30

VCC_NCTF_38

T34

VCC_NCTF_39

T35

VCC_NCTF_40

U29

VCC_NCTF_41

U31

VCC_NCTF_42

U32

VCC_NCTF_43

U33

VCC_NCTF_44

U35

VCC_NCTF_45

U36

VCC_NCTF_46

V32

VCC_NCTF_47

V33

VCC_NCTF_48

V36

VCC_NCTF_49

V37

VCC_NCTF_50

AL24

VCC_AXM_NCTF_1

AL26

VCC_AXM_NCTF_2

AL28

VCC_AXM_NCTF_3

AM26

VCC_AXM_NCTF_4

AM28

VCC_AXM_NCTF_5

AM29

VCC_AXM_NCTF_6

AM31

VCC_AXM_NCTF_7

AM32

VCC_AXM_NCTF_8

AM33

VCC_AXM_NCTF_9

AP29

VCC_AXM_NCTF_10

AP31

VCC_AXM_NCTF_11

AP32

VCC_AXM_NCTF_12

AP33

VCC_AXM_NCTF_13

AL29

VCC_AXM_NCTF_14

AL31

VCC_AXM_NCTF_15

AL32

VCC_AXM_NCTF_16

AR31

VCC_AXM_NCTF_17

AR32

VCC_AXM_NCTF_18

AR33

VCC_AXM_NCTF_19

IC(1299P) PM965 QN14 B0(UFCBGA)

IC(1299P) PM965 QN14 B0(UFCBGA)

1

VCC NCTF

VCC NCTF

POWER

POWER

VCC AXM NCTF

VCC AXM NCTF

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15

VSS NCTF

VSS NCTF

VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21

VSS_SCB1
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6

VSS SCBVCC AXM

VSS SCBVCC AXM

VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_5
VCC_AXM_6
VCC_AXM_7

T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28

A3
B2
C1
BL1
BL51
A51

AT33
AT31
AK29
AK24
AK23
AJ26
AJ23

iAMT

+1.05V_M

IC(1299P) PM965 QN14 B0(UFCBGA)

IC(1299P) PM965 QN14 B0(UFCBGA)

5

4

3

2

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

GMCH Power-1(4 of 6)

GMCH Power-1(4 of 6)

GMCH Power-1(4 of 6)

Date: Sheet

Date: Sheet

Date: Sheet

PROJECT : TA7

PROJECT : TA7

PROJECT : TA7

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

849Friday, March 02, 2007

849Friday, March 02, 2007

849Friday, March 02, 2007

of

of

1

of

1A

1A

1A

5

UMA & Discrete setting

PLL Discrete / UMA
L13 NC 10uH
C38 NC 470U
C72 0 0.1U
L77 NC 10uH
C600 NC 470U
C102 0 0.1U

L13 *10uH/100mA_8@IVL13 *10uH/100mA_8@IV

+1.25V

D D

+1.25V

*470U/2.5V_7343@IV

*470U/2.5V_7343@IV

L77

L77

*470U/2.5V_7343@IV

*470U/2.5V_7343@IV

+

C38

+

C38

*10uH/100mA_8@IV

*10uH/100mA_8@IV

C600

C600

+

+

C72

C72
0_4@EV

0_4@EV

C102

C102
0_4@EV

0_4@EV

+3.3V

+3.3V

R55 *0_6@IVR55 *0_6@IV

L66

L66
*BLM18PG181SN1D@IV

*BLM18PG181SN1D@IV
C610

C610
*10U/6.3V/X5R_8@IV

*10U/6.3V/X5R_8@IV

IVCCA_DPLLA~B current 0.08A

iAMT

+1.25V_M

C C

L80 BLM11A05SL80 BLM11A05S

L82 BLM11A05SL82 BLM11A05S

+VCCA_MPLL_L

C676

C676

22U/4V/X6S_8

22U/4V/X6S_8

+1.25V_M

iAMT

12

C662

C662

22U/10V/Y5V_1206

22U/10V/Y5V_1206

R535

R535

0.5/F_6

0.5/F_6

R203 0_8R203 0_8

+

C306

+

C306
220U/4V_7343

220U/4V_7343

iAMT

+1.25V_M

22U/4V/X6S_8

22U/4V/X6S_8

change C306 value
from 100U/10V to 220U/4V

C661

C661

0.1U/10V/X5R_4

0.1U/10V/X5R_4

C665

C665

0.1U/10V/X5R_4

0.1U/10V/X5R_4

C243

C243

R197 0_6R197 0_6

*1U/6.3V/X5R_6@NC

*1U/6.3V/X5R_6@NC

IVCCA_HPLL current 0.05A
IVCCA_MPLL current 0.15A

C265

C265

Mika 2006/12/26

IVCCD_CRT current 0.06A

+1.5V

B B

L18

L18
*100/F_6

*100/F_6

C608

C608
10U/4V/X6S_8

10U/4V/X6S_8

C44

C44

0.1U/10V/X5R_4

0.1U/10V/X5R_4

+VCCQ_TVDAC

+VCCQ_TVDAC+VCCQ_TVDAC+VCCQ_TVDAC+VCCQ_TVDAC+VCCQ_TVDAC+VCCQ_TVDAC

C60

C60
*0.1U/10V/X5R_4@IV

*0.1U/10V/X5R_4@IV

UMA & Discrete setting

CRT Discrete / UMA

A A

--------------------­L18 NC 100ohm
C60 NC 0.1U
R72 NC 0
R148 0 1UF
R133 0 NC
R141 NC 0

5

R86 0_4R86 0_4

C45

C45

0.022U/16V/X7R_4

0.022U/16V/X7R_4

22nF/3P@NC

22nF/3P@NC

IVCC_QDAC current 0.005A

R72 *0_4@IVR72 *0_4@IV

1

3

C70

C70

2

*22nF/3P@NC

*22nF/3P@NC

123

C68

C68

R148

R148
0_6@EV

0_6@EV

4

R59 *0_4@IVR59 *0_4@IV

C42

C42
*0.1U/10V/X5R_4@IV

*0.1U/10V/X5R_4@IV

IVCC_SYNC current 0.01A

R504 *0_4@IVR504 *0_4@IV

C609

C609
*0.1U/10V/X5R_4@IV

*0.1U/10V/X5R_4@IV

+3.3V

0.1U/10V/X5R_4

0.1U/10V/X5R_4

C287

C287
*22U/4V/X6S_8@NC

*22U/4V/X6S_8@NC

22U/4V/X6S_8

22U/4V/X6S_8

C271

C271

C259

C259

R133 0_4@EVR133 0_4@EV
R141 *0_6@IVR141 *0_6@IV

R95 0_4@EVR95 0_4@EV

LVDS Discrete / UMA

---------------------­R95 0 1000P

C115

C115

0.1U/10V/X5R_4

0.1U/10V/X5R_4

UMA & Discrete setting

C237

C237

4.7U/10V/X5R_8

4.7U/10V/X5R_8

*1U/6.3V/X5R_6@NC

*1U/6.3V/X5R_6@NC

IVCCD_TVDAC current 0.06A

+1.25V_M

iAMT

+1.25V

IVCCD_HPLL current 0.25A

C238

C238

0.1U/10V/X5R_4

0.1U/10V/X5R_4

L76

L76

1 2

BLM21PG221SN1D

BLM21PG221SN1D

IVCCA/D_PEG_PLL current 0.1A

+V1.25S_PEGPLL_FB

C618

C618
10U/6.3V/X5R_8

10U/6.3V/X5R_8

IVCCD_LVDS current 0.15A

+1.8V_SUS

R58 *0_6@IVR58 *0_6@IV

4

123

C46

C46
*22nF/3P@NC

*22nF/3P@NC

123

C613

C613
*22nF/3P@NC

*22nF/3P@NC

+3V_VCCSYNC+3V_VCCSYNC_1+3V_VCCSYNC_1

R124

R124
0_4@EV

0_4@EV

VCCA_CRTVCCA_CRT_1

R87

R87
0_4@EV

0_4@EV

+VCCA_DPLLA
+VCCA_DPLLB
+VCCA_HPLL
+VCCA_MPLL

IVCCA_LVDS current 0.01A

+VCC_TX_LVDS

IVCCA_PEG_BG current 0.04A

+VCCA_PEG_PLL

+VCCA_SM

C253

C253
1U/6.3V/X5R_6

1U/6.3V/X5R_6

C260

C260

+VCCA_SM_CK

VCCA_CRT

+VCCD_CRT
+VCCD_TVDAC_R

+VCCQ_TVDAC_R+VCCQ_TVDAC_R

+VCCA_PEG_PLL

C624

C624

0.1U/10V/X5R_4

0.1U/10V/X5R_4

12

C167

C71

C71

0_6@EV

0_6@EV

C167

0.1U/10V/X5R_4

0.1U/10V/X5R_4

+VCCD_LVDS

C50

C50

*10U/4V/X6S_8@NC

*10U/4V/X6S_8@NC

R516

R516
1/F_6

1/F_6

3

UMA & Discrete setting

CRT Discrete / UMA

--------------------­R55 NC 0
C42 NC 0.1U
R59 NC 0
R124 0 22nF
C610 NC 10U
L66 NC STUFF
C609 NC 0.1U
R504 NC 0
R87 0 22nF

U32H

U32H

J32

VCCSYNC

A33

VCCA_CRT_DAC_1

B33

VCCA_CRT_DAC_2

A30

VCCA_DAC_BG

B32

VSSA_DAC_BG

B49

VCCA_DPLLA

H49

VCCA_DPLLB

AL2

VCCA_HPLL

AM2

VCCA_MPLL

A41

VCCA_LVDS

B41

VSSA_LVDS

K50

VCCA_PEG_BG

K49

VSSA_PEG_BG

U51

VCCA_PEG_PLL

AW18

VCCA_SM_1

AV19

VCCA_SM_2

AU19

VCCA_SM_3

AU18

VCCA_SM_4

AU17

VCCA_SM_5

AT22

VCCA_SM_7

AT21

VCCA_SM_8

AT19

VCCA_SM_9

AT18

VCCA_SM_10

AT17

VCCA_SM_11

AR17

VCCA_SM_NCTF_1

AR16

VCCA_SM_NCTF_2

BC29

VCCA_SM_CK_1

BB29

VCCA_SM_CK_2

C25

VCCA_TVA_DAC_1

B25

VCCA_TVA_DAC_2

C27

VCCA_TVB_DAC_1

B27

VCCA_TVB_DAC_2

B28

VCCA_TVC_DAC_1

A28

VCCA_TVC_DAC_2

M32

VCCD_CRT

L29

VCCD_TVDAC

N28

VCCD_QDAC

AN2

VCCD_HPLL

U48

VCCD_PEG_PLL

J41

VCCD_LVDS_1

H42

VCCD_LVDS_2

IC(1299P) PM965 QN14 B0(UFCBGA)

IC(1299P) PM965 QN14 B0(UFCBGA)

If:SDVO Disabled,VCCD_LVDS to GND.
If:SDVO Enabled,VCCD_LVDS to +1.8V.

UMA & Discrete setting

LVDS Discrete / UMA

---------------------­R58 NC 0
C71 0 1U

C80

C80

C50 NC NC
C80 NC 1000P

*1000P/50V/X7R_4@NC

*1000P/50V/X7R_4@NC

3

CRTPLLA PEGA SMTV

CRTPLLA PEGA SMTV

POWER

POWER

A CK A LVDS

A CK A LVDS

D TV/CRTLVDS

D TV/CRTLVDS

External VGA with @EV part,
Internal VGA with @IV part.

+1.05V_VCCP

U13

VTT_1

U12

VTT_2

U11

VTT_3

U9

VTT_4

U8

VTT_5

U7

VTT_6

U5

VTT_7

U3

VTT_8

U2

VTT_9

U1

VTT_10

T13

VTT_11

T11

VTT_12

T10

VTT_13

T9

VTT

VTT

VTT_14

T7

VTT_15

T6

VTT_16

T5

VTT_17

T3

VTT_18

T2

VTT_19

R3

VTT_20

R2

VTT_21

R1

VTT_22

AT23

VCC_AXD_1

AU28

VCC_AXD_2

AU24

VCC_AXD_3

AT29

VCC_AXD_4

AT25

VCC_AXD_5

VCC_AXD_6

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

VCC_DMI

VCC_HV_1
VCC_HV_2

HV

HV

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5

VTTLF1
VTTLF2
VTTLF3

VTTLF

VTTLF

AT30
AR29

B23
B21
A21

AJ50

BK24
BK23
BJ24
BJ23

A43

IVCC_HV current 0.1A

C40
B40

AD51
W50
W51
V49
V50

AH50
AH51

+VTTLF1

A7

+VTTLF2

F2

+VTTLF3

AH1

C657

C657

0.47U/10V/X7R_6

0.47U/10V/X7R_6

AXD

AXD

VCC_AXD_NCTF

AXF

AXF

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

SM CK

SM CK

VCC_TX_LVDS

PEG

PEG

VCC_RXR_DMI_1
VCC_RXR_DMI_2

DMI

DMI

+3V_VCC_HV

D8

D8

*CH751H-40PT

*CH751H-40PT

+3V_VCC_HV

R502 0_6R502 0_6

4.7U/10V/X5R_8

4.7U/10V/X5R_8

+VCC_AXD

1U/6.3V/X5R_6

1U/6.3V/X5R_6

+VCC_SM_CK

+VCC_TX_LVDS

C90

C90

0.1U/10V/X5R_4

0.1U/10V/X5R_4

12

12

C103

C103

0.47U/10V/X7R_6

0.47U/10V/X7R_6

+1.05V_VCCP

21

+3V_VCC_HV_L

R42

R42
*10_6

*10_6

+3.3V

2

Ivtt_FSB core supply current 0.85A

C643

C643

4.7U/10V/X5R_8

4.7U/10V/X5R_8

C250

C250

1U/6.3V/X5R_6

1U/6.3V/X5R_6

C638

C638

L34 0_6L34 0_6

C290

C290
22U/4V/X6S_8

22U/4V/X6S_8

C67

C67

C160

C160

2.2U/6.3V/X5R_6

2.2U/6.3V/X5R_6

Ivcc_DMI current 0.1A

C245

C245

0.1U/10V/X5R_4

0.1U/10V/X5R_4

C264

C264

0.1U/10V/X5R_4

0.1U/10V/X5R_4

C267

C267
22U/4V/X6S_8

22U/4V/X6S_8

IVCC_TX_LVDS current 0.1A

+3V_VCC_HV

+VCC_PEG

C106

C614

C614

10U/4V/X6S_8

10U/4V/X6S_8

0.47U/10V/X7R_6

0.47U/10V/X7R_6

+VCC_RXR_DMI

C106

*10U/4V/X6S_8@NC

*10U/4V/X6S_8@NC

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

12

40 mil
wide

2

C161

C161

0.47U/6.3V/X5R_4

0.47U/6.3V/X5R_4

Ivcc_AXD current 0.25A

Ivcc_AXF current 0.35A

C65

C65
10U/4V/X6S_8

10U/4V/X6S_8

Ivcc_SM_CK current 0.2A

L33 1uH/300mA_8L33 1uH/300mA_8

+V1.8_SMCK_RC

R196

R196

1 2

1/F_6

1/F_6

L65 *1uH/300mA_8@IVL65 *1uH/300mA_8@IV

R97

R97
0_4@EV

0_4@EV

UMA & Discrete setting

LVDS Discrete / UMA

---------------------­L65 NC 1UH
C34 NC 220U
R97 0 1000P

R100

R100
0_8

0_8

L22 91nH/1.5AL22 91nH/1.5A

12

+

+

C40

C40
220U/4V_7343

220U/4V_7343

+VCC_PEG

Ivcc_RX_DMI current 0.25A

12

+

C224

C224

GMCH Power-2(5 of 6)

GMCH Power-2(5 of 6)

GMCH Power-2(5 of 6)

+

C307

C307
*220U/4V_7343@NC

*220U/4V_7343@NC

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

1

12

+

+

C36

C36
220U/4V_7343

220U/4V_7343

iAMT

+1.25V_M

+1.25V

+1.25V

+1.8V_SUS

C292 22U/4V/X6S_8C292 22U/4V/X6S_8

12

+

+

C34

C34
*220U/4V_7343@IV

*220U/4V_7343@IV

+1.05V_VCCP

Ivcc_PEG PCI-E current 1.2A

L31 *91nH/1.5A@NCL31 *91nH/1.5A@NC

PROJECT : TA7

PROJECT : TA7

PROJECT : TA7

949Friday, March 02, 2007

949Friday, March 02, 2007

949Friday, March 02, 2007

1

+1.8V_SUS

+1.05V_VCCP

of

of

of

1A

1A

1A

5

4

3

2

1

NB(Power-3)

U32I

U32I

A13

VSS_1

A15

VSS_2

A17

VSS_3

A24

VSS_4

AA21

VSS_5

AA24

VSS_6

AA29

VSS_7

AB20

VSS_8

AB23

D D

C C

B B

VSS_9

AB26

VSS_10

AB28

VSS_11

AB31

VSS_12

AC10

VSS_13

AC13

VSS_14

AC3

VSS_15

AC39

VSS_16

AC43

VSS_17

AC47

VSS_18

AD1

VSS_19

AD21

VSS_20

AD26

VSS_21

AD29

VSS_22

AD3

VSS_23

AD41

VSS_24

AD45

VSS_25

AD49

VSS_26

AD5

VSS_27

AD50

VSS_28

AD8

VSS_29

AE10

VSS_30

AE14

VSS_31

AE6

VSS_32

AF20

VSS_33

AF23
AF24
AF31

AG2
AG38
AG43
AG47
AG50

AH3
AH40
AH41

AH7

AH9

AJ11
AJ13
AJ21
AJ24
AJ29
AJ32
AJ43
AJ45

AJ49
AK20
AK21
AK26
AK28
AK31
AK51

AL1
AM11
AM13

AM3

AM4
AM41
AM45

AN1
AN38
AN39
AN43

AN5

AN7

AP4
AP48
AP50
AR11

AR2
AR39
AR44
AR47

AR7
AT10
AT14
AT41
AT49

AU1
AU23
AU29

AU3
AU36
AU49
AU51
AV39
AV48

AW1
AW12
AW16

IC(1299P) PM965 QN14 B0(UFCBGA)

IC(1299P) PM965 QN14 B0(UFCBGA)

VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

VSS

VSS

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198

AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41

U32J

U32J

C46

VSS_199

C50

VSS_200

C7

VSS_201

D13

VSS_202

D24

VSS_203

D3

VSS_204

D32

VSS_205

D39

VSS_206

D45

VSS_207

D49

VSS_208

E10

VSS_209

E16

VSS_210

E24

VSS_211

E28

VSS_212

E32

VSS_213

E47

VSS_214

F19

VSS_215

F36

VSS_216

F4

VSS_217

F40

VSS_218

F50

VSS_219

G1

VSS_220

G13

VSS_221

G16

VSS_222

G19

VSS_223

G24

VSS_224

G28

VSS_225

G29

VSS_226

G33

VSS_227

G42

VSS_228

G45

VSS_229

G48

VSS_230

G8

VSS_231

H24

VSS_232

H28

VSS_233

H4

VSS_234

H45

VSS_235

J11

VSS_236

J16

VSS_237

J2

VSS_238

J24

VSS_239

J28

VSS_240

J33

VSS_241

J35
J39

K12
K47

K8

L1
L17
L20
L24
L28

L3
L33
L49
M28
M42
M46
M49

M5

M50

M9
N11
N14
N17
N29
N32
N36
N39
N44
N49

N7
P19

P2

P23

P3
P50
R49
T39
T43
T47
U41
U45
U50

V2

V3

IC(1299P) PM965 QN14 B0(UFCBGA)

IC(1299P) PM965 QN14 B0(UFCBGA)

VSS_242
VSS_243

VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286

VSS

VSS

VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305

VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313

W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28

AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50

A A

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

GMCH Power-3(6 of 6)

GMCH Power-3(6 of 6)

GMCH Power-3(6 of 6)

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

PROJECT : TA7

PROJECT : TA7

PROJECT : TA7

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

10 49Friday, March 02, 2007

10 49Friday, March 02, 2007

10 49Friday, March 02, 2007

of

of

1

of

1A

1A

1A

Strap table

5

4

3

2

1

All strap are sampled with respect to the leading edge of the GMCH Power OK(PWROK) Signal
CFG[17:3] Have internal Pull-up

CFG[18:19] Have internal Pull-down
Any CFG signal strapping option not list below should be left NC Pin

Pin Name Strap description

D D

CFG[2:0]

CFG[4:3]

CFG5

CFG6

CFG7

CFG8

CFG9

CFG[11:10]

C C

CFG[13:12]

CFG[15:14]

CFG16

CFG[18:17]

SDVO_CTRLDATA

CFG19

CFG20

B B

DMI X2 Select

MCH_CFG_5

MCH_CFG_56

Low = DMIX2
High = IDMIX4(Default)

FSB Frequency Select

Reserved

DMI X2 Select

Reserved

CPU Strap

Low power PCI Express

PCI Express Graphics Lane Reversal

Reserved

XOR/ALLZ

Reserved

FSB Dynamic ODT

Reserved

SDVO Present

DMI Lane Reversal

SDVO/PCIe concurrent

DMI Lane Reversal

MCH_CFG_19

R123

R123
*4.02K/F_4@NC

*4.02K/F_4@NC

MCH_CFG_196

Low = Normal operation(Default)
High = Reverse Lane

+3.3V

R149

R149
*4.02K/F_4@NC

*4.02K/F_4@NC

SDVO/PCIE Concurrent operation

FSB Dynamic ODT

MCH_CFG_16

A A

MCH_CFG_166

Low = ODT Disable
High = ODT Enable(Default)

R138

R138
*4.02K/F_4@NC

*4.02K/F_4@NC

5

MCH_CFG_20

MCH_CFG_206

Low = Only SDVO or PCIE X1 is
operational(Default)
High = SDVO andPCIE X1 are operating
simultaneously via the PEG port

+3.3V

R139

R139
*4.02K/F_4@NC

*4.02K/F_4@NC

4

Configuration

010 = FSB 800MHz
011 = FSB 667MHz

0 = DMI X2
1 = DMI X4(Default)

0 = Reserved
1 = Mobile CPU(Default)

0 = Normal mode
1 = Low Power mode

0 = Reverse Lanes
1 = Normal operation(Default)

00 = Reserved
01 = XOR Mode Enable
10 = All-Z Mode Enabled
11 = Normal operation(Default)

0 = Dynamic ODT disable
1 = Dynamic ODT Enable(Default)

0 = No SDVO Card present(Default)
1 = SDVO Card Present

0 = Normal operation(Default)
1 = Reverse Lanes

0 = Only SDVO or PCIE x1 is operation(Default)
1 = SDVO and PCIE x1 are operating simultaneously via the PEG port

XOR /ALLz /Clock Un-gating

MCH_CFG_12 MCH_CFG_13 Configuration

0

0

1

1

MCH_CFG_126
MCH_CFG_136

*4.02K/F_4@NC

*4.02K/F_4@NC

Layout Note:
Location of all MCH_CFG strap resistors
needs to be close to minmize stub.

3

Clock gating disable

0

1

XOR Mode Enable

ALL-z Mode Enable

0

1

Normal operation(Default)

R108

R108

R137

R137
*4.02K/F_4@NC

*4.02K/F_4@NC

PCI Express Graphics

MCH_CFG_9

MCH_CFG_96

2

SDVO Present

Strap define at External

Low = Reverse Lane
High = Normal operation(Default)

R103

R103
*4.02K/F_4@NC

*4.02K/F_4@NC

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

GMCH Strap Table

GMCH Strap Table

GMCH Strap Table

Friday, March 02, 2007

Friday, March 02, 2007

Friday, March 02, 2007

Date: Sheet

Date: Sheet

Date: Sheet

DVI control page

PROJECT : TA7

PROJECT : TA7

PROJECT : TA7

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

1

11 49

11 49

11 49

of

of

of

1A

1A

1A

1

DDR2 Dual channel A/B PU

2

3

4

5

6

7

8

+0.9V_DDR_VTT

C353

C353

0.1U/10V/X5R_4

A A

B B

C C

D D

CGCLK_SMB_M2,13
CGDAT_SMB_M2,13

PM_EXTTS#06,13
PM_EXTTS#16,13

1

R279 *0_4@NCR279 *0_4@NC

0.1U/10V/X5R_4

+0.9V_DDR_VTT

C390

C390

0.1U/10V/X5R_4

0.1U/10V/X5R_4

U19

U19

8

SCLK

7

SDA

6

ALERT#

4

OVERT#

*LM86CIMM@NC

*LM86CIMM@NC

2

Layout note: Place 1 cap close to every 1 R-pack terminated to SMDDR_VTERM.

C406

C406

C408

C408

0.1U/10V/X5R_4

0.1U/10V/X5R_4

0.1U/10V/X5R_4

0.1U/10V/X5R_4

C427

C427

C428

C428

0.1U/10V/X5R_4

0.1U/10V/X5R_4

0.1U/10V/X5R_4

0.1U/10V/X5R_4

+3.3V_M

R293

R293

*220_6@NC

*220_6@NC

LM86_3V

1

VCC

2

DXP

3

DXN

5

GND

DDRII A CHANNEL

C363

C363

C389

C389

0.1U/10V/X5R_4

0.1U/10V/X5R_4

0.1U/10V/X5R_4

0.1U/10V/X5R_4

DDRII B CHANNEL

C351

C351

C403

C403

0.1U/10V/X5R_4

0.1U/10V/X5R_4

0.1U/10V/X5R_4

0.1U/10V/X5R_4

Please these resistor
closely DIMMA,all
trace length<750 mil.

C431

C431

*0.1U/10V/X5R_4@NC

*0.1U/10V/X5R_4@NC

DDR_THERMDA

C417

C417
*1000P/16V/X7R_4

*1000P/16V/X7R_4

DDR_THERMDC

3

2

C409

C409

0.1U/10V/X5R_4

0.1U/10V/X5R_4

C352

C352

0.1U/10V/X5R_4

0.1U/10V/X5R_4

UninstallDDR2 Thermal Sensor SO-DIMM 0 & 1

13

*MMBT3904_NL@NC

*MMBT3904_NL@NC
Q24

Q24

C362

C362

0.1U/10V/X5R_4

0.1U/10V/X5R_4

C354

C354

0.1U/10V/X5R_4

0.1U/10V/X5R_4

C404

C404

C426

C405

C405

0.1U/10V/X5R_4

0.1U/10V/X5R_4

C425

C425

C349

C349

0.1U/10V/X5R_4

0.1U/10V/X5R_4

0.1U/10V/X5R_4

0.1U/10V/X5R_4

DDR_A_MA[0..13]7,13 DDR_B_MA[0..13] 7,13

M_ODT06,13

DDR_CKE1_DIMMA6,13

DDR_A_BS07,13

DDR_A_RAS#7,13
DDR_A_BS17,13

DDR_A_WE#7,13
DDR_A_CAS#7,13

DDR_CS0_DIMMA#6,13

DDR_CS1_DIMMA#6,13

M_ODT16,13

DDR_CKE0_DIMMA6,13

DDR_A_BS27,13

4

0.1U/10V/X5R_4

0.1U/10V/X5R_4

C387

C387

0.1U/10V/X5R_4

0.1U/10V/X5R_4

M_ODT0
DDR_A_MA13

DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

DDR_A_MA11

DDR_A_MA10
DDR_A_BS0

DDR_A_MA7
DDR_A_MA6

DDR_A_MA2
DDR_A_MA4

DDR_A_RAS#
DDR_A_BS1

DDR_A_MA9
DDR_A_MA12

DDR_A_WE#
DDR_A_CAS#

DDR_A_MA0

C426

0.1U/10V/X5R_4

0.1U/10V/X5R_4

C407

C407

0.1U/10V/X5R_4

0.1U/10V/X5R_4

5

C350

C350

C388

C388

0.1U/10V/X5R_4

0.1U/10V/X5R_4

0.1U/10V/X5R_4

0.1U/10V/X5R_4

C402

C402

0.1U/10V/X5R_4

0.1U/10V/X5R_4

RP32 56X2RP32 56X2

1
3

RP22 56X2RP22 56X2

1
3

RP23 56X2RP23 56X2

1
3

RP27 56X2RP27 56X2

1
3

RP24 56X2RP24 56X2

1
3

RP28 56X2RP28 56X2

1
3

RP29 56X2RP29 56X2

1
3

RP31 56X2RP31 56X2

1
3

RP21 56X2RP21 56X2

1
3

RP25 56X2RP25 56X2

1
3

RP30 56X2RP30 56X2

1
3

RP26 56X2RP26 56X2

1
3

RP20 56X2RP20 56X2

1
3

C386

C386

0.1U/10V/X5R_4

0.1U/10V/X5R_4

C429

C429

0.1U/10V/X5R_4

0.1U/10V/X5R_4

+0.9V_DDR_VTT

2
4

2
4

2
4

2
4

2
4

2
4

2
4

2
4

2
4

2
4

2
4

2
4

2
4

RP17 56X2RP17 56X2

RP10 56X2RP10 56X2

RP9 56X2RP9 56X2

RP16 56X2RP16 56X2

RP8 56X2RP8 56X2

RP15 56X2RP15 56X2

RP7 56X2RP7 56X2

RP18 56X2RP18 56X2

RP12 56X2RP12 56X2

RP11 56X2RP11 56X2

RP19 56X2RP19 56X2

RP13 56X2RP13 56X2

RP14 56X2RP14 56X2

6

1
3

1
3

1
3

1
3

1
3

1
3

1
3

1
3

1
3

1
3

1
3

1
3

1
3

DDR_B_MA0

4

DDR_B_MA5

2

DDR_B_MA3

4

DDR_B_MA1

2

DDR_B_MA8

4

DDR_B_MA4

2

DDR_B_MA2

4

DDR_B_MA12

2

DDR_B_MA9

4

DDR_B_MA7

2

DDR_B_MA6

4

2
4

DDR_B_RAS#

2

DDR_B_MA13

4

DDR_B_WE#

2

DDR_B_CAS#

4

DDR_B_MA10

2

DDR_B_BS0

4

M_ODT2

2
4

2
4

2

DDR_B_MA11

4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

DDR RES. ARRAY

DDR RES. ARRAY

DDR RES. ARRAY

Friday, March 02, 2007

Friday, March 02, 2007

Friday, March 02, 2007

Date: Sheet

Date: Sheet

Date: Sheet

7

DDR_B_BS1 7,13

DDR_B_BS2 7,13

DDR_CKE3_DIMMB 6,13

DDR_B_RAS# 7,13

DDR_B_WE# 7,13
DDR_B_CAS# 7,13

DDR_B_BS0 7,13

M_ODT2 6,13

DDR_CS2_DIMMB# 6,13

M_ODT3 6,13

DDR_CS3_DIMMB# 6,13

DDR_CKE4_DIMMB 6,13

PROJECT : TA7

PROJECT : TA7

PROJECT : TA7

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

DDR_B_BS1

2

Please these resistor
closely DIMMB,all
trace length<750 mil.

12

12

12

8

1A

1A

1A

49

49

49

of

of

of

1

A is required to route to Top
SoDIMM for AMT to
function.This will need to
change for M08

A A

DDR_CKE0_DIMMA6,12

B B

DDR_A_BS27,12

DDR_A_BS07,12
DDR_A_WE#7,12

DDR_A_CAS#7,12
DDR_CS1_DIMMA#6,12

M_ODT16,12

C C

+3.3V_M

D D

iAMT

1

DDR2 Dual channel A/B CONN

V_DDR_MCH_REF

+1.8V_SUS

DDR_A_D0
DDR_A_D6

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D9
DDR_A_D13

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D15
DDR_A_D11

DDR_A_D20
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D23
DDR_A_D19

DDR_A_D25
DDR_A_D24

DDR_A_DM3

DDR_A_D30
DDR_A_D31

DDR_A_BS2
DDR_A_MA12

DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS0
DDR_A_WE#

DDR_A_CAS#

M_ODT1
DDR_A_D32

DDR_A_D33
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D34

DDR_A_D39
DDR_A_D41

DDR_A_D40
DDR_A_DM5
DDR_A_D42

DDR_A_D46
DDR_A_D48

DDR_A_D52

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D55
DDR_A_D50

DDR_A_D57
DDR_A_D61

DDR_A_DM7
DDR_A_D62

DDR_A_D59
CGDAT_SMB_M

CGCLK_SMB_M

2

+1.8V_SUS

CN33

CN33

1

VREF

3

VSS47

5

DQ0

7

DQ1

9

VSS37

11

DQS#0

13

DQS0

15

VSS48

17

DQ2

19

DQ3

21

VSS38

23

DQ8

25

DQ9

27

VSS49

29

DQS#1

31

DQS1

33

VSS39

35

DQ10

37

DQ11

39

VSS50

41

VSS18

43

DQ16

45

DQ17

47

VSS1

49

DQS#2

51

DQS2

53

VSS19

55

DQ18

57

DQ19

59

VSS22

61

DQ24

63

DQ25

65

VSS23

67

DM3

69

NC4

71

VSS9

73

DQ26

75

DQ27

77

VSS4

79

CKE0

81

VDD7

83

NC1

85

A16_BA2

87

VDD9

89

A12

91

A9

93

A8

95

VDD5

97

A5

99

A3

101

A1

103

VDD10

105

A10/AP

107

BA0

109

WE#

111

VDD2

113

CAS#

115

S1#

117

VDD3

119

ODT1

121

VSS11

123

DQ32

125

DQ33

127

VSS26

129

DQS#4

131

DQS4

133

VSS2

135

DQ34

137

DQ35

139

VSS27

141

DQ40

143

DQ41

145

VSS29

147

DM5

149

VSS51

151

DQ42

153

DQ43

155

VSS40

157

DQ48

159

DQ49

161

VSS52

163

NCTEST

165

VSS30

167

DQS#6

169

DQS6

171

VSS31

173

DQ50

175

DQ51

177

VSS33

179

DQ56

181

DQ57

183

VSS3

185

DM7

187

VSS34

189

DQ58

191

DQ59

193

VSS14

195

SDA

197

SCL

199

VDD(SPD)

DDR2_SODIMM

DDR2_SODIMM

H 9.2 H 5.2

2

VSS46

4

DQ4

6

DQ5

8

VSS15

10

DM0

12

VSS5

14

DQ6

16

DQ7

18

VSS16

20

DQ12

22

DQ13

24

VSS17

26

DM1

28

VSS53

30

CK0

32

CK0#

34

VSS41

36

DQ14

38

DQ15

40

VSS54

42

VSS20

44

DQ20

46

DQ21

48

VSS6

50

NC3

52

DM2

54

VSS21

56

DQ22

58

DQ23

60

VSS24

62

DQ28

64

DQ29

66

VSS25

68

DQS#3

70

DQS3

72

VSS10

74

DQ30

76

DQ31

78

VSS8

80

CKE1

82

VDD8

84

A15

86

A14

88

VDD11

90

A11

92

A7

94

A6

96

VDD4

98

PC4800 DDR2 SDRAM

SO-DIMM (200P)

PC4800 DDR2 SDRAM

SO-DIMM (200P)

A4

100

A2

102

A0

104

VDD12

RAS#
VDD1

ODT0
VDD6

NC2

VSS12

DQ36
DQ37

VSS28

DM4

VSS42

DQ38
DQ39

VSS55

DQ44

DQ45
VSS43
DQS#5

DQS5
VSS56

DQ46

DQ47
VSS44

DQ52

DQ53
VSS57

CK1

CK1#

VSS45

DM6

VSS32

DQ54

DQ55
VSS35

DQ60

DQ61

VSS7

DQS#7

DQS7
VSS36

DQ62

DQ63
VSS13

BA1
S0#

A13

SA0
SA1

DDR_A_BS1

106

DDR_A_RAS#

108
110
112
114

DDR_A_MA13

116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

CKE 0,1

DDR_A_D4
DDR_A_D5

DDR_A_DM0
DDR_A_D1

DDR_A_D7
DDR_A_D12

DDR_A_D8
DDR_A_DM1

DDR_A_D14
DDR_A_D10

DDR_A_D21
DDR_A_D16

PM_EXTTS#0
DDR_A_DM2

DDR_A_D18
DDR_A_D22

DDR_A_D29
DDR_A_D28

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D26
DDR_A_D27

DDR_CKE1_DIMMA 6,12

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_CS0_DIMMA# 6,12

M_ODT0

DDR_A_D36
DDR_A_D37

DDR_A_DM4
DDR_A_D35

DDR_A_D38
DDR_A_D44

DDR_A_D45
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D43

DDR_A_D47
DDR_A_D53

DDR_A_D49

DDR_A_DM6
DDR_A_D54

DDR_A_D51
DDR_A_D60

DDR_A_D56
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D58

DDR_A_D63

R300

R300

R299

R299

10K_4

10K_4

10K_4

10K_4

3

DDR_A_DM[0..7] 7
DDR_A_D[0..63] 7
DDR_A_DQS[0..7] 7
DDR_A_DQS#[0..7] 7
DDR_A_MA[0..13] 7,12

M_CLK_DDR0 6
M_CLK_DDR#0 6

PM_EXTTS#0 6,12 PM_EXTTS#1 6,12

DDR_CKE3_DIMMB6,12

DDR_B_BS27,12

DDR_A_BS1 7,12
DDR_A_RAS# 7,12

M_ODT0 6,12

M_CLK_DDR1 6
M_CLK_DDR#1 6

DDR_CS3_DIMMB#6,12

+3.3V_M

DDR_B_CAS#7,12

CGDAT_SMB_M2,12
CGCLK_SMB_M2,12

4

V_DDR_MCH_REF

+1.8V_SUS

DDR_B_D0
DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D7
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D17
DDR_B_D21

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D22
DDR_B_D23

DDR_B_D28
DDR_B_D29

DDR_B_DM3

DDR_B_D26
DDR_B_D27

DDR_B_BS2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10

DDR_B_BS07,12
DDR_B_WE#7,12

M_ODT36,12

DDR_B_BS0
DDR_B_WE#

DDR_B_CAS#

M_ODT3
DDR_B_D32

DDR_B_D36
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D46

DDR_B_D47
DDR_B_D48

DDR_B_D52

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D55
DDR_B_D50

DDR_B_D57
DDR_B_D60

DDR_B_DM7
DDR_B_D62

DDR_B_D59
CGDAT_SMB_M

CGCLK_SMB_M

iAMT

CLOCK 0,1

SMbus address A0

2

3

4

CN31

CN31

1

VREF

3

VSS47

5

DQ0

7

DQ1

9

VSS37

11

DQS#0

13

DQS0

15

VSS48

17

DQ2

19

DQ3

21

VSS38

23

DQ8

25

DQ9

27

VSS49

29

DQS#1

31

DQS1

33

VSS39

35

DQ10

37

DQ11

39

VSS50

41

VSS18

43

DQ16

45

DQ17

47

VSS1

49

DQS#2

51

DQS2

53

VSS19

55

DQ18

57

DQ19

59

VSS22

61

DQ24

63

DQ25

65

VSS23

67

DM3

69

NC4

71

VSS9

73

DQ26

75

DQ27

77

VSS4

79

CKE0

81

VDD7

83

NC1

85

A16_BA2

87

VDD9

89

A12

91

A9

93

A8

95

VDD5

97

A5

99

A3

101

A1

103

VDD10

105

A10/AP

107

BA0

109

WE#

111

VDD2

113

CAS#

115

S1#

117

VDD3

119

ODT1

121

VSS11

123

DQ32

125

DQ33

127

VSS26

129

DQS#4

131

DQS4

133

VSS2

135

DQ34

137

DQ35

139

VSS27

141

DQ40

143

DQ41

145

VSS29

147

DM5

149

VSS51

151

DQ42

153

DQ43

155

VSS40

157

DQ48

159

DQ49

161

VSS52

163

NCTEST

165

VSS30

167

DQS#6

169

DQS6

171

VSS31

173

DQ50

175

DQ51

177

VSS33

179

DQ56

181

DQ57

183

VSS3

185

DM7

187

VSS34

189

DQ58

191

DQ59

193

VSS14

195

SDA

197

SCL

199

VDD(SPD)

2-1734073-2

2-1734073-2

CKE 3,4

CLOCK 3,4

5

+1.8V_SUS

2

VSS46

DQ4
DQ5

VSS15

DM0

VSS5

DQ6
DQ7

VSS16

DQ12
DQ13

VSS17

DM1

VSS53

CK0

CK0#

VSS41

DQ14
DQ15

VSS54
VSS20

DQ20
DQ21

VSS6

NC3
DM2

VSS21

DQ22
DQ23

VSS24

DQ28

DQ29
VSS25
DQS#3

DQS3
VSS10

DQ30

DQ31

VSS8
CKE1

VDD8

A15
A14

VDD11

A11

A7
A6

VDD4

PC4800 DDR2 SDRAM

SO-DIMM (200P)

PC4800 DDR2 SDRAM

SO-DIMM (200P)

A4
A2
A0

VDD12

BA1

RAS#

S0#
VDD1
ODT0

A13
VDD6

NC2

VSS12

DQ36
DQ37

VSS28

DM4

VSS42

DQ38
DQ39

VSS55

DQ44
DQ45

VSS43
DQS#5

DQS5

VSS56

DQ46
DQ47

VSS44

DQ52
DQ53

VSS57

CK1

CK1#

VSS45

DM6

VSS32

DQ54
DQ55

VSS35

DQ60
DQ61

VSS7

DQS#7

DQS7

VSS36

DQ62
DQ63

VSS13

SA0

SA1

GND

202

DDR_B_D4

4

DDR_B_D5

6
8

DDR_B_DM0

10
12

DDR_B_D6

14

DDR_B_D2

16
18

DDR_B_D12

20

DDR_B_D13

22
24

DDR_B_DM1

26
28
30
32
34

DDR_B_D14

36

DDR_B_D15

38
40

42

DDR_B_D16

44

DDR_B_D20

46
48

PM_EXTTS#1

50

DDR_B_DM2

52
54

DDR_B_D18

56

DDR_B_D19

58
60

DDR_B_D24

62

DDR_B_D25

64
66

DDR_B_DQS#3

68

DDR_B_DQS3

70
72

DDR_B_D31

74

DDR_B_D30

76
78
80
82
84
86
88

DDR_B_MA11

90

DDR_B_MA7

92

DDR_B_MA6

94
96

DDR_B_MA4

98

DDR_B_MA2

100

DDR_B_MA0

102
104

DDR_B_BS1

106

DDR_B_RAS#

108
110
112

M_ODT2

114

DDR_B_MA13

116
118
120
122

DDR_B_D37

124

DDR_B_D38

126
128

DDR_B_DM4

130
132

DDR_B_D39

134

DDR_B_D33

136
138

DDR_B_D44

140

DDR_B_D45

142
144

DDR_B_DQS#5

146

DDR_B_DQS5

148
150

DDR_B_D42

152

DDR_B_D43

154
156

DDR_B_D49

158

DDR_B_D53

160
162
164
166
168

DDR_B_DM6

170
172

DDR_B_D54

174

DDR_B_D51

176
178

DDR_B_D56

180

DDR_B_D61

182
184

DDR_B_DQS#7

186

DDR_B_DQS7

188
190

DDR_B_D63

192

DDR_B_D58

194
196
198
200

R268 10K_4R268 10K_4

R267

R267
10K_4

10K_4

SMbus address A4

5

6

DDR_B_DM[0..7] 7
DDR_B_D[0..63] 7
DDR_B_DQS[0..7] 7
DDR_B_DQS#[0..7] 7
DDR_B_MA[0..13] 7,12

M_CLK_DDR3 6
M_CLK_DDR#3 6

DDR_CKE4_DIMMB 6,12

DDR_B_BS1 7,12
DDR_B_RAS# 7,12
DDR_CS2_DIMMB# 6,12

M_ODT2 6,12

M_CLK_DDR4 6
M_CLK_DDR#4 6

+3.3V_M

iAMT

6

7

+1.8V_SUS

Place these Caps near So-Dimm1.

C732

C355

*330U/2.5V_7343@NC

*330U/2.5V_7343@NC

C355

+1.8V_SUS

C731

C731

0.1U/10V/X5R_4

0.1U/10V/X5R_4

V_DDR_MCH_REF

+1.8V_SUS

C733

C733

2.2U/6.3V/X5R_6

2.2U/6.3V/X5R_6

+1.8V_SUS

C737

C737

0.1U/10V/X5R_4

0.1U/10V/X5R_4

V_DDR_MCH_REF

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

DDR SO-DIMM(200P)

DDR SO-DIMM(200P)

DDR SO-DIMM(200P)

Friday, March 02, 2007

Friday, March 02, 2007

Friday, March 02, 2007

Date: Sheet

Date: Sheet

Date: Sheet

7

C732

C734

+

+

2.2U/6.3V/X5R_6

2.2U/6.3V/X5R_6

C744

C744

0.1U/10V/X5R_4

0.1U/10V/X5R_4

C735

C735

0.1U/10V/X5R_4

0.1U/10V/X5R_4

2.2U/6.3V/X5R_6

2.2U/6.3V/X5R_6

C734

2.2U/6.3V/X5R_6

2.2U/6.3V/X5R_6

C747

C747

0.1U/10V/X5R_4

0.1U/10V/X5R_4

iAMT

+3.3V_M

C729

C729

C736

C736

2.2U/10V/X5R_6

2.2U/10V/X5R_6

C750

C750

2.2U/6.3V/X5R_6

2.2U/6.3V/X5R_6

2.2U/6.3V/X5R_6

2.2U/6.3V/X5R_6

C746

C746

0.1U/10V/X5R_4

0.1U/10V/X5R_4

Place these Caps near So-Dimm2.

C751

C751

C749

C749

C723

2.2U/6.3V/X5R_6

2.2U/6.3V/X5R_6

2.2U/6.3V/X5R_6

2.2U/6.3V/X5R_6

C743

C743

C745

C745

0.1U/10V/X5R_4

0.1U/10V/X5R_4

0.1U/10V/X5R_4

0.1U/10V/X5R_4

C401

C401

C400

C400

0.1U/10V/X5R_4

0.1U/10V/X5R_4

2.2U/6.3V/X5R_6

2.2U/6.3V/X5R_6

PROJECT : TA7

PROJECT : TA7

PROJECT : TA7

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

C723

2.2U/6.3V/X5R_6

2.2U/6.3V/X5R_6

2.2U/6.3V/X5R_6

2.2U/6.3V/X5R_6

C748

C748

0.1U/10V/X5R_4

0.1U/10V/X5R_4

iAMT

+3.3V_M

C415

C415

2.2U/10V/X5R_6

2.2U/10V/X5R_6

0.1U/10V/X5R_4

0.1U/10V/X5R_4

8

C752

C752

2.2U/6.3V/X5R_6

2.2U/6.3V/X5R_6

C730

C730

0.1U/10V/X5R_4

0.1U/10V/X5R_4

C738

C738

C724

C724

C726

C726

0.1U/10V/X5R_4

0.1U/10V/X5R_4

C411

C411

0.1U/10V/X5R_4

0.1U/10V/X5R_4

13 49

13 49

13 49

of

of

of

8

C725

C725

C728

C728

0.1U/10V/X5R_4

0.1U/10V/X5R_4

C727

C727

0.1U/10V/X5R_4

0.1U/10V/X5R_4

1A

1A

1A

RTC

5

4

3

SB Strap

2

+RTC_CELL+RTC_CELL

1

+RTC_CELL

D24

+3.3V_ALW

D D

VCCRTC_4

12

+5V_ALW

C C

Place all series terms close to ICH8 except for SDIN input
lines,which should be close to source.Placement of R292, R286,
R283 & R289 should equal distance to the T split trace point as
R291, R285, R284 & R290 respective. Basically,keep the same
distance from T for all series termination resistors.

B B

D24

CH501H-40PT

CH501H-40PT
D23

D23

CH501H-40PT

CH501H-40PT

R310

R310
1K_4

1K_4

CN25

CN25
ML1220-SOCKET

ML1220-SOCKET

R562 1.2K_4R562 1.2K_4

R560

R560

4.7K_4

4.7K_4

R559

R559
15K_4

15K_4

ICH_AZ_MDC_BITCLK30
ICH_AZ_CODEC_BITCLK30

ICH_AZ_MDC_SYNC30
ICH_AZ_CODEC_SYNC30
ICH_AZ_MDC_RST#30
ICH_AZ_CODEC_RST#30
ICH_AZ_MDC_SDOUT30
ICH_AZ_CODEC_SDOUT30

SATA_TX0-33
SATA_TX0+33

Distance between the ICH-8 M and cap on the "P"
signal should be identical distance between the
ICH-6 M and cap on the "N" signal for same pair.

SATA_TX2-33
SATA_TX2+33

+RTC_CELL

R358

R358

1M/F_4

1M/F_4

R556 1K_4R556 1K_4

C754

C754

*10P/50V_4@NC

*10P/50V_4@NC

C323 3900P/25V/X7R_4C323 3900P/25V/X7R_4
C322 3900P/25V/X7R_4C322 3900P/25V/X7R_4

C787 3900P/25V/X7R_4C787 3900P/25V/X7R_4
C784 3900P/25V/X7R_4C784 3900P/25V/X7R_4

C440 1U/10V/X5R_6C440 1U/10V/X5R_6

R331 20K_4R331 20K_4

G7

G7

*SHORT_PAD

*SHORT_PAD

VCCRTC_2VCCRTC_1

R612 33_4R612 33_4
R319 33_4R319 33_4

C437

C437
*10P/50V_4@NC

*10P/50V_4@NC

R610 33_4R610 33_4
R317 33_4R317 33_4
R611 33_4R611 33_4
R318 33_4R318 33_4
R609 33_4R609 33_4
R316 33_4R316 33_4

12

VCCRTC_3

SATA_TX0-_C
SATA_TX0+_C

SATA_TX2-_C
SATA_TX2+_C

C438

C438

1U/10V/X5R_6

1U/10V/X5R_6

13

Q44

Q44
MMBT3904_NL

MMBT3904_NL

2

ACZ_BIT_CLK

ACZ_SYNC

ACZ_RST#

ACZ_SDOUT

R614

R614

*10K_4@NC

*10K_4@NC

+3.3V_S5

ENERGY_DET

C444 18P/50V_4C444 18P/50V_4

Y9

Y9

32.768KHZ

32.768KHZ

C447 18P/50V_4C447 18P/50V_4

+1.5V_PCIE_ICH

+3.3V

1 4

2 3

LAN_RSTSYNC26

ENERGY_DET27

R383 24.9/F_4R383 24.9/F_4

ICH_AZ_CODEC_SDIN030
ICH_AZ_MDC_SDIN130

R324 *10K_4R324 *10K_4
R325 10K_4R325 10K_4

R330 10K_4R330 10K_4

SATA_RX0-33
SATA_RX0+33

SATA_RX2-33
SATA_RX2+33

CLK_PCIE_SATA#2
CLK_PCIE_SATA2

R635 24.9/F_4R635 24.9/F_4

R341

R341
10M_6

10M_6

GLAN_CLK26

LAN_RXD026
LAN_RXD126
LAN_RXD226

LAN_TXD026
LAN_TXD126
LAN_TXD226

T157T157
T68T68

SATA_LED#33

R630 10K_4R630 10K_4
R638 10K_4R638 10K_4

Layout Note:
L<500mils

ICH8M Internal VR Enable Strap
(Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)

ICH_INTVRMEN

ICH_RTCX1
ICH_RTCX2

RTCRST#
SM_INTRUDER#
ICH_INTVRMEN

LAN100_SLP

ENERGY_DET

GLAN_COMP_SB

ACZ_BIT_CLK
ACZ_SYNC

ACZ_RST#

ACZ_SDIN2
ACZ_SDIN3

ACZ_SDOUT

GPIO33
GPIO34

SATA_LED#

SATA_TX0-_C
SATA_TX0+_C

SATA_TX2-_C
SATA_TX2+_C

SATA_BIAS

R338

R338
332K/F_4

332K/F_4

ICH_INTVRMEN

R339

R339
*0_4@NC

*0_4@NC

Low = Internal VR Disabled
High = Internal VR Enabled(Default)

U39A

U39A

AG25

RTCX1

AF24

RTCX2

AF23

RTCRST#

AD22

INTRUDER#

AF25

INTVRMEN

AD21

LAN100_SLP

B24

GLAN_CLK

D22

LAN_RSTSYNC

C21

LAN_RXD0

B21

LAN_RXD1

C22

LAN_RXD2

D21

LAN_TXD0

E20

LAN_TXD1

C20

LAN_TXD2

AH21

GLAN_DOCK#/GPIO13

D25

GLAN_COMPI

C25

GLAN_COMPO

AJ16

HDA_BIT_CLK

AJ15

HDA_SYNC

AE14

HDA_RST#

AJ17

HDA_SDIN0

AH17

HDA_SDIN1

AH15

HDA_SDIN2

AD13

HDA_SDIN3

AE13

HDA_SDOUT

AE10

HDA_DOCK_EN#/GPIO33

AG14

HDA_DOCK_RST#/GPIO34

AF10

SATALED#

AF6

SATA0RXN

AF5

SATA0RXP

AH5

SATA0TXN

AH6

SATA0TXP

AG3

SATA1RXN

AG4

SATA1RXP

AJ4

SATA1TXN

AJ3

SATA1TXP

AF2

SATA2RXN

AF1

SATA2RXP

AE4

SATA2TXN

AE3

SATA2TXP

AB7

SATA_CLKN

AC6

SATA_CLKP

AG1

SATARBIAS#

AG2

SATARBIAS

ICH8M REV 1.0

ICH8M REV 1.0

RTCLAN / GLAN

RTCLAN / GLAN

IHDA

IHDA

SATA

SATA

ICH8M LAN100 SLP Strap
(Internal VR for VccLAN1.05 and VccCL1.05)

ICH_LAN100_SLP

E5

FWH0/LAD0

F5

FWH1/LAD1

G8

FWH2/LAD2

F6

FWH3/LAD3

LDRQ0#

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

IGNNE#

INIT#

INTR

RCIN#

SMI#

STPCLK#

THRMTRIP#

DD10
DD11
DD12
DD13
DD14
DD15

DCS1#
DCS3#

DIOR#

DIOW#

DDACK#

IDEIRQ

IORDY

DDREQ

NMI

TP8
DD0

DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9

DA0
DA1
DA2

C4
G9

E6
AF13

AG26
AF26

AE26
AD24
AG29
AF27
AE24

AC20
AH14

AD23
AG28

AA24
AE27
AA23
V1

U2
V3
T1
V4
T5
AB2
T6
T3
R2
T4
V6
V5
U1
V2
U6

AA4
AA1
AB3

Y6
Y5

W4
W3
Y2
Y3
Y1
W5

FWH4/LFRAME#

LDRQ1#/GPIO23

LPCCPU

LPCCPU

CPUPWRGD/GPIO49

IDE

IDE

R353

R353
332K/F_4

332K/F_4

LAN100_SLP

R345

R345
*0_4@NC

*0_4@NC

Low = Internal VR Disabled
High = Internal VR Enabled(Default)

LDRQ#1

T167T167

GATEA20

H_DPRSTP#
H_DPSLP#

H_FERR#

RCIN#

H_SMI#

H_THERMTRIP_R

ICH_TP8

T72T72

IDE_DD0
IDE_DD1
IDE_DD2
IDE_DD3
IDE_DD4
IDE_DD5
IDE_DD6
IDE_DD7
IDE_DD8

IDE_DD9
IDE_DD10
IDE_DD11
IDE_DD12
IDE_DD13
IDE_DD14
IDE_DD15

IDE_DA0
IDE_DA1
IDE_DA2

IDE_DCS1#
IDE_DCS3#

IDE_DD[0..15]

LPC_LAD0 32,35,37,38
LPC_LAD1 32,35,37,38
LPC_LAD2 32,35,37,38
LPC_LAD3 32,35,37,38

LPC_LFRAME# 32,35,37,38

LPC_LDRQ0# 32,37

GATEA20 35
H_A20M# 3

H_DPRSTP# 3,6,47
H_DPSLP# 3

H_FERR# 3
H_PWRGOOD 3
H_IGNNE# 3
H_INIT# 3

H_INTR 3
RCIN# 35

H_NMI 3
H_SMI# 3

H_STPCLK# 3

R356 24/F_6R356 24/F_6

IDE_DD[0..15] 33

IDE_DA0 33
IDE_DA1 33
IDE_DA2 33

IDE_DCS1# 33
IDE_DCS3# 33

IDE_DIOR# 33
IDE_DIOW# 33
IDE_DDACK# 33
IDE_IRQ 33
IDE_DIORDY 33
IDE_DDREQ 33

R350

R350

*56.2/F_4@NC

*56.2/F_4@NC

+1.05V_VCCP

*56.2/F_4@NC

*56.2/F_4@NC

H_DPSLP#
H_DPRSTP#
H_FERR#

RCIN#
GATEA20

R348

R348

56.2/F_4

56.2/F_4

H_THERMTRIP# 3,6

Layout Note:
Placement close SB L<2"

+1.05V_VCCP

R347

R347

+3.3V +3.3V

R607

R607
10K_4

10K_4

R349

R349

56.2/F_4

56.2/F_4

R370

R370
10K_4

10K_4

XOR Chain Entrance Strap

A A

5

4

ICH_RSV0

HDA_SDOUT Description

0

0

1

1

0

1

0

1

RSVD

Enter XOR Chain

Normal opration(Default)

Set PCIE port config bit 1

3

+3.3V

R321

R321
*1K_4@NC

*1K_4@NC

ACZ_SDOUT

R615

R615
*1K_4@NC

*1K_4@NC

ICH_RSVD 16

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

ICH8M HOST(1 of 4)

ICH8M HOST(1 of 4)

ICH8M HOST(1 of 4)

Date: Sheet

Date: Sheet

2

Date: Sheet

PROJECT : TA7

PROJECT : TA7

PROJECT : TA7

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

14 49Friday, March 02, 2007

14 49Friday, March 02, 2007

14 49Friday, March 02, 2007

of

of

1

of

1A

1A

1A

5

Place TX DC blocking caps close ICH8.

PCIE_TX1-32
PCIE_TX1+32

PCIE_TX2-32
PCIE_TX2+32

D D

PCIE_TX6-/GLAN_TX-26
PCIE_TX6+/GLAN_TX+26

C C

C778 0.1U/10V/X5R_4C778 0.1U/10V/X5R_4
C782 0.1U/10V/X5R_4C782 0.1U/10V/X5R_4

C786 0.1U/10V/X5R_4C786 0.1U/10V/X5R_4
C788 0.1U/10V/X5R_4C788 0.1U/10V/X5R_4

C811 0.1U/10V/X5R_4C811 0.1U/10V/X5R_4
C807 0.1U/10V/X5R_4C807 0.1U/10V/X5R_4

SB-PCI

PCI_AD[0..31]28

B B

A A

PCI_PIRQB#28
PCI_PIRQC#28
PCI_PIRQD#28

R393 *0_4R393 *0_4

Cardbus/
CardReader/1394

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#_R

5

BAYINS#33,35

ICH_SPI_CLK27
ICH_SPI_CS0#27
ICH_SPI_CS1#27

WLAN_RF_OFF#32

+3.3V_S5

+3.3V_S5
+3.3V_S5

D20

E19

D19

A20

D17

A21
A19

C19

A18
B16
A12
E16
A14

G16

A15
C11
D11

B12
C12
D10

F13

E11

E13

E12

A10

GNT0REQ0

ICH_SPI_DIN27
ICH_SPI_DO27

USB_OC0#34
USB_OC1#34
USB_OC2#34

iAMT

U39B

U39B

B6
A9

C7

D8
A6
E8
D6
A3

F9
B5
C5

ICH8M REV 1.0

ICH8M REV 1.0

PCIE_TXN1_C
PCIE_TXP1_C

PCIE_TXN2_C
PCIE_TXP2_C

GLAN_TXN_C
GLAN_TXP_C

PCIE_RX6-/GLAN_RX-26
PCIE_RX6+/GLAN_RX+26

USB_OC2#

WLAN_RF_OFF#

USB_OC4#
USB_OC3#

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

Interrupt I/F

Interrupt I/F

PIRQA#
PIRQB#
PIRQC#
PIRQD#

PIRQA
PIRQB
PIRQC

PCI

PCI

6
7
8
9

10

R332 10K_4R332 10K_4
R617 10K_4R617 10K_4

REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55

PCIRST#
DEVSEL#

PLTRST#

PIRQE#/GPIO2
PIRQF#/GPIO3

PIRQG#/GPIO4

PIRQH#/GPIO5

WLAN_RF_OFF#

RP33

RP33

10K-10P8R

10K-10P8R

REQ0#
GNT0#

C/BE0#
C/BE1#
C/BE2#
C/BE3#

IRDY#

PAR

PERR#

PLOCK#

SERR#
STOP#
TRDY#

FRAME#

PCICLK

PME#

PCIE_RX1-32
PCIE_RX1+32

MiniWLAN

PCIE_RX2-32
PCIE_RX2+32

MiniWWAN

R395 15_4R395 15_4
R399 15_4R399 15_4
R391 15_4R391 15_4

R396 0_4R396 0_4

5
4
3
2
1

USB_OC8#
USB_OC9#

PCI_REQ0#

A4

PCI_GNT0#

D7

BOARD_ID1

E18

BOARD_ID2

C18

PCI_REQ2#

B19

PCI_GNT2#

F18

PCI_REQ3#

A11

SB_NB_PCIE_RST#

C10
C17

E15
F16
E17

PCI_IRDY#

C8
D9
G6

PCI_DEVSEL#

D16

PCI_PERR#

A7

PCI_PLOCK#

B7

PCI_SERR#

F10

PCI_STOP#

C16

PCI_TRDY#

C9

PCI_FRAME#

A17

PLTRST#_NB

AG24

CLK_PCI_ICH

B10
G7

BAYID0

F8

BAYID1

G11

ICH_GPIO4_PIRQG#

F12

ICH_GPIO5_PIRQH#

B3

4

+3.3V_S5

USB_OC1#
BAYINS#
USB_OC0#
USB_OC5#

4

PCIE_TXN1_C
PCIE_TXP1_C

PCIE_TXN2_C
PCIE_TXP2_C

GLAN_TXN_C
GLAN_TXP_C

SPI_CS1#_R

USB_OC0#
USB_OC1#USB_OC1#
USB_OC2#USB_OC2#USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#

USB_OC8#
USB_OC9#

3

U39D

U39D

AJ19
AG16
AG15
AE15
AF15
AG17
AD12

AJ18
AD14
AH18

P27
P26
N29
N28

M27
M26

L29
L28

K27
K26
J29
J28

H27
H26
G29
G28

F27
F26
E29
E28

D27
D26
C29
C28

C23

B23
E22

D23

F21

PERN1
PERP1
PETN1
PETP1

PERN2
PERP2
PETN2
PETP2

PERN3
PERP3
PETN3
PETP3

PERN4
PERP4
PETN4
PETP4

PERN5
PERP5
PETN5
PETP5

PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP

SPI_CLK
SPI_CS0#
SPI_CS1#

SPI_MOSI
SPI_MISO

OC0#
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
OC8#
OC9#

ICH8M REV 1.0

ICH8M REV 1.0

PCI-Express

PCI-Express

DMI_ZCOMP

DMI_IRCOMP

SPI

SPI

USB

USB

V27

DMI0RXN

V26

DMI0RXP

U29

DMI0TXN

U28

DMI0TXP

Y27

DMI1RXN

Y26

DMI1RXP

W29

DMI1TXN

W28

DMI1TXP

AB26

DMI2RXN

AB25

DMI2RXP

AA29

DMI2TXN

AA28

DMI2TXP

AD27

DMI3RXN

AD26

DMI3RXP

AC29

DMI3TXN

AC28

DMI3TXP

T26

DMI_CLKN

T25

DMI_CLKP

Y23
Y24

Direct Media Interface

Direct Media Interface

G3

USBP0N

G2

USBP0P

H5

USBP1N

H4

USBP1P

H2

USBP2N

H1

USBP2P

J3

USBP3N

J2

USBP3P

K5

USBP4N

K4

USBP4P

K2

USBP5N

K1

USBP5P

L3

USBP6N

L2

USBP6P

M5

USBP7N

M4

USBP7P

M2

USBP8N

M1

USBP8P

N3

USBP9N

N2

USBP9P

F2

USBRBIAS#

USBRBIAS

F3

USB_RBIAS_PN

ICH8 Boot BIOS select

Boot BIOS Strap

GNT0# SPI_CS1#

No stuff
No stuff
Stuff

R685

R685

*10_4@NC

*10_4@NC

C834

C834

No stuff
Stuff
No stuff

+3.3V

1
2

3

C436 0.1U/10V/X5R_4C436 0.1U/10V/X5R_4

53

4

U21

U21

TC7SH08FU(F)

TC7SH08FU(F)

11LPC
PCI
SPI1001

SPI_CS1#_R
PCI_GNT0# SB_NB_PCIE_RST#

PCI_REQ0# 28
PCI_GNT0# 28
BOARD_ID1 16
BOARD_ID2 16

T81T81

PCI_C_BE0# 28
PCI_C_BE1# 28
PCI_C_BE2# 28
PCI_C_BE3# 28

PCI_IRDY# 28
PCI_PAR 28

PCI_DEVSEL# 28
PCI_PERR# 28

PCI_SERR# 28
PCI_STOP# 28
PCI_TRDY# 28
PCI_FRAME# 28

CLK_PCI_ICH 2
ICH_PME# 28

BAYID0 33
BAYID1 33

Reserved for EMI.
Place resister and cap
close to ICH.

R392 *1K_4@NCR392 *1K_4@NC
R386 *1K_4@NCR386 *1K_4@NC

CLK_PCI_ICH

*10P/50V_4@NC

*10P/50V_4@NC

DMI_MTX_IRX_N0 6
DMI_MTX_IRX_P0 6

DMI_MRX_ITX_N0 6
DMI_MRX_ITX_P0 6

DMI_MTX_IRX_N1 6
DMI_MTX_IRX_P1 6

DMI_MRX_ITX_N1 6
DMI_MRX_ITX_P1 6

DMI_MTX_IRX_N2 6
DMI_MTX_IRX_P2 6

DMI_MRX_ITX_N2 6
DMI_MRX_ITX_P2 6

DMI_MTX_IRX_N3 6
DMI_MTX_IRX_P3 6

DMI_MRX_ITX_N3 6
DMI_MRX_ITX_P3 6

CLK_PCIE_ICH# 2
CLK_PCIE_ICH 2

DMI_IRCOMP_R

USBP0- 34
USBP0+ 34
USBP1- 34
USBP1+ 34
USBP2- 34

USBP2+ 34

T73T73
T74T74

USBP4- 38

USBP4+ 38

T164T164
T163T163

USBP6- 38

USBP6+ 38

USBP7- 32

USBP7+ 32

USBP8- 36

USBP8+ 36

USBP9- 32

USBP9+ 32

System
System
System

Docking 1

BLUETOOTH
MiniCard 2 WWAN
FINGER PRINT
MiniCard 1 WWAN

Short F2 and F3 at the package

R660

R660

and keep length to less than

22.6/F_6

22.6/F_6

500mils. Trace Impedance
should be 60ohms +/- 15%.

A16 SWAP Override strap

SB_NB_PCIE_RST#

PCIRST# 28,37

PLTRST#_NB 6

R308

R308
100K_4

100K_4

2

+1.5V_PCIE_ICH

R376

R376

24.9/F_4

24.9/F_4

Layout Note:
DMI_IRCOMP_R<500mils

Low = A16 swap override enabled
High = Default

R394 *1K_4@NCR394 *1K_4@NC

PLTRST# 16,18,32,37,38

2

1

PCI Pullups

RP51

PCI_STOP#
PCI_REQ2#
PCI_FRAME#

+3.3V

PCI_SERR#
PCI_IRDY#
PCI_PERR#
PCI_PLOCK#

+3.3V

PCI_PIRQA#

+3.3V

<OrgName>

<OrgName>

<OrgName>
<OrgAddr1>

<OrgAddr1>

<OrgAddr1>
<OrgAddr2>

<OrgAddr2>

<OrgAddr2>
<OrgAddr3>

<OrgAddr3>

<OrgAddr3>
<OrgAddr4>

<OrgAddr4>

<OrgAddr4>
Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

ICH8M PCIE(2 of 4)

ICH8M PCIE(2 of 4)

ICH8M PCIE(2 of 4)

Date: Sheet

Date: Sheet of

Date: Sheet of

RP51

6
7
8
9

10

8.2K-10P8R

8.2K-10P8R
RP39

RP39

6
7
8
9

10

8.2K-10P8R

8.2K-10P8R
RP50

RP50

6
7
8
9

10

8.2K-10P8R

8.2K-10P8R

PROJECT : TA7

PROJECT : TA7

PROJECT : TA7

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

+3.3V

5
4
3
2
1

+3.3V

5
4
3
2
1

+3.3V

5
4
3
2
1

1

PCI_REQ3#
PCI_PIRQD#
PCI_TRDY#
PCI_DEVSEL#

PCI_REQ0#
ICH_GPIO4_PIRQG#
BAYID1

BAYID0
PCI_PIRQC#
PCI_PIRQB#
ICH_GPIO5_PIRQH#

of

15 49Friday, March 02, 2007

15 49Friday, March 02, 2007

15 49Friday, March 02, 2007

1A

1A

1A