Quanta LA-3631P, Satellite A210, Satellite A215 Schematic

A

1 1

B

C

D

E

IALAA

2 2

Minnesota 10A/10AG

LA3631P

3 3

REV 1A

Schematic

AMD Turion,Sempron/ATI RX690/RS690MC / ATI SB600

2007-05-04 Rev. 1A

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/5/4 2008/5/4

C

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Cover

Size Document Number Rev

IALAA-Minnesota10A LA3631P 1A

B

Monday, May 14, 2007

D

Date: Sheet

145

E

of

A

B

C

D

E

Compal confidential

IALAA Minnesota10A FUNCTION BLOCK DIAGRAM

File Name : IALAA Minnesota10A LA3631P
P/N :

Clock Generator

4 4

3 3

ICS951462AGLFT

PAGE 13

TV-OUT Conn.

HDMI Conn.

page 20

Thermal Sensor
GMT G781P8F

CPU VID

CRT Conn.

page 15

LVDS Conn

page 27

page 14

VGA Conn

page 15

33MHz (3.3V)

PAGE 6

PAGE 6

PCI

AMD S1 CPU

638 pin

Turion 64 X2
Turion 64
Sempron

PAGE 1,2,3,4,5,6,7

16x16 1000MHZ

ATI-RX/RS690MC

VGA M26P Embeded

465 pin BGA

PAGE 10,11,12

A-Link Express II

x4 PCIE

HT

533/667MHz
(1.8V)

Memory Bus

x1 PCI-E

x1 PCI-E

x1 PCI-E

x1 PCI-E

USB 2.0

SO-DIMM x 2(DDRII)

BANK 0,1,2,3

HD DVD

PAGE 24

Mini Card-WLAN

PAGE 24

New Card

PAGE 28

LAN

RTL8111B-1G
RTL8101E-10/100M

PAGE 25

480MHz(5V)

PAGE 8,9

RJ-45

PAGE 25

MiniCard w/ 3G (Port 8)

USB Port * 2 (Port 0, 1)

USB Port 0 be debug port.

PAGE 24

PAGE 29

FANController

RTC Battery

DC/DC Interface

Power Buttom

Finger Printer (Port 5)

Int. Camera (Port 7)

PAGE 41

PAGE 22

PAGE 42

PAGE 39

PAGE 29

PAGE 29

ATI-SB600

RealTek WLAN (Port3)

USB/B (Port 6, 2)

PAGE 24

PAGE 29

SATA

PATA

Primary SATA

3.3V,5V

1.5GHz(150MB/s)

Secondary
ATA-100 (5V)

SATA HDD0

PAGE 21

IDE ODD

PAGE 28

CardBus/ 5I N1/ 1394
PCI8412-1394/CardBus/5IN1

2 2

PAGE 22, 23

548 pin BGA

PAGE 16,17,18,19

LPC

33MHz (3.3V)

1394-Port

PAGE 22

1 1

CARD BUS
SOCKET

PAGE 23

A

5 IN 1 Conn

PAGE 22

Debug Port

PAGE 34

B

Embedded Controller

PS2

Issued Date

PAGE 30

Scan
KB

PAGE 33

Int.
K/B
Matrix

ENE KB926

SPI

BIOS

PAGE 31

Track
Pad

PAGE 33

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Azalia

24MHz(3.3V)

HD CODEC
ALC268-GR

PAGE 26

MDC w/Rev1.5

PAGE 28

2007/5/4 2008/5/4

C

Compal Secret Data

Deciphered Date

Audio Amplifier

APA2057A

D

PAGE 27

Bluetooth (Port 4)

NewCard (Port 9)

Compal Electronics, Inc.

Title

Black Diagram

Size Document Number Rev

IALAA-Minnesota10A LA3631P 1A

Custom

Monday, May 14, 2007

Date: Sheet

PAGE 29

PAGE 28

DCIN&DETECTOR

BATT CONN/OTP

2.5V/0.9V/1.5V

E

PAGE 36

PAGE 37

CHARGER

PAGE 38

3V/5V/

PAGE 39

1.8V/1.2V

PAGE 40

PAGE 41

CPU_CORE

PAGE 42

245

of

A

B

C

D

E

Rb

0

NC7

SIGNAL

HIGH

LOW

LOW

AD_BID

0.436 V

0.712 V

1.036 V

1.935 V

2.500 V

SLP_S5#STATE

HIGHHIGH

HIGH

HIGH

LOW

LOWLOW

minV

0 V

+VALW

ON

ON

ON

ON

ON

+V

ON

ON

ON

OFF

OFF

AD_BID

0.503 V

0.819 V

1.650 V1.453 V

2.200 V

3.300 V

typV

0 V

+VSSLP_S3#

ON

OFF

OFF

OFF

Clock

ONON

LOW

OFF

OFF

OFF

V

AD_BID

0.289 V0.250 V0.216 V

0.538 V

0.875 V

1.264 V1.185 V

1.759 V

2.341 V

3.300 V

max

0 V

Voltage Rails

S1 S3 S5Power Plane Description

1 1

2 2

VIN
B+

+VSB B+ switched power rail ON ON ON
+5VALW 5V always on power rail ONONON

+0.9V 0.9V switched power rail OFFON ON

+1.5VS
+CPU_COR E Core voltage for CPU
+1.2V_HT 1.2VS switched power rail ON

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Adapter power supply (19V)
AC or batte ry power rail for power circuit.

3.3V always on power rail+3VALW ON ON ON

1.2V always on power rail+1.2VALW ONON ON

ON ONON

ON+RTC V C C RTC power ON ON

ON OFF OFF+ 5VS 5VS switched power rail
ON+3VS 3.3VS switched power rail OFF OFF
ON OFF OFF+2.5VS 2.5VS switched power rail
ON OFF OFF+1.8VS 1.8VS switched power rail
ON OFF OFF1.5VS switched power rail
ON

OFF OFF

ONONON

OFF+1.8V 1.8V power rail ON ON

OFFOFF

Full ON

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

ID Table for AD channel

Vcc
Ra

Board ID

0
1
2
3
4
5
6

3.3V +/- 5%
100K +/- 5%

8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%

External PCI Devices

Device IDSEL # REQ # / GNT # Interrupts

EC SM Bus1 address

3 3

Device

Smart Battery
24C16

HEX
16H
A0H

AD20 2/ 2

PIRQE/F/G1394/ CardBus/ 5IN1

EC SM Bus2 address

Address Address

1010 000X b

Device

CPU Thermal-G781P8F
VGA Thermal-

HEX
98H

1001 100X b0001 011X b

BTN_ID BOM STURCTUREBTO

0
1
2
3
4
5
6
7

ATi SB600 SM Bus address
SM Bus0 address SM Bus1 address

Device

Clock GEN.
(ICS951462AGLFT)

DDR DIMM0
DDR DIMM1

4 4

Mini Card-WLAN
Mini Card-3G
New Card

HEX

A4
A6

A

Address

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/5/4 2008/5/4

C

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

D

Date: Sheet

Compal Electronics, Inc.

Notes List

IALAA-Minnesota10A LA3631P 1A

Monday, May 14, 2007

345

E

of

5

4

3

2

1

D D

C C

B B

H_CADIP[0..15]<10>

+1.2V_HT

AMD : 49.9 1%
ATI : 51 1%

R52 51_0402_1%
R51 51_0402_1%

H_CLKIP1<10>
H_CLKIN1<10>
H_CLKIP0<10>
H_CLKIN0<10>

H_CTLIP0<10> H_CTLOP0 <10>
H_CTLIN0<10>

H_CADIP[0..15]
H_CADIN[0..15]

VLDT=500mA

H_CADIP15
H_CADIN15
H_CADIP14
H_CADIN14
H_CADIP13
H_CADIN13
H_CADIP12
H_CADIN12
H_CADIP11
H_CADIN11
H_CADIP10
H_CADIN10
H_CADIP9
H_CADIN9
H_CADIP8
H_CADIN8
H_CADIP7
H_CADIN7
H_CADIP6
H_CADIN6
H_CADIP5
H_CADIN5
H_CADIP4 H_CADOP4
H_CADIN4
H_CADIP3
H_CADIN3
H_CADIP2
H_CADIN2
H_CADIP1
H_CADIN1
H_CADIP0
H_CADIN0

12
12

H_CTLIP0

+1.2V_HT

D4

VLDT_A3

D3

VLDT_A2

D2

VLDT_A1

D1

VLDT_A0

N5

L0_CADIN_H15

P5

L0_CADIN_L15

M3

L0_CADIN_H14

M4

L0_CADIN_L14

L5

L0_CADIN_H13

M5

L0_CADIN_L13

K3

L0_CADIN_H12

K4

L0_CADIN_L12

H3

L0_CADIN_H11

H4

L0_CADIN_L11

G5

L0_CADIN_H10

H5

L0_CADIN_L10

F3

L0_CADIN_H9

F4

L0_CADIN_L9

E5

L0_CADIN_H8

F5

L0_CADIN_L8

N3

L0_CADIN_H7

N2

L0_CADIN_L7

L1

L0_CADIN_H6

M1

L0_CADIN_L6

L3

L0_CADIN_H5

L2

L0_CADIN_L5

J1

L0_CADIN_H4

K1

L0_CADIN_L4

G1

L0_CADIN_H3

H1

L0_CADIN_L3

G3

L0_CADIN_H2

G2

L0_CADIN_L2

E1

L0_CADIN_H1

F1

L0_CADIN_L1

E3

L0_CADIN_H0

E2

L0_CADIN_L0

J5

L0_CLKIN_H1

K5

L0_CLKIN_L1

J3

L0_CLKIN_H0

J2

L0_CLKIN_L0

P3

L0_CTLIN_H1

P4

L0_CTLIN_L1

N1

L0_CTLIN_H0

P1

L0_CTLIN_L0

FOX_PZ63823-284S-41F

Athlon 64 S1
Processor Socket

JP27A

VLDT_B3
VLDT_B2
VLDT_B1
VLDT_B0

L0_CADOUT_H15

L0_CADOUT_L15

L0_CADOUT_H14

L0_CADOUT_L14

L0_CADOUT_H13

L0_CADOUT_L13

L0_CADOUT_H12

L0_CADOUT_L12

L0_CADOUT_H11

L0_CADOUT_L11

L0_CADOUT_H10

L0_CADOUT_L10

L0_CADOUT_H9

L0_CADOUT_L9

L0_CADOUT_H8

L0_CADOUT_L8

L0_CADOUT_H7

L0_CADOUT_L7

L0_CADOUT_H6

L0_CADOUT_L6

L0_CADOUT_H5

L0_CADOUT_L5

L0_CADOUT_H4

L0_CADOUT_L4

L0_CADOUT_H3

L0_CADOUT_L3

L0_CADOUT_H2

L0_CADOUT_L2

L0_CADOUT_H1

L0_CADOUT_L1

L0_CADOUT_H0

HTT Interface

L0_CADOUT_L0
L0_CLKOUT_H1

L0_CLKOUT_L1

L0_CLKOUT_H0

L0_CLKOUT_L0

L0_CTLOUT_H1

L0_CTLOUT_L1

L0_CTLOUT_H0

L0_CTLOUT_L0

AE5
AE4
AE3
AE2

T4
T3
V5
U5
V4
V3
Y5
W5
AB5
AA5
AB4
AB3
AD5
AC5
AD4
AD3
T1
R1
U2
U3
V1
U1
W2
W3
AA2
AA3
AB1
AA1
AC2
AC3
AD1
AC1

Y4
Y3
Y1
W1

T5
R5

R2
R3

H_CADOP[0..15]
H_CADON[0..15]

C107 4.7U_0805_10V4Z

H_CADOP15
H_CADON15
H_CADOP14
H_CADON14
H_CADOP13
H_CADON13
H_CADOP12
H_CADON12
H_CADOP11
H_CADON11
H_CADOP10
H_CADON10
H_CADOP9
H_CADON9
H_CADOP8
H_CADON8
H_CADOP7
H_CADON7
H_CADOP6
H_CADON6
H_CADOP5
H_CADON5

H_CADON4
H_CADOP3
H_CADON3
H_CADOP2
H_CADON2
H_CADOP1
H_CADON1
H_CADOP0
H_CADON0

H_CTLOP0
H_CTLON0H_CTLIN0

1 2

H_CLKOP1 <10>
H_CLKON1 <10>
H_CLKOP0 <10>
H_CLKON0 <10>

H_CTLON0 <10>

H_CADOP[0..15] <10>
H_CADON[0..15] <10>H_CADIN[0..15]<10>

+1.2V_HT

250 mil

1

C102

4.7U_0805_10V4Z

2

VLDT CAP.

1

C103

4.7U_0805_10V4Z

2

1 2

C497 0.01U_0402_25V4Z@

1 2

C503 0.01U_0402_25V4Z@

1 2

C496 0.01U_0402_25V4Z@

1

C101

0.22U_0603_16V4Z

2

Near CPU Socket

1

2

1

C104

0.22U_0603_16V4Z

C1447 Near H_CADIP/N[2..4] and
H_CLKIP/N0 near CPU BOT Side

C1448 Near H_CADIP/N[5..7] and
H_CTLIP/N0 near CPU BOT Side

C1449 Near H_CADOP/N[0..1]
near CPU BOT Side

C106
180P_0402_50V8J

2

1

2

GND1VCC GND

C112
180P_0402_50V8J

For IALAA Only-­Change Layer Bridge for HOST3 CADOP/N[0..7]

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/5/4 2008/5/4

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

S1g1 HT I/F

IALAA-Minnesota10A LA3631P

1A

445Monday, May 14, 2007

1

of

A

B

C

D

E

Processor DDR2 Memory Interface

+1.8V

R91

1K_0402_1%

R90

1K_0402_1%

1 2

1 2

1

2

1

C151

2

0.1U_0402_16V4Z

4 4

Need to link SD000006980

R331

+1.8V

3 3

2 2

1 1

1 2

R335

DDR_CS3_DIMMA#<8>
DDR_CS2_DIMMA#<8>
DDR_CS1_DIMMA#<8>
DDR_CS0_DIMMA#<8>

DDR_CS3_DIMMB#<9>
DDR_CS2_DIMMB#<9>
DDR_CS1_DIMMB#<9>
DDR_CS0_DIMMB#<9>

DDR_CKE1_DIMMB<9>
DDR_CKE0_DIMMB<9>
DDR_CKE1_DIMMA<8>
DDR_CKE0_DIMMA<8>

DDR_A_MA[15..0]<8>

DDR_A_BS#2<8>
DDR_A_BS#1<8>
DDR_A_BS#0<8>

DDR_A_RAS#<8>
DDR_A_CAS#<8>
DDR_A_WE#<8>

C156

1000P_0402_25V8J

12

TP2

39.2_0402_1%

39.2_0402_1%

+CPU_M_VREF

+CPU_M_VREF

VTT_SENSE

DDR_CS3_DIMMA#
DDR_CS2_DIMMA#
DDR_CS1_DIMMA#
DDR_CS0_DIMMA#

DDR_CS3_DIMMB#
DDR_CS2_DIMMB#
DDR_CS1_DIMMB#
DDR_CS0_DIMMB#

DDR_CKE1_DIMMB
DDR_CKE0_DIMMB
DDR_CKE1_DIMMA
DDR_CKE0_DIMMA

DDR_A_MA15
DDR_A_MA14
DDR_A_MA13
DDR_A_MA12
DDR_A_MA11
DDR_A_MA10
DDR_A_MA9
DDR_A_MA8
DDR_A_MA7
DDR_A_MA6
DDR_A_MA5
DDR_A_MA4
DDR_A_MA3
DDR_A_MA2
DDR_A_MA1
DDR_A_MA0

DDR_A_BS#2
DDR_A_BS#1
DDR_A_BS#0

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

M_ZN
M_ZP

W17

M_VREF

Y10

VTT_SENSE

AE10

M_ZN

AF10

M_ZP

V19

MA0_CS_L3

J22

MA0_CS_L2

V22

MA0_CS_L1

T19

MA0_CS_L0

Y26

MB0_CS_L3

J24

MB0_CS_L2

W24

MB0_CS_L1

U23

MB0_CS_L0

H26

MB_CKE1

J23

MB_CKE0

J20

MA_CKE1

J21

MA_CKE0

K19

MA_ADD15

K20

MA_ADD14

V24

MA_ADD13

K24

MA_ADD12

L20

MA_ADD11

R19

MA_ADD10

L19

MA_ADD9

L22

MA_ADD8

L21

MA_ADD7

M19

MA_ADD6

M20

MA_ADD5

M24

MA_ADD4

M22

MA_ADD3

N22

MA_ADD2

N21

MA_ADD1

R21

MA_ADD0

K22

MA_BANK2

R20

MA_BANK1

T22

MA_BANK0

T20

MA_RAS_L

U20

MA_CAS_L

U21

MA_WE_L

FOX_PZ63823-284S-41F

Athlon 64 S1
Processor
Socket

JP27B

VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9

MA0_CLK_H2

MA0_CLK_L2

MA0_CLK_H1

MA0_CLK_L1

MB0_CLK_H2

MB0_CLK_L2

MB0_CLK_H1

MB0_CLK_L1

MB0_ODT1
MB0_ODT0
MA0_ODT1
MA0_ODT0

MB_ADD15
MB_ADD14
MB_ADD13
MB_ADD12
MB_ADD11
MB_ADD10

MB_ADD9

DDRII Cmd/Ctrl//Clk

MB_ADD8
MB_ADD7
MB_ADD6
MB_ADD5
MB_ADD4
MB_ADD3
MB_ADD2
MB_ADD1
MB_ADD0

MB_BANK2
MB_BANK1
MB_BANK0

MB_RAS_L
MB_CAS_L

MB_WE_L

D10
C10
B10
AD10
W10
AC10
AB10
AA10
A10

Y16
AA16
E16
F16

AF18
AF17
A17
A18

W23
W26
V20
U19

J25
J26
W25
L23
L25
U25
L24
M26
L26
N23
N24
N25
N26
P24
P26
T24

K26
T26
U26

U24
V26
U22

+0.9V

DDR_A_CLK2
DDR_A_CLK#2
DDR_A_CLK1
DDR_A_CLK#1

DDR_B_CLK2
DDR_B_CLK#2
DDR_B_CLK1
DDR_B_CLK#1

DDR_B_ODT1
DDR_B_ODT0
DDR_A_ODT1
DDR_A_ODT0

DDR_B_MA15
DDR_B_MA14
DDR_B_MA13
DDR_B_MA12
DDR_B_MA11
DDR_B_MA10
DDR_B_MA9
DDR_B_MA8
DDR_B_MA7
DDR_B_MA6
DDR_B_MA5
DDR_B_MA4
DDR_B_MA3
DDR_B_MA2
DDR_B_MA1
DDR_B_MA0

DDR_B_BS#2
DDR_B_BS#1
DDR_B_BS#0

DDR_B_RAS#
DDR_B_CAS#
DDR_B_WE#

DDR_A_CLK2 <8>
DDR_A_CLK#2 <8>
DDR_A_CLK1 <8>
DDR_A_CLK#1 <8>

DDR_B_CLK2 <9>
DDR_B_CLK#2 <9>
DDR_B_CLK1 <9>
DDR_B_CLK#1 <9>

DDR_B_ODT1 <9>
DDR_B_ODT0 <9>
DDR_A_ODT1 <8>
DDR_A_ODT0 <8>

DDR_B_MA[15..0] <9>

DDR_B_BS#2 <9>
DDR_B_BS#1 <9>
DDR_B_BS#0 <9>

DDR_B_RAS# <9>
DDR_B_CAS# <9>
DDR_B_WE# <9>

PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH

DDR_A_CLK2

DDR_A_CLK#2
DDR_A_CLK1

DDR_A_CLK#1

DDR_B_CLK2

DDR_B_CLK#2
DDR_B_CLK1

DDR_B_CLK#1

DDR_B_D[63..0]<9>

1

C148

1.5P_0402_50V9C

2

1

C150

1.5P_0402_50V9C

2

1

C149

1.5P_0402_50V9C

2

1

C568

1.5P_0402_50V9C

2

DDR_B_DM[7..0]<9> DDR_A_DM[7..0] <8>

DDR_B_DQS7<9>
DDR_B_DQS#7<9>
DDR_B_DQS6<9>
DDR_B_DQS#6<9>
DDR_B_DQS5<9>
DDR_B_DQS#5<9>
DDR_B_DQS4<9>
DDR_B_DQS#4<9>
DDR_B_DQS3<9>
DDR_B_DQS#3<9>
DDR_B_DQS2<9>
DDR_B_DQS#2<9>
DDR_B_DQS1<9>
DDR_B_DQS#1<9>
DDR_B_DQS0<9>
DDR_B_DQS#0<9>

DDR_B_D63
DDR_B_D62
DDR_B_D61
DDR_B_D60
DDR_B_D59
DDR_B_D58
DDR_B_D57
DDR_B_D56
DDR_B_D55
DDR_B_D54
DDR_B_D53
DDR_B_D52
DDR_B_D51
DDR_B_D50
DDR_B_D49
DDR_B_D48
DDR_B_D47
DDR_B_D46
DDR_B_D45
DDR_B_D44
DDR_B_D43
DDR_B_D42
DDR_B_D41
DDR_B_D40
DDR_B_D39
DDR_B_D38
DDR_B_D37
DDR_B_D36
DDR_B_D35
DDR_B_D34
DDR_B_D33
DDR_B_D32
DDR_B_D31
DDR_B_D30
DDR_B_D29
DDR_B_D28
DDR_B_D27
DDR_B_D26
DDR_B_D25
DDR_B_D24
DDR_B_D23
DDR_B_D22
DDR_B_D21
DDR_B_D20
DDR_B_D19
DDR_B_D18
DDR_B_D17
DDR_B_D16
DDR_B_D15
DDR_B_D14
DDR_B_D13
DDR_B_D12
DDR_B_D11
DDR_B_D10
DDR_B_D9
DDR_B_D8
DDR_B_D7
DDR_B_D6
DDR_B_D5
DDR_B_D4
DDR_B_D3
DDR_B_D2
DDR_B_D1
DDR_B_D0

DDR_B_DM7
DDR_B_DM6
DDR_B_DM5
DDR_B_DM4
DDR_B_DM3
DDR_B_DM2
DDR_B_DM1
DDR_B_DM0

DDR_B_DQS7
DDR_B_DQS#7
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS0
DDR_B_DQS#0

AD11

MB_DATA63

AF11

MB_DATA62

AF14

MB_DATA61

AE14

MB_DATA60

Y11

MB_DATA59

AB11

MB_DATA58

AC12

MB_DATA57

AF13

MB_DATA56

AF15

MB_DATA55

AF16

MB_DATA54

AC18

MB_DATA53

AF19

MB_DATA52

AD14

MB_DATA51

AC14

MB_DATA50

AE18

MB_DATA49

AD18

MB_DATA48

AD20

MB_DATA47

AC20

MB_DATA46

AF23

MB_DATA45

AF24

MB_DATA44

AF20

MB_DATA43

AE20

MB_DATA42

AD22

MB_DATA41

AC22

MB_DATA40

AE25

MB_DATA39

AD26

MB_DATA38

AA25

MB_DATA37

AA26

MB_DATA36

AE24

MB_DATA35

AD24

MB_DATA34

AA23

MB_DATA33

AA24

MB_DATA32

G24

MB_DATA31

G23

MB_DATA30

D26

MB_DATA29

C26

MB_DATA28

G26

MB_DATA27

G25

MB_DATA26

E24

MB_DATA25

E23

MB_DATA24

C24

MB_DATA23

B24

MB_DATA22

C20

MB_DATA21

B20

MB_DATA20

C25

MB_DATA19

D24

MB_DATA18

A21

MB_DATA17

D20

MB_DATA16

D18

MB_DATA15

C18

MB_DATA14

D14

MB_DATA13

C14

MB_DATA12

A20

MB_DATA11

A19

MB_DATA10

A16

MB_DATA9

A15

MB_DATA8

A13

MB_DATA7

D12

MB_DATA6

E11

MB_DATA5

G11

MB_DATA4

B14

MB_DATA3

A14

MB_DATA2

A11

MB_DATA1

C11

MB_DATA0

AD12

MB_DM7

AC16

MB_DM6

AE22

MB_DM5

AB26

MB_DM4

E25

MB_DM3

A22

MB_DM2

B16

MB_DM1

A12

MB_DM0

AF12

MB_DQS_H7

AE12

MB_DQS_L7

AE16

MB_DQS_H6

AD16

MB_DQS_L6

AF21

MB_DQS_H5

AF22

MB_DQS_L5

AC25

MB_DQS_H4

AC26

MB_DQS_L4

F26

MB_DQS_H3

E26

MB_DQS_L3

A24

MB_DQS_H2

A23

MB_DQS_L2

D16

MB_DQS_H1

C16

MB_DQS_L1

C12

MB_DQS_H0

B12

MB_DQS_L0

FOX_PZ63823-284S-41F

Athlon 64 S1
Processor Socket

JP27C

MA_DATA63
MA_DATA62
MA_DATA61
MA_DATA60
MA_DATA59
MA_DATA58
MA_DATA57
MA_DATA56
MA_DATA55
MA_DATA54
MA_DATA53
MA_DATA52
MA_DATA51
MA_DATA50
MA_DATA49
MA_DATA48
MA_DATA47
MA_DATA46
MA_DATA45
MA_DATA44
MA_DATA43
MA_DATA42
MA_DATA41
MA_DATA40
MA_DATA39
MA_DATA38
MA_DATA37
MA_DATA36
MA_DATA35
MA_DATA34
MA_DATA33
MA_DATA32
MA_DATA31
MA_DATA30
MA_DATA29
MA_DATA28
MA_DATA27
MA_DATA26
MA_DATA25
MA_DATA24
MA_DATA23
MA_DATA22
MA_DATA21
MA_DATA20
MA_DATA19
MA_DATA18
MA_DATA17
MA_DATA16
MA_DATA15
MA_DATA14

DDRII Data

MA_DATA13
MA_DATA12
MA_DATA11
MA_DATA10

MA_DATA9
MA_DATA8
MA_DATA7
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MA_DATA2
MA_DATA1
MA_DATA0

MA_DM7
MA_DM6
MA_DM5
MA_DM4
MA_DM3
MA_DM2
MA_DM1
MA_DM0

MA_DQS_H7

MA_DQS_L7

MA_DQS_H6

MA_DQS_L6

MA_DQS_H5

MA_DQS_L5

MA_DQS_H4

MA_DQS_L4

MA_DQS_H3

MA_DQS_L3

MA_DQS_H2

MA_DQS_L2

MA_DQS_H1

MA_DQS_L1

MA_DQS_H0

MA_DQS_L0

AA12
AB12
AA14
AB14
W11
Y12
AD13
AB13
AD15
AB15
AB17
Y17
Y14
W14
W16
AD17
Y18
AD19
AD21
AB21
AB18
AA18
AA20
Y20
AA22
Y22
W21
W22
AA21
AB22
AB24
Y24
H22
H20
E22
E21
J19
H24
F22
F20
C23
B22
F18
E18
E20
D22
C19
G18
G17
C17
F14
E14
H17
E17
E15
H15
E13
C13
H12
H11
G14
H14
F12
G12

Y13
AB16
Y19
AC24
F24
E19
C15
E12

W12
W13
Y15
W15
AB19
AB20
AD23
AC23
G22
G21
C22
C21
G16
G15
G13
H13

DDR_A_D63
DDR_A_D62
DDR_A_D61
DDR_A_D60
DDR_A_D59
DDR_A_D58
DDR_A_D57
DDR_A_D56
DDR_A_D55
DDR_A_D54
DDR_A_D53
DDR_A_D52
DDR_A_D51
DDR_A_D50
DDR_A_D49
DDR_A_D48
DDR_A_D47
DDR_A_D46
DDR_A_D45
DDR_A_D44
DDR_A_D43
DDR_A_D42
DDR_A_D41
DDR_A_D40
DDR_A_D39
DDR_A_D38
DDR_A_D37
DDR_A_D36
DDR_A_D35
DDR_A_D34
DDR_A_D33
DDR_A_D32
DDR_A_D31
DDR_A_D30
DDR_A_D29
DDR_A_D28
DDR_A_D27
DDR_A_D26
DDR_A_D25
DDR_A_D24
DDR_A_D23
DDR_A_D22
DDR_A_D21
DDR_A_D20
DDR_A_D19
DDR_A_D18
DDR_A_D17
DDR_A_D16
DDR_A_D15
DDR_A_D14
DDR_A_D13
DDR_A_D12
DDR_A_D11
DDR_A_D10
DDR_A_D9
DDR_A_D8
DDR_A_D7
DDR_A_D6
DDR_A_D5
DDR_A_D4
DDR_A_D3
DDR_A_D2
DDR_A_D1
DDR_A_D0

DDR_A_DM7
DDR_A_DM6
DDR_A_DM5
DDR_A_DM4
DDR_A_DM3
DDR_A_DM2
DDR_A_DM1
DDR_A_DM0

DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS0
DDR_A_DQS#0

DDR_A_D[63..0] <8>

DDR_A_DQS7 <8>
DDR_A_DQS#7 <8>
DDR_A_DQS6 <8>
DDR_A_DQS#6 <8>
DDR_A_DQS5 <8>
DDR_A_DQS#5 <8>
DDR_A_DQS4 <8>
DDR_A_DQS#4 <8>
DDR_A_DQS3 <8>
DDR_A_DQS#3 <8>
DDR_A_DQS2 <8>
DDR_A_DQS#2 <8>
DDR_A_DQS1 <8>
DDR_A_DQS#1 <8>
DDR_A_DQS0 <8>
DDR_A_DQS#0 <8>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/5/4 2008/5/4

C

Compal Secret Data

Deciphered Date

Title

S1g1 DDRII I/F

Size Document Number Rev

Custom

IALAA-Minnesota10A LA3631P

D

Date: Sheet

545Monday, May 14, 2007

E

of

1A

5

100U_D2_10VM

+2.5VS

C119

A:Need to re-Link "SGN00000200"

R87

H_PWRGD

12

H_PWRGD<16>

D D

680_0402_5%

A:PA_IXP600AD12

LDT_STOP#<11,16>

680_0402_5%

LDT_RST#<16>

680_0402_5%

C C

LDT_STOP# CPU_SIC

R89

1 2

A:PA_IXP600AD12

LDT_RST#

R44

1 2

A:PA_IXP600AD12

CPUCLK0_H<13>

CPUCLK0_L< 13>

+1.8V

R86 510_0402_5%

R48 510_0402_5%
R49 300_0402_5%
R50 300_0402_5%

Thermal Sensor
GMT G781P8F

1

C111

B B

A A

2200P_0402_50V7K

EC_SMB_CK2<15,30>
EC_SMB_DA2<15,30>

2

B: Change to GM T G 7 81P8F from DVT.

THERMDA_CPU
THERMDC_CPU

U6

2

DXP+

3

DXN-

8

SCLK

7

SDATA

G781P8F_MSOP8

ALERT#

THERM#

VCC

GND

1
6
4
5

4

L16

1 2

FBM_L11_201209_300L_0805

1

+

2

1 2

C547

1 2

C545 3900P_0402_50V7K

CPU_TEST25_H_BYPASSCLK_H

12

CPU_TEST25_L_BYPASSCLK_L

12
12
12

+3VS

1

2

+2.5VDDA

1

C1324.7U_0805_10V4Z

2

+1.2V_HT

3900P_0402_50V7K

12

R333
169_0402_1%

CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1

C105

0.1U_0402_16V4Z

VDDA=300mA

3300P_0402_50V7K

1

1

2

R53 44.2_0402_1%
R54 44.2_0402_1%

R53&R54 place them to CPU within 1"

CPU_VCC_SENSE<42>
CPU_VSS_SENSE<42>

CPU_CLKIN_SC_P
CPU_CLKIN_SC_N

C139

C131

0.22U_0603_16V4Z

2

LDT_RST#
H_PWRGD
LDT_STOP#

R332 300_0402_5%

1 2
1 2

VDDIOFB_H<40>

CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1

12

TP1

CPU_DBRDY
CPU_TMS

CPU_TCK
CPU_TRST#
CPU_TDI

TP4
TP5
TP6
TP3
TP11

THERMDC_CPU
THERMDA_CPU

CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO

NOTE: HD T TE RM INATION IS REQU IRED
FOR REV. Ax SILICON ONLY.

3

CPU_HTREF1
CPU_HTREF0

+1.8V

R77220_0402_5%@

12

F8

VDDA2

F9

VDDA1

B7

RESET_L

A7

PWROK

F10

LDTSTOP_L

AF4

SIC

AF5

SID

P6

HTREF1

R6

HTREF0

F6

VDD_FB_H

E6

VDD_FB_L

W9

VDDIO_FB_H

Y9

VDDIO_FB_L

A9

CLKIN_H

A8

CLKIN_L

G10

DBRDY

AA9

TMS

AC9

TCK

AD9

TRST_L

AF9

TDI

E9

TEST25_H

E8

TEST25_L

G9

TEST19

H10

TEST18

AA7

TEST13

C2

TEST9

D7

TEST17

E7

TEST16

F7

TEST15

C7

TEST14

AC8

TEST12

C3

TEST7

AA6

TEST6

W7

THERMDC

W8

THERMDA

Y6

TEST3

AB6

TEST2

P20

RSVD0

P19

RSVD1

N20

RSVD2

N19

RSVD3

R26

RSVD4

R25

RSVD5

P22

RSVD6

R22

RSVD7

FOX_PZ63823-284S-41F

R75220_0402_5%@

R76220_0402_5%@

12

12

12

R74220_0402_5%@

12

CPU_PRESENT_L

R73220_0402_5%@

JP27D

THERMTRIP_L

PROCHOT_L

VID5
VID4
VID3
VID2
VID1
VID0

PSI_L

DBREQ_L

TDO

TEST29_H

TEST29_L

TEST24
TEST23

MISC

TEST22
TEST21
TEST20

TEST28_H

TEST28_L

TEST27
TEST26
TEST10

TEST8

RSVD8
RSVD9

RSVD10
RSVD11

RSVD12
RSVD13
RSVD14

RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20

2

+1.8V

CPU_THERMTRIP#_R

AF6
AC7

A5
C6
A6
A4
C5
B5

CPU_PRESENT#

AC6
A3

E10

AE9

CPU_TEST29_H_FBCLKOUT_P

C9

CPU_TEST29_L_FBCLKOUT_N

C8

ROUTE AS 80 Ohm DIFFER EN T IAL PAIR
PLACE IT CLOSE TO CPU WITHIN 1"

AE7
AD7
AE8
AB8
AF7

J7
H8
AF8
AE6
K8
C4

H16
B18

B3
C1

H6
G6
D5

R24
W18
R23
AA8
H18
H19

1 2

R37 10K_0402_5%

1 2

R38 300_0402_5%

CPU_PROCHOT#_1.8

CPU_DBREQ#

CPU_TDO

TP8
TP9
TP10

CPU_TEST21_SCANEN

TP7

CPU_TEST26_BURNIN#

VID5 <42>
VID4 <42>
VID3 <42>
VID2 <42>
VID1 <42>
VID0 <42>

+1.8V

TP15

PSI# <42>

HDT Connector

JP9

2

1

4

3

6

5

8

7

10

9

12

11

14

13

16

15

18

17

20

19

22

21

2423
26

SAMTEC_ASP-68200-07

@

HDT_RST#

SN74LVC08APW_TSSOP14

C:Update THERMTRIP# control circuit.

D39

2 1

CH751H-40PT_SOD323-2

B

2

Q10

E

3 1

C

MMBT3904_SOT23-3

R41 10K_0402_5%@

1 2

R43 300_0402_5%

CPU_PROCHOT#_1.8

R88

80.6_0402_1%

1 2

+3VS

14

U20D

11

O

7

12

12

P

A

13

B

G

R35

1 2

0_0402_5%
R36

1 2

0_0402_5%

@

B

2

E

3 1

MMBT3904_SOT23-3@

VID1
CPU_PRESENT#
CPU_TEST26_BURNIN#

CPU_TEST21_SCANEN

LDT_RST#

+3V_SB

R490

Q11

1 2

C

1

PCIRST# <16,22>

MAINPWON <36,37,39>
H_THERMTRIP# <16>

MP:Reserve pull up resistor
R490 for H_PROCHOT#

10K_0402_5%

12

@

R42

0_0402_5%

@

R47 300_0402_5%
R56 1K_0402_5%
R57 300_0402_5%

R55 300_0402_5%

SB_PWRGD <16,30>

1 2
1 2
1 2

1 2

H_PROCHOT# <16>

+1.8V

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/5/4 2008/5/4

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

S1g1 CTRL

IALAA-Minnesota10A LA3631P

1A

645Wednesday, May 16, 2007

1

of

5

VDD(+CPU_CORE) decoupling.

+CPU_CORE

D D

1

+

C544

2

45level

820U_E9_2_5V_M_R745@

1

+

C576

820U_E9_2_5V_M_R745@

2

1

+

C560
330U_D2_2.5VY_R9M

2

Near CPU Socket

+CPU_CORE

1

C123
22U_0805_6.3V6M

2

+CPU_CORE

1

C143

0.22U_0603_16V4Z

C C

2

1

C146
22U_0805_6.3V6M

2

1

C138

0.22U_0603_16V4Z

2

1

C125
22U_0805_6.3V6M

2

+CPU_CORE +CPU_CORE

1

C144
22U_0805_6.3V6M

2

1

C129

0.01U_0402_25V4Z

2

VDDIO decoupling.

+1.8V

1

C153
22U_0805_6.3V6M

2

1

C152
22U_0805_6.3V6M

2

Under CPU Socket

B B

+1.8V

1

C163

0.22U_0603_16V4Z

2

+1.8V +1.8V

1

C159

0.01U_0402_25V4Z

2

A A

+1.8V

1

C183

4.7U_0805_10V4Z

2

Between CPU Socket and DIMM

1

C177

0.22U_0603_16V4Z

2

1

C160

0.01U_0402_25V4Z

2

1

C182

4.7U_0805_10V4Z

2

5

+1.8V

1

C155

0.22U_0603_16V4Z

2

1

C164

0.22U_0603_16V4Z

2

180PF Qt'y follow the distance between
CPU socket and DIMM0. <2.5inch>

1

C157
180P_0402_50V8J

2

1

C162

4.7U_0805_10V4Z

2

1

C154

0.22U_0603_16V4Z

2

1

C172

0.22U_0603_16V4Z

2

1

C158
180P_0402_50V8J

2

A: Add C165 and C176
to follow AMD Layout
review recommand for
EMI

1

C161

4.7U_0805_10V4Z

2

4

1

+

C602
330U_D2_2.5VY_R9M

2

1

C122
22U_0805_6.3V6M

2

1

C136
180P_0402_50V8J

2

4

1

C124
22U_0805_6.3V6M

2

Under CPU Socket

1

C165
180P_0402_50V8J

2

1

C: Change to NBO CAP

+

C652
220U_Y_4VM

@

2

1

2

3

+CPU_CORE +CPU_CORE

AC4

VDD1

AD2

VDD2

G4

VDD3

H2

VDD4

J9

VDD5

J11

VDD6

J13

VDD7

K6

VDD8

K10

VDD9

K12

VDD10

K14

VDD11

L4

VDD12

L7

VDD13

L9

VDD14

L11

VDD15

L13

VDD16

M2

VDD17

M6

VDD18

M8

VDD19

M10

VDD20

N7

VDD21

N9

VDD22

N11

VDD23

1

C145
22U_0805_6.3V6M

2

1

C126
22U_0805_6.3V6M

2

1

C142
22U_0805_6.3V6M

2

VTT decoupling.

+0.9V

1

C556

4.7U_0805_10V4Z

2

C176
180P_0402_50V8J

+0.9V

1

C140

4.7U_0805_10V4Z

2

Near CPU Socket Left side.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

C555

4.7U_0805_10V4Z

2

Near CPU Socket Right side.

1

C137

4.7U_0805_10V4Z

2

1

C548

0.22U_0603_16V4Z

2

1

C133

0.22U_0603_16V4Z

2

2007/5/4 2008/5/4

3

P8

VDD24

P10

VDD25

R4

VDD26

R7

VDD27

R9

VDD28

R11

VDD29

T2

VDD30

T6

VDD31

T8

VDD32

T10

VDD33

T12

VDD34

T14

VDD35

U7

VDD36

U9

VDD37

U11

VDD38

U13

VDD39

V6

VDD40

V8

VDD41

V10

VDD42

FOX_PZ63823-284S-41F

Athlon 64 S1
Processor Socket

+0.9V

1

C: Change to NBO CAP

+

2

1

C549

0.22U_0603_16V4Z

2

1

C134

0.22U_0603_16V4Z

2

Compal Secret Data

Deciphered Date

JP27E

VDD43
VDD44
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51
VDD52
VDD53
VDD54

VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9

VDDIO10

Power

VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27

Near Power Supply

C577
220U_Y_4VM

2

V12
V14
W4
Y2
J15
K16
L15
M16
P16
T16
U15
V16

H25
J17
K18
K21
K23
K25
L17
M18
M21
M23
M25
N17
P18
P21
P23
P25
R17
T18
T21
T23
T25
U17
V18
V21
V23
V25
Y25

1

C559
1000P_0402_25V8J

2

1

C130
1000P_0402_25V8J

2

2

+1.8V

1

C554
1000P_0402_25V8J

2

1

C127
1000P_0402_25V8J

2

1

AA4

VSS1

AA11

VSS2

AA13

VSS3

AA15

VSS4

AA17

VSS5

AA19

VSS6

AB2

VSS7

AB7

VSS8

AB9

VSS9

AB23

VSS10

AB25

VSS11

AC11

VSS12

AC13

VSS13

AC15

VSS14

AC17

VSS15

AC19

VSS16

AC21

VSS17

AD6

VSS18

AD8

VSS19

AD25

VSS20

AE11

VSS21

AE13

VSS22

AE15

VSS23

AE17

VSS24

AE19

VSS25

AE21

VSS26

AE23

VSS27

B4

VSS28

B6

VSS29

B8

VSS30

B9

VSS31

B11

VSS32

B13

VSS33

B15

VSS34

B17

VSS35

B19

VSS36

B21

VSS37

B23

VSS38

B25

VSS39

D6

VSS40

D8

VSS41

D9

VSS42

D11

VSS43

D13

VSS44

D15

VSS45

D17

VSS46

D19

VSS47

D21

VSS48

D23

VSS49

D25

VSS50

E4

VSS51

F2

VSS52

F11

VSS53

F13

VSS54

F15

VSS55

F17

VSS56

F19

VSS57

F21

VSS58

F23

VSS59

F25

VSS60

H7

VSS61

H9

VSS62

H21

VSS63

H23

VSS64

J4

VSS65

FOX_PZ63823-284S-41F

Athlon 64 S1
Processor Socket

1

C552
180P_0402_50V8J

2

1

C147
180P_0402_50V8J

2

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

IALAA-Minnesota10A LA3631P

JP27F

J6

VSS66

J8

VSS67

J10

VSS68

J12

VSS69

J14

VSS70

J16

VSS71

J18

VSS72

K2

VSS73

K7

VSS74

K9

VSS75

K11

VSS76

K13

VSS77

K15

VSS78

K17

VSS79

L6

VSS80

L8

VSS81

L10

VSS82

L12

VSS83

L14

VSS84

L16

VSS85

L18

VSS86

M7

VSS87

M9

VSS88

M11

VSS89

M17

VSS90

N4

VSS91

N8

VSS92

N10

VSS93

N16

VSS94

N18

VSS95

P2

VSS96

P7

VSS97

P9

VSS98

P11

VSS99

P17

VSS100

R8

VSS101

R10

Ground

VSS102

R16

VSS103

R18

VSS104

T7

VSS105

T9

VSS106

T11

VSS107

T13

VSS108

T15

VSS109

T17

VSS110

U4

VSS111

U6

VSS112

U8

VSS113

U10

VSS114

U12

VSS115

U14

VSS116

U16

VSS117

U18

VSS118

V2

VSS119

V7

VSS120

V9

VSS121

V11

VSS122

V13

VSS123

V15

VSS124

V17

VSS125

W6

VSS126

Y21

VSS127

Y23

VSS128

N6

VSS129

1

C550
180P_0402_50V8J

2

1

C128
180P_0402_50V8J

2

S1g1 PWR & GND

745Monday, May 14, 2007

1

of

1A

5

DDR_A_D0
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D3

DDR_A_D8

D D

C C

B B

A A

DDR_CKE0_DIMMA<5>
DDR_CS2_DIMMA#<5>

DDR_A_BS#2<5>

DDR_A_BS#0<5>
DDR_A_WE#<5>

DDR_A_CAS#<5>
DDR_CS1_DIMMA#<5>

DDR_A_ODT1<5>

SMB_CK_DAT0<9,13,17,24,28>
SMB_CK_CLK0<9,13,17,24,28>

+3VS

DDR_A_D9
DDR_A_DQS#1

DDR_A_DQS1
DDR_A_D10

DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_DM3

DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA
DDR_CS2_DIMMA#

DDR_A_BS#2
DDR_A_MA12

DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS#0
DDR_A_WE#

DDR_A_CAS#
DDR_CS1_DIMMA#

DDR_A_ODT1
DDR_A_D32

DDR_A_D33
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D34

DDR_A_D35
DDR_A_D40

DDR_A_D41
DDR_A_DM5
DDR_A_D42

DDR_A_D43
DDR_A_D48

DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_DM7
DDR_A_D58

DDR_A_D59

C237

0.1U_0402_16V4Z

5

+DIMM_VREF +1.8V

JP31

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

1

2

VDDSPD

P-TWO_A5692A-A0G16-N

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

VSS

CK0

CK0#

VSS
DQ14
DQ15

VSS

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

A11

VDD

VDD

BA1

RAS#

S0#

VDD

ODT0

NC/A13

VDD

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

CK1

CK1#

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

SAO

SA1

4

NC

A7
A6

A4
A2
A0

NC

+1.8V+1.8V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196

R121 0_0402_5%

198

R123 0_0402_5%

200

DDR_A_D4
DDR_A_D5

DDR_A_DM0
DDR_A_D6

DDR_A_D7
DDR_A_D12

DDR_A_D13
DDR_A_DM1

DDR_A_D14
DDR_A_D15

DDR_A_D20
DDR_A_D21

DDR_A_DM2
DDR_A_D22

DDR_A_D23
DDR_A_D28

DDR_A_D29
DDR_A_DQS#3

DDR_A_DQS3
DDR_A_D30

DDR_A_D31
DDR_CKE1_DIMMA
DDR_A_MA15

DDR_A_MA14
DDR_A_MA11

DDR_A_MA7
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS#1
DDR_A_RAS#
DDR_CS0_DIMMA#

DDR_A_ODT0
DDR_A_MA13

DDR_CS3_DIMMA#
DDR_A_D36

DDR_A_D37
DDR_A_DM4
DDR_A_D38

DDR_A_D39
DDR_A_D44

DDR_A_D45
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D46

DDR_A_D47
DDR_A_D52

DDR_A_D53

DDR_A_DM6
DDR_A_D54

DDR_A_D55
DDR_A_D60

DDR_A_D61
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D63

12
12

Security Classification

DDR_A_CLK1 <5>
DDR_A_CLK#1 <5>

DDR_CKE1_DIMMA <5>

DDR_A_BS#1 <5>
DDR_A_RAS# <5>
DDR_CS0_DIMMA# <5>

DDR_A_ODT0 <5>

DDR_CS3_DIMMA# <5>

DDR_A_CLK2 <5>
DDR_A_CLK#2 <5>

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

DDR_A_D[0..63]

DDR_A_DM[0..7]
DDR_A_DQS[0..7]
DDR_A_MA[0..15]

DDR_A_DQS#[0..7]

2007/5/4 2008/5/4

3

DDR_A_DM[0..7] <5>

DDR_A_DQS[0..7] <5>

DDR_A_MA[0..15] <5>

DDR_A_DQS#[0..7] <5>

1

C243

2

1000P_0402_25V8J

DDR_A_D[0..63] <5>

+1.8V+DIMM_VREF

1

C249

2

1 2

0.1U_0402_16V4Z

1 2

Compal Secret Data

Deciphered Date

R148
1K_0402_1%

R132
1K_0402_1%

2

DDR_A_MA2
DDR_A_MA11
DDR_A_MA6
DDR_A_MA7

B: RP4 swap for Express Card.

DDR_CKE0_DIMMA
DDR_CS2_DIMMA#
DDR_A_BS#2

DDR_A_MA4
DDR_A_MA0
DDR_A_BS#1
DDR_CS0_DIMMA#

B: RP3 swap for Express Card.

DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_BS#0

C: RP20 swap for DDR Shielding\.

DDR_A_CAS#
DDR_A_WE#
DDR_CS1_DIMMA#
DDR_A_ODT1

DDR_CS3_DIMMA#
DDR_A_ODT0
DDR_A_MA13
DDR_A_RAS#

DDR_A_MA14
DDR_A_MA15
DDR_CKE1_DIMMA

2

1

+0.9V

RP6

18
27
36

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

47_0804_8P4R_5%

45

RP4

18
27
36
45

RP7

18
27
36
45

RP3

18
27
36
45

RP21

18
27
36
45

RP20

18
27
36
45

RP5

18
27
36
45

RP8

18
27
36
45

Title

DDRII SO-DIMM 0

Size Document Number Rev

Custom

IALAA-Minnesota10A LA3631P

Date: Sheet

1 2

C238 0.1U_0402_16V4Z

1 2

C204 0.1U_0402_16V4Z

1 2

C290 0.1U_0402_16V4Z

1 2

C655 0.1U_0402_16V4Z

1 2

C274 0.1U_0402_16V4Z

1 2

C654 0.1U_0402_16V4Z

1 2

C196 0.1U_0402_16V4Z

1 2

C244 0.1U_0402_16V4Z

1 2

C254 0.1U_0402_16V4Z

1 2

C199 0.1U_0402_16V4Z

1 2

C232 0.1U_0402_16V4Z

1 2

C213 0.1U_0402_16V4Z

1 2

C185 0.1U_0402_16V4Z

1 2

C218 0.1U_0402_16V4Z

1 2

C293 0.1U_0402_16V4Z

1 2

C258 0.1U_0402_16V4Z

1

845Monday, May 14, 2007

1A

of

+DIMM_VREF

1

C203

2

D D

C C

B B

A A

DDR_CKE0_DIMMB<5>
DDR_CS2_DIMMB#<5>

DDR_B_BS#2<5>

DDR_B_BS#0<5>
DDR_B_WE#<5>

DDR_B_CAS#<5>
DDR_CS1_DIMMB#<5>

DDR_B_ODT1<5>

1000P_0402_25V8J

SMB_CK_DAT0<8,13,17,24,28>
SMB_CK_CLK0<8,13,17,24,28>

5

DDR_B_D0
DDR_B_D1

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18 DDR_B_D22
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_DM3

DDR_B_D26
DDR_B_D27

DDR_CKE0_DIMMB
DDR_CS2_DIMMB#

DDR_B_BS#2
DDR_B_MA12

DDR_B_MA9

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10
DDR_B_BS#0
DDR_B_WE#

DDR_B_CAS# DDR_B_ODT0
DDR_CS1_DIMMB#

DDR_B_ODT1
DDR_B_D32

DDR_B_D33
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D35
DDR_B_D40

DDR_B_D41
DDR_B_DM5
DDR_B_D42

DDR_B_D43 DDR_B_D47
DDR_B_D48

DDR_B_D49 DDR_B_D53

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51 DDR_B_D55

DDR_B_D56
DDR_B_D57

DDR_B_DM7
DDR_B_D58

DDR_B_D59

+3VS

C207

0.1U_0402_16V4Z

5

+1.8V

1

2

JP33

1

VREF

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DQS0#

13

DQS0

15

VSS

17

DQ2

19

DQ3

21

VSS

23

DQ8

25

DQ9

27

VSS

29

DQS1#

31

DQS1

33

VSS

35

DQ10

37

DQ11

39

VSS

41

VSS

43

DQ16

45

DQ17

47

VSS

49

DQS2#

51

DQS2

53

VSS

55

DQ18

57

DQ19

59

VSS

61

DQ24

63

DQ25

65

VSS

67

DM3

69

NC

71

VSS

73

DQ26

75

DQ27

77

VSS

79

CKE0

81

VDD

83

NC

85

BA2

87

VDD

89

A12

91

A9

93

A8

95

VDD

97

A5

99

A3

101

A1

103

VDD

105

A10/AP

107

BA0

109

WE#

111

VDD

113

CAS#

115

NC/S1#

117

VDD

119

NC/ODT1

121

VSS

123

DQ32

125

DQ33

127

VSS

129

DQS4#

131

DQS4

133

VSS

135

DQ34

137

DQ35

139

VSS

141

DQ40

143

DQ41

145

VSS

147

DM5

149

VSS

151

DQ42

153

DQ43

155

VSS

157

DQ48

159

DQ49

161

VSS

163

NC,TEST

165

VSS

167

DQS6#

169

DQS6

171

VSS

173

DQ50

175

DQ51

177

VSS

179

DQ56

181

DQ57

183

VSS

185

DM7

187

VSS

189

DQ58

191

DQ59

193

VSS

195

SDA

197

SCL

199

VDDSPD

QTC_C111A-052SP31

4

VSS
DQ4
DQ5

VSS
DM0
VSS
DQ6
DQ7
VSS

DQ12
DQ13

VSS
DM1
VSS

CK0

CK0#

VSS

DQ14
DQ15

VSS

VSS

DQ20
DQ21

VSS
DM2

VSS

DQ22
DQ23

VSS

DQ28
DQ29

VSS

DQS3#

DQS3

VSS

DQ30
DQ31

VSS

NC/CKE1

VDD

NC/A15
NC/A14

VDD

A11

VDD

VDD

BA1

RAS#

S0#
VDD

ODT0

NC/A13

VDD
VSS

DQ36
DQ37

VSS
DM4
VSS

DQ38
DQ39

VSS

DQ44
DQ45

VSS

DQS5#

DQS5

VSS

DQ46
DQ47

VSS

DQ52
DQ53

VSS

CK1

CK1#

VSS
DM6
VSS

DQ54
DQ55

VSS

DQ60
DQ61

VSS

DQS7#

DQS7

VSS

DQ62
DQ63

VSS
SAO

SA1

4

3

+1.8V

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

42
44
46
48
50

NC

52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92

A7

94

A6

96
98

A4

100

A2

102

A0

104
106
108
110
112
114
116
118
120

NC

122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDR_B_D4
DDR_B_D5

DDR_B_DM0
DDR_B_D6

DDR_B_D7
DDR_B_D12

DDR_B_D13
DDR_B_DM1

DDR_B_D14
DDR_B_D15

DDR_B_D20
DDR_B_D21

DDR_B_DM2

DDR_B_D23
DDR_B_D28

DDR_B_D29
DDR_B_DQS#3

DDR_B_DQS3
DDR_B_D30

DDR_B_D31
DDR_CKE1_DIMMB
DDR_B_MA15

DDR_B_MA14
DDR_B_MA11

DDR_B_MA7
DDR_B_MA6DDR_B_MA8

DDR_B_MA4
DDR_B_MA2
DDR_B_MA0

DDR_B_BS#1
DDR_B_RAS#
DDR_CS0_DIMMB#

DDR_B_MA13
DDR_CS3_DIMMB#
DDR_B_D36

DDR_B_D37
DDR_B_DM4
DDR_B_D38

DDR_B_D39
DDR_B_D44

DDR_B_D45
DDR_B_DQS#5

DDR_B_DQS5
DDR_B_D46

DDR_B_D52

DDR_B_DM6
DDR_B_D54

DDR_B_D60
DDR_B_D61

DDR_B_DQS#7
DDR_B_DQS7

DDR_B_D62
DDR_B_D63

R423 4.7K_0402_5%

1 2

12

R427 0_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

DDR_B_D[0..63]

DDR_B_DM[0..7]
DDR_B_DQS[0..7]
DDR_B_MA[0..15]

DDR_B_DQS#[0..7]

DDR_B_CLK1 <5>
DDR_B_CLK#1 <5>

DDR_CKE1_DIMMB <5>

DDR_B_BS#1 <5>
DDR_B_RAS# <5>
DDR_CS0_DIMMB# <5>

DDR_B_ODT0 <5>

DDR_CS3_DIMMB# <5>

DDR_B_CLK2 <5>
DDR_B_CLK#2 <5>

+3VS

2007/5/4 2008/5/4

3

DDR_B_D[0..63] <5>

DDR_B_DM[0..7] <5>

DDR_B_DQS[0..7] <5>

DDR_B_MA[0..15] <5>

DDR_B_DQS#[0..7] <5>

Compal Secret Data

Deciphered Date

2

DDR_B_RAS#
DDR_B_BS#1
DDR_B_MA0
DDR_B_MA2

DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4

DDR_CS2_DIMMB#
DDR_B_BS#2
DDR_CKE0_DIMMB

DDR_B_MA5
DDR_B_MA8
DDR_B_MA9
DDR_B_MA12

DDR_B_MA3
DDR_B_MA1
DDR_B_MA10
DDR_B_BS#0

DDR_B_WE#
DDR_B_CAS#
DDR_CS1_DIMMB#
DDR_B_ODT1

DDR_CS3_DIMMB#
DDR_B_MA13
DDR_B_ODT0
DDR_CS0_DIMMB#

DDR_CKE1_DIMMB
DDR_B_MA15
DDR_B_MA14

2

1

RP23

47_0804_8P4R_5%

RP13

47_0804_8P4R_5%

RP10

47_0804_8P4R_5%

RP9

47_0804_8P4R_5%

RP11

47_0804_8P4R_5%

RP12

47_0804_8P4R_5%

RP22

47_0804_8P4R_5%

RP14

47_0804_8P4R_5%

Custom

+0.9V

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

18
27
36
45

Title

DDRII SO-DIMM 1

Size Document Number Rev

IALAA-Minnesota10A LA3631P

Date: Sheet

12

C246 0.1U_0402_16V4Z

1 2

C245 0.1U_0402_16V4Z

12

C261 0.1U_0402_16V4Z

1 2

C267 0.1U_0402_16V4Z

12

C257 0.1U_0402_16V4Z

1 2

C268 0.1U_0402_16V4Z

12

C277 0.1U_0402_16V4Z

1 2

C695 0.1U_0402_16V4Z

12

C222 0.1U_0402_16V4Z

1 2

C241 0.1U_0402_16V4Z

12

C229 0.1U_0402_16V4Z

1 2

C273 0.1U_0402_16V4Z

12

C658 0.1U_0402_16V4Z

1 2

C256 0.1U_0402_16V4Z

12

C215 0.1U_0402_16V4Z

1 2

C235 0.1U_0402_16V4Z

+1.8V

1

1A

945Monday, May 14, 2007

of

5

PCIE_GTX_C_MRX_P[0..15]<15>
PCIE_GTX_C_MRX_N[0..15]<15>

PCIE_GTX_C_MRX_P15
PCIE_GTX_C_MRX_N15
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P13

D D

C C

B B

PCIE_MRX_C_LANTX_P2<25>
PCIE_MRX_C_LANTX_N2<25>

PCIE_MRX_C_WLANTX_P3<24>
PCIE_MRX_C_WLANTX_N3<24>

PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_N0

SB_RX2P<16>
SB_RX2N<16>

SB_RX3P<16>
SB_RX3N<16>

SB_RX0P<16>
SB_RX0N<16>

SB_RX1P<16>
SB_RX1N<16>

PCIE_GTX_C_MRX_P[0..15]
PCIE_GTX_C_MRX_N[0..15]

U5B

G5

GFX_RX0P

G4

GFX_RX0N

J8

GFX_RX1P

J7

GFX_RX1N

J4

GFX_RX2P

J5

GFX_RX2N

L8

GFX_RX3P

L7

GFX_RX3N

L4

GFX_RX4P

L5

GFX_RX4N

M8

GFX_RX5P

M7

GFX_RX5N

M4

GFX_RX6P

M5

GFX_RX6N

P8

GFX_RX7P

P7

GFX_RX7N

P4

GFX_RX8P

P5

GFX_RX8N

R4

GFX_RX9P

R5

GFX_RX9N

R7

GFX_RX10P

R8

GFX_RX10N

U4

GFX_RX11P

U5

GFX_RX11N

W4

GFX_RX12P

W5

GFX_RX12N

Y4

GFX_RX13P

Y5

GFX_RX13N

V9

GFX_RX14P

W9

GFX_RX14N

AB7

GFX_RX15P

AB6

GFX_RX15N

Y7

GPP_RX2P

AA7

GPP_RX2N

AB9

GPP_RX3P

AA9

GPP_RX3N

W11

GPP_RX0P(SB_RX2P)

W12

GPP_RX0N(SB_RX2N)

AA11

GPP_RX1P(SB_RX3P)

AB11

GPP_RX1N(SB_RX3N)

W14

SB_RX0P

W15

SB_RX0N

AB12

SB_RX1P

AA12

SB_RX1N

AA14

PCE_ISET(NC)

AB14

PCE_TXISET(NC)

216MQA6AVA11FG_FCBGA465_RS690MVGAR1@

PART 2 OF 5

PCIE I/F GPP

PCIE I/F SB

GND2
For IALAA Only-­Change Layer Bridge for HOST3 CADOP/N[0..7]

A A

5

4

GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P

GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P

PCIE GFX I/F

GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N

GPP_TX2P
GPP_TX2N

GPP_TX3P
GPP_TX3N

GPP_TX0P(SB_TX2P)
GPP_TX0N(SB_TX2N)

GPP_TX1P(SB_TX3P)
GPP_TX1N(SB_TX3N)

SB_TX0P
SB_TX0N

SB_TX1P
SB_TX1N

PCE_PCAL(PCE_CALRP)

PCE_NCAL(PCE_CALRN)

1 2

C70 0.01U_0402_25V4Z@

1 2

C69 0.01U_0402_25V4Z@

4

PCIE_MTX_GRX_P15

J1

PCIE_MTX_GRX_N15

H2

PCIE_MTX_GRX_P14

K2

PCIE_MTX_GRX_N14

K1

PCIE_MTX_GRX_P13

K3

PCIE_MTX_GRX_N13

L3

PCIE_MTX_GRX_P12

L1

PCIE_MTX_GRX_N12

L2

PCIE_MTX_GRX_P11

N2

PCIE_MTX_GRX_N11

N1

PCIE_MTX_GRX_P10

P2

PCIE_MTX_GRX_N10

P1

PCIE_MTX_GRX_P9

P3

PCIE_MTX_GRX_N9

R3

PCIE_MTX_GRX_P8

R1

PCIE_MTX_GRX_N8

R2

PCIE_MTX_GRX_P7

T2

PCIE_MTX_GRX_N7

U1

PCIE_MTX_GRX_P6

V2

PCIE_MTX_GRX_N6

V1

PCIE_MTX_GRX_P5

V3

PCIE_MTX_GRX_N5

W3

PCIE_MTX_GRX_P4

W1

PCIE_MTX_GRX_N4

W2

PCIE_MTX_GRX_P3

Y2

PCIE_MTX_GRX_N3

AA1

PCIE_MTX_GRX_P2

AA2

PCIE_MTX_GRX_N2

AB2

PCIE_MTX_GRX_P1

AB1

PCIE_MTX_GRX_N1

AC1

PCIE_MTX_GRX_P0

AE3

PCIE_MTX_GRX_N0

AE4

PCIE_MTX_LANRX_P2

AD4

PCIE_MTX_LANRX_N2

AE5

PCIE_MTX_WLANRX_P3

AD5

PCIE_MTX_WLANRX_N3

AD6

SB_TX2P_C

AD8

SB_TX2N_C

AE8

SB_TX3P_C

AD7

SB_TX3N_C

AE7

SB_TX0P_C

AE9

SB_TX0N_C

AD10

SB_TX1P_C

AC8

SB_TX1N_C

AD9
AD11

AE11

3

PCIE_MTX_C_GRX_P[0..15]

PCIE_MTX_C_GRX_N[0..15]

C99 0.1U_0402_16V7KVGA@

C100 0.1U_0402_16V7KVGA@

1 2

C97 0.1U_0402_16V7KVGA@

1 2

C95 0.1U_0402_16V7KVGA@

1 2

C91 0.1U_0402_16V7KVGA@

1 2

C89 0.1U_0402_16V7KVGA@

1 2

C84 0.1U_0402_16V7KVGA@

1 2

C82 0.1U_0402_16V7KVGA@

1 2

C80 0.1U_0402_16V7KVGA@

1 2

C78 0.1U_0402_16V7KVGA@

1 2

C76 0.1U_0402_16V7KVGA@

1 2

C73 0.1U_0402_16V7KVGA@

1 2

C71 0.1U_0402_16V7KVGA@

1 2

C64 0.1U_0402_16V7KVGA@

1 2

C60 0.1U_0402_16V7KVGA@

1 2

C56 0.1U_0402_16V7KVGA@

1 2

C45 0.1U_0402_16V7KVGA@

1 2

C53 0.1U_0402_16V7K

1 2

C52 0.1U_0402_16V7K

1 2

C44 0.1U_0402_16V7KWLAN@

1 2

C43 0.1U_0402_16V7KWLAN@

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2

C48 0.1U_0402_16V7K
C49 0.1U_0402_16V7K

C51 0.1U_0402_16V7K
C50 0.1U_0402_16V7K

C40 0.1U_0402_16V7K
C39 0.1U_0402_16V7K

C42 0.1U_0402_16V7K
C41 0.1U_0402_16V7K

R22 562_0402_1%

1 2

R23 2K_0402_1%

1 2

C1445 Near H_CADOP/N[2..4] and
H_CLKOP/N0 near NB TOP Side

C1446 Near H_CADOP/N[5..7] and
H_CTLOP/N0 near NB TOP Side

1 2

C98 0.1U_0402_16V7KVGA@

1 2

C96 0.1U_0402_16V7KVGA@

1 2

C94 0.1U_0402_16V7KVGA@

1 2

C90 0.1U_0402_16V7KVGA@

1 2

C88 0.1U_0402_16V7KVGA@

1 2

C83 0.1U_0402_16V7KVGA@

1 2

C81 0.1U_0402_16V7KVGA@

1 2

C79 0.1U_0402_16V7KVGA@

1 2

C77 0.1U_0402_16V7KVGA@

1 2

C74 0.1U_0402_16V7KVGA@

1 2

C72 0.1U_0402_16V7KVGA@

1 2

C68 0.1U_0402_16V7KVGA@

1 2

C63 0.1U_0402_16V7KVGA@

1 2

C59 0.1U_0402_16V7KVGA@

1 2

C46 0.1U_0402_16V7KVGA@

1 2

SB_TX2P <16>
SB_TX2N <16>

SB_TX3P <16>
SB_TX3N <16>

SB_TX0P <16>
SB_TX0N <16>

SB_TX1P <16>
SB_TX1N <16>

+VDDA12_PKG2

PCIE_MTX_C_LANRX_P2 <25>
PCIE_MTX_C_LANRX_N2 <25>

PCIE_MTX_C_WLANRX_P3 <24>

PCIE_MTX_C_WLANRX_N3 <24>

GND1

H_CLKOP1<4>
H_CLKON1<4>

H_CLKOP0<4>
H_CLKON0<4>

H_CTLOP0<4>
H_CTLON0<4>

R46 49.9_0402_1%

+VDDHT_PKG

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/5/4 2008/5/4

3

R40 49.9_0402_1%

Compal Secret Data

PCIE_MTX_C_GRX_P[0..15] <15>
PCIE_MTX_C_GRX_N[0..15] <15>

PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0

H_CADOP15
H_CADON15
H_CADOP14
H_CADON14
H_CADOP13
H_CADON13
H_CADOP12
H_CADON12
H_CADOP11
H_CADON11
H_CADOP10
H_CADON10

H_CADOP9
H_CADON9
H_CADOP8
H_CADON8

H_CADOP7
H_CADON7
H_CADOP6
H_CADON6
H_CADOP5
H_CADON5
H_CADOP4
H_CADON4
H_CADOP3
H_CADON3
H_CADOP2
H_CADON2
H_CADOP1
H_CADON1
H_CADOP0
H_CADON0

H_CTLON0

1 2
1 2

Deciphered Date

2

H_CADOP[0..15]<4>
H_CADON[0..15]<4> H_CADIN[0..15] <4>

U5A

R19

HT_RXCAD15P

R18

HT_RXCAD15N

R21

HT_RXCAD14P

R22

HT_RXCAD14N

U22

HT_RXCAD13P

U21

HT_RXCAD13N

U18

HT_RXCAD12P

U19

HT_RXCAD12N

W19

HT_RXCAD11P

W20

HT_RXCAD11N

AC21

HT_RXCAD10P

AB22

HT_RXCAD10N

AB20

HT_RXCAD9P

AA20

HT_RXCAD9N

AA19

HT_RXCAD8P

Y19

HT_RXCAD8N

T24

HT_RXCAD7P

R25

HT_RXCAD7N

U25

HT_RXCAD6P

U24

HT_RXCAD6N

V23

HT_RXCAD5P

U23

HT_RXCAD5N

V24

HT_RXCAD4P

V25

HT_RXCAD4N

AA25

HT_RXCAD3P

AA24

HT_RXCAD3N

AB23

HT_RXCAD2P

AA23

HT_RXCAD2N

AB24

HT_RXCAD1P

AB25

HT_RXCAD1N

AC24

HT_RXCAD0P

AC25

HT_RXCAD0N

W21

HT_RXCLK1P

W22

HT_RXCLK1N

Y24

HT_RXCLK0P

W25

HT_RXCLK0N

P24

HT_RXCTLP

P25

HT_RXCTLN

A24

HT_RXCALP

C24

HT_RXCALN

216MQA6AVA11FG_FCBGA465_RS690MVGAR1@

2

1

H_CADON[0..15]

PART 1 OF 5

HT_TXCAD15P
HT_TXCAD15N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD10P
HT_TXCAD10N

HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD8P
HT_TXCAD8N

HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD0P
HT_TXCAD0N

HT_TXCLK1P

HT_TXCLK1N

HT_TXCLK0P

HT_TXCLK0N

HT_TXCTLP
HT_TXCTLN

HT_TXCALP
HT_TXCALN

H_CADIP[0..15]H_CADOP[0..15]
H_CADIN[0..15]

P21
P22
P18
P19
M22
M21
M18
M19
L18
L19
G22
G21
J20
J21
F21
F22

N24
N25
L25
M24
K25
K24
J23
K23
G25
H24
F25
F24
E23
F23
E24
E25

L21
L22

J24
J25

H_CTLIP0H_CTLOP0

N23

H_CTLIN0

P23

R39 100_0402_1%

C25
D24

H_CADIP15
H_CADIN15
H_CADIP14
H_CADIN14
H_CADIP13
H_CADIN13
H_CADIP12
H_CADIN12
H_CADIP11
H_CADIN11
H_CADIP10
H_CADIN10

H_CADIP9

H_CADIN9

H_CADIP8

H_CADIN8

H_CADIP7

H_CADIN7

H_CADIP6

H_CADIN6

H_CADIP5

H_CADIN5

H_CADIP4

H_CADIN4

H_CADIP3

H_CADIN3

H_CADIP2

H_CADIN2

H_CADIP1

H_CADIN1

H_CADIP0

H_CADIN0

1 2

H_CADIP[0..15] <4>

H_CLKIP1 <4>
H_CLKIN1 <4>

H_CLKIP0 <4>
H_CLKIN0 <4>

H_CTLIP0 <4>

H_CTLIN0 <4>

HYPER TRANSPORT I/F

Title

Size Document Number Rev

Custom

Date: Sheet

RX690/RS690MC HT/VMEM

IALAA-Minnesota10A LA3631P

10 45Monday, May 14, 2007

1

of

1A

+1.8VS

1

1

0.1U_0402_16V4Z

+1.8VS +AVDDQ

1 2

MBC1608121YZF_0603

2.2U_0603_6.3V4Z

+1.8VS +NB_PLLVDD

1 2

MBK2012221YZF 0805

2.2U_0603_6.3V4Z

+1.8VS +NB_HTPVDD

1 2

MBC1608121YZF_0603

+1.2V_HT +PLLVDD12

1 2

MBC1608121YZF_0603

L15

2.2U_0603_6.3V4Z

C515

2

2

L12

1

C113

2

GND to A22

L13

1

C114

L52

10U_0805_10V4Z@

1

C522
1U_0402_6.3V4Z

2

2

GND to B10

1

C514

2

1

C117

2

+3VS

R64 4.7K_0402_5%UMA@
R62 4.7K_0402_5%UMA@

1 2

R70 10K_0402_5%

1 2

R63 10K_0402_5%@

POWER PLAY HI: 1.2V
LOW: 1.0V
Won't Support in IALAA

AVDDI=250mA

C519

2.2U_0603_6.3V4Z

GND to B20

AVDDQ=200mA

1

C523

1U_0402_6.3V4Z

2

PLLVDD18=625mA

+3VS

1 2

R68 24K_0402_5%HDMI@

1 2

R61 24K_0402_5%HDMI@

HTPVDD=200mA

1

C520
1U_0402_6.3V4Z

2

GND to B25

PLLVDD12=70mA

1

C110
1U_0402_6.3V4Z

2

C:Set to UMA@

12
12

UMA_LCD_CLK
UMA_LCD_DAT

NB_STRAP_DATA

LDT_STOP#<6,16>

+3VS

FBM-L11-201209-300LMA30T_0805

1 2

R317 150_0402_1%

1 2

R316 150_0402_1%

1 2

R299 150_0402_1%UMA@

1 2

R297 150_0402_1%UMA@

1 2

R295 150_0402_1%UMA@

UMA_CRT_SCL
UMA_CRT_SDA

R298 3K_0402_5%@
R301 3K_0402_5%@
R59 3K_0402_5%@
R67 3K_0402_5%@
R60 3K_0402_5%@
R66 3K_0402_5%@

L11

1 2

0.1U_0402_16V4Z

UMA_TV_CRMA
UMA_TV_LUMA
UMA_CRT_R
UMA_CRT_G
UMA_CRT_B

UMA_CRT_VSYNC<14>
UMA_CRT_HSYNC<14>

UMA_LCD_DAT<15>

+3VS

+1.8VS

+AVDDQ

UMA_TV_CRMA<14>
UMA_TV_LUMA<14>

1 2

R300 75_0402_1%@

UMA_CRT_R<14>
UMA_CRT_G<14>
UMA_CRT_B<14>

R58 715_0402_1%

1 2

UMA_CRT_SCL<14>

UMA_CRT_SDA<14>

+NB_PLLVDD

+NB_HTPVDD

NB_RST#<15,17,24,25,28,30,34>

NB_PWRGD<30>

ALLOW_LDTSTOP<16>

R45 10K_0402_5%

HTREFCLK<13>

R65 10K_0402_5%

NB_REFCLK<13>
+PLLVDD12

GFX_PCIE<13>

GFX_PCIE#<13>
SBLINKCLK<13>

SBLINKCLK#<13>

12
12
12
12
12
12

BMREQ#<16>

UMA_LCD_CLK<15>

R71 4.7K_0402_5%@
R72 4.7K_0402_5%

1 2

+1.8VS

1 2

B

2

Q12

E

3 1

MMBT3904_SOT23-3

+AVDD

C108

12

NB_STRAP_DATA

R79

10K_0402_5%

C

AVDD=100mA

1

1

2

2

UMA_TV_CRMA
UMA_TV_LUMA
UMA_TV_COMPS

UMA_CRT_R
UMA_CRT_G
UMA_CRT_B

UMA_CRT_SCL
UMA_CRT_SDA

NB_PWRGD
NB_LDTSTOP#

12

12

DFT_GPIO0
DFT_GPIO1
DFT_GPIO2
DFT_GPIO3
DFT_GPIO4
DFT_GPIO5

UMA_LCD_CLK
UMA_LCD_DAT

+3VS

12

R69

1K_0402_5%

NB_LDTSTOP#

C115

2.2U_0603_6.3V4Z
U5C

B14
B15
B13
A13
H14
G14
D17
E17

A15
B16
C17
C18
B17
A17
A18
B18

E15

TXCLK_LP

D15

TXCLK_LN

H15

TXCLK_UP

G15

TXCLK_UN

D14

LPVDD

E14

LPVSS

A12
B12
C12
C13

A16

LVSSR1

A14

LVSSR3

D12

LVSSR5

C19

LVSSR6

C15

LVSSR7

C16

LVSSR8

F14

LVSSR12

F15

LVSSR13

E12
G12
F12

AD14
AD15
AE15
AD16
AE16
AC17
AD18
AE19
AD19
AE20
AD20
AE21

AD13
AC13
AE13
AE17
AD17

RS690 RS690 only

DFT_GPIO1 DFT_GPIO[4:2] DFT_GPIO5

Bypass the loading
of EEPROM straps
and use Hardware
default values

DEFAULT

I2C Master can
load strap values
from EEPROM if
connected, or use
default values if
not connected

UMA_TXOUT0+ <15>
UMA_TXOUT0- <15>
UMA_TXOUT1+ <15>
UMA_TXOUT1- <15>
UMA_TXOUT2+ <15>
UMA_TXOUT2- <15>

UMA_TZOUT0+ <15>

UMA_TZOUT0- <15>

UMA_TZOUT1+ <15>

UMA_TZOUT1- <15>

UMA_TZOUT2+ <15>

UMA_TZOUT2- <15>

UMA_TXCLK+ <15>
UMA_TXCLK- <15>

UMA_TZCLK+ <15>

UMA_TZCLK- <15>

+LPVDD

+LVDDR18D
+LVDDR33A

LVDS_ENVDD
LVDS_ENBKL

PCIE_MTX_DVDRX_P0
PCIE_MTX_DVDRX_N0

PCIE_MRX_C_DVDTX_P0 <24>
PCIE_MRX_C_DVDTX_N0 <24>

PCIE_MTX_NEWRX_N1
PCIE_MTX_NEWRX_P1

PCIE_MRX_C_NEWTX_N1 <28>
PCIE_MRX_C_NEWTX_P1 <28>

R488 2K_0402_5%

MP:Add R488 and
R489 for LCD
flash issue

R489 2K_0402_5%

C:Set to DVD@

C409 0.1U_0402_16V7KDVD@

1 2

C414 0.1U_0402_16V7KDVD@

1 2

C62 0.1U_0402_16V7KNEW@

1 2

C61 0.1U_0402_16V7KNEW@

1 2

These pin straps are used to configure PCI-E GPP mode:
111: register defined (register default to Config E)

110: 4-0-0-0-0 Config A
101: 4-4 Config B
100: 4-2-2 Config C
011: 4-2-1-1 Config D
010: 4-1-1-1-1 Config E
others: register defined ( register defa ult to Config E)

Compal Secret Data

Deciphered Date

G17

G19

AA15
AB15

B22
C22

H17
A20
B20

A21
A22

C21
C20
D19

E19
F19

B21

A10
B10

B24
B25

C10
C11

C23
B23

B11
A11

C14

C6
A5

B6
A6

C5
B5

C2

F2
E1

G1
G2

D6
D7
C8
C7
B8
A8

B2
A2
B4

B3
C3
A3

PART 3 OF 5

AVDD1
AVDD2
AVSSN1
AVSSN2
AVDDDI
AVSSDI

AVDDQ
AVSSQ

C
Y
COMP

RED
GREEN
BLUE
DACVSYNC
DACHSYNC

RSET
DACSCL

DACSDA
PLLVDD(PLLVDD18)

PLLVSS
HTPVDD

HTPVSS
SYSRESET#

POWERGOOD
LDTSTOP#
ALLOW_LDTSTOP

HTTSTCLK
HTREFCLK

TVCLKIN
OSCIN

OSCOUT(PLLVDD12)
GFX_CLKP

GFX_CLKN
SB_CLKP

SB_CLKN
DFT_GPIO0

DFT_GPIO1
DFT_GPIO2
DFT_GPIO3
DFT_GPIO4
DFT_GPIO5

BMREQ#
I2C_CLK
I2C_DATA
THERMALDIODE_P
THERMALDIODE_N

TMDS_HPD
DDC_DATA
TESTMODE
STRP_DATA

216MQA6AVA11FG_FCBGA465_RS690MVGAR1@

PULL HIGH
(internally
pulled high)

PULL
LOW

CRT/TVOUT

PLL PWR

PMCLOCKs

MIS.

TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P

TXOUT_L3N
TXOUT_U0P

TXOUT_U0N

TXOUT_U1P

TXOUT_U1N

TXOUT_U2P

TXOUT_U2N

TXOUT_U3P

TXOUT_U3N

LVDDR18D_1

LVTM

LVDDR18D_2
LVDDR18A_1(LVDDR33_1)
LVDDR18A_2(LVDDR33_2)

LVDS_DIGON

LVDS_BLON
LVDS_BLEN

DVO_D0(GPP_TX0P)
DVO_D1(GPP_TX0N)

DVO_D2(DEBUG6)

DVO_D3(GPP_RX0P)

DVO_D4(GPP_RX0N)

DVO_D5(DEBUG9)

DVO_D6(DEBUG10)

DVO_D7(GPP_TX1N)

DVO_D8(GPP_TX1P)

DVO_D9(GPP_RX1N)

DVO_D10(GPP_RX1P)

DVO

DVO_D11(DEBUG15)

DVO_VSYNC(DEBUG0)

DVO_DE(DEBUG2)
DVO_HSYNC(DEBUG1)
DVO_IDCKP(DEBUG14)
DVO_IDCKN(DEBUG13)

DFT_GPIO0

Memory
side port
not available

DEFAULT

Memory
side port
available

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/5/4 2008/5/4

LVDDR33=180mA

LVDS_ENBKL

1 2

UMA@

NB_PWRGD

LVDS_ENVDD

1 2

UMA@

+LPVDD

1

C504

0.1U_0402_16V4Z

2

GND to E14

+LVDDR18D

C109

0.1U_0402_16V4Z

GND to A14, D12

+LVDDR33A

C505

0.1U_0402_16V4Z

GND to C15

+3VS

14

4

P

A

5

B

G

7

PCIE_MTX_C_DVDRX_P0 <24>
PCIE_MTX_C_DVDRX_N0 <24>

MBC1608121YZF_0603

1

C513

2.2U_0603_6.3V4Z

2

1

2

1

2

+3VS

14

1

A

2

B

7

U20B

6

O

SN74LVC08APW_TSSOP14

PCIE_MTX_C_NEWRX_N1 <28>
PCIE_MTX_C_NEWRX_P1 <28>

DEFAULT

L50

1 2

MBC1608121YZF_0603

L14

1 2

1

C116

2.2U_0603_6.3V4Z

2

MBC1608121YZF_0603

L54

1 2

1

C537

4.7U_0805_10V4Z

2

C499

0.1U_0402_16V4Z

U20A

P

3

O

G

SN74LVC08APW_TSSOP14

UMA_ENVDD <15>

Enable debug bus via the memory
IO pads, if available in the package

use default values

use the memory data bus
to output the debug bus

Title

Size Document Number Rev

Custom

Date: Sheet

RX690/RS690MC VIDEO_IF/CLOCK GEN

IALAA-Minnesota10A LA3631P

+1.8VS

+1.8VS

+3VS

UMA_ENBKL <30>

DEFAULT

of

11 45Wednesday, May 16, 2007

1A

5

4

3

2

1

+1.2V_HT

12

+

C57 330U_D2E_2.5VM@
C54
C55

D D

+1.2V_HT +VDDA12

C C

+1.2V_HT

B B

C442 1U_0402_6.3V4Z
C456 1U_0402_6.3V4Z
C465 1U_0402_6.3V4Z
C445 1U_0402_6.3V4Z
C432 1U_0402_6.3V4Z

+1.8VS

FBMA-L11-201209-221LMA30T_0805

C448
C493 1U_0402_6.3V4Z

1 2

C470 1U_0402_6.3V4Z

1 2

C490 1U_0402_6.3V4Z

1 2

C486 1U_0402_6.3V4Z

1 2

1 2

C511 2.2U_0603_6.3V4Z
C498 0.1U_0402_16V4Z

C433 1U_0402_6.3V4Z
C446 1U_0402_6.3V4Z
C430 1U_0402_6.3V4Z

1 2

MBC1608121YZF_0603

4.7U_0805_10V4Z

10U_0805_10V4Z
10U_0805_10V4Z

1 2
1 2
1 2
1 2
1 2

C492 1U_0402_6.3V4Z

1 2

C489 1U_0402_6.3V4Z

1 2

L45

12

10U_0805_10V4Z

12

+1.8VS

12
12
12

L49

+3VS

C516

VDDA_12=2.5A

VDDR3=70mA

+NB_VDDPLL

1

2

2

1

GND to F9, G9.

VDD_HT(I/O only)=800mA

VDD_18=2mA

VDDPLL=50mA

C501
1U_0402_6.3V4Z

+VDDA12

+NB_VDDPLL

+VDDHT_PKG
+VDDA12_PKG1
+VDDA12_PKG2

+VDDA12_PKG1

1

2

AA17
AB17
AB19
AC18
AC19
AC20
AD21
AD22
AD23
AD24
AE23
AE24
AE25

W17

Y17

AB3
AB4
AC3
AD2
AE1
AE2

D11
E11

AC12
AD12
AE12

D22

AC11

C484

4.7U_0805_10V4Z

U5D

PART 4 OF 5

VDD_HT1
VDD_HT2
VDD_HT3
VDD_HT4
VDD_HT5
VDD_HT6
VDD_HT7
VDD_HT8
VDD_HT9
VDD_HT10
VDD_HT11
VDD_HT12
VDD_HT13
VDD_HT14
VDD_HT15

J14

VDD18_1

J15

VDD18_2
VDDA18_1(VDDA12_13)

VDDA18_2(VDDA12_14)
VDDA18_3(VDDA12_15)
VDDA18_4(VDDA12_16)
VDDA18_5(VDDA12_17)
VDDA18_6(VDDA12_18)

U7

VDDA18_7(VDDA12_19)
VDDA18_8(VDDA12_20)W7VDDC_14

VDDR3_1
VDDR3_2

VDD_DVO1(VDDR_1)
VDD_DVO2(VDDR_2)
VDD_DVO3(VDDR_3)

E7

VDDA12(VDDPLL_1)

F7

VDDA12(VDDPLL_2)

F9

VSSA12(VSSPLL_1)

G9

VSSA12(VSSPLL_2)
VDDHT_PKG

M1

VDDA12_PKG1
VDDA12_PKG2

216MQA6AVA11FG_FCBGA465_RS690MVGAR1@

POWER

VDDA12_1
VDDA12_2
VDDA12_3
VDDA12_4
VDDA12_5
VDDA12_6
VDDA12_7
VDDA12_8

VDDA12_9
VDDA12_10
VDDA12_11
VDDA12_12

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8

VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13

VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDDC_23
VDDC_24
VDDC_25
VDDC_26
VDDC_27
VDDC_28
VDDC_29
VDDC_30
VDDC_31
VDDC_32

VDDA_12=2.5A

B1
C1
D1
D2
D3
E2
E3
F4
E6
G7
L9
M9

A4
A7
A9
A19
B9
B19
C9
D9
D20
G20
H11
J11
J19
L11
L13
L15
L17
M12
M14
N11
N13
N15
P12
P14
P17
R11
R13
R15
U11
U12
U14
U15

FBMA-L11-201209-221LMA30T_0805

1

1

C4910.1U_0402_16V4Z

C4800.1U_0402_16V4Z

2

2

1

C4830.1U_0402_16V4Z

2

+VDDA12

+1.2V_HT +NB_VDDC

1

C5100.1U_0402_16V4Z

2

L43

1 2

C447
C58

C521

C500 1U_0402_6.3V4Z

1 2

C441 1U_0402_6.3V4Z

1 2

C453 1U_0402_6.3V4Z

1 2

C512 1U_0402_6.3V4Z

1 2
1 2
1 2

1 2
1 2

VDD_CORE=5A

1

1

C4710.1U_0402_16V4Z

C4790.1U_0402_16V4Z

2

2

1

C4740.1U_0402_16V4Z

2

C506 1U_0402_6.3V4Z
C463 1U_0402_6.3V4Z

L41
FBMA-L11-201209-221LMA30T_0805
L44

FBMA-L11-201209-221LMA30T_0805

1

C4850.1U_0402_16V4Z

2

10U_0805_10V4Z
10U_0805_10V4Z

10U_0805_10V4Z

1

1

C5020.1U_0402_16V4Z

C52910U_0805_10V4Z

2

2

+1.2V_HT

330U_D2E_2.5VM

1

C424

1

C53010U_0805_10V4Z

+

2

2

A25
D23
G11

Y23
P11
R24

AE18

M15
G23

M11
M20
M23
M25
N12
N14

P13
P20
P15
R12
R14
R20

W23

Y25

AD25

U20
H25

W24

Y22

AC23

D25
G24

AC14
AC22

R23

AE22

AE14

R17
H23
M17
A23

AC15

M13

AC16

H12

U5E

VSS1

F11

E9

J22
J12

L12
L14
L20
L23

L24

C4

T23
T25

F17

D4

B7

VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23

VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42

VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57

VSS59
VSS60
VSS61
VSS62

PAR 5 OF 5

GROUND

216MQA6AVA11FG_FCBGA465_RS690MVGAR1@

VSSA2
VSSA3
VSSA4
VSSA5
VSSA6
VSSA7
VSSA8

VSSA9
VSSA10
VSSA11

VSSA13
VSSA15

VSSA16
VSSA17
VSSA18
VSSA19
VSSA20
VSSA21
VSSA22

VSSA24
VSSA25
VSSA26
VSSA27
VSSA28

VSSA30
VSSA32

VSSA33
VSSA34
VSSA35
VSSA36
VSSA93
VSSA94
VSSA95
VSSA37
VSSA38
VSSA39
VSSA40
VSSA41
VSSA42
VSSA43
VSSA44
VSSA45
VSSA46
VSSA47
VSSA48
VSSA49
VSSA50
VSSA51

V12
V11
V14
F3
V15
A1
H1
G3
J2
H3

J6
F1

L6
M2
M6
J3
P6
T1
N3

R6
U2
T3
U3
U6

Y1
W6

AC2
Y3
Y9
Y11
Y12
Y14
AA3
R9
AD1
AC5
AC6
AC7
AD3
AC9
AC10
G6
Y15
AC4
P9
AE6
AE10
M3

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/5/4 2008/5/4

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

RX690/RS690MC Power/GND

IALAA-Minnesota10A LA3631P

12 45Monday, May 14, 2007

1

of

1A

A

B

C

D

E

F

G

H

+3VS

Need to link "SM010007E00"

L57

1 2

CHB2012U121_0805

VDD_48=50mA

L56

1 1

+3VS

+3VS

1 2

MBC1608121YZF_0603

2.2U_0603_6.3V4Z

L58

1 2

MBC1608121YZF_0603

2.2U_0603_6.3V4Z

C588

C599

2

C596

0.1U_0402_16V4Z

1

2

C597

0.1U_0402_16V4Z

1

+3VS_CLK_VDD48

+3VS_CLK_ V DDREF

1

2

1

2

10U_0805_10V4Z@

1

C592

2

+3VS_CLK_VDD48

+3VS_CLK_ V DDREF

+3VS_CLK

1

C590

2

10U_0805_10V4Z

+3VS_CLK

0.1U_0402_16V4Z

C595

VDD_REF=50mA

C603

33P_0402_50V8J

1 2

1 2

C631

33P_0402_50V8J

12

14.31818MHZ_20P_6X1430004201

Y3

R390

1M_0402_5%@

1 2

SMB_CK_CLK0<8,9,17,24,28>
SMB_CK_DAT0<8,9,17,24,28>

2 2

+3VS_CLK

1 2

R378 10K_0402_5%

3 3

CLK_RESET

XTALIN_CLK CLK_PCIE_VGA_R

XTALOUT_CLK

CLK_RESET

1 2

R394 475_0402_1%

PLACE CLOSE TO U62
WITHIN 0.5 INCH

EXT CLK FREQUENCY SELECT TABLE(MHZ)

FS2

0 0 0
0 0 1

0 1 0
0 1 1
1 0 0
1 0 1

1 1 1

4 4

CPUFS1

Hi-Z
X

180.00

220.00

100.00

133.33

200.00

SRCCLK

[2:1]

100.00

100.00

100.00

100.00

100.00

100.00

HTTFS0 PCI

Hi-Z Hi-Z100.00 Reserved

36.56 73.12

66.66 33.33

66.66 33.33

66.66 33.33 Norma l A T H L O N64 o p er a ti o n

USB

COMMENT

48.00

48.00

48.00

48.00

48.00

48.00

Reserved
Reserved
Reserved
Reserved
Reserved

X/6X/3

30.0060.00

48.00

VDD=500mA

1

1

C593

2

2

0.1U_0402_16V4Z

54
14
23
28
44

5

39

2

60
53

15
22
29
45

8

38

1

58

3
4

11
61

9

10

48

FS0
FS1
FS2

0.1U_0402_16V4Z

1

C170

2

U25

VDDCPU
VDDSRC
VDDSRC
VDDSRC
VDDSRC
VDD48
VDDATIG
VDDREF
VDDHTT

GNDCPU
GNDSRC
GNDSRC
GNDSRC
GNDSRC
GND48
GNDATIG
GNDREF
GNDHTT

X1
X2

RESET_IN#
NC

SMBCLK
SMBDAT

IREF

ICS951462AGLFT_TSSOP64

0.1U_0402_16V4Z

1

C636

2

0.1U_0402_16V4Z

CPUCLK8T0
CPUCLK8C0
CPUCLK8T1
CPUCLK8C1

ATIGCLKC0
ATIGCLKC1
ATIGCLKC2
ATIGCLKC3

C167

VDDA

GNDA

SRCCLKT6
SRCCLKC6
ATIGCLKT0

ATIGCLKT1
ATIGCLKT2
ATIGCLKT3

SRCCLKT5
SRCCLKC5

SRCCLKT4
SRCCLKC4

SRCCLKT3
SRCCLKC3

SRCCLKT2
SRCCLKC2

SRCCLKT0
SRCCLKC0

SRCCLKT1
SRCCLKC1

SRCCLKT7
SRCCLKC7

CLKREQA#
CLKREQB#
CLKREQC#

48MHz_1
48MHz_0

FS1/REF1
FS0/REF0
FS2/REF2

HTTCLK0

R104

R108

1

2

0.1U_0402_16V4Z

12

2.2K_0402_5%

12

2.2K_0402_5%

@

0.1U_0402_16V4Z

1

C594

2

50
49

CPUCLK0

56

CPUCLK0#

55
52
51

SBLINKCLK_R

16

SBLINKCLK#_R

17

GFX_PCIE_R

41

GFX_PCIE_R#

40
37
36
35
34
30
31

SBSRCCLK_R

18

SBSRCCLK_R#

19
20

CLK_PCIE_VGA_R#

21
24
25
26
27

CLK_NEW_R

47

CLK_NEW_R#

46

CLK_PCIE_LAN_R

43

CLK_PCIE_LAN_R#

42

CLK_WLAN_R

12

CLK_WLAN_R#

13

CLKREQ_WLAN#

57

CLKREQ_DVD#

32

CLKREQ_NEW#

33

CLK_CBCLKIREF

7

CLK_USB

6

FS1

63

FS0

64

FS2

62

CLK_HTREFCLK

59

12

R105

2.2K_0402_5%

12

R109

2.2K_0402_5%

@

+3VS_CLK

CLK_DVD_R
CLK_DVD_R#

+3VS_CLK

12

R106

12

R110

@

VDDA=50mA

1

C171

2

2.2K_0402_5%

2.2K_0402_5%

+3VS_CLK_VDDA

C168

0.1U_0402_16V4Z

R99 47.5_0402_1%

1 2

R100 47.5_0402_1%

1 2

R366 33_0402_5%
R365 33_0402_5%
R397 33_0402_5%
R396 33_0402_5%

R360 33_0402_5%
R359 33_0402_5%

R373 33_0402_5%VGA@
R372 33_0402_5%VGA@

C:Set R377 and R376 with DVD@

R377 33_0402_5%DVD@
R376 33_0402_5%DVD@
R404 33_0402_5%NEW@
R403 33_0402_5%NEW@
R402 33_0402_5%
R401 33_0402_5%
R368 33_0402_5%WLAN@
R367 33_0402_5%WLAN@

R369 FBMA-11-100505-900T
R379 33_0402_5%

R95 33_0402_5%
R94 33_0402_5%
R96 33_0402_5%
R97 33_0402_5%

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

CLKREQ_WLAN# <24>
CLKREQ_DVD# <24>
CLKREQ_NEW# <28>

1 2
1 2

1 2
1 2

12

1 2

1

1

C169

2

C179

2

10U_0805_10V4Z

@

SBLINKCLK
SBLINKCLK#
GFX_PCIE
GFX_PCIE# GFX_PCIE

MP:Chg. R369 from
33Ohm to 90Ohm Bead.

HTREFCLK

CLKREQ_WLAN#
CLKREQ_DVD#
CLKREQ_NEW#

1

2

10U_0805_10V4Z

12

SBSRCCLK

SBSRCCLK#
CLK_PCIE_VGA
CLK_PCIE_VGA#

CLK_DVD
CLK_DVD#

CLK_NEW

CLK_NEW#
CLK_PCIE_LAN
CLK_PCIE_LAN#

CLK_WLAN

CLK_WLAN#

1 2

R398 100K_0402_5%

1 2

R386 100K_0402_5%

1 2

R395 100K_0402_5%

L17

1 2

MBC1608121YZF_0603

R101
261_0402_1%

SBLINKCLK <11>
SBLINKCLK# <11>
GFX_PCIE <11>
GFX_PCIE# <11>

SBSRCCLK <16>
SBSRCCLK# <16>
CLK_PCIE_VGA <15>
CLK_PCIE_VGA# <15>

CLK_DVD <24>
CLK_DVD# <24>

CLK_NEW <28>
CLK_NEW# <28>
CLK_PCIE_LAN <25>
CLK_PCIE_LAN# <25>

CLK_WLAN <24>
CLK_W LAN# <24>

C:Set R370 and R371
with DVD@

CLK_48M_CB <22>
USBCLK_EXT <17>

CLK_14M_SIO <34>
SB_OSC_INT <17>

NB_REFCLK <11>

HTREFCLK <11>

+3VS

CPUCLK0_H <6>

CPUCLK0_L <6>

+3VS

SBLINKCLK
SBLINKCLK#

GFX_PCIE#

SBSRCCLK
SBSRCCLK#
CLK_PCIE_VGA
CLK_PCIE_VGA#
CLK_PCIE_LAN
CLK_PCIE_LAN#
CLK_NEW
CLK_NEW#
CLK_DVD
CLK_DVD#
CLK_WLAN
CLK_WLAN#

HTREFCLK

1 2

1 2
1 2
1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

VGA@
VGA@

NEW@
NEW@
DVD@
DVD@
WLAN@
WLAN@

1 2

R356 49.9_0402_1%

1 2

R355 49.9_0402_1%

1 2

R92 49.9_0402_1%

1 2

R93 49.9_0402_1%

R354 49.9_0402_1%
R353 49.9_0402_1%
R352 49.9_0402_1%
R351 49.9_0402_1%
R102 49.9_0402_1%
R103 49.9_0402_1%
R407 49.9_0402_1%
R406 49.9_0402_1%
R371 49.9_0402_1%
R370 49.9_0402_1%
R362 49.9_0402_1%
R361 49.9_0402_1%

1 2

R107 49.9_0402_1%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

C

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

D

2007/5/4 2008/5/4

Compal Secret Data

Deciphered Date

E

Title

Size Document Number Rev

Custom

F

Date: Sheet

G

Clock Generator
IALAA-Minnesota10A LA3631P

13 45Wednesday, May 16, 2007

of

H

1A

A

B

C

D

E

12

1

2

JP24

ACES_85201-1205UMA@

+CRT_VCC

12

R18

UMA@

19.1K_0402_1%

CRT_DDC_DAT

CRT_DDC_CLK

1

C24

@

2

470P_0402_50V8J

1
2
3
4
5
6
7
8
9
10
11
12

CRT CONNECTOR

UMA_CRT_R<11>

1 1

2 2

UMA_CRT_G<11>

UMA_CRT_B<11>

1 2

C428 0.1U_0402_16V4Z

UMA@

UMA_CRT_HSYNC<11>

UMA_CRT_VSYNC<11>

CRT_HSYNC HSYNC

CRT_VSYNC

CRT_G

CRT_B

12

R20

UMA@

+CRT_VCC

C426

UMA@

150_0402_1%

1

5

P

4

OE#

A2Y

G

U16

UMA@

3

SN74AHCT1G125GW_SOT353-5

1 2

UMA@

0.1U_0402_16V4Z

R19

12

R16

UMA@

150_0402_1%

+CRT_VCC

12

150_0402_1%

1

5

P

OE#

A2Y

G

U17

UMA@

3

SN74AHCT1G125GW_SOT353-5

1

C17

UMA@

2

12

R282 10K_0402_5%

UMA@

D_CRT_HSYNC

D_CRT_VSYNC

4

1

C25

UMA@

2

6P_0402_50V8K

6P_0402_50V8K

C37

UMA@

L6

1 2

FCM2012C-800_0805

UMA@

L4

1 2

FCM2012C-800_0805

UMA@

L3

1 2

FCM2012C-800_0805

UMA@

1

2

6P_0402_50V8K

B:As EMI request
L3,L4,L6 need to link
SM010009L00

1 2

L40 10_0402_5%UMA@

1 2

L42 10_0402_5%UMA@

C21

1

2

22P_0402_50V8J

C16

C425

UMA@

CRT_R_LCRT_R

CRT_G_L

CRT_B_L

1

2

1

2

22P_0402_50V8J

C427

UMA@

10P_0402_50V8J

C13

1

2

MP:Update D29 to meet CRT.

+5VS +R_CRT_VCC +CRT_VCC

D29

2 1

RB491D_SOT23

C:EMI solution to add
C13,C16,C21 in BOM with

1

22P value.

2

22P_0402_50V8J

UMA_CRT_SDA<11>

UMA_CRT_SCL<11>

F2

21

1A_6VDC_MINISMDC110

0.1U_0402_16V4Z@

G

2

S

C:Chg. PN to SB770020010.

VSYNC

10P_0402_50V8J

+CRT_VCC

1

C422

2

+3VS

G

2

Q4

13

D

S

2N7002_SOT23-3

UMA@

Q5

13

D

2N7002_SOT23-3

UMA@

CRT_DDC_CLK

CRT_DDC_DAT
VSYNC
HSYNC
CRT_R_L

CRT_G_L
CRT_B_L

A: Follow AMD command.

R21

UMA@

19.1K_0402_1%

C38

@

470P_0402_50V8J

TV-OUT CONNECTOR

3 3

+3VS

C524

1 2

22P_0402_50V8J

VGA_TV_LUMA<15>
UMA_TV_LUMA<11>

VGA_TV_CRMA<15>
UMA_TV_CRMA<11>

4 4

1 2

R288 0_0402_5%VGA@

1 2

R287 0_0402_5%UMA@

1 2

R290 0_0402_5%VGA@

1 2

R289 0_0402_5%UMA@

R307

150_0402_1%

TV_LUMA

TV_CRMA

12

12

R310
150_0402_1%

1

C533

100P_0402_25V8K

2

L51 MBK1608121YZF_0603

L53 MBK1608121YZF_0603

1

C517

100P_0402_25V8K

2

@

1 2

1 2

1 2

22P_0402_50V8J@

C528

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/5/4 2008/5/4

C

D4

DAN217_SC59@

2

1

C536

2

100P_0402_25V8K

Compal Secret Data

Deciphered Date

1

D5

3

1

C535

2

100P_0402_25V8K

DAN217_SC59@

1

2

3

TV_CRMA_L
TV_LUMA_L

JP26

4

4

3

3

2

2

1

ALLTO_C10877-104A1-L_4P

1

D

6
5

TV-OUT Conn.

1. Y ground

2. C ground

3. Y (luminance+sync)

4. C (crominance)

Compal Electronics, Inc.

Title

TV-OUT, LVDS CONNECTOR

Size Document Number Rev

IALAA-Minnesota10A LA3631P 1A

B

Monday, May 14, 2007

Date: Sheet

E

14 45

of

5

VGA BOARD Conn.

B+

D D

+2.5VS

C C

B B

VGA_DVI_SDATA<20>

A:Delete
VGA_SMB_DAT/CLK
bec'z delete
HDMI/1932 fun..

A A

VGA_HPD<20>

VGA_DVI_SCLK<20>

VGA_DVI_TXD0-<20>
VGA_DVI_TXD0+<20>

VGA_DVI_TXD1-<20>
VGA_DVI_TXD1+<20>

VGA_DVI_TXD2-<20>
VGA_DVI_TXD2+<20>

VGA_DVI_TXC+<20>
VGA_DVI_TXC-<20>

EC_SMB_CK2<6,30>
EC_SMB_DA2<6,30>

+5VALW

+CRT_VCC

VGA_ENBKL<30>

VGA_TV_LUMA<14>
VGA_TV_CRMA<14>

SUSP#<26,28,30,35,38>

5

+3VS

+1.5VS

PCEI_GTX_C_MRX_P15
PCEI_GTX_C_MRX_N15

PCEI_GTX_C_MRX_P14
PCEI_GTX_C_MRX_N14

PCEI_GTX_C_MRX_P13
PCEI_GTX_C_MRX_N13

PCEI_GTX_C_MRX_P12
PCEI_GTX_C_MRX_N12

PCEI_GTX_C_MRX_P11
PCEI_GTX_C_MRX_N11

PCEI_GTX_C_MRX_P10
PCEI_GTX_C_MRX_N10

PCEI_GTX_C_MRX_P9
PCEI_GTX_C_MRX_N9

PCEI_GTX_C_MRX_P8
PCEI_GTX_C_MRX_N8

PCEI_GTX_C_MRX_P7
PCEI_GTX_C_MRX_N7

PCEI_GTX_C_MRX_P6
PCEI_GTX_C_MRX_N6

PCEI_GTX_C_MRX_P5
PCEI_GTX_C_MRX_N5

PCEI_GTX_C_MRX_P4
PCEI_GTX_C_MRX_N4

PCEI_GTX_C_MRX_P3
PCEI_GTX_C_MRX_N3

PCEI_GTX_C_MRX_P2
PCEI_GTX_C_MRX_N2

PCEI_GTX_C_MRX_P1
PCEI_GTX_C_MRX_N1

PCEI_GTX_C_MRX_P0
PCEI_GTX_C_MRX_N0

VGA_ENVDD

JP23

101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205

1

1

3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

JAE_WB3F200VD1R1000~DVGA@

4

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206

PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15

PCIE_MTX_C_GRX_P14

PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P13

PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P12

PCIE_MTX_C_GRX_N12

PCIE_MTX_C_GRX_P11

PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P10

PCIE_MTX_C_GRX_N10

PCIE_MTX_C_GRX_P9

PCIE_MTX_C_GRX_N9

PCIE_MTX_C_GRX_P8

PCIE_MTX_C_GRX_N8

PCIE_MTX_C_GRX_P7

PCIE_MTX_C_GRX_N7

PCIE_MTX_C_GRX_P6

PCIE_MTX_C_GRX_N6

PCIE_MTX_C_GRX_P5

PCIE_MTX_C_GRX_N5

PCIE_MTX_C_GRX_P4

PCIE_MTX_C_GRX_N4

PCIE_MTX_C_GRX_P3

PCIE_MTX_C_GRX_N3

PCIE_MTX_C_GRX_P2

PCIE_MTX_C_GRX_N2

PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1

PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0

4

+1.8VS

+2.5VS

LCD_EDID_DATA

LCD_EDID_CLK

LCD_TXCLK­LCD_TXCLK+

LCD_TXOUT0­LCD_TXOUT0+

LCD_TXOUT1­LCD_TXOUT1+

LCD_TXOUT2­LCD_TXOUT2+

LCD_TZOUT0­LCD_TZOUT0+

LCD_TZOUT1­LCD_TZOUT1+

LCD_TZOUT2­LCD_TZOUT2+

LCD_TZCLK­LCD_TZCLK+

PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]

PCEI_GTX_C_MRX_N[0..15]
PCEI_GTX_C_MRX_P[0..15]

+3VS

R279 4.7K_0402_5%

LCD_TZOUT1-

LCD_TXOUT0+
LCD_TXOUT0­LCD_TXOUT1+
LCD_TXOUT1­LCD_TXOUT2­LCD_TXOUT2+

LCD_EDID_CLK
LCD_EDID_DATA

+LCDVDD_C
+LCDVDD_C

A:Follow ISKAA modify for HDMI1932.

CLK_PCIE_VGA <13>
CLK_PCIE_VGA# <13>

NB_RST# <11,17,24,25,28,30,34>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

LCD/PANEL BD. Conn.

UMA_ENVDD<11>

PCIE_MTX_C_GRX_N[0..15] <10>

PCIE_MTX_C_GRX_P[0..15] <10>
PCIE_GTX_C_MRX_N[0..15] <10>
PCIE_GTX_C_MRX_P[0..15] <10>

C:Chg. PN to SB770020010.

1 2

JP3

32
31

29
27
25
23
21
19
17
15
13

7
5
3

ACES_88242-3001
LVDS30CON@

BKOFF#

GND2
GND1

30

29

30

28

27

28

26

25
23
21
19
17
15
13
111112
9910
7
5
3
112

26
24
22
20
18
16
14

8
6
4

BKOFF#

24
22

DAC_BRIG LCD_TZOUT1+

20

INVT_PWM

18
16

LCD_TXCLK-

14

LCD_TXCLK+

12
10
8
6
4
2

+LCDVDD

C403

0.1U_0402_16V4Z

2007/5/4 2008/5/4

3

1 2

R1 0_0402_5%UMA@

VGA_ENVDD

+LCDVDD

470_0805_5%

2N7002_SOT23-3

+3VS

+INV

1

2

Compal Secret Data

Deciphered Date

R5

D

Q2

S

C407 68P_0402_50V8J@
C401 68P_0402_50V8J@
C413 68P_0402_50V8J@
C9 68P_0402_50V8J@
C7 68P_0402_50V8J@

L36

1 2

0_0805_5%

LCD_EDID_CLK
LCD_EDID_DATA

LCD_TXOUT0-

LCD_TXOUT0+

LCD_TXOUT1-

LCD_TXOUT1+

LCD_TXOUT2-

LCD_TXOUT2+

LCD_TZOUT0-

LCD_TZOUT0+

LCD_TZOUT1-

LCD_TZOUT1+
LCD_TZOUT2-

LCD_TZOUT2+

LCD_TZCLK-

LCD_TZCLK+

12

13

2

G

0.047U_0402_16V4Z

1 2
1 2
1 2

LCD_EDID_CLK

1 2

LCD_EDID_DATA

1 2

22U_A_4VM

LCD_TXCLK-

LCD_TXCLK+

2

ENVDD

12

R2
2K_0402_5%

C3

DAC_BRIG
INVT_PWM

BKOFF#

EMI

LCD_TZOUT0­LCD_TZOUT0+
LCD_TZOUT2­LCD_TZOUT2+

LCD_TZOUT1-

LCD_TXOUT0+

LCD_TXOUT0-

LCD_TXOUT1+

LCD_TXOUT1­LCD_TXOUT2-

LCD_TXOUT2+

LCD_EDID_CLK
LCD_EDID_DATA

1

+

C394

2

R8 0_0402_5%UMA@
R9 0_0402_5%UMA@

R255 0_0402_5%LVDS30@
R256 0_0402_5%LVDS30@

R257 0_0402_5%LVDS30@
R258 0_0402_5%LVDS30@

R259 0_0402_5%LVDS30@
R260 0_0402_5%LVDS30@

R268 0_0402_5%LVDS30@
R269 0_0402_5%LVDS30@

R261 0_0402_5%LVDS40@
R262 0_0402_5%LVDS40@

R266 0_0402_5%LVDS40@
R267 0_0402_5%LVDS40@

R263 0_0402_5%LVDS40@
R264 0_0402_5%LVDS40@

R271 0_0402_5%LVDS40@
R270 0_0402_5%LVDS40@

2

+3V_SB

C:Change Q1 and Q3 same as Q52,

Q1

G

2

1

2

use same part in BOM.

S

D

AO3413_SOT23

1 3

12

R6
100_0402_5%

12

R7
100K_0402_5%

+3VS

Q3

G

2

1 3

S

D

C2

4.7U_0805_10V4Z@

AO3413_SOT23

80mil

80mil

1

C4

4.7U_0805_10V4Z@

2

+LCDVDD Width: 80mils

+LCDVDD

1

C1

0.1U_0402_16V4Z

2

B:Set "@".

B+ +INV

+LCDVDD_C

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

L34

1 2

FBMA-L11-201209-221LMA30T_0805

JP4

GND41GND

39

39

37

37

35

35

33

33

31

31

29

29

27

27

25

25

23

23

21

21

19

19

17

17

15

15

13

13

11

11

9

9

7

7

5

5

3

3

1

1

ACES_88242-4001

LVDS40CON@

Title

Size Document Number Rev

B

Date: Sheet

42
40

40

38

38

36

36

34

34

32

32

30

30

28

28

26

26

24

24

22

22

DAC_BRIG

20

20

INVT_PWM

18

18

16

16

14

14

12

12

10

10

8

8

6

6

4

4

2

2

UMA_LCD_CLK
UMA_LCD_DAT

Compal Electronics, Inc.

CRT CONNECTOR

IALAA-Minnesota10A LA3631P 1A

Monday, May 14, 2007

LCD_TZCLK+

LCD_TZCLK-

BKOFF#

LCD_TXCLK­LCD_TXCLK+

1

0.1U_0402_25V4Z

2

1

B:Set "@".

C389

BKOFF# <30>
DAC_BRIG <30>

INVT_PWM <30>

+INV

UMA_LCD_CLK <11>
UMA_LCD_DAT <11>

UMA_TXCLK- <11>
UMA_TXCLK+ <11>

UMA_TXOUT0- <11>
UMA_TXOUT0+ <11>

UMA_TXOUT1- <11>
UMA_TXOUT1+ <11>

UMA_TXOUT2- <11>
UMA_TXOUT2+ <11>

UMA_TZOUT0- <11>

UMA_TZOUT0+ <11>

UMA_TZOUT1- <11>

UMA_TZOUT1+ <11>

UMA_TZOUT2- <11>

UMA_TZOUT2+ <11>

UMA_TZCLK- <11>

UMA_TZCLK+ <11>

1

1

C390
68P_0402_50V8J

2

C415

15 45

of

+3VS

1

2

0.1U_0402_16V4Z

5

SBSRCCLK<13>

SB_RX0P<10>

SB_RX0N<10>

SB_RX1P<10>

SB_RX1N<10>

ALLOW_LDTSTOP

12

R422

12

C688

R417

C679

5

SB_RX2P<10>

SB_RX2N<10>

SB_RX3P<10>

SB_RX3N<10>

+PCIE_VDDR

EC_SWI#

SB_TEST0
SB_TEST1
SB_TEST2

H_THERMTRIP#

12

D D

+1.8VS

C C

R112 1K_0402_5%

+3V_SB

1 2

R416 100K_0402_5%

1 2

R125 2.2K_0402_5%@

1 2

R127 2.2K_0402_5%@

1 2

R126 2.2K_0402_5%@

1 2

R129 4.7K_0402_5%

B B

20M_0603_5%

1 2

18P_0402_50V8J

A A

20M_0603_5%

1 2

18P_0402_50V8J

C632 0.1U_0402_16V7K
C635 0.1U_0402_16V7K
C641 0.1U_0402_16V7K
C642 0.1U_0402_16V7K
C634 0.1U_0402_16V7K
C633 0.1U_0402_16V7K
C640 0.1U_0402_16V7K
C639 0.1U_0402_16V7K

Y4

4

OUT

1

IN

32.768KHZ_12.5P_1TJS125BJ4A421P

SBSRCCLK#<13>

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

SB_TX0P<10>
SB_TX0N<10>
SB_TX1P<10>
SB_TX1N<10>
SB_TX2P<10>
SB_TX2N<10>
SB_TX3P<10>
SB_TX3N<10>

R412 562_0402_1%
R411 2.05K_0402_1%

R413 0_0402_5%

H_PWRGD<6>

LDT_STOP#<6,11>

ALLOW_LDTSTOP<11>

LDT_RST#<6>

EC_SWI#<28,30>

PM_SLP_S3#<30>
PM_SLP_S5#<30>

PBTN_OUT#<30>

SB_PWRGD<6,30>

H_THERMTRIP#<6>

GATEA20<30>

EC_KBRST#< 30>

LPC_AD0<30,34>
LPC_AD1<30,34>
LPC_AD2<30,34>
LPC_AD3<30,34>

LPC_FRAME#<30,34>

LPC_DRQ1#<34>

BMREQ#<11>

SERIRQ<22,30,34>

3

NC

2

NC

SB_32KHO

ALLOW_LDTSTOP

EC_SWI#

H_THERMTRIP#

SB_32KHI

12
12

12

SB_RX0P_C
SB_RX0N_C
SB_RX1P_C
SB_RX1N_C
SB_RX2P_C
SB_RX2N_C
SB_RX3P_C
SB_RX3N_C

SB_TEST0
SB_TEST1
SB_TEST2

SB_32KHI

SB_32KHO

4

U26A

J24

PCIE_RCLKP

J25

PCIE_RCLKN

P29

PCIE_TX0P

P28

PCIE_TX0N

M29

PCIE_TX1P

M28

PCIE_TX1N

K29

PCIE_TX2P

K28

PCIE_TX2N

H29

PCIE_TX3P

H28

PCIE_TX3N

T25

PCIE_RX0P

T26

PCIE_RX0N

T22

PCIE_RX1P

T23

PCIE_RX1N

M25

PCIE_RX2P

M26

PCIE_RX2N

M22

PCIE_RX3P

M23

PCIE_RX3N

E29

PCIE_CALRP

E28

PCIE_CALRN

E27

PCIE_CALI

AC26

CPU_PG/LDT_PG

W26

INTR/LINT0

W24

NMI/LINT1

W25

INIT#

AA24

SMI#

AA23

SLP#/LDT_STP#

AA22

IGNNE#/SIC

AA26

A20M#/SID

Y27

FERR#

AA25

STPCLK#/ALLOW_LDTSTP

AH9

CPU_STP#/DPSLP_3V#

B24

DPSLP_OD#/GPIO37

W23

DPRSLPVR

AC25

LDT_RST#/DPRSTP#/PROCHOT#

A3

PCI_PME#/GEVENT4#

B2

RI#/EXTEVNT0#

F7

SLP_S3#

A5

SLP_S5#

E3

PWR_BTN#

B5

PWR_GOOD

B3

SUS_STAT#

G9

TEST0

E9

TEST1

F9

TEST2

D9

S3_STATE/GEVENT5#

F4

SYS_RESET#/GPM7#

E7

WAKE#/GEVENT8#

C2

BLINK/GPM6#

G7

SMBALERT#/THRMTRIP#/GEVENT2#

D7

LPC_PME#/GEVENT3#

C25

LPC_SMI#/EXTEVNT1#

AF26

GA20IN

AG26

KBRST#

AG24

LAD0

AG25

LAD1

AH24

LAD2

AH25

LAD3

AF24

LFRAME#

AJ24

LDRQ0#

AH26

LDRQ1#/GNT5#/GPIO68

W22

BMREQ#/REQ5#/GPIO65

AF23

SERIRQ

D2

C1

218S6ECLA13FG_FCBGA548_SB600

SBR1@

4

XTAL

X1

X2

3

SB600 SB

SPDIF_OUT/PCICLK7/GPIO41

PCI EXPRESS INTERFACE

CPUACPI / WAKE UP EVENTS

LPC

PCI CLKS

AD0/ROMA18
AD1/ROMA17
AD2/ROMA16
AD3/ROMA15
AD4/ROMA14
AD5/ROMA13
AD6/ROMA12
AD7/ROMA11

AD8/ROMA9

AD9/ROMA8
AD10/ROMA7
AD11/ROMA6
AD12/ROMA5
AD13/ROMA4
AD14/ROMA3
AD15/ROMA2

AD16/ROMD0
AD17/ROMD1
AD18/ROMD2
AD19/ROMD3
AD20/ROMD4
AD21/ROMD5
AD22/ROMD6
AD23/ROMD7

CBE0#/ROMA10

CBE1#/ROMA1

CBE2#/ROMWE#

DEVSEL#/ROMA0

TRDY#/ROMOE#

PCI INTERFACE

PAR/ROMA19

REQ3#/GPIO70
REQ4#/GPIO71

GNT3#/GPIO72
GNT4#/GPIO73

INTE#/GPIO33
INTF#/GPIO34

INTG#/GPIO35

INTH#/GPIO36

RTC_IRQ#/GPIO69

RTC

RTC_GND

B:Swap PCICLK7 and PCICLK2 for debug CLK fail issue.

U2

PCICLK0

T2

PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6

PCIRST#

AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

CBE3#

FRAME#

IRDY#

STOP#
PERR#
SERR#
REQ0#
REQ1#
REQ2#

GNT0#
GNT1#
GNT2#

CLKRUN#

LOCK#

RTCCLK

VBAT

PCICLK2

R419 22_0402_5%

U1

PCICLK3

V2
W3

PCICLK5

U3
V1
T1

PCIRST# PCIRST#

AJ9

PCI_AD0

W7

PCI_AD1

Y1

PCI_AD2

W8

PCI_AD3

W5

PCI_AD4

AA5

PCI_AD5

Y3

PCI_AD6

AA6

PCI_AD7

AC5

PCI_AD8

AA7

PCI_AD9

AC3

PCI_AD10

AC7

PCI_AD11

AJ7

PCI_AD12

AD4

PCI_AD13

AB11

PCI_AD14

AE6

PCI_AD15

AC9

PCI_AD16

AA3

PCI_AD17

AJ4

PCI_AD18

AB1

PCI_AD19

AH4

PCI_AD20

AB2

PCI_AD21

AJ3

PCI_AD22

AB3

PCI_AD23

AH3

PCI_AD24

AC1

PCI_AD25

AH2

PCI_AD26

AC2

PCI_AD27

AH1

PCI_AD28

AD2

PCI_AD29

AG2

PCI_AD30

AD1

PCI_AD31

AG1
AB9
AF9
AJ5
AG3
AA2
AH6
AG5
AA1
AF7
Y2
AG8
AC11
AJ8
AE2
AG9
AH8
AH5
AD11
AF2
AH7
AB12
AG4
AG7
AF6

AD3
AF1
AF4
AF3

D3
F5

E1
D1

0.1U_0402_16V4Z

1 2

R421 22_0402_5%

1 2

R136 22_0402_5%

1 2

PCIRST# <6,22>

PCI_AD[0..31]

PCI_C/BE#0 <22>
PCI_C/BE#1 <22>
PCI_C/BE#2 <22>
PCI_C/BE#3 <22>
PCI_FRAME# <22>
PCI_DEVSEL# <22>
PCI_IRDY# <22>
PCI_TRDY# <22>
PCI_PAR <22>
PCI_STOP# <22>
PCI_PERR# <22>
PCI_SERR# <22>

PCI_REQ#2 <22>

TP16

PCI_GNT#2 <22>

TP14

PCI_PIRQE# <22>
PCI_PIRQF# <22>

PCI_PIRQG# <22>

TP17

H_PROCHOT# <6>

+SB_VBAT

1

1U_0402_6.3V4Z

2

C251

C250

PCI_AD[0..31] <18,22>

+SB_VBAT

1

2

PCICLK0 <18>

PCICLK1 <18>
CLK_PCI_SIO <34>
CLK_PCI_EC <30>
PCICLK4 <18>
CLK_PCI_CB <22>

PCICLK6 <18>

C:Follow AMD
AP, the series
resistor should
be 500 Ohm

R437
120_0402_5%

1 2

W=20mils

Close to SB600 pin E1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/5/4 2008/5/4

3

Compal Secret Data

Deciphered Date

2

1

B:Change to 8.2K_0402

R415 8.2K_0402_5%

RTC Battery

BATT1

-+

ML1220T13RE45@

+RTCVCC

1 2

R436 120_0402_5%

2

1

2

J4

2

JUMP_43X39@

1

1

2

Title

Size Document Number Rev

Custom

Date: Sheet

12

+RTCBATT

+RTCBATT

12

1

D35
BAS40-04_SOT23-3

2

3

C700

0.1U_0402_16V4Z

+CHGRTC

SB600-PCI_EXP/PCI/LPC/RTC

IALAA-Minnesota10A LA3631P

1

1A

16 45Monday, May 14, 2007

of

5

4

3

2

1

C662 0.01U_0402_25V7K

SATA_STX_C_DRX_P0<21>
SATA_STX_C_DRX_N0<21>

C19510P_0402_50V8J

12

12

Y2

D D

MP:Add U35 and C740, reserve
R1178 for LAN Leakage
problem.

C C

+3V_SB

12

L23

MBC1608121YZF_0603

1

@

C236

0.1U_0402_16V4Z@

2

B B

25MHZ_20P

C18610P_0402_50V8J

12

1 2

R119 8.2K_0402_5%

1 2

R134 2.2K_0402_5%

12

R130
10K_0402_5%@

NB_RST#_R

EC_RSMRST#

NB_RST#<11,15,24,25,28,30,34>

USBCLK_EXT<13>

X1 48MHZ_4P_FN4800002@

4

OUT

VDD

1

GND

OE

NB_RST#

12

R113

10M_0402_5%

+3VALW

5

U35

P

B

4

Y

A

G

3

1 2

R1178 0_0402_5%

1 2

R115 0_0402_5%

OSC_48MHZ USB_48M_EXT

3
2

1 2

12P_0402_50V8J@

1 2

C665 0.01U_0402_25V7K

1 2

SATA_X1

SATA_DTX_C_SRX_P0<21>

SATA_X2

B:Chg. name to HDD_LED# and
dis-connect with EC bec'z
chg. to KB926.

C740

1 2

0.1U_0402_16V4Z

2
1

NC7SZ08P5X_NL_SC70-5

@

R116

30_0402_5%@

2

C217

1

SATA_DTX_C_SRX_N0<21>

+3VS

EC_RSMRST#<30>

NB_RST#_R

USB_48M_EXT

B:Chg. to SPI, DEL
EC_FLASH# from GPM1#

R120 10K_0402_5%

HDD_LED#<32>

SB_OSC_INT<13>

EC_SCI#<30>

EXP_CPPE#<28>

EC_LID_OUT#<30>

EC_SMI#<30>

B:Del GPIO1 bec'z not tri-state pin for app..

+3VS

R409 10K_0402_5%

1 2

R410 2.2K_0402_5%

1 2

R408 2.2K_0402_5%

1 2

A A

SIDERST#
SMB_CK_CLK0
SMB_CK_DAT0

SIDERST#<28>

SMB_CK_CLK0<8,9,13,24,28>
SMB_CK_DAT0<8,9,13,24,28>

SATA_STX_DRX_P0
SATA_STX_DRX_N0

SATA_CAL

R118 1K_0402_1%

1 2

R414 11.8K_0402_1%

USBP9+<28>
USBP9-<28>
USBP8+<24>
USBP8-<24>
USBP7+<29>
USBP7-<29>
USBP6+<29>
USBP6-<29>

USBP5+<29>

USBP5-<29>

USBP4+<29>

USBP4-<29>

USBP3+<24>

USBP3-<24>

USBP2+<29>

USBP2-<29>
USBP1+<29>

USBP1-<29>

USBP0+<29>

USBP0-<29>

SB_SPKR<27>

12

NB_RST#_R
EC_RSMRST#

USB_48M_EXT
USB_RCOMP

12

TP13
TP12

SIDERST#

SMB_CK_CLK0
SMB_CK_DAT0

SATA_X1
SATA_X2

U26B

AH21

SATA_TX0+

AJ21

SATA_TX0-

AH18

SATA_TX1+

AJ18

SATA_TX1-

AH13

SATA_TX2+

AH14

SATA_TX2-

AJ11

SATA_TX3+

AH11

SATA_TX3-

AJ20

SATA_RX0+

AH20

SATA_RX0-

AJ17

SATA_RX1+

AH17

SATA_RX1-

AJ16

SATA_RX2+

AH16

SATA_RX2-

AJ13

SATA_RX3+

AH12

SATA_RX3-

AF12

SATA_CAL

AD16

SATA_X1

AD18

SATA_X2

AC12

SATA_ACT#/GPIO67

AG10

A_RST#

E2

RSMRST#

B23

14M_OSC

A17

USBCLK

A14

USB_RCOMP

A10

USB_ATEST0

A11

USB_ATEST1

H12

USB_HSDP9+

G12

USB_HSDM9-

E12

USB_HSDP8+

D12

USB_HSDM8-

E14

USB_HSDP7+

D14

USB_HSDM7-

G14

USB_HSDP6+

H14

USB_HSDM6-

D16

USB_HSDP5+

E16

USB_HSDM5-

D18

USB_HSDP4+

E18

USB_HSDM4-

G16

USB_HSDP3+

H16

USB_HSDM3-

G18

USB_HSDP2+

H18

USB_HSDM2-

D19

USB_HSDP1+

E19

USB_HSDM1-

G19

USB_HSDP0+

H19

USB_HSDM0-

A8

USB_OC0#/GPM0#

B8

USB_OC1#/GPM1#

C7

USB_OC2#/GPM2#

C8

USB_OC3#/GPM3#

A6

USB_OC4#/GPM4#

B6

USB_OC5#/DDR3_RST#/GPM5#

B4

USB_OC6#/GEVENT6#

C4

USB_OC7#/GEVENT7#

C5

USB_OC8#/AZ_DOCK_RST#/GPM8#

C6

USB_OC9#/SLP_S2/GPM9#

A27

SSMUXSEL/SATA_IS3#/GPIO0

A26

ROM_CS#/GPIO1

B26

SPKR/GPIO2

B27

SMARTVOLT/SATA_IS2#/GPIO4

D23

SHUTDOWN#/GPIO5

B29

GHI#/SATA_IS1#/GPIO6

A23

WD_PWRGD/GPIO7

C26

DDC1_SDA/GPIO8

D26

DDC1_SCL/GPIO9

C28

SATA_IS0#/GPIO10

A4

LLB#/GPIO66

C27

SCL0/GPOC0#

B28

SDA0/GPOC1#

SBR1@

C3

SCL1/GPOC2#

F3

SDA1/GPOC3#

SB600 SB

SERIAL ATA

USB INTERFACEOSC / RST

218S6ECLA13FG_FCBGA548_SB600

IDE_D0/GPIO15
IDE_D1/GPIO16
IDE_D2/GPIO17
IDE_D3/GPIO18
IDE_D4/GPIO19
IDE_D5/GPIO20
IDE_D6/GPIO21
IDE_D7/GPIO22
IDE_D8/GPIO23

IDE_D9/GPIO24
IDE_D10/GPIO25
IDE_D11/GPIO26

P-ATA 66/100

IDE_D12/GPIO27
IDE_D13/GPIO28
IDE_D14/GPIO29
IDE_D15/GPIO30

SPI_DI/GPIO12

SPI_DO/GPIO11

SPI_CLK/GPIO47

SPI_HOLD#/GPIO31

SPI_CS#/GPIO32

SPI ROM

LAN_RST#/GPIO13

ROM_RST#/GPIO14

FANOUT0/GPIO3
FANOUT1/GPIO48
FANOUT2/GPIO49

FANIN0/GPIO50
FANIN1/GPIO51
FANIN2/GPIO52

TEMPIN0/GPIO61
TEMPIN1/GPIO62
TEMPIN2/GPIO63

TEMPIN3/TALERT#/GPIO64

HW MONITOR

USB OC

AZ_SDIN3/GPIO46

AZALIA

AC_BITCLK/GPIO38

AC_SDOUT/GPIO39
ACZ_SDIN0/GPIO42
ACZ_SDIN1/GPIO43

AC97

ACZ_SDIN2/GPIO44

GPIO/ SMBUS

AC_SYNC/GPIO40

AC_RST#/GPIO45

IDE_IORDY

IDE_IRQ

IDE_A0
IDE_A1
IDE_A2

IDE_DACK#

IDE_DRQ

IDE_IOR#
IDE_IOW#
IDE_CS1#
IDE_CS3#

TEMP_COMM

VIN0/GPIO53
VIN1/GPIO54
VIN2/GPIO55
VIN3/GPIO56
VIN4/GPIO57
VIN5/GPIO58
VIN6/GPIO59
VIN7/GPIO60

AZ_BITCLK
AZ_SDOUT

AZ_SYNC

AZ_RST#

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8

AB29
AA28
AA29
AB27
Y28
AB28
AC27
AC29
AC28
W28
W27

AD28
AD26
AE29
AF27
AG29
AH28
AJ28
AJ27
AH27
AG27
AG28
AF28
AF29
AE28
AD25
AD29

J3
J6
G3
G2
G6

C23
G5

M4
T3
V4

N3
P2
W4

P5
P7
P8
T8
T7

V5
L7
M8
V6
M6
P4
M7
V7

N2
M2
K2
L3
K3

L1
L2
L4
J2
J4
M3
L5

E23
AC21
AD7
AE7
AA4
T4
D4
AB19

IDE_SDD0
IDE_SDD1
IDE_SDD2
IDE_SDD3
IDE_SDD4
IDE_SDD5
IDE_SDD6
IDE_SDD7
IDE_SDD8
IDE_SDD9
IDE_SDD10
IDE_SDD11
IDE_SDD12
IDE_SDD13
IDE_SDD14
IDE_SDD15

BT_DET#

5IN1_EN
CIR_EN#

AZ_BITCLK
AZ_SDOUT

AZ_SYNC
AZ_RST#

AZ_RST#

IDE_SDIORDY <28>

INT_IRQ15 <28>

IDE_SDA0 <28>
IDE_SDA1 <28>
IDE_SDA2 <28>
IDE_SDDACK# <28>
IDE_SDDREQ <28>
IDE_SDIOR# <28>
IDE_SDIOW# <28>
IDE_SDCS1# <28>
IDE_SDCS3# <28>

BT_DET# <29>
SPK_SEL <26>

SB_INT_FLASH_SEL <31>

EC_THERM# <30>

AZ_SDIN3_HD <26>

AC97_SDOUT <18>

AZ_SDIN0_MD <28>

12

R14010K_0402_5%

IDE_SDD[0..15] <28>

B:1.Add PU R479 for BT_DET#

2.Chg. BT_DET# from GPIO0 to GPIO51.

BT_DET#

5IN1_EN

B:Chg. name to 5IN1_EN

CIR_EN#

A:ISKAA-Add for CIR floating casue S3 shut down issue
B:Chg. name to CIR_EN#

B:Move SB_INT_FLASH_SEL to GPIO63 bec'z
GPIO1 is not tri-state pin in SB600

AZ_BITCLK

AZ_SDOUT

AZ_SYNC

AZ_RST#

B:Del HDMI audio fun. bec'z remove SiI1932.

A:PA_IXP600AF3 reserve for SB600 prior to A21.

12

+3VS

1 2

R128 1K_0402_5%5IN1@

1 2

R466 100K_0402_5%

1 2

R124 100K_0402_5%

1 2

R122 1K_0402_5%CIR@

+3VS

R47910K_0402_5%

0: 5IN1 Disable
1: 5IN1 Enable

+3VS

R15833_0402_5%

12

R16033_0402_5%MDC@

12

R16133_0402_5%

12

R16333_0402_5%MDC@

12

R15533_0402_5%

12

R15733_0402_5%MDC@

12

R15233_0402_5%

12

R15433_0402_5%MDC@

12

AZ_BITCLK_HD <26>
AZ_BITCLK_MD <28>

AZ_SDOUT_HD <26>
AZ_SDOUT_MD <28>

AZ_SYNC_HD <26>
AZ_SYNC_MD <28>

AZ_RST_HD# <26>
AZ_RST_MD# <28>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/5/4 2008/5/4

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

SB600-USB/ACPI/AC97/GPIO

IALAA-Minnesota10A LA3631P

1

1A

17 45Monday, May 14, 2007

of

5

D D

4

3

2

1

Standard Straps

+3VS+3VS +3VS +3VS+3VS

12

R418

2.2K_0402_5%@

AC97_SDOUT<17>

PCICLK4<16>
PCICLK6<16>
PCICLK1<16>

PCICLK0<16>

C C

12

R139

10K_0402_5%@

12

R133
10K_0402_5%

12

R420
10K_0402_5%

12

R146
10K_0402_5%

12

R147

10K_0402_5%@

12

R145

10K_0402_5%@

12

R144
10K_0402_5%

Debug Straps

PCI_AD28<16,22>
PCI_AD27<16,22>
PCI_AD26<16,22>
PCI_AD25<16,22>
PCI_AD24<16,22>

12

R149

2.2K_0402_5%@

12

R142

2.2K_0402_5%@

12

R151

2.2K_0402_5%@

12

R138

2.2K_0402_5%@

12

R150

2.2K_0402_5%@

AC_SDOUT

PULL
HIGH

PULL
LOW

B B

Un-Used Inputs Setting--GPIO pins

USE
DEBUG
STRAPS

IGNORE
DEBUG
STRAPS
<int'l PD>

DEFAULT

PCI_CLK4
<PCICLK4>

USE INT.
PLL48

USE EXT.
48MHZ

DEFAULT

GPIO4/SMAR TVOLT/SATA_IS2#

GPIO5/SHUTDOWN#

GPIO7/WD_PWRGD

GPIO8/DDC1_SDA

GPIO9/DDC1_SCL

GPIO10/SATA_IS0#

GPIO41/PCICLK7/SPDIF_OUT

GPIO50/FANIN0

A A

GPIO51/FANIN1

GPIO52/FANIN2

GPIO53/VIN0

GPIO54/VIN1

GPIO55/VIN2

5

PCI_CLK6
<PCICLK6>

CPU IF=AMD

DEFAULT

PCI_CLK1 PCI_CLK0
<CLK_PCI_LAN> <PCICLK0>

ROM TYPE:

CPU IF=Intel

Config. GPIO to Output Mode.

Config. GPIO to Output Mode.

Config. GPIO to Output Mode.

Config. GPIO to Output Mode.

Config. GPIO to Output Mode.

Config. GPIO to Output Mode.

Config. GPIO to Output Mode.

Config. GPIO to Output Mode.

Config. GPIO to Output Mode.

Config. GPIO to Output Mode.

Config. GPIO to Output Mode.

Config. GPIO to Output Mode.

Config. GPIO to Output Mode.

H, H = Reserve
H, L = LPC ROM

DEFAULT

L, H = SPI ROM
L, L = FWH ROM

Un-Used Inputs Setting--GPM pins

GPIO56/VIN3

GPIO57/VIN4

GPIO58/VIN5

GPIO59/VIN6

GPIO60/VIN7

GPIO61/TEMPIN0

GPOC2#/SCL1

GPOC3#/SDA1

4

Config. GPIO to Output Mode.

Config. GPIO to Output Mode.

Config. GPIO to Output Mode.

Config. GPIO to Output Mode.

Config. GPIO to Output Mode.

Config. GPIO to Output Mode.

Config. GPIO to Output Mode.

Config. GPIO to Output Mode.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PCI_AD27

PULL
HIGH

PULL
LOW

USE
LONG
RESET

DEFAULT

USE
SHORT
RESET

USE PCI
PLL

DEFAULT

BYPASS
PCI PLL

Un-Used Inputs Setting--GPM pins

GPM5#/DDR3_RST#/USB_OC5#

GEVENT5#/S3_STATE

2007/5/4 2008/5/4

3

Compal Secret Data

Deciphered Date

USE ACPI
BCLK

DEFAULT

BYPASS
ACPI
BCLK

Config. for internal PU.

Config. for internal PU.

2

PCI_AD25PCI_AD28 PCI_AD26

USE IDE
PLL

DEFAULT

BYPASS IDE
PLL

PCI_AD24

USE DEFAULT
PCIE STRAPS

DEFAULT

USE EEPROM
PCIE STRAPS

Title

Size Document Number Rev

Custom

Date: Sheet

PCI_AD23
<A11 only>

DISABLE
BOOTFAIL
TIMER

DEFAULT

ENABLE
BOOTFAIL
TIMER

SB600-IDE/SATA/STRAPS

IALAA-Minnesota10A LA3631P

1

18 45Monday, May 14, 2007

of

1A

B:Update footprint w/o
wrong polar mark.

C190 1U_0402_6.3V4Z

1 2

C227 1U_0402_6.3V4Z

1 2

C193 1U_0402_6.3V4Z

1 2

C200 1U_0402_6.3V4Z

1 2

C240 1U_0402_6.3V4Z

1 2

C191 1U_0402_6.3V4Z

1 2

C233 0.1U_0402_16V4Z

1 2

C226 0.1U_0402_16V4Z

1 2

C210 0.1U_0402_16V4Z

1 2

C676 0.1U_0402_16V4Z

1 2

+1.2V_HT

1 2

MBK2012221YZF 0805

C202 22U_A_4VM
C208 1U_0402_6.3V4Z

1 2

C219 1U_0402_6.3V4Z

1 2

C205 1U_0402_6.3V4Z

1 2

C216 1U_0402_6.3V4Z

1 2

C220 0.1U_0402_16V4Z

1 2

C214 0.1U_0402_16V4Z

1 2

C678 22U_A_4VM
C253 1U_0402_6.3V4Z

1 2

C230 1U_0402_6.3V4Z

1 2

C234 0.1U_0402_16V4Z

1 2

C248 0.1U_0402_16V4Z
C239 0.1U_0402_16V4Z
C686 0.1U_0402_16V4Z
C682 0.1U_0402_16V4Z
C242 10U_0805_10V4Z@

+

L20

+

+

12
12
12
12
12

C657

12

220U_Y_4VM

12

12

+3VS

SB_VDD_33=150mA

+1.2VS_SB_VDD

+1.2VS_SB_VDD

SB_VDD_12=500mA

+3V_SB

SB_S5_33=15mA

+1.2V_SB

+1.2V_SB

SB_AVDDCK_12=80mA

+PCIE_VDDR

SB_PCIEPVDDR_12=450mA

L60

12

+1.2V_HT +PCIE_VDDR

+1.2V_HT +PCIE_PVDD

MP:Change C647 to 22u for sequence and L59 to
DCR is 0.4Ohm to meet AMD requirement.

FBMA-L11-201209-221LMA30T_0805

+

12

C646 22U_A_4VM
C187 1U_0402_6.3V4Z

1 2

C192 1U_0402_6.3V4Z

1 2

C189 1U_0402_6.3V4Z

1 2

C648 0.1U_0402_16V4Z

1 2

C649 0.1U_0402_16V4Z

1 2

C650 1U_0402_6.3V4Z
C647 22U_0805_6.3V6M

GND to U28

L59

MBK2012601YZF_0805

1 2
1 2

+PCIE_PVDD

SB_PCIEPVDD_12=35mA

12

+3V_SB

A25
A28
C29
D24

W21

W29
AA12
AA16
AA19

AC4
AC23
AD27

AE1

AE9
AE23
AH29

AJ26

M13

M17

N12

N15

N18

R13

R17

U12

U15

U18

V13

V17

G26

G27

G28

G29

N29

U29

U28

V29

V28

V27

V26

V25

V24

V23

V22

U27

P27

L9

L21

M5

P3
P9
T5

V9
W2
W6

AJ2
AJ6

A2

A7

F1

J5
J7

K1

G4

H1

H2

H3

F27
F28
F29

J27
J29
L25
L26
L29

T29
T28
T27
T24
T21

U26C

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12
VDDQ_13
VDDQ_14
VDDQ_15
VDDQ_16
VDDQ_17
VDDQ_18
VDDQ_19
VDDQ_20
VDDQ_21
VDDQ_22
VDDQ_23
VDDQ_24
VDDQ_25
VDDQ_26
VDDQ_27
VDDQ_28

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12

S5_3.3V_1
S5_3.3V_2
S5_3.3V_3
S5_3.3V_4
S5_3.3V_5
S5_3.3V_6

S5_1.2V_1
S5_1.2V_2
S5_1.2V_3
S5_1.2V_4

PCIE_VDDR_1
PCIE_VDDR_2
PCIE_VDDR_3
PCIE_VDDR_4
PCIE_VDDR_5
PCIE_VDDR_6
PCIE_VDDR_7
PCIE_VDDR_8
PCIE_VDDR_9
PCIE_VDDR_10
PCIE_VDDR_11
PCIE_VDDR_12
PCIE_VDDR_13

PCIE_PVDD
PCIE_PVSS

PCIE_VSS_42
PCIE_VSS_41
PCIE_VSS_40
PCIE_VSS_39
PCIE_VSS_38
PCIE_VSS_37
PCIE_VSS_36
PCIE_VSS_35
PCIE_VSS_34
PCIE_VSS_33
PCIE_VSS_32
PCIE_VSS_31
PCIE_VSS_30
PCIE_VSS_29
PCIE_VSS_28

218S6ECLA13FG_FCBGA548_SB600SBR1@

SB600 SB

POWER

3.3V I/O PWR

Core PWR

3.3V Standby PWR

1.2V Standby PWR

PCIE Analog PWR

VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57

PCIE_VSS_1
PCIE_VSS_2
PCIE_VSS_3
PCIE_VSS_4
PCIE_VSS_5
PCIE_VSS_6
PCIE_VSS_7
PCIE_VSS_8

PCIE_VSS_9
PCIE_VSS_10
PCIE_VSS_11
PCIE_VSS_12
PCIE_VSS_13
PCIE_VSS_14
PCIE_VSS_15
PCIE_VSS_16
PCIE_VSS_17
PCIE_VSS_18
PCIE_VSS_19
PCIE_VSS_20
PCIE_VSS_21
PCIE_VSS_22
PCIE_VSS_23
PCIE_VSS_24
PCIE_VSS_25
PCIE_VSS_26
PCIE_VSS_27

A20
A21
A29
B1
B7
B25
C21
C22
C24
D6
E24
F2
F23
G1
J1
J8
L6
L8
M9
M12
M15
M18
N13
N17
P1
P6
P21
R12
R15
R18
T6
T9
U13
U17
V3
V8
V12
V15
V18
V21
W1
W9
Y29
AA11
AA14
AA18
AC6
AC24
AD9
AD23
AE3
AE27
AG6
AJ1
AJ25
AJ29

D27
D28
D29
F26
G23
G24
G25
H27
J23
J26
J28
K27
L22
L23
L24
L27
L28
M21
M24
M27
N27
N28
P22
P23
P24
P25
P26

L64

+1.2V_HT

C671 1U_0402_6.3V4Z

+3VS +XTLVDD_ATA +XTLVDD_ATA

C209 1U_0402_6.3V4Z

FBMA-L11-201209-221LMA30T_0805

C669 22U_A_4VM
C224 1U_0402_6.3V4Z

1 2

C228 1U_0402_6.3V4Z

1 2

C211 1U_0402_6.3V4Z

1 2

C212 0.1U_0402_16V4Z

1 2

C673 0.1U_0402_16V4Z

1 2

C675 0.1U_0402_16V4Z

1 2

C670 2.2U_0603_6.3V4Z

1 2

C221 0.1U_0402_16V4Z

1 2

GND to A13

C198 1U_0402_6.3V4Z
C666 1U_0402_6.3V4Z
C667 1U_0402_6.3V4Z
C201 1U_0402_6.3V4Z

+3VS +SB_AVDD

1 2

MBC1608121YZF_0603

12

L22

1 2

MBC1608121YZF_0603

12

L63

12

+

C668 22U_A_4VM
C661 1U_0402_6.3V4Z
C197 1U_0402_6.3V4Z
C194 0.1U_0402_16V4Z
C206 0.1U_0402_16V4Z

+

12

C685 2.2U_0603_6.3V4Z
C683 0.1U_0402_16V4Z

12

1 2
1 2
1 2
1 2

12
12
12
12

L65

1 2

MBC1608121YZF_0603

1 2
1 2

+3V_SB

+3V_SB

+1.2V_SB

+PLLVDD_ATA

SB_AVDDSATA_12=300mA

+1.2V_SATA+1.2V_HT

SB_AVDDTX_33=250mA
SB_AVDDRX_33=250mA

C188

0.1U_0402_16V4Z

GND to M1

R131 1K_0402_5%

+5VS
+3VS

1 2

D8

2 1

CH751H-40PT_SOD323-2

C225

1U_0603_10V4Z

2

2

1

1

+V5_VREF

C223

0.1U_0402_16V4Z

SB_PLLVDDSATA_12=65mA

+PLLVDD_ATA

SB_AVDDC_33=5mA

+1.2V_SATA

+3V_SB

SB_AVDDC_33=15mA

+3V_SB

+1.2V_SB

SB_AVDDCK_12=90mA

SB_AVDD_33=1mA

+SB_AVDD

+1.8VS

1

2

SB_CPU_PWR=10mA

+V5_VREF

SB_V5_VREF_5=5mA

+3.3V_AVDDCK

SB_AVDDCK_33=10mA

+1.2V_AVDDCK

SB_AVDDCK_12=40mA

+3VS +3.3 V _AVDDCK

MBC1608121YZF_0603
C659 2.2U_0603_6.3V4Z
C660 0.1U_0402_16V4Z

GND to B22

+1.2V_HT +1.2V_AVDDCK

C663 2.2U_0603_6.3V4Z
C664 0.1U_0402_16V4Z

GND to B22

U26D

AD14

PLLVDD_SATA_1

AJ10

PLLVDD_SATA_2

AC16

XTLVDD_SATA

AE14

AVDD_SATA_1

AE16

AVDD_SATA_2

AE18

AVDD_SATA_3

AE19

AVDD_SATA_4

AF19

AVDD_SATA_5

AF21

AVDD_SATA_6

AG22

AVDD_SATA_7

AG23

AVDD_SATA_8

AH22

AVDD_SATA_9

AH23

AVDD_SATA_10

AJ12

AVDD_SATA_11

AJ14

AVDD_SATA_12

AJ19

AVDD_SATA_13

AJ22

AVDD_SATA_14

AJ23

AVDD_SATA_15

B9

AVDDTX_0

B11

AVDDTX_1

B13

AVDDTX_2

B16

AVDDTX_3

B18

AVDDTX_4

A9

AVDDRX_0

B10

AVDDRX_1

B12

AVDDRX_2

B14

AVDDRX_3

B17

AVDDRX_4

A12

AVDDC

A13

AVSSC

A18

USB_PHY_1.2V_1

A19

USB_PHY_1.2V_2

B19

USB_PHY_1.2V_3

B20

USB_PHY_1.2V_4

B21

USB_PHY_1.2V_5

N1

AVDD

M1

AA27
AE11

A24
A22
B22

HW Monitor PWR

AVSS

CPU_PWR
V5_VREF
AVDDCK_3.3V
AVDDCK_1.2V
AVSSCK

218S6ECLA13FG_FCBGA548_SB600

L61

1 2

1 2
1 2

L62

SBR1@

1 2

MBC1608121YZF_0603

1 2
1 2

SB600 SB

SATA Analog PWR USB Analog PWR

USB PHY Digi. PWR

Special PWR/GND

AVSS_SATA_1
AVSS_SATA_2
AVSS_SATA_3
AVSS_SATA_4
AVSS_SATA_5
AVSS_SATA_6
AVSS_SATA_7
AVSS_SATA_8

AVSS_SATA_9
AVSS_SATA_10
AVSS_SATA_11
AVSS_SATA_12
AVSS_SATA_13
AVSS_SATA_14
AVSS_SATA_15
AVSS_SATA_16
AVSS_SATA_17
AVSS_SATA_18
AVSS_SATA_19
AVSS_SATA_20
AVSS_SATA_21
AVSS_SATA_22
AVSS_SATA_23
AVSS_SATA_24
AVSS_SATA_25
AVSS_SATA_26
AVSS_SATA_27

AVSS_USB_1
AVSS_USB_2
AVSS_USB_3
AVSS_USB_4
AVSS_USB_5
AVSS_USB_6
AVSS_USB_7
AVSS_USB_8

AVSS_USB_9
AVSS_USB_10
AVSS_USB_11
AVSS_USB_12
AVSS_USB_13
AVSS_USB_14
AVSS_USB_15
AVSS_USB_16
AVSS_USB_17
AVSS_USB_18
AVSS_USB_19
AVSS_USB_20
AVSS_USB_21
AVSS_USB_22
AVSS_USB_23
AVSS_USB_24
AVSS_USB_25
AVSS_USB_26
AVSS_USB_27
AVSS_USB_28
AVSS_USB_29
AVSS_USB_30
AVSS_USB_31
AVSS_USB_32
AVSS_USB_33

AB14
AB16
AB18
AC14
AC18
AC19
AD12
AD19
AD21
AE12
AE21
AF11
AF14
AF16
AF18
AG11
AG12
AG13
AG14
AG16
AG17
AG18
AG19
AG20
AG21
AH10
AH19

A16
C9
C10
C11
C12
C13
C14
C16
C17
C18
C19
C20
D11
D21
E11
E21
F11
F12
F14
F16
F18
F19
F21
G11
G21
H11
H21
J11
J12
J14
J16
J18
J19

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/5/4 2008/5/4

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

Date: Sheet

SB600-Power/GND

IALAA-Minnesota10A LA3631P

of

19 45Monday, May 14, 2007

1A

5

B:Remove HDMI transistor, SiI1932; and support by GPU only.

MP:Update D10 to meet HDMI.

D10

+5VS +HDMI_5V_OUT

D D

2 1

RB491D_SOT23

HDMI@

B:Need to open solder door
of J1 for HDMI fun. PWR.

F1 1A_6VDC_MINISMDC110

2 1

J1

112

JUMP_43X79@

HDMI@

2

4

1

C270

HDMI@

0.1U_0402_16V4Z

2

3

MP:Update HDMI Hot Plug DET circuit.

2.2K_0402_5%

VGA_HPD<15>

VGA_DVI_SDATA<15>

VGA_DVI_SCLK<15>

B:1.Level shift circuit for HDMI.

2.Reserve DDC PU Resistor and HPD PU Resistor.

VGA_HPD

VGA_DVI_SCLK

R429

HDMI@

+3VS

12

24K_0402_5%

2

MP:change R431 and R430 to 24K; R1176
and R1177 to 19.2K, follow ATI ER.

12

12

R431

@

R430

@

24K_0402_5%

G

2

S

G

2

Q134

D

S

2N7002_SOT23-3

HDMI@

Q135

13

D

2N7002_SOT23-3

HDMI@

12

R1176

HDMI@

19.1K_0402_1%

13

C:Chg. PN to SB770020010.

1

+HDMI_5V_OUT

12

R1177

HDMI@

19.1K_0402_1%

HDMI_SDATAVGA_DVI_SDATA

HDMI_SCLK

HDMI Connector

VGA_DVI_TXD1-<15>

C C

VGA_DVI_TXD1+<15>

VGA_DVI_TXD2-<15>

VGA_DVI_TXD2+<15>

VGA_DVI_TXD1- HDMI_R_D1-

VGA_DVI_TXD1+

VGA_DVI_TXD2+ HDMI_R_D0+

1 2

L68

1

1

4

4

WCM-2012-900T_0805HDMI@

1 2

1 2

L69

1

1

4

4

WCM-2012-900T_0805HDMI@

1 2

R440

0_0402_5%

@

2

3

R441

0_0402_5%

@

R442

0_0402_5%

@

2

3

R444

0_0402_5%

@

VGA_DVI_TXC-<15>

2

3

2

3

PreMP:Change to common choke for EMI

HDMI_R_D1+

HDMI_R_D2-VGA_DVI_TXD2-

VGA_DVI_TXC+<15>

VGA_DVI_TXD0-<15>

PreMP:Change to common choke for EMI

HDMI_R_D2+

VGA_DVI_TXD0+<15>

VGA_DVI_TXC- HDMI _R_CK-

VGA_DVI_TXD0-

VGA_DVI_TXD0+

L66

1

1

4

4

WCM-2012-900T_0805HDMI@

L67

1

1

4

4

WCM-2012-900T_0805HDMI@

1 2

1 2

1 2

1 2

R432

0_0402_5%

@

2

3

R434

0_0402_5%

@

R435

0_0402_5%

@

2

3

R438

0_0402_5%

@

2

3

HDMI_R_CK+VGA_DVI_TXC+

HDMI_R_D0-

2

3

+HDMI_5V_OUT

HDMI_HPD

HDMI_SDATA
HDMI_SCLK

HDMI_R_CK­HDMI_R_CK+

HDMI_R_D0-

HDMI_R_D0+

HDMI_R_D1-

HDMI_R_D1+

HDMI_R_D2-

HDMI_R_D2+

JP35

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

TYCO_1939864-1

HDMI@

GND
GND
GND
GND

20
21
22
23

+HDMI_5V_OUT

C739

HDMI@

2

1

1

5

P

VGA_HPD

4

OE#

A2Y

G

U34
SN74AHCT1G125GW_SOT353-5

3

HDMI@

R425

100K_0402_5%

HDMI@

1 2

C694

2

0.1U_0402_16V4Z

HDMI@

1

HDMI_HPD

0.1U_0402_16V4Z

B B

MP:Update HDMI Hot Plug DET circuit, to add U34, C739.

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/5/4 2008/5/4

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet

Compal Electronics, Inc.

SiI1392&HDMI Connector

IALAA-Minnesota10A LA3631P

20 45Monday, May 14, 2007

1

of

1A

5

4

3

2

1

+5VS

D D

C C

1

C684
10U_0805_10V4Z

2

+3VS

1

C697
10U_0805_10V4Z

@

2

Place closely JP25 SATA CONN.

C691

1

C687

0.1U_0402_16V4Z

2

1

C693

0.1U_0402_16V4Z@

2

1

C680
10U_0805_10V4Z

2

1

0.1U_0402_16V4Z@

2

1

C689

0.1U_0402_16V4Z

2

1

C696

0.1U_0402_16V4Z@

2

1

C690

0.1U_0402_16V4Z

2

JP34

GND

A+

A-

GND

B-

B+

GND

V33
V33

V33
GND
GND
GND

V5
V5
V5

GND

Reserved

GND

GND
GND

V12

V12

V12

24
23

OCTEK_SAT-22SO1G_RV

1
2
3
4
5
6
7

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

SATA_DTX_SRX_N0
SATA_DTX_SRX_P0

C699 0.01U_0402_25V7K

1 2
1 2

C698 0.01U_0402_25V7K

+3VS

+5VS

SATA_STX_C_DRX_P0 <17>

SATA_STX_C_DRX_N0 <17>

SATA_DTX_C_SRX_N0 <17>
SATA_DTX_C_SRX_P0 <17>

SATA HDD Conn.

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/5/4 2008/5/4

3

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Custom

2

Date: Sheet of

HDD/CDROM
IALAA-Minnesota10A LA3631P

21 45Monday, May 14, 2007

1

1A

5

+3VS

MBK1608301YZF_0603

L25

D D

SDCLK

R213 22_0402_5%5IN1@

MSCLK

R214 22_0402_5%5IN1@

SMELWP#

R215 22_0402_5%5IN1@

C C

22P_0402_50V8J

B B

P-TWO_CU804B-A0G1G-P

1394@

B:ISKAE,re-link to
"AMP_440168-2_4P-S"

+3VS

R174

A A

place near Chip 8412

place near Chip 8412

CLK_48M_CB

R196

33_0402_5%

C320

JP37

8

GND

7

GND

6

GND

5

GND

1 2

4.7K_0402_5%

1394@

C280

1394@

TPA+

TPA-

TPB+

TPB-

1 2
1

2

2

1

4
3
2
1

R179

1394@

C276

1394@

CPS

MP: Add R196 and
C320 in BOM as EMI
request.

CLK_48M_CB<13>

1U_0402_6.3V4Z

56.2_0402_1%

220P_0402_50V8J

12

1394@

12

1

2

12
12
12

+3VS

12

R177

R178

1394@

56.2_0402_1%

12

R180

1394@

56.2_0402_1%

12

R175

1394@

5.1K_0402_1%

CLOSE TO CHIP

24.576MHz_16P_3XG-24576-43E1

+AVDD_7412

0.1U_0402_16V4Z

12

1

1

C279

C275

0.1U_0402_16V4Z

R173 1K_0402_1%
R181 4.7K_0402_5%

56.2_0402_1%

C285 1U_0402_6.3V4Z
R170

R169 1K_0402_1%

1394@

2

2

MC_PWRON#
SM_RB

SD_CD#
MS_CD#

MSCLK_SDCLK_SMELWP#
MSBS_SDCMD_SMWE#
MSD3_SDD3_SMD3
MSD2_SDD2_SMD2
MSD1_SDD1_SMD1
MSD0_SDD0_SMD0

SMRE
SDCMD_SMALE
SDD0_SMD4
SDD1_SMD5
SDD2_SMD6
SDD3_SMD7
SDWP#_SMCE#

SMCLE
XD_CD#

1 2

CLK_48M_CB

1 2

1394@

R186 6.34K_0402_1%

1 2

XTPBIAS0
XTPA0+
XTPA0­XTPB0+
XTPB0-

1 2

1394@

1K_0402_1%1394@

1 2
1 2

CPS
X_OUT

X_IN

C31018P_0402_50V8J

C30418P_0402_50V8J

X_OUT

X2

1 2

0.01U_0402_25V4Z

X_IN

0.01U_0402_25V4Z

1

C281

2

U11B

C8

MC_PWR_CTRL_0

F8

MC_PWR_CTRL_1/SM_R/B#

E9

SD_CD#

A8

MS_CD#

B8

SM_CD#

A7

MS_CLK/SD_CLK/SM_EL_WP#

E8

MS_BS/SD_CMD/SM_WE#

B6

MS_DATA3/SD_DAT3/SM_D3

A6

MS_DATA2/SD_DAT2/SM_D2

C7

MS_DATA1/SD_DAT1/SM_D1

B7

MS_SDIO(DATA0)/SD_DAT0/SM_D0

A4

SD_CLK/SM_RE#

C5

SD_CMD/SM_ALE

C6

SD_DAT0/SM_D4

A5

SD_DAT1/SM_D5

B5

SD_DAT2/SM_D6

E6

SD_DAT3/SM_D7

E7

SD_WP/SM_CE#

G5

SC_PWR_CTRL

B4

SM_CLE

A3

XD_CD#/SM_PHYS_WP#

P12

TEST0

F1

CLK_48

P17

PHY_TEST_MA

T18

R0

T19

R1

R13

TPBIAS0

V14

TPA0P

W14

TPA0N

V13

TPB0P

W13

TPB0N

W17

TPBIAS1

V16

TPA1P

W16

TPA1N

V15

TPB1P

W15

TPB1N

R12

CPS

R18

XO

R19

XI

8412@

PCI7412ZHK_PBGA257

1

2

C289

4

1

C278
10U_0805_10V4Z

2

P13

P14

AVDD_33

AVDD_33

P15

U19

U15

AVDD_33

VDDPLL_15

VDDPLL_33

PCI7412

AGND

AGND

AGND

R17

R14

U13

U14

+CB_VDDPLL33

C282

10U_0805_10V4Z

C295

VSSPLL

1 2

0.1U_0402_16V4Z

1 2

C319 1U_0603_10V4Z

K19

W8

VCCPP1VCCP

VR_PORTK1VR_PORT

VSSPLL

VSSPLL

0.01U_0402_25V4Z

1

1

C294

C296

2

2

0.01U_0402_25V4Z

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10

AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

C/BE3#
C/BE2#
C/BE1#
C/BE0#

PAR

FRAME#

TRDY#

IRDY#

STOP#

DEVSEL#

IDSEL
PERR#
SERR#

REQ#
GNT#

PCLK

PRST#

GRST#

RI_OUT#/PME#

SUSPEND#

SPKROUT

MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6

SCL
SDA

VR_EN#

1K_0402_1%

R190

M1
M2
M3
M6
M5
N1
N2
N3
P3
R1
R2
P5
R3
T1
T2
W4
W7
R8
U8
V8
W9
V9
U9
R9
V10
U10
R10
W11
V11
U11
P11
R11

P2
U5
V7
W10

U7
R6
W5
V5
V6
U6
N5
R7
W6
L3
L2

L1
K3
K5
L5

J5
H3
G1

H5
H2
H1
J1
J2
J3

G2
G3

K2

3

1

2

1

1

C299

0.1U_0402_16V4Z

2

2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

2

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

R184
100_0402_5%

CLK_PCI_CB

R192

1 2

43K_0402_5%

R193 43K_0402_5%

1 2

DEVICE_ID
5IN1_LED

1

C311

0.1U_0402_16V4Z

2

1 2

MBK1608301YZF_0603

1 2

C298

L26

PCI8412:5IN1 + 1394 + CardBus
PCI8402:5IN1 + 1394

0.01U_0402_25V4Z

1

C343

C738 22P_0402_50V8J
C737 22P_0402_50V8J

C302

2

0.1U_0402_16V4Z

PCI_AD[0..31]

C:Chg. Q32 and Q23 PN to
SB770020010.

10K_0402_5%

PCI_C/BE#3 <16>
PCI_C/BE#2 <16>
PCI_C/BE#1 <16>
PCI_C/BE#0 <16>

PCI_AD20

12

+3VS

12

R191 10K_0402_5%

R200 300_0402_5%

1 2
1 2

R199 300_0402_5%

1 2
1 2

MP: Add C737 and
C738 for EMI
request

+3VS

1

C286

2

0.01U_0402_25V4Z

PCI_AD[0..31] <16,18>

5IN1_LED

R225

PCI_PAR <16>
PCI_FRAME# <16>
PCI_TRDY# <16>

PCI_IRDY# <16>

PCI_STOP# <16>

PCI_DEVSEL# <16>
PCI_PERR# <16>

PCI_SERR# <16>
PCI_REQ#2 <16>
PCI_GNT#2 <16>

CLK_PCI_CB <16>

PCIRST# <6,16>

PCM_SPK <27>
PCI_PIRQE# <16>

PCI_PIRQF# <16>
PCI_PIRQG# <16>
SERIRQ <16,30,34>

+3VS

1

C301

2

5 IN 1 LED

2

G

1 2

DEVICE_ID

+3VS

2

C284

1U_0603_10V4Z

1

+5VS

12

R254

5IN1@

120_0402_5%

21

D24

5IN1@

HT-191NB_BLUE_0603

13

D

Q32

5IN1@

2N7002_SOT23-3

S

MSD0_SDD0_SMD0
MSD1_SDD1_SMD1
MSD2_SDD2_SMD2
MSD3_SDD3_SMD3
SDD0_SMD4
SDD1_SMD5
SDD2_SMD6
SDD3_SMD7

MSBS_SDCMD_SMWE#
SMELWP#
SDCMD_SMALE
XD_CD#
SM_RB
SMRE
SDWP#_SMCE#
SMCLE

2

+5VS

5 In 1 Card Power Switch

+3VS

R182

R195
10K_0402_5%

8412@

1 2

R194
100_0402_5%

8402@

1 2

10K_0402_5%

MC_PWRON#

1 2

CLK_PCI_CB

1
2
3
4

R189

1 2
1

2

5 in 1 CardReader Conn.

JP36

41

XD-VCC

33

XD-D0

34
35
36
37
38
39
40

30
31
29
23
25
26
27
28

32
24

42
18

4 IN 1 CONN

XD-D1
XD-D2
XD-D3
XD-D4
XD-D5
XD-D6
XD-D7

XD-WE
XD-WP
XD-ALE
XD-CD
XD-R/B
XD-RE
XD-CE
XD-CLE

XD-GND
XD-GND

N.C.
N.C.

TAITW_R007-530-L3

5IN1@

MSBS_SDCMD_SMWE#

SMRE

SDWP#_SMCE#

SM_RB

+VCC_5IN1

U9

GND
IN
IN

EN#

G528P1UF_SO8

5IN1@

10_0402_5%@

C309

22P_0402_50V8J@

SD-WP-COM

GND47GND

48

8

OUT

7

OUT

6

OUT

5

FLG

0.1U_0402_16V4Z

MC_PWRON#

2N7002_SOT23-3

15

SD-VCC

9

MS-VCC

SD_CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3

SD-CMD

SD-CD-SW

SD-CD-COM

SD-WP-SW

MS-SCLK
MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3

MS-INS

SD-GND
SD-GND
MS-GND
MS-GND

B:IALAA only to add Pin47
and Pin48 to link to GND.

MS-BS

SDCLK

16

MSD0_SDD0_SMD0

19

MSD1_SDD1_SMD1

20

MSD2_SDD2_SMD2

11

MSD3_SDD3_SMD3

12

MSBS_SDCMD_SMWE#

13

SD_CD#

21
22

SDWP#_SMCE#

43
44

MSCLK

8

MSD0_SDD0_SMD0

4

MSD1_SDD1_SMD1

3

MSD2_SDD2_SMD2

5

MSD3_SDD3_SMD3

7

MS_CD#

6

MSBS_SDCMD_SMWE#

2
14
17
1
10

1

+3VS

0.1U_0402_16V4Z

C291

1 2

R176 100K_0402_5%

5IN1@

1 2

R168 100K_0402_5%

5IN1@

1 2

R187 100K_0402_5%

5IN1@

1 2

R167 22K_0402_5%

5IN1@

C292

C297

5IN1@

5IN1@

1U_0603_10V4Z

+VCC_5IN1

R188

5IN1@

470_0805_5%

Q23

2

5IN1@

G

C288

4.7U_0805_10V4Z

+VCC_5IN1

1

C283

5IN1@

2

4.7U_0805_10V4Z

12

13

D

S

+VCC_5IN1+VCC_5IN1

Bottom Side, Normal Insertion

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

2007/5/4 2008/5/4

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

Date: Sheet

2

Compal Electronics, Inc.

TI PCI8412 PCI/1394/5IN1

IALAA-Minnesota10A LA3631P

22 45Tuesday, May 1 5, 2007

1

1A

of

5

4

3

2

1

CardBus Power Switch

U13

9

+5VS

+3VS

R229

PCMCIA@

10K_0402_5%

1 2

12V

5

5V

6

5V

3

3.3V

4

3.3V
GND

7

+S1_VCC

+S1_VCC

C:Symol with wrong Layout Symbol. Update Footprint
"DC000003D00 (FOX_1CA41121-TC-4F_68P_LT)"

+3VS+S1_VCC

D D

PCMCIA@

S1_D10
S1_D9
S1_D1
S1_D8
S1_D0
S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A25
S1_A7
S1_A24
S1_A17
S1_IOWR#
S1_A9
S1_IORD#

S1_CD1#

S1_CD2#

S1_A11
S1_OE#
S1_CE2#
S1_A10
S1_D15
S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_D3

S1_REG#
S1_A12
S1_A8
S1_CE1#

S1_A13
S1_A23
S1_A22
S1_A15
S1_A20
S1_A21
S1_A19
S1_A14
S1_WAIT#
S1_INPACK#
S1_WE#
S1_BVD1
S1_WP
S1_A16
S1_RDY#

S1_RST
S1_BVD2
S1_CD1#

S1_CD2#
S1_VS1
S1_VS2

C C

C314

C342

R202

1 2

33_0402_5%PCMCIA@

12

PCMCIA@

100P_0402_25V8K

12

PCMCIA@

100P_0402_25V8K

B B

S1_A16_C

U11A

C10

CAD31/D10

A10

CAD30/D9

F11

CAD29/D1

E11

CAD28/D8

C11

CAD27/D0

B13

CAD26/A0

C13

CAD25/A1

A14

CAD24/A2

B14

CAD23/A3

B15

CAD22/A4

E14

CAD21/A5

A16

CAD20/A6

D19

CAD19/A25

E17

CAD18/A7

F15

CAD17/A24

H19

CAD16/A17

J17

CAD15/IOWR#

J15

CAD14/A9

J18

CAD13/IORD#

K15

CAD12/A11

K17

CAD11/OE#

K18

CAD10/CE2#

L15

CAD9/A10

L18

CAD8/D15

L19

CAD7/D7

M17

CAD6/D13

M18

CAD5/D6

N19

CAD4/D12

M15

CAD3/D5

N17

CAD2/D11

N18

CAD1/D4

P19

CAD0/D3

E13

CC/BE3#/REG#

E18

CC/BE2#/A12

H18

CC/BE1#/A8

L17

CC/BE0#/CE1#

H14

CPAR/A13

E19

CFRAME#/A23

G15

CTRDY#/A22

F17

CIRDY#/A15

G18

CSTOP#/A20

F19

CDEVSEL#/A21

H15

CBLOCK#/A19

G19

CPERR#/A14

C12

CSERR#/WAIT#

C14

CREQ#/INPACK#

G17

CGNT#/WE#

A12

CSTSCHG/BVD1(STSCHG#/RI#)

A11

CCLKRUN#/WP(IOIS16#)

F18

CCLK/A16

E12

CINT#/READY(IREQ#)

C15

CRST#/RESET

B12

CAUDIO/BVD2(SPKR#)

N15

CCD1#/CD1#

B11

CCD2#/CD2#

A13

CVS1/VS1#

B16

CVS2/VS2#

E10

A_USB_EN#

PCI7412ZHK_PBGA2578412@

C3240.1U_0402_16V4Z

A15

J19

VCCB

VCCB

PCI 7412

GNDF7GND

F10

VCCF6VCCF9VCC

GND

GND

F13

G14

F12

F14

VCC

GNDH6GNDK6GND

K14

J14

VCCJ6VCC

GND

M14

L14

VCCL6VCC

VCCP6VCCP8VCC

GNDN6GNDP7GND

P9

P10

C287

0.1U_0402_16V4Z

DATA/VD2/VPPD1

CLOCK/VD1/VCCD0#

LATCH/VD3/VPPD0

RSVD/VD0/VCCD1#

0.1U_0402_16V4Z

C308

B9
A9
C9

B10

RSVD/D2

C4
D1

RSVD

E1

RSVD

E2

RSVD

E3

RSVD

F2

RSVD

F3

RSVD

F5

RSVD

G6

RSVD

H17

RSVD

M19

RSVD

A2

NC

A17

NC

A18

NC

B1

NC

B2

NC

B3

NC

B17

NC

B18

NC

B19

NC

C1

NC

C2

NC

C3

NC

C16

NC

C17

NC

C18

NC

C19

NC

D2

NC

D3

NC

D17

NC

D18

NC

E5

NC

N14

NC

P18

NC

T3

NC

T17

NC

U1

NC

U2

NC

U3

NC

U4

NC

U12

NC

U16

NC

U17

NC

U18

NC

V1

NC

V2

NC

V3

NC

V4

NC

V12

NC

V17

NC

V18

NC

V19

NC

W2

NC

W3

NC

W12

NC

W18

NC

C303

0.1U_0402_16V4Z

S1_D2

R216 0_0402_5%

S1_A18
S1_D14

VPPD1
VCCD0#
VPPD0

+3VS

12

Near to PCMCIA slot.

+S1_VCC

1

C260

PCMCIA@

10U_0805_10V4Z

2

+S1_VPP

1

C266

PCMCIA@

10U_0805_10V4Z

2

B:Set to "@".

B:Set to "@".

VCCD1#

R217

PCMCIA@

43K_0402_5%

1 2

1

C259

PCMCIA@

0.1U_0402_16V4Z

2

1

C265

PCMCIA@

0.1U_0402_16V4Z

2

C349

PCMCIA@

C341

C354
C364

0.1U_0402_16V4Z

4.7U_0805_10V4Z@

0.1U_0402_16V4ZPCMCIA@

4.7U_0805_10V4Z@

13

VCC

12

VCC

11

VCC

10

VPP

1

VCCD0

2

VCCD1

15

VPPD0

14

VPPD1

8

OC

SHDN

PCMCIA@

16

TPS2211AIDBR_SSOP16

S1_D4
S1_D6
S1_CE1#
S1_OE#
S1_A9
S1_A13
S1_WE#

+S1_VCC

S1_A16_C
S1_A12
S1_A6
S1_A4
S1_A2
S1_A0
S1_D1
S1_WP

S1_D11
S1_D13
S1_D15
S1_VS1
S1_IOWR#
S1_A18
S1_A20

+S1_VCC

S1_A22
S1_A24
S1_VS2
S1_WAIT#
S1_REG#
S1_BVD1
S1_D9
S1_CD2#

40mil

20mil

VCCD0#
VCCD1#
VPPD0
VPPD1

+S1_VCC

+S1_VPP

C352

1 2

C347
C361

1 2

C339

1 2

C334

1 2

B:Set to "@".

JP21

GND1DATA3
DATA43DATA5
DATA65DATA7
CE1#7ADD10
OE#9ADD11
ADD911ADD8
ADD1313ADD14
WE#15READY
VCC17VPP
ADD1619ADD15
ADD1221ADD7
ADD623ADD5
ADD425ADD3
ADD227ADD1
ADD029DATA0
DATA131DATA2
WP33GND
GND35CD1#
DATA1137DATA12
DATA1339DATA14
DATA1541CE2#
VS1#43IORD#
IOWR#45ADD17
ADD1847ADD19
ADD2049ADD21
VCC51VPP
ADD2253ADD23
ADD2455ADD25
VS2#57RESET
WAIT#59INPACK#
REG#61BVD2
BVD163DATA8
DATA965DATA10
CD2#67GND
GND69GND
GND71GND
GND73GND
GND75GND
GND77GND
GND79GND
GND81GND
GND83GND
GND85GND
GND87GND

PCMCIA@

FOX_WZ21131-P4-8F_LT

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88

0.1U_0402_16V4Z@

0.1U_0402_16V4Z@
10U_0805_10V4Z@

0.01U_0402_25V4Z@
1U_0603_10V4Z@

S1_D3
S1_D5
S1_D7
S1_A10
S1_A11
S1_A8
S1_A14
S1_RDY#
+S1_VPP
S1_A15
S1_A7
S1_A5
S1_A3
S1_A1
S1_D0
S1_D2

S1_CD1#
S1_D12
S1_D14
S1_CE2#
S1_IORD#
S1_A17
S1_A19
S1_A21
+S1_VPP
S1_A23
S1_A25
S1_RST
S1_INPACK#
S1_BVD2
S1_D8
S1_D10

+S1_VPP

+S1_VPP

A A

Security Classification

Issued Date

THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2007/5/4 2008/5/4

Compal Secret Data

Deciphered Date

Title

Size Document Number Rev

2

Date: Sheet

Compal Electronics, Inc.

TI PCI8412/CB socket

IALAA-Minnesota10A LA3631P

23 45Monday, May 14, 2007

1

1A

of

Mini-Express Card for 3G

CLKREQ_DVD#<13>

CLK_DVD#<13>
CLK_DVD<13>

PCIE_MRX_C_DVDTX_N0<11>
PCIE_MRX_C_DVDTX_P0<11>

PCIE_MTX_C_DVDRX_N0<11>
PCIE_MTX_C_DVDRX_P0<11>

+3VS

11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

53

Mini-Express Card for WLAN

+3VS_WLAN

C461

WLAN@

0.01U_0402_25V4Z

1

0.1U_0402_16V4Z

2

+3V_WLAN

1

C543

WLAN@

2

1 2

R323 100K_0402_5%

WLAN@

4.7U_0805_10V4Z

A: For WLAN Wake up event.

JP5

1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

GND1

2
4
6

8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

GND2

WLAN@

3
5
7
9

FOX_AS0B226-S40N-7F

3G@

1 2

R294 0_1206_5%

C467

+3VALW_DVD

1

C729

@

+3VALW

SMB_CK_CLK0
SMB_CK_DAT0

4.7U_0805_10V4Z

JP7

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

53

FOX_AS0B226-S40N-7F

WLAN@

0.1U_0402_16V4Z

MP:Swap USB2+/- and USB8+/- for
CAMERA problem.

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

GND1

GND2

2007/5/4 2008/5/4

+3VS

+1.5VS

B:Add +1.5VS on 3G connector to

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

54

+3VS +1.5VS +3V_WLAN

0.01U_0402_25V4Z

PCIE_WAKE#<30>

WLAN_BT_DATA<29>

WLAN_BT_CLK<29>

CLKREQ_WLAN#<13>

CLK_WLAN#<13>
CLK_WLAN<13>

PCIE_MRX_C_WLANTX_N3<10>
PCIE_MRX_C_WLANTX_P3<10>

PCIE_MTX_C_WLANRX_N3<10>
PCIE_MTX_C_WLANRX_P3<10>

support PCIE I/F of HD DVD fun.

+UIM_PWR
UIM_DATA
UIM_CLK
UIM_RESET

1 2

+3VALW_DVD

R278 0_0402_5%@
R275 0_0402_5%@

C495

WLAN@

D28 BAS16_SOT23-33G@

1

2

+UIM_PWR

C:Chg. PN to SC1BAS16000

3G_OFF#
NB_RST#

1 2

R485 0_0603_5%@

USBP8- <17>

USBP8+ <17>
3G_LED# <32>

1

C469

WLAN@

0.1U_0402_16V4Z

PCIE_WAKE#PCIE_WAKE#

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

0.01U_0402_25V7K

A51 request to reserve from ISKAA

SMB_CK_CLK0 <8,9,13,17,28>
SMB_CK_DAT0 <8,9,13,17,28>

C487

WLAN@

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

+3VS

+1.5VS

C725

DVD@

C386

WLAN@

0.1U_0402_16V4Z

XMIT_OFF#
NB_RST#

SMB_CK_CLK0
SMB_CK_DAT0

A:Add USB I/F with WLAN conn.,
reserve to support Realtek WLAN.

Compal Secret Data

Deciphered Date

1

C391

4.7U_0805_10V4Z

2

C:Set to DVD@

1

2

C723

DVD@

0.1U_0402_16V4Z

1

2

NB_RST# <11,15,17,25,28,30,34>

+3V_WLAN

USBP3- <17>
USBP3+ <17>

1

C423

0.1U_0402_16V4Z

2

1

2

+UIM_PWR

C724

4.7U_0805_10V4Z

DVD@

Small/B already had ESD IC

+UIM_PWR

1

C388

0.1U_0402_16V4Z3G@

2

UIM_RESET
UIM_CLK

UIM_DATA

C2: JP1.7 as NC pin
for sordring issue
with PJP1.

12

R265

3G@

4.7K_0402_5%

ACES_85201-06051

3G@

JP1

8

GND

7

GND

6

6

5

5

4

4

3

3

2

2

1

1

Kill SWITCH

+3VALW

+3VALW

2

3

D14

DAN217_SC59@

SW5

5

G2

4

+3VS_WLAN+1.5VS

G1

3

3

2

2

1

1

1BS003-1210L_3P

WLAN@

WL_OFF#<30>

KILL_SW#

Title

MINI PCI SLOT

Size Document Number Rev

IALAA-Minnesota10A LA3631P 1A

B

Date: Sheet

1

+3V_WLAN

5

2

P

B

1

A

G

3

Compal Electronics, Inc.

Monday, May 14, 2007

R246

100K_0402_5%

1 2

KILL_SW# <30>

C387 0.1U_0402_16V4ZWLAN@

1 2

3G_OFF# XMIT_OFF#

4

Y

U15

WLAN@

CH751H-40PT_SOD323-2WLAN@

NC7SZ08P5X_NL_SC70-5

D25

21

of

24 45

5

C92 0.1U_0402_16V7K

PCIE_MRX_C_LANTX_P2<10>

PCIE_MRX_C_LANTX_N2<10>

D D

+3V_LAN

27P_0402_50V8J

+3V_LAN

C C

A:For LAN Wake up

12

C726

8111C@

R31100K_0402_5%

EC_PME#

1

C66
27P_0402_50V8J

2

1

+

2

R291 1K_0402_1%

+3VS

1 2

R482 0_0603_5%

2

C727

8111C@

0.1U_0402_16V4Z

1

1 2

Y1

LAN_X1 LAN_X2

25MHZ_20P

1

C65

2

B:1.For 8111C only.

2.Chg. 100U to 22Ux2 bec'z no enough space.

1

+

C728

8111C@

22U_A_4VM

22U_A_4VM

2

B:For 8111C only.

1 2

8111C@

1000P_0402_25V8J

1 2

C93 0.1U_0402_16V7K

1 2

PCIE_MTX_C_LANRX_P2<10>
PCIE_MTX_C_LANRX_N2<10>

CLK_PCIE_LAN<13>

CLK_PCIE_LAN#<13>

R483 0_0603_5%

C438

1 2

R284 2K_0402_1%100M@

R283 2.49K_0402_1%1G@

1

2

+3V_LAN

R292

15K_0402_5%

NB_RST#<11,15,17,24,28,30,34>

1 2

2

1

Mount for 8101E Only

+LAN_VDD18

12

12

R82

C121

8101E@

0_0402_5%

1

1

2

2

B B

LAN_MDI3­LAN_MDI3+

LAN_MDI2­LAN_MDI2+

LAN_MDI1­LAN_MDI1+

LAN_MDI0­LAN_MDI0+

1

C118

0.01U_0402_25V4Z

A A

1

2

2

8101E@

0_0402_5%

C120

0.01U_0402_25V4Z

0.01U_0402_25V4Z

0.01U_0402_25V4Z

R83

1
2
3

4
5

7
8
9

10
11
12

C135

0.01U_0402_25V4Z

C449

0.01U_0402_25V4Z

U23

1G@

0.5u_GST5009

Place these components
colsed to LAN chip

GST5009 for GIGA LAN
TST1284 for 10/100 LAN

5

4

PCIE_PTX_IRX_P2
PCIE_PTX_IRX_N2

8111C@

EC_PME#<30>

C429

0.1U_0402_16V4Z

8101E@

C458

TCT1
TD1+
TD1-

TCT2
TD2+
TD2-6MX2-

TCT3
TD3+
TD3-

TCT4
TD4+
TD4-

+LAN_CTRL18
+LAN_CTRL15

12

Place Close to Chip

Place Close to Chip

EC_PME#

LAN_X1
LAN_X2

+3V_LAN_R

8101E@

R26 49.9_0402_1%
R24 49.9_0402_1%

12

8101E@

8101E@

R28 49.9_0402_1%

8101E@

R27 49.9_0402_1%

12

8101E@

24

MCT1

23

MX1+

22

MX1-

21

MCT2

20

MX2+

19
18

MCT3

17

MX3+

16

MX3-

15

MCT4

14

MX4+

13

MX4-

R84

75_0402_1%

4

3

1 2

R25

U4

29

HSOP

30

HSON

23

HSIP

24

HSIN

26

REFCLK_P

27

REFCLK_N

20

PERSTB

1

VCTRL18

63

VCTRL15

64

RSET

19

LANWAKEB

36

ISOLATEB

60

CKXTAL1

61

CKXTAL2

62

GVDD

65

EXPOSE_PAD

25

EGND

31

EGND

17

NC

18

NC

35

NC

34

NC

39

NC

40

NC

42

NC

50

NC

51

NC

45

EEDO

47

EDDI/AUX

48

EESK

44

EECS

54

LED3

55

LED2
LED1
LED0

MDIP0
MDIN0
MDIP1
MDIN1

MDIP2
MDIN2
MDIP3
MDIN3

VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15
VDD15

VDD33
VDD33
VDD33

VDD33
AVDD33
AVDD33

AVDD18
AVDD18
AVDD18
AVDD18

EVDD18
EVDD18

RTL8111B_QFN648111B@

56
57

3
4
6
7

9
10
12
13

15
21
32
33
38
41
43
49
52
58

16
37
53
46

2
59

5
8
11
14

22
28

LAN_LINK#
LAN_ACTIVITY#

LAN_MDI0+
LAN_MDI0­LAN_MDI1+
LAN_MDI1-

LAN_MDI2+
LAN_MDI2­LAN_MDI3+
LAN_MDI3-

CLKREQ_LAN

+AVDD33

10U_0805_10V4Z

+AVDD18

3.6K_0402_5%

4

DO

3

DI

2

SK

1

CS

AT93C46-10SI-2.7_SO8

+LAN_VDD15

1 2

R480 0_0603_5%

B:Mount for 8101E and 8111B.

+3V_LAN

+AVDD33

C434

+LAN_VDD18

Mount
for
8101E
Only

2007/5/4

3

12

R81
75_0402_1%

75_0402_1%

R80

LAN_MDI0­LAN_MDI0+

LAN_MDI1­LAN_MDI1+

12

12

R78
75_0402_1%

RJ45_MIDI3-

RJ45_MIDI3+

RJ45_MIDI2-

RJ45_MIDI2+

RJ45_MIDI1-

RJ45_MIDI1+

RJ45_MIDI0-

RJ45_MIDI0+

RJ45_GND

12
12

12
12

12

Security Classification

Issued Date

THIS SHEET OF EN GINEE RING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3V_LAN

U2

5

GND

6

NC

7

NC

8

VCC

+AVDD18

8111B@

2

1

C439

0.1U_0402_16V4Z

1

2

+LAN_CTRL18 +LAN_CTRL15

40mil 40mil

1

+

C444

8101E@

22U_A_4VM

2

2

C47

1

0.1U_0402_16V4Z

2

C460

0.1U_0402_16V4Z

1

+LAN_VDD15

1 2

L47 0_0603_5%

Mount for
8101E and
8111C.

2

C454

0.1U_0402_16V4Z

1

+3V_LAN

+3V_LAN +3V_LAN

Q42

1

1 2

L46 0_0603_5%

8101E@

A:Sync up with ISKAE to replace
L46/L47/L48 to Resistor.
B:L46, need to POP for 8101E and 8111C

Compal Secret Data

Deciphered Date

2

+3V_LAN

2

C455

0.1U_0402_16V4Z

1

2

1

2

C476

0.1U_0402_16V4Z

1

C468

0.1U_0402_16V4Z

2

C451

0.1U_0402_16V4Z

1

2

1

2

C478

0.1U_0402_16V4Z

1

C450

0.1U_0402_16V4Z

2

C472

0.1U_0402_16V4Z

1

2

C459

0.1U_0402_16V4Z

1

2

C436

0.1U_0402_16V4Z

1

R293 0_0603_5%

2

C466

0.1U_0402_16V4Z

1

2

C435

0.1U_0402_16V4Z

1

B:Chg. PN from SB194350080 to SB211880000.

Mount for 8111B Only

8111B@

2SB1188T100R_SC62-3

2 3

40mil 40mil

1

+

C452
22U_A_4VM

2

+LAN_VDD18

2

C440

0.1U_0402_16V4Z

1

C482

8101E@

22U_A_4VM

1

+

2

Q6

1

1 2

L48 0_0603_5%

8101E@

Mount for
8101E Only

C:Symbol is wr on g, need to update.

LAN_LINK#

C601

68P_0402_50V8J

C:Swap LED signals

LAN_ACTIVITY#

68P_0402_50V8J

C565

2

1

2

2008/5/4

R387

300_0402_5%

12

1

+3V_LAN

2

12

R345 300_0402_5%

+3V_LAN

RJ45_GND

1000P_1206_2KV7K

Title

Size Document Number Rev

Date: Sheet

RJ45_MIDI3-

RJ45_MIDI3+

RJ45_MIDI1-

RJ45_MIDI2­RJ45_MIDI2+
RJ45_MIDI1+

RJ45_MIDI0­RJ45_MIDI0+

RTL8111B(1G)/8101E(10/100)

JP28

10

Green LED-

9

Green LED+

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

12

Amber LED-

11

Amber LED+

C166

TYCO_1734819-3

1 2

1

C141

0.1U_0402_16V4Z

2

Compal Electronics, Inc.

IALAA-Minnesota10A LA3631P

Monday, May 14, 2007

1

+3V_LAN

2

C475

0.1U_0402_16V4Z

1

+LAN_VDD18

2

C477

0.1U_0402_16V4Z

1

+LAN_VDD15

2

C437

0.1U_0402_16V4Z

1

8111B@

2SB1188T100R_SC62-3

2 3

1

+

2

C464

8111B@

22U_A_4VM

1

2

B:Mount for 8101E and 8111B.

LAN Conn.

16

SHLD4

15

SHLD3

14

SHLD2

13

SHLD1

LANGND

1

C174

4.7U_0805_10V4Z

2

1

2

C481

0.1U_0402_16V4Z

1

R481

8111C@

0_0603_5%

B:Reserve for 8111C.

+LAN_VDD15

C473

8111B@

1000P_0402_25V8J

of

25 45

1A

5

HD Audio Codec

L28

1 2

FBMA-L11-160808-800LMT_0603

C380

4.7U_0805_10V4Z

D D

SYSON<28,30,32,35,40>
SUSP#<15,28,30,35,38>

L29

+VDDA

C C

+MIC2_VREFO

JP16

MIC@

NC2
NC1

2

2

1

1

4
3

ACES_85204-0200N

1 2

FBMA-L11-160808-800LMT_0603

1 2

R380 4.7K_0402_5%MIC@

C591

MONO_IN<27>

C371

10U_0805_10V4Z

12

220P_0402_50V8JMI C @

MIC1_L<27>
MIC1_R<27>

B:Chg. to link w/ SB600 bec'z chg. to KB926.

B B

NBA_PLUG<27>

MIC_SENSE<27>

B:Remove NBA_PLUG on SENSE B.

R455 39.2K_0402_1%
R456 20K_0402_1%

R464 20K_0402_1%MIC@

R219 0_0402_5%
R226 0_0402_5%@

0.1U_0402_16V4Z

1

1

C373

2

2

C337 100P_0402_25V8K

INT_MIC

C338 1U_0402_6.3V4ZMIC@
C346 1U_0402_6.3V4ZMIC@
C345 100P_0402_25V8K

MIC1_L MIC1_C_L

AZ_RST_HD#<17>
AZ_SYNC_HD<17>
AZ_SDOUT_HD<17>

SPK_SEL<17>

12

1 2

1 2

EAPD<30>

Sense Pin Impedance Codec Signals

SENSE A

A A

SENSE B

5

C376

0.1U_0402_16V4Z

12
12

1

C372

2

0.1U_0402_16V4Z

1 2
1 2
1 2
1 2

1U_0402_6.3V4Z

C714

1 2

C711

1 2

C350 100P_0402_25V8K

1 2
1 2

C351 1U_0402_6.3V4Z

1 2

C356 1U_0402_6.3V4Z

1 2

C355 100P_0402_25V8K

1 2

C707 100P_0402_25V8K

39.2K
20K
10K

5.1K

39.2K PORT-E (PIN 14, 15)
20K
10K PORT-G (PIN 43, 44)

5.1K

4

Adjustable Output

U31

4

VIN

2

SENSE or ADJ

DELAY
ERROR7CNOISE

8

SD

SI9182DH-AD-T1-E3_MSOP8

680P_0402_50V7K

100P_0402_25V8K

100P_0402_25V8K

1

C359

2

MIC2_L
MIC2_R

MIC1_C_RMIC1_R AZ_SDIN3_HD_R

SENSE_ANBA_PLUG
SENSE_B

DGND

B:Need to link SA091820030

5

VOUT

6
1
3

GND

+AVDD_HD

C366

38

U29

AVDD125AVDD2

14

NC

15

NC

16

MIC2_L

17

MIC2_R

23

LINE1_L

24

LINE1_R

18

CD_L

20

CD_R

19

CD_GND

21

MIC1_L

22

MIC1_R

12

PCBEEP

11

RESET#

10

SYNC

5

SDATA_OUT

2

GPIO0

3

GPIO3

13

SENSE A

34

SENSE B

47

EAPD

48

SPDIFO

4

DVSS1

7

DVSS2

ALC268-GR_LQFP48

C360

0.1U_0402_16V4Z

0.1U_0402_16V4Z

20mil40mil

1

DVDD

LINE_OUT_L
LINE_OUT_R

HP_OUT_L

HP_OUT_R

NC

DMIC_CLK

NC
NC

BIT_CLK

SDATA_IN

MONO_OUT

LINE1_VREFO

GPIO1
MIC1_VREFO_L
MIC1_VREFO_R

MIC2_VREFO

VREF

JDREF

NC

AVSS1
AVSS2

1 2

12

1

C327

2

9

DVDD_IO

35
36
39
41
45
46
43
44

6

8
37
29
31
28
32
30
27
40
33
26

42

AGND

+VDDA

R221

69.8K_0603_1%

R222
24K_0402_1%

0.1U_0402_16V4Z

AMP_LEFT
AMP_RIGHT

AZ_BITCLK_HD

10mil
10mil

10mil

DGND To AGND Bypass

1 2

DGND

Issued Date

R247 0_0603_5%

1 2

R207 0_0603_5%

1 2

R206 0_0603_5%

1 2

R233 0_0603_5%

1 2

R218 0_0603_5%

PORT-A (PIN 39, 41)
PORT-B (PIN 21, 22)
PORT-C (PIN 23, 24)
PORT-D (PIN 35, 36)

PORT-F (PIN 16, 17)

PORT-H (PIN 45, 46)

4

Security Classification

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+VDDA+5VALW +5VALW _ VDDA

4.75v

B:Set to "@".

10U_0805_10V4Z

1

1

C331

C332

2

2

1000P_0402_25V8J

@

+MIC1_VREFO_L
+MIC1_VREFO_R

+MIC2_VREFO

12

R224
20K_0402_1%

3

C353

4.7U_0805_10V4Z@

+3V_DVDD

680P_0402_50V7K

C328

680P_0402_50V7K

1

2

1 2
1 2

10U_0805_10V4Z

1

@

2

AZ_BITCLK_HD <17>

C368

1 2

R453 33_0402_5%

C720

C721 100P_0402_25V8K

1

C329

C330

2

100P_0402_25V8K

C367
1000P_0402_25V8J

0.1U_0402_16V4Z

L27

1 2

FBMA-L11-160808-800LMT_0603

AMP_LEFT <27>
AMP_RIGHT <27>

AMP_LEFT_HP <27>

AMP_RIGHT_HP <27>

AZ_SDIN3_HD <17>

+MIC1_VREFO_R +MIC1_VREFO_L

C369

SPK output to AMP

AZ_BITCLK_HD

+3VS

HP output to AMP

1 2

1

2

C370

0.1U_0402_16V4Z

AGND

2007/5/4 2008/5/4

Compal Secret Data

Deciphered Date

2

R454

C708

2

1

10_0402_5%@

10P_0402_50V8J@

Compal Electronics, Inc.

Title

HD CODEC ALC861D

Size Document Number Rev

IALAA-Minnesota10A LA3631P 1A

B

Monday, May 14, 2007

Date: Sheet

1

26 45

of

A

C326

W=40mil

R458

1 2

R459

1 2

+5VS

12

R205
100K_0402_5%

EC_EAPD#

1

2

+5VS

C357

C335

680P_0402_50V7K

AMP_RHPIN_L

24K_0402_5%

AMP_LHPIN_L

24K_0402_5%

1 2

C333 1U_0402_6.3V4Z

12

C719 2.2U_0603_6.3V4Z

12

C344 2.2U_0603_6.3V4Z

1 2

C336 0.1U_0402_16V4Z

HP_EN

1

C325

0.01U_0402_25V4Z@

2

R201

0_0402_5%@

EC_EAPD_R#<30>

4 4

B:1.For 2057 reserve
R198 mount, Q25 unmount
Add R484 for gain adj

2.Remove R198, R484 and Q25

AMP_RIGHT<26>
AMP_LEFT<26>

3 3

AMP_RIGHT_HP<26>
AMP_LEFT_HP<26>

1 2

C340 0.22U_0402_10V4Z

1 2

C348 0.22U_0402_10V4Z

+5VS

1 2

C709 2.2U_0603_6.3V4Z

1 2

C712 2.2U_0603_6.3V4Z

12

0.01U_0402_25V4Z@

R208 100K_0402_5%

1 2

R223 100K_0402_5%

1 2

AMP_RHPIN

AMP_LHPIN

Gain HP 0dB

SPK 10dB

R445

1 2

1 2

10K_0402_5%

R446

1 2

560_0402_5%

R443

1 2

560_0402_5%

@

10K_0402_5%

R447

2 2

EC Beep

BEEP#<30>

PCI Beep

SB_SPKR<17>

CardBus Beep

PCM_SPK<22>

1 1

A:Set PCMCIA@ on CardBus Beep circuit
B:Remove NSE_DPR circuit, bec'z chg. to KB926.

C703
1U_0402_6.3V4Z

PCMCIA@

2

C704

0.01U_0402_25V4Z

1

PCMCIA@

A

1 2

C702

1U_0402_6.3V4Z

C701

1U_0402_6.3V4Z

R448

1 2

560_0402_5%

PCMCIA@

1

2

AMPR
AMPL

AMP_EN#
HP_EN

EC_EAPD#
AMP_BEEP

AMP_CP+
AMP_CP-

AMP_BIAS

+3VS

B

+3VS
+5VS

2

C718

1

0.1U_0402_16V4Z

12

+VDDA

2

B

12

2 1

B

1 2

R227 0_0603_5%

1 2

R220 0_0603_5%@

C374

1U_0402_6.3V4Z

3

5
27
24

4

6
26
28
12

14
25

12

R451
20K_0402_5%

C

Q60

MMBT3904_SOT23-3

E

3 1

D36

CH751H-40PT_SOD323-2

1

2

10U_0805_10V4Z

U30

INR_A
INL_A

/AMP EN
HP_EN
INR_H

INL_H
SET/SD#
BEEP
CP+

CP­BIAS

APA2057ARI-TRL_TSSOP28

B:Co-Layout for
APA2056A and APA2057A

11

CVDD

C706

1 2

1U_0402_6.3V4Z

1 2

R452

2.4K_0402_5%

C

Volume Control

C:Chang PN to
DEB00000600

SW6

+AMP_HVDD

C365

10

20

19

PVDD

PVDD

HVDD

1

VDD

ROUT+

ROUT­LOUT+

LOUT-

HP_R

HP_L

CVSS
HVSS

GND
PGND
PGND
CGND

GND

2

1

1U_0402_6.3V4Z

22
21

8
9

17
18

15
16
2

23
7
13
29

SW_XRE094_3P

SPKR+

SPKR­SPKL+

SPKL­HP_R

HP_L

CVSS

1

C722

2

2.2U_0603_6.3V4Z

Microphone-In Jack

MONO_IN <26>

Headphone-Out Jack

HP_R

0_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/5/4 2008/5/4

C

+3VS

R463

5

10K_0402_5%

DIP

2

A

1

COM

3

B

DIP

4

12

12

R460
10K_0402_5%

R461 10K_0402_5%

R462 10K_0402_5%

1 2

1 2

+3VS

1

C715

2

0.01U_0402_25V4Z

Left Speaker Connector

SPKL+

SPKL-

A:sync up with ISKAE to replace L to R.

Right Speaker Connector

SPKR+

SPKR-

+MIC1_VREFO_L +MIC1_VREFO_R

MIC_SENSE<26>

MIC1_R<26>
MIC1_L<26>

12

R241

@

Compal Secret Data

10mil 10mil

4.7K_0402_5%

L31
KC FBM-L11-160808-121LMT 0603
L30
KC FBM-L11-160808-121LMT 0603

12

R240

@

0_0402_5%

Deciphered Date

R242

MIC1_R
MIC1_L

1 2
1 2

12

12

R243

4.7K_0402_5%

1 2

KC FBM-L11-160808-121LMT 0603

1 2

KC FBM-L11-160808-121LMT 0603

HPR_R
HPL_RHP_L

D

U32

1

C716

2

0.01U_0402_25V4Z

R245

1 2

R244

1 2

D

C717

1 2

0.1U_0402_16V4Z

1

5

P

NC

4

A2Y

G

74LVC1G14GW_SOT353-5

3

L18

1 2
1 2

C383

0_0603_5%

L19 0_0603_5%

L9

1 2
1 2

L10 0_0603_5%

L33
L32

1

C384

2

220P_0402_50V8J

20_0402_5%
20_0402_5%

C381

E

+3VS

12

R457
100K_0402_5%

1

0.1U_0402_16V4Z
C710

2

ENCODER_DIR <30>
ENCODER_PULSE <30>

D6 PACDN042Y3R_SOT23-3

2

1

3

1

C173

10P_0402_50V8J @

0_0603_5%

1

D3 PACDN042Y3R_SOT23-3

MIC1_R_1
MIC1_L_1

1

2

220P_0402_50V8J

HPR
HPL

1

C382

2

10P_0402_50V8J

Title

Size Document Number Rev

B

Date: Sheet

2

3
2

2

3

@

1

D17

NBA_PLUG<26>

1

2

3

10P_0402_50V8J

Compal Electronics, Inc.

AMP&Audio Jack/MDC

IALAA-Minnesota10A LA3631P 1A

Monday, May 14, 2007

U28

1

CD1#

2

D1

CD2#

3

CP1

4

SD1#

5

Q1

SD2#

6

Q1#

7

GND

74LCX74MTC_TSSOP14

C:Add in BOM by EMI

JP18

SPK_L1

1

1

2

2

ACES_85204-0200N

C175

10P_0402_50V8J@

JP6

1

1

2

2

ACES_85204-0200N

C:Add in BOM by EMI

JP39

5
4
3

6
2
1

FOX_JA6033L-5S1-TR

1

J2

1

JUMP_43X39

@

2

2

JP38

5
4
3

6
2
1

FOX_JA6033L-5S1-TR

E

SM05_SOT23

1

1

2

SPK_R1
SPK_R2

2

SPK_L2

D18

@

SM05_SOT23

VCC

CP2

Q2#

NC1
NC2

NC1
NC2

D2

Q2

14
13
12
11
10
09
08

3
4

3
4

1

J3

1

JUMP_43X39

@

2

2

27 45

+3VS

AGND

of

C713

1

2

8

7

8

7

AGND

0.1U_0402_16V4Z

MDC 1.5 Conn.

+3V_SB

1

C569

1000P_0402_25V8JMDC@

2

AZ_SDOUT_MD<17>
AZ_SYNC_MD<17>
AZ_RST_MD#<17>

AZ_SDIN0_MD<17>

+3VS +1.5VS+3V_SB

+3VALW_CARD +3VS_CARD +1.5VS_CARD

C312

NEW@

+3V_SB

1 2

R204 100K_0402_5%NEW@

1 2

R203 100K_0402_5%

share with USB OC PIN
need always pull high

+3VS

12

R183

NEW@

10K_0402_5%

13

2

G

D

Q22
2N7002_SOT23-3

S

NEW@

RCLKEN

12

R357 33_0402_5%MDC@

1

C315

NEW@

0.1U_0402_16V4Z

2

1

2

NEW@

10U_0805_10V4Z

CP_USB#

EXP_CPPE#

R185

NEW@

10K_0402_5%

CLKREQ#

C313

+3VS +3VS

12

C:Chg. PN to SB770020010.

1

2

AZ_SDIN0_MD_R

AZ_SDIN0_MD_R

1

C305

10U_0805_10V4Z@

2

1

0.1U_0402_16V4Z

2

5

U10

2

B

Vcc

1

A

G

NC7SZ32P5X_NL_SC70-5

3

NEW@

C563

Y

NEW@

4

1

0.1U_0402_16V4ZMDC@

1
3
5
7
9

11

C562

2

JP14

GND1
IAC_SDATA_OUT
GND2
IAC_SYNC
IAC_SDATA_IN
IAC_RESET#

Connector for MDC Rev1.5

1

C306

NEW@

0.1U_0402_16V4Z

2

Imax = 1.35A Imax = 0.75AImax = 0.275A

1

C321

2

1

C300

NEW@

0.1U_0402_16V4Z

2

C316

NEW@

10U_0805_10V4Z

4.7U_0805_10V4ZMDC@

RES0
RES1

3.3V
GND3
GND4

IAC_BITCLK

GND13GND14GND15GND16GND17GND

18

1

C307

10U_0805_10V4Z@

2

1

0.1U_0402_16V4Z

2

SYSON<26,30,32,35,40>

CLKREQ_NEW# <13>

+3V_SB

2
4
6
8
10
12

MDC@

ACES_88018-124G

1

C317

NEW@

0.1U_0402_16V4Z

2

1

C323

NEW@

10U_0805_10V4Z

2

+3VS

+3V_SB

+1.5VS

CP_USB#
EXP_CPPE#

NB_RST#

+5VS

Place Components closely to ODD Conn.

ODD CONN

1

C585
10U_0805_10V4Z

2

+3VS

IDE_SDIORDY

1 2

R382 4.7K_0402_5%

U12

3.3Vin1

3.3Vin2

3.3Vaux_in

1.5Vin1

1.5Vin2

CPUSB#
CPPE#
STBY#
SHDN#
SYSRST#

GND

11

AZ_BITCLK_MD <17>

3.3Vout1

3.3Vout2

Aux_out

1.5Vout1

1.5Vout2

OC#

RCLKEN

PERST#

NC11NC210NC312NC413NC5

NEW@

24

TPS2231PWPR_PWP24

C731

@

0.1U_0402_16V4Z

+5VS

60mils

7
8

20

16
17

23
22

9

2007/5/4 2008/5/4

40mil
40mil

RCLKEN
PERST#

+3VS_CARD

+3VALW_CARD

+1.5VS_CARD

Compal Secret Data

C571

R358

12

1 2

10_0402_5%@

NEW@

C322

10P_0402_50V8J@

B:Set to "@"

1

C318

10U_0805_10V4Z@

2

1

0.1U_0402_16V4Z

2

5
6

21

18
19

14
15

4
3
2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

IDE_SDD[0..15]<17>

1

2

1

C732

@

2

0.1U_0402_16V4Z

IDE_SDIOW#<17>

IDE_SDIORDY<17>

INT_IRQ15<17>
IDE_SDA1<17>
IDE_SDA0<17> IDE_SDA2 <17>

IDE_SDCS1#<17> IDE_SDCS3# <17>

12

R374 100K_0402_5%

A:This symbol is for IALAA
only, to add these two
pins for Boss Hole.

R348 470_0402_5%

@

0.1U_0402_16V4Z

12

C734

C:Swap PCIE Tx/Rx signals.

Deciphered Date

+5VS

SEC_CSEL

SIDERST#<17>
NB_RST#<11,15,17,24,25,30,34>

SIDE_RST#
IDE_SDD7
IDE_SDD6
IDE_SDD5
IDE_SDD4
IDE_SDD3
IDE_SDD2
IDE_SDD1
IDE_SDD0

IDE_SDIORDY

1

OCTEK_CDR-50JL1G

2

PCIE_MRX_C_NEWTX_N1<11>
PCIE_MRX_C_NEWTX_P1<11>

PCIE_MTX_C_NEWRX_N1<11>
PCIE_MTX_C_NEWRX_P1<11>

1

C586
10U_0805_10V4Z

2

NB_RST#

IDE_SDD[0..15]

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

USBP9-<17>
USBP9+<17>

SMB_CK_CLK0<8,9,13,17,24>
SMB_CK_DAT0<8,9,13,17,24>

+1.5VS_CARD

EC_SWI#<16,30>

+3VALW_CARD

+3VS_CARD

EXP_CPPE#<17>
CLK_NEW#<13>
CLK_NEW<13>SUSP#<15,26,30,35,38>

1

C579

2

0.1U_0402_16V4Z

+3VS

9

A

10

B

JP29

2

1

2

4

3

4

6

5

6

8

7

8

10

9

10

12

11

12

14

13

14

16

15

16

18

17

18

20

19

20

22

21

22

24

23

24

26

25

26

28

27

28

30

29

30

32

31

32

34

33

34

36

35

36

38

37

38

40

39

40

42

41

42

44

43

44

46

45

46

48

47

48

50

49

50

515152

52

0.1U_0402_16V4Z

@

1

C578

0.1U_0402_16V4Z

2

14

U20C

P

SIDE_RST#

8

O

G

SN74LVC08APW_TSSOP14

7

IDE_SDD8
IDE_SDD9
IDE_SDD10
IDE_SDD11
IDE_SDD12
IDE_SDD13
IDE_SDD14
IDE_SDD15

IDE_PDIAG#

W=80mils

C584 0.1U_0402_16V4Z

1

C735

2

1

C736

@

2

0.1U_0402_16V4Z

1

C580

2

0.1U_0402_16V4Z

C733

@

0.1U_0402_16V4Z

IDE_SDDREQ <17>

IDE_SDIOR# <17>
IDE_SDDACK# <17>

1 2

+5VS

12

C:Reserve
C730~C736 by EMI.

1

C730

@

2

R363
100K_0402_5%

0.1U_0402_16V4Z

B:relink DC030006O00.

JP20

1

GND

2

USB_D-

3

CP_USB#

PERST#

CLKREQ#
EXP_CPPE#

Compal Electronics, Inc.

Title

TPM/ ODD CONNECTORS

Size Document Number Rev

IALAA-Minnesota10A LA3631P 1A

B

Monday, May 14, 2007

Date: Sheet

USB_D+

4

CPUSB#

5

RSV

6

RSV

7

SMB_CLK

8

SMB_DATA

9

+1.5V

10

+1.5V

11

WAKE#

12

+3.3VAUX

13

PERST#

14

+3.3V

15

+3.3V

16

CLKREQ#

17

CPPE#

18

REFCLK-

19

REFCLK+

20

GND

21

PERn0

22

PERp0

23

GND

24

PETn0

25

PETp0

26

GND

27

GND

28

GND

FOX_1CH411ASC-MN

NEW@

GND
GND
GND
GND

29
30
31
32

of

28 45

1

2

+5VS

Int. Camera Conn

Check 5VS or 3VS

+5VS

1
2
3
4
5
6
7

CIR_IN<30>

1 2

R484 0_0603_5%CAMERA@

1 2

R343 0_0603_5%@

USBP7­USBP7+

+5VS

USBP7+

+5VALW

12

+5VALW_CIR

+5VALW

JP11

1
2
3
4

5
GND1
GND2

ACES_88266-05001

CAMERA@

CIR

D32

4

IO1

VIN

3

GND

IO2

PRTR5V0U2X_SOT143-4@

R230

CIR@

100_0805_5%

C375

CIR@

4.7U_0805_10V4Z

+CAM_VDD

USBP7- <17>

USBP7+ <17>

2
1

3
2
1
4

W=20mils

C566

0.1U_0402_16V4Z

CAMERA@

USBP7-

U33

GND
VCC
Vout
GND

CIR@

IRM-V538/TR1_3P

Fingerprint Conn

1

2

USBP5-<17>

USBP5+<17>

C598

FP@

0.1U_0402_16V4Z

+3VS

USBP5-

USB CONN. 1

150U_Y_6.3VM

+5VALW

150U_Y_6.3VM@

+5VALW

USBP1-_R

+USB_VCCC

C681

D7

4

VIN

3

IO2

PRTR5V0U2X_SOT143-4@

+USB_VCCC

C653

D9

4

VIN

3

IO2

PRTR5V0U2X_SOT143-4@

1

+

2

0.1U_0402_16V4Z

IO1

GND

1

+

2

IO1

GND

+3VS

1

2

D34

4
3

PRTR5V0U2X_SOT143-4@

2

IO1

VIN

1

GND

IO2

JP17

5
4
3
2
1

FP@

ACES_85201-0505

USBP5+

USBP0-<17>

USBP0+<17>

B:Set to "@"

USB_EN#<30>

USBP1-<17>

USBP1+<17>

+5VALW

C231

4.7U_0805_10V4Z@

C:Remove R114 and R117, leave
Chock for AMD plateform

USB_EN#

C:Remove R135 and R141, leave
Chock for AMD plateform

WCM2012F2S-900T04_0805

4

4

1

1

L21

U7

1

GND

2
3
4

OUT

IN

OUT
OUT

IN

FLG

EN#

G528P1UF_SO8

L24

4

4

1

1

WCM2012F2S-900T04_0805

3

2

8
7
6
5

3

2

3

2

+USB_VCCC

1

2

3

2

USBP0-_R
USBP0+_R

USBP0-_R

C672

0.1U_0402_16V4Z

USBP1-_R
USBP1+_R

W=60mils

1

C643

2

USBP0+_R

2
1

W=60mils

1

C677

2

0.1U_0402_16V4Z

USBP1+_R

2
1

1

C644
1000P_0402_25V8J

2

JP30

1

VCC

2

D-

3

D+

4

GND

P-TWO_CU304G-A0G1G-P

USB CONN.2

1

C674
1000P_0402_25V8J

2

JP32

1

VCC

2

D-

3

D+

4

GND

P-TWO_CU304G-A0G1G-P

5

GND

6

GND

7

GND

8

GND

5

GND

6

GND

7

GND

8

GND

BlueTooth Interface

R347

1M_0402_5%

BT@

BT_PWR<30>

2

G

R346

1 2

1 2

100K_0402_5%BT@

2

BT@

C558 1000P_0402_25V8J

13

D

Q51

BT@

2N7002_SOT23-3

S

1

C:Chg. PN to SB770020010.

Pull high at SB600 side

Module ID

Indication for polarity of reset
Reset input High Active --> Low ,
Reset input Low Active --> Open

B:Add PD 4.7K bec'z chg. to KB926.

USB Small Board

+3VS+5VS

C557

BT@

0.1U_0402_16V4Z

S

G

2

Q52

D

AO3413_SOT23BT@

1 3

+BT_VCC

USBP4+<17>

USBP4-<17>

WLAN_BT_CLK<24>

WLAN_BT_DATA<24>

+BT_VCC

4.7K_0402_5%

BT_DET#<17>

BT_RST#<30>

R477

BT_DETACH

1 2

10U_0805_10V4Z

(MAX=200mA)

C570

BT@

1

C567

BT@

2

0.1U_0402_16V4Z

JP12

12

GND2

11

GND1

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

ACES_87213-1000G

BT@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

@

4.7U_0805_10V4Z

B:Set to "@"

2007/5/4 2008/5/4

+5VALW

C705

+5VALW

USBP6-

+5VALW

USBP2-

Compal Secret Data

USB_EN#

D12

4

IO1

VIN

3

GND

IO2

PRTR5V0U2X_SOT143-4@

D11

4

IO1

VIN

3

GND

IO2

PRTR5V0U2X_SOT143-4@

Deciphered Date

2
1

2
1

U27

1

GND

2

IN

3

IN

4

EN#

G528P1UF_SO8

USBP6+

USBP2+

+USB_VCCA

8

OUT

7

OUT

6

OUT

5

FLG

USBP6+<17>

USBP6-<17>

USBP2+<17>

USBP2-<17>

MP:Swap USB2+/- and USB8+/- for
CAMERA problem.

Compal Electronics, Inc.

Title

USB Conn.

Size Document Number Rev

IALAA-Minnesota10A LA3631P 1A

B

Date: Sheet

USBP6+
USBP6-

USBP2+
USBP2-

Monday, May 14, 2007

+USB_VCCA

JP22

1
2
3
4
5
6
7
8
9
10
11
12

ACES_85201-1205

of

29 45

5

+3VALW

1 2

C575 0.1U_0402_16V4Z

1 2

L55 0_0603_5%

D D

12

R339

@

10_0402_5%

1

@

C C

+5VALW

B B

A A

C553

22P_0402_50V8J

+3VALW

C541

15P_0402_50V8J

32.768KHZ_12.5P_1TJS125BJ4A421P

MP:ENE's recommend, change C541 and C542 from 10P to 27P.

2

R340
47K_0402_5%

12

C561 0.1U_0402_16V4Z

RP17

1 8
2 7
3 6
4 5

4.7K_0804_8P4R_5%

R315

1 2

20M_0603_5%@

1

1

2

2

CLK_PCI_EC

12

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_DA2
EC_SMB_CK2

CRY2CRY1

4

Y5

IN

OUT

NC3NC

ECRST#

1

C542

2

ECAGND

KSI[0..7]<32,33>

KSO[0..17]<32,33>

15P_0402_50V8J

0.1U_0402_16V4Z

1

C582

2

0.1U_0402_16V4Z

LPC_FRAME#<16,34>

CLK_PCI_EC<16>

NB_RST#<11,15,17,24,25,28,34>

EC_PLAYBTN#<32,33>
EC_STOPBTN#<32,33>

EC_FRDBTN#<32,33>
EC_REVBTN#<32,33>

KSI[0..7]
KSO[0..17]

EC_SMB_CK1<31,37>
EC_SMB_DA1<31,37>
EC_SMB_CK2<6,15>
EC_SMB_DA2<6,15>

PM_SLP_S3#<16>

PM_SLP_S5#<16>
EC_SMI#<17>
LID_SW#<32>
SUSP#<15,26,28,35,38>
PBTN_OUT#<16>

EC_PME#<25>
PCIE_WAKE#<24>
FAN_SPEED1<34>

VLDT_EN<35>

E51_TXD<34>

E51_RXD<34>

ON/OFFBTN#<32>

PWR_SUSP_LED<32>

NUM_LED#<33>

C572

1

2

GATEA20<16>
EC_KBRST#<16>
SERIRQ<16,22,34>

LPC_AD3<16,34>
LPC_AD2<16,34>
LPC_AD1<16,34>
LPC_AD0<16,34>

EC_SCI#<17>
STB_WLAN<35>

0.1U_0402_16V4Z

4

0.1U_0402_16V4Z

1

C540

2

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

CRY1
CRY2

1

C546

2

CLK_PCI_EC
ECRST#

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6

KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9

KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

2

C600

1000P_0402_25V8J

1

1
2
3
4
5
7
8

10
12

13
37
20
38

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

77
78
79
80

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

122
123

2

1

U24

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1

LPC & MISC

LAD0
PCICLK

PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25
KSO6/GPIO26
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

XCLK1
XCLK0

+3VALW

C551
1000P_0402_25V8J

Int. K/B
Matrix

SM Bus

9

22

33

96

111

125

VCC

VCC

VCC

VCC

VCC

VCC

INVT_PWM/PWM1/GPIO0F

ACOFF/FANPWM2/GPIO13

PWM Output

AD Input

DA Output

PS2 Interface

TP_DATA/PSDAT3/GPIO4F

SPI Device Interface

SPI Flash ROM

BATT_CHGI_LED#/GPIO52

GPIO

BATT_LOW_LED#/GPIO54

GPO

GPIO

GPI

GND

GND

GND

GND

GND

11

24

35

94

113

3

B:Chg. U24 from KB910 to KB926.

67

AVCC

BEEP#/PWM2/GPIO10

FANPWM1/GPIO12

BATT_TEMP/AD0/GPIO38

BATT_OVP/AD1/GPIO39

ADP_I/AD2/GPIO3A

AD3/GPIO3B
AD4/GPIO42

SELIO2#/AD5/GPIO43

DAC_BRIG/DA0/GPIO3C

EN_DFAN1/DA1/GPIO3D

IREF/DA2/GPIO3E

DA3/GPIO3F

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C

PSDAT2/GPIO4D

TP_CLK/PSCLK3/GPIO4E

SDICS#/GPXOA00
SDICLK/GPXOA01

SDIDO/GPXOA02

SDIDI/GPXID0

SPIDO/WR#

SPICLK/GPIO58

CIR_RX/GPIO40

CIR_RLC_TX/GPIO41

FSTCHG/SELIO#/GPIO50

CAPS_LED#/GPIO53
SUSP_LED#/GPIO55

SYSON/GPIO56

VR_ON/XCLK32K/GPIO57

AC_IN/GPIO59

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04

EC_ON/GPXO05

EC_SWI#/GPXO06

ICH_PWROK/GPXO06

BKOFF#/GPXO08

WL_OFF#/GPXO09

PM_SLP_S4#/GPXID1

ENBKL/GPXID2

AGND

KB926QFA1_LQFP128_14X14

69

ECAGND

SPIDI/RD#

SPICS#

GPXO10
GPXO11

GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

V18R

21
23
26
27

63
64
65
66
75
76

68
70
71
72

83
84
85
86
87
88

97
98
99
109

119
120
126
128

73
74
89
90
91
92
93
95
121
127

100
101
102
103
104
105
106
107
108

110
112
114
115
116
117
118

124

BATT_TEMPA
ADP_IR

MODE#
BTN_ID

TP_CLK
TP_DATA

STRAP

ACIN_R

ENBKL

IE_BTN#

INVT_PWM <15>
BEEP# <27>

ENCODER_DIR <27>
ACOFF <38>

BATT_TEMPA <37>

BATT_OVP <38>

MODE# <32>

KILL_SW# <24>

BTN_ID <32>

DAC_BRIG <15>
EN_DFAN1 <34>
IREF <38>

EC_EAPD_R# <27>
USB_EN# <29>
WL_BT_LED# <32>

SATTLATE_LED# <32>

TP_CLK <33>

TP_DATA <33>

STB_LAN <35>

STB_SB <35>

VGATE <42>

EC_SI_SPI_SO <31>

EC_SO_SPI_SI <31>

EC_SPICLK <31>

SPI_CS# <31>

CIR_IN <29>
ENCODER_PULSE <27>

FSTCHG <38>
BATT_FULL_LED# <32>
CAPS_LED# <33>
BATT_CHG_LOW_LED# <32>
POWER_LED# <32>
SYSON <26,28,32,35,40>
VR_ON <42>

EC_RSMRST# <17>

EC_LID_OUT# <17>
EC_ON <32>
EC_SWI# <16,28>
SB_PWRGD <6,16>

BKOFF# <15>

WL_OFF# <24>

ALI/MH# <37,38>

CURSOR_LED <33>

NB_PWRGD <11>
EAPD <26>

EC_THERM# <17>

BT_PWR <29>

BT_RST# <29>

IE_BTN# <32>

2

ADP_IR

MODE#

Analog BTN ID definition,
Please see page 3.

BTN_ID

R383 100K_0402_5%

TP_CLK
TP_DATA

STRAP

ACIN<32,36>

ENBKL

D33

CH751H-40PT_SOD323-2

IE_BTN#

1

ECAGNDBATT_TEMPA

12

C574 0.01U_0402_25V4Z

R364
100K_0402_5%

1 2
1 2

C587 0.22U_0402_10V4Z

+3VALW

12

R470100K_0402_5%

+3VALW

12

+5VS

1 2

R3384.7K_0402_5%

1 2

R3374.7K_0402_5%

R471 4.7K_0402_5%

21

12

+3VALW

12

R341 100K_0402_5%

ACIN_R

+3VALW

12

R330100K_0402_5%

12

R11730_0402_5% VGA@

12

R11740_0402_5% UMA@

12

R11752K_0402_5%@

ADP_I <38>

VGA_ENBKL <15>

UMA_ENBKL <11>

B:Set R1175 with "@".

MP:ENE's recommend, change back C541 and C542 from 27P to 15P.

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/5/4 2008/5/4

3

Compal Secret Data

Deciphered Date

Title

ENE-KB910

Size Document Number Rev

IALAA-Minnesota10A LA3631P 1A

Custom

Monday, May 14, 2007

2

Date: Sheet

1

30 45

of

+3VALW

U22

A0
A1
A2

+5VALW

12

R318
100K_0402_5%

1
2
3
4

R325

1 2

100K_0402_5%

INT_SPI_CS#

R303

1 2

22_0402_5%

U21

4

+5VALW

C5380.1U_0402_16V4Z

1 2

8

VCC

7

WP

EC_SMB_CK1<30,37>

EC_SMB_DA1<30,37>

6

SCL

5

SDA

AT24C16AN-10SU-2-7_SO8

GND

5

B

Vcc

Y

A

G

NC7SZ32P5X_NL_SC70-5

3

C527

12

0.1U_0402_16V4Z

INT_FLASH_EN#

2

SPI_CS#

1

R305

100K_0402_5%

1 2

B:Chg. to SPI ROM.

SPI_CS# INT_SP I_CS#

EC_SPICLK<30>

EC_SO_SPI_SI<30>

SB_INT_FLASH_SEL<17>

C507

0.1U_0402_16V4Z

R472 0_0402_5% @

EC_SPICLK

R473 0_0402_5%
R474 0_0402_5%

SPI_CS#<30>

SPI Flash (8Mb*1)

+3VALW

20mils

1

2

1 2
1 2

SPI_CLK_R

EC_SO_SPI_SI_R EC_SI_SPI_SO_R

12

EC_SI_SPI_SO_R

U19

8

VCC

3
7
1
6
5

SST25LF080A_SO8-200mil

VSS
W
HOLD
S
C
D

JP50

112
334
556
778

E&T_2941-G08N-00E~D@

C:Chg. PN to LTC00000200

Q

2
4
6
8

4

2

INT_FLASH_EN#
SPI_CLK_R
EC_SO_SPI_SI_R

12

R475 0_0402_5%

+3VALW

EC_SI_SPI_SO <30>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFO RMATI ON. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/5/4 2008/5/4

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

BIOS& I/O PORT

Size Document Number Rev

IALAA-Minnesota10A LA3631P 1A

B

Monday, May 14, 2007

Date: Sheet

of

31 45

5

SW/LED Connector

D1

MODEBTN#

D D

AC IN LED

C C

+5VALW

BATT CHARGE/FULL LED

+5VALW

2

1

3

DAN202UT106_SC70-3

1 2

R252 120_0402_5%

1 2

R231 300_0402_5%

1 2

R232 120_0402_5%

51_ON#

KSO0<30,33>

EC_PLAYBTN#<30,33>
EC_STOPBTN#<30,33>
EC_FRDBTN#<30,33>
EC_REVBTN#<30,33>

BTN_ID<30>

B:Chg. to link SC5191NB000

D20

2 1

HT-191NB_BLUE_0603

D22

2 1

HT-191UD_AMBER_0603

D27

2 1

HT-191NB_BLUE_0603

B:Chg. to link SC5191NB000

WL&BT LED

D38

+5VS

1 2

R250 300_0402_5%WLAN@

3G LED

B B

+5VS

1 2

R249 120_0402_5%3G@

HDD LED

+5VS

A A

1 2

R253
120_0402_5%

R476 100K_0402_5%

2 1

B:Chg. to link SC5191NB000

D37

2 1

B:Chg. HDD LED control circuit
bec'z chg. to KB926.

D23

2 1

HT-191NB_BLUE_0603

12

D2

IEBTN#

1

DAN202UT106_SC70-3

ON/OFFBTN_R#
IEBTN#

MODEBTN#

KSI1
KSI2
KSI3
KSI5

BATT_CHG_LOW_LED#

BATT_FULL_LED#

VF=1.9V

HT-191UD_AMBER_0603WLAN@

VF=2.8V

HT-191NB_BLUE_06033G@

Q130
2N7002_SOT23-3

D

1 3

G

2

2

51_ON#

3

JP2

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

GND

12

GND

ACES_85201-1005N

2

Q37

1 3

D

2N7002_SOT23-3

C:Chg. PN to SB770020010.

S

D

S

1 3

Q131
2N7002_SOT23-3

G

2

4

IE_BTN# <30>MODE# <30>

1
2

ACIN <30,36>

G

S

C:Chg. PN to SB770020010.

BATT_CHG_LOW_LED# <30>

BATT_FULL_LED# <30>

WL_BT_LED# <30>

3G_LED# <24>

HDD_LED# <17>

Power Button

For debug only

BTN TOP

SW4

3
4

TEST@

5

6

SMT1-05-A_4P

B:Remove SW1 from DVT for
interfere issue.

SW1

1
2

6

+5VALW

47K

1 3

+5VALW

47K

1 3

+5VS

47K

1 3

3

ON/OFFBTN_R#

3
4

SMT1-05-A_4P@

5

EC_ON<30>

10K_0402_5%

1

R251

SUSPEND LED

2

1 3

D

G

Q30

10K

2

DTA114YKAT146_SOT23-3
R234 300_0402_5%

1 2

POWER LED

2

1 3

D

G

Q31

10K

2

DTA114YKAT146_SOT23-3

1 2

R235 120_0402_5%

B:Chg. to link SC5191NB000

Satellite LED

Q33

SATEL@

DTA114YKAT146_SOT23-3

10K

2

B:Chg. from 120 to 100 to
make LED more brightness.

1 2

R238 100_0402_5%SATEL@

1 2

R239 100_0402_5%SATEL@

+3VALW

R228

D13

2
3

DAN202UT106_SC70-3

13

D

2

G

S

100K_0402_5%

1 2

51_ON#

Q38
2N7002_SOT23-3

C:Chg. PN to SB770020010.

1 2

SYSON

Q27
2N7002_SOT23-3

S

C:Chg. PN to SB770020010.

2 1

SYSON

Q26
2N7002_SOT23-3

S

2 1

D15

2 1

12-21-BHC-ZL1M2RY-2C_BLUESATEL@
D16

2 1

SYSON <26,28,30,35,40>

PWR_SUSP_LED <30>

D21

HT-191UD_AMBER_0603

POWER_LED# <30>

C:Chg. PN to SB770020010.

D26

HT-191NB_BLUE_0603

SATTLATE_LED# <30>

VF=2.8V

12-21-BHC-ZL1M2RY-2C_BLUESATEL@

1

C358

0.01U_0402_25V4Z

2

2

Lid SW

ON/OFFBTN# <30>
51_ON# <36>

12

D19
RLZ20A_LL34

C377

B:Chg. to SOT-23 type.

+3VALW

U14
APX9132ATI-TRL_SOT23-3

VDD2VOUT

1

2

0.1U_0402_16V4Z

1

GND

1

+3VALW

12

R236
47K_0402_5%

1

2

C378

10P_0402_50V8J

LID_SW# <30>

3

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/5/4 2008/5/4

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Comm. SW/ Sub Conn./LEDS

Size Document Number Rev

IALAA-Minnesota10A LA3631P 1A

Custom

Monday, May 14, 2007

2

Date: Sheet

1

32 45

of

5

4

3

2

1

TP Conn.

JP15

14

G2

13

G1

D D

TP_DATA<30>

TP_CLK<30>

+5VS

TP_DATA
TP_CLK

SW_R

SW_L

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

ELCO_086212012340800

SW_R
SW_L
TP_DATA
TP_CLK

1 2

C573 33P_0402_50V8J@

1 2

C564 33P_0402_50V8J@

1 2

C583 33P_0402_50V8J@

1 2

C581 33P_0402_50V8J@

TP Button

1
2

SW2

SMT1-05-A_4P

5

6

3
4

SW_L SW _R

C C

1
2

SW3

SMT1-05-A_4P

5

6

3
4

KEYBOARD CONN.

JP19

34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1

ACES_88170-3400

CAPS_LED#
CURSOR_LED
NUM_LED#

KSO2
KSO1
KSO0
KSO4
KSO3
KSO5
KSO14
KSO6
KSO7
KSO13
KSO8
KSO9
KSO10
KSO11
KSO12
KSO15
KSI7
KSI2
KSI3
KSI4
KSI0
KSI5
KSI6
KSI1

R391 300_0402_5%

1 2

R389 300_0402_5%

1 2

R388 300_0402_5%

12

KSI[0..7]
KSO[0..15]

+3VS

+3VS

+3VS
CAPS_LED# <30>
CURSOR_LED <30>
NUM_LED# <30>

KSI[0..7] <30,32>
KSO[0..15] <30,32>

KSO2
KSO1
KSO0
KSO4
KSO3
KSO5

KSO14

KSO6
KSO7

KSO13

KSO8

KSO9
KSO10
KSO11
KSO12
KSO15

KSI7
KSI2
KSI3
KSI4
KSI0
KSI5
KSI6
KSI1

CAPS_LED#

CURSOR_LED

NUM_LED#

For EMI Request

1 2

C630 100P_0402_25V8K

1 2

C616 100P_0402_25V8K

1 2

C629 100P_0402_25V8K

1 2

C615 100P_0402_25V8K

1 2

C628 100P_0402_25V8K

1 2

C614 100P_0402_25V8K

1 2

C627 100P_0402_25V8K

1 2

C613 100P_0402_25V8K

1 2

C626 100P_0402_25V8K

1 2

C612 100P_0402_25V8K

1 2

C625 100P_0402_25V8K

1 2

C611 100P_0402_25V8K

1 2

C624 100P_0402_25V8K

1 2

C610 100P_0402_25V8K

1 2

C623 100P_0402_25V8K

1 2

C609 100P_0402_25V8K

1 2

C622 100P_0402_25V8K

1 2

C608 100P_0402_25V8K

1 2

C621 100P_0402_25V8K

1 2

C607 100P_0402_25V8K

1 2

C620 100P_0402_25V8K

1 2

C606 100P_0402_25V8K

1 2

C619 100P_0402_25V8K

1 2

C605 100P_0402_25V8K

1 2

C604 100P_0402_25V8K

1 2

C618 100P_0402_25V8K

1 2

C617 100P_0402_25V8K

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/5/4 2008/5/4

3

Compal Secret Data

Deciphered Date

Title

KB/Touch Pad& hibernation

Size Document Number Rev

IALAA-Minnesota10A LA3631P 1A

Custom

Monday, May 14, 2007

2

Date: Sheet

1

33 45

of

A

B

C

D

E

FD2

@

1

1

@

1

@

R80x100

@

R80x100

@

H32

1

H3

1

H14

1

@

CF8

CF10

M2

1

M7

1

FD1

@

1

CF9

1

@

CF7

1

@

R80x100

@

R80x100

@

H_C252D118

@

H_C252D118

@

H_C236D122

@

FD6

H30

H2

H11

1

1

@

1

@

M3

1

M8

1

1

1

1

FD4

@

@

1

CF4

1

@

CF6

1

@

R80x100

@

R80x100

@

H_C252D118

@

H_C252D118

@

H_C236D122

@

FD5

CF3

CF2

H27

H1

H9

1

M4

1

M9

1

1

1

1

M5

R80x100

@

1

M10

R80x100

@

1

H10

H_C252D118

@

1

H31

H_C252D118

@

1

M11

R80x100

@

1

H24

H_C252D118

@

1

FAN Conn

VS

1 1

2 2

EN_DFAN1<30>

R309 10K_0402_5%
R281 10K_0402_5%

SERIRQ<16,22,30>

12

E51_RXD

SERIRQ

ENFAN

LPC_AD3<16,30>

LPC_AD1<16,30>

LPC_FRAME#<16,30>

FBFAN

12

8

PU5B

5

P

+

0

6

-

G

4

1 2

R314 5.1K_0402_5%

B:FAN circuit to PWM like
SWAP PU5.5, PU5.6
R281 change to 10K
Q46 change to IRLML5103PBF
R314 conn to +FAN1

R449

0_0402_5%@

1 2

1 2

R450
0_0402_5%

7

LM358DT_SO8P@

+3VALW

LPC_AD3

LPC_AD1

LPC_FRAME#

R313

100_0402_5%

10K_0402_5%@

7

8

9

10

12

R308

1 2

H34

DEBUG_PAD@

C2:Chg. to
AO3409 for
Fan High
speed problem

FAN1_ON

1

+

C508

2

For EC

JP13

1

1
2

3 3

3
4

ACES_85205-0400@

E51_RXD

2

E51_TXD

3
4

+5VALW

+5VS

S

G

2

AO3409_SOT23

D

Q46

1 3

12

D31
BAS16_SOT23-3

22U_B_10VM

+3VS

56

4

3

2

1

C:Chg. PN to
SC1BAS16000

1 2

R312 10K_0402_5%

FAN_SPEED1<30>

R428

0_0402_5%@

1 2

1 2

R426
0_0402_5%

NB_RST#

LPC_AD2

LPC_AD0

R424

1 2
2

C692
22P_0402_50V8J

1

22_0402_5%

12

+FAN1

C532

1000P_0402_25V8J@

E51_TXD

LPC_DRQ1#

NB_RST# <11,15,17,24,25,28,30>

LPC_AD2 <16,30>

LPC_AD0 <16,30>

CLK_PCI_SIO <16>

LPC Debug card

D30
1SS355_SOD323-2

2

1

2

C531
1000P_0402_25V8J@

1

E51_TXD <30>

LPC_DRQ1# <16>E51_RXD<30>

H6

H_C276D157

@

1

H23

H_C276D158

@

1

H4

H_C118D118N

@

1

Need to link SC1SS355010

JP8

5

GND

4

GND

3

3

2

2

1

1

ACES_85205-03001

H7

H_C236D146

@

1

H22

H_C276D158

@

1

H33

H_O118X197D118X197N

@

1

H5

H_O197X55D158X16

@

1

FD3

@

1

CF1

1

@

CF5

1

@

EMI Shielding Clip PADs

M1

R80x100

@

1

M6

R80x100

@

1

Screw Hole

H_C252D118

@

H_C252D118

@

H_C236D122

@

H13

LPC Debug Port

+3VS

JP10

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

4 4

12

12

13

13

R85 0_0402_5%@

14

14

15

15

16

16

17

17

18

18

19

19

20

20

ACES_85201-2005@

1 2

A

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#

LPC_DRQ1#

NB_RST#
CLK_PCI_SIO

SERIRQ

CLK_14M_SIO <13>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

H_S315D118

@

1

H29

H_O173X59D134X20

@

1

H25

H_O158X59DO118X20

@

1

2007/5/4 2008/5/4

Compal Secret Data

H26

H_S315D118

@

1

H28

H_O173X59D134X20

@

H19

H_O158X59DO118X20

@

Deciphered Date

1

1

H12

H_S315D118

@

1

H37

H_O173X59D134X20

@

1

D

H18

H_C236D43

@

1

H8

H_C236B73D43

@

1

H21

H_C276BC185D165

@

1

Title

Size Document Number Rev

Custom

Date: Sheet

H17

H_C236B73D43

@

1

H20

H_C276BC185D165

@

1

Compal Electronics, Inc.

FAN & MDC

IALAA-Minnesota10A LA3631P 1A

Monday, May 14, 2007

H35

H_C236B73D43

@

1

H15

H_C276BC185D165

@

1

H_C236B73D43

@

H_C276BC185D165

@

E

H36

1

H16

1

34 45

of

A

+1.2VALW +1.2V_HT

Q14

IRF8113PBF_SO8

8
7

5

1 1

1

C184

2

4.7U_0805_10V4Z

4

1
2
36

1

2

0.1U_0402_25V4Z

C181

C180

+3VALW TO +3VS

+3VALW +3VS

Q18

8

S

D

7

S

D

6

S

D

5

G

D

SI4800BDY_SO8

1

C262

2

2 2

4.7U_0805_10V4Z

1

C272

R306

STAR@

2

R164

STAR@

47K_0402_5%

1

C525

STAR@

2

10U_0805_10V4Z

STAR@

47K_0402_5%

STB_WLAN#

STB_SB#

10U_0805_10V4Z

STAR@

+VSB

3 3

C518

STAR@

10U_0805_10V4Z

+VSB

4 4

1

C264

1
2

2

3
4

1U_0402_6.3V4Z

1

C247

2

0.01U_0402_25V7K

+3VALW TO +3V_SB

+3VALW

1

C271

2

10U_0805_10V4Z

12

2

G

+3VALW TO +3V_WLAN

+3VALW

Q47

6
2

1

1

STAR@

SI3456BDV-T1-E3_TSOP6

2

12

13

2

G

A

C:Chg.Q14,Q41 part to reduce low Rdson part.

1

2

1U_0402_6.3V4Z

13

D

S

330K_0402_5%

13

D

Q16

2N7002_SOT23-3

S

Q133

D

6
2

1

STAR@

SI3456BDV-T1-E3_TSOP6

13

D

Q20

STAR@

2N7002_SOT23-3

S

2

D

G

3

D

Q48

STAR@

2N7002_SOT23-3

S

1

C178 4.7U_0805_10V4Z

2

R98

1 2

33K_0402_5%

Q13

VLDT_EN#

2

2N7002_SOT23-3

G

2N7002_SOT23-3

1

C263 4.7U_0805_10V4Z

2

R137

12

SUSP

2N7002_SOT23-3

112

S

45

STAR@

10U_0805_10V4Z

112

C494

STAR@

1

C526

STAR@

0.1U_0603_25V4Z

2

+VSB

C252

1

C269

STAR@

0.1U_0603_25V4Z

2

+3V_WLAN

2

G

PJ21

2

JUMP_43X79@

G

3

PJ22

JUMP_43X79@

S

45

10U_0805_10V4Z

R111

+VSB

R166

Q19

2

G

B:1.Chg. PWR SW Q132 and Q133 from AO4422 to SI3456BDV

2.Remove Energy Star 4.0 function.

+3V_SB

1

2

1

STAR@

2

1 2
13

D

Q15

2

G

S

470_0805_5%

1 2
13

D

S

1

C255

STAR@

1U_0603_10V4Z

2

1

C509
1U_0603_10V4Z

2

Q49

470_0805_5%

+5VALW TO +5VS

+5VALW

4.7U_0805_10V4Z

Q17

C:Chg.Q17,Q20,Q7,Q8,Q48,Q49,Q54,Q55
PN to SB770020010.

D

S

+1.8V

4.7U_0805_10V4Z

Q36

8

D

7

D

6

D

5

D

SI4800BDY_SO8

1

C379

2

R143

STAR@

470_0805_5%

1 2
13

D

S

R320

STAR@

470_0805_5%

1 2
13

2

G

STAR@

2N7002_SOT23-3

B

+1.8V TO +1.8VS+1.2VALW TO +1.2V_HT

Q41

IRF8113PBF_SO8

8
7

5

1

C462

2

1

S

2

S

3

S

4

G

1

2

0.1U_0402_25V4Z

STB_SB#

2

G

STAR@

2N7002_SOT23-3

STB_WLAN#

B

B:Q18 and Q36, need to link "SB548000310"
C:Q14 and Q41, change part to reduce Rds(on) to improve PWR drop.
MP: Update R137 and R286 from 22K to 330K and C247 and C457 from 0.1U Y5V
to 0.01U X7R to meet PWR SEQ, and update C180 and C385 to 25V to meet PWR

+1.8VS

request.

1

1U_0402_6.3V4Z

1

C457

2

C362

R248

1 2

10K_0402_5%

2

G

Q35
2N7002_SOT23-3

C75

R30

C637

STAR@

+VSB

R400

C443

2

13

D

S

1

2

1

STAR@

2

STAR@

47K_0402_5%

STB_LAN#

1

STAR@

2

STAR@

47K_0402_5%

1
2
36

4

0.01U_0402_25V7K

C:Chg.Q13,Q15,Q16,Q19,Q34,Q35,Q43,Q44
PN to SB770020010.

+5VS

4.7U_0805_10V4Z

1

C363

2

1U_0402_6.3V4Z

13

D

C385

S

10U_0805_10V4Z

STAR@

+VSB

10U_0805_10V4Z

2

1

R286

330K_0402_5%

Q43

2

G

2N7002_SOT23-3

+VSB

SUSP

2

2N7002_SOT23-3

+3VALW

1

C67

2

10U_0805_10V4Z

12

2

G

+1.2VALW TO +1.2V_SB

+1.2VALW

1

C645

SI3456BDV-T1-E3_TSOP6

2

10U_0805_10V4Z

12

STB_SB#

2

G

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

C431
10U_0805_10V4Z

12

+VSB

SUSP

470_0805_5%

1 2
13

D

Q34

S

2

2N7002_SOT23-3

R237

G

+3VALW TO +3V_LAN

PJ20

2

JUMP_43X79@

Q132

D

6

S

45
2
1

G

3

STAR@

SI3456BDV-T1-E3_TSOP6

13

D

Q7

STAR@

2N7002_SOT23-3

S

2

Q56

D

6

S

2
1

G

STAR@

3

13

D

Q55

STAR@

2N7002_SOT23-3

S

R285

470_0805_5%

1 2
13

D

Q44

G

S

B:Add PD 100K bec'z KB926 is tri-state pin.

+3V_LAN

112

1

C85

STAR@

10U_0805_10V4Z

PJ23

JUMP_43X79@

45

10U_0805_10V4Z

1

C87

STAR@

0.1U_0603_25V4Z

2

112

C651

STAR@

1

C638

STAR@

0.1U_0603_25V4Z

2

2

+1.2V_SB

2007/5/4 2008/5/4

C

VLDT_EN<30>

100K_0402_5%

1

C86

STAR@

2

1U_0603_10V4Z

1

C656

STAR@

2

1U_0603_10V4Z

Compal Secret Data

VLDT_EN#

2

G

12

R478

D

Q8

S

1

2

Q54

Deciphered Date

+5VALW

12

R197
10K_0402_5%

13

D

S

C:Chg. PN to
SB770020010.

R29

STAR@

470_0805_5%

1 2
13

2

G

STAR@

2N7002_SOT23-3

R405

STAR@

470_0805_5%

1 2
13

D

2

G

STAR@

S

2N7002_SOT23-3

D

SUSP

R209

1 2

Q24
2N7002_SOT23-3

SUSP<41>

SUSP#<15,26,28,30,38>

10K_0402_5%

C:Chg. PN to SB770020010.

B:Chg. to POP material for discharge.

B:Remove Energy Star 4.0 function.
C:Chg. PN to SB770020010.

STB_LAN#

B:Remove STB_12SB# control
circuit and chagne control signl
to STB_SB#

STB_SB#

D

E

SUSP

STAR@

12

12

STAR@

12

E

SYSON#

2

G

1 2

R32

STB_LAN#

2

G

STB_SB#

2

G

R324

STB_WLAN#

2

G

+5VALW

+2.5VS

D

S

+5VALW

+5VALW

+5VALW

+5VALW

R210
10K_0402_5%

1 2
13

D

Q28

2

G

2N7002_SOT23-3

S

C:Chg. PN to
SB770020010.

+1.5VS +0.9V

R280

470_0805_5%

1 2
13

D

2

G

Q40

S

2N7002_SOT23-3

Compal Electronics, Inc.

Title

DC-DC INTERFACE

Size Document Number Rev

IALAA-Minnesota10A LA3631P 1A

B

Monday, May 14, 2007

Date: Sheet

SYSON#<41>

SYSON<26,28,30,32,40>

R212

10K_0402_5%

R433

470_0805_5%

1 2
13

STB_WLAN<30>

STB_LAN<30>

STB_SB<30>

D

2

G

Q57

S

2N7002_SOT23-3

R34

STAR@

100K_0402_5%

R172

STAR@

100K_0402_5%

R327

STAR@

100K_0402_5%

100K_0402_5%

100K_0402_5%

SUSP SUSP

R211
10K_0402_5%

1 2
13

D

Q29
2N7002_SOT23-3

S

C:Chg. PN to
SB770020010.

R272

470_0805_5%@

1 2
13

2

G

Q39

2N7002_SOT23-3@

1 2

13

D

Q9

STAR@

2N7002_SOT23-3

S

R165

STAR@

100K_0402_5%

1 2

13

D

Q21

STAR@

2N7002_SOT23-3

S

1 2

13

D

Q50

STAR@

2N7002_SOT23-3

S

35 45

of

A

PL1

HCB4532KF-800T90_1812

1 2

PC2

100P_0402_50V8J

VIN

PD2
RLS4148_LL34-2

1 2
12

PR9

68_1206_5%

13

12

PC8

0.1U_0603_25V7K

PD5
RLZ16B_LL34@

2 1

12

12

PR10
68_1206_5%

PD3

RLS4148_LL34-2

PR12

200_0603_5%

1 2

PR14

100K_0402_1%

1 2

PR15

22K_0402_1%

RTCVREF

3.3V

12

PC9
10U_0805_6.3V6M

PF1

21

10A_125V_451010MRL

12

12

12

PU2 G920AT24U_SOT89-3

3

OUT

GND

12

PC1
1000P_0402_50V7K

PQ1

N1

PC7

0.22U_1206_25V7K

TP0610K-T1-E3_SOT23-3

N2

2

IN

1

12

2

12

PR17
200_0603_5%

12

PC10
1U_0805_25V4Z

DC301001Q00

PJP1

1

+

2

+

3

SINGA_2DW-0005-B03@

560_0603_5%

1 2

-

-

PR21

4

51_ON#<32>

1 1

2 2

+CHGRTC

3 3

DC_IN_S1 DC_IN_S2

BATT+

CHGRTCP

PR22

560_0603_5%

1 2

B

PC3
1000P_0402_50V7K

VS

VIN

12

PC4
100P_0402_50V8J

MAINPWON<6,37,39>

ACON<38>

12

PC5

0.068U_0402_10V6K

2
3

VIN

12

PR3

84.5K_0402_1%

12

PR6
20K_0402_1%

VIN

VL

PD6

1

RB715F_SOT323-3

PR5
22K_0402_1%

1 2

12

PD4

RLS4148_LL34-2

100K_0402_1%

1 2

PC6

0.1U_0402_16V7K

12

PR18

1000P_0402_50V7K

PR1

1M_0402_1%

1 2

VS

8

3

+

2

-

4

PR8

10K_0402_1%

PR11
1K_1206_5%

N3

PR13
1K_1206_5%

PR16
1K_1206_5%

PC12

PU1A

P

1

O

G

LM393DG_SO8

12

RTCVREF

3.3V

1 2

1 2

1 2

LM393DG_SO8

12

1000P_0402_50V7K

C

PU1B

7

O

PD1

RLZ4.3B_LL34

PR19

2.2M_0402_5%

8

P

+

-

G

4

PC13

5
6

VS

12

12

PR2

5.6K_0402_5%

12

12

12

PR25

66.5K_0402_1%

12

PR23

34K_0402_1%

PR4

10K_0402_1%

1 2

PACIN

PR7
10K_0402_1%

12

VL

12

ACIN <30,32>

PACIN <38>

Vin Detector

High 18.384 17.901 17.430
Low 17.728 17.257 16.976

B+

12

PR20
499K_0402_1%

12

PR24

499K_0402_1%
PR26
191K_0402_1%

D

12

PC11
1000P_0402_50V7K

PJ2

+3VALWP +3VALW

+5VALWP

+VSBP +VSB

(120mA,40mils ,Via NO.= 2)

4 4

2

112

(5A,200mils ,Via NO.= 10)

(5A,200mils ,Via NO.= 10)

JUMP_43X118@

PJ4

2

112

JUMP_43X118@

PJ6

2

112

JUMP_43X39 @

+1.8VP +1.8V

(8A,320mils ,Via NO.= 16)

+5VALW

(3.0A,120mils ,Via NO.=6)

(2A,80mils ,Via NO.= 4)

+1.2VALWP

(1A,40mils ,Via NO.=2)

A

PJ3

2

112

JUMP_43X118@

PJ5

2

112

JUMP_43X118@

PJ7

2

112

JUMP_43X79@

PJ9

2

112

JUMP_43X118@

+1.5VS+1.5VSP

+0.9V+0.9VP

+1.2VALW

(8A,320mils ,Via NO.=16)

PJ11

2

112

JUMP_43X39 @

Precharge detector

15.97V/14.84V FOR
ADAPTOR

+2.5VS+2.5VSP

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

C

PQ2

13

D

S

RHU002N06_SOT323-3

2008/5/42007/5/4

PR27

47K_0402_1%

2

G

13

PQ3
DTC115EUA_SC70-3

2

Title

Size Document Number Rev

Date: Sheet

PACIN

12

+5VALWP

Compal Electronics, Inc.

DCIN & DETECTOR

IALAA-Minnesota10A LA3631P

D

1A

of

36 45Monday, May 14, 2007

A

B

C

D

PH1 under CPU botten side :

CPU thermal protection at 92 degree C
Recovery at 56 degree C

VL VS

1 1

2 2

3 3

PJP2

10

GND

11

GND

OCTEK_BTJ-09HA1G

BATT_S1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

PR34

100_0402_1%

POK<39,40>

VL

PR47

1 2

1 2

B+

PR48

100K_0402_1%

0_0402_5%

1 2

1 2

PR29 1K_0402_1%

PR35
100_0402_1%

PR40

1K_0402_1%

2

G

12

PC22

1 2

12

13

D

S

PF2

15A_65V_451015MRL

12

PR33
1K_0402_1%

PR38

6.49K_0402_1%

PR46
22K_0402_1%

1 2

PQ6
RHU002N06_SOT323-3

21

1 2

PR30

47K_0402_1%

12

12

PR45

100K_0402_1%

PQ5 TP0610K-T1-E3_SOT23-3

12

PC20

0.22U_1206_25V7K

@

VMB

+3VALWP

2

PL2

HCB4532KF-800T90_1812

1 2

12

PC15
1000P_0402_50V7K

ALI/MH# <30,38>

+3VALWP

BATT_TEMPA <30>

EC_SMB_DA1 <30,31>
EC_SMB_CK1 <30,31>

13

12

PC21

@

+VSBP

0.1U_0603_25V7K

BATT+

12

PC16

0.01U_0402_25V7K

100K_0603_1%_TH11-4H104FT

PH1

PC17

0.22U_0805_16V7K

12

12

0.1U_0603_25V7K

12

PR36

15.4K_0402_1%

13.7K_0402_1%

1 2

PR32

12

PC14

TM_REF1

12

PC18

1000P_0402_50V7K

12

PH2 near main Battery CONN :

BAT. thermal protection at 92 degree C
Recovery at 56 degree C

12

100K_0603_1%_TH11-4H104FT

0.22U_0805_16V7K

PH2

PR43

13.7K_0402_1%

1 2

12

12

PC19

PR44

15.4K_0402_1%

TM_REF1

8

3

P

+

2

-

G

4

PR37

100K_0402_1%

PR39
100K_0402_1%

47K_0402_1%

5

+

6

-

1 2

1 2

PR31

47K_0402_1%

PU3A

1

O

LM393DG_SO8

12

VL

PR42

8

PU3B

P

7

O

G

LM393DG_SO8

4

VL

PR28
47K_0402_1%

1 2

1SS355_SOD323-2

VLVL

PR41
47K_0402_1%

1 2

PD7

2

12

PD8

12

1SS355_SOD323-2

MAINPWON <6,36,39>

13

PQ4
DTC115EUA_SC70-3

0.1U_0402_16V7K

@

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

C

2008/5/42007/5/4

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

BATTERY CONN / OTP

IALAA-Minnesota10A LA3631P

D

37 45Monday, May 14, 2007

1A

of

A

B

C

D

75W Iadapter=0~3.947A PR49=0.02 ohm CP=3.71A PR66=10.7K

PQ8

VIN

1 1

12

13

D

PQ15

2

G

S

2 2

PACIN<36>

5
6
7
8

PR52
47K_0402_1%

2

13

2

RHU002N06_SOT323-3

ACON<36>

4

G

D

3

S

D

2

S

D

1

S

D

FDS4435BZ_SO8

PQ11

1 3

DTA144EUA_SC70-3

PQ13

DTC115EUA_SC70-3

PACIN

1 2

PR64

22K_0402_1%

ACON

ACOFF

2

150K_0402_1%

P2

12

12

PC26

0.1U_0603_25V7K

12

PR58

13

2

G

13

PQ41
DTC115EUA_SC70-3

PR50
200K_0402_1%

D

PQ17

S

RHU002N06_SOT323-3

IREF<30>

Iadp=0~3.6A

PQ9

1

S

D

2

S

D

3

S

D

4

G

D

FDS4435BZ_SO8

5600P_0402_25V7K

6251VDD

1 2

PR55

10K_0402_1%

ALI/MH#<30,37>

0.01U_0402_25V7K

1 2

15.4K_0402_1%

10K_0402_1%

6251VREF

PR71

47K_0402_1%@

P3 B+

8
7
6
5

P3

12

PC142

100K_0402_1%

13

1 2

12

0_0402_5%

PQ12
DTC115EUA_SC70-3

PR59
10K_0402_1%

1 2

100P_0402_50V8J

0.1U_0402_16V7K

6251VREF

2

FSTCHG<30> ACOFF <30>

2

PC33

1 2

ADP_I<30>

PR65

PR68

12

PR49

0.02_2512_1%

1
2

TP0610K-T1-E3_SOT23-3

12

PR231

6251VDD

PR53

12

PC30

680P_0402_50V7K@

CSON

1 2

1 2

PC31 6800P_0402_25V7K

PC34

PR69

10K_0402_1%

SI2301BDS-T1-E3_SOT23-3@

PC35

1 2

10.7K_0402_1%

PR66

1 2

12

13

28.7K_0402_1%@

PQ40

PR60

1 2

100_0402_1%

6251VREF

PR70

1 2

4
3

PQ52

2

PC27

12

2.2U_0603_6.3V6K

6251_EN

12

PR61

0_0402_5%@

IREF=1.016*Icharge
IREF=0.508V~3.048V

3 3

90W Iadapter=0~4.737A PR49=0.015 ohm CP=4.459A PR66=19.6K
120W Iadapter=0~6.315A PR49=0.010 ohm CP=5.936A PR66=19.6K PR69=4.53K

PJ13

2

DCIN

13

PC172

0.1U_0603_25V7K

1 2

PR230 100K_0402_1%

1 2

PU4

1

VDD

2

ACSET

3

EN

4

CELLS

5

ICOMP

6

VCOMP

7

ICM

8

VREF

9

CHLIM

10

ACLIM

11

VADJ

12

GND

ISL6251AHAZ-T_QSOP24

DCIN

ACPRN

CSON

CSOP

CSIN

CSIP

PHASE

UGATE

BOOT

VDDP

LGATE

PGND

JUMP_43X118@

13

24

23

22

21

20

19

18

17

16

15

14

13

112

PQ51

DTC115EUA_SC70-3

2

RB715F_SOT323-3
PC105

DCIN

1 2

0.1U_0603_25V7K@

PC32

0.1U_0603_25V7K

1 2

LX_CHG

DH_CHG

BST_CHG

2.2_0603_5%

6251VDDP

2

1

3

PD19

BATT+

PR117

20_0603_5%

1 2

PC29

0.047U_0603_25V7M

1 2

1 2

PR56

20_0603_5%

1 2

PR57 20_0603_5%

1 2

PR118

2.2_0603_5%
PR229 0_0603_5%

PR63

1 2

2 1

PC37

1 2

4.7U_0805_6.3V6K

CSIP
CSIN

FSTCHG

BST_CHGA

PC23

4.7U_1206_25V6K

SUSP# <15,26,28,30,35>

12

PC36

0.1U_0603_25V7K

CH751H-40PT_SOD323-2

PD10

6251VDD

1 2

4.7_0603_5%
PR67

DL_CHG

CSON

CSOP

12

12

PC24

4.7U_1206_25V6K

12

BATT Type ALI/MH# Charge Current IREF

3 CELL
6 CELL
9 CELL

3.3V

3.3V

3.3V

1.5A

3.0A

3.0A

1.524V

3.048V

3.048V

B++

12

PC25

4.7U_1206_25V6K

10K_0402_1%

ACOFF#

5

DTC115EUA_SC70-3

D8D7D6D

PQ16

S1S2S3G

SI4800BDY-T1-E3_SO8

4

5

4

PL3

16UH_LF919AS-160M=P3_3.7A_20%

1 2

D8D7D6D

PQ18

S1S2S3G

SI4800BDY-T1-E3_SO8

PQ14

PR54

CHG

1 2

13

PQ7

1 2

PR51
47K_0402_1%

2

0.1U_0603_25V7K

1
2

PR62

0.02_2512_1%

1
2
3
4

@

1
2
3
4

S

D

S

D

S

D

G

D

FDS4435BZ_SO8
PQ10

S

D

S

D

S

D

G

D

FDS4435BZ_SO8

VIN

PD14

1 2

1SS355_SOD323-2

PD15

1 2

1SS355_SOD323-2
PC109

4
3

PC38

8
7
6
5

8
7
6
5

12

1 2

D

S

CC=0.5~3A
CV=12.6V(6 CELLS LI-ION)

PR72

VIN

200K_0402_1%

PQ20

13

PACIN

2

G

RHU002N06_SOT323-3

12

PC39

10U_1206_25V6M

BATT+

12

10U_1206_25V6M

VMB

PC40

0.01U_0402_25V7K

12

PR73

340K_0402_1%

12

PR74

499K_0402_1%

12

PR75

105K_0402_1%

12

2008/5/42007/5/4

LI-3S :13.5V----BATT-OVP=1.5V
LI-4S :18V----BATT-OVP=2V

PC41

BATT-OVP=0.111*BATT+

0.01U_0402_25V7K

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

CHARGER

IALAA-Minnesota10A LA3631P

D

1A

of

38 45Monday, May 14, 2007

8

PU5A

3

P

+

0

2

-

G

LM358DT_SO8

4

Deciphered Date

C

VS

12

6251VREF

12

PR232

100K_0402_1%@
PC173

CSON

1 2

0.01U_0402_25V7K @

4 4

12

PR233

20K_0402_1%@

6251_EN

C

PQ53

2

B

2SC2411KT146_SOT23-3@

E

3 1

BATT_OVP<30>

IALAA-Minnesota10A LA3631P

Security Classification

PR184

1 2

10K_0402_1%

1

Compal Secret Data

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

5

PJ18

12

1

+

1000P_0402_50V7K

2

@

PR82

2

JUMP_43X118@
PC78
680P_0402_50V7K

@

12

PC53

1 2

1 2

4.22K_0402_1%

112

SI4800BDY-T1-E3_SO8

PL6

3.3UH_SIL1045R-3R3PF_8.2A_30%

PR80

10K_0402_1%

12

PR128

4.7_1206_5% @

PC94

680P_0603_50V7K@

PQ22

12

12

B+

D D

OCP=8A

+3VALWP

C C

PC54

330U_D3L_6.3VM_R25M

VL

12

PR86

PR88

MAINPW O N<6,36,37>

B B

0_0402_5%

0.047U_0603_16V7K

PC57

12

806K_0603_1%

12

D8D7D6D

S1S2S3G

D8D7D6D

S1S2S3G

VS

RLZ5.1B_LL34

4

PC42

4.7U_1206_25V6K

5

PR186

4

0_0603_5%

1 2

5

PQ24
SI4810BDY-T1-E3_SO8

4

PD11

1 2

1 2

12

12

PC43

4.7U_1206_25V6K

PC48

0.1U_0603_25V7K

PR89
10K_0402_1%

12

0.1U_0603_25V7K

PC50

12

+VCC_TPS51120

PR79
0_0603_5%

1 2

DH_3V
LX_3V
DL_3V

FB3

1 2

PR105 0_0402_5%

PC56

12

PC58

2.2U_0805_25V6K

@

PC46

1U_0603_10V6K

22
20

9
13
14
15
16
17

8

6
12

29
19
10

+3.3V_RTC_LDO

12

10U_0805_6.3V6M

12

PU6

5.1_0603_5%

VIN
V5FILT
EN5
VBST2
DRVH2
LL2
DRVL2
PGND2
VO2
VFB2
EN2

EN1
VREG3
EN3

3

PR76

32 QFN 5X5

SKIPSEL

32

PR85
10K_0402_1%

1 2

VL

12

21

VREG5

28

VBST1

27

DRVH1

26

LL1

25

DRVL1

24

PGND1

1

VO1

3

VFB1

2

COMP1

7

COMP2

23

CS1

18

CS2

4

VREF2

31

TONSEL

5

GND

30

PGOOD1

11

PGOOD2

PAD

33

TPS51120RHBR_QFN32_5X5

12

PC47

10U_0805_10V4Z

PR77

0_0603_5%

1 2

DH_5V
LX_5V
DL_5V

FB5

TPS51120_CS1
TPS51120_CS2

+3VALWP

PR90

100K_0402_1%

1 2

PC49

0.1U_0603_25V7K

1 2

SI4810BDY-T1-E3_SO8

PC55

POK <37,40>

2

12

PC44

PC45

4.7U_1206_25V6K

4.7U_1206_25V6K

PR185

0_0603_5%

1 2

PQ23

12

1000P_0402_50V7K

PR83

12

5

4

5

4

14.7K_0402_1%

1 2

D8D7D6D

PQ21
SI4800BDY-T1-E3_SO8

S1S2S3G

D8D7D6D

S1S2S3G

PR84

1 2

14.7K_0402_1%

3.3UH_SIL1045R-3R3PF_8.2A_30%

1 2

12

12

PR129

4.7_1206_5%@

PC95

680P_0603_50V7K

@

+VCC_TPS51120

PL5

PR87

0_0402_5%

1 2

1

PR78

10.2K_0402_1%

PR81

2.49K_0402_1%

1 2

1 2

OCP=8A

+5VALWP

12

PC51

1000P_0402_50V7K

@

1

+

PC52

2

330U_D3L_6.3VM_R25M

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2007/5/4 2008/5/4

3

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

2

Date: Sheet

+5V/+3V

IALAA-Minnesota10A LA3631P

Tuesday, M ay 15, 2007

1

39 45

of

1A

A

B

C

D

PJ14

2

1 2

1 2

112

JUMP_43X118@

12

PC74

0.01U_0402_25V7K

12

12

PC59

4.7U_1206_25V6K

D8D7D6D

S1S2S3G

D8D7D6D

S1S2S3G

1 2

PR107

0_0402_5%

PC63

4.7U_0805_6.3V6K

5

4

0.1U_0402_16V7K

5

PQ27

SI4810BDY-T1-E3_SO8

4

VSE_1.8V

0.1U_0402_16V7K@

PC68

2K_0402_1%

1 2

1 1

SI4800BDY-T1-E3_SO8

PQ25

+1.8VP

+1.8VP

1.8U_D104C-919AS-1R8N_9.5A_30%

12

12

12

12

PR188
0_0402_5%

12

PC71

0.01U_0402_25V7K

VDDIOFB_H<6>

1

+

PC70

220U_D2_4VM_R15

2 2

2

PR187

@

0_0402_5%

PR98

10K_0402_1%

PR108

10K_0402_1%

1 2

PR102
0_0402_5%

1 2

PR111

0_0402_5%@

1 2

PL7

LX_1.8V

PR95

4.7_1206_5%@

1 2

PC72

680P_0603_50V8J@

1 2

SYSON<26,28,30,32,35>

12

BST_1.8V-1

1 2

12

0_0603_5%

1 2

PR96

0_0603_5%
PR100

PC76

PC60

4.7U_1206_25V6K

PD12

1

2

3

0.01U_0402_25V7K

PR93

DH_1.8V-1

PC64

0.1U_0603_25V7K

DAP202U_SOT323-3

BST_1.2V-1

PC66

12

12

BST_1.8V-2

6

5
4

ISE_1.8V ISE_1.2V
DL_1.8V

7
2

3

9

10

8

15
11

12

12

PR113
100K_0402_1%

0_1206_5%

PU7

SOFT1

BOOT1

UGATE1
PHASE1

ISEN1
LGATE1

PGND1

VOUT1
VSEN1
EN1
PG1

OCSET1

PR91

12

12

12

12

PC61

12

DH_1.2V-2

LX_1.2V

PQ28

4.7U_1206_25V6K

5

D8D7D6D

PQ26

SI4800BDY-T1-E3_SO8

S1S2S3G

4

1.8U_D104C-919AS-1R8N_9.5A_30%

5

4

D8D7D6D

S1S2S3G

VSE_1.2V

POK <37,39>

PR99

1 2

PC75

1 2

1 2

4.7_1206_5%@

680P_0603_50V8J@

+5VALWP

12

PR92

2.2_0603_5%

1 2

14

28

VCC

SOFT2

VIN

BOOT2

UGATE2
PHASE2

ISEN2

LGATE2

PGND2

VOUT2
VSEN2

EN2

PG2/REF

GND

1

OCSET2

DDR

13

ISL6227CAZ-T_SSOP28

PC65

2.2U_0805_10V6K

PC67

0.01U_0402_25V7K

12

17

BST_1.2V-2

1 2

23

PR94
0_0603_5%

DH_1.2V-1

24
25

22
27

26

20
19
21
16

18

12

PR112
100K_0402_1%

PC69

0.1U_0402_16V7K

1 2

PR97

0_0603_5%
PR101

2K_0402_1%

1 2

SI4810BDY-T1-E3_SO8

DL_1.2V

1 2

PR106
0_0402_5%

12

PC77

0.1U_0402_16V7K @

PL8

PC62

4.7U_1206_25V6K

PR103

0_0402_5%

PR109

0_0402_5%@

B+

+1.2VALWP

+1.2VALWP

PR104

2.21K_0402_1%

PR110

6.49K_0402_1%

1

+

2

12

12

PC73
220U_D2_4VM_R15

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

C

2008/5/42007/5/4

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

1.8V / 1.2V

IALAA-Minnesota10A LA3631P

D

40 45Monday, May 14, 2007

1A

of

5

4

3

2

1

D D

C C

PC79

12

+3VS

2

PQ29

G

1

PJ10

1

JUMP_43X79@

2

2

1 2

1.15K_0402_1%

13

D

S

1K_0402_1%

PR115

PR116

12

12

PC81

0.1U_0402_16V7K

12

2
3
4

12

PC82
10U_1206_6.3V7K

PU10

VIN1VCNTL

NC

GND
VREF

NC

VOUT

NC

TP

APL5331KAC-TRL_SO8

+1.5VSP

SYSON#<35>

6
5
7
8
9

+5VALW

12

PC83
1U_0603_6.3V6M

B B

4.7U_0805_6.3V6K

RHU002N06_SOT323-3

SUSP

0.1U_0402_16V7K@

1 2

PR114

0_0402_5%

PC80

SUSP<35>

A A

+3VS

0_0402_5%

1 2

0.1U_0402_16V7K@

+3VS

4.7U_0805_6.3V6K

PR138

PC101

PJ19

2

JUMP_43X79@

12

112

4.7U_0805_6.3V6K

1 2

PR127

10K_0402_1%

0.1U_0402_16V7K

+1.8V

1

1

2

2

PC97

1 2

13

D

2

G

S

PQ33

RHU002N06_SOT323-3

PC91

PC93

PJ16
JUMP_43X79@

PR136

1K_0402_1%

PR137

1K_0402_1%

1 2

12

12

12

PC99

0.1U_0402_16V7K

PU12

VIN2VO

1
5
6

ADJ

EN
GND

GND
GND

GND

G965-18ADJP1UF_SO8

2
3
4

12

12

PC100
10U_1206_6.3V7K

3
4
7
8

PU9

VIN1VCNTL

NC

GND
VREF

NC

VOUT

NC
TP

APL5331KAC-TRL_SO8

+0.9VP

12

PR125
22K_0402_1%

12

PR126
20K_0402_1%

6
5
7
8
9

PC92
10U_1206_6.3V7K

1 2

+3VALW

12

PC98
1U_0603_6.3V6M

+2.5VSP

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

5

4

3

Compal Secret Data

Deciphered Date

2008/5/42007/5/4

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

0.9V//1.5V/2.5V

IALAA-Minnesota10A LA3631P

41 45Monday, May 14, 2007

1

1A

of

5

4

3

2

1

5

4

12

5

4

1 2

CPU_B+

12

12

12

PC145

PC144

PQ42
SI7840DP-T1-E3_SO8

3 5

241

5

PQ43

PQ49

FDS6676AS_SO8

220P_0402_25V8K@

FDS6676AS_SO8

D8D7D6D

S1S2S3G

4

PR211 0_0402_5%

1 2

PC161

3 5

241

5

D8D7D6D

S1S2S3G

4

PQ44

PQ46

D8D7D6D

S1S2S3G

12

D8D7D6D

S1S2S3G

10U_1206_25VAK

PR198

4.7_1206_5%

FDS6676AS_SO8

SI7840DP-T1-E3_SO8

PR224

4.7_1206_5%

1 2
12

1 2
12

PC153

PC163

220P_0603_50V8J

PC168

10U_1206_25VAK

12

220P_0603_50V8J

12

PC164

10U_1206_25VAK

12

PD18

12

PC146

10U_1206_25VAK

0.36UH_PCMC104T-R36MN1R17_30A_20%

PD17

EC31QS04

12

10U_1206_25VAK

EC31QS04

PC148

PC147

0.1U_0603_25V7K

1 2

12

PR200

4.22K_0402_1%

PR203

2.1K_0402_1%

1 2

PC155

0.1U_0603_16V7K

CPU_B+

12

PC165

10U_1206_25VAK

0.36UH_PCMC104T-R36MN1R17_30A_20%

1 2

PR225

4.22K_0402_1%

1 2

PR227

2.1K_0402_1%

1 2

PC169

0.1U_0603_16V7K

+3VS

12

PR189
10_0402_5%

PC151

1 2

2.2U_0603_6.3V6K

12

12

PR217
0_0402_5%

8774VCC

D0
D1
D2
D3
D4

D5
8774PWRGD
8774PHASEGD
8774VCC
8774SHDN#
8774TIME
8774CCV
8774POUT
8774REF
8774TON
8774OFS

8774SKIP#

12

D D

1 2

PR206
100K_0402_1%@

1 2

PR210
10K_0402_1%

1 2

PR212
200K_0402_1%

12

13

D

PQ45
RHU002N06_SOT323-3

S

PR220

2

PR191 0_0402_5%
PR192 0_0402_5%
PR194 0_0402_5%
PR196 0_0402_5%
PR197 0_0402_5%
PR199 0_0402_5%
PR201 0_0402_5%

1 2

1 2

PR202

100K_0402_1%

PC162
470P_0402_50V8J

1 2

12

PR221

100K_0402_1%

2

G

1

PQ50
PMBT2222A_SOT23-3

3

VID0<6>
VID1<6>
VID2<6>
VID3<6>
VID4<6>
VID5<6>

VGATE<30>

+3VS

PR205

0_0402_5%

POUT

PC158

0.1U_0402_16V7K

PR213

20K_0402_1%

1 2

1 2

1 2

169K_0603_1%

1 2

0_0402_5%

PR216

2

G

100K_0402_1%

PR226

CPU_B+

C C

B B

VR_ON<30>

8774REF

PSI#<6>

PR190

10K_0402_1%

12
12
12
12
12
12

PR207 71.5K_0402_1%

PC156
150P_0402_50V8J

1 2

PC159

0.1U_0603_25V7K

+5VS

12

13

D

PQ47
RHU002N06_SOT323-3

S

12

+5VS

PU13
MAX8774GTL+_TQFN40

19

VCC

31

D0

32

D1

33

D2

34

D3

35

D4

36

D5

1

PWRGD

17

PHASEGD

37

TWO-PH

38

SHDN#

6

TIME

8

CCV

3

POUT

10

REF

7

TON

2

OFS

4

VRHOT#

39

SKIP#

41

4700P_0402_25V7K

EP

PC166

PR223

10_0402_5%

PGND1

PGND2

GNDS

12

12

VDD

THRM

BST1

CSP1
CSN1

GND

BST2

CSP2
CSN2

12

PC149

1 2

2.2U_0603_6.3V6K

25
5

8774BST1 8774BST1A

30

8774DH1

29

DH1

8774LX1

28

LX1

8774DL1

26

DL1

27

8774CSP1

16

8774CSN1

15
18
40

IC

8774FB

11

FB

8774CCI N77

9

CCI

8774BST2

20

8774DH2

21

DH2

8774LX2

22

LX2

8774DL2

24

DL2

23

8774CSP2

13

8774CSN2

14

12

PR222
10_0402_1%

CPU_VSS_SENSE<6>

220P_0402_25V8K @

PR193

2.2_0603_5%

1 2

1 2

PR195 0_0603_5%

PR208
2K_0402_1%

1 2

1 2

PC157
470P_0402_50V8J

PC170

PC152

0.22U_0603_16V7K

1 2

PC154 4700P_0402_25V7K

1 2

1 2

PR209
20K_0402_1%

1 2

PR215

2.2_0603_5%

12

8774BST2A

PR219

12

PC167

0.22U_0603_16V7K

8774DH2A

12

12

PC171

220P_0402_25V8K@

8774DH1A

220P_0402_25V8K@

0_0603_5%

PQ48

PC160

FDS6676AS_SO8

PR228
0_0402_5%

+CPU_CORE

1

12

2

2200P_0402_50V7K

PL10

PH3

10KB_0603_5%_ERTJ1VR103J

1 2

1 2

PR214 10_0402_1%

1 2

PL11

PH4

10KB_0603_5%_ERTJ1VR103J

1 2

1 2

HCB4532KF-800T90_1812

1 2

+

PC143

220U_25V_M

PL9

12

+CPU_CORE

12

PR204
10_0402_5%

12

PR218
0_0402_5%

CPU_VCC_SENSE <6>

B+

PC150

220P_0603_50V8J

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITT EN CON SENT O F COMPAL ELECTRONICS, INC.

3

2007/5/4 2008/5/4

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

+CPU_CORE

IALAA-Minnesota10A LA3631P

Monday, May 14, 2007

of

42 45

1

1A

POWER PIR LIST

page Reason for change

DVT

Design change PF2 value Change PF2 Fuse from 12A to 15A37

Design change PU4 schematic Add PR117,PR118. 38

42 improve CPU-core ripple Change PR214,PR222 from 100 to 10

Add EMI soultion

Modify list

Change value PC29,PC32,PR56,PR57,PQ18

Remove PR232,PR233,PC173,PC105

Change PC155,PC169 from 0.22u to 0.1u

Change PR213 from 31.6K to 20K

Change PC150,PC153,PC168 from 680P to 220P

Change boost resistors PR193,PR215 from 0 to 2.2

Change low-side mosfet PQ43,PQ44,PQ48,PQ49 at CPU-core.

PVT

Pre-MP

Design change PH1 temperature set value Change PR36 from 22K to 15.4K37

Design change PH1 temperature set value Change PR44 from 22K to 15.4K

37

Security Cl assification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE C OMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INF ORMATION IT CONTAI NS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WR ITT EN CO NSE NT OF COMPAL ELECTRONICS, INC.

2007/5/4 2 008/5/4

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Docu m e nt N u m b er Re v

Date: Sheet

PIR

IALAA-Minnesota10A LA3631P

43 45Monday, May 14, 2007

of

1A

5

4

3

HW4 Product Improvement Record (P.I.R.)

2

1

Phase: to Date:

Page#

D D

01. 2007/2/12

Action Plan
(add; del; change)

P30

Location or
Net_List

Before value
(Attached file)

After value
(Attached file)

Writer:

Detail Discretion and Root Cause

Rev.

DL/DM Check

Rev 0.3 LA-3631P Implement items:

01. P06 Update THERMTRIP# control circuit, follow AMD request.

02. P07 Change C652 and C557 to SGN00000800

03. P08 Swap RP20 signals for DDR shielding.

04. P11,P13,P24 Set BOM Structure for UMA@, DVD@

05. ALL Change 2N7002 main source to SB770020010 for unit.

06. P27 Add D6, D3, ESD Diod for EMI, Chenge Encoder, SW6, PN to DEB00000600

07. 15 Unit Q1,Q3,Q52 w/ same part.

08. 24,P34 Change D31 and D28 to SC1BAS16000

09. P14 Add C13,C16,C21 with 22P for EMI.

10. P16 Change R436 and R437 to 120 Ohm to meet ADM request

C C

11. P29 Remove R113, R117, R135 and R141 to leave chock for AMD platform

12. P28 Reserve C730~C736 by EMI request.

13. P21 Swap JP28 LED behaivor signals.

14. P28 Swap JP20 RX/TX Lanes sigals for Express Card cna't detect issue.

Rev 0.4 LA-3631P Implement items:

01. P24 Cut JP1.7 Pad for soldring issue.

02. P34 Change Q46 to SB934090000 for Fan can't meet Max. speed issue.

Rev 1.0 LA-3631P Implement items:

01. P22 Reserve C737, C738 for EMI solution

02. P6 Reserve R490 for PROCHOT funcation

03. P11 Add R488, R489 for LCD flash when boot issue

Rev 1A LA-3631P Implement items:

B B

01. P22 Add R196 and C320 in BOM as EMI requirment.

02. P17 Add U35 and C740, reserve R1178 for LAN Leakage problem

03. P19 Change C647 to 22u for sequence and L59 to DCR is 0.4Ohm to meet AMD requirement.

04. P20 Change R431 and R430 to 24K; R1176 and R1177 to 19.2K, follow ATI ER.

05. P13 Change R369 from 33Ohm to 90Ohm Bead.

06. P30 ENE's recommend, change back C541 and C542 from 27P to 15P.

07. P06 Reserve pull up resistor R490 for H_PROCHOT#

08. P24/P29 Swap USB2+/- and USB8+/- for CAMERA problem.

09. P14/P20 Change D10 and D29 part to meet HDMI and CRT power requirment.

10. P20 Update HDMI Hot Plug DET circuit, to add U34, C739.

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Compal Secret Data

Deciphered Date

2008/5/42007/5/4

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

PIR

44 45Wednesday, May 16, 2007

1

1A

of

45@ Part

5

PJP1

4

3

2

1

DC-IN JACK45@

PCB

D D

CHIPSET(R1)

LAN

ZZZ

DAZ02500101 LA-3631P

U5

U4

U5

RS690MCUMAR1@

RTL8101E8101E@

RS690MCUMAR3@

C473

1000P_0402_25V8J8101E@

C464

U5

RX690VGAR3@

U4

RTL8111C8111C@

U26

SB600SBR3@

L46

0_0603_5%8111C@

22U_A_4VM8101E@

C C

U23

TRANSFORMER

Card BUS

TST1284100M@

U11

PCI84028402@

R480

0_0603_5%8101E@

B B

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Compal Secret Data

Deciphered Date

2008/5/42007/5/4

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

PIR

45 45Tuesday, May 15, 2007

1

1A

of