Quanta LA-1441 ATW05, Satellite 1200 Schematic

A B C

1 1

D

E

ATW05

2 2

LA-1441 REV0.2 Schematics Document

uFCBGA/uFCPGA Coppermine-T or
Tualatin CPU

with Almador-MG
chipset

3 3

4 4

Compal Electronics, Ltd.

Title

Cover Sheet

Size Document Number Rev
Custom

LA-1441

Date: Sheet of

1 43Wednesday, March 06, 2002

E

0.2

檔

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

D

A B C

BLOCK DIAGRAM

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

D

E

4 4

CRT CONN.

PAGE 16

Mobile Tualatin
or
Coppermine-T

(uFCBGA/uFCPGA)

PAGE 4,5,6

PSB

Thermal Sensor
MAX1617MEE

PAGE 5

CK TITAN
ICS9250-38

PAGE12

CPU VID & All
reference voltage

PAGE 7

Almador-M

LVDS CONN.

PAGE 16

3 3

USB Port

HDD Connector

VCH
CONN.

PAGE 27

PAGE 20

GM Bus Interface

PAGE 15

USB

ATA 66/100

CD-ROM Connector

PAGE 20

2 2

LPC

GMCH-M

625 BGA

PAGE 8,9,10,11

HUB Interface

ICH3-M

421 BGA

PAGE 17,18,19

Memory Bus

PCI BUS

SO-DIMM * 2

BANK 2,3,4,5

LAN

RTL8100-L

PAGE 21

Mini PCI
Socket

PAGE 28

CardBus
TI

PCI1420

PAGE 23

PAGE 13,14

Slot 0/1

PAGE 24

FAN on controller &
TEMP. sensing circuit

PAGE 35

DC/DC Interface
RTC Battery

PAGE 37

BATTERY

Super I/O

LPC47N227

PAGE 25

1 1

Parallel

PAGE 26

FIR

PAGE 26

FDD

PAGE 20

Embedded
Controller

NS PC87591

PAGE 33

Scan KB

PAGE 15

BIOS & I/O
PORT

PAGE 34

C

AC'97
CODEC
CS4299

PAGE 31

Audio Jack

PAGE 32

Audio Amplifier

PAGE 32

D

Compal Electronics, Ltd.

Title

Block Digram

Size Document Number Rev
Custom

LA-1441

Date: Sheet of

Charger

POWER
Interface

PAGE 40,42,43,44

PAGE 41

E

2 43Wednesday, March 06, 2002

0.2

檔

A B C

Voltage Rails

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

D

E

PIR

Power Plane Description

1 1

B+
+VCC_H_CORE
+VTT

VIN

Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU

1.2V switched power rail for CPU AGTL Bus
+1.5V 1.5V power rail ON ON OFF
+1.5VS

AGP 4X ON OFF OFF
+1.8V 1.8V power rail ON ON OFF
+1.8VS
+2.5V
+3VALW
+3V
+3VS
+5VALW
+5V ON
+5VS

2 2

+12VALW
+12VS
RTCVCC

1.8V switched power rail

2.5V power rail

3.3V always on power rail ON*

3.3V power rail

3.3V switched power rail

5V always on power rail

5V power rail

5V switched power rail

12V always on power rail

12V switched power rail

RTC power

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

S1 S3 S5

N/A N/A N/A

N/AN/AN/A
ON OFF
ON OFF

ON
ON
ON
ON
ON
ON ON

ON
ON
ON
ON

OFF
ON
ON
ON
OFF

ON
OFF
ON
OFF
ON

OFF

OFF

OFF

OFF

OFF

OFF

ON*

OFF

OFF

ON*

OFF

ON

REV 0.1

Date Page Description

0201 10 R229 change 225 to 255
0204 31 Add R564 @2.2K on pin 3 of MicPhone Jack

42 Modify PU10 pin 11 error

REV 0.2

External PCI Devices

Device IDSEL# REQ#/GNT# Interrupts

CardBus

LAN

Mini-PCI

AD20

AD17

AD18

2

PIRQA/PIRQB

3 PIRQB

1/4

PIRQC/PIRQD

3 3

EC SM Bus1 address

Device

Smart Battery
EEPROM(24C16/02)

(24C04)

Address Address

0001 011X b
1010 000X b
1011 000Xb

EC SM Bus2 address

Device

MAX1617MEE
Smart Battery
Docking
DOT Board

1001 110X b
0001 011X b
0011 011X b
XXXX XXXXb

ICH3-M SM Bus address

Device

4 4

Clock Generator ( ICS9238-50)
SDRAM Select ( 74HC4052 )
CPU Voltage VID select ( F3565 )

Address

1101 0000
1010 0000
0110 111Xb

Compal Electronics, Ltd.

Title

Notes & PIR

Size Document Number Rev
Custom

LA-1441

C

D

Date: Sheet of

3 43Wednesday, March 06, 2002

E

0.2

檔

A

1 1

AF23

AD23

B11

A10
A13

C12
C10

A15
A14
B13
A12

AA3

W2

AB3
C14
AF4

C22

AA2

K1

J1
G2
K3

J2
H3
G1
A3

J3
H1
D3
F3
G3
C2
B5

C6
B9
B7
C8
A8

B3
A9

C3

A6

R1
L3
T1
U1
L1
T4

P3

A7
C4

R2
L2
V3

U2
T3

U9A

A#3
A#4
A#5
A#6
A#7
A#8
A#9
A#10
A#11
A#12
A#13
A#14
A#15
A#16
A#17
A#18
A#19
A#20
A#21
A#22
A#23
A#24
A#25
A#26
A#27
A#28
A#29
A#30
A#31
A#32
A#33
A#34
A#35

REQ#0
REQ#1
REQ#2
REQ#3
REQ#4
RP#
ADS#

AERR#
AP#0
AP#1
BERR#
BINIT#
IERR#

BREQ0#
NC
NC
NC
BPRI#
BNR#
LOCK#

HIT#
HITM#
DEFER#

TUALATIN

H_A#[3..31]<8>

2 2

H_REQ#[0..4]<8>

H_ADS#<8>

3 3

H_BPRI#<8>

H_BNR#<8>

H_LOCK#<8>

H_HIT#<8>

H_HITM#<8>

H_DEFER#<8>

H_A#[3..31]

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_REQ#[0..4] H_D#33

+1.5VS

R331 1.5K

1 2

R87 10

1 2

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

+VCC_H_CORE

D22

F22

VCC_0

VCC_1

Request

Interface

Arbitration

B

E21

H22

G21

K22

VCC_2

VCC_3

VCC_4

Address

Lines

Signals

Error

Signals

Snoop

Signals

VSS_0

VSS_1

VSS_2

E16R4E25

G25

C

J21

M22

L21

P22

N21

T22

R21

V22

U21

Y22

W21

AB22

AA21

AC21

D20

F20

E19

AB20

AA19

AC19

D18

F18

E17

AB18

AA17

AC17

D16

F16

E15

AB16

AA15

AC15

D14

F14

E13

AB14

AA13

AC13

D12

F12

E11

AB12

AA11

AC11

D10

F10E9AB10

AA9

AC9D8F8E7AB8

AA7

VCC_5

VCC_6

VCC_7

VCC_8

VCC_9

VCC_10

VCC_11

VCC_12

VCC_13

VCC_14

VCC_15

VCC_16

VCC_17

VCC_18

VCC_19

VCC_20

VCC_21

VCC_22

VCC_23

VCC_24

VCC_25

VCC_26

VCC_27

VCC_28

VCC_29

VCC_30

VCC_31

VCC_32

VCC_33

VCC_34

VCC_35

VCC_36

VCC_37

VCC_38

VCC_39

VCC_40

VCC_41

VCC_42

VCC_43

VCC_44

VCC_45

VCC_46

VCC_47

VCC_48

VCC_49

VCC_50

VCC_51

VCC_52

VCC_53

VCC_54

VCC_55

VCC_56

VCC_57

VCC_58

VCC_59

VCC_61

VCC

Mobile

Tualatin

VSS VCC

VSS_3

VSS_4

VSS_5

VSS_6

VSS_7

VSS_8

VSS_9

VSS_10

VSS_11

VSS_12

VSS_13

VSS_14

VSS_15

VSS_16

VSS_17

VSS_18

VSS_19

VSS_20

VSS_21

VSS_22

VSS_23

VSS_24

VSS_25

VSS_26

VSS_27

VSS_28

VSS_29

VSS_30

VSS_31

VSS_32

VSS_33

VSS_34

VSS_35

VSS_36

VSS_37

VSS_38

VSS_39

VSS_40

VSS_41

VSS_42

VSS_43

VSS_44

VSS_45

VSS_46

VSS_47

VSS_48

VSS_49

VSS_50

VSS_51

VSS_52

VSS_53

VSS_54

VSS_55

VSS_56

VSS_57

J25

L25

N25

R25

U25

W25

AA25

AC25

AF25

AE26

C23

F23

H23

K23

M23

P23

T23

V23

Y23

AB23

AE23

B22

D21

F21

E22

H21

G22

K21

J22

M21

L22

P21

N22

T21

R22

V21

U22

Y21

W22

AB21

AA22

AC22

AE21

B20

D19

AB19

AA20

AC20

AE19

B18

D17

F17

E18

AB17

D

AC7D6F6E5H6G5K6J5N5T6V6

VCC_62

VCC_63

VCC_64

VCC_65

VCC_66

VCC_67

VCC_68

VCC_69

VCC_70

Data

Signals

VCC_80

VCC_79

VCC_78

VCC_77

VCC_76

VCC_75

VCC_74

VCC_73

U5Y6W5

AB6

AA5

AC5M6P6

E

H_D#[0..63]

H_D#0

A16

VCC_71

VCC_72

D#0

H_D#1

B17

D#1

H_D#2

A17

D#2

H_D#3

D23

D#3

H_D#4

B19

D#4

H_D#5

C20

D#5

H_D#6

C16

D#6

H_D#7

A20

D#7

H_D#8

A22

D#8

H_D#9

A19

D#9

H_D#10

A23

D#10
D#11
D#12
D#13
D#14
D#15
D#16
D#17
D#18
D#19
D#20
D#21
D#22
D#23
D#24
D#25
D#26
D#27
D#28
D#29
D#30
D#31
D#32
D#33
D#34
D#35
D#36
D#37
D#38
D#39
D#40
D#41
D#42
D#43
D#44
D#45
D#46
D#47
D#48
D#49
D#50
D#51
D#52
D#53
D#54
D#55
D#56
D#57
D#58
D#59
D#60
D#61
D#62
D#63

A24
C18
D24
B24
A18
E23
B21
B23
E26
C24
F24
D25
E24
B25
G24
H24
F26
L24
H25
C26
K24
G26
K25
J24
K26
F25
N26
J26
M24
U26
P25
L26
R24
R26
M25
V25
T24
M26
P24
AA26
T26
U24
Y25
W26
V26
AB25
T25
Y24
W24
Y26
AB24
AA24
V24

H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32

H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_D#[0..63] <8>

+VCC_H_CORE

4 4

Compal Electronics, Ltd.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE

A

B

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

D

Mobile Tualatin Micro-FCPGA

Size Document Number Rev
Custom

LA-1441

Date: Sheet of

4 43Wednesday, March 06, 2002

E

0.2

檔

A

B

C

D

E

+VTT

+1.8VS

+1.5VS

+1.5VS

12

1 1

2 2

3 3

4 4

Place H_RESET#
R3<0.1" from U1

H_FERR#<17>

H_PWRGD<17>

H_RESET#<8>

H_PICD0<17>
H_PICD1<17>

C70

2200PF

12

+5VALW

R61

56.2_1%

R53 @0
1 2
1 2

R64 @0

1 2

A

12

R325

1.5K

+1.5VS

R62
150

H_THERMDA
H_THERMDC

R80

1K

R335

12

+VS_CMOSREF

C40
.1UF

1 2

12

12

R336

3K

1.5K

+1.5VS

12

R55
150

CLK_CPU_APIC<12>

PM_CPUPERF#<17,19>

1 2

U8

1

NC

2

VCC
DXP

SMBCLK
DXN
NC

SMBDATA

ADD1

ALERT
GND
GND NC

MAX6654

STBY

ADD0

3
4
5
6
7
8 9

Thermal Sensor

H_IGNNE#<17>

H_STPCLK#<17>

H_DPSLP#<17,43>

+1.5VS

R44

200

NC

NC

H_TRDY#<8>

H_A20M#<17>

H_DBSY#<8>

H_DRDY#<8>

H_BSEL0<10,12>
H_BSEL1<12>

H_RS#0<8>
H_RS#1<8>
H_RS#2<8>

H_SMI#<17>

H_INTR<17>

H_NMI<17>

H_INIT#<17>

C39

@10PF

16
15
14
13
12
11
10

1 2

@33_0402

R482 1.5K

1 2

1 2

R517 200

1 2

R68 56.2_1%

Note :
GHI# Pull-Up internally

+5VALW

12

R50
1K

+5VALW

H_A20M#

H_IGNNE#

H_INTR
H_NMI

H_THERMDA
H_THERMDC

1 2

R280

110_1%

R41

ITP_TRST#

12

R49
10K

AC3
AF6
AF5
AD9
AD3
AB4
AE4

AF8
AD15
AE14

AE6

B15

AF13
AF14

AE12
AF10
AF16

AD19
AD17
AF20

AF22
AE20
AD22
AD21

AD10

AD7
AD11

AF7
AF15
AF19
AE22

AF12

AD5
AE16

B

AA18

AC18

AE17

B16

D15

F15

AB15

AA16

AC16

AE15

B14

D13

F13

E14

AB13

AA14

AC14

AE13

B12

D11

F11

E12

U9B

VSS_58

VSS_59

VSS_60

VSS_61

VSS_62

VSS_63

VSS_64

VSS_65

VSS_66

VSS_67

VSS_68

VSS_69

VSS_70

VSS_71

VSS_72

Y3

RS#0

V1

RS#1

U3

RS#2

M5

Request

RSP#

W1

Signals GND

TRDY#

A20M#
FERR#
FLUSH#
IGNNE#
SMI#
PWRGOOD
STPCLK#

Compatibility

DPSLP#
INTR/LINT0
NMI/LINT1
INIT#
RESET#

W3

DBSY#

Y1

DRDY#

THERMDA
THERMDC

SELFSB0
SELFSB1
EDGECTRLP

PICD0

L5

+VTT

PICD1
PICCLK

RP2#
RP3#
BPM0#
BPM1#

TCK
TDI
TDO
TMS
TRST#
PREQ#
PRDY#

CMOSREF_1
CMOSREF_0
RTTIMPDEP

GHI#

VCCT_1

A26

G23

APIC

Debug
Break

Point

Test

Access

PORT
( ITP )

VCCT_3

VCCT_2

J23

L23

VCCT_4

N23

VCCT_8

VCCT_7

VCCT_6

VCCT_5

R23

U23

W23

AA23

EC_SMC2 <32,40>

VSS_73

VCCT_10

VCCT_11

VCCT_12

VCCT_13

VCCT_14

VCCT_15

VCCT_9

C21

C19

AD20

C17

AD18

C15

AB11

VSS_74

VSS_75

VSS_76

VSS_77

VSS_78

VSS_79

VSS_80

VCCT VID

VCCT_16

VCCT_17

VCCT_18

VCCT_19

VCCT_20

VCCT_21

VCCT_22

C13

AD14

C11

AD12C9C7

AD8C5AD6

From 87591

EC_SMD2 <32,40>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

AA12

AC12

AE11

B10D9F9

VSS_81

VSS_82

VSS_83

VSS_84

VSS_85

VCCT_23

VCCT_24

VCCT_25

VCCT_26

VCCT_27

AC23

AA4E4G4J4L4

C

E10

AB9

AA10

AC10

AE9B8D7F7E8

AB7

VSS_86

VSS_87

VSS_88

VSS_89

VSS_90

VSS_91

VSS_92

VSS_93

VSS_94

VSS_95

Mobile

Tualatin

VCCT_28

VCCT_29

VCCT_30

VCCT_31

VCCT_32

VCCT_33

VCCT_34

VCCT_35

VCCT_36

VCCT_37

AC4V4AE3

AF2

AF1

AE18D5E6

AA8

AC8

AE7B6F5H5G6K5J6N6L6T5R6V5U6Y5W6

VSS_96

VSS_97

VSS_98

VSS_99

VSS_100

VSS_101

VSS_102

VSS_103

VSS_104

VSS_105

VSS_106

VCCT_38

VID0

VID1

VID2

VID3

VID4

VSS

AB1

AC2

AE2

AF3R3B26M4AF26C1AF17

AB5

VSS_107

VSS_108

VSS_109

VSS_110

VSS_111

VSS_112

VSS_113

VSS

VSSNCNC

NC

N4

CPU_VR_VID4 <7>
CPU_VR_VID3 <7>
CPU_VR_VID2 <7>
CPU_VR_VID1 <7>
CPU_VR_VID0 <7>

D

AA6

AC6

AE5B4D4F4H4K4M3U4W4B2D2F2H2

VSS_114

VSS_115

VSS_116

VSS_117

VSS_118

VSS_119

VSS_120

VSS_121

VSS_122

VSS_136

VSS_137

VSS_138

VSS_139

VSS_140

VSS_141

VSS_142

AD2

AE1

A25

C25

E20

F19

+3VS

12

R100
10K

12

C105
.1UF

VSS_123

VSS_124

VSS_125

VSS_126

VSS_127

VSS_128

VSS_129

AE24

DEP#0

AD25

DEP#1

AE25

DEP#2

AC24

DEP#3

AF24

DEP#4

AD26

DEP#5

Data

Signals

VTT Ref

Analog

NCHCTRLP

VTTPWRGOOD

VSS_131

VSS_132

VSS_133

VSS_134

VSS_135

+3V

147

U36F

Title

Size Document Number Rev
Custom

Date: Sheet of

AC26

DEP#6

AD24

DEP#7

AF21

VREF_1

AB26

VREF_2

H26

VREF_3

A21

VREF_4

AF9

VREF_5

A4

VREF_6

N1

VREF_7

AA1

VREF_8

Y4

TESTLO

R5

VCC

N3

PLL1

N2

PLL2

P1

NC

P5

NC

E1

NC

F1

NC

AC1

CLK0

AD1

CLK0#

M1

TESTLO

AF18

NC

AD16
AF11

TESTHI

AE8

NC

N24

NC

AE10

NC

E2

TESTHI

P4

NC

AD4

NC_1

A5

NC_2

D1

NC_3

AD13

NC_4

B1

NC_5

P26

NC_6

A11

NC_7

E3

D26

NC

VSS_130

TUALATIN

K2M2P2T2V2Y2AB2

1213

74LVC14

Compal Electronics, Ltd.

Mobile Tualatin Micro-FCPGA

LA-1441

TESTHI1
TESTHI2

+V_AGTLREF

TESTLO1

+

CLK_HCLK
CLK_HCLK#
TESTLO2

TESTHI1

TESTHI2

CPUVTT_PWRGD

2

+VCC_H_CORE

C520
33UF_16V_D2

R76 14_1%

1 2

+VTT

12

R99
10K

13

VTT_PWRGD# <12,32>VTT_PWRGD<44>

E

RP23
1 8
2 7
3 6
4 5

8P4R_1K

1 2

L30 4.7UH

CLK_HCLK <12>
CLK_HCLK# <12>

CPUVTT_PWRGD

Q6

2N7002

5 43Wednesday, March 06, 2002

+VTT

TESTLO1
TESTLO2

+VTT

+VTT

0.2

檔

A B C

D

E

Layout note :

Place close to CPU, Use 2~3 vias per PAD.

1 1

Place .47uF caps underneath balls on solder side.
Place 10uF caps on the peripheral near balls.
Use 2~3 vias per PAD.

Layout note :

Place close to CPU,
Use 2 vias per PAD.

+VCC_H_CORE

12

12

12

12

12

12

12

12

12

12

12

C388

C389

C391

C392

C393

C394

C395

C396

C397

.47UF

.47UF

.47UF

.47UF

.47UF

.47UF

.47UF

.47UF

+VCC_H_CORE

12

12

12

12

12

12

12

12

C434

C425

C411

C433

C424

C421

.47UF

.47UF

.47UF

.47UF

12

C448
10UF_10V_1206

12

C30
10UF_10V_1206

12

C519

+

150UF_6.3V_D2

.47UF

2 2

+VCC_H_CORE

12

C450
10UF_10V_1206

+VCC_H_CORE

12

C445
10UF_10V_1206

3 3

+VCC_H_CORE

12

C536

+

150UF_6.3V_D2

+VCC_H_CORE

12

C449
10UF_10V_1206

12

C117
10UF_10V_1206

12

C537

+

150UF_6.3V_D2

.47UF

12

C447
10UF_10V_1206

12

C38
10UF_10V_1206

12

C549

+

150UF_6.3V_D2

.47UF

C525

C432

.47UF

12

C446
10UF_10V_1206

12

C33
10UF_10V_1206

12

C538

+

150UF_6.3V_D2

12

.47UF

.47UF

C409

C398

.47UF

12

C420

.47UF

12

C390

C412

.47UF

.47UF

12

12

C408

C431

.47UF

.47UF

+VTT

12

+

+VTT

12

1UF_10V_0603

C45
220UF_4V_D2

1UF_10V_0603

12

C32

C34

12

C513

+

220UF_4V_D2

1UF_10V_0603

12

C37

1UF_10V_0603

12

C41

1UF_10V_0603

1UF_10V_0603

12

C43

12

C48

12

C59

1UF_10V_0603

1UF_10V_0603

12

C67

12

C72

1UF_10V_0603

12

C79
1UF_10V_0603

12

C310

+

150UF_6.3V_D2

4 4

12

C309

+

150UF_6.3V_D2

12

C308

+

150UF_6.3V_D2

12

C314

+

150UF_6.3V_D2

12

C313

+

150UF_6.3V_D2

12

C297

+

150UF_6.3V_D2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

D

Compal Electronics, Ltd.

Title

Almador-M GMCH

Size Document Number Rev
Custom

LA-1441

Date: Sheet of

6 43Wednesday, March 06, 2002

E

0.2

檔

A

B

C

D

E

Tualatin

D4 D3 D2 D1 D0 CPU_Core(V) QS( MP)

CPU_VID4
CPU_VID3
CPU_VID2
CPU_VID1
CPU_VID0

1 1

CPU Voltege ID

Default for Resistors Should
be +VCC_CPU = 0.7V, for
Deeper Sleep Only.

SMB_CLK<12,14,17>

SMB_DATA<12,14,17>

CPU_VR_VID0<5>
CPU_VR_VID1<5>

From Tualatin CPU

2 2

PM_GMUXSEL = 1 : for Performance mode

PM_DPRSLPVR = 1: for Deeper Sleep mode

3 3

SpeedStep function Note for SMT

CPU_VR_VID2<5>
CPU_VR_VID3<5>
CPU_VR_VID4<5>

PM_DPRSLPVR<17,43>

PM_GMUXSEL<17,43>

1 2

R173

@10K

+3VS

0 : for CPU default power

0 : for Performance mode

R321
@10K

182736

12

1
2

U49
NC7SZ02

45

RP30
@8P4R_10K

+3V

1 2

3 5

.1UF

+3V

C647

12

R172
@100K

4

1
1

Override#

1

Address 0110 111X

U17

1

SCL

2

ASEL

SDA

3

Override#

4

I_0

5

MUX_SEL

I_1

6

I_2

7

I_3

8

I_4

9

A/B#

10

GND

FM3565

MUX_SEL

MUX_SEL

1
0

0

VCC

+3V

C213

1 2

.1UF

R460 0

20
19

1 2
1 2

18

WP

NC

Y_0
Y_1
Y_2
Y_3
Y_4

A/B#

17
16
15
14
13
12
11

X
0

1

R461 0

CPU_VID0 <43>
CPU_VID1 <43>
CPU_VID2 <43>
CPU_VID3 <43>
CPU_VID4 <43>

MUX_outputs Mode
MUX_inputs

From
Non-volatile
register(SOPRB)
From
Non-volatile
register(SOPRA)

Battery

Performance

Deeper sleep

Support SpeedStep :

Stuffed : U17, U49, R460, R461
Not Stuffed : RP30, R321

-------------------------------------------------------­0 0 1 1 1 1.40V (Performance)
0 1 1 0 0 1.15V (Battery)
1 0 1 0 1 0.85V (Deeper Sleep)

+3V

System Memory Reference

12

R302

249_1%

49.9_1%

301_1%

249.9_1%

Place capacitor close to GMCH.

12

12

R297

R308

+1.8VS

12

12

C467
.1UF

HUB Interface Reference

Layout note :

1. Place R308 and R296 in middle of Bus.

2. Place capacitors near GMCH.

12

C453

R296

.1UF

301_1%

+V_SMREF

+VS_HUBREF

+VTT

12

12

+1.5VS

12

12

+VAGP_BRDREF

GTL Reference Voltage

R303

Layout note :

1K_1%

1. Place R303 and R322 between and GMCH and CPU.

2. Place decoupling caps near CPU.(Within 500mils)

R322
2K_1%

12

C514
.1UF

12

C35
.1UF

12

C27
.1UF

12

C71
.1UF

CMOS Reference Voltage

R288

Layout note :

1K_1%

1. Place R288 and R291 between and GMCH and CPU.

2. Place decoupling caps near CPU.

12

R291
2K_1%

Place Reference Circuit near GMCH

C439
.1UF

+1.5VS

12

12

12

C440
.1UF

R376
1K_1%

R370
1K_1%

C578

1 2

C555

1 2

470PF

470PF

+V_AGTLREF

+VS_CMOSREF

12

R373

82.5_1%

12

R365

82.5_1%

Without Support SpeedStep :

R93

301_1%

R94

301_1%

+1.8VS

HUB Interface VSwing Voltage

12

1. Place R93 and R94 in middle of Bus.

12

C97
.1UF

+VS_HUBVSWING

12

D

Stuffed : RP30, R321
Not Stuffed : U17, U49, R460, R461

4 4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE

A

B

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

+1.8VS

12

R275

576_1%

1. Place R275 and R274 near GMCH.

12

R274

2K_1%

Compal Electronics, Ltd.

Title

CPU VID & All Reference Voltage

Size Document Number Rev
Custom

LA-1441

Date: Sheet of

+VS_RIMMREF

7 43Wednesday, March 06, 2002

E

0.2

檔

A B C

M12

M13

M17

M18

N12

N13

N14

N15

N16

N17

N18

P13

P14

P15

P16

P17

R13

R14

R15

R16

R17

T13

T14

T15

T16

T17

U12

U13

U14

U15

U16

U17

U18

V12

V13

V17

V18

1 1

2 2

3 3

4 4

H_D#[0..63]

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

HUB_PD[0..10]<17>

HUB_PSTRB<17>

HUB_PSTRB#<17>

U7A

U4

H_D#0

P1

H_D#1

W6

H_D#2

U2

H_D#3

U6

H_D#4

R1

H_D#5

N3

H_D#6

W5

H_D#7

V4

H_D#8

P3

H_D#9

R3

H_D#10

U1

H_D#11

V6

H_D#12

W4

H_D#13

T3

H_D#14

P2

H_D#15

V3

H_D#16

R2

H_D#17

T1

H_D#18

W3

H_D#19

U3

H_D#20

Y4

H_D#21

AA3

H_D#22

W1

H_D#23

V1

H_D#24

Y1

H_D#25

Y6

H_D#26

AD3

H_D#27

AB4

H_D#28

AB5

H_D#29

V2

H_D#30

Y3

H_D#31

Y2

H_D#32

AA4

H_D#33

AA1

H_D#34

AA6

H_D#35

AB1

H_D#36

AC4

H_D#37

AA2

H_D#38

AB3

H_D#39

AD2

H_D#40

AD1

H_D#41

AC2

H_D#42

AB6

H_D#43

AC6

H_D#44

AC1

H_D#45

AF3

H_D#46

AD4

H_D#47

AD6

H_D#48

AC3

H_D#49

AH3

H_D#50

AE5

H_D#51

AE3

H_D#52

AG2

H_D#53

AF4

H_D#54

AF2

H_D#55

AJ3

H_D#56

AE4

H_D#57

AG1

H_D#58

AE1

H_D#59

AG4

H_D#60

AH4

H_D#61

AG3

H_D#62

AF1

H_D#63

ALMADOR-M

+VS_HUBREF

12

.01UF

C476

VSS0

VSS1

VSS2

VSS3

VSS4

Host

Interface

HUB_PD5

HUB_PD4

HUB_PD3

HUB_PD2

HUB_PD1

HUB_PD0

G26

H28

H29

H27

F29

F27

HUB_PD5

HUB_PD4

HUB_PD3

HUB_PD2

HUB_PD1

HUB_PD0

R246 54.9_1%
R92 27.4_1%

1 2

R83 54.9_1%

1 2

VSS5

VSS6

VSS7

VSS8

VSS9

VSS11

VSS10

VSS18

VSS17

VSS16

VSS15

VSS14

VSS13

VSS12

VSS25

VSS24

VSS23

VSS22

VSS21

VSS20

VSS19

VSS32

VSS31

VSS30

VSS29

VSS28

VSS27

VSS26

VSS

Almador-M
GMCH

A3

AGP_RCOMP/DVOBC_RCOMP

RESET#

H_GTLREF1

H_GTLREF0

AB24

AA7J7C2

H_GTLRCOMP

12

C469
.1UF

R78 54.9_1%

12

C470
.1UF

12

SM_RCOMP

HUB_RCOMP

DVO_RCOMP

HUB_REF

AC22F6J23

+VAGP_CRDREF

AGP_REF

J25

K24

C

HUB_PSTRB#

HUB_PD10

HUB_PSTRB

HUB_PD9

HUB_PD8

HUB_PD7

HUB_PD6

E29

E28

G25

G27

H26

G29

H24

F28

HUB_PD10

HUB_PD9

HUB_PD8

HUB_PD6

HUB_PD7

12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

VSSPCMOS_LM0

VSS

VSS

AB23

AC23

AH19

1 2

R91 80.6_1%

+V_AGTLREF

C471
.1UF

12

AJ5D2AC5Y5U5P5L5H5AH2

VSS36

VSS35

VSS34

VSS33

VSSPCMOS_LM1

VSSPCMOS_LM2

VSSP_HUB0

AH20

AF5

G28

H25

VSS_H5

VSS_H4

VSS_H3

VSS_H2

VSS_H1

VSS_H0

VSSP_HUB1

VSSP_IO0

VSSP_IO1

VSSP_IO2

AC26

AD22

AE28

PCIRST# <15,17,19,20,21,22,23,24,25,28,29,34>

10 mils wide,length <=500 mils.

VSS_H7

VSS_H6

VSSP_DVO0

AH24

AE2

AB2W2T2N2K2G2AC7

VSS_H9

VSS_H8

VSS_H10

VSSP_DVO1

VSSP_DVO2

AF25

AF27

D

VSS_H11

VSS_H12

VSS_H13

Interface

VSSA_DAC

AH26G8AD7

D

VSS_H14

Host

VSS_H15

VSS_H16

VSSA_CPLL

VSSA_HPLL

E

H_A#[3..31]

H_A#3

H2

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8

H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_CPURST#

H_ADS#
H_BNR#

H_BPRI#

H_DBSY#

H_DEFER#

H_DRDY#

H_HIT#

H_HITM#

H_LOCK#

H_TRDY#

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#0
H_RS#1
H_RS#2

CLK_HT

CLK_HT#

CLK_DREF

CLK_GBIN

CLK_GBOUT

H_A#4

E3

H_A#5

G3

H_A#6

N4

H_A#7

M6

H_A#8

F1

H_A#9

F2

H_A#10

J3

H_A#11

F3

H_A#12

P6

H_A#13

G1

H_A#14

N5

H_A#15

H1

H_A#16

P4

H_A#17

T4

H_A#18

M2

H_A#19

J2

H_A#20

L2

H_A#21

R4

H_A#22

K1

H_A#23

L3

H_A#24

L1

H_A#25

J1

H_A#26

N1

H_A#27

T5

H_A#28

H3

H_A#29

M3

H_A#30

M1

H_A#31

K3

1 2

R290 @0

R6
C1
E1
L4
G5
J4
F4
D3
D1
J6
G4

H_REQ#0

K6

H_REQ#1

M4

H_REQ#2

K5

H_REQ#3

K4

H_REQ#4

L6

H_RS#0

H6

H_RS#1

H4

H_RS#2

G6

AJ4
AH5

AC19
AG26
AD24

R242

@33_0402

1 2

1 2

C322

@10PF

Compal Electronics, Ltd.

Title

Almador-M GMCH

Size Document Number Rev
Custom

LA-1441

Date: Sheet of

1 2

R26047

R276
@33_0402

C381
@10PF

Close to Ball R6.

H_REQ#[0..4]

H_RS#[0..2]

.01UF
C373

1 2

CLK_GHT <12>
CLK_GHT# <12>

R158
240K

Closely to C.G

E

H_A#[3..31] <4>H_D#[0..63]<4>

H_RESETX#
H_RESET# <5>
H_ADS# <4>
H_BNR# <4>
H_BPRI# <4>
H_DBSY# <5>
H_DEFER# <4>
H_DRDY# <5>
H_HIT# <4>
H_HITM# <4>
H_LOCK# <4>
H_TRDY# <5>
H_REQ#[0..4] <4>

H_RS#[0..2] <5>

CLK_DREF <12>
CLK_GBIN <12>
CLK_GBOUT <12>

8 43Wednesday, March 06, 2002

0.2

檔

A

AD8

AD9

AD10

AJ21

AE8

AE9

AE10

AE11

AE12

AE13

AE17

AE19

AH21

AF8

AF9

AF10

AF11

AF12

VSS_LM

VSS_LM

VSSP_SM14

VSSP_SM15

E22

E25G9G21E4D28

VSS_LM

VSSP_SM16

+VTT

AF13

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSSP_SM17

VSSP_SM18

VSSP_SM19

U7B

SM_DQ0
SM_DQ1
SM_DQ2

1 1

SM_DQ3
SM_DQ4
SM_DQ5
SM_DQ6
SM_DQ7
SM_DQ8
SM_DQ9
SM_DQ10
SM_DQ11
SM_DQ12
SM_DQ13
SM_DQ14
SM_DQ15
SM_DQ16
SM_DQ17
SM_DQ18
SM_DQ19
SM_DQ20
SM_DQ21
SM_DQ22
SM_DQ23
SM_DQ24
SM_DQ25
SM_DQ26
SM_DQ27
SM_DQ28
SM_DQ29
SM_DQ30

2 2

SM_DQ31
SM_DQ32
SM_DQ33
SM_DQ34
SM_DQ35
SM_DQ36
SM_DQ37
SM_DQ38
SM_DQ39
SM_DQ40
SM_DQ41
SM_DQ42
SM_DQ43
SM_DQ44
SM_DQ45
SM_DQ46
SM_DQ47
SM_DQ48
SM_DQ49
SM_DQ50
SM_DQ51
SM_DQ52
SM_DQ53
SM_DQ54
SM_DQ55
SM_DQ56
SM_DQ57
SM_DQ58
SM_DQ59

3 3

SM_DQ60
SM_DQ61
SM_DQ62
SM_DQ63

SM_DQ[0..63]

4 4

D29

SM_DQ0

C29

SM_DQ1

D27

SM_DQ2

C27

SM_DQ3

A27

SM_DQ4

B26

SM_DQ5

E24

SM_DQ6

C25

SM_DQ7

E23

SM_DQ8

B25

SM_DQ9

C23

SM_DQ10

F22

SM_DQ11

B23

SM_DQ12

C22

SM_DQ13

E21

SM_DQ14

B22

SM_DQ15

C12

SM_DQ16

D10

SM_DQ17

C11

SM_DQ18

A10

SM_DQ19

C10

SM_DQ20

C8

SM_DQ21

A7

SM_DQ22

E9

SM_DQ23

C7

SM_DQ24

E8

SM_DQ25

A5

SM_DQ26

F8

SM_DQ27

C5

SM_DQ28

D6

SM_DQ29

B4

SM_DQ30

C4

SM_DQ31

E27

SM_DQ32

C28

SM_DQ33

B28

SM_DQ34

E26

SM_DQ35

C26

SM_DQ36

D25

SM_DQ37

A26

SM_DQ38

D24

SM_DQ39

F23

SM_DQ40

A25

SM_DQ41

G22

SM_DQ42

D22

SM_DQ43

A23

SM_DQ44

F21

SM_DQ45

D21

SM_DQ46

A22

SM_DQ47

F11

SM_DQ48

A11

SM_DQ49

B11

SM_DQ50

F10

SM_DQ51

B10

SM_DQ52

B8

SM_DQ53

D9

SM_DQ54

B7

SM_DQ55

F9

SM_DQ56

A6

SM_DQ57

C6

SM_DQ58

D7

SM_DQ59

B5

SM_DQ60

E6

SM_DQ61

A4

SM_DQ62

D4

SM_DQ63

ALMADOR-M

SM_DQ[0..63] <14>

VSS_LM

SDRAM
System
Memory

VSSP_SM0

VSSP_SM1

VSSP_SM2

B3B6B9

B12

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS Power

VSSP_SM3

VSSP_SM4

VSSP_SM5

VSSP_SM6

VSSP_SM7

VSSP_SM8

VSSP_SM9

VSSP_SM10

VSSP_SM11

VSSP_SM12

VSSP_SM13

B15

B18

B21

B24

B27E7E10

E13

E16

E19

B

AF14

AF15

AF16

AF17

AF18

AF19

AF20

AG7

AG15

AG16

AG21

AH6

AH8

AH9

AH11

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSS

Almador-M
GMCH

A3

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

H7

H23K7K23L7N6T6W7Y7AB7

M24

P24

T24

V24

C

VSSA_DPLL0 <10>
VSSA_DPLL1 <10>

AH12

AH14

AH17

AH18

K28

N28

T28

W28

AB28

L25

P25

U25

Y25

AE20

G24

SM_D_MA0

VSS_LM

VSS_LM

VSS_LM

VSS_LM

VSSP_AGP0

VSSP_AGP1

VSSP_AGP2

VSSP_AGP3

VSSP_AGP4

VSSP_AGP5

VSSP_AGP6

VSSP_AGP7

VSSP_AGP8

VSSA_DPLL0

VSSA_DPLL1

SDRAM
System
Memory

SM_MA0
SM_MA1
SM_MA2
SM_MA3
SM_MA4
SM_MA5
SM_MA6
SM_MA7
SM_MA8

SM_MA9
SM_MA10
SM_MA11
SM_MA12

VCC_SM
VCC_SM

SM_BA0
SM_BA1

SM_DQM0
SM_DQM1
SM_DQM2
SM_DQM3
SM_DQM4
SM_DQM5
SM_DQM6
SM_DQM7

SM_CS#0
SM_CS#1
SM_CS#2
SM_CS#3

VCCQ_SM

SM_CLK0
SM_CLK1
SM_CLK2
SM_CLK3

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

VCC_SM

VSS
VSS

VSS

VSS
VSS

VSS

A20

SM_D_MA1

B20

SM_D_MA2

B19

SM_D_MA3

C19

SM_D_MA4

A18

SM_D_MA5

A19

SM_D_MA6

C17

SM_D_MA7

C18

SM_D_MA8

B17

SM_D_MA9

A17

SM_D_MA10

A16

SM_D_MA11

C15

SM_D_MA12

C14

F20

NC

E20

NC

F12

NC

E11

NC

C21
F19
E12
A12

B16
C16

SM_DQM0

F18

SM_DQM1

D18

SM_DQM2

D13

SM_DQM3

D12

SM_DQM4

E18

SM_DQM5

F17

SM_DQM6

F14

SM_DQM7

F13

SM_CS#0

E17

SM_CS#1

F16

SM_CS#2

D16

SM_CS#3

D15
E15
E14

SM_D_CLK0

A15

SM_D_CLK1

B2

SM_D_CLK2

B14

SM_D_CLK3

A3
A14
C3

SM_CKE0

A13

SM_CKE1

C9

SM_CKE2

C13

SM_CKE3

A9
B13
A8

SM_D_MA[0..12]

XOR layout note:
F20,E20,F12,E11 add
testpoint for
factory

R319 10

1 2

R310 10

1 2

C452 .1UF

1 2

1 2

C512 .1UF

+3V

+3V

D

SM_D_MA[0..12] <13>

+3V

SM_BA0 <14>
SM_BA1 <14>
SM_DQM[0..7] <14>

SM_CS#0 <14>
SM_CS#1 <14>
SM_CS#2 <14>
SM_CS#3 <14>

SM_D_CLK0
SM_D_CLK1
SM_D_CLK2
SM_D_CLK3

SM_CKE0 <14>
SM_CKE1 <14>
SM_CKE2 <14>
SM_CKE3 <14>

R254 0

1 2

R306 0

1 2

*
*

VSSA_DPLL0
VSSA_DPLL1

Layout note :

Place resistors & capacitors near GMCH

R318 10

1 2

R313 10

1 2

R317 10

1 2

R315 10

1 2

12

12

C506
@33PF

C516
@33PF

12

E

C515
@33PF

12

C517
@33PF

SMD_CLK0 <14>
SMD_CLK1 <14>
SMD_CLK2 <14>
SMD_CLK3 <14>

Layout note :

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

SM_VREF0

SM_VREF1

C24

E5

Y23

M14

M15

M16

P12

R12

F24

T12

P18

R18

T18

Line length 0.15 inches +- 50mils

12

C494
.1UF

SM_OCLK

SM_RCLK

A24

12

C493
.1UF

SM_RAS#

SM_CAS#

SM_W E#

C20

D19

A21

SM_OCLK

SM_RCLK

Layout note :

+V_SMREF

Close to Ball E5 and F24

1.Placement TP6 for Almador-M A2 stepping die.

2.The 0.1uF capacitor and connection to +3V
must be implanted for Almador-M A3 stepping
die.

R312 10

1 2

R311 10

1 2

R316 10

1 2

1 2

C507 @22PF

Layout note :

SM_RAS# <14>
SM_CAS# <14>
SM_WE# <14>

near pin C24

A

檔

Compal Electronics, Ltd.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE

B

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

D

Almador-M GMCH

Size Document Number Rev
Custom

LA-1441

Date: Sheet of

9 43Wednesday, March 06, 2002

E

0.2

A

Layout note :

Place close to AE16,
AE15 of GMCH

1 1

AGP_SBA[0..7]<15>

AGP_CBE#[0..3]<15>

AGP_ADSTB0<15>

AGP_ADSTB#0<15>

AGP_ADSTB1<15>

2 2

3 3

4 4

AGP_ADSTB#1<15>

AGP_SBSTB<15>
AGP_SBSTB#<15>
AGP_FRAME#<15>

AGP_IRDY#<15>
AGP_TRDY#<15>
AGP_STOP#<15>

AGP_DEVSEL#<15>

AGP_REQ#<15>

AGP_GNT#<15>

AGP_PAR<15>

AGP_AD[0..31]<15>

AGP_PAR : Strapping option for SW detection of
AGP or DVO device.
0 -> DVO B/C device
1 -> AGP device

+1.5VS

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

AGP_SBA[0..7]

AGP_CBE#[0..3]

AGP_AD[0..31]

AGP_PAR

R272

1 2

@8.2K

A

AGP_ADSTB0
AGP_ADSTB#0
AGP_ADSTB1
AGP_ADSTB#1
AGP_SBSTB
AGP_SBSTB#
AGP_FRAME#
AGP_IRDY#
AGP_TRDY#
AGP_STOP#
AGP_DEVSEL#
AGP_REQ#
AGP_GNT#
AGP_PAR

1 2

R279

330

12

AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7

AGP_CBE#0
AGP_CBE#1
AGP_CBE#2
AGP_CBE#3

AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31

C413
68PF

U7C

AA29

AGP_SBA0/ZV_D8

AA24

AGP_SBA1/ZV_D7

AA25

AGP_SBA2/ZV_D6

Y24

AGP_SBA3/ZV_D5

Y27

AGP_SBA4/ZV_D2

Y26

AGP_SBA5/ZV_D1

W24

AGP_SBA6/ZV_D0

Y28

AGP_SBA7/ZV_HREF

L27

AGP_CBE#0/DVOB_D7

P29

AGP_CBE#1/DVOB_BLANK#

R27

AGP_CBE#2/ZV_VSYNC

T25

AGP_CBE#3/DVOC_D5

L29

AGP_ADSTB0/DVOB_CLK

L28

AGP_ADSTB#0/DVOB_CLK#

U29

AGP_ADSTB1/DVOC_CLK

U28

AGP_ADSTB#1/DVOC_CLK#

AA27

AGP_SBSTB/ZV_D4

AA28

AGP_SBSTB#/ZV_D3

R29

AGP_FRAME#/M_DDC1_DATA

P26

AGP_IRDY#/M_I2C_CLK

P27

AGP_TRDY#/M_DDC1_CLK

N25

AGP_STOP#/M_DDC2_DATA

R28

AGP_DEVSEL#/M_I2C_DATA

AC27

AGP_REQ#/ZV_CLK

AD29

AGP_GNT#/ZV_D15

P28

AGP_PAR/DVO_DETECT

J29

AGP_AD0/DVOB_HSYNC

J28

AGP_AD1/DVOB_VSYNC

K26

AGP_AD2/DVOB_D1

K25

AGP_AD3/DVOB_D0

L26

AGP_AD4/DVOB_D3

J27

AGP_AD5/DVOB_D2

K29

AGP_AD6/DVOB_D5

K27

AGP_AD7/DVOB_D4

M29

AGP_AD8/DVOB_D6

M28

AGP_AD9/DVOB_D9

L24

AGP_AD10/DVOB_D8

M27

AGP_AD11/DVOB_D11

N29

AGP_AD12/DVOB_D10

M25

AGP_AD13/DVOBC_CLKINT#

N26

AGP_AD14/DVOB_FLD/STL

N27

AGP_AD15/M_DDC2_CLK

R25

AGP_AD16/DVOC_VSYNC

R24

AGP_AD17/DVOC_HSYNC

T29

AGP_AD18/DVOC_BLANK#

T27

AGP_AD19/DVOC_D0

T26

AGP_AD20/DVOC_D1

U27

AGP_AD21/DVOC_D2

V27

AGP_AD22/DVOC_D3

V28

AGP_AD23/DVOC_D4

U26

AGP_AD24/DVOC_D7

V29

AGP_AD25/DVOC_D6

W29

AGP_AD26/DVOC_D9

V25

AGP_AD27/DVOC_D8

W26

AGP_AD28/DVOC_D11

W25

AGP_AD29/DVOC_D10

W27

AGP_AD30/DVOBC_INTR#/DPMS_CLK

Y29

AGP_AD31/DVOC_FLD/STL

ALMADOR-M

AGP_PIPE#<15>
AGP_WBF#<15>

AGP_RBF#<15>

AGP_ST[0..2]<15>

B

+VTT

V14

V15

V16

AE16

AE15

AD15

AD16

VDD_LM

VDD_LM

VDD_LM

VDD_LM

VDD_LM

VDD_LM

AGP

Interface

(DVOB/DVOC & ZV port)

AGP_PIPE#/ZV_D10

AGP_WBF#/ZV_D9

AGP_RBF#/ZV_D11

AGP_ST0/ZV_D14

AGP_ST1/ZV_D13

AB26

AB29

AB25

AC28

AC29

AB27

AGP_PIPE#
AGP_WBF#
AGP_RBF#

AGP_ST[0..2]

B

AGP_ST2

AGP_ST0

AGP_ST1

C

+1.5VS

+1.8VS

+3V

AE25

AD23

J24

VDD_LM

VCCP_IO

VCCP_IO

VCCP_HUB

C330 .1UF

C483 .1UF

F26

N24

W23

J26

M26

VCCP_HUB

VCCP_AGP

VCCP_AGP

VCCQ _A GP

VCCQ _A GP

+VTT

+3V

12
12

R26

V26

AA26

L23

AA23

U24

AE6G7G10

G20

AF6

VCCQ _S M

VCCP_AGP

Interface

VCCA_CPLL

VCCA_HPLL

Power

VCCQ _S M

VCCPCM OS _L M

VCCP_AGP

VCCP_AGP

VCCP_AGP

VCCP_AGP

VCCP_AGP

+1.8VS

AE7

AC9

VCCPCM OS _L M

AC8

VCCPCM OS _L M

VCCPCM OS _L M

0_0805

1 2

R277

12

C383
.01UF

+VTT

AF26

AG27F5J5M5R5V5AA5

VCC_H

VCC_H

VCCA_DAC

VCCA_DAC

+1.8VS

12

12

C384
.1UF

C283
@.1UF

+1.5VS

AD5

AG5

E2

AC20

F25

AC21

AF21

VCC_H

VCC_H

VCC_H

VCC_H

VCCP_DVO

VCCP_DVO

VCCA_DPLL0

VCCA_DPLL1

Display

Interface

12

VCC_H

VCC_H

VCC_H

(DVOA port)

Almador-M
GMCH

A3

Local Memory
Interface

Local Memory
Interface

LM_CMD

LM_SCK

LM_SIO

LM_RQ0

LM_RQ1

LM_RQ2

LM_RQ3

LM_RQ4

LM_RQ5

LM_RQ6

AGP_ST2/ZV_D12

AH7

AF7

AJ7

AG11

AJ12

LM_RQ7

AG12

AH13

AG13

AJ13

AG14

AJ14

AJ6

LM_CTM

LM_RCLK

AG6

LM_CTM #

LM_GCLK

LM_RAMREF0

LM_RAMREF1

LM_CFM

LM_CFM #

VCCP_SM

VCCP_SM

VCCP_SM

VCCP_SM

VCCP_SM

VCCP_SM

VCCP_SM

VCCP_SM

VCCQ _S M

VCCQ _S M

VCCP_SM

VCCQ _S M

VCCP_SM

VCC_LM

VCC_LM

VCC_LM

VCC_LM

VCC_LM

VCC_LM

VCC_LM

VCC_LM

AD14

AE14

AH15

AJ15

AJ16

AH16

D5D8D11

D14

D17

D20

D23

D26F7F15

G11

G19

G23

AC10

AC11

AD11

AD12

AD13

AE18

AD17

AD18

R234 10K

1 2

R239 10K

1 2

12

C340
.1UF

C

12

C328
.1UF

**

C282
@.1UF

@220UF_4V_D2

AF24

DAC_VSYNC

DAC_HSYNC

VCCP_DVO

DAC_RED#

DAC_GREEN#

DAC_BLUE#

DAC_RED

DAC_GREEN

DAC_BLUE

IO_DDC1CLK

IO_DDC1DATA

DAC_REFSET

DVO_CLKIN

DVO_BLANK#

DVO_VSYNC
DVO_HSYNC

IO_I2CCLK

IO_I2CDATA

DVO_CLK#

DVO_CLK

DVO_D0
DVO_D1
DVO_D2
DVO_D3
DVO_D4
DVO_D5
DVO_D6
DVO_D7
DVO_D8

DVO_D9
DVO_D10
DVO_D11

IO_DDC2DATA

IO_DDC2CLK

DVO_INTR#
DVO_FIELD

LM_DQA0
LM_DQA1
LM_DQA2
LM_DQA3
LM_DQA4
LM_DQA5
LM_DQA6
LM_DQA7

LM_DQB0
LM_DQB1
LM_DQB2
LM_DQB3
LM_DQB4
LM_DQB5
LM_DQB6
LM_DQB7

AGP_BUSY#

VCC_LM

AD19

+3V

+VS_RIMMREF

C286

D

D

**

@220UF_4V_D2

*

AE29
AD28
AF28
AG28
AH27
AF29
AG29
AH28
AE27
AD27
AJ27

AD20
AD21
AF23
AF22
AD25
AC25
AG24
AJ24

AJ22
AH22
AG22
AJ23
AH23
AG23
AE23
AE24
AJ25
AH25
AG25
AJ26

AD26
AE26
AE21
AE22

AG17
AJ17
AG18
AJ18
AG19
AJ19
AG20
AJ20

AJ11
AH10
AJ10
AG10
AJ9
AG9
AJ8
AG8

AC24

+1.8VS

E

VSSA_DPLL0 <9>
VSSA_DPLL1 <9>

C285

L3 0_0805
1 2
1 2

L4 0_0805

IO_DDC1CLK

IO_DDC1DATA

AGP_BUSY#

12

R301 0
1 2
1 2

R299 0

R269 @2.2K

+1.5VS

R226 2.2K

R240 @2.2K

1 2

R229 255_1%
DVOA_CLKIN

R261 10K
R263 10K

DVOA_D0
DVOA_D1

DVOA_D4
DVOA_D5
DVOA_D6

DVOA_INTR#

DVOA_FIELD

XOR layout note: AE24,AJ25
add testpoint for factory

R251 10K
R250 10K

C354
68PF

Title

Size Document Number Rev
Custom

Date: Sheet of

Strap Name Low High
DVOA_D0 Reserved 133MHz
DVOA_D1 IOQD=2 IOQD=8

+VTT

DVOA_D5 Desktop Mobile

*

DVOA_D6 Dual Ended Term Single Ended Term

**

1 2
1 2

1 2

DAC_VSYNC <16>
DAC_HSYNC <16>
DAC_RED# <16>
DAC_GREEN# <16>
DAC_BLUE# <16>
DAC_RED <16>
DAC_GREEN <16>
DAC_BLUE <16>

VCH_I2CDATA <15>
VCH_I2CCLK <15>

1 2
1 2

TV_OUT_DDC2DATA<15>
TV_OUT_DDC2CLK <15>

1 2
1 2

R257

1 2

@10K

AGP_BUSY# <15,17>

DVOA_D6
DVOA_D5

DVOA_D0

R252 10K

1 2

R262 10K

1 2

R551 0

1 2

R552 0

1 2

+3VS

DVOA_CLKIN
DVOA_INTR#

DVOA_FIELD

+3VS

+3VS

*

1 2

R232@2.2K

R551,R552: No stuff in AGP mode,
Stuff in VCH mode

Compal Electronics, Ltd.

Almador-M GMCH

LA-1441

E

H_BSEL0 <5,12>

+3VS

AGP_DDCCLK <15,16>
AGP_DDCDATA <15,16>

+1.5VS

R259 100K

1 2

R255 100K

1 2

R256 10K

1 2

10 43Wednesday, March 06, 2002

0.2

檔

A B C

D

E

Layout note :

Distribute as close as possible
to GMCH Processor Quadrant .

+VTT

1 1

2 2

3 3

+VTT

+VTT

+

+VTT

+

+VTT

+

+VTT

12

12

12

12

12

12

12

C353
.1UF

12

C437
.1UF

C127
220UF_4V_D2

C80
220UF_4V_D2

C36
220UF_4V_D2

12

C475
.1UF

C327
.1UF

C454
.1UF

C484
.1UF

12

C350
.1UF

12

C466
.1UF

12

12

C405
.1UF

12

12

C410
.1UF

12

12

C380
.1UF

12

C490
.1UF

12

C404
.1UF

C463
.1UF

C401
.1UF

12

C357
.1UF

C474
.1UF

C504
.1UF

C358
.1UF

12

C427
.1UF

12

C403
.1UF

12

C473
.1UF

12

C422
.1UF

12

C402
.1UF

12

12

12

12

C343
.1UF

12

C435
.1UF

12

C418
.1UF

12

C81
.1UF

12

C441
.1UF

12

C414
.1UF

12

12

C344

C387

.1UF

.1UF

12

12

C460

C438

.1UF

.1UF

12

12

C436

C429

.1UF

.1UF

12

12

C74

C28

.1UF

.1UF

12

12

C456

C451

.1UF

.1UF

12

12

C417

C464

.1UF

.1UF

12

C407

C419

.1UF

.1UF

12

12

C459

C462

.1UF

.1UF

12

12

12

C386

C372

.1UF

.1UF

12

12

C88

C31

.1UF

.1UF

12

12

C465

C458

.1UF

.1UF

12

C399

C423

.1UF

.1UF

12

12

C78

C83

.1UF

.1UF

12

12

C468

C472

.1UF

.1UF

Layout note :

Distribute as close as possible
to VCCPCMOS_LM .

+1.8VS

12

C302

+

22UF_16V_1206

12

C363
.1UF

Layout note :

Distribute as close as possible
to GMCH Local Memory Quadrant .

+1.8VS

12

C345
82PF

12

+

22UF_16V_1206

C301

12

Layout note :

Distribute as close as possible
to GMCH AGP/DVO Quadrant .

+1.5VS

12

+

22UF_16V_1206

C287

12

12

C336
.1UF

Layout note :

Distribute as close as possible
to GMCH System Memory Quadrant .

+3V

12

+

22UF_16V_1206

C523

12

12

C477
.1UF

C359
.1UF

C335
.1UF

C482
.1UF

12

C364
.1UF

12

12

C360

C361

.1UF

82PF

12

12

C379

C382
.1UF

82PF

12

12

C481

C503
.1UF

82PF

12

C365
.01UF

12

12

C355

C356

.1UF

.1UF

12

12

C415
C400
.1UF

82PF

12

12

C501
C502
.1UF

82PF

12

+

12

12

C298
68UF_4V_B2

12

C366
.1UF

12

C500
.1UF

12

C406
.1UF

C489
.1UF

C334
.01UF

+

12

C299
68UF_4V_B2

12

C428
82PF

12

C496
82PF

12

12

+

C442
.1UF

C498
.1UF

12

C319
68UF_4V_B2

12

C244
.1UF

12

C495
.1UF

12

C320

+

@68UF_4V_B2

12

C457
82PF

12

C497
82PF

12

C300

+

@68UF_4V_B2

12

C443
.1UF

12

12

12

C480
.1UF

C479
.1UF

C491
.1UF

12

C505
.1UF

Layout note :

+VTT

12

C62

+

220UF_4V_D2

4 4

12

C106

+

220UF_4V_D2

Distribute as close as possible
to IO Quadrant .

+3V

12

C524

+

22UF_16V_1206

12

C499
.1UF

12

C511
.1UF

檔

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

D

Compal Electronics, Ltd.

Title

GMCH-M Decoupling

Size Document Number Rev
Custom

LA-1441

Date: Sheet of

11 43Wednesday, March 06, 2002

E

0.2

A B C

D

E

+3VS

Check Bead Value
should be 19.6K

1 1

+3VS

+3VS

+3VS

12

12

12

R146
10K

H_BSEL1<5>
H_BSEL0<5,10>

2 2

CLK_ICH48<17>

3 3

CLK_DREF<8>

CLK_ICH14<17>
CLK_SIO14<25>

12

R145
@0

12

12

R110
1K

R112
@0

C135
@10PF

12

12

R111
1K

SEL2
SEL1
SEL0

R114
@0

VTT_PWRGD#<5,32>

C148
@10PF

Place Crystal within 500 mils of CK_Titan

C118 5PF

1 2

caps are internal
to CK_TITAN

1 2

C129 5PF

PM_SLP_S1#<17,32>
PM_SLP_S3#<17,32>

PM_STPPCI#<17>

PM_STPCPU#<17>

+3V

SMB_DATA<7,14,17>

SMB_CLK<7,14,17>

+3V

CLK_VCH<15>

R137 220_1%

R141 22

R149 22

R108 33
R109 33

Place caps. near
CK Titan (U5)

R528 0

R529 @0

R116 0
R562 10K

+3VS

D47

RB751V

R138 10K

R157 4.7K

1 2

1 2

R154 4.7K
R151 33

1 2

R151: No stuff in AGP mode
Stuff in VCH mode

1 2

* 221_1%

1 2

* 33

1 2

* 33

1 2
1 2

12

1 2

1 2

1 2
1 2
21

1 2

Y1

14.318MHZ

L6
CHB2012U170

1 2

2

40
55
54

25
34
53

28

43

29
30

33
35

42

39

38

56

U10

XTAL_IN

SEL2
SEL1
SEL0

PWR_DWN#
PCI_STOP#
CPU_STOP#

VTT_PWRGD#

MULT0

SDATA
SCLK

3V66_0/DRCG
3V66_1/VCH_CLK

IREF

48MHZ_USB

48MHZ_DOT

REF

ICS950805

+3V_CLK

181419323746

VDD_REF

GND_REF

491520313641

Width=40 mils

VDD_PCI

VDD_PCI

VDD_3V66

VDD_3V66

66MHZ_OUT2/3V66_4
66MHZ_OUT1/3V66_3
66MHZ_OUT0/3V66_2

GND_3V66

GND_PCI

GND_3V66

GND_PCI

12

+

C115

22UF_16V_1206

50

VDD_CORE

VDD_CPU

VDD_CPU

VDD_48MHZ

GND_COREXTAL_OUT

CPUCLKT2

CPU_CLKC2

CPUCLKT1

CPUCLKC1
CPUCLKT0

CPUCLKC0

66MHZ_IN/3V66_5

PCICLK_F2
PCICLK_F1
PCICLK_F0

PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0

GND_CPU

GND_48MHZ

GND_IREF

47

12

C130
.01UF

26

273
45

44
49

48
52

51
24

23
22
21

7
6
5

18
17
16
13
12
11
10

C152

C133

.01UF

.01UF

12

12

+

C128

C120

22UF_16V_1206

.01UF

R153 33

1 2

R150 33

1 2

R147 33

1 2

R119: Stuff in AGP mode
No stuff in VCH mode

R119 33

1 2

R118 33

1 2

R115 @33

1 2

R143 33

1 2

R144 33

1 2

R140 33

1 2

R136 @33

1 2

R125 @33

1 2

R121 33

1 2

R122 33

1 2

12

12

12

C121
.01UF

L5
CHB2012U170

1 2

CLK_BCLK

CLK_BCLK#
CLK_GCLK

CLK_GCLK#

12

12

C122
.01UF

PCIF1
PCIF0

12

C124

C155

.01UF

.01UF

+3VS

Place all these Block's
Components near CK_Titan(U5)

1 2

R324 33

12

12

R334
475_1%

R34
475_1%

1 2

R329 61.9_1%

R328 61.9_1%

1 2
1 2

R323

1 2

R32 33

1 2

R33 61.9_1%

R31 61.9_1%

1 2

R30 33

1 2

12

C147
@10PF

12

12

C156
.01UF

C149
@10PF

12

C123
.01UF

CLK_HCLK <5>

Place all these Block's
Components near CPU (U1)

33

12

C150
@10PF

CLK_HCLK# <5>
CLK_GHT <8>

CLK_GHT# <8>

CLK_GBOUT <8>

CLK_AGPCONN <15>
CLK_GBIN <8>
CLK_ICHHUB <17>

CLK_ICHPCI <17>

CLK_PCI_CB <23>
CLK_PCI_LAN <21>
CLK_LPC_SIO <25>
CLK_PCI_1394 <22>
CLK_PCI_SD/SM <29>
CLK_LPC_EC <32>
CLK_MINIPCI <28>

Place caps. near
CK_Titan (U5)

Place all these Block's
Components near GMCH (U6)

12

@33_0402

@10PF

C154

R155

Place near CPU

R36 26.7_1%

PCIF1

1 2

SEL2 SEL1 SEL0 CPUCLKC[0..2] CPUCLKT[0..2]

1 0 0 66.67 66.67
1 0 1 100.00 100.00
1 1 0 200.00 200.00
1 1 1 133.33 133.33

4 4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

PCIF0

12

R35

137_1%

D

1 2
R351
@51.1_1%

Title

Size Document Number Rev
Custom

Date: Sheet of

12

R352
0_0603
0 ohm resistor for ICH3 doesn't
need to support APIC function.

Compal Electronics, Ltd.

Almador-M GMCH CLOCK GENERATOR

LA-1441

348_1%

CLK_CPU_APIC <5>
CLK_ICHAPIC <17>

12 43Wednesday, March 06, 2002

E

0.2

檔

A

SM_DQ[0..63]<9,14> MD[0..63] <9,14>

B

C

D

E

SM_DQ1 MD1

1 1

2 2

3 3

SM_DQ3 MD3

SM_DQ18 MD18

SM_DQ20 MD20
SM_DQ21 MD21

SM_DQ23 MD23

SM_DQ24 MD24
SM_DQ26 MD26

SM_DQ28 MD28
SM_DQ29 MD29
SM_DQ30 MD30

MD0SM_DQ0
MD2SM_DQ2

MD4SM_DQ4
MD5SM_DQ5
MD6SM_DQ6
MD7SM_DQ7

MD8SM_DQ8
MD9SM_DQ9
MD10SM_DQ10
MD11SM_DQ11

MD12SM_DQ12
MD13SM_DQ13
MD14SM_DQ14
MD15SM_DQ15

MD16SM_DQ16
MD17SM_DQ17

MD19SM_DQ19

MD22SM_DQ22

MD25SM_DQ25 MD57SM_DQ57
MD27SM_DQ27

SM_DQ38 MD38
SM_DQ39 MD39

SM_DQ40 MD40
SM_DQ41 MD41

SM_DQ44 MD44

SM_DQ56 MD56

SM_DQ59 MD59

SM_DQ60 MD60
SM_DQ61 MD61
SM_DQ62 MD62

MD32SM_DQ32
MD33SM_DQ33
MD34SM_DQ34
MD35SM_DQ35

MD36SM_DQ36
MD37SM_DQ37

MD42SM_DQ42
MD43SM_DQ43

MD45SM_DQ45
MD46SM_DQ46
MD47SM_DQ47

MD48SM_DQ48
MD49SM_DQ49
MD50SM_DQ50
MD51SM_DQ51

MD52SM_DQ52
MD53SM_DQ53
MD54SM_DQ54
MD55SM_DQ55

MD58SM_DQ58

MD63SM_DQ63MD31SM_DQ31

Layout note :

One .1uF cap per power pin .
Place each cap close to SODIMM(DIMM 0) pin .

+3V

12

C192
.1UF

+3V

12

C119

+

22UF_16V_1206

C167

1000PF

12

C168
.1UF

C184

1000PF

12

C164
.1UF

Layout note :

One .1uF cap per power pin .
Place each cap close to SODIMM(DIMM 1) pin .

+3V

12

C212
.1UF

+3V

12

C126

+

22UF_16V_1206

C211

1000PF

12

C205
.1UF

C210

1000PF

12

C206
.1UF

C169

1000PF

C207

1000PF

C199

1000PF

C166

1000PF

12

C196
.1UF

12

C215
.1UF

12

C170
.1UF

12

C222
.1UF

C195

1000PF

C221

1000PF

12

C194
.1UF

12

C220
.1UF

C190

1000PF

C219

1000PF

12

C189
.1UF

12

C218
.1UF

C188

1000PF

C217

1000PF

12

C209
.1UF

12

C160
.1UF

C216

1000PF

C165

1000PF

12

C203

C202

1000PF

.1UF

12

C214

C187

1000PF

.1UF

SM_D_MA[0..12]<9> MAA[0..12] <14>

SM_D_MA0
SM_D_MA1
SM_D_MA2
SM_D_MA3

SM_D_MA4
SM_D_MA5
SM_D_MA6
SM_D_MA7

SM_D_MA8
SM_D_MA9
SM_D_MA10

4 4

SM_D_MA11

SM_D_MA12

A

RP22
1 8
2 7
3 6
4 5

8P4R_10

RP21
1 8
2 7
3 6
4 5

8P4R_10

RP20
1 8
2 7
3 6
4 5

8P4R_10
1 2

R176 10

MAA0
MAA1
MAA2
MAA3

MAA4
MAA5
MAA6
MAA7

MAA8
MAA9
MAA10
MAA11

MAA12

Compal Electronics, Ltd.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE

B

USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

D

SODIMM Damping & Decoupling

Size Document Number Rev
Custom

LA-1441

Date: Sheet of

13 43Wednesday, March 06, 2002

E

0.2

檔

A

SO-DIM 144 PINS
RAM MODULE CONN.

MD0

1 1

MAA[0..12]<13>

MD[0..63]<9>

SM_DQM[0..7]<9>

2 2

3 3

MAA[0..12]

MD[0..63]
SM_DQM[0..7]

SMD_CLK0<9>

SM_RAS#<9>
SM_WE#<9>
SM_CS#0<9>
SM_CS#1<9>

MD1
MD2
MD3

MD4
MD5
MD6
MD7

SM_DQM0
SM_DQM4

MAA0
MAA1
MAA2

MD32
MD33
MD34
MD35

MD36
MD37
MD38
MD39

R174

C204

10PF

22

SM_RAS# SM_CAS#
SM_WE# SM_CKE1
SM_CS#0 MAA12
SM_CS#1

MD16
MD17
MD18
MD19

MD20
MD21
MD22
MD23

MAA6 MAA7
MAA8

MAA9
MAA10 MAA11

SM_DQM2
SM_DQM6

MD48
MD49
MD50
MD51

MD52
MD53
MD54
MD55

SDADIMM0 SCKDIMM0

BANK 0/1

+3V +3V

JP26

1

VSS

3

DQ0

5

DQ1

7

DQ2

9

DQ3

11

VCC

13

DQ4

15

DQ5

17

DQ6

19

DQ7

21

VSS

23

CE0#

25

CE1#

27

VCC

29

A0

31

A1

33

A2

35

VSS

37

DQ8

39

DQ9

41

DQ10

43

DQ11

45

VCC

47

DQ12

49

DQ13

51

DQ14

53

DQ15

55

VSS

57

RESVD/DQ64

59

RESVD/DQ65

61

RFU/CLK0

63

VCC

65

RFU

67

WE#

69

RE0#

71

RE1#

73

OE#/RESVD

75

VSS

77

RESVD/DQ66

79

RESVD/DQ67

81

VCC

83

DQ16

85

DQ17

87

DQ18

89

DQ19

91

VSS

93

DQ20

95

DQ21

97

DQ22

99

DQ23

101

VCC

103

A6

105

A8

107

VSS

109

A9

111

A10

113

VCC

115

CE2#/RESVD

117

CE3#/RESVD

119

VSS

121

DQ24

123

DQ25

125

DQ26

127

DQ27

129

VCC

131

DQ28

133

DQ29

135

DQ30

137

DQ31

139

VSS

141

SDA

143

VCC

SO-DIMM144-STANDRD

DIMM0

4 4

+3V

RP4

SCKDIMM1

1 8

SCKDIMM0

2 7

SDADIMM1

3 6

SDADIMM0

4 5

8P4R_10K

A

B

DQ32
DQ33
DQ34
DQ35

VCC
DQ36
DQ37
DQ38
DQ39

CE4#
CE5#

VCC

DQ40
DQ41
DQ42
DQ43

VCC
DQ44
DQ45
DQ46
DQ47

RESVD/DQ68
RESVD/DQ69

RFU/CKE0

VCC

RFU

RFU/CKE1

RFU

RFU

RFU/CLK1

RESVD/DQ70
RESVD/DQ71

VCC
DQ48
DQ49
DQ50
DQ51

DQ52
DQ53
DQ54
DQ55

VCC

A11/BA0
A12/BA1

A13/A11

VCC

CE6#/RESVD
CE7#/RESVD

DQ56
DQ57
DQ58
DQ59

VCC
DQ60
DQ61
DQ62
DQ63

VCC

B

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
SCL

A3
A4
A5

A7

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144

PROPRIETARY NOTE

C

+3V+3V

C142

+

10UF_10V_1206

MD8
MD9
MD10
MD11

MD12
MD13
MD14
MD15

SM_DQM1
SM_DQM5

MAA3
MAA4
MAA5

MD40
MD41
MD42
MD43

MD44
MD45
MD46
MD47

SM_CKE0

MD24
MD25
MD26
MD27

MD28
MD29
MD30
MD31

SM_BA0
SM_BA1

SM_DQM3
SM_DQM7

MD56
MD57
MD58
MD59

MD60
MD61
MD62
MD63

SM_CKE0 <9>

SM_CKE1 <9>

R175
22

C223
10PF

SM_BA0 <9>
SM_BA1 <9>

SM_SEL0<17>

SMB_CLK<7,12,17>

SMB_DATA<7,12,17>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C143

+

10UF_10V_1206

SMD_CLK1 <9>

C230

6

INH

10

A

9

B

3

X

13

Y

.1UF

+3V

7

C

16

GND

8

+3V

X0
X1

VCC

X2
X3

GND

C132

+

10UF_10V_1206

SMD_CLK2<9>

U18

1
5
2
4

12

Y0

14

Y1

15

Y2

11

Y3

74HC4052

SM_CS#2<9>
SM_CS#3<9>

SCKDIMM0
SCKDIMM1

SDADIMM0
SDADIMM1

BANK 2/3

+3V +3V

MD0
MD1
MD2
MD3

MD4
MD5
MD6
MD7

SM_DQM0
SM_DQM4

MAA0
MAA1
MAA2

MD32
MD33
MD34
MD35

MD36
MD37
MD38
MD39

C163

R162

10PF

22

SM_RAS# SM_CAS#

SM_WE# SM_CKE3
SM_CS#2 MAA12
SM_CS#3

MD16
MD17
MD18
MD19

MD20
MD21
MD22
MD23

MAA6 MAA7
MAA8

MAA9
MAA10 MAA11

SM_DQM2
SM_DQM6

MD48
MD49
MD50
MD51

MD52
MD53
MD54
MD55

SDADIMM1

SM_SEL0 X/Y

0 SCKDIMM0

SCKDIMM11

JP27

1

VSS

3

DQ0

5

DQ1

7

DQ2

9

DQ3

11

VCC

13

DQ4

15

DQ5

17

DQ6

19

DQ7

21

VSS

23

CE0#

25

CE1#

27

VCC

29

A0

31

A1

33

A2

35

VSS

37

DQ8

39

DQ9

41

DQ10

43

DQ11

45

VCC

47

DQ12

49

DQ13

51

DQ14

53

DQ15

55

VSS

57

RESVD/DQ64

59

RESVD/DQ65

61

RFU/CLK0

63

VCC

65

RFU

67

WE#

69

RE0#

71

RE1#

73

OE#/RESVD

75

VSS

77

RESVD/DQ66

79

RESVD/DQ67

81

VCC

83

DQ16

85

DQ17

87

DQ18

89

DQ19

91

VSS

93

DQ20

95

DQ21

97

DQ22

99

DQ23

101

VCC

103

A6

105

A8

107

VSS

109

A9

111

A10

113

VCC

115

CE2#/RESVD

117

CE3#/RESVD

119

VSS

121

DQ24

123

DQ25

125

DQ26

127

DQ27

129

VCC

131

DQ28

133

DQ29

135

DQ30

137

DQ31

139

VSS

141

SDA

143

VCC

SO-DIMM144 REVERSE

D

DIMM1

D

E

2

DQ32
DQ33
DQ34
DQ35

DQ36
DQ37
DQ38
DQ39

CE4#
CE5#

DQ40
DQ41
DQ42
DQ43

DQ44
DQ45
DQ46
DQ47

RESVD/DQ68
RESVD/DQ69

RFU/CKE0

RFU/CKE1

RFU/CLK1

RESVD/DQ70
RESVD/DQ71

DQ48
DQ49
DQ50
DQ51

DQ52
DQ53
DQ54
DQ55

A11/BA0
A12/BA1

A13/A11

CE6#/RESVD
CE7#/RESVD

DQ56
DQ57
DQ58
DQ59

DQ60
DQ61
DQ62
DQ63

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC
RFU

RFU
RFU

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS
SCL

VCC

A3
A4
A5

A7

MD8

4

MD9

6

MD10

8

MD11

10
12

MD12

14

MD13

16

MD14

18

MD15

20
22

SM_DQM1

24

SM_DQM5

26
28

MAA3

30

MAA4

32

MAA5

34
36

MD40

38

MD41

40

MD42

42

MD43

44
46

MD44

48

MD45

50

MD46

52

MD47

54
56
58
60

SM_CKE2

62
64
66
68
70
72
74
76
78
80
82

MD24

84

MD25

86

MD26

88

MD27

90
92

MD28

94

MD29

96

MD30

98

MD31

100
102
104

SM_BA0

106
108

SM_BA1

110
112
114

SM_DQM3

116

SM_DQM7

118
120

MD56

122

MD57

124

MD58

126

MD59

128
130

MD60

132

MD61

134

MD62

136

MD63

138
140

SCKDIMM1

142
144

SM_CKE2 <9>
SM_CAS# <9>

SM_CKE3 <9>

R170
22

C193
10PF

SMD_CLK3 <9>

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet of

S.O. DIMM CONNECTOR

B

LA-1441

E

14 43Wednesday, March 06, 2002

0.2

檔

5

4

3

2

1

RTCCLK<17,23,24,29>

+2.5V

+3VS
+5VS

+1.5V

+

C101

22UF_16V_1206

JP13

1

MONO_OUT/PC_BEEP

3

GND

5

AUXA_RIGHT

7

AUXA_LEFT

9

CD_GND

11

CD_RIGHT

13

CD_LEFT

15

GND

17

3.3Vaux

19

GND

21

3.3Vmain

23

AC97_SDATA_OUT

25

AC97_RESET#

27

GND

29

AC97_MSTRCLK

AMP-108-5424

KSI[0..7]
KS0[0..15]

KSI0
KSI2
KSI4
KSI6
KSO0
KSO2
KSO4
KSO6
KSO8
KSO10
KSO12
KSO14

Int. Keyboard CONN.

JP11

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40

HEADER 2X20

12

C146
1UF_25V_0805

GND

GND

2
4
6
8
10

+5V

12
14
16
18
20
22
24
26
28
30

AUDIO_PWDN

MONO_PHONE

RESERVED

RESERVED
RESERVED
RESERVED
RESERVED
RESERVED

AC97_SYNC
AC97_SDATA_IN1
AC97_SDATA_IN0

AC97_BITCLK

MDC CONN.

KSI1
KSI3
KSI5
KSI7
KSO1
KSO3
KSO5
KSO7
KSO9
KSO11
KSO13
KSO15

12

C145

1UF_25V_0805

+5VS_MDC

1 2

R378 22

+12V
+3V+3V

+5V

1 2

L41 CHB1608B121

1 2

R388 10K

1 2

R548 @22

1 2

R383 22

+5VS_MDC+3VS_MDC+3.3VAUX

12

C159

1UF_25V_0805

MDC_DN# <33>MD_MIC<30>
MD_SPK <30>

+5VS

+3VS

1 2

R381 10K

IAC_BITCLK <17,30>

IAC_SYNC <17,30>

IAC_SDATAI1 <17>

KSI[0..7]<32>

KSO[0..15]<32>

AGP CONN.

JP8

D D

C C

AGP_DEVSEL#<10>

B B

AGP_AD[0..31]<10>
AGP_SBA[0..7]<10>

AGP_R<16>
AGP_G<16>

AGP_B<16>
AGP_HSYNC1<16>
AGP_VSYNC1<16>

AGP_DDCDATA<10,16>

AGP_DDCCLK<10,16>

DDC_MD2<16>

M_SEN#<16,18>

+5VALW

DAC_BRIG<32>

CBRST#<21,22,23,24,28,29>

+1.5VS +1.5VS

SUS_STAT#<17,21,25,34>

AGP_BUSY#<10,17>

AGP_REQ#<10>

AGP_ST0<10>
AGP_ST2<10>

AGP_RBF#<10>

AGP_SBSTB<10>

CLK_AGPCONN<12>

AGP_ADSTB1<10>

AGP_CBE#2<10>

CLK_VCH<12>

AGP_IRDY#<10>

AGP_CBE#1<10>

AGP_ADSTB0<10>

+VAGP_BRDREF +VAGP_CRDREF

R104

AGP_CLK

1 2

@33
R120

CLK_VCH

1 2

@33

+1.5V

AGP_IRDY#
AGP_DEVSEL#

AGP_AD[0..31]
AGP_SBA[0..7]

DAC_BRIG

AGP_SBA0
AGP_SBA2

AGP_SBA4
AGP_SBA6
AGP_CLK

AGP_AD31
AGP_AD29
AGP_AD27
AGP_AD25

AGP_AD23
AGP_AD21
AGP_AD19
AGP_AD17

CLK_VCH

AGP_AD14
AGP_AD12
AGP_AD10
AGP_AD8

STP_AGP#
AGP_AD7
AGP_AD5
AGP_AD3
AGP_AD1

C112

1 2

@15PF
C125

1 2

@15PF

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99

101
103
105
107
109
111
113
115
117
119

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119

HEADER 2X60

2

2

4

4

6

6

8

8

10

10

12

12

14

14

16

16

18

18

20

20

22

22

24

24

26

26

28

28

30

30

32

32

34

34

36

36

38

38

40

40

42

42

44

44

46

46

48

48

50

50

52

52

54

54

56

56

58

58

60

60

62

62

64

64

66

66

68

68

70

70

72

72

74

74

76

76

78

78

80

80

82

82

84

84

86

86

88

88

90

90

92

92

94

94

96

96

98

98

100

100

102

102

104

104

106

106

108

108

110

110

112

112

114

114

116

116

118

118

120

120

INVT_PWM

ENBKL
ENVEE

PCI_RST#

AGP_SBA1
AGP_SBA3

AGP_SBA5
AGP_SBA7

AGP_AD30
AGP_AD28
AGP_AD26
AGP_AD24

AGP_AD22
AGP_AD20
AGP_AD18
AGP_AD16

AGP_FRAME#

AGP_AD15
AGP_AD13
AGP_AD11
AGP_AD9

AGP_AD6
AGP_AD4
AGP_AD2
AGP_AD0

C3_STAT#<17>

CRMA <16>
LUMA <16>
COMPS <16>
TV_SYNC <16>

SUS_STAT#

TVOUT_IO_DDC2CLK
TVOUT_IO_DDC2DATA
VCH_IO_I2CCLK
VCH_IO_I2CDATA

INVT_PWM <32>

+5VALW

ENBKL <32>
ENVEE <32>

+1.5V

PIRQA# <17,19,22,23>
PCIRST# <8,17,19,20,21,22,23,24,25,28,29,34>
AGP_GNT# <10>
AGP_ST1 <10>
AGP_PIPE# <10>
AGP_WBF# <10>

AGP_SBSTB# <10>

AGP_CBE#3 <10>

AGP_ADSTB#1 <10>

AGP_FRAME# <10>
AGP_TRDY# <10>
AGP_STOP# <10>
AGP_PAR <10>

AGP_ADSTB#0 <10>
AGP_CBE#0 <10>

+3V

C727

1 2

.1UF

U60

5

1
2

3

4

@7SH08FU

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

STP_AGP#

RP38

In AGP mode : stuff RP38, no stuff RP39.

@8P4R_0

In VCH mode: stuff RP39, no stuff RP38.

RP39

8P4R_0

+3.3VAUX

+3VS

IAC_SDATAO<17,30>

IAC_RST#<17,30>

PID0 <25>
PID1 <25>
PID2 <25>
PID3 <25>

TV_OUT_DDC2CLK <10>
TV_OUT_DDC2DATA <10>
VCH_I2CCLK <10>
VCH_I2CDATA <10>

L39

+3VS_MDC

1 2

CHB1608B121

TP_DATA<32> TP_CLK <32>

1 2

A A

5

4

R544 0

PROPRIETARY NOTE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Compal Electronics, Inc.

Title

VGA Connector & MDC Connector

Size Document Number Rev

B

LA-1441

Date: Sheet of

15 43Wednesday, March 06, 2002

1

0.2

檔

A

B

C

D

E

TV_OUT CONN.

D11

@DAN217

12
C291

@47PF

2

@FBM-11-160808-121

@FBM-11-160808-121

@FBM-11-160808-121

12

C292

@47PF

1 1

TV_SYNC<15>

LUMA<15>

CRMA<15>

COMPS<15>

12

12

R218

@75

R219

R220

@75

TV_GND

1 2

@FBM-11-160808-121

12

@75

12

C293

@47PF

L17

1

3

L21

1 2

L20

1 2

L22

1 2

D10

@DAN217

2

C262

@47PF

D9

1

@DAN217

1

R559 For VCH (CH7011)

1 2

3

12

12

C261

@47PF

12
C270

@47PF

2

12

C269
@470PF

R559 @0

3

1 2

R560 @0

+3VS

+5VS

R560 For CH7007

JP2

1
2
3
4
5
6
7

@S CONN._SUYIN

2 2

3 3

In AGP mode: No stuff R6,R8,R10,R12,R14. Stuff R9,R11,R13,R549,R550
In VCH mode: Stuff R6,R8,R10,R12,R14. No stuff R9,R11,R13,R549,R550

DAC_RED<10>

AGP_R<15>

DAC_GREEN<10>

AGP_G<15>

DAC_BLUE<10>

AGP_B<15>

4 4

In AGP mode: No stuff C326,R245,C318,R231,C325,R230.
In VCH mode: Stuff C326,R245,C318,R231,C325,R230

DAC_RED#<10>

DAC_GREEN#<10>

DAC_BLUE#<10>

C326 .1UF

R245 37.5_1%

1 2

C318 .1UF

R231 37.5_1%

1 2

C325 .1UF

R230 37.5_1%

1 2

CRT Connector

DDC_MD2<15>

M_SEN#<15,18>

R14 0

1 2

R13 @0

1 2

R12 0

1 2

R11 @0

1 2

R10 0

1 2

R9 @0

1 2

12

R199

75

1 2

AGP_HSYNC1<15>

FROM AGP CONN.

FROM GMCH

AGP_VSYNC1<15>

+12VS

DAC_HSYNC<10>

DAC_VSYNC<10>

A

1 2

1 2

1 2

R200

C265
18PF

75

R549

R550

R202 100K

R6 33

1 2

*

1 2

R8 33

*
*
*
*
*
*

+5VS

+5VS

12

R86
10K

L10

1 2

FCM2012C80_0805

L11

1 2

FCM2012C80_0805

L12

1 2

R201

75

2

FCM2012C80_0805

12

C266
18PF

1 2

13

Q18

2N7002

2

B

13

Q17

2N7002

CHB1608B121

12

C264
18PF

1 2

@0

@0

D7

12

C256
15PF

L1

1 2

CHB1608B121

L2

1 2

DAN217

2

1

1

D6

DAN217

2

3

12

C255
15PF

12

C3
68PF
*10PF *10PF

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

D5

DAN217

3

2

12

C254
15PF

12

C4
68PF

+5VS

1

3

12

C250
100PF

C

D8

2 1

RB491D

FUSE_1A

12

C253
100PF

220PF

CRT_VCCR_CRT_VCC

F1

21

12

C5
.1UF

CRT_VCC

12

12

C2

C252
220PF

6

11

1
7

12

2
8

13

3
9

14

4
10
15

5

5VDDCDA

5VDDCCL

JP3
CRT-15P

CRT_VCC

12

CRT_VCC

R553

2.2K

In AGP mode: Stuff R16,R15,R7. No stuff R553,R554,R555.
In VCH mode: Stuff R553,R554,R555. No stuff R16,R15,R7

+5VS+5VS+12VS +3VS

12

12

R554

2.2K

Q1

2N7002

1 3

12

2

1 3

R555
@2.2K

12

R15
@2.2K

R16
100K

2

Q3
2N7002

12

R7
@2.2K

AGP_DDCDATA <10,15>

AGP_DDCCLK <10,15>

Compal Electronics, Inc.

Title

CRT&TV-OUT Connector

Size Document Number Rev

Custom

ATW03

D

Date: Sheet of

16 43Wednesday, March 06, 2002

E

0.2

檔

A B C

PCI_CLK

PCI_DEVSEL#

PCI_FRAME#

PCI_IRDY#

PCI_PAR
PCI_PERR#
PCI_LOCK#

PCI_PME#

PCI_RST#

PCI_SERR#

STOP#

PCI_TRDY#

SM_INTRUDER#

SMLINK0

SMLINK1

SMB_CLK

SMB_DATA

CPU_A20GATE

CPU_A20M#

CPU_DPSLP#

CPU_FERR#

CPU_IGNNE#

CPU_INIT#
CPU_INTR

CPU_NMI

CPU_RCIN#

CPU_SLP#
CPU_SMI#

STPCLK#

HUB_PD0
HUB_PD1
HUB_PD2
HUB_PD3
HUB_PD4
HUB_PD5
HUB_PD6
HUB_PD7
HUB_PD8
HUB_PD9

HUB_PD10

CLK_ICHHUB

PM_LANPWROK

C44

1 2

.1UF

LPC_AD0 <25,32>
LPC_AD1 <25,32>
LPC_AD2 <25,32>
LPC_AD3 <25,32>
LPC_DRQ#0 <19,32>
LPC_DRQ#1 <19,25>
LPC_FRAME# <25,32>

SM_SEL0 <14>
SIDEPWR <20>
CLK_ICHAPIC <12>
H_PICD0 <5>
H_PICD1 <5>

INT_IRQ14 <19,20>
INT_IRQ15 <19,20>
INT_SERIRQ <19,23,25,32>

PIRQA#
PIRQB#
PIRQC#
PIRQD#

CLK_ICHPCI

T5
M3
F1
C4
D4

GNTA#

B6
B3
N3
G5
M2
M1
W1
Y1
L5
H2
H1

Y6
AC3
AB2
AC4
AB5
AC5

Y22
V23
AB22
J22
AA21
AB23
AA23
Y21
W23
U22
W21
Y23
U23

HUB_PD0

L22

HUB_PD1

M21

HUB_PD2

M23

HUB_PD3

N20

HUB_PD4

P21

HUB_PD5

R22

HUB_PD6

R20

HUB_PD7

T23

HUB_PD8

M19

HUB_PD9

P19

HUB_PD10

N19

+VS_HUBREF

CLK_ICHHUB <12>
HUB_PSTRB <8>
HUB_PSTRB# <8>

Title

Size Document Number Rev
Custom

Date: Sheet of

CLK_ICHPCI <12>
PCI_DEVSEL# <19,21,22,23,28,29>
PCI_FRAME# <19,21,22,23,28,29>
PCI_REQA# <19>
PCI_REQB# <19>

PCI_IRDY# <19,21,22,23,28,29>
PCI_PAR <19,21,22,23,28,29>
PCI_PERR# <19,21,22,23,28>
PCI_LOCK# <19>
ICH_WAKE_UP# <32>
PCIRST# <8,15,19,20,21,22,23,24,25,28,29,34>
PCI_SERR# <19,21,22,23,28>
PCI_STOP# <19,21,22,23,28,29>
PCI_TRDY# <19,21,22,23,28,29>

SM_INTRUDER# <19>
SMLINK0 <19>
SMLINK1 <19>
SMB_CLK <7,12,14>
SMB_DATA <7,12,14>
SMB_ALERT# <19>

GATEA20 <32>
H_A20M# <5>

H_FERR# <5>
H_IGNNE# <5>
H_INIT# <5>
H_INTR <5>
H_NMI <5>
H_PWRGD <5>
RC# <32>

H_SMI# <5>
H_STPCLK# <5>

HUB_PD[0..10]

+VS_HUBVSWING

12

C530
.01UF

Compal Electronics, Ltd.

Intel ICH3-M

LA-1441

PM_BATLOW#<32>

1 2

R295 10M

12

R522

2.4M

PM_CPUPERF#<5,19>

PM_DPRSLPVR<7,43>

J2

K1

J4
K3
H5
K4
H3

L1

L2
G2

L4
H4
M4

J3
M5

J1

F5
N2
G4
P2
G1
P1

F2
P3

F3
R1
E2
N4
D1
P4
E1
P5

K2
K5
N1
R2

A4
E3
D2
D5
B4

D3

F4
A3
R4
E4

C461
12PF

PM_GMUXSEL<7,43>

PM_STPCPU#<12>

PM_RSMRST#<35>
SYS_PWROK<35>

PM_CLKRUN#<19,22,23,25,28,29,32>

ICH_VGATE<35>

ATF_INT#<32>

SUS_STAT#<15,21,25,34>

PM_STPPCI#<12>
PM_SLP_S5#<32>

PM_SLP_S3#<12,32>
PM_SLP_S1#<12,32>

ICH_RI#<19>

C3_STAT#<15>

AGP_BUSY#<10,15>

U33A

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3

PCI_GNT#0
PCI_GNT#1
PCI_GNT#2
PCI_GNT#3
PCI_GNT#4

PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
PCI_REQ#4

ICH3-M

12

PBTN#<19>

PM_LANPWROK

1 2

R294 10M

X2

32.768KHZ

PM_RSMRST#

1 2

V4Y5AB3V5AC2

PCI

Interface

VSS0

A1

A13

12

C444
12PF

PM_BATLOW#

PM_AUXPW ROK

PM_AGPBUSY#/GPIO6

PM_C3_STAT#/GPIO21

VSS1

VSS2

VSS3

VSS4

A16

A17

A20

RTC_VBIAS
RTC_X1

RTC_X2

PM_CLKRUN#/GPIO24

VSS5

A23B8B10

C60

10PF

IAC_SDAT AO

IAC_SYNC

12

10K

Y20

PM_GMUXSEL/GPIO23

PM_CPUPREF#/GPIO22

R72

1 2

1 2

IAC_RST#

IAC_SDAT AI0

IAC_SDAT AI1

IAC_BITCL K

R69 47

R70 47

V19B7D11

B11

C11C7A7V1U3T3U2T2U4U1V2W2Y4Y2W3W4Y3

LPC_AD0

LPC_AD1

AC_SYNC

AC_SDATAIN1

AC_SDATAOUT

LPC

Interface

PM_VGATE/VRMPWRGD

AC_RST#

AC_BITCLK

AC_SDATAIN0

AC'97

Interface

PIDEPW R

CLK_ICHAPIC

H_PICD1

H_PICD0

ECSCI#

ECSMI#

IDE_PATADET

LID#

GPIO_25

GPIO_7

GPIO_8

GPIO_12

GPIO_13

GPIO_25

unMUX

GPIO

GPIO_27

LPC_AD2

LPC_AD3

LPC_DRQ#0

LPC_DRQ#1

LPC_FRAME#

PIRQA#

J21

J20

J19

GPIO_28

INT_APICD0

INT_APICD1

INT_PIRQA#

INT_APICCLK

Interrupt
Interface

ICH_PID3

PIRQB#

ICH_PID1

ICH_PID0

PIRQD#

ICH_PID2

PIRQC#

H22

W19

AB14A5C5B5A6A2B2C1B1

INT_IRQ15

INT_PIRQD#

INT_PIRQC#

INT_PIRQF#/GPIO3

INT_PIRQE#/GPIO2

INT_PIRQG#/GPIO4

INT_IRQ14

INT_SERIRQ

INT_PIRQH#/GPIO5

PCI_GPIO0/REQA#

PCI_GPIO1/REQB#/REQ5#

PCI_GPIO16/GNTA#

PCI_GPIO17/GNTB#/GNT5#

PCI

Interface

System

Managment

Interface

SMB_ALERT#/GPIO11

INT_PIRQB#

R370

PM_SUSCLK

AB21

AB1

AA6

AA1

AA7

W20

AA5

AA2

V21

U21

AA4

AB4U5U20

PM_RI#

PM_PWROK

PM_RSMRST#

PM_PWRBTN#

PM_DPRSLPVR

PM_SLP_S1#/GPIO19

PM_THRM#

PM_SLP_S3#

PM_SLP_S5#

PM_SUS_CLK

PM_SUS_STAT#

PM_STPPCI#/GPIO18

PM_STPCPU#/GPIO20

GeyservillePower Management

ICH3-M (1/2)

CPU

Interface

CPU_PWRGOOD

VSS

VSS6

VSS7

VSS8

VSS9

VSS10

VSS11

VSS12

VSS13

VSS14

VSS15

VSS16

VSS17

VSS18

VSS19

VSS20

VSS21

VSS22

VSS23

VSS24

VSS25

VSS26

VSS27

VSS28

VSS29

VSS30

B13

B14

B15

B18

B19

B20

B22C3C6

F19

C14

C15

C16

C17

C18

C19

C20

C21

C22D9D13

D16

D17

+RTCVCC

CLK_ICH14<12>
CLK_ICH48<12>

1 2

R286 15K

CLK_ICH14
CLK_ICH48

C416

1UF_10V_0603

Clocks EEPROM

VSS31

VSS32

VSS33

VSS34

CLK_48

CLK_14

J23

D20

D21

D22

E5

RTC_RST#

12

12

12

CLK_RTEST#

AC7Y7F20

RTC_X1

J1
JOPEN

R278
1K

LAN_RSTSYNC

CLK_VBIAS

CLK_RTCX1

CLK_RTCX2

AC6

AB7

RTC_X2

RTC_VBIAS

LAN

Interface

LAN_TXD1

LAN_TXD2

LAN_JCLK

A10C9D7

Interface

LAN_TXD0

LAN_RXD2

LAN_RXD1

EEP_SHCLK

LAN_RXD0

EEP_DOUT

EEP_DIN

D10

C8A8A9B9C10

12

R77
@0

+3V

PM_RSMRST#

EEP_CS

E9D8E8

HUB_VSW ING

HUB_VREF

L20

L19

100K
R59

1 2

R67 10K

1 2

C

HubLink

Interface

HUB_RCOMP

HUB_PSTRB#

HUB_PSTRB

HUB_PAR

HUB_CLK

T19

R19

N22

P23

K19

HUB_ICH_RCOMP

LID#<19>

PCI_AD[0..31]<21,22,23,28,29>

ECSMI#
ECSCI#
LID#
IDE_PATADET
R60 0

R287 1K

1 2

PM_SUSCLK

12

IAC_BITCLK
IAC_RST#

IAC_SDATAI0
IAC_SDATAI1

IAC_SDATAO
IAC_SYNC

PCI_C/BE#0<21,22,23,28,29>
PCI_C/BE#1<21,22,23,28,29>
PCI_C/BE#2<21,22,23,28,29>
PCI_C/BE#3<21,22,23,28,29>

PCI_GNT#0<19,22>
PCI_GNT#1<19,28>
PCI_GNT#2<19,23>
PCI_GNT#3<19,21>
PCI_GNT#4<19,28>

PCI_REQ#0<19,22>
PCI_REQ#1<19,28>
PCI_REQ#2<19,23>
PCI_REQ#3<19,21>
PCI_REQ#4<19,28>

1 2

R521 22M

C426

1 2

.047UF

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

ECSMI#<19>
ECSCI#<19>

IDE_PATADET<20>

RTCCLK

23,24,29>

IAC_BITCLK<15,30>

IAC_RST#<15,30>
IAC_SDATAI0<30>
IAC_SDATAI1<15>

1 1

IAC_SDATAO<15,30>

IAC_SYNC<15,30>

2 2

Place closely to ICH3-M

CLK_ICH14

12

R337
@10

12

C541
@15PF

CLK_ICH48

12

3 3

R340
@10

12

C534
@15PF

+RTCVCC

4 4

D

+3VS

GNTA#
GPIO_25

R54 10K

PIRQA# <15,19,22,23>
PIRQB# <19,21,23>
PIRQC# <19,28,29>
PIRQD# <19,28,29>

+1.5VS

1 2

R332 0

H_PICD0
H_PICD1

HUB_PD[0..10] <8>

1 2

R346

36.5_1%

12

C529
.01UF

Close to ICH3-M.

D

RP15

8P4R_4.7K

CLK_ICHAPIC

R342
@33_0402

1 2

C540
@10PF

CLK_ICHPCI

12

R66
@10

12

C42
@15PF

(for use if CPU unable
to support DPSLP#)

H_DPSLP# <5,43>

12

12

R338

1K

17 43Wednesday, March 06, 2002

ICH_PID0
ICH_PID1
ICH_PID2
ICH_PID3

R339

1K

CLK_ICHHUB

R344
10

1 2

C543
5PF

1 8
2 7
3 6
4 5

R65 @10K

1 2
1 2

Place closely to ICH3-M

12

R327
@10K

+3VS
+3V

0.2

檔

A

B

C

D

E

CLOSE TO ICH3-M(< 1 inch)

C508 @5PF

1 2

USB_PP1<27>
USB_PN1<27>
USB_PP0<27>
USB_PN0<27>

1 1

USB_PP3<27>
USB_PN3<27>
USB_PP2<27>
USB_PN2<27>

USB_PP4
USB_PN4

+3V

RP19

2 2

3 3

4 4

8P4R_10K

1 8
2 7
3 6
4 5

Disable Timeout Feature

+3VS

C509 @5PF
C91 @5PF

C197 @5PF
C86 @5PF

12

1 2

R343
@1K

ACIN<32,34,37,41>

1 2

1 2

1 2

1 2

USB_OC#2
USB_OC#4

USB_OC#5

R314

18.2_1%

ICH_SPKR

A

USB_D_PP1
USB_D_PN1
USB_D_PP0
USB_D_PN0

USB_D_PP3
USB_D_PN3
USB_D_PP2
USB_D_PN2

USB_D_PP4
USB_D_PN4

USB_OC#0<27>
USB_OC#1<27>

USB_OC#3<27>

ICH_IDE_PRST#<20>
ICH_IDE_SRST#<20>

FWH_WP#<19>

FWH_TBL#<19>

EC_FLASH#<33>

M_SEN#<15,16>

ICH_SPKR<31>

+1.8VS

+3V

R326
100K

21

D32 RB751V

1 2

USB_RBIAS

1 2

+V3A_ICH

+3VS

12

USB_D_PP0
USB_D_PP1
USB_D_PP2
USB_D_PP3
USB_D_PP4
USB_PP5
USB_D_PN0
USB_D_PN1
USB_D_PN2
USB_D_PN3
USB_D_PN4
USB_PN5

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5

R98 @0

ICH_ACIN

ICH_SPKR

R309

0_0805

ICH_ACIN

+5VS +3VS

R73

1K

+1.8V

R320

1 2

0_0805

U33B

D19

USB_PP0

A19

USB_PP1

E17

USB_PP2

B17

USB_PP3

D15

USB_PP4

A15

USB_PP5

D18

USB_PN#0

A18

USB_PN#1

E16

USB_PN#2

B16

USB_PN#3

D14

USB_PN#4

A14

USB_PN#5

E12

USB_OC#0

D12

USB_OC#1

C12

USB_OC#2

B12

USB_OC#3

A12

USB_OC#4

A11

USB_OC#5

H20

USB_LEDA#0/GPIO32

G22

USB_LEDA#1/GPIO33

F21

USB_LEDA#2/GPIO34

G19

USB_LEDA#3/GPIO35

E22

USB_LEDA#4/GPIO36

E21

USB_LEDA#5/GPIO37

H21

USB_LEDG#0/GPIO38

G23

USB_LEDG#1/GPIO39

F23

USB_LEDG#2/GPIO40

G21

USB_LEDG#3/GPIO41

D23

USB_LEDG#4/GPIO42

E23

USB_LEDG#5/GPIO43

B21

USB_RBIAS

H23

SPKR

U19

VCCA

F17

VCCPSUS3/VCCPUSB0

F18

VCCPSUS4/VCCPUSB1

K14

VCCPSUS5/VCCPUSB2

E10

VCCPSUS0

V8

VCCPSUS1

V9

VCCPSUS2

ICH3-M

21

12

D26
1SS355

12

C58
.1UF

L33

1 2

CHB2012U170

E13

F14

K12

P10V6V7

VCC_SUS0

VCC_SUS1

VCC_SUS2

USB

Interface

12

VCC_SUS3

VCC_SUS4

VCC_SUS5

VCC5REF

C455
1UF_10V_0603

+V1.8_ICHLAN

F15

F16F7F8

VCC_USB0/VCC_SUS6

VCC_USB1/VCC_SUS7

VCC_AUX0/VCCLAN1_8

VCC_AUX1/VCCLAN1_8

+RTCVCC

K10

AB6E6W8

VCC_RTC

VCC_AUX2/VCCLAN1_8

+V5S_ICHREF

VCC5REF1

VCC5REF2

Misc

Power

VSS35

VSS36

VSS37

VSS38

VSS39

VSS40

VSS41

VSS42

VSS43

VSS44

VSS45

VSS46

VSS47

VSS48

VSS49

VSS50

E14

E15

E18

E19

E20

F22G3G20

H19

AA22J5K11

K13

K20

K21

K22

B

+3V

12

R305
0

12

C492
.1UF

+3V

VCC5R EFSUS

12

C13W5F9

F10

VCC5REFSUS1

VCC5REFSUS2

VCCPAUX0/VCCLAN3_3

VCCPAUX1/VCCLAN3_3

VSS51

VSS52

VSS53

VSS54

VSS55

VSS56

K23L3L10

L11

L12

L13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

+1.8V

+1.5VS

12

R341
0_0805

U18

V22

VCCPCPU1

VCCPCPU2

+1.8VA_ICH

C23

B23E7T21D6T1C2A21

N/C0

Power

VCCUSBBG/VCC_SUS8

VCCUSBPLL/VCC_SUS9

N/C1

N/C2

N/C3

N/C4

R298
0_0805

P14

VCCPCPU0

ICH3-M (2/2)

VSS

VSS57

VSS58

VSS59

VSS60

VSS61

VSS62

VSS63

VSS64

VSS65

VSS66

VSS67

VSS68

VSS69

VSS70

L14

L21

L23

M11

M12

M13

M20

M22N5N10

N11

N12

N13

N14

C

VSS102

VSS71

VSS72

N21

N23

A22F6G6H6J6

VSS103

VCCPPCI0

VCCPPCI1

VSS73

VSS74

VSS75

VSS76

P11

P13

P20

P22R3R5

M10R6T6U6G18

VCCPPCI2

VCCPPCI3

VCCPPCI4

VSS77

VSS78

VSS79

R21

VCCPPCI5

VSS80

R23T4T20

+3VS +1.8VS

H18

P12

V15

V16

V17

V18

J18

M14

R18

T18

E11K6K18P6P18

V10

V14

VCCP0

VCCP1

VCCPPCI6

VCCPPCI7

VSS81

VSS82

VSS83

VSS84

VSS85

VSS86

T22V3AC23

V20W6W7

VCCPHL0

VCCPHL1

VCCPHL2

VCCPIDE0

VCCPIDE1

VCCPIDE2

VSS87

VSS88

VSS89

W10

W14

VCCPHL3

VCCPIDE3

VCCPIDE4

VSS90

VSS91

W18

W22Y8AA3

VCCCORE0

VSS92

VSS93

VSS94

VSS95

VSS96

VSS97

VSS98

AA8

AA12

AA16

AA20

D

VCCCORE1

VCCCORE2

VCCCORE3

IDE

Interface

VSS99

VSS100

VSS101

AB8

AC1

AC8

IDE_PDCS1#
IDE_PDCS3#

VCCCORE4

VCCCORE5

VCCCORE6

IDE_SDCS1#
IDE_SDCS3#

IDE_PDDACK#
IDE_SDDACK#

IDE_PDDREQ
IDE_SDDREQ

IDE_PDIOR#

IDE_SDIOR#
IDE_PDIOW#
IDE_SDIOW#

IDE_PIORDY

IDE_SIORDY

IDE_PDA0
IDE_PDA1
IDE_PDA2
IDE_SDA0
IDE_SDA1
IDE_SDA2

IDE_PDD0
IDE_PDD1
IDE_PDD2
IDE_PDD3
IDE_PDD4
IDE_PDD5
IDE_PDD6
IDE_PDD7
IDE_PDD8

IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15

IDE_SDD0

IDE_SDD1

IDE_SDD2

IDE_SDD3

IDE_SDD4

IDE_SDD5

IDE_SDD6

IDE_SDD7

IDE_SDD8

IDE_SDD9
IDE_SDD10
IDE_SDD11
IDE_SDD12
IDE_SDD13
IDE_SDD14
IDE_SDD15

AC15
AB15
AC21
AC22

AA14
AC14
AA15
AC20
AA19
AB20

IDE_PDD0

W12

IDE_PDD1

AB11

IDE_PDD2

AA10

IDE_PDD3

AC10

IDE_PDD4

W11

IDE_PDD5

Y9

IDE_PDD6

AB9

IDE_PDD7

AA9

IDE_PDD8

AC9

IDE_PDD9

Y10

IDE_PDD10

W9

IDE_PDD11

Y11

IDE_PDD12

AB10

IDE_PDD13

AC11

IDE_PDD14

AA11

IDE_PDD15

AC12

IDE_SDD0

Y17

IDE_SDD1

W17

IDE_SDD2

AC17

IDE_SDD3

AB16

IDE_SDD4

W16

IDE_SDD5

Y14

IDE_SDD6

AA13

IDE_SDD7

W15

IDE_SDD8

W13

IDE_SDD9

Y16

IDE_SDD10

Y15

IDE_SDD11

AC16

IDE_SDD12

AB17

IDE_SDD13

AA17

IDE_SDD14

Y18

IDE_SDD15

AC18
Y13

Y19
AB12
AB18
AC13
AC19
Y12
AA18
AB13
AB19

Compal Electronics, Ltd.

Title

Intel ICH3-M

Size Document Number Rev
Custom

LA-1441

Date: Sheet of

IDE_PDCS1# <20>
IDE_PDCS3# <20>
IDE_SDCS1# <20>
IDE_SDCS3# <20>

IDE_PDA0 <20>
IDE_PDA1 <20>
IDE_PDA2 <20>
IDE_SDA0 <20>
IDE_SDA1 <20>
IDE_SDA2 <20>
IDE_PDD[0..15] <20>

IDE_SDD[0..15] <20>

IDE_PDDACK# <20>
IDE_SDDACK# <20>
IDE_PDDREQ <20>
IDE_SDDREQ <20>
IDE_PDIOR# <20>
IDE_SDIOR# <20>
IDE_PDIOW# <20>
IDE_SDIOW# <20>
IDE_PIORDY <20>
IDE_SIORDY <20>

18 43Wednesday, March 06, 2002

E

0.2

檔

A B C

+3VS +3VS

RP13

PCI_FRAME#<17,21,22,23,28,29>

PCI_IRDY#<17,21,22,23,28,29>

PCI_TRDY#<17,21,22,23,28,29>

PCI_STOP#<17,21,22,23,28,29>

1 1

PCI_REQA#<17>
PCI_REQB#<17>
PCI_REQ#0<17,22>
PCI_REQ#1<17,28>

PCI_GNT#1<17,28>
PCI_GNT#2<17,23>

PIRQD#<17,28,29>

INT_IRQ14<17,20>

PCI_GNT#0<17,22>

2 2

3 3

4 4

PCI_GNT#3<17,21>

PCI_GNT#4<17,28>

PCIRST#<8,15,17,20,21,22,23,24,25,28,29,34>
SMLINK0<17>
SMLINK1<17>

SM_INTRUDER#<17>

PM_CPUPERF#<5,17>

PBTN_OUT#<32> PBTN# <17>

ON/OFF<32,34>

+3V

EC_RIOUT#<32> ICH_RI# <17>

+3V

EC_SMI#<32>

+3V

EC_SCI#<32>

+3V

EC_LID_OUT#<32>

1
2
3
4
5

10P8R_8.2K

+3VS +3VS

RP18
1
2
3
4
5

10P8R_8.2K

+3VS

D14 RB751V

D15 @RB751V

R38 10K
D13 RB751V

R47 10K
D16 RB751V
R42 10K
D17 RB751V

R40 10K
D18 RB751V

1 2

1 2

1 2

1 2

RP14
1
2
3
4
5

10P8R_8.2K

21

21

21

21

21

21

10
9
8
7
6

10
9
8
7
6

10
9
8
7
6

1 2

R57 8.2K

1 2

R63 8.2K

1 2

R58 8.2K

1 2

R39 @8.2K

1 2

R515 4.7K

1 2

R516 4.7K

1 2

R282 100K

R300 @10K

1 2

PBTN#

ICH_RI#

ECSMI#

ECSCI#

LID#

+3VS

ECSMI# <17>

ECSCI# <17>

LID# <17>

PCI_SERR# <17,21,22,23,28>
PCI_DEVSEL# <17,21,22,23,28,29>
PCI_PERR# <17,21,22,23,28>
PCI_LOCK# <17>

PCI_REQ#2 <17,23>
PCI_REQ#3 <17,21>
PCI_REQ#4 <17,28>
INT_SERIRQ <17,23,25,32>

INT_IRQ15 <17,20>
PIRQA# <15,17,22,23>
PIRQB# <17,21,23>
PIRQC# <17,28,29>

+3VS

+3V

+RTCVCC

+VTT

+3VS

12

+

+3V

12

+

22UF_16V_1206

+1.8VS

12

+

+1.8VA_ICH

12

+

22UF_16V_1206

PM_CLKRUN#<17,22,23,25,28,29,32>

SMB_ALERT#<17>

LPC_DRQ#0<17,32>

LPC_DRQ#1<17,25>

C362
22UF_16V_1206

C341

C317
150UF_6.3V_D2

C527

C92

C82

.1UF

.1UF

FWH_WP#<18>
FWH_TBL#<18>

12

+

C385
22UF_16V_1206

12

C486
.1UF

12

C85
.1UF

12

C531
.1UF

R289 10K

R45 10K

R56 10K

12

12

12

C485

C488

.1UF

.1UF

12

C52
47PF

12

12

C533

C532

.1UF

.1UF

C61

C66

.1UF

.1UF

1 8
2 7
3 6
4 5

1 2

1 2

1 2

C51
.1UF

12

C95
.1UF

RP24

8P4R_10K

12

12

C487
47PF

C104
.01UF

C47
.1UF

12

C96
.1UF

+V3A_ICH

+3VS

+3V

+3VS

C76
47PF

12

C50
.1UF

+V1.8_ICHLAN

12

C98
.1UF

12

C55
.1UF

C69
.1UF

12

12

C46
47PF

12

C68
.01UF

C99
.1UF

12

12

C56
47PF

C63
.1UF

PCI_PAR<17,21,22,23,28,29>

+V5S_ICHREF

12

+

C75

1UF_10V_0603

12

C57
.1UF

C54
.1UF

C65
.1UF

D

12

C77
47PF

R71 @100

1 2

12

12

C49

C64

.1UF

.1UF

12

12

C93

C94

.1UF

.1UF

+1.5VS

12

+

C84
1UF_10V_0603

12

C87
.1UF

E

12

12

C102

C110

.1UF

.1UF

12

12

C89

C100
.1UF

47PF

12

C162
47PF

12

12

C161

C73

.1UF

.1UF

12

C103
.1UF

檔

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

D

Compal Electronics, Ltd.

Title

ICH3-M PullupS & Decoupling

Size Document Number Rev
Custom

LA-1441

Date: Sheet of

19 43Wednesday, March 06, 2002

E

0.2

+5VS

IDE,CD-ROM Module CONN.

12

C109

IDE_PDD[0..15]<18>

IDE_PDDREQ<18>

IDE_PDIOW#<18>

IDE_PDIOR#<18>
IDE_PIORDY<18>
IDE_PDDACK#<18>

INT_IRQ14<17,19>
IDE_PDA1<18>
IDE_PDA0<18>
IDE_PDCS1#<18> IDE_PDCS3# <18>
PHDD_LED#<33>

1 2

+5VS

R95 100K

1 2

+5VMOD

R167 100K

IDE_SDD[0..15]<18>

+5VS

RP2

DSKCHG#

18

INDEX#

27

WP#

36

TRACK0#

45

8P4R_1K

DRV0#

1 2

R253 1K

WDATA#
WGATE#
HDSEL#
FDDIR#

+5VS

1 2

R166 470

6
7
8
9

10

EXTCSEL

IDE_PDD[0..15]

PIDE_RST#
IDE_PDD7
IDE_PDD6
IDE_PDD5
IDE_PDD4
IDE_PDD3
IDE_PDD2
IDE_PDD1
IDE_PDD0

IDE_PDDREQ

IDE_PIORDY

INT_IRQ14

+5VS

SHDD_LED#

IDE_SDD[0..15]

INT_CD_L<30> INT_CD_R <30>
CD_AGND<30>

IDE_SDIOW#<18>

IDE_SIORDY<18>

INT_IRQ15<17,19>

IDE_SDA1<18>
IDE_SDA0<18>

IDE_SDCS1#<18>

SHDD_LED#<33>

RDATA#<25>

TRACK0#<25>

WDATA#<25>

STEP#<25>

MTR0#<25>

DSKCHG#<25>

DRV0#<25,33>

RP1

10P8R_1K

CD_AGND
SIDE_RST#
IDE_SDD7
IDE_SDD6
IDE_SDD5
IDE_SDD4
IDE_SDD3
IDE_SDD2
IDE_SDD1
IDE_SDD0

IDE_SIORDY

SHDD_LED#
EXTCSEL

RDATA#
WP#

WP#<25>

TRACK0#
WDATA#
STEP#
MTR0#
DSKCHG#
DRV0#

5

STEP#

4

MTR0#

3

RDATA#

2
1

1000PF

Place component's closely IDE CONN.

JP7

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44

HDD 44P SUYIN 20225A-44G5-A

JP17

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
51 52
53 54
55 56
57 58
59 60

HEADER 2X30

+3VALW

+5VS

C518
10UF_16V_1206

RP3
1 8
2 7
3 6
4 5

8P4R_100K

+5VMOD

12

C114

1UF_25V_0805

EXTID0
EXTID1
EXTID2

12

C107

.1UF

IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15

PCSEL

1 2

R84 470

1 2

R556 @0

+5VS

CD_AGND
IDE_SDD8
IDE_SDD9
IDE_SDD10
IDE_SDD11
IDE_SDD12
IDE_SDD13
IDE_SDD14
IDE_SDD15

EXTID0
EXTID1
EXTID2
HDSEL#

WGATE#

FDDIR#
3MODE#

INDEX#

12
C186

1000PF

W=80mils

C183
10UF_16V_1206

Place component's closely CD-ROM CONN.

IDE_PDA2 <18>

IDE_SDDREQ <18>
IDE_SDIOR# <18>
IDE_SDDACK# <18>
IDE_SDA2 <18>
IDE_SDCS3# <18>
EXTID0 <33>
EXTID1 <33>
EXTID2 <33>
HDSEL# <25>

WGATE# <25>

FDDIR# <25>
3MODE# <25>

INDEX# <25>

+5VMOD

12
C182

1UF_25V_0805

12
C185

.1UF

+5VS

12

12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

HDD Manual ATA Type Selection:

ATA33 : populate R43, de-populate R46.
ATA66/100 : populate R46, de-populate R43.

R43
@10K

IDE_PATADET <17>

R46
10K

+3VS

+5VMOD

+5VS

Q9

SI3456DV
6
5
2
1

+12VALW

R165

12

100K

47K

EXTIDEPWR#<33>

SIDEPWR<17>

R75 10K

R429 10K

1 2

1 2

R88 1K

1 2

R428 1K

1 2

R412 1K

IDE_PDD7

IDE_SDD7

IDE_PIORDY

IDE_SIORDY

ICH_IDE_SRST#<18>

D1 S1

61

2

G1

ICH_IDE_PRST#<18>

SI1906DL

PCIRST#<8,15,17,19,21,22,23,24,25,28,29,34>

PCIRST#

2

47K

Q41A

R82 5.6K

1 2

R152 5.6K

1 2

C139

1 2

.1UF

IDE_PDDREQ

IDE_SDDREQ

+5VS

C140

1 2

.1UF

PCIRST#

+5VS

1
2

5

1
2

3

U13

5

4

3

7SH08FU

Title

IDE/ FDD MODULE CONN.

Size Document Number Rev

B

LA-1441

Date: Sheet of

+5VMOD

4

3

1

3

U12

7SH08FU

Q39
DTC144EKA

4

SIDE_RST#

12

+

<1st Part Field>

12

PIDE_RST#

12

C174

4.7UF_16V_1206

R161
1K

D2

34

S2

C176
.01UF

SI3456DV: N CHANNEL
VGS: 4.5V, RDS: 65 mOHM
Id(MAX): 5.1A
VGS,+-20V

Compal Electronics, Inc

EXTIDE_EN#

5

G2

Q41B
SI1906DL

20 43Wednesday, March 06, 2002

0.2

檔

5

LAN_IDSEL

12

R271

100K

D D

Q24

EN_LAN#<33>

+12VALW

C C

B B

CLK_PCI_LAN

A A

2

1 3

R241

1 2

470K

2

1 3

Q23
FDV301

12

R238
@22

12

C324
@10PF

For 8100B only

1 2

12

C732
@0.1UF

2N7002

+3VLAN

12

R563 @0

5

LAN_IDSELPCI_AD17

C370

.1UF

SUS_STAT#<15,17,25,34>

1 2

+3VS

R227 @1K

PIRQB#<17,19,23>

PCIRST#<8,15,17,19,20,22,23,24,25,28,29,34>

CBRST#<15,22,23,24,28,29>

CLK_PCI_LAN<12>

PCI_C/BE#3<17,22,23,28,29>

PCI_AD[0..31]<17,22,23,28,29>

+2.5VLANAVDD25

PCI_GNT#3<17,19>

PCI_REQ#3<17,19>

+2.5VLAN

1 2

LAN_IDSEL

PCI_AD[0..31]

1 2

R270 100

R222
@15K

R484@0

R4850

CLK_PCI_LAN

PCI_AD31
PCI_AD30

PCI_AD29
PCI_AD28

PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24

1 2

PCI_AD23

PCI_C/BE#2<17,22,23,28,29>

PCI_FRAME#<17,19,22,23,28,29>

PCI_IRDY#<17,19,22,23,28,29>

PCI_TRDY#<17,19,22,23,28,29>

PCI_DEVSEL#<17,19,22,23,28,29>

PCI_STOP#<17,19,22,23,28,29>
PCI_PERR#<17,19,22,23,28>
PCI_SERR#<17,19,22,23,28>

PCI_PAR<17,19,22,23,28,29>

PCI_C/BE#1<17,22,23,28,29>

R22
50

12

12

LAN_PME#<32>

LAN_RD­LAN_RD+

LAN_TD­LAN_TD+

12

12

C12
.1UF

4

*BOM 16.9K_1%

ACTIVITY#

LINK10_100#

8079787776757473727170696867666564636261605958575655545352

GND

LED0

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99

100

R21
50

LED1NCLED2

INTAB
RSTB
CLK
GNTB
REQB
AD31
AD30
GND
AD29
VDD
AD28
AD27
AD26
AD25
AD24
VDD25
VDD
CBE3B
IDSEL
AD23

AD22

GND

AD21

1234567891011121314151617181920212223242526272829

PCI_AD22

PCI_AD20

PCI_AD21

R25
50

1 2

C11 .1UF

4

TXD+

AVDD

AVDD25

ISOLATEB

AD20

AD19

VDD

VDD25

AD18

AD17

PCI_AD18

PCI_AD16

PCI_AD17

PCI_AD19

12

12

R24
50

PROPRIETARY NOTE

TXD-

RXIN-

AVDD

RXIN+

AVDD25

TRDYB

FRAMEB

IRDYB

AD16

CBE2B

PCI_TRDY#

PCI_IRDY#

PCI_FRAME#

PCI_C/BE#2

PCI_DEVSEL#

LAN_RD+
LAN_RD-

LAN_TD+
LAN_TD-

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

GND

DEVSELB

C19
.1UF

R217

1.69K_1%

RTT2

RTSET

GND

STOPB

PCI_PERR#

PCI_STOP#

3

AVDD-1

AVDD-2

AVDD-3

12

LAN_X1
LAN_X2
VCTRL
AVDD25

+2.5VLAN

51

X1

X2

AVDD

AVDD25

VDD

AD15

CBE1B

PCI_AD14

PCI_AD15

12

12

NCNCNC

GND

PMEB

VCTRL

AD14

AD13

AD12

AD11

PCI_AD12

PCI_AD11

PCI_AD13

+3VLAN

C352
.1UF

1
2
3
4
5
6
7 10

+3V

C18
.1UF

GND

RTT3

PAR

SERRB

PERRB

PCI_PAR

PCI_SERR#

12

VDD25

AUX
EECS
EESK

EEDI

EEDO

AD0
AD1

GND

AD2
AD3

VDD25

VDD

AD4
AD5
AD6

VDD25

VDD

AD7

CBE0B

GND

AD10

AD9

AD8

30

PCI_AD10

PCI_AD8

PCI_AD9

U23

RD+
RD­CT
NC
NC
CT
TD+ TX+

Pulse H0013

3

RTL8100-L

RX+

U6

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31

Layout Note
H0013 pls close to
conn.

RX-

CT
NC
NC

CT
TX-TD-

16
15
14
13
12
11

98

C295
.1UF

AUX

PCI_AD0
PCI_AD1

PCI_AD2
PCI_AD3

PCI_AD4
PCI_AD5
PCI_AD6

PCI_AD7

R17

75

12

C306
.1UF

12

+3V

12

12

R18
75

LAN_GND

12

R224

5.6K

RJ45_RX+
RJ45_RX-

RJ45_TX+
RJ45_TX-

1 2

L28 4.7UH

1 2

L27 4.7UH

1 2

L25 4.7UH

C304
.1UF

LAN_EECS
LAN_EECLK
LAN_EEDI
LAN_EEDO

+3VLAN

C333

4.7UF_10V_1206

ACTIVITY#

LINK10_100#

PCI_C/BE#0 <17,22,23,28,29>

2

Y2
25 MHz

LAN_X1 LAN_X2

12

C312
18PF

U5

1

CS

2

SK

3

DI

4

DO

2

2

B

9346

2

8

VCC

7

NC

6

NC

5

GND

C

10K

47K

E

3 1

+3V

C

10K

B

47K

E

3 1

+3V

+3V

Q20

DTA114YKA

Q21

DTA114YKA

1

For 8100B only

+3VLAN

VCTRL

C288

4.7UF_10V_1206

@22UF_16V_1206

12

C311
18PF

For 3V LAN only

+3V

12

C21
.1UF

R187
510_0603

1 2

RJ45_RX-

RJ45_RX+
RJ45_TX­RJ45_TX+

R186

1 2

510_0603

12

12

R184

75

Title

Size Document Number Rev

B

Date: Sheet of

R185
75

LAN_GND

Termination plane should be copled to chassis ground

Compal Electronics, Inc.

LAN REALTEK RTL8100L

LA-1441

1 2
GND

+3VLAN

12

12

C348
.1UF

+2.5VLAN

12

12

C368
.1UF

JP5

12

Amber LED+

11

Amber LED-

8

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

10

Green LED-

9

Green LED+

AMP RJ45/RJ11 with LED

C248

1000P_2KV_1206

Q65
@2SA1036K

+2.5VLAN

C730

1 2

12

C347
1000PF

12

C351
1000PF

LANGND
12

1

C731
@0.1U

GND

R52

0_1206

C367
.1UF

C371
.1UF

C249

.1UF

+3V+3VLAN

12

C369

1000PF

12

C329

1000PF

SHLD4
SHLD3

SHLD2
SHLD1

12

C257

4.7UF_10V_0805

21 43Wednesday, March 06, 2002

+2.5VLAN

12

C332
.1UF

12

C349
.1UF

16
15

14
13

0.2

檔

A B C

@ 8P4R_4.7K

PCI_AD[0..31]<17,21,23,28,29>

PCI_AD[0..31]

+3V

RP31
1 8
2 7
3 6
4 5

+3V

D

+3V

12

C640

.01UF

12

C649

.01UF

12

C614

.01UF

12

12

C645

.01UF

C631
.01UF

E

12

12

12

12

C609

C642

.1UF

.1UF

C651
.1UF

C632
.1UF

1 1

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11

R411
@ 220

PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1

PCI_AD0
PCI_C/BE#3
PCI_C/BE#2
PCI_C/BE#1
PCI_C/BE#0
CLK_PCI_1394

1394_IDSEL

1394_PME#
PCI_SERR#
PCI_PAR

PCIRST#

1 2

2 2

PCI_AD16

R475 @ 100

3 3

1 2

1394_IDSEL

PCI_C/BE#3<17,21,23,28,29>
PCI_C/BE#2<17,21,23,28,29>
PCI_C/BE#1<17,21,23,28,29>
PCI_C/BE#0<17,21,23,28,29>

CLK_PCI_1394<12>

PCI_GNT#0<17,19>

PCI_REQ#0<17,19>

PCI_FRAME#<17,19,21,23,28,29>

PCI_DEVSEL#<17,19,21,23,28,29>

PM_CLKRUN#<17,19,23,25,28,29,32>

PCI_IRDY#<17,19,21,23,28,29>

PCI_TRDY#<17,19,21,23,28,29>

PCI_STOP#<17,19,21,23,28,29>

PCI_PERR#<17,19,21,23,28>

PIRQA#<15,17,19,23>

1394_PME#<32>

PCI_SERR#<17,19,21,23,28>

PCI_PAR<17,19,21,23,28,29>
PCIRST#<8,15,17,19,20,21,23,24,25,28,29,34>

CBRST#<15,21,23,24,28,29>

1 2

R410
@ 220

U48

@ TSB43AB22

22

PCI_AD31

24

PCI_AD30

25

PCI_AD29

26

PCI_AD28

28

PCI_AD27

29

PCI_AD26

31

PCI_AD25

32

PCI_AD24

37

PCI_AD23

38

PCI_AD22

40

PCI_AD21

41

PCI_AD20

42

PCI_AD19

43

PCI_AD18

45

PCI_AD17

46

PCI_AD16

61

PCI_AD15

63

PCI_AD14

65

PCI_AD13

66

PCI_AD12

67

PCI_AD11

69

PCI_AD10

70

PCI_AD9

71

PCI_AD8

74

PCI_AD7

76

PCI_AD6

77

PCI_AD5

79

PCI_AD4

80

PCI_AD3

81

PCI_AD2

82

PCI_AD1

84

PCI_AD0

34

PCI_C/BE3

47

PCI_C/BE2

60

PCI_C/BE1

73

PCI_C/BE0

16

PCI_CLK

18

PCI_GNT

19

PCI_REQ

36

PCI_IDSEL

49

PCI_FRAME

50

PCI_IRDY

52

PCI_TRDY

53

PCI_DEVSEL

54

PCI_STOP

56

PCI_PERR

13

PCI_INTA

21

PCI_PME

57

PCI_SERR

58

PCI_PAR

12

PCI_CLKRUN

85

PCI_RST

14

G_RST

89

GPIO3

90

GPIO2

PCI BUS INTERFACE

PLLGND1

PLLGND2

AGND

AGND

AGND

109

110

111

8

9

2035486278

VDDP

VDDP

VDDP

VDDP

TSB43AB22

AGND

AGND

AGND

AGND

DGND

DGND

117

126

127

128

172330

87

VDDP

CYCLEIN

PHY PORT 2

BIAS CURRENT

OSCILLATOR

FILTER

EEPROM 2 WIRE BUS

POWER CLASS

PHY PORT 1

DGND

DGND

DGND

DGND

DGND

DGND

DGND

DGND

445564

68

758393

33

101186

96

15

DVDD

27

DVDD

TEST7

CYCLEOUT

DGND

DGND

103

TEST17

TEST16

DVDD
DVDD
DVDD
DVDD
DVDD
DVDD

PLLVDD

AVDD
AVDD
AVDD
AVDD
AVDD

TPBIAS1

TPA1+

TPA1-

TPB1+

TPB1-

FILTER0
FILTER1

TPBIAS0

TPA0+

TPA0-

TPB0 +

TPB0 -

TEST9
TEST8

TEST3
TEST2
TEST1
TEST0

CPS

SDA

SCL
PC0

PC1
PC2

39
51
59
72
88
100
7
1
2
107
108
120

106

125
124
123
122
121

118

R0

119

R1

6

X0

5

X1

3
4
92
91
99

98
97

116
115
114
113
112

94
95

101
102
104
105

+3V

+3V

1 2

R434 @ 1K

1 2

C646 @ 0.1UF

R459@ 1K

1 2
1 2

R458 @ 1K
R453

@ 6.34K_1%

1 2

C650 @ 0.1UF

1 2

R424 @ 220

1 2

R425 @ 220

TPBIAS0

R423 @ 220

1 2

R422 @ 220

1 2

R437 @ 220

1 2

R439 @ 220

1 2

R441 @ 220

1 2

R442 @ 220

1 2

PLLVDD

C652

@ 0.01UF

Y4

@ 24.576MHz

R399
@ 56.2_1%

12

1 2

1 2

R394 @ 56.2_1%

C656

@ 15PF

C655

@ 15PF

R400
@ 56.2_1%

R395
@ 56.2_1%

C653
@ 4.7UF_10V_0805

1 2

12

L45

@ 0_0805

TPA0+
TPA0­TPB0+
TPB0-

C585 @ 220PF

+3V

12

R387
@ 5.11K_1%

C590
@ 0.33UF

TPB0­TPB0+
TPA0­TPA0+

JP12
1

1

2

2

3

3

4

4

@Molex SD-54030-0411

CLK_PCI_1394

4 4

12

R462

@22

1 2

C657

@.1UF

1 2

C605

@.1UF

TSB43AB22 USE

C654

@10PF

PROPRIETARY NOTE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

For TSB43AA22
C657,C605
change to 0
ohm to short
to GND

C

Title

Size Document Number Rev

B

D

Date: Sheet of

Compal Electronics, Inc.

IEEE 1394 Interface (RESERVE)

LA-1441

E

22 43Wednesday, March 06, 2002

0.2

檔

A B C

SLATCH<24>

RTCCLK<15,17,24,29>

SLDATA<24>

PCI_GNT#2<17,19>

PCI_REQ#2<17,19>
PCI_C/BE#3<17,21,22,28,29>
PCI_C/BE#2<17,21,22,28,29>
PCI_C/BE#1<17,21,22,28,29>
PCI_C/BE#0<17,21,22,28,29>

CLK_PCI_CB<12>
PCI_FRAME#<17,19,21,22,28,29>

1 1

S1_D[0..15]<24>
S1_A[0..25]<24>

S2_D[0..15]<24>
S2_A[0..25]<24>

2 2

3 3

+12VS

PCI_SERR#<17,19,21,22,28>

R478

1 2

100K

2

13

Q60 2N7002
S1_D[0..15]
S1_A[0..25]
S2_D[0..15]
S2_A[0..25]

S2_A16 SB_A16 SA_A16 S1_A16

Placement near
to PCMCIA
controller

S2_BVD1<24>
S2_BVD2<24>
S2_CD1#<24>
S2_CD2#<24>
S2_RDY#<24>
S2_WAIT#<24>

S2_WP<24>

S2_INPACK#<24>

S2_CE1#<24>
S2_CE2#<24>
S2_WE#<24>

S2_IORD#<24>

S2_IOWR#<24>

S2_OE#<24>
S2_VS1<24>

S2_VS2<24>
S2_REG#<24>
S2_RST<24>

S2_D0 S1_D0
S2_D1 S1_D1
S2_D2 S1_D2
S2_D3 S1_D3
S2_D4 S1_D4
S2_D5 S1_D5
S2_D6 S1_D6
S2_D7 S1_D7
S2_D8 S1_D8
S2_D9 S1_D9
S2_D10 S1_D10
S2_D11 S1_D11
S2_D12 S1_D12
S2_D13 S1_D13
S2_D14 S1_D14
S2_D15 S1_D15

S2_A0 S1_A0
S2_A1 S1_A1
S2_A2 S1_A2
S2_A3 S1_A3
S2_A4 S1_A4
S2_A5 S1_A5
S2_A6 S1_A6
S2_A7 S1_A7
S2_A8 S1_A8
S2_A9 S1_A9
S2_A10 S1_A10
S2_A11 S1_A11
S2_A12 S1_A12
S2_A13 S1_A13
S2_A14 S1_A14
S2_A15 S1_A15

R463

1 2

S2_A17 S1_A17
S2_A18 S1_A18

47

S2_A19 S1_A19
S2_A20 S1_A20
S2_A21 S1_A21
S2_A22 S1_A22
S2_A23 S1_A23
S2_A24 S1_A24
S2_A25 S1_A25

S2_BVD1 S1_BVD1
S2_BVD2 S1_BVD2
S2_CD1# S1_CD1#
S2_CD2# S1_CD2#
S2_RDY# S1_RDY#
S2_WAIT# S1_WAIT#
S2_WP S1_WP
S2_INPACK# S1_INPACK#

S2_VS2
S2_RST

PCI_DEVSEL#<17,19,21,22,28,29>

PCIRST#<8,15,17,19,20,21,22,24,25,28,29,34>

PCI_TRDY#<17,19,21,22,28,29>

PCI_IRDY#<17,19,21,22,28,29>
PCI_STOP#<17,19,21,22,28,29>

PCI_PERR#<17,19,21,22,28>

PCI_PAR<17,19,21,22,28,29>

C6B6A6F7A7B7A14C7F8

W10

B_D0/CAD27

U10

B_D1/CAD29

P10

B_D2/RSVD

H2

B_D3/CAD0

J1

B_D4/CAD1

J3

B_D5/CAD3

K1

B_D6/CAD5

K3

B_D7/CAD7

V10

B_D8/CAD28

R10

B_D9/CAD30

W11

B_D10/CAD31

H1

B_D11/CAD2

J2

B_D12/CAD4

J6

B_D13/CAD6

K2

B_D14/RSVD

K5

B_D15/CAD8

R8

B_A0/CAD26

W7

B_A1/CAD25

V7

B_A2/CAD24

W6

B_A3/CAD23

V6

B_A4/CAD22

U6

B_A5/CAD21

V5

B_A6/CAD20

U5

B_A7/CAD18

N1

B_A8/CC/BE1#

M3

B_A9/CAD14

L1

B_A10/CAD9

M1

B_A11/CAD12

T1

B_A12/CC/BE2#

N3

B_A13/CPAR

P1

B_A14/CPERR#

P5

B_A15/CIRDY#

P6

B_A16/CCLK

M6

B_A17/CAD16

N2

B_A18/RSVD

N6

B_A19/CBLOCK#

N5

B_A20/CSTOP#

R1

B_A21/CDEVSEL#

R2

B_A22/CTRDY#

R3

B_A23/CFRAME#

W4

B_A24/CAD17

R6

B_A25/CAD19

V9

B_BVD1/CSTSCHG

W9 J15

B_BVD2/CAUDIO A_BVD2/CAUDIO

H3

B_CD1#/CCD1#

R9

B_CD2#/CCD2#

V8

B_READY/CINT#

W8

B_WAIT#/CSERR#

U9

B_WP/CCLKRUN#

R7

B_INPACK/CREQ#

K6

B_CE1#/CC/BE0#

L2

B_CE2#/CAD10

P3

B_WE#/CGNT#

L5

B_IORD#/CAD13

M2

B_IOWR#/CAD15

L6

B_OE#/CAD11

U8

B_VS1#/CVS1

P7

B_VS2#/CVS2

P8

B_REG#/CC/BE3#

W5

B_RESET/CRST#

PAR

PERR#

SERR#

STOP#

IRDY#

TRDY#

RSTIN#

FRAME#

DEVSEL#

Slot

B

12
R473

@33

12
C695

@10PF

A10E2A5C8A15

PCLK

C/BE1#

C/BE0#

B13

C13

GNT#

REQ#

C/BE3#

C/BE2#

Interface

F14

DATA

PCI

E19

CLOCK

G15

F17

LATCH

SPKOUT

PCM_SPK# <31>

+3V

E11

D1

F18

VCCI

VCCP

VCCP

IRQ/DMA

12

C667
.1UF

W12

L3

U7

F3

VCC

VCC

VCC

VCC

Power

Slot

A

+3V

12

C668
.1UF

+3V

N15

G19

B14

C9

E7

M5

VCC

VCC

VCC

VCC

VCC

VCCB

C664 .1UF

C681 .1UF

CBRST#

A11

M17

VCCA

GRST#

A_D10/CAD31

A_A8/CC/BE1#

A_A11/CAD12

A_A12/CC/BE2#
A_A14/CPERR#

A_A15/CIRDY#

A_A17/CAD16

A_A19/CBLOCK#

A_A20/CSTOP#

A_A21/CDEVSEL#

A_A22/TRDY#

A_A23/CFRAME#

A_A24/CAD17
A_A25/CAD19

A_BVD1/CSTSCHG

A_CD1#/CCD1#
A_CD2#/CCD2#

A_READY/CINT#
A_WAIT#/CSERR#
A_WP/CCLKRUN#
A_INPACK/CREQ#

A_CE1#/CC/BE0#

A_CE2#/CAD10

A_WE#/CGNT#

A_IORD#/CAD13

A_IOWR#/CAD15

A_OE#/CAD11

A_VS1#/CVS1
A_VS2#/CVS2

A_REG#/CC/BE3#

A_RESET/CRST#

1 2

1 2

A_D0/CAD27
A_D1/CAD29

A_D2/RSVD
A_D3/CAD0
A_D4/CAD1
A_D5/CAD3
A_D6/CAD5

A_D7/CAD7
A_D8/CAD28
A_D9/CAD30

A_D11/CAD2
A_D12/CAD4
A_D13/CAD6

A_D14/RSVD

A_D15/CAD8
A_A0/CAD26

A_A1/CAD25
A_A2/CAD24
A_A3/CAD23
A_A4/CAD22
A_A5/CAD21
A_A6/CAD20
A_A7/CAD18

A_A9/CAD14
A_A10/CAD9

A_A13/CPAR

A_A16/CCLK

A_A18/RSVD

GND

AD5

AD3

AD2

AD1

AD0

G1

H5

4 4

PCI_AD1

PCI_AD2

PCI_AD0

S2_WP

1 2

R435 22K

S2_A23

R177

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

S2_VCC
S2_VCC

22K

PCI_AD[0..31]<17,21,22,28,29>

PCI_AD[0..31]

PCI_AD3

AD9

AD8

AD7

AD6

AD10

AD11

AD12

AD13

AD4

F2

G5H6G3

PCI_AD6

PCI_AD5

PCI_AD4

PCI_AD7

PCI_AD8

AD14

AD15

AD17

AD19

AD20

AD21

AD22

AD23

AD24

AD18

AD16

E13

F11

E10

F10A9B9F9A8F1F6B5E6A4C12E3F5G6E1

E9

B8

PCI_AD11

PCI_AD10

PCI_AD12

PCI_AD13

PCI_AD9

PCI_AD20

PCI_AD14

PCI_AD15

PCI_AD16

PCI_AD18

PCI_AD17

PCI_AD25

PCI_AD22

PCI_AD21

PCI_AD19

PCI_AD24

PCI_AD23

AD31

AD25

AD26

AD27

AD28

AD29

AD30

IDSEL

B12

A12

B11

C11

A13

E12

C10

12

R474

PCI_AD29

PCI_AD31

PCI_AD28

PCI_AD27

PCI_AD30

PCI_AD26

100

PCI_AD20

IRQSER/MFUNC3

DMAGNT#/MFUNC5

LOCK#/MFUNC4

RIOUT#/PME#

GND

GND

C14

J5

P2

G2

PCM_PME#
PCM1_LED

PCM2_LED

GND

P9

INTA#/MFUNC0

INTB#/MFUNC1

SUSPE ND #

DMARE Q# /MF UN C2

CLKRU N#/MF UNC6

F13

E14

C15

F15

E17

D19

A16

PCM_INTA#

C

B15

PCM_INTB#

GND

GND

GND

GND

GND

GND

GND

GND

V14

K18

E18

F12

B10

E8

C5

PCM_PME# <32>
PM_CLKRUN# <17,19,22,25,28,29,32>
PCM1_LED <33>
PCM_RI# <29>
INT_SERIRQ <17,19,25,32>
PCM2_LED <33>

R307 22K

2 1

D27

RB751V

D

S2_VCC
S1_VCC

CBRST# <15,21,22,24,28,29>

U51

H14
G18
G14
U11
R11
U12
R12
V13
H15
G17
F19
P11
V12
P12
W13
U13

J19
K14
K15
K19
L15
L17
L19
M15
W16
R14
W14
P14
N18
R17
N14
M14
P18
U15
T19
P15
R18
P17
P19
N17
N19
M18

H19
V11

H17
J17
J14
H18
L14

P13
R13
R19
W15
V15
U14

S1_VS1S2_VS1

J18

S1_VS2

M19
K17

S1_RST

L18

PCI1420-GHK

+3V

PCM_SUSP# <32>

D

E

S1_A23
S1_WP

R468

1 2

R470

+3V

R472
22K

D41

RB751V
D40

RB751V

+3V

12

C669
.1UF

+3V

12

C692
1000PF

22K

21

21

22K

PIRQA# <15,17,19,22>

PIRQB# <17,19,21>

CARDBUS
PCI1420

+3V

12

C691
.1UF

+3V

12

C687
1000PF

R466

1 2

47

Placement near
to PCMCIA
controller

S1_BVD1 <24>
S1_BVD2 <24>
S1_CD1# <24>
S1_CD2# <24>
S1_RDY# <24>
S1_WAIT# <24>
S1_WP <24>
S1_INPACK# <24>

S1_CE1# <24>
S1_CE2# <24>
S1_WE# <24>
S1_IORD# <24>
S1_IOWR# <24>
S1_OE# <24>
S1_VS1 <24>
S1_VS2 <24>
S1_REG# <24>
S1_RST <24>

PCM_INTA#

PCM_INTB#

R477

12

C693
.1UF

12

C688
1000PF

22K

Compal Electronics, Inc.

Title

Size Document Number Rev

B

LA-1441

Date: Sheet of

CardBus TI 1420

E

S1_VCC
S1_VCC

23 43Wednesday, March 06, 2002

12

C666
.1UF

12

C690
1000PF

0.2

檔

PCMCIA POWER CTRL.

1 2
1 2
1 2
1 2
1 2
1 2
1 2

S1_A[0..25]<23>

S1_D[0..15]<23>
S2_A[0..25]<23>
S2_D[0..15]<23>

S2_VPP

S1_VPP

C671
10UF_16V_1206

C678
10UF_16V_1206

C231
1UF_25V_0805

C226
.1UF
C225

.1UF

C227

.1UF

C660

.1UF

C638

.1UF

C641

.1UF

OCCB#<33>

+3V

12

12

1 2

R455
100K

S1_A[0..25]
S1_D[0..15]
S2_A[0..25]
S2_D[0..15]

W=30mils

C233
.01UF

W=30mils

C229
.01UF

12
C234

12
C663

56PF

56PF

12

C673

SLDATA<23>
SLATCH<23>

RTCCLK<15,17,23,29>

12

12

.1UF

12

C661

.1UF

+5V_CBS

+12V

+3V

C659

1UF_25V_0805

C228
1UF_25V_0805

S1_VCC

12

C662

1000PF

S2_VCC

12

C674

1000PF

U19

25

VCC_5V

7

12V

24

12V

1

5V

2

5V

30

5V

15

3.3V

16

3.3V

17

3.3V

3

DATA

5

LATCH

4

CLOCK

13

APWR_GOOD#

19

BPWR_GOOD#

18 12

OC# GND

TPS2206AI/TPS2216

@1UF_10V_0603

C718

AVPP
AVCC
AVCC
AVCC

BVPP
BVCC
BVCC
BVCC

RESET

RESET#

NC
NC
NC
NC

PCIRST#<8,15,17,19,20,21,22,23,25,28,29,34>

G_RST#<32>

+5V +5V_CBS

12

S1_VPP

8
9
10
11

S2_VPP

23
20
21
22

6
14

26
27
28
29

R533 @10K

1 2
1 2

R534

@10K

W=40mils

12

C240

4.7UF_10V_0805

W=40mils

12

C237

4.7UF_10V_0805

CBRST#

+3V

12

C116
.1UF

2 3

1
2
3 6
4

1
2
3 6
4

S1_VPP
S1_VCC

S2_VPP
S2_VCC

U37A

1

147

74LVC125

+3V POWER

JP29

1 2

PAD-OPEN 4x4m

U58

IN
IN
RST# SET
SHDN#

@MAX1857

U59

IN
IN
RST# SET
SHDN#

@MAX1857

S1_CD2#<23>

S1_WP<23>

S1_BVD1<23>

S1_BVD2<23>

S1_REG#<23>

S1_INPACK#<23>

S1_WAIT#<23>

S1_RST<23>
S1_VS2<23>

PCMRST# <33>

1 2

R348 0

1 2

R349 @0

8

OUT

7

OUT

5

GND

8

OUT

7

OUT

5

GND

CBRST#

80 mils80 mils

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

R354
10K

+3V

4.926V

R531
@100K_1%

1 2

1.25V

R532
@34K_1%_0603

1 2

CBRST# <15,21,22,23,28,29>

12

C719
@2.2UF_0805

S1_CD1#

@1000PF

S1_CD2#

@1000PF

S2_CD1#

@1000PF

S2_CD2#

@1000PF

S1_VPP S2_VPP

S1_VCC

S1_RDY#<23>

S1_WE#<23>

S1_IOWR#<23>

S1_IORD#<23>

S1_VS1<23>
S1_OE#<23>

S1_CE2#<23>

S1_CE1#<23>

S1_CD1#<23>

C670

1 2

C686

1 2

C689

1 2

C665

1 2

S1_CD2#
S1_WP

S1_D10
S1_D2
S1_D9
S1_D1
S1_D8
S1_D0
S1_BVD1

S1_A0
S1_BVD2
S1_A1
S1_REG#
S1_A2
S1_INPACK#
S1_A3

S1_WAIT#
S1_A4
S1_RST
S1_A5
S1_VS2
S1_A6
S1_A25

S1_A7
S1_A24
S1_A12
S1_A23
S1_A15
S1_A22

S1_A16

S1_A21
S1_RDY#
S1_A20
S1_WE#
S1_A19
S1_A14
S1_A18
S1_A13

S1_A17
S1_A8
S1_IOWR#
S1_A9
S1_IORD#

S1_A11
S1_VS1
S1_OE#
S1_CE2#
S1_A10

S1_D15
S1_CE1#
S1_D14
S1_D7
S1_D13
S1_D6

S1_D12 S2_D12
S1_D5
S1_D11
S1_D4

S1_CD1#

S1_D3

CARDBUS

SOCKET

JP19

A77

a68

A76

a34

A75

a67

A74

a33

A73

GND

A72

a66

A71

a32

A70

a65

A69

a31

A68

a64

A67

a30

A66

a63

A65

GND

A64

a29

A63

a62

A62

a28

A61

a61

A60

a27

A59

a60

A58

a26

A57

GND

A56

a59

A55

a25

A54

a58

A53

a24

A52

a57

A51

a23

A50

a56

A49

GND

A48

a22

A47

a55

A46

a21

A45

a54

A44

a20

A43

a53

A42

GND

A41

a19

A40

a52

A39

a18

A38

a51

A37

a17

A36

a50

A35

a16

A34

a49

A33

a15

A32

a48

A31

a14

A30

a47

A29

a13

A28

GND

A27

a46

A26

a12

A25

a45

A24

a11

A23

a44

A22

GND

A21

a10

A20

a43

A19

a9

A18

a42

A17

a8

A16

GND

A15

a41

A14

a7

A13

a40

A12

a6

A11

a39

A10

a5

A9

GND

A8

a38

A7

a4

A6

a37

A5

a3

A4

a36

A3

a2

A2

a35

A1

a1

PCMC154PIN

Title

Size Document Number Rev

B

Date: Sheet of

B77

b68

B76

GND

GND

GND

GND

GND

GND

GND

GND

GND

b34
b67
b33

b66
b32
b65
b31
b64
b30
b63

b29
b62
b28
b61
b27
b60
b26

b59
b25
b58
b24
b57
b23
b56

b22
b55
b21
b54
b20
b53

b19
b52
b18
b51
b17
b50
b16
b49
b15
b48
b14
b47
b13

b46
b12
b45
b11
b44

b10
b43

b9

b42

b8

b41

b7

b40

b6

b39

b5

b38

b4

b37

b3

b36

b2

b35

b1

S2_CD2#

B75

S2_WP

B74
B73

S2_D10

B72

S2_D2

B71

S2_D9

B70

S2_D1

B69

S2_D8

B68

S2_D0

B67

S2_BVD1

B66
B65

S2_A0

B64

S2_BVD2

B63

S2_A1

B62

S2_REG#

B61

S2_A2

B60

S2_INPACK#

B59

S2_A3

B58
B57

S2_WAIT#

B56

S2_A4

B55

S2_RST

B54

S2_A5

B53

S2_VS2

B52

S2_A6

B51

S2_A25

B50
B49

S2_A7

B48

S2_A24

B47

S2_A12

B46

S2_A23

B45

S2_A15

B44

S2_A22

B43
B42

S2_A16

B41
B40
B39
B38
B37

S2_A21

B36

S2_RDY#

B35

S2_A20

B34

S2_WE#

B33

S2_A19

B32

S2_A14

B31

S2_A18

B30

S2_A13

B29
B28

S2_A17

B27

S2_A8

B26

S2_IOWR#

B25

S2_A9

B24

S2_IORD#

B23
B22

S2_A11

B21

S2_VS1

B20

S2_OE#

B19

S2_CE2#

B18

S2_A10

B17
B16

S2_D15

B15

S2_CE1#

B14

S2_D14

B13

S2_D7

B12

S2_D13

B11

S2_D6

B10
B9
B8

S2_D5

B7

S2_D11

B6

S2_D4

B5

S2_CD1#

B4

S2_D3

B3
B2
B1

Compal Electronics, Inc

FCI PCMCIA SOCKET

LA-1441

S2_CD2# <23>
S2_WP <23>

S2_BVD1 <23>

S2_BVD2 <23>
S2_REG# <23>

S2_INPACK# <23>

S2_WAIT# <23>
S2_RST <23>
S2_VS2 <23>

S2_VCC

S2_RDY# <23>
S2_WE# <23>

S2_IOWR# <23>
S2_IORD# <23>

S2_VS1 <23>
S2_OE# <23>
S2_CE2# <23>

S2_CE1# <23>

S2_CD1# <23>

24 43Wednesday, March 06, 2002

0.2

檔

A

SUPER I/O SMsC FDC47N227

1 1

B

C

C713

1 2

1 2

R524
10K

+3V

PCIRST#<8,15,17,19,20,21,22,23,24,28,29,34>

LPCRST

.1UF

12

C714
.1UF

D

U55

5 6

VCC Y1

1

A1

3

A2

GND

NC7WZ14

E

21

1 2

R518 10K

LPC_RST#

LPCRST

4

Y2

2

D45

RB751V

+3VS

LPC_RST# <32>

1 2

1 2

R228

@33

C307

@22PF

LPC_AD[0..3]

LPC_FRAME#<17,32>

LPC_DRQ#1<17,19>

SUS_STAT#<15,17,21,34>

INT_SERIRQ<17,19,23,32>
PM_CLKRUN#<17,19,22,23,28,29,32>
CLK_LPC_SIO<12>

CLK_SIO14<12>

BT_DET#<27>

1 2

R195 10K

1 2

R196 10K

+3VS

+3VS

PID0<15>
PID1<15>
PID2<15>
PID3<15>

+3VS

C278

4.7UF_10V_0805
10V

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

1 2

R209 10K

CLK_LPC_SIO

CLK_SIO14

1 2

R520 10K

12

C294
.1UF

LPC_RST#

R248 10K

12

C338
.1UF

1 2

12

C276
.1UF

U29

20

LAD0

21

LAD1

22

LAD2

23

LAD3

24

LFRAME#

25

LDRQ#

26

PCIRST#

27

LPCPD#

50

GPIO12/IO_SMI#

17

IO_PME#

30

SIRQ

28

CLKRUN#

29

PCICLK

19

CLK14

48

GPIO10

54

GPIO15

55

GPIO16

56

GPIO17

57

GPIO20

58

GPIO21

59

GPIO22

6

GPIO24

32

GPIO30

33

GPIO31

34

GPIO32

35

GPIO33

36

GPIO34

37

GPIO35

38

GPIO36

39

GPIO37

40

GPIO40

41

GPIO41

42

GPIO42

43

GPIO43

44

GPIO44

45

GPIO45

46

GPIO46

47

GPIO47

51

GPIO13/IRQIN1

52

GPIO14/IRQIN2

64

GPIO23/FDC_PP

18

VTR

53

VCC

65

VCC

93

VCC

7

VSS

31

VSS

60

VSS

76

VSS

SMsC LPC47N227

PD0/INDEX#

PD1/TRK0

PD2/WRTPRT#

PD3/RDATA#

PD4/DSKCHG#

PD6/MTR0#

BUSY/MTR1#

PE/WDATA#

SLCT/WGATE#

ERROR#/HDSEL#

ACK#/DS1#

INIT#/DIR#

AUTOFD#/DRVDEN0#

STROBE#/DS0#

SLCTIN#/STEP#

DTR2#
CTS2#
RTS2#
DSR2#

TXD2
RXD2

DCD2#

DTR1#
CTS1#
RTS1#
DSR1#

TXD1
RXD1

DCD1#

IRMODE/IRRX3

IRRX2
IRTX2

RDATA#
WDATA#
WGATE#

HDSEL#

STEP#

DS0#

INDEX#

DSKCHG#

WRTPRT#

TRK0#
MTR0#

DRVDEN0
DRVDEN1

GPIO11/SYSOPT

RI2#

RI1#

DIR#

PD5
PD7

68
69
70
71
72
73
74
75

79
78
77
81
80
66
82
83
67

100
99
98
97
96
95
94
92

89
88
87
86
85
84
91
90

63
61
62

16
10
11
12
8
9
5
13
4
15
14
3
1

2
49

LPD0
LPD1
LPD2
LPD3
LPD4
LPD5
LPD6
LPD7

LPTBUSY
LPTPE
LPTSLCT
LPTERR#
LPTACK#

CTS#2

DSR#2

DCD#2
RI#2

DTR#1
CTS#1
RTS#1
DSR#1
TXD1
RXD1
DCD#1
RI#1

Base I/O Address

0 = 02Eh

*

1 = 04Eh

R223 1K

R213 1K

RDATA#
WDATA#
WGATE#

HDSEL#

FDDIR#

STEP#

DRV0#

INDEX#

DSKCHG#

WP#

TRACK0#

MTR0#

LPTBUSY <26>
LPTPE <26>
LPTSLCT <26>
LPTERR# <26>
LPTACK# <26>
INIT# <26>
LPTAFD# <26>
LPTSTB# <26>
SLCTIN# <26>

1 2

1 2

R247 10K

1 2

R208 1K

IRMODE <26>
IRRX <26>
IRTXOUT <26>

RDATA# <20>
WDATA# <20>
WGATE# <20>
HDSEL# <20>
FDDIR# <20>
STEP# <20>
DRV0# <20,33>
INDEX# <20>
DSKCHG# <20>
WP# <20>
TRACK0# <20>
MTR0# <20>
3MODE# <20>

12

+5VS

LPD[0..7]

DCD#1
RI#1
CTS#1
DSR#1

LPD[0..7] <26>

RP10

1 8
2 7
3 6
4 5

8P4R_4.7K

+3VS

CTS#2
DSR#2
DCD#2
RI#2

+5V

RXD1<29>
TXD1<29>

DSR#1<29>

RTS#1<29>
CTS#1<29>

DTR#1<29>

RI#1<29>

DCD#1<29>

RXD1
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1

RP11

1 8
2 7
3 6
4 5

8P4R_4.7K

JP24

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

@96212-1011S

+3VS

LPC_AD[0..3]<17,32>

2 2

3 3

CLK_SIO14

CLK_LPC_SIO

R249

10

1 2

C339

15PF

1 2

4 4

Compal Electronics, Inc.

Title

PROPRIETARY NOTE

A

B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

LPC SUPER I/O SMSC FDC47N227

Size Document Number Rev

B

LA-1441

Date: Sheet of

25 43Wednesday, March 06, 2002

E

0.2

檔

C7

@68UF_4V_B2

+3VS

+

FIR Module

12

IRMODE<25>

W=40mils

12

C1
@.47UF

1 2

R4 @10K

1 2

R3 @10K

IRMODE

The component's most place
cloely IRDA MODULE.

1

4
5
3

U1

VCC

MODE0
MODE1
FIR_SEL

AGNDGND

@HSDL-3600

LEDA

TXD

RXD

+3VS

12

12

R2

R5

@4.7_1206

@4.7_1206

FIR_VCC

W=40mils

10
27

IRTXOUT

9

IRRX

8
6

N.C

1/4W

12

R561
10K

(R561 For VCH ONLY)

IRTXOUT <25>
IRRX <25>

12

C259

+

@68UF_4V_B2

+5V_PRN

109876

12345

+5V_PRN

109876

12345

LPTSLCT
LPTPE
LPTBUSY
LPTACK#

RP7
10P8R_2.7K

+5V_PRN

AFD#/3M#
LPTERR#
LPTINIT#
LPTSLCTIN#

FD4
FD5
FD6
FD7

RP8
10P8R_2.7K

+5V_PRN

FD3
FD2
FD1
FD0

PARALLEL PORT

+5V_PRN

D4

2 1

+5VS

LPTSTB#<25>

R189
33

R188
33

LPD[0..7]

LPTINIT#

LPTSLCTIN#

RP6

1 8
2 7
3 6
4 5

8P4R_68

RP5
1 8
2 7
3 6
4 5

8P4R_68

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

INIT#<25>

SLCTIN#<25>

LPD[0..7]<25>

1 2

1 2

LPD0 FD0
LPD1 FD1
LPD2 FD2
LPD3 FD3

LPD7 FD7
LPD6 FD6
LPD5 FD5
LPD4 FD4

LPTAFD#<25>

LPTERR#<25>

LPTACK#<25>
LPTBUSY<25>

LPTPE<25>

LPTSLCT<25>

LPTSTB#
AFD#/3M#

FD0
LPTERR#

LPTINIT#
FD2
LPTSLCTIN#
FD3

FD4
FD5
FD6
FD7
LPTACK#
LPTBUSY
LPTPE
LPTSLCT

RB420D

R191

R190

33

R192

C251

2.2K
220PF

33

1

14

2

15

3

16

4

17

5

18

6

19

7

20

8

JP4

21

9

LPTCN-25

22
10
23
11
24
12
25
13

Title

Size Document Number Rev

Date: Sheet of

Compal Electronics, Inc.

PARALLEL PORT & FIR MODULE
LA-1441

AFD#/3M#
LPTERR#
LPTINIT#
LPTSLCTIN#

LPTSLCT
LPTPE
LPTBUSY
LPTACK#

FD0
FD1
FD2
FD3FD1

FD4
FD5
FD6
FD7

CP2
1 8
2 7
3 6
4 5

8P4C_220PF

CP1
4 5
3 6
2 7
1 8

8P4C_220PF

CP3
1 8
2 7
3 6
4 5

8P4C_220PF

CP4
1 8
2 7
3 6
4 5

8P4C_220PF

26 43Wednesday, March 06, 2002

0.2

檔

USB PORT

+5VS

USB_OC#0<18>

F4

POLYSWITCH_0.75A

12

C560
1000PF

USB_VCCA

12

12

R353

470K

R355

560K

12

C208
.1UF
USB_AGND

C153

150UF_E

F3

+

+5VS

POLYSWITCH_0.75A

USB_OC#3<18>

USB_VCCC

12

12

R194
470K

C279
1000PF

12

R197
560K

12

C263
.1UF

USB_CGND

C267

150UF_E

+

Bluetooth

RFOFF#<33,34>

L36

FBM-160808-121T
1 2
1 2

L34

12

C172
.1UF

BT_VCC

C201

@4.7UF_10V_1206

12

12

C721

C720

47PF

47PF

CHB4516G750_1806

BT_DETACH<33>

BT_WAKE_UP<33>

12

L35

4516

USB_PP2<18> BT_DET# <25>
USB_PN2<18>

BT_RESET#<33>

BT_VCC

12

USB2_D+
USB2_D-

12

C171
@.1UF

USB0_D­USB0_D+

2

Q10
@SI2301DS

FBM-160808-121T

+3VALW+5VALW

1 3

12

+

USB_PN0<18>

USB_PP0<18>

R163
@100K

1 2

13

22K

2

Q40

22K

@DTC124EK

JP9

1
2
3
4

SUYIN USB Connector 2569A-04G3T-B

C535
.1UF

12

R171
100K

JP15

1 2
3 4
5 6
7 8
9 10

121411
13
15 16

12

C198
@.1UF

171918

20

@ HRS DF15-08-20DS-065V

+5VS

USB_OC#1<18>

USB_PN3<18>

USB_PP3<18>

F2

POLYSWITCH_0.75A

12

USB_PN1<18>

USB_PP1<18>

C273
1000PF

USB_VCCB

12

12

USB3_D­USB3_D+

R203
470K

R204
560K

USB1_D­USB1_D+

L19 FBM-160808-121T

1 2
1 2

L18

FBM-160808-121T

L13

CHB4516G750_1806

4516

12

C272

C281

150UF_E

.1UF

USB_BGND

L16

FBM-160808-121T

1 2
1 2

L15

FBM-160808-121T

L14

CHB4516G750_1806

4516

12

12

C271
.1UF

+

12

12

C725

C275
.1UF

C724
47PF

47PF

12

12

12

12

C723

C722

47PF

47PF

JP1

1
2
3
4
5
6
7
8

SUYIN 2553A-0BG5T-A

檔

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

USB PORT & BLUE TOOTH

Size Document Number Rev

B

LA-1441

Date: Sheet of

Compal Electronics, Inc

0.2

27 43Wednesday, March 06, 2002

+3VALW

EN_WOL#<32>

+3VS_MINIPCI

+3V

CHB1608B121

12

C629
@1UF_25V_0805

L9

1 2

0603

Q54
@SI2301DS

S

G

2

12

R169
@10

12

C180
@33PF

D

13

R454

1 2

@100K

C232
.1UF

CLK_MINIPCI

C224
.1UF

12

C200
.1UF

+5VS_MINIPCI

C178
@10UF_16V_1206

C177
10UF_16V_1206

+3VS_MINIPCI

L8

1 2

CHB1608B121

0603

+3VS_MINIPCI

+3V

+3.3VAUX

R385

1 2

12

C592
@1UF_25V_0805

+5VALW

WL_OFF#<33>

KILL_SW<33,34>

W=40mils

12

C191

.1UF

0

PCI_AD27<17,21,22,23,29>
PCI_AD25<17,21,22,23,29>

+5VS

+3V

+3V

5

1
2

3

PIRQD#<17,19,29>

CLK_MINIPCI<12>

PCI_REQ#1<17,19>

PCI_AD31<17,21,22,23,29>
PCI_AD29<17,21,22,23,29>

PCI_C/BE#3<17,21,22,23,29>

PCI_AD23<17,21,22,23,29>
PCI_AD21<17,21,22,23,29>

PCI_AD19<17,21,22,23,29>
PCI_AD17<17,21,22,23,29>

PCI_C/BE#2<17,21,22,23,29>

PCI_IRDY#<17,19,21,22,23,29>

PM_CLKRUN#<17,19,22,23,25,29,32>

PCI_SERR#<17,19,21,22,23>
PCI_PERR#<17,19,21,22,23>

PCI_C/BE#1<17,21,22,23,29>

PCI_AD14<17,21,22,23,29>
PCI_AD12<17,21,22,23,29>

PCI_AD10<17,21,22,23,29>

PCI_AD8<17,21,22,23,29>
PCI_AD7<17,21,22,23,29>

PCI_AD5<17,21,22,23,29>
PCI_AD3<17,21,22,23,29>

+5VS_MINIPCI

PCI_AD1<17,21,22,23,29>

L7 0_0603

+5VS_MINIPCI

1 2

U61

7SH08FU

PCI_AD27
PCI_AD25

1 2

0603

C728

.1UF

4

MINI_RST#

LAN RESERVED

PIRQD#
PCI_REQ#4

CLK_MINIPCI

PCI_REQ#1
PCI_AD31

PCI_AD29

PCI_C/BE#3

PCI_AD23
PCI_AD21

PCI_AD19
PCI_AD17

PCI_C/BE#2
PCI_IRDY#

PM_CLKRUN#
PCI_SERR#

PCI_PERR#
PCI_C/BE#1
PCI_AD14

PCI_AD12
PCI_AD10

PCI_AD8
PCI_AD7

PCI_AD5
PCI_AD3
PCI_AD1

W=30mils

W=30mils

1 2

R168 0

1 2

R164 @0

TIP

11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
51 52
53 54
55 56
57 58
59 60
61 62
63 64
65 66
67 68
69 70
71 72
73 74
75 76
77 78
79 80
81 82
83 84
85 86
87 88
89 90
91 92
93 94
95 96
97 98

99 100
101 102
103 104
105 106
107 108
109 110
111 112
113 114
115 116
117 118
119 120
121 122
123 124

PCIRST#

JP18

1 2

1 2

KEY KEY

3 4

3 4

5 6

5 6

7 8

7 8

9 10

9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
51 52
53 54
55 56
57 58
59 60
61 62
63 64
65 66
67 68
69 70
71 72
73 74
75 76
77 78
79 80
81 82
83 84
85 86
87 88
89 90
91 92
93 94
95 96
97 98
99 100
101 102
103 104
105 106
107 108
109 110
111 112
113 114
115 116
117 118
119 120
121 122
123 124

Mini-PCI SLOT

PCIRST# <8,15,17,19,20,21,22,23,24,25,29,34>
CBRST# <15,21,22,23,24,29>

RING

LAN RESERVED

W=40mils
MINI_RST#

MINI_IDSEL

W=20mils

W=30mils
PIRQC#

+5VS_MINIPCI

PIRQC# <17,19,29>
PCI_GNT#4 <17,19>PCI_REQ#4<17,19>

+3.3VAUX

PCI_GNT#1 <17,19>
WLANPME# <32>

PCI_AD30
PCI_AD28

PCI_AD26
PCI_AD24

1 2

R48 100

PCI_AD22
PCI_AD20
PCI_PAR
PCI_AD18
PCI_AD16

PCI_FRAME#
PCI_TRDY#
PCI_STOP#

PCI_DEVSEL#
PCI_AD15

PCI_AD13
PCI_AD11

PCI_AD9
PCI_C/BE#0

PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0

+3.3VAUX

12

C179
.1UF

PCI_AD30 <17,21,22,23,29>
PCI_AD28 <17,21,22,23,29>

PCI_AD26 <17,21,22,23,29>

PCI_AD18

PCI_AD24 <17,21,22,23,29>

PCI_AD22 <17,21,22,23,29>
PCI_AD20 <17,21,22,23,29>
PCI_PAR <17,19,21,22,23,29>
PCI_AD18 <17,21,22,23,29>
PCI_AD16 <17,21,22,23,29>

PCI_FRAME# <17,19,21,22,23,29>
PCI_TRDY# <17,19,21,22,23,29>
PCI_STOP# <17,19,21,22,23,29>

PCI_DEVSEL# <17,19,21,22,23,29>
PCI_AD15 <17,21,22,23,29>

PCI_AD13 <17,21,22,23,29>
PCI_AD11 <17,21,22,23,29>

PCI_AD9 <17,21,22,23,29>
PCI_C/BE#0 <17,21,22,23,29>

PCI_AD6 <17,21,22,23,29>
PCI_AD4 <17,21,22,23,29>
PCI_AD2 <17,21,22,23,29>
PCI_AD0 <17,21,22,23,29>

12

C173
@1000PF

W=40mils

12

C175
@.1UF

C181
.1UF

12

C236
@.1UF

12

檔

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Size Document Number Rev

B

LA-1441

Date: Sheet of

Compal Electronics, Inc

MINI_PCI

0.2

28 43Wednesday, March 06, 2002

+3V+3V

12

12

C699

C698

1000PF

.1UF

PWRST#

FCMODE

CLK_PCI_SD/SM

R511
@22

+3V

DSR#1<25>

CTS#1<25>

DTR#1<25>

12

C700
.1UF

C716 @ 0.1UF

1 2

R525 @10K

1 2

R493 @10K

1 2

R526 @0

1 2

@0
R536

1 2

R514 @100K

1 2

RXD1<25>

+5V

12

12

C701

1000PF

CBRST#<15,21,22,23,24,28>

PCIRST#<8,15,17,19,20,21,22,23,24,25,28,34>

12

C711
@10PF

12

C702

C703

.1UF

.1UF

+3V

+3V

IDSEL0

IDSEL1

R546 @0

PCTRST#

SD Transfer Conn.

SDCD0
SDCD2

SDCD# SDWP
SDPWR

RXD1
DSR#1
CTS#1
DTR#1
DCD#1 RI#1
SUSP# COM_RI#

12

12

C704

1000PF

PCI_AD[0..31]<17,21,22,23,28>

PCI_AD22 IDSEL0
PCI_AD22 IDSEL1

1 2
1 2

R547 @0

+3V

JP28

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30

@SD/COM

C705
.1UF

12

12

C707

C706

.1UF

1000PF

PCI_AD[0..31]

PCI_C/BE#0<17,21,22,23,28>
PCI_C/BE#1<17,21,22,23,28>
PCI_C/BE#2<17,21,22,23,28>
PCI_C/BE#3<17,21,22,23,28>

PCI_PAR<17,19,21,22,23,28>

PCI_FRAME#<17,19,21,22,23,28>

PCI_IRDY#<17,19,21,22,23,28>

PCI_TRDY#<17,19,21,22,23,28>

PCI_STOP#<17,19,21,22,23,28>

R496 @100

1 2

R497 @100

1 2

PM_CLKRUN#<17,19,22,23,25,28,32>
PCI_DEVSEL#<17,19,21,22,23,28>

CLK_PCI_SD/SM<12>

PIRQC#<17,19,28>

PIRQD#<17,19,28>

SM/SD_PME#<32>

R537 @100K

1 2

R538 @100K

1 2

R539 @100K

1 2

R540 @100K

1 2

R541 @100K

1 2

SDCD1
SDCD3
SDCLKSDCMD

SDLED

+3V

TXD1
RTS#1

檔

1 2

R542 @0

TXD1 <25>
RTS#1 <25>
RI#1 <25>DCD#1<25>

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3

CLK_PCI_SD/SM

SDCD0
SDCD1
SDCD2
SDCD3
SDCMD

R486 @1M

@.1UF
C729

+3V

U53

61728394960708192

VDD

VDD

VDD

VDD

VDD

VDD

VDD

1 2

SMC_VCC

103

113

124

VDD

VDD

VDD

VDD

VDD

Power

53

AD0

52

AD1

51

AD2

50

AD3

48

AD4

47

AD5

46

AD6

45

AD7

42

AD8

41

AD9

40

AD10

38

AD11

37

AD12

36

AD13

35

AD14

34

AD15

22

AD16

21

AD17

20

AD18

19

AD19

18

AD20

16

AD21

15

AD22

14

AD23

10

AD24

9

AD25

8

AD26

7

AD27

5

AD28

4

AD29

3

AD30

2

AD31

43

CBE0#

32

CBE1#

31

CBE2#

11

CBE3#

30

PAR

24

FRAME#

25

IRDY#

26

TRDY#

29

STOP#

13

IDSEL0

120

IDSEL1

55

CLKRUN#

27

DEVSEL#

125

PCICLK

123

PCIRST#

121

INTA#

122

INTB#

128

PME#

101

SDCD0

102

SDCD1

83

SDCD2

85

SDCD3

89

SDCMD

98

SDCLK

104

SDCD#

105

SDWP

69

SDPWR

SmartMedia I/FSystem I/FGPIO I/FTest Pins

PCI I/F SD CARD I/F

SMD0
SMD1
SMD2
SMD3
SMD4
SMD5
SMD6

SMD7
SMCLE
SMALE
SMCE#

SMWE#

SMRE#

SMWP#

SMRB#
SMCD#
SMLVD

SMWPD#

SMEJSW#

SMLED#

SMLOCK#

SMEJCT#
SMVC3EN
SMVC5EN

CLK32

PWRST#

SUSPEND#

FCMODE
ROM_CS
ROM_SK

ROM_D

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7

TEST0
TEST1
TEST2
TEST3

86
90
93
95
99
96
94
91
75
78
77
80
79
84
82
100
88
73
74
107
109
106
72
71

59
56
57
58
68
67
66

110
111
112
114
115
116
117
119

126

NC

127

NC

61
62
63
64

1 2

U62

2

OUTPUT

INPUT

5

VCC

3

GND

@NC7S14

SMD0
SMD1
SMD2
SMD3
SMD4
SMD5
SMD6
SMD7
SM_CLE
SM_ALE
SM_CE#
SMWE#
SM_RE#
SM_WP#
SM_R/B#
SMCD#
SM_LVD
SMWPD#
SMEJSW#

R490 @100K

1 2

R491 @100K

1 2

R492 @100K

SMVC3EN

PWRST#
FCMODE

R499 @100K
R500 @100K
R501 @100K
R502 @100K
R503 @100K
R504 @100K
R505 @100K
R506 @100K

1 2

1 2

R498 @100K

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2

R508 @0

SM_LED

4

12

R545

1

NC

RTCCLK <15,17,23,24>
SUSP# <32,36,41>

@1K

SMC_VCC

SMCD# SMEJSW#

+3V

+3V
+3V

When the serial
ROM interface is

+3V

not applied need
pull up.

SM_LED <34>

SM_LED

+3V SMC_VCC

SMVC3EN

R523

@ 0

1 2

+3V
+3V
+3V

U52

3

VIN

4

VIN/CE

2

GND

@RT9701-CB

+3V

2

1

VOUT

5

VOUT

@ 0.1UF

R487 @100K

1 2

SMC_VCC

C708

+3V

10K

47K

13

12

C726 @1000PF

1 2

SMCD#

SMD4
SMD5

SMD3
SMD6
SMD2
SMD7
SMD1
SM_LVD
SMD0

SM_WP#
SM_R/B#
SMWE#
SM_RE#
SM_ALE
SM_CE#
SM_CLE

1 2

R488 @10K

D46

@HSMB-C110 BLUE

Q64

@DTC114YKA

12

C709
@1000PF

@10UF_16V_1206

SMWPD#

SMD0
SMD1
SMD2
SMD3

SMD4
SMD5
SMD6
SMD7

SM_CLE
SM_ALE
SM_WP#
SM_LVD

21

C717

RP34
1 8
2 7
3 6
4 5

@8P4R_100K*

RP35
1 8
2 7
3 6
4 5

@8P4R_100K*

RP36
1 8
2 7
3 6
4 5

@8P4R_100K*

R543 @110

GND

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

1122333445465768797108

VSS

VSS

VSS

118

@TC6371AF

PCM_RI#<23>

+3V +3V

R509

@10K

D43

1 2

2 1

@RB751V

COM_RI#

R510

@10K

1 2

13

D

2

G

S

Q62
@2N7002

RING# <32>

Compal Electronics, Ltd.

Title

Size Document Number Rev

B

LA-1441

Date: Sheet of

SM_CE#
SMWE#
SM_RE#

SM_R/B#

TOSHIBA SD+SM(RESERVE)

RP37
1 8
2 7
3 6
4 5

@8P4R_100K*

1 2

R494 @10K

12

12

R535
@1K

JP14

12

VCC

11

PCD#

13

I/O4

10

VSS

14

I/O5

9

I/O3

15

I/O6

8

I/O2

16

I/O7

7

I/O1

17

LVD

6

I/O0

18

GND

5

WP#

19

RDY

4

WE#

20

RD#

3

ALE

21

CE#

2

CLE

22

VCC

1

VSS

23

GND

24

WPRO#

@SmartMedia Slot

SMC_VCC

29 43Wednesday, March 06, 2002

+5VS

0.2

C580

4.7UF_10V_0805

INT_CD_L<20>
INT_CD_R<20>

1 2

C606 1000PF

MD_SPK<15>

12

LINE_IN_L<31>
LINE_IN_R<31>

MIC<31>

1 2

C604 1UF_25V_0805

MONO_IN<31>

IAC_RST#<15,17>

IAC_SYNC<15,17>

IAC_SDATAO<15,17>

EAPD<31>

12

C577
.1UF

+5VS+5VS

R418 6.8K
R402 6.8K

R417 6.8K
R403 6.8K
R405 6.8K
R408 6.8K

R406 20K
R407 20K

MIC

R379 100

U40

4

VIN

2
7 1
8

SENSE

DELAY
ERROR CNOISE
ON/OFF#

SI9182

12
12

12
12
12
12

12
12

R404 2.4K
R393 10K

12

VOUT

GND

CD_L_R

CD_GNA

12
12

5
6

3

12

C565
.1UF

AUD_VREF

1 2

C597 1UF_25V_0805

1 2

C598 1UF_25V_0805

1 2

C595 1UF_25V_0805

CD_R_R

1 2

C596 1UF_25V_0805

1 2

C602 1UF_25V_0805

1 2

C603 1UF_25V_0805

AUD_VREF
1 2

C600 1UF_25V_0805

12

VDDA

C564
.1UF

12

12

C552

4.7UF_10V_0805

L37

1 2

CHB2012U170

C599

4.7UF_10V_0805

U41

14
15
16
17
23
24
18
20
19
21
22
13
12

11
10

5

45
46

47
48

4
7

VDDA

AVDD_AC97

25

38

AVCC

AUX_L
AUX_R
VIDEO_L
VIDEO_R
LIN_IN_L
LIN_IN_R
CD_L
CD_R
CD_GNA
MIC1
MIC2
PHONE
PC_BEEP

RESET#
SYNC
SDATA_OUT
ID0#

ID1#
EAPD#
S/PDIF_OUT
GND

GND

AC97 Codec

VDDC

12

C579

.1UF

1

9

VCC

LINE_OUT_L

LINE_OUT_R

MONO_OUT

HP_OUT_L

HP_OUT_R

BIT_CLK

SDATA_IN

XTL_IN

XTL_OUT

AFLT1
AFLT2

VREFOUT

REFFLT

FLT3D

BPCFG

FLTO

AGND
AGND

CS4299A

FLTI

VCC

LINEL

35

LINER

36
37
39
41

6
8
2

3
29
30
28
27
32

31
33
34
43

NC

44

NC

40

NC

26
42

AVCC

R124

1 2

0_0603

12

C568

4.7UF_10V_0805

12
1 2
1 2
1 2
1 2

12

R374 22

1 2

R377
22

1 2

1 2

C589 1000PF

NPO

C583 1000PF

C576

12

1000PF

NPO

+3VS

C571
1000PF
C573
1000PF
C567

4.7UF_10V_0805
C566

4.7UF_10V_0805
C557
1UF_25V_0805
C559
1000PF

R81 10K

1 2

1 2

NPO

1 2

R396 0

LEFT
RIGHT

IAC_BITCLK <15,17>

C570
22PF

Y3

24.576MHz

C572
22PF

R380
@100K

1 2

LEFT <31>
RIGHT <31>
MD_MIC <15>

NPO

NPO

AUD_VREF

12

12

C581
.01UF

IAC_SDATAI0 <17>

C574

1UF_25V_0805

12

12

C584

C591

1UF_25V_0805

.1UF

L44 CHB2012U170

1 2

L40 CHB2012U170

1 2

L38 CHB2012U170

1 2

AUD_VREF

12

12

C593
.1UF

C594

4.7UF_10V_0805

CD_GNA

R427

12

R416

3.3K
12

0

R415

3.3K

CD_AGND<20>

12

檔

PROPRIETARY NOTE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Size Document Number Rev

B

Date: Sheet of

Compal Electronics, Inc.

LA-1441

AC97 CODEC

30 43Wednesday, March 06, 2002

0.2

A B C

+5VS

U56

VOL_OP

C712

4 4

3 3

@1000PF

LM7111

LEFT<30>

RIGHT<30>

25

3

+

1

4

-

R432 100K

1 2

C610 .47UF

1 2
1 2

C643 .47UF

R512

1.65K

1 2

C644 .47UF

VOL_AMP <32>

VOL_OP
INTSPK_L1
INTSPK_R1

1 2

C615 .47UF

1 2

W=40Mil

R513

10K

1 2

12

C613
@.1UF

U3-5
U3-23
U3-6
U3-20

C630

12

.047UF_0805

L51

1 2

CHB3216U121

12

C601
.1UF

7
18
19

2

3

4
21

5
23

6
20

17

12

C612

4.7UF_10V_0805

U46

PVDD

SHUTDOWN#
PVDD
VDD

PC-ENABLE
VOLUME
LOUT+
ROUT+
LLINEIN
RLINEIN
LHPIN
RHPIN

CLK

TPA0132

SE/BTL#

PC-BEEP

BYPASS

LOUT-

ROUT-

GND
GND
GND
GND

RIN

+5VS

LIN

22
15
14
11
9
16
10
8

1

12
C618

12
13
24

INTSPK_R1
INTSPK_R2
INTSPK_L1
INTSPK_L2

SHUTDOWN#

NBA_PLUG

C637

1 2

INTSPK_L2
INTSPK_R2

.47UF

+5VS

.1UF

12
C625

12

R401

13

Q30

2N7002

.47UF

100K

2

12
C622

.47UF

JP16

1
2
3
4

ACES 85205-0400

EAPD <30>

R448 100K

INTSPK_L1

INTSPK_L2

12

INTSPK_R1

R444 33

INTSPK_R2

R443 33

VDDA

1 2

R446 33

1 2

R447 33

LINE_IN_R<30>
LINE_IN_L<30>

D

1 2

1 2

2

Q44 DTC314TK

10K

1 3

FBM-11-160808-700T

1 2

L46

1 2
L47
FBM-11-160808-700T

Q52 DTC314TK

1 3

2

Q43 DTC314TK

10K

1 3

Q53 DTC314TK

1 3

2

10K

12

C685
330PF

E

AMP & Audio Jack

Q42

2

10K

12

C680
330PF

32

2SB1188

1

1 2

R420 2.2K

12

R419

4.7K
10UF_16V_1206

12

C626

4.7UF_10V_0805

JP20

5
4
3

6
2
1

PHONEJACK

C620

12

R430

2.2K

12

D39

3

1

2

DAN217

LINE_IN JACK

+5VS

1 2

R479 1K
C633
150UF_6.3V_D2

1 2
1 2

C623
150UF_6.3V_D2

AVDD_AC97

MIC<30>

+
+

1 2

R480 47

1 2

R481 47

R457
18K_1%

1 2

1 2
R456
18K_1%

MIC

INTSPK_R1

MONO_IN <30>

4

+3V

12

R345
100K

1 2

R350 8.2K

.22UF

PCM_SPK#<23>

ICH_SPKR<18>

C539

BEEP#<32>

U37B

74LVC125

2 2

1 1

5 6

+3V POWER

+3V

C551

1 2

.1UF

147

U36A

21

+3V

147

74LVC14

+3V POWER

U36B

74LVC14

+3V POWER

12

C528

1 2

1UF_10V_0603

C586

1 2

1UF_10V_0603

C587

1 2

43

1UF_10V_0603

R333

1 2

560

R390

1 2

560

R391

1 2

560

VDDA

2

12

R389
10K

2 1

PROPRIETARY NOTE

12

R392
10K

12

12

3 1

RB751V

C611
R397
10K

10UF_16V_1206

C588

MONO_IN

1 2

1UF_10V_0603

Q34
2SC2411K

D33

R409

2.4K

1 2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

L49

FBM-11-160808-700T

L50

FBM-11-160808-700T

R464

100K_1%

1 2

L48
FBM-11-160808-700T

1 2
1 2

12

D

INTSPK_R1-3
INTSPK_L1-3INTSPK_L1

12

C648

1UF_10V_0603

NBA_PLUG

12

12

C697
330PF

2

C696
330PF

AVDD_AC97

Q47
2SC2411K

3 1
12

R476

2.2K

12

C694
220PF

Title

Size Document Number Rev

B

LA-1441

Date: Sheet of

JP23

5
4
3

6
2
1

PHONEJACK

12

R564

JP21

@2.2K

5
4
3

6
2
1

PHONEJACK

Compal Electronics, Inc.

AMP & Audio Jack

E

SPEAKER OUT
JACK

EXT.
MICPHONE

JACK

31 43Wednesday, March 06, 2002

0.2

檔

5

12

12

C374
.1UF

+RTCVCC

D D

12

C375
.1UF

C C

ICH_WAKE_UP#<17>

B B

A A

SM/SD_PME#<29>

1394_PME#<22>

PCM_PME#<23>

WLANPME#<28>

LAN_PME#<21>

C378
.1UF

EC_AVCC

GATEA20<17>

ECAGND

+5VALW

12

C430
.1UF

12

C510
.1UF

RC#<17>

1 2

R237 4.7K

1 2

R236 4.7K

JP25

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

@96212-1011S

12

C108
.1UF

L31

1 2

CHB1608U800

ECAGND

+3VS

R292
10K

1 2

D19 RB751V

D20

1
2

RB717F
D21

1
2

RB717F

D44 RB751V

1 2

C521 .01UF

1 2
C522 .01UF
+3VALW

1 8

2 7

3 6

4 5

5

12

C90
1000PF

+3VALW

R285
10K

1 2

2 1

RB751V

2 1

RB751V

21

RP16

8P4R_10K

EC_SMC2
EC_SMD2

EC_TINIT#
EC_TCK
EC_TDO
EC_TDI
EC_TMS

EC_URXD
EC_UTXD
EC_USCLK

1000PF

D25

D24

3

3

21

BATT_TEMPA
BATT_TEMPB

G_RST#
FRD#
SELIO#
FSEL#

+3VALW

+3VALW

C377

G20

RCL#

1 2

PCI_PME#

12

R265 10K

+3VALW

+3VS

+3VALW

LPC_AD[0..3]<17,25>

1 2

R79 0

1 2

R74 @0

PM_BATLOW#<17>
EC_LID_OUT#<19>

PCM_SUSP#<23>

PBTN_OUT#<19>

FAN_SPEED<34>

PM_SLP_S3#<12,17>

CAPS_LED#<34>

ARROW_LED#<34>

EC_RIOUT#<19>

PM_SLP_S1#<12,17>

BATT_TEMPA<40>
BATT_TEMPB<40>

PM_SLP_S5#<17>

LPC_AD[0..3]

LPC_FRAME#<17,25>

LPC_DRQ#0<17,19>

INT_SERIRQ<17,19,23,25>

C478 @22PF

4

INVT_PWM<15>

EN_WOL#<28>
EC_SMC1<33,40>
EC_SMD1<33,40>

LPC_RST#<25>

EC_SMC2<5,40>
EC_SMD2<5,40>

NUM_LED#<34>

DAC_BRIG<15>

VOL_AMP<31>

EN_DFAN<34>

4

EC_SMI#<19>

G_RST#<24>

A/B#USE<40>

ALI/MH#<40>
BLI/MH#<40>

ON/OFF<19,34>

1 2

BEEP#<31>

ACOFF<39>

51ON<34>

KSO16
KSO17

MP3#<34>

PC7<34>

ACIN<18,34,37,41>

RING#<29>

IREF<39>

EC_RST#<34>

PM_CLKRUN#<17,19,22,23,25,28,29>

EC_SCI#<19>

CLK_LPC_EC<12>

3

+3VALW EC_AVCC +RTCVCC

12

C53
.1UF

INVT_PWM

For PWM
EN_DFAN

EC_URXD
EC_UTXD
EC_USCLK
EC_SMC1
EC_SMD1

EC_SMC2
EC_SMD2

PCI_PME#
ATFOUT#

PC7
ACIN

RING#

SCR_LED#

VGA_SUSP#

BATT_TEMPA SYSON
BATT_TEMPB

VBATTA

VBATTB

BATT_CHGI

ADP_I

OEM

OEM

EC_TINIT#
EC_TCK
EC_TDO
EC_TDI
EC_TMS

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

1 2

R293 @0

LPCPD#<34>

R304 @33

51RST#

G20
RCL#

1 2

PROPRIETARY NOTE

51VDD

3445123

136

157

1661695

VCC4

VCC5

VCC6

AVCC

NC3

NC2

NC1

AGND

111220218586919297

96

ECAGND

3

161

IOPH0/A0/ENV0

VBAT

IOPH1/A1/ENV1
IOPH2/A2/BADDR0
IOPH3/A3/BADDR1

IOPH4/A4/TRIS

IOPH5/A5/SHBM

IOPK5/A13/BE0
IOPK6/A14/BE1

IOPK7/A15/CBRD

IOPL4/WR1#

IOPJ1/WR0#

IOPM2/D10
IOPM3/D11
IOPM4/D12
IOPM5/D13
IOPM6/D14
IOPM7/D15

PSCLK1/IOPF0
PSDAT1/IOPF1
PSCLK2/IOPF2
PSDAT2/IOPF3
PSCLK3/IOPF4
PSDAT3/IOPF5
PSCLK4/IOPF6
PSDAT4/IOPF7

KBSOUT10
KBSOUT11
KBSOUT12
KBSOUT13
KBSOUT14
KBSOUT15

32KX1/32KCLKOUT

NC9

NC8

NC7

NC6

NC5

NC4

IOPH6/A6
IOPH7/A7

IOPK0/A8

IOPK1/A9
IOPK2/A10
IOPK3/A11
IOPK4/A12

IOPL0/A16
IOPL1/A17
IOPL2/A18
IOPL3/A19

IOPI0/D0
IOPI1/D1
IOPI2/D2
IOPI3/D3
IOPI4/D4
IOPI5/D5
IOPI6/D6
IOPI7/D7

IOPJ0/RD#

SELIO#

SEL0#
SEL1#

IOPM0/D8
IOPM1/D9

KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7

KBSOUT0
KBSOUT1
KBSOUT2
KBSOUT3
KBSOUT4
KBSOUT5
KBSOUT6
KBSOUT7
KBSOUT8
KBSOUT9

32KX2

NC10

98

1 2

CHB1608U800

CLK

U34

GND1

173546

VDD

VCC1

VCC2

VCC3

GND2

GND3

GND4

GND5

GND6

GND7

122

137

159

167

32

IOPA0/PWM0

33

IOPA1/PWM1

36

IOPA2/PWM2

37

IOPA3/PWM3

38

IOPA4/PWM4

39

IOPA5/PWM5

40

IOPA6/PWM6

43

IOPA7/PWM7

153

IOPB0/URXD

154

IOPB1/UTXD

162

IOPB2/USCLK

163

IOPB3/SCL1

164

IOPB4/SDA1

165

IOPB7/RING#/PFAIL#

168

IOPC0

169

IOPC1/SCL2

170

IOPC2/SDA2

171

IOPC3/TA1

172

IOPC4/TB1/EXWINT22

175

IOPC5/TA2

176

IOPC6/TB2/EXWINT23

1

IOPC7/CLKOUT

26

IOPD0/RI1#/EXWINT20

29

IOPD1/RI2#/EXWINT21

30

IOPD2/EXWINT24

41

IOPD4

42

IOPD5

54

IOPD6

55

IOPD7

62

IOPJ2/BST0

63

IOPJ3/BST1

69

IOPJ4/BST2

70

IOPJ5/PFS#

75

IOPJ6/PLI

76

IOPJ7/BRKL_RSTO#

81

AD0

82

AD1

83

AD2

84

AD3

87

IOPE0AD4

88

IOPE1/AD5

89

IOPE2/AD6

90

IOPE3/AD7

2

IOPE4/SWIN

44

IOPE5/EXWINT40

93

DP/AD8

94

DN/AD9

99

DA0

100

DA1

101

DA2

102

DA3

105

TINT#

106

TCK

107

TDO

108

TDI

109

TMS

15

LAD0

14

LAD1

13

LAD2

10

LAD3

9

LFRAME#

8

LDRQ#

7

SERIRQ

19

LREST#

22

SMI#

23

PWUREQ#

24

IOPE6/LPCPD#/EXWIN45

25

IOPE7/CLKRUN#/EXWINT46

31

IOPD3/ECSCI#

5

GA20/IOPB5

6

KBRST#/IOPB6

18

LCLK

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

124
125
126
127
128
131
132
133

143
142
135
134
130
129
121
120

113
112
104
103
48

138
139
140
141
144
145
146
147

150
151

152
173

174
148

149
155
156
3
4
27
28

110
111
114
115
116
117
118
119

71
72
73
74
77
78
79
80

49
50
51
52
53
56
57
58
59
60
61
64
65
66
67
68

158
160
47

PC87591VPC

L32

KBA[0..18]<33>

ADB[0..7]<33>

KSI[0..7]<15>

KSO[0..15]<15>

KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7

KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15

KBA16
KBA17
KBA18
KBA19

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

FRD#

SELIO#
FSEL#

SUSP#

MMO_ON
VTT_ON

VTT_PWRGD#

ENVEE
ENBKL

KBD_CLK
KBD_DATA
PS2_CLK
PS2_DATA

TP_CLK
TP_DATA

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

CRY1
CRY2

12

C376
10PF

2

KBA[0..18]
ADB[0..7]
KSI[0..7]
KSO[0..15]

FSTCHG <39,40>

FRD# <33>
FWR# <33>

SELIO# <33>
FSEL# <33>

SYSON <36>
SUSP# <29,36,41>

TRICKLE <40>
VTT_ON <44>
VTT_PWRGD# <5,12>
ENVEE <15>
ENBKL <15>

TP_CLK <15>
TP_DATA <15>
LID_SW# <34>
CDON#/MP3 <34>

BADDR1(KBA3) BADDR0(KBA2)

0
0

*

1 1

R266

CRY2CRY1

1 2

20M

X1

32.768KHZ

1 2
12

2

1

1 2

+3V

R258 10K

MMO_ON

+3VS

ATFOUT#

D22 RB751V

R283 10K

21

D23 RB751V

21

VR_ON <43>

12

ATF_INT# <17>

KBA0
KBA1
KBA2
KBA3
KBA4
KBA5

I/O Address

Index
0
1
01

2E 2F

4E

(HCFGBAH, HCFGBAL) (HCFGBAH, HCFGBAL)+1

Reserved

ENV0 (KBA0) TRIS (KBA4)

IRE

R267

OBD 0

*

120K

DEV 0
PROG

SHBM(KBA5)=1: Enable shared memory with host BIOS
TRIS(KBA4)=1: While in IRE and OBD, float all the

signals for clip-on ISE use

C346
12PF

Compal Electronics, Inc.

Title

EC PC87591

Size Document Number Rev

B

LA-1441

Date: Sheet of

ENV1 (KBA1)
0
1

1

0
1

1

1

1 2

R129 @1K

1 2

R130 1K
R131 @1K

1 2

R132 1K
R133 @1K

1 2

R134 1K

Data

4F

0
0
0
0

32 43Wednesday, March 06, 2002

+3VALW

0.2

檔

PCM1_LED<23>
PCM2_LED<23>

KBA5
SELIO#

7SH32FU

C151

1 2

.1UF

KBA[0..18]<32>

ADB[0..7]<32>

+3VALW

2
1

C331

1 2

.1UF

3 5

FLASH_VCC

KBA11
KBA9
KBA8
KBA13
KBA14
KBA17
FWE#

KBA18
KBA16
KBA15
KBA12
KBA7
KBA6
KBA5
KBA4

SELIO#<32>

D12

1
2

DAN202U

U30

KBA[0..18]
ADB[0..7]

4

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

BUTTON1#<34>

INTERNET#<34>

SHDD_LED#<20>
PHDD_LED#<20>

DRV0#<20,25>

OCCB#<24>

KBA1
SELIO#

12

R243
100K

PCM_LED

3

EXTID0<20>
EXTID1<20>
EXTID2<20>

BT_WAKE_UP<27>

VOL_UP#<34>
VOL_DW#<34>
KILL_SW<28,34>

KBA3
SELIO#

+3VALW

1 2

R159 @0

1 2

R156 0
U15

A11
A9
A8
A13
A14
A17
WE#
VCC
A18
A16
A15
A12
A7
A6
A5
A4

@SST39VF040_TSOP

PCM_LED

+3VALW

147

4
5

+3VALW

147

12
13

R28

R29 @100K

+5VALW
+3VALW

OE#

A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0

A0
A1
A2
A3

U25B

74LVC32

U25D

74LVC32

R26 100K

1 2
1 2
1 2

R27

1 2

R557 @100K
R558 @100K

FRD#

32

KBA10

31

FSEL#

30

ADB7

29

ADB6

28

ADB5

27

ADB4

26

ADB3

25
24

ADB2

23

ADB1

22

ADB0

21

KBA0

20

KBA1

19

KBA2

18

KBA3

17

6

11

12
12

100K

100K

CC

DD

BID

FRD# <32>
FSEL# <32>

+3VALW

1 2

20

1A1 1Y1
1A2 1Y2

VCC
1A3 1Y3
1A4 1Y4
2A1 2Y1
2A2 2Y2
2A3 2Y3
2A4 2Y4

1G
2G

GND

10

+3VALW

20

1A1 1Y1
1A2 1Y2

VCC
1A3 1Y3
1A4 1Y4
2A1 2Y1
2A2 2Y2
2A3 2Y3
2A4 2Y4

1G
2G

+3VALW

20

1A1 1Y1
1A2 1Y2

VCC
1A3 1Y3
1A4 1Y4
2A1 2Y1
2A2 2Y2
2A3 2Y3
2A4 2Y4

1G
2G

U31

74LVC244

C316

1 2

.1UF

U32

GND

10

C290

1 2

.1UF

U24

GND

10

2 18
4 16
6 14

8 12
11 9
13 7
15 5
17 3

1
19

2 18
4 16
6 14

8 12
11 9
13 7
15 5
17 3

1
19

2 18

4 16

6 14

8 12
11 9
13 7
15 5
17 3

1
19

C315

.1UF

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

74LVC244

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

74LVC244

KBA18
KBA16
KBA15 KBA17
KBA12 KBA14
KBA7 KBA13
KBA6 KBA8
KBA5 KBA9
KBA4 KBA11
KBA3 FRD#
KBA2 KBA10
KBA1 FSEL#
KBA0
ADB0 ADB6
ADB1
ADB2 ADB4

U14

1

NC

2

A16

3

A15

4

A12

5

A7

6

A6

7

A5

8

A4

9

A3

10

A2

11

A1

12

A0

13

DQ0

14

DQ1

15

DQ2

16

VSS

29F040/SST39VF040_PLCC

RP12

DD

1 8

AA

2 7

BB

3 6

CC

4 5

8P4R_100K

1 2

C608 .1UF

FWE#

4

U44
7SH32FU

C158 .1UF

32

VCC
WE*

DQ7
DQ6
DQ5
DQ4
DQ3

FWE#

31
30

A17

29

A14

28

A13

27

A8

26

A9

25

A11

24

OE*

23

A10

22

CE*

ADB7

21
20

ADB5

19
18

ADB3

17

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+3VALW

+3VALW

1 2

FLASH_VCC

+5VALW

.1UF

C289

1 2

20

ADB0

3

8

ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

AA

C342

1 2

1UF_25V_0805

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

BB

OE#

A10

CE#
DQ7
DQ6
DQ5
DQ4
DQ3

VSS
DQ2
DQ1
DQ0

A0
A1
A2
A3

13 12
14 15
17 16
18 19

11

3
4 5
7 6

8 9
13 12
14 15
17 16
18 19

11

1

EC_SMC1<32,40>
EC_SMD1<32,40>

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

+3VALW

C284

1 2

U25A

.1UF

147

KBA2
SELIO# LARST#

KBA4
SELIO# LARST#

+3VALW

12

R398
100K

2

2N7002

1

3 5

1 3

D

FLASH_VCC

R433

1 2

2

100K

G

Q36

S

1
2

+5VALW

+3VALW

9

10

EC_FLASH# <18>
FWR# <32>

KBA11
KBA9
KBA8
KBA13
KBA14
KBA17
FWE#

KBA18
KBA16
KBA15
KBA12
KBA7
KBA6
KBA5
KBA4

74LVC32

1 2

147

74LVC32

+12VS

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

U25C

R268

20K

U16

A11
A9
A8
A13
A14
A17
WE#
VCC
A18
A16
A15
A12
A7
A6
A5
A4

@29F040_TSOP

U27

D0
D1 Q1

VCC
D2 Q2
D3 Q3
D4 Q4
D5 Q5
D6 Q6
D7 Q7

CLK
CLR

+5VALW

20

Q0

VCC

GND

10

2

Q0

GND

74HCT273

10

C243

1 2

.1UF

U26

2

74HCT273

+5VALW +5VALW

12

R206

4.7K

1 2

R221 0

+5VALW

12

R214

4.7K

EXTIDEPWR# <20>
MDC_DN# <15>
BT_DETACH <27>
RFOFF# <27,34>
BT_RESET# <27>

HDD_LED# <34>
2ND_CHGI_CD_FDD_LED# <34>

PWR_LED# <34>
2nd_BATT_LOW_LED#<34>
BATT_LOW_LED#<34>
BATT_CHGI_LED# <34>
WL_OFF# <28>

PCMRST# <24>
EN_LAN# <21>

C280

1 2

.1UF

U21

8

VCC

7

WC

6

SCL

5

SDA

NM24C16

3
4 5
7 6
8 9

1

D0
D1 Q1
D2 Q2
D3 Q3
D4 Q4
D5 Q5
D6 Q6
D7 Q7

CLK
CLR

FRD#
KBA10
FSEL#
ADB7
ADB6
ADB5
ADB4
ADB3

ADB2
ADB1
ADB0
KBA0
KBA1
KBA2
KBA3

Compal Electronics, Inc

Title

BIOS & EXT. I/O PORT

Size Document Number Rev

B

LA-1441

Date: Sheet of

GND

+5VALW

12

R205
100K

1

A0

2

A1

3

A2

4

12

R198
100K

33 43Wednesday, March 06, 2002

0.2

檔

5

+3VALW

12

R273
470K

+3VALW

12

R85
470K

EC_RST#

13

Q26

2

2N7002

U28

5

1
2

3

7SH08FU

4

LPCPD#

+3VALW

D D

PC7<32>

1 2

SUS_STAT#<15,17,21,25>

LPCPD#

R233 @0

C321 .1UF

PCIRST#<8,15,17,19,20,21,22,23,24,25,28,29>

C C

4

EC_RST# <32>

LPCPD# <32>

3

2

1

Switch Board Connector

ON/OFF<19,32>

2nd_BATT_LOW_LED#<33>

51ON<32>

RFOFF#<27,33>

KILL_SW<28,33>

ARROW_LED#<32>

INTERNET#<33>

VOL_DW#<33>

BATT_LOW_LED#<33>

HDD_LED#<33>

CDON#/MP3<32>

1 2

R19 @0

ACIN<18,32,37,41>

JP6

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40

SUYIN-80065A-040G2T

SMLED

51ON# <37>
LID_SW# <32>
MP3# <32>
SM_LED <29>
CAPS_LED# <32>
NUM_LED# <32>
BUTTON1# <33>
VOL_UP# <33>
PWR_LED# <33>
BATT_CHGI_LED# <33>
2ND_CHGI_CD_FDD_LED# <33>

+3VALW+5VALW
+3VS+3V

For PC87591 REV 0.A Only

FAN CONN.

+12V

12

R160

21

D37

Q33
2SA1036K

3.6K

1N4148

+3V

12

B B

12

C548
.1UF

EN_DFAN<32>

A A

EN_DFAN

1 2
R113
13K_1%

1
3

+5V

VCC

VEE

2 5

R347

7.32K_1%

1 2

C556 .1UF

U39

4

LMV321_SOT23-5

1 2

FAN_SPEED<32>

Compal Electronics, Inc.

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Switchs & Connectors

Size Document Number Rev

B

LA-1441

Date: Sheet of

檔

12

R369
10K

C157

.1UF

+5V

1

C

Q29

2

FMMT619

B

E

3

FAN1

D35
1N4148

2 1

1

2 1

1SS355

D38

JP10

53398-0310-FAN

34 43Wednesday, March 06, 2002

12

C569
@10UF_16V_1206

1
2
3

0.2

A

RTC Batt. Connector

D3
RB751V

21

+RTC_BATT

W=30mils

C141

1 2

12

.1UF

21

CHGRTC

W=30mils

D1
RB751V

+RTCVCC

1 1

12

C131
.1UF

BATT1

- +

RTCBATT

Place near ICH3-M

B

C

+3V

R105

47K

R101

12

330K

R102

1 2

330K

.22UF

+5V +3V

12

12

D

+3V +3V

147

U36C

C526

R106
47K

C113
.1UF

74LVC14

+3V POWER +3V POWER

+3V

147

U36E

65

1011

74LVC14

E

147

U36D

2
1

3 5

89

74LVC14

1 2

U35

7SH32FU

C111

.1UF

4

PM_RSMRST#

PM_RSMRST#<17>

H30

2 2

EMI FINGER

ST1

Screw Boss 070

3 3

J CPU Thermal Plane Screw Hold

H3

A Screw Hold

H11

L Screw Hold

4 4

H25

H12

H31

1

EMI FINGER

H18

1

Stand-Off 090

1

H28

1

C Screw Hold

H24

1

M Screw Hold

H32

1

EMI FINGER

H2

1

Stand-Off 115

J CPU Thermal Plane Screw Hold

H23

1

D Screw Hold

H14

1

N Screw Hold

H16

H33

H35

EMI FINGER

H8

Stand-Off 053

1

F Screw Hold

H13

O Screw Hold

1

EMI FINGER

ST2

1

Stand-Off 053

J CPU Thermal Plane Screw Hold

H1

1

G Screw Hold

1

O Screw Hold

H15

1

1

H27

1

1

H37

1

EMI FINGER

ST3

1

Stand-Off 053

H10

1

H4

1

I Screw Hold

H7

1

O Screw Hold

H6

H29

H17

H38

1

EMI FINGER

ST4

1

Stand-Off 090

J CPU Thermal Plane Screw Hold

H20

1

I Fixed Position Hold

1

1

1

1

H39

EMI FINGER

H9

1

F Fixed Position Hold

O Screw Hold

+3VS

C136

1

M Fixed Position Hold

H19

1

O Screw Hold

H22

1

H26

1

O Screw Hold

H5

1

H21

1

+5VS

12

R126
100K

12

12

C137

.01UF

12

C138

.1UF

VGATE<43>

CF11
SMD40M80

1

CF10
SMD40M80

1

FD2
FIDUCAL

1

R127

240K

5
3

CF18
SMD40M80

1

CF6
SMD40M80

1

FD1
FIDUCAL

1

MR#
PFI

CF15
SMD40M80

1

CF7
SMD40M80

1

FD3
FIDUCAL

1

12 11

1 2

U11
MAX6342

12

RST#

VCCGND

PFO#

13

+3V POWER

CF13
SMD40M80

1

CF8
SMD40M80

1

FD5
FIDUCAL

1

.1UF

6

4

U37D
74LVC125

CF16
SMD40M80

CF3
SMD40M80

FD4
FIDUCAL

U37C

10

74LVC125

9 8

+3V POWER

+3V

12

R97

R107

1 2

@0

CF2

CF4

SMD40M80

SMD40M80

1

1

1

CF5
SMD40M80

1

FD6
FIDUCAL

1

1

CF19
SMD40M80

1

1

CF20
SMD40M80

1

12

100K

R103
10K

SYS_PWROK <17>

ICH_VGATE <17>

CF1
SMD40M80

1

CF17
SMD40M80

1

CF9
SMD40M80

1

CF12
SMD40M80

1

Compal Electronics, Inc.

1

E HDD Frame Hold

1

E HDD Frame Hold

A

1

E HDD Frame Hold

1

E HDD Frame Hold

PROPRIETARY NOTE

B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

D

Title

RESET

Size Document Number Rev

B

LA-1441

Date: Sheet of

35 43Wednesday, March 06, 2002

E

0.2

檔

A B C

+3VALW To +3V Transfer

U47

VIN
VIN
VIN VHV

VON/OFF

SI4702DY

3

S2

4

S2

1

S1

7

12

C628

4.7UF_10V_0805

1 1

SYSON#

6
5 8

2

+3V+3VALW

12

C636

4.7UF_10V_0805

ON_GATE

12

C624

.01UF

12

C639
1UF_25V_0805

12

R438
100K

+12VALW

12

R440

1M

+5VALW To +5V Transfer

12

C246

4.7UF_10V_0805

SYSON#

U20

7

S2

VIN

6

S2

VIN

5 8

VIN VHV

S1

2

VON/OFF

SI4702DY

3
4

1

+5V+5VALW

C245

4.7UF_10V_0805
12

12

C242

.01UF

12

C247
1UF_25V_0805

ON_GATE

SYSON#

13

D

Q12

2

2N7002

G

S

D

+1.5V TO +1.5V_SW Transfer

+1.5V +1.5VS

U4

D
D
D
D

SI4800

SUSP

1

S

2

S

3

S

+5VS_GATE

4

G

12

R20
1K

13

D

Q5

2

2N7002

G

S

8
7
6
5

12

C16

4.7UF_10V_0805

12

C20
1UF_10V_0603

E

12

C23

4.7UF_10V_0805

12

C25

4.7UF_10V_0805

+3VALW

SUSP

12

C323

4.7UF_10V_0805

2 2

+3VALW To +3VS Transfer

U22

7

S2

VIN

6

S2

VIN

5 8

VIN VHV

S1

2

VON/OFF

SI4702DY

3
4

1

1UF_10V_0603

12

C268

C26
.1UF

12

C277
10UF_16V_1206

+5VS_GATE

12

12

R211
1M

12

C6
10UF_16V_1206

1 2

R212 100K

12

+5VALW To +5VS Transfer

+5VALW +5VS

SUSP

12

C658

4.7UF_10V_0805

3 3

C239
.1UF_25V_0805

1 2

4 4

+12VALW

12

C241

1000PF

SYSON

2

U50

VIN
VIN
VIN VHV

VON/OFF

SI4702DY

3

S2

4

S2

1

S1

7
6
5 8

2

+12VALW To +12V Transfer

+12VALW

12

R180
100K

G

2

12

R179
47K

13

D

G

Q13
2N7002

S

S

Q11

NDS352P

D

1 3

+12V

12

C235
1UF_25V_0805

12

C672

4.7UF_10V_0805

12

C621

.01UF

12

C238
1UF_25V_0805

+5VS_GATE

12

R436

330K

12

C675
.1UF

D

S

12

C677

4.7UF_25V_1206

Q2

13

2N7002

2

G

12

C682
.1UF_25V_0805

SUSP#

12

C679

4.7UF_25V_1206

SUSP

+12VALW To +12VS Transfer

+12VALW

12

R469
100K

2

12

R471
51K

13

D

2

Q59

G

2N7002

S

C258
10UF_16V_1206

+12V

12

+12VALW

S

G

Q58

NDS352P

D

1 3

+12VS

12

C683
1UF_25V_0805

+3VS

12

C260
10UF_16V_1206

C676

4.7UF_25V_1206

12

C684

1UF_25V_0805

SYSON#

+3VS+3V

12

R183
470

13

D

2

G

S

R182
470

13

D

2

G

S

2

G

C

Q16
2N7002

Q15
2N7002

12

13

D

S

R178
1K

Q14
2N7002

SUSP

SUSPSYSON#

R193
1K

13

D

2

Q19

G

2N7002

S

+5VS+5V

12

R465
1K

13

D

2

Q55

G

2N7002

S

+12VS+12V

12

13

D

SUSPSYSON#

2

G

S

+1.8V_ALW TO +1.8V_SW Transfer

R467
1K

Q57
2N7002

+1.8V

8
7
6
5

12

C14

4.7UF_10V_0805

SYSON<32>

D

U3

D
D
D
D

SI4800

SUSP

+1.8VS

1

S

2

S

3

S

4

G

12

13

D

2

G

S

+1.8V

12

2

G1

C22
1UF_10V_0603

C8
1UF_10V_0603

SUSP#<29,32,41>

12

C17

4.7UF_10V_0805

12

C10

4.7UF_10V_0805

SUSP#

+5VS_GATE

R23
1K

Q56
2N7002

C13

4.7UF_10V_0805

+3VALW

12

R210
10K

D1 S1

SYSON#

61

Q22A

SI1906DL

Title

Size Document Number Rev
Custom

Date: Sheet of

12

12

SYSON# <42>

Compal Electronics, Ltd.

DC-DC Interface / RTC Batt. Conn.

LA-1441

12

C24

4.7UF_10V_0805

12

C9

4.7UF_10V_0805

+3VALW

12

R216

4.7K

D2

SUSP

34

5

S2

36 43Wednesday, March 06, 2002

Q22B

SI1906DL

G2

E

0.2

檔

A B C

Vin Detector

D

PL1

PF1

PCN1

1 1

1

3

3

2

2DC-S026B201 2.5D 5P

PJP1

1 2

3MM

1

2

5A 32V UL/CSA FAST

12

BYS10-45

PD1

PC1

1000PF_50V

CHC4532U800_1812

1 2

PC2

100PF_50V

1 2

PL2

CHC4532U800_1812

PC3

1000PF_50V

VIN

100PF_50V

PC4

12

PR1
@10_1206

12

@RLZ24B

PZD1

PH1 under CPU botten side :

CPU thermal protection at 82 degree C
Recovery at 50(51) degree C

PR9

2.15K_1%

VL

12

PC7

0.1UF_50V

PR12

16.9K_1%

TM_REF1

PH1

10K_1%_0805

PC9

0.22UF_0805_16V

5
6

PR14

100K_1%

VS

84

+

-

PR10
47K_1%

PU1B
LM393M

PR13

100K_1%

MAINPWON

7

VL

MAINPWON <41,42>

CHGRTC

1 2

PR19
200

RTCVREF

3.3V

PC13
10UF_1206_10V

S-81233SGUP (SOT-89)

3

3

2 2

PC8

1000PF_50V

3 3

High 18.764 17.901 17.063
Low 17.745 16.903 16.038

84.5K_1%

12

PC5

PU2

1000PF_50V

2

2

1

1

20K_1%

PR18
200_0805

PC12
1UF_0805_25V

PR4

PR7

VIN

12

12

0.1UF_50V

2 1

PR6
22K

1 2

PC6

PZD4
RLZ16B

12

CHGRTCP

PR2
1M_1%

1 2

84

3

+

1

2

­PU1A

LM393M

RTCVREF

12

PR11
10K

3.3V

PD3
RB751V

VMBA<40>

VMBB<40>

51ON#<34>

2 1

PD4
RB751V

2 1

PZD3

RLZ6.2C

PR16
100K

1 2

PR17
22K

12

12

VS

12

12

12

PC10

0.22UF_1206_25V

PR3

10K

PZD2
RLZ3.6B

12

PR8
10K

PQ1

TP0610T

2

PR5
1K

1 2

PD2

RLS4148

13

VIN

21

PR15

33_1206

12

PC11

0.1UF_0805_25V

ACIN <18,32,34,41>

PACIN <39,40>

VS

PJP2

+12VALWP

+5VALWP

4 4

+3VALWP

2 1

JOPEN/+12V

PJP3

1 2

PAD-OPEN 4x4m

PJP4

1 2

PAD-OPEN 4x4m

+12VALW

+5VALW

+3VALW

(120mA,20mils ,Via NO.= 1)

(5A,200mils ,Via NO.= 10)

(5A,200mils ,Via NO.= 10)

+1_5VP

+1_8VP

+VTTP

PJP5

2 1

3MMA/CPU_IO

PJP6

2 1

3MMA/CPU_IO

PJP7

1 2

PAD-OPEN 4x4m

+1.5V

+1.8V

+VTT

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
INC.

(1.5A,60mils ,Via NO.= 3)

(3A,120mils ,Via NO.= 6)

(6A,240mils ,Via NO.= 12)

C

COMPAL ELECTRONICS, INC

Title

Connector / DC-DC Interface

Size Document Number Rev

B

Date: Sheet of

LA-1441 0.2

D

37 43Wednesday, March 06, 2002

檔

A B C

1 1

D

PC30

0.1UF_16V

Iadp=0~2.9A

PR20

0.02_2512_1%

12

PR27
10K

1 2

1 2

PC21

PR31

4700PF_50V

10K

1 2

1 2

PC24
2200PF_50V

PR37 10K

12

PR32
10K

12

10

11

12

1

2

3

4

5

6

7

8

9

PU3
MB3878

-INC2

OUTC2

+INE2

-INE2

FB2

VREF

FB1

-INE1

+INE1

OUTC1

OUTD

-INC1

B+

FBM-L11-453215-900LMAT_1812

1 2

24

+INC2

23

GND

22

CS

21

VCC(o)

20

OUT

19

VH

18

VCC

17

RT

16

-INE3

15

FB3

14

CTL

13

+INC1

PL3

PC22

0.1UF_50V

1 2

1 2

PR34
68K

1 2

PR38
47K

12

PC14

4.7UF_1210_25V

12

PR25
0

PC18
220PF_50V

1 2

1 2

PC19

0.1UF_0805_25V

PC25

0.1UF_0805_25V

1 2

1 2

PC27
1500PF_50V

12

PC15

4.7UF_1210_25V

FSTCHG <32,40>

PD6
1SS355

1 2

12

PR40
47K

12

PC16

0.1UF_0805_25V

PD8

RB051L-40

B++

12

36

241

PQ5
FDS4435

578

LXCHRG

PL4

22UH_SPC-1205P-220A

1 2

12

PC17
@1000PF

ACOFF#

PQ4

SI4835DY
1
2
3 6

4

1 2

PR23 10K

13

100K

100K

PQ6
DTC115EK

CC=0~2.52A

CV=16.84V(8 CELLS)

1 2

PR35

0.02_2512_1%

8
7

5

1 2

2

12

+

PC28

PC26

100UF_EC_25V

4.7UF_1210_25V

PR24 47K

ACOFF <32>

12

PC29

VIN

BATT+

12

4.7UF_1210_25V

PQ2

SI4835DY

VIN

12

PR21
10K

2 2

PACIN<37,40>

ACON<40>

3 3

8
7

5

ACOFF#

1 2

1 2

*

IREF=1.31*Icharge
IREF=0.73 ~ 3.3V

1SS355

IREF<32>

PD5

PR28
10K

P2 P3

1
2
36

4

2

G

PQ3

SI4835DY

1
2
3 6

12

4

PR22
200K

12

PR26
150K

13

D

PQ7
2N7002

S

PC20

0.1UF_16V

PR36
162K_1%

1 2

8
7

5

12

12

PR30
10K_1%

12

0.1UF_16V

PR39

100K_1%

PC23

12

PR29

24.9K_1%

12

12

12

PR41

47.5K_1%

4 4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
INC.

C

PR42
143K_1%

12

COMPAL ELECTRONICS, INC

Title

CHARGER

Size Document Number Rev

B

Date: Sheet of

ATW05 0.2

D

38 43Wednesday, March 06, 2002

檔

A

B

C

D

12

PC31
1000PF_50V

PJP8

1
2

+5VALWP

VL

PR64
270K

PQ16

DTC115EK

2

3
4
5
6
7

@BAS40-04

12

100K

100K

PD9

13

12

PC36

0.1UF_50V

A

TSA

12

1

3

74HC253

A/B#USE<32>

1 1

SUYIN 25063A-07G1-E 7P P2.5

2 2

ACON<39>

3 3

FSTCHG<32,39>

4 4

PF2

7A 24V UL/CSA FAST

12

PR47

PR48

100

100

1

2

2

PU4

7

1Y

16

VCC

1C0

1C1

6543101112131421

PR68
100K

1 2

1 2

PR73
100K

12

EC_SMD1
EC_SMC1

3

1C2

1C3

PQ17
DTC115EK

PR43
1K

PD10

@BAS40-04

9

2Y

2C0

2C1

2

VMBA

VMBA<37>

8
7

5

100K

2

PR55

10K

1 2

PR58
100K

1 2

PR62 4.7K

PR71

100K

1 2

PR76 4.7K

PQ8

FDS4435

100K

1 2

PR80

5.6M

PL5

BLM41P600S_1806

12

12

PC33

0.01UF_50V

EC_SMD1 <32,33>
EC_SMC1 <32,33>

GA<42> GB<42>

8

VL

12

GND

2C2

2C3S0S1

1EN

2EN

15

S1

VL

12

S0

13

100K

100K

4

1 2

13

1

1 2

PR67 5.6M

7

P5 P4

12

3
2

PU5B
LM393M

5
6

PQ18

13

1
2
3 6

12

PR45
39K

PD11

RLS4148

1 2

12

PC35

0.01UF_50V

13

100K

100K

1
2
36

PR51 22K

2

PQ12

HMBT2222A

PR53
10K

PQ14
DTC115EK

VS

PU5A

84

LM393M

+

-

+

-

DTC115EK

B

PQ9

FDS4435

4

RTCVREF

2

BATT+

GBGA

PR60

100K_1%

1 2

3.3V

12

PR69
10K

PR74

100K_1%

12

PC39
1000PF_50V

PR81
47K

PD19
RLS4148

8

8

7

7

5

5

2

PR56

10K

1 2

12

12

12

FDS4435

100K

100K

12

12

12

12

PQ10

VMBB

PR57
1M_0.5%

PR65
499K_1%

VMBA

PR70
1M_0.5%

PR78
499K_1%

VMBB <37>

PQ11

1
2
36

4

1 2

PR52 22K

13

2

PQ13

HMBT2222A

PR54

10K

13

PACIN <37,39>

TRICKLE <32>

12

PQ15
DTC115EK

12

PC37
100PF_50V

12

PC38
100PF_50V

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
INC.

FDS4435

4

C

PC34

0.01UF_50V

8
7

5

EC_SMD2<5,32>

EC_SMC2<5,32>

1
2
3 6

12

PR46
39K

PD12

RLS4148

1 2

8 CELLS BATTERY UVP
H 10.68V L 9.518V

BLM41P600S_1806

12

PD13

@BAS40-04

ALI/NIMH#

ALI/MH#<32>

BLI/NIMH#

BLI/MH#<32>

PL6

PR44

EC_SMD2

1K

12

12

PR49
100

1

3

12

PC32

PF3
5A 125V UL/CSA SLOW

12

PR50
100

EC_SMC2

2

PR66
@1K

12

PR79
@1K

12

Title

Size Document Number Rev

Date: Sheet of

1000PF_50V

PJP9

BLI/NIMH#ALI/NIMH#

BB/IAB/I

TSB

12

1

3

2

12

PR61
@47K

PD15

1

@BAS40-04

12

PR75
@47K

PD17

1

@BAS40-04

1
2
3
4
5
6
7

SUYIN 25063A-07G1-E 7P P2.5

PD14
@BAS40-04

+5VALWP

+3VALWP

3

2

+3VALWP

3

3

2

2

COMPAL ELECTRONICS, INC

Charger Slecter

B

ATW05 0.2

1 2

PD16

3

2

@BAS40-04

1 2

PD18

@BAS40-04

D

PR59

25.5K_1%

1

PR72

25.5K_1%

1

TSA

12

PR63
1K

BATT_TEMPA<32>

TSB

12

PR77
1K

BATT_TEMPB<32>

39 43Wednesday, March 06, 2002

檔

A

B

C

D

PC47

25

TRIP1

GND

VL

2

PR82
15K_1%

0.1UF_0805_25V

REF

8

9611

PC59 0.1UF_16V

0.85VREF

PR101
47K

22K

47K

STBY1

VS

24

VCC

STBY2

10

SCP

10PF_50V

PC70

0.047U_16V

31

B++

12

BYS10-45

PD23

PC42

4.7UF_1210_25V

+3VALWP

PC40

876

5

PR83
15K_1%

PC48

0.1UF_0805_25V

23

SCP

SOFT2

PGOD

131215

PC67

TRIP2

OUT2_U

OUT2_D

OUTGND2

FB2

14

PC56 0.01UF_50V

16

LH2

17

18

LL2

19

20

INV2

PR92
330

PC61
2200PF_50V

PR96

11.5K_1%

PR86 0

PR88 0

+3VALWP

PR99
@100K

PC54

@1000PF_50V

PR90

33.2K_1%

PR94
220

PC52

0.1UF_0805_25V

PC60 4700PF_50V

PC65

@150UF_D_6.3V

PQ20
SI4800

+

D

5

D

DDD

SSG

S

134

2

876

S

134

2

150UF_D_6.3V

DDD

SSG

4.7UF_1210_25V

10UH_SPC_1205P_100

PQ22
SI4810DY

PC66

+

PL7

PZD7

RLZ4.3B

PC41

0.1UF_0805_25V

12

12

+3.3V : Ipeak = 6.66A ~10A

MAINPWON

PR202
100K

PC121

1UF_0805_25V

PZD8
RLZ10C

12

C

PR204
100K

1UF_0805_25V

PR203
47K

PC122

COMPAL ELECTRONICS, INC

Title

5V/3.3V/12V

Size Document Number Rev

B

Date: Sheet of

PQ44

2

FMMT3904

3 1

2

PR205
47K

ATW05 0.2

D

MAINPWON <37,42>

5V_STBY

PQ45
FMMT3904

3 1

40 43Wednesday, March 06, 2002

3

INV1

FB1

123

330

VS

+5VALWP

PC46

2.2UF_0805_16V

21

22

VREF5

REG5V_IN

PU6

TPS5120

CT

SKIP/PWM #

5V_STBY

SOFT1

4

5

7

PC58 47P_50V

PC69 0.01UF_50V

5V_STBY

12

PR103
100KPC71

PR207
2K

B++

PQ43

DTA144WKA

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,
INC.

PC50

13

VS

PQ24
2N7002

DAP202U

2

VL

30

LH1

29

OUT1_U

28

LL1

27

OUT1_D

26

OUTGND1

2200PF_50V

11.5K_1%

PR102 150K

PD20

1

PR91

PC64

PR97

0.01UF_50V

B++

PC44

4.7UF_1210_25V

14

32

12

PC45

4.7UF_1210_25V

PQ21

SI4810DY

+

PC62

150UF_D_6.3V

SUSP#<29,32,36>

ACIN<18,32,34,37>

876

DDD

SSG

S

134

2

876

DDD

SSG

S

134

2

+

5

D

PQ19
SI4800

5

D

PC63
150UF_D_6.3V

100K

2

PQ23
DTC115EK

B

4.7UF_1206_16V

PR85 0

PC51 0.1UF_0805_25V

PR87 0

PC55

@1000PF_50V

PC57
3300P_50V

VL

PR100
47K

13

100K

2

PR89

57.6K_1%

PR93 430

PC43

2200PF_50V

1 1

12

PZD5

RLZ16B

PRA1
@0_0402

2 2

3 3

4 4

PRB1
0_0402

+12VALWP

PC68

4.7UF_1206_16V

PR95
75_1%

PR98
649_1%

2

Vout

SCP

470PF_0805_100V

2.2UF_1206_25V

PU7
AMS2906

ADJ Vin

1 3

PRA2
@0_0402

PQ25
TP0610T

1 3
12

PR105
330

A

PC49

PR84
22_1206

1 2

PD21 EC11FS2

PC53

A Type AMS2906
B Type XC6202

PRB2
0_0402

VIN

12

2

12

PT1

10UH_SDT-1205P-100-118

+5VALWP

12

PD22

BYS10-45

PZD6

RLZ6.2C

+5V : Ipeak = 6.66A ~ 10A

PC72

0.1UF_0805_25V

1 2

PR104 10K

VL

檔

A

B

C

D

+1_8VP

1 1

PC74

4.7UF_1206_25V

2 2

3 3

4 4

PQ26

SI3442DV

D

6

S

45
2
1

G

3

PU8A
LM358A

1

PC78

68PF_50V

GA<40>

GB<40>

13

13

PQ29

2N7002

PQ31

2N7002

+5VALWP

0

5.1K
PR107

12

PC75

84

3

+

2

-

1 2

PR111 5.1K

2

PR113
36K

PR119
309K 1%

2

PR124
100K

PC82

1UF_1206_25V

PR106

1 2

1 2

0.1UF_50V

VIN

1

PC76

220PF_50V

PR109

30.1K_1%

1 2

0.01UF_50V

PC77

8 Cells Charger OVP : 18.059V

VS

PU9A
LM393M

84

3

+

2

-

1000PF_50V

PC83

PR120
100K

+ PC73

PR118 0

+1.5V+-5%

47UF_D_6.3V

13

100K

100K

0.85VREF

PC84

1UF_0805_16V

+1_5VP

69.8K_1%

2

PQ27
DTC115EK

BATT+

PR116
1M_0.5%

PR108

12

1 2

PR110 0

PR121
100K_0.5%

VL

SYSON#

PR122

97.6K_1%

PH2 near main Battery CONN :

BAT. thermal protection at 73 degree C
Recovery at 50(51) degree C

VL

12

TM_REF2

PC119

0.22UF_0805_16V

13

PC117

0.1UF_50V

100K_1%

12

PR114
10K

PU13A
LM393M

SYSON# <36>

PC80

4.7UF_1206_25V

+5VALWP

12

PC118 1000PF_50V

PD24

RB751V

PC81

2200PF_50V

PQ32
2SA1036K

PR170

2.37K_1%

1 2

1 2

PR115

12

1K

31

2

PH2

10K_1%_0805

HMBT2222A

PR172
10K_1%

PQ30

2

VS

5

+

6

-

PR173 100K_1%

PR174

PQ28
SI3445DV

S

4 5

3

1

PR171
47K_1%

7

PU9B
LM393M

D

6
2

1

G

+5VALWP

84

3

+

2

-

PC85

0.01UF_50V

MAINPWON

VL

5UH-SPC-06704-5R0

LX18

1 2

12

PD25
RB051L-40

12

13

100K

PL8

100K

PQ33
DTC115EK

MAINPWON <37,41>

+1.8V+-5%

12

PR112
191K_1%

12

PR117
162K_1%

1 2

PR123 10K

SYSON#

2

+1_8VP

12

+

PC79
150UF_D_4V_FP

0.85VREF

SYSON# <36>

A

檔

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,

B

INC.

C

COMPAL ELECTRONICS, INC

Title

1.8V / 1.5V / OVP

Size Document Number Rev

B

Date: Sheet of

ATW05 0.2

D

41 43Wednesday, March 06, 2002

A

B

C

D

PC91

4.7UF_1210_25V

+3V

1 1

CPU_VID4<7>
CPU_VID3<7>
CPU_VID2<7>
CPU_VID1<7>
CPU_VID0<7>

2 2

VGATE

VR_ON<32>

3 3

4 4

PR125

0

PC86
@4700PF_50V

12

PR126
10K

1 2

PC87
@4700PF_50V

1 2

PR144

@0

PC123
@0.01UF_50V

1 2

PR147
150K

PR175
180K

CPU CONTROL MODE

MODE
DEEPER SLEEP
BATTEY SLEEP

PERFORMANCE SLEEP

BATTERY MODE

PERFORMANCE MODE

1 2

PR143
@10K

PR127
10K

PC88

@4700PF_50V

+3V
12

12

OFFSET
0mV

-56mV

-51mV

-16mV

-1.8mV

PR128
10K

1 2

1 2

PC89
@4700PF_50V

1 2

PR140 0

1 2

1 2

PR206@1K

PC102 4.7UF_1206_16V

PC105 1UF_0805_16V

249K_1%

150K_1%

RBOTTOM

X

16.2K

19.6K

61.9K
604K

PR129
10K

PR138 0

PC104 470PF_50V

PR150

PR155

PC90
@4700PF_50V

1 2

PR137 0

Vout(0A)

0.850

1.094

1.199

1.134

1.248

PR130
10K

1 2

PR136 0

1 2

PR145 51K

ADDA
X
1
1
0
0

PR132 10

PR133 0

1 2

21
22
23
24
25
14

12

17

20
11
12
15 10

PR154
0

ADDB
X
0
1
0
1

241

241

PQ36
SI4894DY

PQ40
SI4404DY

2

4.7UF_1210_25V

PR153
@0

1 2

*

*

PD27
1SS355

PC96

0.1UF_0805_25V

PC99 0.1UF_0805_25V

PC100 @0.01UF_50V

PR161
@61.9K_1%

(61.9K_1%)(604K_1%)

*

PR160
@16.2K_1%

1 2

GL2

1 2

578

3 6

241

PQ38

578

SI4404DY

3 6

241

GL3

1

NO2

2

NO3

3

NO1

4

INH

5 6

GND ADDB

*

BL1

PQ34
SI4894DY

V+

COM

NO0

ADDA

PU11
@MAX4524

(MAX4524)

*

578

3 6

241

BL2

PQ39

578

SI4404DY

3 6

241

10
9
8
7

PQ41

@DTC115EK

(DTC115EK)

PQ35
SI4894DY

1 2

13

100K

578

3 6

578

3 6

*

PR151
@10K

(10K)

100K

+5VALWP

PR131
0_0805

1 2

1 2

PR152

0

*

PR158

@19.6K_1%

PR135

1 2

PR141 0

1 2

1 2

PU10 MAX1718

D4
D3
D2
D1
D0
VGATE

3

TIME

2

SDN/SKIP
VDD

6

CC
OVP
REF
ILIM
GND TON

PR200 0

PR201 0 PR156 @0

VCC

POS

NEG

ZMODE

SUS

BST

27

LX

28

DH

26
16

DL

1

V+

9
4

FB

13
5
19
18
8

S1

7

S0

(19.6K_1%) (MAX4524)

21

20

1 2

PC101 4.7UF_1206_16V

* *

PR159
@604K_1%

1 2

2 1

PR157 0

PR162 @0

PC93

4.7UF_1210_25V

PC92

PR139

0.002_21515_1%(2W)

LC

PL9

0.7UF HK-RM136-22A0R7

PD28

EC10QS04

1 2

PR146
100

PC103
1000PF_50V

COM

1 2

PR149

*

@0

(0)

12

(0)

12

12

(0)

PC94

4.7UF_1210_25V

12

PC97

220UF_D_4V

1 2

12

*

+3VALWP

PM_GMUXSEL<7,17>

PM_DPRSLPVR <7,17>

H_DPSLP# <5,17>

B++

2200PF_50V

+

+

PC98
220UF_D_4V

PC120

0.1UF_0805_25V

PR142 0

PR148
0

(1K_1%)

PR176
1K_1%

CPU_COREP OUTPUT_ MODE

D3

0

0

0 0 1 1 0.900 1.60

0

0

1

1

1

1

1 1 0 0

1

1

1

PC95

MAX4322

0

0

1

10

1

0

0

0

1

1

1

1

PU14

+VCC_H_CORE

+5VALWP

5

3

+

4

-

2

12

D1

D0

0

0

1 1.70

000

1

0

0

1

0

0

1

1110

0

0

0

1

1

0

1

1

100.650

0

0

1

11

PR177
499_1%

12
12

PR178
1K_1%

VOLTS

D4 = 0D2

D4 = 1

0.975

1.75

0.950

1.65

0.925

0.875

1.55

0.850

1.50

0.825

1.45

0.800 1.40

0.775

1.35

0.7500

1.30

0.725

1.25

1.20

0.700

1.150.675

1.10

0.625

1.05

1.00

0.600

*

A

檔

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,

B

INC.

C

COMPAL ELECTRONICS, INC

Title

CPU_COREP

Size Document Number Rev

B

Date: Sheet of

ATW05 0.2

D

42 43Wednesday, March 06, 2002

5 4 3

D D

+5VALWP

PR163
0_0805

1 2

IO_BST
IO_GL4
IO_LX
IO_GL5

PC115

@0.1UF

PC109

4.7UF_1206_16V

PC111

0.1UF_0805_25V

IO_FB

4
3
2
1

PQ42
SI4834DY

5
6
7
8

21

14
19
1
20
13
12
11
9
5
48

PC114

PD29
1SS355

PR164 10

PC110

4.7UF_1206_16V

C C

VTT_PWRGD<5>

VTT_ON<32>

PR169

84.5K_1%

PR166 0

1 2

12

PR168
15K_1%

Vref 2.0V

PC113

0.1UF_16V

15
18
17
10

3
6
2
7

16

VCC
SKIP
V+
PGOOD
SHDN
ILIM
N/C
REF
TON

MAX1714A

PU12

VDD
BST

DH

LX

DL

PGND

N/C
N/C

OUT

FBAGND

@150PF_50V

2

PC106

0.1UF_0805_25V

PL10

10UH_SPC-1205P-100

PD30

EC10QS04

PC112

150UF_D_6.3V

2 1

FB 1.0V

+

PC107

4.7UF_1210_25V

PC108

4.7UF_1210_25V

(+1.25V : I_peak = 6A)

PR165

2.49K_1%

PR167
10K_1%

1

B++

+VTTP

B B

A A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,

3

Title

CPU_IOP

Size Document Number Rev

B

2

Date: Sheet of

Compal Electronics, Inc.

ATW05

43 43Wednesday, March 06, 2002

1

0.2

檔