Quanta RM5 Calpella Discrete, Studio XPS 1644, Studio XPS 1645 Schematic

1

2

3

4

5

6

7

8

PWA : Y507R
PWB : Y509R
SCH : Y510R

POWER

A A

AC/BATT CONNECTOR
BATT CHARGER

Calpella Intel Discrete Block Diagram

VER : D3A

PG 55
PG 45

CLOCK

SLG8SP585V

(QFN-64)

PG 15

FAN & THERMAL

EMC1422

(8P TSSOP)

PG 37

Clarksfield

(Qual Core)

SYSTEM POWER

PCH REGULATOR

+1.05V_PCH

DDR3 VR

+1.5V_SUS/+0.75V_DDR_VTT

Load Switch

+5V_SUS/+3.3V_SUS/+5V_RUN/
+3.3V_RUN/+1.5V_RUN/
+1.5V_GDDR

SYS VR

+5V_ALW2/+3.3V_ALW

PG 49

+5V_ALW/+15V_ALW

CPU VR

+1.1V_VTT

VCC Core

+VCC_CORE

VGA Core

+VCC_GFX_CORE

PG 51 PG 52

+1.1V_GFX_PCIE

REGULATOR

+1.8V_RUN

PG 46PG 47 PG 48

VGA VDDCI

+VDDCI

PG 50

PG 53PG 54

DDR3-SODIMM1

DDR3-SODIMM2

Subwoofer
CONN

B B

PG 40

MIC

Internal Speaker

Subwoofer AMP
MAXIM MAX9759

(16 Pin TQFN)

Amplifier

PG 13

PG 14

PG 40

TI TPA6040A4

(32 Pin QFN)

HP2

PG 39

Amplifier

HP1

TI TPA4411MRTJR

(20 Pin QFN)

PG 39

Camera + D-MIC

PG 35

TV CONN

C C

PG 33

USB CONN

USB/eSATA Combo

PG 33 & eSATA board

SATA-ODD

SATA-HDD

1394 CONN

CardReader
CONN

D D

PG 34

PG 34

PG 27

PG 27

PC Card/1394
RICOH R5U230

(48 Pin QFN)

6 x 6 mm

PG 26

800 / 1066 MHZ DDR III

800 / 1066 MHZ DDR III

AUDIO

IDT 92HD73C

IHDA

(56 LQFP)

9 x 9 mm

PG 38

USB2.0 [11]

USB2.0 [9]

USB2.0 x 2 [0:1]

USB2.0 [8]
SATA2 [A5]
SATA2 [A1]
SATA2 [A0]
PCIE [5]

SPI

(989 PGA)

PG 3,4,5,6

DMI x 4

Ibex Peak-M

PG 7,8,9,10,11,12

LPC

SIO

ITE ITE8512E

(128 Pin LQFP)

16 x 16 mm

PG 29

PCIEx16

PCIE [1]
USB2.0 [5]

PCIE [2]
USB2.0 [4]

PCIE [3]
USB2.0 [6]

PCIE [4]
USB2.0 [7]

PCIE [6]

SMBus [2]

AMD M96XT

PCI EXPRESS GFX

(962 FCBGA)

PG 17,18,19,20

DDR3 x 8 (1G, 64Mx16 bit)

(100P FBGA)

PG 21,22

WWAN MINI-CARD

WLAN Half MINI-CARD

UWB/BT MINI-CARD

Express Card

LAN

Broadcom BCM5784M

(68P QFN)

PAD &
SCREW &
SPRING

System
Reset
Circuit

PG 43PG 44

PS/2

RM5 MB PCB (rev D)RM5 MB PCB (rev D)

1

SPI ROM

2MB

(8 Pin SO8W)

2

3

Keyboard CIR Touchpad

PG 30 PG 30 PG 30

PG 35 PG 36

4

Media Button

5

RTCLED

6

HDMI

DP

LVDS

VGA

HDMI CONN.

DISPLAYPORT

Panel Connector

CRT CONN.

GPU THERMAL

ANALOG DEVICES ADM1032

(8 MSOP) 3 x 3 mm

PG 32

PG 31

PG 32

Express Switch

PG 28

RICOH R5538D001

(20 QFN) 4 x 4 mm

Magnetic RJ45

PG 41

To IO Board

(USB*2/ MIC/
HP2/ HP1/ LED)

Title

Title

Title

BLOCK DIAGRAM

BLOCK DIAGRAM

BLOCK DIAGRAM

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Calpella 3A

Calpella 3A

Calpella 3A

Date: Sheet

Date: Sheet

Date: Sheet

7

PG 42 PG 42

To Daughter Board

(Power Button/Speaker/
KB LED/Touch PAD/

PG 40

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

Media Button)

PG 23

PG 23

PG 24

PG 25

PG 20

PG 28

PG 35

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Table of Contents Power States

PAGE DESCRIPTION

Block Diagram

1
2

Front Page

3-6

CPU (Clarksfield)

7-12

PCH (IBex Peak-M)

13-14

A A

B B

C C

DDR3 SO-DIMM(204P)
Clock Generator

15

GPU (M96XT)

16-22

HDMI & DP

23

LCD connector

24

CRT

25

Card reader PCIe interface

26

Card reader & 1394 CONN

27

Express card

28

SIO (IT8512)

29
30

Flash/RTC/CIR
WLAN

31

WWAN/WPAN

32

USB & eSATA & TV

33

SATA HDD & ODD

34

KB/CCD/UI

35

LED

36
37

FAN/Thermal

38-40

Audio/CONN/Subwoofer (92HD73C).

41-42

LAN/RJ45 (BCM5784M)
System Reset Circuit

43

PAD & SCREW & SPRING

44

CHARGER (MAX8731A)

45

1.8V_RUN (TPS51218)

46

1.5_SUS/0.75(TPS51116)

47

1.1V_VTT(TPS51218)

48

1.05V_PCH (TPS51218)

49

VCC_CORE(MAX17036GTL+)

50
51

3.3V/5V/15V (MAX17020)
VGA_M97(MAX8792)

52

VDDCI_M97(TPS51218)

53

Run Power Switch

54
55

DCIN & Batt

56

XDP Connector

57

Power Block Diagram
SMBUS BLOCK

58

Power status

59

POWER PLANE

+PWR_SRC
+RTC_CELL
+3.3V_ALW
+5V_ALW
+15V_ALW
+3.3V_LAN
+5V_SUS
+3.3V_SUS
+1.5V_SUS +1.5V 3,5,13,14,47,52,54 SODIMM POWER
+0.75V_DDR_VTT
+5V_RUN
+3.3V_RUN
+1.8V_RUN
+1.5V_RUN
+1.1V_VTT
+1.05V_PCH
+VCC_CORE
+LCDVCC
+5V_MOD
+5V_HDD
+5V_ALW2

GND PLANE PAGE

AGND
AGND_DC/DC
AGND_VCORE
GND

10V~+19V

+3.0V~+3.3V

+3.3V
+5V
+15V
+3.3V
+5V
+3.3V

+0.75V
+5V
+3.3V
+1.8V
+1.5V
+1.1V
+1.05V

+0.7V~+1.5V

+3.3V
+5V
+5V
+5V

38,39,40

51
50
ALL

24,30,45,46,47,48,49,50,51,52,53
8,11,29,30
3,29,30,34,35,36,43,45,51,54,55
24,33,34,35,47,51,52,54
24,34,51,54
41,42
11,46,48,49,52,53,54

7,8,9,10,11,20,24,28,29,42,43,46,47,48,
49,52,53,54

13,14,47,54
11,18,23,25,33,35,36,37,38,50,54

7,8,9,10,11,13,14,15,18,23,24,26,28,29,30,31,
32,33,34,35,36,37,38,39,40,41,50,52,54,56

5,11,17,18,19,46,54
28,31,32,54
3,5,10,11,48,50,56
8,9,11,15,49
5,50
24
34
34
35,36,51,54,55

DESCRIPTION

DESCRIPTION

MAIN POWER
RTC
8051 POWER
LCD/CHARGE POWER
LARGE POWER
LAN POWER
SLP_S5# CTRLD POWER
SLP_S5# CTRLD POWER

SODIMM POWER
SLP_S3# CTRLD POWER
SLP_S3# CTRLD POWER
SDVO POWER
PCH POWER
CPU POWER
PCH POWER
CPU CORE POWER
LCD Power
Module Power
HDD Power
LED power source

CONTROL
SIGNAL

ALWON
ALWON
+5V_ALW
AUX_ON
SUS_ON

3.3V_SUS_ON
SUS_ON
SUS_ON
RUN_ON

3.3V_RUN_ON
RUN_ON

1.5V_RUN_ON
RUN_ON
RUN_ON
IMVP_VR_ON

LCDVCC_TST_EN
& ENVDD

MODC_EN#
HDDC_EN#
LDO output

ACTIVE INVOLTAGE PAGE

S0~S5
S0~S5
S0~S5
S0~S5
S0~S5

D D

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

1

2

3

4

5

6

Date: Sheet

COMPUTER

FRONTPAGE

FRONTPAGE

FRONTPAGE

RM5 3A

RM5 3A

RM5 3A

7

261Thursday, August 20, 2009

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261Thursday, August 20, 2009

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AUBURNDALE/CLARKSFIELD PROCESSOR (DMI,PEG,FDI) AUBURNDALE/CLARKSFIELD PROCESSOR (CLK,MISC,JTAG)

U38B

U38A

U38A

R1581KR158
1K

R1701KR170
1K

A24
C23
B22
A21

B24
D23
B23
A22

D24
G24
F23
H23

D25
F24
E23
G23

E22
D21
D19
D18
G21
E19
F21
G18

D22
C21
D20
C18
G22
E20
F20
G19

F17
E17

C17
F18

D17

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]

DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]

DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]

DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

FDI_TX#[0]
FDI_TX#[1]
FDI_TX#[2]
FDI_TX#[3]
FDI_TX#[4]
FDI_TX#[5]
FDI_TX#[6]
FDI_TX#[7]

FDI_TX[0]
FDI_TX[1]
FDI_TX[2]
FDI_TX[3]
FDI_TX[4]
FDI_TX[5]
FDI_TX[6]
FDI_TX[7]

FDI_FSYNC[0]
FDI_FSYNC[1]

FDI_INT
FDI_LSYNC[0]

FDI_LSYNC[1]

Clarksfield/Auburndale

Clarksfield/Auburndale

C619 0.1U10C619 0.1U10

C604 0.1U10C604 0.1U10

C621 0.1U10C621 0.1U10

C606 0.1U10C606 0.1U10

C623 0.1U10C623 0.1U10

C608 0.1U10C608 0.1U10

C625 0.1U10C625 0.1U10

C610 0.1U10C610 0.1U10

C632 0.1U10C632 0.1U10

C633 0.1U10C633 0.1U10

C636 0.1U10C636 0.1U10

C637 0.1U10C637 0.1U10

C640 0.1U10C640 0.1U10

C645 0.1U10C645 0.1U10

C648 0.1U10C648 0.1U10

C650 0.1U10C650 0.1U10

C618 0.1U10C618 0.1U10

C603 0.1U10C603 0.1U10

C620 0.1U10C620 0.1U10

C605 0.1U10C605 0.1U10

C622 0.1U10C622 0.1U10

C607 0.1U10C607 0.1U10

C624 0.1U10C624 0.1U10

C609 0.1U10C609 0.1U10

C630 0.1U10C630 0.1U10

C631 0.1U10C631 0.1U10

C634 0.1U10C634 0.1U10

C635 0.1U10C635 0.1U10

C638 0.1U10C638 0.1U10

C641 0.1U10C641 0.1U10

C646 0.1U10C646 0.1U10

C649 0.1U10C649 0.1U10

DMI_TXN07
DMI_TXN17
DMI_TXN27
DMI_TXN37

DMI_TXP07
DMI_TXP17
DMI_TXP27

D D

C C

B B

A A

DMI_TXP37
DMI_RXN07

DMI_RXN17
DMI_RXN27
DMI_RXN37

DMI_RXP07
DMI_RXP17
DMI_RXP27
DMI_RXP37

5/14: Change FDI signals
from GND to NC to support
Arrandale discrete

PCIE_MTX_GRX_C_N0
PCIE_MTX_GRX_C_N1
PCIE_MTX_GRX_C_N2
PCIE_MTX_GRX_C_N3
PCIE_MTX_GRX_C_N4
PCIE_MTX_GRX_C_N5
PCIE_MTX_GRX_C_N6
PCIE_MTX_GRX_C_N7
PCIE_MTX_GRX_C_N8
PCIE_MTX_GRX_C_N9
PCIE_MTX_GRX_C_N10
PCIE_MTX_GRX_C_N11
PCIE_MTX_GRX_C_N12
PCIE_MTX_GRX_C_N13
PCIE_MTX_GRX_C_N14
PCIE_MTX_GRX_C_N15

PCIE_MTX_GRX_C_P0
PCIE_MTX_GRX_C_P1
PCIE_MTX_GRX_C_P2
PCIE_MTX_GRX_C_P3
PCIE_MTX_GRX_C_P4
PCIE_MTX_GRX_C_P5 H_COMP0
PCIE_MTX_GRX_C_P6
PCIE_MTX_GRX_C_P7
PCIE_MTX_GRX_C_P8
PCIE_MTX_GRX_C_P9
PCIE_MTX_GRX_C_P10
PCIE_MTX_GRX_C_P11
PCIE_MTX_GRX_C_P12
PCIE_MTX_GRX_C_P13
PCIE_MTX_GRX_C_P14
PCIE_MTX_GRX_C_P15

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RBIAS
PEG_RX#[0]

PEG_RX#[1]
PEG_RX#[2]

DMI Intel(R) FDI

DMI Intel(R) FDI

PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]

PCI EXPRESS -- GRAPHICS

PCI EXPRESS -- GRAPHICS

PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

PCIE_MTX_GRX_N0
PCIE_MTX_GRX_N1
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_N3
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_N5
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_N7
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_N9
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_N11
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_N13
PCIE_MTX_GRX_N14
PCIE_MTX_GRX_N15

PCIE_MTX_GRX_P0
PCIE_MTX_GRX_P1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_P3
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_P5
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_P7
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_P9
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_P11
PCIE_MTX_GRX_P12
PCIE_MTX_GRX_P13
PCIE_MTX_GRX_P14
PCIE_MTX_GRX_P15

B26
A26
B27
A25

PCIE_MRX_GTX_N15

K35

PCIE_MRX_GTX_N14

J34

PCIE_MRX_GTX_N13

J33

PCIE_MRX_GTX_N12

G35

PCIE_MRX_GTX_N11

G32

PCIE_MRX_GTX_N10

F34

PCIE_MRX_GTX_N9

F31

PCIE_MRX_GTX_N8

D35

PCIE_MRX_GTX_N7

E33

PCIE_MRX_GTX_N6

C33

PCIE_MRX_GTX_N5

D32

PCIE_MRX_GTX_N4

B32

PCIE_MRX_GTX_N3

C31

PCIE_MRX_GTX_N2

B28

PCIE_MRX_GTX_N1

B30

PCIE_MRX_GTX_N0

A31

PCIE_MRX_GTX_P15

J35

PCIE_MRX_GTX_P14

H34

PCIE_MRX_GTX_P13

H33

PCIE_MRX_GTX_P12

F35

PCIE_MRX_GTX_P11

G33

PCIE_MRX_GTX_P10

E34

PCIE_MRX_GTX_P9

F32

PCIE_MRX_GTX_P8

D34

PCIE_MRX_GTX_P7

F33

PCIE_MRX_GTX_P6

B33

PCIE_MRX_GTX_P5

D31

PCIE_MRX_GTX_P4

A32

PCIE_MRX_GTX_P3

C30

PCIE_MRX_GTX_P2

A28

PCIE_MRX_GTX_P1

B29

PCIE_MRX_GTX_P0

A30

PCIE_MTX_GRX_C_N15

L33

PCIE_MTX_GRX_C_N14

M35

PCIE_MTX_GRX_C_N13

M33

PCIE_MTX_GRX_C_N12

M30

PCIE_MTX_GRX_C_N11

L31

PCIE_MTX_GRX_C_N10

K32

PCIE_MTX_GRX_C_N9

M29

PCIE_MTX_GRX_C_N8

J31

PCIE_MTX_GRX_C_N7

K29

PCIE_MTX_GRX_C_N6

H30

PCIE_MTX_GRX_C_N5

H29

PCIE_MTX_GRX_C_N4

F29

PCIE_MTX_GRX_C_N3

E28

PCIE_MTX_GRX_C_N2

D29

PCIE_MTX_GRX_C_N1

D27

PCIE_MTX_GRX_C_N0

C26

PCIE_MTX_GRX_C_P15

L34

PCIE_MTX_GRX_C_P14

M34

PCIE_MTX_GRX_C_P13

M32

PCIE_MTX_GRX_C_P12

L30

PCIE_MTX_GRX_C_P11

M31

PCIE_MTX_GRX_C_P10

K31

PCIE_MTX_GRX_C_P9

M28

PCIE_MTX_GRX_C_P8

H31

PCIE_MTX_GRX_C_P7

K28

PCIE_MTX_GRX_C_P6

G30

PCIE_MTX_GRX_C_P5

G29

PCIE_MTX_GRX_C_P4

F28

PCIE_MTX_GRX_C_P3

E27

PCIE_MTX_GRX_C_P2

D28

PCIE_MTX_GRX_C_P1

C27

PCIE_MTX_GRX_C_P0

C25

PCIE_MTX_GRX_N[0..15] 16

PCIE_MTX_GRX_P[0..15] 16

R480 49.9/FR480 49.9/F

R479 750/FR479 750/F

PCIE_MRX_GTX_N[0..15] 16

PCIE_MRX_GTX_P[0..15] 16

6/23: Pull SKTOCC# to EC
according to EC request

H_CPURST#56

PM_SYNC7

H_CPUPWRGD10,56

PM_DRAM_PWRGD7

H_PWRGD_XDP56

PLTRST#9,16,26,28,29,31,32,41,56

+1.5V_SUS

4/27: Change R200 to 1.1K
and R202 to 3K according
to Intel Design guide 1.52

R200

R200

1.1K/F

1.1K/F

= 1.075V

VDDPWRGOOD_R

DG 1.1, processor requires this

R202

R202

pin to be never driven high before
DDR3 voltage planes have ramped

3K/F

3K/F

to a stable value. It requires a

1.05V or 1.1V Suspend power rail

Thermtrip

H_CPUPWRGD

MMST3904-7-F

MMST3904-7-F

H_THERM#

Processor Pullups

R208

R208

49.9/F

H_CATERR#
H_PROCHOT#
H_CPURST#_R

H_PROCHOT#
use : pull to 68 ohm
unused : pull to 50 ohm

49.9/F

SKTOCC#29

H_PECI10

H_THERM#10

R499 1KR499 1K

R180 0R180 0

R210 0R210 0

R241 1.5K/FR241 1.5K/F

2

Q37

Q37

+1.1V_VTT

R306

R306

49.9/F

49.9/F

H_COMP3
H_COMP2
H_COMP1
H_COMP0

H_CATERR#

H_PROCHOT#

H_THERM#

H_CPURST#_R XDP_TMS

T12 PADT12 PAD

VDDPWRGOOD_R

VTTPWRGOOD

RSTIN#

= 1.1V

H_THERMTRIP# 51

1 3

RSTIN#

CLK_CPU_BCLK

R501

R501
*68_NC

*68_NC

CLK_CPU_BCLK#

For Boundary scan purpose!

U38B

AT23

COMP3

AT24

COMP2

G16

COMP1

AT26

COMP0

AH24

SKTOCC#

AK14

CATERR#

AT15

PECI

AN26

PROCHOT#

AK15

THERMTRIP#

AP26

RESET_OBS#

AL15

PM_SYNC

AN14

VCCPWRGOOD_1

AN27

VCCPWRGOOD_0

AK13

SM_DRAMPWROK

AM15

VTTPWRGOOD

AM26

TAPPWRGOOD

AL14

RSTIN#

R242

R242

Clarksfield/Auburndale

Clarksfield/Auburndale

750/F

750/F

1.1V_VTT_PWRGD43,48

from power
+1.1V_VTT circuit

DDR3 Compensation Signals

R221

R221
130/F

130/F

T42PAD T42PAD

R218

R218

24.9/F

24.9/F

MISC THERMAL

MISC THERMAL

CLOCKS

CLOCKS

DDR3

MISC

DDR3

MISC

PWR MANAGEMENT

PWR MANAGEMENT

JTAG & BPM

JTAG & BPM

+3.3V_ALW

C851 0.1U/10VC851 0.1U/10V

5

U55

U55

2
1

3

74AHC1G08GW

74AHC1G08GW

SM_RCOMP_2
SM_RCOMP_1
SM_RCOMP_0

R214

R214

Layout Note: Place

100/F

100/F

these resistors
near Processor

Processor
Compensation
Signals

H_COMP1
H_COMP2
H_COMP3

R310

R310

49.9/F

49.9/F

R156

R156

49.9/F

49.9/F

R238

R238
20/F

20/F

R239

R239
20/F

20/F

A16

BCLK

B16

BCLK#

AR30

BCLK_ITP

AT30

BCLK_ITP#

E16

PEG_CLK

D16

PEG_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

PM_EXT_TS#[0]
PM_EXT_TS#[1]

4

R243 2K/FR243 2K/F

A18
A17

F6
AL1

AM1
AN1

AN15
AP15

AT28

PRDY#

AP27

PREQ#

AN28

TCK

AP28

TMS

AT27

TRST#

AT29

TDI

AR27

TDO

AR29

TDI_M

AP29

TDO_M

AN25

DBR#

AJ22

BPM#[0]

AK22

BPM#[1]

AK24

BPM#[2]

AJ24

BPM#[3]

AJ25

BPM#[4]

AH22

BPM#[5]

AK23

BPM#[6]

AH23

BPM#[7]

1 2

1 2

5/3: Added buffer to prevent
power good voltage to fluctuate

SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2

PM_EXTTS#0_R
PM_EXTTS#1_R

XDP_PREQ#
XDP_TCLK
XDP_TRST#
XDP_TDI_R

XDP_TDO_R
XDP_TDI_M
XDP_TDO_M

H_DBR#_R

XDP_OBS0_R
XDP_OBS1_R
XDP_OBS2_R

XDP_OBS4_R
XDP_OBS5_R
XDP_OBS6_R
XDP_OBS7_R

H_VTTPWRGD
high level:1.1V

VTTPWRGOOD

R244

R244
1K/F

1K/F

CLK_CPU_BCLK 10
CLK_CPU_BCLK# 10

CLK_PCIE_3GPLL 9
CLK_PCIE_3GPLL# 9

R245 0R245 0
R248 0R248 0

R495 0R495 0

R203 0R203 0
R211 0R211 0
R207 0R207 0
R206 0R206 0
R198 0R198 0
R201 0R201 0
R204 0R204 0
R197 0R197 0

JTAG MAPPING

BCLK_ITP 56
BCLK_ITP# 56

DDR3_DRAMRST# 13,14

PM_EXTTS#0 13
PM_EXTTS#1 14

XDP_PRDY# 56
XDP_PREQ# 56

T85PAD T85PAD
T76PAD T76PAD
T82PAD T82PAD
T80PAD T80PAD

XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3XDP_OBS3_R
XDP_OBS4
XDP_OBS5
XDP_OBS6
XDP_OBS7

XDP_TDI_R

XDP_TDO_M

C

R5210R521
0

XDP_TDI_M

XDP_TDO_R

Scan Chain
(Default)

CPU Only

PCH Only

XDP_TCLK 56
XDP_TMS 56
XDP_TRST# 56

T10PAD T10PAD
T75PAD T75PAD
T49PAD T49PAD

XDP_DBRESET# 7,56
XDP_OBS[0:7] 56

XDP_TMS
XDP_TDI_R
XDP_PREQ#
XDP_TCLK

A

R529 0R529 0

R522 *0_NCR522 *0_NC

B

D

R525 *0_NCR525 *0_NC

R490 0R490 0

E

STUFF -> A, C, E
NO STUFF -> B, D

STUFF -> A, B
NO STUFF -> C, D, E

STUFF -> D, E
NO STUFF -> A, B, C

PM_EXTTS#0_R
PM_EXTTS#1_R

R489 *51_NCR489 *51_NC
R528 *51_NCR528 *51_NC
R190 *51_NCR190 *51_NC
R168 *51_NCR168 *51_NC

+1.1V_VTT

R246

R246
10K

10K

+1.1V_VTT

XDP_TDI 56

XDP_TDO 56

XDP_TRST#

R29051R290
51

R247

R247
10K

10K

R249

R249

*12.4K/F_NC

*12.4K/F_NC

1 2

F

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

COMPUTER

CPU 1/4(PEG/DMI)

CPU 1/4(PEG/DMI)

CPU 1/4(PEG/DMI)

RM5 3A

RM5 3A

RM5 3A

1

361Thursday, August 20, 2009

361Thursday, August 20, 2009

361Thursday, August 20, 2009

of

of

of

5

4

3

2

1

AUBURNDALE/CLARKSFIELD PROCESSOR (DDR3)

U38D

U38C

U38C

U38D

AA6

SA_CK[0]

AA7

SA_CK#[0]

M_A_DQ[63:0]13

D D

C C

B B

M_A_BS013
M_A_BS113
M_A_BS213

M_A_CAS#13
M_A_RAS#13
M_A_WE#13

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

A10

C10

B10

D10

E10

F10

H10

G10

AH5
AF5
AK6
AK7
AF6
AG5

AJ7
AJ6

AJ10

AJ9

AL10

AK12

AK8

AL7

AK11

AL8

AN8
AM10
AR11

AL11

AM9

AN9
AT11
AP12
AM12
AN12
AM13
AT14
AT12

AL13
AR14
AP14

AC3
AB2

AE1
AB3
AE9

C7

D8

C6
G8

G7

J10

M6
M8

N8

U7

A7

A8

E6
F7
E9
B7
E7

K7

J8

J7

L7

L9
L6
K8

P9

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_CKE[0]

SA_CK[1]

SA_CK#[1]

SA_CKE[1]

SA_CS#[0]
SA_CS#[1]

SA_ODT[0]
SA_ODT[1]

SA_DM[0]
SA_DM[1]
SA_DM[2]
SA_DM[3]
SA_DM[4]
SA_DM[5]
SA_DM[6]
SA_DM[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

P7

Y6
Y5
P6

AE2
AE8

AD8
AF9

B9
D7
H7
M7
AG6
AM7
AN10
AN13

C9
F8
J9
N9
AH7
AK9
AP11
AT13

C8
F9
H9
M9
AH8
AK10
AN11
AR13

Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_CLK0 13
M_A_CLK0# 13
M_A_CKE0 13

M_A_CLK1 13
M_A_CLK1# 13
M_A_CKE1 13

M_A_CS#0 13
M_A_CS#1 13

M_A_ODT0 13
M_A_ODT1 13

M_A_DM[7:0] 13

M_A_DQS#[7:0] 13

M_A_DQS[7:0] 13

M_A_A[15:0] 13

M_B_DQ[63:0]14

M_B_BS014
M_B_BS114
M_B_BS214

M_B_CAS#14
M_B_RAS#14
M_B_WE#14

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

AF3
AG1

AK1
AG4
AG3

AH4
AK3

AK4
AM6
AN2

AK5

AK2
AM4
AM3

AP3
AN5

AT4
AN6
AN4
AN3

AT5

AT6
AN7

AP6

AP8

AT9

AT7

AP9

AR10
AT10

AB1

AC5

AC6

AJ3

AJ4

B5
A5
C3
B3
E4
A6
A4
C4
D1
D2
F2
F1
C2
F5
F3
G4
H6
G2

G1
G5

K2

M1

K5
K4

M4

N5

W5

R7

Y7

J6
J3

J2
J1
J5

L3

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

DDR SYSTEM MEMORY - B

DDR SYSTEM MEMORY - B

SB_CK[0]

SB_CK#[0]

SB_CKE[0]

SB_CK[1]

SB_CK#[1]

SB_CKE[1]

SB_CS#[0]
SB_CS#[1]

SB_ODT[0]
SB_ODT[1]

SB_DM[0]
SB_DM[1]
SB_DM[2]
SB_DM[3]
SB_DM[4]
SB_DM[5]
SB_DM[6]
SB_DM[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

W8
W9
M3

V7
V6
M2

AB8
AD6

AC7
AD1

D4
E1
H3
K1
AH1
AL2
AR4
AT8

D5
F4
J4
L4
AH2
AL4
AR5
AR8

C5
E3
H4
M5
AG2
AL5
AP5
AR7

U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1

M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

M_B_CLK0 14
M_B_CLK0# 14
M_B_CKE0 14

M_B_CLK1 14
M_B_CLK1# 14
M_B_CKE1 14

M_B_CS#0 14
M_B_CS#1 14

M_B_ODT0 14
M_B_ODT1 14

M_B_DM[7:0] 14

M_B_DQS#[7:0] 14

M_B_DQS[7:0] 14

M_B_A[15:0] 14

Clarksfield/Auburndale

Clarksfield/Auburndale

Channel A DQ[15,32,48,54], DM[5]

A A

5

Requires minimum 12mils spacing
with all other signals, including data signals.

4

Channel B DQ[16,18,36,42,56,57,60,61,62]
Requires minimum 12mils spacing
with all other signals, including data signals.

3

Clarksfield/Auburndale

Clarksfield/Auburndale

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

COMPUTER

CPU 2/4(DDR)

CPU 2/4(DDR)

CPU 2/4(DDR)

RM5 3A

RM5 3A

RM5 3A

461Thursday, August 20, 2009

461Thursday, August 20, 2009

461Thursday, August 20, 2009

of

of

1

of

5

4

3

2

1

AUBURNDALE/CLARKSFIELD PROCESSOR (POWER)

C683

C685

C685
22U

22U

C676

C676
22U

22U

C674

C674
22U

22U

C684

C684
22U

22U

C330

C330
10U

10U

C346

C346
10U

10U

C393

C393
10U

10U

C408

C408
10U

10U

C397

C397
10U

10U

C683
22U

22U

C672

C672
22U

22U

C677

C677
22U

22U

C686

C686
22U

22U

C336

C336
10U

10U

C363

C363
10U

10U

C366

C366
10U

10U

C392

C392
10U

10U

C410

C410
10U

10U

C409

C409
10U

10U

5

C669

D D

C669
22U

22U

C678

C678
22U

22U

C680

C680
22U

22U

C679

C679
22U

22U

Inside cavity of the socket

C321

C321
10U

10U

C C

C356

C356
10U

10U

Under cavity of the socket

C378

C378
10U

10U

C389

C389
10U

10U

C407

C407
10U

10U

B B

A A

Between inductor and
socket on top layer

470U x 4 or 330U x 6
put on Power side

U38F

U38F

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

Clarksfield/Auburndale

Clarksfield/Auburndale

1.1V RAIL POWER

1.1V RAIL POWER

CPU CORE SUPPLY

CPU CORE SUPPLY

POWER

POWER

PROC_DPRSLPVR

CPU VIDS

CPU VIDS

VTT_SELECT

VCC_SENSE
VSS_SENSE

VSS_SENSE_VTT

SENSE LINES

SENSE LINES

VTT0_1
VTT0_2
VTT0_3
VTT0_4
VTT0_5
VTT0_6
VTT0_7
VTT0_8

VTT0_9
VTT0_10
VTT0_11
VTT0_12
VTT0_13
VTT0_14
VTT0_15
VTT0_16
VTT0_17
VTT0_18
VTT0_19
VTT0_20
VTT0_21
VTT0_22
VTT0_23
VTT0_24
VTT0_25
VTT0_26
VTT0_27
VTT0_28
VTT0_29
VTT0_30
VTT0_31
VTT0_32

VTT0_33
VTT0_34
VTT0_35
VTT0_36
VTT0_37
VTT0_38
VTT0_39
VTT0_40
VTT0_41
VTT0_42
VTT0_43
VTT0_44

PSI#

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

ISENSE

VTT_SENSE

AH14
AH12
AH11
AH10
J14
J13
H14
H12
G14
G13
G12
G11
F14
F13
F12
F11
E14
E12
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

AF10
AE10
AC10
AB10
Y10
W10
U10
T10
J12
J11
J16
J15

AN33

AK35
AK33
AK34
AL35
AL33
AM33
AM35
AM34

G15

AN35

AJ34
AJ35

B15
A15

+1.1V_VTT+VCC_CORE

VID0
VID1
VID2
VID3
VID4
VID5
VID6

DPRSLPVR

4

+1.1V_VTT

C310

C310
22U

22U

C351

C351
22U

22U

C365

C365
22U

22U

Under cavity of the socket

C708

C708
10U

10U

C706

C706
10U

10U

C629

C629
10U

10U

Edge of the socket

330U x 3 put on Power side

C311

C311
22U

22U

C328

C328
22U

22U

C709

C709
10U

10U

C616

C616
10U

10U

C627

C627
10U

10U

H_PSI# 50

VID0 50
VID1 50
VID2 50
VID3 50
VID4 50
VID5 50
VID6 50
DPRSLPVR 50

H_VTTVID1 48

I_MON 50

VTT_SENSE 48

C312

C312
22U

22U

C309

C309
22U

22U

C707

C707
10U

10U

C613

C613
10U

10U

Auburndale : drive VTT_SELECT = 1 for 1.05V
Clarksfield : drive VTT_SELECT = 0 for 1.1V

+VCC_CORE

12

12

AUBURNDALE/CLARKSFIELD PROCESSOR (GRAPHICS POWER)

5/14: Change to GND to
support Arrandale disable

+1.1V_VTT

R216

R216
100/F

100/F

VCCSENSE 50
VSSSENSE 50

R212

R212
100/F

100/F

U38G

U38G

AT21

VAXG1

AT19

VAXG2

AT18

VAXG3

AT16

VAXG4

AR21

VAXG5

AR19

VAXG6

AR18

VAXG7

AR16

VAXG8

AP21

VAXG9

AP19

VAXG10

AP18

VAXG11

AP16

VAXG12

AN21

VAXG13

AN19

VAXG14

AN18

VAXG15

AN16

VAXG16

AM21

VAXG17

AM19

VAXG18

AM18

VAXG19

AM16

VAXG20

AL21

VAXG21

AL19

VAXG22

AL18

VAXG23

AL16

VAXG24

AK21

VAXG25

AK19

VAXG26

AK18

VAXG27

AK16

VAXG28

AJ21

VAXG29

AJ19

VAXG30

AJ18

VAXG31

AJ16

VAXG32

AH21

VAXG33

AH19

VAXG34

AH18

VAXG35

AH16

VAXG36

J24

VTT1_45

J23

VTT1_46

H25

VTT1_47

K26

VTT1_48

J27

VTT1_49

J26

VTT1_50

J25

VTT1_51

H27

VTT1_52

G28

VTT1_53

G27

VTT1_54

G26

VTT1_55

F26

VTT1_56

E26

VTT1_57

E25

VTT1_58

Clarksfield/Auburndale

Clarksfield/Auburndale

VID0
VID1
VID2
VID3
VID4
VID5
VID6
DPRSLPVR
H_PSI#

Note : For Validating IMVP VR R?
should be STUFF and R? NO_STUFF

3

R2921KR292
1K

R291

R291
*1K_NC

*1K_NC

GRAPHICS

GRAPHICS

FDI PEG & DMI

FDI PEG & DMI

R2831KR283
1K

R282

R282
*1K_NC

*1K_NC

VAXG_SENSE

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
GFX_VID[4]
GFX_VID[5]
GFX_VID[6]

GFX_VR_EN

GFX_DPRSLPVR

GFX_IMON

GRAPHICS VIDs

GRAPHICS VIDs

POWER

POWER

DDR3 - 1.5V RAILS

DDR3 - 1.5V RAILS

1.1V1.8V

1.1V1.8V

+1.1V_VTT

R2891KR2891KR298

R298
*1K_NC

*1K_NC

R288

R288

R2971KR297

*1K_NC

*1K_NC

1K

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18

VTT0_59
VTT0_60
VTT0_61
VTT0_62

VTT1_63
VTT1_64
VTT1_65
VTT1_66
VTT1_67
VTT1_68

VCCPLL1
VCCPLL2
VCCPLL3

R296

R296
*1K_NC

*1K_NC

R2951KR295
1K

AR22
AT22

AM22
AP22
AN22
AP23
AM23
AP24
AN24

AR25
AT25
AM24

AJ1
AF1
AE7
AE4
AC1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1

+1.1V_VTT

P10
N10
L10
K10

J22
J20
J18
H21
H20
H19

L26
L27
M26

R3171KR317
1K

R314

R314
*1K_NC

*1K_NC

R205 1KR205 1K

5/14: Change to NC to
support Arrandale disable

C3271UC327

C3171UC317

1U

1U

C303

C303

C371

C371

22U

22U

22U

22U

C6661UC666

C6651UC665

1U

1U

R304

R304
*1K_NC

*1K_NC

R3031KR303
1K

2

R3011KR301
1K

R300

R300
*1K_NC

*1K_NC

R311

R311
*1K_NC

*1K_NC

R3071KR307
1K

C3451UC345

C3641UC364

1U

1U

& no 330U x 1 for
Clarksfield only.

C313

C313

C304

C304

2.2U

2.2U

4.7U

4.7U

+1.5V_SUS

+1.8V_RUN

C3551UC355
1U

C668

C668
22U

22U

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

COMPUTER

CPU 3/4(POWER)

CPU 3/4(POWER)

CPU 3/4(POWER)

RM5 3A

RM5 3A

RM5 3A

1

561Thursday, August 20, 2009

561Thursday, August 20, 2009

561Thursday, August 20, 2009

of

of

of

5

AUBURNDALE/CLARKSFIELD PROCESSOR (GND)

U38H

U38H

AT20

VSS1

AT17

VSS2

AR31

VSS3

AR28

VSS4

AR26

VSS5

AR24

VSS6

AR23

VSS7

D D

C C

B B

A A

AR20

VSS8

AR17

VSS9

AR15

VSS10

AR12

VSS11

AR9

VSS12

AR6

VSS13

AR3

VSS14

AP20

VSS15

AP17

VSS16

AP13

VSS17

AP10

VSS18

AP7

VSS19

AP4

VSS20

AP2

VSS21

AN34

VSS22

AN31

VSS23

AN23

VSS24

AN20

VSS25

AN17

VSS26

AM29

VSS27

AM27

VSS28

AM25

VSS29

AM20

VSS30

AM17

VSS31

AM14

VSS32

AM11

VSS33

AM8

VSS34

AM5

VSS35

AM2

VSS36

AL34

VSS37

AL31

VSS38

AL23

VSS39

AL20

VSS40

AL17

VSS41

AL12

VSS42

AL9

VSS43

AL6

VSS44

AL3

VSS45

AK29

VSS46

AK27

VSS47

AK25

VSS48

AK20

VSS49

AK17

VSS50

AJ31

VSS51

AJ23

VSS52

AJ20

VSS53

AJ17

VSS54

AJ14

VSS55

AJ11

VSS56

AJ8

VSS57

AJ5

VSS58

AJ2

VSS59

AH35

VSS60

AH34

VSS61

AH33

VSS62

AH32

VSS63

AH31

VSS64

AH30

VSS65

AH29

VSS66

AH28

VSS67

AH27

VSS68

AH26

VSS69

AH20

VSS70

AH17

VSS71

AH13

VSS72

AH9

VSS73

AH6

VSS74

AH3

VSS75

AG10

VSS76

AF8

VSS77

AF4

VSS78

AF2

VSS79

AE35

VSS80

Clarksfield/Auburndale

Clarksfield/Auburndale

5

VSS

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30

Scott_0630:Change R294
footprint from RC0402-C to
RC0402

4

U38I

U38I

K27

VSS161

K9

VSS162

K6

VSS163

K3

VSS164

J32

VSS165

J30

VSS166

J21

VSS167

J19

VSS168

H35

VSS169

H32

VSS170

H28

VSS171

H26

VSS172

H24

VSS173

H22

VSS174

H18

VSS175

H15

VSS176

H13

VSS177

H11

VSS178

H8

VSS179

H5

VSS180

H2

VSS181

G34

VSS182

G31

VSS183

G20

VSS184

G9

VSS185

G6

VSS186

G3

VSS187

F30

VSS188

F27

VSS189

F25

VSS190

F22

VSS191

F19

VSS192

F16

VSS193

E35

VSS194

E32

VSS195

E29

VSS196

E24

VSS197

E21

VSS198

E18

VSS199

E13

VSS200

E11

VSS201

E8

VSS202

E5

VSS203

E2

VSS204

D33

VSS205

D30

VSS206

D26

VSS207

D9

VSS208

D6

VSS209

D3

VSS210

C34

VSS211

C32

VSS212

C29

VSS213

C28

VSS214

C24

VSS215

C22

VSS216

C20

VSS217

C19

VSS218

C16

VSS219

B31

VSS220

B25

VSS221

B21

VSS222

B18

VSS223

B17

VSS224

B13

VSS225

B11

VSS226

B8

VSS227

B6

VSS228

B4

VSS229

A29

VSS230

A27

VSS231

A23

VSS232

A9

VSS233

Clarksfield/Auburndale

Clarksfield/Auburndale

4

VSS

VSS

VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7

NCTF

NCTF

CFG0

R285 *3.01K_NCR285 *3.01K_NC

CFG3

R294 3.01KR294 3.01K

CFG4

R281 *3.01K_NCR281 *3.01K_NC

CFG7

R276 *3.01K_NCR276 *3.01K_NC

The Clarksfield processor's PCI
Express interface may not meet
PCI Express 2.0 jitter
specifications. Intel recommends
placing a 3.01K +/- 5% pull down
resistor to VSS on CFG[7] pin for
both rPGA and BGA components.
This pull down resistor should be
removed when this issue is fixed.

AT35
AT1
AR34
B34
B2
B1
A35

3

AUBURNDALE/CLARKSFIELD PROCESSOR( RESERVED, CFG)

Processor Generated
SO-DIMM VREF_DQ (M3)
Connect to page 13, 14

R140

M_VREF_DQ_DIMM0
M_VREF_DQ_DIMM1

CFG0
(PCI-Epress
Configuration Select)

CFG3
(PCI-Epress Static
Lane Reversal)

CFG4
(Display Port
Presence)

CFG7
Clarksfield (only for
early samples pre-ES1)

3

R140
R142

R142

& NC CFG12 for Clarksfield only.

Follow Intel CRB to GND

T113PADT113PAD

R702 *0_NCR702 *0_NC
R703 *0_NCR703 *0_NC

T114PADT114PAD

Single PEG (Default)

Normal Operation
(Default)

Disabled; No Physical
Display Port attached to
Embedded Diplay Port
(Default)

Common
motherboard
design

2

U38E

U38E

AP25

RSVD1

AL25

RSVD2

AL24

RSVD3

AL22

RSVD4

AJ33

RSVD5

AG9

RSVD6

M27

*0_NC

*0_NC

*0_NC

*0_NC

T48 PADT48 PAD
T77 PADT77 PAD
T36 PADT36 PAD
T50 PADT50 PAD
T46 PADT46 PAD
T53 PADT53 PAD
T79 PADT79 PAD
T47 PADT47 PAD
T27 PADT27 PAD
T52 PADT52 PAD
T78 PADT78 PAD
T16 PADT16 PAD

T51 PADT51 PAD
T20 PADT20 PAD
T81 PADT81 PAD
T24 PADT24 PAD
T35 PADT35 PAD

SA_DIMM_VREF
SB_DIMM_VREF

CFG0

CFG3
CFG4

CFG7

TP_RSVD17_RTP_RSVD17_R

TP_RSVD17_RTP_RSVD17_R
TP_RSVD18_R

TP_RSVD18_R

RSVD7

L28

RSVD8

J17

SA_DIMM_VREF

H17

SB_DIMM_VREF

G25

RSVD11

G17

RSVD12

E31

RSVD13

E30

RSVD14

AM30

CFG[0]

AM28

CFG[1]

AP31

CFG[2]

AL32

CFG[3]

AL30

CFG[4]

AM31

CFG[5]

AN29

CFG[6]

AM32

CFG[7]

AK32

CFG[8]

AK31

CFG[9]

AK28

CFG[10]

AJ28

CFG[11]

AN30

CFG[12]

AN32

CFG[13]

AJ32

CFG[14]

AJ29

CFG[15]

AJ30

CFG[16]

AK30

CFG[17]

H16

RSVD_TP_86

B19

RSVD15

A19

RSVD16

A20

RSVD17

B20

RSVD18

U9

RSVD19

T9

RSVD20

AC9

RSVD21

AB9

RSVD22

C1

RSVD_NCTF_23

A3

RSVD_NCTF_24

J29

RSVD26

J28

RSVD27

A34

RSVD_NCTF_28

A33

RSVD_NCTF_29

C35

RSVD_NCTF_30

B35

RSVD_NCTF_31

Clarksfield/Auburndale

Clarksfield/Auburndale

10

Bifurcation enabled

Lane Numbers Reversed

Enabled; An external Display
port device is connected to
the Embedded Display port

For early samples
pre-ES1 CFD
(Default)

2

1

AJ13

RSVD32

AJ12

RSVD33

AH25

RSVD34

AK26

RSVD35

AL26

RSVD36

RSVD_NCTF_37

RSVD_NCTF_40
RSVD_NCTF_41

RSVD_NCTF_42
RSVD_NCTF_43

RSVD_NCTF_54
RSVD_NCTF_55
RSVD_NCTF_56
RSVD_NCTF_57

RSVD_TP_59
RSVD_TP_60

RESERVED

RESERVED

RSVD_TP_66
RSVD_TP_67
RSVD_TP_68
RSVD_TP_69
RSVD_TP_70
RSVD_TP_71
RSVD_TP_72
RSVD_TP_73
RSVD_TP_74
RSVD_TP_75

RSVD_TP_76
RSVD_TP_77
RSVD_TP_78
RSVD_TP_79
RSVD_TP_80
RSVD_TP_81
RSVD_TP_82
RSVD_TP_83
RSVD_TP_84
RSVD_TP_85

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

AR2
AJ26

RSVD38

AJ27

RSVD39

AP1
AT2

AT3
AR1

AL28

RSVD45

AL29

RSVD46

AP30

RSVD47

AP32

RSVD48

AL27

RSVD49

AT31

RSVD50

AT32

RSVD51

AP33

RSVD52

AR33

RSVD53

AT33
AT34
AP35
AR35
AR32

RSVD58

E15
F15

Follow Intel CRB to GND

A2

KEY

D15

RSVD62

C15

RSVD63
RSVD64
RSVD65

VSS

CPU 4/4(GND_RESV)

CPU 4/4(GND_RESV)

CPU 4/4(GND_RESV)

RM5 3A

RM5 3A

RM5 3A

RSVD64_R

AJ15

RSVD65_R

AH15

AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3

V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9

AP34

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

R700 *0_NCR700 *0_NC
R701 *0_NCR701 *0_NC

T90PAD T90PAD
T96PAD T96PAD

T89PAD T89PAD

Can be left NC is Intel CRM

R3020R302

implementation; ESD/DG
recommendation to GND

0

1

T111PAD T111PAD

T112PAD T112PAD

661Thursday, August 20, 2009

661Thursday, August 20, 2009

661Thursday, August 20, 2009

of

of

of

5

4

3

2

1

U39C

DMI_RXN03
DMI_RXN13
DMI_RXN23
DMI_RXN33

DMI_RXP03
DMI_RXP13

D D

C C

B B

DMI_RXP23
DMI_RXP33

DMI_TXN03
DMI_TXN13
DMI_TXN23
DMI_TXN33

DMI_TXP03
DMI_TXP13
DMI_TXP23
DMI_TXP33

+1.05V_VCCIO

DG1.1, Page 314.
SYS_PWROK : This signal should be used on the platform to
indicate that the processor VR power is good and therefore
it can be connected to the same source as PWROK on PCH.
MEPWROK : For platform not supporting Intel AMT it can be
connected to PWROK

XDP_DBRESET#3,56

PCH_PWRGD29

PM_DRAM_PWRGD3

PCH_RSMRST#29

SUS_PWR_ACK29

SIO_PWRBTN#29

AC_PRESENT29

+3.3V_SUS

+3.3V_SUS

Width = 4 mil ; close
PCH within 500 mil

R494 49.9/FR494 49.9/F

R228 0R228 0

R555 0R555 0

R234 0R234 0

R566 10KR566 10K

R268 10KR268 10K

12

12

DMI_COMP

SYS_PWROK

PWROK

MEPWROK

LAN_RST#

PCH_RSMRST#

SUS_PWR_ACK

PM_BATLOW#

PM_RI#

BC24

DMI0RXN

BJ22

DMI1RXN

AW20

DMI2RXN

BJ20

DMI3RXN

BD24

DMI0RXP

BG22

DMI1RXP

BA20

DMI2RXP

BG20

DMI3RXP

BE22

DMI0TXN

BF21

DMI1TXN

BD20

DMI2TXN

BE18

DMI3TXN

BD22

DMI0TXP

BH21

DMI1TXP

BC20

DMI2TXP

BD18

DMI3TXP

BH25

DMI_ZCOMP

BF25

DMI_IRCOMP

T6

SYS_RESET#

M6

SYS_PWROK

B17

PWROK

K5

MEPWROK

A10

LAN_RST#

D9

DRAMPWROK

C16

RSMRST#

M1

SUS_PWR_DN_ACK / GPIO30

P5

PWRBTN#

P7

ACPRESENT / GPIO31

A6

BATLOW# / GPIO72

F14

RI#

IbexPeak-M_R1P0

IbexPeak-M_R1P0

FDI_FSYNC0

DMI

FDI

DMI

FDI

FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

System Power Management

System Power Management

SLP_LAN# / GPIO29

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

FDI_INT

WAKE#

SLP_S4#

SLP_S3#

SLP_M#

TP23

PMSYNCH

BA18
BH17
BD16
BJ16
BA16
BE14
BA14
BC12

BB18
BF17
BC16
BG16
AW16
BD14
BB14
BD12

BJ14
BF13
BH13
BJ12
BG14

J12

Y1

P8

F3

E4

H7

P12

K8

N2

BJ10

F6

PCIE_WAKE#

CLKRUN#

RSV_LPCPD#

SUSCLK

SLP_M#

SLP_LAN#

FDI Disable :
NC all signals
as DG 1.1,
Page 82 & 83

PCIE_WAKE# 28,41

CLKRUN# 29

T25PAD T25PAD

T102PAD T102PAD

SIO_SLP_S5# 29

T26PAD T26PAD

SIO_SLP_S3# 29

T31PAD T31PAD

T29PAD T29PAD

PM_SYNC 3

T39PAD T39PAD

LVDS Disable :
All signals associated
with the interface can
be left asNo connects.

CRT Disable :
CRT_RED
CRT_GREEN
CRT_BLUE
CRT_HSYCN
CRT_VSYNC
Leave as NC (floating).

R215

R215
1K

1K

0.5%

0.5%

AB48

AB46

AP39
AP41

AT43
AT42

AV53
AV51

BB47
BA52
AY48
AV47

BB48
BA50
AY49
AV48

AP48
AP47

AY53
AT49
AU52
AT53

AY51
AT48
AU50
AT51

AA52
AB53
AD53

AD48
AB51

T48
T47

Y48

Y45

V48

V51
V53

Y53
Y51

U39D

U39D

L_BKLTEN
L_VDD_EN

L_BKLTCTL
L_DDC_CLK

L_DDC_DATA
L_CTRL_CLK

L_CTRL_DATA
LVD_IBG

LVD_VBG
LVD_VREFH

LVD_VREFL

LVDSA_CLK#
LVDSA_CLK

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

LVDSB_CLK#
LVDSB_CLK

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

CRT_BLUE
CRT_GREEN
CRT_RED

CRT_DDC_CLK
CRT_DDC_DATA

CRT_HSYNC
CRT_VSYNC

DAC_IREF
CRT_IRTN

IbexPeak-M_R1P0

IbexPeak-M_R1P0

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

BJ46
BG46

BJ48
BG48

BF45
BH45

T51
T53

BG44
BJ44
AU38

BD42
BC42
BJ42
BG42
BB40
BA40
AW38
BA38

Y49
AB49

BE44
BD44
AV40

BE40
BD40
BF41
BH41
BD38
BC38
BB36
BA36

U50
U52

BC46
BD46
AT38

BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36

SDVO_TVCLKINN

SDVO_TVCLKINP

SDVO_STALLN
SDVO_STALLP

SDVO_INTN
SDVO_INTP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPB_AUXN

DDPB_AUXP

DDPB_HPD

LVDS

LVDS

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_AUXN
DDPC_AUXP

DDPC_HPD

Digital Display Interface

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_AUXN
DDPD_AUXP

DDPD_HPD

CRT

CRT

SDVO

Display port BDisplay port CDisplay port D

U39C

IBEX PEAK-M (LVDS,DDI)IBEX PEAK-M (DMI,FDI,GPIO)

12

+3.3V_SUS

+3.3V_RUN

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

3

2

Date: Sheet

COMPUTER

PCH 1/6(DMI_VIDEO)

PCH 1/6(DMI_VIDEO)

PCH 1/6(DMI_VIDEO)

RM5 3A

RM5 3A

RM5 3A

761Thursday, August 20, 2009

761Thursday, August 20, 2009

761Thursday, August 20, 2009

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of

1

of

PCH_PWRGD
PCH_RSMRST#
LAN_RST#

Internal LAN disable, LAN_RST#
is required 8.2K ~ 10K PD.

A A

5

R564 10KR564 10K
R571 10KR571 10K
R557 10KR557 10K

12
12
12

PCIE_WAKE#

CLKRUN#

R254 1KR254 1K

R531 10KR531 10K

4

5

+RTC_CELL

12

R5701MR570
1M

1 2

D D

12

R562 33R562 33

ICH_AZ_CODEC_BITCLK38

ICH_AZ_CODEC_SYNC38
ICH_AZ_CODEC_RST#29,38

C C

ICH_AZ_CODEC_SDOUT38

Place all series terms close to PCH (within 500 mil) except for SDIN
input lines,which should be close to source.Placement of R773, R775,
R776 & R777 should equal distance to the T split trace point.
Basically, keep the same distance from T for all series
termination resistors.

No Reboot strap.

Low = Default.

SPKR

+3.3V_RUN

R545 *1K_NCR545 *1K_NC

1 2

High = No Reboot.

SPKR

1 2

C703

C703
*27P/50V_NC

*27P/50V_NC

1 2

R273 33R273 33

1 2

R561 33R561 33

1 2

R573 33R573 33

1 2

Scott_0630:Change R545 footprint from RC0402-C to RC0402.

R568

R568
20K

20K

C700

C700
1U/10V

1U/10V

R574

R574
20K

20K

1 2

12

C699

C699
1U/10V

1U/10V

ACZ_BIT_CLK

ACZ_SYNC
ACZ_RST#
ACZ_SDOUT

INTVRMEN(Internal Voltage Regulator Enable) :
This signal enables the internal 1.05 V regulators.
This signal must be always pulled-up to VccRTC.

4

Cap values depend on Xtal

C701

+RTC_CELL

C701

15P/50V

15P/50V

C696

C696

15P/50V

15P/50V

ICH_AZ_CODEC_SDIN038

12

1 2

12

R556 330KR556 330K

KB_LED_DET35

Y3

Y3

32.768KHZ

32.768KHZ

SPKR38

T93 PADT93 PAD
T88 PADT88 PAD
T97 PADT97 PAD
T99 PADT99 PAD
T95 PADT95 PAD

RTC_X1

R552

R552
10M

10M

1 2

RTC_X2

RTC_RST#
SRTC_RST#
SM_INTRUDER#
PCH_INVRMEN

ACZ_BIT_CLK
ACZ_SYNC
SPKR
ACZ_RST#

T37 PADT37 PAD
T40 PADT40 PAD
T43 PADT43 PAD

ACZ_SDOUT

GPIO33

PCH_JTAG_TCK_BUF
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_RST#

3

IBEX PEAK-M (HDA,JTAG,SATA)

U39A

U39A

B13

RTCX1

D13

RTCX2

C14

RTCRST#

D17

SRTCRST#

A16

INTRUDER#

A14

INTVRMEN

A30

HDA_BCLK

D29

HDA_SYNC

P1

SPKR

C30

HDA_RST#

G30

HDA_SDIN0

F30

HDA_SDIN1

E32

HDA_SDIN2

F32

HDA_SDIN3

B29

HDA_SDO

H32

HDA_DOCK_EN# / GPIO33

J30

HDA_DOCK_RST# / GPIO13

M3

JTAG_TCK

K3

JTAG_TMS

K1

JTAG_TDI

J2

JTAG_TDO

J4

TRST#

RTCIHDA

RTCIHDA

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

FWH4 / LFRAME#

LDRQ1# / GPIO23

LPC

LPC

SATA

SATA

SATAICOMPO

SATAICOMPI

LDRQ0#

SERIRQ

SATA0RXN
SATA0RXP
SATA0TXN

SATA0TXP

SATA1RXN
SATA1RXP
SATA1TXN

SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN

SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN

SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN

SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN

SATA5TXP

D33
B33
C32
A32

C34
A34

F34
AB9

AK7
AK6
AK11
AK9

AH6
AH5
AH9
AH8

AF11
AF9
AF7
AF6

AH3
AH1
AF3
AF1

AD9
AD8
AD6
AD5

AD3
AD1
AB3
AB1

AF16
AF15

2

LPC_LAD0 29,32
LPC_LAD1 29,32
LPC_LAD2 29,32
LPC_LAD3 29,32

T92PAD T92PAD
T34PAD T34PAD

IRQ_SERIRQ

Notes : Put AC Coupling Cap. near device side.
As DG1.1, Page 299, the series capacitors may
be placed at any point on the traces between
PCH and the Serial ATA connector. However, it
is recommended that they should be close to
the connector for optimal signal quality

LPC_LFRAME# 29,32

IRQ_SERIRQ 29

SATA_RX0- 34
SATA_RX0+ 34
SATA_TX0-_C 34

SATA_TX0+_C 34

SATA_RX1- 34
SATA_RX1+ 34
SATA_TX1-_C 34

SATA_TX1+_C 34

SATA_RX5- 33
SATA_RX5+ 33
SATA_TX5-_C 33

SATA_TX5+_C 33

within 500 mils of the PCH

SATA_COMP

R213 37.4/FR213 37.4/F

HDD

ODD

E-SATA

+1.05V_PCH

1

Notes : FIS-based Port
Multiplier support on
SATA Ports 4 and 5 in
AHCI/RAID mode.

PCH_SPI_CLK30

R261 *1K_NCR261 *1K_NC

1 2

B B

Note : GPIO33 is a signal used for Flash
Descriptor Security Override/ME Debug
Mode.This signal should be only asserted
lowthrough an external pull-down in
manufacturing or debug environments
ONLY.

6/2: NC JTAG resistors as PCH is in QT stage

+3.3V_SUS

Res. of TDI near PCH

R263

R263

R251

R251

R236

R236

*200_NC

*200_NC

A A

R546

R546

*100_NC

*100_NC

NC all Res. when PCH is
production stage.

*200_NC

*200_NC

R547

R547

*100_NC

*100_NC

*200_NC

*200_NC

R549

R549

*100_NC

*100_NC

GPIO33

R259

R259

*20K_NC

*20K_NC

R548

R548

*10K_NC

*10K_NC

Res. of TDO
PCH ES1 stage : NC
PCH ES2 stage : pop

5

6/2: Change R261 from 10K_NC
to 1K_NC according to Intel design guide 1.51

PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_RST#

Scott_0707: Reserver
PCH_JTAG_RST#
circuit as review.

Note : Only pop when PCH is production
stage & need "JTAG boundary Scan".
Remember to depop XDP side Res.

Scott_0703 : Note : Delete pull up 1.05V according to
Intel change notice! (Reserved for debug purpose)

4

PCH_SPI_CS0#30

T13 PADT13 PAD

PCH_SPI_SI30
PCH_SPI_SO30

R54451R544

51

BA2

SPI_CLK

AV3

SPI_CS0#

AY3

SPI_CS1#

AY1

SPI_MOSI

AV1

SPI_MISO

IbexPeak-M_R1P0

IbexPeak-M_R1P0

PCH_JTAG_TCK_BUF

3

SPI JTAG

SPI JTAG

SATALED#

SATA0GP / GPIO21
SATA1GP / GPIO19

PU 10K to +3.3V_RUN
at Page 38

T3

R188 10KR188 10K

Y9
V1

1 2

R537 10KR537 10K

1 2

2

SATA_ACT# 36

+3.3V_RUN

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

COMPUTER

PCH 2/6(SATA_SPI)

PCH 2/6(SATA_SPI)

PCH 2/6(SATA_SPI)

RM5 3A

RM5 3A

RM5 3A

861Thursday, August 20, 2009

861Thursday, August 20, 2009

861Thursday, August 20, 2009

of

of

1

of

5

4

3

2

1

IBEX PEAK-M (PCI,USB,NVRAM)

U39E

U39E

H40

AD0

N34

AD1

C44

AD2

A38

AD3

C36

AD4

J34

AD5

A40

AD6

D45

D D

Change Cardreader to PCIE
Interface!
Del PCI debug card!

C C

CLK_LPC_DEBUG32

B B

CLK_PCI_851229

USB_MCARD3_DET#32
USB_MCARD1_DET#31

PCH_IRQH_GPIO534

CLK_PCI_FB

R534 22R534 22
R220 22R220 22

R526 22R526 22

T45 PADT45 PAD

T94 PADT94 PAD

T104PADT104 PAD

T28 PADT28 PAD
T44 PADT44 PAD
T87 PADT87 PAD

T103PADT103 PAD
T86 PADT86 PAD
T91 PADT91 PAD

T33 PADT33 PAD

T30 PADT30 PAD

1 2
1 2

1 2

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

PCI_REQ0#
PCI_REQ1#
USB_MCARD3_DET#
USB_MCARD1_DET#

PCI_GNT0#
PCI_GNT1#
PCI_GNT2#
PCI_GNT3#

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCH_IRQH_GPIO5

PCI_RST#_G
PCI_SERR#

PCI_PERR#

PCI_IRDY#
PCI_DEVSEL#

PCI_FRAME#
PCI_PLOCK#
PCI_STOP#

PCI_TRDY#
PME#
PCI_PLTRST#
CLK_LPC_DEBUG_C
CLK_PCI_8512_C

CLK_PCI_FB_C

E36
H48
E40

C40
M48
M45

F53
M40
M43

J36
K48
F40

C42

K46

M51

J52

K51

L34

F42

J40
G46
F44

M47

H36

J50
G42
H47
G34

G38
H51
B37
A44

F51
A46
B45

M53

F48
K45
F36
H53

B41
K53
A36
A48

K6

E44
E50

A42
H44
F46
C46

D49
D41

C48

M7
D5

N52
P53
P46
P51
P48

IbexPeak-M_R1P0

IbexPeak-M_R1P0

AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

C/BE0#
C/BE1#
C/BE2#
C/BE3#

PIRQA#
PIRQB#
PIRQC#
PIRQD#

REQ0#
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54

GNT0#
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55

PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5

PCIRST#
SERR#

PERR#

IRDY#
PAR
DEVSEL#
FRAME#

PLOCK#
STOP#

TRDY#
PME#
PLTRST#
CLKOUT_PCI0

CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

PCI

PCI

NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8

NV_DQ9 / NV_IO9
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11

NVRAM

NVRAM

NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15

USB

USB

PCI Pullup

PCI_PIRQE#
PCI_PIRQF#

+3.3V_SUS

C401

C401

1 2

5

U8

2
1

USB OC Pullup

RP1

RP1

6
7
8
9

10

10P8R-10K

10P8R-10K

7SH32U87SH32

4

PLTRST# 3,16,26,28,29,31,32,41,56

+3.3V_SUS

5

OC6#

4
3

OC2#

2

OC5#

1

5

0.047U/10V

0.047U/10V

PCI_PLTRST#

A A

OC7#
OC3#
OC0# OC4#
OC1#

+3.3V_SUS

PCI_PIRQG#
USB_MCARD3_DET#

PCI_REQ1#
PCI_FRAME#
PCI_TRDY#
PCH_IRQH_GPIO5

+3.3V_RUN

PCI_PIRQC#
PCI_STOP#

PCI_PIRQD#

+3.3V_RUN

R572 8.2KR572 8.2K

R541 8.2KR541 8.2K

R560 8.2KR560 8.2K

R577 8.2KR577 8.2K

RP5

RP5

6
7
8
9

10

10P8R-8.2K

10P8R-8.2K
RP6

RP6

6
7
8
9

10

10P8R-8.2K

10P8R-8.2K

NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3

NV_DQS0
NV_DQS1

NV_ALE
NV_CLE

NV_RCOMP

NV_RB#

NV_WR#0_RE#
NV_WR#1_RE#

NV_WE#_CK0
NV_WE#_CK1

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N

USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43

OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

+3.3V_RUN

+3.3V_RUN

5
4
3
2
1

+3.3V_RUN

5
4
3
2
1

AY9
BD1
AP15
BD8

AV9
BG8

AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6

BD3
AY6

AU2
AV7
AY8

AY5
AV11

BF5

H18
J18
A18
C18
N20
P20
J20
L20
F20
G20
A20
C20
M22
N22
B21
D21
H22
J22
E22
F22
A22
C22
G24
H24
L24
M24
A24
C24

B25
D25

N16
J16
F16
L16
E14
G16
F12
T15

NV_ALE 10
NV_CLE 10

PCH_USBP0- 40
PCH_USBP0+ 40
PCH_USBP1- 40
PCH_USBP1+ 40
PCH_USBP2- 33

PCH_USBP3­PCH_USBP3+

USB_BIAS

OC0#
OC1#
OC2#
OC3#
OC4#
OC5#
OC6#
OC7#

PCH_USBP2+ 33

T32PAD T32PAD

T23PAD T23PAD

PCH_USBP4- 31
PCH_USBP4+ 31
PCH_USBP5- 32
PCH_USBP5+ 32

5/12: Move WPAN from port 6 to port 8 and
Expresscard from port 7 to port 10 to support HM55

PCH_USBP8- 32
PCH_USBP8+ 32
PCH_USBP9- 33
PCH_USBP9+ 33
PCH_USBP10- 28
PCH_USBP10+ 28
PCH_USBP11- 35
PCH_USBP11+ 35

R262 22.6/FR262 22.6/F

for USB 0/1

OC0# 33

for USB 2

OC1# 33

5/12: Depop R226 and R229 as BIOS decided
to boot from SPI ROM connected to PCH

5/19: Update BIOS strap table

R226 *1K_NCR226 *1K_NC
R229 *1K_NCR229 *1K_NC

Boot BIOS Strap

PCI_GNT0#PCI_GNT1#

0

0
0

1
01

PCI_PLOCK#
USB_MCARD1_DET#
PCI_PIRQB#
PCI_REQ0#

PCI_PIRQA#
PCI_SERR#PCI_IRDY#
PCI_DEVSEL#
PCI_PERR#

4

1 1

R542 *1K_NCR542 *1K_NC

A16 swap override Strap/Top-Block
Swap Override jumper

PCI_GNT3#

Side pair (Top / left, IB)
Side pair (Bottom / left, IB)
USB W/ E-SATA port

Mini Card (WLAN)
Mini Card (WPAN)

Mini Card (WWAN)
TV

Express Card
Camera

PCI_GNT0#
PCI_GNT1#

Boot BIOS Location
LPC
Reserved (NAND)
PCI
SPI

PCI_GNT3#

0 = A16 swap
override/Top-Block
Swap Override enabled
1 = Default

PCIE_RX1-32

PCIE_RX6-/GLAN_RX-41
PCIE_RX6+/GLAN_RX+41

PCIE_TX6-/GLAN_TX-41
PCIE_TX6+/GLAN_TX+41

PCIE_RX1+32
PCIE_TX1-32
PCIE_TX1+32

PCIE_RX2-31
PCIE_RX2+31
PCIE_TX2-31
PCIE_TX2+31

PCIE_RX3-32
PCIE_RX3+32
PCIE_TX3-32
PCIE_TX3+32

PCIE_RX4-28
PCIE_RX4+28
PCIE_TX4-28
PCIE_TX4+28

PCIE_RX5-26
PCIE_RX5+26
PCIE_TX5-26
PCIE_TX5+26

Mini WPAN

MINI2CLK_REQ#32

Mini WWAN

MINI3CLK_REQ#32

Mini WLAN

Express Card

CARD_CLK_REQ#28

Card Reader

Giga Bit LOM

MINI1CLK_REQ#31

SML1_SMBCLK

SML1_SMBDATA

C659 0.1U/10VC659 0.1U/10V
C660 0.1U/10VC660 0.1U/10V

C318 0.1U/10VC318 0.1U/10V
C315 0.1U/10VC315 0.1U/10V

C353 0.1U/10VC353 0.1U/10V
C349 0.1U/10VC349 0.1U/10V

C329 0.1U/10VC329 0.1U/10V
C324 0.1U/10VC324 0.1U/10V

C658 0.1U/10VC658 0.1U/10V
C657 0.1U/10VC657 0.1U/10V

C339 0.1U/10VC339 0.1U/10V
C332 0.1U/10VC332 0.1U/10V

5/3: Added 0 ohms and change
pull up to PCH side

CLK_PCIE_MINI2#32

CLK_PCIE_MINI232

R671 0R671 0

CLK_PCIE_MINI3#32

CLK_PCIE_MINI332

R672 0R672 0

CLK_PCIE_MINI1#31

CLK_PCIE_MINI131

CLK_PCIE_EXPCARD#28

CLK_PCIE_EXPCARD28

R674 0R674 0

CLK_PCIE_CARD_READER#26
CLK_PCIE_CARD_READER26

CLK_PCIE_LOM#41

CLK_PCIE_LOM41

2N7002W-7-F

2N7002W-7-F

Q61

Q61

2N7002W-7-F

2N7002W-7-F

Q62

Q62

2N7002W-7-F

2N7002W-7-F

R225 0R225 0

Q81

Q81

2

+3.3V_SUS

2

LOMCLK_REQ#41

5/13: Added MOSFET Q81 to prevent leakage
from 3.3V_SUS to cardreader during S3

4/28: Change polarity to prevent leakage

3

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

1 2
1 2

31

31

1 2

1 2

1 2

1 2

2

31

Mini WPAN

PCIE_TXN1_C
PCIE_TXP1_C

Mini WLAN

PCIE_TXN2_C
PCIE_TXP2_C

Mini WWAN

PCIE_TXN3_C
PCIE_TXP3_C

Express Card

PCIE_TXN4_C
PCIE_TXP4_C

Card Reader

PCIE_TXN5_C
PCIE_TXP5_C

Giga Bit LOM

GLAN_TXN_C
GLAN_TXP_C

CLK_PCIE_REQ0#

MINI2CLK_REQ#_R

MINI3CLK_REQ#_R

MINI1CLK_REQ#_R

CARD_CLK_REQ#_C

CLK_PCIE_REQ5#_R

LOMCLK_REQ#_R

MINI1CLK_REQ#_R

SMBCLK1 20,24,29

SMBDAT1 20,24,29

IBEX PEAK-M (PCI-E,SMBUS,CLK)

U39B

U39B

BG30

PERN1

BJ30

PERP1

BF29

PETN1

BH29

PETP1

AW30

PERN2

BA30

PERP2

BC30

PETN2

BD30

PETP2

AU30

PERN3

AT30

PERP3

AU32

PETN3

AV32

PETP3

BA32

PERN4

BB32

PERP4

BD32

PETN4

BE32

PETP4

BF33

PERN5

BH33

PERP5

BG32

PETN5

BJ32

PETP5

BA34

PERN6

AW34

PERP6

BC34

PETN6

BD34

PETP6

AT34

PERN7

AU34

PERP7

AU36

PETN7

AV36

PETP7

BG34

PERN8

BJ34

PERP8

BG36

PETN8

BJ36

PETP8

AK48

CLKOUT_PCIE0N

AK47

CLKOUT_PCIE0P

P9

PCIECLKRQ0# / GPIO73

AM43

CLKOUT_PCIE1N

AM45

CLKOUT_PCIE1P

U4

PCIECLKRQ1# / GPIO18

AM47

CLKOUT_PCIE2N

AM48

CLKOUT_PCIE2P

N4

PCIECLKRQ2# / GPIO20

AH42

CLKOUT_PCIE3N

AH41

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

AM51

CLKOUT_PCIE4N

AM53

CLKOUT_PCIE4P

M9

PCIECLKRQ4# / GPIO26

AJ50

CLKOUT_PCIE5N

AJ52

CLKOUT_PCIE5P

H6

PCIECLKRQ5# / GPIO44

AK53

CLKOUT_PEG_B_N

AK51

CLKOUT_PEG_B_P

P13

PEG_B_CLKRQ# / GPIO56

IbexPeak-M_R1P0

IbexPeak-M_R1P0

5/4: Added MOSFET Q80 to prevent leakage
from 3.3V_SUS to cardreader during S3

CLK_PCIE_REQ5#26

CLK_PCIE_REQ0#
MINI1CLK_REQ#_R

CLK_PCIE_REQ5#_R
LOMCLK_REQ#_R
CARD_CLK_REQ#_C

MINI2CLK_REQ#_R
MINI3CLK_REQ#_R

PCH_SMB_ALERT#
PCH_SML0ALERT#
PCH_SML1ALERT#
PCH_SMBCLK
PCH_SMBDATA
SML0CLK
SML0DATA
SML1_SMBCLK
SML1_SMBDATA

PCI-E*

PCI-E*

Q80

Q80

2N7002W-7-F

2N7002W-7-F

R558 10K/FR558 10K/F
R250 10K/FR250 10K/F
R219 10K/FR219 10K/F
R267 2.2K/FR267 2.2K/F
R255 2.2K/FR255 2.2K/F
R565 2.2K/FR565 2.2K/F
R271 2.2K/FR271 2.2K/F
R266 2.2K/FR266 2.2K/F
R235 2.2K/FR235 2.2K/F

R232 10KR232 10K
R576 10KR576 10K

R258 10KR258 10K
R227 10KR227 10K
R277 10KR277 10K

R536 10KR536 10K
R231 10KR231 10K

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML1ALERT# / GPIO74

SMBus

SMBus

SML1CLK / GPIO58

SML1DATA / GPIO75

Link

Link

Controller

Controller

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N

CLKOUT_PEG_A_P

CLKOUT_DMI_N

CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P

CLKIN_PCILOOPBACK

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

CLK_PCIE_REQ5#_R

31

12
12

12
12
12

12
12

2

CLKOUT_DMI_P

CLKIN_BCLK_N
CLKIN_BCLK_P

CLKIN_DOT_96N
CLKIN_DOT_96P

+3.3V_SUS+3.3V_SUS

+3.3V_RUN

PEG

PEG

CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P

From CLK BUFFER

From CLK BUFFER

Clock Flex

Clock Flex

+3.3V_RUN+3.3V_RUN

2

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1
CL_DATA1
CL_RST1#

CLKIN_DMI_N
CLKIN_DMI_P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

PCH_SMB_ALERT#

B9

PCH_SMBCLK

H14

PCH_SMBDATA

C8

PCH_SML0ALERT#

J14

SML0CLK

C6

SML0DATA

G8

PCH_SML1ALERT#

M14

SML1_SMBCLK

E10

SML1_SMBDATA

G12

T13
T11
T9

PEG_A_CLKRQ#

H1

AD43
AD45

AN4
AN2

AT1
AT3

AW24
BA24

AP3
AP1

F18
E18

AH13
AH12

P41

CLK_PCI_FB

J42

R675 0R675 0

AH51

R676 0R676 0

AH53

XCLK_RCOMP

AF38

CLK_FLEX0

T45

CLK_FLEX1

P43

CLK_FLEX2

T42

CLK_FLEX3

N50

These are for
backdrive issue.

PCH_SMBDATA56

PCH_SMBCLK56

NC for Non-iAMT

1 2
1 2

R191 90.9/FR191 90.9/F

T100PAD T100PAD

T38PAD T38PAD

T22PAD T22PAD

To EC

R563 10KR563 10K

CLK_PCIE_VGA# 16
CLK_PCIE_VGA 16

CLK_PCIE_3GPLL# 3
CLK_PCIE_3GPLL 3

CLK_BUF_PCIE_3GPLL# 15
CLK_BUF_PCIE_3GPLL 15

CLK_BUF_BCLK# 15
CLK_BUF_BCLK 15

CLK_BUF_DREFCLK# 15
CLK_BUF_DREFCLK 15

CLK_BUF_DREFSSCLK# 15
CLK_BUF_DREFSSCLK 15

CLK_ICH_14M 15

5/3: Added 0 ohms to GND according
to Intel reccomandation

+1.05V_PCH

T18PAD T18PAD

T21PAD T21PAD

T19PAD T19PAD

T84PAD T84PAD

+3.3V_RUN

2

Q63

PCH_SMBDATA

PCH_SMBCLK

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Q63

3 1

2N7002W-7-F

2N7002W-7-F

+3.3V_RUN

2

Q60

Q60

3 1

2N7002W-7-F

2N7002W-7-F

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

PCH 3/6(PCI_SMBUS_CLK)

PCH 3/6(PCI_SMBUS_CLK)

PCH 3/6(PCI_SMBUS_CLK)

RM5 3A

RM5 3A

RM5 3A

2

1

1

4

RP7

RP7
4P2R-2.2K

4P2R-2.2K

3

Non-iAMT

MEM_SDATA 13,14,28,31,32,34

MEM_SCLK 13,14,28,31,32,34

of

of

of

961Thursday, August 20, 2009

961Thursday, August 20, 2009

961Thursday, August 20, 2009

5

4

3

2

1

IBEX PEAK-M (GPIO,VSS_NCTF,RSVD)

U39F

S_GPIO

SIO_EXT_SMI#29
SIO_EXT_SCI#29

TEST_WOOFER_EN39
PCIE_MCARD3_DET#32
PCIE_MCARD1_DET#31
PCIE_MCARD2_DET#32

USB_MCARD2_DET#32

CAMERA_CBL_DET#35

WLAN_RADIO_DIS#31

5

SIO_EXT_WAKE#29

T41 PADT41 PAD

T15 PADT15 PAD

R540 0R540 0
T101 PADT101 PAD
T98 PADT98 PAD

R192 0R192 0

R511 0R511 0

R538 10KR538 10K
R539 10KR539 10K
R575 10KR575 10K
R559 10KR559 10K
R272 10KR272 10K

R186 10KR186 10K
R196 10KR196 10K

R233 10KR233 10K
R257 10KR257 10K
R193 10KR193 10K
R527 10KR527 10K

R530 10KR530 10K
R532 10KR532 10K
R533 10KR533 10K

R223 10KR223 10K
R270 10KR270 10K
R222 1KR222 1K
R269 10KR269 10K

D D

WPAN_RADIO_DIS_MINI#32

C C

WWAN_RADIO_DIS#32

CRIT_TEMP_REP#29

SIO_RCIN#
SIO_A20GATE

B B

A A

SIO_EXT_SCI#
SIO_EXT_SMI#
SIO_EXT_WAKE#

CAMERA_CBL_DET#
SATA3GP

USB_MCARD2_DET#
PCIE_MCARD1_DET#
PCIE_MCARD2_DET#
PCIE_MCARD3_DET#

SATA5GP
S_GPIO
WLAN_RADIO_DIS#

PCH_GPIO28
GPIO12
TEST_WOOFER_EN
RSV_WOL_EN

SIO_EXT_SMI#
SIO_EXT_SCI#
SIO_EXT_WAKE#
RSV_WOL_EN
GPIO12
TEST_WOOFER_EN
PCIE_MCARD3_DET#
PCIE_MCARD1_DET#
PCIE_MCARD2_DET#

GPIO27
PCH_GPIO28
USB_MCARD2_DET#
GPIO35
CAMERA_CBL_DET#
SATA3GP
WLAN_RADIO_DIS#
CRB_SV_DET
GPIO45
GPIO46
SV_SET_UP
SATA5GP
GPIO57

+3.3V_RUN

+3.3V_SUS

Y3
C38
D37

J32

F10

K9

T7
AA2
F38

Y7
H10

AB12

V13
M11

V6
AB7

AB13

V3

P3

H3

F1
AB6
AA4

F8

A4
A49

A5
A50
A52
A53

B2

B4
B52
B53
BE1

BE53

BF1

BF53

BH1
BH2

BH52
BH53

BJ1
BJ2
BJ4

BJ49

BJ5

BJ50
BJ52
BJ53

D1

D2
D53

E1
E53

CRB_SV_DET

GPIO35

U39F

BMBUSY# / GPIO0
TACH1 / GPIO1
TACH2 / GPIO6
TACH3 / GPIO7
GPIO8
LAN_PHY_PWR_CTRL / GPIO12
GPIO15
SATA4GP / GPIO16
TACH0 / GPIO17
SCLOCK / GPIO22
GPIO24
GPIO27
GPIO28
STP_PCI# / GPIO34
SATACLKREQ# / GPIO35
SATA2GP / GPIO36
SATA3GP / GPIO37
SLOAD / GPIO38
SDATAOUT0 / GPIO39
PCIECLKRQ6# / GPIO45
PCIECLKRQ7# / GPIO46
SDATAOUT1 / GPIO48
SATA5GP / GPIO49
GPIO57

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31

IbexPeak-M_R1P0

IbexPeak-M_R1P0

4

+3.3V_RUN

R543

R543
10K

10K

R217

R217
10K

10K

GPIO

GPIO

NCTF

NCTF

CLKOUT_PCIE6N

CLKOUT_PCIE6P

CLKOUT_PCIE7N

MISC

MISC

CLKOUT_BCLK0_N / CLKOUT_PCIE8N
CLKOUT_BCLK0_P / CLKOUT_PCIE8P

CPU

CPU

RSVD

RSVD

CLKOUT_PCIE7P

GPIO57

A20GATE

PECI

RCIN#

PROCPWRGD

THRMTRIP#

TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18

TP19
NC_1
NC_2
NC_3
NC_4
NC_5

INIT3_3V#

TP24

+3.3V_SUS

TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9

R256

R256
10K

10K

R677

R677
*10K_NC

*10K_NC

AH45
AH46

AF48
AF47

SIO_A20GATE

U2

AM3
AM1
BG10
T1
BE10
BD10

BA22
AW22

PCH_TP3

BB22
AY45

Note : TP3 is not part of the JTAG
interface, but is required to select

AY46

the Boundary Scan test mode.

AV43
AV45
AF13
M18
N18
AJ24
AK41
AK42
M32
N32
M30
N30
H12
AA23
AB45
AB38
AB42
AB41
T39

P6
C10

!!!
5/6: Added GPIO57 to
recognize
M96 and Madison
1 = M96 ; 0 = Madison

3

SIO_A20GATE 29

CLK_CPU_BCLK# 3
CLK_CPU_BCLK 3
H_PECI 3
SIO_RCIN# 29
H_CPUPWRGD 3,56

R181 56R181 56

T14PAD T14PAD

+1.1V_VTT

R17856R178
56

H_THERM# 3

NV_ALE9
NV_CLE9

2/12: Peter: According to checklist,
default is set to low for disabling anti ­theif!

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

+NVRAM_VCCQ

R185 *1K_NCR185 *1K_NC
R189 *1K_NCR189 *1K_NC

DMI Termination Voltage

NV_CLE

Set to Vcc when LOW
Set to Vcc/2 when HIGH

Anti-Thief Enabled

NV_ALE

High = Enable (Default)
Low = Disable

SV_SET_UP

R187 10KR187 10K

+3.3V_RUN

SV_SET_UP 1-X High = Strong (Default)

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

PCH 4/6(GPIO)

PCH 4/6(GPIO)

PCH 4/6(GPIO)

RM5 3A

RM5 3A

RM5 3A

10 61Thursday, August 20, 2009

10 61Thursday, August 20, 2009

10 61Thursday, August 20, 2009

of

of

1

of

5

U39G

IBEX PEAK-M (POWER)

D D

+1.05V_PCH

+1.05V_VCCIO

PJP8

PJP8

+1.05V_PCH

C C

B B

A A

POWER_JP

POWER_JP

+1.05V_PCH

5

12

+1.05V_PCH

+1.05V_PCH

L62 *1uH_NCL62 *1uH_NC

C331

C331
10U

10U

+3.3V_RUN

L63 *1uH_NCL63 *1uH_NC

C350

C350
10U

10U

+1.05V_RUN_PLLEXP

C3471UC347

C3331UC333

1U

1U

C352

C352

0.1U

0.1U

+1.8V_RUN

+V1.1LAN_VCCAPLL_FDI

+1.05V_PCH

C662

C662
*10U_NC

*10U_NC

C661

C661
*10U_NC

*10U_NC

C3421UC342
1U

C3821UC382

1U

C3611UC361
1U

AB24
AB26

AB28
AD26
AD28

AF26

AF28

AF30

AF31
AH26
AH28
AH30
AH31

AJ30

AJ31

AK24

BJ24

AN20
AN22
AN23
AN24
AN26
AN28

BJ26

BJ28

AT26

AT28
AU26
AU28

AV26

AV28

AW26
AW28

BA26

BA28

BB26

BB28
BC26
BC28
BD26
BD28

BE26

BE28
BG26
BG28
BH27

AN30
AN31

AN35

AT22

BJ18
AM23

U39G

VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]

VCCIO[24]

VCCAPLLEXP

VCCIO[25]
VCCIO[26]
VCCIO[27]
VCCIO[28]
VCCIO[29]
VCCIO[30]
VCCIO[31]
VCCIO[32]
VCCIO[33]
VCCIO[34]
VCCIO[35]
VCCIO[36]
VCCIO[37]
VCCIO[38]
VCCIO[39]
VCCIO[40]
VCCIO[41]
VCCIO[42]
VCCIO[43]
VCCIO[44]
VCCIO[45]
VCCIO[46]
VCCIO[47]
VCCIO[48]
VCCIO[49]
VCCIO[50]
VCCIO[51]
VCCIO[52]
VCCIO[53]

VCCIO[54]
VCCIO[55]

VCC3_3[1]

VCCVRM[1]
VCCFDIPLL
VCCIO[1]

IbexPeak-M_R1P0

IbexPeak-M_R1P0

4

POWER

POWER

CRTLVDS

CRTLVDS

VCC CORE

VCC CORE

VCCTX_LVDS[1]
VCCTX_LVDS[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]

HVCMOS

HVCMOS

DMI

DMI

PCI E*

PCI E*

NAND / SPI

NAND / SPI

FDI

FDI

+1.05V_PCH

L60 10uHL60 10uH

L61 10uHL61 10uH

Use External Graphics. Can connect power directly
without Inductor & Cap ? As Ibex peak-M EDS 1.0,
need +1.05V. Can use +1.1V_VTT as CPU ?

4

VCCADAC[1]

VCCADAC[2]
VSSA_DAC[1]
VSSA_DAC[2]

VCCALVDS

VSSA_LVDS

VCC3_3[2]
VCC3_3[3]
VCC3_3[4]

VCCVRM[2]

VCCDMI[1]
VCCDMI[2]

VCCPNAND[1]
VCCPNAND[2]
VCCPNAND[3]
VCCPNAND[4]
VCCPNAND[5]
VCCPNAND[6]
VCCPNAND[7]
VCCPNAND[8]
VCCPNAND[9]

VCCME3_3[1]
VCCME3_3[2]
VCCME3_3[3]
VCCME3_3[4]

C652

C652
220U

220U

3528

3528

C653

C653
220U

220U

3528

3528

AE50
AE52
AF53
AF51

AH38
AH39

AP43
AP45
AT46
AT45

AB34
AB35
AD35

AT24

AT16
AU16

AM16
AK16
AK20
AK19
AK15
AK13
AM12
AM13
AM15

AM8
AM9
AP11
AP9

+1.05V_VCCADPLLA

+

+

C6631UC663
1U

+1.05V_VCCADPLLB

+

+

C6641UC664
1U

+3.3V_RUN

C396

C396

0.1U

0.1U

+VCCDMI

C3341UC334
1U

+NVRAM_VCCQ

C358

C358

0.1U

0.1U

+3.3V_RUN

C343

C343

0.1U

0.1U

+1.05V_PCH

+3.3V_RUN

+1.8V_RUN

R184 0R184 0
R183 *0_NCR183 *0_NC

R194

R194

*0_0603_NC

*0_0603_NC

12

R195

R195

0_0603

0_0603

12

3

L59 *10uH_NCL59 *10uH_NC

+1.05V_PCH

+1.05V_PCH

+1.1V_VTT
+1.05V_PCH

+3.3V_RUN
+1.8V_RUN

+1.1V_VTT

+RTC_CELL

3

+1.05V_PCH

+3.3V_SUS

+3.3V_RUN

C359

C359
22U

22U

+1.05V_RUN_VCCA_CLK

C643

C643
*10U_NC

*10U_NC

C385

C385

0.1U

0.1U

C354

C354
22U

22U

+VCCRTCEXT

C388 0.1UC388 0.1U

+1.8V_RUN

+1.05V_VCCADPLLA

+1.05V_VCCADPLLB

C3791UC379

C3801UC380

C3771UC377

1U

1U

1U

+VCCSST

C376 0.1UC376 0.1U

+V1.1LAN_INT_VCCSUS

C386

C386

0.1U

0.1U

C394

C394

0.1U

0.1U

C387

C387

0.1U

0.1U

C325

C325

C326

C326

C344

C344

4.7U

4.7U

0.1U

0.1U

C6971UC697
1U

0.1U

0.1U

C705

C705

0.1U

0.1U

C644

C644
*1U_NC

*1U_NC

C3811UC381
1U

C704

C704

0.1U

0.1U

AP51
AP53

AF23
AF24

AD38
AD39
AD41

AF43
AF41
AF42

AU24

BB51
BB53

BD51
BD53

AH23
AH35

AF34

AH34

AF32

AT18

AU18

AJ35

U39J

U39J

VCCACLK[1]
VCCACLK[2]

VCCLAN[1]
VCCLAN[2]

Y20

DCPSUSBYP

VCCME[1]
VCCME[2]
VCCME[3]
VCCME[4]
VCCME[5]
VCCME[6]

V39

VCCME[7]

V41

VCCME[8]

V42

VCCME[9]

Y39

VCCME[10]

Y41

VCCME[11]

Y42

VCCME[12]

V9

DCPRTC

VCCVRM[3]

VCCADPLLA[1]
VCCADPLLA[2]

VCCADPLLB[1]
VCCADPLLB[2]

VCCIO[21]
VCCIO[22]
VCCIO[23]

VCCIO[2]
VCCIO[3]
VCCIO[4]

V12

DCPSST

Y22

DCPSUS

P18

VCCSUS3_3[29]

U19

VCCSUS3_3[30]

U20

VCCSUS3_3[31]

U22

VCCSUS3_3[32]

V15

VCC3_3[5]

V16

VCC3_3[6]

Y16

VCC3_3[7]

V_CPU_IO[1]

V_CPU_IO[2]

A12

VCCRTC

IbexPeak-M_R1P0

IbexPeak-M_R1P0

2

POWER

POWER

VCCSUS3_3[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCCSUS3_3[6]
VCCSUS3_3[7]
VCCSUS3_3[8]

VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]

USB

USB

VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]
VCCSUS3_3[21]
VCCSUS3_3[22]
VCCSUS3_3[23]
VCCSUS3_3[24]
VCCSUS3_3[25]
VCCSUS3_3[26]
VCCSUS3_3[27]

VCCSUS3_3[28]

Clock and Miscellaneous

Clock and Miscellaneous

PCI/GPIO/LPC

PCI/GPIO/LPC

VCCSATAPLL[1]
VCCSATAPLL[2]

SATA

SATA

PCI/GPIO/LPC

PCI/GPIO/LPC

CPU

CPU

RTC

RTC

HDA

HDA

2

VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]

VCCIO[56]

V5REF_SUS

V5REF

VCC3_3[8]

VCC3_3[9]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]

VCC3_3[14]

VCCIO[9]

VCCVRM[4]

VCCIO[10]

VCCIO[11]

VCCIO[12]

VCCIO[13]

VCCIO[14]

VCCIO[15]

VCCIO[16]

VCCIO[17]

VCCIO[18]

VCCIO[19]

VCCIO[20]
VCCME[13]

VCCME[14]
VCCME[15]
VCCME[16]

VCCSUSHDA

V24
V26
Y24
Y26

V28
U28
U26
U24
P28
P26
N28
N26
M28
M26
L28
L26
J28
J26
H28
H26
G28
G26
F28
F26
E28
E26
C28
C26
B27
A28
A26

U23
V23
F24

K49

J38
L38
M36
N36
P36
U35

AD13

AK3
AK1

AH22

AT20

AH19
AD20
AF22
AD19

AF20
AF19
AH20

AB19
AB20
AB22
AD22

AA34
Y34
Y35
AA35

L30

+V5REF_SUS

+V5REF

C673

C673

*1U_NC

*1U_NC

+1.8V_RUN

+VCCSUSHDA

C3841UC384
1U

C399

C399

C391

C391

0.1U

0.1U

0.1U

0.1U

+1.05V_PCH

C400

C400
1uF

1uF

C395

C395
1uF

1uF

C390

C390

0.1U

0.1U

C340

C340

0.1U

0.1U

+V1.1LAN_VCCAPLL

C671

C671
*10U_NC

*10U_NC

+1.05V_PCH

R224 0_0603R224 0_0603

C3981UC398
1U

1

+1.05V_PCH

+3.3V_SUS

Scott_0626:Change D9,D10 PN from BCRB500VZ29
to BC010K45004.

R274 100R274 100

1 2

D9 SDM10K45-7-FD9 SDM10K45-7-F

R230 100R230 100

1 2

D10 SDM10K45-7-FD10 SDM10K45-7-F

+3.3V_RUN

L64 *10uH_NCL64 *10uH_NC

C3831UC383
1U

12

Title

Title

Title

PCH 5/6(POWER)

PCH 5/6(POWER)

PCH 5/6(POWER)

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

RM5 3A

RM5 3A

RM5 3A

Date: Sheet

Date: Sheet

Date: Sheet

+5V_SUS
+3.3V_SUS

+5V_RUN
+3.3V_RUN

+1.05V_PCH

+1.05V_PCH

+3.3V_SUS

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

1

11 61Thursday, August 20, 2009

11 61Thursday, August 20, 2009

11 61Thursday, August 20, 2009

of

of

of

5

4

3

2

1

U39H

AB16

VSS[0]

AA19

VSS[1]

AA20

VSS[2]

AA22

VSS[3]

AM19

VSS[4]

AA24

VSS[5]

AA26

VSS[6]

D D

C C

B B

A A

AA28
AA30
AA31
AA32
AB11
AB15
AB23
AB30
AB31
AB32
AB39
AB43
AB47

AC52
AD11
AD12
AD16
AD23
AD30
AD31
AD32
AD34
AU22
AD42
AD46
AD49

AF12
AH49
AF35

AP13
AN34
AF45
AF46
AF49

AG52
AH11
AH15
AH16
AH24
AH32
AV18
AH43
AH47

AJ19
AJ20

AJ22
AJ23
AJ26
AJ28
AJ32
AJ34

AK12

AM41

AN19
AK26
AK22
AK23
AK28

AB5
AB8
AC2

AD7
AE2
AE4

AU4

AF5
AF8
AG2

AH7

AT5

Y13

AJ2

AJ4

VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]

IbexPeak-M_R1P0

IbexPeak-M_R1P0

5

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

AK30
AK31
AK32
AK34
AK35
AK38
AK43
AK46
AK49
AK5
AK8
AL2
AL52
AM11
BB44
AD24
AM20
AM22
AM24
AM26
AM28
BA42
AM30
AM31
AM32
AM34
AM35
AM38
AM39
AM42
AU20
AM46
AV22
AM49
AM7
AA50
BB10
AN32
AN50
AN52
AP12
AP42
AP46
AP49
AP5
AP8
AR2
AR52
AT11
BA12
AH48
AT32
AT36
AT41
AT47
AT7
AV12
AV16
AV20
AV24
AV30
AV34
AV38
AV42
AV46
AV49
AV5
AV8
AW14
AW18
AW2
BF9
AW32
AW36
AW40
AW52
AY11
AY43
AY47

4

BG12

BB12
BB16
BB20
BB24
BB30
BB34
BB38
BB42
BB49

BC10
BC14
BC18

BC22
BC32
BC36
BC40
BC44
BC52

BD48
BD49

BE12
BE16
BE20
BE24
BE30
BE34
BE38
BE42
BE46
BE48
BE50

BF49

BF51
BG18
BG24

BG50

BH11

BH15

BH19

BH23

BH31

BH35

BH39

BH43

BH47

AF39

AY7
B11
B15
B19
B23
B31
B35
B39
B43
B47

BB5

BC2

BH9

BD5

BE6
BE8
BF3

BG4

BH7
C12
C50
D51
E12
E16
E20
E24
E30
E34
E38
E42
E46
E48

G10
G14
G18

G22
G32
G36
G40
G44
G52

H16
H20
H30
H34
H38
H42

B7

E6
E8

F49

F5

G2

U39I

U39I

VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]

IbexPeak-M_R1P0

IbexPeak-M_R1P0

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[326]
VSS[327]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[332]
VSS[333]
VSS[334]
VSS[335]
VSS[336]
VSS[337]
VSS[338]
VSS[339]
VSS[340]
VSS[341]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
VSS[353]
VSS[354]
VSS[355]
VSS[356]
VSS[366]

H49
H5
J24
K11
K43
K47
K7
L14
L18
L2
L22
L32
L36
L40
L52
M12
M16
M20
N38
M34
M38
M42
M46
M49
M5
M8
N24
P11
AD15
P22
P30
P32
P34
P42
P45
P47
R2
R52
T12
T41
T46
T49
T5
T8
U30
U31
U32
U34
P38
V11
P16
V19
V20
V22
V30
V31
V32
V34
V35
V38
V43
V45
V46
V47
V49
V5
V7
V8
W2
W52
Y11
Y12
Y15
Y19
Y23
Y28
Y30
Y31
Y32
Y38
Y43
Y46
P49
Y5
Y6
Y8
P24
T43
AD51
AT8
AD47
Y47
AT12
AM6
AT13
AM5
AK45
AK39
AV14

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

3

2

Date: Sheet

COMPUTER

PCH 6/6(GND)

PCH 6/6(GND)

PCH 6/6(GND)

RM5 3A

RM5 3A

RM5 3A

12 61Thursday, August 20, 2009

12 61Thursday, August 20, 2009

12 61Thursday, August 20, 2009

of

of

1

of

U39H

IBEX PEAK-M (GND)

5

5/13: Change connector from Tyco to Foxconn to avoid shortage

JDIM2A

M_A_A[15:0]4

D D

M_A_BS04
M_A_BS14
M_A_BS24
M_A_CS#04
M_A_CS#14
M_A_CLK04
M_A_CLK0#4
M_A_CLK14
M_A_CLK1#4
M_A_CKE04
M_A_CKE14
M_A_CAS#4
M_A_RAS#4
M_A_WE#4

MEM_SCLK9,14,28,31,32,34

MEM_SDATA9,14,28,31,32,34
M_A_ODT04

R293

R293
10K

10K

1 2

+1.5V_SUS

M_A_DM[7:0]4

M_A_DQS[7:0]4

M_A_DQS#[7:0]4

1 2

C305

C305
10U

10U

C420

C420
1U/6.3V_4

1U/6.3V_4

M_A_ODT14

SA1_DIM0_0
SA0_DIM0_0

R278

R278
10K

10K

C370

C370
10U

10U

C417

C417
1U/6.3V_4

1U/6.3V_4

5

C C

B B

A A

+0.75V_DDR_VTT

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

SA0_DIM0_0
SA1_DIM0_0
MEM_SCLK
MEM_SDATA

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

Note:
If SA1_DIM0 = 0, SA0_DIM0 = 0
SO-DIMMA SPD Address is 0xA0
SO-DIMMA TS Address is 0x30
If SA1_DIM0 = 0, SA0_DIM0 = 1
SO-DIMMA SPD Address is 0xA2
SO-DIMMA TS Address is 0x32

C368

C368

C307

C307

10U

10U

10U

10U

C421

C421

C418

C418

1U/6.3V_4

1U/6.3V_4

1U/6.3V_4

1U/6.3V_4

JDIM2A

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12/BC#

119

A13

80

A14

78

A15

109

BA0

108

BA1

79

BA2

114

S0#

121

S1#

101

CK0

103

CK0#

102

CK1

104

CK1#

73

CKE0

74

CKE1

115

CAS#

110

RAS#

113

WE#

197

SA0

201

SA1

202

SCL

200

SDA

116

ODT0

120

ODT1

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

PC2100 DDR3 SDRAM SO-DIMM

12
29
47

64
137
154
171
188

10

27

45

62
135
152
169
186

PC2100 DDR3 SDRAM SO-DIMM

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7

AS0A626-U4SN-7F

AS0A626-U4SN-7F

Channel A Decoupling

C316

C419

C419
10U

10U

C335

C335
10U

10U

C316
.1U/10V_4

.1U/10V_4

C338

C338
10U

10U

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46

(204P)

(204P)

DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

C362

C362
.1U/10V_4

.1U/10V_4

4

M_A_DQ0

5

M_A_DQ1

7

M_A_DQ2

15

M_A_DQ3

17

M_A_DQ4

4

M_A_DQ5

6

M_A_DQ6

16

M_A_DQ7

18

M_A_DQ8

21

M_A_DQ9

23

M_A_DQ10

33

M_A_DQ11

35

M_A_DQ12

22

M_A_DQ13

24

M_A_DQ14

34

M_A_DQ15

36

M_A_DQ16

39

M_A_DQ17

41

M_A_DQ18

51

M_A_DQ19

53

M_A_DQ20

40

M_A_DQ21

42

M_A_DQ22

50

M_A_DQ23

52

M_A_DQ24

57

M_A_DQ25

59

M_A_DQ26

67

M_A_DQ27

69

M_A_DQ28

56

M_A_DQ29

58

M_A_DQ30

68

M_A_DQ31

70

M_A_DQ32

129

M_A_DQ33

131

M_A_DQ34

141

M_A_DQ35

143

M_A_DQ36

130

M_A_DQ37

132

M_A_DQ38

140

M_A_DQ39

142

M_A_DQ40

147

M_A_DQ41

149

M_A_DQ42

157

M_A_DQ43

159

M_A_DQ44

146

M_A_DQ45

148

M_A_DQ46

158

M_A_DQ47

160

M_A_DQ48

163

M_A_DQ49

165

M_A_DQ50

175

M_A_DQ51

177

M_A_DQ52

164

M_A_DQ53

166

M_A_DQ54

174

M_A_DQ55

176

M_A_DQ56

181

M_A_DQ57

183

M_A_DQ58

191

M_A_DQ59

193

M_A_DQ60

180

M_A_DQ61

182

M_A_DQ62

192

M_A_DQ63

194

M_A_DQ[63:0] 4

3

Channel A

PM_EXTTS#03

DDR3_DRAMRST#3,14

M_VREF_DQ_DIMM0

M_VREF_CA_DIMM0

+3.3V_RUN

C402

C402

2.2U/6.3V_6

2.2U/6.3V_6

2.2U/6.3V_6

2.2U/6.3V_6

2.2U/6.3V_6

2.2U/6.3V_6

PM_EXTTS#0

C272

C272

C374

C374

C404

C404
.1U/10V_4

.1U/10V_4

C275

C275
.1U/10V_4

.1U/10V_4

C372

C372
.1U/10V_4

.1U/10V_4

+1.5V_SUS

For CH A SO-DIMM VREF_DQ for M2

Delete according to Intel Design Change

M1 VREF

5/18: Separate voltage divider for M_VREF_DQ_DIMM0
and M_VREF_CA_DIMM0 to follow Intel CRB design

JDIM2B

JDIM2B

75

VDD1

76

VDD2

81

VDD3

82

VDD4

87

VDD5

88

VDD6

93

VDD7

94

VDD8

99

VDD9

100

VDD10

105

VDD11

106

VDD12

111

VDD13

112

VDD14

117

VDD15

118

VDD16

123

VDD17

124

VDD18

199

VDDSPD

77

NC1

122

NC2

125

NCTEST

198

EVENT#

30

RESET#

1

VREF_DQ

126

VREF_CA

2

VSS1

3

VSS2

8

VSS3

9

VSS4

13

VSS5

14

VSS6

19

VSS7

20

VSS8

25

VSS9

26

VSS10

31

VSS11

32

VSS12

37

VSS13

38

VSS14

43

VSS15

AS0A626-U4SN-7F

AS0A626-U4SN-7F

2

44

VSS16

48

VSS17

49

VSS18

54

VSS19

55

VSS20

60

VSS21

61

VSS22

65

VSS23

66

VSS24

71

VSS25

72

VSS26

127

VSS27

128

VSS28

133

VSS29

134

VSS30

138

VSS31

139

VSS32

144

VSS33

145

VSS34

150

VSS35

151

VSS36

155

VSS37

156

VSS38

161

VSS39

162

VSS40

167

VSS41

168

VSS42

172

VSS43

173

VSS44

178

VSS45

179

VSS46

184

VSS47

185

VSS48

189

VSS49

190

VSS50

195

VSS51

196

VSS52

(204P)

(204P)

PC2100 DDR3 SDRAM SO-DIMM

PC2100 DDR3 SDRAM SO-DIMM

VTT1
VTT2

203
204

205

G1

206

G2

207

H1

208

H2

+0.75V_DDR_VTT

1

6/02: Change M1 from voltage regulator to voltage divider

+DDR_VTTREF

R685

R685
*0_NC

+1.5V_SUS

R155 1K/FR155 1K/F

1 2

R153

R153
1K/F

1K/F

+

+

C687

C319

C319

C348

C348

.1U/10V_4

.1U/10V_4

.1U/10V_4

.1U/10V_4

4

C323

C323
.1U/10V_4

.1U/10V_4

C687
330U

330U

+1.5V_SUS

R143 1K/FR143 1K/F

3

1 2

R151

R151
1K/F

1K/F

*0_NC

1 2

C283

C283
.1U/10V_4

.1U/10V_4

1 2

R686

R686
*0_NC

*0_NC

1 2

C860

C860
.1U/10V_4

.1U/10V_4

1 2

M_VREF_DQ_DIMM0

+DDR_VTTREF

M_VREF_CA_DIMM0

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

COMPUTER

DDR3 DIMM-A

DDR3 DIMM-A

DDR3 DIMM-A

RM5 3A

RM5 3A

RM5 3A

13 61Thursday, August 20, 2009

13 61Thursday, August 20, 2009

13 61Thursday, August 20, 2009

of

of

1

of

5

5/13: Change connector from Tyco to Foxconn to avoid shortage

JDIM1A

C337

C337
10U

10U

JDIM1A

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10/AP

84

A11

83

A12/BC#

119

A13

80

A14

78

A15

109

BA0

108

BA1

79

BA2

114

S0#

121

S1#

101

CK0

103

CK0#

102

CK1

104

CK1#

73

CKE0

74

CKE1

115

CAS#

110

RAS#

113

WE#

197

SA0

201

SA1

202

SCL

200

SDA

116

ODT0

120

ODT1

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

10

DQS#0

27

DQS#1

45

DQS#2

62

DQS#3

135

DQS#4

152

DQS#5

169

DQS#6

186

DQS#7

AS0A626-U8SN-7F

AS0A626-U8SN-7F

C369

C369
10U

10U

C414

C414
10U

10U

PC2100 DDR3 SDRAM SO-DIMM

PC2100 DDR3 SDRAM SO-DIMM

C314

C314
.1U/10V_4

.1U/10V_4

M_B_A[15:0]4

D D

M_B_BS04
M_B_BS14
M_B_BS24
M_B_CS#04
M_B_CS#14
M_B_CLK04
M_B_CLK0#4
M_B_CLK14
M_B_CLK1#4
M_B_CKE04
M_B_CKE14
M_B_CAS#4
M_B_RAS#4
M_B_WE#4

MEM_SCLK9,13,28,31,32,34

MEM_SDATA9,13,28,31,32,34
M_B_ODT04

+3.3V_RUN

R280

R280
10K

10K

1 2

SA1_DIM1_0
SA0_DIM1_0

1 2

+1.5V_SUS

C308

C308
10U

10U

C413

C413
1U/6.3V_4

1U/6.3V_4

R275

R275
10K

10K

M_B_ODT14

M_B_DM[7:0]4

M_B_DQS[7:0]4

M_B_DQS#[7:0]4

C341

C341
10U

10U

C412

C412
1U/6.3V_4

1U/6.3V_4

5

C C

B B

A A

+0.75V_DDR_VTT

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

SA0_DIM1_0
SA1_DIM1_0
MEM_SCLK
MEM_SDATA

M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

Note:
If SA1_DIM1 = 1, SA0_DIM1 = 0
SO-DIMMA SPD Address is 0xA4
SO-DIMMA TS Address is 0x34
If SA1_DIM1 = 1, SA0_DIM1 = 1
SO-DIMMA SPD Address is 0xA6
SO-DIMMA TS Address is 0x36

Channel B Decoupling

C367

C367

C306

C306

10U

10U

10U

10U

C416

C416

C415

C415

1U/6.3V_4

1U/6.3V_4

1U/6.3V_4

1U/6.3V_4

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46

(204P)

(204P)

DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

C320

C320
.1U/10V_4

.1U/10V_4

5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194

4

4

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

C357

C357
.1U/10V_4

.1U/10V_4

C322

C322
.1U/10V_4

.1U/10V_4

M_B_DQ[63:0] 4

C360

C360
.1U/10V_4

.1U/10V_4

3

Channel B

+3.3V_RUN

C403

C403

2.2U/6.3V_6

2.2U/6.3V_6

C274

C274

2.2U/6.3V_6

2.2U/6.3V_6

C375

C375

2.2U/6.3V_6

2.2U/6.3V_6

PM_EXTTS#1

PM_EXTTS#13

DDR3_DRAMRST#3,13

M_VREF_DQ_DIMM1

M_VREF_CA_DIMM1

For CH B SO-DIMM VREF_DQ for M2

Delete according to Intel Design Change

M1 VREF

+

+

C667

C667
330U

330U

5/18: Separate voltage divider for M_VREF_DQ_DIMM1
and M_VREF_CA_DIMM1 to follow Intel CRB design

6/02: Change M1 from voltage regulator to voltage divider

+1.5V_SUS

R154 1K/FR154 1K/F

+1.5V_SUS

3

1 2

R141 1K/FR141 1K/F

1 2

R152

R152
1K/F

1K/F

R150

R150
1K/F

1K/F

1 2

C282

C282
.1U/10V_4

.1U/10V_4

1 2

1 2

1 2

C406

C406
.1U/10V_4

.1U/10V_4

C276

C276
.1U/10V_4

.1U/10V_4

C373

C373
.1U/10V_4

.1U/10V_4

R687

R687
*0_NC

*0_NC

R688

R688
*0_NC

*0_NC

C861

C861
.1U/10V_4

.1U/10V_4

+1.5V_SUS

75
76
81
82
87
88
93
94

99
100
105
106
111
112
117
118
123
124

199

77
122
125

198

30

1

126

2
3
8

9
13
14
19
20
25
26
31
32
37
38
43

+DDR_VTTREF

M_VREF_DQ_DIMM1

+DDR_VTTREF

M_VREF_CA_DIMM1

2

JDIM1B

JDIM1B

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

VDDSPD
NC1

NC2
NCTEST

EVENT#
RESET#

VREF_DQ
VREF_CA

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8

PC2100 DDR3 SDRAM SO-DIMM

PC2100 DDR3 SDRAM SO-DIMM

VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15

AS0A626-U8SN-7F

AS0A626-U8SN-7F

2

44

VSS16

48

VSS17

49

VSS18

54

VSS19

55

VSS20

60

VSS21

61

VSS22

65

VSS23

66

VSS24

71

VSS25

72

VSS26

127

VSS27

128

VSS28

133

VSS29

134

VSS30

138

VSS31

139

VSS32

144

VSS33

145

VSS34

150

VSS35

151

VSS36

155

VSS37

156

VSS38

161

VSS39

162

VSS40

167

VSS41

168

VSS42

172

VSS43

173

VSS44

178

VSS45

179

VSS46

184

VSS47

185

VSS48

189

VSS49

190

VSS50

195

VSS51

196

VSS52

(204P)

(204P)

203

VTT1

204

VTT2

205

G1

206

G2

207

H1

208

H2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

+0.75V_DDR_VTT

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

DDR3 DIMM-B

DDR3 DIMM-B

DDR3 DIMM-B

RM5 3A

RM5 3A

RM5 3A

1

14 61Thursday, August 20, 2009

14 61Thursday, August 20, 2009

14 61Thursday, August 20, 2009

of

of

1

of

5

4

3

2

1

+3.3V_RUN

L68 BLM21PG600SN1D

L68 BLM21PG600SN1D

0805

D D

0805

8

CK_PWRGD_R43
CLK_ICH_14M9

C C

Realtek: 0.1uFx6pcs, 22uFx1pcs
IDT: 0.1uFx5pcs, 10uFx1pcs

C738

C738

C761

C761

0.1U

0.1U

10U/6.3V

10U/6.3V

0.1uF near the every power pin.

+3.3V_RUN

CLK_ICH_14M

Place the 33 ohm
resistors close to the CK 505

C754

C754

C746

C746

0.1U

0.1U

0.1U

0.1U

R607 10KR607 10K
R590 33R590 33

EC_SMBDAT037

EC_SMBCLK037

40mil

C749

C749

0.1U

0.1U

C745

C745

0.1U

0.1U

+3.3V_CLK_VDD

+VDDIO_CLK

CPU_SEL

XTAL_OUT
XTAL_IN

EC_SMBDAT0
EC_SMBCLK0

XTAL_IN XTAL_OUT

C733

C733
33P

33P

50

50

1

5
17
24
29
15
18

9

2

8
12
21
26

16
25
30

27
28

31
32

Y5

Y5

14.318MHZ

14.318MHZ

U47

U47

VDD_USB
VDD_LCD
VDD_SRC
VDD_CPU
VDD_REF
VDD_SRC_IO
VDD_CPU_IO

VSS_SATA
VSS_USB
VSS_LCD
VSS_SRC
VSS_CPU
VSS_REF

CPU_STOP#
CK_PWRGD/PD#_3.3
REF_0/CPU_SEL

XOUT
XIN

SDATA
SCLK

SLG8SP585VTR

SLG8SP585VTR

21

CK505

CK505

QFN32

QFN32

C734

C734
33P

33P

1 2

50

50

CPU-0

CPU-0#

CPU-1

CPU-1#

DOT96T_LPR

DOT96C_LPR

SRC-1

SRC-1#

SATA

SATA#

27MHz_nonSS

27MHz_SS

CLK_BUF_BCLK

23

CLK_BUF_BCLK#

22
20

19

CLK_BUF_DREFCLK

3

CLK_BUF_DREFCLK#

4

CLK_BUF_PCIE_3GPLL

13

CLK_BUF_PCIE_3GPLL#

14

CLK_BUF_DREFSSCLK

10

CLK_BUF_DREFSSCLK#

11

27M_NSS

6

27M_SS

7

33

GND

+3.3V_RUN

R614 *0_NCR614 *0_NC

+1.05V_PCH

R613 0R613 0

SLG,IDT: +1.05V
Realtek: +3.3V

R601 33R601 33
R604 33R604 33

Place within

0.5" of CLKGEN

L69 BLM21PG600SN1D

L69 BLM21PG600SN1D

CLK_BUF_BCLK 9
CLK_BUF_BCLK# 9

CLK_BUF_DREFCLK 9
CLK_BUF_DREFCLK# 9

CLK_BUF_PCIE_3GPLL 9
CLK_BUF_PCIE_3GPLL# 9

CLK_BUF_DREFSSCLK 9
CLK_BUF_DREFSSCLK# 9

CLK_VGA_27M 17

CLK_VGA_27M_SS 17

Realtek: 0.1uFx3pcs, 22uFx1pcs
IDT: 0.1uFx2pcs, 10uFx1pcs

+VDDIO_CLK

0805

0805

C772

C772
10U

10U

40mil

C750

C750

0.1U

0.1U

C762

C762

0.1U

0.1U

HP: 10u x2pcs

Place each 0.1uF cap as close as
possible to each VDD IO pin. Place
the 10uF caps on the VDD_IO plane.

+VDDIO_CLK:
SLG date sheet (V0.2) P15: Min 1.05V,Max3.465V.
Realtek date sheet(V1.2) P11: Min 1.05V,Max 3.3V.

B B

A A

+3.3V_RUN

1 2

1 2

R591

R591
*4.7K_NC

*4.7K_NC

CPU_SEL

R592

R592

4.7K

4.7K

5

C737

C737
*10P_NC

*10P_NC

EMI Capacitor

PIN 30 CPU_0 CPU_1

0(default)

1(0.7V-1.5V)

133MHz

100MHz 100MHz

133MHz

4

CPU_SEL:
SLG date sheet (V0.2) P15:
High Voltage: Min 0.7V, Max 1.5V.
Low Voltage: Min Vss-0.3V, Max 0.35V.
Realtek date sheet(V1.2) P11:
High Voltage: Min 0.7V, Max 1.5V.
Low Voltage: Min Vss-0.3V, Max 0.35V.
IDT date sheet(V0.7) P10:
High Voltage: Min 0.7V, Max 1.5V.
Low Voltage: Min Vss-0.3V, Max 0.35V.

3

IDT date sheet(V0.7) P10: Min 0.9975V,Max 3.465V.

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

COMPUTER

CLOCK GENERATOR

CLOCK GENERATOR

CLOCK GENERATOR

RM5 3A

RM5 3A

RM5 3A

15 61Thursday, August 20, 2009

15 61Thursday, August 20, 2009

15 61Thursday, August 20, 2009

of

of

1

of

5

U29A

U29A

PCIE_MTX_GRX_P[0..15]3
PCIE_MTX_GRX_N[0..15]3

PCIE_MTX_GRX_P0
PCIE_MTX_GRX_N0

D D

C C

B B

CLK_PCIE_VGA9
CLK_PCIE_VGA#9

!!! Park, Madison : Pop 0 Ohm
M96: depop 0 ohm

PLTRST#3,9,26,28,29,31,32,41,56

PCIE_MTX_GRX_P1
PCIE_MTX_GRX_N1

PCIE_MTX_GRX_P2
PCIE_MTX_GRX_N2

PCIE_MTX_GRX_P3
PCIE_MTX_GRX_N3

PCIE_MTX_GRX_P4
PCIE_MTX_GRX_N4

PCIE_MTX_GRX_P5
PCIE_MTX_GRX_N5

PCIE_MTX_GRX_P6
PCIE_MTX_GRX_N6

PCIE_MTX_GRX_P7
PCIE_MTX_GRX_N7

PCIE_MTX_GRX_P8
PCIE_MTX_GRX_N8

PCIE_MTX_GRX_P9
PCIE_MTX_GRX_N9

PCIE_MTX_GRX_P10
PCIE_MTX_GRX_N10

PCIE_MTX_GRX_P11
PCIE_MTX_GRX_N11

PCIE_MTX_GRX_P12
PCIE_MTX_GRX_N12

PCIE_MTX_GRX_P13
PCIE_MTX_GRX_N13

PCIE_MTX_GRX_P14
PCIE_MTX_GRX_N14

PCIE_MTX_GRX_P15
PCIE_MTX_GRX_N15

R426 *0_NCR426 *0_NC

R1000R100

12

0

PERST#PERST#

AA38

PCIE_RX0P

Y37

PCIE_RX0N

Y35

PCIE_RX1P

W36

PCIE_RX1N

W38

PCIE_RX2P

V37

PCIE_RX2N

V35

PCIE_RX3P

U36

PCIE_RX3N

U38

PCIE_RX4P

T37

PCIE_RX4N

T35

PCIE_RX5P

R36

PCIE_RX5N

R38

PCIE_RX6P

P37

PCIE_RX6N

P35

PCIE_RX7P

N36

PCIE_RX7N

N38

PCIE_RX8P

M37

PCIE_RX8N

M35

PCIE_RX9P

L36

PCIE_RX9N

L38

PCIE_RX10P

K37

PCIE_RX10N

K35

PCIE_RX11P

J36

PCIE_RX11N

J38

PCIE_RX12P

H37

PCIE_RX12N

H35

PCIE_RX13P

G36

PCIE_RX13N

G38

PCIE_RX14P

F37

PCIE_RX14N

F35

PCIE_RX15P

E37

PCIE_RX15N

CLOCK

CLOCK

AB35

PCIE_REFCLKP

AA36

PCIE_REFCLKN

AJ21

NC#1

AK21

NC#2

AH16

PWRGOOD

AA30

PERSTB

216-0729051(M96-M2 XT)

216-0729051(M96-M2 XT)

4

ASIC PN 100-CK QCI P/N

----------------------------------------------------------------------------------------­M96-M2 XT A13 216-0729051 100-CK3186 AJ072900T08
M97-M2 LP A11 216-0731001 100-CG1806 AJ073100T01

PCIE_MRX_GTX_C_P0

PCIE_TX0P
PCIE_TX0N

PCIE_TX1P
PCIE_TX1N

PCIE_TX2P
PCIE_TX2N

PCIE_TX3P
PCIE_TX3N

PCIE_TX4P

PCI EXPRESS INTERFACE

PCI EXPRESS INTERFACE

PCIE_TX4N

PCIE_TX5P
PCIE_TX5N

PCIE_TX6P
PCIE_TX6N

PCIE_TX7P
PCIE_TX7N

PCIE_TX8P
PCIE_TX8N

PCIE_TX9P
PCIE_TX9N

PCIE_TX10P
PCIE_TX10N

PCIE_TX11P
PCIE_TX11N

PCIE_TX12P
PCIE_TX12N

PCIE_TX13P
PCIE_TX13N

PCIE_TX14P
PCIE_TX14N

PCIE_TX15P
PCIE_TX15N

CALIBRATION

CALIBRATION

PCIE_CALRP
PCIE_CALRN

Y33
Y32

W33
W32

U33
U32

U30
U29

T33
T32

T30
T29

P33
P32

P30
P29

N33
N32

N30
N29

L33
L32

L30
L29

K33
K32

J33
J32

K30
K29

H33
H32

Y30
Y29

PCIE_MRX_GTX_C_N0

PCIE_MRX_GTX_C_P1
PCIE_MRX_GTX_C_N1

PCIE_MRX_GTX_C_P2
PCIE_MRX_GTX_C_N2

PCIE_MRX_GTX_C_P3
PCIE_MRX_GTX_C_N3

PCIE_MRX_GTX_C_P4
PCIE_MRX_GTX_C_N4

PCIE_MRX_GTX_C_P5
PCIE_MRX_GTX_C_N5

PCIE_MRX_GTX_C_P6
PCIE_MRX_GTX_C_N6

PCIE_MRX_GTX_C_P7
PCIE_MRX_GTX_C_N7

PCIE_MRX_GTX_C_P8
PCIE_MRX_GTX_C_N8

PCIE_MRX_GTX_C_P9
PCIE_MRX_GTX_C_N9

PCIE_MRX_GTX_C_P10
PCIE_MRX_GTX_C_N10

PCIE_MRX_GTX_C_P11
PCIE_MRX_GTX_C_N11

PCIE_MRX_GTX_C_P12
PCIE_MRX_GTX_C_N12

PCIE_MRX_GTX_C_P13
PCIE_MRX_GTX_C_N13

PCIE_MRX_GTX_C_P14
PCIE_MRX_GTX_C_N14

PCIE_MRX_GTX_C_P15
PCIE_MRX_GTX_C_N15

R101 1.27KR101 1.27K
R99 2K/FR99 2K/F

3

PCIE_MRX_GTX_C_P0
PCIE_MRX_GTX_C_P1
PCIE_MRX_GTX_C_P2
PCIE_MRX_GTX_C_P3
PCIE_MRX_GTX_C_P4
PCIE_MRX_GTX_C_P5
PCIE_MRX_GTX_C_P6
PCIE_MRX_GTX_C_P7
PCIE_MRX_GTX_C_P8
PCIE_MRX_GTX_C_P9
PCIE_MRX_GTX_C_P10
PCIE_MRX_GTX_C_P11
PCIE_MRX_GTX_C_P12
PCIE_MRX_GTX_C_P13
PCIE_MRX_GTX_C_P14
PCIE_MRX_GTX_C_P15
PCIE_MRX_GTX_C_N0
PCIE_MRX_GTX_C_N1
PCIE_MRX_GTX_C_N2
PCIE_MRX_GTX_C_N3
PCIE_MRX_GTX_C_N4
PCIE_MRX_GTX_C_N5
PCIE_MRX_GTX_C_N6
PCIE_MRX_GTX_C_N7
PCIE_MRX_GTX_C_N8
PCIE_MRX_GTX_C_N9
PCIE_MRX_GTX_C_N10
PCIE_MRX_GTX_C_N11
PCIE_MRX_GTX_C_N12
PCIE_MRX_GTX_C_N13
PCIE_MRX_GTX_C_N14
PCIE_MRX_GTX_C_N15

+PCIE_VDDC

C189 0.1UC189 0.1U
C188 0.1UC188 0.1U
C205 0.1UC205 0.1U
C176 0.1UC176 0.1U
C212 0.1UC212 0.1U
C204 0.1UC204 0.1U
C218 0.1UC218 0.1U
C216 0.1UC216 0.1U
C222 0.1UC222 0.1U
C211 0.1UC211 0.1U
C230 0.1UC230 0.1U
C221 0.1UC221 0.1U
C245 0.1UC245 0.1U
C247 0.1UC247 0.1U
C249 0.1UC249 0.1U
C251 0.1UC251 0.1U
C194 0.1UC194 0.1U
C179 0.1UC179 0.1U
C207 0.1UC207 0.1U
C171 0.1UC171 0.1U
C215 0.1UC215 0.1U
C195 0.1UC195 0.1U
C219 0.1UC219 0.1U
C217 0.1UC217 0.1U
C223 0.1UC223 0.1U
C208 0.1UC208 0.1U
C231 0.1UC231 0.1U
C220 0.1UC220 0.1U
C246 0.1UC246 0.1U
C248 0.1UC248 0.1U
C250 0.1UC250 0.1U
C252 0.1UC252 0.1U

PCIE_MRX_GTX_P0
PCIE_MRX_GTX_P1
PCIE_MRX_GTX_P2
PCIE_MRX_GTX_P3
PCIE_MRX_GTX_P4
PCIE_MRX_GTX_P5
PCIE_MRX_GTX_P6
PCIE_MRX_GTX_P7
PCIE_MRX_GTX_P8
PCIE_MRX_GTX_P9
PCIE_MRX_GTX_P10
PCIE_MRX_GTX_P11
PCIE_MRX_GTX_P12
PCIE_MRX_GTX_P13
PCIE_MRX_GTX_P14
PCIE_MRX_GTX_P15
PCIE_MRX_GTX_N0
PCIE_MRX_GTX_N1
PCIE_MRX_GTX_N2
PCIE_MRX_GTX_N3
PCIE_MRX_GTX_N4
PCIE_MRX_GTX_N5
PCIE_MRX_GTX_N6
PCIE_MRX_GTX_N7
PCIE_MRX_GTX_N8
PCIE_MRX_GTX_N9
PCIE_MRX_GTX_N10
PCIE_MRX_GTX_N11
PCIE_MRX_GTX_N12
PCIE_MRX_GTX_N13
PCIE_MRX_GTX_N14
PCIE_MRX_GTX_N15

2

PCIE_MRX_GTX_P[0..15] 3

PCIE_MRX_GTX_N[0..15] 3

1

A A

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

COMPUTER

M96XT_PCIE

M96XT_PCIE

M96XT_PCIE

RM5 3A

RM5 3A

RM5 3A

16 61Thursday, August 20, 2009

16 61Thursday, August 20, 2009

16 61Thursday, August 20, 2009

of

of

1

of

5

RAM_

Memory Straps
800 MHz 512MB(32M*16) Hynix_Tiva die

reserve for Qimonda
reserve for Samsung

800 MHz 1GB(64M*16) Hynix_Orion die
800 MHz 1GB(64M*16) Qimonda_A1 die
800 MHz 1GB(64M*16) Samsung_E die

Note : Required Frequency = 800 MHz

D D

+1.8V_RUN

R427 10KR427 10K
R429 *10K_NCR429 *10K_NC
R428 *10K_NCR428 *10K_NC
R430 10KR430 10K

+3.3V_DELAY

R61 3KR61 3K
R62 *3K_NCR62 *3K_NC
R63 *3K_NCR63 *3K_NC

+3.3V_DELAY

R77 3KR77 3K
R79 3KR79 3K
R64 *3K_NCR64 *3K_NC
R85 *3K_NCR85 *3K_NC
R76 *3K_NCR76 *3K_NC
R80 3KR80 3K
R60 *3K_NCR60 *3K_NC
R83 *3K_NCR83 *3K_NC
R82 *3K_NCR82 *3K_NC
R81 *3K_NCR81 *3K_NC

R444 3KR444 3K
R442 3KR442 3K

R89 *3K_NCR89 *3K_NC

C C

B B

A A

R71 *10K_NCR71 *10K_NC

ATI_DP_HPD23

ATI_HDMI_DET23

1 2

+1.1V_GFX_PCIE

CLK_VGA_27M_SS15

+1.8V_RUN

RAM_TYPE_CFG0
RAM_TYPE_CFG1
RAM_TYPE_CFG2
RAM_TYPE_CFG3

RAM_CFG0
RAM_CFG1
RAM_CFG2

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO8
GFX_CORE_CNTRL2
GPIO10

VGAHSYNC
VGAVSYNC

VGAVSYNC2
TEMP_FAIL

R44

R44

*365K/F_NC

*365K/F_NC

R45

R45

*365K/F_NC

*365K/F_NC

+3.3V_DELAY

R47

R47

2

12

150K

150K

R50

R50
10K

10K

+3.3V_DELAY

R46

R46

12

2

150K

150K

R51

R51
10K

10K

L9

L9

BLM15BD121SN1D

BLM15BD121SN1D

120ohm, 300mA

L10

L10

BLM15BD121SN1D

BLM15BD121SN1D

120ohm, 300mA

H5TQ5163MFR-12

H5TQ1G63BFR-12C
IDGH1G-04A1F1C-16X
K4W1G1646E-HC12

VRAM TYPE

APERTURE SIZE

Q19

Q19

MMST3904-7-F

MMST3904-7-F

1 3

GPIO14_HPD2

Q20

Q20

MMST3904-7-F

MMST3904-7-F

1 3

C46

C46
10uF

10uF

C51

C51
10uF

10uF

R431 *0_NCR431 *0_NC

1 2

HPD1

C47

C47
1uF

1uF

C53

C53
1uF

1uF

RAM_
TYPE_CFG2

TYPE_CFG3

1111

11
1

1
1

0

1

01

MEMORY APERTURE SIZE SELECT
MEMORY

CFG2

SIZE

GPIO13

128MB
256MB
64MB

+DPLL_PVDD

C48

C48

(1.8V @ 120mA DPLL_PVDD)

100nF

100nF

+DPLL_VDDC

C54

C54

!!!
(1.1V @ 150mA DPLL_VDDC)

100nF

100nF

(1.0V @ 150mA DPLL_VDDC for M97)

CLK_VGA_27M_SS_R

12

R432

R432
*10K_NC

*10K_NC

CLK_VGA_27M15

+1.8V_RUN

Scott_0703:Delete Spread Spectrum XTAL circuit as placement required of thermal issue.

5

4

RAM_

RAM_

TYPE_CFG0

TYPE_CFG1

1
0
110

0

CFG1
GPIO12

00

0
00

PANEL_BKEN29

GFX_CORE_CNTRL252

GFX_CORE_CNTRL052

THERMAL_INT#20

GFX_CORE_CNTRL152

R412 100/FR412 100/F

R413 120/FR413 120/F

L20

L20

BLM15BD121SN1D

BLM15BD121SN1D

120ohm, 300mA

4

0
1

01
1

CFG0
GPIO11

1
001

BB_ENA18

+1.8V_RUN

R419

R419
499/F

499/F

R417

R417
249/F

249/F

T110 PADT110 PAD

12

VGA_THERMDP20
VGA_THERMDN20

+TSVDD

(1.8V @ 20mA TSVDD)

C115

C115
10uF

10uF

RAM_TYPE_CFG0
RAM_TYPE_CFG1
RAM_TYPE_CFG2
RAM_TYPE_CFG3

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6

GPIO8
GFX_CORE_CNTRL2
GPIO10
RAM_CFG0
RAM_CFG1
RAM_CFG2
GPIO14_HPD2

CLK_VGA_27M_SS_R

T70

T70

TEMP_FAIL

T62 PADT62 PAD
T59 PADT59 PAD
T61 PADT61 PAD
T63 PADT63 PAD
T73 PADT73 PAD
T72 PADT72 PAD
T71 PADT71 PAD
T65 PADT65 PAD
T69 PADT69 PAD
T64 PADT64 PAD
T60 PADT60 PAD
T66 PADT66 PAD
T68 PADT68 PAD
T67 PADT67 PAD

PLACE
VREFG
DIVIDER
AND CAP
CLOSE TO
ASIC

C530

C530
100nF

100nF

+DPLL_PVDD

+DPLL_VDDC

C114

C114
1uF

1uF

PAD

PAD

C90

C90
100nF

100nF

HPD1

XTAOUT

U29B

U29B

AR8

DVPCNTL_MVP_0

AU8

DVPCNTL_MVP_1

AP8

DVPCNTL_0

AW8

DVPCNTL_1

AR3

DVPCNTL_2

AR1

DVPCLK

AU1

DVPDATA_0

AU3

DVPDATA_1

AW3

DVPDATA_2

AP6

DVPDATA_3

AW5

DVPDATA_4

AU5

DVPDATA_5

AR6

DVPDATA_6

AW6

DVPDATA_7

AU6

DVPDATA_8

AT7

DVPDATA_9

AV7

DVPDATA_10

AN7

DVPDATA_11

AV9

DVPDATA_12

AT9

DVPDATA_13

AR10

DVPDATA_14

AW10

DVPDATA_15

AU10

DVPDATA_16

AP10

DVPDATA_17

AV11

DVPDATA_18

AT11

DVPDATA_19

AR12

DVPDATA_20

AW12

DVPDATA_21

AU12

DVPDATA_22

AP12

DVPDATA_23

AK26

SCL

AJ26

SDA

GENERAL PURPOSE I/O

GENERAL PURPOSE I/O

AH20

GPIO_0

AH18

GPIO_1

AN16

GPIO_2

AH23

GPIO_3_SMBDATA

AJ23

GPIO_4_SMBCLK

AH17

GPIO_5_AC_BATT

AJ17

GPIO_6

AK17

GPIO_7_BLON

AJ13

GPIO_8_ROMSO

AH15

GPIO_9_ROMSI

AJ16

GPIO_10_ROMSCK

AK16

GPIO_11

AL16

GPIO_12

AM16

GPIO_13

AM14

GPIO_14_HPD2

AM13

GPIO_15_PWRCNTL_0

AK14

GPIO_16_SSIN

AG30

GPIO_17_THERMAL_INT

AN14

GPIO_18_HPD3

AM17

GPIO_19_CTF

AL13

GPIO_20_PWRCNTL_1

AJ14

GPIO_21_BB_EN

AK13

GPIO_22_ROMCSB

AN13

GPIO_23_CLKREQB

AM23

JTAG_TRSTB

AN23

JTAG_TDI

AK23

JTAG_TCK

AL24

JTAG_TMS

AM24

JTAG_TDO

AJ19

GENERICA

AK19

GENERICB

AJ20

GENERICC

AK20

GENERICD

AJ24

GENERICE_HPD4

AH26

GENERICF

AH24

GENERICG

AK24

HPD1

AH13

VREFG

AM32

DPLL_PVDD

AN32

DPLL_PVSS

AN31

DPLL_VDDC

AV33

XTALIN

AU34

XTALOUT

AF29

DPLUS

AG29

DMINUS

AK32

TS_FDO

AJ32

TSVDD

AJ33

TSVSS

216-0729051(M96-M2 XT)

216-0729051(M96-M2 XT)

MUTI GFX

MUTI GFX

I2C

I2C

PLL/CLOCK

PLL/CLOCK

THERMAL

THERMAL

3

TXCAP_DPA3P
TXCAM_DPA3N

TX0P_DPA2P
TX0M_DPA2N

DPA

DPA

TX1P_DPA1P
TX1M_DPA1N

TX2P_DPA0P
TX2M_DPA0N

TXCBP_DPB3P
TXCBM_DPB3N

TX3P_DPB2P
TX3M_DPB2N

DPB

DPB

TX4P_DPB1P
TX4M_DPB1N

TX5P_DPB0P
TX5M_DPB0N

TXCCP_DPC3P

TXCCM_DPC3N

TX0P_DPC2P
TX0M_DPC2N

DPC

DPC

TX1P_DPC1P
TX1M_DPC1N

TX2P_DPC0P
TX2M_DPC0N

TXCDP_DPD3P

TXCDM_DPD3N

TX3P_DPD2P
TX3M_DPD2N

DPD

DPD

TX4P_DPD1P
TX4M_DPD1N

TX5P_DPD0P
TX5M_DPD0N

DAC1

DAC1

DAC2

DAC2

DDC/AUX

DDC/AUX

DDC1CLK

DDC1DATA

DDC2CLK

DDC2DATA

DDCCLK_AUX3P

DDCDATA_AUX3N

DDCCLK_AUX4P

DDCDATA_AUX4N

DDCCLK_AUX5P

DDCDATA_AUX5N

DDC6CLK

DDC6DATA

NC_DDCCLK_AUX7P

NC_DDCDATA_AUX7N

3

HSYNC

VSYNC

RSET
AVDD

AVSSQ

VDD1DI
VSS1DI

COMP

H2SYNC
V2SYNC

VDD2DI
VSS2DI

A2VDD

A2VDDQ

A2VSSQ

R2SET

AUX1P
AUX1N

AUX2P
AUX2N

AU24
AV23

AT25
AR24

AU26
AV25

AT27
AR26

AR30
AT29

AV31
AU30

AR32
AT31

AT33
AU32

AU14
AV13

AT15
AR14

AU16
AV15

AT17
AR16

!!! NC when M92-M2

AU20
AT19

AT21
AR20

AU22
AV21

AT23
AR22

AD39

R

AD37

RB

AE36

G

AD35

GB

AF37

B

AE38

BB

AC36
AC38

RSET

R97 499/FR97 499/F

AB34
AD34

AE34
AC33

AC34

AC30

R2

AC31

R2B

AD30

G2

AD31

G2B

AF30

B2

AF31

B2B

AC32

C

AD32

Y

AF32

AD29

VGAVSYNC2

AC29

AG31
AG32

AG33
AD33
AF33

R2SET

R94 715/FR94 715/F

AA29

AM26
AN26

AM27
AL27

DDC2CLK

AM19

DDC2DATA

AL19
AN20

AM20
AL30

AM30

!!! NC when M92-M2

AL29
AM29

ATI_LCD_DDCCLK

AN21

ATI_LCD_DDCDAT

AM21
AJ30

AJ31
AK30

AK29

DDC6CLK/DDC6DATA support
internal HDCP(High-bandwidth
Digital Content Protection) function.

ATI_HDMI_CLK+ 23
ATI_HDMI_CLK- 23

ATI_HDMI_TX0+ 23
ATI_HDMI_TX0- 23

ATI_HDMI_TX1+ 23
ATI_HDMI_TX1- 23

ATI_HDMI_TX2+ 23
ATI_HDMI_TX2- 23

DP_LANE3_P 23
DP_LANE3_N 23

DP_LANE2_P 23
DP_LANE2_N 23

DP_LANE1_P 23
DP_LANE1_N 23

DP_LANE0_P 23
DP_LANE0_N 23

12

+AVDD

+VDD1DI

+VDD1DI

*100nF_NCC89 *100nF_NCC89

+3.3V_DELAY

+A2VDDQ

12

R67 0R67 0

1 2
1 2

R74 0R74 0

VGA_RED

VGA_GRN

VGA_BLU

VGAHSYNC
VGAVSYNC

+1.8V_RUN

+1.8V_RUN

+1.8V_RUN

ATI_HDMI_SCL 23
ATI_HDMI_SDA 23

Reserve 0 ohm for
Dual mode DDC/AUX

AUX_SINK_P 23
AUX_SINK_N 23

ATI_LCD_DDCCLK 24
ATI_LCD_DDCDAT 24

G_CLK_DDC 25
G_DAT_DDC 25

2

VGA_RED 25

VGA_GRN 25

VGA_BLU 25

VGAHSYNC 25
VGAVSYNC 25

L21

L21

BLM15BD121SN1D

BLM15BD121SN1D

120ohm, 300mA

L22

L22

BLM15BD121SN1D

BLM15BD121SN1D

120ohm, 300mA

L51

L51

BLM15BD121SN1D

BLM15BD121SN1D

120ohm, 300mA

HDMI

DP

LVDS

CRT

2

CONFIGURATION STRAPS
STRAPS PIN
TX_PWRS_ENB

TX_DEEMPH_EN

BIF_GEN2_EN_A

(M96-M2)
VGA_DIS

BIOS_ROM_EN

AUD[1]
AUD[0]

GPIO0

GPIO1

GPIO2

GPIO5GPIO_5_AC_BATT

GPIO9

GPIO22

VGAHSYNC
VGAVSYNC

VIP_DEVICE_STRAP_EN1BIOS_ROM_EN

VGA_BLU
VGA_GRN
VGA_RED

R441

R441

R443

R443

R445

R445

150/F

150/F

150/F

150/F

Layout Note:
Place 150 ohm
termination resistors
close to ATI CHIP.

C130

C130

C131

C131

1uF

1uF

100nF

100nF

C146

C146

C147

C147

1uF

1uF

100nF

100nF

C540

C540

C106

C106

1uF

1uF

100nF

100nF

R78 2.2KR78 2.2K

12

R70 2.2KR70 2.2K

12

C129

C129
10uF

10uF

C145

C145
10uF

10uF

ATI_LCD_DDCDAT
ATI_LCD_DDCCLK

150/F

150/F

1

DESCRIPTION
PCIE FULL TX OUTPUT SWING

0 = 50% Tx output swing
1 = Full Tx output swing
PCIE TRANSMITTER DE-EMPHASIS ENABLED
0 = Disable ; 1 = Enable

0 = Advertises the PCIe device as

2.5 GT/s capable at power-on.
1 = Advertises the PCIe device as

5.0 GT/s capable at power-on.
1 = AC (Performance mode)

0 = Battery saving mode
0: VGA Controller capacity enabled

1: The device will not be recognized
as the system’s VGA controller
Enable external BIOS ROM device
0 = Disable ; 1 = Enable

AUD[1:0]:
00 - No audio function;
01 - Audio for DisplayPort only;
10 - Audio for DisplayPort and HDMI if dongle is
detected;
11 - Audio for both DisplayPort and HDMI.

VIP Device Strap Enable
0 = Disable ; 1 = Enable

(1.8V @ 70mA AVDD)

+AVDD

( 1.8V @ 45mA VDD1DI)

+VDD1DI

SET

1

0

1

0

0

11

0

( 1.8V @ 40mA VDD2DI)

(1.8V @ 20mA A2VDDQ)

+A2VDDQ

+3.3V_DELAY

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

COMPUTER

M96XT_IO & STRAP

M96XT_IO & STRAP

M96XT_IO & STRAP

RM5 3A

RM5 3A

RM5 3A

1

of

of

of

17 61Thursday, August 20, 2009

17 61Thursday, August 20, 2009

17 61Thursday, August 20, 2009

5

+1.5V_GDDR

For DDR3, VDDR1 = 1.5V
(1.5V @ 2.9A VDDR1+VDDRHA+VDDRHB)

C580

C580

C576

C576

1uF

1uF

1uF

1uF

C567

C567

C575

D D

BLM15BD121SN1D

BLM15BD121SN1D

120ohm, 300mA

C C

DVP isn't used.

BLM15BD121SN1D

BLM15BD121SN1D

120ohm, 300mA

BLM15BD121SN1D

BLM15BD121SN1D

120ohm, 300mA

B B

A A

(0.95-1.2V @ 136mA SPV10)

+1.1V_GFX_PCIE

+VCC_GFX_CORE

!!!
For M96 SPV10 = +VCC_GFX_CORE
For Park, Madison SPV10 = +1.1V_GFX_PCIE = 1.0V

+1.8V_RUN

*BLM15BD121SN1D_NC

*BLM15BD121SN1D_NC

120ohm, 300mA

*BLM15BD121SN1D_NC

*BLM15BD121SN1D_NC

120ohm, 300mA

*BLM15BD121SN1D_NC

*BLM15BD121SN1D_NC

120ohm, 300mA

BLM15BD121SN1D_

BLM15BD121SN1D_

120ohm, 300mA

L26

L26

L13

L13

+MPV18

+SPV18

L12

L12

L11

L11

!!! For Park, Madison

C575
1uF

1uF

C93

C93
1uF

1uF

C150

C150
1uF

1uF

C234

C234
10uF

10uF

1U = 20 pcs
10U = 5pcs

+VDD_CT+1.8V_RUN

L53

L53

L18

L18

+VDDR4+1.8V_RUN

+PCIE_PVDD+1.8V_RUN

L56

L56

+SPV10

(1.8V @ 136mA VDD_CT)

C544

C544
10uF

10uF

C107

C107
1uF

1uF

(1.8V @ 68mA PCIE_PVDD)

C556

C556
10uF

10uF

C60

C60
10uF

10uF

(1.8V @ 40mA MPV18)

C228

C228

C233

C233

*1uF_NC

*1uF_NC

*10uF_NC

*10uF_NC

(1.8V @ 75mA SPV18)

C68

C68

C69

C69

*10uF_NC

*10uF_NC

*1uF_NC

*1uF_NC

5

1uF

1uF

C200

C200
1uF

1uF

C111

C111
1uF

1uF

C232

C232
10uF

10uF

C543

C543
1uF

1uF

+3.3V_DELAY

(3.3V @ 60mA VDDR3)

C91

C91
10uF

10uF

+1.5V_GDDR +VDDRHA

C113

C113
100nF

100nF

C552

C552
1uF

1uF

C67

C67
1uF

1uF

C229

C229
*1uF_NC

*1uF_NC

C71

C71
*100nF_NC

*100nF_NC

C238

C238
1uF

1uF

C587

C587
1uF

1uF

C104

C104
1uF

1uF

C210

C210
1uF

1uF

C577

C577
10uF

10uF

C109

C109
1uF

1uF

C98

C98
1uF

1uF

C553

C553
100nF

100nF

C70

C70
100nF

100nF

C213

C213
*100nF_NC

*100nF_NC

C578

C578
1uF

1uF

C581

C581
1uF

1uF

C186

C186
1uF

1uF

C568

C568
1uF

1uF

C583

C583
10uF

10uF

C108

C108
100nF

100nF

C110

C110
1uF

1uF

L57

L57

BLM15BD121SN1D

BLM15BD121SN1D

120ohm, 300mA

!!! M96 Only

L23

L23

BLM15BD121SN1D

BLM15BD121SN1D

!!! M96 Only

C203

C203
*100nF_NC

*100nF_NC

+VDDRHB

C566

C566
1uF

1uF

C569

C569
1uF

1uF

C173

C173
1uF

1uF

C88

C88
1uF

1uF

C555

C555
10uF

10uF

C94

C94
1uF

1uF

+VDDR4

C99

C99
1uF

1uF

C224

C224
1uF

1uF

C163

C163
1uF

1uF

+MPV18

+SPV18

C10

C10
1U

1U

603

603
10

10

BB_ENA17

U29E

U29E

MEM I/O

MEM I/O

AC7

VDDR1#1

AD11

VDDR1#2

AF7

VDDR1#3

AG10

VDDR1#4

AJ7

VDDR1#5

AK8

VDDR1#6

AL9

VDDR1#7

G11

VDDR1#8

G14

VDDR1#9

G17

VDDR1#10

G20

VDDR1#11

G23

VDDR1#12

G26

VDDR1#13

G29

VDDR1#14

H10

VDDR1#15

J7

VDDR1#16

J9

VDDR1#17

K11

VDDR1#18

K13

VDDR1#19

K8

VDDR1#20

L12

VDDR1#21

L16

VDDR1#22

L21

VDDR1#23

L23

VDDR1#24

L26

VDDR1#25

L7

VDDR1#26

M11

VDDR1#27

N11

VDDR1#28

P7

VDDR1#29

R11

VDDR1#30

U11

VDDR1#31

U7

VDDR1#32

Y11

VDDR1#33

Y7

VDDR1#34

LEVEL

LEVEL
TRANSLATION

TRANSLATION

AF26

VDD_CT#1

AF27

VDD_CT#2

AG26

VDD_CT#3

AG27

VDD_CT#4

I/O

I/O

AF23

VDDR3#1

AF24

VDDR3#2

AG23

VDDR3#3

AG24

VDDR3#4

AF13

VDDR4#4

AF15

VDDR4#5

AG13

VDDR4#7

AG15

VDDR4#8

AD12

VDDR4#1

AF11

VDDR4#2

AF12

VDDR4#3

AG11

VDDR4#6

M20

NC_VDDRHA

M21

NC_VSSRHA

V12

NC_VDDRHB

U12

NC_VSSRHB

PLL

PLL

AB37

PCIE_PVDD

H7

MPV18#1

H8

MPV18#2

AM10

SPV18

AN9

SPV10

AN10

SPVSS

VOLTAGE

VOLTAGE
SENESE

SENESE

AF28

FB_VDDC

AG28

FB_VDDCI

AH29

FB_GND

216-0729051(M96-M2 XT)

216-0729051(M96-M2 XT)

+BBP

3

12

2

R35

R35
10K

10K

4

PCIE

PCIE

PCIE_VDDR#1
PCIE_VDDR#2
PCIE_VDDR#3
PCIE_VDDR#4
PCIE_VDDR#5
PCIE_VDDR#6
PCIE_VDDR#7
PCIE_VDDR#8

PCIE_VDDC#1
PCIE_VDDC#2
PCIE_VDDC#3
PCIE_VDDC#4
PCIE_VDDC#5
PCIE_VDDC#6
PCIE_VDDC#7
PCIE_VDDC#8

PCIE_VDDC#9
PCIE_VDDC#10
PCIE_VDDC#11
PCIE_VDDC#12

VDDC#1

CORE

CORE

VDDC#2
VDDC#3
VDDC#4
VDDC#5
VDDC#6
VDDC#7
VDDC#8

VDDC#9
VDDC#10
VDDC#11
VDDC#12
VDDC#13
VDDC#14
VDDC#15

POWER

POWER

VDDC#16
VDDC#17
VDDC#18
VDDC#19
VDDC#20
VDDC#21
VDDC#22
VDDC#23
VDDC#24
VDDC#25
VDDC#26
VDDC#27
VDDC#28
VDDC#29
VDDC#30
VDDC#31
VDDC#32
VDDC#33
VDDC#34
VDDC#35
VDDC#36
VDDC#37
VDDC#38
VDDC#39
VDDC#40
VDDC#41
VDDC#42
VDDC#43
VDDC#44
VDDC#45
VDDC#46
VDDC#47
VDDC#48
VDDC#49
VDDC#50
VDDC#51
VDDC#52
VDDC#53
VDDC#54
VDDC#55
VDDC#56
VDDC#57
VDDC#58

VDDCI#1
VDDCI#2
VDDCI#3
VDDCI#4
VDDCI#5
VDDCI#6
VDDCI#7
VDDCI#8
VDDCI#9

VDDCI#10
VDDCI#11
VDDCI#12
VDDCI#13
VDDCI#14
VDDCI#15

ISOLATED

ISOLATED

VDDCI#16

CORE I/O

CORE I/O

VDDCI#17
VDDCI#18
VDDCI#19
VDDCI#20
VDDCI#21
VDDCI#22

R37 *0_0603_NCR37 *0_0603_NC

1 2

1

+1.8V_RUN

Q11

Q11

2

SI2301BDS-T1-E3

SI2301BDS-T1-E3

31

Q14

Q14
2N7002W-7-F

2N7002W-7-F

!!!
M96 support Back Bias
Park, Madison : pop 0 ohm, depop other parts
M96 : pop other parts, depop 0 ohm

4

3 1

5/03: Added 4700pF for time tuning purpose

AA31
AA32
AA33
AA34
V28
W29
W30
Y31

G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28

AA15
AA17
AA20
AA22
AA24
AA27
AB16
AB18
AB21
AB23
AB26
AB28
AC17
AC20
AC22
AC24
AC27
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18
AG21
AH22
AH27
AH28
M26
N24
N27
R18
R21
R23
R26
T17
T20
T22
T24
T27
U16
U18
U21
U23
U26
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28

AA13
AB13
AC12
AC15
AD13
AD16
M15
M16
M18
M23
N13
N15
N17
N20
N22
R12
R13
R16
T12
T15
V15
Y13

+VDDCI

+VCC_GFX_CORE

Q15

Q15
2N7002W-7-F

2N7002W-7-F

2

R36 100KR36 100K

C856

C856
*4700P_NC

*4700P_NC

25

25

3

C545

C545
10uF

10uF

+PCIE_VDDR

(1.8V @ 210mA PCIE_VDDR)

C118

C118

C119

C119

1uF

1uF

100nF

100nF

C144

C144

C138

C138

1uF

1uF

1uF

1uF

(1.1V @ 1.4A PCIE_VDDC)

C167

C191

C191

C175

C175

1uF

1uF

1uF

1uF

C167

C182

C182
1uF

1uF

1uF

1uF

C187

C187

C198

C198

1uF

1uF

1uF

1uF

(1.2V @ 29.5A VCC_GFX_CORE)

C92

C92
1uF

1uF

C128

C128
1uF

1uF

C154

C154
1uF

1uF

C172

C172
1uF

1uF

C192

C192
1uF

1uF

C105

C105
10uF

10uF

1U = 30 pcs
10U = 7 pcs
22U = 5pcs

C103

C103
1uF

1uF

C132

C132
1uF

1uF

C155

C155
1uF

1uF

C174

C174
1uF

1uF

C199

C199
1uF

1uF

C123

C123
10uF

10uF

VDDC/VDDCI decoupling Cap follow AMD "ref137-03"

C121

C121

C124

C120

C120
1uF

1uF

C136

C136
1uF

1uF

C156

C156
1uF

1uF

C177

C177
1uF

1uF

C140

C140
10uF

10uF

C124

1uF

1uF

1uF

1uF

C151

C151

C137

C137

1uF

1uF

1uF

1uF

C159

C159

C158

C158

1uF

1uF

1uF

1uF

C178

C178

C181

C181

1uF

1uF

1uF

1uF

C142

C142

C141

C141

10uF

10uF

10uF

10uF

5/18: Adjusted cap values and quantities!

Scott_0701: Change 5pcs*22U to 5pcs*47U as Loki's suggestion

+BBP

C112

C112
47U

47U

+BBP

(For M96, 1.2V @ 375mA VDDCI)
VDDCI UNDER REVIEW FOR M97

12

+5V_RUN

C193

C193
1uF

1uF

C160

C160
47U

47U

+BBP

C161

C161
47U

47U

C184

C184
1uF

1uF

1U = 3 pcs
10U = 1 pcs

C148

C148
1uF

1uF

C185

C185
1uF

1uF

C139

C139
1uF

1uF

3

+VCC_GFX_CORE

C162

C162

C201

C201

47U

47U

47U

47U

+VDDCI

L25

L25

BLM18PG121SN1D

BLM18PG121SN1D

C180

C180
10uF

10uF

RUN_ON24,43,46,47,48,49,54

Scott_0819:Reserve +3.3V_delay circuit and add 0ohm resistor from +3.3V_Run to +3.3V_Delay

L54

L54

+PCIE_VDDC

C126

C126
1uF

1uF

C153

C153
1uF

1uF

C165

C165
1uF

1uF

C190

C190
1uF

1uF

C166

C166
10uF

10uF

+1.8V_RUN

C209

C209
10uF

10uF

+VCC_GFX_CORE

!!!
For M96/M92 PCIE_VDDC = 1.1V
For M97 PCIE_VDDC = 1.0V

L24

L24

BLM18PG121SN1D

BLM18PG121SN1D

120ohm, 2A

BLM18PG471SN1D

BLM18PG471SN1D

470ohm, 1A

C197

C197
1uF

1uF

C125

C125
1uF

1uF

C152

C152
1uF

1uF

C164

C164
1uF

1uF

C183

C183
1uF

1uF

C149

C149
10uF

10uF

5/13: Added 5 0805 caps!

+VCC_GFX_CORE

Scott_0821:Change R704 F/P to 0603 type.

R704 0_0603R704 0_0603

Q82

Q82

*SI2303BDS-T1-E3_NC

*SI2303BDS-T1-E3_NC

C863

C863
*0.1U_NC

*0.1U_NC

10

10

3

2

+3.3V_DELAY +3.3V_RUN

R706 *75K/F_NCR706 *75K/F_NC

OPTIONAL RC
NETWORK
TO FINE TUNE
POWER SEQUENCING

2

+1.1V_GFX_PCIE

1

12

2

31

*2N7002W-7-F_NC

*2N7002W-7-F_NC

R705

R705
*100K_NC

*100K_NC

Q83

Q83

C862

C862
*4700P_NC

*4700P_NC

25

25

5/03: Added 4700pF for time tuning purpose

2

U29F

U29F

AB39

PCIE_VSS#1

E39

PCIE_VSS#2

F34

PCIE_VSS#3

F39

PCIE_VSS#4

G33

PCIE_VSS#5

G34

PCIE_VSS#6

H31

PCIE_VSS#7

H34

PCIE_VSS#8

H39

PCIE_VSS#9

J31

PCIE_VSS#10

J34

PCIE_VSS#11

K31

PCIE_VSS#12

K34

PCIE_VSS#13

K39

PCIE_VSS#14

L31

PCIE_VSS#15

L34

PCIE_VSS#16

M34

PCIE_VSS#17

M39

PCIE_VSS#18

N31

PCIE_VSS#19

N34

PCIE_VSS#20

P31

PCIE_VSS#21

P34

PCIE_VSS#22

P39

PCIE_VSS#23

R34

PCIE_VSS#24

T31

PCIE_VSS#25

T34

PCIE_VSS#26

T39

PCIE_VSS#27

U31

PCIE_VSS#28

U34

PCIE_VSS#29

V34

PCIE_VSS#30

V39

PCIE_VSS#31

W31

PCIE_VSS#32

W34

PCIE_VSS#33

Y34

PCIE_VSS#34

Y39

PCIE_VSS#35

F15

GND#100

F17

GND#101

F19

GND#102

F21

GND#103

F23

GND#104

F25

GND#105

F27

GND#106

F29

GND#107

F31

GND#108

F33

GND#109

F7

GND#110

F9

GND#111

G2

GND#112

G6

GND#113

H9

GND#114

J2

GND#115

J27

GND#116

J6

GND#117

J8

GND#118

K14

GND#119

K7

GND#120

L11

GND#121

L17

GND#122

L2

GND#123

L22

GND#124

L24

GND#125

L6

GND#126

M17

GND#127

M22

GND#128

M24

GND#129

N16

GND#130

N18

GND#131

N2

GND#132

N21

GND#133

N23

GND#134

N26

GND#135

N6

GND#136

R15

GND#137

R17

GND#138

R2

GND#139

R20

GND#140

R22

GND#141

R24

GND#142

R27

GND#143

R6

GND#144

T11

GND#145

T13

GND#146

T16

GND#147

T18

GND#148

T21

GND#149

T23

GND#150

T26

GND#151

U15

GND#153

U17

GND#154

U2

GND#155

U20

GND#156

U22

GND#157

U24

GND#158

U27

GND#159

U6

GND#160

V11

GND#161

V16

GND#163

V18

GND#164

V21

GND#165

V23

GND#166

V26

GND#167

W2

GND#168

W6

GND#169

Y15

GND#170

Y17

GND#171

Y20

GND#172

Y22

GND#173

Y24

GND#174

Y27

GND#175

U13

GND#152

V13

GND#162

216-0729051(M96-M2 XT)

216-0729051(M96-M2 XT)

GND

GND

1

A3

GND#1

A37

GND#2

AA16

GND#3

AA18

GND#4

AA2

GND#5

AA21

GND#6

AA23

GND#7

AA26

GND#8

AA28

GND#9

AA6

GND#10

AB12

GND#11

AB15

GND#12

AB17

GND#13

AB20

GND#14

AB22

GND#15

AB24

GND#16

AB27

GND#17

AC11

GND#18

AC13

GND#19

AC16

GND#20

AC18

GND#21

AC2

GND#22

AC21

GND#23

AC23

GND#24

AC26

GND#25

AC28

GND#26

AC6

GND#27

AD15

GND#28

AD17

GND#29

AD20

GND#30

AD22

GND#31

AD24

GND#32

AD27

GND#33

AD9

GND#34

AE2

GND#35

AE6

GND#36

AF10

GND#37

AF16

GND#38

AF18

GND#39

AF21

GND#40

AG17

GND#41

AG2

GND#42

AG20

GND#43

AG22

GND#44

AG6

GND#45

AG9

GND#46

AH21

GND#47

AJ10

GND#48

AJ11

GND#49

AJ2

GND#50

AJ28

GND#51

AJ6

GND#52

AK11

GND#53

AK31

GND#54

AK7

GND#55

AL11

GND#56

AL14

GND#57

AL17

GND#58

AL2

GND#59

AL20

GND#60

AL21

GND#61

AL23

GND#62

AL26

GND#63

AL32

GND#64

AL6

GND#65

AL8

GND#66

AM11

GND#67

AM31

GND#68

AM9

GND#69

AN11

GND#70

AN2

GND#71

AN30

GND#72

AN6

GND#73

AN8

GND#74

AP11

GND#75

AP7

GND#76

AP9

GND#77

AR5

GND#78

AW34

GND#79

B11

GND#80

B13

GND#81

B15

GND#82

B17

GND#83

B19

GND#84

B21

GND#85

B23

GND#86

B25

GND#87

B27

GND#88

B29

GND#89

B31

GND#90

B33

GND#91

B7

GND#92

B9

GND#93

C1

GND#94

C39

GND#95

E35

GND#96

E5

GND#97

F11

GND#98

F13

GND#99

A39

VSS_MECH#1

AW1

VSS_MECH#2

AW39

VSS_MECH#3

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

R4220R422
0

!!!
Reserve for PX_EN
for Park and Madison

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

M96XT_POWER

M96XT_POWER

M96XT_POWER

RM5 3A

RM5 3A

RM5 3A

1

of

of

of

18 61Thursday, August 20, 2009

18 61Thursday, August 20, 2009

18 61Thursday, August 20, 2009