Quanta RM3 Paltrow MLK, Studio XPS 1640 Schematic

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RM3 (Paltrow MLK) Block Diagram
PWA : Y503R/Y504R(TV) PWB : Y505R
VER : 3A
SCH : Y506R
A A
POWER
AC/BATT CONNECTOR
PG 54 PG 47
CLOCK
SLG8SP513V
(QFN-64)
PG 17
BATT CHARGER
DDR3-SODIMM1
DDR3-SODIMM2
Subwoofer CONN
B B
MIC
PG 42
PG 42 & IB
Internal Speaker
PG 37 & DB
Subwoofer AMP MAXIM MAX9759
(16 Pin TQFN)
Amplifier
TI TPA6040A4
(32 Pin QFN)
HP2
HP1
PG 42 & IB
PG 42 & IB
Amplifier
TI TPA4411MRTJR
(20 Pin QFN)
PG 15
PG 16
PG 42
PG 41
PG 41
Camera + D-MIC
PG 37
TV CONN
C C
PG 35
USB CONN
PG 42 & IB
USB/eSATA Combo
PG 35 & eSATA board
SATA-ODD
SATA-HDD
1394 CONN
PG 29 & 1394 board
CardReader CONN
D D
RM3 MB PCB (rev D)RM3 MB PCB (rev D)
PG 36
PG 36
PC Card/1394
RICOH R5C833T
(128 Pin TQFP)
PG 29
1
14 x 14 mm
PG 28,29
2
FAN & THERMAL
EMC1423
(10P TSSOP)
PG 39
667 / 800 / 1066 MHz FSB
800 / 1066 MHZ DDR III
800 / 1066 MHZ DDR III
AUDIO
IDT 92HD73C
IHDA
(56 LQFP)
9 x 9 mm
PG 40
USB2.0 [11]
USB2.0 [9]
USB2.0 x 2 [0:1]
USB2.0 [8] SATA2 [A5] SATA2 [A1] SATA2 [A0] 33MHz PCI
Debug Port (Mini PCI)
PG 56
SPI ROM
2MB
(8 Pin SO8W)
3
PG 32
SPI
(478 Micro-FCPGA)
Keyboard
PG 37 PG 32
4
Penryn
Cantiga
(1299 uFCBGA)
PG 5,6,7,8,9,10
DMI interface
ICH9-M
(676 BGA)
PG 11,12,13,14
LPC
SIO
ITE ITE8512E
(128 Pin LQFP)
16 x 16 mm
CIR Touchpad
PG 3,4
PG 31
PS/2
PG 37 & DB
SYSTEM POWER
REGULATOR
+1.5V_RUN/+1.05V_VCCP
DDR3 VR
+1.5V_DDR/+0.75V_DDR_VTT +V_DDR_MCH_REF
Load Switch
+5V_SUS/+3.3V_SUS/+5V_RUN/+3.3V_RUN/+1.8V_RUN
PCIEx16
PCI EXPRESS GFX
AMD M96-M2 XT (128 bit)
M96-M2 : DDR3 x 8(1G)
PCIE [1] USB2.0 [5]
WWAN MINI-CARD
PCIE [2] USB2.0 [4]
WLAN Half MINI-CARD
PCIE [3] USB2.0 [6]
UWB/BT MINI-CARD
PCIE [4] USB2.0 [7]
PCIE [6]
Express Card
Broadcom BCM5784M
PAD & SCREW &
SMBus [2]
SPRING
PG 46
Media Button
PG 37 & DB
5
PG 48
PG 49
(962 FCBGA)
PG 18,19,20,21,22,26
(96P FBGA)
LAN
(68P QFN)
System Reset Circuit
LED
PG 38
RTC
PG 32
6
PG 23,24
PG 45
SYS VR
+5V_ALW2/+3.3V_ALW +5V_ALW/+15V_ALW
CPU VR
+VCC_CORE
HDMI
DP
LVDS
VGA
HDMI CONN.
DISPLAYPORT
Panel Connector
CRT CONN.
PG 50
PG 51
PG 55
VGA Core
+VCC_GFX_CORE +1.1V_GFX_PCIE
REGULATOR
+1.8V_SUS
GPU THERMAL
ANALOG DEVICES ADM1032
(8 MSOP) 3 x 3 mm
PG 34
PG 33
PG 34
Express Switch
PG 30
RICOH R5538D001
(20 QFN) 4 x 4 mm
Magnetic RJ45
PG 43
To IO Board
(USB*2/ MIC/ HP2/ HP1/ LED)
Title
Title
Title
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
RM3 3A
RM3 3A
RM3 3A
Date: Sheet
Date: Sheet
Date: Sheet
7
PG 44 PG 44
To Daughter Board
(Power Button/Speaker/ KB LED/Touch PAD/
PG 42
QUANTA
QUANTA
QUANTA COMPUTER
Media Button)
160Wednesday, May 06, 2009
160Wednesday, May 06, 2009
160Wednesday, May 06, 2009
PG 52
PG 53
8
PG 25
PG 25
PG 26
PG 27
PG 22
PG 30
PG 37
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Table of Contents Power States
PAGE DESCRIPTION
1
Block Diagram
2
Front Page
3-4
CPU (Penryn)
5-10
NB (Cantiga) SB (ICH9-M)
A A
B B
C C
11-14 15-16
DDR3 SO-DIMM(204P) Clock Generator
17
GPU (M96XT)
18-24
HDMI & DP
25
LCD connector
26
CRT
27
Card reader PCI interface
28 29
Card reader & 1394 CONN Express card
30
SIO (IT8512)
31
Flash/RTC/CIR
32 33
WLAN WWAN/WPAN
34 35
USB & eSATA & TV SATA HDD & ODD
36 37
KB/CCD/UI LED
38 39
FAN/Thermal
40-42
Audio/CONN/Subwoofer (92HD73C).
43-44
LAN/RJ45 (BCM5784M) System Reset Circuit
45
PAD & SCREW & SPRING
46
CHARGER (MAX8731A)
47
1.05VCCP & 1.5VRUN
48
1.5_DDR/0.75(TPS51116)
49 50
3.3V/5V/15V (MAX17020) CPU_POWER (ISL6262A) - 2 phase
51 52
VGA_M86 (MAX8632)
1.8V_SUS (TPS51117)
53
DCIN & Batt
54 55
Load Switch
56
Debug Port (Mini PCI)
57
SMBUS BLOCK
58
Power statu
59
Power Block Diagram
POWER PLANE
+PWR_SRC +RTC_CELL +3.3V_ALW +5V_ALW +15V_ALW +3.3V_LAN +5V_SUS +3.3V_SUS +1.8V_SUS +0.9V_DDR_VTT +5V_RUN +3.3V_RUN +1.8V_RUN +1.5V_RUN +1.25V_RUN +1.05V_VCCP +VCC_CORE +LCDVCC +5V_MOD +5V_HDD +5V_ALW2
10V~+19V
+3.0V~+3.3V
+3.3V +5V +15V +3.3V +5V +3.3V +1.8V +0.9V +5V +3.3V +1.8V +1.5V +1.25V +1.05V
+0.7V~+1.5V
+3.3V +5V +5V +5V
GND PLANE PAGE
8731AGND AGND_0.9V AGND_DC/DC AGND_DC2 AGND_DDR AGND_ISL6260
GND
46 49 52 48 49 51 ALL
4,26,32,34,48,49,50,51,52,55 11,14,31,32
3,13,26,31,32,34,36,37,38,44,46,49,52,53,54
35,36,46,48,49,52,53,54 26,36,37,52,53 42,43 14,38,50,51,53 3,11,12,13,14,20,30,37,38,43,48,49,50,51,53 6,8,9,15,48,49,50,53,55 16,49,53
14,20,25,27,36,37,38,39,40,41,53 6,8,9,11,12,13,14,15,17,19,20,22,25,26,27,28,
30,33,34,36,38,39,40,41,42,53,55 19,20,21,22,23,24,25,38,53
4,9,14,30,33,34,48,,53,55 6,9,14,49,53 3,4,5,6,8,9,11,14,37,48,55 4,51 26 36 36 37,38.52,53
DESCRIPTION
DESCRIPTION
MAIN POWER RTC 8051 POWER LCD/CHARGE POWER LARGE POWER LAN POWER SLP_S5# CTRLD POWER SLP_S5# CTRLD POWER SODIMM POWER SODIMM POWER SLP_S3# CTRLD POWER SLP_S3# CTRLD POWER SDVO POWER CALISTOGA/ICH8 POWER CALISTOGA/ICH8 POWER CPU/CALISTOGA/ICH8 POWER CPU CORE POWER LCD Power Module Power HDD Power LED power source
CONTROL SIGNAL
ALWON ALWON +5V_ALW AUX_ON SUS_ON
3.3V_SUS_ON DDR_ON
0.9V_DDR_VTT_ON RUN_ON
3.3V_RUN_ON RUN_ON
1.5V_RUN_ON
1.25V_RUN_ON
1.05V_RUN_ON IMVP_VR_ON
LCDVCC_TST_EN & ENVDD
MODC_EN# HDDC_EN# LDO output
ACTIVE INVOLTAGE PAGE
S0~S5 S0~S5 S0~S5 S0~S5 S0~S5
D D
QUANTA
QUANTA
QUANTA COMPUTER
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
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3
4
5
6
Date: Sheet
FRONTPAGE
FRONTPAGE
FRONTPAGE
RM3 3A
RM3 3A
RM3 3A
7
260Wednesday, May 06, 2009
260Wednesday, May 06, 2009
260Wednesday, May 06, 2009
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H_A#[3..16](5)
A A
H_ADSTB#0(5) H_REQ#[0..4](5)
H_A#[17..35](5)
B B
H_ADSTB#1(5)
H_A20M#(11)
H_FERR#(11)
H_IGNNE#(11) H_STPCLK#(11)
H_INTR(11) H_NMI(11) H_SMI#(11)
C C
H_A#[3..16]
H_REQ#[0..4]
H_A#[17..35]
T18T18 T25T25
T14T14 T15T15 T21T21 T105T105 T27T27 T16T16 T17T17 T13T13 T12T12 T11T11 T104T104 T10T10
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
U27A
U27A
J4
A[3]#
L5
A[4]#
L4
A[5]#
K5
A[6]#
M3
A[7]#
N2
A[8]#
J1
A[9]#
N3
A[10]#
P5
A[11]#
P2
A[12]#
L2
A[13]#
P4
A[14]#
P1
A[15]#
R1
A[16]#
M1
ADSTB[0]#
K3
REQ[0]#
H2
REQ[1]#
K2
REQ[2]#
J3
REQ[3]#
L1
REQ[4]#
Y2
A[17]#
U5
A[18]#
R3
A[19]#
W6
A[20]#
U4
A[21]#
Y5
A[22]#
U1
A[23]#
R4
A[24]#
T5
A[25]#
T3
A[26]#
W2
A[27]#
W5
A[28]#
Y4
A[29]#
U2
A[30]#
V4
A[31]#
W3
A[32]#
AA4
A[33]#
AB2
A[34]#
AA3
A[35]#
V1
ADSTB[1]#
A6
A20M#
A5
FERR#
C4
IGNNE#
D5
STPCLK#
C6
LINT0
B4
LINT1
A3
SMI#
F6
TDI_1/RSV
D3
TDO_2/RSV
N5
BMP_1#[0]/RSV
M4
BMP_1#[1]/RSV
B2
BMP_1#[2]/RSV
AE8
BMP_1#[3]/VSS
D8
DCLKPH_1/VSS
F8
ACLKPH_1/VSS
D22
GTLREF_2/RSV
T2
THRMDA_1/RSV
V3
THRMDC_1/RSV
AA8
HFPLL_1/VSS
AC8
SPARE_1[4]/VSS
AA7
BR1#/VCC
Penryn_uFCPGA479
Penryn_uFCPGA479
ADDR GROUP 0 ADDR GROUP 1
ADDR GROUP 0 ADDR GROUP 1
BPRI#
DEFER#
DRDY#
DBSY#
CONTROL
CONTROL
IERR#
LOCK#
RESET#
RS[0]# RS[1]# RS[2]#
TRDY#
HITM#
BPM[0]#
XDP/ITP SIGNALS
XDP/ITP SIGNALS
BPM[1]# BPM[2]# BPM[3]#
PRDY#
PREQ#
TRST#
THERMAL
THERMAL
PROCHOT#
THERMDA THERMDC
ICH
ICH
THERMTRIP#
H CLK
H CLK
BCLK[0] BCLK[1]
Quard Core Only
Quard Core Only
RSVD[06]
H1
ADS#
E2
BNR#
G5 H5
F21 E1
F1
BR0#
INIT#
HIT#
TCK
TDO TMS
DBR#
H_IERR#
D20 B3
H4 C1
F3 F4 G3 G2
G6 E4
AD4 AD3 AD1 AC4 AC2 AC1
ITP_TCK
AC5
ITP_TDI
AA6
TDI
ITP_TDO
AB3
ITP_TMS
AB5
ITP_TRST#
AB6
ITP_DBRESET#
C20
R58 56R58 56
H_PROCHOT#
D21
H_THERMDA
A24
H_THERMDC
B25
H_THERM
C7
R59 56R59 56
A22 A21
D2
H_THERMDA H_THERMDC
C79
C79
*2200P_NC 50
*2200P_NC 50
R57 56R57 56
H_ADS# (5) H_BNR# (5) H_BPRI# (5)
H_DEFER# (5) H_DRDY# (5) H_DBSY# (5)
H_BR0# (5)
+1.05V_VCCP
H_INIT# (11) H_LOCK# (5)
H_RS#0 (5) H_RS#1 (5) H_RS#2 (5) H_TRDY# (5)
H_HIT# (5) H_HITM# (5)
ITP_DBRESET# (13)
+1.05V_VCCP
T26PAD T26PAD
H_THERMDA (39)
H_THERMDC (39)
+1.05V_VCCP
CLK_CPU_BCLK (17) CLK_CPU_BCLK# (17)
T19T19
+1.05V_VCCP
R56
R56 *51_NC
*51_NC
Layout Note: Place voltage divider within
0.5" of GTLREF pin
+1.05V_VCCP
H_PROCHOT#
Layout Note: Place R116 close to CPU.
H_RESET# (5)
R432
R432 1K/F
1K/F
R431
R431 2K/F
2K/F
+1.05V_VCCP
2
Q6
Q6
*2N7002W-7-F_NC
*2N7002W-7-F_NC
CPU_MCH_BSEL0(6,17) CPU_MCH_BSEL1(6,17) CPU_MCH_BSEL2(6,17)
+3.3V_ALW
R60
R60 *2.2K_NC
*2.2K_NC
31
H_D#[0..15](5)
H_DSTBN#0(5) H_DSTBP#0(5) H_DINV#0(5)
H_D#[16..31](5)
H_DSTBN#1(5) H_DSTBP#1(5) H_DINV#1(5)
Voltage Level shift
H_D#[0..15] H_D#[32..47]
H_D#[16..31]
T24
T24
PAD
PAD
T20
T20
PAD
PAD
T23
T23
PAD
PAD
T106
T106
PAD
PAD
T9
PADT9PAD
T107
T107
PAD
PAD
T22
T22
PAD
PAD
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15
H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31
V_CPU_GTLREF CPU_TEST1 CPU_TEST2 CPU_TEST3 CPU_TEST4 CPU_TEST5 CPU_TEST6 CPU_TEST7
FSB 667 800
U27B
U27B
E22
D[0]#
F24
D[1]#
E26
D[2]#
G22
D[3]#
F23
D[4]#
G25
D[5]#
E25
D[6]#
E23
D[7]#
K24
D[8]#
G24
D[9]#
J24
D[10]#
J23
D[11]#
H22
D[12]#
F26
D[13]#
K22
D[14]#
H23
D[15]#
J26
DSTBN[0]#
H26
DSTBP[0]#
H25
DINV[0]#
N22
D[16]#
K25
D[17]#
P26
D[18]#
R23
D[19]#
L23
D[20]#
M24
D[21]#
L22
D[22]#
M23
D[23]#
P25
D[24]#
P23
D[25]#
P22
D[26]#
T24
D[27]#
R24
D[28]#
L25
D[29]#
T25
D[30]#
N25
D[31]#
L26
DSTBN[1]#
M26
DSTBP[1]#
N24
DINV[1]#
AD26
GTLREF
C23
TEST1
D25
TEST2
C24
TEST3
AF26
TEST4
AF1
TEST5
A26
TEST6
C3
TEST7
B22
BSEL[0]
B23
BSEL[1]
C21
BSEL[2]
Penryn_uFCPGA479
Penryn_uFCPGA479
BSEL2 BSEL1 BSEL0
BCLK
0
200
1166
DATA GRP 0
DATA GRP 0
DATA GRP 1
DATA GRP 1
MISC
MISC
D[32]# D[33]# D[34]# D[35]# D[36]# D[37]#
DATA GRP 2
DATA GRP 2
D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]#
D[47]# DSTBN[2]# DSTBP[2]#
DINV[2]#
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
DATA GRP 3
DATA GRP 3
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]# DSTBN[3]# DSTBP[3]#
DINV[3]# COMP[0]
COMP[1] COMP[2] COMP[3]
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
0011
Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22
AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20
R26 U26 AA1 Y1
E5 B5 D24 D6 D7 AE6
H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47
H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
COMP0 COMP1 COMP2 COMP3
1066 0 0 0266
H_D#[48..63]
H_D#[32..47] (5)
H_DSTBN#2 (5) H_DSTBP#2 (5) H_DINV#2 (5)
H_D#[48..63] (5)
H_DSTBN#3 (5) H_DSTBP#3 (5) H_DINV#3 (5)
H_DPRSTP# (6,11,51) H_DPSLP# (11) H_DPWR# (5) H_PWRGOOD (11) H_CPUSLP# (5) H_PSI# (51)
COMP0 COMP1 COMP2 COMP3
R53
R53
R54
R54
27.4/F
27.4/F
54.9/F
54.9/F
Comp0,2 connect with Zo=27.4ohm,Comp1,3 connect with Zo=55ohm, make those traces length shorter than 0.5".Trace should be at least 25 mils away from any other toggling signal.
R433
R433
54.9/F
54.9/F
R434
R434
27.4/F
27.4/F
+3.3V_RUN
12
R64
R64 10M
10M
+1.05V_VCCP
R33
R33
R32
R32
54.9/F
54.9/F
54.9/F
54.9/F
ITP_TDI ITP_TMS
D D
ITP_TDO ITP_DBRESET# ITP_TCK
ITP_TRST#
Layout note: Place R32, R33, R35, R38, R40, R48 close to CPU
R48 150R48 150 R40 54.9/FR40 54.9/F
R35 54.9/FR35 54.9/F
1
*54.9/F_NC
*54.9/F_NC
R38
R38
+3.3V_SUS
2
3
H_THERM
Q7
Q7
MMST3904-7-F
MMST3904-7-F
2
4
2
12
C83
C83
0.068U
0.068U
1 3
16
16
Scott_0403: Change C83 from 0.1U to
0.068U for timing tunninng.
31
H_THERMTRIP# (50)
Q8
Q8 2N7002W-7-F
2N7002W-7-F
(28)
5
QUANTA
QUANTA
QUANTA COMPUTER
COMPUTER
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
6
Date: Sheet
COMPUTER
Penryn (HOST BUS)
Penryn (HOST BUS)
Penryn (HOST BUS)
RM3 3A
RM3 3A
RM3 3A
7
360Wednesday, May 06, 2009
360Wednesday, May 06, 2009
360Wednesday, May 06, 2009
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+VCC_CORE +VCC_CORE
+VCC_CORE
A A
+VCC_CORE
All use 10U 4V(+-20%,X6S,0805)Pb-Free.
C74
C75
C75 10U
10U
4
4 805
805
C57
C57 10U
10U
4
4 805
805
C74 10U
10U
4
4 805
805
C56
C56 10U
10U
4
4 805
805
C73
C73 10U
10U
4
4 805
805
C70
C70 10U
10U
4
4 805
805
C72
C72 10U
10U
4
4 805
805
C76
C76 10U
10U
4
4 805
805
C71
C71 10U
10U
4
4 805
805
C67
C67 10U
10U
4
4 805
805
8 inside cavity, north side, secondary layer.
+VCC_CORE
C58
C59
C60
C60 10U
10U
4
4 805
805
B B
+VCC_CORE
C80
C80 10U
10U
4
4 805
805
C59 10U
10U
4
4 805
805
C81
C81 10U
10U
4
4 805
805
C58 10U
10U
4
4 805
805
C53
C53 10U
10U
4
4 805
805
C61
C61 10U
10U
4
4 805
805
C54
C54 10U
10U
4
4 805
805
C55
C55 10U
10U
4
4 805
805
C62
C62 10U
10U
4
4 805
805
8 inside cavity, south side, secondary layer.
+VCC_CORE
C564
C563
C563 10U
10U
4
4 805
805
C564 10U
10U
4
4 805
805
C565
C565 10U
10U
4
4 805
805
C566
C566 10U
10U
4
4 805
805
C567
C567 10U
10U
4
4 805
805
C568
C568 10U
10U
4
4 805
805
6 inside cavity, north side, primary layer.
+VCC_CORE
C C
C570
C570 10U
10U
4
4 805
805
C571
C571 10U
10U
4
4 805
805
C572
C572 10U
10U
4
4 805
805
C573
C573 10U
10U
4
4 805
805
C574
C574 10U
10U
4
4 805
805
C575
C575 10U
10U
4
4 805
805
6 inside cavity, south side, primary layer.
+PWR_SRC
+1.05V_VCCP
+
+
C558
C558 100U
C66
C68
C69
C69
0.1U
0.1U
10
10
Layout out:
D D
Place these inside socket cavity on North side secondary.
C64
C64
0.1U
0.1U
10
10
C68
0.1U
0.1U
10
10
C66
0.1U
0.1U
10
10
C63
C63
0.1U
0.1U
10
10
C65
C65
0.1U
0.1U
10
10
100U
25
25
Layout Note: Need to add 100uF cap on PWR_SRC for cap singing. Place on PWR_SRC near +VCC_CORE.
AA10 AA12 AA13 AA15 AA17 AA18 AA20
AC10 AB10 AB12 AB14 AB15 AB17 AB18
A10 A12 A13 A15 A17 A18 A20
B10 B12 B14 B15 B17 B18 B20
C10 C12 C13 C15 C17 C18
D10 D12 D14 D15 D17 D18
E10 E12 E13 E15 E17 E18 E20
F10 F12 F14 F15 F17 F18 F20
AA9
AB9
A7 A9
B7 B9
C9
D9
E7 E9
F7 F9
39
U27C
U27C
VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050]
VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064]
VCCSENSE VCC[065] VCC[066] VCC[067]
VSSSENSE
Penryn_uFCPGA479
Penryn_uFCPGA479
+PWR_SRC
+
+
C557
C557 100U
100U
25
25
VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100]
VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16]
VCCA[01] VCCA[02]
VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6]
AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20
G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21
B26 C26
AD6 AF5 AE5 AF4 AE3 AF3 AE2
AF7
AE7
.
.
+
+
C562
C562 *100U_NC
*100U_NC
25
25
T91T91
+VCCSENSE
+VSSSENSE
T28T28
T96T96
+1.05V_VCCP
+
+
C577
C577 220U
220U
4
4
VID0 (51) VID1 (51) VID2 (51) VID3 (51) VID4 (51) VID5 (51) VID6 (51)
+VCCSENSE (51)
+VSSSENSE (51)
+
+
C576
C576 *100U_NC
*100U_NC
25
25
+1.5V_RUN
C78
+VCC_CORE
R52
R52 100/F
100/F
R51
R51 100/F
100/F
C78 10U
10U
4
4
C77
C77
0.01U
0.01U
25
25
Layout Note: Place C194 near PIN B26.
+VCCSENSE +VSSSENSE
Route VCCSENSE and VSSSENSE traces at 27.4ohms and length matched to within 25 mil. Place PU and PD within 2 inch of CPU.
U27D
U27D
A4
VSS[001]
A8
VSS[002]
A11
VSS[003]
A14
VSS[004]
A16
VSS[005]
A19
VSS[006]
A23
VSS[007]
AF2
VSS[008]
B6
VSS[009]
B8
VSS[010]
B11
VSS[011]
B13
VSS[012]
B16
VSS[013]
B19
VSS[014]
B21
VSS[015]
B24
VSS[016]
C5
VSS[017]
C8
VSS[018]
C11
VSS[019]
C14
VSS[020]
C16
VSS[021]
C19
VSS[022]
C2
VSS[023]
C22
VSS[024]
C25
VSS[025]
D1
VSS[026]
D4
VSS[027]
D11
VSS[029]
D13
VSS[030]
D16
VSS[031]
D19
VSS[032]
D23
VSS[033]
D26
VSS[034]
E3
VSS[035]
E6
VSS[036]
E8
VSS[037]
E11
VSS[038]
E14
VSS[039]
E16
VSS[040]
E19
VSS[041]
E21
VSS[042]
E24
VSS[043]
F5
VSS[044]
F11
VSS[046]
F13
VSS[047]
F16
VSS[048]
F19
VSS[049]
F2
VSS[050]
F22
VSS[051]
F25
VSS[052]
G4
VSS[053]
G1
VSS[054]
G23
VSS[055]
G26
VSS[056]
H3
VSS[057]
H6
VSS[058]
H21
VSS[059]
H24
VSS[060]
J2
VSS[061]
J5
VSS[062]
J22
VSS[063]
J25
VSS[064]
K1
VSS[065]
K4
VSS[066]
K23
VSS[067]
K26
VSS[068]
L3
VSS[069]
L6
VSS[070]
L21
VSS[071]
L24
VSS[072]
M2
VSS[073]
M5
VSS[074]
M22
VSS[075]
M25
VSS[076]
N1
VSS[077]
N4
VSS[078]
N23
VSS[079]
N26
VSS[080] VSS[081]P3VSS[162]
Penryn_uFCPGA479
Penryn_uFCPGA479
VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110]
VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128]
VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146]
VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161]
VSS[163]
P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5
AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6
AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4
AE11 AE14 AE16 AE19
.
. AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25
QUANTA
QUANTA
QUANTA COMPUTER
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
1
2
3
4
5
6
Date: Sheet
Penryn (POWER/NC)
Penryn (POWER/NC)
Penryn (POWER/NC)
RM3 3A
RM3 3A
RM3 3A
7
460Wednesday, May 06, 2009
460Wednesday, May 06, 2009
460Wednesday, May 06, 2009
of
of
of
8
1
A A
B B
C C
+1.05V_VCCP
12
R442
R442 221/F
221/F
H_SWING
12
R441
R441 100/F
100/F
12
R71
R71
24.9/F
24.9/F
Layout Note: H_RCOMP trace should be 10-mil wide with 20-mil spacing.
1 2
H_RCOMP
2
Layout Note:
C590
C590
0.1uF place close
0.1U/10V
0.1U/10V
to pin C5
H_D#[0..63](3)
+1.05V_VCCP
R443
R443 1K/F
1K/F
1 2
12
R445
R445 2K/F
2K/F
3
H_RESET#(3)
H_CPUSLP#(3)
H_REF
12
C597
C597
0.1U/10V
0.1U/10V
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
H_SWING H_RCOMP
4
M11
N12
N10
AD14
AA8
AA13
AA9 AA11 AD11 AD10 AD13 AE12
AE9
AA2
AD8
AA3
AD3
AD7 AE14
AF3
AC1
AE3
AC3 AE11
AE8
AG2
AD6
C12
F2
G8
F8
E6 G2 H6 H2
F6 D4 H3 M9
J1
J2
J6
P2
L2 R2 N9
L6 M5
J3 N2 R1 N5 N6
P13
N8
L7 M3
Y3
Y6
Y10 Y12 Y14
Y7 W2
Y9
C5
E3
E11
A11 B11
U30A
U30A
H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63
H_SWING H_RCOMP
H_CPURST# H_CPUSLP#
H_AVREF H_DVREF
CANTIGA_verB3
CANTIGA_verB3
5
H_ADSTB#_0 H_ADSTB#_1
HOST
HOST
H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3
H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3
H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8
H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35
H_ADS#
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK# H_TRDY#
H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3
H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4
H_RS#_0 H_RS#_1 H_RS#_2
A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20
H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9
J8 L3 Y13 Y1
L10 M7 AA5 AE6
L9 M8 AA6 AE5
B15 K13 F13 B13 B14
B6 F12 C8
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35
6
H_A#[3..35] (3)
H_ADS# (3) H_ADSTB#0 (3) H_ADSTB#1 (3) H_BNR# (3) H_BPRI# (3) H_BR0# (3) H_DEFER# (3) H_DBSY# (3) CLK_MCH_BCLK (17) CLK_MCH_BCLK# (17) H_DPWR# (3) H_DRDY# (3) H_HIT# (3) H_HITM# (3) H_LOCK# (3) H_TRDY# (3)
H_DINV#0 (3) H_DINV#1 (3) H_DINV#2 (3) H_DINV#3 (3)
H_DSTBN#0 (3) H_DSTBN#1 (3) H_DSTBN#2 (3) H_DSTBN#3 (3)
H_DSTBP#0 (3) H_DSTBP#1 (3) H_DSTBP#2 (3) H_DSTBP#3 (3)
H_REQ#0 (3) H_REQ#1 (3) H_REQ#2 (3) H_REQ#3 (3) H_REQ#4 (3)
H_RS#0 (3) H_RS#1 (3) H_RS#2 (3)
7
8
Layout Note: Place the 0.1 uF
D D
1
2
decoupling capacitor within 100 mils from GMCH pins.
3
QUANTA
QUANTA
QUANTA COMPUTER
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
4
5
6
Date: Sheet
Cantiga_A (HOST)
Cantiga_A (HOST)
Cantiga_A (HOST)
RM3 3A
RM3 3A
RM3 3A
7
560Wednesday, May 06, 2009
560Wednesday, May 06, 2009
560Wednesday, May 06, 2009
of
of
of
8
1
+1.5V_DDR
R120
R120 1K/F
SM_RCOMP_VOH
C139
C139
0.01U
0.01U
25
25
A A
SM_RCOMP_VOL
C146
C146
0.01U
0.01U
25
25
+3.3V_RUN
R122 10KR122 10K R126 10KR126 10K
+1.05V_VCCP
R84 56R84 56
B B
+3.3V_RUN
C C
D D
1K/F
C136
C136
2.2U
2.2U
R115
R115
10
10
3.01K
3.01K
C147
C147
2.2U
2.2U
R118
R118
10
10
1K/F
1K/F
PM_EXTTS#0 PM_EXTTS#1
THERMTRIP_MCH#
Layout Note: Location of all MCH_CFG strap resistors needs to be close to minmize stub.
CPU_MCH_BSEL0(3,17) CPU_MCH_BSEL1(3,17) CPU_MCH_BSEL2(3,17)
1
T30
T30
PAD
PAD
T38
T38
PAD
PAD
R104 *2.21K/F_NCR104 *2.21K/F_NC
12
T36
T36
PAD
PAD
T39
T39
PAD
PAD
T33
T33
PAD
PAD
R95 *2.21K/F_NCR95 *2.21K/F_NC
12
T112
T112
PAD
PAD
T34
T34
PAD
PAD
T32
T32
PAD
PAD
T35
T35
PAD
PAD
T29
T29
PAD
PAD
T31
T31
PAD
PAD
R96 *2.21K/F_NCR96 *2.21K/F_NC
12
T37
T37
PAD
PAD
T40
T40
PAD
PAD
R116 *4.02K_NCR116 *4.02K_NC R108 *4.02K_NCR108 *4.02K_NC
PM_BMBUSY#(13)
H_DPRSTP#(3,11,51) PM_EXTTS#0(15) PM_EXTTS#1(16) ICH_PWRGD(13,45)
DPRSLPVR(13,51)
T128
T128
PAD
PAD
T131
T131
PAD
PAD
T129
T129
PAD
PAD
T127
T127
PAD
PAD
T126
T126
PAD
PAD
T125
T125
PAD
PAD
T132
T132
PAD
PAD
T124
T124
PAD
PAD
T48
T48
PAD
PAD
T122
T122
PAD
PAD
T121
T121
PAD
PAD
T123
T123
PAD
PAD
T111
T111
PAD
PAD
T110
T110
PAD
PAD
T108
T108
PAD
PAD
T109
T109
PAD
PAD
SB_NB_PCIE_RST#(12)
PLTRST#(12,18,30,31,33,34,43)
CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20
PM_EXTTS#0 PM_EXTTS#1
PLTRST#_R THERMTRIP_MCH#
R75 *0_NCR75 *0_NC
R73 0R73 0
AH10 AH12 AH13
AL34 AK34 AN35 AM35
AY21
BG23 BF23 BH18 BF18
AT40 AT11
BG48 BF48 BD48 BC48 BH47 BG47 BE47 BH46 BF46 BG45 BH44 BH43
M36
N36 R33 T33
AH9
K12
T24 B31
AJ6
M1
A47
T25 R25 P25 P20 P24 C25 N24
M24
E21 C23 C24 N21 P21 T21 R20
M20
L21 H21 P29 R28 T28
R29
B7 N33 P32
T20 R32
BH6 BH5 BG4 BH3
BF3
BH2 BG2 BE2 BG1
BF1
BD1 BC1
F1
2
U30B
U30B
RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14
RSVD15 RSVD16 RSVD17
RSVD20
RSVD21 RSVD22 RSVD23 RSVD24 RSVD25
CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20
PM_SYNC# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR
NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20 NC_21 NC_22 NC_23 NC_24 NC_25
CANTIGA_verB3
CANTIGA_verB3
R80 100R80 100
2
NC
NC
PLTRST#_R
3
AP24
SA_CK_0
AT21
SA_CK_1
AV24
SB_CK_0
AU20
SB_CK_1
AR24
SA_CK#_0
AR21
SA_CK#_1
AU24
SB_CK#_0
AV20
SB_CK#_1
BC28
SA_CKE_0
AY28
SA_CKE_1
AY36
SB_CKE_0
RSVD
RSVD
SM_RCOMP_VOH SM_RCOMP_VOL
DDR CONTROL/COMPENSATION
DDR CONTROL/COMPENSATION
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
CLK
CLK
CFG
CFG
DMI
DMI
PM
PM
GRAPHICS VID
GRAPHICS VID
MEHDA
MEHDA
DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
MISC
MISC
SB_CKE_1 SA_CS#_0
SA_CS#_1 SB_CS#_0 SB_CS#_1
SA_ODT_0 SA_ODT_1 SB_ODT_0 SB_ODT_1
SM_RCOMP
SM_RCOMP#
SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST# DPLL_REF_CLK
PEG_CLK
PEG_CLK#
DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3
DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3
DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3
DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3
GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4
GFX_VR_EN
CL_CLK
CL_DATA
CL_PWROK
CL_RST# CL_VREF
CLKREQ#
ICH_SYNC#
TSATN
HDA_BCLK HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC
BB36 BA17
AY16 AV16 AR13
BD17 AY17 BF15 AY13
BG22 BH21
BF28 BH28
AV42 AR36 BF17 BC36
B38 A38 E41 F41
F43 E43
AE41 AE37 AE47 AH39
AE40 AE38 AE48 AH40
AE35 AE43 AE46 AH42
AD35 AE44 AF46 AH43
B33 B32 G33 F33 E33
C34
AH37 AH36 AN36 AJ35 AH34
N28 M28 G36 E36 K36 H36
B12
B28 B30 B29 C29 A28
SMRCOMPP SMRCOMPN
SM_RCOMP_VOH SM_RCOMP_VOL
SM_PWROK
12
R88 499/FR88 499/F
T115 PADT115 PAD T113 PADT113 PAD T41 PADT41 PAD T117 PADT117 PAD T114 PADT114 PAD
T118 PADT118 PAD
CL_CLK0 (13) CL_DATA0 (13) ICH_CL_PWROK (13,31)
ICH_CL_RST0# (13)
MCH_CLVREF
CLK_3GPLLREQ# (17) MCH_ICH_SYNC# (13)
R449 56R449 56
3
M_CLK_DDR0 (15) M_CLK_DDR1 (15) M_CLK_DDR3 (16) M_CLK_DDR4 (16)
M_CLK_DDR#0 (15) M_CLK_DDR#1 (15) M_CLK_DDR#3 (16) M_CLK_DDR#4 (16)
DDR_CKE0_DIMMA (15) DDR_CKE1_DIMMA (15) DDR_CKE3_DIMMB (16) DDR_CKE4_DIMMB (16)
DDR_CS0_DIMMA# (15) DDR_CS1_DIMMA# (15) DDR_CS2_DIMMB# (16) DDR_CS3_DIMMB# (16)
M_ODT0 (15) M_ODT1 (15) M_ODT2 (16) M_ODT3 (16)
CLK_MCH_3GPLL (17) CLK_MCH_3GPLL# (17)
DMI_MRX_ITX_N0 (12) DMI_MRX_ITX_N1 (12) DMI_MRX_ITX_N2 (12) DMI_MRX_ITX_N3 (12)
DMI_MRX_ITX_P0 (12) DMI_MRX_ITX_P1 (12) DMI_MRX_ITX_P2 (12) DMI_MRX_ITX_P3 (12)
DMI_MTX_IRX_N0 (12) DMI_MTX_IRX_N1 (12) DMI_MTX_IRX_N2 (12) DMI_MTX_IRX_N3 (12)
DMI_MTX_IRX_P0 (12) DMI_MTX_IRX_P1 (12) DMI_MTX_IRX_P2 (12) DMI_MTX_IRX_P3 (12)
+V_DDR_MCH_REF
DDR3_DRAMRST# (15,16)
+1.05V_VCCP
4
SMRCOMPP SMRCOMPN
R311
R311
12.1K/F
12.1K/F
SM_PWROK
R131
R131 10K/F
10K/F
+1.05V_VCCP
Non-iAMT
MCH_CLVREF
12
C158
C158
0.1U
0.1U
CL_VREF~=0.35V
4
R124
R124 1K/F
1K/F
R128
R128 499/F
499/F
+1.5V_DDR
12
R93
R93
80.6/F
80.6/F
12
R94
R94
80.6/F
80.6/F
SM_PWROK_R
1.5V
4
U12
U12 74AHC1G08GW
74AHC1G08GW
+3.3V_ALW
3 5
2 1
5
1.5V_DDR_PWRGD (45,49)
5
CFG5
CFG9
CFG16
CFG19
CFG20
SDVO_CRTL_DATA
U30C
U30C
L32
L_BKLT_CTRL
G32
L_BKLT_EN
M32
L_CTRL_CLK
M33
L_CTRL_DATA
K33
L_DDC_CLK
J33
L_DDC_DATA
M29
L_VDD_EN
C44
LVDS_IBG
B43
LVDS_VBG
E37
LVDS_VREFH
E38
LVDS_VREFL
C41
LVDSA_CLK#
C40
LVDSA_CLK
B37
LVDSB_CLK#
A37
LVDSB_CLK
H47
LVDSA_DATA#_0
E46
LVDSA_DATA#_1
G40
LVDSA_DATA#_2
A40
LVDSA_DATA#_3
H48
LVDSA_DATA_0
D45
LVDSA_DATA_1
F40
LVDSA_DATA_2
B40
LVDSA_DATA_3
A41
LVDSB_DATA#_0
H38
LVDSB_DATA#_1
G37
LVDSB_DATA#_2
J37
LVDSB_DATA#_3
B42
LVDSB_DATA_0
G38
LVDSB_DATA_1
F37
LVDSB_DATA_2
K37
LVDSB_DATA_3
F25
TVA_DAC
H25
TVB_DAC
K25
TVC_DAC
H24
TV_RTN
C31
TV_DCONSEL_0
E32
TV_DCONSEL_1
E28
CRT_BLUE
G28
CRT_GREEN
J28
CRT_RED
G29
CRT_IRTN
H32
CRT_DDC_CLK
J32
CRT_DDC_DATA
J29
CRT_HSYNC
E29
CRT_TVO_IREF
L29
CRT_VSYNC
CANTIGA_verB3
CANTIGA_verB3
DMI X2 Select PCI Express
Graphic Lane FSB Dynamic
ODT DMI Lane
Reversal
SDVO/PCIE Concurrent Operation
SDVO Present.
6
PEG_COMPI
PEG_COMPO
PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6
LVDS
LVDS
TV
TV
Low=DMIx2 High=DMIx4(Default)
Low= Reveise Lane High=Normal operation
Low=Dynamic ODT Disable High=Dynamic ODT Enable(default).
Low=Normal(default). High=Lane Reversed
Low=Only SDVO or PCIEx1 is operational (defaults) High=SDVO and PCIEx1 are operating simultaneously via PEG port
Low=No SDVO Device Present (default) High=SDVO Device Present
6
PEG_RX#_7 PEG_RX#_8
PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15
PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8
PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15
PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9
PEG_TX#_10 PEG_TX#_11
PCI-EXPRESS GRAPHICS
PCI-EXPRESS GRAPHICS
PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
VGA
VGA
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15
+VCC3G_PCIE_R
T37 T36
PCIE_MRX_GTX_N0PCIE_MRX_GTX_N0
H44
PCIE_MRX_GTX_N1
J46
PCIE_MRX_GTX_N2PCIE_MRX_GTX_N2
L44
PCIE_MRX_GTX_N3PCIE_MRX_GTX_N3
L40
PCIE_MRX_GTX_N4PCIE_MRX_GTX_N4
N41
PCIE_MRX_GTX_N5PCIE_MRX_GTX_N5
P48
PCIE_MRX_GTX_N6PCIE_MRX_GTX_N6
N44
PCIE_MRX_GTX_N7PCIE_MRX_GTX_N7
T43
PCIE_MRX_GTX_N8PCIE_MRX_GTX_N8
U43
PCIE_MRX_GTX_N9PCIE_MRX_GTX_N9
Y43
PCIE_MRX_GTX_N10PCIE_MRX_GTX_N10
Y48
PCIE_MRX_GTX_N11PCIE_MRX_GTX_N11
Y36
PCIE_MRX_GTX_N12PCIE_MRX_GTX_N12
AA43
PCIE_MRX_GTX_N13PCIE_MRX_GTX_N13
AD37
PCIE_MRX_GTX_N14PCIE_MRX_GTX_N14
AC47
PCIE_MRX_GTX_N15PCIE_MRX_GTX_N15
AD39
PCIE_MRX_GTX_P0PCIE_MRX_GTX_P0
H43
PCIE_MRX_GTX_P1
J44
PCIE_MRX_GTX_P2PCIE_MRX_GTX_P2
L43
PCIE_MRX_GTX_P3PCIE_MRX_GTX_P3
L41
PCIE_MRX_GTX_P4PCIE_MRX_GTX_P4
N40
PCIE_MRX_GTX_P5PCIE_MRX_GTX_P5
P47
PCIE_MRX_GTX_P6PCIE_MRX_GTX_P6
N43
PCIE_MRX_GTX_P7PCIE_MRX_GTX_P7
T42
PCIE_MRX_GTX_P8PCIE_MRX_GTX_P8
U42
PCIE_MRX_GTX_P9PCIE_MRX_GTX_P9
Y42
PCIE_MRX_GTX_P10PCIE_MRX_GTX_P10
W47
PCIE_MRX_GTX_P11PCIE_MRX_GTX_P11
Y37
PCIE_MRX_GTX_P12PCIE_MRX_GTX_P12
AA42
PCIE_MRX_GTX_P13PCIE_MRX_GTX_P13
AD36
PCIE_MRX_GTX_P14PCIE_MRX_GTX_P14
AC48
PCIE_MRX_GTX_P15PCIE_MRX_GTX_P15
AD40
PCIE_MTX_GRX_C_N0PCIE_MTX_GRX_C_N0
J41
PCIE_MTX_GRX_C_N1PCIE_MTX_GRX_C_N1
M46
PCIE_MTX_GRX_C_N2PCIE_MTX_GRX_C_N2
M47
PCIE_MTX_GRX_C_N3PCIE_MTX_GRX_C_N3
M40
PCIE_MTX_GRX_C_N4PCIE_MTX_GRX_C_N4
M42
PCIE_MTX_GRX_C_N5PCIE_MTX_GRX_C_N5
R48
PCIE_MTX_GRX_C_N6PCIE_MTX_GRX_C_N6
N38
PCIE_MTX_GRX_C_N7PCIE_MTX_GRX_C_N7
T40
PCIE_MTX_GRX_C_N8PCIE_MTX_GRX_C_N8
U37
PCIE_MTX_GRX_C_N9PCIE_MTX_GRX_C_N9
U40
PCIE_MTX_GRX_C_N10PCIE_MTX_GRX_C_N10
Y40
PCIE_MTX_GRX_C_N11PCIE_MTX_GRX_C_N11
AA46
PCIE_MTX_GRX_C_N12PCIE_MTX_GRX_C_N12
AA37
PCIE_MTX_GRX_C_N13PCIE_MTX_GRX_C_N13
AA40
PCIE_MTX_GRX_C_N14PCIE_MTX_GRX_C_N14
AD43
PCIE_MTX_GRX_C_N15PCIE_MTX_GRX_C_N15
AC46
PCIE_MTX_GRX_C_P0PCIE_MTX_GRX_C_P0
J42
PCIE_MTX_GRX_C_P1PCIE_MTX_GRX_C_P1
L46
PCIE_MTX_GRX_C_P2PCIE_MTX_GRX_C_P2
M48
PCIE_MTX_GRX_C_P3PCIE_MTX_GRX_C_P3
M39
PCIE_MTX_GRX_C_P4PCIE_MTX_GRX_C_P4
M43
PCIE_MTX_GRX_C_P5PCIE_MTX_GRX_C_P5
R47
PCIE_MTX_GRX_C_P6PCIE_MTX_GRX_C_P6
N37
PCIE_MTX_GRX_C_P7PCIE_MTX_GRX_C_P7
T39
PCIE_MTX_GRX_C_P8PCIE_MTX_GRX_C_P8
U36
PCIE_MTX_GRX_C_P9PCIE_MTX_GRX_C_P9
U39
PCIE_MTX_GRX_C_P10PCIE_MTX_GRX_C_P10
Y39
PCIE_MTX_GRX_C_P11PCIE_MTX_GRX_C_P11
Y46
PCIE_MTX_GRX_C_P12PCIE_MTX_GRX_C_P12
AA36
PCIE_MTX_GRX_C_P13PCIE_MTX_GRX_C_P13
AA39
PCIE_MTX_GRX_C_P14PCIE_MTX_GRX_C_P14
AD42
PCIE_MTX_GRX_C_P15PCIE_MTX_GRX_C_P15
AD46
7
+VCC_PEG
R130 49.9/FR130 49.9/F
1 2
PCIE_MRX_GTX_N[0..15] (18)
PCIE_MRX_GTX_P[0..15] (18)
C213 0.1UC213 0.1U C631 0.1UC631 0.1U C627 0.1UC627 0.1U C190 0.1UC190 0.1U C630 0.1UC630 0.1U C626 0.1UC626 0.1U C208 0.1UC208 0.1U C211 0.1UC211 0.1U C181 0.1UC181 0.1U C206 0.1UC206 0.1U C204 0.1UC204 0.1U C216 0.1UC216 0.1U C202 0.1UC202 0.1U C201 0.1UC201 0.1U C247 0.1UC247 0.1U C215 0.1UC215 0.1U
C212 0.1UC212 0.1U C632 0.1UC632 0.1U C628 0.1UC628 0.1U C182 0.1UC182 0.1U C629 0.1UC629 0.1U C625 0.1UC625 0.1U C209 0.1UC209 0.1U C210 0.1UC210 0.1U C174 0.1UC174 0.1U C207 0.1UC207 0.1U C205 0.1UC205 0.1U C217 0.1UC217 0.1U C203 0.1UC203 0.1U C200 0.1UC200 0.1U C246 0.1UC246 0.1U C214 0.1UC214 0.1U
Title
Title
Title
Cantiga_B (VGA,DMI)
Cantiga_B (VGA,DMI)
Cantiga_B (VGA,DMI)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
RM3 3A
RM3 3A
RM3 3A
Date: Sheet
Date: Sheet
Date: Sheet
7
PCIE_MTX_GRX_N0 PCIE_MTX_GRX_N1 PCIE_MTX_GRX_N2 PCIE_MTX_GRX_N3 PCIE_MTX_GRX_N4 PCIE_MTX_GRX_N5 PCIE_MTX_GRX_N6 PCIE_MTX_GRX_N7 PCIE_MTX_GRX_N8 PCIE_MTX_GRX_N9 PCIE_MTX_GRX_N10 PCIE_MTX_GRX_N11 PCIE_MTX_GRX_N12 PCIE_MTX_GRX_N13 PCIE_MTX_GRX_N14 PCIE_MTX_GRX_N15
PCIE_MTX_GRX_P0 PCIE_MTX_GRX_P1 PCIE_MTX_GRX_P2 PCIE_MTX_GRX_P3 PCIE_MTX_GRX_P4 PCIE_MTX_GRX_P5 PCIE_MTX_GRX_P6 PCIE_MTX_GRX_P7 PCIE_MTX_GRX_P8 PCIE_MTX_GRX_P9 PCIE_MTX_GRX_P10 PCIE_MTX_GRX_P11 PCIE_MTX_GRX_P12 PCIE_MTX_GRX_P13 PCIE_MTX_GRX_P14 PCIE_MTX_GRX_P15
QUANTA
QUANTA
QUANTA COMPUTER
COMPUTER
COMPUTER
8
PCIE_MTX_GRX_N[0..15] (18) PCIE_MTX_GRX_P[0..15] (18)
of
of
of
660Wednesday, May 06, 2009
660Wednesday, May 06, 2009
660Wednesday, May 06, 2009
8
1
2
3
4
5
6
7
8
DDR_A_D[0..63](15)
A A
B B
C C
DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63
AJ38
AJ41 AN38 AM38
AJ36
AJ40
AM44 AM42
AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36
AW36
BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12
BB9 BA9
AU10
AV9
BA11
BD9 AY8 BA6 AV5 AV7
AN8 AU5 AU6
AN10
AM11
AM5
AN12
AM13
AJ11
AJ12
AT9
AT5
AJ9 AJ8
U30D
U30D
SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63
CANTIGA_verB3
CANTIGA_verB3
DDR_A_BS0
BD21
SA_BS_0 SA_BS_1 SA_BS_2
SA_RAS# SA_CAS#
SA_WE#
SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7
SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6
SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7
SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8
SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
SA_MA_14
BG18 AT25
BB20 BD20 AY20
AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5
AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8
BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25
DDR_A_BS1 DDR_A_BS2
DDR_A_RAS# DDR_A_CAS# DDR_A_WE#
DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7
DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14
DDR_A_BS0 (15) DDR_A_BS1 (15) DDR_A_BS2 (15)
DDR_A_RAS# (15) DDR_A_CAS# (15) DDR_A_WE# (15)
DDR_A_DM[0..7] (15)
DDR_A_DQS[0..7] (15)
DDR_A_DQS#[0..7] (15)
DDR_A_MA[0..14] (15)
DDR_B_D[0..63](16)
DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63
AK47 AH46 AP47 AP46
AJ46 AJ48
AM48
AP48 AU47 AU46 BA48 AY48 AT47 AR47 BA47 BC47 BC46 BC44 BG43 BF43 BE45 BC41 BF40 BF41 BG38 BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11
BG8 BH12 BF11
BG7
BC5
BC6
AY3
AY1
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1
AH1
AM2
AM3
AH3
BF8
BF6 BF5
AL1 AL2 AJ1
AJ3
U30E
U30E
SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63
CANTIGA_verB3
CANTIGA_verB3
DDR_B_BS0
BC16
SB_BS_0 SB_BS_1 SB_BS_2
SB_RAS# SB_CAS#
SB_WE#
SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7
SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6
SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7
SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8
SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
SB_MA_14
BB17 BB33
AU17 BG16 BF14
AM47 AY47 BD40 BF35 BG11 BA3 AP1 AK2
AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5
AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33
DDR_B_BS1 DDR_B_BS2
DDR_B_RAS# DDR_B_CAS# DDR_B_WE#
DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7
DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7
DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14
DDR_B_BS0 (16) DDR_B_BS1 (16) DDR_B_BS2 (16)
DDR_B_RAS# (16) DDR_B_CAS# (16) DDR_B_WE# (16)
DDR_B_DM[0..7] (16)
DDR_B_DQS[0..7] (16)
DDR_B_DQS#[0..7] (16)
DDR_B_MA[0..14] (16)
D D
QUANTA
QUANTA
QUANTA COMPUTER
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
1
2
3
4
5
6
Date: Sheet
Cantiga_C (DDR3)
Cantiga_C (DDR3)
Cantiga_C (DDR3)
RM3 3A
RM3 3A
RM3 3A
7
760Wednesday, May 06, 2009
760Wednesday, May 06, 2009
760Wednesday, May 06, 2009
of
of
of
8
5
U30G
AP33 AN33 BH32
BG32
BF32 BD32 BC32 BB32 BA32 AY32
AW32
AV32 AU32 AT32 AR32 AP32 AN32 BH31
BG31
BF31
BG30
BH29
BG29
BF29 BD29 BC29 BB29 BA29 AY29
AW29
AV29 AU29 AT29 AR29 AP29
BA36 BB24 BD16
BB21 AW16 AW13
AT13
AE25
AB25
AA25
AE24
AC24
AA24
AE23
AC23
AB23
AA23
AJ21
AG21
AE21
AC21
AA21
AH20
AF20
AE20
AC20
AB20
AA20
AM15
AL15
AE15
AJ15
AH15
AG15
AF15
AB15
AA15
AN14
AM14
AJ14
AH14
Y26
Y24
Y21
T17 T16
Y15 V15 U15
U14 T14
U30G
VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35
VCC_SM_36/NC VCC_SM_37/NC VCC_SM_38/NC VCC_SM_39/NC VCC_SM_40/NC VCC_SM_41/NC VCC_SM_42/NC
VCC_AXG_1 VCC_AXG_2 VCC_AXG_3 VCC_AXG_4 VCC_AXG_5 VCC_AXG_6 VCC_AXG_7 VCC_AXG_8 VCC_AXG_9 VCC_AXG_10 VCC_AXG_11 VCC_AXG_12 VCC_AXG_13 VCC_AXG_14 VCC_AXG_15 VCC_AXG_16 VCC_AXG_17 VCC_AXG_18 VCC_AXG_19 VCC_AXG_20 VCC_AXG_21 VCC_AXG_22 VCC_AXG_23 VCC_AXG_24 VCC_AXG_25 VCC_AXG_26 VCC_AXG_27 VCC_AXG_28 VCC_AXG_29 VCC_AXG_30 VCC_AXG_31 VCC_AXG_32 VCC_AXG_33 VCC_AXG_34 VCC_AXG_35 VCC_AXG_36 VCC_AXG_37 VCC_AXG_38 VCC_AXG_39 VCC_AXG_40 VCC_AXG_41 VCC_AXG_42
VCC_AXG_SENSE VSS_AXG_SENSE
CANTIGA_verB3
CANTIGA_verB3
VCC_AXG_NCTF_1 VCC_AXG_NCTF_2 VCC_AXG_NCTF_3 VCC_AXG_NCTF_4 VCC_AXG_NCTF_5 VCC_AXG_NCTF_6 VCC_AXG_NCTF_7 VCC_AXG_NCTF_8
VCC_AXG_NCTF_9 VCC_AXG_NCTF_10 VCC_AXG_NCTF_11 VCC_AXG_NCTF_12 VCC_AXG_NCTF_13 VCC_AXG_NCTF_14 VCC_AXG_NCTF_15 VCC_AXG_NCTF_16 VCC_AXG_NCTF_17 VCC_AXG_NCTF_18 VCC_AXG_NCTF_19 VCC_AXG_NCTF_20 VCC_AXG_NCTF_21
POWER
POWER
VCC_AXG_NCTF_22 VCC_AXG_NCTF_23 VCC_AXG_NCTF_24 VCC_AXG_NCTF_25 VCC_AXG_NCTF_26 VCC_AXG_NCTF_27 VCC_AXG_NCTF_28 VCC_AXG_NCTF_29 VCC_AXG_NCTF_30
VCC SMVCC GFX
VCC SMVCC GFX
VCC_AXG_NCTF_31 VCC_AXG_NCTF_32 VCC_AXG_NCTF_33 VCC_AXG_NCTF_34 VCC_AXG_NCTF_35 VCC_AXG_NCTF_36 VCC_AXG_NCTF_37 VCC_AXG_NCTF_38 VCC_AXG_NCTF_39 VCC_AXG_NCTF_40 VCC_AXG_NCTF_41 VCC_AXG_NCTF_42 VCC_AXG_NCTF_43 VCC_AXG_NCTF_44 VCC_AXG_NCTF_45 VCC_AXG_NCTF_46 VCC_AXG_NCTF_47 VCC_AXG_NCTF_48 VCC_AXG_NCTF_49 VCC_AXG_NCTF_50 VCC_AXG_NCTF_51 VCC_AXG_NCTF_52 VCC_AXG_NCTF_53 VCC_AXG_NCTF_54 VCC_AXG_NCTF_55
VCC GFX NCTF
VCC GFX NCTF
VCC_AXG_NCTF_56 VCC_AXG_NCTF_57 VCC_AXG_NCTF_58 VCC_AXG_NCTF_59 VCC_AXG_NCTF_60
Added for SI recommend.
D D
+1.5V_DDR
1 2
C151 0.1U/10VC151 0.1U/10V
1 2
C152 0.1U/10VC152 0.1U/10V
1 2
C150 0.1U/10VC150 0.1U/10V
1 2
C154 0.1U/10VC154 0.1U/10V
2600mA
C C
B B
A A
5
4
VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7
VCC SM LF
VCC SM LF
4
W28 V28 W26 V26 W25 V25 W24 V24 W23 V23 AM21 AL21 AK21 W21 V21 U21 AM20 AK20 W20 U20 AM19 AL19 AK19 AJ19 AH19 AG19 AF19 AE19 AB19 AA19 Y19 W19 V19 U19 AM17 AK17 AH17 AG17 AF17 AE17 AC17 AB17 Y17 W17 V17 AM16 AL16 AK16 AJ16 AH16 AG16 AF16 AE16 AC16 AB16 AA16 Y16 W16 V16 U16
AV44 BA37 AM40 AV21 AY5 AM10 BB13
VCCSM_LF1 VCCSM_LF2 VCCSM_LF3 VCCSM_LF4 VCCSM_LF5 VCCSM_LF6 VCCSM_LF7
Layout Note: 370 mils from edge.
+1.5V_DDR
12
C142
C142
0.1U/10V
0.1U/10V
Layout Note: Place C233 where LVDS and DDR2 taps.
C111
C111
0.1U/10V
0.1U/10V
12
C110
C110
0.1U/10V
0.1U/10V
12
+1.05V_VCCP
+
+
C587
C587 330U
330U
12
C98
C98
0.22U/10V
0.22U/10V
3
+3.3V_RUN
R440 10R440 10
1 2
Layout Note: Inside GMCH cavity.
+VCC_GMCH_L
Ivcc=1930.4+508.12=2438.52mA
12
C99
C99
0.22U/10V
0.22U/10V
12
C140
C140 22U/4V
22U/4V
Layout Note: Place on the edge.
12
C161
C161 1U/10V
1U/10V
3
12
C129
C129
0.22U/10V
0.22U/10V
12
C109
C109 22U/4V
22U/4V
+
+
12
C245
C245 330U/2.5V
330U/2.5V
12
C169
C169
0.47U/10V
0.47U/10V
12
C156
C156
0.22U/10V
0.22U/10V
VCC_SM
12
12
C175
C175 1U/10V
1U/10V
D25
D25
SDMK0340L-7-F
SDMK0340L-7-F
12
C94
C94
0.1U/10V
0.1U/10V
C153
C153 22U/4V
22U/4V
2
U30F
U30F
21
2
AG34
VCC_1
AC34
VCC_2
AB34
VCC_3
AA34
VCC_4
Y34
VCC_5
V34
VCC_6
U34
VCC_7
AM33
VCC_8
AK33
VCC_9
AJ33
VCC_10
AG33
VCC_11
AF33
VCC_12
AE33
VCC_13
AC33
VCC_14
AA33
VCC_15
Y33
VCC_16
W33
VCC_17
V33
VCC_18
U33
VCC_19
AH28
VCC_20
AF28
VCC_21
AC28
VCC_22
AA28
VCC_23
AJ26
VCC_24
AG26
VCC_25
AE26
VCC_26
AC26
VCC_27
AH25
VCC_28
AG25
VCC_29
AF25
VCC_30
AG24
VCC_31
AJ23
VCC_32
AH23
VCC_33
AF23
VCC_34
T32
VCC_35
CANTIGA_verB3
CANTIGA_verB3
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
VCC CORE
VCC CORE
POWER
POWER
VCC NCTF
VCC NCTF
QUANTA
QUANTA
QUANTA COMPUTER
Cantiga_D (VCC,NCTF)
Cantiga_D (VCC,NCTF)
Cantiga_D (VCC,NCTF)
RM3 3A
RM3 3A
RM3 3A
VCC_NCTF_1 VCC_NCTF_2 VCC_NCTF_3 VCC_NCTF_4 VCC_NCTF_5 VCC_NCTF_6 VCC_NCTF_7 VCC_NCTF_8
VCC_NCTF_9 VCC_NCTF_10 VCC_NCTF_11 VCC_NCTF_12 VCC_NCTF_13 VCC_NCTF_14 VCC_NCTF_15 VCC_NCTF_16 VCC_NCTF_17 VCC_NCTF_18 VCC_NCTF_19 VCC_NCTF_20 VCC_NCTF_21 VCC_NCTF_22 VCC_NCTF_23 VCC_NCTF_24 VCC_NCTF_25 VCC_NCTF_26 VCC_NCTF_27 VCC_NCTF_28 VCC_NCTF_29 VCC_NCTF_30 VCC_NCTF_31 VCC_NCTF_32 VCC_NCTF_33 VCC_NCTF_34 VCC_NCTF_35 VCC_NCTF_36 VCC_NCTF_37 VCC_NCTF_38 VCC_NCTF_39 VCC_NCTF_40 VCC_NCTF_41 VCC_NCTF_42 VCC_NCTF_43 VCC_NCTF_44
1
+1.05V_VCCP
AM32 AL32 AK32 AJ32 AH32 AG32 AE32 AC32 AA32 Y32 W32 U32 AM30 AL30 AK30 AH30 AG30 AF30 AE30 AC30 AB30 AA30 Y30 W30 V30 U30 AL29 AK29 AJ29 AH29 AG29 AE29 AC29 AA29 Y29 W29 V29 AL28 AK28 AL26 AK26 AK25 AK24 AK23
860Wednesday, May 06, 2009
860Wednesday, May 06, 2009
860Wednesday, May 06, 2009
of
of
1
of
5
+1.05V_VCCP
D D
C C
B B
45mA MAx.
R660R66
FB_120ohm+-25%_100mHz
0
_200mA_0.2ohm DC
L10
L10
12
BLM18AG121SN1D
BLM18AG121SN1D
603
603
+VCCA_MPLL_L
L9
L9 BLM18AG121SN1D
BLM18AG121SN1D
603
603
R70
R70
1 2
0.5/F 603
0.5/F 603
12
C90
C90 22U
22U
1206 10V
1206 10V
+1.05V_VCCP
FB_220ohm+-25% _100MHz_2A_0.1ohm DC
+1.05V_VCCP
+1.5V_RUN
12
L25
L25
1 2
BLM21PG221SN1D
BLM21PG221SN1D
805
805
L22
L22
BLM18PG181SN1D
BLM18PG181SN1D
603
603
L14
L14
BLM18PG181SN1D
BLM18PG181SN1D
603
603
1 2
+VCCA_MPLL
+VCCA_HPLL
C91
C91
4.7U
4.7U
603
603
6.3
6.3
+VCCA_PEG_PLL
12
R174
R174 1/F
1/F
603
603
+VCCA_PEG_PLL_R
12
C254
C254 10U
10U
603
603
6.3
6.3
+VCCD_PEG_PLL
12
R1631R163 1
+VCCD_PEG_PLL_RC
C232
C232 10U
10U
603
603
6.3
6.3
12
C589
C589
0.1U/10V
0.1U/10V
10V
10V
12
C588
C588
0.1U
0.1U
10V
10V
50mA
C143
C143
0.01U
0.01U
25
25
+1.05V_VCCP
+VCCD_QDAC
12
C144
C144
0.1U
0.1U
10V
10V
H=1.9
+1.05V_VCCP
12
C586
C586
+
+
100U/6.3V_3528
100U/6.3V_3528
3528
3528
6.3
6.3
1uH+-20%_300mA
120uA
L13
L13 1uH/300mA
1uH/300mA
4
U30H
U30H
B27
VCCA_CRT_DAC_1
A26
VCCA_CRT_DAC_2
A25
VCCA_DAC_BG
B25
VSSA_DAC_BG
F47
VCCA_DPLLA
L48
24mA
139.2mA
+1.5V_RUN
+VCCA_HPLL +VCCA_MPLL
414uA
12
C624
C624
0.1U
0.1U
10V
10V
+VCCA_PEG_PLL
12
C248
C248
0.1U
0.1U
10V
10V
50mA
480mA
12
12
C117
C117
C127
C127
4.7U
*22U_NC
*22U_NC
4.7U
603
805
805
603
1 2
6.3
10
10
6.3
+VCCA_SM_CK
12
12
C141
C141 *22U/10V_NC
*22U/10V_NC
12
C112
C112 22U
22U
805
805 10
10
C137
C137 22U/10V
22U/10V
24mA
12
12
C115
C115 1U
1U
603
603 10
10
C138
C138
0.1U/10V
0.1U/10V
35mA
C244
C244
0.1U/10V
0.1U/10V
12 12
+VCCD_QDAC +VCCA_MPLL_L +VCCD_PEG_PLL
157.2mA
C585 0.1U/10VC585 0.1U/10V
VCCA_DPLLB
AD1
VCCA_HPLL
AE1
VCCA_MPLL
J48
VCCA_LVDS
J47
VSSA_LVDS
AD48
VCCA_PEG_BG
AA48
VCCA_PEG_PLL
AR20
VCCA_SM_1
AP20
VCCA_SM_2
AN20
VCCA_SM_3
AR17
VCCA_SM_4
AP17
VCCA_SM_5
AN17
VCCA_SM_6
AT16
VCCA_SM_7
AR16
VCCA_SM_8
AP16
VCCA_SM_9
AP28
VCCA_SM_CK_1
AN28
VCCA_SM_CK_2
AP25
VCCA_SM_CK_3
AN25
VCCA_SM_CK_4
AN24
VCCA_SM_CK_5
AM28
VCCA_SM_CK_NCTF_1
AM26
VCCA_SM_CK_NCTF_2
AM25
VCCA_SM_CK_NCTF_3
AL25
VCCA_SM_CK_NCTF_4
AM24
VCCA_SM_CK_NCTF_5
AL24
VCCA_SM_CK_NCTF_6
AM23
VCCA_SM_CK_NCTF_7
AL23
VCCA_SM_CK_NCTF_8
B24
VCCA_TV_DAC_1
A24
VCCA_TV_DAC_2
A32
VCC_HDA
M25
VCCD_TVDAC
L28
VCCD_QDAC
AF1
VCCD_HPLL
AA47
VCCD_PEG_PLL
M38
VCCD_LVDS_1
L37
VCCD_LVDS_2
CANTIGA_verB3
CANTIGA_verB3
3
CRTPLLA PEGA SM
CRTPLLA PEGA SM
A LVDS
A LVDS
POWER
POWER
A CK
A CK
TV
TV
HDA
HDA
D TV/CRT
D TV/CRT
LVDS
LVDS
AXF
AXF
VCC_SM_CK_1 VCC_SM_CK_2 VCC_SM_CK_3 VCC_SM_CK_4
SM CK
SM CK
VCC_TX_LVDS
HV
HV
PEG
PEG
DMI
DMI
VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8
VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14
VTT
VTT
VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25
VCC_AXF_1 VCC_AXF_2 VCC_AXF_3
VCC_HV_1 VCC_HV_2 VCC_HV_3
VCC_PEG_1 VCC_PEG_2 VCC_PEG_3 VCC_PEG_4 VCC_PEG_5
VCC_DMI_1 VCC_DMI_2 VCC_DMI_3 VCC_DMI_4
VTTLF1 VTTLF2 VTTLF3
VTTLF
VTTLF
U13 T13 U12 T12 U11 T11 U10 T10 U9 T9 U8 T8 U7 T7 U6 T6 U5 T5 V3 U3 V2 U2 T2 V1 U1
B22 B21 A21
BF21 BH20 BG20 BF20
K47 C35
B35 A35
V48 U48 V47 U47 U46
AH48 AF48 AH47 AG47
A8 L1 AB2
+VCC_SM_CK
+3.3V_VCC_HV
456mA
+VTTLF1 +VTTLF2 +VTTLF3
12
C149
C149
2.2U/6.3V
2.2U/6.3V
1782mA
+VCC_PEG
852mA
12
C145
C145
4.7U/6.3V
4.7U/6.3V
Close to VTT
119.85mA
105.3mA
12
+
+
12
C221
C221
0.1U/10V
0.1U/10V
+VTTLF1 +VTTLF2 +VTTLF3
C636
C636 220U/4V
220U/4V
2V
2V
12
2
12
+VCC_PEG
C100
C100
0.47U/10V
0.47U/10V
C130
C130
0.47U/6.3V
0.47U/6.3V
12
C634
C634 22U/10V
22U/10V
+1.05V_VCCP
12
C148
C148
4.7U
4.7U
603
603
6.3
6.3
12
C128
C128 1U/10V
1U/10V
12
C118
C118
0.1U/10V
0.1U/10V
Actual measurement (VCC_PEG+VCC_DMI) :
1386.7 mA (under 3DMark06)
120 ohm, 3A
L70 BLM31PG121SN1LL70 BLM31PG121SN1L
1 2
C240
C240
4.7U
4.7U
603
603
1 2
6.3
6.3
12
12
C96
C96
0.47U/10V
0.47U/10V
12
+
+
C582
C582 220U/4V
220U/4V
7343
7343 2
2
Place on chip edge.
C131
C131 *10U_NC
*10U_NC
603
603
6.3
6.3
L11
805L11
805
1uH/300MA
1uH/300MA
12
R871R87 1
+VCC_SM_CK_L
C116
C116 10U
10U
603
603
6.3
6.3
+1.05V_VCCP
+3.3V_VCC_HV
C594
C594
0.47U/10V
0.47U/10V
+1.5V_DDR
R132 0R132 0
1 2
12
C167
C167
0.1U/10V
0.1U/10V
1
VCC_HV
D9
D9 *SDMK0340L-7-F_NC
*SDMK0340L-7-F_NC
+1.05V_VCCP
+1.05V_VCCP
21
D10
D10 SDM10K45-7-F
SDM10K45-7-F
R12910R129 10
1 2
+1.05V_VCCP
+3.3V_RUN
+3.3V_RUN
21
+VCC_HV_L
12
R69
R69 *10_NC
*10_NC
A A
QUANTA
QUANTA
QUANTA COMPUTER
COMPUTER
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
COMPUTER
Cantiga_E (POWER)
Cantiga_E (POWER)
Cantiga_E (POWER)
RM3 3A
RM3 3A
RM3 3A
960Wednesday, May 06, 2009
960Wednesday, May 06, 2009
960Wednesday, May 06, 2009
of
of
1
of
5
U30I
U30I
AU48
VSS_1
AR48
VSS_2
AL48
VSS_3
BB47
VSS_4
AW47
VSS_5
AN47
VSS_6
AJ47
VSS_7
D D
C C
B B
A A
5
AF47
AD47
AB47
Y47 N47 G47
BD46
BA46 AY46
AV46 AR46 AM46
V46 R46 P46 H46
BF44 AH44 AD44
AA44
Y44 U44
M44
BC43
AV43 AU43 AM43
C43
BG42
AY42
AT42 AN42
AJ42
AE42
N42
BD41 AU41 AM41 AH41 AD41
AA41
Y41 U41
M41 G41 B41
BG40
BB40
AV40 AN40
H40 E40
AT39 AM39
AJ39
AE39
N39
B39 BH38 BC38
BA38 AU38 AH38 AD38
AA38
Y38 U38
C38 BF37 BB37
AW37
AT37
AN37
AJ37
H37
C37
BG36 BD36
AK15
AU36
T47 L47
F46
T44 F44
J43
L42
T41
L39
T38 J38 F38
VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99
CANTIGA_verB3
CANTIGA_verB3
VSS
VSS
4
4
VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198
AM36 AE36 P36 L36 J36 F36 B36 AH35 AA35 Y35 U35 T35 BF34 AM34 AJ34 AF34 AE34 W34 B34 A34 BG33 BC33 BA33 AV33 AR33 AL33 AH33 AB33 P33 L33 H33 N32 K32 F32 C32 A31 AN29 T29 N29 K29 H29 F29 A29 BG28 BD28 BA28 AV28 AT28 AR28 AJ28 AG28 AE28 AB28 Y28 P28 K28 H28 F28 C28 BF26 AH26 AF26 AB26 AA26 C26 B26 BH25 BD25 BB25 AV25 AR25 AJ25 AC25 Y25 N25 L25 J25 G25 E25 BF24 AD12 AY24 AT24 AJ24 AH24 AF24 AB24 R24 L24 K24 J24 G24 F24 E24 BH23 AG23 Y23 B23 A23
3
U30J
U30J
BG21
VSS_199
L12
VSS_200
AW21
VSS_201
AU21
VSS_202
AP21
VSS_203
AN21
VSS_204
AH21
VSS_205
AF21
VSS_206
AB21
VSS_207
R21
VSS_208
M21
VSS_209
J21
VSS_210
G21
VSS_211
BC20
VSS_212
BA20
VSS_213
AW20
VSS_214
AT20
VSS_215
AJ20
VSS_216
AG20
VSS_217
Y20
VSS_218
N20
VSS_219
K20
VSS_220
F20
VSS_221
C20
VSS_222
A20
VSS_223
BG19
VSS_224
A18
VSS_225
BG17
VSS_226
BC17
VSS_227
AW17
VSS_228
AT17
VSS_229
R17 M17 H17 C17
BA16
AU16 AN16
N16 K16 G16
E16 BG15 AC15
W15
A15 BG14
AA14
C14 BG13 BC13
BA13
AN13
AJ13 AE13
N13
L13 G13 E13
BF12 AV12 AT12
AM12
AA12
J12 A12
BD11
BB11
AY11 AN11 AH11
Y11 N11 G11 C11
BG10
AV10
AT10
AJ10
AE10
AA10
M10
BF9 BC9 AN9 AM9 AD9
G9
B9
BH8
BB8
AV8
AT8
3
VSS_230 VSS_231 VSS_232 VSS_233
VSS_235 VSS_237
VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252
VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS_273
VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296
CANTIGA_verB3
CANTIGA_verB3
VSS
VSS
VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13
VSS NCTF
VSS NCTF
VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16
VSS SCB
VSS SCB
NC
NC
VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325
VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350
VSS_351 VSS_352 VSS_353 VSS_354
VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9
VSS_SCB_1 VSS_SCB_2 VSS_SCB_3 VSS_SCB_4 VSS_SCB_5 VSS_SCB_6
NC_26 NC_27 NC_28 NC_29 NC_30 NC_31 NC_32 NC_33 NC_34 NC_35 NC_36 NC_37 NC_38 NC_39 NC_40 NC_41 NC_42
2
AH8 Y8 L8 E8 B8 AY7 AU7 AN7 AJ7 AE7 AA7 N7 J7 BG6 BD6 AV6 AT6 AM6 M6 C6 BA5 AH5 AD5 Y5 L5 J5 H5 F5 BE4
BC3 AV3 AL3 R3 P3 F3 BA2 AW2 AU2 AR2 AP2 AJ2 AH2 AF2 AE2 AD2 AC2 Y2 M2 K2 AM1 AA1 P1 H1
U24 U28 U25 U29
AF32 AB32 V32 AJ30 AM29 AF29 AB29 U26 U23 AL20 V20 AC19 AL17 AJ17 AA17 U17
BH48 BH1 A48 C1 B2 A3
E1 D2 C3 B4 A5 A6 A43 A44 B45 C46 D47 B47 A46 F48 E48 C48 B48
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
QUANTA
QUANTA
QUANTA COMPUTER
Cantiga_F (VSS)
Cantiga_F (VSS)
Cantiga_F (VSS)
RM3 3A
RM3 3A
RM3 3A
1
10 60Wednesday, May 06, 2009
10 60Wednesday, May 06, 2009
10 60Wednesday, May 06, 2009
of
of
1
of
1
2
3
4
5
6
7
8
+RTC_CELL +RTC_CELL
12
R477
R477 332K/F
332K/F
ICH_INTVRMEN ICH_LAN100_SLP
12
R476
R476 *0_NC
*0_NC
ICH9M LAN100 SLP Strap
Low = Internal VR Disabled High = Internal VR Enabled(Default)
U34A
U34A
C23
RTCX1
C24
RTCX2
A25
RTCRST#
F20
SRTCRST#
C22
INTRUDER#
B22
INTVRMEN
A22
LAN100_SLP
E25
GLAN_CLK
C13
LAN_RSTSYNC
F14
LAN_RXD0
G13
LAN_RXD1
D14
LAN_RXD2
D13
LAN_TXD0
D12
LAN_TXD1
E13
LAN_TXD2
B10
GLAN_DOCK#/GPIO56
B28
GLAN_COMPI
B27
GLAN_COMPO
AF6
HDA_BIT_CLK
AH4
HDA_SYNC
AE7
HDA_RST#
AF4
HDA_SDIN0
AG4
HDA_SDIN1
AH3
HDA_SDIN2
AE5
HDA_SDIN3
AG5
HDA_SDOUT
AG7
HDA_DOCK_EN#/GPIO33
AE8
HDA_DOCK_RST#/GPIO34
AG8
SATALED#
AJ16
SATA0RXN
AH16
SATA0RXP
AF17
SATA0TXN
AG17
SATA0TXP
AH13
SATA1RXN
AJ13
SATA1RXP
AG14
SATA1TXN
AF14
SATA1TXP
ICH9M_verA3
ICH9M_verA3
RTCLAN / GLAN
RTCLAN / GLAN
IHDA
IHDA
SATA
SATA
(Internal VR for VccLAN1.05 and VccCL1.05)
Low = Internal VR Disabled High = Internal VR Enabled(Default)
SIO_A20GATE
H_DPRSTP# H_DPSLP#
H_FERR#_L
SIO_RCIN#
THERMTRIP#_ICH
SATABIAS
FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3
FWH4/LFRAME#
LDRQ1#/GPIO23
LPCCPU
LPCCPU
A20GATE
DPRSTP#
CPUPWRGD
STPCLK#
THRMTRIP#
SATA4RXN SATA4RXP SATA4TXN SATA4TXP
SATA5RXN SATA5RXP SATA5TXN SATA5TXP
SATA_CLKN
SATA_CLKP
SATARBIAS#
SATARBIAS
ICH_LAN100_SLP
K5 K4 L6 K2
K3 J3
LDRQ0#
J1 N7
AJ27
A20M#
AJ25 AE23
DPSLP#
AJ26
FERR#
AD22 AF25
IGNNE#
AE22
INIT#
AG25
INTR
L3
RCIN#
AF23
NMI
AF24
SMI#
AH27 AG26 AG27
TP9
AH11 AJ11 AG12 AF12
AH9 AJ9 AE10 AF10
AH18 AJ18
AJ7 AH7
12
R473
R473 332K/F
332K/F
12
R472
R472 *0_NC
*0_NC
R139 56R139 56
R210 24.9/FR210 24.9/F
1 2
LPC_LAD0 (31,34) LPC_LAD1 (31,34) LPC_LAD2 (31,34) LPC_LAD3 (31,34)
LPC_LFRAME# (31,34)
T81PAD T81PAD T147PAD T147PAD
SIO_A20GATE (31) H_A20M# (3)
H_DPRSTP# (3,6,51) H_DPSLP# (3)
H_FERR#
12
H_PWRGOOD (3) H_IGNNE# (3) H_INIT# (3)
H_INTR (3)
SIO_RCIN# (31)
H_NMI (3) H_SMI# (3)
H_STPCLK# (3)
T119PAD T119PAD
SATA_RX5- (35) SATA_RX5+ (35) SATA_TX5-_C (35)
SATA_TX5+_C (35) CLK_PCIE_SATA# (17)
CLK_PCIE_SATA (17)
Place within 500mils of ICH9 ball
H_FERR# (3)
E-SATA
1 2
H_DPRSTP# H_DPSLP# H_FERR#
SIO_A20GATE SIO_RCIN#
THERMTRIP#_ICH
R147
R147 *56_NC
*56_NC
+1.05V_VCCP
R156
R156 *56_NC
*56_NC
1 2
R197
R197
8.2K
8.2K
1 2
+1.05V_VCCP
1 2
+3.3V_RUN
1 2
1 2
R14056R140 56
R525
R525 10K
10K
R46356R463 56
+RTC_CELL
12
R1511MR151 1M
R467 10MR467 10M
W1
W1
32.768KHZ
32.768KHZ
R135
R135 20K
20K
1 2
12
C195
C195 1U/10V
1U/10V
12
12
R466
R466 20K
20K
1 2
ICH_RTCRST# ICH_SRTCRST# ICH_INTRUDER#
12
C621
C621 1U/10V
1U/10V
ICH_RTCX2ICH_RTCX1
12
C622
C622 15P/50V
15P/50V
R225 33R225 33
1 2
C338
C338 *27P/50V_NC
*27P/50V_NC
1 2
R228 33R228 33
1 2
R236 33R236 33
1 2
R229 33R229 33
1 2
ICH9M Internal VR Enable Strap (Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)
ICH_INTVRMEN
ICH_RTCX1 ICH_RTCX2
ICH_RTCRST# ICH_SRTCRST# ICH_INTRUDER#
ICH_INTVRMEN ICH_LAN100_SLP
T50 PADT50 PAD
+3.3V_SUS
+3.3V_SUS
SATA_ACT#(38)
SATA_RX0-(36)
SATA_RX0+(36) SATA_TX0-_C(36) SATA_TX0+_C(36)
SATA_RX1-(36)
SATA_RX1+(36) SATA_TX1-_C(36) SATA_TX1+_C(36)
T144
T144 T145
T145 T77
T77
T140 PADT140 PAD T61 PADT61 PAD
T66 PADT66 PAD T64 PADT64 PAD T67 PADT67 PAD T68 PADT68 PAD T69 PADT69 PAD
R496 *10K_NCR496 *10K_NC
R462 24.9/FR462 24.9/F
1 2
ACZ_BIT_CLK
ACZ_SYNC ACZ_RST# ACZ_SDOUT ACZ_SYNC
Reserved for Intel Nineveh design.
+1.5V_PCIE_ICH
ICH_AZ_CODEC_SDIN0(40)
HDD
ODD
GLAN_CLK LAN_RSTSYNC LAN_RXD0
LAN_RXD1 LAN_RXD2 LAN_TXD0 LAN_TXD1 LAN_TXD2
12
GLAN_COMP ACZ_BIT_CLK
ACZ_RST#
PAD
PAD PAD
PAD PAD
PAD
ACZ_SDOUT
R196 *10K_NCR196 *10K_NC R247 *10K_NCR247 *10K_NC
12 12
32.768KHZ
12
C623
C623 15P/50V
15P/50V
A A
B B
C C
ICH_AZ_CODEC_BITCLK(40)
ICH_AZ_CODEC_SYNC(40) ICH_AZ_CODEC_RST#(31,40) ICH_AZ_CODEC_SDOUT(40)
Place all series terms close to ICH9 except for SDIN input lines,which should be close to source.Placement of R603, R600, R607 & R612 should equal distance to the T split trace point as R604, R599, R606 & R608 respective. Basically,keep the same distance from T for all series termination resistors.
+3.3V_RUN
R223
5
1 2
1 2
R223 *1K_NC
*1K_NC
R475
R475 *1K_NC
*1K_NC
ACZ_SDOUT
ICH_RSVD (13)
QUANTA
QUANTA
QUANTA COMPUTER
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
6
Date: Sheet
ICH9-M(CPU,SATA,IDE)
ICH9-M(CPU,SATA,IDE)
ICH9-M(CPU,SATA,IDE)
RM3 3A
RM3 3A
RM3 3A
7
11 60Wednesday, May 06, 2009
11 60Wednesday, May 06, 2009
11 60Wednesday, May 06, 2009
of
of
of
8
D D
1
2
3
XOR Chain Entrance Strap
ICH RSVD
HDA SDOUT
0 0 1 1
Description
RSVD
0 1
Enter XOR Chain
0
Normal Operation (Default)
1
Set PCIE port config bit 1
4
1
Place TX DC blocking caps close ICH8.
C617 0.1U 10C617 0.1U 10
PCIE_TX1-(34) PCIE_TX1+(34)
PCIE_TX2-(33) PCIE_TX2+(33)
PCIE_TX3-(34)
A A
B B
PCIE_TX3+(34)
PCIE_TX4-(30) PCIE_TX4+(30)
PCIE_TX6-/GLAN_TX-(43) PCIE_TX6+/GLAN_TX+(43)
ICH_SPI_CS1#_R PCI_GNT0#
1 2
R227
R227 *1K_NC
*1K_NC
12
1 2
C616 0.1U 10C616 0.1U 10
1 2
C615 0.1U 10C615 0.1U 10
1 2
C614 0.1U 10C614 0.1U 10
1 2
C613 0.1U 10C613 0.1U 10
1 2
C612 0.1U 10C612 0.1U 10
1 2
C611 0.1U 10C611 0.1U 10
1 2
C610 0.1U 10C610 0.1U 10
1 2
C609 0.1U 10C609 0.1U 10
1 2
C608 0.1U 10C608 0.1U 10
1 2
R150
R150 *1K_NC
*1K_NC
PCI SPI1001
WWAN Noise - ICH improvements
OC6# OC4# OC5# OC7# USB_OC8# OC2_3# USB_OC0_1# OC9#
C C
D D
C339 *0.1U_NC 10C339 *0.1U_NC 10 C690 *0.1U_NC 10C690 *0.1U_NC 10 C692 *0.1U_NC 10C692 *0.1U_NC 10 C325 *0.1U_NC 10C325 *0.1U_NC 10 C342 *0.1U_NC 10C342 *0.1U_NC 10 C336 *0.1U_NC 10C336 *0.1U_NC 10 C310 *0.1U_NC 10C310 *0.1U_NC 10 C691 *0.1U_NC 10C691 *0.1U_NC 10
PCI_AD[0..31](28,56)
PCI_PIRQA & D : Mini PCI debug PCI_PIRQB & C : Card Reader
PCI_PIRQA#(56) PCI_PIRQB#(28)
PCI_PIRQD#(56)
1
1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2
PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31
PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#
2
PCIE_TXN1_C PCIE_TXP1_C
PCIE_TXN2_C PCIE_TXP2_C
PCIE_TXN3_C PCIE_TXP3_C
PCIE_TXN4_C PCIE_TXP4_C
GLAN_TXN_C GLAN_TXP_C
PCIE_RX6-/GLAN_RX-(43) PCIE_RX6+/GLAN_RX+(43)
Boot BIOS Strap
GNT0# SPI_CS1#
No stuff
11LPC
Places within 500 mils of the ICH9
D11
C8 D9
E12
E9
C9
E10
B7 C7 C5
G11
F8
F11
E7
A3 D2
F10
D5
D10
B3
F7 C3
F3
F4 C1 G7 H7 D1 G5 H6 G1 H3
J5
E1
J6
No stuff Stuff
No stuff Stuff
No stuff
+3.3V_SUS
U34B
U34B
AD0
PCI
PCI
AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
Interrupt I/F
Interrupt I/F
PIRQA# PIRQB# PIRQC# PIRQD#C4PIRQH#/GPIO5
ICH9M_verA3
ICH9M_verA3
2
OC9# OC4# USB_OC8# OC5#
OC10# OC11#
REQ0#
GNT0# REQ1#/GPIO50 GNT1#/GPIO51 REQ2#/GPIO52 GNT2#/GPIO53 REQ3#/GPIO54 GNT3#/GPIO55
C/BE0# C/BE1# C/BE2# C/BE3#
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR# STOP# TRDY#
FRAME#
PLTRST#
PCICLK
PME#
PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4
3
PCIE_RX1-(34) PCIE_RX1+(34)
MiniWWAN
PCIE_RX2-(33) PCIE_RX2+(33)
MiniWLAN
PCIE_RX3-(34) PCIE_RX3+(34)
MiniWPAN
PCIE_RX4-(30) PCIE_RX4+(30)
Express Card
Giga Bit LOM
T51 PADT51 PAD T45 PADT45 PAD
T49 PADT49 PAD T52 PADT52 PAD
USB_OC0_1#(35)
USB_OC8#(35)
R527 22.6/FR527 22.6/F
1 2
RP6
RP6
6 7 8 9
10
10KX8
10KX8 R219 10KR219 10K R224 10KR224 10K
PCI_REQ0#
F1
PCI_GNT0#
G4
PCI_REQ1#
B6
PCI_GNT1#
A7
SB_WWAN_PCIE_RST#
F13
PCI_GNT2#
F12
SB_LOM_PCIE_RST#
E6
PCI_GNT3#
F6 D8
B4 D6 A5
PCI_IRDY#
D3 E3
PCI_RST#_G
R1
PCI_DEVSEL#
C6
PCI_PERR#
E4
PCI_PLOCK#
C2
PCI_SERR#
J4
PCI_STOP#
A4
PCI_TRDY#
F5
PCI_FRAME#
D7
PCI_PLTRST#
C14
CLK_PCI_ICH
D4 R2
SB_WPAN_PCIE_RST#
H4
SB_WLAN_PCIE_RST#
K6
SB_NB_PCIE_RST#
F2
ICH_IRQH_GPIO5
G2
3
ICH_SPI_CS1#_R
USB_OC0_1# OC2_3# OC4#
OC5# OC6# OC7# USB_OC8# OC9# OC10# OC11#
USBRBIAS
+3.3V_SUS
5 4 3 2 1
12 12
PCIE_TXN1_C PCIE_TXP1_C
PCIE_TXN2_C PCIE_TXP2_C
PCIE_TXN3_C PCIE_TXP3_C
PCIE_TXN4_C PCIE_TXP4_C
T44 PADT44 PAD T116 PADT116 PAD T47 PADT47 PAD T46 PADT46 PAD
GLAN_TXN_C GLAN_TXP_C
OC7# OC6# USB_OC0_1# OC2_3#
+3.3V_SUS
PCI_REQ0# (28) PCI_GNT0# (28) PCI_REQ1# (56) PCI_GNT1# (56) SB_WWAN_PCIE_RST# (34)
T71PAD T71PAD
SB_LOM_PCIE_RST# (43)
T75PAD T75PAD
PCI_C_BE0# (28,56) PCI_C_BE1# (28,56) PCI_C_BE2# (28,56) PCI_C_BE3# (28,56)
PCI_IRDY# (28,56) PCI_PAR (28,56)
PCI_DEVSEL# (28,56) PCI_PERR# (28,56)
PCI_SERR# (28,56) PCI_STOP# (28,56) PCI_TRDY# (28,56) PCI_FRAME# (28,56)
CLK_PCI_ICH (17) ICH_PME# (28,56)
SB_WPAN_PCIE_RST# (34) SB_WLAN_PCIE_RST# (33) SB_NB_PCIE_RST# (6)PCI_PIRQC#(28) ICH_IRQH_GPIO5 (36)
T83PAD T83PAD
4
U34D
U34D
N29
PERN1
N28
PERP1
P27
PETN1
P26
PETP1
L29
PERN2
L28
PERP2
M27
PETN2
M26
PETP2
J29
PERN3
J28
PERP3
K27
PETN3
K26
PETP3
G29
PERN4
G28
PERP4
H27
PETN4
H26
PETP4
E29
PERN5
E28
PERP5
F27
PETN5
F26
PETP5
C29
PERN6/GLAN_RXN
C28
PERP6/GLAN_RXP
D27
PETN6/GLAN_TXN
D26
PETP6/GLAN_TXP
D23
SPI_CLK
D24
SPI_CS0#
F23
SPI_CS1#/GPIO58/CLGPIO6
D25
SPI_MOSI
E23
SPI_MISO
N4
OC0#/GPIO59
N5
OC1#/GPIO40
N6
OC2#/GPIO41
P6
OC3#/GPIO42
M1
OC4#/GPIO43
N2
OC5#/GPIO29
M4
OC6#/GPIO30
M3
OC7#/GPIO31
N3
OC8#/GPIO44
N1
OC9#/GPIIO45
P5
OC10#/GPIO46
P3
OC11#/GPIO47
AG2
USBRBIAS
AG1
USBRBIAS#
ICH9M_verA3
ICH9M_verA3
Card Reader Mini PCI debug
4
5
V27
DMI0RXN
V26
DMI0RXP
U29
DMI0TXN
U28
DMI0TXP
Y27
DMI1RXN
Y26
DMI1RXP
W29
DMI1TXN
W28
DMI1TXP
AB27
DMI2RXN
AB26
DMI2RXP
AA29
DMI2TXN
AA28
DMI2TXP
AD27
DMI3RXN
AD26
DMI3RXP
AC29
DMI3TXN
AC28
DMI3TXP
T26
DMI_CLKN DMI_CLKP
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
T25 AF29
AF28 AC5
AC4 AD3 AD2 AC1 AC2 AA5 AA4 AB2 AB3 AA1 AA2 W5 W4 Y3 Y2 W1 W2 V2 V3 U5 U4 U1 U2
DMI_COMP
PCI-Express
PCI-Express
DMI_ZCOMP
Direct Media Interface
Direct Media Interface
DMI_IRCOMP
SPI
SPI
USB
USB
A16 away override strap.
SB_NB_PCIE_RST#
5
DMI_MTX_IRX_N0 (6) DMI_MTX_IRX_P0 (6)
DMI_MRX_ITX_N0 (6) DMI_MRX_ITX_P0 (6)
DMI_MTX_IRX_N1 (6) DMI_MTX_IRX_P1 (6)
DMI_MRX_ITX_N1 (6) DMI_MRX_ITX_P1 (6)
DMI_MTX_IRX_N2 (6) DMI_MTX_IRX_P2 (6)
DMI_MRX_ITX_N2 (6) DMI_MRX_ITX_P2 (6)
DMI_MTX_IRX_N3 (6) DMI_MTX_IRX_P3 (6)
DMI_MRX_ITX_N3 (6) DMI_MRX_ITX_P3 (6)
CLK_PCIE_ICH# (17) CLK_PCIE_ICH (17)
1 2
R464 24.9/FR464 24.9/F
ICH_USBP0- (42) ICH_USBP0+ (42) ICH_USBP1- (42) ICH_USBP1+ (42)
T151PAD T151PAD T152PAD T152PAD T78PAD T78PAD
T80PAD T80PAD
ICH_USBP4- (33) ICH_USBP4+ (33) ICH_USBP5- (34) ICH_USBP5+ (34) ICH_USBP6- (34) ICH_USBP6+ (34) ICH_USBP7- (30) ICH_USBP7+ (30) ICH_USBP8- (35) ICH_USBP8+ (35) ICH_USBP9- (35) ICH_USBP9+ (35)
T76PAD T76PAD
T79PAD T79PAD
ICH_USBP11- (37) ICH_USBP11+ (37)
PCI_GNT3#
12
R209
R209
*1K_NC
*1K_NC
Low = A16 swap override enabled. High = Default.
CLK_PCI_ICH
Reserved for EMI.Place resister and cap close to ICH.
6
+1.5V_PCIE_ICH
Place within 500mils of ICH8
Side pair (Top / left, IB) Side pair (Bottom / left, IB)
Mini Card (WLAN) Mini Card (WWAN) Mini Card (WPAN) Express Card USB W/ E-SATA port TV
Camera
Non-iAMT
R232
R232 *10_NC
C340
C340 *8.2P_NC
*8.2P_NC
6
*10_NC
16
16
PCI_PLTRST#
1 2
1 2
7
8
PCI Pullups
RP5
PCI_FRAME# PCI_DEVSEL# PCI_TRDY# PCI_STOP#
+3.3V_RUN
PCI_PIRQB# PCI_PIRQC# PCI_PIRQA# PCI_REQ0#
+3.3V_RUN
SB_WPAN_PCIE_RST# SB_WWAN_PCIE_RST# SB_WLAN_PCIE_RST# SB_LOM_PCIE_RST# SB_NB_PCIE_RST#
BIOS should not enable the internal GPIO pull up resistor.
+3.3V_SUS
C349
C349
1 2
0.047U
0.047U
2
10
10
PCI_RST#_G
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
1
+3.3V_SUS
C647
C647
1 2
0.047U
0.047U
2
10
10
1
ICH9-M(USB,PCIE,DMI)
ICH9-M(USB,PCIE,DMI)
ICH9-M(USB,PCIE,DMI)
RM3 3A
RM3 3A
RM3 3A
7
RP5
6 7 8 9
10
8.2K_10P8R
8.2K_10P8R RP7
RP7
6 7 8 9
10
8.2K_10P8R
8.2K_10P8R
Add Buffers as needed for Loading and fanout concerns.
5
U5
U5
4
TC7SZ32FU(T5L,F,T)
TC7SZ32FU(T5L,F,T)
5
U35
U35
4
TC7SZ32FU(T5L,F,T)
TC7SZ32FU(T5L,F,T)
QUANTA
QUANTA
QUANTA COMPUTER
+3.3V_RUN
5
PCI_REQ1#
4
PCI_IRDY#
3
PCI_PIRQD#
2
PCI_PERR#
1
+3.3V_RUN
5
PCI_PLOCK#
4 3
ICH_IRQH_GPIO5
2
PCI_SERR#
1
R203 20KR203 20K R182 20KR182 20K R205 20KR205 20K R220 20KR220 20K R522 20KR522 20K
PLTRST# (6,18,30,31,33,34,43)
12 12 12 12 12
PCI_RST# (28,56)
12 60Wednesday, May 06, 2009
12 60Wednesday, May 06, 2009
12 60Wednesday, May 06, 2009
8
of
of
of
1
2
3
4
5
6
7
8
+3.3V_SUS
RP2
RP2
1 3
2.2KX2
2.2KX2
A A
+3.3V_RUN
R242
R242
8.2K
8.2K
1 2
R233
B B
C C
+3.3V_RUN
+3.3V_RUN
D D
+3.3V_SUS
R233
*10_NC
*10_NC
1 2
Option to " Disable " clkrun. Pulling it down will keep the clks running.
PCIE_MCARD1_DET#(33)
R177 10KR177 10K
R159 2.2KR159 2.2K R171 100KR171 100K
1 2
R154 100KR154 100K
1 2
R243 100KR243 100K
1 2
R215 100KR215 100K
1 2
R158 100KR158 100K
1 2
R148 *10K_NCR148 *10K_NC R193 10KR193 10K R149 10KR149 10K
R164 10KR164 10K R478 10KR478 10K R480 100KR480 100K
1 2
CLKRUN#
1
ICH_SMBDATA
2
ICH_SMBCLK
4
12
12
12 12 12
12 12
Non-iAMT
PCIE_MCARD1_DET#
PLTRST_DELAY#
IMVP_PWRGD
USB_MCARD2_DET#
USB_MCARD3_DET#
PCIE_MCARD1_DET#
PCIE_MCARD2_DET# PCIE_MCARD3_DET#
MCH_ICH_SYNC# IRQ_SERIRQ THERM_ALERT#
RSV_WOL_EN SIO_EXT_SMI# USB_MCARD1_DET#
R244
R244
4.7K
4.7K
2
12
WPAN_RADIO_DIS_MINI#(34)
+3.3V_SUS
R180 *10K_NCR180 *10K_NC R176 10KR176 10K R489 10KR489 10K R173 1KR173 1K
ITP_DBRESET#(3) PM_BMBUSY#(6)
USB_MCARD1_DET#(33)
H_STP_PCI#(17) H_STP_CPU#(17)
CLKRUN#(28,31,56) PCIE_WAKE#(30,33,34,43)
IRQ_SERIRQ(28,31,56)
THERM_ALERT#(39)
IMVP_PWRGD(31,45,51)
USB_MCARD2_DET#(34) USB_MCARD3_DET#(34)
SIO_EXT_WAKE#(31) SIO_EXT_SMI#(31) SIO_EXT_SCI#(31)
T133 PADT133 PAD
KB_LED_DET(37)
PCIE_MCARD2_DET#(34) PCIE_MCARD3_DET#(34)
WLAN_RADIO_DIS#(33)
CAMERA_CBL_DET#(37)
SATA_CLKREQ#(17)
PLTRST_DELAY#(18)
WWAN_RADIO_DIS#(34)
T120 PADT120 PAD T143 PADT143 PAD
MCH_ICH_SYNC#(6)
ICH_RSVD(11)
T138 PADT138 PAD T135 PADT135 PAD T130 PADT130 PAD
SPKR
T63 PADT63 PAD T60 PADT60 PAD T65 PADT65 PAD
T72 PADT72 PAD
T134 PADT134 PAD
SPKR(40)
+3.3V_RUN
12
R200
R200
*1K_NC
*1K_NC
No Reboot strap.
RSV_ICH_CL_RST1#
12
ICH_RI#
12
SIO_EXT_SCI#
12
PCIE_WAKE#
12
ICH_SMBCLK ICH_SMBDATA RSV_ICH_CL_RST1# ICH_SMBCLK ICH_SMBDATA
ICH_RI# RSV_LPCPD#
USB_MCARD1_DET#
CLKRUN# PCIE_WAKE#
IRQ_SERIRQ THERM_ALERT#
IMVP_PWRGD
USB_MCARD2_DET# USB_MCARD3_DET#
SIO_EXT_SMI# SIO_EXT_SCI#
PCIE_MCARD2_DET# PCIE_MCARD3_DET#
PLTRST_DELAY#
SPKR MCH_ICH_SYNC#
TP9 TP10 TP11
SPKR
Low = Default. High = No Reboot.
3
Non-iAMT
AJ23
AG19 AH21 AG21
AE18
AJ22
AE19 AG22 AF21 AH24
AJ24
AH20
AJ20 AJ21
U34C
U34C
G16
SMBCLK
A13
SMBDATA
E17
LINKALERT#/GPIO60/CLGPIO4
C17
SMLINK0
B18
SMLINK1
F19
RI#
R4
SUS_STAT#/LPCPD#
G19
SYS_RESET#
M6
PMSYNC#/GPIO0
A17
SMBALERT#/GPIO11
A14
STP_PCI#/GPIO15
E19
STP_CPU#/GPIO25
L4
CLKRUN#/GPIO32
E20
WAKE#
M5
SERIRQ THRM#
D21
VRMPWRGD
A20
TP8 TACH1/GPIO1
TACH2/GPIO6 TACH3/GPIO7
A21
GPIO8
C12
LANPHYPC/GPIO12
C21
ENGDET/GPIO13 TACH0/GPIO17
K1
GPIO18
AF8
GPIO20 SCLOCK/GPIO22
A9
QRT_STATE0/GPIO27
D19
QRT_STATE1/GPIO28
L1
SATACLKREQ#/GPIO35 SLOAD/GPIO38 SDATAOUT0/GPIO39 SDATAOUT1/GPIO48 GPIO49
A8
GPIO57/CLGPIO5
M7
SPKR MCH_SYNC#
B21
TP3 TP9 TP10 TP11
ICH9M_verA3
ICH9M_verA3
+3.3V_RUN
R155
R155
8.2K
8.2K
1 2
CLK_ICH_14M CLK_ICH_48M
ICH_SUSCLK
ICH_PWRGD DPRSLPVR
ICH_BATLOW#
RSV_ICH_LAN_RST# ICH_RSMRST#
ICH_CL_PWROK
RSV_ICH_CL_CLK1
RSV_ICH_CL_DATA1 CL_VREF0
CL_VREF1
CL_RST1# RSV_GPIO24
RSV_GPIO10 RSV_GPIO14 RSV_WOL_EN
Non-iAMT
2
4
RP3
RP3
2.2KX2
2.2KX2
1
3
CLK_ICH_14M (17) CLK_ICH_48M (17)
SIO_SLP_S3# (31) SIO_SLP_S5# (31)
ICH_PWRGD (6,45) DPRSLPVR (6,51)
R488 8.2KR488 8.2K
SIO_PWRBTN# (31)
ICH_RSMRST# (31) CLK_PWRGD (17) ICH_CL_PWROK (6,31)
CL_CLK0 (6)
CL_DATA0 (6)
ICH_CL_RST0# (6)
R188 8.2KR188 8.2K
MEM_SCLK (15,16)ICH_SMBCLK(30,33,34)
12
12
T148PAD T148PAD
T58PAD T58PAD
+3.3V_SUS
T53PAD T53PAD
T55PAD T55PAD
T136PAD T136PAD
T137PAD T137PAD
T139PAD T139PAD T62PAD T62PAD
T56PAD T56PAD T70PAD T70PAD T54PAD T54PAD
+3.3V_SUS
6
CLK14 CLK48
SUSCLK
SLP_S3# SLP_S4# SLP_S5#
PWROK
BATLOW# PWRBTN#
LAN_RST#
RSMRST#
CLPWROK
SLP_M#
CL_CLK0 CL_CLK1
CL_DATA0 CL_DATA1
CL_VREF0 CL_VREF1
CL_RST0# CL_RST1#
+3.3V_RUN
AH23 AF19 AE21 AD20
H1 AF3
P1 C16
E16 G17
C10 G20 M2 B13 R3 D20 D22 R5 R6 B16 F24
B19 F22
C19 C25
A19 F21
D18 A16
C18 C11 C20
SATA0GP/GPIO21 SATA1GP/GPIO19 SATA4GP/GPIO36 SATA5GP/GPIO37
SATA
SATA
GPIO
GPIO
SMB
SMB
Clocks
Clocks
S4_STATE#/GPIO26
DPRSLPVR/GPIO16
SYS GPIO
SYS GPIO
Power MGTController Link
Power MGTController Link
CK_PWRGD
GPIO
GPIO
MEM_LED/GPIO24
ALERT#/GPIO10
NETDETECT/GPIO14
WOL_EN/GPIO9
MISC
MISC
SMbus address D2
These are for backdrive issue.
2
Q26
ICH_SMBDATA(30,33,34) MEM_SDATA (15,16)
4
ICH_SMBDATA
ICH_SMBCLK
3 1
2N7002W-7-F
2N7002W-7-F
+3.3V_RUN
2
3 1
2N7002W-7-F
2N7002W-7-F
5
Q26
Q25
Q25
Place these close to ICH8.
CLK_ICH_48M
R235
R235 *10_NC
*10_NC
1 2 12
50
50
R524
R524 *10_NC
*10_NC
1 2 12
50
50
R162 10KR162 10K R526 100KR526 100K R152 10KR152 10K R167 10KR167 10K R198 1MR198 1M
R170 10KR170 10K
12
1 2
12 12 12
12
Non-iAMT
CLK_ICH_14M
ICH_PWRGD DPRSLPVR ICH_RSMRST# RSV_ICH_LAN_RST# ICH_CL_PWROK
RSV_GPIO10
DIS:ALW UMA:SUS
Non-iAMT
CL_VREF0/1 ~=0.405V
Title
Title
Title
ICH9-M(PM,GPIO,SMB)
ICH9-M(PM,GPIO,SMB)
ICH9-M(PM,GPIO,SMB)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
RM3 3A
RM3 3A
RM3 3A
Date: Sheet
Date: Sheet
Date: Sheet
+3.3V_RUN
R136
R136
3.24K/F
3.24K/F
1 2
CL_VREF0
C179
C179
0.1U
0.1U
12
R137
R137 453/F
453/F
12
10
10
QUANTA
QUANTA
QUANTA COMPUTER
7
1 2
12
10
10
R469
R469 *3.24K/F_NC
*3.24K/F_NC
CL_VREF1
C249
C249 *0.1U_NC
*0.1U_NC
C348
C348 *4.7P_NC
*4.7P_NC
C689
C689 *4.7P_NC
*4.7P_NC
+3.3V_SUS
+3.3V_SUS+3.3V_ALW
R471
R471 *3.24K/F_NC
*3.24K/F_NC
1 2
12
R169
R169 *453/F_NC
*453/F_NC
13 60Wednesday, May 06, 2009
13 60Wednesday, May 06, 2009
13 60Wednesday, May 06, 2009
8
of
of
of
1
U34E
U34E
AA26
VSS[001]
AA27
VSS[002]
AA3
VSS[003]
AA6
VSS[004]
AB1
VSS[005]
AA23
VSS[006]
AB28
VSS[007]
AB29
VSS[008]
AB4
VSS[009]
AB5
VSS[010]
AC17
VSS[011]
AC26
VSS[012]
A A
B B
C C
D D
AC27
AC3
AD1 AD10 AD12 AD13 AD14 AD17 AD18 AD21 AD28 AD29
AD4
AD5
AD6
AD7
AD9 AE12 AE13 AE14 AE16 AE17
AE2 AE20 AE24
AE3
AE4
AE6
AE9 AF13 AF16 AF18 AF22 AH26 AF26 AF27
AF5
AF7
AF9 AG13 AG16 AG18 AG20 AG23
AG3
AG6
AG9 AH12 AH14 AH17 AH19
AH2 AH22 AH25 AH28
AH5
AH8 AJ12 AJ14 AJ17
AJ8 B11 B14 B17
B20 B23
C26 C27 E11 E14 E18
E21 E24
F16
F28
F29 G12 G14 G18 G21 G24 G26 G27
H23 H28 H29
G8 H2
VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076]
B2
VSS[077] VSS[078] VSS[079]
B5
VSS[080]
B8
VSS[081] VSS[082] VSS[083] VSS[084] VSS[085] VSS[086]
E2
VSS[087] VSS[088] VSS[089]
E5
VSS[090]
E8
VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106]
ICH9M_verA3
ICH9M_verA3
1
VSS_NCTF[01] VSS_NCTF[02] VSS_NCTF[03] VSS_NCTF[04] VSS_NCTF[05] VSS_NCTF[06] VSS_NCTF[07] VSS_NCTF[08] VSS_NCTF[09] VSS_NCTF[10] VSS_NCTF[11] VSS_NCTF[12]
VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198]
H5 J23 J26 J27 AC22 K28 K29 L13 L15 L2 L26 L27 L5 L7 M12 M13 M14 M15 M16 M17 M23 M28 M29 N11 N12 N13 N14 N15 N16 N17 N18 N26 N27 P12 P13 P14 P15 P16 P17 P2 P23 P28 P29 P4 P7 R11 R12 R13 R14 R15 R16 R17 R18 R28 T12 T13 T14 T15 T16 T17 T23 B26 U12 U13 U14 U15 U16 U17 AD23 U26 U27 U3 V1 V13 V15 V23 V28 V29 V4 V5 W26 W27 W3 Y1 Y28 Y29 Y4 Y5 AG28 AH6 AF2 B25
A1 A2 A28 A29 AH1 AH29 AJ1 AJ2 AJ28 AJ29 B1 B29
2
+RTC_CELL
R501 100R501 100
+1.5V_RUN
1 2
D28
D28
2 1
SDMK0340L-7-F
SDMK0340L-7-F
R535 10R535 10
1 2
D29
D29
2 1
SDMK0340L-7-F
SDMK0340L-7-F
L69
L69 BLM21PG331SN1D
BLM21PG331SN1D
805
805
+5V_RUN
+3.3V_RUN
Non-iAMT
+5V_SUS
+3.3V_SUS
646mA
12
+
+
+1.5V_RUN
12
Non-iAMT
Place C625 close to A27.
+1.5V_RUN
C196
C196
0.1U
0.1U
1 2
10
10
Scott_0226:change C196 to 3300p for EMC concern.
2
12
C606
C606 220U
220U
4
4 7343
7343
L24
L24 10uH
10uH
10uH+-20%_100mA
+VCCSATPLL
C239
C239 1U
1U
10
10 603
603
C605
C605 22U
22U
10
10 1206
1206
805
805
47mA
12
C251
C251 10U
10U
6.3
6.3 603
603
3
12
C199
C199
C228
C228
1U
1U
0.1U
0.1U
1 2
1 2
603
603
10
10
10
10
+ICH_V5REF_RUN
12
C672
C672
2mA
1U
1U
603
603 10
10
+ICH_V5REF_SUS
2mA
C694
C694
0.1U
0.1U
1 2
10
10
FB_330ohm+-25%_100mHz_
1.5A_0.09 ohm DC
+1.5V_PCIE_ICH
12
C604
C604 22U
22U
10
10 1206
1206
C607
C607
2.2U
2.2U
1 2
10
10 805
805
+1.5V_RUN
+1.5V_RUN
VCC1_5_A TOTAL 1.342A
+1.5V_RUN
Non-iAMT
+3.3V_RUN
+1.5V_PCIE_ICH
3
1 2
C278
C278
0.1U
0.1U
10
10
T142PADT142PAD T141PADT141PAD
11mA
+1.5V_RUN
C299
C299
0.1U
0.1U
1 2
10
10
12
C191
C191
4.7U
4.7U
6.3
6.3 603
603
C620
C620
0.1U
0.1U
10
10
+VCCSATPLL
12
C263
C263 1U
1U
10
10 603
603
12
C283
C283 1U
1U
10
10 603
603
C311
C311
0.1U
0.1U
1 2
10
10
TP_VCCSUSLAN1 TP_VCCSUSLAN2
19mA
+1.5V_RUN
23mA
80mA
+3.3V_RUN
1mA
4
4
AA24 AA25 AB24 AB25 AC24 AC25 AD24 AD25 AE25 AE26 AE27 AE28 AE29
AJ19
AC16 AD15 AD16 AE15 AF15
AG15
AH15
AJ15
AC11 AD11 AE11
AF11 AG10 AG11
AH10
AJ10
AC18
AC19
AC21
AC12
AC13
AC14
AE1
G25 H24 H25
M24 M25 N23 N24 N25
R24 R25 R26 R27
U24 U25
U23 W24 W25
AC9
G10
AA7 AB6 AB7 AC6 AC7
D28 D29
A23
A6
F25
J24 J25 K24 K25 L23 L24 L25
P24 P25
T24 T27 T28 T29
V24 V25
K23 Y24 Y25
G9
AJ5
A10 A11
A12 B12
A27
E26 E27
A26
U34F
U34F
ICH9M_verA3
ICH9M_verA3
VCCRTC V5REF V5REF_SUS VCC1_5_B[01]
VCC1_5_B[02] VCC1_5_B[03] VCC1_5_B[04] VCC1_5_B[05] VCC1_5_B[06] VCC1_5_B[07] VCC1_5_B[08] VCC1_5_B[09] VCC1_5_B[10] VCC1_5_B[11] VCC1_5_B[12] VCC1_5_B[13] VCC1_5_B[14] VCC1_5_B[15] VCC1_5_B[16] VCC1_5_B[17] VCC1_5_B[18] VCC1_5_B[19] VCC1_5_B[20] VCC1_5_B[21] VCC1_5_B[22] VCC1_5_B[23] VCC1_5_B[24] VCC1_5_B[25] VCC1_5_B[26] VCC1_5_B[27] VCC1_5_B[28] VCC1_5_B[29] VCC1_5_B[30] VCC1_5_B[31] VCC1_5_B[32] VCC1_5_B[33] VCC1_5_B[34] VCC1_5_B[35] VCC1_5_B[36] VCC1_5_B[37] VCC1_5_B[38] VCC1_5_B[39] VCC1_5_B[40] VCC1_5_B[41] VCC1_5_B[42] VCC1_5_B[43] VCC1_5_B[44] VCC1_5_B[45] VCC1_5_B[46] VCC1_5_B[47] VCC1_5_B[48] VCC1_5_B[49]
VCCSATAPLL VCC1_5_A[01]
VCC1_5_A[02] VCC1_5_A[03] VCC1_5_A[04] VCC1_5_A[05] VCC1_5_A[06] VCC1_5_A[07] VCC1_5_A[08]
VCC1_5_A[09] VCC1_5_A[10] VCC1_5_A[11] VCC1_5_A[12] VCC1_5_A[13] VCC1_5_A[14] VCC1_5_A[15] VCC1_5_A[16]
VCC1_5_A[17] VCC1_5_A[18]
VCC1_5_A[19] VCC1_5_A[20] VCC1_5_A[21]
VCC1_5_A[22] VCC1_5_A[23]
VCC1_5_A[24] VCC1_5_A[25]
VCCUSBPLL VCC1_5_A[26]
VCC1_5_A[27] VCC1_5_A[28] VCC1_5_A[29] VCC1_5_A[30]
VCCLAN1_05[1] VCCLAN1_05[2]
VCCLAN3_3[1] VCCLAN3_3[2]
VCCGLANPLL VCCGLAN1_5[1]
VCCGLAN1_5[2] VCCGLAN1_5[3] VCCGLAN1_5[4]
VCCGLAN3_3
VCC1_05[01] VCC1_05[02] VCC1_05[03] VCC1_05[04] VCC1_05[05] VCC1_05[06] VCC1_05[07] VCC1_05[08] VCC1_05[09] VCC1_05[10] VCC1_05[11] VCC1_05[12] VCC1_05[13] VCC1_05[14] VCC1_05[15] VCC1_05[16]
CORE
CORE
VCC1_05[17] VCC1_05[18] VCC1_05[19] VCC1_05[20] VCC1_05[21] VCC1_05[22] VCC1_05[23] VCC1_05[24] VCC1_05[25] VCC1_05[26]
VCCA3GP ATXARX USB CORE
VCCA3GP ATXARX USB CORE
VCCDMIPLL
V_CPU_IO[1] V_CPU_IO[2]
VCCP_COREVCCPSUSVCCPUSB
VCCP_COREVCCPSUSVCCPUSB
PCI
PCI
VCCSUSHDA
VCCSUS1_05[1] VCCSUS1_05[2]
VCCSUS1_5[1] VCCSUS1_5[2]
VCCSUS3_3[01] VCCSUS3_3[02] VCCSUS3_3[03] VCCSUS3_3[04]
VCCSUS3_3[05]
VCCSUS3_3[06] VCCSUS3_3[07] VCCSUS3_3[08] VCCSUS3_3[09] VCCSUS3_3[10] VCCSUS3_3[11] VCCSUS3_3[12] VCCSUS3_3[13] VCCSUS3_3[14] VCCSUS3_3[15] VCCSUS3_3[16] VCCSUS3_3[17] VCCSUS3_3[18] VCCSUS3_3[19] VCCSUS3_3[20]
VCCCL3_3[1] VCCCL3_3[2]
GLAN POWER
GLAN POWER
VCC_DMI[1] VCC_DMI[2]
VCC3_3[01] VCC3_3[02] VCC3_3[07] VCC3_3[03]
VCC3_3[04] VCC3_3[05] VCC3_3[06]
VCC3_3[08] VCC3_3[09] VCC3_3[10] VCC3_3[11] VCC3_3[12] VCC3_3[13] VCC3_3[14]
VCCHDA
VCCCL1_05
VCCCL1_5
5
A15 B15 C15 D15 E15 F15 L11 L12 L14 L16 L17 L18 M11 M18 P11 P18 T11 T18 U11 U18 V11 V12 V14 V16 V17 V18
23mA
R29
48mA
W23 Y23
2mA
AB23 AC23
VCC3_3 308mA
AG29 AJ6 AC10 AD19
AF20 AG24 AC20
B9 F9 G3 G6 J2 J7 K7
AJ4 AJ3
TP_VCCSUS1.05_1
AC8
TP_VCCSUS1.05_2TP_VCCSUS1.05_2
F17
TP_VCCSUS1.5_1
AD8
TP_VCCSUS1.5_2
F18
A18 D16 D17 E22
AF1
VCCSUS 3_3 212mA
T1 T2 T3 T4 T5 T6 U6 U7 V6 V7 W6 W7 Y6 Y7 T7
+VCCCL1_05
G22
+VCCCL1_5
G23
A24 B24
19mA
5
6
+1.05V_VCCP
C293
C273
C273
0.1U
0.1U
1 2
10
10
C293
0.1U
0.1U
1 2
10
10
1uH+-30%_60mA
+1.5V_DMIPLL
C173
C173
0.01U
0.01U
1 2
25
25
+VCC_DMI_ICH
C302
C238
C238
0.1U
0.1U
1 2
10
10
C334
C334
0.1U
0.1U
1 2
10
10
C302
0.1U
0.1U
1 2
10
10
C319
C319
0.1U
0.1U
1 2
10
10
C304
C304
0.1U
0.1U
1 2
10
10
C326
C326
0.1U
0.1U
1 2
10
10
12
+3.3V_RUN
11mA 11mA
T73PAD T73PAD T57PAD T57PAD
T74PAD T74PAD
1 2
C256 0.1U
C256 0.1U
10
10
12
C344
C344
0.022U/16V
0.022U/16V
WWAN Noise - ICH improvements
12
12
C318
C318 *0.1U_NC
*0.1U_NC
10
10
+3.3V_RUN
Non-iAMT
C323
C323 *0.1U_NC
*0.1U_NC
10
10
12
C321
C321 *0.1U_NC
*0.1U_NC
10
10
C220
C220
0.1U
0.1U
10
10
1 2
6
7
+1.05V_VCCP +1.5V_RUN
C168
C168 10U
10U
1 2
6.3
6.3 603
603
C233
C233 22U/4V/0805
22U/4V/0805
+3.3V_SUS
12
L15
L15 1uH
1uH
+1.5V_DMIPLL_R
12
L21
L21 BLM21PG331SN1D
BLM21PG331SN1D
805
805
1 2
+3.3V_RUN
12
C693
C693
0.1U
0.1U
10
10
C330
C330
0.022U/16V
0.022U/16V
D27
D27
1
2
BAT54C T/R
BAT54C T/R
C257
C257
0.1U
0.1U
10
10
12
C324
C324
0.1U
0.1U
10
10
+3.3V_SUS
12
C316
C316
0.1U
0.1U
10
10
R459
R459
3
1 2
10
10
805
805
R133 1R133 1
+1.05V_VCCP
C276
C276
0.1U
0.1U
1 2
10
10
+1.5V_RUN
12
12
C237
C237
4.7U
4.7U
603
603
6.3
6.3
RESERVE 1.5V_SUS FOR VCCSUSHDA
12
C313
C313 *0.1U_NC
*0.1U_NC
10
10
C219
C219 *1U_NC
*1U_NC
10
10 603
603
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
+3.3V_SUS
12
C320
C320
0.1U
0.1U
10
10
C347
C347 *1U/6.3V_NC
*1U/6.3V_NC
12
C231
C231
0.1U
0.1U
10
10
QUANTA
QUANTA
QUANTA COMPUTER
ICH9-M(POWER,GND)
ICH9-M(POWER,GND)
ICH9-M(POWER,GND)
RM3 3A
RM3 3A
RM3 3A
7
8
+1.05V_VCCP
WWAN Noise - ICH improvements
C258
C258 *0.1U_NC
*0.1U_NC
U4
U4
VIN3VOUT
1
SHDN
2
GND
*G913C_NC
*G913C_NC
10
10
12
C180
C180 *0.1U_NC
*0.1U_NC
SET
12
10
10
4
R1
5
R2
12
10
10
+3.3V_RUN
C337
C337 *0.1U_NC
*0.1U_NC
R240
R240
*22.1K/F_NC
*22.1K/F_NC
*4.7U/6.3V_NC
*4.7U/6.3V_NC
R245
R245 *100K/F_NC
*100K/F_NC
14 60Wednesday, May 06, 2009
14 60Wednesday, May 06, 2009
14 60Wednesday, May 06, 2009
8
C350
C350
of
of
of
12
10
10
+1.5V_SUS
C194
C194 *0.1U_NC
*0.1U_NC
1
2
3
4
5
6
7
8
+3.3V_RUN
+1.5V_DDR
CN23B
CN23A
CN23A
DDR-AS0A62X-U4RN-7F-204P
A A
DDR_A_MA[0..14](7)
DDR_A_BS0(7) DDR_A_BS1(7) DDR_A_BS2(7)
DDR_A_RAS#(7) DDR_A_CAS#(7) DDR_A_WE#(7)
B B
DDR_CS0_DIMMA#(6) DDR_CS1_DIMMA#(6)
M_ODT0(6) M_ODT1(6)
M_CLK_DDR1(6) M_CLK_DDR#1(6) M_CLK_DDR0(6) M_CLK_DDR#0(6)
DDR_CKE0_DIMMA(6) DDR_CKE1_DIMMA(6)
DDR_A_DM[0..7](7)
C C
DDR_A_DQS[0..7](7) DDR_A_DQS#[0..7](7)
MEM_SDATA(13,16)
MEM_SCLK(13,16)
DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14
M_CLK_DDR1 M_CLK_DDR#1 M_CLK_DDR0 M_CLK_DDR#0
DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7
DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS7 DDR_A_DQS#7
MEM_SDATA MEM_SCLK
SM_MEM BUS ADDRESS SO-DIMM0 1010 000 SO-DIMM1 1010 010
DDR-AS0A62X-U4RN-7F-204P
SO_DIMM204_DDR3
SO_DIMM204_DDR3
98
A0
A0
97
A1
A1
96
A2
A2
95
A3
A3
92
A4
A4
91
A5
A5
90
A6
A6
86
A7
A7
89
A8
A8
85
A9
A9
107
A10/AP
A10/AP
84
A11
A11
83
A12/BC*
A12/BC*
119
A13
A13
80
A14
A14
78
A15
A15
109
BA0
BA0
108
BA1
BA1
79
BA2
BA2
110
RAS*
RAS*
115
CAS*
CAS*
113
WE*
WE*
114
S0*
S0*
121
S1*
S1*
116
ODT0
ODT0
120
ODT1
ODT1
101
CK0
CK0
103
CK0*
CK0*
102
CK1
CK1
104
CK1*
CK1*
73
CKE0 DQ41
CKE0 DQ41
74
CKE1
CKE1
11
DM0
DM0
28
DM1
DM1
46
DM2
DM2
63
DM3
DM3
136
DM4
DM4
153
DM5
DM5
170
DM6
DM6
187
DM7
DM7
12
DQS0
DQS0
10
DQS0*
DQS0*
29
DQS1
DQS1
27
DQS1*
DQS1*
47
DQS2
DQS2
45
DQS2*
DQS2*
64
DQS3
DQS3
62
DQS3*
DQS3*
137
DQS4
DQS4
135
DQS4*
DQS4*
154
DQS5
DQS5
152
DQS5*
DQS5*
171
DQS6
DQS6
169
DQS6*
DQS6*
188
DQS7
DQS7
186
DQS7*
DQS7*
200
SDA
SDA
202
SCL
SCL
197
SA0
SA0
201
SA1
SA1
SO_DIMM204_DDR3
SO_DIMM204_DDR3
EVENT*
EVENT*
RESET*
RESET*
DQ10
DQ10 DQ11
DQ11 DQ12
DQ12 DQ13
DQ13 DQ14
DQ14 DQ15
DQ15 DQ16
DQ16 DQ17
DQ17 DQ18
DQ18 DQ19
DQ19 DQ20
DQ20 DQ21
DQ21 DQ22
DQ22 DQ23
DQ23 DQ24
DQ24 DQ25
DQ25 DQ26
DQ26 DQ27
DQ27 DQ28
DQ28 DQ29
DQ29 DQ30
DQ30 DQ31
DQ31 DQ32
DQ32 DQ33
DQ33 DQ34
DQ34 DQ35
DQ35 DQ36
DQ36 DQ37
DQ37 DQ38
DQ38 DQ39
DQ39 DQ40
DQ40
DQ42
DQ42 DQ43
DQ43 DQ44
DQ44 DQ45
DQ45 DQ46
DQ46 DQ47
DQ47 DQ48
DQ48 DQ49
DQ49 DQ50
DQ50 DQ51
DQ51 DQ52
DQ52 DQ53
DQ53 DQ54
DQ54 DQ55
DQ55 DQ56
DQ56 DQ57
DQ57 DQ58
DQ58 DQ59
DQ59 DQ60
DQ60 DQ61
DQ61 DQ62
DQ62 DQ63
DQ63
TEST
TEST
DQ0 DQ1
DQ1 DQ2
DQ2 DQ3
DQ3 DQ4
DQ4 DQ5
DQ5 DQ6
DQ6 DQ7
DQ7 DQ8
DQ8 DQ9
DQ9
7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194
DDR_A_D0 DDR_A_D3 DDR_A_D2 DDR_A_D5 DDR_A_D1 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D15 DDR_A_D14 DDR_A_D21 DDR_A_D16 DDR_A_D23 DDR_A_D18 DDR_A_D17 DDR_A_D20 DDR_A_D22 DDR_A_D19 DDR_A_D24 DDR_A_D25 DDR_A_D30 DDR_A_D31 DDR_A_D28 DDR_A_D29 DDR_A_D26 DDR_A_D27 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D47 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D42 DDR_A_D49 DDR_A_D48 DDR_A_D50 DDR_A_D55 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D51 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 DDR_A_D57 DDR_A_D56 DDR_A_D58 DDR_A_D59
DDR_A_D4
5
DQ0
198
30
125
T43 PADT43 PAD
DDR_A_D[0..63] (7)
PM_EXTTS#0 (6)
DDR3_DRAMRST# (6,16)
+V_DDR_MCH_REF
+0.75V_DDR_VTT
12
C101
C101 10U/10V
10U/10V
CC0805
CC0805
12
C106
C106
0.1U/10V
0.1U/10V
12
C157
C157
0.1U/10V
0.1U/10V
12
C102
C102
0.1U/10V
0.1U/10V
+1.5V_DDR
+1.5V_DDR
12
C162
C162
4.7U/6.3V
4.7U/6.3V
CC0603
CC0603
12
C170
C170 10U/10V
10U/10V
CC0805
CC0805
CN23B
DDR-AS0A62X-U4RN-7F-204P
DDR-AS0A62X-U4RN-7F-204P
SO_DIMM204_DDR3
SO_DIMM204_DDR3
199
VDDSPD
VDDSPD
1
VREFDQ
VREFDQ
126
VREFCA
VREFCA
77
NC
NC
122
NC
NC
203
VTT
VTT
204
VTT
VTT
2
VSS
VSS
3
VSS
VSS
8
VSS
VSS
9
VSS
VSS
13
VSS
VSS
14
VSS
VSS
19
VSS
VSS
20
VSS
VSS
25
VSS
VSS
26
VSS
VSS
31
VSS
VSS
32
VSS
VSS
37
VSS
VSS
38
VSS
VSS
43
VSS
VSS
44
VSS
VSS
48
VSS
VSS
49
VSS
VSS
54
VSS
VSS
55
VSS
VSS
60
VSS
VSS
61
VSS
VSS
65
VSS
VSS
66
VSS
VSS
71
VSS
VSS
72
VSS
VSS
127
VSS
VSS
128
VSS
VSS
133
VSS
VSS
134
VSS
VSS
SO_DIMM204_DDR3
SO_DIMM204_DDR3
12
C255
C255
4.7U/6.3V
4.7U/6.3V
CC0603
CC0603
12
C184
C184
0.1U/10V
0.1U/10V
12
C197
C197 1U/10V
1U/10V
CC0603
CC0603
12
C226
C226
0.1U/10V
0.1U/10V
VDD
VDD VDD
VDD VDD
VDD VDD
VDD VDD
VDD VDD
VDD VDD
VDD VDD
VDD VDD
VDD VDD
VDD VDD
VDD VDD
VDD VDD
VDD VDD
VDD VDD
VDD VDD
VDD VDD
VDD VDD
VDD
VSS
VSS VSS
VSS VSS
VSS VSS
VSS VSS
VSS VSS
VSS VSS
VSS VSS
VSS VSS
VSS VSS
VSS VSS
VSS VSS
VSS VSS
VSS VSS
VSS VSS
VSS VSS
VSS VSS
VSS VSS
VSS VSS
VSS VSS
VSS VSS
VSS VSS
VSS
12
C183
C183 1U/10V
1U/10V
CC0603
CC0603
12
C229
C229
0.1U/10V
0.1U/10V
75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124
138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196
12
12
C252
C252 1U/10V
1U/10V
CC0603
CC0603
C166
C166
0.1U/10V
0.1U/10V
12
+
+
C640
C640 *330U/6.3V_NC
*330U/6.3V_NC
CC7343
CC7343
D D
For EMI Reserved
M_CLK_DDR1 M_CLK_DDR0
1
R144 *200/F_NCR144 *200/F_NC
1 2
R143 *200/F_NCR143 *200/F_NC
1 2
2
M_CLK_DDR#1 M_CLK_DDR#0
Place ESD Protection diodes.
ESD1
MEM_SDATA MEM_SCLK
3
ESD1
1
1
2
2 334
*RCLAMP0504S.TCT_NC
*RCLAMP0504S.TCT_NC
6
6
5
5
4
+3.3V_RUN
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
4
5
6
Date: Sheet
QUANTA
QUANTA
QUANTA COMPUTER
DDR3 SO-DIMM1 (204P)
DDR3 SO-DIMM1 (204P)
DDR3 SO-DIMM1 (204P)
RM3 3A
RM3 3A
RM3 3A
7
15 60Wednesday, May 06, 2009
15 60Wednesday, May 06, 2009
15 60Wednesday, May 06, 2009
of
of
of
8
1
2
3
4
5
6
7
8
+3.3V_RUN
+1.5V_DDR
CN22B
CN22A
CN22A
DDR-AS0A62X-U8RN-7F-204P
A A
DDR_B_MA[0..14](7)
DDR_B_BS0(7) DDR_B_BS1(7) DDR_B_BS2(7)
DDR_B_RAS#(7) DDR_B_CAS#(7) DDR_B_WE#(7)
B B
DDR_CS2_DIMMB#(6) DDR_CS3_DIMMB#(6)
M_ODT2(6) M_ODT3(6)
M_CLK_DDR4(6) M_CLK_DDR#4(6) M_CLK_DDR3(6) M_CLK_DDR#3(6)
DDR_CKE3_DIMMB(6) DDR_CKE4_DIMMB(6)
DDR_B_DM[0..7](7)
C C
DDR_B_DQS[0..7](7) DDR_B_DQS#[0..7](7)
MEM_SDATA(13,15)
MEM_SCLK(13,15)
DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14
M_CLK_DDR4 M_CLK_DDR#4 M_CLK_DDR3 M_CLK_DDR#3
DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7
DDR_B_DQS0 DDR_B_DQS#0 DDR_B_DQS1 DDR_B_DQS#1 DDR_B_DQS2 DDR_B_DQS#2 DDR_B_DQS3 DDR_B_DQS#3 DDR_B_DQS4 DDR_B_DQS#4 DDR_B_DQS5 DDR_B_DQS#5 DDR_B_DQS6 DDR_B_DQS#6 DDR_B_DQS7 DDR_B_DQS#7
+3.3V_RUN
D D
1
2
DDR-AS0A62X-U8RN-7F-204P
SO_DIMM204_DDR3
SO_DIMM204_DDR3
98
A0
A0
97
A1
A1
96
A2
A2
95
A3
A3
92
A4
A4
91
A5
A5
90
A6
A6
86
A7
A7
89
A8
A8
85
A9
A9
107
A10/AP
A10/AP
84
A11
A11
83
A12/BC*
A12/BC*
119
A13
A13
80
A14
A14
78
A15
A15
109
BA0
BA0
108
BA1
BA1
79
BA2
BA2
110
RAS*
RAS*
115
CAS*
CAS*
113
WE*
WE*
114
S0*
S0*
121
S1*
S1*
116
ODT0
ODT0
120
ODT1
ODT1
101
CK0
CK0
103
CK0*
CK0*
102
CK1
CK1
104
CK1*
CK1*
73
CKE0 DQ41
CKE0 DQ41
74
CKE1
CKE1
11
DM0
DM0
28
DM1
DM1
46
DM2
DM2
63
DM3
DM3
136
DM4
DM4
153
DM5
DM5
170
DM6
DM6
187
DM7
DM7
12
DQS0
DQS0
10
DQS0*
DQS0*
29
DQS1
DQS1
27
DQS1*
DQS1*
47
DQS2
DQS2
45
DQS2*
DQS2*
64
DQS3
DQS3
62
DQS3*
DQS3*
137
DQS4
DQS4
135
DQS4*
DQS4*
154
DQS5
DQS5
152
DQS5*
DQS5*
171
DQS6
DQS6
169
DQS6*
DQS6*
188
DQS7
DQS7
186
DQS7*
DQS7*
200
SDA
SDA
202
SCL
SCL
197
SA0
SA0
201
SA1
SA1
SO_DIMM204_DDR3
SO_DIMM204_DDR3
For EMI Reserved
M_CLK_DDR4 M_CLK_DDR3
R138 *200/F_NCR138 *200/F_NC R142 *200/F_NCR142 *200/F_NC
1 2 1 2
3
EVENT*
EVENT*
RESET*
RESET*
DQ10
DQ10 DQ11
DQ11 DQ12
DQ12 DQ13
DQ13 DQ14
DQ14 DQ15
DQ15 DQ16
DQ16 DQ17
DQ17 DQ18
DQ18 DQ19
DQ19 DQ20
DQ20 DQ21
DQ21 DQ22
DQ22 DQ23
DQ23 DQ24
DQ24 DQ25
DQ25 DQ26
DQ26 DQ27
DQ27 DQ28
DQ28 DQ29
DQ29 DQ30
DQ30 DQ31
DQ31 DQ32
DQ32 DQ33
DQ33 DQ34
DQ34 DQ35
DQ35 DQ36
DQ36 DQ37
DQ37 DQ38
DQ38 DQ39
DQ39 DQ40
DQ40
DQ42
DQ42 DQ43
DQ43 DQ44
DQ44 DQ45
DQ45 DQ46
DQ46 DQ47
DQ47 DQ48
DQ48 DQ49
DQ49 DQ50
DQ50 DQ51
DQ51 DQ52
DQ52 DQ53
DQ53 DQ54
DQ54 DQ55
DQ55 DQ56
DQ56 DQ57
DQ57 DQ58
DQ58 DQ59
DQ59 DQ60
DQ60 DQ61
DQ61 DQ62
DQ62 DQ63
DQ63
TEST
TEST
DQ0
DQ0 DQ1
DQ1 DQ2
DQ2 DQ3
DQ3 DQ4
DQ4 DQ5
DQ5 DQ6
DQ6 DQ7
DQ7 DQ8
DQ8 DQ9
DQ9
M_CLK_DDR#4 M_CLK_DDR#3
5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194
198
30
125
DDR_B_D4 DDR_B_D5 DDR_B_D2 DDR_B_D7 DDR_B_D1 DDR_B_D0 DDR_B_D6 DDR_B_D3 DDR_B_D13 DDR_B_D12 DDR_B_D15 DDR_B_D14 DDR_B_D9 DDR_B_D8 DDR_B_D11 DDR_B_D10 DDR_B_D19 DDR_B_D16 DDR_B_D22 DDR_B_D23 DDR_B_D17 DDR_B_D20 DDR_B_D21 DDR_B_D18 DDR_B_D24 DDR_B_D25 DDR_B_D30 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D31 DDR_B_D26 DDR_B_D32 DDR_B_D37 DDR_B_D39 DDR_B_D35 DDR_B_D33 DDR_B_D36 DDR_B_D38 DDR_B_D34 DDR_B_D40 DDR_B_D45 DDR_B_D47 DDR_B_D46 DDR_B_D44 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D52 DDR_B_D48 DDR_B_D50 DDR_B_D55 DDR_B_D49 DDR_B_D53 DDR_B_D54 DDR_B_D51 DDR_B_D61 DDR_B_D60 DDR_B_D58 DDR_B_D62 DDR_B_D57 DDR_B_D56 DDR_B_D59 DDR_B_D63
T42 PADT42 PAD
DDR_B_D[0..63] (7)
+V_DDR_MCH_REF
+0.75V_DDR_VTT
12
C95
C95 10U/10V
10U/10V
CC0805
CC0805
PM_EXTTS#1 (6)
DDR3_DRAMRST# (6,15)
+1.5V_DDR
12
C186
C186
0.1U/10V
0.1U/10V
AC Stitch Cap
12
C185
C185
0.1U/10V
0.1U/10V
12
C193
C193
0.1U/10V
0.1U/10V
+1.5V_DDR
C159
C159
0.1U/10V
0.1U/10V
12
12
4
C198
C198
0.1U/10V
0.1U/10V
12
C225
C225
0.1U/10V
0.1U/10V
5
+1.5V_DDR
12
+1.5V_DDR
12
12
C104
C104
0.1U/10V
0.1U/10V
12
C160
C160
0.1U/10V
0.1U/10V
12
C103
C103
0.1U/10V
0.1U/10V
C164
C164
4.7U/6.3V
4.7U/6.3V
CC0603
CC0603
C171
C171 10U/10V
10U/10V
CC0805
CC0805
12
C250
C250
4.7U/6.3V
4.7U/6.3V
CC0603
CC0603
12
C230
C230
0.1U/10V
0.1U/10V
6
CN22B
DDR-AS0A62X-U8RN-7F-204P
DDR-AS0A62X-U8RN-7F-204P
SO_DIMM204_DDR3
SO_DIMM204_DDR3
199
VDDSPD
VDDSPD
1
VREFDQ
VREFDQ
126
VREFCA
VREFCA
77
NC
NC
122
NC
NC
203
VTT
VTT
204
VTT
VTT
2
VSS
VSS
3
VSS
VSS
8
VSS
VSS
9
VSS
VSS
13
VSS
VSS
14
VSS
VSS
19
VSS
VSS
20
VSS
VSS
25
VSS
VSS
26
VSS
VSS
31
VSS
VSS
32
VSS
VSS
37
VSS
VSS
38
VSS
VSS
43
VSS
VSS
44
VSS
VSS
48
VSS
VSS
49
VSS
VSS
54
VSS
VSS
55
VSS
VSS
60
VSS
VSS
61
VSS
VSS
65
VSS
VSS
66
VSS
VSS
71
VSS
VSS
72
VSS
VSS
127
VSS
VSS
128
VSS
VSS
133
VSS
VSS
134
VSS
VSS
SO_DIMM204_DDR3
SO_DIMM204_DDR3
12
C218
C218 1U/10V
1U/10V
CC0603
CC0603
12
C172
C172
0.1U/10V
0.1U/10V
12
C163
C163 1U/10V
1U/10V
CC0603
CC0603
12
C227
C227
0.1U/10V
0.1U/10V
Title
Title
Title
DDR3 SO-DIMM2 (204P)
DDR3 SO-DIMM2 (204P)
DDR3 SO-DIMM2 (204P)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
RM3 3A
RM3 3A
RM3 3A
Date: Sheet
Date: Sheet
Date: Sheet
7
75
VDD
VDD
76
VDD
VDD
81
VDD
VDD
82
VDD
VDD
87
VDD
VDD
88
VDD
VDD
93
VDD
VDD
94
VDD
VDD
99
VDD
VDD
100
VDD
VDD
105
VDD
VDD
106
VDD
VDD
111
VDD
VDD
112
VDD
VDD
117
VDD
VDD
118
VDD
VDD
123
VDD
VDD
124
VDD
VDD
138
VSS
VSS
139
VSS
VSS
144
VSS
VSS
145
VSS
VSS
150
VSS
VSS
151
VSS
VSS
155
VSS
VSS
156
VSS
VSS
161
VSS
VSS
162
VSS
VSS
167
VSS
VSS
168
VSS
VSS
172
VSS
VSS
173
VSS
VSS
178
VSS
VSS
179
VSS
VSS
184
VSS
VSS
185
VSS
VSS
189
VSS
VSS
190
VSS
VSS
195
VSS
VSS
196
VSS
VSS
12
C253
C253 1U/10V
1U/10V
CC0603
CC0603
12
C192
C192
0.1U/10V
0.1U/10V
QUANTA
QUANTA
QUANTA COMPUTER
12
+
+
C619
C619 *330U/6.3V_NC
*330U/6.3V_NC
CC7343
CC7343
16 60Wednesday, May 06, 2009
16 60Wednesday, May 06, 2009
16 60Wednesday, May 06, 2009
of
of
of
8
1
2
3
4
5
6
7
8
Add capacitor pads for improving WWAN.
Y3
Y3
21
14.318MHZ
14.318MHZ
CLK_XTAL_OUTCLK_XTAL_IN
12
C267
C267
0.1U
0.1U
10
10
FSA FSC PCI_SIO PCI_PCCARD PCI_ICH 27M_SEL
SATA_CLKREQ# CLK_3GPLLREQ#
12
C280
C280
0.1U
0.1U
10
10
R230 2.2R230 2.2
1 2
R185 2.2R185 2.2
1 2
R192 2.2R192 2.2
1 2
R191 2.2R191 2.2
1 2
C661
C661 33P
33P
50
50
1 2
R490 475/FR490 475/F R491 475/FR491 475/F
1 2
R492 22R492 22
1 2
R493 22R493 22
1 2
R494 33R494 33 R195 33R195 33 R495 33R495 33
R486 33R486 33 R487 2.2KR487 2.2K
1 2
R497 10KR497 10K
1 2
R498 33R498 33
+CK_VDD_MAIN
12
C242
C242
0.1U
0.1U
10
10
+CK_VDD_PCI
+CK_VDD_PLL3
+CK_VDD_48
+CK_VDD_SRC
2
+CK_VDD_PCI +CK_VDD_PLL3
+CK_VDD_48 +CK_VDD_SRC
+CK_VDD_MAIN
SATA_CLKREQ#_C CLK_3GPLLREQ#_C
PCI_PCCARD
12 12 12
12
12
PCI_SIO
27M_SEL
PCI_ICH
FSA
FSC
CLK_XTAL_OUT
CLK_XTAL_IN
CLK_SDATA
CLK_SCLK
UMA without iAMT
12
12
C243
C243
0.1U
0.1U
10
10
12
12
12
12
C308
C308
0.1U
0.1U
10
10
C281
C281
0.1U
0.1U
10
10
C301
C301
0.1U
0.1U
10
10
C241
C241
0.1U
0.1U
10
10
C274
C274
0.1U
0.1U
10
10
12
1 2
C309
C309
0.1U
0.1U
10
10
12
C295
C295
0.1U
0.1U
10
10
C296
C296
4.7U
4.7U
6.3
6.3 603
603
12
C294
C294
0.1U
0.1U
10
10
3
C657 27P 50C657 27P 50
1 2
C662 *27P_NC 50C662 *27P_NC 50
1 2
C332 *27P_NC 50C332 *27P_NC 50
1 2
C331 *27P_NC 50C331 *27P_NC 50
1 2
C666 *27P_NC 50C666 *27P_NC 50
1 2
C322 *27P_NC 50C322 *27P_NC 50
1 2
A A
C673
C673 33P
33P
50
50
1 2
CLK_LPC_DEBUG FOR DEBUG NEED POP RESISTOR
B B
+3.3V_RUN
14.318MHz
SATA_CLKREQ#(13)
CLK_3GPLLREQ#(6)
CLK_LPC_DEBUG(34) CLK_PCI_PCCARD(28)
CLK_PCI_8512(31)
CLK_PCI_DEBUG(56)
CLK_PCI_ICH(12) CLK_ICH_48M(13) CPU_MCH_BSEL0(3,6)
CPU_MCH_BSEL1(3,6) CPU_MCH_BSEL2(3,6)
CLK_ICH_14M(13) CLK_PWRGD(13)
L36 BLM21PG600SN1D
L36 BLM21PG600SN1D
805
805
120 ohms@100Mhz
C C
L35 BLM21PG600SN1D
L35 BLM21PG600SN1D
805
805
120 ohms@100Mhz
D D
1
C259
C259 *10U_NC
*10U_NC
1 2
6.3
6.3
U36
U36
9
VDD_PCI
4
VDD_REF
23
VDD_PLL3
16
VDD_48
46
VDD_SRC
62
VDD_CPU
19
VDD_IO
27
VDD_IO
33
VDD_IO
43
VDD_IO
52
VDD_IO
56
VDD_IO
15
GND
18
GND
22
GND
26
GND
30
GND
36
GND
49
GND
59
GND
1
GND
8
CR#_A/PCI-0
10
CR_B/PCI-1
11
TME/PCI-2
12
SRC5_EN/PCI-3
13
27M_SEL/PCI-4
14
ITP_EN/PCIF-5#
17
FSA/USB48
64
FSB/TEST_MODE
5
FSC/TEST_SEL/REF
55
RESET#
63
CK_PWRGD/PD#
2
XOUT
3
XIN
6
SDATA
7
SCLK
SLG8SP513V
SLG8SP513V
SMbus address D2
These are for backdrive issue.
CK505
CK505
QFN64
QFN64
SMBDAT1(26,31,39)
SMBCLK1(26,31,39)
4
CPU-0
CPU-0#
CPU-1
CPU-1#
SRC-8/CPU_ITP
SRC-8#/CPU_ITP#
SRC-0/DOT96
SRC-0#/DOT96#
SRC-1/SE1
SRC-1#/SE2
SRC-2/SATA
SRC-2#/SATA#
CR#_C/SRC-3
CR#_D/SRC-3#
SRC-4
SRC-4#
PCI_STOP#/SRC-5
CPU_STOP#/SRC5-5#
SRC-6
SRC-6#
CR#_F/SRC-7
CR#_E/SRC-7#
SRC-9
SRC-9# SRC-10
SRC-10#
CR#_H/SRC-11
CR#_G/SRC-11#
GND
61 60
58 57
54 53
20 21
24 25
28 29
31 32
34 35
45 44
48 47
51 50
37 38
41 42
40 39
65
+3.3V_RUN
RP4
RP4
2.2KX2
2.2KX2
2
3 1
2N7002W-7-F
2N7002W-7-F
+3.3V_RUN
2
3 1
2N7002W-7-F
2N7002W-7-F
CPU_BCLK CPU_BCLK#
MCH_BCLK MCH_BCLK#
CPU_ITP CPU_ITP#
DOT96_SSC DOT96_SSC#
27M_NSS 27M_SS
PCIE_SATA PCIE_SATA#
PCIE_MINI3 PCIE_MINI3#
MCH_3GPLL MCH_3GPLL#
PCIE_EXPCARD PCIE_EXPCARD#
MINI1CLK_REQ#_C MINI1CLK_REQ#
PCIE_MINI2 PCIE_MINI2#
PCIE_ICH PCIE_ICH#
PCIE_LOM PCIE_LOM#
4 2
4 2
4 2
2 4
2 4
2 4
2 4
2 4
4 2
R484 475/FR484 475/F
1 2
R482 475/FR482 475/F
1 2
2 4
2 4
4 2
Non-iAMT 27M_SEL
2
4
1
3
Q28
Q28
CLK_SDATA
Q27
Q27
CLK_SCLK
5
RP19 0RP19 0
3 1
RP18 0RP18 0
3 1
RP16 0RP16 0
3 1
RP20 0RP20 0
1 3
RP17 33RP17 33
1 3
RP15 0RP15 0
1 3
RP13 0RP13 0
1 3
RP12 0RP12 0
1 3
RP8 0RP8 0
3 1
RP11 0RP11 0
1 3
RP9 0RP9 0
1 3
RP10 0RP10 0
3 1
27M_SEL
H_STP_PCI# H_STP_CPU#
CARD_CLK_REQ#CARD_CLK_REQ#_C
+3.3V_RUN
6
1 2
1 2
R202
R202 10K
10K
R213
R213 *10K_NC
*10K_NC
CLK_CPU_BCLK (3) CLK_CPU_BCLK# (3)
CLK_MCH_BCLK (5) CLK_MCH_BCLK# (5)
CLK_PCIE_MINI1 (33) CLK_PCIE_MINI1# (33)
CLK_PCIE_VGA (18) CLK_PCIE_VGA# (18)
CLK_VGA_27M_NSS (19)
CLK_VGA_27M_SS (19)
CLK_PCIE_SATA (11) CLK_PCIE_SATA# (11)
CLK_PCIE_MINI3 (34) CLK_PCIE_MINI3# (34)
CLK_MCH_3GPLL (6) CLK_MCH_3GPLL# (6)
H_STP_PCI# (13) H_STP_CPU# (13)
CLK_PCIE_EXPCARD (30) CLK_PCIE_EXPCARD# (30)
MINI1CLK_REQ# (33) CARD_CLK_REQ# (30)
CLK_PCIE_MINI2 (34) CLK_PCIE_MINI2# (34)
CLK_PCIE_ICH (12) CLK_PCIE_ICH# (12)
CLK_PCIE_LOM (43) CLK_PCIE_LOM# (43)
CLK_3GPLLREQ# SATA_CLKREQ# CARD_CLK_REQ# MINI1CLK_REQ# PCI_PCCARD
PCI_SIO
Mini Card (WLAN)
to ATI VGA
Mini Card (WPAN)
H_STP_PCI# H_STP_CPU#
R474 10KR474 10K R165 10KR165 10K
Mini Card (WWAN)
R500 10KR500 10K R499 10KR499 10K R481 10KR481 10K R483 10KR483 10K R212 *10K_NCR212 *10K_NC
1 2
R214 *10K_NCR214 *10K_NC
1 2
12 12
12 12 12 12
FSC FSB FSA CPU SRC PCI 1 0 0 0 00 1 1 1
27M_SEL (PIN13)
0=UMA 1 = Disc.
GRFX down
PIN20 PIN21 PIN24 PIN25
DOT96T
SRCT0 SRCC0
QUANTA
QUANTA
QUANTA COMPUTER
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
CLOCK GENERATOR
CLOCK GENERATOR
CLOCK GENERATOR
RM3 3A
RM3 3A
RM3 3A
7
1 1
0 1 1
DOT96C
1 10 1 0 0 0 0 1
96/ 100M_T
27Mout
100 133 166 200 266 333 400
RSVD
100 100 100 100 100 100 100 100
27MSSout
17 60Wednesday, May 06, 2009
17 60Wednesday, May 06, 2009
17 60Wednesday, May 06, 2009
8
96/ 100M_C
of
of
of
+3.3V_RUN
+3.3V_RUN
330 33 33 33 33 33 33 33
5
U55A
U55A
PCIE_MTX_GRX_P[0..15](6) PCIE_MTX_GRX_N[0..15](6)
PCIE_MTX_GRX_P0 PCIE_MTX_GRX_N0
D D
C C
B B
CLK_PCIE_VGA(17) CLK_PCIE_VGA#(17)
!!! M97 Only, M97 glitch free GPIO feature. For future ASIC, PWRGOOD not required, should be pulled to GND.
Gur_0131 : add Cap to reserve M97 PWRGOOD timing tune
PLTRST_DELAY#(13)
PLTRST#(6,12,30,31,33,34,43)
PCIE_MTX_GRX_P1 PCIE_MTX_GRX_N1
PCIE_MTX_GRX_P2 PCIE_MTX_GRX_N2
PCIE_MTX_GRX_P3 PCIE_MTX_GRX_N3
PCIE_MTX_GRX_P4 PCIE_MTX_GRX_N4
PCIE_MTX_GRX_P5 PCIE_MTX_GRX_N5
PCIE_MTX_GRX_P6 PCIE_MTX_GRX_N6
PCIE_MTX_GRX_P7 PCIE_MTX_GRX_N7
PCIE_MTX_GRX_P8 PCIE_MTX_GRX_N8
PCIE_MTX_GRX_P9 PCIE_MTX_GRX_N9
PCIE_MTX_GRX_P10 PCIE_MTX_GRX_N10
PCIE_MTX_GRX_P11 PCIE_MTX_GRX_N11
PCIE_MTX_GRX_P12 PCIE_MTX_GRX_N12
PCIE_MTX_GRX_P13 PCIE_MTX_GRX_N13
PCIE_MTX_GRX_P14 PCIE_MTX_GRX_N14
PCIE_MTX_GRX_P15 PCIE_MTX_GRX_N15
R729 *10K_NCR729 *10K_NC C1035 *0.1U_NCC1035 *0.1U_NC
R797 *0_NCR797 *0_NC
12 12
R798 0R798 0
AA38
PCIE_RX0P
Y37
PCIE_RX0N
Y35
PCIE_RX1P
W36
PCIE_RX1N
W38
PCIE_RX2P
V37
PCIE_RX2N
V35
PCIE_RX3P
U36
PCIE_RX3N
U38
PCIE_RX4P
T37
PCIE_RX4N
T35
PCIE_RX5P
R36
PCIE_RX5N
R38
PCIE_RX6P
P37
PCIE_RX6N
P35
PCIE_RX7P
N36
PCIE_RX7N
N38
PCIE_RX8P
M37
PCIE_RX8N
M35
PCIE_RX9P
L36
PCIE_RX9N
L38
PCIE_RX10P
K37
PCIE_RX10N
K35
PCIE_RX11P
J36
PCIE_RX11N
J38
PCIE_RX12P
H37
PCIE_RX12N
H35
PCIE_RX13P
G36
PCIE_RX13N
G38
PCIE_RX14P
F37
PCIE_RX14N
F35
PCIE_RX15P
E37
PCIE_RX15N
CLOCK
CLOCK
AB35
PCIE_REFCLKP
AA36
PCIE_REFCLKN
AJ21
NC#1
AK21
NC#2
AH16
NC_PWRGOOD
AA30
PERSTB
PERST#
Scott_0204:change C1035 from 0603 to 0402 for layout request.
216-0729051(M96-M2 XT)
216-0729051(M96-M2 XT)
4
ASIC PN 100-CK QCI P/N
----------------------------------------------------------------------------------------­M96-M2 XT A13 216-0729051 100-CK3186 AJ072900T08 M97-M2 LP A11 216-0731001 100-CG1806 AJ073100T01
PCIE_MRX_GTX_C_P0
PCIE_TX0P PCIE_TX0N
PCIE_TX1P PCIE_TX1N
PCIE_TX2P PCIE_TX2N
PCIE_TX3P PCIE_TX3N
PCIE_TX4P
PCI EXPRESS INTERFACE
PCI EXPRESS INTERFACE
PCIE_TX4N
PCIE_TX5P PCIE_TX5N
PCIE_TX6P PCIE_TX6N
PCIE_TX7P PCIE_TX7N
PCIE_TX8P PCIE_TX8N
PCIE_TX9P PCIE_TX9N
PCIE_TX10P PCIE_TX10N
PCIE_TX11P PCIE_TX11N
PCIE_TX12P PCIE_TX12N
PCIE_TX13P PCIE_TX13N
PCIE_TX14P PCIE_TX14N
PCIE_TX15P PCIE_TX15N
CALIBRATION
CALIBRATION
PCIE_CALRP PCIE_CALRN
Y33 Y32
W33 W32
U33 U32
U30 U29
T33 T32
T30 T29
P33 P32
P30 P29
N33 N32
N30 N29
L33 L32
L30 L29
K33 K32
J33 J32
K30 K29
H33 H32
Y30 Y29
PCIE_MRX_GTX_C_N0
PCIE_MRX_GTX_C_P1 PCIE_MRX_GTX_C_N1
PCIE_MRX_GTX_C_P2 PCIE_MRX_GTX_C_N2
PCIE_MRX_GTX_C_P3 PCIE_MRX_GTX_C_N3
PCIE_MRX_GTX_C_P4 PCIE_MRX_GTX_C_N4
PCIE_MRX_GTX_C_P5 PCIE_MRX_GTX_C_N5
PCIE_MRX_GTX_C_P6 PCIE_MRX_GTX_C_N6
PCIE_MRX_GTX_C_P7 PCIE_MRX_GTX_C_N7
PCIE_MRX_GTX_C_P8 PCIE_MRX_GTX_C_N8
PCIE_MRX_GTX_C_P9 PCIE_MRX_GTX_C_N9
PCIE_MRX_GTX_C_P10 PCIE_MRX_GTX_C_N10
PCIE_MRX_GTX_C_P11 PCIE_MRX_GTX_C_N11
PCIE_MRX_GTX_C_P12 PCIE_MRX_GTX_C_N12
PCIE_MRX_GTX_C_P13 PCIE_MRX_GTX_C_N13
PCIE_MRX_GTX_C_P14 PCIE_MRX_GTX_C_N14
PCIE_MRX_GTX_C_P15 PCIE_MRX_GTX_C_N15
R168 1.27KR168 1.27K R238 2K/FR238 2K/F
3
PCIE_MRX_GTX_C_P0 PCIE_MRX_GTX_C_P1 PCIE_MRX_GTX_C_P2 PCIE_MRX_GTX_C_P3 PCIE_MRX_GTX_C_P4 PCIE_MRX_GTX_C_P5 PCIE_MRX_GTX_C_P6 PCIE_MRX_GTX_C_P7 PCIE_MRX_GTX_C_P8 PCIE_MRX_GTX_C_P9 PCIE_MRX_GTX_C_P10 PCIE_MRX_GTX_C_P11 PCIE_MRX_GTX_C_P12 PCIE_MRX_GTX_C_P13 PCIE_MRX_GTX_C_P14 PCIE_MRX_GTX_C_P15 PCIE_MRX_GTX_C_N0 PCIE_MRX_GTX_C_N1 PCIE_MRX_GTX_C_N2 PCIE_MRX_GTX_C_N3 PCIE_MRX_GTX_C_N4 PCIE_MRX_GTX_C_N5 PCIE_MRX_GTX_C_N6 PCIE_MRX_GTX_C_N7 PCIE_MRX_GTX_C_N8 PCIE_MRX_GTX_C_N9 PCIE_MRX_GTX_C_N10 PCIE_MRX_GTX_C_N11 PCIE_MRX_GTX_C_N12 PCIE_MRX_GTX_C_N13 PCIE_MRX_GTX_C_N14 PCIE_MRX_GTX_C_N15
+PCIE_VDDC+1.8V_RUN
C638 0.1UC638 0.1U C650 0.1UC650 0.1U C644 0.1UC644 0.1U C653 0.1UC653 0.1U C643 0.1UC643 0.1U C649 0.1UC649 0.1U C665 0.1UC665 0.1U C668 0.1UC668 0.1U C654 0.1UC654 0.1U C679 0.1UC679 0.1U C639 0.1UC639 0.1U C674 0.1UC674 0.1U C669 0.1UC669 0.1U C683 0.1UC683 0.1U C671 0.1UC671 0.1U C677 0.1UC677 0.1U C641 0.1UC641 0.1U C648 0.1UC648 0.1U C645 0.1UC645 0.1U C656 0.1UC656 0.1U C642 0.1UC642 0.1U C646 0.1UC646 0.1U C660 0.1UC660 0.1U C663 0.1UC663 0.1U C652 0.1UC652 0.1U C675 0.1UC675 0.1U C637 0.1UC637 0.1U C678 0.1UC678 0.1U C664 0.1UC664 0.1U C682 0.1UC682 0.1U C667 0.1UC667 0.1U C680 0.1UC680 0.1U
PCIE_MRX_GTX_P0 PCIE_MRX_GTX_P1 PCIE_MRX_GTX_P2 PCIE_MRX_GTX_P3 PCIE_MRX_GTX_P4 PCIE_MRX_GTX_P5 PCIE_MRX_GTX_P6 PCIE_MRX_GTX_P7 PCIE_MRX_GTX_P8 PCIE_MRX_GTX_P9 PCIE_MRX_GTX_P10 PCIE_MRX_GTX_P11 PCIE_MRX_GTX_P12 PCIE_MRX_GTX_P13 PCIE_MRX_GTX_P14 PCIE_MRX_GTX_P15 PCIE_MRX_GTX_N0 PCIE_MRX_GTX_N1 PCIE_MRX_GTX_N2 PCIE_MRX_GTX_N3 PCIE_MRX_GTX_N4 PCIE_MRX_GTX_N5 PCIE_MRX_GTX_N6 PCIE_MRX_GTX_N7 PCIE_MRX_GTX_N8 PCIE_MRX_GTX_N9 PCIE_MRX_GTX_N10 PCIE_MRX_GTX_N11 PCIE_MRX_GTX_N12 PCIE_MRX_GTX_N13 PCIE_MRX_GTX_N14 PCIE_MRX_GTX_N15
2
PCIE_MRX_GTX_P[0..15] (6)
PCIE_MRX_GTX_N[0..15] (6)
1
A A
QUANTA
QUANTA
QUANTA COMPUTER
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
M97LP_PCIE
M97LP_PCIE
M97LP_PCIE
RM3 3A
RM3 3A
RM3 3A
18 60Wednesday, May 06, 2009
18 60Wednesday, May 06, 2009
18 60Wednesday, May 06, 2009
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of
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