QUANTA R03 Schematics
1
3&%67$&.83
2
3
4
5
6
7
8
/
/$<(5723
/$<(5*1'
/$<(5,1
A A
/$<(5,1
/$<(5*1'
/$<(5%27
5H'ULYHU
61/9&357-5
B B
C C
D D
DIS
(6$7$
PAGE 20
6$7$+''
2''
D[LV)DOO6HQVRU
.H\ERDUG&RQQ
7RXFK3DG
/('
PAGE 29
1
R03/V03 UMA BLOCK DIAGRAM
DDRIII-SODIMM1
AA00
DDRIII-SODIMM2
01
PAGE 28
PAGE 28
PAGE 16
PAGE 17
PAGE 20
PAGE 21
PAGE 21
PAGE 21
3:0)$1
7KHUPDO
PAGE 31
DDRIII 1333 MT/s
DDRIII 1333 MT/s
SATA4 300MB /S
SATA0 300MB /S
SATA1 300MB /S
SMBUS
32.768KHz
.%&
,7(
PAGE 23
63,520
2
N%
PAGE 27
FDI LINK
LPC
CPU
Sandy Bridge 45W
PGA 989
2.5GT /s
Mobile Intel
Series 6 Chipset
PCH
HM67
Couger Point
BGA 989
25 mm X 25 mm
SPI
63,520
0%
PAGE 27
3
25MHz
PAGE 4~8
DMI LINK
2.5GT /s
,17+'0,
,17'XDO&+$11(//9'6
iGFX Interfaces
(6$7$86%
USB2.0
PAGE 9~15
32.768KHz
6XEZRRIHU
0$;(7(
IHDA
$XGLR&RGHF
$/&49%*5
PAGE 26
http://hobi-elektronika.net
4
&DPHUD
PAGE 20
USB[0]
&57%RDUG
:/$1
PAGE 05
PCIE[5]
/$1
5HDOWHN
57/(9%*5
PAGE 09
25MHz
PAGE 25
PAGE 25 PAGE 25
5
PAGE 18
USB[11]
PAGE 03
USB[5]USB[4]
:L0$;
PCIE[2]PCIE[1]
%OXH7RRWK
5-
PAGE 10
-DFN6SHDNHU 'LJLWDO0,&
PAGE 25
;
&DUG5HDGHU
576*5
IO Board
PAGE 04
PAGE 05
USB[6]
PAGE 22
USB[8]
PCIE[3]
86%&RQWUROOHU
PAGE 06
86%3RUWV[
PAGE 07
86%3RUW[
PAGE 08
USB[2]
6
)3
PAGE 28
USB[10]
+'0,6ZLWFK
PAGE 19
/&'&211
1600 x 900 (HD)
7RXFK6FUHHQ
USB[8]
([SUHVV&DUG
5'
USB[12]
PAGE 02
+'0,&211
PAGE 19
PAGE 18
PAGE 27
EXP Board
LED Board
PB Board
TP Board
HotKey Board
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Wednesday, October 06, 2010
Wednesday, October 06, 2010
Wednesday, October 06, 2010
Date: Sheet of
Date: Sheet of
Date: Sheet
7
PROJECT :
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
Charger
3/5V
1.5V_SUS/0.75V_DDR
Batt/DC-IN
1.05V_PCH
VCCSA
CPU_CORE
1.8V_RUN
PAGE 35
PAGE 36
PAGE 37
PAGE 34
PAGE 38
PAGE 39
PAGE 40
PAGE 38
R03/V03
R03/V03
R03/V03
of
142
142
142
8
2A
2A
2A
1
2
3
4
5
6
7
8
+RTC_CELL
power
A A
+DC_IN
+DC_IN_SS
+PWR_SRC
+5V_ALW_2
+3.3V_ALW
+5V_ALW
+15V_ALW
+3.3V_LAN (for V03)
State
S0
ON
ON
+VCHGR
+PWR_SRC
+5V_ALW_2
+3.3V_ALW
+5V_ALW
+15V_ALW
+3.3V_LAN (for V03)
ON
+5V_SUS
+3.3V_SUS
+1.5V_SUS
+1.5V_CPU
+DDR_VTTREF
+3.3V_LAN (for R03)
ON
+VCC_CORE
+1.05V_PCH
+5V_RUN
+3.3V_RUN
+1.8V_RUN
+1.5V_RUN
+VCCSA
+0.75V_DDR_VTT
+LCDVCC
+VCC_GFX_CORE
ON
S1
S3
B B
S4/S5 AC
S4/S5
ON
ON
ON
ON
ON
ON
ON
ON
OFF
OFF
OFF
DC Only
AC/DC
ON
OFF OFF
OFF
OFF
No Exist
C C
SMBCLK
SMBDATA
SMB_CLK_ME1
SMB_DAT_ME1
AB1A_CLK
AB1A_DATA
D D
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
http://hobi-elektronika.net
1
2
3
4
5
6
Size Document Number Rev
Wednesday, October 27, 2010
Wednesday, October 27, 2010
Wednesday, October 27, 2010
Date: Sheet of
Date: Sheet of
Date: Sheet
7
PROJECT :
Power Rails
Power Rails
Power Rails
R03/V03
R03/V03
R03/V03
2A
2A
2A
of
242
242
242
8
5
D D
C C
4
3
2
1
B B
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
http://hobi-elektronika.net
5
4
3
2
Size Document Number Rev
Wednesday, October 06, 2010
Wednesday, October 06, 2010
Wednesday, October 06, 2010
Date: Sheet of
Date: Sheet of
Date: Sheet
PROJECT :
BLANK
BLANK
BLANK
R03/V03
R03/V03
R03/V03
of
342
342
342
1
2A
2A
2A
5
4
3
2
1
DP & PEG Compensation
Sandy Bridge Processor (DMI,PEG,FDI)
U17A
D D
DMI_TXN0[9]
DMI_TXN1[9]
DMI_TXN2[9]
DMI_TXN3[9]
DMI_TXP0[9]
DMI_TXP1[9]
DMI_TXP2[9]
DMI_TXP3[9]
DMI_RXN0[9]
DMI_RXN1[9]
DMI_RXN2[9]
DMI_RXN3[9]
DMI_RXP0[9]
DMI_RXP1[9]
DMI_RXP2[9]
DMI_RXP3[9]
FDI_TXN0[9]
FDI_TXN1[9]
FDI_TXN2[9]
C C
eDP_ICOMPO 12mil
B B
eDP_COMPIO 4mil
FDI_TXN3[9]
FDI_TXN4[9]
FDI_TXN5[9]
FDI_TXN6[9]
FDI_TXN7[9]
FDI_TXP0[9]
FDI_TXP1[9]
FDI_TXP2[9]
FDI_TXP3[9]
FDI_TXP4[9]
FDI_TXP5[9]
FDI_TXP6[9]
FDI_TXP7[9]
FDI_FSYNC0[9]
FDI_FSYNC1[9]
FDI_LSYNC0[9]
FDI_LSYNC1[9]
FDI_INT[9]
EDP_COMP
INT_EDP_HPD
Programing Disable eDP interface(BIOS)
U17A
B27
DMI_RX#[0]
B25
DMI_RX#[1]
A25
DMI_RX#[2]
B24
DMI_RX#[3]
B28
DMI_RX[0]
B26
DMI_RX[1]
A24
DMI_RX[2]
B23
DMI_RX[3]
G21
DMI_TX#[0]
E22
DMI_TX#[1]
F21
DMI_TX#[2]
D21
DMI_TX#[3]
G22
DMI_TX[0]
D22
DMI_TX[1]
F20
DMI_TX[2]
C21
DMI_TX[3]
A21
FDI0_TX#[0]
H19
FDI0_TX#[1]
E19
FDI0_TX#[2]
F18
FDI0_TX#[3]
B21
FDI1_TX#[0]
C20
FDI1_TX#[1]
D18
FDI1_TX#[2]
E17
FDI1_TX#[3]
A22
FDI0_TX[0]
G19
FDI0_TX[1]
E20
FDI0_TX[2]
G18
FDI0_TX[3]
B20
FDI1_TX[0]
C19
FDI1_TX[1]
D19
FDI1_TX[2]
F17
FDI1_TX[3]
J18
FDI0_FSYNC
J17
FDI1_FSYNC
H20
FDI_INT
J19
FDI0_LSYNC
H17
FDI1_LSYNC
A18
eDP_COMPIO
A17
eDP_ICOMPO
B16
eDP_HPD
C15
eDP_AUX
D15
eDP_AUX#
C17
eDP_TX[0]
F16
eDP_TX[1]
C16
eDP_TX[2]
G15
eDP_TX[3]
C18
eDP_TX#[0]
E16
eDP_TX#[1]
D16
eDP_TX#[2]
F15
eDP_TX#[3]
Sandy Bridge_rPGA_4SODIMM_Rev1p0
Sandy Bridge_rPGA_4SODIMM_Rev1p0
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
DMI
DMI
Intel(R) FDI
Intel(R) FDI
eDP
eDP
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PCI EXPRESS* - GRAPHICS
PCI EXPRESS* - GRAPHICS
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
J22
J21
H22
K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32
J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32
M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25
M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25
PEG_COMP
PEG_ICOMPO 12mil
PEG_ICOMPI, PEG_RCOMPO 4mil,
+1.05V_PCH
R309 24.9/F_4R309 24.9/F_4
eDP_COMPIO and ICOMPO signals should
be shorted near balls and
routed within 500 mils
+1.05V_PCH
R55 24.9/F_4R55 24.9/F_4
PEG_ICOMPI and RCOMPO signals should
be routed within 500 mils
PEG_ICOMPO signals should
be routed within 500 mils
EDP_COMP
PEG_COMP
eDP Hot-plug (Disable)
+1.05V_PCH
R304
R304
*10K_4_NC
*10K_4_NC
INT_EDP_HPD
CAD Note: Place PU resistor within 2 inches
of CPU
This signal can be left as no connect if
entire eDP interface is disabled.
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
http://hobi-elektronika.net
5
4
3
2
Size Document Number Rev
Date: Sheet
Friday, January 07, 2011
Friday, January 07, 2011
Friday, January 07, 2011
Date: Sheet of
Date: Sheet of
PROJECT :
Sandy Bridge 1/5
Sandy Bridge 1/5
Sandy Bridge 1/5
R03/V03
R03/V03
R03/V03
of
442
442
442
1
2A
2A
2A
5
4
3
2
1
Sandy Bridge Processor (CLK,MISC,JTAG)
U17B
U17B
follow SS8: SNB_IVB# N.A at SNB EDS #27637 0.7v1
C26
PROC_SELECT#
AN34
SKTOCC#
AL33
CATERR#
AN33
PECI
AL32
PROCHOT#
AN32
THERMTRIP#
AM34
PM_SYNC
AP33
UNCOREPWRGOOD
V8
SM_DRAMPWROK
AR33
RESET#
MISCTHERMALPWR MANAGEMENT
MISCTHERMALPWR MANAGEMENT
DPLL_REF_CLK
DPLL_REF_CLK#
CLOCKS
CLOCKS
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
DDR3
MISC
DDR3
MISC
JTAG & BPM
JTAG & BPM
TP34TP34
TP43TP43
TP_CATERR#
H_PECI_R
H_PROCHOT#_R
SM_DRAMPWROK
CPU_PLTRST#_R
+1.05V_PCH
D D
Over 130 degree C will
drive low
C C
R186 62/F_4R186 62/F_4
+1.05V_PCH
H_PROCHOT#
PECI_EC[23]
H_PROCHOT#[23,35,40]
PM_THRMTRIP#[14]
H_PM_SYNC[9]
H_PWRGOOD[14]
R192 *75/J_4_NCR192 *75/J_4_NC
CPU_PLTRST#
H_CPUDET#[23]
R445 43/J_4R445 43/J_4
R181 56/J_4R181 56/J_4
R189 10K/J_4R189 10K/J_4
R193 *43/J_4_NCR193 *43/J_4_NC
+3.3V_SUS
IN OUT
BCLK
BCLK#
PRDY#
PREQ#
TCK
TMS
TRST#
TDO
DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
A28
A27
CLK_DP_P_R
A16
CLK_DP_N_R
A15
CPU_DRAMRST#
R8
SM_RCOMP_0
AK1
SM_RCOMP_1
A5
SM_RCOMP_2
A4
AP29
AP27
XDP_TCLK
AR26
XDP_TMS
AR27
XDP_TRST#
AP30
XDP_TDI
AR28
TDI
AP26
AL35
AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32
XDP_TDO
XDP_DBRST#
R310 1K_4R310 1K_4
R305 *0_4_NCR305 *0_4_NC
R306 *0_4_NCR306 *0_4_NC
R311 1K_4R311 1K_4
R153 140/F_4R153 140/F_4
R312 25.5/F_4R312 25.5/F_4
R313 200/F_4R313 200/F_4
R447 51/J_4R447 51/J_4
R443 1K_4R443 1K_4
XDP_DBRST# use a 1k pull-up to 3.3V_S
TRST# use a 51ohm pull down.
When MP, JTAG PU/PD resistor
can be removed?
Need to confirm with Intel
CLK_CPU_BCLKP [13]
CLK_CPU_BCLKN [13]
SM_RCOMP_0, SM_RCOMP_1 20mil
SM_RCOMP_2 15mil,
+3.3V_RUN
CLK_DP_P [13]
CLK_DP_N [13]
+1.05V_PCH
XDP_TMS
XDP_TDI
XDP_TDO
XDP_TCLK
Schematic C/L_v1.0, P56 (PU, P D 1k/J)
(Intel and PD3)
Reserve (Intel confirm now)
+1.05V_PCH
R452 51/J_4R452 51/J_4
R450 51/J_4R450 51/J_4
R201 51/J_4R201 51/J_4
R202 51/J_4R202 51/J_4
LL
C333
H
B B
High-Z
PLTRST#[12,23,24]
R556
R556
1.5K
1.5K
1%
1%
CPU_PLTRST#_R voltage level Ckt.
CPU_PLTRST#_R
1%
1%
750
750
R557
R557
U8
U8
1
VCC
NC
2
IN
GND3OUT
*74LVC1G07GW_NC
*74LVC1G07GW_NC
Change OD part same with PDC
Copy from PDC
A A
PM_DRAM_PWRGD[9]
SYS_PWROK[9]
Follow #DG1.0 436735 P105
DDR Power Gating Topology
5
+3.3V_SUS
R183
R183
200_4
200_4
5
4
2
1
74AHC1G09GW
74AHC1G09GW
C333
*0.1U/10V/X7R_4_NC
*0.1U/10V/X7R_4_NC
CPU_PLTRST#CPU_PLTRST#CPU_PLTRST#
U6
U6
4
3 5
DRAM_PWRGD
SYS_PWROK
SM_DRAMPWROK
C301
C301
0.1U/10V/X7R_4
0.1U/10V/X7R_4
R184 *39_NCR184 *39_NC
4
Sandy Bridge_rPGA_4SODIMM_Rev1p0
Sandy Bridge_rPGA_4SODIMM_Rev1p0
Boot S3
+1.5V_CPU
R8239, R8241 change to 5%
Pin1
Pin2 Pin4
LL
+1.5V_CPU
R170
R170
200/F_4
200/F_4
R176 130/F_4R176 130/F_4
3
Q14 *2N7002K_NCQ14 *2N7002K_NC
2
H
H
SM_DRAMPWROKSM_DRAMPWROK_R
1
http://hobi-elektronika.net
PS_S3CNTRL [7,16]
S3 RSM
100 ns after +1.5V_CPU
reaches 80%
Follow #DG1.0 436735 P107
DRAMRST# Routing Illustration
R63
R63
1K/F_4
DDR3_DRAMRST#[16,17]
1K/F_4
L
L
HL
L
L
H
H
3
DDR_HVREF_RST_PCH[13]
2
+1.5V_SUS
R72
R72
1K/F_4
1K/F_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Monday, January 24, 2011
Monday, January 24, 2011
Monday, January 24, 2011
Date: Sheet of
Date: Sheet of
Date: Sheet
R54 *0_4_NCR54 *0_4_NC
Q5 BSS138-7-FQ5 BSS138-7-F
3
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
Sandy Bridge 2/5
Sandy Bridge 2/5
Sandy Bridge 2/5
2
C86
C86
0.047U/10V_4
0.047U/10V_4
1
R03/V03
R03/V03
R03/V03
1
CPU_DRAMRST#DDR3_DRAMRST#_R
R56
R56
4.99K/F_4
4.99K/F_4
of
542
542
542
2A
2A
2A
5
4
Sandy Bridge Processor (DDR3)
U17C
U17C
3
U17D
U17D
2
1
D D
C C
B B
M_A_DQ[63:0][16]
M_A_BS0[16]
M_A_BS1[16]
M_A_BS2[16]
M_A_CAS#[16]
M_A_RAS#[16]
M_A_WE#[16]
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33 M_B_DQ34
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
F10
G10
N10
M10
AG6
AG5
AK6
AK5
AH5
AH6
AJ5
AJ6
AJ8
AK8
AJ9
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
AE10
AF10
AE8
AD9
AF9
C5
D5
D3
D2
D6
C6
C2
C3
F8
G9
F9
F7
G8
G7
K4
K5
K1
J1
J5
J4
J2
K2
M8
N8
N7
M9
N9
M7
V6
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
SA_BS[0]
SA_BS[1]
SA_BS[2]
SA_CAS#
SA_RAS#
SA_WE#
SA_CLK#[0]
SA_CLK#[1]
SA_CLK#[2]
SA_CLK#[3]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
SA_CLK[0]
SA_CKE[0]
SA_CLK[1]
SA_CKE[1]
SA_CLK[2]
SA_CKE[2]
SA_CLK[3]
SA_CKE[3]
SA_CS#[0]
SA_CS#[1]
SA_CS#[2]
SA_CS#[3]
SA_ODT[0]
SA_ODT[1]
SA_ODT[2]
SA_ODT[3]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
AB6
AA6
V9
AA5
AB5
V10
AB4
AA4
W9
AB3
AA3
W10
AK3
AL3
AG1
AH1
AH3
AG3
AG2
AH2
C4
G6
J3
M6
AL6
AM8
AR12
AM15
D4
F6
K3
N6
AL5
AM9
AR11
AM14
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
M_A_DQSN0
M_A_DQSN1
M_A_DQSN2
M_A_DQSN3
M_A_DQSN4
M_A_DQSN5
M_A_DQSN6
M_A_DQSN7
M_A_DQSP0
M_A_DQSP1
M_A_DQSP2
M_A_DQSP3
M_A_DQSP4
M_A_DQSP5
M_A_DQSP6
M_A_DQSP7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_CLKP0 [16]
M_A_CLKN0 [16]
M_A_CKE0 [16]
M_A_CLKP1 [16]
M_A_CLKN1 [16]
M_A_CKE1 [16]
M_A_CS#0 [16]
M_A_CS#1 [16]
M_A_ODT0 [16]
M_A_ODT1 [16]
M_A_DQSN[7:0] [16]
M_A_DQSP[7:0] [16]
M_A_A[15:0] [16]
M_B_DQ[63:0][17]
M_B_BS0[17]
M_B_BS1[17]
M_B_BS2[17]
M_B_CAS#[17]
M_B_RAS#[17]
M_B_WE#[17]
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
D10
K10
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
AA9
AA7
AA10
AB8
AB9
C9
A7
C8
A9
A8
D9
D8
G4
G1
G5
G2
K9
J10
K8
K7
M5
N4
N2
N1
M4
N5
M2
M1
R6
F4
F1
F5
F2
J7
J8
J9
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
SB_BS[0]
SB_BS[1]
SB_BS[2]
SB_CAS#
SB_RAS#
SB_WE#
SB_CLK#[0]
SB_CLK#[1]
SB_CLK#[2]
SB_CLK#[3]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
SB_CLK[0]
SB_CKE[0]
SB_CLK[1]
SB_CKE[1]
SB_CLK[2]
SB_CKE[2]
SB_CLK[3]
SB_CKE[3]
SB_CS#[0]
SB_CS#[1]
SB_CS#[2]
SB_CS#[3]
SB_ODT[0]
SB_ODT[1]
SB_ODT[2]
SB_ODT[3]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
AE2
AD2
R9
AE1
AD1
R10
AB2
AA2
T9
AA1
AB1
T10
AD3
AE3
AD6
AE6
AE4
AD4
AD5
AE5
D7
F3
K6
N3
AN5
AP9
AK12
AP15
C7
G3
J6
M3
AN6
AP8
AK11
AP14
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
M_B_DQSN0
M_B_DQSN1
M_B_DQSN2
M_B_DQSN3
M_B_DQSN4
M_B_DQSN5
M_B_DQSN6
M_B_DQSN7
M_B_DQSP0
M_B_DQSP1
M_B_DQSP2
M_B_DQSP3
M_B_DQSP4
M_B_DQSP5
M_B_DQSP6
M_B_DQSP7
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_CLKP0 [17]
M_B_CLKN0 [17]
M_B_CKE0 [17]
M_B_CLKP1 [17]
M_B_CLKN1 [17]
M_B_CKE1 [17]
M_B_CS#0 [17]
M_B_CS#1 [17]
M_B_ODT0 [17]
M_B_ODT1 [17]
M_B_DQSN[7:0] [17]
M_B_DQSP[7:0] [17]
M_B_A[15:0] [17]
Sandy Bridge_rPGA_4SODIMM_Rev1p0
Sandy Bridge_rPGA_4SODIMM_Rev1p0
Sandy Bridge_rPGA_4SODIMM_Rev1p0
A A
http://hobi-elektronika.net
5
4
3
Sandy Bridge_rPGA_4SODIMM_Rev1p0
2
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Friday, January 07, 2011
Friday, January 07, 2011
Friday, January 07, 2011
Date: Sheet of
Date: Sheet of
Date: Sheet
PROJECT :
Sandy Bridge 3/5
Sandy Bridge 3/5
Sandy Bridge 3/5
R03/V03
R03/V03
R03/V03
of
642
642
642
1
2A
2A
2A
5
Sandy Bridge Processor (POWER)
POWER
POWER
U17F
U17F
+VCC_CORE
AG35
VCC1
AG34
VCC2
C497
C497
10U/6.3V_8
10U/6.3V_8
C508
C508
10U/6.3V_8
10U/6.3V_8
C194
C194
C175
C175
C210
C210
*22U/6.3V_8_NC
*22U/6.3V_8_NC
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
Y35
VCC51
Y34
VCC52
Y33
VCC53
Y32
VCC54
Y31
VCC55
Y30
VCC56
Y29
VCC57
Y28
VCC58
Y27
VCC59
Y26
VCC60
V35
VCC61
V34
VCC62
V33
VCC63
V32
VCC64
V31
VCC65
V30
VCC66
V29
VCC67
V28
VCC68
V27
VCC69
V26
VCC70
U35
VCC71
U34
VCC72
U33
VCC73
U32
VCC74
U31
VCC75
U30
VCC76
U29
VCC77
U28
VCC78
U27
VCC79
U26
VCC80
R35
VCC81
R34
VCC82
R33
VCC83
R32
VCC84
R31
VCC85
R30
VCC86
R29
VCC87
R28
VCC88
R27
VCC89
R26
VCC90
P35
VCC91
P34
VCC92
P33
VCC93
P32
VCC94
P31
VCC95
P30
VCC96
P29
VCC97
P28
VCC98
P27
VCC99
P26
VCC100
CORE SUPPLY
CORE SUPPLY
SENSE LINES SVID
SENSE LINES SVID
D D
CPU Core Power
SNB 45W:95A
470uF/4mohm x 4
22uF x 16
10uF x 10
C541
C541
C501
C501
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
C495
C495
C507
C507
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
C C
10U/6.3V_6
10U/6.3V_6
10U/6.3V_6
10U/6.3V_6
B B
22uF (Reserved)
C536
C536
10U/6.3V_8
10U/6.3V_8
C551
C551
10U/6.3V_8
10U/6.3V_8
C163
C163
10U/6.3V_6
10U/6.3V_6
C156
C156
10U/6.3V_6
10U/6.3V_6
C211
C211
*22U/6.3V_8_NC
*22U/6.3V_8_NC
+
+
C127
C127
470U/2V_7343
470U/2V_7343
C516
C516
10U/6.3V_8
10U/6.3V_8
C178
C178
10U/6.3V_8
10U/6.3V_8
C205
C205
10U/6.3V_6
10U/6.3V_6
C170
C170
10U/6.3V_6
10U/6.3V_6
C478
C478
*22U/6.3V_8_NC
*22U/6.3V_8_NC
C525
C525
10U/6.3V_8
10U/6.3V_8
C496
C496
10U/6.3V_8
10U/6.3V_8
C123
C123
10U/6.3V_6
10U/6.3V_6
C135
C135
10U/6.3V_6
10U/6.3V_6
C491
C491
*22U/6.3V_8_NC
*22U/6.3V_8_NC
+
+
C126
C126
470U/2V_7343
470U/2V_7343
C482
C482
10U/6.3V_8
10U/6.3V_8
C212
C212
10U/6.3V_8
10U/6.3V_8
C142
C142
10U/6.3V_6
10U/6.3V_6
C546
C546
10U/6.3V_6
10U/6.3V_6
C213
C213
*22U/6.3V_8_NC
*22U/6.3V_8_NC
4
AH13
VCCIO1
AH10
VCCIO2
AG10
VCCIO3
AC10
VCCIO4
Y10
VCCIO5
U10
VCCIO6
P10
VCCIO7
L10
VCCIO8
J14
VCCIO9
J13
VCCIO10
J12
VCCIO11
J11
VCCIO12
H14
VCCIO13
H12
VCCIO14
H11
VCCIO15
G14
VCCIO16
G13
VCCIO17
G12
VCCIO18
F14
VCCIO19
F13
VCCIO20
F12
VCCIO21
F11
VCCIO22
E14
VCCIO23
E12
VCCIO24
E11
VCCIO25
D14
VCCIO26
D13
VCCIO27
D12
VCCIO28
D11
VCCIO29
C14
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
VCCIO40
VIDALERT#
VIDSCLK
VIDSOUT
VCC_SENSE
VSS_SENSE
VCCIO_SENSE
VSSIO_SENSE
C13
C12
C11
B14
B12
A14
A13
A12
A11
J23
H_CPU_SVIDALRT#
AJ29
H_CPU_SVIDCLK VCCSA _VID0
AJ30
H_CPU_SVIDDAT VCCSA_ VID1
AJ28
AJ35
AJ34
B10
A10
PEG AND DDR
PEG AND DDR
CPU VTT
SNB 45W:8.5A
330uF/6mohm x 2
22uF x 12
22uF x 7 (Non-stuff)
+
+
C472
C472
*330U/2V_7343_NC
*330U/2V_7343_NC
C494
C494
10U/6.3V_8
10U/6.3V_8
C513
C513
10U/6.3V_8
10U/6.3V_8
C106
C106
*22U/6.3V_8_NC
*22U/6.3V_8_NC
R145 100/J_4R145 100/J_4
R151 100/J_4R151 100/J_4
VSSIO_SENSE [38]
+
+
C465
C465
*330U/2V_7343_NC
*330U/2V_7343_NC
C215
C215
C172
C172
10U/6.3V_6
10U/6.3V_6
10U/6.3V_8
10U/6.3V_8
C150
C150
C484
C484
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
22uF (Reserved)
C161
C161
C526
C526
*22U/6.3V_8_NC
*22U/6.3V_8_NC
*22U/6.3V_8_NC
*22U/6.3V_8_NC
+VCC_CORE
VCCSENSE [40]
VSSSENSE [40]
+1.05V_PCH
C533
C533
10U/6.3V_8
10U/6.3V_8
C498
C498
10U/6.3V_6
10U/6.3V_6
C130
C130
*22U/6.3V_8_NC
*22U/6.3V_8_NC
+VCC_GFX_CORE
C22
C22
C540
C540
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
C197
C197
C17
C17
10U/6.3V_6
10U/6.3V_6
10U/6.3V_8
10U/6.3V_8
CPU VCCPL
SNB 45W:3A
330uF/7mohm x 1
10uF x 1
1uF x 2
3
CPU VGT
SNB 45W:22A
22uF x 12
+1.8V_RUN
SIO_SLP_S3#[9,23]VCCIO_SENSE [38]
10U/6.3V_6
10U/6.3V_6
10U/6.3V_6
10U/6.3V_6
C316
C316
22U/6.3V_8
22U/6.3V_8
C331
C331
10U/6.3V_8
10U/6.3V_8
C323
C323
22U/6.3V_8
22U/6.3V_8
C238
C238
C470
C470
22U/6.3V_8
22U/6.3V_8
Sandy Bridge Processor (GRAPHIC POWER)
2
POWER
U17G
U17G
AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
C544
C545
C545
10U/6.3V_6
10U/6.3V_6
C317
C317
22U/6.3V_8
22U/6.3V_8
C236
C236
10U/6.3V_6
10U/6.3V_6
C561
C561
C474
C474
1U/6.3V_4
1U/6.3V_4
C544
AP21
10U/6.3V_6
10U/6.3V_6
AP20
AP18
AP17
AN24
AN23
AN21
AN20
C324
C324
C334
C334
10U/6.3V_8
10U/6.3V_8
C237
C237
10U/6.3V_6
10U/6.3V_6
C473
C473
1U/6.3V_4
1U/6.3V_4
+5V_ALW +15V_ALW
2
R163
R163
*10K_4_NC
*10K_4_NC
10U/6.3V_8
10U/6.3V_8
C335
C335
22U/6.3V_8
22U/6.3V_8
+
+
C26
C26
*330U/2V_7343_NC
*330U/2V_7343_NC
12
R188
R188
10K_4
10K_4
31
Q12
Q12
2N7002W-7-F
2N7002W-7-F
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17
B6
A6
A2
Sandy Bridge_rPGA_4SODIMM_Rev1p0
Sandy Bridge_rPGA_4SODIMM_Rev1p0
VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54
VCCPLL1
VCCPLL2
VCCPLL3
POWER
GRAPHICS
GRAPHICS
1.8V RAIL
1.8V RAIL
PS_S3CNTRL [5,16]
2N7002W-7-F
2N7002W-7-F
VAXG_SENSE
VSSAXG_SENSE
SENSE
LINES
SENSE
LINES
SM_VREF
VREFMISC
VREFMISC
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
DDR3 -1.5V RAILS
DDR3 -1.5V RAILS
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
SA RAIL
SA RAIL
VCCSA_SENSE
FC_C22
VCCSA_ VID1
S3 Power reduce
R149
R149
100K_4
100K_4
PS_S3CNTRL_S
31
C226
2
Q8
Q8
C226
*0.01U/25V/X7R_4_NC
*0.01U/25V/X7R_4_NC
TP11TP11
AK35
AK34
+VDDR_REF_CPU
AL1
CAD Note: +VDDR_REF_CPU should
have 10 mil trace width
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
M27
M26
L26
J26
J25
J24
H26
H25
H23
C22
C24
VCCSA_VID0
VCCSA_VID1
73
VCC_AXG_SENSE [40]
VSS_AXG_SENSE [40]
TP13TP13
+VDDR_REF_CPU
C198
C198
C208
C208
*10U/6.3V_6_NC
*10U/6.3V_6_NC
*10U/6.3V_6_NC
*10U/6.3V_6_NC
C185
C185
C234
C234
10U/6.3V_6
10U/6.3V_6
10U/6.3V_6
10U/6.3V_6
C80
C80
C81
C81
10U/6.3V_6
10U/6.3V_6
*10U/6.3V_6_NC
*10U/6.3V_6_NC
R28 10K/F_4R28 10K/F_4
1 2
R26 *10K/F_4_NCR26 *10K/F_4_NC
1 2
R27 10K/F_4R27 10K/F_4
1 2
PS_S3CNTRL_S
1
CPU MCH
SNB 45W: 5A
330uF/6mohm x 1
10uF x 6
C98
C98
10U/6.3V_6
10U/6.3V_6
10U/6.3V_6
10U/6.3V_6
+
+
C151
C151
*330U/2V_7343_NC
*330U/2V_7343_NC
+
+
C486
C486
10U/6.3V_6
10U/6.3V_6
VCCSA_SENSE [39]
VCCSA_VID1 [39]
+1.5V_SUS +1.5V_CPU
10A
Q7
FDMS7670Q7FDMS7670
9
8
762
5
4
C201
C201
4700P/2 5V/X7R _4
4700P/2 5V/X7R _4
+1.5V_CPU
C155
C155
C132
C132
C133
C133
*22U/6.3V_8_NC
*22U/6.3V_8_NC
*22U/6.3V_8_NC
*22U/6.3V_8_NC
+VCCSA_CORE
C20
C20
*330U/2V_7343_NC
*330U/2V_7343_NC
CPU SA
SNB 45W: 6A
330uF/7mohm x 1
10uF x 3
+1.05V_PCH
3
1
change 1kohm to 220ohm
12
R141
R141
*220_NC
*220_NC
31
PS_S3CNTRL
2
Q10
Q10
*2N7002W-7-F_NC
*2N7002W-7-F_NC
Take care Q3509 Vgs(MAX)=2.5
Sandy Bridge_rPGA_4SODIMM_Rev1p0
Sandy Bridge_rPGA_4SODIMM_Rev1p0
Change R8281,R8285, R8704,R8329 to +/-5%
A A
Layout note: need routing
together and ALERT need
between CLK and DATA
H_CPU_SVIDCLK
R187 *0_0402short_NCR187 *0_0402short_NC
5
SVID CLK
PU Close to VR
VR_SVID _CLK [4 0]
Place PU resistor close to CPU
+1.05V_PCH +1.05V_PCH
R156
R156
130_4
130_4
H_CPU_SVIDDAT H_CPU_SVIDALRT#
54.9 ohm has no 5%
R150 *0_0402short_NCR150 *0_0402short_NC
4
SVID DATA
Place PU resistor close to CPU
R180
R180
75_4
R175 43_4R175 43_4
75_4
3
SVID ALERTPU Close to VR
R174 *0_0402short_NCR174 *0_0402short_NC
1/61/61/6
+1.5V_SUS +1.5V_CPU
VR_SVID _ALER T# [40]VR_SVID_DATA [40]
2
C134 0.1U/25/X5R_4C134 0.1U/25/X5R_4
C139 0.1U/25/X5R_4C139 0.1U/25/X5R_4
C122 0.1U/25/X5R_4C122 0.1U/25/X5R_4
C114 0.1U/25/X5R_4C114 0.1U/25/X5R_4
Size Document Nu mb e r Rev
Size Document Nu mb e r Rev
Size Document Nu mb e r Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
R173 *0_8_NCR173 *0_8_NC
2N7002W-7-F
2N7002W-7-F
PS_S3CNTRL_S
Sandy Bridge 4/5
Sandy Bridge 4/5
Sandy Bridge 4/5
Monday, January 24, 2011
Monday, January 24, 2011
Monday, January 24, 2011
+VDDR_REF_CPU+DDR_VTTREF
3 1
Q11
Q11
2
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
1
R167
R167
100K_4
100K_4
R03/V03
R03/V03
R03/V03
742
742
742
C264
C264
0.1U/10V/X7R_4
0.1U/10V/X7R_4
of
2A
2A
2A
http://hobi-elektronika.net
5
4
3
2
1
Sandy Bridge Processor (GND) Sandy Bridge Processor (RESERVED, CFG)
U17H
U17H
AT35
VSS1
AT32
VSS2
AT29
VSS3
AT27
VSS4
AT25
VSS5
AT22
VSS6
AT19
VSS7
AT16
VSS8
D D
C C
B B
AT13
VSS9
AT10
VSS10
AT7
VSS11
AT4
VSS12
AT3
VSS13
AR25
VSS14
AR22
VSS15
AR19
VSS16
AR16
VSS17
AR13
VSS18
AR10
VSS19
AR7
VSS20
AR4
VSS21
AR2
VSS22
AP34
VSS23
AP31
VSS24
AP28
VSS25
AP25
VSS26
AP22
VSS27
AP19
VSS28
AP16
VSS29
AP13
VSS30
AP10
VSS31
AP7
VSS32
AP4
VSS33
AP1
VSS34
AN30
VSS35
AN27
VSS36
AN25
VSS37
AN22
VSS38
AN19
VSS39
AN16
VSS40
AN13
VSS41
AN10
VSS42
AN7
VSS43
AN4
VSS44
AM29
VSS45
AM25
VSS46
AM22
VSS47
AM19
VSS48
AM16
VSS49
AM13
VSS50
AM10
VSS51
AM7
VSS52
AM4
VSS53
AM3
VSS54
AM2
VSS55
AM1
VSS56
AL34
VSS57
AL31
VSS58
AL28
VSS59
AL25
VSS60
AL22
VSS61
AL19
VSS62
AL16
VSS63
AL13
VSS64
AL10
VSS65
AL7
VSS66
AL4
VSS67
AL2
VSS68
AK33
VSS69
AK30
VSS70
AK27
VSS71
AK25
VSS72
AK22
VSS73
AK19
VSS74
AK16
VSS75
AK13
VSS76
AK10
VSS77
AK7
VSS78
AK4
VSS79
AJ25
VSS80
Sandy Bridge_rPGA_4SODIMM_Rev1p0
Sandy Bridge_rPGA_4SODIMM_Rev1p0
VSS
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH26
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
U17I
U17I
T35
VSS161
T34
VSS162
T33
VSS163
T32
VSS164
T31
VSS165
T30
VSS166
T29
VSS167
T28
VSS168
T27
VSS169
T26
VSS170
P9
VSS171
P8
VSS172
P6
VSS173
P5
VSS174
P3
VSS175
P2
VSS176
N35
VSS177
N34
VSS178
N33
VSS179
N32
VSS180
N31
VSS181
N30
VSS182
N29
VSS183
N28
VSS184
N27
VSS185
N26
VSS186
M34
VSS187
L33
VSS188
L30
VSS189
L27
VSS190
L9
VSS191
L8
VSS192
L6
VSS193
L5
VSS194
L4
VSS195
L3
VSS196
L2
VSS197
L1
VSS198
K35
VSS199
K32
VSS200
K29
VSS201
K26
VSS202
J34
VSS203
J31
VSS204
H33
VSS205
H30
VSS206
H27
VSS207
H24
VSS208
H21
VSS209
H18
VSS210
H15
VSS211
H13
VSS212
H10
VSS213
H9
VSS214
H8
VSS215
H7
VSS216
H6
VSS217
H5
VSS218
H4
VSS219
H3
VSS220
H2
VSS221
H1
VSS222
G35
VSS223
G32
VSS224
G29
VSS225
G26
VSS226
G23
VSS227
G20
VSS228
G17
VSS229
G11
VSS230
F34
VSS231
F31
VSS232
F29
VSS233
Sandy Bridge_rPGA_4SODIMM_Rev1p0
Sandy Bridge_rPGA_4SODIMM_Rev1p0
VSS
VSS
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
TP19TP19
TP18TP18
TP17TP17
TP20TP20
SMDDR_VREF_DQ0_M3[16]
SMDDR_VREF_DQ1_M3[17]
+3.3V_RUN
check pull high voltage
CFG2
CFG3
CFG4CFG4
CFG5
CFG6
R11
R11
*1K/J_4_NC
*1K/J_4_NC
R308 *10K_4_NCR308 *10K_4_NC
12
R16
R16
*1K/J_4_NC
*1K/J_4_NC
U17E
U17E
L7
RSVD28
AG7
AK28
CFG[0]
AK29
CFG[1]
AL26
CFG[2]
AL27
CFG[3]
AK26
CFG[4]
AL29
CFG[5]
AL30
CFG[6]
AM31
CFG[7]
AM32
CFG[8]
AM30
CFG[9]
AM28
CFG[10]
AM26
CFG[11]
AN28
CFG[12]
AN31
CFG[13]
AN26
CFG[14]
AM27
CFG[15]
AK31
CFG[16]
AN29
CFG[17]
AJ31
VAXG_VAL_SENSE
AH31
VSSAXG_VAL_SENSE
AJ33
VCC_VAL_SENSE
AH33
VSS_VAL_SENSE
AJ26
RSVD5
B4
RSVD6
D1
RSVD7
F25
RSVD8
F24
RSVD9
F23
RSVD10
D24
RSVD11
G25
RSVD12
G24
RSVD13
E23
RSVD14
D23
RSVD15
C30
RSVD16
A31
RSVD17
B30
RSVD18
B29
RSVD19
D30
RSVD20
B31
RSVD21
A30
RSVD22
C29
RSVD23
J20
RSVD24
B18
RSVD25
A19
VCCIO_SEL
J15
RSVD27
Sandy Bridge_rPGA_4SODIMM_Rev1p0
Sandy Bridge_rPGA_4SODIMM_Rev1p0
RESERVED
RESERVED
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD37
RSVD38
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
VCC_DIE_SENSE
RSVD54
RSVD55
RSVD56
RSVD57
RSVD58
KEY
AE7
AK2
W8
AT26
AM33
AJ27
T8
J16
H16
G16
AR35
AT34
AT33
AP35
AR34
B34
A33
A34
B35
C35
AJ32
AK32
AH27
AN35
AM35
TP37TP37
TP35TP35
#27636 SNB EDS0.7v1 no function.
AT2
AT1
AR1
B1
CFG[6:5] (PCIE Port Bifurcation Straps)
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
Processor Strapping
A A
5
CFG2
(PCI-E Static x16 Lane Reversal)
CFG3
(PCI-E Static x4 Lane Reversal)
CFG4
(DP Presence Strap)
4
Normal Operation Lane Reversed
Normal Operation Lane Reversed
Disable; No physical DP attached to eDP
http://hobi-elektronika.net
The CFG signals have a default value of '1' if not terminated on the board.
10
Enable; An ext DP device is connected to eDP
3
2
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
CFG2
R199 1K/F_4R199 1K/F_4
Sandy Bridge 5/5
Sandy Bridge 5/5
Sandy Bridge 5/5
Monday, January 24, 2011
Monday, January 24, 2011
Monday, January 24, 2011
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
R03/V03
R03/V03
R03/V03
of
842
842
842
1
2A
2A
2A
5
DMI_RXN0[4]
DMI_RXN1[4]
DMI_RXN2[4]
DMI_RXN3[4]
HWPG[23,31,32]
RSMRST#[23]
AC_PRESENT[23]
DMI_RXP0[4]
DMI_RXP1[4]
DMI_RXP2[4]
DMI_RXP3[4]
DMI_TXN0[4]
DMI_TXN1[4]
DMI_TXN2[4]
DMI_TXN3[4]
DMI_TXP0[4]
DMI_TXP1[4]
DMI_TXP2[4]
DMI_TXP3[4]
+1.05V_PCH
SYS_PWROK
R297 49.9/F_4R297 49.9/F_4
R17 750/F_4R17 750/F_4
R324 *0_0402short_NCR324 *0_0402short_NC
R322 *0_0402short_NCR322 *0_0402short_NC
R385 *0_0402short_NCR385 *0_0402short_NC
DMI_COMP
DMI2RBIAS
ME_SUS_PWR_ACK
SYS_RESET#
SYS_PWROK_R
PWROK_R
APWROK_R
RSMRST#
ME_SUS_PWR_ACK
AC_PRESENT
PM_BATLOW#
PM_RI#
D D
DMI_ZCOMP, DMI_IRCOMP 4mil
C C
EC_PWROK[23]
PM_DRAM_PWRGD[5]
ME_SUS_PWR_ACK[23]
SIO_PWRBTN#[23]
B B
4
3
Cougar Point (DMI,FDI,PM)
U16C
U16C
BC24
DMI0RXN
BE20
DMI1RXN
BG18
DMI2RXN
BG20
DMI3RXN
BE24
DMI0RXP
BC20
DMI1RXP
BJ18
DMI2RXP
BJ20
DMI3RXP
AW24
DMI0TXN
AW20
DMI1TXN
BB18
DMI2TXN
AV18
DMI3TXN
AY24
DMI0TXP
AY20
DMI1TXP
AY18
DMI2TXP
AU18
DMI3TXP
BJ24
DMI_ZCOMP
BG25
DMI_IRCOMP
BH21
DMI2RBIAS
C12
SUSACK#
K3
SYS_RESET#
P12
SYS_PWROK
L22
PWROK
L10
APWROK
B13
DRAMPWROK
C21
RSMRST#
K16
SUSWARN#/SUSPWRDNACK/GPIO30
E20
H20
E10
A10
CougarPoint_R1P0
CougarPoint_R1P0
DSW
PWRBTN#
ACPRESENT / GPIO31
BATLOW# / GPIO72
RI#
DMI
FDI
DMI
FDI
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1
DSWVRMEN
+3V
CLKRUN# / GPIO32
+3V_S5
SUS_STAT# / GPIO61
+3V_S5
SUSCLK / GPIO62
+3V_S5
SLP_S5# / GPIO63
System Power Management
System Power Management
+3V_S5
DSW
+3V_S5
+3V_S5
SLP_LAN# / GPIO29
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
FDI_INT
DPWROK
WAKE#
SLP_S4#
SLP_S3#
SLP_A#
SLP_SUS#
PMSYNCH
BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9
BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9
AW16
AV12
BC10
AV14
BB10
DSWVRMEN
A18
RSMRST#
E22
PCIE_WAKE#
B9
CLKRUN#
N3
G8
SUSCLK
N14
D10
SLP_S4#
H4
F4
G10
W/O support iAMT
G16
W/O support Deep Sx
AP14
SIO_SLP_LAN#
K14
FDI_TXN0 [4]
FDI_TXN1 [4]
FDI_TXN2 [4]
FDI_TXN3 [4]
FDI_TXN4 [4]
FDI_TXN5 [4]
FDI_TXN6 [4]
FDI_TXN7 [4]
FDI_TXP0 [4]
FDI_TXP1 [4]
FDI_TXP2 [4]
FDI_TXP3 [4]
FDI_TXP4 [4]
FDI_TXP5 [4]
FDI_TXP6 [4]
FDI_TXP7 [4]
FDI_INT [4]
FDI_FSYNC0 [4]
FDI_FSYNC1 [4]
FDI_LSYNC0 [4]
FDI_LSYNC1 [4]
02/20 Pre-ES1 can Stuff R8292 for timing
PCIE_WAKE# [24]
CLKRUN# [23]
refer UM9
TP10TP10
TP2TP2
T2T2
W/O support
SIO_SLP_S3# [7,23]
H_PM_SYNC [5]
T3T3
W/O support iAMT
2
SIO_SLP_S5# [23]
1
PCH Pull-high/low(CLG)
PM_RI#
PM_BATLOW#
PCIE_WAKE#
10k, Follow HR_DG_v1.0 P200(Intel)
SIO_SLP_LAN#
ME_SUS_PWR_ACK
AC_PRESENT
CLKRUN#
SYS_RESET#
RSMRST#
SYS_PWROK_R
On Die DSW VR Enable
High = Enable (Default)
Low = Disable
R419 10K_4R419 10K_4
R116 8.2K/J_4R116 8.2K/J_4
R407 10K_4R407 10K_4
R134 10K_4R134 10K_4
R420 10K_4R420 10K_4
R130 10K_4R130 10K_4
DSWVRMEN
R326 8.2K/J_4R326 8.2K/J_4
R353 8.2K/J_4R353 8.2K/J_4
R119 10K_4R119 10K_4
R325 10K_4R325 10K_4
+RTC_CELL
R439
R439
330K/J_4
330K/J_4
R435
R435
*330K/J_4_NC
*330K/J_4_NC
+3.3V_SUS
+3.3V_RUN
System PWR_OK(CLG)
+3.3V_SUS
check use IMVP_PWRGD to enable SYS_PWROK
C58
C58
0.1U/10V/X7R_4
0.1U/10V/X7R_4
U1
U1
A A
SYS_PWROK[5]
SYS_PWROK
4
TC7SH08FU
TC7SH08FU
http://hobi-elektronika.net
5
4
3
2
EC_PWROK
1
3 5
R319
R319
100K_4
100K_4
2
IMVP_PWRGD [23,40]
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Monday, January 24, 2011
Monday, January 24, 2011
Monday, January 24, 2011
Date: Sheet of
Date: Sheet of
Date: Sheet
PROJECT :
Cougar Point 1/7
Cougar Point 1/7
Cougar Point 1/7
R03/V03
R03/V03
R03/V03
of
942
942
942
1
2A
2A
2A
5
4
3
2
1
Cougar Point (LVDS,DDI)
U16D
U16D
PANEL_BKEN[23]
ENVDD[23]
BIA_PWM[18]
D D
LCD_DDCCLK[18]
LCD_DDCDAT[18]
R33 2.37K/F_4R33 2.37K/F_4
T1T1
1231 change R33 PN for ST interanl notice
INT_TXLCLKOUTN[18]
INT_TXLCLKOUTP[18]
INT_TXLOUTN0[18]
INT_TXLOUTN1[18]
INT_TXLOUTN2[18]
INT_TXLOUTP0[18]
INT_TXLOUTP1[18]
INT_TXLOUTP2[18]
INT_TXUCLKOUTN[18]
C C
INT_TXUCLKOUTP[18]
INT_TXUOUTN0[18]
INT_TXUOUTN1[18]
INT_TXUOUTN2[18]
INT_TXUOUTP0[18]
INT_TXUOUTP1[18]
INT_TXUOUTP2[18]
INT_CRT_BLU[24]
INT_CRT_GRE[24]
INT_CRT_RED[24]
INT_DDCCLK[24]
INT_DDCDAT[24]
B B
INT_CRT_HSYNC[24]
INT_CRT_VSYNC[24]
LCD_DDCCLK
LCD_DDCDAT
DIS_L_CTRL_CLK
DIS_L_CTRL_DATA
LVDS_VBG
INT_CRT_BLU
INT_CRT_GRE
INT_CRT_RED
INT_CRT_HSYNC_R
INT_CRT_VSYNC_R
DAC_IREF
R51
R51
1K_4
1K_4
R place close to PCH
R74 150/F_4R74 150/F_4
R64 150/F_4R64 150/F_4
R52 150/F_4R52 150/F_4
LCD_DDCDAT
A A
LCD_DDCCLK
DIS_L_CTRL_CLK
DIS_L_CTRL_DATA
ENVDD
R389 2.2KR389 2.2K
R50 2.2KR50 2.2K
R61 2.2KR61 2.2K
R96 2.2KR96 2.2K
R73 100K_4R73 100K_4
M45
LVDS_IBG
AF37
AF36
AE48
AE47
AK39
AK40
AN48
AM47
AK47
AJ48
AN47
AM49
AK49
AJ47
AF40
AF39
AH45
AH47
AF49
AF45
AH43
AH49
AF47
AF43
M40
M47
M49
R383 20/F_4R383 20/F_4
R382 20/F_4R382 20/F_4
INT_CRT_BLU
INT_CRT_GRE
INT_CRT_RED
5
J47
L_BKLTEN
L_VDD_EN
P45
L_BKLTCTL
T40
L_DDC_CLK
K47
L_DDC_DATA
T45
L_CTRL_CLK
P39
L_CTRL_DATA
LVD_IBG
LVD_VBG
LVD_VREFH
LVD_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LVDSB_CLK#
LVDSB_CLK
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
N48
CRT_BLUE
P49
CRT_GREEN
T49
CRT_RED
T39
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_VSYNC
T43
DAC_IREF
T42
CRT_IRTN
CougarPoint_R1P0
CougarPoint_R1P0
12
INT_CRT_HSYNC_R
INT_CRT_VSYNC_R
+3.3V_RUN
SDVO_TVCLKINN
SDVO_TVCLKINP
SDVO_STALLN
SDVO_STALLP
SDVO_INTN
SDVO_INTP
SDVO_CTRLCLK
SDVO_CTRLDATA
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
LVDS
LVDS
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
Digital Display Interface
Digital Display Interface
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPD_AUXN
DDPD_AUXP
CRT
CRT
DDPD_HPD
INT_CRT_RED
INT_CRT_GRE
INT_CRT_BLU
AP43
AP45
AM42
AM40
AP39
AP40
P38
M39
AT49
AT47
AT40
AV42
DDPB_0N
AV40
DDPB_0P
AV45
DDPB_1N
AV46
DDPB_1P
AU48
DDPB_2N
AU47
DDPB_2P
AV47
DDPB_3N
AV49
DDPB_3P
P46
P42
AP47
AP49
AT38
AY47
DDPC_0N
AY49
DDPC_0P
AY43
DDPC_1N
AY45
DDPC_1P
BA47
DDPC_2N
BA48
DDPC_2P
BB47
DDPC_3N
BB49
DDPC_3P
M43
M36
AT45
AT43
BH41
BB43
DDPD_0N
BB45
DDPD_0P
BF44
DDPD_1N
BE44
DDPD_1P
BF42
DDPD_2N
BE42
DDPD_2P
BJ42
DDPD_3N
BG42
DDPD_3P
22P
22P
C680
C680
EMI solution
4
INT_HDMI_TXDN2_C
INT_HDMI_TXDP2_C
INT_HDMI_TXDN1_C
INT_HDMI_TXDP1_C
INT_HDMI_TXDN0_C
INT_HDMI_TXDP0_C
INT_HDMI_TXCN_C
INT_HDMI_TXCP_C
22P
C681
C681
22P
C682
C682
22P
22P
INT_HDMI_HPD [19]
C659 0.1U/10V_4C659 0.1U/10V_4
C661 0.1U/10V_4C661 0.1U/10V_4
C654 0.1U/10V_4C654 0.1U/10V_4
C655 0.1U/10V_4C655 0.1U/10V_4
C649 0.1U/10V_4C649 0.1U/10V_4
C653 0.1U/10V_4C653 0.1U/10V_4
C644 0.1U/10V_4C644 0.1U/10V_4
C648 0.1U/10V_4C648 0.1U/10V_4
HDMI_SCL [19]
HDMI_SDA [19]
INT. HDMI
INT_HDMI_TXN2 [19]
INT_HDMI_TXP2 [19]
INT_HDMI_TXN1 [19]
INT_HDMI_TXP1 [19]
INT_HDMI_TXN0 [19]
INT_HDMI_TXP0 [19]
INT_HDMI_TXCN [19]
INT_HDMI_TXCP [19]
http://hobi-elektronika.net
3
Cougar Point (GND)
U16I
U16I
AY4
VSS[159]
AY42
VSS[160]
AY46
VSS[161]
AY8
VSS[162]
B11
VSS[163]
B15
VSS[164]
B19
VSS[165]
B23
VSS[166]
B27
VSS[167]
B31
VSS[168]
B35
VSS[169]
B39
VSS[170]
B7
VSS[171]
F45
VSS[172]
BB12
VSS[173]
BB16
VSS[174]
BB20
VSS[175]
BB22
VSS[176]
BB24
VSS[177]
BB28
VSS[178]
BB30
VSS[179]
BB38
VSS[180]
BB4
VSS[181]
BB46
VSS[182]
BC14
VSS[183]
BC18
VSS[184]
BC2
VSS[185]
BC22
VSS[186]
BC26
VSS[187]
BC32
VSS[188]
BC34
VSS[189]
BC36
VSS[190]
BC40
VSS[191]
BC42
VSS[192]
BC48
VSS[193]
BD46
VSS[194]
BD5
VSS[195]
BE22
VSS[196]
BE26
VSS[197]
BE40
VSS[198]
BF10
VSS[199]
BF12
VSS[200]
BF16
VSS[201]
BF20
VSS[202]
BF22
VSS[203]
BF24
VSS[204]
BF26
VSS[205]
BF28
VSS[206]
BD3
VSS[207]
BF30
VSS[208]
BF38
VSS[209]
BF40
VSS[210]
BF8
VSS[211]
BG17
VSS[212]
BG21
VSS[213]
BG33
VSS[214]
BG44
VSS[215]
BG8
VSS[216]
BH11
VSS[217]
BH15
VSS[218]
BH17
VSS[219]
BH19
VSS[220]
H10
VSS[221]
BH27
VSS[222]
BH31
VSS[223]
BH33
VSS[224]
BH35
VSS[225]
BH39
VSS[226]
BH43
VSS[227]
BH7
VSS[228]
D3
VSS[229]
D12
VSS[230]
D16
VSS[231]
D18
VSS[232]
D22
VSS[233]
D24
VSS[234]
D26
VSS[235]
D30
VSS[236]
D32
VSS[237]
D34
VSS[238]
D38
VSS[239]
D42
VSS[240]
D8
VSS[241]
E18
VSS[242]
E26
VSS[243]
G18
VSS[244]
G20
VSS[245]
G26
VSS[246]
G28
VSS[247]
G36
VSS[248]
G48
VSS[249]
H12
VSS[250]
H18
VSS[251]
H22
VSS[252]
H24
VSS[253]
H26
VSS[254]
H30
VSS[255]
H32
VSS[256]
H34
VSS[257]
F3
VSS[258]
CougarPoint_R1P0
CougarPoint_R1P0
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
2
H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28
U16H
U16H
H5
VSS[0]
AA17
VSS[1]
AA2
VSS[2]
AA3
VSS[3]
AA33
VSS[4]
AA34
VSS[5]
AB11
VSS[6]
AB14
VSS[7]
AB39
VSS[8]
AB4
VSS[9]
AB43
VSS[10]
AB5
VSS[11]
AB7
VSS[12]
AC19
VSS[13]
AC2
VSS[14]
AC21
VSS[15]
AC24
VSS[16]
AC33
VSS[17]
AC34
VSS[18]
AC48
VSS[19]
AD10
VSS[20]
AD11
VSS[21]
AD12
VSS[22]
AD13
VSS[23]
AD19
VSS[24]
AD24
VSS[25]
AD26
VSS[26]
AD27
VSS[27]
AD33
VSS[28]
AD34
VSS[29]
AD36
VSS[30]
AD37
VSS[31]
AD38
VSS[32]
AD39
VSS[33]
AD4
VSS[34]
AD40
VSS[35]
AD42
VSS[36]
AD43
VSS[37]
AD45
VSS[38]
AD46
VSS[39]
AD8
VSS[40]
AE2
VSS[41]
AE3
VSS[42]
AF10
VSS[43]
AF12
VSS[44]
AD14
VSS[45]
AD16
VSS[46]
AF16
VSS[47]
AF19
VSS[48]
AF24
VSS[49]
AF26
VSS[50]
AF27
VSS[51]
AF29
VSS[52]
AF31
VSS[53]
AF38
VSS[54]
AF4
VSS[55]
AF42
VSS[56]
AF46
VSS[57]
AF5
VSS[58]
AF7
VSS[59]
AF8
VSS[60]
AG19
VSS[61]
AG2
VSS[62]
AG31
VSS[63]
AG48
VSS[64]
AH11
VSS[65]
AH3
VSS[66]
AH36
VSS[67]
AH39
VSS[68]
AH40
VSS[69]
AH42
VSS[70]
AH46
VSS[71]
AH7
VSS[72]
AJ19
VSS[73]
AJ21
VSS[74]
AJ24
VSS[75]
AJ33
VSS[76]
AJ34
VSS[77]
AK12
VSS[78]
AK3
VSS[79]
CougarPoint_R1P0
CougarPoint_R1P0
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Monday, January 24, 2011
Monday, January 24, 2011
Monday, January 24, 2011
Date: Sheet of
Date: Sheet of
Date: Sheet
PROJECT :
Cougar Point 2/7
Cougar Point 2/7
Cougar Point 2/7
R03/V03
R03/V03
R03/V03
1
AK38
VSS[80]
AK4
VSS[81]
AK42
VSS[82]
AK46
VSS[83]
AK8
VSS[84]
AL16
VSS[85]
AL17
VSS[86]
AL19
VSS[87]
AL2
VSS[88]
AL21
VSS[89]
AL23
VSS[90]
AL26
VSS[91]
AL27
VSS[92]
AL31
VSS[93]
AL33
VSS[94]
AL34
VSS[95]
AL48
VSS[96]
AM11
VSS[97]
AM14
VSS[98]
AM36
VSS[99]
AM39
VSS[100]
AM43
VSS[101]
AM45
VSS[102]
AM46
VSS[103]
AM7
VSS[104]
AN2
VSS[105]
AN29
VSS[106]
AN3
VSS[107]
AN31
VSS[108]
AP12
VSS[109]
AP19
VSS[110]
AP28
VSS[111]
AP30
VSS[112]
AP32
VSS[113]
AP38
VSS[114]
AP4
VSS[115]
AP42
VSS[116]
AP46
VSS[117]
AP8
VSS[118]
AR2
VSS[119]
AR48
VSS[120]
AT11
VSS[121]
AT13
VSS[122]
AT18
VSS[123]
AT22
VSS[124]
AT26
VSS[125]
AT28
VSS[126]
AT30
VSS[127]
AT32
VSS[128]
AT34
VSS[129]
AT39
VSS[130]
AT42
VSS[131]
AT46
VSS[132]
AT7
VSS[133]
AU24
VSS[134]
AU30
VSS[135]
AV16
VSS[136]
AV20
VSS[137]
AV24
VSS[138]
AV30
VSS[139]
AV38
VSS[140]
AV4
VSS[141]
AV43
VSS[142]
AV8
VSS[143]
AW14
VSS[144]
AW18
VSS[145]
AW2
VSS[146]
AW22
VSS[147]
AW26
VSS[148]
AW28
VSS[149]
AW32
VSS[150]
AW34
VSS[151]
AW36
VSS[152]
AW40
VSS[153]
AW48
VSS[154]
AV11
VSS[155]
AY12
VSS[156]
AY22
VSS[157]
AY28
VSS[158]
of
10 42
10 42
10 42
2A
2A
2A
5
C557 18P/50V/C0G_4C557 18P/50V/C0G_4
23
Y3
Y3
32.768KHZ
32.768KHZ
D D
C C
B B
C556 18P/50V/C0G_4C556 18P/50V/C0G_4
ACZ_BITCLK_AUDIO[25]
ACZ_SYNC_AUDIO[25]
ACZ_RST#_AUDIO[23,25]
PCH_MELOCK[23]
ACZ_SDOUT_AUDIO[25]
R105 10K_4R105 10K_4
SMIB# change to High active,
PD 10k to GND
4 1
+RTC_CELL
ACZ_SPKR[25]
ACZ_SDIN0[25]
SMI
PCH_SPI_CLK[27]
PCH_SPI_CS0#[27]
PCH_SPI_SI[27]
PCH_SPI_SO[27]
R438
R438
10M/J_4
10M/J_4
R135 1M/J_4R135 1M/J_4
C179 *27P_NC
C179 *27P_NC
R111 33_4R111 33_4
R112 33_4R112 33_4
R107 33_4R107 33_4
R152 1K_4R152 1K_4
R157 33_4R157 33_4
SMI[24]
TP27TP27
TP8TP8
TP4TP4
TP26TP26
PCH_SPI_SI
PCH_SPI_SO
RTC_X1
RTC_X2
RTC_RST#
SRTC_RST#
SM_INTRUDER#
PCH_INTVRMEN
SMI
1 2
R323 *0_short_NCR323 *0_short_NC
Cougar Point (HDA,JTAG,SATA)
50
50
ACZ_BITCLK_R
ACZ_SYNC_R
ACZ_SPKR
ACZ_RST#_R
TP33TP33
ACZ_SDOUT
PCH_JTAG_TCK
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
C477
C477
*22P_NC
*22P_NC
4
U16A
U16A
A20
RTCX1
C20
RTCX2
D20
RTCRST#
G22
SRTCRST#
K22
INTRUDER#
C17
INTVRMEN
N34
HDA_BCLK
L34
HDA_SYNC
T10
SPKR
K34
HDA_RST#
E34
HDA_SDIN0
G34
HDA_SDIN1
C34
HDA_SDIN2
A34
HDA_SDIN3
A36
HDA_SDO
C36
HDA_DOCK_EN# / GPIO33
N32
HDA_DOCK_RST# / GPIO1 3
J3
JTAG_TCK
H7
JTAG_TMS
K5
JTAG_TDI
H1
JTAG_TDO
T3
SPI_CLK
Y14
SPI_CS0#
T1
SPI_CS1#
V4
SPI_MOSI
U3
SPI_MISO
CougarPoint_R1P0
CougarPoint_R1P0
RTCIHDA
RTCIHDA
JTAG
JTAG
SPI
SPI
+3V
+3V
LPC
LPC
FWH4 / LFRAME#
+3V
LDRQ1# / GPIO23
SATA 6G
SATA 6G
+3V
SATA
SATA
+3V_S5
SATA3RCOMPO
SATA0GP / GPIO21
SATA1GP / GPIO19
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
LDRQ0#
SERIRQ
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATAICOMPO
SATAICOMPI
SATA3COMPI
SATA3RBIAS
SATALED#
C38
A38
B37
C37
D36
LPC_LDRQ0#
E36
LPC_LDRQ1#
K36
IRQ_SERIRQ
V5
AM3
AM1
AP7
AP5
AM10
AM8
AP11
AP10
AD7
AD5
AH5
AH4
AB8
AB10
AF3
AF1
Y7
Y5
AD3
AD1
Y3
Y1
AB3
AB1
Y11
Y10
AB12
AB13
AH1
PCH_SATA_LED#
P3
SATA_DET0#
V14
P1
SATA_COMP
SATA3_COMP
SATA3_RBIAS
BBS_BIT0
3
TP9TP9
TP3TP3
R43 37.4/F_4R43 37.4/F_4
R39 49.9/F_4R39 49.9/F_4
R318 750/F_4R318 750/F_4
PCH_SATA_LED# [29]
LPC_LAD0 [23,24]
LPC_LAD1 [23,24]
LPC_LAD2 [23,24]
LPC_LAD3 [23,24]
LPC_LFRAME# [23,24]
IRQ_SERIRQ [23]
BBS_BIT0 [12]
SATA_RXN0 [21]
SATA_RXP0 [21]
SATA_TXN0 [21]
SATA_TXP0 [21]
SATA_RXN1 [21]
SATA_RXP1 [21]
SATA_TXN1 [21]
SATA_TXP1 [21]
SATA_RXN4 [20]
SATA_RXP4 [20]
SATA_TXN4 [20]
SATA_TXP4 [20]
+1.05V_PCH
Take care while using
GPIO19 for Hot P lug
function
2
SATA HDD/SSD
SATA ODD
ESATA
IRQ_SERIRQ
SATA_DET0#
PCH JTAG Debug (CLG)
5% fine (Intel), 2 1 0 -> 2 0 0 (P D D G, Intel)
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TCK
R8356 change 4.7kohm
to 51ohm 5/3 (Inte l)
+RTC_CELL
1
R34 10K/J_4R34 10K/J_4
R45 10K/J_4R45 10K/J_4
MP remove(Intel)
R110 200_4R110 200_4
R76 200_4R76 200_4
R375 200_4R375 200_4
R98 100_4R98 100_4
1 2
R77 100_4R77 100_4
1 2
R376 100_4R376 100_4
1 2
R367 51_4R367 51_4
R121 20KR121 20K
R132 20KR132 20K
+3.3V_RUN
+3.3V_SUS
RTC_RST#
SRTC_RST#
C162
C162
1U/6.3V/X5R_4
1U/6.3V/X5R_4
C174
C174
1U/6.3V/X5R_4
1U/6.3V/X5R_4
PCH Strap Table
Pin Name Strap description
SPKR
HDA_SDO
A A
Del 0510
INTVRMEN
HDA_SYNC
No reboot mode setting PWROK
Integrated 1.05V VRM enable ALWAYS
On-Die PLL VR Volatge Select RSMRST
5
Sampled
PWROKFlash Descriptor Security
Configuration
0 = Default (weak pull-down 20K)
1 = Setting to No-Reboot mode
0 = Default (weak pull-down 20K)
1 = Override
Remove SPI_MOSI from P CH strappi ng, HR_C/L_v0.91
Should be always pull-up
0 = Support by 1.8V (weak PD)
1 = Support by 1.5V
4
note
+3.3V_SUS
+3.3V_SUS
+RTC_CELL
+3.3V_SUS
R41 *1K_4_NCR41 *1K_4_NC
R146 *1K_4_NCR146 *1K_4_NC
R434 330K/J_4R434 330K/J_4
R118 1K_4R118 1K_4
ACZ_SPKR
ACZ_SDOUT
PCH_INTVRMEN
ACZ_SYNC_R
http://hobi-elektronika.net
3
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Monday, January 24, 2011
Monday, January 24, 2011
Monday, January 24, 2011
Date: Sheet of
Date: Sheet of
2
Date: Sheet
PROJECT :
Cougar Point 3/7
Cougar Point 3/7
Cougar Point 3/7
R03/V03
R03/V03
R03/V03
1
of
11 42
11 42
11 42
2A
2A
2A
5
PCI/USBOC# Pull-up(CLG)
+3.3V_RUN
R1038.2K/J_4 R1038.2K/J_4
R1158.2K/J_4 R1158.2K/J_4
R1288.2K/J_4 R1288.2K/J_4
R1248.2K/J_4 R1248.2K/J_4
R12910K_4 R12910K_4
R10910K_4 R10910K_4
D D
USB_OC2#
USB_OC1#
USB_OC5# USB_OC3#
USB_OC6#
C C
R1618.2K/J_4 R1618.2K/J_4
R11310K_4 R11310K_4
R148*10K_4_NC R148*10K_4_NC
+3.3V_SUS
10
9
8
7 4
R31710K_4 R31710K_4
R424
R424
10KX8
10KX8
change SMIB# to SMI
swap pin cause MODC_EN follow 14"
TEST_WOOFER_EN[26]
VIA USB3.0 Drop now,
no need VIA_LP net
PCIE_MCARD2_DET#[24]
B B
A A
PCH_IRQH_GPIO2[21]
SATA_ODD_DA#[21]
KB_LED_DET[28]
Check with BIOS program
or not? (have to be not)
CLK_33M_LPC[24]
CLK_33M_KBC[23]
CLK_PCI_FB[13]
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCIE_MCARD2_DET#
BT_DET#
PCH_IRQH_GPIO2
SATA_ODD_DA#
TEST_WOOFER_EN
GPIO5
R15410K_4 R15410K_4
USB_OC0#
1
SIO_EXT_WAKE#
2
USB_OC4#
3
56
TEST_WOOFER_EN
TP41TP41
TP7TP7
R398 22_4R398 22_4
R394 22_4R394 22_4
R97 22_4R97 22_4
CLK_33M_LPC
C51810P/50V/C0G_4 C51810P/50V/C0G_4
CLK_33M_KBC
C51210P/50V/C0G_4 C51210P/50V/C0G_4
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
BT_DET#
BBS_BIT1
PCIE_MCARD2_DET#
PCH_IRQH_GPIO2
SATA_ODD_DA#
KB_LED_DET
GPIO5
PCI_PME#
PCI_PLTRST#
CLK_33M_LPC_R
CLK_33M_KBC_R
Cougar Point-M (PCI,USB,NVRAM)
U16E
U16E
BG26
TP1
BJ26
TP2
BH25
TP3
BJ16
TP4
BG16
TP5
AH38
TP6
AH37
TP7
AK43
TP8
AK45
TP9
C18
TP10
N30
TP11
H3
TP12
AH12
TP13
AM4
TP14
AM5
TP15
Y13
TP16
K24
TP17
L24
TP18
AB46
TP19
AB45
TP20
B21
TP21
M20
TP22
AY16
TP23
BG46
TP24
BE28
TP25
BC30
TP26
BE32
TP27
BJ32
TP28
BC28
TP29
BE30
TP30
BF32
TP31
BG32
TP32
AV26
TP33
BB26
TP34
AU28
TP35
AY30
TP36
AU26
TP37
AY26
TP38
AV28
TP39
AW30
TP40
K40
PIRQA#
K38
PIRQB#
H38
PIRQC#
G38
PIRQD#
C46
REQ1# / GPIO50
C44
REQ2# / GPIO52
E40
REQ3# / GPIO54
D47
GNT1# / GPIO51
E42
GPIO55
GNT2# / GPIO53
F46
GNT3# / GPIO55
G42
PIRQE# / GPIO2
G40
PIRQF# / GPIO3
C42
PIRQG# / GPIO4
D44
PIRQH# / GPIO5
K10
PME#
C6
PLTRST#
H49
CLKOUT_PCI0
H43
CLKOUT_PCI1
J48
CLKOUT_PCI2
K42
CLKOUT_PCI3
H40
CLKOUT_PCI4
CougarPoint_R1P0
CougarPoint_R1P0
4
RSVD
RSVD
PCI
PCI
+5V
+5V
+5V
USB
USB
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
SV_SET_UP
High = Strong (Default)
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
USBRBIAS#
USBRBIAS
AY7
AV7
AU3
BG4
AT10
BC8
AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6
AV5
AV10
AT8
AY5
BA2
AT12
BF3
C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32
C33
B33
A14
K20
B17
C16
L16
A16
D14
C14
USB_BIAS
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
SIO_EXT_WAKE#CLK_PCI_FB_R
3
TP6TP6
TP5TP5
USBP1N [20]
USBP1P [20]
USBP2N [24]
USBP2P [24]
USBP4N [24]
USBP4P [24]
USBP5N [24]
USBP5P [24]
USBP8N [22]
USBP8P [22]
USBP9N [24]
USBP9P [24]
USBP10N [28]
USBP10P [28]
USBP11N [18]
USBP11P [18]
USBP12N [27]
USBP12P [27]
R413 22.6/F_4R413 22.6/F_4
USB_OC0# [20]
USB_OC1# [24]
SIO_EXT_WAKE# [23]
USB2.0 &ESATA LEFT
USB2.0 RIGHT
WLAN
WWAN
BT
CARD READER
Express card
Biometric
Camera
Touch Screen
2
PLTRST#(CLG)
+3.3V_SUS
C527
C527
*0.1U/10V/X7R_4_NC
*0.1U/10V/X7R_4_NC
PCI_PLTRST#
Pin Name Strap description
GNT2# / GPIO53
GNT3# / GPIO55
GNT1# / GPIO51
GPIO19
BBS_BIT1
BBS_BIT0[11]
DF_TVS
follow CheckList_1.5, DF_TVS pu-high 2,2k only, Remove R315
ESI strap (Server only) PWROK
Top-Block Swap Override
Boot BIOS Selection 1 [bit-1]
Boot BIOS Selection 0 [bit-0]
R102 *1K_4_NCR102 *1K_4_NC
R327 *1K_4_NCR327 *1K_4_NC
DMI and FDI Tx/Rx
Termination Voltage
R314 2.2KR314 2.2K
2
1
U3
U3
3 5
*TC7SH08FU_NC
*TC7SH08FU_NC
R406 *0_0402short_NCR406 *0_0402short_NC
Sampled
PWROK
PWROK
PWROK
PWROK
+1.8V_RUN
DF_TVS [14]
4
Defined in EDS (Intel)
PLTRST#
R93
R93
100K_4
100K_4
Configuration
Should not be pull-down
(weak pull-up 20K)
0 = "top-block swap" mode
1 = Default (weak pull-up 20K)
Default weak pull-up on GNT0/1#
[Need external pull-down for LPC
BIOS]
weak pull-down 20kohm
CheckList_1.0 p58; HR_v1.0 p450
1
PLTRST# [5,23,24]
Bit 1Bit 0
Boot Location
11
00
SPI
LPC
*
EMI solution pop C518, C512
5
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
http://hobi-elektronika.net
4
3
2
Size Document Number Rev
Monday, January 24, 2011
Monday, January 24, 2011
Monday, January 24, 2011
Date: Sheet of
Date: Sheet of
Date: Sheet
PROJECT :
Cougar Point 4/7
Cougar Point 4/7
Cougar Point 4/7
R03/V03
R03/V03
R03/V03
1
of
12 42
12 42
12 42
2A
2A
2A
5
Cougar Point-M (PCI-E,SMBUS,CLK)
WLAN
WWAN
D D
USB 3.0
LAN
Express card
C C
WLAN
WWAN
USB3.0
B B
LAN
Express card
A A
CLKOUTFLEX0 /GPIO64
CLKOUTFLEX1 /GPIO65
CLKOUTFLEX2 /GPIO66
CLKOUTFLEX3 /GPIO67
PCIE_RXN1[24]
PCIE_RXP1[24]
PCIE_TXN1[24]
PCIE_TXP1[24]
PCIE_RXN2[24]
PCIE_RXP2[24]
PCIE_TXN2[24]
PCIE_TXP2[24]
PCIE_RXN3[24]
PCIE_RXP3[24]
PCIE_TXN3[24]
PCIE_TXP3[24]
PCIE_RXN5[24]
PCIE_RXP5[24]
PCIE_TXN5[24]
PCIE_TXP5[24]
PCIE_RXN6[24]
PCIE_RXP6[24]
PCIE_TXN6[24]
PCIE_TXP6[24]
CLK_PCIE_WLANN[24]
CLK_PCIE_WLANP[24]
PCIE_CLK_REQ0#[24]
CLK_PCIE_WMAXN[24]
CLK_PCIE_WMAXP[24]
PCIE_CLK_REQ1#[24]
CLK_PCIE_USB30N[24]
CLK_PCIE_USB30P[24]
PCIE_CLK_REQ2#[24]
CLK_PCIE_LANN[24]
CLK_PCIE_LANP[24]
PCIE_CLK_REQ4#[24]
CLK_PCIE_EXPN[24]
CLK_PCIE_EXPP[24]
PCIE_CLK_REQ5#[24]
C31 0.1U/10V/X7R_4C31 0.1U/10V/X7R_4
C30 0.1U/10V/X7R_4C30 0.1U/10V/X7R_4
C11 0.1U/10V/X7R_4C11 0.1U/10V/X7R_4
C12 0.1U/10V/X7R_4C12 0.1U/10V/X7R_4
C16 0.1U/10V/X7R_4C16 0.1U/10V/X7R_4
C14 0.1U/10V/X7R_4C14 0.1U/10V/X7R_4
C24 0.1U/10V/X7R_4C24 0.1U/10V/X7R_4
C21 0.1U/10V/X7R_4C21 0.1U/10V/X7R_4
C52 0.1U/10V/X7R_4C52 0.1U/10V/X7R_4
C46 0.1U/10V/X7R_4C46 0.1U/10V/X7R_4
add test point for XDP
CLK_PCIE_XDPN
XDP
CLK_PCIE_XDPP
Configurable as a GPIO or as a programmable output clock
which can be configured as one of the following:
33 /27 /48/ 14.318 MHz / DC Output logic ‘0’
Θ
unsupported clock output value (Default) / 27/ 14.318 MHz output to SIO/EC /48/24 MHz
33/25/27/48/24/14.318 MHz / DC Output logic ‘0’
Θ
27/14.318 output to SIO/48/24 MHz (Default)
Θ
5
T5T5
T4T4
PCIE_TXN1_C
PCIE_TXP1_C
PCIE_TXN2_C
PCIE_TXP2_C
PCIE_TXN3_C
PCIE_TXP3_C
PCIE_TXN5_C
PCIE_TXP5_C
PCIE_TXN6_LAN_C
PCIE_TXP6_LAN_C
PCIE_CLK_REQ0#
PCIE_CLK_REQ1#
PCIE_CLK_REQ2#
PCIE_CLK_REQ3#
PCIE_CLK_REQ4#
PCIE_CLK_REQ5#
PEG_B_CLKRQ#
PCIE_CLK_REQ6#
PCIE_CLK_REQ7#
BG34
BJ34
AV32
AU32
BE34
BF34
BB32
AY32
BG36
BJ36
AV34
AU34
BF36
BE36
AY34
BB34
BG37
BH37
AY36
BB36
BJ38
BG38
AU36
AV36
BG40
BJ40
AY40
BB40
BE38
BC38
AW38
AY38
AB49
AB47
AA48
AA47
AB42
AB40
AK14
AK13
Y40
Y39
V10
Y37
Y36
Y43
Y45
L12
V45
V46
L14
V40
V42
T13
V38
V37
K12
4
U16B
U16B
PERN1
PERP1
PETN1
PETP1
PERN2
PERP2
PETN2
PETP2
PERN3
PERP3
PETN3
PETP3
PERN4
PERP4
PETN4
PETP4
PERN5
PERP5
PETN5
PETP5
PERN6
PERP6
PETN6
PETP6
PERN7
PERP7
PETN7
PETP7
PERN8
PERP8
PETN8
PETP8
CLKOUT_PCIE0N
CLKOUT_PCIE0P
J2
PCIECLKRQ0# / GPIO73
CLKOUT_PCIE1N
CLKOUT_PCIE1P
M1
PCIECLKRQ1# / GPIO18
CLKOUT_PCIE2N
CLKOUT_PCIE2P
PCIECLKRQ2# / GPIO20
CLKOUT_PCIE3N
CLKOUT_PCIE3P
A8
PCIECLKRQ3# / GPIO25
CLKOUT_PCIE4N
CLKOUT_PCIE4P
PCIECLKRQ4# / GPIO26
CLKOUT_PCIE5N
CLKOUT_PCIE5P
PCIECLKRQ5# / GPIO44
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
E6
PEG_B_CLKRQ# / GPIO56
CLKOUT_PCIE6N
CLKOUT_PCIE6P
PCIECLKRQ6# / GPIO45
CLKOUT_PCIE7N
CLKOUT_PCIE7P
PCIECLKRQ7# / GPIO46
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
CougarPoint_R1P0
CougarPoint_R1P0
4
+3V_S5
PCI-E*
PCI-E*
+3V_S5
+3V_S5
CLOCKS
CLOCKS
+3V
+3V
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
+3V_S5
SMBALERT# / GPIO11
SMBCLK
SMBDATA
SML0ALERT# / GPIO60
SMBUSController
SMBUSController
SML1ALERT# / PCHHOT# / GPIO74
+3V_S5
+3V_S5
Link
Link
PEG_A_CLKRQ# / GPIO47
+3V
CLKOUTFLEX0 / GPIO 6 4
+3V
CLKOUTFLEX1 / GPIO 6 5
+3V
CLKOUTFLEX2 / GPIO 6 6
+3V
CLKOUTFLEX3 / GPIO 6 7
FLEX CLOCKS
FLEX CLOCKS
SML0CLK
SML0DATA
SML1CLK / GPIO58
SML1DATA / GPIO75
CL_CLK1
CL_DATA1
CL_RST1#
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKOUT_DP_N
CLKOUT_DP_P
CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_GND1_N
CLKIN_GND1_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKIN_SATA_N
CLKIN_SATA_P
REFCLK14IN
CLKIN_PCILOOPBACK
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
http://hobi-elektronika.net
3
PCH_SMB_ALERT#
E12
SMBCLK
H14
SMBDATA
C9
A12
SML0CLK
C8
SML0DATA
G12
PCH_GPIO74
C13
SMB_CLK_ME1
E14
SMB_DATA_ME1
M16
M7
T11
P10
PEG_A_CLKRQ#
M10
AB37
AB38
AV22
AU22
AM12
AM13
CLK_DMIN
BF18
CLK_DMIP
BE18
CLK_GND1_N
BJ30
CLK_GND1_P
BG30
CLK_BUF_DREFCLKN
G24
CLK_BUF_DREFCLKP
E24
CLK_BUF_DREFSSCLKN
AK7
CLK_BUF_DREFSSCLKP
AK5
CLK_PCH_14M
K45
CLK_PCI_FB
H45
XTAL25_IN
V47
XTAL25_OUT
V49
XCLK_RCOMP
Y47
CLK_48M_CARD_R
K43
F47
CLK_FLEX2
H47
CLK_VGA_27M_SS_R
K49
3
SMBCLK [24]
R4211K_4 R4211K_4
R329 90.9/F_4R329 90.9/F_4
SMBDATA [24]
+3.3V_SUS
CLK_PCI_FB [12]
R91 22_4R91 22_4
T7T7
T6T6
T8T8
DDR_HVREF_RST_PCH [5]
CLK_CPU_BCLKN [5]
CLK_CPU_BCLKP [5]
CLK_DP_N [5]
CLK_DP_P [5]
R368
R368
1M/J_4
1M/J_4
+1.05V_PCH
CLK_48M_CARD [22]
C131
C131
*22P_NC
*22P_NC
2
C480 27P
C480 27P
Y2
25MHzY225MHz
1 2
C493 27P
C493 27P
2
1
2N7002W-7-F
2N7002W-7-F
SMBCLK
SMBDATA
SMB_CLK_ME1
SMB_DATA_ME1
+3.3V_RUN
Q3
Q3
3 1
2N7002W-7-F
2N7002W-7-F
+3.3V_SUS
Q33
Q33
2
3 1
Q4
Q4
2N7002W-7-F
2N7002W-7-F
SMBus/Pull-up(CLG)
R425
R425
R330
R330
2.2K
2.2K
2.2K
2.2K
2
31
2
Q6
Q6
2
2N7002W-7-F
2N7002W-7-F
31
WLAN_SCLK [16,17,21,24]
WLAN_SDATA [16,17,21,24]
SMBCLK1 [23]
SMBDAT1 [23]
change direction
CLK_REQ/Strap Pin(CLG)
+3.3V_SUS
PCIE_CLK_REQ0#
PCIE_CLK_REQ3#
PCIE_CLK_REQ4#
PCIE_CLK_REQ5#
PCIE_CLK_REQ6#
PCIE_CLK_REQ7#
PCIE_CLK_REQ2#
PEG_B_CLKRQ#
PCIE_CLK_REQ1#
PEG_A_CLKRQ#
PCH_GPIO74
PCH_SMB_ALERT#
50
50
50
50
SMBCLK
SMBDATA
SML0CLK
SML0DATA
SMB_CLK_ME1
SMB_DATA_ME1
R334 2.2KR334 2.2K
R411 2.2KR411 2.2K
R396 2.2KR396 2.2K
R127 2.2KR127 2.2K
R351 2.2KR351 2.2K
R374 2.2KR374 2.2K
R42210K_4 R42210K_4
R12210K_4 R12210K_4
R8910K_4 R8910K_4
R39910K_4 R39910K_4
R10010K_4 R10010K_4
R12310K_4 R12310K_4
R11710K_4 R11710K_4
R10110K_4 R10110K_4
R4210K_4 R4210K_4
R9910K_4 R9910K_4
+3.3V_RUN
R34910K_4 R34910K_4
+3.3V_SUS
R9410K_4 R9410K_4
R95*10K_4_NC R95*10K_4_NC
+3.3V_SUS
Stuff for Integrated CLK Gen Mode
CLK_DMIN
CLK_DMIP
CLK_GND1_N
CLK_GND1_P
CLK_BUF_DREFCLKNCLK_VGA_27M_R
CLK_BUF_DREFCLKP
CLK_BUF_DREFSSCLKN
CLK_BUF_DREFSSCLKP
CLK_PCH_14M
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
Cougar Point 5/7
Cougar Point 5/7
Cougar Point 5/7
Monday, January 24, 2011
Monday, January 24, 2011
Monday, January 24, 2011
R25 10K_4R25 10K_4
R29 10K_4R29 10K_4
R302 10K_4R302 10K_4
1 2
R126 10K_4R126 10K_4
R125 10K_4R125 10K_4
R31 10K_4R31 10K_4
R30 10K_4R30 10K_4
R78 10K_4R78 10K_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
R03/V03
R03/V03
R03/V03
1
of
13 42
13 42
13 42
2A
2A
2A
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