Quanta PL3 Schematic

1

2

3

4

5

6

7

8

PCB STACK UP

LAYER 1 : TOP

01

LAYER 2 : SGND1
LAYER 3 : IN1
LAYER 4 : IN2

A A

LAYER 5 : VCC
LAYER 6 : BOT

VCC_CORE

MAX8736

VCC1.5

G966

VCC1.05

MAX1933

B B

VCC1.25

CRT

Page 14

LCD(WXGA 15.4)

Page 14

1.8VSUS

TPS51116

3VPCU
RVCC3
3VSUS
VCC3
5VPCU
RVCC5
5VSUS
VCC5

MAXIM
MAX8744ETJ+

C C

Page:26

SATA - HDD

Page 25

IDE - ODD

Page 25

USB PORT 0

Page 29

USB PORT 2

Page 29

USB PORT 6

Page 29

USB PORT 5

Page 29 4 IN 1 CARD

SATA

PATA

USB 2.0

PL3 Block Diagram

Intel

Merom

(35W)

Page 4,5

FSB(667/800MHZ)

R.G.B

LVDS X1

Crestline GM

Page 6,7,8,9,10,11,12,13

DMI(x2/x4)

ICH8M

Page 17,18,19,20

LPC

PC8769

32.768KHz

533/ 667 MHZ DDR II

PCI-E, 1X

PCI-E, 1X

USB4

Page 23

LAN(10/100M)
M88E8039

Page 24 Page 24

Azalia

MDC
CX20548-S
(Optional)

Page 28

CLOCK GENERATOR

ICS9LPR363

Page 3

DDRII-SODIMM1

Page 15,16

DDRII-SODIMM2

Page 15,16

PCIEMINI

AUDIO CODEC

CX20549-12Z

Page 26

RJ45

MAX 9789A

Page 27

Ext MIC

Page 26

INT SPK

Page 27

HP

Page 27

Page 31,32

D D

FAN Touch

PAD Board

Key FLASH

ROM

PCB P/N:DA0PL3MB6A7

1

2

3

4

RJ11

Page 28

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Block Diagram

Block Diagram

Block Diagram

Date: Sheet

Date: Sheet

5

6

Date: Sheet

7

PROJECT : PL3

8

A

A

138Thursday, January 11, 2007

138Thursday, January 11, 2007

138Thursday, January 11, 2007

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Page 01:
Page 02:
Page 03:
Page 04:
Page 05:
Page 06:

A A

Page 07:
Page 08:
Page 09:
Page 10:
Page 11:
Page 12:
Page 13:
Page 14:
Page 15:
Page 16:
Page 17:
Page 18:
Page 19:
Page 20:

B B

Page 21:
Page 22:
Page 23:
Page 24:
Page 25:
Page 26:
Page 27:
Page 28:
Page 29:
Page 30:
Page 31:
Page 32:
Page 33:
Page 34:

C C

Page 35:
Page 36:
Page 37:
Page 38:
Page 39:

Block diagram
Table of contents
Clock generator ICS9PR363
Merom(Host Bus)
Merom(Power)
CPU Thermal/Fan Control
Crestline A(Host)
Crestline B(VGA,DMI)
Crestline C(DDR2)
Crestline D(VCC)
Crestline E(Power)
Crestline F(VSS)
Crestline (Straps)
Panel LCD/CRT
DDR2 SODIMM
DDR2 Termination
ICH8M (Host)
ICH8M (PCIE)
ICH8M (GPIO)
ICH8M (Power)
R5C832 (PCI)
R5C832 (4in1)
SD/MS/xD Connector
PCIE LAN 88E8039
Mini PCIE/EMI
SATA/ODD Connector
CODEC(CX20549)
Audio Amplifier MAX9789A
CONEXTANT MDC
Kerboard/USB
TP/LED/SW
KBC uR PC8769
KBC PC87541
CPU CORE MAX8736
VCC1.05

1.8VSUS/VCC1.5/VCC1.25
3VPCU/5VPCU
Battery Charger
Battery Connector

Voltage Rails

Power ON S0~S2 Ctl SignalON S3 ON S4 ON S5

9VPCU
5VPCU
3VPCU

RVCC3

5VSUS
3VSUS

1.8VSUS
VCC5

VCC3

VCC1.5 1.5V
VCC1.25 1.25V
VCC1.05
SMDDR_VTERM

VCC_CORE

Power On Sequence

ACIN
5VPCU/3VPCU
NBSWON#

PWRBTN#

RVCC_ON

RSMRST#

SUSB#,SUSC#

SUSON

MAINON

VSUS,VCC

VR_ON

VCORE_CPU

Voltage

9V
5V
3V

3V

5V
3V

1.8V
5V

3V

1.05V

0.9V

By CPU

V VVV
V VVV
V

VVV

V
V

V
V
V
V

V

VVV

VV
VV
VV

From 87541

From 87541

From 87541

From 87541

From 87541

RVCC_ON

SUSON
SUSON
SUSON

MAINON
MAINON

MAINON
MAINON
MAINON
MAINON

VR_ON

PCB STACK UP

LAYER 1 : TOP
LAYER 2 : GND
LAYER 3 : IN1
LAYER 4 : IN2
LAYER 5 : VCC
LAYER 8 : BOT

PCI DEVICES IRQ ROUTING

PCI ROUTING
TABLE

REQ0# / GNT0# RICOH832

IDSEL

AD17

INTERUPT

INTA#,INTB#

DEVICE

2

PWROK

D D

1

2

PCIRST#

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

System Information

System Information

System Information

Date: Sheet

Date: Sheet

3

4

5

6

Date: Sheet

7

PROJECT : PL3

A

A

238Wednesday, January 10, 2007

238Wednesday, January 10, 2007

238Wednesday, January 10, 2007

8

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of

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1

2

3

4

5

6

7

8

Clock Generator

A A

U5

U5
ICS9LPRS365AGLFT/ SLG8SP512T

L10 BKP1608HS181-T

L10 BKP1608HS181-T

VCC3

EMI FILTER BKP1608HS181-T(180,1.5A)

EMI FILTER BKP1608HS181-T(180,1.5A)

L12 BKP1608HS181-T

L12 BKP1608HS181-T

VCC1.05

EMI FILTER BKP1608HS181-T(180,1.5A)

EMI FILTER BKP1608HS181-T(180,1.5A)

0.1U close to each VDD_IO Power pin

B B

C241

C241

10U_8

10U_8

C234

C234

.1U_4

.1U_4

SATACLKREQ#19

PCLK_DEBUG23,31

PCLK_59131

C222 33P_4C222 33P_4

<check list>
XTAL length < 500mils

C217 33P_4C217 33P_4

CLKUSB_4819

14M_ICH19

C188

C188

10U_8

10U_8

C190

C190

.1U_4

.1U_4

CPU_BSEL0
CPU_BSEL2

C236

C236
.1U_4

.1U_4

C233

C233

.1U_4

.1U_4

C232

C232

C384

C384

.1U_4

.1U_4

.1U_4

.1U_4

VDD_CK_VCC1.05

C402

C402

C189

C189

.1U_4

.1U_4

.1U_4

.1U_4

T251T251

21

Y1

Y1

14.318MHZ

14.318MHZ

R110 2.2K_4R110 2.2K_4
R158 10K_4R158 10K_4

R159 22_4R159 22_4

C235

C235
.1U_4

.1U_4

C381

C381

.1U_4

.1U_4

R121 475_4R121 475_4
R113 *33_4R113 *33_4
R101 33_4R101 33_4
R298 33_4R298 33_4

R123 33_4R123 33_4

VDD_CK_VCC3

C192

C192

C380

C380

.1U_4

.1U_4

.1U_4

.1U_4

VDD_CK_VCC1.05

C183

C183

C240

C240

10U_8

10U_8

10U_8

10U_8

VDD_CK_VCC1.05

SATACLKREQ#_R
PCLK_R5C832_R
PCLK_MINI_R
PCLK_591_R
PCI_CLK_SIO_R
PCLK_ICH_R
CG_XIN
CG_XOUT
FSA
CPU_BSEL1
FSC

ICS9LPRS365AGLFT/ SLG8SP512T

IC(64P) ICS9LPRS365BGLFT(TSSOP)

IC(64P) ICS9LPRS365BGLFT(TSSOP)

2

VDD_PCI

9

VDD_48

16

VDD_PLL3

61

VDD_REF

39

VDD_SRC

55

VDD_CPU

12

VDD_96_IO

20

VDD_PLL3_IO

26

VDD_SRC_IO_1

42

VSS_SRC3

36

VDD_SRC_IO_2

49

VDD_CPU_IO

1

PCI0/CR#_A

3

PCI1/CR#_B

4

PCI2/TME

5

PCI3

6

PCI4/SRC5_EN

7

PCIF5/ITP_EN

60

XTAL_IN

59

XTAL_OUT

10

USB_48/FSA

57

FSB/TEST/MODE

62

REF0/FSC/TESTSEL

8

VSS_PCI

11

VSS_48

15

VSS_IO

19

VSS_PLL3

52

VSS_CPU

23

VSS_SRC1

29

VSS_SRC2

45

VDD_SRC_IO_3

58

VSS_REF

ICS9LPRS365BGLFT:ALPRS365K13
SLG8SP512T: AL8SP512K05

CK505

CK505

SRC5/PCI_STOP#

SRC5#/CPU_STOP#

CKPWRGD/PWRDWN#

SRC8#/ITP#

SRC11/CR#_H

SRC11#/CR#_G

SRC7/CR#_F

SRC7#/CR#_E

SRC3/CR#_C

SRC3#/CR#_D

SRC2/SATA

SRC2#/SATA#

SRC1/SE1

SRC1#/SE2

SRC0/DOT96

SRC0#/DOT96#

IO_VOUT

SCLK

SDA

CPU0

CPU0#

CPU1

CPU1#

SRC8/ITP

SRC10#

SRC10

SRC9

SRC9#

SRC6

SRC6#

SRC4

SRC4#

48

CGCLK_SMB

64

CGDAT_SMB

63
38

37

CLK_CPU_BCLK_R

54

CLK_CPU_BCLK#_R

53

CLK_MCH_BCLK_R

51

CLK_MCH_BCLK#_R

50
47

46

CLK_PCIE_3GPLL#_R

35

CLK_PCIE_3GPLL_R

34

PCIE_CLK_RBS_R

33
32

R_CLK_PCIE_LAN

30

R_CLK_PCIE_LAN#

31
44

43

CLK_PCIE_ICH_R

41

CLK_PCIE_ICH#_R

40

CLK_PCIE_MINI_R

27

CLK_PCIE_MINI#_R

28
24

25

CLK_PCIE_SATA_R

21

CLK_PCIE_SATA#_R

22

DREFSSCLK_R

17

DREFSSCLK#_R

18

DREFCLK_R

13

DREFCLK#_R

14
56

During initial power-up be used to
sample FSB speed with FSA/B/C

RP35 0X2RP35 0X2

1
3

RP34 0X2RP34 0X2

1
3

1

RP36

RP36

3

R155 475_4R155 475_4

3

RP29

RP29

1

RP37 0X2RP37 0X2

1
3

RP30 0X2RP30 0X2

3
1

RP28 0X2RP28 0X2

3
1

3
1

RP31 0X2RP31 0X2

3
1

RP32 0X2RP32 0X2

CK_PWG 19

CGCLK_SMB 15
CGDAT_SMB 15

PM_STPPCI# 19

2
4

2
4

2
4

0X2

0X2

4
2

0X2

0X2

2
4

4
2

4
2

4
2

4
2

PM_STPCPU# 19
HCLK_CPU 4

HCLK_CPU# 4
HCLK_MCH 7

HCLK_MCH# 7

CLK_PCIE_3GPLL# 8
CLK_PCIE_3GPLL 8

CLK_MCH_OE# 8

CLK_PCIE_LAN 24
CLK_PCIE_LAN# 24

CLK_PCIE_ICH 18
CLK_PCIE_ICH# 18

CLK_PCIE_MINI 23
CLK_PCIE_MINI# 23

CLK_PCIE_SATA 17
CLK_PCIE_SATA# 17

DREFSSCLK 8
DREFSSCLK# 8

DREFCLK 8

DREFCLK# 8

C C

CPU_BSEL04

CPU_BSEL14

CPU_BSEL24

D D

R109 0_4R109 0_4

VCC1.05

R310 0_4R310 0_4

VCC1.05

R173 0_4R173 0_4 R162 0_4R162 0_4

VCC1.05

1

CPU_BSEL0_

R107 *56_4R107 *56_4
R95 1K_4R95 1K_4

CPU_BSEL1_

R161 *0_4R161 *0_4
R157 1K_4R157 1K_4

CPU_BSEL2_

R164 *0_4R164 *0_4
R163 1K_4R163 1K_4

R108 0_4R108 0_4

R165 0_4R165 0_4

2

MCH_BSEL0 8

MCH_BSEL1 8

MCH_BSEL2 8

3

BSEL Frequency Select Table

FrequencyFSAFSBFSC

0

0

1

0

0

1

1

0

1

0

1

1

1

0

1

01

1

1

1

0

0

0

4

266Mhz0

133Mhz

166Mhz

200Mhz

400Mhz

Reserved

100Mhz

333Mhz

CGCLK_SMB

CGDAT_SMB

5

PCLK_MINI_R
PCLK_ICH_R
PCI_CLK_SIO_R
SATACLKREQ#_R
PCIE_CLK_RBS_R

PCLK_ICH_R
PCI_CLK_SIO_R

R153

R153
10K_4

10K_4

Clock Gen I2C

VCC3

R154

R154
10K_4

10K_4

R297 10K_4R297 10K_4
R94 *10K_4R94 *10K_4
R124 *10K_4R124 *10K_4
R122 10K_4R122 10K_4
R156 10K_4R156 10K_4

R93 10K_4R93 10K_4
R112 10K_4R112 10K_4

Q6

2

2N7002EQ62N7002E

1

VCC3

Q5

2

2N7002EQ52N7002E

1

6

3

PCLK_SMB 19,23

change1:clock to data wrong connection b-test

3

PDAT_SMB 19,23

VCC3

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Clock Generator

Clock Generator

Clock Generator

Date: Sheet

Date: Sheet

Date: Sheet

7

PROJECT : PL3

A

A

A

of

of

of

338Wednesday, January 10, 2007

338Wednesday, January 10, 2007

338Wednesday, January 10, 2007

8

1

2

3

4

5

6

7

8

VCC1.05

12

VCC1.5

R60

R60

27.4_4

27.4_4

1 2

438Wednesday, January 10, 2007

438Wednesday, January 10, 2007

438Wednesday, January 10, 2007

4

C153

C153
.1U_4

.1U_4

A

A

A

of

8

H_A#[3..16]7

A A

H_ADSTB#07
H_REQ#[0..4]7

H_A#[17..35]7

B B

H_ADSTB#17

H_A20M#17

H_FERR#17

H_IGNNE#17
H_STPCLK#17

H_INTR17
H_NMI17
H_SMI#17

C C

Populate ITP700Flex for bringup

del r5109 -b-test

ITP_TDI
ITP_TMS
ITP_TCK
ITP_TDO ITP_DBRESET#
ITP_TRST#

H_RESET#

R174 27_4R174 27_4

D D

R175 680/F_4R175 680/F_4

H_A#[3..16]

H_REQ#[0..4]

H_A#[17..35]

T68T68
T67T67
T82T82
T72T72
T83T83
T93T93
T79T79
T27T27
T65T65
T80T80

VCC1.05

12

R166

R166
*51/F_4

*51/F_4

Layout Note:
Place R8 close ITP.

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

Layout Note:
Place R4,R361,R346 & R7 close to CPU.

12

12

R171

R171

R167

R167

51/F_4

51/F_4

39/F_4

39/F_4

ITP_TCK

12

ITP_TRST#

J4
L5
L4
K5

M3

N2
J1
N3
P5
P2
L2
P4
P1
R1

M1

K3
H2
K2
J3
L1

Y2
U5
R3

W6

U4
Y5
U1
R4
T5

T3
W2
W5

Y4

U2

V4
W3

AA4
AB2
AA3

V1

A6

A5

C4

D5

C6

B4

A3
M4

N5

T2

V3

B2

C3

D2

D22

D3

F6

12

R170

R170
150_4

150_4

U16A

U16A

A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#

ADDR GROUP 0

ADDR GROUP 0

A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#

REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#

A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#

A20M#
FERR#
IGNNE#

STPCLK#
LINT0
LINT1
SMI#

RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]
RSVD[10]

Merom Ball-out Rev 1a

Merom Ball-out Rev 1a

T64T64
T63T63
T96T96
T71T71
T92T92

T73T73

T95T95
T99T99

CONTROLXDP/ITP SIGNALS

CONTROLXDP/ITP SIGNALS

ADDR GROUP 1

ADDR GROUP 1

THERMAL

THERMAL

PROCHOT#

THERMDA
THERMDC

ICH

ICH

THERMTRIP#

H CLK

H CLK

RESERVED

RESERVED

ITP debug signals

T29T29

ADS#
BNR#

BPRI#

DEFER#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TCK
TDO

TMS

TRST#

DBR#

BCLK[0]
BCLK[1]

H1
E2
G5

H5
F21
E1

F1
D20

B3
H4
C1

F3
F4
G3
G2

G6
E4

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6

TDI

AB3
AB5
AB6
C20

D21
A24
B25

C7

A22
A21

H_IERR#

H_RESET#

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5
ITP_TCK
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
ITP_DBRESET#

ITP_DBRESET#

R89 0_4R89 0_4

R106 75_4R106 75_4

R103 *2.2K_4R103 *2.2K_4

H_THERMDA
H_THERMDC

R150 *0_4R150 *0_4

12

R80 150_4R80 150_4

12

VCC3

H_ADS# 7
H_BNR# 7
H_BPRI# 7

H_DEFER# 7
H_DRDY# 7
H_DBSY# 7

H_BR0# 7

R105 56_4R105 56_4

1 2

H_INIT# 17
H_LOCK# 7
H_RESET# 7

H_RS#0 7
H_RS#1 7
H_RS#2 7
H_TRDY# 7

H_HIT# 7
H_HITM# 7

T91T91
T97T97
T84T84
T88T88
T85T85
T78T78

SYS_RST# 19

VCC1.05

H_PROCHOT# 34
H_THERMDA 6

H_THERMDC 6
THERMTRIP#_PWR 6

PM_THRMTRIP# 8,17

HCLK_CPU 3
HCLK_CPU# 3

H_D#[0..63]7

VCC1.05

H_DSTBN#07
H_DSTBP#07
H_DINV#07

Layout Note:
Place voltage
divider within

0.5" of GTLREF
pin

VCC1.05

R53

R53
1K_4

1K_4

1 2

R52

R52
2K/F_4

2K/F_4

1 2

R75 *1K_4R75 *1K_4

1 2

R58 *1K_4R58 *1K_4

1 2

C152 *.1U_4C152 *.1U_4

FSB

H_DSTBN#17
H_DSTBP#17
H_DINV#17

CPU_BSEL03
CPU_BSEL13
CPU_BSEL23

CPU_TEST1
CPU_TEST2

CPU_TEST4

12

BCLK

533 0 0 1133

166

667
800

200

ITP disable guidelines

Signal Resistor Value Connect To Resistor Placement

150 ohm +/- 5%

TDI

39 ohm +/- 1%

TMS

500-680ohm +/- 5%

TRST#

27 ohm +/- 1%

TCK
TDO

150 ohm +/- 5%

VTT
GND
GND
VTT

Note: Populate R5, R8, C372 & R430 when ITP connector is populated.

1

2

3

4

H_D#[0..63]

H_D#[0..63]

BSEL2 BSEL1 BSEL0

0

1
1

Within 2.0" of the ITPVTT
Within 2.0" of the ITP
Within 2.0" of the ITP
Within 2.0" of the ITP
Within 2.0" of the ITP

5

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31

V_CPU_GTLREF
CPU_TEST1
CPU_TEST2
CPU_TEST3
CPU_TEST4
CPU_TEST5
CPU_TEST6

T22T22
T182T182
T153T153

1
00

U16B

U16B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

Merom Ball-out Rev 1a

Merom Ball-out Rev 1a

CPU_TEST3
CPU_TEST5
CPU_TEST6

6

H_D#[0..63]

H_D#32

Y22

DATA GRP 0 DATA GRP 1

DATA GRP 0 DATA GRP 1

DATA GRP 2DATA GRP 3

DATA GRP 2DATA GRP 3

DSTBN[2]#
DSTBP[2]#

DINV[2]#

DSTBN[3]#
DSTBP[3]#

DINV[3]#
COMP[0]

MISC

MISC

COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#

D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#

SLP#

PSI#

AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

COMP0
COMP1
COMP2
COMP3

H_DSTBN#2 7
H_DSTBP#2 7

H_D#[0..63]

Note:
H_DPRTSTP need to daisy chain
from ICH8 to IMVP6 to CPU.

H_DINV#2 7

H_DSTBN#3 7
H_DSTBP#3 7
H_DINV#3 7

ICH_DPRSTP# 8,17,34
H_DPSLP# 17
H_DPWR# 7
H_PWRGD 17
H_CPUSLP# 7
PSI# 34

Reserved for EMI.

COMP0
COMP1
COMP2
COMP3

R169

R169

R168

R168

R59

1 2

27.4_4

27.4_4

1 2

R59

54.9/F_4

54.9/F_4

54.9/F_4

54.9/F_4

1 2

Comp0,2 connect with Zo=27.4ohm,Comp1,3
connect with Zo=55ohm, make those traces
length shorter than 0.5".Trace should be
at least 25 mils away from any other
toggling signal.

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

CPU Host Bus

CPU Host Bus

CPU Host Bus

Date: Sheet of

Date: Sheet of

Date: Sheet

7

PROJECT : PL3

1

VCC_CORE

12

A A

VCC_CORE

12

C174

C174
10U_8

10U_8

C171

C171
10U_8

10U_8

12

C394

C394
10U_8

10U_8

12

C176

C176
10U_8

10U_8

8 inside cavity, north side, secondary layer.

VCC_CORE

C204

C204
10U_8

10U_8

C181

C181
10U_8

10U_8

12

C210

C210
10U_8

10U_8

12

C187

C187
10U_8

10U_8

12

B B

VCC_CORE

12

8 inside cavity, south side, secondary layer.

VCC_CORE

C215

C215
10U_8

10U_8

12

C216

C216
10U_8

10U_8

12

6 inside cavity, north side, primary layer.

VCC_CORE

C C

12

C393

C393
10U_8

10U_8

12

C388

C388
10U_8

10U_8

6 inside cavity, south side, primary layer.

VCC1.05

C185

C185
.1U_4

.1U_4

12

C186

C186
.1U_4

.1U_4

12

2

C389

C389
10U_8

10U_8

C376

C376
10U_8

10U_8

C180

C180
10U_8

10U_8

C218

C218
10U_8

10U_8

C219

C219
10U_8

10U_8

C382

C382
10U_8

10U_8

C196

C196
.1U_4

.1U_4

12

C383

C383
10U_8

10U_8

12

C371

C371
10U_8

10U_8

12

C184

C184
10U_8

10U_8

12

C172

C172
10U_8

10U_8

12

12

12

C211

C211
10U_8

10U_8

C378

C378
10U_8

10U_8

C194

C194
.1U_4

.1U_4

12

C206

C206
10U_8

10U_8

12

C375

C375
10U_8

10U_8

12

C207

C207
.1U_4

.1U_4

12

12

12

12

12

12

12

3

VCC_CORE VCC_CORE

12

C379

C379
10U_8

10U_8

12

C173

C173
10U_8

10U_8

12

C193

C193
10U_8

10U_8

12

C177

C177
10U_8

10U_8

12

C195

C195
10U_8

10U_8

12

C370

C370
10U_8

10U_8

12

C205

C205
.1U_4

.1U_4

4

U16C

U16C

A7

VCC[001]

A9

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

B7

VCC[010]

B9

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

C9

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

D9

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

E7

VCC[033]

E9

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

F7

VCC[042]

F9

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15

VCC[065]

AB17

VCC[066]

AB18

VCC[067]

Merom Ball-out Rev 1a

Merom Ball-out Rev 1a

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[01]
VCCA[02]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

.

.

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

AF7

AE7

VCCSENSE

VSSSENSE

5

ICCODE:
for Merom processors
recommended design
target is 44A

ICCP:
1before vccore stable
peak current is 4.5A

2.after vccore stable

VCC1.05

continue current is

2.5A

12

+

+

C202

C202
330U_7343

330U_7343

ICCA 130mA

H_VID0 34
H_VID1 34
H_VID2 34
H_VID3 34
H_VID4 34
H_VID5 34
H_VID6 34

6

VCC1.5

R54

R54
0_6

0_6

12

VCC_CORE

12

C156

C156
.01U_4

.01U_4

Layout Note:
Place C105 near PIN
B26.

C151

C151
10U_8

10U_8

12

R137

R137
100_4

100_4

VCCSENSE 34

12

R140

R140
100_4

100_4

VSSSENSE 34

7

U16D

U16D

A4
A8

A11
A14
A16
A19
A23
AF2

B6
B8

B11
B13
B16
B19
B21
B24

C5

C8
C11
C14
C16
C19

C2
C22
C25

D1

D4

D8
D11
D13
D16
D19
D23
D26

E3
E6

E8
E11
E14
E16
E19
E21
E24

F5

F8
F11
F13
F16
F19

F2
F22
F25

G4

G1
G23
G26

H3

H6
H21
H24

J2

J5
J22
J25

K1

K4

K23
K26

L3

L6

L21
L24

M2

M5
M22
M25

N1

N4
N23
N26

Merom Ball-out Rev 1a

Merom Ball-out Rev 1a

VSS[082]

VSS[001]
VSS[002]

VSS[083]

VSS[003]

VSS[084]

VSS[004]

VSS[085]

VSS[005]

VSS[086]

VSS[006]

VSS[087]

VSS[007]

VSS[088]

VSS[008]

VSS[089]

VSS[009]

VSS[090]

VSS[010]

VSS[091]

VSS[011]

VSS[092]

VSS[012]

VSS[093]

VSS[013]

VSS[094]

VSS[014]

VSS[095]

VSS[015]

VSS[096]

VSS[016]

VSS[097]

VSS[017]

VSS[098]

VSS[018]

VSS[099]

VSS[019]

VSS[100]

VSS[020]

VSS[101]

VSS[021]

VSS[102]

VSS[022]

VSS[103]

VSS[023]

VSS[104]

VSS[024]

VSS[105]

VSS[025]

VSS[106]

VSS[026]

VSS[107]

VSS[027]

VSS[108]

VSS[028]

VSS[109]

VSS[029]

VSS[110]

VSS[030]

VSS[111]

VSS[031]

VSS[112]

VSS[032]

VSS[113]

VSS[033]

VSS[114]

VSS[034]

VSS[115]

VSS[035]

VSS[116]

VSS[036]

VSS[117]

VSS[037]

VSS[118]

VSS[038]

VSS[119]

VSS[039]

VSS[120]

VSS[040]

VSS[121]

VSS[041]

VSS[122]

VSS[042]

VSS[123]

VSS[043]

VSS[124]

VSS[044]

VSS[125]

VSS[045]

VSS[126]

VSS[046]

VSS[127]

VSS[047]

VSS[128]

VSS[048]

VSS[129]

VSS[049]

VSS[130]

VSS[050]

VSS[131]

VSS[051]

VSS[132]

VSS[052]

VSS[133]

VSS[053]

VSS[134]

VSS[054]

VSS[135]

VSS[055]

VSS[136]

VSS[056]

VSS[137]

VSS[057]

VSS[138]

VSS[058]

VSS[139]

VSS[059]

VSS[140]

VSS[060]

VSS[141]

VSS[061]

VSS[142]

VSS[062]

VSS[143]

VSS[063]

VSS[144]

VSS[064]

VSS[145]

VSS[065]

VSS[146]

VSS[066]

VSS[147]
VSS[148]

VSS[067]
VSS[068]

VSS[149]

VSS[069]

VSS[150]

VSS[070]

VSS[151]

VSS[071]

VSS[152]

VSS[072]

VSS[153]

VSS[073]

VSS[154]

VSS[074]

VSS[155]

VSS[075]

VSS[156]

VSS[076]

VSS[157]

VSS[077]

VSS[158]

VSS[078]

VSS[159]

VSS[079]

VSS[160]

VSS[080]

VSS[161]

VSS[081]P3VSS[162]

VSS[163]

8

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

.

.

5

Layout out:
Place these inside socket cavity on North side secondary.

D D

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

CPU Power

CPU Power

CPU Power

Date: Sheet of

Date: Sheet of

1

2

3

4

5

6

Date: Sheet

7

PROJECT : PL3

A

A

A

of

538Wednesday, January 10, 2007

538Wednesday, January 10, 2007

538Wednesday, January 10, 2007

8

5

CPU Thermal Sensor

4

VCC3

3

2

1

6

D D

C C

SMBus from KBC

MBCLK31,32

MBDATA31,32

Thermal Trip

B B

THERMTRIP#_PWR4

VCC3

Q13

Q13

2

2N7002E

2N7002E

3

VCC3

Q12

Q12

2

2N7002E

2N7002E

3

DELAY_VR_PWRGOOD8,19,34

THERMTRIP#_PWR

VCC1.05

1

1

R148

R148

56.2/F_4

56.2/F_4

THERM_ALERT#19

R274

R274
10K_4

10K_4

R269

R269
10K_4

10K_4

VCC5

VCC1.05

2

1 3

R264 10K_4R264 10K_4

3

Q4

Q4
FDV301N

FDV301N

1

Q3

Q3

2

MMBT3904

MMBT3904

R265 *0_4R265 *0_4

CPUFAN#_ON

U15

U15

8

SCLK

7

SDA

6

ALERT#

4

OVERT#

MAX6657

MAX6657

ADDRESS: 98H

SYS_SHDN# 33

R289

R289
200_6

200_6

LM86VCC

C373

C373
.1U_4

.1U_4

1

VCC

2

DXP

3

DXN

5

GND

<check list>
Layout Note:Routing 10:10 mils and away
from noise source with ground gard

C367

C367
2200P_4

2200P_4

VFAN31

H_THERMDA

H_THERMDC

C360

C360
.1U_4

.1U_4

CPUFAN#_ON

VCC5

H_THERMDA 4

H_THERMDC 4

CPU FAN Control

FANSIG31

U13

U13

VIN2VO

1

/FON

4

VSET

G995

G995

GND
GND
GND
GND

3
5
6
7
8

TH_FAN_POWER

TH_FAN_POWER

C354

C354
10U_8

10U_8

C353

C353
.01U_4

.01U_4

C358

C358
*.01U_4

*.01U_4

VCC3

R259

R259
10K_4

10K_4

CN13

CN13

1
2
3

FAN-CONN

FAN-CONN

4

5

FANPWR = 1.6*VSET

<CRB & Design guide>
Layout Note: Thermal trip should connect to ICH8 & GMCH without T-ing
(ZS1 default NC)

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Thermal/FAN Control

Thermal/FAN Control

Thermal/FAN Control

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

PROJECT : PL3

1

A

A

A

638Wednesday, January 10, 2007

638Wednesday, January 10, 2007

638Wednesday, January 10, 2007

of

of

of

1

2

3

4

5

6

7

8

7

U12A

M10
N12

W10

AD12

AE3
AD9
AC9

AC7
AC14
AD11
AC11

AB2

AD7

AB1

AC6

AE2

AC5

AG3

AH8

AJ14

AE9
AE11
AH12

AH5

AE7

AE5

AH2
AH13

E2
G2
G7

M6

H7
H3
G4
F3
N8
H2

N9
H5

P13

K9

M2

Y8
V4
M3

J1
N5
N3

W6
W9

N2
Y7
Y9
P4

W3

N1

Y3

AJ9

AJ5
AJ6
AJ7

AJ2
AJ3

B3
C2

W1
W2

B6
E5

B9
A9

U12A

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

H_SWING
H_RCOMP

H_SCOMP
H_SCOMP#

H_CPURST#
H_CPUSLP#

H_AVREF
H_DVREF

CRESTLINE_1p0

CRESTLINE_1p0

H_ADSTB#_0
H_ADSTB#_1

HOST

HOST

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HIT#

H_HITM#

H_LOCK#
H_TRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_REQ#_0
H_REQ#_1

H_REQ#_2
H_REQ#_3

H_REQ#_4

H_RS#_0
H_RS#_1
H_RS#_2

J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19

G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7

K5
L2
AD13
AE13

M7
K3
AD2
AH11

L7
K2
AC2
AJ10

M14
E13
A11
H13
B12

E12
D7
D8

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

12

C327

C327
.1U_4

.1U_4

H_D#[0..63]

H_RESET#4

H_CPUSLP#4

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_SWING
H_RCOMP

H_SCOMP
H_SCOMP#

H_REF

H_D#[0..63]4

A A

VCC1.05

12

R246

R246
221_4

221_4

0.331V

H_SWING

12

R245

R245
100_4

100_4

B B

VCC1.05

C324

C324
.1U_4

.1U_4

1 2

impedance 55 ohm

12

12

R8

R9

54.9/F_4R854.9/F_4

54.9/F_4R954.9/F_4

H_SCOMP
H_SCOMP#

12

R244

R244

24.9_4

24.9_4

C C

H_RCOMP

Layout Note:
H_RCOMP trace should be
10-mil wide with 20-mil
spacing.

0.705V

VCC1.05

R248

R248
1K_4

1K_4

1 2

12

R247

R247
2K/F_4

2K/F_4

H_A#[3..35]

H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4
H_BPRI# 4
H_BR0# 4
H_DEFER# 4
H_DBSY# 4

H_DPWR# 4
H_DRDY# 4
H_HIT# 4
H_HITM# 4
H_LOCK# 4
H_TRDY# 4

H_DINV#0 4
H_DINV#1 4
H_DINV#2 4
H_DINV#3 4

H_DSTBN#0 4
H_DSTBN#1 4
H_DSTBN#2 4
H_DSTBN#3 4

H_DSTBP#0 4
H_DSTBP#1 4
H_DSTBP#2 4
H_DSTBP#3 4

H_REQ#0 4
H_REQ#1 4
H_REQ#2 4
H_REQ#3 4
H_REQ#4 4

H_RS#0 4
H_RS#1 4
H_RS#2 4

H_A#[3..35] 4

HCLK_MCH 3
HCLK_MCH# 3

Layout Note:
Place the 0.1 uF

D D

1

2

decoupling capacitor
within 100 mils from
GMCH pins.

3

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

GMCH HOST

GMCH HOST

GMCH HOST

Date: Sheet of

Date: Sheet of

4

5

6

Date: Sheet

7

PROJECT : PL3

A

A

A

of

738Wednesday, January 10, 2007

738Wednesday, January 10, 2007

738Wednesday, January 10, 2007

8

1

2

3

4

5

6

7

8

U12B

U12B

P36

RSVD1

P37

RSVD2

R35

RSVD3

N35

RSVD4

AR12

RSVD5

AR13

RSVD6

AM12

RSVD7

AN13

RSVD8

J12

RSVD9

AR37

RSVD10

AM36

CFG3
CFG4
CFG5
CFG6

CFG8
CFG9
CFG10

CFG12
CFG13

CFG16

CFG19
CFG20

AL36

AM37

D20

H10

B51
BJ20
BK22
BF19
BH20
BK18
BJ18
BF23

BG23

BC23
BD24
BJ29
BE24
BH39

AW20

BK20

C48

D47

B44

C44

A35

B37

B36

B34

C34

P27
N27
N24
C21
C23
F23
N23

G23

J20
C20
R24

L23

J23
E23
E20
K23
M20
M24

L32

N33

L35

G41

L39

L36

J36

AW49

AV20

N20
G36

BJ51
BK51
BK50
BL50
BL49

BL3
BL2
BK1
BJ1

E1

A5
C51
B50
A50
A49
BK2

CRESTLINE_1p0

CRESTLINE_1p0

RSVD11
RSVD12
RSVD13
RSVD14

RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31
SA-MA14
SB_MA14
RSVD34
RSVD35
RSVD36
LVDSA_DATA#_3
LVDSA_DATA_3
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20

PM_BM_BUSY#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16

DDR MUXINGCLKDMI

DDR MUXINGCLKDMI

CFGRSVD

CFGRSVD

PM

PM

GRAPHICS VIDME

GRAPHICS VIDME

NC

NC

MISC

MISC

SM_RCOMP_VOH
SM_RCOMP_VOL

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

SDVO_CTRL_CLK

SDVO_CTRL_DATA

A A

12

C328

C328
.1U_4

.1U_4

SA_MA1415,16
SB_MA1415,16

T145T145
T20T20

B B

MCH_BSEL03
MCH_BSEL13
MCH_BSEL23

MCH_CFG_513

MCH_CFG_913

MCH_CFG_1213
MCH_CFG_1313

MCH_CFG_1613

MCH_CFG_1913
MCH_CFG_2013

PM_BMBUSY#19
ICH_DPRSTP#4,17,34
PM_EXTTS#015
PM_EXTTS#115

DELAY_VR_PWRGOOD6,19,34

C C

PM_THRMTRIP#4,17

PM_DPRSLPVR19,34

VCC3

R42 10K_4R42 10K_4

1 2

R38 10K_4R38 10K_4

1 2

R45 10K_4R45 10K_4

1 2

PLT_RST-R#18

PM_EXTTS#0
PM_EXTTS#1
PCIE_REQ4#

T7T7
T132T132

T10T10
T2T2
T3T3

T11T11
T6T6

T4T4
T5T5

T9T9
T14T14

R57 0_4R57 0_4
R44 0_4R44 0_4

R19 100_4R19 100_4
R15 *0_4R15 *0_4
R55 0_4R55 0_4

T148T148
T147T147
T146T146
T141T141
T142T142
T130T130
T125T125
T126T126
T127T127
T128T128
T131T131
T152T152
T151T151
T149T149
T144T144
T129T129

CFG15
CFG17

CFG18

TP_NC1
TP_NC2
TP_NC3
TP_NC4
TP_NC5
TP_NC6
TP_NC7
TP_NC8
TP_NC9

TP_NC10

TP_NC11
TP_NC12

TP_NC13

TP_NC14

SM_CK_0
SM_CK_1
SM_CK_3
SM_CK_4

SM_CK#_0
SM_CK#_1
SM_CK#_3
SM_CK#_4

SM_CKE_0
SM_CKE_1
SM_CKE_3
SM_CKE_4

SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3

SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3

SM_RCOMP

SM_RCOMP#

SM_VREF_0
SM_VREF_1

PEG_CLK

PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3

GFX_VR_EN

CL_CLK

CL_DATA

CL_PWROK

CL_RST#

CL_VREF

CLK_REQ#

ICH_SYNC#

TEST_1
TEST_2

AV29
BB23
BA25
AV23

AW30
BA23
AW25
AW23

BE29
AY32
BD39
BG37

BG20
BK16
BG16
BE13

BH18
BJ15
BJ14
BE16

BL15
BK14

BK31
BL31

AR49
AW4

B42
C42
H48
H47

K44
K45

AN47
AJ38
AN42
AN46

AM47
AJ39
AN41
AN45

AJ46
AJ41
AM40
AM44

AJ47
AJ42
AM39
AM43

E35
A39
C38
B39
E36

AM49
AK50
AT43
AN49
AM50

H35
K36
G39
G40

A37
R32

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

M_A_CLK0 15
M_A_CLK1 15
M_B_CLK0 15
M_B_CLK1 15

M_A_CLK0# 15
M_A_CLK1# 15
M_B_CLK0# 15
M_B_CLK1# 15

M_A_CKE0 15,16
M_A_CKE1 15,16
M_B_CKE0 15,16
M_B_CKE1 15,16

M_A_CS#0 15,16
M_A_CS#1 15,16
M_B_CS#0 15,16
M_B_CS#1 15,16

M_A_ODT0 15,16
M_A_ODT1 15,16
M_B_ODT0 15,16
M_B_ODT1 15,16

SMRCOMPP
SMRCOMPN

SM_RCOMP_VOH
SM_RCOMP_VOL

SMDDR_VREF_MCH

CLK_PCIE_3GPLL 3
CLK_PCIE_3GPLL# 3

DFGT_VID_0
DFGT_VID_1
DFGT_VID_2
DFGT_VID_3
DFGT_VR_EN

MCH_CLVREF

T15T15
T17T17

PCIE_REQ4#

R33

R33
20K_4

20K_4

1 2

1 2

C44 .1U_4C44 .1U_4
C143 .1U_4C143 .1U_4
R7 0_4R7 0_4

DREFCLK 3
DREFCLK# 3
DREFSSCLK 3
DREFSSCLK# 3

DMI_TXN[3:0] 18

DMI_TXP[3:0] 18

DMI_RXN[3:0] 18

DMI_RXP[3:0] 18

T133T133
T136T136
T135T135
T137T137
T134T134

CL_PWROK 19
CL_RST#0 19

CLK_MCH_OE# 3

R254

R254
0_4

0_4

DIGON14

CL_CLK0 19
CL_DATA0 19

MCH_ICH_SYNC# 19

VCC3

SMDDR_VREF

INT_LVDS_BKLT_PWM14

CRT_B14
CRT_G14
CRT_R14

BLON14

LVDS_CLK14
LVDS_DAT14

R49 2.4K_4R49 2.4K_4

TXLCLKOUT#14
TXLCLKOUT14

TXLOUT#014
TXLOUT#114
TXLOUT#214

TXLOUT014
TXLOUT114
TXLOUT214

R22 150_4R22 150_4
R20 150_4R20 150_4
R21 150_4R21 150_4

T13T13
T12T12

INTEL FAE (08/17)
PD 0OHM

DDCCLK14
DDCDAT14
HSYNC14

VSYNC14

R35 1.3K_4R35 1.3K_4

R34 150_4R34 150_4
R26 150_4R26 150_4
R25 150_4R25 150_4

0.333V

R41 10K_4R41 10K_4
R48 10K_4R48 10K_4

LVDS_IBG

T150T150

T16T16
T18T18

T19T19
T140T140
T139T139

T21T21
T143T143
T138T138

TV_COMP
TV_Y/G
TV_C/R

TV_DCONSEL_0
TV_DCONSEL_1

R37 0_4R37 0_4
R32 0_4R32 0_4

R30 0_4R30 0_4
R28 0_4R28 0_4
R23 0_4R23 0_4

DDCCLK
DDCDAT

R253 39_4R253 39_4

CRTIREF

R252 39_4R252 39_4

MCH_CLVREF

C355

C355
.1U_4

.1U_4

1 2

CRT_B_R
CRT_G_R
CRT_R_R

HSYNC_C
VSYNC_C

CRTIREF

CRT_B_R
CRT_G_R
CRT_R_R

VCC1.25 1.8VSUS

12

R262

R262
1K_4

1K_4

12

R260

R260
392_4

392_4

J40
H39
E39
E40
C37
D35
K40

L41
L43
N41
N40
D46
C45
D44
E42

G51
E51
F49

G50
E50
F48

G44
B47
B45

E44
A47
A45

E27
G27
K27

F27
J27
L27

M35

P33

H32
G32
K29
J29
F29
E29

K33
G35
F33
C32
E33

U12C

U12C

L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN

LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK

LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2

LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2

LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2

LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2

TVA_DAC
TVB_DAC
TVC_DAC

TVA_RTN
TVB_RTN
TVC_RTN

TV_DCONSEL_0
TV_DCONSEL_1

CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#

CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC

CRESTLINE_1p0

CRESTLINE_1p0

C106*.1U_4C106*.1U_4

C100*.1U_4C100*.1U_4

C91 *.1U_4C91 *.1U_4

SMRCOMPP
SMRCOMPN

1 2

12

12

VCC3G_PCIE_R

N43

PEG_COMPI

M43

PEG_COMPO

J51

PEG_RX#_0

L51

PEG_RX#_1

N47

PEG_RX#_2

T45

PEG_RX#_3

T50

PEG_RX#_4

U40

PEG_RX#_5

Y44

PEG_RX#_6

Y40

PEG_RX#_7

AB51

PEG_RX#_8

W49

PEG_RX#_9

LVDS

LVDS

TV VGA

TV VGA

PCI-EXPRESS GRAPHICS

PCI-EXPRESS GRAPHICS

CRT_B

CRT_G

CRT_R

12

R12

R12
20_4

20_4

12

R11

R11
20_4

20_4

PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8

PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

1.439V

SM_RCOMP_VOH

12

C107

C107
.01U_4

.01U_4

SM_RCOMP_VOL

12

C97

C97
.01U_4

.01U_4

AD44
AD40
AG46
AH49
AG45
AG41

J50
L50
M47
U44
T49
T41
W45
W41
AB50
Y48
AC45
AC41
AH47
AG49
AH45
AG42

N45
U39
U47
N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44

M45
T38
T46
N50
R51
U43
W42
Y47
Y39
AC38
AD47
AC50
AD43
AG39
AE50
AH43

12

12

C120

C120

2.2U_8

2.2U_8

C102

C102

2.2U_8

2.2U_8

1.8VSUS

12

12

12

R51 24.9_4R51 24.9_4

1 2

R36

R36
1K_4

1K_4

R31

R31

3.01K/F

3.01K/F

0.360V

R29

R29
1K_4

1K_4

1.05V_VCC_PEG

D D

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

GMCH (VGA,DMI)

GMCH (VGA,DMI)

GMCH (VGA,DMI)

Date: Sheet

Date: Sheet

1

2

3

4

5

6

Date: Sheet

7

PROJECT : PL3

A

A

838Wednesday, January 10, 2007

838Wednesday, January 10, 2007

838Wednesday, January 10, 2007

8

A

of

of

of

1

2

3

4

5

6

7

8

9

M_A_DQ[63:0]15 M_B_DQ[63:0]15

A A

B B

C C

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

AR43

AW44

BA45
AY46
AR41
AR45
AT42

AW47

BB45
BF48
BG47

BJ45
BB47
BG50
BH49
BE45

AW43

BE44
BG42
BE40
BF44
BH45
BG40
BF40
AR40

AW40

AT39

AW36
AW41

AY41
AV38
AT38
AV13
AT13

AW11

AV11
AU15
AT11
BA13
BA11
BE10
BD10

BD8
AY9

BG10

AW9

BD7
BB9
BB5
AY7

AY6
BB7
AR5
AR8
AR9
AN3
AM8

AN10

AN9
AM9

AN11

AT5
AT7

AT9

U12D

U12D

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

CRESTLINE_1p0

CRESTLINE_1p0

BB19

SA_BS_0

BK19

SA_BS_1

BF29

SA_BS_2

BL17

SA_CAS#
SA_DM_0

SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6

SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13

SA_RAS#

SA_RCVEN#

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_WE#

AT45
BD44
BD42
AW38
AW13
BG8
AY5
AN6

AT46
BE48
BB43
BC37
BB16
BH6
BB2
AP3
AT47
BD47
BC41
BA37
BA16
BH7
BC1
AP2

BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16

BE18
AY20

BA19

M_A_DQM0
M_A_DQM1
M_A_DQM2
M_A_DQM3
M_A_DQM4
M_A_DQM5
M_A_DQM6
M_A_DQM7

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13

TP_SA_RCVEN#

M_A_BS#0 15,16
M_A_BS#1 15,16
M_A_BS#2 15,16

M_A_CAS# 15,16
M_A_DQM[0..7] 15

M_A_DQS[7:0] 15

M_A_DQS#[7:0] 15

M_A_A[13:0] 15,16

T8T8

M_A_RAS# 15,16

M_A_WE# 15,16

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

AP49

AR51
AW50
AW51

AN51

AN50

AV50

AV49

BA50

BB50

BA49

BE50

BA51

AY49

BF50

BF49

BJ50
BJ44
BJ43

BL43
BK47
BK49
BK43
BK42

BJ41

BL41

BJ37

BJ36
BK41

BJ40

BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12

BG12

BJ10

BL9
BK5
BL5
BK9

BK10

BJ8
BJ6
BF4

BH5
BG1
BC2
BK3
BE4
BD3

BJ2
BA3
BB3
AR1

AT3
AY2
AY3
AU2

AT2

U12E

U12E

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

CRESTLINE_1p0

CRESTLINE_1p0

AY17

SB_BS_0

BG18

SB_BS_1

BG36

SB_BS_2

BE17

SB_CAS#
SB_DM_0

SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6

SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13

SB_RAS#

SB_RCVEN#

SB_WE#

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

AR50
BD49
BK45
BL39
BH12
BJ7
BF3
AW2

AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3

BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13

AV16
AY18

BC17

M_B_DQM0
M_B_DQM1
M_B_DQM2
M_B_DQM3
M_B_DQM4
M_B_DQM5
M_B_DQM6
M_B_DQM7

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13

TP_SB_RCVEN#

M_B_BS#0 15,16
M_B_BS#1 15,16
M_B_BS#2 15,16

M_B_CAS# 15,16
M_B_DQM[0..7] 15

M_B_DQS[7:0] 15

M_B_DQS#[7:0] 15

M_B_A[13:0] 15,16

M_B_RAS# 15,16

T1 *PADT1 *PAD

M_B_WE# 15,16

D D

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

GMCH DDR2

GMCH DDR2

GMCH DDR2

Date: Sheet of

Date: Sheet of

1

2

3

4

5

6

Date: Sheet

7

PROJECT : PL3

A

A

A

of

938Wednesday, January 10, 2007

938Wednesday, January 10, 2007

938Wednesday, January 10, 2007

8

AT35

AT34
AH28
AC32
AC31

AK32

AJ31

AJ28
AH32
AH31
AH29

AF32

R30

AU32
AU33
AU35

AV33
AW33
AW35

AY35

BA32

BA33

BA35

BB33
BC32
BC33
BC35
BD32
BD35

BE32

BE33

BE35

BF33

BF34
BG32
BG33
BG35
BH32
BH34
BH35

BJ32

BJ33

BJ34

BK32

BK33

BK34

BK35

BL33
AU30

R20

T14
W13
W14

Y12

AA20
AA23
AA26
AA28
AB21
AB24

AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28

AF21

AF26

AA31
AH20
AH21
AH23
AH24
AH26
AD31

AJ20
AN14

5

U12G

U12G

VCC_1
VCC_2
VCC_3
VCC_5
VCC_4
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

VCC_13

VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34

VCC CORE

VCC CORE

POWER

POWER

VCC SMVCC GFX

VCC SMVCC GFX

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8

VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55

VCC GFX NCTF

VCC GFX NCTF

VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

VCC SM LF

VCC SM LF

VCC1.05

D D

IVCCSM MAX: 3.318A

1.8VSUS

C C

VCC1.05

B B

A A

T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31

AW45
BC39
BE39
BD17
BD4
AW8
AT6

4

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

Ivcc (External GFX 1.310 A,
integrate 1.572 A)

Layout Note:
370 mils from edge.

12

+

+

C317

C317
330U_7343

330U_7343

Layout Note:
Inside GMCH cavity for VCC_AXG.

12

C70

C70
.1U_4

.1U_4

GMCH 1.05V

VCC Core

VCC_AXG

VCC_AXD

VTT

VCC_PEG

VCC_AXM

VCCR_RX_DMI

12

+

+

C319

C319
330U_7343

330U_7343

12

C95

C95
.1U_4

.1U_4

current(A)

1.573

7.7

0.2

0.85

1.2

0.54

0.25

Ivcc_AXG Graphics core supply
current 7.7A

12

12

C83

C83
.47U_6

.47U_6

Remark

( 1.3A for
external
GFX )

for integrated
Gfx

FSB VCCP

for PCIEG

for IAMT
function

DMI

12.313SUM

12

C51

C51
.1U_4

.1U_4

12

12

C49

C49
.1U_4

.1U_4

C38

C38
.22U_6

.22U_6

3

VCC1.05

12

+

+

C320

C320
220U_7343

220U_7343

Layout Note:
370 mils from edge.

12

C96

C96

C57

C57

1U_6

1U_6

10U_8

10U_8

VCC1.05

Ivcc_AXM
Controller
supply
current
540mA

C46

C46
.22U_6

.22U_6

12

C125

C125
.47U_6

.47U_6

12

VCC3

R249 10_4R249 10_4

1 2

12

Layout Note:
Inside GMCH cavity.

12

12

C326

C326
22U_8

22U_8

C60

C60
22U_8

22U_8

C108

C108
.22U_6

.22U_6

12

C124

C124
.1U_4

.1U_4

12

C135

C135
22U_8

22U_8

Layout Note:
Place close to GMCH edge.

12

12

C130

C130
1U_6

1U_6

C139

C139
1U_6

1U_6

CH751H-40HPT

CH751H-40HPT

12

C134

C134
.22U_6

.22U_6

VCC1.05

Layout Note:
Inside GMCH
cavity.

12

C115

C115
.1U_4

.1U_4

12

C84

C84
.22U_6

.22U_6

2

U12F

D11

D11

21

12

C118

C118
.1U_4

.1U_4

12

C117

C117
.1U_4

.1U_4

12

C116

C116
.22U_6

.22U_6

from CH73301M8L9 to CH733LM8812 1/11

1.8VSUS

12

C119

C119
.1U_4

.1U_4

Layout Note:
Place C901 where LVDS
and DDR2 taps.

U12F

AB33

VCC_NCTF_1

AB36

VCC_NCTF_2

AB37

VCC_NCTF_3

AC33

VCC_NCTF_4

AC35

VCC_NCTF_5

AC36

VCC_NCTF_6

AD35

VCC_NCTF_7

AD36

VCC_NCTF_8

AF33

VCC_NCTF_9

AF36

VCC_NCTF_10

AH33

VCC_NCTF_11

AH35

VCC_NCTF_12

AH36

VCC_NCTF_13

AH37

VCC_NCTF_14

AJ33

VCC_NCTF_15

AJ35

VCC_NCTF_16

AK33

VCC_NCTF_17

AK35

VCC_NCTF_18

AK36

VCC_NCTF_19

AK37

VCC_NCTF_20

AD33

VCC_NCTF_21

AJ36

VCC_NCTF_22

AM35

VCC_NCTF_23

AL33

VCC_NCTF_24

AL35

VCC_NCTF_25

AA33

VCC_NCTF_26

AA35

VCC_NCTF_27

AA36

VCC_NCTF_28

AP35

VCC_NCTF_29

AP36

VCC_NCTF_30

AR35

VCC_NCTF_31

AR36

VCC_NCTF_32

Y32

VCC_NCTF_33

Y33

VCC_NCTF_34

Y35

VCC_NCTF_35

Y36

VCC_NCTF_36

Y37

VCC_NCTF_37

T30

VCC_NCTF_38

T34

VCC_NCTF_39

T35

VCC_NCTF_40

U29

VCC_NCTF_41

U31

VCC_NCTF_42

U32

VCC_NCTF_43

U33

VCC_NCTF_44

U35

VCC_NCTF_45

U36

VCC_NCTF_46

V32

VCC_NCTF_47

V33

VCC_NCTF_48

V36

VCC_NCTF_49

V37

VCC_NCTF_50

AL24

VCC_AXM_NCTF_1

AL26

VCC_AXM_NCTF_2

AL28

VCC_AXM_NCTF_3

AM26

VCC_AXM_NCTF_4

AM28

VCC_AXM_NCTF_5

AM29

VCC_AXM_NCTF_6

AM31

VCC_AXM_NCTF_7

AM32

VCC_AXM_NCTF_8

AM33

VCC_AXM_NCTF_9

AP29

VCC_AXM_NCTF_10

AP31

VCC_AXM_NCTF_11

AP32

VCC_AXM_NCTF_12

AP33

VCC_AXM_NCTF_13

AL29

VCC_AXM_NCTF_14

AL31

VCC_AXM_NCTF_15

AL32

VCC_AXM_NCTF_16

AR31

VCC_AXM_NCTF_17

AR32

VCC_AXM_NCTF_18

AR33

VCC_AXM_NCTF_19

CRESTLINE_1p0

CRESTLINE_1p0

+

+

12

C138

C138
330U_7343

330U_7343

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16

VSS NCTF

VSS NCTF

VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21

VCC NCTF

VCC NCTF

POWER

POWER

VSS_SCB1
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6

VSS SCBVCC AXM

VSS SCBVCC AXM

VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_5
VCC_AXM_6
VCC_AXM_7

VCC AXM NCTF

VCC AXM NCTF

1.8VSUS

12

12

Layout Note:
Place on the edge.

C131

C131
22U_8

22U_8

C114

C114
22U_8

22U_8

1

10

T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28

A3
B2
C1
BL1
BL51
A51

AT33
AT31
AK29
AK24
AK23
AJ26
AJ23

VCC1.05

CRESTLINE_1p0

CRESTLINE_1p0

5

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

GMCH VCC,NCTF

GMCH VCC,NCTF

GMCH VCC,NCTF

Date: Sheet of

Date: Sheet of

4

3

2

Date: Sheet

PROJECT : PL3

1

A

A

A

of

10 38Thursday, January 11, 2007

10 38Thursday, January 11, 2007

10 38Thursday, January 11, 2007

5

VCC3

D D

VCC1.25

VCC1.25

C C

VCC1.5

VCC3

B B

1.25V_VCC_AXF

1.8VSUS_VCC_SM_CK

A A

BLM18PG181SN1D

BLM18PG181SN1D

1 2

L4

L4

1 2

BLM18PG181SN1D

BLM18PG181SN1D

L21

L21

1 2

BLM18PG181SN1D

BLM18PG181SN1D

12

C332

C332
1U_6

1U_6

12

C79

C79
10U_8

10U_8

L3

L3
BLM18PG181SN1D

BLM18PG181SN1D

1 2

5

L23

L23

1 2

3V_VCCSYNC

1.25V_VCCA_DPLLA

L7

L7
BLM18PG181SN1D

BLM18PG181SN1D

1.5V_VCCD_TVDAC

12

C90

C90
.1U_4

.1U_4

3V_TV_DAC

12

C337

C337
10U_8

10U_8

R251 0_6R251 0_6

12

C333

C333
10U_8

10U_8

Place caps close
to VCC_AXF

12

12

C74

C74
.1U_4

.1U_4

12

C345

C345

C111

C111

.1U_4

.1U_4

.1U_4

.1U_4

12

12

C36

C36

C35

C35

10U_8

10U_8

.1U_4

.1U_4

1.25V_VCCA_PEG_PLL

12

C155

C155
10U_8

10U_8

12

C99

C99
.1U_4

.1U_4

12

12

C93

C93

C339

C339

.1U_4

.1U_4

.1U_4

.1U_4

VCC1.25

L5

L5

1 2

BLM18PG181SN1D

BLM18PG181SN1D

C78

C78
10U_8

10U_8

12

12

C344

C344
.1U_4

.1U_4

12

12

C146

C146
.1U_4

.1U_4

VCC1.25

C336

C336
.1U_4

.1U_4

1.8VSUS

C142

C142
.1U_4

.1U_4

1.8VSUS

VCC3

12

C149

C149
.1U_4

.1U_4

VCC1.25

R47 0_6R47 0_6

VCC1.25

250mA

R258 0_6R258 0_6

4

12

C41

C41
.1U_4

.1U_4

4

1 2

C89

C89

+

+

*100U_7343

*100U_7343

12

C127

C127
10U_8

10U_8

1.25V_VCCA_PEG_PLL

C43

C43
.1U_4

.1U_4

C137

C137
1U_6

1U_6

3V_VCCA_DAC_BG

VCC3

C133

C133
1U_6

1U_6

L22

L22
BLM18PG181SN1D

BLM18PG181SN1D

R10 0_8R10 0_8

12

12

12

12

12

C144

C144
.1U_4

.1U_4

1 2

C352

C352
10U_8

10U_8

C67

C67

4.7U_6

4.7U_6

12

C341

C341
.1U_4

.1U_4

1.25V_VCCA_PEG_PLL

1.25V_VCCA_SM_CK

12

C98

C98
.1U_4

.1U_4

1.8VSUS_VCC_TX_LVDS

1.25V_VCCA_SM

12

C58

C58
10U_8

10U_8

12

C140

C140
.1U_4

.1U_4

VTTLF1
VTTLF2
VTTLF3

12

3V_VCCSYNC

3V_VCCA_DAC_BG

1.25V_VCCA_DPLLA

12

C47

C47
10U_8

10U_8

3V_TV_DAC

1.5V_VCCD_TVDAC

1.8V_VCCD_LVDS

12

C37

C37
.47U_6

.47U_6

3

100mA

12

C66

C66
1U_6

1U_6

150mA

C323

C323
.47U_6

.47U_6

3

C349

C349
1000P_4

1000P_4

12

C325

C325
.47U_6

.47U_6

AM2

AW18

AV19
AU19
AU18
AU17

AT22
AT21
AT19
AT18
AT17
AR17
AR16

BC29
BB29

AN2

A33
B33

A30
B32

B49
H49
AL2

A41
B41

K50
K49

U51

C25
B25
C27
B27
B28
A28

M32

N28

U48

H42

J32

L29

J41

U12H

U12H

VCCSYNC
VCCA_CRT_DAC_1

VCCA_CRT_DAC_2

VCCA_DAC_BG
VSSA_DAC_BG

VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL

VCCA_LVDS
VSSA_LVDS

VCCA_PEG_BG
VSSA_PEG_BG

VCCA_PEG_PLL

VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5

VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
VCCA_SM_10
VCCA_SM_11
VCCA_SM_NCTF_1
VCCA_SM_NCTF_2

VCCA_SM_CK_1
VCCA_SM_CK_2

VCCA_TVA_DAC_1
VCCA_TVA_DAC_2
VCCA_TVB_DAC_1
VCCA_TVB_DAC_2
VCCA_TVC_DAC_1
VCCA_TVC_DAC_2

VCCD_CRT
VCCD_TVDAC

VCCD_QDAC
VCCD_HPLL
VCCD_PEG_PLL
VCCD_LVDS_1

VCCD_LVDS_2

3V_VCC_HV

3V_VCC_HV

CRTPLLA PEGA SMTV

CRTPLLA PEGA SMTV

POWER

POWER

A CK A LVDS

A CK A LVDS

D TV/CRTLVDS

D TV/CRTLVDS

D12

D12
CH751H-40HPT

CH751H-40HPT

R255 0_4R255 0_4

VTT_10
VTT_11
VTT_12
VTT_13
VTT_14

VTT

VTT

VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22

VCC_AXD_1
VCC_AXD_2
VCC_AXD_3
VCC_AXD_4
VCC_AXD_5
VCC_AXD_6

AXD

AXD

VCC_AXD_NCTF

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

AXF

AXF

VCC_DMI

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

SM CK

SM CK

VCC_TX_LVDS

VCC_HV_1
VCC_HV_2

HV

HV

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5

PEG

PEG

VCC_RXR_DMI_1
VCC_RXR_DMI_2

DMI

DMI

VTTLF1
VTTLF2
VTTLF3

VTTLF

VTTLF

CRESTLINE_1p0

CRESTLINE_1p0

VCC1.05

21

40 mil
wide

12

R256

R256
10_4

10_4

Ivcc_PEG
supply current

1.2A

VCC3

2

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9

2

U13
U12
U11
U9
U8
U7
U5
U3
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1

AT23
AU28
AU24
AT29
AT25
AT30

AR29

B23
B21
A21

AJ50

BK24
BK23
BJ24
BJ23

A43

C40
B40

AD51
W50
W51
V49
V50

AH50
AH51

A7
F2
AH1

change p/n:FROM CH44701ZB38 TO CH4471Z3B07

12

12

12

C52

C52

2.2U_6

2.2U_6

1.25V_AXD

12

C86

C86
1U_6

1U_6

1.25V_VCC_AXF

1.25V_VCC_DMI_MCH

1.8VSUS_VCC_SM_CK

200mA

1.8VSUS_VCC_TX_LVDS

12

1.05V_VCC_PEG

1.05V_VCC_RXR_DMI

VTTLF1
VTTLF2
VTTLF3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

C348

C348
.1U_4

.1U_4

12

C42

C42

C31

C31

.47U_4

.47U_4

4.7U_8

4.7U_8

12

C85

C85

C71

C71

1U_6

1U_6

22U_1206

22U_1206

1.25V_VCC_AXF

3V_VCC_HV

1.05V_VCC_PEG

12

C147

C147
.1U_4

.1U_4

12

12

C357

C357
.1U_4

.1U_4

GMCH POWER

GMCH POWER

GMCH POWER

1

VCC1.05

12

12

+

+

C32

C32

C321

C321

Ivcc_VTT FSB

220U_7343

220U_7343

VCC1.05

supply
current

0.85A

11 38Wednesday, January 10, 2007

11 38Wednesday, January 10, 2007

11 38Wednesday, January 10, 2007

4.7U_8

4.7U_8

R13 0_8R13 0_8

12

C104

C104
1U_6

1U_6

R261 0_6R261 0_6

12

C356

C356
.1U_4

.1U_4

R257 0_6R257 0_6

12

C350

C350
1000P_4

1000P_4

L6

L6

1 2

BLM18PG181SN1D

BLM18PG181SN1D

12

C150

C150
10U_6

10U_6

L24

L24

1 2

BLM18PG181SN1D

BLM18PG181SN1D

Ivcc_RX_DMI

C359

C359

supply current

10U_6

10U_6

250mA

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

PROJECT : PL3

1

11

VCC1.25

VCC1.25

1.8VSUS

VCC1.05

of

of

of

A

A

A

5

U12I

U12I

A13

VSS_1

A15

VSS_2

A17

VSS_3

A24

VSS_4

AA21

VSS_5

AA24

VSS_6

AA29

VSS_7

D D

C C

B B

A A

5

AB20
AB23
AB26
AB28
AB31
AC10
AC13

AC3
AC39
AC43

AC47

AD1
AD21
AD26
AD29

AD3
AD41
AD45
AD49

AD5
AD50

AD8
AE10
AE14

AE6
AF20
AF23
AF24
AF31

AG2
AG38
AG43
AG47
AG50

AH3
AH40
AH41

AH7

AH9

AJ11
AJ13
AJ21
AJ24
AJ29
AJ32
AJ43
AJ45

AJ49
AK20
AK21
AK26
AK28
AK31
AK51

AL1
AM11
AM13

AM3

AM4
AM41
AM45

AN1
AN38
AN39
AN43

AN5

AN7

AP4

AP48
AP50

AR11

AR2
AR39
AR44
AR47

AR7

AT10
AT14
AT41
AT49

AU1
AU23
AU29

AU3
AU36
AU49
AU51

AV39
AV48

AW1
AW12
AW16

VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

CRESTLINE_1p0

CRESTLINE_1p0

VSS

VSS

4

4

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198

AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41

3

U12J

U12J

C46

VSS_199

C50

VSS_200

C7

VSS_201

D13

VSS_202

D24

VSS_203

D3

VSS_204

D32

VSS_205

D39

VSS_206

D45

VSS_207

D49

VSS_208

E10

VSS_209

E16

VSS_210

E24

VSS_211

E28

VSS_212

E32

VSS_213

E47

VSS_214

F19

VSS_215

F36

VSS_216

F4

VSS_217

F40

VSS_218

F50

VSS_219

G1

VSS_220

G13

VSS_221

G16

VSS_222

G19

VSS_223

G24

VSS_224

G28

VSS_225

G29

VSS_226

G33

VSS_227

G42

VSS_228

G45

VSS_229

G48

VSS_230

G8

VSS_231

H24

VSS_232

H28

VSS_233

H4

VSS_234

H45

VSS_235

J11

VSS_236

J16

VSS_237

J2

VSS_238

J24

VSS_239

J28

VSS_240

J33

VSS_241

J35

VSS_242

J39

VSS_243

K12

VSS_245

K47

VSS_246

K8

VSS_247

L1

VSS_248

L17

VSS_249

L20

VSS_250

L24

VSS_251

L28

VSS_252

L3

VSS_253

L33

VSS_254

L49

VSS_255

M28

VSS_256

M42

VSS_257

M46

VSS_258

M49

VSS_259

M5

VSS_260

M50

VSS_261

M9

VSS_262

N11

VSS_263

N14

VSS_264

N17

VSS_265

N29

VSS_266

N32

VSS_267

N36

VSS_268

N39

VSS_269

N44

VSS_270

N49

VSS_271

N7

VSS_272

P19

VSS_273

P2

VSS_274

P23

VSS_275

P3

VSS_276

P50

VSS_277

R49

VSS_278

T39

VSS_279

T43

VSS_280

T47

VSS_281

U41

VSS_282

U45

VSS_283

U50

VSS_284

V2

VSS_285

V3

VSS_286

CRESTLINE_1p0

CRESTLINE_1p0

3

VSS

VSS

VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305

VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313

2

W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28

AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

GMCH VSS

GMCH VSS

GMCH VSS

Date: Sheet of

Date: Sheet of

2

Date: Sheet

PROJECT : PL3

1

1

12

of

12 38Wednesday, January 10, 2007

12 38Wednesday, January 10, 2007

12 38Wednesday, January 10, 2007

A

A

A

Strap table

5

All strap are sampled with respect to the leading edge of the GMCH Power OK(PWROK) Signal
CFG[17:3] Have internal Pull-up

CFG[18:19] Have internal Pull-down
Any CFG signal strapping option not list below should be left NC Pin

Pin Name Strap description

D D

CFG[2:0]

CFG[4:3]

CFG5

CFG6

CFG7

CFG8

CFG9

CFG[11:10]

C C

CFG[13:12]

CFG[15:14]

CFG16

CFG[18:17]

SDVO_CTRLDATA

CFG19

CFG20

B B

DMI X2 Select

MCH_CFG_5 Low = DMIX2

MCH_CFG_58

High = IDMIX4(Default)

R17

R17
*4.02K_4

*4.02K_4

FSB Dynamic ODT

MCH_CFG_16 Low = ODT Disable

A A

MCH_CFG_168

High = ODT Enable(Default)

R14

R14
*4.02K_4

*4.02K_4

5

FSB Frequency Select

Reserved

DMI X2 Select

Reserved

CPU Strap

Low power PCI Express

PCI Express Graphics Lane Reversal

Reserved

XOR/ALLZ

Reserved

FSB Dynamic ODT

Reserved

SDVO Present

DMI Lane Reversal

SDVO/PCIe concurrent

DMI Lane Reversal

MCH_CFG_19 Low = Normal operation(Default)

MCH_CFG_198

SDVO/PCIE Concurrent operation

MCH_CFG_20

MCH_CFG_208

4

High = Reverse Lane

VCC3

R40

R40
*4.02K_4

*4.02K_4

Low = Only SDVO or PCIE X1 is
operational(Default)
High = SDVO andPCIE X1 are operating
simultaneously via the PEG port

VCC3

R39

R39
*4.02K_4

*4.02K_4

4

3

2

Configuration

010 = FSB 800MHz
011 = FSB 667MHz

0 = DMI X2
1 = DMI X4(Default)

0 = Reserved
1 = Mobile CPU(Default)

0 = Normal mode
1 = Low Power mode

0 = Reverse Lanes
1 = Normal operation(Default)

00 = Reserved
01 = XOR Mode Enable
10 = All-Z Mode Enabled
11 = Normal operation(Default)

0 = Dynamic ODT disable
1 = Dynamic ODT Enable(Default)

0 = No SDVO Card present(Default)
1 = SDVO Card Present

0 = Normal operation(Default)
1 = Reverse Lanes

0 = Only SDVO or PCIE x1 is operation(Default)
1 = SDVO and PCIE x1 are operating simultaneously via the PEG port

XOR /ALLz /Clock Un-gating

MCH_CFG_12MCH_CFG_13 Configuration

0

0

1

1

MCH_CFG_128
MCH_CFG_138

0

1

0

1

Clock gating disable

XOR Mode Enable

ALL-z Mode Enable

Normal operation(Default)

3

R16

R16
*4.02K_4

*4.02K_4

R18

R18
*4.02K_4

*4.02K_4

PCI Express Graphics

MCH_CFG_9 Low = Reverse Lane

High = Normal operation(Default)

MCH_CFG_98

2

1

13

SDVO Present

Strap define at External
DVI control page

R250

R250
*4.02K_4

*4.02K_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

GMCH STRAP

GMCH STRAP

GMCH STRAP

Date: Sheet

Date: Sheet

Date: Sheet

PROJECT : PL3

1

of

of

of

13 38Wednesday, January 10, 2007

13 38Wednesday, January 10, 2007

13 38Wednesday, January 10, 2007

A

A

A

A

M

CRT PORT

D D

CRT_R8
CRT_G8
CRT_B8

5V_CRT2

VCC5

C298 .22U_6C298 .22U_6

VCC3

CRT_R1
CRT_G1
CRT_B1

C C

C547

C547

.1U_4

.1U_4

VCC5

C297

C297
.1U_4

.1U_4

VCC3

5

D1 SSM14

D1 SSM14

VCC5

CRT_R CRT_R1
CRT_G
CRT_B

1
7

8
2

3
4
5

6

U11

U11

VCC_SYNC
VCC_DDC

BYP
VCC_VIDEO

VIDEO_1
VIDEO_2
VIDEO_3

GND

CM2009

CM2009

C302

C302
.1U_4

.1U_4

R243

R243

150_4

150_4

SYNC_OUT2
SYNC_OUT1

SYNC_IN2
SYNC_IN1

DDC_IN1
DDC_IN2

DDC_OUT1
DDC_OUT2

C306

C306
6P_4

6P_4

R242

R242

150_4

150_4

16
14

15
13

10
11

9
12

2 1

Part Number = BC0SSM14Z30

Part Number = BC0SSM14Z30

L19 FBM-10-160808-600_6L19 FBM-10-160808-600_6
L17 FBM-10-160808-600_6L17 FBM-10-160808-600_6
L16 FBM-10-160808-600_6L16 FBM-10-160808-600_6

C300

C300

R240

R240

C303

C303

6P_4

6P_4

6P_4

6P_4

150_4

150_4

VSYNC1

R241 39_4R241 39_4

HSYNC1

R239 39_4R239 39_4

VSYNC
HSYNC

DDCCLK
DDCDAT

CRTDCLK
CRTDDAT

DDCCLK
DDCDAT

DDCCLK 8
DDCDAT 8

VSYNC 8
HSYNC 8

4

C5 .1U_4C5 .1U_4

5V_CRT2

25 MIL

CRT_G1
CRT_B1

C299

C299

C304

C304

C301

C301

6P_4

6P_4

6P_4

6P_4

6P_4

6P_4

L1 BLM18BA220SN1L1 BLM18BA220SN1
L2 BLM18BA220SN1L2 BLM18BA220SN1

R236 2.7K_4R236 2.7K_4
R237 2.7K_4R237 2.7K_4

5V_CRT2

R235

R235

2.7K_4

2.7K_4

R238

R238

2.7K_4

2.7K_4

VCC3

6
7

2
8
3
9
4

10

5

10P_4C410P_4

CN9

CN9

1617

CRT_DFDS15FR0G6

CRT_DFDS15FR0G6

111
12
13
14
15

CRTVSYNC
CRTHSYNC

C4

C6

10P_4C610P_4

10P_4C310P_4

D2 MTW355D2 MTW355

ECN 2A
RESERVE FOR ESD

C7

C3

10P_4C710P_4

3

D3
*MTW355D3*MTW355

CRT_SENSE# 31

LCD CONNECTOR

VCC3

VCC3

R2

2.2K_4R22.2K_4

LVDS_DAT8
LVDS_CLK8

TXLOUT28

TXLOUT#28

TXLOUT18

TXLOUT#18

TXLOUT08

TXLOUT#08

TXLCLKOUT8

TXLCLKOUT#8

LVDS_DAT
LVDS_CLK

TXLOUT2
TXLOUT#2

TXLOUT1
TXLOUT#1

TXLOUT0
TXLOUT#0

TXLCLKOUT
TXLCLKOUT#

EMI

C91000P_4 C91000P_4

12

R1

2.2K_4R12.2K_4

C81000P_4 C81000P_4

12

2

VIN_LCD

C305

C305
10U_1206

10U_1206

CH61004M291

CH61004M291

CN1

CN1

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30

31 32

ACES_88107-30001

ACES_88107-30001

VAD_J

DISPON

L18

L18

1 2

BLM21PG600SN1D

BLM21PG600SN1D

C307

C307
.1U_6

.1U_6

CC0603

CC0603

VIN_LCD

VAD_J

L20 BLM18PG181SN1DL20 BLM18PG181SN1D

C309

C309
1000P_4

1000P_4

VCC5
VCC3

LCDVCC

R56 *0_4R56 *0_4

EMI

1

VIN

14

VCC3 VCC5

EMI

INT_LVDS_BKLT_PWM 8

C310

C310
.1U_4

.1U_4

DISPON

CONTRAST 31

C308

C308
.1U_4

.1U_4

C311

C311
1000P_4

1000P_4

C:E

PANEL VCC CONTROL

VCC3

C312

C312

.1U_4

B B

<demo circuit>
Crestline suggest 100K
G73 suggest 10K(ZS1 Default)

DIGON8

.1U_4

R43

R43
10K_4

10K_4

5

Q11

Q11

5

OUT

IN

4

IN

3

ON/OFF

GND

G5241T1U

G5241T1U

G5241T1U:AL005241008

LID SWITCH

LCDVCC

1

C313

2

C313
.1U_4

.1U_4

4

VCC3

R399

R399
10K_4

10K_4

DISPON

D20 BAS316D20 BAS316

D21 BAS316D21 BAS316

R404 *1K_4R404 *1K_4

2

Q20

Q20

1 3

DTC144EU

DTC144EU

3

SW2

SW2

3
4

SW-DT016-PT11AB

SW-DT016-PT11AB

R405

R405
100K_4

100K_4

1
2

LID591#

R400 0_4R400 0_4

2

LID591# 19,31

BLON 8

EC_FPBACK# 31

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

PANEL LCD CRT

PANEL LCD CRT

PANEL LCD CRT

Date: Sheet

Date: Sheet

Date: Sheet

PROJECT : PL3

of

of

of

14 38Wednesday, January 10, 2007

14 38Wednesday, January 10, 2007

14 38Wednesday, January 10, 2007

1

A

A

A

A

1

CGCLK_SMB
CGDAT_SMB

M_A_CKE[0..1]
M_A_CS#[0..1]

M_A_RAS#
M_A_CAS#
M_A_WE#

A A

M_B_DQ5
M_B_DQ4
M_B_DQ3
M_B_DQ2
M_B_DQ0
M_B_DQ1
M_B_DQ7
M_B_DQ6
M_B_DQ13
M_B_DQ12
M_B_DQ10
M_B_DQ11
M_B_DQ8
M_B_DQ9
M_B_DQ15
M_B_DQ14
M_B_DQ21
M_B_DQ17
M_B_DQ19
M_B_DQ23
M_B_DQ20
M_B_DQ16
M_B_DQ18
M_B_DQ22
M_B_DQ28
M_B_DQ29
M_B_DQ27
M_B_DQ26
M_B_DQ24
M_B_DQ25
M_B_DQ31
M_B_DQ30

B B

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12

M_B_BS#0
M_B_BS#1
M_B_BS#2

M_B_CLK0
M_B_CLK0#

M_B_CLK1
M_B_CLK1#

CGCLK_SMB
CGDAT_SMB
DIM2_SA0
DIM2_SA1

VCC3

C C

CGCLK_SMB 3
CGDAT_SMB 3

M_A_CKE[0..1] 8,16 M_A_CLK0 8
M_A_CS#[0..1] 8,16

M_A_RAS# 9,16
M_A_CAS# 9,16
M_A_WE# 9,16

CN11A

CN11A

5

DQ0

7

DQ1

17

DQ2

19

DQ3

4

DQ4

6

DQ5

14

DQ6

16

DQ7

23

DQ8

25

DQ9

35

DQ10

37

DQ11

20

DQ12

22

DQ13

36

DQ14

38

DQ15

43

DQ16

45

DQ17

55

DQ18

57

DQ19

44

DQ20

46

DQ21

56

DQ22

58

DQ23

61

DQ24

63

DQ25

73

DQ26

75

DQ27

62

DQ28

64

DQ29

74

DQ30

76

DQ31

102

A0

101

A1

100

A2

99

A3

98

A4

97

A5

94

A6

92

A7

93

A8

91

A9

105

A10/AP

90

A11

89

A12

107

BA0

106

BA1

85

NC/BA2

30

CLK0

32

CLK0

164

CLK1

166

CKL1

197

SCL

195

SDA

198

SA0

200

SA1

199

VDDSPD

FOX=DDR-AS0A426-MAR-200P

FOX=DDR-AS0A426-MAR-200P

DIM2_SA1

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DM0
DM1
DM2
DM3
DM4
DM5
DM6

DM7
DQS0
DQS0
DQS1
DQS1

PC2100 DDR2 SDRAM SO-DIMM

(200P)

PC2100 DDR2 SDRAM SO-DIMM

(200P)

DQS2
DQS2
DQS3
DQS3
DQS4
DQS4
DQS5
DQS5
DQS6
DQS6
DQS7
DQS7

CS0

CS1

RAS

CAS

WE
CKE0
CKE1

R6 10K_4R6 10K_4
R5 10K_4R5 10K_4

SMbus address A4

M_A_CLK0
M_A_CLK0#
M_A_CLK1
M_A_CLK1#

M_A_BS#[0..2]
M_A_ODT[0..1]

123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194

10
26
52
67
130
147
170
185
13
11
31
29
51
49
70
68
131
129
148
146
169
167
188
186

110
115
108
113
109
79
80

CKEA 0,1

2

M_B_DQ36
M_B_DQ33
M_B_DQ34
M_B_DQ39
M_B_DQ37
M_B_DQ32
M_B_DQ35
M_B_DQ38
M_B_DQ40
M_B_DQ41
M_B_DQ46
M_B_DQ43
M_B_DQ45
M_B_DQ44
M_B_DQ42
M_B_DQ47
M_B_DQ55
M_B_DQ49
M_B_DQ51
M_B_DQ53
M_B_DQ48
M_B_DQ52
M_B_DQ50
M_B_DQ54
M_B_DQ56
M_B_DQ57
M_B_DQ63
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ58
M_B_DQ62

M_B_DQM0
M_B_DQM1
M_B_DQM2
M_B_DQM3
M_B_DQM4
M_B_DQM5
M_B_DQM6
M_B_DQM7
M_B_DQS0
M_B_DQS#0
M_B_DQS1
M_B_DQS#1
M_B_DQS2
M_B_DQS#2
M_B_DQS3
M_B_DQS#3
M_B_DQS4
M_B_DQS#4
M_B_DQS5
M_B_DQS#5
M_B_DQS6
M_B_DQS#6
M_B_DQS7
M_B_DQS#7

M_B_CS#0
M_B_CS#1
M_B_RAS#
M_B_CAS#
M_B_WE#
M_B_CKE0
M_B_CKE1

VCC3

3

M_A_CLK0# 8
M_A_CLK1 8
M_A_CLK1# 8
M_A_BS#[0..2] 9,16 M_A_DQS#[0..7] 9
M_A_ODT[0..1] 8,16

PM_EXTTS#18

SB_MA148,16

M_A_DQM[0..7]
M_A_DQ[0..63]
M_A_DQS[0..7]
M_A_DQS#[0..7]
M_A_A[13..0]

SMDDR_VREF_DIMM

1.8VSUS

M_B_ODT0
M_B_ODT1

R50 *0_4R50 *0_4

M_B_A13

M_A_DQM[0..7] 9
M_A_DQ[0..63] 9
M_A_DQS[0..7] 9

M_A_A[13..0] 9,16

CN11B

CN11B

1

VREF

81

VDD_1

82

VDD_2

87

VDD_3

88

VDD_4

95

VDD_5

96

VDD_6

103

VDD_7

104

VDD_8

111

VDD_9

112

VDD_10

117

VDD_11

118

VDD_12

114

ODT0

119

ODT1

50

NC_1

69

NC_2

83

NC_3

84

NC_4/A15

86

NC_5/A14

116

NC_6/A13

120

NC_7

163

NC_8

162

VSS_45

PC2100 DDR2 SDRAM

165
168
171
172
177
178
183
184
187
190
193
196
201

PC2100 DDR2 SDRAM

VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58

FOX=DDR-AS0A426-MAR-200P

FOX=DDR-AS0A426-MAR-200P

VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32

SO-DIMM (200P)

SO-DIMM (200P)

VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_59

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9

4

2
3
8
9
12
15
18
21
24
27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
202

M_B_CKE[0..1]
M_B_CS#[0..1]

M_B_RAS#
M_B_CAS#
M_B_WE#

M_A_DQ1
M_A_DQ5
M_A_DQ3
M_A_DQ2
M_A_DQ4
M_A_DQ0
M_A_DQ7
M_A_DQ6
M_A_DQ13
M_A_DQ8
M_A_DQ15
M_A_DQ10
M_A_DQ9
M_A_DQ12
M_A_DQ14
M_A_DQ11
M_A_DQ16
M_A_DQ21
M_A_DQ19
M_A_DQ23
M_A_DQ20
M_A_DQ17
M_A_DQ18
M_A_DQ22
M_A_DQ24
M_A_DQ28
M_A_DQ31
M_A_DQ30
M_A_DQ29
M_A_DQ25
M_A_DQ26
M_A_DQ27

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12

M_A_BS#0
M_A_BS#1
M_A_BS#2

M_A_CLK0
M_A_CLK0#

M_A_CLK1
M_A_CLK1#

CGCLK_SMB
CGDAT_SMB
DIM1_SA0
DIM1_SA1

VCC3

5

M_B_CKE[0..1] 8,16

M_B_RAS# 9,16
M_B_CAS# 9,16
M_B_WE# 9,16

CN12A

CN12A

5

DQ0

7

DQ1

17

DQ2

19

DQ3

4

DQ4

6

DQ5

14

DQ6

16

DQ7

23

DQ8

25

DQ9

35

DQ10

37

DQ11

20

DQ12

22

DQ13

36

DQ14

38

DQ15

43

DQ16

45

DQ17

55

DQ18

57

DQ19

44

DQ20

46

DQ21

56

DQ22

58

DQ23

61

DQ24

63

DQ25

73

DQ26

75

DQ27

62

DQ28

64

DQ29

74

DQ30

76

DQ31

102

A0

101

A1

100

A2

99

A3

98

A4

97

A5

94

A6

92

A7

93

A8

91

A9

105

A10/AP

90

A11

PC2100 DDR2 SDRAM SO-DIMM

89

107
106

85
30

32

164
166

197
195
198
200

199

PC2100 DDR2 SDRAM SO-DIMM

A12
BA0

BA1
NC/BA2

CLK0
CLK0

CLK1
CKL1

SCL
SDA
SA0
SA1

VDDSPD

FOX=DDR-AS0A426-M2R-RVS-200P

FOX=DDR-AS0A426-M2R-RVS-200P

R4 10K_4R4 10K_4
R3 10K_4R3 10K_4

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DM0
DM1
DM2
DM3
DM4
DM5
DM6

DM7
DQS0
DQS0
DQS1
DQS1

(200P)

(200P)

DQS2
DQS2
DQS3
DQS3
DQS4
DQS4
DQS5
DQS5
DQS6
DQS6
DQS7
DQS7

CS0

CS1

RAS

CAS

WE
CKE0
CKE1

6

M_B_CLK0
M_B_CLK0#
M_B_CLK1
M_B_CLK1#
M_B_BS#[0..2]
M_B_ODT[0..1]

123
125
135
137
124
126
134
136
141
143
151
153
140
142
152
154
157
159
173
175
158
160
174
176
179
181
189
191
180
182
192
194

10
26
52
67
130
147
170
185
13
11
31
29
51
49
70
68
131
129
148
146
169
167
188
186

110
115
108
113
109
79
80

CKEB 0,1

H 5.2H 9.2

DIM1_SA0
DIM1_SA1DIM2_SA0

M_A_DQ32
M_A_DQ35
M_A_DQ34
M_A_DQ39
M_A_DQ33
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ40
M_A_DQ41
M_A_DQ46
M_A_DQ42
M_A_DQ45
M_A_DQ44
M_A_DQ43
M_A_DQ47
M_A_DQ52
M_A_DQ48
M_A_DQ55
M_A_DQ54
M_A_DQ53
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ60
M_A_DQ56
M_A_DQ62
M_A_DQ58
M_A_DQ57
M_A_DQ61
M_A_DQ59
M_A_DQ63

M_A_DQM0
M_A_DQM1
M_A_DQM2
M_A_DQM3
M_A_DQM4
M_A_DQM5
M_A_DQM6
M_A_DQM7
M_A_DQS0
M_A_DQS#0
M_A_DQS1
M_A_DQS#1
M_A_DQS2
M_A_DQS#2
M_A_DQS3
M_A_DQS#3
M_A_DQS4
M_A_DQS#4
M_A_DQS5
M_A_DQS#5
M_A_DQS6
M_A_DQS#6
M_A_DQS7
M_A_DQS#7

M_A_CS#0
M_A_CS#1
M_A_RAS#
M_A_CAS#
M_A_WE#
M_A_CKE0
M_A_CKE1

M_B_CLK0 8
M_B_CLK0# 8
M_B_CLK1 8
M_B_CLK1# 8
M_B_BS#[0..2] 9,16
M_B_ODT[0..1] 8,16

SMDDR_VREF_DIMM

PM_EXTTS#08

SA_MA148,16

7

M_B_DQM[0..7]
M_B_DQ[0..63]
M_B_DQS[0..7]
M_B_DQS#[0..7]
M_B_A[13..0]

1.8VSUS

M_A_ODT0
M_A_ODT1

R46 *0_4R46 *0_4

M_A_A13

8

M_B_DQM[0..7] 9M_B_CS#[0..1] 8,16
M_B_DQ[0..63] 9
M_B_DQS[0..7] 9
M_B_DQS#[0..7] 9
M_B_A[13..0] 9,16

CN12B

CN12B

1

VREF

81

VDD_1

82

VDD_2

87

VDD_3

88

VDD_4

95

VDD_5

96

VDD_6

103

VDD_7

104

VDD_8

111

VDD_9

112

VDD_10

117

VDD_11

118

VDD_12

114

ODT0

119

ODT1

50

NC_1

69

NC_2

83

NC_3

84

NC_4/A15

86

NC_5/A14

116

NC_6/A13

120

NC_7

163

NC_8

162

VSS_45

165

VSS_46

168

VSS_47

171

VSS_48

172

VSS_49

177

VSS_50

178

VSS_51

183

VSS_52

184

VSS_53

187

VSS_54

190

VSS_55

193

VSS_56

196

VSS_57

201

VSS_58

FOX=DDR-AS0A426-M2R-RVS-200P

FOX=DDR-AS0A426-M2R-RVS-200P

VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32

PC2100 DDR2 SDRAM

SO-DIMM (200P)

PC2100 DDR2 SDRAM

SO-DIMM (200P)

VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_59

15

2

VSS_1

3

VSS_2

8

VSS_3

9

VSS_4

12

VSS_5

15

VSS_6

18

VSS_7

21

VSS_8

24

VSS_9

27
28
33
34
39
40
41
42
47
48
53
54
59
60
65
66
71
72
77
78
121
122
127
128
132
133
138
139
144
145
149
150
155
156
161
202

SMbus address A0

1.8VSUS

C94

C94

2.2U_6

2.2U_6

SMDDR_VREF_DIMM

D D

Place these Caps near So-Dimm1.

C61

C165

C165
.1U_4

.1U_4

C55

C55

2.2U_6

2.2U_6

C167

C167

2.2U_6

2.2U_6

C342

C342

2.2U_6

2.2U_6

C331

C331

2.2U_6

2.2U_6

VCC3

C26

C26

2.2U_6

2.2U_6

C110

C110

2.2U_6

2.2U_6

C61
.1U_4

.1U_4

C25

C25
.1U_4

.1U_4

C343

C343
.1U_4

.1U_4

C335

C335
.1U_4

.1U_4

C330

C330
.1U_4

.1U_4

C109

C109
.1U_4

.1U_4

C68

C68
.1U_4

.1U_4

SO-DIMM BYPASS PLACEMENT :

1.8VSUS

C69

C69

2.2U_6

2.2U_6

SMDDR_VREF_DIMM

C162

C162
.1U_4

.1U_4

Place these Caps near So-Dimm2.

C346

C338

C338

2.2U_6

2.2U_6

C164

C164

2.2U_6

2.2U_6

C346

2.2U_6

2.2U_6

VCC3

C63

C63

2.2U_6

2.2U_6

C23

C23

2.2U_6

2.2U_6

C81

C81

2.2U_6

2.2U_6

C80

C20

C20
.1U_4

.1U_4

C80
.1U_4

.1U_4

C340

C340
.1U_4

.1U_4

C347

C347
.1U_4

.1U_4

SO-DIMM BYPASS PLACEMENT :

C334

C334
.1U_4

.1U_4

C92

C92
.1U_4

.1U_4

C53

C53
.1U_4

.1U_4

Place these Caps near So-Dimm1. Place these Caps near So-Dimm2
No Vias Between the Trace of PIN to CAP.

1

2

3

4

No Vias Between the Trace of PIN to CAP.

5

SMDDR_VREF

C166 470P_4C166 470P_4

SMDDR_VREF_DIMM

1 2

R64 *10K_6R64 *10K_6

change2:SMDDR_VREF_DIMM is from SMDDR_VREF;
wrong connection of SMDDR_VTERM and SMDDR_VREF

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

6

Date: Sheet

R68 0_6R68 0_6

R63

R63

*10K_6

*10K_6

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

PROJECT : PL3

DDR2 SD-DIMM

DDR2 SD-DIMM

DDR2 SD-DIMM

7

1.8VSUS

SMDDR_VREF

15 38Wednesday, January 10, 2007

15 38Wednesday, January 10, 2007

15 38Wednesday, January 10, 2007

A

A

A

of

of

of

8

1

2

3

4

5

6

7

8

DDRII DUAL CHANNEL A,B.

A A

16

DDRII A CHANNEL DDRII B CHANNEL

M_A_A[13..0] M_B_A[13..0]
SMDDR_VTERM

SMDDR_VTERM

SMDDR_VTERM

C48

C48

C103

.1U_4

.1U_4

C103
.1U_4

.1U_4

M_A_ODT0
M_A_A13
M_A_A8
M_A_A5
M_A_A3
M_A_A1

M_A_CKE1
M_A_A11
M_A_A10
M_A_BS#0
M_A_A7
M_A_A6
M_A_A2
M_A_A4

M_A_BS#1
M_A_A9
M_A_A12

C50

C50
.1U_4

.1U_4

B B

M_A_ODT08,15

M_A_CKE18,15

M_A_BS#09,15

M_A_RAS#9,15

M_A_BS#19,15

C C

M_A_WE#9,15

M_A_CAS#9,15

SA_MA148,15

C75

C75

C132

C132

.1U_4

.1U_4

.1U_4

.1U_4

RP3 56X2RP3 56X2
RP17 56X2RP17 56X2
RP12 56X2RP12 56X2

RP24 56X2RP24 56X2
RP8 56X2RP8 56X2
RP21 56X2RP21 56X2
RP15 56X2RP15 56X2

RP6 56X2RP6 56X2
RP26 56X2RP26 56X2
RP4 56X2RP4 56X2

C77

C77
.1U_4

.1U_4

1
3
1
3
1
3

1
3
1
3
1
3
1
3

1
3
1
3
1
3

R27 56_4R27 56_4

M_A_A[13..0] 9,15 M_B_A[13..0] 9,15

C82

C82
.1U_4

.1U_4

SMDDR_VTERM 36,37

C59

C59

C136

C136

.1U_4

.1U_4

.1U_4

.1U_4

C112

C112
.1U_4

.1U_4

C141

C141
.1U_4

.1U_4

C88

C88
.1U_4

.1U_4

C113

C113
.1U_4

.1U_4

SMDDR_VTERM

C54

C54
.1U_4

.1U_4

C62

C62
.1U_4

.1U_4

C126

C126
.1U_4

.1U_4

C123

C123
.1U_4

.1U_4

C105

C105
.1U_4

.1U_4

C121

C121
.1U_4

.1U_4

C76

C76
.1U_4

.1U_4

Layout note: Place one cap close to every 2 pullup resistors terminated to SMDDR_VTERM

RP14 56X2RP14 56X2

2
4
2
4
2
4

2
4
2
4
2
4
2
4

2
4
2
4
2
4

SMDDR_VTERM

SMDDR_VTERM

SMDDR_VTERM

M_B_BS#19,15

M_B_BS#29,15

M_B_CKE08,15
M_B_RAS#9,15

M_B_BS#09,15

M_B_CAS#9,15

M_B_WE#9,15

SB_MA148,15

M_B_A0
M_B_A5
M_B_A1
M_B_A8
M_B_A3

M_B_A4
M_B_A2
M_B_A12
M_B_A9
M_B_A7
M_B_A6

M_B_A13

M_B_A10

1
3

RP13 56X2RP13 56X2

1
3

RP18 56X2RP18 56X2

1
3

RP16 56X2RP16 56X2

1
3

RP19 56X2RP19 56X2

1
3

RP22 56X2RP22 56X2

1
3

RP25 56X2RP25 56X2

1
3

RP11 56X2RP11 56X2

1
3

RP5 56X2RP5 56X2

1
3

RP9 56X2RP9 56X2

1
3

R24 56_4R24 56_4

2
4
2
4
2
4

2
4
2
4
2
4
2
4

2
4
2
4
2
4

C65

C65
.1U_4

.1U_4

C129

C129

C122

C122

.1U_4

.1U_4

.1U_4

.1U_4

SMDDR_VTERM

SMDDR_VTERM
SMDDR_VTERM

C45

C45
.1U_4

.1U_4

C73

C73
.1U_4

.1U_4

C128

C128
.1U_4

.1U_4

RP10 56X2RP10 56X2

M_A_CS#08,15

M_B_CS#08,15

M_B_ODT08,15
M_B_ODT18,15
M_B_CS#18,15
M_A_CS#18,15
M_A_ODT18,15
M_B_CKE18,15

M_A_BS#29,15

M_A_CKE08,15

D D

1

2

3

4

5

M_A_A0

M_A_ODT1
M_B_A11

6

1
3

RP7 56X2RP7 56X2

1
3

RP1 56X2RP1 56X2

1
3

RP2 56X2RP2 56X2

1
3

RP23 56X2RP23 56X2

1
3

RP20 56X2RP20 56X2

1
3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

2
4
2
4
2
4
2
4
2
4
2
4

DDR2 RES.ARRAY

DDR2 RES.ARRAY

DDR2 RES.ARRAY

7

SMDDR_VTERM

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

PROJECT : PL3

A

A

A

16 38Wednesday, January 10, 2007

16 38Wednesday, January 10, 2007

16 38Wednesday, January 10, 2007

of

of

of

8

5

D16

D16
CH500H-40

CH500H-40

D15

D15
CH500H-40

CH500H-40

VCCRTC

VCCRTC

R323

R323
20K_6

20K_6

R322

R322
1M_6

1M_6

R326

R326

1K_6

1K_6

CKL:1n ~ 20nF

C428

C428
1U_6

1U_6

20MIL20MIL

SATA_LED#25
SATA_RXN025

SATA_RXP025
SATA_TXN025
SATA_TXP025

RTC

3VPCU

VCCRTC_2

R321

R321
1K_6

R332

R332

4.7K_6

4.7K_6

R328

R328
15K_6

15K_6

1K_6

12

CN19

CN19
BATCON

BATCON

R331

R331

VCCRTC_1 VCCRTC_3

1.2K_6

1.2K_6

D D

5VPCU

C C

B B

C429

C429
1U_6

1U_6

CLK_PCIE_SATA#3
CLK_PCIE_SATA3

Q16

Q16

13

MMBT3904

MMBT3904

2

Place near to Mini-door

12

G1

G1
*SHORT_ PAD1

*SHORT_ PAD1

1.5V_PCIE

C179 3900P_4C179 3900P_4
C175 3900P_4C175 3900P_4

R295

R295

10K_6

10K_6

R117 24.9_4R117 24.9_4

<check list>
L<500mils

4

R176 24.9_4R176 24.9_4

ACZ_SDIN026

T169T169
T163T163

T168T168

T43T43
T45T45

C369 10P_4C369 10P_4

32.768KHZ

32.768KHZ

C377 10P_4C377 10P_4

CLK_32KX1
CLK_32KX2

RTCRST#
SM_INTRUDER#
ICH_INTVRMEN

LAN100_SLP

T186T186
T98T98
T108T108

T187T187
T191T191

T109T109
T62T62
T104T104

T155T155

GLAN_COMP_SB

ACZ_BCLK
ACZ_SYNC_ICH

ACZ_RST_ICH#
ACZ_SDIN0

T164T164
T157T157
T42T42

ACZ_SDOUT_ICH

T44T44
T34T34

SATA_LED#

SATA_TXN0_C
SATA_TXP0_C

SATA_BIAS

3

CLK_32KX1

23

Y3

Y3

4 1

CLK_32KX2

AG25

AF24
AF23

AD22

AF25

AD21

D22
C21

B21
C22

D21
E20
C20

AH21

D25
C25

AJ16
AJ15

AE14

AJ17
AH17
AH15
AD13

AE13
AE10

AG14

AF10

AF6
AF5
AH5
AH6

AG3
AG4

AJ4
AJ3

AF2
AF1
AE4
AE3

AB7
AC6

AG1
AG2

R294

R294
10M_6

10M_6

U18A

U18A

RTCX1
RTCX2

RTCRST#
INTRUDER#
INTVRMEN

LAN100_SLP

B24

GLAN_CLK
LAN_RSTSYNC
LAN_RXD0

LAN_RXD1
LAN_RXD2

LAN_TXD0
LAN_TXD1
LAN_TXD2

GLAN_DOCK#/GPIO13
GLAN_COMPI

GLAN_COMPO
HDA_BIT_CLK

HDA_SYNC
HDA_RST#
HDA_SDIN0

HDA_SDIN1
HDA_SDIN2
HDA_SDIN3

HDA_SDOUT
HDA_DOCK_EN#/GPIO33

HDA_DOCK_RST#/GPIO34
SATALED#
SATA0RXN

SATA0RXP
SATA0TXN
SATA0TXP

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA_CLKN
SATA_CLKP

SATARBIAS#
SATARBIAS

ICH8M REV 1.0

ICH8M REV 1.0

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

FWH4/LFRAME#

LDRQ0#

LDRQ1#/GPIO23

RTCLAN / GLAN

LPCCPU

RTCLAN / GLAN

LPCCPU

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

CPUPWRGD/GPIO49

IGNNE#

RCIN#

STPCLK#

THRMTRIP#

IHDA

IHDA

IDE

IDE

SATA

SATA

DCS1#
DCS3#

DIOR#

DIOW#

DDACK#

IDEIRQ

IORDY

DDREQ

INIT#

INTR

SMI#

DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8

DD9
DD10
DD11
DD12
DD13
DD14
DD15

DA0

DA1

DA2

E5
F5
G8
F6

C4
G9

E6
AF13

AG26
AF26

AE26
AD24
AG29
AF27
AE24

AC20
AH14

AD23

NMI

AG28
AA24
AE27
AA23

TP8

V1
U2
V3
T1
V4
T5
AB2
T6
T3
R2
T4
V6
V5
U1
V2
U6

AA4
AA1
AB3

Y6
Y5

W4
W3
Y2
Y3
Y1
W5

LDRQ#1

H_DPRSTP#_R
H_DPSLP#_R

RCIN#

H_SMI#

H_THERMTRIP_R

PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

PDA0
PDA1
PDA2

IRQ14
PDIORDY

T77T77
T86T86

T51T51

LDRQ#1 23

R90 0_4R90 0_4
R119 0_4R119 0_4

2

LAD0 23,31
LAD1 23,31
LAD2 23,31
LAD3 23,31

LFRAME# 23,31

GATEA20 31
H_A20M# 4

H_PWRGD 4
H_IGNNE# 4
H_INIT# 4

H_INTR 4
RCIN# 31

H_NMI 4
H_SMI# 4

H_STPCLK# 4

PDD[15:0] 25

PDA[2:0] 25

PDCS1# 25
PDCS3# 25

PDIOR# 25
PDIOW# 25
PDDACK# 25
IRQ14 25

PDIORDY 25

PDDREQ 25

0810 UR FAE:
RCIN# DOESN'T NEED PU

1.05V_V_CPU_IO

R126

R126
*56.2_4

*56.2_4

R151 24_6R151 24_6

R92

R92
*56.2_4

*56.2_4

1.05V_V_CPU_IO

RCIN#

GATEA20
LDRQ#1

ICH_DPRSTP# 4,8,34
H_DPSLP# 4

R130

R130

56.2/F_4

56.2/F_4
R136 *0_4R136 *0_4

Placement close SB L<2"

HD Audio Link for ALC268

ACZ_SDOUT_ICH

ACZ_SYNC_ICH

ACZ_BCLK

ACZ_RST_ICH#

R303 33_4R303 33_4

R305 33_4R305 33_4

R302 33_4R302 33_4

R307 33_4R307 33_4

1

VCC3

VCC3

R271

R271
*10K_6

*10K_6

VCC1.05

R91

R91
56/F_6

56/F_6

PM_THRMTRIP# 4,8

C392

C392
*10P_4

*10P_4

C390

C390
*10P_4

*10P_4

C391

C391
*10P_4

*10P_4

VCC3

R82

R82
10K_6

10K_6

H_FERR# 4

ACZ_SDOUT 26

ACZ_SYNC 26

ACZ_BIT_CLK 26

ACZ_RST# 26

17

R199

R199
10K_6

10K_6

SB Strap

Internal VR Enable :
VccSus1.05,VccSus1.5,VccCL1.5

INTVRMEN

VCCRTC VCCRTC

A A

Low = Internal VR disable
High = Internal VR
enable(Default)

R73

R73
332K/F_6

332K/F_6

ICH_INTVRMEN LAN100_SLP

R102

R102
*0_4

*0_4

5

Internal VR Enable :
VccLAN1.05,VccCL1.05

R127

R127
332K/F_6

332K/F_6

R115

R115
*0_4

*0_4

Low = Internal VR disable
High = Internal VR
enable(Default)

LAN100_SLP

XOR Chain Entrance Strap

HDA_SDOUT

ICH_RSV0

0

0

1

1 Set PCIE port config bit 1

VCC3

R81

R81
*1K_6

*1K_6

ACZ_SDOUT_ICH

R278

R278
*1K_4

*1K_4

4

Description

0

1

1

RSVD

Enter XOR Chain

Normal opration(Default)0

ICH_TP3 19

3

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

ICH8-HOST

ICH8-HOST

ICH8-HOST

Date: Sheet

Date: Sheet

2

Date: Sheet

PROJECT : PL3

1

A

A

A

of

of

of

17 38Wednesday, January 10, 2007

17 38Wednesday, January 10, 2007

17 38Wednesday, January 10, 2007

5

PCIE_RXN023
PCIE_RXP023

MINI CARD PCI-E

PCIE-LAN

D D

USB OverCurrent

USBOC#6
USBOC#2

USBOC#4 USBOC#1

C C

3VSUS

USBOC#8
USBOC#9

6
7
8
9

10

PCIE_TXN023
PCIE_TXP023

PCIE_RXN124
PCIE_RXP124
PCIE_TXN124
PCIE_TXP124

RP27

RP27

10KX8

10KX8
R83 10K_4R83 10K_4

R282 10K_4R282 10K_4

5
4
3
2
1

3VSUS

USBOC#0USBOC#3
USBOC#7

USBOC#5

3VSUS
3VSUS

C398 .1U_4C398 .1U_4
C400 .1U_4C400 .1U_4

C401 .1U_4C401 .1U_4
C404 .1U_4C404 .1U_4

PCI Pull-High

RP39

STOP#
REQ2#
FRAME#
REQ1#

VCC3

B B

A A

SERR#
INTA#
INTE#
INTC#

VCC3

INTH#
REQ0#

VCC3

RP39

6
7
8
9

10

8.2KX8

8.2KX8

RP38

RP38

6
7
8
9

10

8.2KX8

8.2KX8

RP40

RP40

6
7
8
9

10

8.2KX8

8.2KX8

VCC3

5

REQ3#

4

INTD#

3

DEVSEL#

2

TRDY#

1

VCC3

5
4
3

INTG#

2

INTF#

1

VCC3

5

IRDY#

4

PERR#

3

INTB#

2

LOCK#

1

4

U18D

U18D

P27

PERN1

P26

PCIE_TXN0_C
PCIE_TXP0_C

PCIE_TXN1_C
PCIE_TXP1_C

T59T59
T60T60
T175T175
T176T176

T75T75
T74T74
T177T177
T178T178

T90T90
T87T87
T179T179
T180T180

T102T102
T103T103
T183T183
T184T184

T105T105
T185T185
T81T81

T107T107
T61T61

T26T26
T37T37
T32T32
T31T31
T40T40
T30T30
T25T25
T160T160
T33T33
T159T159

T217T217
T218T218
T219T219
T220T220
T221T221
T222T222
T223T223
T224T224
T225T225
T226T226
T227T227
T228T228
T229T229
T230T230
T231T231
T232T232
T233T233
T234T234
T235T235
T236T236
T237T237
T238T238 T206T206
T239T239
T240T240
T241T241
T242T242
T243T243
T244T244
T245T245
T246T246
T247T247
T248T248

T117T117
T205T205
T113T113
T190T190

USBOC#0
USBOC#1
USBOC#2
USBOC#3
USBOC#4
USBOC#5
USBOC#6
USBOC#7
USBOC#8
USBOC#9

SPI_CS1#

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

INTA#
INTB#
INTC#
INTD#

PERP1

N29

PETN1

N28

PETP1

M27

PERN2

M26

PERP2

L29

PETN2

L28

PETP2

K27

PERN3

K26

PERP3

J29

PETN3

J28

PETP3

H27

PERN4

H26

PERP4

G29

PETN4

G28

PETP4

F27

PERN5

F26

PERP5

E29

PETN5

E28

PETP5

D27

PERN6/GLAN_RXN

D26

PERP6/GLAN_RXP

C29

PETN6/GLAN_TXN

C28

PETP6/GLAN_TXP

C23

SPI_CLK

B23

SPI_CS0#

E22

SPI_CS1#

D23

SPI_MOSI

F21

SPI_MISO

AJ19

OC0#

AG16

OC1#/GPIO40

AG15

OC2#/GPIO41

AE15

OC3#/GPIO42

AF15

OC4#/GPIO43

AG17

OC5#/GPIO29

AD12

OC6#/GPIO30

AJ18

OC7#/GPIO31

AD14

OC8#

AH18

OC9#

ICH8M REV 1.0

ICH8M REV 1.0

U18B

U18B

D20

AD0

E19

AD1

D19

AD2

A20

AD3

D17

AD4

A21

AD5

A19

AD6

C19

AD7

A18

AD8

B16

AD9

A12

AD10

E16

AD11

A14

AD12

G16

AD13

A15

AD14

B6

AD15

C11

AD16

A9

AD17

D11

AD18

B12

AD19

C12

AD20

D10

AD21

C7

AD22

F13

AD23

E11

AD24

E13

AD25

E12

AD26

D8

AD27

A6

AD28

E8

AD29

D6

AD30

A3

AD31

Interrupt I/F

Interrupt I/F

F9

PIRQA#

B5

PIRQB#

C5

PIRQC#

A10

PIRQD#

ICH8M REV 1.0

ICH8M REV 1.0

PCI-Express

PCI-Express

SPI

SPI

USB

USB

PCI

PCI

REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55

PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

DMI_IRCOMP

PCIRST#
DEVSEL#

FRAME#

PLTRST#

3

V27

DMI0RXN

V26

DMI0RXP

U29

DMI0TXN

U28

DMI0TXP

Y27

DMI1RXN

Y26

DMI1RXP

W29

DMI1TXN

W28

DMI1TXP

AB26

DMI2RXN

AB25

DMI2RXP

AA29

DMI2TXN

AA28

DMI2TXP

AD27

DMI3RXN

AD26

DMI3RXP

AC29

DMI3TXN

AC28

DMI3TXP

T26

DMI_CLKN

T25

DMI_CLKP

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

USBRBIAS

IRDY#

PAR

PME#

Y23
Y24

G3
G2
H5
H4
H2
H1
J3
J2
K5
K4
K2
K1
L3
L2
M5
M4
M2
M1
N3
N2

F2
F3

A4
D7
E18
C18
B19
F18
A11
C10

C17
E15
F16
E17

C8
D9
G6
D16
A7
B7
F10
C16
C9
A17

AG24
B10
G7

F8
G11
F12
B3

PCLK_ICH

USB_RBIAS_PN

25mils/15mils

REQ0#
GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#

IRDY#

DEVSEL#
PERR#
LOCK#
SERR#
STOP#
TRDY#
FRAME#

PLT_RST-R#
PCLK_ICH

INTE#
INTF#
INTG#
INTH#

R180 *0_4R180 *0_4

DMI_ZCOMP

Direct Media Interface

Direct Media Interface

USBRBIAS#

REQ0#
GNT0#

C/BE0#
C/BE1#
C/BE2#
C/BE3#

PERR#

PLOCK#

SERR#
STOP#
TRDY#

PCICLK

DMI_RXN0 8
DMI_RXP0 8
DMI_TXN0 8
DMI_TXP0 8

DMI_RXN1 8
DMI_RXP1 8
DMI_TXN1 8
DMI_TXP1 8

DMI_RXN2 8
DMI_RXP2 8
DMI_TXN2 8
DMI_TXP2 8

DMI_RXN3 8
DMI_RXP3 8
DMI_TXN3 8
DMI_TXP3 8

CLK_PCIE_ICH# 3
CLK_PCIE_ICH 3

DMI_IRCOMP_R

T76T76
T56T56

T69T69
T174T174

T55T55
T53T53
T57T57
T170T170
T52T52
T54T54

R316

R316

22.6_6

22.6_6

T110T110
T70T70

T112T112
T189T189

C249 *33P_4C249 *33P_4

T252T252
T249T249

T215T215
T216T216
T192T192
T100T100
T111T111
T89T89
T188T188
T106T106

T209T209
T210T210
T211T211
T212T212

T213T213
T214T214

T207T207
T118T118
T171T171
T119T119

T172T172
T208T208

1.5V_PCIE

R147

R147

24.9_4

24.9_4

15/15mils

USBP0- 29
USBP0+ 29

USBP2- 29
USBP2+ 29

USBP4- 23
USBP4+ 23
USBP5- 22
USBP5+ 22
USBP6- 29
USBP6+ 29

<CRB>
USB_RBIAS_PN<500mils

USB Connector

USB Connector

PCIE
CARD READER

USB Connector

PCIRST# 23

2

PLTRST#

PLT_RST-R# 8

PLT_RST-R#

1

A16 SWAP Override strap

PCI_GNT#3

GNT3#

Low = A16 swap override enabled
High = Default

R178 *1K_4R178 *1K_4

ICH8 Boot BIOS select

SPI_CS#1PCI_GNT#0

SPI_CS1#

R172 *1K_4R172 *1K_4

GNT0#

R177 *1K_4R177 *1K_4

PCI ROUTING
TABLE

REQ0# / GNT0# R5C832

VCC3 VCC3

U3

U3

2
1

TC7SH08FU

TC7SH08FU

IDSEL

AD17

3 5

Boot BIOS Location

SPI(Default)10

PCI01

LPC11

INTERUPT

INTA#,INTB#

C170

C170
.1U_6

.1U_6

4

R67

R67
100K_6

100K_6

DEVICE

PLTRST# 19,23,24,25,31

18

for EMI request

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

ICH8-PCI E

ICH8-PCI E

ICH8-PCI E

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet

PROJECT : PL3

1

A

A

A

of

18 38Wednesday, January 10, 2007

18 38Wednesday, January 10, 2007

18 38Wednesday, January 10, 2007

5

VCC3VCC3

C368

C368

.1U_4

.1U_4

U14

U14

1

5

VR_PWRGD_CK410#34

D D

PCLK_SMB3,23

<FAE>
CRB STP_PCI# PU is no stuff.
CRB STP_CPU# always keeps high to
ensure ME alive in M1 state.
(CLK_MCH_BCLK/# must keep alive to
make ME work)
I think there will be update for this design,
I suggest you to keep PU and 0　
isolation resistors for this signal.

C C

MCH_ICH_SYNC#8

B B

DELAY_VR_PWRGOOD6,8,34

R266

R266
10K_6

10K_6

A A

R279

R279
*10K_6

*10K_6

PDAT_SMB3,23

PM_STPPCI#3
PM_STPCPU#3

CLKRUN#31

PCIE_WAKE#23,24

SERIRQ23,31

THERM_ALERT#6

KBSMI#31

LID591#14,31
SCI#31

ICH_TP317

VCC3 VCC3VCC3

R276

R276
*10K_6

*10K_6

R275

R275
10K_6

10K_6

5

2

VR_PWRGD_CK410

43

NL17SZ14DFT2G

NL17SZ14DFT2G

PCLK_SMB
PDAT_SMB

VCC3

R99

R99

R97

R97

*10K_4

*10K_4

*10K_4

*10K_4

CLKRUN#
PCIE_WAKE#

SERIRQ
THERM_ALERT#

KBSMI#
LID591#

SCI#
R5C832_RST#

VCC3

R273

R273
*10K_4

*10K_4

R284 0_4R284 0_4

DELAY_VR_PWRGOOD
ECPWROK

R268

R268
*10K_6

*10K_6

BOARD_ID2BOARD_ID0 BOARD_ID1

R280

R280
10K_6

10K_6

R267

R267
100K_4

100K_4

T28T28

T50T50

T24T24
T41T41

T94T94

SYS_RST#4

PM_BMBUSY#8

T156T156

T162T162

T39T39

T158T158
T47T47

SATACLKREQ#3

T167T167

R308

R308
100K_6

100K_6

SMB_LINK_ALERT#
SMLINK0
SMLINK1

SYS_RST#

R286 0_4R286 0_4

SMB_ALERT#

R96 0_4R96 0_4
R98 0_4R98 0_4

VR_PWRGD_CK410

BOARD_ID0
BOARD_ID1
BOARD_ID3
ICH_GPIO22

ICH_GPIO27
ICH_GPIO28

RST_HDD#25

SPKR26

MCH_ICH_SYNC#_R

3VSUS 3VSUS RVCC3

U17

U17

2
1

TC7SH08FU

TC7SH08FU

3 5

VCC3

4

R301

R301
*10K_6

*10K_6

BOARD_ID3

R306

R306
10K_6

10K_6

DOCKIN#_R

SATACLKREQ#

ICH_GPIO39
ICH_GPIO48

C395

C395

.1U_4

.1U_4

4

AD19
AG21
AC17

AD15
AG12
AG22

AG18
AH11

AC13

AC19
AH12
AG10

AH25
AD16
AG13

AD10

ICH_PWROK

R304

R304
10K_4

10K_4

4

U18C

U18C

AJ26

SMBCLK
SMBDATA
LINKALERT#
SMLINK0

AE19

SMLINK1

AF17

RI#

F4

SUS_STAT#/LPCPD#
SYS_RESET#

BMBUSY#/GPIO0
SMBALERT#/GPIO11

AE20

STP_PCI#/GPIO15
STP_CPU#/GPIO25

CLKRUN#/GPIO32

AE17

WAKE#

AF12

SERIRQ
THRM#

AJ20

VRMPWRGD

AJ22

TP7

AJ8

TACH1/GPIO1

AJ9

TACH2/GPIO6

AH9

TACH3/GPIO7

AE16

GPIO8
GPIO12

AG8

TACH0/GPIO17
GPIO18

AE11

GPIO20
SCLOCK/GPIO22
QRT_STATE0/GPIO27
QRT_STATE1/GPIO28
SATACLKREQ#/GPIO35

AF9

SLOAD/GPIO38

AJ11

SDATAOUT0/GPIO39
SDATAOUT1/GPIO48

AD9

SPKR

AJ13

MCH_SYNC#

AJ21

TP3

ICH8M REV 1.0

ICH8M REV 1.0

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA2GP/GPIO36

SATA

GPIO

SATA

GPIO

SATA3GP/GPIO37

SMB

SMB

Clocks

Clocks

S4_STATE#/GPIO26

SYS

GPIO

SYS

GPIO

DPRSLPVR/GPIO16

BATLOW#
PWRBTN#
LAN_RST#

Power MGTController Link

Power MGTController Link

CK_PWRGD

CLPWROK

CL_DATA0

GPIO

GPIO

MISC

MISC

CL_DATA1
CL_VREF0

CL_VREF1

MEM_LED/GPIO24
ME_EC_ALERT/GPIO10
EC_ME_ALERT/GPIO14

WOL_EN/GPIO9

R293

R293
10K_4

10K_4

AK

AK

R292

R292

2.2K_4

2.2K_4

CLK14
CLK48

SUSCLK

SLP_S3#
SLP_S4#
SLP_S5#

PWROK

RSMRST#

SLP_M#

CL_CLK0
CL_CLK1

CL_RST#

C E

3

B

A

D14

D14

K
A

K

3

2

R285 8.2K_4R285 8.2K_4

AJ12

BOARD_ID2

AJ10

R86 8.2K_4R86 8.2K_4

AF11

R87 8.2K_4R87 8.2K_4

AG11

14M_ICH

AG9

CLKUSB_48RI#

G5
D3
AG23

AF21
AD18

AH27
AE23
AJ14
AE21
C2
AH20
AG27
E1
E3
AJ25
F23

AE18
F22

AF19
D24

AH23
AJ23
AJ27

AJ24
AF22
AG19

Q14

Q14
MMBT3906

MMBT3906

BAV99

BAV99

D13

D13
BAV99

BAV99

T181T181

SLP_S3#
SLP_S4#
SLP_S5#

T154T154

ICH_PWROK

R283 100_4R283 100_4

PM_BATLOW#_R

DNBSWON#

R65 0_4R65 0_4
R66 *100_6R66 *100_6

R319 0_4R319 0_4

R320 0_4R320 0_4

T165T165
T46T46

T35T35

CL_VREF0_SB CL_VREF0_SB

CL_VREF1_SB

3VSUS

R299

R299

4.7K_4

4.7K_4

RSMRST#PM_RSMRST#_R

VCC3

VCC3

14M_ICH 3
CLKUSB_48 3

R104 100_4R104 100_4
R149 100_4R149 100_4

T48T48

R270 100K_4R270 100K_4

R296 *0_4R296 *0_4

CK_PWG 3

ECPWROK

CL_CLK0 8

CL_DATA0 8

CL_RST#0 8

T161T161
T166T166
T36T36
T38T38

FROM uR(EC)TO ICH8

SUSB# 31
SUSC# 31

PM_DPRSLPVR 8,34

DNBSWON# 31

ECPWROK 31
CL_PWROK 8

2

PLTRST# 18,23,24,25,31
RSMRST# 31

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

RSMRST#PM_RSMRST#_R

SMB_LINK_ALERT#
SPKR
DOCKIN#_R
THERM_ALERT#
CLKRUN#
SERIRQ
SCI#
RST_HDD#
ICH_GPIO48
ICH_GPIO22
SATACLKREQ#

INTEL CRB SHOW IT

PM_RSMRST#_R

0.412V

CL_VREF1_SB

0.410V

ICH8-GPIO

ICH8-GPIO

ICH8-GPIO

1

R5C832_RST#
PCLK_SMB
PDAT_SMB
PCIE_WAKE#
PM_BATLOW#_R
RI#
DNBSWON#
SYS_RST#

SMB_ALERT#

KBSMI#
SMLINK0

SMLINK1

ICH_GPIO39

R143 *10K_4R143 *10K_4
R74 2.2K_4R74 2.2K_4
R144 2.2K_4R144 2.2K_4
R132 1K_4R132 1K_4
R139 8.2K_4R139 8.2K_4
R131 8.2K_4R131 8.2K_4
R179 *10K_4R179 *10K_4
R145 10K_4R145 10K_4
R77 10K_4R77 10K_4
R100 10K_4R100 10K_4

R138 10K_4R138 10K_4
R69 10K_4R69 10K_4

R114 10K_4R114 10K_4
R128 *1K_4R128 *1K_4
R118 8.2K_4R118 8.2K_4
R135 8.2K_4R135 8.2K_4
R287 8.2K_4R287 8.2K_4
R125 8.2K_4R125 8.2K_4
R133 10K_4R133 10K_4
R120 10K_4R120 10K_4
R134 10K_4R134 10K_4
R281 10K_4R281 10K_4
R116 10K_4R116 10K_4

R85 10K_4R85 10K_4
R291 10K_4R291 10K_4

VCC3

R182

R182

3.24K_0603F

3.24K_0603F

C246

C246

R181

R181

.1U_4

.1U_4

453/F_4

453/F_4

R76

R76

3.24K_0603F

3.24K_0603F

C178

C178

R88

R88
453/F_4

453/F_4

.1U_4

.1U_4

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

PROJECT : PL3

19 38Wednesday, January 10, 2007

19 38Wednesday, January 10, 2007

19 38Wednesday, January 10, 2007

1

RVCC3

VCC3

of

of

of

A

A

A

5

U18E

U18E

A23

VSS[001]

A5

VSS[002]

AA2

VSS[003]

AA7

VSS[004]

A25

VSS[005]

AB1

D D

C C

B B

AB24
AC11
AC14
AC25
AC26
AC27
AD17
AD20
AD28
AD29

AD3
AD4
AD6
AE1

AE12

AE2

AE22

AD1

AE25

AE5
AE6

AE9
AF14
AF16
AF18

AF3

AF4

AG5

AG6
AH10
AH13
AH16
AH19

AH2
AF28
AH22
AH24
AH26

AH3

AH4

AH8

B11

B14

B17

B20

B22

C24

C26

C27

D12

D15

D18

E21

E24

E23

G10

G13

G19

G23

G25

G26

G27

H25

H28

H29

K23

K28

K29

AJ5

B2

B8

C6

D2
D4

E4
E9

F15
F28

F29

F7
G1
E2

H3
H6

J1
J25
J26
J27

J4

J5

K3

K6

VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]

ICH8M REV 1.0

ICH8M REV 1.0

VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]

VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]

K7
L1
L13
L15
L26
L27
L4
L5
M12
M13
M14
M15
M16
M17
M23
M28
M29
M3
N1
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
N4
N5
N6
P12
P13
P14
P15
P16
P17
P23
P28
P29
R11
R12
R13
R14
R15
R16
R17
R18
R28
R4
T12
T13
T14
T15
T16
T17
T2
U12
U13
U14
U15
U16
U17
U23
U26
U27
U3
U5
V13
V15
V28
V29
W2
W26
W27
Y28
Y29
Y4
AB4
AB23
AB5
AB6
AD5
U4
W24

A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29

5VPCU

4

R330 10_6R330 10_6

VCC1.5

VCC1.5

VCC3

VCC1.5

VCC1.5

3VPCU

21

D17

D17

PDZ5.6B

PDZ5.6B

5VREF_SUS_SB

C437

C437
.1U_4

.1U_4

L13

L13

1 2

BLM21PG600SN1D

BLM21PG600SN1D

L11

L11

1 2

BLM21PG600SN1D

BLM21PG600SN1D

R183 0_6R183 0_6

R327 0_6R327 0_6

R324 0_6R324 0_6

VCC5

R152 100_6R152 100_6

1.5V_PCIE

+

+

C406

C406
220U_7343

220U_7343

VCC1.5

C242

C242
1U_6

1U_6

3V_VCCLAN

C238

C238
.1U_4

.1U_4

1.5V_VCCGLANPLL

C410

C410
10U_6

10U_6

1.5V_VCCGLAN

C416

C416

4.7U_6

4.7U_6

VCC3

C229

C229
22U_8

22U_8

100mA

R288 0_6R288 0_6

C213

C213
1U_6

1U_6

R317 0_6R317 0_6

VCC1.5

C415

C415

2.2U_6

2.2U_6

21

C239

C239
1U_6

1U_6

VCCRTC

D4

PDZ5.6BD4PDZ5.6B

C223

C223
.1U_4

.1U_4

C231

C231
22U_8

22U_8

VCC3

1.5V_APLL

C374

C374
10U_6

10U_6

3

C203

C203
1U_4

1U_4

5VREF_SB
5VREF_SUS_SB

C227

C227

2.2U_6

2.2U_6

C372

C372
1U_6

1U_6

C405

C405
.1U_4

.1U_4

TP_VCCLAN1_05_ICH_1
TP_VCCLAN1_05_ICH_2

3V_VCCLAN

1.5V_VCCGLANPLL

1.5V_VCCGLAN

R325 0_6R325 0_6

C197

C197
.1U_4

.1U_4

C407

C407
.1U_4

.1U_4

C198

C198
.1U_4

.1U_4

C409

C409
.1U_4

.1U_4

AD25

AA25
AA26
AA27
AB27
AB28
AB29

G24

M24
M25

W25

AG7
AH7

AC1
AC2
AC3
AC4
AC5

AC10

AC9

G12
G17

AC7
AD7

W23

G18

G20

A16

T7

G4

D28
D29
E25
E26
E27
F24
F25

H23
H24

J23

J24
K24
K25
L23
L24
L25

N23
N24
N25
P24
P25
R24
R25
R26
R27
T23
T24
T27
T28
T29
U24
U25
V23
V24
V25

Y25
AJ6
AE7

AF7

AJ7

AA5
AA6

H7

D1
F1

L6

L7
M6
M7

F17

F19

A24
A26

A27
B26
B27
B28

B25

U18F

U18F

VCCRTC
V5REF[1]

V5REF[2]
V5REF_SUS
VCC1_5_B[01]

VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]

VCCSATAPLL
VCC1_5_A[01]

VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]

VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]
VCC1_5_A[09]
VCC1_5_A[10]

VCC1_5_A[11]
VCC1_5_A[12]

VCC1_5_A[13]
VCC1_5_A[14]

VCC1_5_A[15]
VCC1_5_A[16]
VCC1_5_A[17]

VCC1_5_A[18]
VCC1_5_A[19]

VCCUSBPLL
VCC1_5_A[20]

VCC1_5_A[21]
VCC1_5_A[22]
VCC1_5_A[23]
VCC1_5_A[24]

VCC1_5_A[25]
VCCLAN1_05[1]

VCCLAN1_05[2]
VCCLAN3_3[1]

VCCLAN3_3[2]
VCCGLANPLL
VCCGLAN1_5[1]

VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]
VCCGLAN1_5[5]

VCCGLAN3_3

ICH8M REV 1.0

ICH8M REV 1.0

VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]

CORE

CORE

VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]
VCC1_05[27]
VCC1_05[28]

VCCA3GP ATXARX

VCCA3GP ATXARX

V_CPU_IO[1]
V_CPU_IO[2]

VCCP_COREVCCPSUSVCCPUSB

VCCP_COREVCCPSUSVCCPUSB

IDE

IDE

PCI

PCI

VCCSUSHDA

VCCSUS1_05[1]
VCCSUS1_05[2]

VCCSUS1_5[1]

VCCSUS1_5[2]
VCCSUS3_3[01]
VCCSUS3_3[02]

VCCSUS3_3[03]
VCCSUS3_3[04]
VCCSUS3_3[05]

USB CORE

USB CORE

VCCSUS3_3[06]
VCCSUS3_3[07]

VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]

GLAN POWER

GLAN POWER

VCCCL3_3[1]
VCCCL3_3[2]

VCCDMIPLL

VCC_DMI[1]
VCC_DMI[2]

VCC3_3[01]
VCC3_3[02]
VCC3_3[03]

VCC3_3[04]
VCC3_3[05]
VCC3_3[06]

VCC3_3[07]
VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]

VCC3_3[14]
VCC3_3[15]
VCC3_3[16]
VCC3_3[17]
VCC3_3[18]
VCC3_3[19]
VCC3_3[20]
VCC3_3[21]
VCC3_3[22]
VCC3_3[23]
VCC3_3[24]

VCCHDA

VCCCL1_05

VCCCL1_5

2

A13
B13
C13
C14
D14
E14
F14
G14
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

R29
AE28

AE29
AC23

AC24
AF29
AD2
AC8

AD8
AE8
AF8

AA3
U7
V7
W1
W6
W7
Y7

A8
B15
B18
B4
B9
C15
D13
D5
E10
E7
F11

AC12
AD11
J6

AF20
AC16
J7
C3
AC18

AC21
AC22
AG20
AH28

P6
P7
C1
N7
P1
P2
P3
P4
P5
R1
R3
R5
R6

G22

VCCCL1_5_INT_ICH

A22
F20

G21

TP_VCCCL1_05_ICH

V3.3M_ICH

VCC1.05

C226

C226
.047U_4

.047U_4

1.5V_VCCDMIPLL

1.25V_VCC_DMI

1.05V_V_CPU_IO

VCC3

3.3V_VCCHDA

3.3V_VCCSUSHDA

TP_VCCSUS1_05_ICH_1
TP_VCCSUS1_05_ICH_2

TP_VCCSUS1_5_ICH_1
TP_VCCSUS1_5_ICH_2

RVCC3

1.5V_VCCDMIPLL

C225

C225
.022U_4

.022U_4

1.05V_V_CPU_IO

3.3V_VCCHDA

3.3V_VCCSUSHDA

R160 0_6R160 0_6

C414

C414
*1U_6

*1U_6

C396

C396
.001U_4

.001U_4

1.25V_VCC_DMI

C387

C387
22U_8

22U_8

C208

C208
.1U_4

.1U_4

C221

C221
.1U_4

.1U_4

C199

C199
.1U_4

.1U_4

C209

C209
.1U_6

.1U_6

T58T58
T49T49

C200

C200
.1U_4

.1U_4

T66T66

R309 0_6R309 0_6
C397

C397
10U_6

10U_6

R300 0_6R300 0_6

C212

C212
.1U_4

.1U_4

C220

C220
.1U_4

.1U_4

R142 0_6R142 0_6

R141 0_6R141 0_6

RVCC3

C182

C182
.022U_4

.022U_4

TP_VCCLAN1_05_ICH_1
TP_VCCLAN1_05_ICH_2

TP_VCCSUS1_05_ICH_1
TP_VCCSUS1_05_ICH_2

VCC3

R146 0_6R146 0_6
C214

C214

4.7U_6

4.7U_6

C191

C191
.1U_4

.1U_4

C224

C224

4.7U_6

4.7U_6

1

VCC1.5

VCC1.25

C244

C244

C250

C250

.1U_4

.1U_4

.1U_4

.1U_4

VCC3

RVCC3

C253 .1U_6C253 .1U_6
C252 .1U_6C252 .1U_6

C237 .1U_6C237 .1U_6
C169 .1U_6C169 .1U_6

20

VCC1.05

VCC3

C245

C245
.1U_4

.1U_4

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

ICH8-POWER

ICH8-POWER

ICH8-POWER

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

PROJECT : PL3

1

A

A

20 38Wednesday, January 10, 2007

20 38Wednesday, January 10, 2007

20 38Wednesday, January 10, 2007

A

of

of

of

A

4 4

3 3

2 2

B

C

D

E

1 1

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

R5C832-1394/SD

R5C832-1394/SD

R5C832-1394/SD

Date: Sheet

Date: Sheet

A

B

C

D

Date: Sheet

PROJECT : PL3

E

A

A

21 38Wednesday, January 10, 2007

21 38Wednesday, January 10, 2007

21 38Wednesday, January 10, 2007

A

of

of

of

A

B

C

D

E

22

4 4

XD_CD#
XD_RB#

MODE_SEL

RST#

XD_CLE

XTLO

XTLI

R345 *0_4R345 *0_4

RFCM1632100M3

RFCM1632100M3

USBP5-18

USBP5+18

3 3

2 2

2

2

3

L34

L34

R342 *0_4R342 *0_4

12

C558

C558

.1U_4

.1U_4

VCC5

12

C559

C559
.1U_4

.1U_4

1
443

1

C561

C561

*4.7U_6

*4.7U_6

VCC3

DM
DP

12

C557

C557
.1U_4

.1U_4

RREF

A3V3
DM
DP

A3V3
VCC5
VCC3
VREG
D3V3

12

C555

C555
.1U_4

.1U_4

C553

C553
1U_4

1U_4

VREG

C560

C560
.1U_4

.1U_4

C556

C556
1U_4

1U_4

R216 0_4R216 0_4

R334 6 .2_4R334 6 .2_4

12

C552

C552
.1U_4

.1U_4

12

GND

10
11
12

U23

U23

1
2
3
4
5
6
7
8
9

AV_PLL
RREF
AV33
DM
DP
AG33
A3V3_OUT
5V_IN
CARD_3V3
VREG
D3V3_OUT
DGND

GND

47

48

46

XTLI

XTLO

AG_PLL

CF_CD#13GPIO014CF_D1015CF_D916CF_D217CF_D8/SM_CD#18CF_D1/XD_CD#19CF_D0/SM_WPM#/SD_WP20CF_A0/SD_CD#21CF_DMACK#22CF_A1/XD_D423CF_DMARQ

GPIO0

XD_CE#

44

45

43

RST#

MODE_SEL

XD_CLE/CF_D3

RTS5158

RTS5158

XD_CD#

XD_WE#

XD_RB#

XD_ALE

XD_RE#

42

XD_CE#/CF_D11

SD_WP

38

39

40

41

XD_ALE/CF_D4

XD_RDY/CF_D13

SD_DAT3/XD_WE#/CF_D5

SD_DAT2/XD_RE#/CF_D12

SD_DAT5/XD_D0/CF_D14

SD_CLK/XD_D1/MS_CLK/CF_D7

SD_DAT6/XD_D7/MS_D3/CF_D15

SD_DAT7/XD_D2/MS_D2/CF_IOWR#

SD_DAT0/XD_D6/MS_D0/CF_RST#

SD_DAT1/XD_D3/MS_D1/CF_IORDY

XD_D4

XD_WP#

37

SD_CMD

SD_DAT4/XD_WP#/CF_D6

D3V3

DGND

CF_CS0#

MS_INS#/CF_IORD#

XD_D5/MS_BS/CF_A2

24

SD_CMD

36

XD_D0

35

XD_D1

34
33
32
31
30
29
28
27
26
25

R214 0_4R214 0_4

D3V3
GND
XD_D7

XD_D2
XD_D6
XD_D3
XD_D5

XD_RE#
XD_CE#
XD_CLE
XD_ALE
XD_WE#
XD_WP#

XD_D0
XD_D1
XD_D2
XD_D3
XD_D4
XD_D5
XD_D6
XD_D7

MS/SDCLK 23

MS_INS# 23

XD_CD# 23
XD_RB# 23
XD_RE# 23
XD_CE# 23
XD_CLE 23
XD_ALE 23
XD_WE# 23
XD_WP# 23

XD_D0 23
XD_D1 23
XD_D2 23
XD_D3 23
XD_D4 23
XD_D5 23
XD_D6 23
XD_D7 23SD_CMD 23

GPIO0 25

1 2

A3V3

R333

R333
100K_4

100K_4

RST#

C563

C563
1U_4

1U_4

SD_WP

23

SD_CD#

23

XTLI XTLO

Y6

2 1

12MHZY612MHZ

1 2

R411 270K_4R411 270K_4

C562

C562
20P_4

20P_4

C554

C554

20P_4

20P_4

10K_4

10K_4

R410

R410

MODE_SEL

C564

C564
*1U_4

*1U_4

C564 can't be Mounted, reserved for future

1 1

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

RTS5158

RTS5158

RTS5158

Date: Sheet of

Date: Sheet of

A

B

C

D

Date: Sheet

PROJECT : PL3

E

A

A

A

of

22 38Sunday, January 14, 2007

22 38Sunday, January 14, 2007

22 38Sunday, January 14, 2007

A

VCC3

Mini PCI-E Card

3VSUS

C500

C500

C497

4 4

PCIE_WAKE#19,24

3 3

MS/SDCLK22

SD_CMD22
SD_CD#22
SD_WP22

2 2

.1U_4

.1U_4

C497
1U_6

1U_6

3VSUS

2

3

MS_INS#22

1

Q10

Q10
*2N7002E-LF

*2N7002E-LF

XD_D6
XD_D3
XD_RE#
XD_WE#
MS/SDCLK
SD_CMD
SD_CD#
SD_WP

C471

C471
.1U_4

.1U_4

SERIRQ19,31
LDRQ#117

PCIRST#18

PCLK_DEBUG3,31

PCIE_TXP018
PCIE_TXN018

PCIE_RXP018
PCIE_RXN018

uR_SOUT_CR31

uR_SWD31

CLK_PCIE_MINI3
CLK_PCIE_MINI#3

C567

C567

R195 56_4R195 56_4
R196 56_4R196 56_4
R198 56_4R198 56_4
R206 56_4R206 56_4
R207 56_4R207 56_4
R211 56_4R211 56_4
R212 56_4R212 56_4
R217 56_4R217 56_4

C566 .1U_4C566 .1U_4

XD_D6
XD_D3
XD_D2
XD_D7
MS/SDCLK XD_D7
MS_INS#
XD_D5

C511

C511
10U_8

10U_8

SERIRQ
LDRQ#1
PCIRST#
PCLK_MINI

.1U_4

.1U_4

SD_D0
SD_D1
SD_D2
SD_D3
SDCLK
SD_CMD_
SD_CD
SD_WP_

B

VCC3

C509

C509
.001U_4

.001U_4

R194 0_4R194 0_4
R197 0_4R197 0_4
R200 0_4R200 0_4
R201 0_4R201 0_4

PCIE_TXP0
PCIE_TXN0

PCIE_RXP0
PCIE_RXN0

CLK_PCIE_MINI
CLK_PCIE_MINI#

CN23

CN23

21

(4)SD-VCC

31

(7)SD-DAT0

34

(8)SD-DAT1

9

(9)SD-DAT2

11

(1)SD-DAT3

25

(5)SD-CLK

15

(2)SD-CMD

39

SD-CD

41

SD-WP

40

SD-GND

42

SD-GND

19

(3)SD-GND

29

(6)SD-GND

12

(9)MS-VCC

22

(4)MS-DATA0

24

(3)MS-DATA1

20

(5)MS-DATA2

16

(7)MS-DATA3

14

(8)MS-SCLK

18

(6)MS-INS

26

(2)MS-BS

10

(1)MS-GND

28

(10)MS-GND

CARD_READER_TTN

CARD_READER_TTN

VCC1.5

C481

C481

C493

C493

10U_8

10U_8

.1U_4

.1U_4

C495 .1U_4C495 .1U_4
C499 .1U_4C499 .1U_4

REV:2A MODIFY P/N

(18)XD-VCC

(19)XD-CD

(5)XD-CLE
(6)XD-ALE

(10)XD-D0
(11)XD-D1
(12)XD-D2
(13)XD-D3
(14)XD-D4
(15)XD-D5
(16)XD-D6

(17)XD-D7
(1)XD-GND
(9)XD-GND

(2)XD-R/B

(3)XD-RE
(4)XD-CE

(7)XD-WE
(8)XD-WP

NC

CN22

CN22

51

Reserved

49

Reserved

47

Reserved

45

Reserved

43

Reserved

41

Reserved

39

Reserved

37

Reserved

35

GND

33

PETp0

31

PETn0

29

GND

27

GND

25

PERp0

23

PERn0

21

GND

19

Reserved

17

Reserved

15

GND

13

REFCLK+

11

REFCLK-

9

GND

7

CLKREQ#

5

Reserved

3

Reserved

1

WAKE#

67910-0001

67910-0001

67910-0002

VCC3

C565 .1U_4C565 .1U_4

38

XD_CD#

2

XD_RB#

3

XD_RE#

4

XD_CE#

5

XD_CLE

6

XD_ALE

7

XD_WE#

8

XD_WP#

13

XD_D0

23

XD_D1

27

XD_D2

30

XD_D3

32

XD_D4

33

XD_D5

35

XD_D6

36
37
1
17
45

C

+3.3V

GND

+1.5V

LED_WPAN#

LED_WLAN#

LED_WWAN#

GND

USB_D+

USB_D-

GND

SMB_DATA

SMB_CLK

+1.5V

GND

+3.3Vaux

PERST#

Reserved

GND

Reserved
Reserved
Reserved
Reserved
Reserved

+1.5V

GND

+3.3V

XD_CD# 22
XD_RB# 22
XD_RE# 22
XD_CE# 22
XD_CLE 22
XD_ALE 22
XD_WE# 22
XD_WP# 22

XD_D0 22
XD_D1 22
XD_D2 22
XD_D3 22
XD_D4 22
XD_D5 22
XD_D6 22
XD_D7 22

D

3VSUSVCC3

VCC1.5

52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18

16
14
12
10
8
6
4
2

VCC3

WLAN_LED#

USBP4+
USBP4-

PDAT_SMB
PCLK_SMB

PLTRST#

R3770_4 R3770_4
R3790_4 R3790_4
R3810_4 R3810_4
R3820_4 R3820_4
R3840_4 R3840_4

T195T195

USBP4+ 18
USBP4- 18

PDAT_SMB 3,19
PCLK_SMB 3,19

PLTRST# 18,19,24,25,31

LFRAME#
LAD3
LAD2
LAD1
LAD0

change 4:change LPC schematic to
match ZH3 debug card

LFRAME# 17,31
LAD3 17,31
LAD2 17,31

LAD1 17,31
LAD0 17,31

R375 0_6R375 0_6

WLAN_LED

E

23

Activate: H

RF_EN 31

WLAN_LED 29

1 1

MDIO00 MDIO01
SD/MMC
MS
xD L L

A

HL
LH

B

C

D

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

R5C832-4 IN 1/MINI PCIE

R5C832-4 IN 1/MINI PCIE

R5C832-4 IN 1/MINI PCIE

Date: Sheet

Date: Sheet

Date: Sheet

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

PROJECT : PL3

of

of

of

23 38Friday, January 12, 2007

23 38Friday, January 12, 2007

23 38Friday, January 12, 2007

E

A

A

A

5

4

3

2

1

R234

R234
75/F_4

75/F_4

RJ45_TER

24

R233

R233

75/F_4

75/F_4

RVCC3

C441

C441
.1U_4

.1U_4

D D

CLK_PCIE_LAN3
CLK_PCIE_LAN#3

C C

L26 0_6L26 0_6

RVCC3

120 ohms@100Mhz

B B

C440

C440

C464

C464

.1U_4

.1U_4

.1U_4

.1U_4

C419

C419

C445

.1U_4

.1U_4

C445
1000P_4

1000P_4

C436

C436
.1U_4

.1U_4

TW3 final:0.1u

VCC3

(426mA)

C447

C447

4.7U_6

4.7U_6

C427 .1U_4C427 .1U_4
C426 .1U_4C426 .1U_4

C456

C456
.1U_4

.1U_4

CTRL_12

C431

C431
.1U_4

.1U_4

PCIE_RXP118
PCIE_RXN118
PCIE_TXP118
PCIE_TXN118

PCIE_WAKE#19,23

PLTRST#18,19,23,25,31

C421

C421
.1U_4

.1U_4

C432

C432
1000P_4

1000P_4

MDI0+
MDI0­MDI1+
MDI1-

LAN_VPDCLK
LAN_VPDDATA

R336 *0_4R336 *0_4

T116T116

R341

R341

4.7K_4

4.7K_4

1

C443

C443

C435

C435

1000P_4

1000P_4

.1U_4

.1U_4

C454

C454
1000P_4

1000P_4

PCIE_RXP1_R
PCIE_RXN1_R

32

4

C466

C466
10U_6

10U_6

C457

C457
*4.7U_6

*4.7U_6

Q19

Q19
BCP69T1

BCP69T1

49
50
54
53

6
55
56

5
17
18
20
21
26
27
30
31

38
41
42
43

U22

U22

TX_P
TX_N
RX_P
RX_N
WAKEn
REFCLKP
REFCLKN
PERSTn
MDIP[0]
MDIN[0]
MDIP[1]
MDIN[1]
MDIP[2]
MDIN[2]
MDIP[3]
MDIN[3]

VPD_CLK
VPD_DATA
SMCLK
SMDATA

VDD

C420

C420
1000P_4

1000P_4

RVCC3

(4mA)

1

40

45

61

8

VDDO_TTL

VDDO_TTL

VDDO_TTL

VDDO_TTL_MAIN

88E8039/88E8055

88E8039/88E8055

VDD

VDD

VDD

VDD

VDD

2

7

C442

C442
1000P_4

1000P_4

VDD

13

33

39

44

C459

C459
1000P_4

1000P_4

VDDO_TTL

VDD

48

58

VDD

65

AVDDL

19

EPAD

22

AVDDL

36

37

SPI_CS

AVDDL

28

35

SPI_CLK

32

SPI_DI

AVDDL

34

GND66GND67GND68GND69GND70GND71GND72GND73GND

SPI_DO

AVDDL51AVDDL

AVDDL

52

57

74

LOM_DISABLEn

VAUX_AVLBL

SWITCH_VCC

VMAIN_AVAL

SWITCH_VAUX

HSDACP
HSDACN

RSET
CTRL25
CTRL12

TSTPT

TESTMODE

LED_ACTn

LED_LINK10/100n

LED_LINK1000n

LED_LINKn

XTALI

XTALO

AVDD

VDD25

23

64

88E8055

88E8055

AVDD25VDD

(218mA)

change to DB0EW5LAN02 C- TEST_1/11

U10

U10
NS0013LF

RVCC3

R339

R339
10K_4

LOM_DISABLE#

10
12
11
47
9
24
25
16
4
3

29
46

59
60
62
63

15
14

RVCC3

LAN_RTSET

CTRL_25
CTRL_12

T114T114
T194T194

T193T193
T115T115

CLK_LAN_X1

CLK_LAN_X2

10K_4

C452

C452
*1U/10V

*1U/10V

R349 2K/F_4R349 2K/F_4

C479 22P_4C479 22P_4

Y5
25MHzY525MHz

2 1

C463 22P_4C463 22P_4

AVDD25

V_DAC

C295

C295
.1U_4

.1U_4

MDI1+
MDI1-

MDI0+
MDI0-

MDI1­MDI1+

MDI0­MDI0+

1
2
3
7
8
6

R353 49.9/F_4R353 49.9/F_4
R352 49.9/F_4R352 49.9/F_4

R351 49.9/F_4R351 49.9/F_4
R350 49.9/F_4R350 49.9/F_4

RJ45_MX0+
RJ45_MX0­RJ45_MX1+

RJ45_MX1-

NS0013LF

RD+
RD­CT
TD+
TD­CT

1
2
3
4
5
6
7
8

16

RX+

14

CT

15

RX-

9

TX-

11

CMT

10

TX+

C485 .001U_4C485 .001U_4

C484 .001U_4C484 .001U_4

CN8

CN8

9 10

RJ45-C100F8-100B-8P-L

RJ45-C100F8-100B-8P-L

RJ45_MX1+
MCT1
RJ45_MX1­RJ45_MX0­MCT0
RJ45_MX0+

C1

C1
1000P/3KV_1808

1000P/3KV_1808

L25 0_6L25 0_6

RVCC3

120 ohms@100Mhz

A A

C425

C425
1000P_4

1000P_4

10U_6

10U_6

C422

C422
1000P_4

1000P_4

C408

C408

C417

C417
1000P_4

1000P_4

5

C423

C423
1000P_4

1000P_4

C413

C413

4.7U_6

4.7U_6

C418

C418
1000P_4

1000P_4

C430

C430
.1U_4

.1U_4

CTRL_25

C478

C478

4.7U_6

4.7U_6

R329

R329

4.7K_4

4.7K_4

C474

C474
.1U_4

.1U_4

32

Q17

Q17

1

BCP69T1

BCP69T1

4

AVDD25

C475

C473

C473
.1U_4

.1U_4

C424

C424
.1U_4

.1U_4

4

C472

C472
.1U_4

.1U_4

C475
.1U_4

.1U_4

C476

C476
.1U_4

.1U_4

LAN_VPDCLK
LAN_VPDDATA

R205 4.7K_4R205 4.7K_4
R203 4.7K_4R203 4.7K_4

U7

U7

6

SCL

5

SDA

7

WP

GND

24LC08BT-I

24LC08BT-I

3

VCC

1

A0

2

A1

3

A2

8
4

C260

C260
.1U_4

.1U_4

RVCC3

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

PCIE LAN 10/100M MARVELL 88E8039

PCIE LAN 10/100M MARVELL 88E8039

PCIE LAN 10/100M MARVELL 88E8039

Date: Sheet

Date: Sheet

2

Date: Sheet

PROJECT : PL3

1

A

A

A

of

of

of

24 38Thursday, January 11, 2007

24 38Thursday, January 11, 2007

24 38Thursday, January 11, 2007

1

2

3

4

5

6

7

8

ODD

A A

ODD_5V

B B

R263 470_6R263 470_6

PDD[0..15]17

PDDREQ17
PDIOW#17
PDIOR#17
PDIORDY17
PDDACK#17
IRQ1417
PDA117
PDA017
PDCS1#17
PDA217
PDCS3#17

-IDERST
PDD6

PDD5
PDD4
PDD3
PDD2
PDD1
PDD0

PDIOW#
IRQ14

PDA1
PDA0
PDCS1#
ODDLED#

PDD[0..15]

PDDREQ
PDIOW#
PDIOR#
PDIORDY
PDDACK#
IRQ14
PDA1
PDA0
PDCS1#
PDA2
PDCS3#

CN15

CN15
AOP-CDR-CONN-50P

AOP-CDR-CONN-50P

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

515152

52

PDD8
PDD9PDD7
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15
PDDREQ
PDIOR#

PDDACK#PDIORDY
DIAG#

PDA2
PDCS3#

C362

C362
.1U_4

.1U_4

R277 *10K_4R277 *10K_4

80 mils

C365

C365
1000P_6

1000P_6

VCC5

C364

C364
.1U_4

.1U_4

ODD_5V

C361

C361
10U_8

10U_8

IN for Master
NC for Slave

RES-TYPE

80 mils

R272 0_8R272 0_8

VCC5ODD_5V

SATA HDD

CN20

CN20

GND23

GND1

RXP

RXN

GND2

TXN
TXP

GND3

3.3V

3.3V

3.3V
GND
GND
GND

5V
5V
5V

GND

RSVD

GND

12V
12V
12V

GND24

SA@Serial_ATA

SA@Serial_ATA

23
1

2
3
4
5
6
7

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

24

SATA_TXP0
SATA_TXN0

SATA_RXN0_C
SATA_RXP0_C

3.3VSATA

C453

C453
.1U_4

.1U_4

C266 3900P_4C266 3900P_4
C264 3900P_4C264 3900P_4

R343 *0_8R343 *0_8

C444

C444

C458

C458

10U_8

10U_8

.1U_4

.1U_4

40 mils

R335 0_8R335 0_8

3.3VSATA

*4.7U_8

*4.7U_8

VCC5HDD_5V

SATA_TXP0 17
SATA_TXN0 17

SATA_RXN0 17
SATA_RXP0 17

VCC3

HDD_5V

C470

C470

25

C480

C480
*.1U_4

*.1U_4

HDD/ODD/cardreader LED

VCC3

C C

VCC3

2

2
1

74AHCT1G08GW

74AHCT1G08GW

3 5

U2

U2

ODD_LED#30 SATA_LED# 17

D D

1

4

GPIO0

R70

R70
10K_4

10K_4

4

3

VCC3

3 5

GPIO0 22

2
1

74AHCT1G08GW

74AHCT1G08GW
U4

U4

R79

R79
10K_4

10K_4

VCC3VCC3

R78

R78
10K_4

10K_4

ODDLED#
SATA_LED# -IDERST

4

5

RST_HDD#19

PLTRST#18,19,23,24,31

R290 *0_4R290 *0_4
R84 0_4R84 0_4

6

VCC3 VCC5

Q2

Q2

2

DTC144EU

DTC144EU

1 3

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

SATA/PATA

SATA/PATA

SATA/PATA

Date: Sheet of

Date: Sheet of

Date: Sheet

7

PROJECT : PL3

R129

R129
10K_4

10K_4

A

A

A

of

25 38Friday, January 12, 2007

25 38Friday, January 12, 2007

25 38Friday, January 12, 2007

8

A

B

C

D

E

3VSUS

DIBP_HS28

DIBN_HS28

1 1

AUD_EAPD27

3V_DVDD

ACZ_RST#17
ACZ_BIT_CLK17

ACZ_SYNC17

ACZ_SDIN017

ACZ_SDOUT17

DIBN_HS

1 2

L28

L28
BLM18PG181SN1D

BLM18PG181SN1D

R389 0_4R389 0_4

R392 0_4R392 0_4

R387

R387

237K_8

237K_8

RC0805

RC0805

BEEP

C514

C514
10U_8

10U_8

DIB_PDIBP_HS

DIB_N

RCOSC

C524

C524
.1U_4

.1U_4

U27

U27

10

RESET#

5

BIT_CLK

9

SYNC

7

SDI

4

SDO

44

DIBP

43

DIBN

11

PCBEEP

48

SPDIF

47

EAPD

1

NC_1

2

NC_2

16

NC_16

41

RCOSC

CX20549-12Z

CX20549-12Z

C516

C516
.1U_4

.1U_4

3

8

DVDD

VDDIO

VSSIO_46

VSSIO_42

46

42

45

DVDDM

DVSS

6

C532

C532
.1U_4

.1U_4

20

31

37

AVDDHP

AVDD_20

AVDD_31

MIC_BIAS_L

MIC_BIAS_R

LINEOUT_L

LINEOUT_R

PORT-A_BIAS_L
PORT-A_BIAS_R

PORT-A_L
PORT-A_R

PORT-B_BIAS_L
PORT-B_BIAS_R

PORT-B_L
PORT-B_R

AVSS_25

AVSSHP

AVSS_12

AVSS_32

25

40

12

32

AGND

MIC_L

MIC_R

CD_L

CD_GND

CD_R

SENSE

VREF_HI
VREF_LO
VC_REFA

ANALOGDIGITAL

C528

C528
.1U_4

.1U_4

29
30
21
22

35
36

33
34
38
39

14
15
23
24

17
18
19

13

26
27
28

C538

C538
.1U_4

.1U_4

MICVREFL
MICVREFR

T204T204
T202T202

T196T196
T198T198
T201T201
T203T203

SENSE

VREF_HI
VREF_LO
VC_REFA

3.3VA3V_DVDD

AGND

AGND

C533

C533
10U_8

10U_8

C288 1U_6C288 1U_6
C285 1U_6C285 1U_6

T197T197
T199T199
T200T200

R386 5.11K/F_6R386 5.11K/F_6
R388 20K_4R388 20K_4

R385 5.11K/F_6R385 5.11K/F_6

C539 1U_8C539 1U_8

C540

C540
1U_8

1U_8

MIC1-JD
HP-JD

11/14 EMI suggest to add cap.

VCC3

0.1u*4 for VCC3

C544

C544

C543

C543

.1U_4

.1U_4

.1U_4

.1U_4

MICIN1_L
MICIN1_R

LINEOUT_L 27
LINEOUT_R 27

HPOUT_L 27
HPOUT_R 27

3.3VA

C545

C545
.1U_4

.1U_4

HP-JD 27

C546

C546
.1U_4

.1U_4

FOR EMI SOLUTION

R232 0_6R232 0_6
R231 *0_6R231 *0_6
R221 *0_6R221 *0_6

C513 *.1U_4C513 *.1U_4
C504 *.01U_4C504 *.01U_4

26

AGND

EXT MIC

AGND

MICIN1_L
MICIN1_R

AGND

C542 220P_6C542 220P_6

L32 MNB-160808-0600A-N2QL32 MNB-160808-0600A-N2Q
L30 MNB-160808-0600A-N2QL30 MNB-160808-0600A-N2Q

C541 220P_6C541 220P_6

MICVREFL MICVREFR

R398

R398

R396

R396

2.2K_4

2.2K_4

2.2K_4

2.2K_4

MICIN1-LL

MICIN1-RL

MIC1-JD

change p/n:FROM CX080600002TO X080600037 B-TEST

A

B

AGND

CN7

CN7

1
2
6
3
4

5

MIC_DFPJ06MS310

MIC_DFPJ06MS310

Q9

PC BEEP

SPKR19

ENBEEP31

7

8

C

3

ENBEEP

Q9
2N7002E

2N7002E

2

PC_BEEP

1

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

D

R219 10K_4R219 10K_4

Audio codec

Audio codec

Audio codec

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

PROJECT : PL3

C515 .47U_6C515 .47U_6

R218

R218
10K_4

10K_4

of

of

of

26 38Wednesday, January 10, 2007

26 38Wednesday, January 10, 2007

26 38Wednesday, January 10, 2007

E

BEEPSPKR

A

A

A

5

4

3

2

1

AUDIO AMPLIFIER

U26

U26

LINEOUT_L26
LINEOUT_R26

HPOUT_L26

D D

C C

B B

HPOUT_R26

AUD_EAPD26

AMP_MUTE#31

5V_SPK_AMP

R226

R226
100K_4

100K_4

1 2

12

R229

R229
*100K_4

*100K_4

AGND

LINEOUT_L
LINEOUT_R

HPOUT_L
HPOUT_R

R227

R227
*100K_4

*100K_4

1 2

AUD_AMP_GAIN1
AUD_AMP_GAIN2

12

R230

R230
100K_4

100K_4

C526 1U_6C526 1U_6
C531 1U_6C531 1U_6

C534 1U_6C534 1U_6
C291 1U_6C291 1U_6

5V_SPK_AMP

U9

AUD_EAPD
AMP_MUTE#

0 0 6dB

U9

2
1

TC7SH08FU

TC7SH08FU

3 5

AGND

GAIN1GAIN2 GAIN

1 0 10dB
0 1 15.6dB
1 1 21.6dB

12

C290

C290
*47P_4

*47P_4

AGND AGND

AUD_AMP_MUTE#

4

R390 0_4R390 0_4

1 2

R393 0_4R393 0_4

1 2

R394 0_4R394 0_4

1 2

R228 0_4R228 0_4

12

C530

C530
*47P_4

*47P_4

12

C525

C525
*47P_4

*47P_4

5V_SPK_AMP

5V_SPK_AMP

AGND

R223

R223
10K_4

10K_4

R391

R391
10K_4

10K_4

12

C535

C535
*47P_4

*47P_4

1 2

C529 1U_6C529 1U_6

AGND

12

C520

C520
10U_8

10U_8

AGND AGND

HP_EN
AUD_SPK_ENABLE#

1 2

12

C536

C536
1U_6

1U_6

AUD_SPK_ENABLE#
HP_EN
AUD_AMP_MUTE#
AUD_AMP_GAIN1
AUD_AMP_GAIN2

C519 1U_8C519 1U_8

1 2

AGND

AGND

REGEN

3.3VA

12

C289

C289
1U_6

1U_6

AGND

3

SPKR_INL

2

SPKR_INR

27

HP_INL

26

HP_INR

24

BIAS

23

SPKR_EN#

22

HP_EN

25

MUTE#

31

GAIN1

32

GAIN2

17

HPVDD

9

CPVDD

10

C1P

12

C1N

11

CPGND

14

PVSS

13

12

VCC5

AGND

CPVSS

C518

C518
1U_8

1U_8

MAX9789A

MAX9789A

cR 225 from 2k to 17.3k 1/11

12

R222

R222
0_4

0_4

12

C282

C282
*.033U_4

*.033U_4

Layout Note:
Place close U22.

r224 from 1k to 10k _1/11

12

C286

C286
1U_6

1U_6

MAX9789A

MAX9789A
TQFN 32PIN

TQFN 32PIN

REGEN

PVDD_8

PVDD_18

GND_28
PGND_5

PGND_21

OUTL+

OUTL-

OUTR+

OUTR-

VOUT

HPL
HPR

SET

VDD

AUD_SPK_L1

6

AUD_SPK_L2

7

AUD_SPK_R1

20

AUD_SPK_R2

19

AUD_HP_JACK_L

16

AUD_HP_JACK_R

15

REGEN

4

SET

1
29
30

8
18

28
5
21

3.3VA

AGND

SET

5V_SPK_AMP

3.3VA

R225

R225

C284

C284
10P_4

10P_4

17.3/F_4

17.3/F_4

R224

R224
10K_4

10K_4

AGND

FOR EMI SOLUTION

R397 0_6R397 0_6
R395 0_6R395 0_6
R380 0_6R380 0_6

AGND

5V_SPK_AMP VCC5

12

C521

C521
*1U_6

*1U_6

AGND

12

C293

C293
1U_6

1U_6

5V_SPK_AMP

12

AGND

C292

C292
1U_6

1U_6

12

C537

C537
1U_6

1U_6

L29

L29
BLM21PG600SN1D

BLM21PG600SN1D

12

C523

C523
*10U_8

*10U_8

5V_SPK_AMP

12

AGND

12

C517

C517
10U_8

10U_8

C522

C522
.1U_4

.1U_4

12

27

C test change: gain value change to 10dB

Headphone out

4

HP

CN6

CN6

1
2
6
3
4

5

LIN_DFTJ06MS481

LIN_DFTJ06MS481

7

8

change p/n:FROM CX080600002TO X080600037 B-TEST

AUD_HP_JACK_L
AUD_HP_JACK_R

A A

5

L31 MNB-160808-0600A-N2QL31 MNB-160808-0600A-N2Q
L33 MNB-160808-0600A-N2QL33 MNB-160808-0600A-N2Q

HP-JD26

HP-JD

AGND AGND

Int. Stereo Speakers

AUD_SPK_R1
AUD_SPK_R2
AUD_SPK_L1
AUD_SPK_L2

1 2

3

C271

C271
100P_4

100P_4

1 2

C269

C269
100P_4

100P_4

CN5

CN5

6
4
3
2
1

5

R_L_SPEAKERS

R_L_SPEAKERS

C270

C268

C268
100P_4

100P_4

1 2

AGND AGND AGNDAGND AGND

1 2

C270
100P_4

100P_4

2

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

AMP MAX9789A

AMP MAX9789A

AMP MAX9789A

Date: Sheet

Date: Sheet

Date: Sheet

PROJECT : PL3

1

27 38Thursday, January 11, 2007

27 38Thursday, January 11, 2007

27 38Thursday, January 11, 2007

of

of

of

A

A

A

5

4

3

2

1

3

28

CN16

CN16

G1

1

1

2

D D

C C

MJ4

MJ4

2
1

*127214FS002G200ZO

*127214FS002G200ZO

MJ6

MJ6

1
2
3
4

B B

*127214FS004G200ZO

*127214FS004G200ZO

MJ5

MJ5

1
2

*127214FS002G200ZO

*127214FS002G200ZO

GND

G2

4

RJ11-CON

RJ11-CON

DIBN_HS26
DIBP_HS26

2

DIBN_HS
DIBP_HS

GND

TIPL

RINGL

DIBN_HS
DIBP_HS

MC12

MC12
150P_4

150P_4

CNXT-0402

CNXT-0402

MC13

MC13
150P_4

150P_4

CNXT-0402

CNXT-0402

GND

REV_2A 8/04 Modify

C385

C385
1000P/3KV_1808

1000P/3KV_1808

C386

C386
1000P/3KV_1808

1000P/3KV_1808

EMI solution

MT1

MT1

2 3

1

4

MODEM-SMAR

MODEM-SMAR

CN17

CN17

4
2
1

3

<Manufacturer>

<Manufacturer>

Modem Header

Modem Header

MTH1MTH1

GND

MC6

MC6
47P_4

47P_4

CNXT-0402

CNXT-0402

MC5

MC5

.1U_4

.1U_4

CNXT-0402

CNXT-0402

MC4

MC4
.1U_4

.1U_4

CNXT-0402

CNXT-0402

AVdd

AGND_LSD

AGND_LSD

DIBN

PWR+

MC3

MC3

DIBP

DVdd

.1U_4

.1U_4

CNXT-0402

CNXT-0402

12

16

15

2

14

1

MU1

MU1
CX20548-S

CX20548-S

TEST

DIBN

PWR

AVDD

DIBP

DVDD

MC2

MC2
.1U_4

.1U_4

5335R13-005_6

RAC1_RING

MBR1

MBR1
MMBD3004S

MMBD3004S

MR3 6.81M_8

MR3 6.81M_8

RAC1

4

RAC

5

TAC

11

EIC

R810 and C810 must be placed near pin 6 (RXI)
and there should be no vias on the(RXI)net.

6

RXI

10

EIO

9

EIF

8

TXO

7

TXF

13

VC

3

VC_LSD

GPIO

EP

17

TAC1

EIC

RXI

EIF

TXO

TXF

CNXT-0805

CNXT-0805

MR1 6.81M_8

MR1 6.81M_8

CNXT-0805

CNXT-0805

MC11 .1U_4

MC11 .1U_4

CNXT-0402

CNXT-0402

AGND_LSD

MR2

MR2

RX1_1 BRIDGE_CC

237K_8

237K_8

CNXT-0805

CNXT-0805

MR13 100_4

MR13 100_4

CNXT-0402

CNXT-0402

TAC1_TIP

MC1 .047U_1206

MC1 .047U_1206

MBR2

MBR2
MMBD3004S

MMBD3004S

AGND_LSD

<DC_WORK_VOLT>

<DC_WORK_VOLT>

MQ2

MQ2
MMBTA42

MMBTA42

MR4

MR4
110_6

110_6

RESIST_TOL

RESIST_TOL
CNXT-0603

CNXT-0603

5335R13-005_6

MFB2

MFB2

1
4

ML1

ML1
*600_1206

*600_1206

5335R13-005_6

5335R13-005_6

MFB1

MFB1

MC10 .01U_6

MC10 .01U_6

CNXT-0603

CNXT-0603

MQ1

MQ1
MMBTA42

MMBTA42

MR8

MR8
*47_1206

*47_1206

RESIST_TOL

RESIST_TOL
CNXT-0603

CNXT-0603

AGND_LSD

2
3

AGND_LSD

MC8

MC8
470P_1808

470P_1808

MR9

MR9
280_1206

280_1206

CNXT-1206

CNXT-1206

BRIDGE_CC2

QBASE

MQ3

MQ3
MMBTA42

MMBTA42
MR11

MR11

3.01_4

3.01_4

CNXT-0402

CNXT-0402

MR7

MR7

9.1_1206

9.1_1206

CNXT-1206

CNXT-1206

MC7

MC7
*470P_4

*470P_4

MR5

MR5
280_1206

280_1206

CNXT-1206

CNXT-1206

RING_1

TIP_1

GND

MR6

MR6
280_1206

280_1206

CNXT-1206

CNXT-1206

MQ4

MQ4
MMBTA42

MMBTA42

MR12

MR12

3.01_4

3.01_4

CNXT-0402

CNXT-0402

MRV1MRV1

MC9

MC9
470P_1808

470P_1808

MR10

MR10
280_1206

280_1206

CNXT-1206

CNXT-1206

MJ2

MJ2

WIRE-TO-BOARD

WIRE-TO-BOARD

2
1

2
1

*127214FS002G200ZO

*127214FS002G200ZO

2
1

*127214FS002G200ZO

*127214FS002G200ZO

MJ1

MJ1

MJ3

MJ3

AGND_LSD

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

MODEM DAA

MODEM DAA

MODEM DAA

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

PROJECT : PL3

1

A

A

A

of

of

of

28 38Wednesday, January 10, 2007

28 38Wednesday, January 10, 2007

28 38Wednesday, January 10, 2007

A

U1

USB

5VSUS

4 4

USBPWR2

USBP2-18
USBP2+18

U1
G545B2RD1U

G545B2RD1U

2

4
1
9

+

+

IN1

OUT3

IN23OUT2

OUT1
EN#
GND
GND-C

100U_3528

100U_3528
C159

C159

R72 *0_4R72 *0_4

RFCM1632100M3

RFCM1632100M3

2

2

3

L9

L9

R71 *0_4R71 *0_4

OC#

8
7
6

5

BUSBP2­BUSBP2+

1
443

USBPWR2

T23T23

USB_DFHD04MR671

USB_DFHD04MR671

BUSBP2-BUSBP2-

1

BUSBP2+

CN14

CN14

4
3
2
1

5 6

7 8

B

U19

U19
G545B2RD1U

G545B2RD1U

5VSUS

5VSUS

2

IN1
IN23OUT2

4

EN#

1

GND

9

GND-C

U6

U6
G545B2RD1U

G545B2RD1U

2

IN1
IN23OUT2

4

EN#

1

GND

9

GND-C

OUT3
OUT1

OC#

OUT3
OUT1

OC#

8
7
6

5

8
7
6

5

USBPWR0

T173T173

USBPWR6

T101T101

C

D

E

29

CN18

USBPWR0

USBPWR6

R318

R318

0_6

0_6

R408

R408

0_6

0_6

13

R315 0_6R315 0_6
R314 0_6R314 0_6

R313 0_6R313 0_6
R312 0_6R312 0_6

WL_LED

ECO_LED

USBP0+18

USBP0-18

USBP6+18

WL_SW#31

WLAN_LED23

VCC5

ECO#_LED31

USBP6-18

WLAN_LED

R311 330_4R311 330_4

Q15

Q15

2

PDTC143TT

PDTC143TT

2

CN18

12
11
10
9
8
7
6
5
4
3
2
1

14 13

87212-1210-12P-L

87212-1210-12P-L

+

+

+

+

USBPWR0

C243

C243
100U_3528

100U_3528

USBPWR6

C247

C247
100U_3528

100U_3528

R409 330_4R409 330_4

VCC5

3 3

ECO#31

Q21

Q21

13

PDTC143TT

PDTC143TT

INT KeyBoard

VCC3

CN4

MY0
MY1
MY2

MY3
MY4
MY5
MY6
MY7
MY8

MY9

MX7
MX6
MX5

MX4

MX3
MX2

MX1

MX0

CN4

27

25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

26

KB_DFFC25FS033

KB_DFFC25FS033

7 8
5
3
1

220Px4

220Px4
CP2

CP2

7 8
5
3
1

220Px4

220Px4
CP1

CP1

MX3
MX2

6

MX1

4

MX0

2

MX7
MX6

6

MX5

4

MX4

2

INT K/B

MX0

MX031

MX1

MX131

MX2

MX231

MX3

MX331

MX4

MX431

MX5

MX531

MX6

MX631

MX7

MX731
MY1531

MY1431
MY1331
MY1231
MY1131
MY1031
MY931
MY831
MY731

MX7
MX6
MX5
MX4

MY631
MY531
MY431
MY331
MY231
MY131
MY031

2 2

3VPCU

10

9
8
7 4

RP33

RP33

10KX8

10KX8

MY15
MY14
MY13
MY12
MY11
MY10
MY9
MY8
MY7
MY6
MY5
MY4
MY3
MY2
MY1
MY0

MY10
MY11

MY12
MY13
MY14
MY15

MX0

1

MX1

2

MX2

3

MX3

56

EMI

3VSUS

C548

C548
.1U_4

.1U_4

1.8VSUS 5VSUS

C329

C329

C87

.1U_4

.1U_4

3VPCU

C287

C287
.1U_4

.1U_4

H7

H7

h-c315d110p2

h-c315d110p2

C87
.1U_4

.1U_4

C255

C255
.1U_4

.1U_4

h-c315d110p2

h-c315d110p2

H17

H17

C64

C64
.1U_4

.1U_4

C510

C510
.1U_4

.1U_4

C56

C56
.1U_4

.1U_4

C278

C278
.1U_4

.1U_4

H21

H21

h-c315d110p2

h-c315d110p2

C72

C72
.1U_4

.1U_4

C294

C294
.1U_4

.1U_4

C512

C512
1000P_4

1000P_4

SMDDR_VREF

C507

C507
1000P_4

1000P_4

C101

C101
.1U_4

.1U_4

C39

C39
.1U_4

.1U_4

H5

H5

h-c315d110p2

h-c315d110p2

C277

C277
1000P_4

1000P_4

C10

C10
.1U_4

.1U_4

h-c315d110p2

h-c315d110p2

C256

C256

C254

C254

.1U_4

.1U_4

.1U_4

.1U_4

VIN

C14

C14

C24

C279

C279
.1U_4

.1U_4

H-C197D83B

H-C197D83B

C13

C13
1000P_4

1000P_4

C527

C527
.1U_4

.1U_4

C248

C248
.1U_4

.1U_4

C24
1000P_4

1000P_4

C322

C322
.1U_4

.1U_4

H22

H22

.1U_4

.1U_4

AVDD25 VCC1.25

C11

C11
.1U_4

.1U_4

C257

C257
.1U_4

.1U_4

H28

H28

h-c98d98n

h-c98d98n

H-C197D83B

H-C197D83B

C21

C21

C168

C168

1000P_4

1000P_4

1000P_4

1000P_4

C160

C160

C272

C272

.1U_4

.1U_4

.1U_4

.1U_4

5VPCU VCC1.05

C506

C506

C280

C280

.1U_4

.1U_4

.1U_4

.1U_4

H23

H3

H3

H23

C33

C33
.1U_4

.1U_4

C411

C411
.1U_4

.1U_4

C460

C460
1000P_4

1000P_4

C22

C22
.1U_4

.1U_4

h-c98d98nH6h-c98d98n

C318

C318
.1U_4

.1U_4

C296

C296
.1U_4

.1U_4

C366

C366
1000P_4

1000P_4

C148

C148
.1U_4

.1U_4

H6

C315

C315
1000P_4

1000P_4

C154

C154
.1U_4

.1U_4

C316

C316
.1U_4

.1U_4

H-C236D142P2

H-C236D142P2

VCC1.5 VCC5

C403

C403

C399

C399

C314

C314

.1U_4

.1U_4

1000P_4

1000P_4

C19

C19

C40

C40

.1U_4

.1U_4

.1U_4

.1U_4

C281

C281

C283

C283

.1U_4

.1U_4

.1U_4

.1U_4

C30

C30

C251

C251

.1U_4

.1U_4

.1U_4

.1U_4

H14

H14

H-C236D142IN1

H-C236D142IN1

C12

C12
.1U_4

.1U_4

H8

H8

C201

C201
.1U_4

.1U_4

.1U_4

.1U_4

C230

C230
.1U_4

.1U_4

C16

C16
.1U_4

.1U_4

C27

C27
.1U_4

.1U_4

h-c394d394n

h-c394d394n

C28

C28
.1U_4

.1U_4

C34

C34
.1U_4

.1U_4

H15

H15

C228

C228
.1U_4

.1U_4

C15

C15
.1U_4

.1U_4

1.8VSUS

C18

C18
.1U_4

.1U_4

C276

C276
.1U_4

.1U_4

h-c315d110p2

h-c315d110p2

H13

H13

H-C236D142P2

H-C236D142P2

C351

C351
.1U_4

.1U_4

H24

H24

C263

C263
.1U_4

.1U_4

C17

C17
.1U_4

.1U_4

1

C267

C267
.1U_4

.1U_4

C145

C145
.1U_4

.1U_4

C363

C363

C29

C29

.1U_4

.1U_4

.1U_4

.1U_4

h-c315d110p2

h-c315d110p2

H4

H4

h-c315d98p2

h-c315d98p2

H20

H20

1

h-c315d110p2

h-c315d110p2

H2

H2

h-c315d98p2

h-c315d98p2

H10

H10

1

1 1

A

B

1

h-c315d110p2

h-c315d110p2

H25

H25

1

1

H16

H16

h-c315d110p2

h-c315d110p2

1

1

h-c315d110p2

h-c315d110p2

1

H26

H26

h-c315d110p2

h-c315d110p2

1

1

H1

H1

h-c315d110p2

h-c315d110p2

1

C

1

H27

H27

h-c315d110p2

h-c315d110p2

1

1

H12

1

H12

h-c295d142p2

h-c295d142p2

H9

H9

1

1

H11

H11

h-c295d142p2

h-c295d142p2

1

1

H19

H19

h-c295d142p2

h-c295d142p2

1

D

1

H18

H18

h-c295d142p2

h-c295d142p2

1

1

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

1

KEYBOARD /USB/SCREW

KEYBOARD /USB/SCREW

KEYBOARD /USB/SCREW

1

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

PROJECT : PL3

1

29 38Friday, January 12, 2007

29 38Friday, January 12, 2007

29 38Friday, January 12, 2007

E

1

A

A

A

of

of

of

5

4

3

2

1

T/P

3VPCU

R401 330_4R401 330_4
R407 330_4R407 330_4

D D

R402 330_4R402 330_4
R406 330_4R406 330_4

VCC3

C C

R403 150_4R403 150_4

NBSWON#31

-BATLED0

-BATLED1

-PWRLED

-SUSLED

IDE_LED

LED3

LED3
LED_G/Y_LTST-C155KGJSKT

LED_G/Y_LTST-C155KGJSKT

LED2

LED2
LED_G/Y_LTST-C155KGJSKT

LED_G/Y_LTST-C155KGJSKT

LED1

LED1

2 1

LED_G_LTST-C190TGKT

LED_G_LTST-C190TGKT

NBSWON#

C2
560P_4C2560P_4

1
2

SW1SW1

BATLED0# 31
BATLED1# 31

PWRLED# 31
SUSLED# 31

ODD_LED# 25

3
4

C161 4.7U_8C161 4.7U_8
C163 .1U_4C163 .1U_4

C158

C158
*10P_4

*10P_4

TPDATA_1TPDATA

VCC5_TP
TPDATA_1
TPCLK_1

TPDATA31

TPCLK31

TPCLK TPCLK_1

R62 0_4R62 0_4
R61 0_4R61 0_4

C157

C157
*10P_4

*10P_4

VCC5_TP

L8

L8

1 2

BLM18PG181SN1D

BLM18PG181SN1D

CN3

CN3

8
6
5
4
3
2
1

7

*88058-6

*88058-6

CN2

CN2

8
6
5
4
3
2
1

7

BL123-06R-6P-L

BL123-06R-6P-L

VCC5

REV_2A 8/03 Add 2'nd source

30

EMI PAD Modem

PAD1

1

PAD1
*Modem_PAD

*Modem_PAD

1

of

of

of

30 38Wednesday, January 10, 2007

30 38Wednesday, January 10, 2007

30 38Wednesday, January 10, 2007

A

A

A

PAD3

PAD2

PAD2
*EMI_PAD

*EMI_PAD

B B

A A

5

4

3

2

PAD3
*EMI_PAD

*EMI_PAD

1

1

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

TP/SW

TP/SW

TP/SW

Date: Sheet

Date: Sheet

Date: Sheet

PAD4

PAD4
*Modem_PAD

*Modem_PAD

1

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

PROJECT : PL3

5

4

3

2

1

I/O Address

R210 *10K_4R210 *10K_4
R209 *10K_4R209 *10K_4
R184 10K_4R184 10K_4

U25

U25

6

SCL

5

SDA

7

WP

24LC08BT-I

24LC08BT-I

U24

U24

2
5
6
1

W25X80VSSIG

W25X80VSSIG

EC-PC8769

EC-PC8769

EC-PC8769

3VPCU

VCC3

Data

164Fh

3VPCU

1

A0

2

A1

3

A2

8

VCC

4

GND

3VPCU3VPCU

8

SO

VDD

7

SI

HOLD

WP

SCK
CE

VSS

VCC5

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PB2

PROJECT : PB2

PROJECT : PB2

3
4

3VPCU

C501

C501
.1U_4

.1U_4

1

C488

C488
.1U_4

.1U_4

A

A

A

of

of

of

31 38Sunday, January 14, 2007

31 38Sunday, January 14, 2007

31 38Sunday, January 14, 2007

SM BUS PU

3VPCU

L14 BLM18AG601SN1L14 BLM18AG601SN1

D D

C491

C491

C494

C508

C508
10U_8

10U_8

PCLK_591

R220

R220
*22_4

*22_4

C275

C275
*10P_4

*10P_4

C C

B B

A A

08/10 FAE: SMI DOESN'T NEED DIODE

FOLLOW INTEL ME-EC INTERFACE SPECIFICATION,
2ND_SMB IS DEDICATED FOR ICH8 CONTROLLER LINK BUS.

0810 FAE:
CHECK X'TAL'S FOOTPRINT
CEECK RESULT: OK

C258

C258

5.6P_4

5.6P_4

1/13 Comfirm by vendor mail :
Connect to AGND

HWPG_CPUIO37

SYS_HWPG33

HWPG_1.05V35

HWPG_1.8V36

5

C494

.1U_4

.1U_4

.1U_4

.1U_4

LFRAME#17,23

LAD017,23
LAD117,23
LAD217,23
LAD317,23

PCLK_5913
CLKRUN#19

GATEA2017

RCIN#17

SCI#19

PLTRST#18,19,23,24,25

T122T122

SERIRQ19,23
KBSMI#19

R192 20M_6R192 20M_6

Y2

4 1

32.768KHZY232.768KHZ

8769AGND

D8 BAS316D8 BAS316
D7 BAS316D7 BAS316
D6 BAS316D6 BAS316
D9 BAS316D9 BAS316

23

C492

C492

C502

C469

C469
.1U_4

.1U_4

D10 BAS316D10 BAS316

MX029
MX129
MX229
MX329
MX429
MX529
MX629
MX729

MY029
MY129
MY229
MY329
MY429
MY529
MY629
MY729
MY829

MY929
MY1029
MY1129
MY1229
MY1329
MY1429
MY1529

MBCLK6,32

MBDATA6,32

TPCLK30

TPDATA30

R187

R187
33K_6

33K_6

C259

C259

5.6P_4

5.6P_4

C502

.1U_4

.1U_4

.1U_4

.1U_4

LFRAME#
LAD0
LAD1
LAD2
LAD3
PCLK_591

SCI#_uR

PLTRST#
TP_uR_PWUREQ#
SERIRQ

MX0
MX1
MX2
MX3
MX4
MX5
MX6

MY16
MY17

MBCLK
MBDATA
2ND_MBCLK
2ND_MBDATA

8768_32KX1

8768_32KX2

08/10 FAE:
ADD ONE GAD PAD UNDER X'TAL,
AND KEEP CLEANCE.

VCC3

R383

R383
10K_4

10K_4

HWPG

4

3
126
127
128

1

2

8
121
122

29

6
124

7
123
125

9

54
55
56
57
58
59
60
61

53
52
51
50
49
48
47
43
42
41
40
39
38
37
36
35
34
33

70
69
67
68

72
71
10
11
12
13

77

79

U8

U8

WPC8763LDG

WPC8763LDG

LFRAME
LAD0
LAD1
LAD2
LAD3
LCLK

CLKRUN/GPIO11/HGPIO02
GA20
KBRST
ECSCI
LDRQ/GPIO24/HGPIO01
LPCPD/GPIO10/HGPIO00
LREST
PWUREQ
SERIRQ
SMI

KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7

KBSOUT0/JENK
KBSOUT1/TCK
KBSOUT2/TMS
KBSOUT3/TDI
KBSOUT4
KBSOUT5/TDO
KBSOUT6/RDY
KBSOUT7
KBSOUT8
KBSOUT9
KBSOUT10
KBSOUT11
KBSOUT12/GPIO64
KBSOUT13/GPIO63
KBSOUT14/GPIO62
KBSOUT15/GPIO61/XOR_OUT
KBSOUT16/GPIO60
KBSOUT17/GPIO57/HGPIO03

SCL1
SDA1
SCL2
SDA2

PSCLK1
PSDAT1
PSCLK2/GPIO26
PSDAT2/GPIO27
PSCLK3/GPIO25
PSDAT3/GPIO12

32KX1/32KCLKIN

32KX2

1/13 Vendor mail:
Dedicate cap for AVCC

+A3VPCU

C261

C261

C262

C262

.1U_4

.1U_4

10U_8

10U_8

8769AGND

102

19

46

76

88

115

VCC1

VCC2

VCC3

VCC4

VCC5

AVCC

A/D

A/D

D/A

D/A

LPC

LPC

GPIO

GPIO

GPO82/HGPIO00/TRIS

GPO84/HGPIO01/BADDR0

KB

SMB

SMB

PS/2

PS/2

GND1

GND2

GND3

5

18

45

78

L15

L15
HZ0603B601R-00

HZ0603B601R-00

KB

GND4

89

GND5

116

GND6

TIMER

TIMER

SPI

SPI

IR

IR

FIU

FIU

TB1/GPIO14/HGPIO4

SPI_DO/GPO76/SHBM

IRRX2_IRSL0/GPIO70

SIN_CR/CIRRX/GPIO87

CIRTX/GPIO16/HGPIO04

SOUT_CR/GPO83/BADDR1

AGND

103

8769AGND

08/10 FAE:
L83 CAN CHANGE FROM BEAD TO
SHORT.
BUT, PLEASE PUT AGND & 32K CAP &
AVCC CAP AT ONE POINT.

ZS1 STILL USE BEAD FOR SAFE.

08/10 FAE:

0.1UF

80

VBAT

GPIO06/HGPIO06
GPIO07/HGPIP07

A_PWM1/GPIO21
B_PWM0/GPIO13

SPI_DI/GPIO77

SPI_SCK/GPIO75

IRRX1/GPIO72

GPIO34/CIRRX2

CLKOUT/GPIO55

VCORF

44

VCORF_uR

1/13 Comfirm by vendor mail:

VCC3

VDD must power up after VCC/AVCC

C468

C468
.1U_4

.1U_4

AD0/GPI90
AD1/GPI91
AD2/GPI92

AD3/GPI93
AD4/GPIO05
AD5/GPIO04

DA0/GPI94

DA1/GPI95

DA2/GPI96

DA3/GPI97

GPIO01
GPIO03

GPIO23
GPIO30
GPIO31
GPIO32
GPIO33
GPIO36

GPIO40
GPIO42/TCK
GPIO43/TMS

GPIO44/TDI

GPIO45

GPIO46/TRST

GPO47/JEN0
GPIO50/TDO

GPIO51
GPIO52/RDY

GPIO53

GPIO81

TA1/GPIO56
TA2/GPIO20

A_PWM0

IRTX/GPIO71

F_SDI

F_SDO

F_CS0
F_SCK

SWD/GPIO66

VCC_POR

VREF

C265

C265
1U_6

1U_6

4

C274

C274

C273

C273

10U_8

10U_8

.1U_4

.1U_4

VDD

97
98
99
100
108
96

101
105
106
107

64
95
93
94
119
109
120
65
66
15
16
17
20
21
22
23
24
25
26
27
28

DNBSWON#_uR

91
110

BADDR0

112

31
117
63

32
118
62

CRT_SENSE#

84

SHBM

83
82

RSMRST#_uR

75
73

PWROK_EC_uR

74
113
14
114

SOUT_CR_DEBUG

111

SPI_SDI_uR

86

SPI_SDO_uR

87

SPI_CS0#_uR

90

SPI_SCK_uR

92

SWD_DEBUG

81
30

VCC_POR#

85
104

R191 4.7K_4R191 4.7K_4

VREF_uR +A3VPCU

R202 0_4R202 0_4

1/13 Comfirm by vendor mail:
VBAT for keep PLL power let power up can quick.
If no VBAT will switch to VCCpower.
If PLL no power will cause boot time delay.

D5 BAS316D5 BAS316

R360 0_4R360 0_4

R208 0_4R208 0_4

EC_ME_ALERT: (Intel 08/28)
Logic high = ¨AC present 〃, Logic low = ¨AC not present (DC
operation)〃.
EC must not drive a high value on pin until SUS Well is fully powered to
prevent leakage.
AC/DC indication should be de-bounced by EC.

R185 0_4R185 0_4

3VPCU

0~AVCC power for DA pin
power reference

08/14 FAE:
Please connect VREF(uRider pin104) to
+A3VPCU instead of +3VPCU.

DEBUG PORTS

EC Debug Port

VCC3

1

SOUT_CR_DEBUG
SWD_DEBUG

2

3

4

CN21

CN21

*ACES_88231-0400

*ACES_88231-0400

1
2
3
4

PCLK_DEBUG3,23

-- DAISY CHAIN TOPOLOGY --

3

TEMP_MBAT 32

ECO# 29
WL_SW# 29

CC-SET 32
VFAN 6

T121T121

T123T123

ECO#_LED 29

ACIN 32
NBSWON# 30
LID591# 14,19

SUSB# 19

EC_FPBACK# 14

SUSLED# 30

BATLED0# 30
BATLED1# 30

PWRLED# 30
VRON 34
MAINON 35,36,37

AMP_MUTE# 27

SUSON 36,37

D/C# 32

RVCCD 33

DNBSWON# 19

FANSIG 6
CONTRAST 14

ENBEEP 26

CRT_SENSE# 14

RF_EN 23

CELL-SET 32

RSMRST# 19
SUSC# 19
ECPWROK 19

uR_SOUT_CR 23

uR_SWD 23

T120T120

HWPG

R3610_4 R3610_4

T124T124

Reserved for LPC debug card

VCC3

LAD0
LAD1
LAD2
LAD3

LFRAME#
PLTRST#
SERIRQ

I/O ADDRESS SETTING

NEC ID

SPI FLASH

INTERNAL KEYBOARD STRIP SET

CN24

CN24

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

*ACS

*ACS

2

MBCLK
MBDATA
2ND_MBCLK
2ND_MBDATA

CRT_SENSE#

BADDR1-0

SHBM=0: Enable shared memory with host BIOS

BADDR0
BADDR1
SHBM

1/13 Comfirm by vendor mail :
Disabled ('1') if using FWH device on LPC.
Enabled ('0') if using SPI flash for both system BIOS and EC firmware

R188 4.7K_4R188 4.7K_4
R189 4.7K_4R189 4.7K_4
R193 4.7K_4R193 4.7K_4
R190 4.7K_4R190 4.7K_4

R186 4.7K_4R186 4.7K_4

0 0
0 1
1 0
1 1

1/13 Comfirm by vendor mail :
If the Southbridge enables 'Long Wait Abort' by default, the
flash device should be 50MHz (or faster)

TPCLK
TPDATA

Index
XOR TREE TEST MODE
CORE DEFINED
2Eh 2Fh
164Eh

BADDR0
SOUT_CR_DEBUG
SHBM

MBCLK
MBDATA

SPI_SDI_uR

R376

R376

SPI_SDO_uR

10K_4

10K_4

SPI_SCK_uR
SPI_CS0#_uR

R359 10K_4R359 10K_4
R358 10K_4R358 10K_4

MY0

R204 10K_4R204 10K_4

MY16

R213 10K_4R213 10K_4

MY17

R215 10K_4R215 10K_4

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

5

C

T

C

T

4

3

2

1

PR117

PR117

10K_6

10K_6

2 1

PL8

PL8

PL9

PL9

PC5

PC5

100P_4

100P_4

PD3

PD3
ZD5.6V

ZD5.6V

del fuse

ACIN_1

PR118

PR118
10K_6

10K_6

12

PC6

PC6

PC4

PC4

0.1U/X7R-50V_6

0.1U/X7R-50V_6

47P/NPO-50V_4

47P/NPO-50V_4

MBCLK 6,31

MBDATA 6,31

PD9

PD9

2 1

ZD12V

ZD12V

12

VA

.1U/X7R-25V_8

.1U/X7R-25V_8

TEMP_MBAT 31

HI0805R800R-00_8

HI0805R800R-00_8

HI0805R800R-00_8

HI0805R800R-00_8

PR3 10K_6PR3 10K_6

TEMP_MBAT

PC54

PC54
.01U/X7R-50V_6

.01U/X7R-50V_6

PC76

PC76

PD4

PD4
RB500V

RB500V

PL3

PL3

PL2

PL2

PC79

PC79

.1U/X7R-25V_8

.1U/X7R-25V_8

2200P_4

2200P_4

BAT-V

BAT-V

3VPCU

CELL-SET31

1
2

PD10

PD10
PDS1040S

PDS1040S

PC145

PC145

PC150

PC150

.1U_4

.1U_4

change p/n:CS-2203F911 b-test

CSOP

CSON

ISL6251_VDD

2

PR14

PR14

100K_6

100K_6

3

PR12 2.2/F_6PR12 2.2/F_6

PC15

PC15

1U/X7R-25V_8

1U/X7R-25V_8

PR18

PR18
130K/F_6

130K/F_6

PR17

PR17

10K_6

10K_6

PR16 10K_6PR16 10K_6

PR15 10K_6PR15 10K_6

PR21

PR21
10K_6

10K_6

3

PQ2

PQ2

2N7002E

2N7002E

1

0.02_3720

0.02_3720
PR116

PR116

1 2

1P

2P

CSIP

CSOP_1

1 2

PC81

PC81

0.1U/X7R-50V_6

0.1U/X7R-50V_6

DCIN

6251ACSET

6251EN

6251CELLS_2

PR22

PR22
100K_6

100K_6

21

CSOP

22

CSON

23

ACPRN

24

DCIN

2

ACSET

3

EN

6251CELLS_1

2

PQ1

PQ1

2N7002E

2N7002E

PC64

PC64

0.1U/X7R-25V_8

0.1U/X7R-25V_8

CSIN

Modify P/N to CS01803F918

PR11

PR11
18_6

18_6

PC77

PC77

0.1U/X7R-50V_6

0.1U/X7R-50V_6

CSIN_1

20

19

CSIP

CSIN

CELLS

4

3

1

PC10

PC10
*100P_4

*100P_4

ICOMP5VCOMP

6

6251ICOMP

6251VCOMP1

PC13

PC13
.01U/X7R-16V_4

.01U/X7R-16V_4

ICM7CHLIM

PR10

PR10

3.3K/F_4

3.3K/F_4

6251VCOMP2

PC12

PC12
.01U/X7R-16V_4

.01U/X7R-16V_4

PR107

PR107
220K/F_6

220K/F_6

PR108

PR108
220K/F_6

220K/F_6

ISL6251_VDD

15

1

VDD

BOOT

UGATE

PHASE

LGATE

PGND

VADJ

ACLIM

VRFE

9

8

VREF

1 6
2
3

PC80 2.2U/X5R-10V_8PC80 2.2U/X5R-10V_8

1 2

PR5

PR5

4.7_6

4.7_6

ISL6251_VDDP

VDDP

6251B_2

16

17

18

14

13
12

GND

11

10

PU4

PU4
ISL6251A

ISL6251A

PC69

PC69
100P_4

100P_4

*3300P/X7R-50V_4

*3300P/X7R-50V_4

PQ26

PQ26

IMD2AT108

IMD2AT108

PR110 2.7_6PR110 2.7_6

ISL6251_UGATE

ISL6251_PHASE

ISL6251_LGATE

PR8

PR8

*100_4

*100_4

PC9

PC9

Function Code = PBC

Function Code = PBC

CC-SET 31

PCN1

PCN1

POWER_CON

POWER_CON

4
3

2
1

.1U/X7R-50V_8

.1U/X7R-50V_8

D D

PC72

PC72

PC73

PC73
.1U/X7R-50V_8

.1U/X7R-50V_8

HI0805R800R-00_8

HI0805R800R-00_8

HI0805R800R-00_8

HI0805R800R-00_8

change p/n and footprint for b-test

ACIN31

PR119

PR119

6.8K/F_6

6.8K/F_6

C C

CN10

CN10

7

1

9

2
3
4
5

8
6

SUYIN BATTERY

B B

SUYIN BATTERY

PR1

PR1
100_4

100_4

2 1

MBAT+

PC7

PC7
47P/NPO-50V_4

47P/NPO-50V_4

PR2

PR2
100_4

100_4

MBDATA

PD2

PD2
ZD5.6V

ZD5.6V

TEMP_MBAT

change p/n and footprint for b-test

PQ28

PQ28
FDS6675BZ

FDS6675BZ

8

1

7

2

6

3

5

4

PR103 0_6PR103 0_6

5
4

PC67 4.7U/X5R-10_8PC67 4.7U/X5R-10_8

1 2

Modify P/N to CH5472K9A02

PD1

PD1

Modify Value to 4.7U/X5R-10_8

RB500V

RB500V

PC74 .1U/X7R-50V_8PC74 .1U/X7R-50V_8

6251B_1

PR111

PR111
107K_6

107K_6

VADJ
ACLIM

PR105

PR105
33K_6

33K_6

LIM = 1/R2(((0.05/VREF=2.39)VACLM)+0.050)
CURRNT LIMIT POINT = 3.25A

3.25A=1/0.02((0.05/2.365)Vaclm+0.05)
Vaclm=0.7095V

ICMNT

0.1U/X7R-25V_8

0.1U/X7R-25V_8

PC82 10U/X6S-25V_1210PC82 10U/X6S-25V_1210

PC16 .1U/X7R-50V_8PC16 .1U/X7R-50V_8

PQ32

PQ32

FDS6900AS

FDS6900AS

G1

G1

8
7
6
5

VREF

PR112

PR112
*514K_F_6

*514K_F_6

Float = 4.2V / CELL

PR106

PR106
*514K_F_6

*514K_F_6

ADP WATT monitor output

For 62W setting. Vicm will 1.3V

VIN

PC66

PC66

D/C# 31

VIN

PL10

PL10

HI0805R800R-00_8

HI0805R800R-00_8

change to CV-6880MZ01 C-TEST_1/11

VA3

D1

D1

1

D1S1/D2

D1S1/D2

2

PL7

G2

G2

S2

S2

PL7

MPL73-6R8

MPL73-6R8

3
4

CSOP
CSON

PR104

PR104
.03_3720

.03_3720

6251LR BAT-V

Modify P/N to CS+0308FL00

1 2

1P

2P

10U/X6S-25V_1206

10U/X6S-25V_1206

2N7002E

2N7002E

1
2
3

PR114

PR114
33K_6

33K_6

2

PQ31

PQ31

PC61

PC61

10U/X6S-25V_1206

10U/X6S-25V_1206

PQ29

PQ29
FDS6675BZ

FDS6675BZ

PC60

PC60

8
7
6
5

4

PR113

PR113

10K_6

10K_6

3

1

PC1

PC1
.01U/X7R-50V_6

.01U/X7R-50V_6

CELL-SET = Hi ----> Cells = VDD ---->4S
CELL-SET = Low ----> Cells = GND ---->3S

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

ISL6251

ISL6251

ISL6251

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

PROJECT : PL3

1

32 38Thursday, January 11, 2007

32 38Thursday, January 11, 2007

32 38Thursday, January 11, 2007

of

of

of

PROJEC

PROJEC

Quanta

Quanta

A

A

A

5

4

3

2

1

E E

D D

C C

B B

5VPCU

PC111

PC111

330U/6.3V_6X5.7

330U/6.3V_6X5.7

MAIND

SUSD

PL16

PL16

VIN

HI0805R800R-00_8

HI0805R800R-00_8

0.1U/X7R-50V_6

0.1U/X7R-50V_6

OCP: 12A

change p/n c-test 1/11

5VPCU

PC55

PC55

+

+

0.1U/X7R-50V_6

0.1U/X7R-50V_6

10U/X6S-25V_1206

10U/X6S-25V_1206

OCP:12A

L(ripple current)
=(19-5)*5/(1.5u*0.4M*19)
~6A

Iocp=12-(6/2)=9A
Vth=9A*15mOhm=135mV
R(Ilim)=(135mV*10)/5uA
~270K

5VPCU

65241

PQ38

PQ38

3

FDC653N_NL

FDC653N_NL

5VSUS

PC112

PC112

0.1U/X7R-50V_6

0.1U/X7R-50V_6

MAIND 37

SUSD 37

PC116

PC116

2200P/X7R-50V_4

2200P/X7R-50V_4

PC109

PC109

PR146

PR146
*2.2_F_6

*2.2_F_6

PC141

PC141

*2200P_50V_6

*2200P_50V_6

PC120

PC120

1 2
12

PR98

PR98

0_4

0_4

PC115

PC115

0.1U/X7R-50V_6

0.1U/X7R-50V_6

PR100

PR100
*0_4

*0_4

PC113

PC113

SYS_SHDN#6

PC114

PC114

10U/X6S-25V_1206

10U/X6S-25V_1206

10U/X6S-25V_1206

10U/X6S-25V_1206

PL15

PL15

1.5uH_10A

1.5uH_10A

MAINDSUSD

PQ39

PQ39

FDS8884

FDS8884

PQ40

PQ40

FDS6690AS

FDS6690AS

15V

5VPCU

3

1 2

PR140

PR140

0_4

0_4

578

3 6

241

578

3 6

241

0.1U/X7R-50V_6

0.1U/X7R-50V_6

PR134

PR134

22_8

22_8

65241

PQ37

PQ37
FDC653N_NL

FDC653N_NL

VCC5

PC110

PC110

0.1U/X7R-50V_6

0.1U/X7R-50V_6

5V_DH

5V_LX

PC135

PC135

+15V_ALWP

5V_DL

3V5V_EN

PC57

PC57

0.1U/X7R-50V_6

0.1U/X7R-50V_6

PC108

PC108

0.1U/X7R-50V_6

0.1U/X7R-50V_6

VL

12

PR144

PR144
39K/F_4

39K/F_4

1 2

PR139 267K/F_4PR139 267K/F_4

PC134

PC134

0.1U/X7R-50V_6

0.1U/X7R-50V_6

PD12

PD12

2

1

CHN217

CHN217

PD11

PD11

2

1

CHN217

CHN217

RVCCD31

ISL6236_3V

PR102

PR102
390K_4

390K_4

PC140

PC140

0.1U/X7R-50V_6

0.1U/X7R-50V_6

PR101

PR101
150K/F_4

150K/F_4

DDPWRGD_R

3V5V_EN

PC132

PC132

0.1U/X7R-50V_6

0.1U/X7R-50V_6

3

PC131

PC131

0.1U/X7R-50V_6

0.1U/X7R-50V_6

3

1 2

PR97

PR97
200K/F_4

200K/F_4

PQ9

PQ9
PDTC143TT

PDTC143TT

5VPCU

PR136

PR136
1_6

1_6

1 2

1 3

.01U/X7R-16V_4

.01U/X7R-16V_4

9

BYP

10

OUT1

11

FB1

12

ILIM1

13

PGOOD1

14

EN1

15

DH1

16

LX1

37

PAD

36

PAD

35

VL

3

2

1

PD7

PD7

BAT54-7-F

BAT54-7-F

3VPCU 15V

2

RVCC3D

PC136

PC136

8

LDOREFIN

BST117DL118VDD19SECFB20GND21PGND22DL223BST2

PAD33PAD34PAD

PC130

PC130
1U/10V_6

1U/10V_6

PR79

PR79
1M_6

1M_6

7

LDO

3

VL

1 2

5

6

VIN

PU7

PU7

ISL6236

ISL6236

12

3VPCU

PC137

PC137

4.7U/X7R-10V_8

4.7U/X7R-10V_8

1 2

PR145

PR145
0_4

0_4

12

4

3

RTC

TON2VCC

ONLDO

PR133 0_6PR133 0_6

PR135

PR135
39K/F_4

39K/F_4

65241

PC118

PC118

0.1U/X7R-50V_6

0.1U/X7R-50V_6

1

REF

REFIN2

SKIP#

PGOOD2

24

PQ41

PQ41
FDC653N_NL

FDC653N_NL

PC139

PC139

0.1U/X7R-50V_6

0.1U/X7R-50V_6

PR141

PR141
*0_4

*0_4

32
31

ILIM2

30

OUT2

29
28
27

EN2

26

DH2

25

LX2

PR132

PR132
1_6

1_6

1 2

PC123

PC123

0.1U/X7R-50V_6

0.1U/X7R-50V_6

RVCC3

12

PR143

PR143

PC138

PC138

0_4

0_4

1U/10V_6

1U/10V_6

12

1 2

DDPWRGD_R

1 2

3V5V_EN

PR142

PR142
*0_4

*0_4

PR138

PR138
287K/F_4

287K/F_4

PC133

PC133

0.1U/X7R-50V_6

0.1U/X7R-50V_6

3V_DH

3V_DL

OCP:6.25A

L(ripple current)
=(19-3.3)*3.3/(2.5u*0.5M*19)
~2.18A

Iocp=6.25-(2.18/2)=5.16A
Vth=5.16A*28mOhm=145mV
R(Ilim)=(145mV*10)/5uA
~294K

MAIND

3

3V_DL

3V_LX

3VPCU

4

S2

S2

5

DDPWRGD_R

65241

PC119

PC119

0.1U/X7R-50V_6

0.1U/X7R-50V_6

D1 S1/D2

D1 S1/D2

G2

G2

PQ42

PQ42
FDC653N_NL

FDC653N_NL

VCC3

123

D1

D1

G1

G1

876

3V_DH

PC127

PC127

0.1U/X7R-50V_6

0.1U/X7R-50V_6

PQ44

PQ44

FDS6900AS

FDS6900AS

2.5uH_7.5A

2.5uH_7.5A

PR137

PR137
0_6

0_6

SUSD

PC124

PC124

0.1U/X7R-50V_6

0.1U/X7R-50V_6

PC128

PC128

2200P/X7R-50V_4

2200P/X7R-50V_4

10U/X6S-25V_1206

10U/X6S-25V_1206

PL18

PL18

3

PC126

PC126

SYS_HWPG 31

3VPCU

HI0805R800R-00_8

HI0805R800R-00_8

PC129

PC129

10U/X6S-25V_1206

10U/X6S-25V_1206

OCP : 6.25A

3VPCU

PC121

PC121

0.1U/X7R-50V_6

0.1U/X7R-50V_6

65241

PQ43

PQ43
FDC653N_NL

FDC653N_NL

PC117

PC117

0.1U/X7R-50V_6

0.1U/X7R-50V_6

3VSUS

PL17

PL17

3VPCU

+

+

VIN

PC122

PC122

330U/6.3V_6X5.7

330U/6.3V_6X5.7

PC125

PC125

0.1U/X7R-50V_6

0.1U/X7R-50V_6

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

SYSTEM 5V/3V

SYSTEM 5V/3V

SYSTEM 5V/3V

Date: Sheet

Date: Sheet

Date: Sheet

5

4

3

2

PROJECT : PL3

1

A

A

33 38Thursday, January 11, 2007

33 38Thursday, January 11, 2007

33 38Thursday, January 11, 2007

A

of

of

of

5

VCC1.05

PR61

PR55

PR55
*0_6

D D

C C

H_PROCHOT#4

Panasonic
ERT-J0EV474J

PSI#_1

DPRSLPVR

B B

A A

*0_6

H_VID6

PWR_MON PGD_IN

Close to Phase 1 Inductor

H_VID5 H_VID2H_VID3 H_VID0H_VID1H_VID4

PR39

PR39

4.99K/F_6

4.99K/F_6

12

12

for ISL6262A

PC24

PC24

0.1U/X7R-50V_6

0.1U/X7R-50V_6

PSI#

PSI#4

PR67 0_8PR67 0_8

3VSUS

Throttling temp.
105 degree C

PSI# PSI#_1
VR_ON

PR34

PR34

10K_4

10K_4

PR26

PR26

PR76

PR76

4.02K/F_4

4.02K/F_4

470K_4 NTC

470K_4 NTC

PC30

PC30

1 2

.01U/X7R-16V_4

.01U/X7R-16V_4

H_VID05
H_VID15

H_VID25
H_VID35
H_VID45
H_VID55
H_VID65

VRON31

PM_DPRSLPVR8,19

ICH_DPRSTP#4,8,17

VR_PWRGD_CK410#19

PR27 97.6K/F_4PR27 97.6K/F_4

220P/X7R-50V_4

220P/X7R-50V_4

ED8-B -0623-390p to330p

PR52 0_4PR52 0_4
PR48 499/F_4PR48 499/F_4
PR47 0_4PR47 0_4
PR45 0_4PR45 0_4

PR32 1K/F_4PR32 1K/F_4

PR30

PR30

255/F_4

255/F_4

1000P/X7R-50V_6

1000P/X7R-50V_6

PC21

PC21

12

Modify P/N to CH31003KB11
Modify Value to .01U/X7R-16V_4

PR57

PR57
*0_6

*0_6

1U/X7R-25V_8

1U/X7R-25V_8

PR42 0_4PR42 0_4
PR38 0_4PR38 0_4
PR35 147K/F_6PR35 147K/F_6

H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6

PC27

PC27

1 2

PC22

PC22

12

470P/X7R-50V_4

470P/X7R-50V_4

PR25 6.81K/F_4PR25 6.81K/F_4

PC20

PC20

1 2

1000P/X7R-50V_6

1000P/X7R-50V_6

PC38

PC38

PR59

PR59
10_6

10_6

PR61
*0_6

*0_6

5VSUS

12

15N/X7R-50V_6

15N/X7R-50V_6

VR_ON
DPRSLPVR

CLKEN#

.01U/X7R-16V_4

.01U/X7R-16V_4

0.1U/X7R-50V_6

0.1U/X7R-50V_6

1 2

PGD_IN

PC23

PC23

PR44

PR44

1K/F_4

1K/F_4

.01U/X7R-16V_4

.01U/X7R-16V_4

PC31

PC31

PC37

PC37

PR63

PR63
*0_6

*0_6

21
49

37
38
39
40
41
42
43
44
45
46
47

13

12

11

10

2
3
4
5
6
7

9

PC34

PC34

1 2

4

VIN_6262

PR58

PR58
10_6

10_6

12

22

VCC

GND
GND_T

PSI#
PGD_IN
RBIAS
VR_TT#
NTC
SOFT

VID0
VID1
VID2
VID3
VID4
VID5
VID6
VR_ON
DPRSLPVR
DPRSTP#
CLK_EN#

VDIFF

FB2

FB

COMP

VW

RTN

15

1 2

20

VIN

ISL6262A

ISL6262A

PR41

PR41
10_4

10_4

12

PU3

PU3

VSEN

14

1 2

PR66

PR66

PR70

PR70

*0_6

*0_6

*0_6

*0_6

VCC3

Modify P/N to CS21912FB13
Modify Value to 1.91K/F_4

12

PR40

PR40

1.91K/F_4

1.91K/F_4

PC28 0.1U/X7R-50V_6PC28 0.1U/X7R-50V_6

1

48

3V3

PGOOD

35

UGATE1

36

BOOT1

34

PHASE1

32

LGATE1

33

PGND1

24

ISEN1

31

PVCC

27

UGATE2

26

BOOT2

28

PHASE2

30

LGATE2

29

PGND2

23

ISEN2

25

NC

8

OCSET

19

VSUM

18

VO

DFB

DROOP

17

16

PR50

PR50

3.48K/F_4

3.48K/F_4

PC35

PC35
180P/NPO-50V_4

180P/NPO-50V_4

12

PC29

PC29

.01U/X7R-16V_4

.01U/X7R-16V_4

PR36 0_4PR36 0_4
PR37 0_4PR37 0_4

PR71 2.2/F_6PR71 2.2/F_6

1 2

0.22U/X5R-25V_8

0.22U/X5R-25V_8

PC43

PC43

1 2

4.7U/X6S-25V_8

4.7U/X6S-25V_8

PR75 2.2/F_6PR75 2.2/F_6

1 2

0.22U/X5R-25V_8

0.22U/X5R-25V_8

12

PC41

PC41

0.22U/X7R-10V_6

0.22U/X7R-10V_6

PR54

PR54

1K_4

1K_4

ISL6262_VO

Parallel

PR73

PR73
*0_6

*0_6

12

PC44

PC44

ISEN1

5VSUS

12

PC46

PC46

ISEN2

PC25

PC25

12

1000P/X7R-50V_4

1000P/X7R-50V_4

PR31 13.3K/F_4PR31 13.3K/F_4

VSUM

ED8-B -0623-33nf to 68nf

12

PR74

PR74

11K/F_4

11K/F_4

PC42

PC42

68N/X7R-25V_6

68N/X7R-25V_6

PR125

PR125

12

PC45

PC45

0.22U/X5R-25V_6

0.22U/X5R-25V_6

DELAY_VR_PWRGOOD 6,8,19

PC39

PC39

0.22U/X5R-25V_6

0.22U/X5R-25V_6

6262_UG2

6262_LG2

PC40

PC40

0.22U/X5R-25V_6

0.22U/X5R-25V_6

PR124

PR124

2.7K_4

2.7K_4

Panasonic
ERT-J1VR103J

10K_6

10K_6

VCCSENSE 5

VSSSENSE 5

3

6262_UG1

6262_PH1

6262_LG1

12

12

Modify P/N to CS1332FB02
Modify Value to 13.3K/F_4

6262_PH2

4

4

VSUM

ISEN2

4

4

VSUM

ISEN1

PR65 3.65K/F_6PR65 3.65K/F_6

PR62 10K_6PR62 10K_6

PR72 1_6PR72 1_6

PR68 *0_6PR68 *0_6

Close to Phase 1 Inductor

5

10U/X6S-25V_1206

10U/X6S-25V_1206

213

PQ4

PQ4
AOL1414

AOL1414

5

PQ6

PQ6

213

AOL1412

AOL1412

5

10U/X6S-25V_1206

10U/X6S-25V_1206

213

PQ3

PQ3
AOL1414

AOL1414

5

PQ7

PQ7

213

AOL1412

AOL1412

PR46 3.65K/F_6PR46 3.65K/F_6

PR49 10K_6PR49 10K_6

PR53 1_6PR53 1_6

PR60 *0_6PR60 *0_6

PC49

PC49

12

4

PC50

PC50

10U/X6S-25V_1206

10U/X6S-25V_1206

5

213

12

4

VIN_6262

12

PC51

PC51

*SSM24PT-LF

*SSM24PT-LF

PQ8

PQ8

*AOL1412

*AOL1412

VIN_6262

12

PC48

PC48

10U/X6S-25V_1206

10U/X6S-25V_1206

5

PQ5

PQ5

213

*AOL1412

*AOL1412

+

+

PC59

PC59
470U/25V

470U/25V

PD6

PD6

2 1

*SSM24PT-LF

*SSM24PT-LF

2 1

12

PC52

PC52

0.1U/X7R-50V_6

0.1U/X7R-50V_6

PR148

PR148
*2.2_F_6

*2.2_F_6

PC143

PC143
*2200P_50V_6

*2200P_50V_6

12

PC47

PC47

0.1U/X7R-50V_6

0.1U/X7R-50V_6

PD5

PD5

*2200P_50V_6

*2200P_50V_6

2

PL4

PL4

HI0805R800R-00_8

HI0805R800R-00_8

PL5

PL5

HI0805R800R-00_8

HI0805R800R-00_8

VIN

Merom: VCC_CORE/ 44A
Yonah: VCC_CORE/ 36A

PL13

PL13

1 2

.36uH

.36uH

12

3

4

+

+

PC94

PC94

470u_2V_7343

470u_2V_7343

470u_2V_7343

470u_2V_7343

PR69

PR69

PR64

PR64

0_6

0_6

0_6

0_6

PL14

PL14

1 2

.36uH

.36uH

3

4

PR56

PR56
0_6

0_6

12

+

+

PC101

PC101

470u_2V_7343

470u_2V_7343

PR147

PR147
*2.2_F_6

*2.2_F_6

PC142

PC142

PR51

PR51

0_6

0_6

12

PC146

PC146

PC148

.1U_4

.1U_4

PC148
.1U_4

.1U_4

PC95

PC95

+

+

Modify P/N to CV+18V0MZ04

PC147

PC147

PC149

PC149

.1U_4

.1U_4

.1U_4

.1U_4

VCC_CORE

12

PC100

PC100
470u_2V_7343

470u_2V_7343

+

+

1

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

CPU CAORE (6262A)

CPU CAORE (6262A)

CPU CAORE (6262A)

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

PROJECT : PL3

1

A

A

34 38Wednesday, January 10, 2007

34 38Wednesday, January 10, 2007

34 38Wednesday, January 10, 2007

A

of

of

of

1

2

3

4

5

A A

PR9

PR9

10_6

PR13

PR13

1M_6

PC78

PC78

1000P/X7R-50V_6

1000P/X7R-50V_6

1M_6

12

PC14

PC14

.01U/X7R-50V_6

.01U/X7R-50V_6

12

C test change: add PR150

PR115 0_6PR115 0_6

MAINON31,36,37

HWPG_1.05V31

B B

PR150

PR150
10K_6

10K_6

VCC3

PR109

PR109
10K_6

10K_6

PC75

PC75

0.1U/X7R-50V_6

0.1U/X7R-50V_6

10_6

PU1

PU1
SC411MLTRT

SC411MLTRT

15
16

1
2
3
4
6
5

14

EN/PSV
VIN
VOUT
VCCA
FBK
PGOOD
VSSA
NC
NC

VDDP

PGND

TPAD

GND18GND19GND20GND

21

BST

DH
LX

ILIM

DL

PC70

PC70
*.1U/50V_6

*.1U/50V_6

5VSUS

21

PD8

PD8

12

SW1010C

SW1010C

PC11

PC11
.1U/X7R-50V_8

13
12
11
10
9
8
7
17

.1U/X7R-50V_8

DH-1.05V

PR7 20K_6PR7 20K_6

from 20k to 6.65k C -TEST_1/11

DL-1.05V

PC8

PC8

4.7U/Y5V-10V_8

4.7U/Y5V-10V_8

5

PQ27

PQ27
AOL1414

AOL1414

4

213

PL6

PL6

1R5UH-3.8mR

1R5UH-3.8mR

5

4

213

PQ30

PQ30
AOL1412

AOL1412

PR149

PR149
*2.2_F_6

*2.2_F_6

PC144

PC144
*2200P_50V_6

*2200P_50V_6

PC2

PC2

.1U/X7R-50V_8

.1U/X7R-50V_8

12

+

+

PC63

PC63

560U/2.5V_6X5.7

560U/2.5V_6X5.7

VIN-1.5V

PC3

PC3

10U/X6S-25V_1206

10U/X6S-25V_1206

12

+

+

PC62

PC62

560U/2.5V_6X5.7

560U/2.5V_6X5.7

PC65

PC65

10U/X6S-25V_1206

10U/X6S-25V_1206

PC68

PC68

10U/Y5U-10V_8

10U/Y5U-10V_8

PL1

PL1

HI0805R800R-00_8

HI0805R800R-00_8

PR6

PR6
11K_6

11K_6

PR4

PR4
10K_6

10K_6

VIN

JP2 SHORT PADJP2 SHORT PAD

JP3 SHORT PADJP3 SHORT PAD

PC71

PC71
33P/NPO-50V_6

33P/NPO-50V_6

change 5:PR105 change from
20K to 11K.VCC1.05 change
from 1.5V to 1.05V

16A

12

VCC1.05

12

VOUT=(1+R2/R3)*0.5

C C

D D

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

VTT 1.05V (SC11)

VTT 1.05V (SC11)

VTT 1.05V (SC11)

Date: Sheet

Date: Sheet

1

2

3

4

Date: Sheet

PROJECT : PL3

5

A

A

35 38Thursday, January 11, 2007

35 38Thursday, January 11, 2007

35 38Thursday, January 11, 2007

A

of

of

of

5

4

3

2

1

E E

1.8VSUS

SHORT PAD

SHORT PAD

JP1

JP1

10U/Y5V-10V_1206

10U/Y5V-10V_1206

12

PR24

PR24

0_6

0_6

DIS_MODE

SMDDR_VTERM

SMDDR_VREF

D D

PR20 *0_6PR20 *0_6

1.8VSUS

PR23 0_6PR23 0_6

C C

PC18

PC18

PC19

PC19
10U/Y5V-10V_1206

10U/Y5V-10V_1206

PC83

PC83
10U/Y5V-10V_1206

10U/Y5V-10V_1206

DIS_MODE

PC17

PC17
.033U/50V_6

.033U/50V_6

5VIN

5VIN

PR19

PR19

0_6

0_6

FOR DDR II

10

1
2
4
5
3
6
7
8
9

PU2

PU2
TPS51116

TPS51116

VLDOIN
VTT
VTTSNS
GND
VTTGND
MODE
VTTREF
COMP
VDDSNS
VDDQSET

5VPCU

DRVH

PGND

PGOOD

GND21GND22GND23GND24GND25GND26GND

27

*1000P_50V_6

*1000P_50V_6

PR120

PR120

0_6

0_6

19
20

VBST

18

LL

17

DRVL

16

S3_1.8V

11

S3

12

S5

14

V5IN

13
15

CS

PC33

PC33

5VIN

PR29 0_6PR29 0_6

S5_1.8V

PR28 0_6PR28 0_6

5VIN

PR121

PR121

8.25K/F_6

8.25K/F_6

from 12k to 8.25k C-TEST_1/11

12

PC84

PC84

4.7U/X5R-6.3V_6

4.7U/X5R-6.3V_6

PC32 0.1U/X7R-50V_6PC32 0.1U/X7R-50V_6

PR43

PR43

3VPCU

100K_6

100K_6

S3_1.8V S5_1.8V

MAINON 31,35,37
SUSON 31,37

3VPCU

PR33 *0_6PR33 *0_6

HWPG_1.8V 31

578

PQ33

PQ33
FDS8884

FDS8884

3 6

241

578

3 6

241

FDS6690AS

FDS6690AS

change 3:should unstuff PR33.mainon
and suson cannot be connected together

PQ35

PQ35

578

3 6

241

PQ34

PQ34
FDS6690AS

FDS6690AS

PR122

PR122
*2.2_F_6

*2.2_F_6

PC87

PC87

*2200P_50V_6

*2200P_50V_6

PR123

PR123
*2.2_F_6

*2.2_F_6

PC88

PC88
*2200P_50V_6

*2200P_50V_6

1R5UH-3.8mR

1R5UH-3.8mR

PC86

PC86

2200P/X7R-50V_6

2200P/X7R-50V_6

10U/X6S-25V_1206

10U/X6S-25V_1206

PC85

PC85

PC36

PC36

10U/X6S-25V_1206

10U/X6S-25V_1206

PL12

PL12

PC89

PC89

+

+

560U/2.5V_6X5.7

560U/2.5V_6X5.7

PL11

PL11

HI0805R800R-00_8

HI0805R800R-00_8

10U/X6S-25V_1206

10U/X6S-25V_1206
PC26

PC26
JP4 SHORT PADJP4 SHORT PAD

12

JP5 SHORT PADJP5 SHORT PAD

12

MAX Current 10A

PC90

PC90
10U/Y5V-10V_8

10U/Y5V-10V_8

VIN

1.8VSUS

B B

A A

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

DDR2 1.8V(TP1116)

DDR2 1.8V(TP1116)

DDR2 1.8V(TP1116)

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

PROJECT : PL3

1

A

A

36 38Thursday, January 11, 2007

36 38Thursday, January 11, 2007

36 38Thursday, January 11, 2007

A

of

of

of

5

4

3

2

1

PC92

PC92
10U/X5R-6.3V_6

10U/X5R-6.3V_6

9338DRV

6

5

Vout1 = (1+Rg/Rh)*0.5

SUSD 33

PQ36 FDS8884PQ36 FDS8884

8
7

5

4

PR77

PR77
0_6

0_6

PC53

PC53
.01U/X7R-25V_4

.01U/X7R-25V_4

1
2
36

from 15k to 15.8k c-test 1/12

PR126

PR126

15.8K/F_6

15.8K/F_6

PR130

PR130

10K_6

10K_6

Rg

Rh

PR78

PR78
10K_6

10K_6

PC104

PC104

0.1U/X7R-50V_6

0.1U/X7R-50V_6

3VSUS

PC102

PC102

10U/Y5U-10V_8

10U/Y5U-10V_8

PC97

PC97

0.1U/Y5V-16V_4

0.1U/Y5V-16V_4

PC103

PC103
1U/16V_6

1U/16V_6

PC98

PC98
10U/X5R-6.3V_6

10U/X5R-6.3V_6

1

3
4

1.24V R1

VCC1.25

3A

560U/2.5V_6X5.7

560U/2.5V_6X5.7

GND0
EN2VO2

GND1

VIN1
VIN2

GND2

ADJ

7

PU6

PU6
AT815

AT815

VTT-ADJ

PR131

PR131
10K_6

10K_6

+

+

VO1

VCC1.25 8,11,20,29

PC99

PC99

5
6
8
9

PR129

PR129

Vout=1.24*[1+(R1/R2)]

2.15K/F_6

2.15K/F_6

PC106

PC106
10U/Y5U-10V_8

10U/Y5U-10V_8

PC107

PC107

0.1U/X7R-50V_6

0.1U/X7R-50V_6

12

+

+

PC105

PC105
*150U_4V_3528

*150U_4V_3528

JP6 SHORT PADJP6 SHORT PAD

12

VCC1.5

1.8VSUS

+

+

PC93

PC91

560U/2.5V_6X5.7

560U/2.5V_6X5.7

PR128 100K_4PR128 100K_4

REV:3A MODIFY

PR127 0_4PR127 0_4

5VSUS

PR84

PR84
22_6

22_6

3

2

PQ11

PQ11
2N7002E

2N7002E

1

PC91

2

E E

VCC3

HWPG_CPUIO31

D D

VIN

PR85

PR83

PR83
1M_6

1M_6

SUSON31,36

C C

2

PQ13

PQ13

DTC144EU

DTC144EU

PR86

PR86
1M_6

1M_6

1 3

PR85
22_6

22_6

3

2

2

PQ14

PQ14
2N7002E

2N7002E

1

3VSUS 15V1.8VSUSSMDDR_VREF

PR82

PR82

PR81

PR81

22_6

22_6

22_6

22_6

3

3

2

PQ10

PQ10

PQ15

PQ15

2N7002E

2N7002E

2N7002E

2N7002E

1

1

PC93

0.1U/Y5V-16V_4

0.1U/Y5V-16V_4

3

PGD

4

EN

1

VCC

PC96

PC96

0.1U/Y5V-16V_4

0.1U/Y5V-16V_4

DRV

GND

2

PC56

PC56
*2200P_4

*2200P_4

ADJ

PU5

PU5
G9338 ADJ

G9338 ADJ

9338ENMAINON

5VPCU

PR80

PR80
1M_6

1M_6

SUSDSUS_ON_G MAINON

3

PQ12

PQ12
2N7002E

2N7002E

1

VIN

B B

MAINON31,35,36

A A

2

PQ18

PQ18

DTC144EU

DTC144EU

1 3

5

VCC1.25 VCC1.05 VCC_Core

PR96

PR96
1M_6

1M_6

RUN_ON_G

PR99

PR99
1M_6

1M_6

PR91

PR91
22_6

22_6

3

2

PQ21

PQ21
2N7002E

2N7002E

1

PR87

PR88

PR88
22_6

22_6

3

2

PQ17

PQ17
2N7002E

2N7002E

1

PR87
22_6

22_6

3

2

PQ16

PQ16
2N7002E

2N7002E

1

4

2

VCC3 15VVCC5VCC1.5 VCC1.5SMDDR_VTERM

PR92

PR92
22_6

22_6

3

1

PQ19

PQ19
2N7002E

2N7002E

PR89

PR89
22_6

22_6

3

2

PQ22

PQ22
2N7002E

2N7002E

1

PR93

PR93
22_6

22_6

3

2

1

PQ25

PQ25
2N7002E

2N7002E

PR95

PR95
22_6

22_6

3

2

1

3

PQ23

PQ23
2N7002E

2N7002E

PR94

PR94

PR90

PR90

22_6

22_6

1M_6

1M_6

MAIND

3

3

2

2

1

PQ24

PQ24
2N7002E

2N7002E

PQ20

PQ20
2N7002E

2N7002E

1

PC58

PC58
*2200P_4

*2200P_4

MAIND 33

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

PROJECT : PL3

PROJECT : PL3

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

DISCHARGE/1.5V/2.5V

DISCHARGE/1.5V/2.5V

DISCHARGE/1.5V/2.5V

Date: Sheet

Date: Sheet

2

Date: Sheet

PROJECT : PL3

1

A

A

37 38Friday, January 12, 2007

37 38Friday, January 12, 2007

37 38Friday, January 12, 2007

A

of

of

of

5

d

d

d

4

3

2

1

D D

change1:SMBUS clock to data wrong connection

change2:change SMDDR_VTERM to SMDDR_VREF_DIMM in page 15
SMDDR_VREF_DIMM is from SMDDR_VREF;
wrong connection of SMDDR_VTERM and SMDDR_VREF

change 3:should unstuff PR114

C C

change 4:change LPC schematic to
match ZH3 debug card

change 5:PR105 change from
20K to 11K.VCC1.05 change
from 1.5V to 1.05V

B B

A A

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

5

4

3

Date: Sheet

<Title>

<Title>

<Title>

<Doc> <RevCo

<Doc> <RevCo

<Doc> <RevCo

A

A

A

of

of

of

38 38Wednesday, January 10, 2007

38 38Wednesday, January 10, 2007

2

38 38Wednesday, January 10, 2007

1