Quanta PB5, PB6 Schematic
1
2
3
4
5
6
7
8
http://hobi-elektronika.net
VCC_CORE
+1.5V
A A
+1.05V
+1.25V
+1.8VSUS
+1.8V
+3VPCU
+3V_S5
+3VSUS
+3V
+5VPCU
+5V_S5
+5V
+SMDDR_VTERM
+SMDDR_VREF
B B
C C
HP
Page 30
MIC JACK
Page 30
D D
INT SPK
Page 29
SPK AMP
Page 29
INT MIC
Page 19
Port-A
Port-B
CRT
LCD PANEL
SATA - HDD
SATA - ODD
eSATA
WLAN
Camera
Bluetooth
New Card
M/B USB2
M/B USB
TV/ROBSON
AUDIO CODEC
ALC268/ALC272
Page 20
Page 19
SATA
Page 22
SATA
Page 22
SATA
Page 22
USB-5
Page 25
USB-3
Page 19
USB-2
Page 26
USB-9
Page 27
USB-7
Page 27
USB-6
Page 27
USB-8
Page 25
Page 29
PB5/6 Block Diagram
Intel
PENRYN
uFCPGA
Page 3,4
FSB(667/800MHZ)
CRT
NB
FAN
CANTIGA
Page 5,7,8,9,10,11
DMI(x2/x4)
SB
ICH9M
Page 12, 13, 14, 15
LPC
ITE8512
Key FLASH
T/P
Board
Page 26
Board
Page 26 Page 28 Page 28
ROM
LVDS
USB 2.0
Azalia
Page 3
PCI-E 16X Lan
533/ 667 MHZ DDR II
PCI-Express
PCIE-6 PCIE-5
MINI CARD-1
WLAN
PCI Bus
32.768KHz
Page 28
CIR
CLOCK GENERATOR
CK505
ICS9LPR363
VGA CONNECTOR
DDRII-SODIMM1
DDRII-SODIMM2
Page 16, 17
(FTB)
MINI CARD-2
Page 25
UMA TV/ROBSON
Page 25
OZ129
Page 24
4 IN 1 1394
Page 24 Page 24
Page 2
Page 18
MINI CARD-4
ROBSON
Page 25
PCIE-4
CRT
HDMI
LCD/LED
PCIE-1PCIE-3
NEW CARD
Page 27
LAN
RTL8102
VGA
Board
USB
Board
Touch Pad
Board
Function
Board
Page 26
Daughter
Board
01
PROJECT : PB5/6
PROJECT : PB5/6
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Block Diagram
Block Diagram
Block Diagram
Date: Sheet
Date: Sheet
1
2
3
4
5
6
Date: Sheet
7
Quanta Computer Inc.
135Friday, March 21, 2008
135Friday, March 21, 2008
135Friday, March 21, 2008
of
of
of
8
1A
1A
1A
5
Clock Generator
L41 PBY160808T-301Y-N_6L41 PBY160808T-301Y-N_6
VCC3
D D
C101 33p/50V_4C101 33p/50V_4
CL=20p
C100 33p/50V_4C100 33p/50V_4
C C
ICS9LPRS365
(ALPRS365K13)
Pin 4
PCI2/TME
Pin 5
PCI-3
PCI-4/27M_SEL
Pin 6
PCIF-5/ITP_EN
Pin 7
B B
CG_XIN PCI_CLK_SIO_R
21
Y2
14.318MHZY214.318MHZ
CG_XOUT
RTM875T-606
(AL000875K06)
PCI2/TME
internal PD
PCI-3/SRC5_EN
internal PD
PCI-4/27M_SEL
internal PD
PCIF-5/ITP_EN
internal PD
PULL HIGH PULL DOWN
NO OVERCLOCKING NORMAL RUN
PIN37/38 IS SRC5
PIN 17/18 IS 27MHz
PIN 46/47 IS CPUITP PIN 46/47 IS SRC8
(default)
C535
C535
10u/10V_6
10u/10V_6
PCLK_DEBUG24
T36T36
PCLK_OZ12925
PCLK_EC28
PCLK_ICH13
CLKUSB_4814
14M_ICH14
PIN37/38 IS
PCI_STOP/CPU_STOP
PIN 17/18
IS SRC/DOT
PCLK_OZ129
PCLK_ICH
CLK_BSEL0
CLK_BSEL1
CLK_BSEL2
(default)
(default)
(default)
R86 33_4R86 33_4
R91 2.2K_4R91 2.2K_4
R111 10K_4R111 10K_4
R108 33_4R108 33_4
4
C507 0.1u/10V_4C507 0.1u/10V_4
C88 0.1u/10V_4C88 0.1u/10V_4
C521 10u/10V_6C521 10u/10V_6
C84 0.1u/10V_4C84 0.1u/10V_4
C542 0.1u/10V_4C542 0.1u/10V_4
C515 0.1u/10V_4C515 0.1u/10V_4
C93 0.1u/10V_4C93 0.1u/10V_4
R118 56R118 56
R114 33_4R114 33_4
R110 33_4R110 33_4
R109 10K_4R109 10K_4
R107 33_4R107 33_4
R101 33_4R101 33_4
VCC3
VCC3
VCC3
VDD_CK_VDD_PCI
VDD_CK_VDD_48
VDD_CK_VDD_PCI
VDD_CK_VDD_REF
VDD_CK_VDD_PCI
VDD_CK_VDD_CPU
VCCP_VDD
PCLK_DEBUG_RPCLK_DEBUG
PCLK_PCM_R
PCLK_OZ129_R
PCLK_EC_RPCLK_EC
PCLK_ICH_R
CG_XIN
CG_XOUT
FSA
FSB
FSC
R520 10K_4R520 10K_4
R113 *10K_4R113 *10K_4
R521 *10K_4R521 *10K_4
R106 10K_4R106 10K_4
R526 *10K_4R526 *10K_4
R100 10K_4R100 10K_4
3
http://hobi-elektronika.net
C544
U8
U8
2
VDD_PCI
9
VDD_48
16
VDD_PLL3
61
VDD_REF
39
VDD_SRC
55
VDD_CPU
12
VDD_96_IO
20
VDD_PLL3_IO
26
VDD_SRC_IO_1
45
VDD_SRC_IO_3
36
VDD_SRC_IO_2
49
VDD_CPU_IO
1
PCI0/CR#_A
3
PCI1/CR#_B
4
PCI2/TME
5
PCI3
6
PCI4/SRC5_EN
7
PCIF5/ITP_EN
60
XTAL_IN
59
XTAL_OUT
10
USB_48/FSA
57
FSB/TEST/MODE
62
REF0/FSC/TESTSEL
8
VSS_PCI
11
VSS_48
15
VSS_IO
19
VSS_PLL3
52
VSS_CPU
23
VSS_SRC1
29
VSS_SRC2
42
VSS_SRC3
58
VSS_REF
ICS9LPRS365BGLFT
ICS9LPRS365BGLFT
PCLK_OZ129
PCLK_EC
HIGH 27MHz
LOW SRC
PCLK_ICH
C544
C553
C553
10u/10V_6
10u/10V_6
*10u/10V_6
*10u/10V_6
48
IO_VOUT
CGCLK_SMB
64
SCLK
CGDAT_SMB
63
CK505
CK505
CKPWRGD/PWRDWN#
SDA
PM_STPPCI#
CPU0
CPU0#
CPU1
CPU1#
SRC8/ITP
SRC8#/ITP#
SRC10#
SRC10
SRC11/CR#_H
SRC11#/CR#_G
SRC9
SRC9#
SRC7/CR#_F
SRC7#/CR#_E
SRC6
SRC6#
SRC4
SRC4#
SRC3/CR#_C
SRC3#/CR#_D
SRC2/SATA
SRC2#/SATA#
SRC1/SE1
SRC1#/SE2
SRC0/DOT96
SRC0#/DOT96#
38
PM_STPCPU#
37
CLK_CPU_BCLK_R
54
CLK_CPU_BCLK#_R
53
CLK_MCH_BCLK_R
51
CLK_MCH_BCLK#_R
50
CLK_PCIE_MINI3_R
47
CLK_PCIE_MINI3#_R
46
CLK_PCIE_3GPLL#_R
35
CLK_PCIE_3GPLL_R
34
CLK_MCH_OE#_R
33
NEW_CLKREQ#_R
32
CLK_PCIE_NEW_R
30
CLK_PCIE_NEW_R#
31
CLK_PCIE_MINI2_R
44
CLK_PCIE_MINI2#_R
43
CLK_PCIE_MINI_R
41
CLK_PCIE_MINI#_R
40
CLK_PCIE_LAN_R
27
CLK_PCIE_LAN#_R
28
CLK_PCIE_ICH_R
24
CLK_PCIE_ICH#_R
25
CLK_PCIE_SATA_R
21
CLK_PCIE_SATA#_R
22
DREFSSCLK_R
17
DREFSSCLK#_R
18
DREFCLK_R
13
DREFCLK#_R
14
56
SRC5/PCI_STOP#
SRC5#/CPU_STOP#
<MAIN>:ICS9LPRS365BGLFT QCI:ALPRS365K13
<SECOND>:SLG8SP512TTR: QCI:AL8SP512K05
C540
C540
0.1u/10V_4
0.1u/10V_4
C543
C543
0.1u/10V_4
0.1u/10V_4
C528
C528
0.1u/10V_4
0.1u/10V_4
RP14 0X2RP14 0X2
1
3
RP12 0X2RP12 0X2
1
3
RP10 IV@0X2RP10 IV@0X2
1
3
RP3 0X2RP3 0X2
1
3
R74 475/F_4R74 475/F_4
R73 475/F_4R73 475/F_4
RP2 0X2RP2 0X2
3
1
RP8 0X2RP8 0X2
1
3
RP6 0X2RP6 0X2
1
3
RP4 0X2RP4 0X2
3
1
RP5 0X2RP5 0X2
3
1
RP7 0X2RP7 0X2
3
1
RP13 0RP13 0
3
1
C532
C532
0.1u/10V_4
0.1u/10V_4
DREFSSCLK_R
DREFSSCLK#_R
2
4
2
4
2
4
2
4
4
2
2
4
2
4
4
2
4
2
4
2
4
2
C537
C537
0.1u/10V_4
0.1u/10V_4
2
VCCP_VDD
C545
C545
0.1u/10V_4
0.1u/10V_4
PM_STPPCI# 14
PM_STPCPU# 14
CLK_CPU_BCLK 3
CLK_CPU_BCLK# 3
CLK_MCH_BCLK 5
CLK_MCH_BCLK# 5
CLK_PCIE_MINI3 24
CLK_PCIE_MINI3# 24
CLK_PCIE_3GPLL# 6
CLK_PCIE_3GPLL 6
CLK_MCH_OE# 6
NEW_CLKREQ# 24
CLK_PCIE_NEW 24
CLK_PCIE_NEW# 24
CLK_PCIE_MINI2 24
CLK_PCIE_MINI2# 24
CLK_PCIE_MINI 24
CLK_PCIE_MINI# 24
CLK_PCIE_LAN 23
CLK_PCIE_LAN# 23
CLK_PCIE_ICH 13
CLK_PCIE_ICH# 13
CLK_PCIE_SATA 12
CLK_PCIE_SATA# 12
DREFCLK 6
DREFCLK# 6
CK_PWRGD 14
RP9 IV@0X2RP9 IV@0X2
RP11 EV@0X2RP11 EV@0X2
1
L50PBY160808T-301Y-N_6 L50PBY160808T-301Y-N_6
VCCP
02
BOM Option Table
To SB
To CPU
Reference
IV@
Description
INT VGA
EXT VGAEV@
To NB
To ROBSON
To NB
To New Card
To TV
To WLAN
To LAN
PM_STPPCI#
PM_STPCPU#
NEW_CLKREQ#_R
R76 2.2K_4R76 2.2K_4
R75 2.2K_4R75 2.2K_4
R560 10K_4R560 10K_4
VCC3
To SB
To SB
To NB
2
1
4
3
4
3
2
1
DREFSSCLK 6
DREFSSCLK# 6
CLK_MXM 20
CLK_MXM# 20
To NB
To VGA Card
FREQ. SEL TABLE
BSEL Frequency Select Table
VCCP
CPU_BSEL03
R87 0_4R87 0_4
R88 *56_4R88 *56_4
R89 1K_4R89 1K_4
CLK_BSEL0
MCH_BSEL0 6
Clock Gen I2C
SDATA14,24
FSC FSB FSA Frequency
0
0
0
A A
1
0
1
0
1
1
1
0
1
000
266Mhz0
1
133Mhz
1
166Mhz
200Mhz
0
400Mhz
011
1
Reserved
1
100Mhz
CPU_BSEL13
VCCP
CPU_BSEL23
VCCP
R95 0_4R95 0_4
R93 *0_4R93 *0_4
R94 1K_4R94 1K_4
R112 0_4R112 0_4
R116 *0_4R116 *0_4
R117 1K_4R117 1K_4
CLK_BSEL1
CLK_BSEL2
MCH_BSEL1 6
SCLK14,24
MCH_BSEL2 6
333Mhz
5
4
3
VCC3
Q7
2
RHU002N06Q7RHU002N06
3
VCC3
Q8
2
RHU002N06Q8RHU002N06
3
R127
R127
10K_4
10K_4
2
R134
R134
10K_4
10K_4
CGDAT_SMB
CGCLK_SMB
CGDAT_SMB 17
CGCLK_SMB 17
1
1
PCLK_OZ129
C506 10pC506 10p
PCLK_EC
C508 10pC508 10p
CLKUSB_48
C87 10pC87 10p
14M_ICH
C95 10pC95 10p
PCLK_ICH
C512 10pC512 10p
PCLK_DEBUG
C505 22pC505 22p
PROJECT : PB5/6
PROJECT : PB5/6
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
CLK GEN
CLK GEN
CLK GEN
Date: Sheet
Date: Sheet
Date: Sheet
Quanta Computer Inc.
of
of
of
235Friday, May 30, 2008
235Friday, May 30, 2008
1
235Friday, May 30, 2008
1A
1A
1A
5
4
3
2
1
H_A#[3..16]5
D D
H_ADSTB#05
H_REQ#[0..4]5
H_A#[17..35]5
H_ADSTB#15
H_A20M#12
H_FERR#12
C C
H_IGNNE#12
H_STPCLK#12
H_INTR12
H_NMI12
H_SMI#12
Thermal Trip
VCCP
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1
H_A20M#
H_FERR#
H_IGNNE#
R578 0_4R578 0_4
H_INTR
H_NMI
H_SMI#
T19T19
T18T18
T15T15
T13T13
T158T158
T159T159
T26T26
T160T160
T20T20
VCCP
M3
N2
N3
R1
M1
H2
U5
R3
W6
U4
U1
R4
W2
W5
U2
W3
AA4
AB2
AA3
C4
D5
C6
M4
N5
D2
D22
D3
J4
L5
L4
K5
J1
P5
P2
L2
P4
P1
K3
K2
J3
L1
Y2
Y5
T5
T3
Y4
V4
V1
A6
A5
B4
A3
T2
V3
B2
F6
U29A
U29A
A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#
A20M#
FERR#
IGNNE#
STPCLK#
LINT0
LINT1
SMI#
RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]
Penryn_1p0
Penryn_1p0
ADDR GROUP_0
ADDR GROUP_0
ADDR GROUP_1
ADDR GROUP_1
ICH
ICH
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
CONTROL
CONTROL
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
HIT#
HITM#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDO
TMS
TRST#
DBR#
XDP/ITP SIGNALS
XDP/ITP SIGNALS
THERMAL
THERMAL
PROCHOT#
THERMDA
THERMDC
THERMTRIP#
H CLK
H CLK
BCLK[0]
BCLK[1]
RESERVED
RESERVED
TDI
H_ADS#
H1
H_BNR#
E2
H_BPRI#
G5
H_DEFER#
H5
H_DRDY#
F21
H_DBSY#
E1
H_BREQ#
F1
H_IERR#
D20
H_INIT#
B3
H_LOCK#
H4
H_CPURST#
C1
H_RS#0
F3
H_RS#1
F4
H_RS#2
G3
H_TRDY#
G2
H_HIT#
G6
H_HITM#
E4
XDP_BPM#0
AD4
XDP_BPM#1
AD3
XDP_BPM#2
AD1
XDP_BPM#3
AC4
XDP_BPM#4
AC2
XDP_BPM#5
AC1
XDP_TCK
AC5
XDP_TDI
AA6
XDP_TDO
AB3
XDP_TMS
AB5
XDP_TRST#
AB6
C20
H_PROCHOT#_D
D21
H_THERMDA
A24
H_THERMDC
B25
CPU_PM_THRMTRIP#
C7
CLK_CPU_BCLK
A22
CLK_CPU_BCLK#
A21
H_ADS# 5
H_BNR# 5
H_BPRI# 5
H_DEFER# 5
H_DRDY# 5
H_DBSY# 5
H_BREQ# 5
H_INIT# 12
H_LOCK# 5
H_CPURST# 5
H_RS#0 5
H_RS#1 5
H_RS#2 5
H_TRDY# 5
H_HIT# 5
H_HITM# 5
T11T11
T7T7
T6T6
T9T9
T10T10
T5T5
R68 0_4R68 0_4
CLK_CPU_BCLK 2
CLK_CPU_BCLK# 2
SYS_RST#XDP_DBRESET#
http://hobi-elektronika.net
H_D#[0..15]5
ZS2 Default no use this function
R67 56_4R67 56_4
Connect it to CPU DBR# is for ITP debug port
or CPU interposer (like ICE) to reset the system
SYS_RST# 14
VCCP
Layout note:
H_GTLREF: Zo=55 ohm,L<0.5"
2/3*VCCP+-2%
VCCP
R40
R40
1K/F_4
1K/F_4
R39
R39
2K/F_4
2K/F_4
H_DSTBN#05
H_DSTBP#05
H_DINV#05
H_D#[16..31]5
H_DSTBN#15
H_DSTBP#15
H_DINV#15
CPU_BSEL02
CPU_BSEL12
CPU_BSEL22
U29B
AD26
AF26
E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25
N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24
C23
D25
C24
AF1
A26
B22
B23
C21
C3
U29B
D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL[0]
BSEL[1]
BSEL[2]
Penryn_1p0
Penryn_1p0
DATA GRP 0
DATA GRP 0
DATA GRP 1
DATA GRP 1
MISC
MISC
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
DATA GRP 2DATA GRP 3
DATA GRP 2DATA GRP 3
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
COMP[0]
COMP[1]
COMP[2]
COMP[3]
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
R26
U26
AA1
Y1
E5
B5
D24
D6
D7
AE6
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3
COMP0
COMP1
COMP2
COMP3
ICH_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGD
H_CPUSLP#
PSI#
R48 27.4/F_6R48 27.4/F_6
R47 54.9/F_4R47 54.9/F_4
R43 27.4/F_6R43 27.4/F_6
R44 54.9/F_4R44 54.9/F_4
Layout note:
ICH_DPRSTP# , Daisy Chain
(SB>PowerIC>NB>CPU)
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1
H_GTLREF
CPU_TEST1
T25T25
CPU_TEST2
T23T23
CPU_TEST3
T22T22
CPU_TEST4
T12T12
CPU_TEST5
T8T8
CPU_TEST6
T24T24
CPU_TEST7
T21T21
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
H_D#[32..47] 5
H_DSTBN#2 5
H_DSTBP#2 5
H_DINV#2 5
H_D#[48..63] 5
H_DSTBN#3 5
H_DSTBP#3 5
H_DINV#3 5
ICH_DPRSTP# 6,12,31
H_DPSLP# 12
H_DPWR# 5
H_CPUSLP# 5
PSI# 31
BOM Option Table
Reference
N/A
Layout note:
comp0,2: Zo=27.4ohm, L<0.5"
comp1,3: Zo=55ohm, L<0.5"
H_PWRGD 12
Description
CPU Thermal monitorXDP
03
N/A
3
R580
SYS_SHDN#CPU_PM_THRMTRIP#
PM_THRMTRIP#
R580
*10K_4
*10K_4
SYS_SHDN# 30
PM_THRMTRIP# 6,12
D31
D31
*BAS316
*BAS316
C562
C562
*1u/16V_6
*1u/16V_6
Q29
Q29
VCCP
2
FDV301N
FDV301N
1
R572
R572
56.2/F_4
56.2/F_4
Q26
Q26
2
MMBT3904
MMBT3904
1 3
R571 *0_4R571 *0_4
No use Thermal trip CPU side still PU 56ohm.
Use Thermal trip can share PU at SB side
DELAY_VR_PWRGOOD6,14,31
B B
Processor hot
VCCP
No use PROCHOT CPU side still PU 56ohm.
Use PROCHOT to optional receiver CPU side PU
68ohm and through isolat 2.2K ohm to receiver
R71
R71
A A
H_PROCHOT#_D
56_4
56_4
R70 *0_4R70 *0_4
5
side
H_PROCHOT# 31
R581
R581
*51/F_4
*51/F_4
H_CPURST#
VCCP
12
4
Reserve 1K for XDP function
XDP_TDO
R32 *51/F_4R32 *51/F_4
XDP_TDI
R33 56_4R33 56_4
XDP_TMS
R34 54.9/F_4R34 54.9/F_4
XDP_TCK
R36 56_4R36 56_4
XDP_TRST#
R35 56_4R35 56_4
VCCP
MBCLK20,28,35
MBDATA20,28,35
THERM_ALERT#14,29
3
VCC3
2
Q22
Q22
3
RHU002N06
RHU002N06
NS LM95245 PU this pin
VCC3
VCC3
VCC3
SYS_SHDN#30
2
1
2
3
Q24 RHU002N06Q24 RHU002N06
R563 *10K_4R563 *10K_4
R565 0_4R565 0_4
R566 10K_4R566 10K_4
R569 330_4R569 330_4
1
2
13
Q23 MMBT3904Q23 MMBT3904
2ND_MBCLK#
2ND_MBDATA#
THERM_ALERT#_R
THER_SHD#
R562
R562
10K_4
10K_4
VCC3VCC3
LM86VCC
SDAT
SCLK
VCC
GND
C554 0.1u/10V_4C554 0.1u/10V_4
4
OVT
6
ALERT
2
DXP
3
DXN
PROJECT : PB5/6
PROJECT : PB5/6
Quanta Computer Inc.
Quanta Computer Inc.
1
C555
C555
2200p/50V_4
2200p/50V_4
R561 200_6R561 200_6
R568
R568
10K_4
10K_4
U27
U27
7
8
1
5
G780
G780
ADDRESS: 98H
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
CPU(1/2) HOST BUS
CPU(1/2) HOST BUS
CPU(1/2) HOST BUS
Date: Sheet
Date: Sheet
Date: Sheet
H_THERMDA
H_THERMDC
335Friday, May 30, 2008
335Friday, May 30, 2008
335Friday, May 30, 2008
1A
1A
1A
of
of
of
5
4
http://hobi-elektronika.net
3
2
BOM Option Table
Reference
N/A
Description
N/A
1
04
Need NC 20PCS 10u before A1 BOM released(A0 all stuff)
D D
C C
B B
A A
U29D
U29D
A4
VSS[001]
A8
VSS[002]
A11
VSS[003]
A14
VSS[004]
A16
VSS[005]
A19
VSS[006]
A23
VSS[007]
AF2
VSS[008]
B6
VSS[009]
B8
VSS[010]
B11
VSS[011]
B13
VSS[012]
B16
VSS[013]
B19
VSS[014]
B21
VSS[015]
B24
VSS[016]
C5
VSS[017]
C8
VSS[018]
C11
VSS[019]
C14
VSS[020]
C16
VSS[021]
C19
VSS[022]
C2
VSS[023]
C22
VSS[024]
C25
VSS[025]
D1
VSS[026]
D4
VSS[027]
D8
VSS[028]
D11
VSS[029]
D13
VSS[030]
D16
VSS[031]
D19
VSS[032]
D23
VSS[033]
D26
VSS[034]
E3
VSS[035]
E6
VSS[036]
E8
VSS[037]
E11
VSS[038]
E14
VSS[039]
E16
VSS[040]
E19
VSS[041]
E21
VSS[042]
E24
VSS[043]
F5
VSS[044]
F8
VSS[045]
F11
VSS[046]
F13
VSS[047]
F16
VSS[048]
F19
VSS[049]
F2
VSS[050]
F22
VSS[051]
F25
VSS[052]
G4
VSS[053]
G1
VSS[054]
G23
VSS[055]
G26
VSS[056]
H3
VSS[057]
H6
VSS[058]
H21
VSS[059]
H24
VSS[060]
J2
VSS[061]
J5
VSS[062]
J22
VSS[063]
J25
VSS[064]
K1
VSS[065]
K4
VSS[066]
K23
VSS[067]
K26
VSS[068]
L3
VSS[069]
L6
VSS[070]
L21
VSS[071]
L24
VSS[072]
M2
VSS[073]
M5
VSS[074]
M22
VSS[075]
M25
VSS[076]
N1
VSS[077]
N4
VSS[078]
N23
VSS[079]
N26
VSS[080]
VSS[081]P3VSS[162]
Penryn_1p0
Penryn_1p0
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[163]
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
.
.
C658
C658
0.1u
0.1u
C659
C659
0.1u
0.1u
Place these parts reference
to Intel demo board.
C591
C591
C27
C586
C586
10u/10V_8
10u/10V_8
C593
C593
10u/10V_8
10u/10V_8
C589
C589
10u/10V_8
10u/10V_8
C587
C587
10u/10V_8
10u/10V_8
C44
C44
+
+
330u/2.5V_7343
330u/2.5V_7343
C588
C588
10u/10V_8
10u/10V_8
C46
C46
10u/10V_8
10u/10V_8
C598
C598
10u/10V_8
10u/10V_8
C592
C592
10u/10V_8
10u/10V_8
C35
C35
10u/10V_8
10u/10V_8
C54
C54
10u/10V_8
10u/10V_8
C32
C32
10u/10V_8
10u/10V_8
C585
C585
10u/10V_8
10u/10V_8
VCC_CORE
+
+
C58
C58
330u/2.5V_7343
330u/2.5V_7343
10u/10V_8
10u/10V_8
C39
C39
10u/10V_8
10u/10V_8
C29
C29
10u/10V_8
10u/10V_8
C583
C583
10u/10V_8
10u/10V_8
C27
C573
C573
10u/10V_8
10u/10V_8
10u/10V_8
10u/10V_8
C597
C597
C594
C594
10u/10V_8
10u/10V_8
10u/10V_8
10u/10V_8
C574
C574
C61
C61
10u/10V_8
10u/10V_8
10u/10V_8
10u/10V_8
C596
C596
C584
C584
10u/10V_8
10u/10V_8
10u/10V_8
10u/10V_8
VCC_CORE Bulk CAPs place
to BOT of CPU centeral
Penryn CPU Power Status and max current table
POWER PLANE
VCC_CORE
VCC_CORE
VCC_CORE
VCC_CORE
VCCA
VCCP
VCCP
S0
S3
O
O
O
O
O
O
O
S4/S5
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Voltage
VID
VID
VID
VID
+1.5V
+1.05V
+1.05V
I(max)
47A
50A
TBD
67A
130mA
4.5A
2.5A
Standard Voltage CPU
SV Design Target
Extreme Edition CPU
EE Design Target
Before VCC Stable
After VCC Stable
C599
C599
10u/10V_8
10u/10V_8
C45
C45
10u/10V_8
10u/10V_8
C28
C28
10u/10V_8
10u/10V_8
C572
C572
10u/10V_8
10u/10V_8
Note
C38
C38
10u/10V_8
10u/10V_8
C31
C31
10u/10V_8
10u/10V_8
C37
C37
10u/10V_8
10u/10V_8
C590
C590
10u/10V_8
10u/10V_8
VCC_CORE
C59
C59
10u/10V_8
10u/10V_8
VCC_CORE
C26
C26
10u/10V_8
10u/10V_8
VCC_CORE
C595
C595
10u/10V_8
10u/10V_8
VCC_CORE
C571
C571
10u/10V_8
10u/10V_8
VCC_CORE VCC_CORE
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AC10
AB10
AB12
AB14
AB15
AB17
AB18
A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AB9
U29C
U29C
VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]
Penryn_1p0
Penryn_1p0
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
VCCA[01]
VCCA[02]
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VCCSENSE
VSSSENSE
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
CPU_G21
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
+VCCA_PROC
B26
C26
AD6
AF5
AE5
AF4
AE3
AF3
AE2
AF7
AE7
.
.
R51 0_4R51 0_4
H_VID0 31
H_VID1 31
H_VID2 31
H_VID3 31
H_VID4 31
H_VID5 31
H_VID6 31
VCC_CORE
R586
R586
100/F_6
100/F_6
R587
R587
100/F_6
100/F_6
Layout Note:
Route VCCSENSE and VSSSENSE traces at
27.4 Ohms with 50 mil spacing.
Place PU and PD within 1 inch of CPU.
(See Penryn EMTS Rev:1.0 Table7,8 for voltage and current)
(See Penryn EMTS Rev:1.0 Table-3 for VID table)
5
4
3
2
Layout Note:
Inside CPU center cavity in 2 rows
VCCP_CPU
C52
C52
0.1u/10V_4
0.1u/10V_4
C34
C34
0.1u/10V_4
0.1u/10V_4
VCCP_CPU VCCP
+
+
C78
C78
0.01u/16V_4
0.01u/16V_4
C72
C72
10u/10V_8
10u/10V_8
VCCSENSE 31
VSSSENSE 31
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
CPU(2/2) POWER
CPU(2/2) POWER
CPU(2/2) POWER
Date: Sheet
Date: Sheet
Date: Sheet
C41
C41
0.1u/10V_4
0.1u/10V_4
C57
C57
0.1u/10V_4
0.1u/10V_4
R564 0_1206R564 0_1206
C556
C556
270u/2V_7343
270u/2V_7343
R69 0_6R69 0_6
PROJECT : PB5/6
PROJECT : PB5/6
Quanta Computer Inc.
Quanta Computer Inc.
C48
C48
0.1u/10V_4
0.1u/10V_4
VCCP_CPU
C36
C36
0.1u/10V_4
0.1u/10V_4
VCCP Bulk CAP
close to Pin
VCC1.5
Place 0.01u
near pin-B26
1
of
of
of
435Friday, May 30, 2008
435Friday, May 30, 2008
435Friday, May 30, 2008
1A
1A
1A
5
4
3
2
1
http://hobi-elektronika.net
05
U26A
M11
N12
P13
N10
AD14
Y10
Y12
Y14
AA8
AA13
AA9
AA11
AD11
AD10
AD13
AE12
AE9
AA2
AD8
AA3
AD3
AD7
AE14
AF3
AC1
AE3
AC3
AE11
AE8
AG2
AD6
C12
E11
A11
B11
F2
G8
F8
E6
G2
H6
H2
F6
D4
H3
M9
J1
J2
J6
P2
L2
R2
N9
L6
M5
J3
N2
R1
N5
N6
N8
L7
M3
Y3
Y6
Y7
W2
Y9
C5
E3
U26A
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
H_SWING
H_RCOMP
H_CPURST#
H_CPUSLP#
H_AVREF
H_DVREF
CANTIGA_1p2
CANTIGA_1p2
H_ADSTB#_0
H_ADSTB#_1
HOST
HOST
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
H_ADS#
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
H_RS#_0
H_RS#_1
H_RS#_2
H_D#[0..15]3
D D
H_D#[16..31]3
VCCP
R538
R538
221/F_4
221/F_4
C C
R530
R530
100/F_4
100/F_4
H_SWING
C509
C509
0.1u/10V_4
0.1u/10V_4
0.3125*VCCP
W:10,S:20 , L<0.5"
H_D#[32..47]3
W:10,S:20 , L<0.5"
H_RCOMP
R128
R128
24.9/F_4
24.9/F_4
B B
VCCP
R539
R539
1K/F_4
1K/F_4
R534
2K/F_4
2K/F_4
A A
R522 0_4R522 0_4R534
2/3*VCCP
W:10,S:20 , L<0.5"
H_AVREF
H_DVREF
H_D#[48..63]3
H_CPURST#3
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_SWING
H_RCOMP
H_CPURST#
H_CPUSLP#
H_AVREF
H_DVREF
A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20
H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9
J8
L3
Y13
Y1
L10
M7
AA5
AE6
L9
M8
AA6
AE5
B15
K13
F13
B13
B14
B6
F12
C8
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
H_A#[3..16] 3
H_A#[17..35] 3
H_ADS# 3
H_ADSTB#0 3
H_ADSTB#1 3
H_BNR# 3
H_BPRI# 3
H_BREQ# 3
H_DEFER# 3
H_DBSY# 3
CLK_MCH_BCLK 2
CLK_MCH_BCLK# 2
H_DPWR# 3
H_DRDY# 3
H_HIT# 3
H_HITM# 3
H_LOCK# 3
H_TRDY# 3
H_DINV#[3..0] 3
H_DSTBN#[3..0] 3
H_DSTBP#[3..0] 3
H_REQ#[0..4] 3
H_RS#[2..0] 3H_CPUSLP#3
BOM Option Table
Reference
N/A
Description
N/A
PROJECT : PB5/6
PROJECT : PB5/6
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
NB (1/7) HOST
NB (1/7) HOST
NB (1/7) HOST
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
1
of
of
of
535Friday, May 30, 2008
535Friday, May 30, 2008
535Friday, May 30, 2008
1A
1A
1A
5
U26B
AM35
M36
N36
R33
T33
AH9
AH10
AH12
AH13
K12
T24
B31
M1
AY21
BG23
BF23
BH18
BF18
AL34
AK34
AN35
T25
R25
P25
P20
P24
C25
N24
M24
E21
C23
C24
N21
P21
T21
R20
M20
L21
H21
P29
R28
T28
R29
N33
P32
AT40
AT11
T20
R32
BG48
BF48
BD48
BC48
BH47
BG47
BE47
BH46
BF46
BG45
BH44
BH43
BH6
BH5
BG4
BH3
BF3
BH2
BG2
BE2
BG1
BF1
BD1
BC1
U26B
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD14
RSVD15
RSVD17
RSVD20
B2
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
ME_JTAG_TCK
ME_JTAG_TDI
ME_JTAG_TDO
ME_JTAG_TMS
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
PM_SYNC#
B7
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
F1
NC_25
CANTIGA_1p2
CANTIGA_1p2
CFG
CFG
PM
PM
MCH_RSVD1
T50T50
MCH_RSVD2
T53T53
MCH_RSVD3
T30T30
MCH_RSVD4
T58T58
MCH_RSVD5
T64T64
MCH_RSVD6
T62T62
MCH_RSVD7
T60T60
MCH_RSVD8
T61T61
MCH_RSVD9
T49T49
MCH_RSVD14
T57T57
D D
MCH_BSEL02
MCH_BSEL12
C C
PM_SYNC#14
ICH_DPRSTP#3,12,31
PM_EXTTS#017
PM_EXTTS#117
DELAY_VR_PWRGOOD3,14,31
PLT_RST#_NB13
PM_THRMTRIP#3,12
PM_DPRSLPVR14,31
NB Thermal trip pin
No use Thermal trip NB side can
NC.(NB has ODT)
PM_DPRSTP#
The Daisy chain topology should
be routed from ICH9M to IMVP ,
then to (G)MCH and CPU, in that
B B
order.
MCH_CFG_511
MCH_CFG_611
MCH_CFG_711
MCH_CFG_911
MCH_CFG_1011
MCH_CFG_1211
MCH_CFG_1311
MCH_CFG_1611
MCH_CFG_1911
MCH_CFG_2011
MCH_BSEL22
R99 0_4R99 0_4
R528 0_4R528 0_4
R147 0_4R147 0_4
R143 0_4R143 0_4
R203 0_4R203 0_4
R186 100_4R186 100_4
R141 *0_4R141 *0_4
R104 0_4R104 0_4
MCH_RSVD15
T37T37
MCH_RSVD17
T51T51
MCH_RSVD20
T72T72
MCH_RSVD21
T38T38
MCH_RSVD22
T74T74
MCH_RSVD23
T76T76
MCH_RSVD24
T156T156
MCH_RSVD25
T75T75
JTAG_TDI
T65T65
JTAG_TMS
T67T67
MCH_BSEL0
MCH_BSEL1
MCH_BSEL2
MCH_CFG_3
T48T48
MCH_CFG_4
T55T55
MCH_CFG_5
MCH_CFG_6
MCH_CFG_7
MCH_CFG_8
T40T40
MCH_CFG_9
MCH_CFG_10
MCH_CFG_11
T46T46
MCH_CFG_12
MCH_CFG_13
MCH_CFG_14
T59T59
MCH_CFG_15
T43T43
MCH_CFG_16
MCH_CFG_17
T41T41
MCH_CFG_18
T56T56
MCH_CFG_19
MCH_CFG_20
PM_SYNC#_R
ICH_DPRSTP#_R
PM_EXTTS#0_1_EC_RPM_EXTTS#0
TS#DIMM0_1_RPM_EXTTS#1
RST_IN#_MCH
THRMTRIP#_R
DPRSLPVR_R
TP_MCH_NC1
T153T153
TP_MCH_NC2
T146T146
TP_MCH_NC3
T143T143
TP_MCH_NC4
T139T139
TP_MCH_NC5
T152T152
TP_MCH_NC6
T80T80
TP_MCH_NC7
T154T154
TP_MCH_NC8
T145T145
TP_MCH_NC9
T78T78
TP_MCH_NC10
T151T151
TP_MCH_NC11
T144T144
TP_MCH_NC12
T150T150
TP_MCH_NC13
T149T149
TP_MCH_NC14
T142T142
TP_MCH_NC15
T138T138
TP_MCH_NC16
T148T148
TP_MCH_NC17
T73T73
TP_MCH_NC18
T155T155
TP_MCH_NC19
T77T77
TP_MCH_NC20
T157T157
TP_MCH_NC21
T141T141
TP_MCH_NC22
T137T137
TP_MCH_NC23
T147T147
TP_MCH_NC24
T140T140
TP_MCH_NC25
T44T44
4
http://hobi-elektronika.net
M_CLK_DDR0
AP24
SA_CK_0
M_CLK_DDR1
AT21
SA_CK_1
M_CLK_DDR3
AV24
SB_CK_0
M_CLK_DDR4
AU20
SB_CK_1
M_CLK_DDR#0
AR24
SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1
SA_CKE_0
SA_CKE_1
SB_CKE_0
RSVD
RSVD
SB_CKE_1
SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1
SA_ODT_0
SA_ODT_1
SB_ODT_0
SB_ODT_1
SM_RCOMP
SM_RCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST#
DPLL_REF_CLK
DDR CLK/ CONTROL/COMPENSATION
DDR CLK/ CONTROL/COMPENSATION
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
ME JTAG
ME JTAG
PEG_CLK
PEG_CLK#
CLK
CLK
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI
DMI
DMI_TXP_3
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4
GFX_VR_EN
GRAPHICS VID
GRAPHICS VID
CL_PWROK
CL_VREF
MEHDA
MEHDA
DDPC_CTRLCLK
DDPC_CTRLDATA
NC
NC
SDVO_CTRLCLK
SDVO_CTRLDATA
CLKREQ#
ICH_SYNC#
MISC
MISC
HDA_BCLK
HDA_RST#
HDA_SDO
HDA_SYNC
CL_CLK
CL_DATA
CL_RST#
TSATN#
HDA_SDI
M_CLK_DDR#1
AR21
M_CLK_DDR#3
AU24
M_CLK_DDR#4
AV20
M_CKE0
BC28
M_CKE1
AY28
M_CKE3
AY36
M_CKE4
BB36
M_CS#0
BA17
M_CS#1
AY16
M_CS#2
AV16
M_CS#3
AR13
M_ODT0
BD17
M_ODT1
AY17
M_ODT2
BF15
M_ODT3
AY13
M_RCOMP
BG22
M_RCOMP#
BH21
SM_RCOMP_VOH
BF28
SM_RCOMP_VOL
BH28
SM_VREF
AV42
SM_PWROK
AR36
SM_REXT
BF17
MCH_SM_DRAMRST#
BC36
DREFCLK
B38
DREFCLK#
A38
DREFSSCLK
E41
DREFSSCLK#
F41
CLK_PCIE_3GPLL
F43
CLK_PCIE_3GPLL#
E43
DMI_TXN0
AE41
DMI_TXN1
AE37
DMI_TXN2
AE47
DMI_TXN3
AH39
DMI_TXP0
AE40
DMI_TXP1
AE38
DMI_TXP2
AE48
DMI_TXP3
AH40
DMI_RXN0
AE35
DMI_RXN1
AE43
DMI_RXN2
AE46
DMI_RXN3
AH42
DMI_RXP0
AD35
DMI_RXP1
AE44
DMI_RXP2
AF46
DMI_RXP3
AH43
B33
B32
G33
F33
E33
C34
CL_CLK0
AH37
CL_DATA0
AH36
MPWROK
AN36
CL_RST#0
AJ35
AH34
DDPC_CTRLCLK
N28
DDPC_CTRLDATA
M28
SDVO_CTRLCLK
G36
SDVO_CTRLDATA
E36
CLK_MCH_OE#
K36
MCH_ICH_SYNC#
H36
TSATN#
B12
B28
B30
B29
C29
A28
T32T32
T34T34
T47T47
T42T42
11
T39T39
MCH_CLVREF_R
T29T29
T45T45
T162T162
T163T163
T164T164
T165T165
T166T166
M_CLK_DDR0 17
M_CLK_DDR1 17
M_CLK_DDR3 17
M_CLK_DDR4 17
M_CLK_DDR#0 17
M_CLK_DDR#1 17
M_CLK_DDR#3 17
M_CLK_DDR#4 17
M_CKE0 16,17
M_CKE1 16,17
M_CKE3 16,17
M_CKE4 16,17
M_CS#0 16,17
M_CS#1 16,17
M_CS#2 16,17
M_CS#3 16,17
M_ODT0 16,17
M_ODT1 16,17
M_ODT2 16,17
M_ODT3 16,17
SM_DRAMRST# only for
DDR3.(DDR2 NC).
T71T71
DREFCLK 2
DREFCLK# 2
DREFSSCLK 2
DREFSSCLK# 2
CLK_PCIE_3GPLL 2
CLK_PCIE_3GPLL# 2
DMI_TXN[3:0] 13
DMI_TXP[3:0] 13
DMI_RXN[3:0] 13
DMI_RXP[3:0] 13
CL_CLK0 14
CL_DATA0 14
MPWROK 14
CL_RST#0 14
DDPC_CTRL for HDMI port C
SDVO_CTRL for HDMI port B
DDPC_CTRLDATA 11
SDVO_CTRLDATA 11
CLK_MCH_OE# 2
MCH_ICH_SYNC# 14
3
CRT I/F
INT_CRT_DDCCLK18
INT_CRT_DDCDAT18
INT_HSYNC18
INT_VSYNC18
HSYNC/VSYNC serial R place close to NB
NOTE:
If (G)MCH's HD Audio signals are connected to ICH9M for
iHDMI, VCCHDA and VCCSUSHDA on ICH9M should be
only on 1.5V. These power pins on ICH9M can be supplied
with 3.3V if and only if (G)MCH's HDA is not connected to
ICH9M. Consequently, only 1.5V audio/modem codecs can
be used on the platform.
BOM Option Table
LVDS I/F
INT_LVDS_PWM19
INT_LVDS_BLON19
INT_LVDS_EDIDCLK19
INT_LVDS_EDIDDATA11,19
INT_LVDS_DIGON19
INT_TXLCLKOUT-19
INT_TXLCLKOUT+19
INT_TXUCLKOUT-19
INT_TXUCLKOUT+19
INT_TXLOUT0-19
INT_TXLOUT1-19
INT_TXLOUT2-19
INT_TXLOUT0+19
INT_TXLOUT1+19
INT_TXLOUT2+19
INT_TXUOUT0-19
INT_TXUOUT1-19
INT_TXUOUT2-19
INT_TXUOUT0+19
INT_TXUOUT1+19
INT_TXUOUT2+19
TV IF (Disable)
Reference
Description
INT VGAIV@
EXT VGAEV@
IHM@ INT HDMI
EV_IV@ EV&IV diff. value
T31T31
T35T35
T33T33
T52T52
T54T54
R140 IV@30.1/F_4R140 IV@30.1/F_4
R148 IV@30.1/F_4R148 IV@30.1/F_4
For IV @ Connect to 30.1ohm
For EV@ NC
INT_LVDS_PWM
INT_LVDS_BLON
L_CTRL_CLK
L_CTRL_DATA
INT_LVDS_EDIDCLK
INT_LVDS_EDIDDATA
INT_LVDS_DIGON
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
INT_TXLCLKOUTINT_TXLCLKOUT+
INT_TXUCLKOUTINT_TXUCLKOUT+
INT_TXLOUT0INT_TXLOUT1INT_TXLOUT2INT_TXLOUT3-
INT_TXLOUT0+
INT_TXLOUT1+
INT_TXLOUT2+
INT_TXLOUT3+
INT_TXUOUT0INT_TXUOUT1INT_TXUOUT2INT_TXUOUT3-
INT_TXUOUT0+
INT_TXUOUT1+
INT_TXUOUT2+
INT_TXUOUT3+
INT_TV_COMP
INT_TV_Y/G
INT_TV_C/R
INT_TV_RNT
TV_DCONSEL_0
TV_DCONSEL_1
INTB
INTG
INTR
CRT_IRTN
INT_CRT_DDCCLK
INT_CRT_DDCDAT
HSYNC_GINT_HSYNC
CRTIREF
VSYNC_GINT_VSYNC
L32
G32
M32
M33
K33
J33
M29
C44
B43
E37
E38
C41
C40
B37
A37
H47
E46
G40
A40
H48
D45
F40
B40
A41
H38
G37
J37
B42
G38
F37
K37
F25
H25
K25
H24
C31
E32
E28
G28
J28
G29
H32
J32
J29
E29
L29
U26C
U26C
L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK
LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA#_3
LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
LVDSA_DATA_3
LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA#_3
LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
LVDSB_DATA_3
TVA_DAC
TVB_DAC
TVC_DAC
TV_RTN
TV_DCONSEL_0
TV_DCONSEL_1
CRT_BLUE
CRT_GREEN
CRT_RED
CRT_IRTN
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC
CANTIGA_1p2
CANTIGA_1p2
2
1
06
L<0.5" , If PCIE not support
still connect to +VCC_PEG
EXP_A_COMPX
T37
PEG_COMPI
T36
PEG_COMPO
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
LVDS
LVDS
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
TV
TV
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PCI-EXPRESS GRAPHICS
PCI-EXPRESS GRAPHICS
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
VGA
VGA
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
H44
J46
L44
L40
N41
P48
N44
T43
U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39
H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40
J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46
J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46
PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15
PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15
C_PEG_TXN0
C_PEG_TXN1
C_PEG_TXN2
C_PEG_TXN3
C_PEG_TXN4
C_PEG_TXN5
C_PEG_TXN6
C_PEG_TXN7
C_PEG_TXN8
C_PEG_TXN9
C_PEG_TXN10
C_PEG_TXN11
C_PEG_TXN12
C_PEG_TXN13
C_PEG_TXN14
C_PEG_TXN15
C_PEG_TXP0
C_PEG_TXP1
C_PEG_TXP2
C_PEG_TXP3
C_PEG_TXP4
C_PEG_TXP5
C_PEG_TXP6
C_PEG_TXP7
C_PEG_TXP8
C_PEG_TXP9
C_PEG_TXP10
C_PEG_TXP11
C_PEG_TXP12
C_PEG_TXP13
C_PEG_TXP14
C_PEG_TXP15
Close U3030
INTR
INTG
INTB
L48 0@IVL48 0@IV
L49 0@IVL49 0@IV
L47 0@IVL47 0@IV
C552
C549
C549
C550
C550
C551
C551
*5.6P
*5.6P
*5.6P
*5.6P
*5.6P
*5.6P
C552
*5.6P
*5.6P
R153 49.9/F_4R153 49.9/F_4
C497 EV@0.1u/10V_4C497 EV@0.1u/10V_4
C121 EV@0.1u/10V_4C121 EV@0.1u/10V_4
C495 EV@0.1u/10V_4C495 EV@0.1u/10V_4
C137 EV@0.1u/10V_4C137 EV@0.1u/10V_4
C490 EV@0.1u/10V_4C490 EV@0.1u/10V_4
C148 EV@0.1u/10V_4C148 EV@0.1u/10V_4
C487 EV@0.1u/10V_4C487 EV@0.1u/10V_4
C158 EV@0.1u/10V_4C158 EV@0.1u/10V_4
C484 EV@0.1u/10V_4C484 EV@0.1u/10V_4
C164 EV@0.1u/10V_4C164 EV@0.1u/10V_4
C481 EV@0.1u/10V_4C481 EV@0.1u/10V_4
C170 EV@0.1u/10V_4C170 EV@0.1u/10V_4
C476 EV@0.1u/10V_4C476 EV@0.1u/10V_4
C174 EV@0.1u/10V_4C174 EV@0.1u/10V_4
C468 EV@0.1u/10V_4C468 EV@0.1u/10V_4
C179 EV@0.1u/10V_4C179 EV@0.1u/10V_4
C498 EV@0.1u/10V_4C498 EV@0.1u/10V_4
C120 EV@0.1u/10V_4C120 EV@0.1u/10V_4
C493 EV@0.1u/10V_4C493 EV@0.1u/10V_4
C132 EV@0.1u/10V_4C132 EV@0.1u/10V_4
C491 EV@0.1u/10V_4C491 EV@0.1u/10V_4
C145 EV@0.1u/10V_4C145 EV@0.1u/10V_4
C489 EV@0.1u/10V_4C489 EV@0.1u/10V_4
C153 EV@0.1u/10V_4C153 EV@0.1u/10V_4
C485 EV@0.1u/10V_4C485 EV@0.1u/10V_4
C161 EV@0.1u/10V_4C161 EV@0.1u/10V_4
C483 EV@0.1u/10V_4C483 EV@0.1u/10V_4
C168 EV@0.1u/10V_4C168 EV@0.1u/10V_4
C480 EV@0.1u/10V_4C480 EV@0.1u/10V_4
C173 EV@0.1u/10V_4C173 EV@0.1u/10V_4
C469 EV@0.1u/10V_4C469 EV@0.1u/10V_4
C177 EV@0.1u/10V_4C177 EV@0.1u/10V_4
C548
C548
C547
C547
*5.6P
*5.6P
*5.6P
*5.6P
+1.05V_VCC_PEG
PEG_RXN[15:0] 20
PEG_RXP[15:0] 20
INT_CRT_RED 18
INT_CRT_GRN 18
INT_CRT_BLU 18
PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15
PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15
PEG_TXN[15:0] 20
PEG_TXP[15:0] 20
Check list note : CL_REF=0.35V
MCH_CLVREF_R SM_VREF
A A
+1.8VSUS_GMCH +1.8VSUS_GMCH
R492
R492
80.6/F_4
80.6/F_4
R497
R497
*20/F_4
*20/F_4
VCCP
C136
C136
0.1u/10V_4
0.1u/10V_4
M_RCOMP#M_RCOMP SM_RCOMP_VOL
5
SM_VREF.Default use voltage divider for poor layout cause +SMDDR_VREF not
meet spec.And Intel circuit PU/PD is 1K,But Check list PU/PD is 10K.
R166
R166
1K/F_4
1K/F_4
R170
R170
511/F_6
511/F_6
R491
R491
*20/F_4
*20/F_4
R496
R496
80.6/F_4
80.6/F_4
+1.8VSUS_GMCH
R202 0_6R202 0_6
R189 *10K/F_4R189 *10K/F_4
R195
R195
*10K/F_4
*10K/F_4
R495 1K/F_4R495 1K/F_4
3.01K/F_4
3.01K/F_4
R500
R500
R488
R488
1K/F_4
1K/F_4
SMDDR_VREF
+1.8VSUS_GMCH
SM_RCOMP_VOH
C465
C465
0.01u/16V_4
0.01u/16V_4
C461
C461
0.01u/16V_4
0.01u/16V_4
C464
C464
2.2u/6.3V_6
2.2u/6.3V_6
C458
C458
2.2u/6.3V_6
2.2u/6.3V_6
<Checklist ver0.8>
If TSATN# is not used, then it must be terminated
with a 56-ȍ pull-up resistor to VCCP.
TSATN#
CLK_MCH_OE#
PM_EXTTS#0
PM_EXTTS#1
SM_REXT
R199 499/F_4R199 499/F_4
SM_PWROK only for DDR3.(DDR2 PD only)
R185
R185
*12K/F_4
SM_PWROK
4
*12K/F_4
R184
R184
10K/F_6
10K/F_6
R52956_4 R52956_4
R10210K_4 R10210K_4
R15210K_4 R15210K_4
R14910K_4 R14910K_4
HWPG_1.8V 28,33
IV&EV Dis/Enable LVDS setting(See DG 1.0 P190 Table 103)
VCCP
VCC3
VCC3
R122 IV@0_4R122 IV@0_4
R120 IV@2.37K/F_4R120 IV@2.37K/F_4
R79 IV@10K_4R79 IV@10K_4
R80 IV@10K_4R80 IV@10K_4
LVDS_VREFH
LVDS_VREFL
LVDS_IBG
L_CTRL_CLK
L_CTRL_DATA
For IV @ 0ohm
For EV@ NC
For IV @ 2.37K/F
For EV@ NC
For IV @ 2.37K 10K
For EV@ NC
IV&EV Dis/Enable CRT setting(See DG 1.0 P190 Table 103) Dis TV/En CRT( See DG1.0 P208 Table 118)
R130 *EV@0_4R130 *EV@0_4
R136 *EV@0_4R136 *EV@0_4
R137 *EV@0_4R137 *EV@0_4
R145 *EV@0_4R145 *EV@0_4
R129 EV_IV@150/F_4R129 EV_IV@150/F_4
R131 EV_IV@150/F_4R131 EV_IV@150/F_4
R135 EV_IV@150/F_4R135 EV_IV@150/F_4
R119 EV_IV@1K/F_4R119 EV_IV@1K/F_4
3
INT_CRT_DDCCLK
INT_CRT_DDCDAT
HSYNC_G
VSYNC_G
INTB
INTG
INTR
CRTIREF
Layout Note :See DG1.0 P180
For IV @ NC
For EV@ 0ohm to GND or NC
For IV @ NC
For EV@ 0ohm to GND or NC
For IV @ Connect to 150ohm/F
For EV@ Connect to 0ohm GND
For IV @ Connect to 1.02K/F
For EV@ Connect to 0ohm GND
IV&EV Dis/Enable PLL setting(See DG 1.0 P190 Table 103)
R125 EV_IV@75_4R125 EV_IV@75_4
R132 EV_IV@75_4R132 EV_IV@75_4
R139 EV_IV@75_4R139 EV_IV@75_4
R124 0_4R124 0_4
R121 0_4R121 0_4
DREFCLK
DREFCLK#
DREFSSCLK
DREFSSCLK#
2
INT_TV_COMP
INT_TV_Y/G
INT_TV_C/R
TV_DCONSEL_0
TV_DCONSEL_1
R535 EV@0_4R535 EV@0_4
R523 EV@0_4R523 EV@0_4
R126 EV@0_4R126 EV@0_4
R133 EV@0_4R133 EV@0_4
For IV @ 75ohm to GND
For EV@ 0ohm to GND
For IV @ 0ohm to GND
For EV@ 0ohm to GND
For IV @ NC
For EV@ 0ohm to GND
PROJECT : PB5/6
PROJECT : PB5/6
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
NB(2/7)
NB(2/7)
NB(2/7)
Date: Sheet
Date: Sheet
Date: Sheet
Quanta Computer Inc.
of
of
of
635Wednesday, June 04, 2008
635Wednesday, June 04, 2008
1
635Wednesday, June 04, 2008
1A
1A
1A
5
D D
U26D
M_A_DQ[0..7]17
M_A_DQ[8..15]17
M_A_DQ[16..23]17
C C
M_A_DQ[24..31]17
M_A_DQ[32..39]17
M_A_DQ[40..47]17
M_A_DQ[48..55]17
B B
M_A_DQ[56..63]17
M_A_DQ0 M_A_BS#0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
AJ38
AJ41
AN38
AM38
AJ36
AJ40
AM44
AM42
AN43
AN44
AU40
AT38
AN41
AN39
AU44
AU42
AV39
AY44
BA40
BD43
AV41
AY43
BB41
BC40
AY37
BD38
AV37
AT36
AY38
BB38
AV36
AW36
BD13
AU11
BC11
BA12
AU13
AV13
BD12
BC12
AU10
BA11
AN10
AM11
AN12
AM13
AJ11
AJ12
BB9
BA9
AV9
BD9
AY8
BA6
AV5
AV7
AT9
AN8
AU5
AU6
AT5
AM5
AJ9
AJ8
U26D
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
CANTIGA_1p2
CANTIGA_1p2
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
SA_BS_0
SA_BS_1
SA_BS_2
SA_RAS#
SA_CAS#
SA_WE#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
4
http://hobi-elektronika.net
BD21
BG18
AT25
BB20
BD20
AY20
AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5
AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7
AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8
BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25
M_A_BS#1
M_A_BS#2
M_A_RAS#
M_A_CAS#
M_A_WE#
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_BS#0 16,17
M_A_BS#1 16,17
M_A_BS#2 16,17
M_A_RAS# 16,17
M_A_CAS# 16,17
M_A_WE# 16,17
M_A_DM[0..7] 17
M_A_DQS[0..7] 17
M_A_DQS#[0..7] 17
M_A_A[0..14] 16,17
3
2
1
BOM Option Table
Reference
N/A
U26E
M_B_DQ[0..7]17
M_B_DQ[8..15]17
M_B_DQ[16..23]17
M_B_DQ[24..31]17
M_B_DQ[32..39]17
M_B_DQ[40..47]17
M_B_DQ[48..55]17
M_B_DQ[56..63]17
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
AK47
AH46
AP47
AP46
AJ46
AJ48
AM48
AP48
AU47
AU46
BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44
BG43
BF43
BE45
BC41
BF40
BF41
BG38
BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11
BH12
BF11
BG8
BF8
BG7
BC5
BC6
AY3
AY1
BF6
BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1
AL1
AL2
AJ1
AH1
AM2
AM3
AH3
AJ3
U26E
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
CANTIGA_1p2
CANTIGA_1p2
SB_BS_0
SB_BS_1
SB_BS_2
SB_RAS#
SB_CAS#
SB_WE#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
BC16
BB17
BB33
AU17
BG16
BF14
AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2
AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6
AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5
AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33
Description
N/A
M_B_BS#0
M_B_BS#1
M_B_BS#2
M_B_RAS#
M_B_CAS#
M_B_WE#
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_BS#0 16,17
M_B_BS#1 16,17
M_B_BS#2 16,17
M_B_RAS# 16,17
M_B_CAS# 16,17
M_B_WE# 16,17
M_B_DM[0..7] 17
M_B_DQS[0..7] 17
M_B_DQS#[0..7] 17
M_B_A[0..14] 16,17
07
A A
PROJECT : PB5/6
PROJECT : PB5/6
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
DDRII
DDRII
DDRII
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
Quanta Computer Inc.
of
of
of
735Friday, May 30, 2008
735Friday, May 30, 2008
735Friday, May 30, 2008
1
1A
1A
1A
5
4
3
2
1
BOM Option Table
http://hobi-elektronika.net
Reference
IV@
Description
INT VGA
08
EXT VGAEV@
1.8VSUS+1.8VSUS_GMCH
Close to GMCH
+
+
C91
C91
270u/2V_7343
270u/2V_7343
Close to GMCH
C133
C111
C111
IV@0.1u/10V_4
IV@0.1u/10V_4
I(max)
2178mA+1.05V
C133
IV@0.1u/10V_4
IV@0.1u/10V_4
Note
2899mA
Graphics Core
8700mA
3A
1mA+1.8VSUSVCC_SM(Standby) Self Refresh during S3
C160
C160
1u/16V_6
1u/16V_6
See Page 9 EV&IV table
R163
R163
R167
R167
EV@0_6
EV@0_6
EV@0_6
EV@0_6
Place close to the GMCH
and different location
R172 IV@0_0402R172 IV@0_0402
R154 IV@0_0402R154 IV@0_0402
R164 IV@0_0402R164 IV@0_0402
R169 IV@0_0402R169 IV@0_0402
R155 IV@0_1206R155 IV@0_1206
R519 IV@0_1206R519 IV@0_1206
R165
R165
EV@0_6
EV@0_6
DR8
DR9
VCCP
W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16
AV44
BA37
AM40
AV21
AY5
AM10
BB13
+VGFX_CORE_INT+1.8VSUS_GMCH
1.8V Internal connect to power
C169
C169
0.1u/10V_4
0.1u/10V_4
C463
C463
10u/6.3V_8
10u/6.3V_8
VCCP
C122
C122
0.1u/10V_4
0.1u/10V_4
+VGFX_CORE_INT
C128
C128
IV@0.47u/6.3V_4
IV@0.47u/6.3V_4
+VGFX_CORE_INT
+
+
C92
C92
IV@330u/2.5V_7343
IV@330u/2.5V_7343
NB Power Status and max current table(1/3)
POWER PLANE
VCC(EXT_VGA)
VCC(INT_VGA)
VCC_AXG
VCC_SM(800) (DDRII-667) 2.6A
C462
C462
10u/6.3V_8
10u/6.3V_8
C135
C135
0.22u/6.3V_4
0.22u/6.3V_4
C112
C112
IV@1u/16V_6
IV@1u/16V_6
+
+
C85
C85
IV@330u/2.5V_7343
IV@330u/2.5V_7343
S0
O
O
O
O
O XO
S3
X
X
X
O
(See NB EDS Rev:1.0 Section 10.1 for max current)
(See NB EDS Rev:1.0 Section 12.2 for DC voltage)
C165
C150
C150
0.1u/10V_4
0.1u/10V_4
C165
0.22u/6.3V_4
0.22u/6.3V_4
C162
C162
0.22u/6.3V_4
0.22u/6.3V_4
C140
C140
0.47u/10V_6
0.47u/10V_6
C163
C163
0.1u/10V_4
0.1u/10V_4
C131
C131
0.22u/6.3V_4
0.22u/6.3V_4
C124
C124
IV@10u/10V_8
IV@10u/10V_8
U26G
AP33
AN33
BH32
BG32
BF32
BD32
BC32
BB32
BA32
AY32
AW32
AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31
BF31
BG30
BH29
BG29
BF29
BD29
BC29
BB29
BA29
AY29
AW29
AV29
AU29
AT29
AR29
AP29
BA36
BB24
BD16
BB21
AW16
AW13
AT13
AE25
AB25
AA25
AE24
AC24
AA24
AE23
AC23
AB23
AA23
AJ21
AG21
AE21
AC21
AA21
AH20
AF20
AE20
AC20
AB20
AA20
AM15
AL15
AE15
AJ15
AH15
AG15
AF15
AB15
AA15
AN14
AM14
AJ14
AH14
Y26
Y24
Y21
T17
T16
Y15
V15
U15
U14
T14
U26G
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36/NC
VCC_SM_37/NC
VCC_SM_38/NC
VCC_SM_39/NC
VCC_SM_40/NC
VCC_SM_41/NC
VCC_SM_42/NC
VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC_AXG_35
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_42
VCC_AXG_SENSE
VSS_AXG_SENSE
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
POWER
POWER
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC SMVCC GFX
VCC SMVCC GFX
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC GFX NCTF
VCC GFX NCTF
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
VCC SM LF
VCC SM LF
U26F
AG34
AC34
AB34
AA34
AM33
AK33
AJ33
AG33
AF33
AE33
AC33
AA33
AH28
AF28
AC28
AA28
AJ26
AG26
AE26
AC26
AH25
AG25
AF25
AG24
AJ23
AH23
AF23
Y34
V34
U34
Y33
W33
V33
U33
T32
U26F
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
CANTIGA_1p2
CANTIGA_1p2
VCC CORE
VCC CORE
POWER
POWER
VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC NCTF
VCC NCTF
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23
+VGFX_CORE_INT
VCCP
R174 IV@10/F_6R174 IV@10/F_6
R173 IV@10/F_6R173 IV@10/F_6
+VGFX_CORE_INT
R156
R156
VCCP
0_4
0_4
D D
C C
B B
R208 0_1206R208 0_1206
+
+
C156
C156
330u/2.5V_7343
330u/2.5V_7343
C127
C127
22u/6.3V_8
22u/6.3V_8
C143
C143
IV@10u/6.3V_8
IV@10u/6.3V_8
Close to GMCH
S4/S5
Voltage
X
X
+1.05V
X
+1.05V
X
+1.8VSUS
Close to each pins
C167
C167
1u/16V_6
1u/16V_6
1. Route VCC_AXG_SENSE and VSS_AXG_SENSE differentially
A A
5
2. VCC_AXG_SENSE PU to +VGFX_CORE_INT with 10ohm
and VSS_AXG_SENSE PD with 10ohm for Intel suggest
CANTIGA_1p2
CANTIGA_1p2
PROJECT : PB5/6
PROJECT : PB5/6
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
NB(4/7) VCC ,NCTF
NB(4/7) VCC ,NCTF
NB(4/7) VCC ,NCTF
Date: Sheet
Date: Sheet
4
3
2
Date: Sheet
Quanta Computer Inc.
835Friday, March 21, 2008
835Friday, March 21, 2008
835Friday, March 21, 2008
of
of
1
of
1A
1A
1A
5
4
3
2
1
http://hobi-elektronika.net
+3V_A_CRT_DAC
R123
R123
EV@0_4
EV@0_4
DR10DR11
R514 0_8R514 0_8
C488
C488
0.1u/10V_4
0.1u/10V_4
+1.05VM_MCH_PLL2
+1.05VM_PEGPLL
+3V_A_CRT_DAC
+3V_A_DAC_BG
+1.05VM_DPLLA
+1.05VM_DPLLB
+1.05VM_HPLL
+1.05VM_MPLL
+1.8VSUS_TXLVDS
+1.5V_VCCA_PEG_BG
+1.05VM_PEGPLL
+1.05VM_A_SM
+1.05VM_A_SM_CK
+3V_TV_DAC
+1.5V_VCC_HDA
+1.5V_TVDAC
+1.5V_QDAC
+1.8VSUS_DLVDS
AD48
AA48
AR20
AP20
AN20
AR17
AP17
AN17
AT16
AR16
AP16
AP28
AN28
AP25
AN25
AN24
AM28
AM26
AM25
AL25
AM24
AL24
AM23
AL23
AA47
B27
A26
A25
B25
F47
L48
AD1
AE1
J48
J47
B24
A24
A32
M25
L28
AF1
M38
L37
U26H
U26H
CANTIGA_1p2
CANTIGA_1p2
VCCA_CRT_DAC_1
VCCA_CRT_DAC_2
VCCA_DAC_BG
VSSA_DAC_BG
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL
VCCA_LVDS
VSSA_LVDS
VCCA_PEG_BG
VCCA_PEG_PLL
VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_6
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
VCCA_SM_CK_1
VCCA_SM_CK_2
VCCA_SM_CK_3
VCCA_SM_CK_4
VCCA_SM_CK_5
VCCA_SM_CK_NCTF_1
VCCA_SM_CK_NCTF_2
VCCA_SM_CK_NCTF_3
VCCA_SM_CK_NCTF_4
VCCA_SM_CK_NCTF_5
VCCA_SM_CK_NCTF_6
VCCA_SM_CK_NCTF_7
VCCA_SM_CK_NCTF_8
VCCA_TV_DAC_1
VCCA_TV_DAC_2
VCC_HDA
VCCD_TVDAC
VCCD_QDAC
VCCD_HPLL
VCCD_PEG_PLL
VCCD_LVDS_1
VCCD_LVDS_2
CRTPLLA PEGA SM
CRTPLLA PEGA SM
A LVDS
A LVDS
POWER
POWER
A CK
A CK
TV
TV
HDA
HDA
D TV/CRT
D TV/CRT
LVDS
LVDS
AXF
AXF
VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4
SM CK
SM CK
VCC_TX_LVDS
HV
HV
PEG
PEG
DMI
DMI
VCC_AXF_1
VCC_AXF_2
VCC_AXF_3
VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5
VTTLF
VTTLF
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT
VTT
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25
VCC_HV_1
VCC_HV_2
VCC_HV_3
VCC_DMI_1
VCC_DMI_2
VCC_DMI_3
VCC_DMI_4
VTTLF1
VTTLF2
VTTLF3
U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1
B22
B21
A21
BF21
BH20
BG20
BF20
K47
C35
B35
A35
V48
U48
V47
U47
U46
AH48
AF48
AH47
AG47
A8
L1
AB2
C123
C123
0.47u/6.3V_4
0.47u/6.3V_4
+1.05VM_AXF
+1.8VSUS_VCC_SM_CK
+1.8VSUS_TXLVDS
+3V_VCC_HV
+1.05V_VCC_PEG
+1.05V_VCC_DMI
C119
C119
C107
C107
0.47u/6.3V_4
0.47u/6.3V_4
0.47u/6.3V_4
0.47u/6.3V_4
C500
C501
C501
2.2u/6.3V_6
2.2u/6.3V_6
C500
4.7u/10V_6
4.7u/10V_6
+1.05VM_AXF
+1.8VSUS_VCC_SM_CK
C459
C459
0.1u/10V_4
0.1u/10V_4
+1.8VSUS_TXLVDS
R548
R548
EV@0_4
EV@0_4
+3V_VCC_HV
C525
C525
0.1u/10V_4
0.1u/10V_4
+1.05V_VCC_PEG
C109
C109
4.7u/10V_6
4.7u/10V_6
+1.05V_VCC_DMI
C102
C102
0.47u/6.3V_4
0.47u/6.3V_4
C502
C502
4.7u/10V_6
4.7u/10V_6
C513
C513
1u/6.3V_4
1u/6.3V_4
C522
C522
IV@1000p/50V_4
IV@1000p/50V_4
DR3
DR4
R5470_6 R5470_6
C108
C108
10u/6.3V_8
10u/6.3V_8
C467
C467
*10u/10V_8
*10u/10V_8
+
+
IV@0.1u/10V_4
IV@0.1u/10V_4
+3V_A_TV_CRT
C539
C539
C517
C517
IV@0.1u/10V_4
IV@0.1u/10V_4
C510
C510
IV@0.01u/16V_4
IV@0.01u/16V_4
R559
R559
EV@0_4
EV@0_4
VCC3
D D
VCCP
L44 IV@BLM18PG181SN1D_6L44 IV@BLM18PG181SN1D_6
C538
C538
IV@10u/10V_8
IV@10u/10V_8
L46 IV@0_8L46 IV@0_8
C546
C546
IV@220u/2.5V_7343
IV@220u/2.5V_7343
R536
R536
EV@0_4
EV@0_4
DR1
DR7
+3V_A_DAC_BG
VCCP
+3V_A_TV_CRT
L13 IV@0_8L13 IV@0_8
C86
C86
IV@220u/2.5V_7343
IV@220u/2.5V_7343
+
+
IV@0.1u/10V_4
IV@0.1u/10V_4
C529
C529
IV@0.1u/10V_4
IV@0.1u/10V_4
C99
C99
C533
C533
IV@0.01u/16V_4
IV@0.01u/16V_4
+1.05VM_DPLLA
+1.05VM_DPLLB
+1.05VM_MCH_PLL2
R188 0_6R188 0_6
VCCP
R194 0_6R194 0_6
VCCP
C C
R175 0_6R175 0_6
VCCP
R545 IV@0_6R545 IV@0_6
VCC3
R541 IHM@0_6R541 IHM@0_6
VCC1.5
B B
R546 0_6R546 0_6
VCC1.5
VCC1.5
C172
C172
+
+
100u/10V_7343
100u/10V_7343
C157
C157
*2.2u/6.3V_6
*2.2u/6.3V_6
C523
C523
IV@0.1u/10V_4
IV@0.1u/10V_4
C520
C520
IHM@0.1u/10V_4
IHM@0.1u/10V_4
C518
C518
0.1u/10V_4
0.1u/10V_4
L43 IV@BLM18PG181SN1D_6L43 IV@BLM18PG181SN1D_6
C536
C536
IV@10u/6.3V_8
IV@10u/6.3V_8
R168 0_6R168 0_6
4.7u/10V_6
4.7u/10V_6
L18 0_6L18 0_6
R187 *0.5/F_6R187 *0.5/F_6
0.1u/10V_4
0.1u/10V_4
C154
C154
C155
C155
*10u/6.3V_8
*10u/6.3V_8
10u/6.3V_8
10u/6.3V_8
C144
C144
C149
C149
0.1u/10V_4
0.1u/10V_4
10u/6.3V_8
10u/6.3V_8
C516
C516
IV@0.01u/16V_4
IV@0.01u/16V_4
FOR iHDMI HDA I/F only
C524
C524
0.01u/16V_4
0.01u/16V_4
C519
C519
IV@0.1u/10V_4
IV@0.1u/10V_4
C125
C125
C129
C129
0.1u/10V_4
0.1u/10V_4
C134
C134
C151
C151
4.7u/10V_6
4.7u/10V_6
C511
C511
IV@0.01u/16V_4
IV@0.01u/16V_4
C142
C142
*22u/6.3V_8
*22u/6.3V_8
C152
C152
1u/6.3V_4
1u/6.3V_4
+1.05VM_HPLL
+1.05VM_MPLL
+1.05VM_MPLL_RC
IV@1000p/50V_4
IV@1000p/50V_4
+1.05VM_A_SM
+1.05VM_A_SM_CK
+3V_TV_DAC
R525
R525
EV@0_4
EV@0_4
DR5
+1.5V_VCC_HDA
R527
R527
IF iHDMI not used,HDA
connect ot GND(DG1.0 P277)
EV@0_4
EV@0_4
DR12
+1.5V_TVDAC
+1.5V_QDAC
R537
R537
EV@0_4
EV@0_4
C530
C530
VCC1.5
C130
C130
0.1u/10V_4
0.1u/10V_4
BOM Option Table
VCCP
+
+
C504
C504
270u/2V_7343
270u/2V_7343
L42 0.1uh_6L42 0.1uh_6
C531
C531
*10u/10V_8
*10u/10V_8
L37 1uh_8L37 1uh_8
+1.8VSUS_SMCK_RC
R4981/F_4 R4981/F_4
C466
C466
10u/10V_8
10u/10V_8
L45 IV@0.1uh_6L45 IV@0.1uh_6
C514
C514
IV@10u/6.3V_8
IV@10u/6.3V_8
R551 10_4R551 10_4
+1.05V_VCC_PEG
R518 0_8R518 0_8
+
+
C503
C503
220u/2.5V_7343
220u/2.5V_7343
R158 0_8R158 0_8
C471
C471
0.1u/10V_4
0.1u/10V_4
L38
L38
C478
C478
+
+
*220u/2.5V_7343
*220u/2.5V_7343
Reference
IHM@ INT HDMI
VCCP
+1.8VSUS_GMCH
VCCP
21
+1.05V_SD
VCCP
+1.05V_VCC_PEG
*91nh_32X25
*91nh_32X25
Del it to save space?
Description
INT VGAIV@
EXT VGAEV@
1.8VSUS
D30
D30
BAT54
BAT54
VCC3
VCCP
09
DR6
NB Power Status and max current table(2/3)(NB left side)
VCCP
A A
1.8VSUS
L40 BLM18PG181SN1D_6L40 BLM18PG181SN1D_6
R552 IV@0_6R552 IV@0_6
R515 1/F_4R515 1/F_4
5
C494
C494
0.1u/10V_4
0.1u/10V_4
C499
C499
10u/10V_8
10u/10V_8
C534
C534
IV@1u/6.3V_4
IV@1u/6.3V_4
C496
C496
0.1u/10V_4
0.1u/10V_4
+1.05VM_PEGPLL
+1.05VM_PEGPLL_RC
+1.8VSUS_DLVDS
R540
R540
EV@0_4
EV@0_4
DR2
4
POWER PLANE
VCCA_CRT_DAC
VCCA_DAC_BG
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL
VCCA_LVDS
VCCA_PEG_BG 414uA+1.5V
VCCA_PEG_PLL 50mA+1.05V
VCCA_SM(DDRII-800)
VCCA_SM_CK(800)
VCCA_TV_DAC
VCC_HDA
VCCD_TVDAC
VCCD_QDAC
VCCD_HPLL
VCCD_PEG_PLL
VCCD_LVDS
S0
S3
S4/S5
X
X
O
O
X
X
X
O
X
O
X
X
O
X
X
O
X
X
X
O
O
XXO
OXX
X
X
O
X
X
O
X
X
X
O
X
O
X
X
O
X
X
X
X
O
O
XXX
O
O
Voltage
+3.3V
+3.3V
+1.05V
+1.05V
+1.05V
139.2mA
+1.05V
+1.8VSUS
+1.05V
+1.05V 157mA
+1.8VSUS 60mA
I(max)
73mA
5mA
64.8mA
64.8mA
24mA
13.2mA
720mA+1.05V
26mA
79mA+3.3V
50mA+1.5V
35mA+1.5V
125uA+1.5V
50mA+1.05V
3
Note
(DDRII-667) 480mA
(DDRII-667) 24mAO
EXT&INT VGA Power Plane Option table
POWER PLANE
VCCA_CRT_DAC
VCCD_LVDS
VCC_TX_LVDS
VCCA_LVDS
VCCD_TVDAC
VCCA_TV_DAC
VCCD_QDAC
VCCA_DAC_BG
VCC_AXG
VCC_AXG_NCTF
VCCA_DPLLA
VCCA_DPLLB
VCC_HDA
EXT VGA->Disable TV/CRT/LVDS/HDMI(See DG 1.0 P190 Table 103)
INT VGA->Disable TV/Enable CRT( See DG1.0 P208 Table 118)
INT VGA->Disable HDMI(See DG 1.0 P277 section 3.10.4)
EXT VGA
GND
GND
GND
GND
+1.5V
GND
GND
GND
GND
GND
GND
GND
GND
INT VGA
+3V
+1.8VSUS
+1.8VSUS
+1.8VSUS
+1.5V
+3V
+1.5V
+3V
+1.05V
+1.05V
+1.05V
+1.05V
+1.5V
2
MARK
DR1
DR2
DR3
DR4
DR5
DR6
DR7
Page 8
DR8
DR9 Page 8
DR10
DR11
For iHDMI
DR12
NB Power Status and max current table(3/3)(NB Right side)
POWER PLANE
VTT
VCCA_AXF
VCC_SM_CK(800)
VCC_TX_LVDS
VCC_HV
VCC_PEG
VCC_DMI
(See NB EDS Rev:1.0 Section 10.1 for max current)
(See NB EDS Rev:1.0 Section 12.2 for DC voltage)
S0
S3
S4/S5
X
X
O
O
X
X
X
O
O
O
X
O
O
X
X
O
X
X
X
O
X
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
NB(5/7) POWER
NB(5/7) POWER
NB(5/7) POWER
Date: Sheet of
Date: Sheet of
Date: Sheet
I(max)
Voltage
852mA
+1.05V
322mA
+1.05V
124mA
+1.8VSUS
+1.8VSUS
119mA
+3V
106mA
1782mA
+1.05V
456mA
+1.05V
PROJECT : PB5/6
PROJECT : PB5/6
Quanta Computer Inc.
Quanta Computer Inc.
1
FSB at 1067MHz
(DDRII-667) 120mA
Note
1A
1A
1A
of
935Thursday, April 24, 2008
935Thursday, April 24, 2008
935Thursday, April 24, 2008
5
4
3
2
1
U26I
U26I
AU48
VSS_1
AR48
VSS_2
AL48
VSS_3
BB47
VSS_4
AW47
VSS_5
AN47
VSS_6
AJ47
VSS_7
AF47
VSS_8
D D
C C
B B
A A
5
AD47
AB47
N47
G47
BD46
BA46
AY46
AV46
AR46
AM46
R46
H46
BF44
AH44
AD44
AA44
U44
M44
BC43
AV43
AU43
AM43
C43
BG42
AY42
AT42
AN42
AJ42
AE42
N42
BD41
AU41
AM41
AH41
AD41
AA41
U41
M41
G41
BG40
BB40
AV40
AN40
H40
AT39
AM39
AJ39
AE39
N39
BH38
BC38
BA38
AU38
AH38
AD38
AA38
U38
C38
BF37
BB37
AW37
AT37
AN37
AJ37
H37
C37
BG36
BD36
AK15
AU36
Y47
T47
L47
V46
P46
F46
Y44
T44
F44
J43
L42
Y41
T41
B41
E40
L39
B39
Y38
T38
J38
F38
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
CANTIGA_1p2
CANTIGA_1p2
VSS
VSS
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
4
http://hobi-elektronika.net
BG21
AW21
AU21
AP21
AN21
AH21
AF21
AB21
BC20
BA20
AW20
AT20
AJ20
AG20
BG19
BG17
BC17
AW17
AT17
BA16
AU16
AN16
BG15
AC15
W15
BG14
AA14
BG13
BC13
BA13
AN13
AJ13
AE13
BF12
AV12
AT12
AM12
AA12
BD11
BB11
AY11
AN11
AH11
BG10
AV10
AT10
AJ10
AE10
AA10
M10
BC9
AN9
AM9
AD9
BH8
R21
M21
G21
Y20
N20
K20
F20
C20
A20
A18
R17
M17
H17
C17
N16
K16
G16
E16
A15
C14
N13
G13
E13
A12
Y11
N11
G11
C11
BF9
BB8
AV8
AT8
L12
J21
L13
J12
G9
B9
CANTIGA_1p2
CANTIGA_1p2
U26J
U26J
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_235
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
3
VSS
VSS
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS NCTF
VSS NCTF
VSS_NCTF_15
VSS_NCTF_16
VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_6
VSS SCB
VSS SCB
NC
NC
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42
NC_43
AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4
BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1
U24
U28
U25
U29
AJ6
AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17
BH48
BH1
A48
C1
A3
E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48
A47
MCH_VSS_351
MCH_VSS_352
MCH_VSS_353
MCH_VSS_354
MCH_VSS_355
R160 0_4R160 0_4
R159 0_4R159 0_4
R151 0_4R151 0_4
R157 0_4R157 0_4
R178 0_4R178 0_4
2
10
BOM Option Table
Reference
N/A
PROJECT : PB5/6
PROJECT : PB5/6
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
NB(6/7) VSS
NB(6/7) VSS
NB(6/7) VSS
Date: Sheet
Date: Sheet
Date: Sheet
Quanta Computer Inc.
1
Description
10 35Friday, March 21, 2008
10 35Friday, March 21, 2008
10 35Friday, March 21, 2008
N/A
of
of
of
1A
1A
1A
5
North Bridge Strap Pin Configuration Table
(See DG 1.0 P295 Table 184)
(See NB EDS 1.0 P187 Table 74)
Pin Name
D D
CFG[2:0]
FSB Frequency Select
[000]= FSB 1066MHz [010] = FSB 800MHz [011] = FSB 667MHz
4
3
2
1
http://hobi-elektronika.net
11
PU<4.02K> PD <2.21K>ConfigurationStrap description Note
See Page 2 FSB selection table
CFG[4:3]
CFG5
CFG6
CFG7
CFG8
CFG9
C C
CFG10
CFG11
CFG12
CFG13
CFG[15:14]
CFG16
CFG[18:17]
B B
CFG19
CFG20
SDVO_CTRLDATA
L_DDC_DATA
DDPC_CTRLDATA
Reserved
DMI X2 Select
iTPM Host Interface
ME TLS Confidentiality
Reserved
PCI Express Graphics
Lane Reversal
PCIE Loopback enable
Reserved
ALLZ
XOR
Reserved
FSB Dynamic ODT
Reserved
DMI Lane Reversal
Digital Display Port
(SDVO/DP/iHDMI)
Concurrent with PCIE
SDVO Present
Local Flat Panel(LFP) Present
Digital Display Present
0 = DMI X2
1 = DMI X4(Default)
0 = iTPM Host Interface is enabled
1 = iTPM Host Interface is disabled(Default)
0 = AMT Firmware will use TLS cipher suite with no confidentiality
1 = AMT Firmware will use TLS cipher suite with confidentiality(Default)
0 = Reverse Lanes
1 = Normal operation(Default)
0 = Enabled
1 = Disabled (Default)
0 = ALLZ mode enable
1 = disable(Default)
0 = XOR mode enable
1 = disable(Default)
0 = Dynamic ODT disable
1 = Dynamic ODT Enable(Default)
0 = Normal (Default)
1 = Lanes Reversed
0 = Only Digital Display port (SDVO/DP/iHDMI) or PCIE is
operational (Default)
1 = Digital Display port (SDVO/DP/iHDMI) and PCIE are operating
simultaneously via PEG port
0 = No SDVO/HDMI/DP Device Present(Default)
1 = SDVO/HDMI/DP Device present
0 = LFP Disable(Default)
1 = LFP Card Present;PCIE disable
0 = Digital display(HDMI/DP) device absent(Default)
1 = Digital display(HDMI/DP) device present
MCH_CFG_56
MCH_CFG_66
MCH_CFG_76
MCH_CFG_96
MCH_CFG_106
MCH_CFG_126
MCH_CFG_136
MCH_CFG_166
MCH_CFG_196
MCH_CFG_206
SDVO_CTRLDATA6
INT_LVDS_EDIDDATA6,19
DDPC_CTRLDATA6
R115 *4.02K/F_4R115 *4.02K/F_4
R146 *10K/F_4R146 *10K/F_4
R142 *4.02K/F_4R142 *4.02K/F_4
R549 *4.02K/F_4R549 *4.02K/F_4
R550 *4.02K/F_4R550 *4.02K/F_4
R144 *4.02K/F_4R144 *4.02K/F_4
R150 *4.02K/F_4R150 *4.02K/F_4
R138 *4.02K/F_4R138 *4.02K/F_4
R85 *4.02K/F_4R85 *4.02K/F_4
R84 *4.02K/F_4R84 *4.02K/F_4
R92 *2.2K/F_4R92 *2.2K/F_4
R103 *2.2K/F_4R103 *2.2K/F_4
R90 *2.2K/F_4R90 *2.2K/F_4
VCC3
VCC3
VCC3
VCC3
VCC3
Enable iTPM
BOM Option Table
Reference
N/A
Description
N/A
Enable iTPM Table
A A
PAGE
11
13
14
Net Name
MCH_CFG_6
SPI_MOSI
CLGPIO5
PU & PD NOTE
PD 10K to GND
PU 20K to +3V_S5 SB Strap pin
PU 10K to +3V_S5 SB Strap pin
5
NB Strap pin
PROJECT : PB5/6
PROJECT : PB5/6
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
NB(7/7) STRAP
NB(7/7) STRAP
NB(7/7) STRAP
Date: Sheet
Date: Sheet
4
3
2
Date: Sheet
11 35Friday, May 30, 2008
11 35Friday, May 30, 2008
11 35Friday, May 30, 2008
1
1A
1A
1A
of
of
of
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