Quanta OT2, Compaq 2510P Schematic

5

4

3

2

1

CK505

P16

14.318MHz

P17

Cable Docking

1 TO 4 USB HUB
LINE IN
LINE OUT
RJ45
CRT PORT
SVIDEO OUT
POWER JACK

Sapporo 1.0 BLOCK DIAGRAM

CPU Thermal
Sensor

MAX6657

P04

DDR2-SODIMM1

Clock Generator

P33

P35

P34

P38

P37

Ambient Light Sensor

P36

LCD Panel

P39

CRT port

P18

P27

LVDS

R.G,B

Merom

478Pins

(Micro-FCBGA)

667/800 MHz FSB

Crestline

1299 uFCBGA

P7,P8,P9,P10,P11

DMI

P4,P5

Singal Channel DDR2

CPU CORE

DD

+1.05V/+1.5V

/+1.25V/+1.25VM

3VPCU/5VPCU

1.8V/SMDDR_VTERM/SMDR_VREF

BATT CHARGER
MAX8724/1908

DISCHARGE

+3VM_LAN_SW/3V_S5/+3V_CK505/3VSUS/+3V

CC

+5V/5VSUS

P35

PCI-E

HDD (1.8 inch)

DVD-ROM

BB

SIM CARD

P19

AA

P28

P28

USB PORT 0

USB PORT 1(POWER
USB)

Bluetooth Module

FingerPrint(AES2501B)

WWAN MiniCard

USB for Docking

P30

P30

P30

P30

P19

P32

PATA

USB 2.0

Accelerometer

TPM (1.2)

SLB9635

SMBUS

LIS3LV02DL

3.3V LPC, 33MHz

ICH8M

P12,P13,P14,P15

SMSC KBC1070

PCI-E

PCI BUS

PCMCIA /SMART CARD

Azalia

SPI

SYSTEM
BIOS

P31

P26

SATA/PATA

WLAN MiniCard

PCMCIA Controller

Ricoh 5C847

P20,P21

P20

P19

Intel Nineveh-MM

1394

P21

Audio

CODEC

AD1981

MODEM
MDC 1.5JACK

P22,P23

RJ11

P30P30

LAN

P24,P25

RJ45

P25

AMP

TPA6211A

P23

AMP

TLV2462CDGKR

P23

AUDIO
JACK

P23

MIC
JACK

P23

FAN

P29P29P29

5

4

Track
Point

3

Keyboard

SizeDocument NumberRev

2

Date:Sheet of

PROJECT : OT2

Quanta Computer Inc.

System Block Diagram

1

142Thursday, March 22, 2007

1ACustom

5

4

3

2

1

INDEXPower & Ground

Description

1

Schematic Block Diagram

2

DD

CC

BB

System Information

3

System Power Block Diagram

4-5

Merom CPU/THERMAL SENSOR

7-11

Crestline_

12-15

ICH8_M

16

DDR II SO-DIMM

17

CLOCK GEN

18

LCD CONNECTOR / LCD PWR

19

WAN/WWAN /SIM CARD connector

20-21

CARDBUS CONTROLLER

22-23

AUDIO CODEC / AUDIO JACK

24-25

LAN/TRANSFORMER

26

KBC

27

CRT PORT

28

HDD / CD-ROM

29

FAN,KB,LEDs,TRACK POINT

30

USB,BLUE TOOTH,FINGER PRINT, MDC,TPM

31

POWER SEQUENCE,BIOS

32

CABLE DOCKING

33

DISCHARGE

34

-CHARGER(MAX1908/8724)

35

MAX1999(3VPCU/5VPCU)

36

MAX1992(1.8VSUS/DDR_VTERM)

37

MAX1540 (+1.05V/+1.5V)

38

--MAX8736

39

+3VM/+3V_S5/1.25V_M

40

POWER SEQUENCE

NOTEPg#

Label

VIN
MBAT
VCCRTC
+15V
CPU_CORE
+1.05V
+1.05VMM0.M1IAMT_ON
+3V
3VSUS
3V_S5S5_ONS0, S3, S4, S5
3VPCU
+5V
5VSUS

5VPCU
+1.5VS0

+1.5VM

1.8VSUS
+2.5VMAINONS0

SMDDR_VREF
VDDA

+3V_CK505M0.M1IAMT_ON

+3V_LAN_SWM0.M1IAMT_ON

+1.25VS0MAIND

+1.25VMM0.M1IAMT_ON

ACTIVE

S0, S3, S4, S5.M0.M1.Moff

S0, S3, S4, S5.M0.M1.Moff

S0, S3, S4, S5.M0.M1.Moff

S0, S3, S4, S5.M0.M1.Moff

S0
S0

S0
S0, S3

S0, S3, S4, S5.M0.M1.Moff

S0
S0, S3

S0, S3, S4, S5.M0.M1.Moff

M0.M1

S0, S3SUSON

S0
S0, S3
S0MAINON

+15V

DDR COMMAND & CONTROL PULL UP POWER
DDR REF POWER
AUDIO ANALOG POWER (5V)

Description

AC ADAPTER (19V)

MAIN BATTERY + (10~17V)

RTC & KBC POWER

CPU CORE POWER (1.25/1.15V)

FSB POWER (1.05V)

ALWAYS POWER (3V)

ALWAYS POWER (5V)

DDR CORE POWER

(3_3V)

Control
Signal

VRON
MAIND

MAIND
SUSON

MAIND
SUSON
S5_ONS0, S3, S4, S55V_S5

MAIND

IAMT_ON

MAINONSMDDR_VTERM
SUSON

PCB STACK UPPCI DEVICES IRQ ROUTING

PCI_INTDEVICEREQ/GNT #IDSEL #

AA

5

LAYER 1 : TOP
LAYER 2 : GND
LAYER 3 : IN1
LAYER 4 : IN2
LAYER 5 : VCC
LAYER 6 : IN3
LAYER 7 : GND
LAYER 8 : BOT

4

SM BUS

CLOCK GENERATOR
DDR II
Accelemter sensor
CHARGER
CPU THERMAL SENSOR

3

ADDRESSDEVICEBUS

PROJECT : OT2

SizeDocument NumberRev

2

Date:Sheet of

Quanta Computer Inc.

System Information

1

242Thursday, March 22, 2007

1ACustom

5

4

3

S5_ON

2

1

SYSTEM POWER BLOCK DIAGRAM

IAMT_ON

DD

Adaptor

VIN

CC

CHARGER

S.W

MOS-FET

VIN

3VPCU
ALWAYS

MAX1999

MAIND

S.W

MOS-FET

S.W

MOS-FET

IAMT_ON

S.W

MOS-FET

IAMT_ON

SC4215+1.25VM

S.W

MOS-FET

SUSD

3V_S5

+3V_CK505

+3VM_LAN_SW

+3V

3VSUS

MAX8724/1908

+15V

MAIND

SUSD

S.W

MOS-FET

+5V

5VSUS

5VPCU

ALWAYS

BATTERY

BB

S.W

MOS-FET

SUSON

MAX1992

MAINON

1.8VSUS

MAINON

MAINON

TPS51100

SMDDR_VTERM
SMDDR_VREF

VIN

1.5V

MAX1540

1.05V_M

VIN

VRON

AA

CPU_VID[0..5]

HWPG
DPRSLPVR
STP_CPU#

5

MAX1907

4

IAMAT_ON

KBC_PW_ON

SLP_S5#

SLP_S3#

CPU_CORE

3

SC4215

MAIND

S.W

MOS-FET

TC7SH08FU
TC7SH08FU
TC7SH08FU

S5_ON

+1.25V

+1.05V

MAINON

DISCHARGE

DISCHARGE

DISCHARGE

2

S5_OND

SUSDSUSON

MAIND

PROJECT : OT2

SizeDocument NumberRev

Date:Sheet of

Quanta Computer Inc.

System pwr block diagram

1

342Thursday, March 22, 2007

1ACustom

1

2

3

4

5

6

7

8

R11256

H_IERR#

1 2

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#

R10575

H_PROCHOT#
H_THERMDA
H_THERMDC

OBSFN_C0
OBSFN_C1

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSFN_D0
OBSFN_D1

OBSDATA_D0
OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

3

H_ADS#(6)

T25PAD

H_BNR#(6)
H_BPRI#(6)

H_DEFER#(6)
H_DRDY#(6)
H_DBSY#(6)
H_BR0#(6)

H_INIT#(12)
H_LOCK#(6)
H_RESET#(6)

H_RS#0(6)
H_RS#1(6)
H_RS#2(6)
H_TRDY#(6)

H_HIT#(6)
H_HITM#(6)

XDP_DBRESET#(14,31)

12

+1.05V

PM_THRMTRIP#(7,12)

CLK_CPU_BCLK(17)
CLK_CPU_BCLK#(17)

2

GND1

4
6
8

GND3

10
12
14

GND5

16
18
20

GND7

22
24
26

GND9

28
30
32

GND11

34
36
38

GND13

40
42
44
46
48
50

GND15

52

TDO

54

TRSTn

56

TDI

58

TMS

60

GND17

+1.05V

Layout Note:
Place voltage
divider within

0.5" of GTLREF
pin

+1.05V

R62
1K/F

H_PROCHOT#(39)

layout note for H_THERMDA/H_THERMDC - Trace width/Spacing
should be 10/10 mils

SI stage:no install to avoid leakage current

CLK_CPU_XDP(17)
CLK_CPU_XDP#(17)

XDP_DBRESET#
XDP_TDO

XDP_TRST#
XDP_TDI
XDP_TMS

DB1A stage:change for change list

1 2

R54
2K/F

1 2

XDP_DBRESET#(14,31)

+1.05V

R471K/F
R46*1K/F

R41*54.9/F
R40680
R36150
R3939

4

H_D#[0..63](6)

H_DSTBN#0(6)
H_DSTBP#0(6)
H_DINV#0(6)

H_D#[0..63](6)

H_DSTBN#1(6)
H_DSTBP#1(6)
H_DINV#1(6)

CPU_BSEL0(17)
CPU_BSEL1(17)
CPU_BSEL2(17)

DB1A:change for intel
schematic

R124

1 2

R119

1 2

C49
R125

1 2

Place C close to the
CPU_TEST4 pin. Make sure
CPU_TEST4 routing is
reference to GND and away
from other noisy signal.

*1K/F
*1K/F

12

*0.1U/10V

*0

H_RESET#

+3V

CPU_TEST1
CPU_TEST2
CPU_TEST4
CPU_TEST6

C50

0.1U

SYS_SHDN#(35)

C39

0.1U

C420

0.1U

C422
2200P

+1.05V

5

+3V

H_D#[0..63]

H_D#[0..63]

R350
100R

6657VCC

H_THERMDA

H_THERMDC

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31

V_CPU_GTLREF
CPU_TEST1
CPU_TEST2
CPU_TEST3
CPU_TEST4
CPU_TEST5
CPU_TEST6

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

T92

PAD

T6

PAD

For the purpose of testability, route these signals
through a ground referenced Z0 = 55ohm trace that
ends in a via that is near a GND via and is
accessible through an oscilloscope connection.

U21B

E22

D[0]#

F24

D[1]#

E26

D[2]#

G22

D[3]#

F23

D[4]#

G25

D[5]#

E25

D[6]#

E23

D[7]#

K24

D[8]#

G24

D[9]#

J24

D[10]#

J23

D[11]#

H22

D[12]#

F26

D[13]#

K22

D[14]#

H23

D[15]#

J26

DSTBN[0]#

H26

DSTBP[0]#

H25

DINV[0]#

N22

D[16]#

K25

D[17]#

P26

D[18]#

R23

D[19]#

L23

D[20]#

M24

D[21]#

L22

D[22]#

M23

D[23]#

P25

D[24]#

P23

D[25]#

P22

D[26]#

T24

D[27]#

R24

D[28]#

L25

D[29]#

T25

D[30]#

N25

D[31]#

L26

DSTBN[1]#

M26

DSTBP[1]#

N24

DINV[1]#

AD26

GTLREF

C23

TEST1

D25

TEST2

C24

TEST3

AF26

TEST4

AF1

TEST5

A26

TEST6

B22

BSEL[0]

B23

BSEL[1]

C21

BSEL[2]

Merom Ball-out Rev 1a

CPU_TEST3
CPU_TEST5

DATA GRP 0 DATA GRP 1

MISC

DATA GRP 2DATA GRP 3

DSTBN[2]#
DSTBP[2]#

DINV[2]#

DSTBN[3]#
DSTBP[3]#

DINV[3]#
COMP[0]

COMP[1]
COMP[2]
COMP[3]

DPRSTP#

DPSLP#
DPWR#

PWRGOOD

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#

D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#

SLP#

H_D#33

AB24

H_D#34

V24

H_D#35

V26

H_D#36

V23

H_D#37

T22

H_D#38

U25

H_D#39

U23

H_D#40

Y25

H_D#41

W22

H_D#42

Y23

H_D#43

W24

H_D#44

W25

H_D#45

AA23

H_D#46

AA24

H_D#47

AB25
Y26
AA26
U22

H_D#48

AE24

H_D#49

AD24

H_D#50

AA21

H_D#51

AB22

H_D#52

AB21

H_D#53

AC26

H_D#54

AD20

H_D#55

AE22

H_D#56

AF23

H_D#57

AC25

H_D#58

AE21

H_D#59

AD21

H_D#60

AC22

H_D#61

AD23

H_D#62

AF22

H_D#63

AC23
AE25
AF24
AC20

COMP0

R26

COMP1

U26

COMP2

AA1

COMP3

Y1
E5

B5
D24
D6
D7
AE6

PSI#

Comp0,2 connect with Zo=27.4ohm,Comp1,3
connect with Zo=55ohm, make those traces
length shorter than 0.5".Trace should be
at least 25 mils away from any other
toggling signal.

H_D#32

Y22

H/W MONITOR

U28

1

VCC

2

DXP

3

DXN

4 5

-OVTGND

SMCLK

SMDATA

-ALT

MAX6657/GMT-781

6

SMBCK

8

SMBDT

7

THERM_ALERT#

6

SMBCK(17,19,27)

SMBDT(17,19,27)

THERM_ALERT#(14)

SizeDocument NumberRev

Date:Sheet of

(HOST BUS)/THERMAL

7

H_D#[0..63]

H_D#[0..63]

COMP0
COMP1
COMP2
COMP3

R78

54.9/F

1 2

H_D#[0..63](6)

H_DSTBN#2(6)
H_DSTBP#2(6)
H_DINV#2(6)

H_D#[0..63](6)

H_DSTBN#3(6)
H_DSTBP#3(6)
H_DINV#3(6)

H_DPRSTP#(7,12)
H_DPSLP#(12)
H_DPWR#(6)
H_PWRGOOD(12)
H_CPUSLP#(6)
PSI#(39)

R83

R67

54.9/F

27.4/F

1 2

1 2

1 2

PROJECT : OT2

Quanta Computer Inc.

442Thursday, March 22, 2007

8

R87

27.4/F

1ACustom

XDP_BPM#3

H_PWRGOOD

+1.05V

1

H_A#[3..16]

H_REQ#[0..4]

H_A#[17..35]

H_ADSTB#1(6)

+1.05V

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

T11

R760
R69*0
R710
R63*56/F
R660
R560

R571K/F
R4254.9/F

L_CLKCTLB(7)
L_CLKCTLA(7)

R3827/F

DB1A stage:change for change list

H_A#[3..16](6)

AA

H_ADSTB#0(6)
H_REQ#[0..4](6)

H_A#[17..35](6)

BB

H_A20M#(12)

H_FERR#(12)

H_IGNNE#(12)
H_STPCLK#(12)

H_INTR(12)
H_NMI(12)
H_SMI#(12)

CC

XDP_BPM#2
XDP_BPM#1

XDP_BPM#0

DD

U21A

J4

A[3]#

L5

A[4]#

L4

A[5]#

K5

A[6]#

M3

A[7]#

N2

A[8]#

J1

A[9]#

N3

A[10]#

P5

A[11]#

P2

A[12]#

L2

A[13]#

P4

A[14]#

P1

A[15]#

R1

A[16]#

M1

ADSTB[0]#

K3

REQ[0]#

H2

REQ[1]#

K2

REQ[2]#

J3

REQ[3]#

L1

REQ[4]#

Y2

A[17]#

U5

A[18]#

R3

A[19]#

W6

A[20]#

U4

A[21]#

Y5

A[22]#

U1

A[23]#

R4

A[24]#

T5

A[25]#

T3

A[26]#

W2

A[27]#

W5

A[28]#

Y4

A[29]#

U2

A[30]#

V4

A[31]#

W3

A[32]#

AA4

A[33]#

AB2

A[34]#

AA3

A[35]#

V1

ADSTB[1]#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD[01]

N5

RSVD[02]

T2

RSVD[03]

V3

RSVD[04]

B2

RSVD[05]

C3

RSVD[06]

D2

RSVD[07]

D22

RSVD[08]

D3

RSVD[09]

F6

RSVD[10]

Merom Ball-out Rev 1a

XDP_BPM#5
XDP_BPM#4

XDP_OBS0
XDP_OBS1

XDP_OBS2
XDP_OBS3

H_PWRGD_XDP

L_CLKCTLB
L_CLKCTLA

XDP_TCK

2

ADDR GROUP

0

ADDR GROUP

1

THERMAL

ICH

THERMTRIP#

RESERVED

T5
T2

ADS#
BNR#
BPRI#

DEFER#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROLXDP/ITP SIGNALS

RESET#

RS[0]#
RS[1]#
RS[2]#

TRDY#

HIT#

HITM#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#

PRDY#
PREQ#

TCK
TDO

TMS

TRST#

DBR#

PROCHOT#

THERMDA
THERMDC

H CLK

BCLK[0]
BCLK[1]

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

H1
E2
G5

H5
F21
E1

F1
D20

B3
H4
C1

F3
F4
G3
G2

G6
E4

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6

TDI

AB3
AB5
AB6
C20

D21
A24
B25

C7

A22
A21

JITP1

GND0
OBSFN_A0
OBSFN_A1
GND2
OBSDATA_A0
OBSDATA_A1
GND4
OBSDATA_A2
OBSDATA_A3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B0
OBSDATA_B1
GND10
OBSDATA_B2
OBSDATA_B3
GND12
PWRGD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16

*CONN60_ITP-XDP

1

2

3

4

5

6

7

8

VCC_CORE VCC_CORE

VCC_CORE

AA

VCC_CORE

All use 22U 6.3V(+-20%,X5R,0805)Pb-Free.

12

C44
22U/6.3V

12

C86
22U/6.3V

12

12

C173
22U/6.3V

C85
22U/6.3V

12

C172
22U/6.3V

12

C168
22U/6.3V

12

C171
22U/6.3V

12

C167
22U/6.3V

12

C169
22U/6.3V

12

C174
22U/6.3V

8 inside cavity, north side, secondary layer.

VCC_CORE

12

BB

VCC_CORE

12

C81
22U/6.3V

C143
22U/6.3V

12

C80
22U/6.3V

12

C142
22U/6.3V

12

12

C84
22U/6.3V

C79
22U/6.3V

12

C83
22U/6.3V

12

C145
22U/6.3V

12

C82
22U/6.3V

12

C144
22U/6.3V

8 inside cavity, south side, secondary layer.

VCC_CORE

12

C45
22U/6.3V

12

C170
22U/6.3V

12

C138
22U/6.3V

12

C139
22U/6.3V

12

C140
22U/6.3V

12

C141
22U/6.3V

6 inside cavity, north side, primary layer.

VCC_CORE

CC

12

C48
22U/6.3V

12

C47
22U/6.3V

12

C46
22U/6.3V

12

C43
22U/6.3V

12

C42
22U/6.3V

12

C41
22U/6.3V

6 inside cavity, south side, primary layer.

+1.05V

12

Layout out:
Place these

DD

inside
socket
cavity on
North side
secondary.

C98

0.1U/10V

12

C87

0.1U/10V

12

C105

0.1U/10V

12

C117

0.1U/10V

12

C96

0.1U/10V

12

C123

0.1U/10V

U21C

A7

VCC[001]

A9

VCC[002]

A10

VCC[003]

A12

VCC[004]

A13

VCC[005]

A15

VCC[006]

A17

VCC[007]

A18

VCC[008]

A20

VCC[009]

B7

VCC[010]

B9

VCC[011]

B10

VCC[012]

B12

VCC[013]

B14

VCC[014]

B15

VCC[015]

B17

VCC[016]

B18

VCC[017]

B20

VCC[018]

C9

VCC[019]

C10

VCC[020]

C12

VCC[021]

C13

VCC[022]

C15

VCC[023]

C17

VCC[024]

C18

VCC[025]

D9

VCC[026]

D10

VCC[027]

D12

VCC[028]

D14

VCC[029]

D15

VCC[030]

D17

VCC[031]

D18

VCC[032]

E7

VCC[033]

E9

VCC[034]

E10

VCC[035]

E12

VCC[036]

E13

VCC[037]

E15

VCC[038]

E17

VCC[039]

E18

VCC[040]

E20

VCC[041]

F7

VCC[042]

F9

VCC[043]

F10

VCC[044]

F12

VCC[045]

F14

VCC[046]

F15

VCC[047]

F17

VCC[048]

F18

VCC[049]

F20

VCC[050]

AA7

VCC[051]

AA9

VCC[052]

AA10

VCC[053]

AA12

VCC[054]

AA13

VCC[055]

AA15

VCC[056]

AA17

VCC[057]

AA18

VCC[058]

AA20

VCC[059]

AB9

VCC[060]

AC10

VCC[061]

AB10

VCC[062]

AB12

VCC[063]

AB14

VCC[064]

AB15

VCC[065]

AB17

VCC[066]

AB18

VCC[067]

Merom Ball-out Rev 1a

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

VCCA[01]
VCCA[02]

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VCCSENSE

VSSSENSE

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

AF7

AE7

.

DB1A stage:change
to 330u

VCCSENSE

VSSSENSE

+1.05V

12

+

H_VID0(39)
H_VID1(39)
H_VID2(39)
H_VID3(39)
H_VID4(39)
H_VID5(39)
H_VID6(39)

VCCSENSE(39)

VSSSENSE(39)

C106
330U/4V

12

C156

0.01U/25V

Layout Note:
Place C156 near
PIN B26.

VCC_CORE

VCCSENSE
VSSSENSE

Route VCCSENSE and VSSSENSE
traces at 27.4ohms and
length matched to within 25
mil. Place PU and PD within
2 inch of CPU.

+1.5V

12

C163
10U/4V

12

R45
100/F

12

R44
100/F

U21D

A4
A8

A11
A14
A16
A19
A23
AF2

B6
B8

B11
B13
B16
B19
B21
B24

C5
C8

C11
C14
C16
C19

C2

C22
C25

D1
D4
D8

D11
D13
D16
D19
D23
D26

E3
E6
E8

E11
E14
E16
E19
E21
E24

F5
F8

F11
F13
F16
F19

F2

F22
F25

G4

G1
G23
G26

H3

H6
H21
H24

J2

J5
J22
J25

K1

K4
K23
K26

L3

L6
L21
L24

M2

M5
M22
M25

N1

N4
N23
N26

P3 A25

VSS[082]

VSS[001]
VSS[002]

VSS[083]

VSS[003]

VSS[084]

VSS[004]

VSS[085]

VSS[005]

VSS[086]

VSS[006]

VSS[087]

VSS[007]

VSS[088]

VSS[008]

VSS[089]

VSS[009]

VSS[090]

VSS[010]

VSS[091]

VSS[011]

VSS[092]

VSS[012]

VSS[093]

VSS[013]

VSS[094]

VSS[014]

VSS[095]

VSS[015]

VSS[096]

VSS[016]

VSS[097]

VSS[017]

VSS[098]

VSS[018]

VSS[099]

VSS[019]

VSS[100]

VSS[020]

VSS[101]

VSS[021]

VSS[102]

VSS[022]

VSS[103]

VSS[023]

VSS[104]

VSS[024]

VSS[105]

VSS[025]

VSS[106]

VSS[026]

VSS[107]

VSS[027]

VSS[108]

VSS[028]

VSS[109]

VSS[029]

VSS[110]

VSS[030]

VSS[111]

VSS[031]

VSS[112]

VSS[032]

VSS[113]

VSS[033]

VSS[114]

VSS[034]

VSS[115]

VSS[035]

VSS[116]

VSS[036]

VSS[117]

VSS[037]

VSS[118]

VSS[038]

VSS[119]

VSS[039]

VSS[120]

VSS[040]

VSS[121]

VSS[041]

VSS[122]

VSS[042]

VSS[123]

VSS[043]

VSS[124]

VSS[044]

VSS[125]

VSS[045]

VSS[126]

VSS[046]

VSS[127]

VSS[047]

VSS[128]

VSS[048]

VSS[129]

VSS[049]

VSS[130]

VSS[050]

VSS[131]

VSS[051]

VSS[132]

VSS[052]

VSS[133]

VSS[053]

VSS[134]

VSS[054]

VSS[135]

VSS[055]

VSS[136]

VSS[056]

VSS[137]

VSS[057]

VSS[138]

VSS[058]

VSS[139]

VSS[059]

VSS[140]

VSS[060]

VSS[141]

VSS[061]

VSS[142]

VSS[062]

VSS[143]

VSS[063]

VSS[144]

VSS[064]

VSS[145]

VSS[065]

VSS[146]

VSS[066]

VSS[147]
VSS[148]

VSS[067]
VSS[068]

VSS[149]

VSS[069]

VSS[150]

VSS[070]

VSS[151]

VSS[071]

VSS[152]

VSS[072]

VSS[153]

VSS[073]

VSS[154]

VSS[074]

VSS[155]

VSS[075]

VSS[156]

VSS[076]

VSS[157]

VSS[077]

VSS[158]

VSS[078]

VSS[159]

VSS[079]

VSS[160]

VSS[080]

VSS[161]

VSS[081]VSS[162]

VSS[163]

Merom Ball-out Rev 1a

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21

AF25

.

PROJECT : OT2

SizeDocument NumberRev

1

2

3

4

5

6

Date:Sheet of

Quanta Computer Inc.

Merom(POWER/NC)

7

542Thursday, March 22, 2007

8

1ACustom

1

2

3

4

5

6

7

8

H_A#[3..35]

H_ADS#(4)
H_ADSTB#0(4)
H_ADSTB#1(4)
H_BNR#(4)
H_BPRI#(4)
H_BR0#(4)
H_DEFER#(4)
H_DBSY#(4)
CLK_MCH_BCLK(17)
CLK_MCH_BCLK#(17)
H_DPWR#(4)
H_DRDY#(4)
H_HIT#(4)
H_HITM#(4)
H_LOCK#(4)
H_TRDY#(4)

H_DINV#0(4)
H_DINV#1(4)
H_DINV#2(4)
H_DINV#3(4)

H_DSTBN#0(4)
H_DSTBN#1(4)
H_DSTBN#2(4)
H_DSTBN#3(4)

H_DSTBP#0(4)
H_DSTBP#1(4)
H_DSTBP#2(4)
H_DSTBP#3(4)

H_REQ#0(4)
H_REQ#1(4)
H_REQ#2(4)
H_REQ#3(4)
H_REQ#4(4)

H_RS#0(4)
H_RS#1(4)
H_RS#2(4)

H_A#[3..35](4)

W10

AD12

AC14
AD11
AC11

AJ14

AE11
AH12

AH13

M10
N12

AE3
AD9
AC9
AC7

AB2
AD7
AB1

AC6
AE2
AC5
AG3

AH8
AE9

AH5
AE7

AE5
AH2

E2

G2
G7
M6
H7
H3
G4

F3
N8
H2

N9
H5

P13

K9
M2

Y8

V4
M3

J1
N5
N3

W6
W9

N2

Y7

Y9

P4

W3

N1

Y3

AJ9

AJ5
AJ6
AJ7

AJ2
AJ3

B3
C2

W1
W2

B6

E5

B9

A9

U30A

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

H_SWING
H_RCOMP

H_SCOMP
H_SCOMP#

H_CPURST#
H_CPUSLP#

H_AVREF
H_DVREF

CRESTLINE_1p0

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

H_ADS#
H_ADSTB#_0
H_ADSTB#_1

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

HOST

H_DPWR#

H_DRDY#

H_HIT#

H_HITM#
H_LOCK#
H_TRDY#

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_REQ#_0
H_REQ#_1

H_REQ#_2
H_REQ#_3

H_REQ#_4

H_RS#_0
H_RS#_1
H_RS#_2

H_D#[0..63]

H_RESET#(4)

H_CPUSLP#(4)

12

C186

0.1U/10V

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_SWING
H_RCOMP

H_SCOMP
H_SCOMP#

H_REF

C189

0.1U/10V

1 2

+1.05V

H_D#[0..63](4)

R132
1K/F

1 2

12

R136
2K/F

AA

+1.05V

12

R134
221/F

H_SWING

12

R141
100/F

BB

+1.05V

12

12

R175

R174

54.9/F

54.9/F

H_SCOMP
H_SCOMP#

12

CC

H_RCOMP

R142

24.9/F

Layout Note:
H_RCOMP trace should be
10-mil wide with 20-mil
spacing.

J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19

G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7

K5
L2
AD13
AE13

M7
K3
AD2
AH11

L7
K2
AC2
AJ10

M14
E13
A11
H13
B12

E12
D7
D8

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

Layout Note:
Place the 0.1 uF

DD

decoupling capacitor
within 100 mils from
GMCH pins.

PROJECT : OT2

SizeDocument NumberRev

1

2

3

4

5

6

Date:Sheet of

Quanta Computer Inc.

Crestline_1(HOST)

7

642Thursday, March 22, 2007

8

1ACustom

1

SM_RCOMP_VOH

12

C280

0.01U/25V

SM_RCOMP_VOL

AA

12

C286

0.01U/25V

BB

Layout Note:
Location of all MCH_CFG strap
resistors needs to be close to
minmize stub.

MCH_BSEL0(17)
MCH_BSEL1(17)
MCH_BSEL2(17)

CC

+3V

PM_BMBUSY#(14)

DELAY_VR_PWRGOOD(14,31,39)

PM_THRMTRIP#(4,12)

PM_DPRSLPVR(14,39)

DD

1K/F

12

C279

2.2U/10V

12

C283

2.2U/10V

T18

PAD

T100

PAD

R159*4.02K/F

T33

PAD

T21

PAD

T23

PAD

R148*4.02K/F

T38

PAD

T26

PAD

R165*4.02K/F
R152*4.02K/F

T19

PAD

T27

PAD

R168*4.02K/F

T34

PAD

T30

PAD

R171*4.02K/F
R161*4.02K/F

H_DPRSTP#(4,12)
PM_EXTTS#0(16)

PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD

PLT_RST-R#(13)

1

12

R210

PAD
PAD
PAD
PAD

12

PAD
PAD

R209

PAD

3.01K/F

PAD
PAD
PAD
PAD
PAD

12

PAD
PAD

R208
1K/F

PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD

PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD
PAD

12

12

12
12

12

12
12

PM_EXTTS#0
PM_EXTTS#1

PLTRST#_R

PM_THRMTRIP#

1 2

R1540

T109
T111
T120
T118
T113
T116
T115
T110
T108
T103
T98
T105
T107
T101
T99
T112

1.8VSUS

T36
T35
T37
T31
T49
T48
T46
T45
T29
T43
T44
T42
T47
T17

T22
T104
T58
T114
T55
T59
T119
T56
T54
T57
T52
T53

T117
T50
T60
T106
T20
T97
T24
T96
T102
T95
T94
T93

CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20

TP_NC1
TP_NC2
TP_NC3
TP_NC4
TP_NC5
TP_NC6
TP_NC7
TP_NC8
TP_NC9
TP_NC10
TP_NC11
TP_NC12
TP_NC13
TP_NC14
TP_NC15
TP_NC16

2

U30B

P36

RSVD1

P37

RSVD2

R35

RSVD3

N35

RSVD4

AR12

RSVD5

AR13

RSVD6

AM12

RSVD7

AN13

RSVD8

J12

RSVD9

AR37

RSVD10

AM36

RSVD11

AL36

RSVD12

AM37

RSVD13

D20

RSVD14

H10

RSVD20

B51

RSVD21

BJ20

RSVD22

BK22

RSVD23

BF19

RSVD24

BH20

RSVD25

BK18

RSVD26

BJ18

RSVD27

BF23

RSVD28

BG23

RSVD29

BC23

RSVD30

BD24

RSVD31

BH39

RSVD34

AW20

RSVD35

BK20

RSVD36

C48

RSVD37

D47

RSVD38

B44

RSVD39

C44

RSVD40

A35

RSVD41

B37

RSVD42

B36

RSVD43

B34

RSVD44

C34

RSVD45

P27

CFG_0

N27

CFG_1

N24

CFG_2

C21

CFG_3

C23

CFG_4

F23

CFG_5

N23

CFG_6

G23

CFG_7

J20

CFG_8

C20

CFG_9

R24

CFG_10

L23

CFG_11

J23

CFG_12

E23

CFG_13

E20

CFG_14

K23

CFG_15

M20

CFG_16

M24

CFG_17

L32

CFG_18

N33

CFG_19

L35

CFG_20

G41

PM_BM_BUSY#

L39

PM_DPRSTP#

L36

PM_EXT_TS#_0

J36

PM_EXT_TS#_1

AW49

PWROK

AV20

RSTIN#

N20

THERMTRIP#

G36

DPRSLPVR

BJ51

NC_1

BK51

NC_2

BK50

NC_3

BL50

NC_4

BL49

NC_5

BL3

NC_6

BL2

NC_7

BK1

NC_8

BJ1

NC_9

E1

NC_10

A5

NC_11

C51

NC_12

B50

NC_13

A50

NC_14

A49

NC_15

BK2 R32

NC_16TEST_2

CRESTLINE_1p0

R182100

PLTRST#_R

12

2

CFGRSVD

PM

NC

SM_CK#_0
SM_CK#_1
SM_CK#_3

SM_CK#_4
SM_CKE_0

SM_CKE_1
SM_CKE_3
SM_CKE_4

SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3

SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3

SM_RCOMP

DDR MUXINGCLKDMI

SM_RCOMP#

SM_RCOMP_VOH

SM_RCOMP_VOL

SM_VREF_0
SM_VREF_1

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

PEG_CLK#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3

GFX_VR_EN

GRAPHICS VIDME

CL_PWROK

SDVO_CTRL_CLK

SDVO_CTRL_DATA

CLK_REQ#

ICH_SYNC#

MISC

3

SM_CK_0
SM_CK_1
SM_CK_3
SM_CK_4

PEG_CLK

CL_CLK

CL_DATA

CL_RST#

CL_VREF

TEST_1

3

AV29
BB23
BA25
AV23

AW30
BA23
AW25
AW23

BE29
AY32
BD39
BG37

BG20
BK16
BG16
BE13

BH18
BJ15
BJ14
BE16

BL15
BK14

BK31
BL31

AR49
AW4

B42
C42
H48
H47

K44
K45

AN47
AJ38
AN42
AN46

AM47
AJ39
AN41
AN45

AJ46
AJ41
AM40
AM44

AJ47
AJ42
AM39
AM43

E35
A39
C38
B39
E36

AM49
AK50
AT43
AN49
AM50

H35
K36
G39
G40

A37

GFX_VR_EN

M_CLK_DDR0(16)
M_CLK_DDR1(16)

M_CLK_DDR#0(16)
M_CLK_DDR#1(16)

DDR_CKE0_DIMMA(16)
DDR_CKE1_DIMMA(16)

DDR_CS0_DIMMA#(16)
DDR_CS1_DIMMA#(16)

M_ODT0(16)
M_ODT1(16)

SMRCOMPP
SMRCOMPN

SM_RCOMP_VOH
SM_RCOMP_VOL

SMDDR_VREF_MCH

HP request

MCH_CLVREF

CLKREQ#_B(17)
MCH_ICH_SYNC#(14)

R172
20K

1 2

1 2

4

MCH_DREFCLK(17)
MCH_DREFCLK#(17)
DREF_SSCLK(17)
DREF_SSCLK#(17)

CLK_MCH_3GPLL(17)
CLK_MCH_3GPLL#(17)

DMI_MRX_ITX_N0(13)
DMI_MRX_ITX_N1(13)
DMI_MRX_ITX_N2(13)
DMI_MRX_ITX_N3(13)

DMI_MRX_ITX_P0(13)
DMI_MRX_ITX_P1(13)
DMI_MRX_ITX_P2(13)
DMI_MRX_ITX_P3(13)

DMI_MTX_IRX_N0(13)
DMI_MTX_IRX_N1(13)
DMI_MTX_IRX_N2(13)
DMI_MTX_IRX_N3(13)

DMI_MTX_IRX_P0(13)
DMI_MTX_IRX_P1(13)
DMI_MTX_IRX_P2(13)
DMI_MTX_IRX_P3(13)

R139
<check lisr & CRB>
For Calero : 255
For Cresstline:1.3K/F
For external VGA:0
ohm

DFGT_VID_0(38)
DFGT_VID_1(38)
DFGT_VID_2(38)
DFGT_VID_3(38)

R144

12

0

CL_CLK0(14)
CL_DATA0(14)
MPWROK(14,31)

ICH_CL_RST0#(14)

R137
0

4

L_IBG

R167

2.4K

1 2

UMA

SMRCOMPP
SMRCOMPN

TV_Y/G(32)
TV_C/R(32)

CRT_HSYNC(27)

DFGT_VR_EN(38)

CFG5

CFG9

CFG
[12:13]

CFG16

CFG19

CFG20

1.8VSUS

12

R198
20/F

12

R199
20/F

R166150/F
R163150/F

+3V

R15675/F
R16275/F
R14975/F

CRT_B(27)
CRT_G(27)
CRT_R(27)

DDCCLK(27)
DDCDATA(27)

CRT_VSYNC(27)

DMI X2 Select
PCI Express

Graphic Lane

XOR/ALLZ/Clock
Un-gating

FSB Dynamic
ODT
DMI Lane
Reversal

SDVO/PCIE
Concurrent
Operation

5

R160
100K

L_IBG

DPST_PWM
LCD_BLON
L_CLKCTLA
L_CLKCTLB
EDIDCLK
EDIDDATA

DISP_ONDISP_ON

L_VBG
L_VREFH
L_VREFL
TXLCLKOUT­TXLCLKOUT+

TXLOUT0­TXLOUT1­TXLOUT2-

TXLOUT0+
TXLOUT1+
TXLOUT2+

R155*150/F

TV_Y/G
TV_C/R

DPST_PWM(18)
LCD_BLON(18)
L_CLKCTLA(4)
L_CLKCTLB(4)
EDIDCLK(18)
EDIDDATA(18)

DISP_ON(18)

TXLCLKOUT-(18)
TXLCLKOUT+(18)

TXLOUT0-(18)
TXLOUT1-(18)
TXLOUT2-(18)

TXLOUT0+(18)
TXLOUT1+(18)
TXLOUT2+(18)

LCD_BLON

T32

PAD

R9562.2K
R9572.2K

DB1A Stage: ADD

CRT_B
CRT_G
CRT_R

DDCCLK

R15039/F

R1391.3K/F

+1.25VM

MCH_CLVREF

C237

0.1U/10V

1 2

5

DDCDATA
CRTIREFCRTIREF

R14539/F

12

R179
1K/F

12

R180
392/F

Low=DMIx2
High=DMIx4(Default)
Low= Reveise Lane
High=Normal operation
00=Reserved.
01=XOR Mode Enabled.
10=ALL-Z Node Enabled.
11=Clock gating Enabled(default).
Low=Dynamic ODT Disable
High=Dynamic ODT Enable(default).
Low=Normal(default).
High=Lane Reversed
Low=Only SDVO or PCIEx1 is operational
(defaults)
High=SDVO and PCIEx1 are operating
simultaneously via PEG port

VSYNC

DB1A :install

+3V

R15110K

1 2

R15310K

1 2

R143*10K

1 2

DB1A:change to
10k

6

U30C

J40

L_BKLT_CTRL

H39

L_BKLT_EN

E39

L_CTRL_CLK

E40

L_CTRL_DATA

C37

L_DDC_CLK

D35

L_DDC_DATA

K40

L_VDD_EN

L41

LVDS_IBG

L43

LVDS_VBG

N41

LVDS_VREFH

N40

LVDS_VREFL

D46

LVDSA_CLK#

C45

LVDSA_CLK

D44

LVDSB_CLK#

E42

LVDSB_CLK

G51

LVDSA_DATA#_0

E51

LVDSA_DATA#_1

F49

LVDSA_DATA#_2

G50

LVDSA_DATA_0

E50

LVDSA_DATA_1

F48

LVDSA_DATA_2

G44

LVDSB_DATA#_0

B47

LVDSB_DATA#_1

B45

LVDSB_DATA#_2

E44

LVDSB_DATA_0

A47

LVDSB_DATA_1

A45

LVDSB_DATA_2

E27

TVA_DAC

G27

TVB_DAC

K27

TVC_DAC

F27

TVA_RTN

J27

TVB_RTN

L27

TVC_RTN

M35

TV_DCONSEL_0

P33

TV_DCONSEL_1

H32

CRT_BLUE

G32

CRT_BLUE#

K29

CRT_GREEN

J29

CRT_GREEN#

F29

CRT_RED

E29

CRT_RED#

K33

CRT_DDC_CLK

G35

CRT_DDC_DATA

F33

CRT_HSYNC

C32

CRT_TVO_IREF

E33

CRT_VSYNC

CRESTLINE_1p0

6

L_CLKCTLA
L_CLKCTLB

DFGT_VR_EN

LVDS

TV VGA

PCI-EXPRESS GRAPHICS

UMA

+3V

SMDDR_VREF_MCH

C633

0.1U/10V

1 2

DB2 stage:add

7

PEG_COMPI

PEG_COMPO

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8

PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8

PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9

PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

R17010K

1 2

R16410K

1 2

1.8VSUS

R192
*10K/F

R1870

R191
*10K/F

PM_EXTTS#1

N43
M43

J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
AD44
AD40
AG46
AH49
AG45
AG41

J50
L50
M47
U44
T49
T41
W45
W41
AB50
Y48
AC45
AC41
AH47
AG49
AH45
AG42

N45
U39
U47
N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44

M45
T38
T46
N50
R51
U43
W42
Y47
Y39
AC38
AD47
AC50
AD43
AG39
AE50
AH43

DB2 stage:R164 installPV stage:install for

SMDDR_VREF

R158*0

PM_EXTTS#0
PM_EXTTS#1

8

R16924.9/F

1 2

SMDDR_VREF(16,37)

PM_DPRSLPVR(14,39)

PROJECT : OT2

SizeDocument NumberRev

Date:Sheet of

Quanta Computer Inc.

Crestline(VGA,DMI)

7

742Thursday, March 22, 2007

8

+VCC_PEG

1ACustom

1

2

3

4

5

6

7

8

AA

DDR_A_D[0..63](16)

BB

CC

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

AR43

AW44

BA45
AY46
AR41
AR45
AT42

AW47

BB45
BF48
BG47

BJ45
BB47
BG50
BH49
BE45

AW43

BE44
BG42
BE40
BF44
BH45
BG40
BF40
AR40

AW40

AT39

AW36
AW41

AY41
AV38
AT38
AV13
AT13

AW11

AV11
AU15
AT11
BA13
BA11
BE10
BD10

BD8
AY9

BG10

AW9

BD7
BB9
BB5
AY7
AT5
AT7
AY6
BB7
AR5
AR8
AR9
AN3

AM8

AN10

AT9
AN9

AM9

AN11

U30D

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

CRESTLINE_1p0

DDR_A_BS0

BB19

SA_BS_0
SA_BS_1
SA_BS_2

SA_CAS#
SA_DM_0

SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6

SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8

SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14

SA_RAS#

SA_RCVEN#

DDR SYSTEM MEMORY A

SA_WE#

BK19
BF29

BL17
AT45

BD44
BD42
AW38
AW13
BG8
AY5
AN6

AT46
BE48
BB43
BC37
BB16
BH6
BB2
AP3
AT47
BD47
BC41
BA37
BA16
BH7
BC1
AP2

BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16
BJ29

BE18
AY20

BA19

DDR_A_BS1
DDR_A_BS2

DDR_A_CAS#
DDR_A_DM0

DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14

DDR_A_RAS#

DDR_A_WE#

*PAD

T51

DDR_A_BS0(16)
DDR_A_BS1(16)
DDR_A_BS2(16)

DDR_A_CAS#(16)
DDR_A_DM[0..7](16)

DDR_A_DQS[0..7](16)

DDR_A_DQS#[0..7](16)

DDR_A_MA[0..14](16)

BJ29 renamed to
SA_MA14 pin for intel
update 6/9

DDR_A_RAS#(16)

DDR_A_WE#(16)

AP49

AR51
AW50
AW51

AN51

AN50

AV50

AV49

BA50

BB50

BA49

BE50

BA51

AY49

BF50
BF49
BJ50
BJ44
BJ43

BL43
BK47
BK49
BK43
BK42

BJ41

BL41

BJ37

BJ36
BK41

BJ40

BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12

BJ10

BK10

BH5

BG1

BC2
BK3
BE4
BD3

BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2

BL9
BK5
BL5
BK9

BJ8
BJ6
BF4

BJ2

U30E

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

CRESTLINE_1p0

AY17

SB_BS_0

BG18

SB_BS_1

BG36

SB_BS_2

BE17

SB_CAS#

AR50

SB_DM_0

BD49

SB_DM_1

BK45

SB_DM_2

BL39

SB_DM_3

BH12

SB_DM_4

BJ7

SB_DM_5

BF3

SB_DM_6

AW2

SB_DM_7

AT50

SB_DQS_0

BD50

SB_DQS_1

BK46

SB_DQS_2

BK39

SB_DQS_3

BJ12

SB_DQS_4

BL7

SB_DQS_5

BE2

SB_DQS_6

AV2

SB_DQS_7

AU50

SB_DQS#_0

BC50

SB_DQS#_1

BL45

SB_DQS#_2

BK38

SB_DQS#_3

BK12

SB_DQS#_4

BK7

SB_DQS#_5

BF2

SB_DQS#_6

AV3

SB_DQS#_7

BC18

SB_MA_0

BG28

SB_MA_1

BG25

SB_MA_2

AW17

SB_MA_3

BF25

SB_MA_4

BE25

SB_MA_5

BA29

SB_MA_6

BC28

SB_MA_7

AY28

SB_MA_8

SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14

SB_RAS#

SB_RCVEN#

SB_WE#

BD37
BG17
BE37
BA39
BG13
BE24
AV16
AY18

BC17

BE24 renamed to
SB_MA14 pin for intel
update 6/9

DDR SYSTEM MEMORY B

DD

PROJECT : OT2

SizeDocument NumberRev

1

2

3

4

5

6

Date:Sheet of

Quanta Computer Inc.

Crestline(DDR2)

7

842Thursday, March 22, 2007

8

1ACustom

5

+1.05V

DD

1.8VSUS

CC

+VCCGFX

BB

AA

AT35

AT34
AH28
AC32
AC31
AK32

AJ31

AJ28
AH32
AH31
AH29

AF32

AU32
AU33
AU35
AV33

AW33
AW35

AY35
BA32
BA33
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35

BF33

BF34
BG32
BG33
BG35
BH32
BH34
BH35

BJ32

BJ33

BJ34
BK32
BK33
BK34
BK35

BL33
AU30

W13

W14
AA20

AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28

AF21

AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31

AJ20
AN14

R30

R20
T14

Y12

U30G

VCC_1
VCC_2
VCC_3
VCC_5
VCC_4
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

VCC_13

VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34

VCC CORE

POWER

VCC SMVCC GFX

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8

VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55

VCC GFX NCTF

VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

VCC SM LF

T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31

AW45
BC39
BE39
BD17
BD4
AW8
AT6

VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7

4

Layout Note:
370 mils
from edge.

12

+

C429
330U/6.3V

Layout Note:
Inside GMCH
cavity for
VCC_AXG.

12

C216

0.1U/10V

12

C251

0.1U/10V

+

12

C204
330U/6.3V

12

C233

0.1U/10V

12

C258

0.1U/10V

Layout Note:
370 mils from edge.

+VCCGFX

12

C227

0.47U/10V

12

C269

0.22U/10V

+1.05V

12

C212
1U/10V

12

C270

0.22U/10V

+VCCGFX

12

C210
10U/6.3V

12

C276

0.47U/10V

12

+

C425
220U/2.5V

3

12

C223
22U/4V

Layout Note:
Inside GMCH cavity.

12

C228
22U/4V

+1.05VM

12

12

C267
1U/10V

+3V

R15710

+VCC_GMCH_L

1 2

12

*SHORT PAD

B2_DET(11)

BL1_DET(11)

BL51_DET(11)

A51 _DET(11)

Layout Note:
Place close to GMCH edge.

C259
1U/10V

12

C217

0.22U/10V

+VCCGFX

JP2

1 2

Layout Note:
Inside GMCH cavity.

12

C238

0.1U/10V

12

C442
22U/4V

C214

0.22U/10V

12

12

D10

CH751H-40HPT

12

C225

0.1U/10V

+1.05V

B2_DET

BL1_DET

BL51_DET

A51 _DET

12

C234

0.1U/10V

12

C249

0.22U/10V

1.8VSUS

Layout Note:
Place C2630 where
LVDS and DDR2 taps.

C243

0.1U/10V

C253

0.22U/10V

12

C461

0.1U/10V

2

21

U30F

AB33

VCC_NCTF_1

AB36

VCC_NCTF_2

AB37

VCC_NCTF_3

AC33

VCC_NCTF_4

AC35

VCC_NCTF_5

AC36

VCC_NCTF_6

AD35

VCC_NCTF_7

AD36

VCC_NCTF_8

AF33

VCC_NCTF_9

AF36

VCC_NCTF_10

AH33

VCC_NCTF_11

AH35

VCC_NCTF_12

AH36

VCC_NCTF_13

AH37

VCC_NCTF_14

AJ33

VCC_NCTF_15

AJ35

VCC_NCTF_16

AK33

VCC_NCTF_17

AK35

VCC_NCTF_18

AK36

VCC_NCTF_19

AK37

VCC_NCTF_20

AD33

VCC_NCTF_21

AJ36

VCC_NCTF_22

AM35

VCC_NCTF_23

AL33

VCC_NCTF_24

AL35

VCC_NCTF_25

AA33

VCC_NCTF_26

AA35

VCC_NCTF_27

AA36

VCC_NCTF_28

AP35

VCC_NCTF_29

AP36

VCC_NCTF_30

AR35

VCC_NCTF_31

AR36

VCC_NCTF_32

Y32

VCC_NCTF_33

Y33

VCC_NCTF_34

Y35

VCC_NCTF_35

Y36

VCC_NCTF_36

Y37 A3

VCC_NCTF_37VSS_SCB1

T30

VCC_NCTF_38

T34

VCC_NCTF_39

T35

VCC_NCTF_40

U29

VCC_NCTF_41

U31

VCC_NCTF_42

U32

VCC_NCTF_43

U33

VCC_NCTF_44

U35

VCC_NCTF_45

U36

VCC_NCTF_46

V32

VCC_NCTF_47

V33

VCC_NCTF_48

V36

VCC_NCTF_49

V37

VCC_NCTF_50

AL24

VCC_AXM_NCTF_1

AL26

VCC_AXM_NCTF_2

AL28

VCC_AXM_NCTF_3

AM26

VCC_AXM_NCTF_4

AM28

VCC_AXM_NCTF_5

AM29

VCC_AXM_NCTF_6

AM31

VCC_AXM_NCTF_7

AM32

VCC_AXM_NCTF_8

AM33

VCC_AXM_NCTF_9

AP29

VCC_AXM_NCTF_10

AP31

VCC_AXM_NCTF_11

AP32

VCC_AXM_NCTF_12

AP33

VCC_AXM_NCTF_13

AL29

VCC_AXM_NCTF_14

AL31

VCC_AXM_NCTF_15

AL32

VCC_AXM_NCTF_16

AR31

VCC_AXM_NCTF_17

AR32

VCC_AXM_NCTF_18

AR33

VCC_AXM_NCTF_19

CRESTLINE_1p0

12

+

C313
330U/6.3V

VCC NCTF

POWER

VCC AXM NCTF

12

C288
22U/4V

Layout Note:
Place on the edge.

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16

VSS NCTF

VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21

VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6

VSS SCBVCC AXM

VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_5
VCC_AXM_6
VCC_AXM_7

12

C287
22U/4V

1

T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28

B2_DET

B2
C1

BL1_DET

BL1

BL51_DET

BL51

A51 _DET

A51

+1.05VM

AT33
AT31
AK29
AK24
AK23
AJ26
AJ23

CRESTLINE_1p0

5

PROJECT : OT2

SizeDocument NumberRev

4

3

2

Date:Sheet of

Quanta Computer Inc.

Crestline_D(VCC,NCTF)

1

942Thursday, March 22, 2007

1ACustom

5

FB_180ohm+-25%_100mHz_1500mA_0.09ohm DC

+3V

DD

+1.25VM

L30
BLM11A121S

L31
BLM11A121S

R186

0.5/F/0603

1 2

+VCCA_MPLL_L

12

C255
22U/10V

CC

+1.25V

FB_220ohm+-25%_100MHz
_2A_0.1ohm DC

BB

22nF & 0.1uF for
VCC_TVDACA:C_R should
be placed with in 250
mils from Crestline.

+VCC_TVBG_R

AA

+1.5V

TV DAC Voltage Follower Circuit -700 mV.

L17

1 2

BLM18PG181SN1

45mA MAx.

FB_120ohm+-25%_100mHz
_200mA_0.2ohm DC

+VCCA_HPLL

12

12

12

+VCCA_MPLL

12

BLM21PG221SN1D

D9

2 1

*CH751H-40HPT

C245

C250

0.1U/10V

22U/10V

12

C244

0.1U/10V

L29

1 2

FB_180ohm+-25%_100mHz_1500mA_0.09ohm DC

L16

+3V

1 2

BLM18PG181SN1

R1210

1 2

+VCC_TVDAC_L

5

+VCCA_CRTDAC

+1.25VM

+VCCA_PEG_PLL

12

R177
1/F/0603

12

C219
10U/6.3V

+VCC_TVBG

12

C154

C149

0.1U/10V

*22nF

R128*10

1 2

12

C185

0.1U/10V

+1.25V

0.1Caps should be
placed 200 mils
with in its pins.

+1.25VM

R1180/F

+3V

L26
10uH/100MA

R1890

12

C220

0.1U/10V

12

C181
10U/4V

12

40mA MAx.

10uH+-20%_100mA

12

L28

12

10uH/100MA

12

C454

+

100U/6.3V

12

C271
22U/4V

+1.25VM

12

C242

0.1U/10V

+VCC_TVDACA

12

C160

0.1U/10V

+VCC_TVDACB

12

C162

0.1U/10V

+VCC_TVDACC

12

C165

0.1U/10V

R1350

+VCCA_DPLLA

12

C201

+

470U/4V

+VCCA_DPLLB

12

C273

+

470U/4V

12

4

+VCCA_CRTDAC_R

C190

*22nF

1 2

12

C197

0.1U/10V

12

C207

0.1U/10V

C241

4.7U/6.3V

1 2

12

C260
1U/10V

1.8VSUS

C215

0.1U/10V

R1230

R1290

R1310

4

+3V

12

C176

0.1U/10V

+3V

12

12

C261
22U/4V

12

C272
1U/10V

R1380

+VCC_TVDACA_R

C166

*22nF

1 2

+VCC_TVDACB_R

C175

*22nF

1 2

+VCC_TVDACC_R

C183

*22nF

1 2

C191
1000P/50V

C202

0.1U/10V

12

C264
22U/4V

12

C278

0.1U/10V

+VCCA_CRTDAC_R

+VCC_TVBG_R

+VCCA_DPLLA
+VCCA_DPLLB
+VCCA_HPLL
+VCCA_MPLL

+VCC_TX_LVDS

12

+VCCA_PEG_PLL

12

C240
1U/10V

+VCCA_SM_CK
+VCC_TVDACA_R
+VCC_TVDACB_R
+VCC_TVDACC_R

+VCCD_TVDAC_R

+VCCQ_TVDAC_R

+VCCA_PEG_PLL

12

C205
1U/10V

+1.5V

L18

1 2

BLM18PG181SN1

FB_180ohm+-25%_
100mHz_1500mA_

0.09ohm DC

U30H

J32
A33

B33

A30
B32

B49

H49

AL2

AM2

A41
B41

K50
K49

U51

AW18

AV19
AU19
AU18
AU17

AT22
AT21
AT19
AT18

AT17
AR17
AR16

BC29
BB29

C25

B25

C27

B27
B28
A28

M32

L29
N28
AN2
U48

J41
H42

12

C187
10U/6.3V

+VCCQ_TVDAC

3

VCCSYNC
VCCA_CRT_DAC_1

VCCA_CRT_DAC_2

VCCA_DAC_BG
VSSA_DAC_BG

VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_MPLL

VCCA_LVDS
VSSA_LVDS

VCCA_PEG_BG
VSSA_PEG_BG

VCCA_PEG_PLL

VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5

VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
VCCA_SM_10
VCCA_SM_11
VCCA_SM_NCTF_1
VCCA_SM_NCTF_2

VCCA_SM_CK_1
VCCA_SM_CK_2

VCCA_TVA_DAC_1
VCCA_TVA_DAC_2
VCCA_TVB_DAC_1
VCCA_TVB_DAC_2
VCCA_TVC_DAC_1
VCCA_TVC_DAC_2

VCCD_CRT
VCCD_TVDAC

VCCD_QDAC
VCCD_HPLL
VCCD_PEG_PLL
VCCD_LVDS_1

VCCD_LVDS_2

+VTTLF1
+VTTLF2
+VTTLF3

12

C164

0.1U/10V

12

C182

0.1U/10V

3

CRTPLLA PEGA SMTV

POWER

A CK A LVDS

D TV/CRTLVDS

C232

0.47U/10V

R1300

C659
.1U

1 2

12

C200

0.47U/10V

C177

*22nF

12

R133100

SI stage:change R133 to 100ohm and
C658,C659,C184 install

VTT

VCC_AXD_1
VCC_AXD_2
VCC_AXD_3
VCC_AXD_4
VCC_AXD_5
VCC_AXD_6

AXD

VCC_AXD_NCTF

VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

AXF

VCC_DMI

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

SM CK

VCC_TX_LVDS

VCC_HV_1
VCC_HV_2

HV

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5

PEG

VCC_RXR_DMI_1
VCC_RXR_DMI_2

DMI

VTTLF

CRESTLINE_1p0

12

+VCCD_TVDAC_R

+VCCQ_TVDAC_R

C658
1U

C184

22nF

1 2

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8

VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22

VTTLF1
VTTLF2
VTTLF3

C196

0.47U/10V

U13
U12
U11
U9
U8
U7
U5
U3
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1

AT23
AU28
AU24
AT29
AT25
AT30

AR29

B23
B21
A21

AJ50

BK24
BK23
BJ24
BJ23

A43

C40
B40

AD51
W50
W51
V49
V50

AH50
AH51

A7
F2
AH1

+VCC_AXF

+VCC_SM_CK

+VCC_TX_LVDS

+VCC_RXR_DMI

+VTTLF1
+VTTLF2
+VTTLF3

2

12

C221

2.2U/6.3V

12

C188

4.7U/10V

Place on the edge.

12

C226

0.47U/6.3V

12

C231

4.7U/10V

Place on the edge.

+VCC_AXD_L

12

C257
1U/10V

+3V

12

C199

0.1U/10V

2

1 2

12

C457
22U/10V

Place caps close
to VCC_AXD.

12

C195
1000P/50V

+VCC_PEG

12

+

C282
220U/4V

12

+

C447
220U/4V

+VCC_SM_CK

12

C456
22U/10V

1

+1.05V

21

+VCC_HV_L

12

R127
*10

+3V

+1.25V

R140

+VCC_AXF

C193
1U/10V

1.8VSUS

12

C194
10U/6.3V

1.8VSUS

12

Place caps close
to VCC_AXF

0

+1.05V

12

+

C198
220U/4V

L320

Reserved L2612 pad
for inductor.

+1.25V

12

C224

0.1U/10V

1uH+-20%_300mA

L25

12

1uH/300MA

12

+

C192
220U/4V

L38

12

91nH/1.5A

91uH+-20%_1.5A

12

C222
10U/6.3V

L34

12

91nH/1.5A

91uH+-20%_1.5A

12

C229
10U/6.3V

L39
1uH/300mA

12

1uH+-20%_300mA

C281

0.1U/10V

R196
1/F/0603

+VCC_SM_CK_L

12

C285
10U/6.3V

12

+1.05V

+1.25VM

12

VCC_HV

D8
*CH751H-40HPT

+1.05V

PROJECT : OT2

SizeDocument NumberRev

Date:Sheet of

Quanta Computer Inc.

Crestline_E(POWER)

1

1042Thursday, March 22, 2007

1ACustom

5

4

3

2

1

SI stage: add test pin

U30I

A13

VSS_1

A15

VSS_2

A17

VSS_3

A24

VSS_4

AA21

VSS_5

AA24

VSS_6

AA29

VSS_7

DD

CC

BB

AA

AB20
AB23
AB26
AB28
AB31
AC10
AC13

AC3
AC39
AC43
AC47

AD1
AD21
AD26
AD29

AD3
AD41
AD45
AD49

AD5
AD50

AD8
AE10
AE14

AE6

AF20
AF23
AF24
AF31

AG2
AG38
AG43
AG47
AG50

AH3
AH40
AH41

AH7

AH9

AJ11
AJ13
AJ21
AJ24
AJ29
AJ32
AJ43
AJ45

AJ49
AK20
AK21
AK26
AK28
AK31
AK51

AM11
AM13

AM3

AM4
AM41
AM45

AN1
AN38
AN39
AN43

AN5

AN7

AP4
AP48
AP50
AR11

AR2
AR39
AR44
AR47

AR7

AT10
AT14
AT41
AT49

AU1
AU23
AU29

AU3
AU36
AU49
AU51
AV39
AV48

AW1
AW12
AW16

AL1

VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

CRESTLINE_1p0

VSS

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198

AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41

U30J

C46

VSS_199

C50

VSS_200

C7

VSS_201

D13

VSS_202

D24

VSS_203

D3

VSS_204

D32

VSS_205

D39

VSS_206

D45

VSS_207

D49

VSS_208

E10

VSS_209

E16

VSS_210

E24

VSS_211

E28

VSS_212

E32

VSS_213

E47

VSS_214

F19

VSS_215

F36

VSS_216

F4

VSS_217

F40

VSS_218

F50

VSS_219

G1

VSS_220

G13

VSS_221

G16

VSS_222

G19

VSS_223

G24

VSS_224

G28

VSS_225

G29

VSS_226

G33

VSS_227

G42

VSS_228

G45

VSS_229

G48

VSS_230

G8

VSS_231

H24

VSS_232

H28

VSS_233

H4

VSS_234

H45

VSS_235

J11

VSS_236

J16

VSS_237

J2

VSS_238

J24

VSS_239

J28

VSS_240

J33

VSS_241

J35

VSS_242

J39

VSS_243

K12

VSS_245

K47

VSS_246

K8

VSS_247

L1

VSS_248

L17

VSS_249

L20

VSS_250

L24

VSS_251

L28

VSS_252

L3

VSS_253

L33

VSS_254

L49

VSS_255

M28

VSS_256

M42

VSS_257

M46

VSS_258

M49

VSS_259

M5

VSS_260

M50

VSS_261

M9

VSS_262

N11

VSS_263

N14

VSS_264

N17

VSS_265

N29

VSS_266

N32

VSS_267

N36

VSS_268

N39

VSS_269

N44

VSS_270

N49

VSS_271

N7

VSS_272

P19

VSS_273

P2

VSS_274

P23

VSS_275

P3

VSS_276

P50

VSS_277

R49

VSS_278

T39

VSS_279

T43

VSS_280

T47

VSS_281

U41

VSS_282

U45

VSS_283

U50

VSS_284

V2

VSS_285

V3

VSS_286

CRESTLINE_1p0

VSS

VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305

VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313

W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28

AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50

BL1_DET(9)

B2_DET(9)

A51 _DET(9)

BL51_DET(9)

+3V

R202

100K

R203

100K

BL1_DETBL1_DETBL1_DETBL1_DET

R206

T162

*0

+3V

R204

100K

R207

100K

B2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DETB2_DET

R205

T163

*0

+3V

R200

100K

R193

100K

A51 _DET

R194

T164

*0

+3V

R201

R216

100K

BL51_DET

R217

T165

*0

3

2

Q142N7002E

1

3

2

Q132N7002E

1

BGA_MON_DET(14,26)

3

2

Q122N7002E

1

100K

3

2

Q152N7002E

1

PROJECT : OT2

SizeDocument NumberRev

5

4

3

2

Date:Sheet of

Quanta Computer Inc.

Crestline(VSS)

1

1142Thursday, March 22, 2007

1ACustom

1

AA

3VPCU

VCCRTC_2

R415
1K

CN32

1
2

BAT_CONN

BB

ACZ_BITCLK_ADI(22)

ACZ_SYNC_ADI(22)

ACZ_RST_ADI#(22,23)

ACZ_SDIN0(22)
ACZ_SDIN1(30)

ACZ_SDOUT_ADI(22)

ACZ_BITCLK_MDC(30)

ACZ_SYNC_MDC(30)

ACZ_RST_MDC#(30)

CC

ACZ_SDOUT_MDC(30)

VCCRTC

D19
CH500H-40

D18
CH500H-40

C514
*10P

C521
*10P

VCCRTC

R414
20K

R420
1M/F

C526
*10P

C517
*10P

C340
*10P

2

C341
*10P

C4821U

C337
*10P

C485
1U

C339
*22P

12

G1
SHORT_ PAD1

INTRUDER#

R24233
R24433

R47633

R47133
R24033

R24333
R47033
R46433

C335
18P

Y5

32.768KHZ

C336
18P

3

+1.5V_PCIE_ICH

ACZ_SDIN0
ACZ_SDIN1

ACZ_SDOUTACZ_SDOUT

G_BATLED#(29)

CLK_32KX1

R238

10M

2 1

CLK_32KX2

GLAN_CLK(24)

LAN_RSTSYNC(24)

LAN_RXD0(24)
LAN_RXD1(24)

LAN_RXD2(24)
LAN_TXD0(24)
LAN_TXD1(24)
LAN_TXD2(24)

ENERGY_DET(25)

*SHORT PAD

ACZ_BCLK
ACZ_SYNC

ACZ_RST#

JP5

R40124.9/F

1 2

T68
T131

12

R518*24.9/F

4

ICH_INTVRMEN
ICH_LAN100_SLP

GLAN_COMP

T129
T132
T158

T159
T160
T161

T73
T75

T144
T78

T171
T172

SATABIAS

12

+3V

5

VCCRTC VCCRTC

12

R407
332K/F

ICH_INTVRMEN

12

R413
*0

U17A

AG25

RTCX1

AF24

RTCX2

AF23

RTCRST#

AD22

INTRUDER#

AF25

INTVRMEN

AD21

LAN100_SLP

B24

GLAN_CLK

D22

LAN_RSTSYNC

C21

LAN_RXD0

B21

LAN_RXD1

C22

LAN_RXD2

D21

LAN_TXD0

E20

LAN_TXD1

C20

LAN_TXD2

AH21

GLAN_DOCK#/GPIO13

D25

GLAN_COMPI

C25

GLAN_COMPO

AJ16

HDA_BIT_CLK

AJ15

HDA_SYNC

AE14

HDA_RST#

AJ17

HDA_SDIN0

AH17

HDA_SDIN1

AH15

HDA_SDIN2

AD13

HDA_SDIN3

AE13

HDA_SDOUT

AE10

HDA_DOCK_EN#/GPIO33

AG14

HDA_DOCK_RST#/GPIO34

AF10

SATALED#

AF6

SATA0RXN

AF5

SATA0RXP

AH5

SATA0TXN

AH6

SATA0TXP

AG3

SATA1RXN

AG4

SATA1RXP

AJ4

SATA1TXN

AJ3

SATA1TXP

AF2

SATA2RXN

AF1

SATA2RXP

AE4

SATA2TXN

AE3

SATA2TXP

AB7

SATA_CLKN

AC6

SATA_CLKP

AG1

SATARBIAS#

AG2

SATARBIAS

ICH8M REV 1.0

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

FWH4/LFRAME#

RTCLAN / GLANIHDASATA

LPC

LDRQ1#/GPIO23

CPUPWRGD/GPIO49

CPU

THRMTRIP#

IDE

LDRQ0#

A20GATE

A20M#

DPRSTP#

DPSLP#

FERR#

IGNNE#

INIT#
INTR

RCIN#

SMI#

STPCLK#

DD10
DD11
DD12
DD13
DD14
DD15

DCS1#
DCS3#

DIOR#

DIOW#

DDACK#

IDEIRQ

IORDY

DDREQ

NMI

TP8
DD0

DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9

DA0
DA1
DA2

E5
F5
G8
F6

C4
G9

E6
AF13

AG26
AF26

AE26
AD24
AG29
AF27
AE24

AC20
AH14

AD23
AG28

AA24
AE27
AA23
V1

U2
V3
T1
V4
T5
AB2
T6
T3
R2
T4
V6
V5
U1
V2
U6

AA4
AA1
AB3

Y6
Y5

W4
W3
Y2
Y3
Y1
W5

LAD0/FWH0
LAD1/FWH1
LAD2/FWH2
LAD3/FWH3

LFRAME#/FWH4

H_FERR#

KBCCPURST#

THERMTRIP#_ICH

PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8

PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

PDA0

PDA1

PDA2

PDCS1#
PDCS3#

6

12

R421
332K/F

ICH_LAN100_SLP

12

R424
*0

T136PAD
T141PAD

GATEA20

R3930/F
R3960/F

R1260/F

T121PAD

LFRAME#/FWH4(26,30)

GATEA20(26)
H_A20M#(4)

H_DPRSTP#
H_DPSLP#

H_FERR#(4)

H_PWRGOOD(4)
H_IGNNE#(4)
H_INIT#(4)

H_INTR(4)

H_NMI(4)
H_SMI#(4)

H_STPCLK#(4)

R38424.9/F

PDIOR#(28)
PDIOW#(28)
PDDACK#(28)
IRQ14(28)
PDIORDY(28)
PDDREQ(28)

7

LAD0/FWH0(26,30)
LAD1/FWH1(26,30)
LAD2/FWH2(26,30)
LAD3/FWH3(26,30)

H_DPRSTP#(4,7)
H_DPSLP#(4)

KBCCPURST#(26)

PDD[15:0](28)

PDA[2:0](28)

PDCS1#(28)
PDCS3#(28)

H_DPRSTP#
H_DPSLP#
H_FERR#

GATEA20
KBCCPURST#

R383

1 2

56

+3V

R958

8.2K

R959

4.7K

1 2

R390
*56

+1.05V

8

+1.05V

R395
*56

R417

56

1 2

1 2

+3V

R468

R466

10K

10K

1 2

1 2

PM_THRMTRIP#(4,7)

DD

1

2

3

R462
*1K

1 2

ACZ_SDOUT

R239
*1K

1 2

4

ICH_RSVD(14)

PROJECT : OT2

SizeDocument NumberRev

5

6

Date:Sheet of

Quanta Computer Inc.

ICH8(CPU,SATA,IDE)

7

PDIORDY
IRQ14

1242Thursday, March 22, 2007

8

1ACustom

1

MINI CARD PCI-E

AA

SPI_CLK(31)
SPI_CS0#(31)

SPI_CS1#(14,26)

SI2 stage:Change power source to avoid leakage
current

BB

USBOC#3
USBOC#4

3V_S5

CC

DD

USBOC#0

USBOC#6

SI stage:Change power source to avoid leakage current

USBOC#9

AD[31..0](20)

RP31

6
7
8
9

10

8.2KX8

3V_S5

R241

8.2K

INTC#(20)
INTD#(20)

1

5
4
3
2
1

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

2

PCIE_RXN2(19)
PCIE_RXP2(19)

PCIE_TXN2(19)
PCIE_TXP2(19)

3

C4660.1U
C4650.1U

Intel LAN

PCIE_RXN6(24)

PCIE_RXP6(24)
PCIE_TXN6(24)
PCIE_TXP6(24) USBP1-(30)

PV stage:change R399 to 15 ohm for intel request

SPI_SI(31)

SPI_SO(31)

BT_OFF(30)

3V_S5

USBOC#7
USBOC#2
USBOC#1
USBOC#8

WWAN_OFF#(19)

USBOC#0
USBOC#2
USBOC#4
USBOC#6
USBOC#7
USBOC#8
USBOC#9

SI stage:add to avoid WWAN Noise

U17B

D20

AD0

E19
D19
A20
D17
A21
A19
C19
A18
B16
A12
E16
A14
G16
A15

B6

C11

A9
D11
B12
C12
D10

C7

F13
E11
E13
E12

D8
A6
E8
D6
A3

INTA#

F9

INTB#

B5

INTC#

C5

INTD#

A10 B3

2

PCI

AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

Interrupt I/F

PIRQA#
PIRQB#
PIRQC#
PIRQD#PIRQH#/GPIO5

ICH8M REV 1.0

REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55

PIRQE#/GPIO2
PIRQF#/GPIO3

PIRQG#/GPIO4

C4680.1U
C4670.1U

R39815
R40315
R41015

R39915

R4090/F

R4560/F
R4550/F

C6440.1U/10V
C6460.1U/10V
C6470.1U/10V
C6490.1U/10V
C6500.1U/10V
C6510.1U/10V
C6520.1U/10V

A4

REQ0#

D7

GNT0#

E18
C18
B19
F18
A11
C10

C17

C/BE0#

E15

C/BE1#

F16

C/BE2#

E17

C/BE3#

C8

IRDY#

D9

PAR

G6

PCIRST#

D16

DEVSEL#

A7

PERR#

B7

PLOCK#

F10

SERR#

C16

STOP#

C9

TRDY#

A17

FRAME#

AG24

PLTRST#

B10

PCICLK

G7

PME#

F8
G11
F12

1 2
1 2
1 2
1 2
1 2
1 2
1 2

REQ0#
GNT0#GNT0#
REQ1#
GNT1#
REQ2#
GNT2#
REQ3#
GNT3#

CLK_PCI_ICH

3

C/BE0#
C/BE1#
C/BE2#
C/BE3#

IRDY#
PAR
PCI_RST#_G
DEVSEL#
PERR#
LOCK#
SERR_1#
STOP#
TRDY#
FRAME#

PCI_PME#

INTE#
INTF#
INTG#
SES_INT

PCIE_RXN2
PCIE_RXP2
PCIE_TXN2_C
PCIE_TXP2_C

PCIE_RXN6
PCIE_RXP6
PCIE_TXN6_C
PCIE_TXP6_C

SPI_CS1_R#

USBOC#0
USBOC#1
USBOC#2
USBOC#3
USBOC#4
USBOC#5
USBOC#6

USBOC#8
USBOC#9

PLT_RST-R#

T74PAD
T140PAD
T127PAD
T123PAD

T70PAD
T134PAD

C/BE0#(20)
C/BE1#(20)
C/BE2#(20)
C/BE3#(20)

IRDY#(20)
PAR(20)

DEVSEL#(20)
PERR#(20)

SERR_1#(20)
STOP#(20)
TRDY#(20)
FRAME#(20)

INTE#(20)

U17D

P27
P26
N29
N28

M27
M26

L29
L28

K27
K26

J29
J28

H27
H26
G29
G28

F27
F26
E29
E28

D27
D26
C29
C28

C23
B23
E22

D23
F21

AJ19
AG16
AG15
AE15

AF15
AG17
AD12

AJ18
AD14
AH18

ICH8M REV 1.0

REQ2#(20)
GNT2#(20)

CLK_PCI_ICH(17)
PCI_PME#(20)

SES_INT(27)

4

PERN1
PERP1
PETN1
PETP1

PERN2
PERP2
PETN2
PETP2

PERN3
PERP3
PETN3
PETP3

PERN4
PERP4
PETN4
PETP4

PERN5
PERP5
PETN5
PETP5

PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP

SPI_CLK
SPI_CS0#
SPI_CS1#

SPI_MOSI
SPI_MISO

OC0#
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
OC8#
OC9#

Short F2 and F3 at the package
and keep length to less than
500mils. Trace Impedance
should be 60ohms +/- 15%.

SPI_CS1_R#
GNT0#

PCI-Express

SPI

USB

DMI0RXN
DMI0RXP
DMI0TXN

DMI0TXP

DMI1RXN
DMI1RXP
DMI1TXN

DMI1TXP

DMI2RXN
DMI2RXP
DMI2TXN

DMI2TXP

DMI3RXN
DMI3RXP
DMI3TXN

DMI3TXP

DMI_CLKN
DMI_CLKP

Direct Media Interface

DMI_ZCOMP

DMI_IRCOMP

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

USBRBIAS#

USBRBIAS

R501
1K

1 2

1 2

PCI DEVICES IRQ ROUTING

DEVICEREQ/GNT #

PLT_RST-R#(7)

4

R411
*1K

5

V27
V26
U29
U28

Y27
Y26
W29
W28

AB26
AB25
AA29
AA28

AD27
AD26
AC29
AC28

T26
T25

Y23
Y24

G3
G2
H5
H4
H2
H1
J3
J2
K5
K4
K2
K1
L3
L2
M5
M4
M2
M1
N3
N2

F2
F3

DMI_COMP

USBP0­USBP0+

USBP1+
USBP2­USBP2+
USBP3­USBP3+

USBP5­USBP5+
USBP6­USBP6+
USBP7­USBP7+
USBP8­USBP8+
USBP9-USBOC#7
USBP9+

USBRBIAS

T155PAD
T156PAD

1 2

DMI_MTX_IRX_N0(7)
DMI_MTX_IRX_P0(7)

DMI_MRX_ITX_N0(7)
DMI_MRX_ITX_P0(7)

DMI_MTX_IRX_N1(7)
DMI_MTX_IRX_P1(7)

DMI_MRX_ITX_N1(7)
DMI_MRX_ITX_P1(7)

DMI_MTX_IRX_N2(7)
DMI_MTX_IRX_P2(7)

DMI_MRX_ITX_N2(7)
DMI_MRX_ITX_P2(7)

DMI_MTX_IRX_N3(7)
DMI_MTX_IRX_P3(7)

DMI_MRX_ITX_N3(7)
DMI_MRX_ITX_P3(7)

CLK_PCIE_ICH#(17)
CLK_PCIE_ICH(17)

R41224.9/F

12

USBP1+(30)

T77PAD
T76PAD
T149PAD
T145PAD

USBP7-(32)

USBP7+(32)

USBP8-(19)

USBP8+(19)

T146PAD
T79PAD

R512

22.6/F

Boot BIOS Strap

GNT0#SPI_CS1#

No stuff
No stuff
Stuff

No stuff
Stuff
No stuff

11LPC
PCI
SPI1001

IDSEL #

AD22CardBus2

CLK_PCI_ICH

Reserved for EMI.
Place resister and cap
close to ICH.

5

6

+1.5V_PCIE_ICH
USBP0-(30)

USBP0+(30)

FINGER PRINT

DB1A stage:change for HP
request

USBP5-(30)

USBP5+(30)
USBP6-(30)
USBP6+(30)

Docking

Place within 500mils of ICH8

SYSTEM(RIGHT)

SYSTEM(LEFT)

Bluetooth Module

WWAN

PCI_INT

C,D,E

R479
*10

1 2

C525
*8.2P/16V

1 2

6

7

D33

SERR_1#SERR#

2 1

CH751H-40HPT

SERR#(26)

SI stage:add to avoid leakage currurt

+3V

PCI_RST#_G

PLT_RST-R#

3V_S5

+3V

+3V

C539

1 2

0.047U/10V

C490

1 2

0.047U/10V

R4488.2K

SI stage:Change power source to avoid leakage current

USBOC#5(30)

STOP#

INTF#
INTG#
REQ3#
INTD#

IRDY#

INTA#
INTE#
LOCK#

+3V

5

U36

2
1

7SH32

R489*0

+3V

5

U32

2
1

7SH32

USBOC#5

+3V

RP30

6
7
8
9

10

8.2KX8

RP32

6
7
8
9

10

8.2KX8

RP33

6
7
8
9

10

8.2KX8

Add Buffers as needed for
Loading and fanout concerns.

5

REQ2#

4

REQ1#

3

FRAME#

2

DEVSEL#

1

+3V

5
4
3

TRDY#

2

SERR_1#

1

+3V

5

REQ0#

4

INTB#

3

INTC#

2

PERR#

1

4

R990
100K

DB1A stage:add

4

R991
100K

PLTRST#(19,26,28,30)

PROJECT : OT2

SizeDocument NumberRev

Date:Sheet of

Quanta Computer Inc.

ICH8(USB,PCIE,DMI)

7

1342Thursday, March 22, 2007

8

PCIRST#(20)

1ACustom

8

+3V

AA

DB1A stage:change R487 to 8.2K ,and pull
up to

DB1A stage:add R962 refer to
Oak schematic

DB1A stage:change R473 to 10k refer to
intel schematic

BB

DB1A stage:delete
Q32,R394,add U46,C628 to
control VRMPWRGD

CC

DD

1

Option to " Disable "
clkrun. Pulling it down
will keep the clks
running.

R481

8.2K

1 2

CLKRUN#

12

R482
*10

+3V

SLP_S3#(26,31)

LAN_LINKLED#(24,25,32)

SI stage:add R1028 ,Q62,reserve R1029 for
auto power on issue

SDATAOUT0

R48510K

SATA3GP

R4878.2K

SERIRQ

R47310K

SDATAOUT1

R48310K

RUNSCI_EC#

R49010K

SLOAD

R4801K

THERM_ALERT#(4)

C628.1U/16V/04

CLK_PWRGD

PCSPK(22)

PR_INSERT_DOCK#(25,32) PR_INSERT#(22,27)

R246
*10K

1 2

3V_S5

RP29

1
3

4P2R-2.2K

1

+3V

U46

1
2

NL17SZ14DFT2G

R940*0

+3V

DB1A stage:add for
pr_insert_dock#

MCH_ICH_SYNC#_R

DB1A stage:change to
3V_S5

PDAT_SMB

2

PCLK_SMB

4

2

12
12

12
12
12

5

SI2 stage:add R1049 to modify CLK_PWRGD timing to avoid CPU frequency
error

43

PV stage:add option (Add R1066)from LAN_PHYPC and
reserve R1065

R492
*10K

1 2

2

3V_S5

R1028

10K

1 2

SMBALERT#

3

Q62

12

2N7002E

R1029

1

DB2 stage:no install R960 to avoid leakage current

+3V

DB2 stage:reserve 0
ohm

PV stage:R442 install for intel suggestion

+3V

H_STP_CPU#(17)

R472
10K/F

R1049

100K_4

RUNSCI_EC#(26)

LAN_PHYPC(25)

SPI_CS1#(13,26)

D24
PDZ5.6B

LID_SW#(18)DELAY_VR_PWRGOOD(7,31,39)

SI2 stage:delete R467 ,add T170 test
point

MCH_ICH_SYNC#(7)

PR_INSERT#

21

R961
10K

+3V

+3V

DB1A stage:Add,refer to

3V_S5

Oak schematic

R97210K

R9698.2K

R96610K

R96210K

R40510K
R425*10K
R45310K

*0

R43510K
R45110K
R423*10K
R4541K
R45210K

R960*8.2K

PCLK_SMB(16,17)
PDAT_SMB(16,17)

ICH_CL_RST1#(19)
ME_EC_CLK(26)
ME_EC_DATA(26)

SUS_STAT#(30)

XDP_DBRESET#(4,31)

H_STP_PCI#(17)

CLKRUN#(20,26,30)

PCIE_WAKE#(19)

SERIRQ(20,26,30)

R3850

R941*0

R10660

12

ALS_EN#(18)

R2470

ICH_RSVD(12)

PCSPK

A1_DET

R515100K

AJ1_DET

R253100K

A29_DET

R219100K

AJ29_DET

R391100K

SI stage: add test pin

2

3

RF_OFF#

12

PM_BATLOW#_R

MPWROK

12

LAN_PHYPC_R

12

CB_IN#CB_IN#

12

ICH_CL_RST1#

12

ME_EC_CLK

12

ME_EC_DATA

12

ICH_RI#

12

OCP#

12

PCIE_WAKE#

12

XDP_DBRESET#

12

SI stage: install to avoid leakage current

PM_BMBUSY#

PCLK_SMB
PDAT_SMB
ICH_CL_RST1#

R10120
R10130

ICH_RI#CLK_ICH_48M

PM_BMBUSY#

SMBALERT#

R4570
R4420

CLKRUN#
PCIE_WAKE#

SERIRQ

T65

PR_INSERT#

12

T71
T133
T139

T138
T72
T135

PCSPK

PCSPKPCSPK

MCH_ICH_SYNC#_R

12

OCP#

LAN_PHYPC_R

SDATAOUT0
SDATAOUT1

OCP#(34)

R1065*0

+3V

DB1A stage:no
install R423,due to
dual pull up

DB1A stage:Add,refer to
Oak schematic

AJ26
AD19
AG21
AC17
AE19

AF17

F4

AD15
AG12
AG22
AE20

12

AG18

12

AH11
AE17

AF12
AC13

AJ20

AJ22

AJ8
AJ9

AH9
AE16
AC19

AG8

GPIO18

AH12

GPIO20

AE11

GPIO22

AG10
AH25

T63

AD16

T157

AG13

T170

SLOAD

AF9

AJ11

AD10

AD9

AJ13
AJ21

No Reboot strap.

Low = Default.
High = No
Reboot.

A1_DET(15)

T166
T167
T168
T169

A29_DET(15)

3

4

R9638.2K
R9648.2K
R9658.2K

R9718.2K

R10520

GPIO18
GPIO22
GPIO20

NPCI_RST#

SI stage: add to avoid leakage current

SI2 stage:delete D32,Add
R1052

U17C

SMBCLK
SMBDATA
LINKALERT#
SMLINK0
SMLINK1

RI#
SUS_STAT#/LPCPD#

SYS_RESET#
BMBUSY#/GPIO0
SMBALERT#/GPIO11
STP_PCI#/GPIO15

STP_CPU#/GPIO25
CLKRUN#/GPIO32
WAKE#

SERIRQ
THRM#

VRMPWRGD
TP7
TACH1/GPIO1

TACH2/GPIO6
TACH3/GPIO7
GPIO8
GPIO12
TACH0/GPIO17
GPIO18
GPIO20
SCLOCK/GPIO22
QRT_STATE0/GPIO27
QRT_STATE1/GPIO28
SATACLKREQ#/GPIO35
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48

SPKR
MCH_SYNC#
TP3

ICH8M REV 1.0

+3V

A1_DET

R516
*0

+3V

A29_DETA29_DETA29_DETA29_DETA29_DETA29_DETAJ29_DET

A29_DET

R224
*0

4

R517

100K

R508

100K

SATA

SMB

SYS

GPIO

Power MGTController Link

GPIO

MISC

3

2

1

3

2

1

DB1A stage:Add,refer to
Oak schematic

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA2GP/GPIO36
SATA3GP/GPIO37

GPIO

Clocks

Q422N7002E

Q182N7002E

SLP_S3#
SLP_S4#
SLP_S5#

S4_STATE#/GPIO26

DPRSLPVR/GPIO16

BATLOW#
PWRBTN#
LAN_RST#

RSMRST#

CK_PWRGD

CLPWROK

CL_CLK0
CL_CLK1

CL_DATA0
CL_DATA1

CL_VREF0
CL_VREF1

CL_RST#

MEM_LED/GPIO24
ME_EC_ALERT/GPIO10
EC_ME_ALERT/GPIO14

WOL_EN/GPIO9

BGA_MON_DET(11,26)

BGA_MON_DET(11,26)

GPIO29(26)

CLK14
CLK48

SUSCLK

PWROK

SLP_M#

AJ1_DET(15)

5

AJ29_DET(15)

5

R9708.2K

AJ12
AJ10

NPCI_RST#

AF11

SATA3GPSATA3GP

AG11

CLK_ICH_14M

AG9
G5

ICH_SUSCLK

D3
AG23

R4300

AF21

R4400

AD18
AH27

ICH_PWROK

AE23

PM_DPRSLPVR_R

AJ14

PM_BATLOW#_R

AE21

NBSWON#

C2
AH20

PM_RSMRST#_R

AG27

R3880

E1

MPWROK

E3

SUSM_1#

AJ25
F23

AE18
F22

AF19

CL_VREF0

D24

CL_VREF1

AH23
AJ23
AJ27

CB_IN#

AJ24
AF22

LAN_WOL_EN

AG19

6

+3VM

R434

R441

*10K

*10K

H_STP_PCI#

H_STP_CPU#

PV stage:no install R441,R434
for intel request

SUSM_1#

R10510

SI2 stage:delete Q61,add R1051

+3V

ACC_LED(29)
NPCI_RST#(26)

T137PAD

CLK_ICH_14M(17)
CLK_ICH_48M(17)

T147PAD

SLP_S3#(26,31)

12

SLP_S4#(37)PM_BMBUSY#(7)

12

SLP_S5#(31)
S4_STATE(40)

ICH_PWROK(31)

DB1A stage:Add

D26

2 1

CH751H-40HPT

R4280

12

R397*0

12

R2310

R1063100K

PV stage:Add for intel suggestion

+3V

R252
*0

+3V

LAN_RST#(25)VR_PWRGD_CLKEN#(39)

R400100/F

CLK_PWRGD(17)

MPWROK(7,31)

CL_CLK0(7)
ICH_CL_CLK1(19)

CL_DATA0(7)
ICH_CL_DATA1(19)

ICH_CL_RST0#(7)

R4080

12

1 2

R511

100K

AJ1_DET

2

R513

100K

2

R389
*0

NBSWON#(31)

RSMRST#

12

LAN_WOL_EN(40)

3V_S5

3

Q412N7002E

1

3

Q312N7002E

1

6

R245
100R

7

Place these close to ICH8.

CLK_ICH_48M

SUSM#(26,31)

CLK_ICH_14M

BATLOW#(26)

RSMRST#(26)

DB1A :reserve 100k
ohm

RF_OFF#(19)

AMT ADP_PRES(26)

BGA_MON_DET(11,26)

BGA_MON_DET(11,26)

PM_DPRSLPVR(7,39)

ICH_PWROK

LAN_WOL_EN
PM_RSMRST#_R

MPWROK

PM_DPRSLPVR_R

DB1A :no install
R418,due to dual layout

R418*10K

R437*100K
R404*10K

R507*1M

R955100K

DET_P(25)

+3VM 3V_S5

CL_VREF0

12

C483

0.1U/10V

1 2

1 2

DB1A stage:delete
R431

R392

3.24K/F

1 2

12

12

R402
453/F

PROJECT : OT2

SizeDocument NumberRev

Date:Sheet of

Quanta Computer Inc.

ICH8(PM,GPIO,SMB)

7

12

12

12

12

12

12

12

CL_VREF1

C486

0.1U/10V

8

R495
*10

C550
*4.7P/50V

R491
*10

C536
*4.7P/50V

1442Thursday, March 22, 2007

8

1 2

12

R416

3.24K/F

R419
453/F

1ACustom

1

VCCRTC

R447100

+5V

+3V

AA

5VPCU

3VPCU

BB

CC

1 2

D22

2 1

CH751H-40HPT

R48410

1 2

D21

2 1

CH751H-40HPT

+1.5V

12

L46
BLM21PG331SN1D

12

+

C297
220U/4V

+1.5V

SI stage:Change footprint to 0805

12

R493
0

+VCCSATPLL_L

12

L49
10uH/100MA

10uH+-20%_100mA

+VCCSATPLL

12

C547
1U/10V

SI stage:Change footprint to 0805

+1.5V

12

R225
1

+VCCGLANPLL_L

12

L43

DD

1uH_800MA

1uH+-20%_800mA

+VCCGLANPLL

C321

2.2U/10V

1 2

1

12

C499
1U/10V

+ICH_V5REF_RUN

C543

0.1U/10V

1 2

+ICH_V5REF_SUS

C531

0.1U/10V

1 2

FB_330ohm+-25%_100mHz_

1.5A_0.09 ohm DC

12

12

12

C320
22U/10V

C542
10U/6.3V

C319
10U/6.3V

12

C316
22U/10V

+1.5V

+3VM

+1.5V_PCIE_ICH

C491

0.1U/10V

1 2

+1.5V_PCIE_ICH

1 2

+1.5V

+1.5V

+1.5V

C548

0.1U/10V

1 2

T128PAD
T124PAD

C493

0.1U/10V

2

C489

2.2U/10V

1 2

12

C481

4.7U/6.3V

2

C494

0.1U/10V

1 2

+VCCSATPLL

12

C540
1U/10V

12

C519
1U/10V

C546

0.1U/10V

1 2

TP_VCCSUSLAN1
TP_VCCSUSLAN2

+VCCGLANPLL

+3V

AD25

AA25
AA26
AA27
AB27
AB28
AB29

W25

AG7
AH7

AC1
AC2
AC3
AC4
AC5

AC10

AC9
AA5

AA6
G12

G17

AC7
AD7

W23

G18

G20

A16

D28
D29
E25
E26
E27
F24
F25
G24
H23
H24

K24
K25
L23
L24
L25
M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27
T23
T24
T27
T28
T29
U24
U25
V23
V24
V25

Y25
AJ6
AE7

AF7

AJ7

F17

F19

A24
A26

A27
B26
B27
B28

B25

T7

G4

J23
J24

H7

D1
F1

L6

L7
M6
M7

U17F

VCCRTC
V5REF[1]

V5REF[2]
V5REF_SUS
VCC1_5_B[01]

VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]

VCCSATAPLL
VCC1_5_A[01]

VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]

VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]
VCC1_5_A[09]
VCC1_5_A[10]

VCC1_5_A[11]
VCC1_5_A[12]

VCC1_5_A[13]
VCC1_5_A[14]

VCC1_5_A[15]
VCC1_5_A[16]
VCC1_5_A[17]

VCC1_5_A[18]
VCC1_5_A[19]

VCCUSBPLL
VCC1_5_A[20]

VCC1_5_A[21]
VCC1_5_A[22]
VCC1_5_A[23]
VCC1_5_A[24]

VCC1_5_A[25]
VCCLAN1_05[1]

VCCLAN1_05[2]
VCCLAN3_3[1]

VCCLAN3_3[2]
VCCGLANPLL
VCCGLAN1_5[1]

VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]
VCCGLAN1_5[5]

VCCGLAN3_3

ICH8M REV 1.0

3

VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]

CORE

VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]
VCC1_05[27]
VCC1_05[28]

VCCA3GP ATXARX

VCCDMIPLL
VCC_DMI[1]

VCC_DMI[2]

V_CPU_IO[1]
V_CPU_IO[2]

VCC3_3[01]
VCC3_3[02]
VCC3_3[03]

VCC3_3[04]
VCC3_3[05]
VCC3_3[06]

VCCP_COREVCCPSUSVCCPUSB

VCC3_3[07]
VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]

IDE

VCC3_3[12]
VCC3_3[13]

VCC3_3[14]
VCC3_3[15]
VCC3_3[16]
VCC3_3[17]
VCC3_3[18]
VCC3_3[19]
VCC3_3[20]

PCI

VCC3_3[21]
VCC3_3[22]
VCC3_3[23]
VCC3_3[24]

VCCHDA

VCCSUSHDA

VCCSUS1_05[1]
VCCSUS1_05[2]

VCCSUS1_5[1]

VCCSUS1_5[2]
VCCSUS3_3[01]
VCCSUS3_3[02]

VCCSUS3_3[03]
VCCSUS3_3[04]
VCCSUS3_3[05]

USB CORE

VCCSUS3_3[06]
VCCSUS3_3[07]

VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]

GLAN POWER

VCCCL1_05

VCCCL1_5

VCCCL3_3[1]
VCCCL3_3[2]

3

4

+1.05V

A13
B13
C13
C14
D14
E14
F14
G14
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

R29
AE28

AE29
AC23

AC24
AF29
AD2
AC8

AD8
AE8
AF8

AA3
U7
V7
W1
W6
W7
Y7

A8
B15
B18
B4
B9
C15
D13
D5
E10
E7
F11

AC12
AD11
J6

AF20
AC16
J7
C3
AC18

AC21
AC22
AG20
AH28

P6
P7
C1
N7
P1
P2
P3
P4
P5
R1
R3
R5
R6

G22
A22
F20

G21

C518

.047U/10V/04

+V_CPU_IO

C544

0.1U/10V

1 2

TP_VCCSUS1.05_1
TP_VCCSUS1.05_2

TP_VCCSUS1.5_1
TP_VCCSUS1.5_2

SI stage:WWAN Noise -ICH improvements

12

C653

0.1U/10V

TP_VCCCL1.05
+VCCCL1_5

+3VM

4

+1.5V_DMIPLL

C472

0.01U/25V

1 2

1 2

1 2

1 2

12

C654

0.1U/10V

C515
.022U/04

C469

10U/6.3V

1 2

C471

0.1U/10V

C480

0.1U/10V

1 2

C470

0.1U/10V

C580

0.1U/10V

T143PAD
T125PAD

T130PAD
T142PAD

12

12

C655

C656

0.1U/10V

0.1U/10V

DB2 stage:change C561,C560,C577 for intel recommend

T122PAD

5

DB1A stage:change for check list

+1.05V +1.5V

1uH+-20%_800mA

L42
1uH_800MA

1 2

+1.25V

12

C464
22U/10V

+3V

C558

0.1U/10V

C578

0.1U/10V

1 2

+3V3V_S5

C545

0.1U/10V

1 2

C487
*0.1U/10V

1 2

5

D20

2 1

*CH751H-40HPT

+1.5V_DMIPLL_R

12

+V_CPU_IO

12

C528

0.1U/10V

C538

0.1U/10V

1 2

12

C561

0.1U

SI stage:change size
to 0805

12

C488
*1U/10V

R422

1 2

*0/0805

R226

1 2

0/0805

12

C484

0.1U/10V

12

C560

0.1U

12

C577

4.7U/10V

+1.5V

3V_S5

6

+1.05V

6

1 2

12

C495

4.7U/10V

R446

0/0805

AB24
AC11
AC14
AC25
AC26
AC27
AD17
AD20
AD28
AD29

AE12
AE22
AE25

AF14
AF16
AF18

AH10
AH13
AH16
AH19

AF28
AH22
AH24
AH26

AA2
AA7
A25
AB1

AD3
AD4
AD6
AE1

AE2
AD1
AE5

AE6
AE9

AF3
AF4
AG5
AG6

AH2

AH3
AH4
AH8
AJ5
B11
B14
B17

B20
B22

C24
C26
C27

D12
D15
D18

E21
E24

E23

G10
G13
G19
G23
G25
G26
G27
H25
H28
H29

K23
K28
K29

A23

A5

B2

B8

C6

D2
D4

E4
E9

F15
F28

F29

F7

G1

E2

H3
H6

J1
J25
J26
J27

J4

J5

K3
K6

7

U17E

VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]

ICH8M REV 1.0

VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]

VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]

K7
L1
L13
L15
L26
L27
L4
L5
M12
M13
M14
M15
M16
M17
M23
M28
M29
M3
N1
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
N4
N5
N6
P12
P13
P14
P15
P16
P17
P23
P28
P29
R11
R12
R13
R14
R15
R16
R17
R18
R28
R4
T12
T13
T14
T15
T16
T17
T2
U12
U13
U14
U15
U16
U17
U23
U26
U27
U3
U5
V13
V15
V28
V29
W2
W26
W27
Y28
Y29
Y4
AB4
AB23
AB5
AB6
AD5
U4
W24

A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29

8

A1_DET(14)

A29_DET(14)

AJ1_DET(14)

AJ29_DET(14)

PROJECT : OT2

SizeDocument NumberRev

Date:Sheet of

Quanta Computer Inc.

ICH8(POWER,GND)

7

1542Thursday, March 22, 2007

8

1ACustom

1

A is required to route to Top
SoDIMM for AMT to
function.This will need to
change for M08

AA

BB

DDR_CKE0_DIMMA(7)

DDR_A_BS2(8)

DDR_A_BS0(8)
DDR_A_WE#(8)

DDR_A_CAS#(8)
DDR_CS1_DIMMA#(7)

M_ODT1(7)

CC

DD

DDRDAT_SMB
DDRCLK_SMB
+3VM

1.8VSUS 1.8VSUS

DDR_A_D0
DDR_A_D4

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D6
DDR_A_D7

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D17
DDR_A_D16

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D22

DDR_A_D28
DDR_A_D29

DDR_A_DM3

DDR_A_D26
DDR_A_D30

DDR_A_BS2
DDR_A_MA12

DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS0
DDR_A_WE#

DDR_A_CAS#

M_ODT1
DDR_A_D32

DDR_A_D33
DDR_A_DQS#4

DDR_A_DQS4
DDR_A_D35

DDR_A_D38
DDR_A_D41

DDR_A_D45
DDR_A_DM5
DDR_A_D47

DDR_A_D43
DDR_A_D48

DDR_A_D52

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D55

DDR_A_D61
DDR_A_D57

DDR_A_DM7
DDR_A_D59

DDR_A_D63
DDRDAT_SMB

DDRCLK_SMB

SMbus address A0

1

SMDDR_VREF_1

JDIM1

1

VREF

3

VSS47

5

DQ0

7

DQ1

9

VSS37

11

DQS#0

13

DQS0

15

VSS48

17

DQ2

19

DQ3

21

VSS38

23

DQ8

25

DQ9

27

VSS49

29

DQS#1

31

DQS1

33

VSS39

35

DQ10

37

DQ11

39

VSS50

41

VSS18

43

DQ16

45

DQ17

47

VSS1

49

DQS#2

51

DQS2

53

VSS19

55

DQ18

57

DQ19

59

VSS22

61

DQ24

63

DQ25

65

VSS23

67

DM3

69

NC4

71

VSS9

73

DQ26

75

DQ27

77

VSS4

79

CKE0

81

VDD7

83

NC1

85

A16_BA2

87

VDD9

89

A12

91

A9

93

A8

95

VDD5

97

A5

99

A3

101

A1

103

VDD10

105

A10/AP

107

BA0

109

WE#

111

VDD2

113

CAS#

115

S1#

117

VDD3

119

ODT1

121

VSS11

123

DQ32

125

DQ33

127

VSS26

129

DQS#4

131

DQS4

133

VSS2

135

DQ34

137

DQ35

139

VSS27

141

DQ40

143

DQ41

145

VSS29

147

DM5

149

VSS51

151

DQ42

153

DQ43

155

VSS40

157

DQ48

159

DQ49

161

VSS52

163

NCTEST

165

VSS30

167

DQS#6

169

DQS6

171

VSS31

173

DQ50

175

DQ51

177

VSS33

179

DQ56

181

DQ57

183

VSS3

185

DM7

187

VSS34

189

DQ58

191

DQ59

193

VSS14

195

SDA

197

SCL

199

VDD(SPD)

FOX_AS0A426-M2SN-7F

CLOCK 0,1

CKE 0,1

2

1.8VSUS

BOT

2

VSS46

4

DQ4

6

DQ5

8

VSS15

10

DM0

12

VSS5

14

DQ6

16

DQ7

18

VSS16

20

DQ12

22

DQ13

24

VSS17

26

DM1

28

VSS53

30

CK0

32

CK0#

34

VSS41

36

DQ14

38

DQ15

40

VSS54

42

VSS20

44

DQ20

46

DQ21

48

VSS6

50

NC3

52

DM2

54

VSS21

56

DQ22

58

DQ23

60

VSS24

62

DQ28

64

DQ29

66

VSS25

68

DQS#3

70

DQS3

72

VSS10

74

DQ30

76

DQ31

78

VSS8

80

CKE1

82

PC4800 DDR2

SDRAM SO-DIMM

(200P)

VDD8

84

A15

86

A14

88

VDD11

90

A11

92

A7

94

A6

96

VDD4

98

A4

100

A2

102

A0

104

VDD12

106

BA1

108

RAS#

110

S0#

112

VDD1

114

ODT0

116

A13

118

VDD6

120

NC2

122

VSS12

124

DQ36

126

DQ37

128

VSS28

130

DM4

132

VSS42

134

DQ38

136

DQ39

138

VSS55

140

DQ44

142

DQ45

144

VSS43

146

DQS#5

148

DQS5

150

VSS56

152

DQ46

154

DQ47

156

VSS44

158

DQ52

160

DQ53

162

VSS57

164

CK1

166

CK1#

168

VSS45

170

DM6

172

VSS32

174

DQ54

176

DQ55

178

VSS35

180

DQ60

182

DQ61

184

VSS7

186

DQS#7

188

DQS7

190

VSS36

192

DQ62

194

DQ63

196

VSS13

198

SA0

200

SA1

2

3

DDR_A_D5
DDR_A_D1

DDR_A_DM0
DDR_A_D2

DDR_A_D3
DDR_A_D12

DDR_A_D13
DDR_A_DM1

DDR_A_D14
DDR_A_D15

DDR_A_D21
DDR_A_D20

PM_EXTTS#0
DDR_A_DM2

DDR_A_D19
DDR_A_D23

DDR_A_D25
DDR_A_D24

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D31
DDR_A_D27

DDR_CKE1_DIMMA(7)

DDR_A_MA14

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS1
DDR_A_RAS#

DDR_CS0_DIMMA#(7)

M_ODT0

DDR_A_MA13

DDR_A_D36
DDR_A_D37

DDR_A_DM4
DDR_A_D34

DDR_A_D39
DDR_A_D40

DDR_A_D44
DDR_A_DQS#5

DDR_A_DQS5
DDR_A_D46

DDR_A_D42
DDR_A_D49

DDR_A_D53

DDR_A_DM6
DDR_A_D54

DDR_A_D51
DDR_A_D60

DDR_A_D56
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D62

DDR_A_D58

R236
10K

1 2

3

SMDDR_VREF_1

M_CLK_DDR0(7)
M_CLK_DDR#0(7)

Add for intel update

DDR_A_BS1(8)
DDR_A_RAS#(8)

M_ODT0(7)

M_CLK_DDR1(7)
M_CLK_DDR#1(7)

+3VM

R1004

*10K

R237

DB2 stage:reaerve

10K

1 2

DDR_A_DM[0..7](8)
DDR_A_D[0..63](8)
DDR_A_DQS[0..7](8)
DDR_A_DQS#[0..7](8)
DDR_A_MA[0..14](8)

12

C334

0.1U/10V

PM_EXTTS#0(7)

12

C300

2.2U/6.3V

12

12

+3VM

12

C322

2.2U/6.3V

C301

0.1U/10V

4

5

6

Place these Caps near So-Dimm1.

12

C473

2.2U/6.3V

12

C460

0.1U/10V

12

C307

0.1U/10V

12

C328
*0.1U/10V

R227
10K

12

C458

2.2U/6.3V

SMDDR_VREF(7,37)

R235
10K

DDRDAT_SMB

DDRCLK_SMB

12

12

C309

0.1U/10V

12

12

C325
*0.1U/10V

TOP

C326

0.1U/10V

BOT

C292
*0.1U/10V

SMDDR_VREF_1

PDAT_SMB(14,17)

PCLK_SMB(14,17)

SMDDR_VTERM

SMDDR_VTERM

12

12

C474

2.2U/6.3V

1.8VSUS

12

C296
*0.1U

C462

0.1U/10V

C289
*0.1U

12

C459

C475

2.2U/6.3V

2.2U/6.3V

Place these Caps near So-Dimm1.

12

12

C477

C476

0.1U/10V

0.1U/10V

1.8VSUS

R211
*10K/F

R2120

SMDDR_VREF

R214
*10K/F

+3VM

2

3

+3VM

2

3

Layout note: Place 1 cap close to every 1 R-pack terminated to SMDDR_VTERM.

12

C310

0.1U/10V

12

C291
*0.1U/10V

12

C302

0.1U/10V

12

C308
*0.1U/10V

12

C311

0.1U/10V

12

C327
*0.1U/10V

Q17
RHU002N06

1

Q16
RHU002N06

1

DB2 stage:on install for C327,C219---C331 for only one channel DIMM

4

5

6

DDR_A_MA[0..14](8)

Add for intel update

DDR_A_RAS#(8)
DDR_A_BS1(8)

M_ODT0(7)

DDR_A_BS2(8)

Please these resistor
closely DIMMA,all
trace length<750 mil.

DDR_A_BS0(8)

DDR_A_WE#(8)
DDR_A_CAS#(8)

M_ODT1(7)

DDR_CS0_DIMMA#(7)
DDR_CS1_DIMMA#(7)
DDR_CKE0_DIMMA(7)
DDR_CKE1_DIMMA(7)

12

C306

0.1U/10V

12

C330
*0.1U/10V

12

12

C323

0.1U/10V

12

12

C329
*0.1U/10V

SizeDocument NumberRev

Date:Sheet of

7

DDR_A_MA14

DDR_A_MA11
DDR_A_MA7

DDR_A_MA6
DDR_A_MA4

DDR_A_RAS#
DDR_A_BS1

DDR_A_MA13
M_ODT0

DDR_A_BS2
DDR_A_MA12

DDR_A_MA8
DDR_A_MA9

DDR_A_MA3
DDR_A_MA5

DDR_A_BS0
DDR_A_MA10

DDR_A_WE#
DDR_A_CAS#

DDR_A_MA2
DDR_A_MA0

DDR_A_MA1

12

C324

C332

0.1U/10V

0.1U/10V

12

C333

C290

*0.1U/10V

*0.1U/10V

DDR2 SO-DIMM(200P)

7

8

SMDDR_VTERM

56

R234

1 2

RP17

2

1

4

3

4P2R-S-56
RP18

2

1

4

3

4P2R-S-56
RP20

2

1

4

3

4P2R-S-56
RP21

2

1

4

3

4P2R-S-56
RP12

2

1

4

3

4P2R-S-56
RP13

2

1

4

3

4P2R-S-56
RP14

2

1

4

3

4P2R-S-56
RP15

2

1

4

3

4P2R-S-56
RP16

2

1

4

3

4P2R-S-56
RP19

2

1

4

3

4P2R-S-56

R22356

1 2

R22156

1 2

R23256

1 2

R22256

1 2

R22056

1 2

R23356

1 2

12

C293

0.1U/10V

12

C303
*0.1U/10V

12

C304

0.1U/10V

12

C305
*0.1U/10V

12

C312

0.1U/10V

12

C331
*0.1U/10V

PROJECT : OT2

Quanta Computer Inc.

1642Thursday, March 22, 2007

8

1ACustom

1

+3VM_CK505

L11

R861.0

1 2

BK2125HM601

120 ohms@100Mhz

AA

L7

BK2125HM601

L12

R991.0

BK2125HM601

DB1A:change R59 for
intel schematic

BB

MINI1CLK_REQ#G

CC

SATA_CLKREQ#

CLKREQ#_B

CLK_PCI_ICH_1

DD

1 2

PCLK_SMB(14,16) SMBCK(4,19,27)

R34610K

R33810K

R104
10K
R81

C409

0.1U/10V

0.1U/10V

12

*10K

12

12

12

0.1U/10V

C115

Q30

2N7002E

3

Q29

2N7002E

3

12

C63

0.1U/10V

R771.0

1 2

12

C107

0.1U/10V

+3VM_CK505

2

+3VM_CK505

2

+3V

2

VDD

12

12

C114

C67

0.1U/10V

0.1U/10V

12

C64
3300P

12

12

12

C66

C65

0.1U/10V

R61
10K

0.1U/10V

CLK_BSEL1

R60
10K

0.1U/10V

CLK_PWRGD(14)

1

1

Pull low for UMA

C112

C62

VDDCPU

SMBDTSMBDTSMBDTSMBDT

SMBCKSMBCK

SMBCKSMBCK

12

12

C104
22U/10V

12

C113

0.1U/10V

12

C56
22U/10V

VDDIO

12

12

C57
22U/10V

CLK_XTAL_IN
CLK_XTAL_OUT

R590

SMBCK
SMBDT

SMBDT(4,19,27)PDAT_SMB(14,16)

PCLKKBC

12

R96

4.7K

CPU Clock select

CPU_BSEL0(4) MCH_BSEL0(7)

+1.05V

CPU_BSEL1(4)

+1.05V

CPU_BSEL2(4)

+1.05V

3

U5

16

VDDPLL3

9

VDD48

2

VDDPCI

61

VDDREF

39

VDDSRC

55

VDDCPU

20

VDDPLL3I/O

26

VDDSRCI/O

45

VDDSRCI/O

36

VDDSRCI/O

49

VDDCPU_IO

48

NC

60

X1

59

X2

56

CK_PWRGD/PD#

57

FSLB/TEST_MODE

64

SCLK

63

SDATA

15

GND

19

GND

11

GND48

52

GNDCPU

8

GNDPCI

58

GNDREF

23

GNDSRC

29

GNDSRC

42

GNDSRC

R10360/04
R1037*56/04
R1038*1K/04
R10390/04
R1040*0/04
R1041*1K/04
R10420/04
R1043*0/04
R1044*1K/04

4

CK505

27MHz_Nonss/SRCCLK1/SE1

CLK_BSEL0

CLK_BSEL1

CLK_BSEL2

CPUCLKT0
CPUCLKC0

CPUCLKT1
CPUCLKC1

CPUT2_ITP/SRCT8
CPUT2_ITP/SRCC8VDD96I/O

DOTT_96/SRCT0
DOTC_96/SRCC0

27Mhz_ss/SRCCLC1/SE2

SRCCLKT2/SATACL
SRCCLKC2/SATACL

SRCCLKT3/CR#_C

SRCCLKC3/CR#_D

SRCCLKT4
SRCCLKC4

PCI_STOP#

CPU_STOP#

SRCCLKT6
SRCCLKC6

SRCCLKT7/CR#_F
SRCCLKC7/CR#_E

SRCCLKT9
SRCCLKC9

SRCCLKT10
SRCCLKC10

SRCCLKT11/CR#_H
SRCCLKC11/CR#_G

PCICLK0/CR#_A
PCICLK1/CR#_B

PCICLK2/TME

PCICLK3

PCICLK4/27_SELECT

PCI_F5/ITP_EN
USB_48MHZ/FSLA
FSLC/TST_SL/REF

ICS9LPRS355AGLFT

5

internal have
already build-in
33ohm damping
resisteor

PV stage:delete RP2 ,add
R1067,R1068

CPU_BCLK

54
53

51
50

47
4612

13
14

17
18

21
22

24
25

27
28

38
37

41
40

44
43

30
31

34
35

33
32

1
3
4
5
6

7
10
62

PV stage:change R51,R53 to 33ohm for EA issue

R952

1K/F

R953

1K/F

1K/F

R10674.7

CPU_BCLK#

R10684.7

MCH_BCLK

4

MCH_BCLK#

2

CPU_XTP

4

CPU XTP#

2

DOT96

2

DOT96#

4
3

1

PCIE_SATA
PCIE_SATA#

PCIE_ICH
PCIE_ICH#

MCH_3GPLL
MCH_3GPLL#

PCIE_MINI1
PCIE_MINI1#

T9

MINI1CLK_REQ#MINI1CLK_REQ#G

SATA_CLKREQ#

CLKREQ#

R34733

PCLKKBC

R34833

PV stage: change R347,R348 to 33 ohm for EA issue

CLK_PCI_ICH_1

R10340

L55

*BK1608LL680

12

12

R954

12

RP3

3

4P2R-S-0

1

RP4

3

4P2R-S-0

1

RP7

1

4P2R-S-0

3

RP8

4

4P2R-S-0

2

T173
T174

2
4

2
4

4
2

2
4

R106475_1%

R9733
R34033

RP10

1

4P2R-S-0

3

RP11

1

4P2R-S-0

3

RP5

3

4P2R-S-0

1

DB2 Stage:no install RP9,R82 due to no
SATA HDD

RP6

1
3

4P2R-S-0

R98

R103133

12

475_1%

12

12

12

R33733

12

R3392.2K
R5210K

MCH_BSEL1(7)

MCH_BSEL2(7)

12

12
12

12

R5133

R5333

SI stage:reserve L53, L54,add
R1033,R1034 for WWAN noise
improvement

6

C55
27P/50V

Y2

1 2

14.318MHZ

12

CLK_XTAL_IN

12

PV stage:reserve for WWAN issue

C6693.3P

C6703.3P
C671*10P

C672*10P

CLK_PCIE_ICH(13)
CLK_PCIE_ICH#(13)

CLK_MCH_3GPLL(7)
CLK_MCH_3GPLL#(7)

H_STP_PCI#(14)
H_STP_CPU#(14)

CLK_PCIE_MINI1(19)
CLK_PCIE_MINI1#(19)

SI stage:add R1031 for EA team test easy

CLKREQ#_B(7)

SI2 stage:delete ,R82, R341 due to
no use

CLK_PCI_ICH(13)
CLK_ICH_48M(14)

R10330

L54

DB1A:change R339,R52
for intel schematic

CLK_BSEL2

12

12

*BK1608LL680

FSBBSEL0
533
667
800

CLK_CPU_BCLK(4)
CLK_CPU_BCLK#(4)

CLK_CPU_XDP(4)
CLK_CPU_XDP#(4)
MCH_DREFCLK(7)
MCH_DREFCLK#(7)

DREF_SSCLK(7)
DREF_SSCLK#(7)

MINI1CLK_REQ#G(19)

PCLK_TPM(30)
PCLK_KBC(26)

PCLK_R5C847(20)

14M_KBC(26)

CLK_ICH_14M(14)

BCLK

133
166
200

CLK_MCH_BCLK(6)
CLK_MCH_BCLK#(6)

PCLK_DBP_1(26)

CLK_BSEL0

BSEL2

0
0
00

7

CLK_XTAL_OUT

C72
27P/50V

BSEL1

0
1
1

14.318MHz

FSC

FSB

1

0

0

0

0

1

0

1
0

0
1

0
1

1

1

1

EMI

CLK_ICH_48M

C128*10P

PCLK_KBC

C412*10P

PCLK_R5C847

C126*10P

CLK_PCI_ICH

PCLK_TPM

CLK_ICH_14M

14M_KBC

1
1

C127*10P

C125*10P

C53*10P

C52*10P

8

PCISRCCPUFSA

100

1001
133

1
1

166

0

200

0

266

0

333

0

400

RSVD

1

100
100
100
100
100
100
100

33
33
33
33
33
33
33
33

SI stage: strapping options for
CPU_BSEL{0:2}

SizeDocument NumberRev

1

2

3

4

5

6

Date:Sheet of

7

PROJECT : OT2

Quanta Computer Inc.

CLOCK(CK505)

1742Thursday, March 22, 2007

8

1ACustom

5

4

+3V

3

2

1

CN3

30

32

29

31

28

LCD_CON30

27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

DD

CC

PWM_INV_1

C15
*0.1U

+3V

3

1

12

C29
10U/25V

R26

330

Q2
2N7002E

LCDVCC

EDIDDATA_1
EDIDCLK_1

ALS_EN

R17

0

TXLOUT0+
TXLOUT0-

TXLOUT1+

9

TXLOUT1-

8
7

TXLOUT2+

6

TXLOUT2-

5
4

TXLCLKOUT+

3

TXLCLKOUT-

2
1

+3V

C18

C20

1000P

0.1U

+5V

TXLOUT0+(7)
TXLOUT0-(7)

TXLOUT1+(7)
TXLOUT1-(7)

TXLOUT2+(7)
TXLOUT2-(7)

TXLCLKOUT+(7)
TXLCLKOUT-(7)

C16
1000P

ALS_EN

4

VIN

U3
TC7SH08FU

2

R22
*10K

ALS_EN#(14)

2

FPBACK

1

3 5

SI2 stage:delete

LCD_BLON(7)

L2BK1608HS121-T

C5
*0.1U/0402

LCD_BLON

2

+3V

1 3

R35
10K

2

Q7
DTC144EUA

DPST_PWM(7)

+3V

R23
10K

FPBACK

Q6
DTC144EUA

1 3

D2

2 1

1SS355

C690

3V_S5

0.1U

R25
33K

LID_SW_EC#(26)

C19

0.1U

CN2

2
1

LID SW

D3

21

CH751H-40HPT

D34

CH751H-40HPT

21

PV stage:reser for Lid s/w function to EC

LID_SW#(14)

PANEL VCC CONTROL

3VPCU

R3082K

Q4
DTC144EUA

1 3

R2010K

C32

0.1U

Q3
FDC624P

3 4

GS

2

D

D

1

D

D

+3V

5
6

C17

0.1U

L3
FBM2125HM330

C34
10U/10V/0805

40mil

C14
1000P

C13

0.1U

LCDVCC

C33

4.7U/10V

+3V

Q52N7002E

BB

EDIDCLK(7)

2.2K

EDIDDATA(7)

R32

R28

2.2K

1

2
2

1

Q12N7002E

+3V

EDIDCLK_1

3

DISP_ON(7)

EDIDDATA_1

3

R19
*10K

R27
100K

2

SI2 stage:add soft start for LCD panel rush current issue

AA

PROJECT : OT2

SizeDocument NumberRev

5

4

3

2

Date:Sheet of

Quanta Computer Inc.

LCD CON

1

1842Thursday, March 22, 2007

1AB

A

Mini PCI-E Card1 LAN

3VPCU

ICH_CL_RST1#(14)

ICH_CL_DATA1(14)
ICH_CL_CLK1(14)

CLK_PCIE_MINI1(17)
CLK_PCIE_MINI1#(17)

MINI1CLK_REQ#G(17)

ICH_CL_CLK1_1

DB2 stage:change

R2620
R2670
R2690

R268

0

R271

0

DB1A stage:change R268,R271 to footprint
1206

PCIE_TXP2(13)

PCIE_RXP2(13)
PCIE_RXN2(13)

CH_CLK(30)

CH_DATA(30)

R2720
R2730

SI2 stage:delete R1025 due to no use

R255*0
R256*0

R270*0

DD

+3VM_WLAN

DB2 stage:change power source

DB2 Stage:delete R274,R265
Add R1025

+3V

R1024*0

CC

DB2 stage:install

PCIE_WAKE#(14)

3V_S5

R2570

2

Q23
DTC144EUA

13

B

ICH_CL_CLK1_1

PCIE_RXP2_C
PCIE_RXN2_C

MINI1CLK_REQ#G

CCI_CLK
CCI_DATA

51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17

15
13
11

9
7
5
3
1

CN33

Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
GND
PETp0
PETn0
GND
GND
PERp0
PERn0
GND
Reserved
Reserved

GND
REFCLK+
REFCLK­GND
CLKREQ#
Reserved
Reserved
WAKE#

PCI-E Card

RF_LINK(29)

DB2 stage:change

+3VM_WLAN

+3V

R249

0

+3.3V

GND

+1.5V
LED_WPAN#
LED_WLAN#

LED_WWAN#

GND

USB_D+

USB_D-

GND

SMB_DATA

SMB_CLK

+1.5V

GND

+3.3Vaux

PERST#

Reserved

GND

Reserved
Reserved
Reserved
Reserved
Reserved

+1.5V

GND

+3.3V

52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18

16
14
12
10
8
6
4
2

C

D16*SW1010C

2 1

BLUELEDRF_LINK

3V_S5

SI stage:change footprint to 1206

R258

0

R259

*0

DB1A stage:change to footprint
1206

R250*0
R2510

T80

RF_OFF#_1

R1026

0

+1.5V_WLAN

+3VM_WLAN

D

C348

C351

1000P

0.01U

+3VM

C353
1000P

BLUELED
RF_LINK

C347
1000P

SMBDT(4,17,27)PCIE_TXN2(13)
SMBCK(4,17,27)
PLTRST#(13,26,28,30)

D15

2 1

CH751H-40HPT

+1.5V

DB2 Stage:delete RP22,RP23,R254

SI2 stage:change to CH751H-40HPT for lower Vf

C345

0.1U/10V

C352

0.1U/10V

C346

0.1U/10V

+1.5V_WLAN

C354
10U/10V/0805

3V_S5

C355
1U

SI2 stage:no install

+3VM_WLAN

DB2 stage:change power source

C350
10U/10V/0805

RF_OFF#_1

RF_OFF#(14)

E

3V_S5

R248
*10K

DB2 stage:change

Mini PCI-E Card2 WWAN

+1.5V

+3V

LED_WPAN#
LED_WLAN#

LED_WWAN#

USB_D+

USB_D-

SMB_DATA

SMB_CLK

+3.3Vaux

PERST#

Reserved

Reserved
Reserved
Reserved
Reserved
Reserved

+3.3V

GND

+1.5V

GND

GND

+1.5V

GND

GND

+1.5V

GND

+3.3V

C89
1000P

C75

0.1U/10V

R43

0

52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18

16
14
12
10
8
6
4
2

C74

C124

0.01U

1000P

BB

+3V

AA

51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17

15
13
11

C61

0.1U/10V

CN20

Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
GND
PETp0
PETn0
GND
GND
PERp0
PERn0
GND
Reserved
Reserved

GND
REFCLK+
REFCLK-

9

GND

7

CLKREQ#

5

Reserved

3

Reserved

1

WAKE#

PCI-E Card

A

C109
10U/10V/0805

3VSUS +3V

C59

C88
1U

+1.5V

R730

WWLAN_OFF_SIM

UIM_VPP
UIM_RST

UIM_DATA_1UIM_DATA

UIM_PWR

+3V

C58

1000P

0.1U/10V

3VSUS

R74

*0

R640

R850
R1010

C132
.1U

B

C68
10U/10V/0805

+3V

WWAN#(29)

USBP8+(13)
USBP8-(13)

SMBDT(4,17,27)
SMBCK(4,17,27)

PLTRST#(13,26,28,30)

R1020

UIM_CLKUIM_CLK_1

C120

4.7UA

C91
*.1U

C100
*.1U

R111

UIM_PWR

*10K

WWAN_OFF#(13)

U8

1

CH1

2

VN

3

CH2

*CM1213_04ST

CN4

1

GND

3

VPP

5

I_O

7

N/A

9

CT

SHIELDSHIELD

600-0000-0012

PV stage:Add shielding connect to
GND

C

CH3

VP

CH4

VCC
RST

CLK

N/A

DET

R550

4
5
6

2
4
6
8
10

1413

UIM_PWR
UIM_RSTUIM_RST
UIM_CLK

WWLAN_OFF_SIMWWLAN_OFF_SIMWWLAN_OFF_SIM

+3V

D6

BAV99W

EMI

2

3

1

UIM_CLK

R92
*22R

C94
*22P

PROJECT : OT2

SizeDocument NumberRev

D

Date:Sheet of

Quanta Computer Inc.

WAN/WWAN CARD

E

1942Thursday, March 22, 2007

1ACustom

5

12

C612

C605

C604

C572

0.01U

PAR
C/BE3#
C/BE2#
C/BE1#
C/BE0#
AD22

REQ2#
GNT2#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR_1#

R547
*100K

0.01U

C573

0.47U

C606

0.01U

C571

0.47U

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

PCIRST#
PCLK_R5C847

CLKRUN#

R5C847_PME#

10U/6.3V

0.01U

+3V

PCIRST#GRESET#

R1027*0

PCIRST#(13)

SHIELD GND

12

C597

C574

C611

0.01U

0.01U

10U/6.3V

AD[31..0](13)

PAR(13)
C/BE3#(13)
C/BE2#(13)
C/BE1#(13)
C/BE0#(13)
AD22(13)

REQ2#(13)
GNT2#(13)
FRAME#(13)
IRDY#(13)
TRDY#(13)
DEVSEL#(13)

STOP#(13)
PERR#(13)
SERR_1#(13)

CLKRUN#(14,26,30)

CoreLogic CLOCKRUN#

When CLKRUN# is controlled by
system, the pull-down
resistor(R1050) dose not need to
apply.

C575

0.01U

GRESET#

C603

0.01U

+3V

DD

CC

R545*0

HWPG(26,31)

+3V

R551
10K

C615

1U/25V

DB2 Stage:R551 from 100k chang to
10K to solve GBRST too slow for 1394/Firewire

PowerOnReset for VccCore

BB

When GRESET# is controlled by system,
the pull-up resistor(R551) and
capacitor(C615) do not need to apply.

PCLK_R5C847(17) OE#(21)

EMI

PCLK_R5C847

R555
*22R

*22P

AA

R5C847_PME#

+3V

R981220K

RC0402

1 3

Q53

DTC144EU

MDID4

5

R548

2

10K

1

500mA

D

S

C609

Q52

G

AO3413

0.1U

BAM34130001

CC0402

DB1A change :modify for
detect function

2

3

Q47
2N7002E

C610

0.1U

CC0402

SHIELD GND

C608
1U

+3V

W3
R11
R12

R6

E13

L1

E14

M2
M1

N5
N4
N2
N1
P5
P4
R4
R2
R1
T2
T1
U2
U1
V1
T7
V7

W7

R8
T8
V8

W8

R9

V9
W9
T11

V11
W11

T12

V12
W12

V6

P2
W2
W6

T9

P1

M4
M5

V3

V4
W4

T5

V5
W5

T6

G2

L4

K1

L5

G4

PCI_PME#(13)

R542
*150KA

4

U40A

VCC_PCI1
VCC_PCI2
VCC_PCI3

VCC_RIN1
VCC_RIN2
VCC_ROUT1
VCC_ROUT2

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
PAR
C/BE3#
C/BE2#
C/BE1#
C/BE0#
IDSEL

REQ#
GNT#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#

GBRST#
PCIRST#
PCICLK

CLKRUN#
PME#/RI_OUT#

R5C847-V10_0

MDID12
MDID13
MDID8

MDID9

MDID10

MDID11

SDVCC_MSVCC

4

3

+3V

DB2 stage:change power source form 3VSUS to 3V due to not support wake up in S3

F5

VCC_3V1

J19

VCC_3V2

PCI / OTHER

R52847
R52747
R53033

R53147

R52947C616

R53247

VCC_3V3
VCC_3V4

VCC_MD

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8

GND9
GND10
AGND1
AGND2
AGND3
AGND4
AGND5
AGND6

TEST1

TEST2

HWSPND#

SPKROUT#

UDIO5

UDIO4

UDIO3

UDIO2

UDIO1

UDIO0/SRIRQ#

INTA#

INTB#

INTC#

MDID12_R

MDID13_R

MDID8_R

MDID9_R

MDID10_R

MDID11_R

K19
G5

A4

J1
J5
K5
E9
R10
T10
V10
W10
L15
M19
A9
B9
D9
D14
A15
B15

F4
R7

F2
F1

G1
H5
H4
H2
H1
J4

J2
K4
K2
L2

NC0

C552

C602

0.01U

0.01U

+3V

R546
10K

PCMSPK#

SDA

SCL

SERIRQ(14,26,30)

INTC#(13)
INTD#(13)
INTE#(13)

C592

22P

C594

22P

C596

22P

C595

22P

C598

22P

MDID0

R54133

MDID3

R53433

12

C593

C613

C607

0.01U

10U/6.3V

0.01U

When HWSPND# is controlled by
system, the pull-up
resistor(R1041) dose not need to
apply.

PCMSPK#(22)

+3V

R533
100K

T153

R537

*100K

R524

+3V

+3V

10K

R522
10K

* NOT Use EEPROM :

R524,R522,R537 : installed

R533,U39,C585: NOT installed
* Use EEPROM :
R533: NOT installed

R522,R524,U39,C585,R537 :
installed

SDVCC_MSVCC

CN34

9

DATA2

1

DATA3

2

CMD

4

VDD

5

CLK

6

VSS2

3

VSS1

7

DATA0

8

DATA1

SD_SLOT

WP

CD

CD/WP

GND

GND

10

111213

14

DB2 stage:change to push-push type

MDID0_R

MDID3_R

C585

U39

8

VCC

7

WP

6

SCL

5

SDAA2GND

*24C02

Serial EEPROM

0.01U

A0
A1

reserve for MMC card detect properly

3

1
2
3
4

MDID11
MDID10

MDID4
MDID3

MDID0

MDID13
MDID12

MDID9
MDID8

U40B

C1

D1

E1

C2

D2

E2

E4

E8
D8

B8
A8
E7
D7
B7
A7
E6
D6

B6
A6
D5
B5
A5
B4
B3
A3
A2
B1

R5C847-V10_0

NC1

NC2

NC3

NC4

NC5

NC6

NC7

MDIO19
MDIO18

MDIO17
MDIO16
MDIO15
MDIO14
MDIO13
MDIO12
MDIO11
MDIO10

MDIO09
MDIO08
MDIO07
MDIO06
MDIO05
MDIO04
MDIO03
MDIO02
MDIO01
MDIO00

2

CADR25/CAD19
CADR24/CAD17

CADR23/CFRAME#

CADR22/CTRDY#

CADR21/CDEVSEL#

CADR20/CSTOP#

CADR17/CAD16

CADR16/CCLK

CADR15/CIRDY#

CADR14/CPERR#

CADR13/CPAR

CADR12/CCBE2#

CADR11/CAD12

CADR10/CAD9
CADR9/CAD14

CADR8/CCBE1#

CADR7/CAD18
CADR6/CAD20
CADR5/CAD21
CADR4/CAD22
CADR3/CAD23
CADR2/CAD24
CADR1/CAD25

CADR0/CAD26
CDATA15/CAD8
CDATA13/CAD6

CDATA12/CAD4
CDATA11/CAD2

CDATA10/CAD31

CDATA9/CAD30
CDATA8/CAD28

CDATA7/CAD7

CDATA6/CAD5

CDATA5/CAD3

CDATA4/CAD1

CARDBUS / MEDIA CARD

CDATA3/CAD0
CDATA1/CAD29

CDATA0/CAD27

CE2#/CAD10
CE1#/CCBE0#
REG#/CCBE3#
RESET/CRST#

WAIT#/CSERR#
WP/CCLKRUN#

BVD2/CAUDIO

BVD1/CSTSCHG

CD2#/CCD2#

CD1#/CCD1#

INPACK#/CREQ#

IORD#/CAD13

IOWR#/CAD15

2

CADR19
CADR18

CDATA14

CDATA2

OE#/CAD11

WE#/CGNT#

RDY/CINT#

VS2#/CVS2
VS1#/CVS1

USBDP

USBDM

VPPEN1

VPPEN0
VCC3EN#
VCC5EN#

J18
J15
K16
L16
L18
M16
N19
N16
P16
L19

R5090

K15
N18
N15
K18
R18
U19
R19
P15
J16
H15
H18
G15
G18
F15
F18
E16

U18
W18
V17
V16
V15
B19
C18
D18
W17
W16
W15
T15
R14
C19
D19
E19

T19
M15
T18
V19
F16
H19
G16
A18
M18
F19
E18
H16
R16
D15
T14
G19

DIFFERENTIAL IMPEDANCE : 90 ohms

P18
P19

V14

T151

W14

T152

W13
V13
T13
R13

WE#(21)
CE2#(21)
CE1#(21)
REG#(21)
RESET(21)
WAIT#(21)
WP(21)
RDY(21)
BVD2(21)
BVD1(21)
VS2#(21)
VS1#(21)
CD2#(21)
CD1#(21)
INPACK#(21)

CHECK FOOTPRINT

SizeDocument NumberRev

Date:Sheet of

1

CADR25
CADR24
CADR23
CADR22
CADR21
CADR20
CADR19
CADR18

SHIELD GND

CADR17
CADR16
CADR15
CADR14

*CLOCK LINE FOR CARDBUS MODE

CADR13
CADR12
CADR11
CADR10
CADR9
CADR8
CADR7
CADR6
CADR5
CADR4
CADR3
CADR2
CADR1
CADR0

CDATA15
CDATA14
CDATA13
CDATA12
CDATA11
CDATA10
CDATA9
CDATA8
CDATA7
CDATA6
CDATA5
CDATA4
CDATA3
CDATA2
CDATA1
CDATA0

R497100K

PROJECT : OT2

Quanta Computer Inc.

RC5847(1394)

1

CADR[25..0](21)

CDATA[15..0](21)

SHIELD GND

IORD#(21)
IOWR#(21)

VPPEN1(21)
VPPEN0(21)
VCC3EN#(21)
VCC5EN#(21)

2042Thursday, March 22, 2007

1AC

5

U40C

AVCC_PHY1

IEEE1394

AVCC_PHY2
AVCC_PHY3
AVCC_PHY4

TPBIAS0

TPBN0

TPBP0

TPAN0

TPAP0

NC9

NC10
NC11

NC12
NC13

AVCC_PHY

DD

GUARD GND

10P

24.576MHz 50ppm 10pF

CC

C584
10P

R519
10K 1%

C591

0.01U/25V

Y6

GUARD GND

1394_XIN

1394_XOUT

REXT

VREF

D11

CPS

A16

XI

B16

XO

A14

FIL0

B14

REXT

D13

VREF

E12

NC8

R5C847-V10_0

CARDBUS POWER SWITCH

+3V

C505

BB

VPPEN1(20)
VPPEN0(20)
VCC3EN#(20)

SI stage:change to 5V due not
support wake on S3

VCC5EN#(20)

1U

CC0402

C506
1U

CC0402

+5V

R5531V-002

DB2 stage:change power source form 3VSUS to 3V due to not support wake up in S3

U35

10

NC3

7

NC2

11

3VIN

13

5VIN1

15

5VIN2

6

NC1

4

EN1

2

VCC3EN

1

VCC5EN

VCCOUT1
VCCOUT2
VCCOUT3

VPPOUT

4

+3V

E10
E11
A17
B17

TPBIAS0

D12

R526

R525

56

56

A13

B13

A12

B12

D10

A11
B11

A10
B10

9
12
14

8

53

/FLAGEN0

16

GND

270pF

5.1K

C588
R521

A_VCC

0.33U

0.01U/25V

R520
56

12

C504

0.1U/10V

A_VPP

12

C551

0.1U/10V

TPB0N

TPB0P

TPA0N

TPA0P

R523
56

12

C553
10U/6.3V

C590
C589

EB4

L48BLM21P300S

12

C587

C586

0.1U/10V

10U/6.3V

R5000

*1632090

43

2

R4990
R4960

2

EB3*1632090

R4980

1

1432

1

1432

43

C554

0.001U

3

C567

0.1U/10V

TPB0N_C

TPB0P_C

TPA0N_C

TPA0P_C

AVCC_PHY

C568

0.001U

1394_CONN
CN31

1

1

1

2

2

3

3

4

4

5678

567

CHECK FOOTPRINT

2

CADR[25..0](20)

CDATA[15..0](20)

SHIELD GND

8

OE#(20)
WE#(20)
CE2#(20)
CE1#(20)
REG#(20)
RESET(20)
WAIT#(20)
WP(20)
RDY(20)
BVD2(20)
BVD1(20)
VS2#(20)
VS1#(20)
CD2#(20)
CD1#(20)

INPACK#(20)

DIFFERENTIAL IMPEDANCE : 90 ohms

IORD#(20)
IOWR#(20)

SHIELD GND

CADR25
CADR24
CADR23
CADR22
CADR21
CADR20
CADR19
CADR18
CADR17
CADR16
CADR15
CADR14
CADR13
CADR12
CADR11
CADR10
CADR9
CADR8
CADR7
CADR6
CADR5
CADR4
CADR3
CADR2
CADR1
CADR0
CDATA15
CDATA14
CDATA13
CDATA12
CDATA11
CDATA10
CDATA9
CDATA8
CDATA7
CDATA6
CDATA5
CDATA4
CDATA3
CDATA2
CDATA1
CDATA0

C357

270pF

C338

270pF

56
55
54
53
50
49
48
47
46
19
20
14
13
21
10

11
12
22
23
24
25
26
27
28
29
41
40
39
38
37
66
65
64

32
31
30

15
42

61
58
59
33
16
62
63
57
43
67
36
60

44

45

C342
*0.01uF

CN10

A25/CAD19
A24/CAD17
A23/CFRAME#
A22/CTRDY#
A21/CDEVSEL#
A20/CSTOP#
A19/CBLOCK#
A18/RSVA18
A17/CAD16
A16/CCLK
A15/CIRDY#
A14/CPERR#
A13/CPAR
A12/CCBE2#
A11/CAD12

8

A10/CAD9
A9/CAD14
A8/CCBE1#
A7/CAD18
A6/CAD20
A5/CAD21
A4/CAD22
A3/CAD23
A2/CAD24
A1/CAD25
A0/CAD26
D15/CAD8
D14/RSVD14
D13/CAD6
D12/CAD4
D11/CAD2
D10/CAD31
D9/CAD30
D8/CAD28

6

D7/CAD7

5

D6/CAD5

4

D5/CAD3

3

D4/CAD1

2

D3/CAD0
D2/RSVD2
D1/CAD29
D0/CAD27

9

OE#/CAD11
WE#/CGNT#
CE2#/CAD10

7

CE1#/CCBE0#
REG#/CCBE3#
RESET/CRST#
WAIT#/CSERR#
WP/CCLKRUN#
READY/CINT#
BVD2/CAUDIO
BVD1/CSTSCHG
VS2#/CVS2
VS1#/CVS1
CD2#/CCD2
CD1#/CCD1
INPACK#/CREQ#

IORD#/CAD13
IOWR#/CAD15

CARD_SLOT_0

VCC1
VCC2

VPP1
VPP2

GND1
GND2
GND3
GND4

1

A_VCCA_VPP

17
51

18
52

C343

0.01uFC569

1
34
35
68

C344

0.01uF

12

C349
10U/6.3V

DB1A stage:delete C342

AA

PROJECT : OT2

SizeDocument NumberRev

5

4

3

2

Date:Sheet of

Quanta Computer Inc.

RC5847(Cardbus)

1

2142Thursday, March 22, 2007

1AB

5

JP6

*SHORT PAD

1 2

JP7

1 2

*SHORT PAD
JP8

1 2

DD

SI2 stage:reserve for
ADI suggest

AC_BITCLK1

R465
0

C509
10P

CC

*SHORT PAD

ACZ_SYNC_ADI(12)
ACZ_BITCLK_ADI(12)
ACZ_SDOUT_ADI(12)

ACZ_SDIN0(12)

ACZ_RST_ADI#(12,23)

SENSE_A_A_R(23)

PR_INSERT#(14,27)

AGND

3V_DVDD

EAPD(23,26)

+3V

L470

C520

C524

10U/10V

0.1U

ACZ_SYNC_ADI
ACZ_BITCLK_ADI
ACZ_SDOUT_ADI

ACZ_RST_ADI#

AGND

ACZ_RST_ADI#

R47410
R46933

R504*4.7K
R503*4.7K
R502*4.7K
R477*4.7K

R1054*4.7K

DB1A stage:change to 33 ohm for change list

SI stage:R502 no install

EAPD

C4970.1U

R432

C496

4.7K

.01U

AGND

C516
1U

AGND AGND

PC BEEP CONTROL

AVDD

C500

AGND

R1015

3K

0.1U

53

AGND

BEEP1

4

U33
7SH86

R1016

3K

C639

4.7U

CN36

2
1

Mic

AGND

AGND

NORMAL : LOW

BB

PCMSPK#(20)

PCSPK(14)

1
2

AVDD

PV stage:change due to BOM error

AA

INT_MIC1_CN

C664

R1050

*1000P

*0

AGND

AGND

5

PLACED NEAR
PIN1&9

AC_BITCLK1
AC_SDINACZ_SDIN0

BEEPBEEP2BEEP1

C513

0.1U

INT_MIC1_CN

C6370.22U

0603CS-101EJTS

C657
47P

4

C508
10U/10V

4

3V_DVDD

C512

C537

0.1U

0.1U

1

SYNC
BIT-CLK
SDATA-OUT
SDATA-IN
RESET#

GPIO0_JS1
GPIO1/JS0
GPIO2
GPIO3

EPAD
SPDIF_OUT
PCBEEP
VREF_FILT

NC
NC
NC
NC
NC

9

DVDD1

DVDD2

DVSS1

DVSS2

4

7

AGND

U34

10

6
5
8

11

43
44

2
3

47
48
12
27

31
33
40
45
46

L53

INT MIC

AVDD

38

MONO-O

AVDD2

PORT-A_R
PORT-A_L

PORT-B_R
PORT-B_L

PORT-C_R
PORT-C_L

PORT-D_R
PORT-D_L

PORT-E_R
PORT-E_L

PORT-F_R

PORT-F_L

MIC_BIAS_B
MIC_BIAS_C
MIC_BIAS_D

MIC_BIAS_F
SENSE_B/SRC_A
SENSE_A/SRC_B

AVSS1 AVDD1

AVSS2

AD1981HDJSTZ

26 25

42

AGND

R101710K

C640

68P

3

SI2 stage:change 22U for ESD issue

U37

5

Vout

Vin

4

C556

C555

22U/25V

0.1U

AGND

37

HP_OUT_R

41

HP_OUT_L

39

MIC2

22

MIC1

21
24

LINE_IN_LSENSE_A_A_R

23

LINE_OUTR1

36

LINE_OUTL1

35
15

14
17

16
20

18
19

28
29
32
30
34
13

INT_MIC

C641220P

R1020182K

PV stage:change C641 to 220P and R1020 to 182K
for Mic gain issue

SI stage:change for HP request

INT_MIC

C6431U

C498
*0.1U

AGND

R4780

R486

*0

R4330

MIC_REF1

C636

100P

AGND

SI stage:change connect to pin1
for internal mic issue

3

AGND

CD-R

CD-L

CD-GND

C510

0.1U

BYP

2 3

GNDEN

C549

TPS793475

1U

AGND

Vset=1.242V

HP_OUT_R(23)
HP_OUT_L(23)

MIC2(23)
MIC1(23)

LINE_IN_R_1LINE_IN_R

C5071U

LINE_IN_L_1

C5021U

LINE_OUTR

C5410.33U

LINE_OUTL

C5350.33U

AVDD

AVDD

SI stage:add for internal mic issue

R438

R475

2.67K/F

2.67K

SI stage:change for HP request

AGND

U47

1OUT

VDD+

1IN-

2OUT
1IN+
GND2IN+

TLV2462CDGKR

R43939.2K/F
R45020K/F
R45910K/F

C501
1U

2IN-

SENSE_A_RSENSE_A_B

1
2
3
4 5

1

R4614.7K
R4454.7K

R4444.7K
R4604.7K

8
7
6

C530

0.1U

SENSE_A_A

SENSE_A_C

AVDD

C635
.01U

AGND

R10190

C534

C527

0.047U

1U

MAINON

DOCK_LINE_IN_R(32)
DOCK_LINE_IN_L(32)

LINE_OUTR(23)
LINE_OUTL(23)

AGND

AGND

AVDD

12

AGND

2

L50

1 2

BLM11A20

MAINON(25,31,34,36,37,38,39,40)

SENSE_A_A(23)
SENSE_A_B(23)

31

2

Q38
2N7002

AGND

R1014

PV stage:change due to BOM error

47K

R1018100

R1021

C642

47K

4.7U

2

1

+5V

C581

C583

10U/10V

0.1U

PORT

MONO_OUT

PORT A
PORT B

PLACE TO
X
HP OUT, DOCK HP LO
M/B MIC

PORT CDOCK LI

M/B SPK
X
X

LINE_IN_SENSE

R4940_1206

C582.1U
C562.1UR43647K
C446.1U
C298.1U
C529.1U
C557.1U
C492.1U
C277.1U
C236.1U

AGND

LINE_IN_SENSE(32)

R458
100K

PORT D
PORT E
PORT F

AVDD

R449
*10K

C503
*1U

AGND

MIC_REF1

C638

4.7U

AGND

PROJECT : OT2

SizeDocument NumberRev

Date:Sheet of

Quanta Computer Inc.

Audio codec(ADI1981)

1

2242Thursday, March 22, 2007

1ACustom

5

AVDD

3V_DVDD

DD

ACZ_RST_ADI#(12,22)

R1055

1 2

*330K/F

R1056

1 2

*10K/F

R1057

1 2

*1K/F

HP_CONTROL

12

C665

3

Q63

*2N7002E

2

1

C666
*0.047U

AGND

*4.7U/10V

AGND

PV stage:change for HP request

SI stage:change to 56.2 ohm

+

C479100U/6.3V

+

C478100U/6.3V

AVDD

4
1

SENSE_A_A_R

SENSE_A_A

DOCK_HP_SENSE

EXT_MIC2_1

HP_L
HP_RHP_R_1

R1058

*22.K/F_6

AGND AGND

31

2

Q33
2N7002

AGND

31

2

Q36
2N7002

AGND

L37BK1608LL121
L33BK1608LL121

AGND

R427
100K

R38260.4
R38160.4

R1059

*22K/F_6

AVDD

AGND

SI2 stage:change to 2N7002K for ESD issue

EXT_MIC1
EXT_MIC2

HP_OUT_L
HP_OUT_R

U31SR05

2

IO1

3

IO2

SENSE_A_A_R(22)

SENSE_A_A(22)

C2680.33U
C2630.33U

Vin

Gnd

HP_OUT_L(22)
HP_OUT_R(22)

SI2 stage:reserve for anti-pop circuit

DOCK_HP_OUT_R

CC

MICSENSE

SI2 stage:for
ESD issue

BB

DOCK_HP_SENSE(32)

AA

SI stage: change to 10k for Mic gain

5

4

SI2 stage:reserve for anti-pop circuit

LINE_OUTR(22)
LINE_OUTL(22)

PV stage:reser for mute noise issue

HP_L_1

HP_L_2
HP_R_2

R380
100K

31

2

Q34
2N7002

C5640.1U

AGND

EAPD(22,26)

L41BK1608LL121
L40BK1608LL121

R218

R215

1K

1K

AGNDAGND AGNDAGND

AVDD

31

AGND

R379
100K

R51434.8K/F
R51034.8K/F

R50616.2K

+5V

R505
10K

31

2

Q40
*2N7002

AGND AGND

DOCK_HP_OUT_L(32)
DOCK_HP_OUT_R(32)

C294
470P

R195100K

2

Q35
2N7002k

C274

2.2U

AGND

AVDD

R376
33K

CLOSE TO #3 #5

R377

C451

33K

.01U

AGND

CLOSE TO #2 #3
CLOSE TO #5 #6

EXT_MIC1_2
EXT_MIC2_2EXT_MIC2_3

C266
68P

R19010K
R18810K

C254
68P

AGNDAGND

4

AGND

C445

EXT_MIC1_3EXT_MIC1_1

33P

12

C691

*.1U_10V

AGND

A_SD(26)

C299
470P

AVDD

R197
100K

C450

4.7U

AGND

U15

3

1IN+

C453
33P

6 7

2IN-2OUT

TLV2462CDGKR
R378100K
C452100P
R375100K
C443100P

3

LINE_OUT

C565
10U

MUTE_AMP

31

2

HP_L_3
HP_R_3

T-GND

DB2 stage:Close CN32

8

VDD+

45

GND2IN+

12

1OUT1IN-

3

U38

4 5

IN-VO+

3

IN+

2

BYPASS

1

SHUTDOWN

TPA6211A1DRBR

Q39
2N7002

CN30

1
2
6
3
4
5

HP-JACK-GREEN

LINE OUT

AVDD

C444
.1U_16V

AGND

MIC1_1
MIC2_1

+5V

AGND

C576
10U

VDD

GND

VO-

7

8

C4481U
C4491U

12

C566
.1U_10V

6
7
8

T-GND

AGND

EXT_MIC1
EXT_MIC2

SPK-

HP_CONTROL

HP_R_1

SENSE_A_B(22)

MIC1(22)
MIC2(22)

2

L52BK1608LL121

L51BK1608LL121

R2290

Q21
*2N7002E

3

HP_CONTROL

C248

4.7U

Q22
*2N7002E

3

2

R371
470

R372

3.9K

1

R2300

2

AVDD

SI2 stage:change to 2N7002K for ESD issue

2

SPK_1+SPK+
SPK_1-

C617
100P

Q19

*2N7002E

1

2

Q20

*2N7002E

1

1

2

R373
470

C262

R374

4.7U

3.9K

AGNDAGND

L36BK1608LL121
L35BK1608LL121

31

2

Q11
2N7002K

AGND

SizeDocument NumberRev

Date:Sheet of

3

AGND

AVDD

AGND

C619
100P

CN13

2
1

Speaker

AGNDAGND

HP_L_2HP_L_1

3

R3700_1206

T-GND

EXT_MIC1_4
EXT_MIC2_4

C265
470P

AGND

R183
47K

C252

0.1U

1

INT. SPEAKER

SI2 sage:change to 0 ohm for
EA audio issue

1 2

1 2

1 2

HP_R_2

1 2

1 2

1 2

C4550.1U/10V

C3180.1U/10V

C3140.1U/10V

T-GND

MIC

CN29

1
2
6
3
4

C275
470P

MICSENSE

AUDIO AMP&JACK

5

MIC-JACK-PINK

T-GND T-GND

PROJECT : OT2

Quanta Computer Inc.

1

C2560.1U/10V

C2840 ohm

C4630.1U/10V

AGND

7

8

1ACustom

2342Thursday, March 22, 2007

5

PV stage:reserve for EMI

DD

Link Speed LCI GLCI
1000Mbps Runing Runing
100Mbps Runing Idle
10Mbps Runing Idle
No Link Runing or power down Idle
Power down Power down Power down

CC

BB

12

R317

49.9/F

12

C391

0.1U/10V

12

R325

AA

49.9/F

12

C397

0.1U/10V

Layout Note:
Place termination resistors close to
LAN controller(less than 0.25").

5

C689
*0.1U

PCIE_RXP6(13)
PCIE_RXN6(13)

Layout Note:
Place the resistors less than 1" from LAN controller.

Layout Note:
Keep this resistor on
top side.

Layout Note:
Connect the resistor
to GND near ball E6

TX1N_R
TX1P_R

12

12

R321

49.9/F

TX2N_R
TX2P_R

R328

49.9/F

12

12

R314

49.9/F

12

C385

0.1U/10V

TX3N_R
TX3P_R

12

12

R330

R332

49.9/F

49.9/F

12

C407

0.1U/10V

JKCLK Pin
Power down 0MHz
10Mbps 5MHz
100Mbps 50MHz
1000Mbps 62.5MHz

GLAN_CLK(12)

LAN_RSTSYNC(12)

LAN_TXD0(12)
LAN_TXD1(12)
LAN_TXD2(12)

LAN_RXD0(12)
LAN_RXD1(12)
LAN_RXD2(12)

PCIE_TXP6(13)
PCIE_TXN6(13)

R3351.4K/F

1 2

LAN_LINKLED#(14,25,32)

LOM_ACTLED#(25,32)

TX0P_R(25)
TX0N_R(25)

TX1P_R(25)
TX1N_R(25)

TX2P_R(25)
TX2N_R(25)

TX3P_R(25)
TX3N_R(25)

TX0N_R
TX0P_R

R311

49.9/F

4

R8433_F

1 2

R3200
R3340
R3270

R3240
R3150
R3130

C4000.1U/10V
C4040.1U/10V

R307*0

R3361.4K/F

1 2

+1.8V_LOM

12

+1.0V_LOM

12

1 2
1 2

TX0P_R
TX0N_R

TX1P_R
TX1N_R

TX2P_R
TX2N_R

TX3P_R
TX3N_R

C71
22U/4V

C69
22U/4V

4

12

PAD

12
12
12

12
12
12

LAN_KMRN_RCOMP_P
LAN_KMRN_RCOMP_N

LAN_ATEST_P
LAN_ATEST_N

LAN_RBIAS_P

T85

R306100/F

1 2

12

C406

0.1U/10V

12

SI stage:change to 1%

LAN_TXD0_R
LAN_TXD1_R
LAN_TXD2_R

LAN_RXD0_R
LAN_RXD1_R
LAN_RXD2_R

PCIE_RXP6_R
PCIE_RXN6_R

NINEVEH-EKRON_N (REV 1p0)

12

C378

0.1U/10V

U6

E2

JKCLK-JCLK

E3

JRSTSYNC

D1

JTXD0

F3

JTXD1

F1

JTXD2

D3

JRXD0

D2

JRXD1

C1

JRXD2

H2

GLAN_TXP-NC

J2

GLAN_TXN-NC

J4

GLAN_RXP-NC

H4

GLAN_RXN-NC

G7

KBIAS_P-RBIAS100

H7

KBIAS_N-RBIAS10

A4

LED0-LINK_UP_N

B4

LED1-ACT_LED_N

A5

LED2-SPEED_LED_N

B8

MDI_PLUS[0]-TDP

B9

MDI_MINUS[0]-TDN

D9

MDI_PLUS[1]-RDP

D8

MDI_MINUS[1]-RDN

F9

MDI_PLUS[2]-NC

F8

MDI_MINUS[2]-NC

H8

MDI_PLUS[3]-NC

H9

MDI_MINUS[3]-NC

A7

IEEE_TEST_P-NC

B7

IEEE_TEST_N-NC

J6

RSVD_J6-NC

J7

RSVD_J7-NC

E7

RBIAS_P-NC

E6

RBIAS_N-NC

B5

RSVD_B5-NC

A6

RSVD_A6-ADV10/LAN_DIS_N

C5

RSVD_C5-NC

B6

TEST_EN

12

C402

0.1U/10V

12

C401

0.1U/10V

C395

0.1U/10V

12

C393

0.1U/10V

3

SI2 stage:add R1053 for LAN issue

H5

H6

XTAL2-X2

XTAL1-X1

LCI

GLCI

MDI

JTAG

JTAG_TCK-ISOL_TCK

JTAG_TDI-ISOL_TI

JTAG_TDO-TOUT

JTAG_TMS-ISOL_EXEC

G1H1G3

G2

T14

PAD

T16

PAD

T90

PAD

T15

PAD

12

12

C388

0.1U/10V

C387

0.1U/10V

DB1A stage:reserve

12

12

3

R105330

LOM_XTAL2GLAN_CLK
LOM_XTAL1

DB2 stage:change to vender: KDS for
intel recommend

VSSA[17]-NC
VSSA[16]-NC

VSSA[15]-VSSA2

VSSA[14]-VSS

VSSA[13]-NC
VSSA[12]-VSS
VSSA[11]-VSS
VSSA[10]-VSS
VSSA[09]-VSS
VSSA[08]-VSS
VSSA[07]-VSS
VSSA[06]-VSS
VSSA[05]-VSS
VSSA[04]-VSS

VSSA[03]-VSSR

VSSA[02]-NC
VSSA[01]-VSS

VSS[04]-VSS
VSS[03]-VSSP

VSS[02]-VSS

VSS[01]-NC

VDD1P0[03]-VCCA
VDD1P0[02]-VCCT
VDD1P0[01]-VCCR

VCCF1P0-VCC

VCCFC1P0-VCC

VCC3P3[02]-VCCP

VCC3P3[01]-VCC

VCC1P8[04]-NC
VCC1P8[03]-NC
VCC1P8[02]-NC
VCC1P8[01]-NC

VCC1P0-VCCA2

VCC[02]
VCC[01]

V1P0_OUT-NC

CTRL_10-NC

CTRL_18-NC

THERM_D_P-NC
THERM_D_N-NC

+3VM_LAN_SW

R982*200

1 2

R983*200

1 2

12

C375

0.1U/10V

C379

0.1U/10V

C382
470P/50V

12

C405

0.1U/10V

12

12

J9
J8
J5
J3
J1
G9
G8
G6
F6
E9
D6
C9
C8
C7
C6
A9
A8
F4
E1
C4
A1

F7

+1.0V_LOM

E8
D7

E5

H3
F2

B3

G5

+1.8V_LOM

F5
D5
C2

G4

+1.0V_LOM

E4
D4

B1

+1.8V_LOM

CTRL_10

C3

CTRL_18

B2

LAN_THERM_D_P

A2

LAN_THERM_D_N

A3

Layout Note:
Keep this resistor on
top side.

12

C394

0.1U/10V

Y4
25MHz

2

C410
27P/50V

1 2

C411
27P/50V

1 2

12

C396

0.1U/10V

R305*0

12

C380

0.1U/10V

2

+3VM_LAN_SW

1 2

12

12

C392
470P/50V

1

+3VM_LAN_SW

CTRL_10

CTRL_18

C77

4.7U/10V

C377

0.01U/25V

1 2

C376

0.01U/25V

1 2

Q10
BCP69T1

1

B

4

C

C E

2 3
12

C78
10U/6.3V

Q9
BCP69T1

1

B

4

C

C E

2 3
12

C70
10U/6.3V

+1.0V_LOM

+1.8V_LOM

12

12

C367

0.1U/10V

C368

0.1U/10V

+3VM_LAN_SW

PROJECT : OT2

SizeDocument NumberRev

Date:Sheet of

Quanta Computer Inc.

LAN(Nineveh)

1

2442Thursday, March 22, 2007

C40

4.7U/10V

1 2

C54

4.7U/10V

1 2

1ACustom

5

4

3

2

1

LAN

RJ45 Connector

DB2 stage:change to 330 ohm for intel recommend

DD

+3VM_LAN_SW

TO SYSTEM

+3VM_LAN_SW

2

C631

0.1U

+1.8V_LOM

C632

0.1U

2

L56

BLM18AG601SN1D

1
2
3

4
5
6

7
8
9

10
11
12

1 3

U18

TCT1
TD1+
TD1-

TCT2
TD2+
TD2-

TCT3
TD3+
TD3-

TCT4
TD4+
TD4-

NS892402P

PR_INSERT_DOCK#(14,32)

CC

DB1A tage:Remove U1, RP24,
RP25, RP26, RP27, and
RP1,C24,C26,C28,R941-R951

DB2 stage:change to +1.8V_LOM for intel
recommend

LAN TRANSFORMER

TX0P_R(24)
TX0N_R(24)

TX1P_R(24)
TX1N_R(24)

TX2P_R(24)
TX2N_R(24)

BB

TX3P_R(24)
TX3N_R(24)

C629

C630

0.1U

0.1U

DB2 stage:add for intel
recommend,please make sure this
capacitor(C629-C632) is 16V,X7R

LAN_LED_M#LAN_LINKLED#

R985
10K Q54

2N7002E

R986
10K

Q55

2N7002E

DTC144EUA

1 3

Q57
DTC144EUA

PV stage:add for EMI

24

MCT1
MX1+

MCT2
MX2+

MCT3
MX3+

MCT4
MX4+

MX1-

MX2-

MX3-

MX4-

XTX0P

23

XTX0N

22
21

XTX1P

20

XTX1N

19
18

XTX2P

17

XTX2N

16
15

XTX3P

14

XTX3N

13

R6
75/F

TO DOCK

3

1

2

2

3

Q56

LOM_ACTLED#LAN_ACTLED_M#

1

R3

R4

75/F

75/F

C2
1500P/2KV

R2
75/F

LAN_LINKLED#(14,24,32)

LOM_ACTLED#(24,32)

DB2 stage:change to 330 ohm for intel recommend

SI2 stage:change power
source for HP request

+3VM

C22

C21
.1U

C23

.1U

.1U

PVstage:delete C27

PV stage:change to +3VM for
ACBS issue

+3VM

XTX0P

XTX0N
XTX1P

XTX1N

XTX2P

XTX2N
XTX3P

XTX3N

DET_P

R7
*0

+3VM

LAN Energy Detect circuit

82556 Support Deep Smart Power Down Feature for power saving

C1.01U

AA

TX1P_R

C4.01U

SI stage:change to 1.4K from Intel on LAN Energy Detect.

SI2 stage:change to 1.87K for Intel

5

suggestion

TRD0+_ENTX0P_R

TRD1+_ENED_ACT

R810K

R1610K

4

C3

R10

10P

100K

R9
100K

R18

1.87K

R11
*200K

U2

5

G1331

+

1

-

3

2

SI stage:change footprint

4

DB2
stage:install

3

R21

C25

1.5K

.1U

+3VM

XTX0P(32)
XTX0N(32)

XTX1P(32)
XTX1N(32)

XTX2P(32)
XTX2N(32)

XTX3P(32)
XTX3N(32)

LAN RESET

R967

120K

DB1A
stage:add

ENERGY_DET(12)

C622

0.1U

CN14

9

G+

10

G-

1

TX+/0+

2

TX-/0-

3

RX+/1+

4

NC1/2+

5

NC2/2-

6

RX-/1-

7

NC/3+

8

NC4/3-

11

Y+

12

Y-

13

DET1

14

DET2

15

GND

16

GND

RJ45

3VPCU3VPCU

5

2 4

1

3

C621

0.1U

U43
7SV17

R1330

+3VM

R5330

DET_P(14)

LAN_LED_M#

XTX0P
XTX0N
XTX1P
XTX2P
XTX2N
XTX1N
XTX3P
XTX3N

LAN_ACTLED_M#

DET_P

10 ms time delay

D25

C620

0.1U

5

2 4

U42

1

3

7SV17

SI2 stage:no install R973 ,install
Q48 for HP request

CH751H-40HPT

R968100K

21

+3VM transfer to +3VM_LAN_SW

DB1A
stage:add

Q50

*2N7002E

2

2

LAN_PHYPC(14)

2

ACPRES(26,33)

MAINON(22,31,34,36,37,38,39,40)

SI2 stage:no install Q50,Q51
,install R976 for HP request

2

3

1

LAN_RST#(14)

R974
1M/F

R975

3

100K

Q49

2N7002E

1

3

Q51

*2N7002E

1

SizeDocument NumberRev

Date:Sheet of

SI2 stage:EMI suggest

LAN_LED_M#LAN_ACTLED_M#

C667
*.1U

*0

R973

SI2301DBS

2

Q48

C623

1000P

C668
*.1U

+3VM_LAN_SW+3VM

3

1

C624

4.7U/10V/0805

R976

0

PROJECT : OT2

Quanta Computer Inc.

Transformer&RJ45

1

2542Thursday, March 22, 2007

1AC

PLTRST#
LAD0/FWH0

LAD1/FWH1
LAD2/FWH2
LAD3/FWH3

VIN

5

R10320

LOOPBACK

SI stage:add for EA team easy test

PCLK_DBP_1(17)

LFRAME#/FWH4

+3V

DD

R9870
R9880

500mA

For debug(BIOS)

PCLK_KBC

R301
*33

C372
*10P

PV stage: reserve for lid S/W for EC side

14M_KBC

R291
*33

C366
*10P

KBCLK(30)
KBDAT(30)

PLTRST#(13,19,28,30)

SERIRQ(14,20,30)

3VPCU

KSIN[0..7](29)

+5V +5V

R323
10K

TS_CLK(29)
TS_DAT(29)

R3000

R943*0

CC

FOR EMI

NPCI_RST#(14)

BB

DB2 stage:move T/P connector to Finger
board

AA

DB2 stage:change pin12 to VIN, pin16 to
VCC1_PWRGD,reserve R987,R988 for +3V

CN6

87216-24

SPI_CS1#_1

SPI_HOLD#_R

KSOUT[0..11](29)

LID_SW_EC#(18)

R2961K

1
2
3
4
5
6
7
8
9
10
11
12

13
14
15
16
17
18
19
20
21
22
23
24

R3650

R500

12

POWER_LED#
CAPSLED#
NUMLED#

VCC1_PWRGD

SPI_CLK_1(31)
SPI_CS0#_1(31)
SPI_SI_1(31)

SPI_HOLD#_R
SPI_CS1#_1

LOOPBACK

12

12

3VPCU

SPI_CS1#(13,14)

R329
100K

CELL_DET(34)

KSIN[0..7]

KSIN0

R997
10K

LAD0/FWH0(12,30)
LAD1/FWH1(12,30)
LAD2/FWH2(12,30)
LAD3/FWH3(12,30)

LFRAME#/FWH4(12,30)

14M_KBC(17)

C31
22P

KSIN1
KSIN2
KSIN3
KSIN4
KSIN5
KSIN6
KSIN7

SI stage:R1045-R1048

T88
T10

PCLK_KBC(17)

CLKRUN#(14,20,30)

R10110

3VPCU

+5V +5V

R319
10K

DB1A stage:Add

SERIRQ

DB2 stage:install 0 ohm

RUNSCI_EC#(14)

C370
*10P

C35
22P

R996
10K

Y1

32.768KHZ

21

SPI_SO_1(31)

SPI_HOLD#(31)

4

3VPCU

C362
10U/10V/0805

PV stage:install
R1062 ,no install
R995

KSOUT0
KSOUT1
KSOUT2
KSOUT3
KSOUT4
KSOUT5
KSOUT6
KSOUT7
KSOUT8
KSOUT9
KSOUT10
KSOUT11

T154
T86

T83

R10450
R10460
R10470
R10480

EMCLK
EMDAT

LAD0/FWH0
LAD1/FWH1
LAD2/FWH2
LAD3/FWH3
LFRAME#/FWH4

PCLK_KBC
CLKRUN#

14M_KBC

ADP_PS1

KBC_XTAL1
KBC_XTAL2KBC_XTAL2

R31

*4.7K

RSMRST#_R

MD2

C364
1U

108

U4

21
20
19
18
17
16
13
12
10

9
8
7
6

5
81
83

4

29
28
27
26
25
24
23
22

35
36
38
40
41
42

46
48
50
51
52
53
54
55
57
59

45
76

70
71

TQFP128-16X16-4

C371

C363

0.1U

VCCRTC

C365

0.1U

123303132333462636465666794959697127

NCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNC

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12/GPIO00/KBRST
KSO13/GPIO18
GPIO04/KSO14
GPIO05/KSO15
GPIO24/KS016
GPIO26/KSO17/(EA~)

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

IMCLK
IMDAT
KCLK
KDAT
EMCLK
EMDAT

LAD0
LAD1
LAD2
LAD3
LFRAME~
LRESET~
PCI_CLK
CLKRUN~
SER_IRQ
CLOCKI

LPCPD~/GPIO23
EC_SCI~

XTAL1
XTAL2

R580

Q8

*MMBT3906

1 3

2

C384

0.1U

0.1U

DB1A
stage:add

R995

*0

43

44

NC

NC

Keyboard/Mouse Interface

LPC Bus

AGND

72

RSMRST#(14)

R283

10K

DB1A stage:no install R31,Q8,install
R58

C369

0.1U

R984

*0

R10620

KBC1070

GND

GND

11

3

+3V

SI stage: R1005 install,R297 no install

R1005

C389

C398

0.1U

0.1U

3VPCU

68

128

NC

119

58

1064939

14

84

VCC0

VCC1

VCC1

VCC1

VCC1

VCC1

VCC1

RESET_OUT~/GPIO06

GPIO19/WINDMON/24MHZ_OUT

General Purpose I/O Interface

GND

GND

GND

GND

GND

CAP

117

10482564737

15

C101

4.7U/10V

3VPCU

0

R297*0

C374

0.1U

VCC2

OUT0

OUT1/IRQ8~

OUT7/SMI~
OUT8/KBRST
OUT9/PWM2

OUT10/PWM0
OUT11/PWM1

GPIO01
GPIO02
GPIO03

GPIO07/PWM3

GPIO08/RXD

GPIO09/TXD

GPIO11/AB2A_DATA

GPIO12/AB2A_CLK

GPIO13/AB2B_DATA

GPIO14/AB2B_CLK
GPIO15/FAN_TACH1
GPIO16/FAN_TACH2

GPIO17/A20M

GPIO20/PS2CLK
GPIO21/PS2DAT

32KHZ_OUT/GPIO22

GPIO25/(PGM)

GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
GPIO32

AB1A_DATA

AB1A_CLK

AB1B_DATA

AB1B_CLK

TEST_PIN

PWRGD

VCC1_PWRGD

DMS_LED~/GPIO10

BAT_LED~

PWR_LED~/8051TX

FDD_LED~/8051RX

R287

*4.7K

C76
10U/10V/0805

124
125

BATSELB

123
122
121
120
118

107
79
80
60
85
86
87

CA_DATA

88

CA_CLK

89
90
91
92
101
102
61
103
105
75
73
74
93
98
99
100
126

111
112

ABDATA

109
110

TEST_PIN

69
78
77
116
113
115
114

TEST_PIN

R288

1K

A_SD

KBC_PW_ON

CC-SET

MBAT_ID

GATEA20_R
ADP_PS0
NUMLED#
SLP_S3#

GPIO29

MBDATA
MBCLK

ABCLK

3VPCU

HWPG_1

PWM_FAN#

T7

BATLOW#
RSMRST#_R

CA_AKZ

R2890

HWPG_1

R310
10K

2

R322*4.7K

R106010K

T89

R2940

BGA_MON_DET(11,14)
CAP_RST(29)

CA_DATA(29)
CA_CLK(29)

ME_EC_DATA(14)
ME_EC_CLK(14)
AIR_NON_CHG#(33)

SLP_S3#(14,31)
ADP_EN(34)
CA_AKZ(29)
ACPRES(25,33)

GPIO29(14)

12

3VPCU

SERR#(13)

T8
T87

R2850

R2861K

R308
10K

MBDATA

R2994.7K

MBCLK

R3024.7K

AMT ADP_PRES(14)

DB2 stage: change to +3V
power source

ADP_PS0

R29010K

ADP_PS1

R30910K

3VPCU

SI2 stage:add for HP request

KBC_PW_ON(31)

A_SD(23)

POWER_LED#(29,32)

3VPCU

BAT_GRNLED#(29)

PWM_FAN#(29)

3VPCU

MBAT_ID(33)

R304

100K

3VPCU

3VPCU

CC-SET(33)

PWSWON#(31,32)

3VPCU

R295
10K

R1030

10K

SI stage: add to avoid leakage current

MBDATA(33)
MBCLK(33)

HWPG(20,31)
VCC1_PWRGD(31)

LED_BAT#(29)

1

+3V

3VPCU

R316
10K
D5RB751V-40

3VPCU

DB2 stage:change to 100K for
same as Chimay

R284
100K

R292*0

R298
100K
D4RB751V-40

21

3VPCU

Q60
2N7002E

3

2
+3V

SI stage: add to avoid leakage current

CAPSLED#

21

BATLOW#(14)
PWROK(31,39)

HWPG_1

GATEA20(12)

NUMLED#

SUSM#(14,31)

1

KBCCPURST#(12)

EAPD(22,23)

BAV99

5

4

MD1

BAV99

2.2K

R29

3

2

SizeDocument NumberRev

Date:Sheet of

PROJECT : OT2

Quanta Computer Inc.

SMSC 1070

1

2642Thursday, March 22, 2007

1ACustom

5

MB_CRT_R1MB_CRT_R2
MB_CRT_G1
MB_CRT_B1

C662

C661

*18P

DD

SI2 stage:reserve for EMI
suggestion

CRT_G(7)
CRT_B(7)

*18P

CRT_R(7)

L2239nH
L2439nH
L2339nH

*18P

C663

L8BK1608LL680
L10BK1608LL680
L14BK1608LL680

C146
*18P

SI2 stage:change for EMI suggestion

C180

C179

18P

18P

18P

close to Northbridge

CC

PR_INSERT#(14,22)

DOCK_CRT_B(32)

DOCK_CRT_G(32)

BB

PR_INSERT#

MB_CRT_B1

CRT_B_1

MB_CRT_G1

CRT_G_1

Accelerometer Sensor

SES_INT

+3V

AA

SES_INT(13)

SMBDT(4,17,19)
SMBCK(4,17,19)

R228

8.2K

DB1 stage:install R373

C315

C317

10U

0.1U

R21310K

+3V

5

1
2
3
4
5
6
7
8 9

12

C295

0.1U

U12

S

VCC

1B1

OE#

1B2

4B1

1A

4B2

2B1

4A

2B2

3B1

2A

3B2

GND3A

FSAV330QSCX_NL

+3V

U16

13

VDD

11

VDD

4

VDD_IO

10

Reserved

15

Reserved

12

Reserved

1

RDY/INT

2

SDO

3

SDA/SDI/SDO

5

SCL/SPC

6

CS

8

CK

LIS3LV02DL

16

R1140

15
14
13
12
11

MB_CRT_R1

10

NC

GND
GND
GND

CRT_R_1

7

16
9
14

4

MB_CRT_G2
MB_CRT_B2

C116
C133
*18P

*18P

L19110nH
L21110nH
L20110nH

C178

+5V

C153

.1U

2 1

DOCK_CRT_R(32)

S OE#Function

L

H

4

L

L

CRT_R_1
CRT_G_1
CRT_B_1

+3V

C419

0.1U

+5V

5V_CRT

A=B1

A=B2

POLY SWITCH 1.1A

MB_CRT_R2
MB_CRT_G2
MB_CRT_B2

C417

0.1U

3

F1

12

5V_CRT

ESD PROTECTION

U14

1

VCC_SYNC

2

VCC_VIDEO

3

VIDEO_1

4

VIDEO_2

5

VIDEO_3

6

GND

7

VCC_DDC

8 9

BYPDDC_OUT1

CM2009

C418

0.22U

3

C415

0.1U

2

1

CRT PORT

CN22

1617

CRT_CONN

6

111

7

12

2
8

13

3
9

14

SYNC_IN2
SYNC_IN1

DDC_IN2
DDC_IN1

4

10

15

5

16

CRT_HSYNC

15
14

CRT_VSYNC

13

DDCCLK1

12

DDCCLK

11

DDCDATA

10

DDCDAT1

T91

SYNC_OUT2
SYNC_OUT1

DDC_OUT2

DDCDAT2
PR_CRT_HSYNC
PR_CRT_VSYNC

DDCCLK2

R12039
R11739

R354

2.2K

+3V

R351

2.2K

2

For EMI

CRT_HSYNC(7)
CRT_VSYNC(7)

DDCCLK(7)
DDCDATA(7)

R352

2.2K

C161
*10P

5V_CRT

D17

BAS316

C155
*10P

R353

2.2K

C414

C159

*10P

*10P

PR_CRT_HSYNC(32)
PR_CRT_VSYNC(32)

R1220

R3490

DDCCLK2

DDCDAT2

DDCCLK2(32)
DDCDAT2(32)

PROJECT : OT2

SizeDocument NumberRev

Date:Sheet of

Quanta Computer Inc.

CRT PORT

1

2742Thursday, March 22, 2007

1AB

1

2

3

4

5

6

7

8

1.8 inch HDD CONNECTOR

HDD, CD-ROM

PDA[0..2]
PDD[0..15]

PDIOW#
PDDREQ
PDIORDY
PDIOR#
IRQ14
PDDACK#
PDCS1#
PDCS3#

PLTRST_#

HDDLED#(29)

HDD_VDD

PLTRST#

PDA[0..2](12)
PDD[0..15](12)

PDIOW#(12)

PDDREQ(12)

PDIORDY(12)

PDIOR#(12)

IRQ14(12)

PDDACK#(12)

PDCS1#(12)
PDCS3#(12)

PLTRST#(13,19,26,30)

R28233

AA

BB

DB2 Stage:delete CN9,R463,C533,C532,C522,C523,C511,R488

PLTRST_#
PDD7
PDD6
PDD5
PDD4
PDD3
PDD2
PDD1
PDD0

PDIOR#
PDIORDY
PDDACK#
PDA1
PDA0
PDCS1#
HDDLED#

CN19

40-Pin

45
42
2
4

PDD8

6

PDD9

8

PDD10

10

PDD11

12

PDD12

14

PDD13

16

PDD14

18

PDD15

20

PDDREQ

22

PDIOW#

24
26
28

IRQ14

30

PDIAG

32

PDA2

34

PDCS3#

36
38
40
44

46

HDD_VDD

C399

0.1U

HDD_VDD

C390
1000P

60MIL

C403

0.1U

L440_0805

C383
10U/10V/0805

+3V

41

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

43

CC

CDVCC

DD

1

2

CDVCC

CDSEL

--> High, Slave device

3

R178470R

CD-ROM

1

PLTRST_#
PDD7
PDD6
PDD5
PDD4
PDD3
PDD2
PDD1
PDD0

PDIOW#
PDIORDY
IRQ14
PDA1
PDA0

HDDLED#

T39

3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45

CDSEL

47
49

CN26CD-ROM

4

2
4

PDD8

6

PDD9

8

PDD10

10

PDD11

12

PDD12

14

PDD13

16

PDD14

18

PDD15

20

PDDREQ

22

PDIOR#

24
26

PDDACK#

28

IOCS16#

30

PDIAG

32

PDA2

34

PDCS3#PDCS1#

36
38
40
42
44
46
48
50

51

52

51

52

T28

CDVCC

T41
T40

5

C203

0.1U

C208

C209

0.1U

0.1U

6

C206

0.1U

CDVCC

L27
PBY201209T-4A

C211
10U/10V/0805

60MIL

+5V

PROJECT : OT2

SizeDocument NumberRev

Date:Sheet of

Quanta Computer Inc.

HDD,CD-ROM

7

2842Thursday, March 22, 2007

8

1AB

5

KEYBOARD

KEYBOARD

DD

CC

CN7

KSOUT11

30

KSOUT0

29

KSOUT2

28

KSOUT5

27

KB_KSIN14

26

KB_KSIN8

25

KB_KSIN12

24

KB_KSIN10

23

KB_KSIN0

22

KB_KSIN4

21

KB_KSIN2

20

KB_KSIN1

19

KB_KSIN3

18

KSOUT3

17

KSOUT8

16

KSOUT4

15

KSOUT7

14

KSOUT6

13

KSOUT10

12

KSOUT1

11

KB_KSIN5

10

KB_KSIN6

9

KSIN7

8

KB_KSIN13

7

KB_KSIN11

6

KB_KSIN9

5

KSOUT9

4
3

L_BUTTOM

2

R_BUTTOM

1

DB2 stage:change K/B footprint

BB

KB_KSIN0

KB_KSIN8

KSIN1

KB_KSIN2

AA

KSIN3KB_KSIN3

U23

4 3

5

6

UMP11

U26

4 3

5

6

UMP11

KSIN0KSIN4

KB_KSIN9

2

KB_KSIN1

1

KSIN2

KB_KSIN11

2

1

5

CP1*220PX4

1
3
5
7 8

CP2*220PX4

1
3
5
7 8

CP3*220PX4

1
3
5
7 8

CP4*220PX4

1
3
5
7 8

CP5*220PX4

1
3
5
7 8

CP6*220PX4

1
3
5
7 8

CP7*220PX4

1
3
5
7 8

KB_KSIN4

KB_KSIN12

KSIN5

KB_KSIN6KSIN6

KB_KSIN14KB_KSIN10

KSOUT5

2

KSOUT2

4

KSOUT0

6

KSOUT11

KB_KSIN12

2
4

KB_KSIN8

6

KB_KSIN14

KB_KSIN2

2

KB_KSIN4

4

KB_KSIN0

6

KB_KSIN10

KSOUT8

2

KSOUT3

4

KB_KSIN3

6

KB_KSIN1

KSOUT10

2

KSOUT6

4

KSOUT7

6

KSOUT4

KSIN7

2

KB_KSIN6

4

KB_KSIN5

6

KSOUT1

KSOUT9

2

KB_KSIN9

4

KB_KSIN11

6

KB_KSIN13

U24

4 3

5

6

UMP11

U27

4 3

5

6

UMP11

2

1

2

1

5VPCU

BAT_GRNLED#(26)

KB_KSIN13

KB_KSIN5

4

KSIN2

KSIN7

KSOUT[0..11](26)

KSIN[0..7](26)

POWER_LED_1#

POWER_LED#(26,32)

4

3VPCU

10

9
8
7 4

RP28

10KX8

2N7002E

Q24

2

LED

2

KSIN1

1

KSIN0

2

KSIN5KSIN3

3

KSIN4KSIN6

56

3VPCU

KSOUT[0..11]
KSIN[0..7]

D1

R277
10K

3

Q262N7002E

1

R276
10K

3

1

3

TRACK POINT

R_BUTTOM
L_BUTTOM

+5V

TS_CLK
TS_DAT

C618
1000P

TS_CLK(26)
TS_DAT(26)

SI stage: change footprint for another vender

R279330

3

2

1

5VPCU5VSUS

3

2

1

R278
10K

Q272N7002E

2

R275
10K

POWER_LED_1#

Q252N7002E

+5V

BAT_GRNLED#1

R10611K

3

1

Active : LOW

5VPCU

Q64

2N7002E

POWER/SLEEP LED

W/L B/T ON/OFF LED

3

CN8

8
7
6
5
4
3
2
1

TRACK POINT

FAN OUT PWM CONTROL

L450-0805

PWM_FAN#(26)

C421

C424

10U

0.1U

G_BATLED#(12)

Accelerometer LED

ACC_LED(14)

HDD LED

POWER LED

+3V

Active : LOW

RF_LINK(19)

+3V

WWAN#(19)

BT_LED(30)

Active : High

HDDLED#(28)

R53610K
D23

SW1010CPT

2

APPLICATION BUTTON BOARD

CA_CLK

R154.7K

CA_DATA

R134.7K

CA_AKZ

R1022

C7
1000P

C416
1000P

C8
1000P

*10K

5V_FAN

C423
1000P

3VPCU

3VPCU

C6
1000P

3VPCU

DB2 stage:install

C9
1000P

CN25

1
2
3
4

FAN

CAP_RST(26)

CA_CLK(26)

CA_DATA(26)

3VPCU

CA_AKZ(26)

+3V

PV stage:dul-layout for second source

ACC_LED#

LED BOARD

5VPCU

2

LED_BAT#(26)

R53510K

21

2

Q45
DTC144EUA

1 3

POWER_LED_1#

Q44
DTC144EUA

1 3

C614

0.1U

2
1

+3V

3 5

2

HDDLED#
LED_BAT#
BAT_GRNLED#1

C601

0.1U

U41
TC7SH08FU

+5V 5VPCU

R544
10K

RF_LED#

4

SizeDocument NumberRev

Date:Sheet of

R1410

1 2

1 2

R10000/F

RF_LED#

+3V

CA_DATA_1

C11

C10

33P

33P

R543330
R552330

R554330
R556330

FAN ,KB,LED,TP

1

C12

10k

CA_DATA_1

CA_CLK_1

POWER
RF_LED_1#

3VPCU

CAP_RST_1

CA_CLK_1

POWER
RF_LED_1#

CA_AKZ

CAP_RST_1

LED-BOARD

1
2
3
4
5
6
7
8
9
10

CN12

CN37

1
2
3
4
5
6
7
8
9
10
11
12

SW-BOARD

R9980/F

R1210

R10020/F
R1003*0/F

CA_CLK_1

CA_DATA_1

ACC_LED#

PROJECT : OT2

Quanta Computer Inc.

2942Thursday, March 22, 2007

1

CN5

1
2
3
4
5
6
7
8
9
10
11
12

SW-BOARD

1AB

5

FINGER PRINT

DB2 stage:move T/P connector to Finger board,so change connector type

DD

USBP1-(13)

USBP1+(13)

3V_FP

C600
1000P

3V_FP

R5390
R5400

C599

0.1U

USBP1-1
USBP1+1

KBCLK(26)
KBDAT(26)

+5V

CN11

C634

Finger Printer/Touch pad

0.1U

8
7
6
5
4
3
2
1

4

SI stage:it make for a much smoother transition when modems transition to deriving the IO voltage from that pin

MDC

CN28

1 2

ACZ_SDOUT_MDC(12)

ACZ_SYNC_MDC(12)

ACZ_SDIN1(12)

ACZ_RST_MDC#(12)

ACZ_SDOUT_MDC
ACZ_SYNC_MDC

R18433
C246*10P

CN16

2
1

MDC

AC_SDIN1

GNDREV

3 4

A_SDOREV

5 6

GNDVCC

7 8

A_SYNCGND

9 10

A_SDIGND

11 12

A_RST#A_BCLK

MDC

RJ11 CONNECTOR

TIP

RING

C37

C30

1000P

1000P

3

3VSUS

C230

0.1U

ACZ_BITCLK_MDC

R185
*33

C247
*10P

CN17

1

TIP

GND
GND

2

RING

RJ11

C239

2.2U

ACZ_BITCLK_MDC(12)

3
4

C235
1000P

2

+3V_BT

3V_S5

R5530
R5500

R538
10K

R549

1 2

220K

USBP6+(13)

BT_LED(29)

CH_DATA(19)

CH_CLK(19)

SI stage:Change power source to avoid leakage currurt

BT_OFF(13)

USBP6-(13)

BT_OFF

BLUE TOOTH

1

USBP6+1
USBP6-1

2
3
4
5
6
7
8

3VSUS

1

Q46

2

IRLML5103

3

1

CN35

1
2
3
4
5

10

6

10

9

7

9

8

BLUE TOOTH

24mil

C359
1000P

12

C356
100U/10V

+3V_BT

C358

0.1U

SI2 stage:delete R280,R281for EMI suggestion

CC

TPM (1.2)

5VSUS

C440
1U

U29

5 1

INOUT

4 3

ON#SET

2

GND

G5240

USBPWR0_1

R368
*6.8K

R3690-0805

C441
470P

C439

+

220U/6.3V_ESR25

PV stage:change to 220U for USB drop fail issue

R1760

EB1

1432

*1632090

R1730

R79

0

*1000P

1
43

12

C218
*Clamp-Diode

C97
1U

R93
10K

R88

C93

*0

12

9

3
5

4
6

13

USBP0-(13)

BB

AA

USBP0+(13)

5VSUS

USBOC#5(13)

2

12

C213
*Clamp-Diode

U7

IN
IN

SEL
FAULT

ON(ON)
GND

THREMAL-G

MAX1563

ESD

USBPWR0
USBP0-1
USBP0+1

NC

OUT
OUT

ISET

NC
NC

8
10

1

7

11
2

CN27

8

1

GND

7

2

GND

3

GND

4GND

Suyin_020173

USB 1

6
5

PV stage:change to 220U for USB drop fail issue

R72

4.22K

4.7U/10V/0805/X5S
C90

C73

+

220U/6.3V_ESR25

USBP5-(13)

USBP5+(13)

C102

0.1U

I Limit:17120/R814

5

4

=17120/4220=4.05687A

R107
*33

C129
*10P

FOR EMI

Address

HIGH
LOW

C108
1000P

R3260

EB2

2

1432

*1632090

R3310

3

PCLK_TPM

LAD0/FWH0(12,26)
LAD1/FWH1(12,26)
LAD2/FWH2(12,26)
LAD3/FWH3(12,26)

PCLK_TPM(17)

LFRAME#/FWH4(12,26)

PLTRST#(13,19,26,28)

SUS_STAT#(14)

SERIRQ(14,20,26)

CLKRUN#(14,20,26)

BADD
4EH/4F(default)
2EH/2FH

POWER USB (LEFT SIDE)

USBPWR1

C92
*Clamp-Diode

USBP5-1
USBP5+1

12

C99
*Clamp-Diode

ESD

43
1

12

LAD0/FWH0
LAD1/FWH1
LAD2/FWH2
LAD3/FWH3
PCLK_TPM

LFRAME#/FWH4
PLTRST#
SUS_STAT#
SERIRQ

CLKRUN#

+3V

R116

4.7K

R115
*4.7K

CN21

1

GND

2

GND

3

GND

4GND

Suyin_020173

2

U10

26

LAD0

23

LAD1

20

LAD2

17

LAD3

21

LCLK

22

LFRAME#

16

LRESET#

28

LPCPD#

27

SERIRQ

9

TEST/BADD

15

CLKRUN#

1

NC

3

NC

12 14

NCXTALO

SLB9635

8
7
6
5

10

VDD

19

VDD

24

VDD
VSB

GND
GND
GND
GND

GPIO

GPIO2

TESTI

XTALI/32K IN

5
4

11
18
25

6
2

7

PP

8
13

TPM_XIN
TPM_XOUT

C122

0.1U

R109*0
R110*0

Y3

32.768KHZ

C148
22P

USB 2

PROJECT : OT2

SizeDocument NumberRev

Date:Sheet of

Quanta Computer Inc.

USB,BT,FP,TPM,MDC

C137

0.1U

+3V

+3V

C111

C135

0.1U

0.1U

R90

R100

*4.7K

*4.7K

+3V

R91

R103

4.7K

4.7K

21

C147
22P

3042Thursday, March 22, 2007

1

1ACustom

5

POWER SEQUENCE

DD

3VPCU

R303
100K

C373

0.1U

CC

DELAY_VR_PWRGOOD(7,14,39)

PWROK(26,39)

INT_VGA_PWRGD(38)

HWPG_1.25V(36)
HWPG_3/5VPCU(35)
HWPG_1.05VM(36)
HWPG_1.8VSUS(37)

DB1A stage: no install
D7,D13,D14,C95

3VPCU

5

2 4

U19
7SV17

1

3

R9420

R3440

D7*BAS316 C625
D11BAS316
D12BAS316
D13*BAS316
D14*BAS316

VCC1_PWRGD

R345
10K

3V_S5

2
1

3 5

VCC1_PWRGD(26)

C413

0.047U

4

U25
TC7SH08FU

XDP_DBRESET#(4,14)

4

+3V

R89
10K

HWPGVRON

C95
*1U

DB1A stage: reserve for
power sequence modify

3V_S5

2
1

U22

3 5

TC7SH08FU

C408

0.047U

4

+3V

5

2 4

1

3

HWPG(20,26)

R3330

R343
10K

D27*1SS355

*0.1U

R989*180K

U44
*7SV17

R9800

SPI_CLK_1(26)
SPI_CS0#_1(26)

3

21

C627
*1U

ICH_PWROK(14)

SI2 stage:delete R49

+3V

5

2 4

1

3

R361

C626
*0.1U

U45
*7SV17

SPI_HOLD#(26)

R367

2

HWPG_1.25VM(36)

D29

HWPG_1.05VM

R993
10K

C426

0.1U

12
12

HWPG_1.8VSUS

+3VM

SPI_WP0#

SPI_CLK_R_0
SPI_SI_R_0SPI_S0

3V_S5

VRON(38,39)

SPI_CS0#(13)
SPI_CLK(13)

SPI_SI(13)

12

12

SPI_CS0#

SPI_CLK

SPI_CLK

0

SPI_CS0#

0

SMDDR_VTERM

R9943.3K

+3VM

+3VM

R362

C431
*33P

3.3K

R3553.3K

R3570

R3560

C432

C433

*33P

*33P

PV stage:change R357,R356 to 0 ohm,and C431,C432,C433 no install for intel request

R9920

Q59

2

MMBT3904

1 3

16Mbit (2M Byte), SPI

CN23

8

VSS

VCC

3

W

7

HOLD

1

S

6

C

5

Q

D

G6179-1001

CH751H-40HPT

CH751H-40HPT

3

2

1

FLASH ROM(BIOS)

4

SPI_SO_R_0SPI_SO

2

21

D30

21

D28

CH751H-40HPT

Q58

*2N7002E

R36615

1

21

C430
33P

MPWROK(7,14)

SPI_SO(13)

SPI_SI_1(26)

POWER SWITCH

BB

SW1

1
3 4
5

AA

5

2

3VPCU

2
1

R113*0

3VPCU

2
1

R108*0

3VPCU

R318
10K

C386

0.1U

3VPCU

C151

0.1U

C381

0.1U

S5_ON

MAINON

4

U13
TC7SH08FU

3 5

3VPCU

4

U11
TC7SH08FU

3 5

3V_S5

2

3

Q28
2N7002E

R9790

DB1A
stage:add

S5_ON(40)KBC_PW_ON(26)

MAINON(22,25,34,36,37,38,39,40)SLP_S3#(14,26)

1

4

R9780

DB1A stage:add

PWSWON#

SLP_S5#(14)

NBSWON#

PWSWON#(26,32)

2
1

R312*0

SUSM#(14,26) IAMT_ON(36,37,40)

3VPCU

3 5

2
1

R94*0

U20
TC7SH08FU

3VPCU

3 5

3VPCU

SPI_SO_1(26)

NBSWON#(14)

C118

0.1U

4

3VPCU

4

U9
TC7SH08FU

C131

0.1U

R147

R146

SUSON

IAMT_ON

3

0

12

0

12

SUSON(37,40)

SPI_SI

SPI_SO

SI stage:delete CN24 due to only one 4MB
flash part

C121

0.1U

+1.05V

C136

0.1U

C130

0.1U

C134

0.1U

+5V

C679

0.1U

C680

0.1U

C681

0.1U

5VSUS

C682

0.1U

C152

0.1U

C157

0.1U

C119

0.1U

+3V

C103

C110

0.1U

0.1U

EMI

PROJECT : OT2

SizeDocument NumberRev

2

Date:Sheet of

Quanta Computer Inc.

POWER SEQUENCE,BIOS

1

3142Thursday, March 22, 2007

1ACustom

A

VA

12

12

C674
.1U/50V_6

12

C675
.1U/50V_6

C673
.1U/50V_6

PV stage:for EMI

44

request

LAN

12

C676
.1U/50V_6

12

12

C677

C678

.1U/50V_6

.1U/50V_6

VA

XTX0P(25)
XTX0N(25)
XTX1P(25)

XTX1N(25)

XTX0P
XTX0N
XTX1P
XTX1N

DB2 stage:modify due to no LAN S/W

USB
TV

33

CRT
Line-out

USBP7+(13)

USBP7-(13)
TV_C/R(7)

TV_Y/G(7)

POWER_LED#(26,29)

DOCK_HP_OUT_L(23)
DOCK_HP_OUT_R(23)

DOCK_HP_OUT_L
DOCK_HP_OUT_R

Pin43 for Dock detect

B

DOCKING BOARD CONNECT

51

C360

0.1U

TV_C/R
TV_Y/G
POWER_LED#

DOCK_CRT_B_1
DOCK_CRT_G_1
DOCK_CRT_R_1

AGND

C361

0.1U

5VSUS

R330
R370

R680
R650

+5V

USBP7+1
USBP7-1

CN15

49
47
24

25
26
27

28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46

50
48
1

2
3
4

5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

DOCK

52

C

XTX2P
XTX2N
XTX3P
XTX3N

5VSUS

LAN_LINKLED#
LOM_ACTLED#

PWSWON#
PR_INSERT_DOCK#
DDCDAT2
DDCCLK2
PR_CRT_HSYNC
PR_CRT_VSYNC

AGND

LINE_IN_SENSE

DOCK_HP_SENSE

R750
R700

DOCK_LINE_IN_L

DOCK_LINE_IN_R

ADP_ID

D

XTX2P(25)
XTX2N(25)
XTX3P(25)
XTX3N(25)

LAN_LINKLED#(14,24,25)
LOM_ACTLED#(24,25)

ADP_ID(33,34)
PWSWON#(26,31)
PR_INSERT_DOCK#(14,25)

DDCDAT2(27)

DDCCLK2(27)

PR_CRT_HSYNC(27)

PR_CRT_VSYNC(27)

LINE_IN_SENSE(22)

DOCK_HP_SENSE(23)

DOCK_LINE_IN_L(22)

DOCK_LINE_IN_R(22)

LAN

DOCK_CRT_B(27)

DOCK_CRT_G(27)
DOCK_CRT_R(27)

CRT

Line-in

E

C51
*5.6P

DOCK_CRT_B_1
DOCK_CRT_G_1
DOCK_CRT_R_1

C38
*5.6P

L4BK1608LL680
L5BK1608LL680
L6BK1608LL680

C60
*5.6P

ADP_ID

C660
1000P

SI2 stage:add for EMI suggestion

3V_S5

R34
10K

PR_INSERT_DOCK#

C36

0.1U

EMI spring

PAD8

1

22

PAD3
EMIPAD-276X100

EMI spring

PAD7

1

EMI spring

PAD6

11

1

1

PAD1
EMIPAD-276X100

1

EMI spring

PAD5

1

PAD2
EMIPAD-276X100

1

EMI spring

PAD4

1

H22
h-c59d59n

1

H23
h-O91x59d91x59n

1

Area of Hole

H3
H-C313I160D110P2

1

H8
h-c313d118p2

1

H10
h-c197d47p2

1

H13
h-c197d47p2

1

H12
H-C313I160D110P2

1

H7
h-c313d118p2

1

H15
H-C315I160D110P2

1

H11
H-C313D110P2

1

H6
H-C313D110P2

1

H9
h-r313x165d118p2L

1

H5
H-C313D110P2

1

H2

H-OT1-2-2P

1

H19
H-C313D110P2

1

H14
h-c313d118p2

1

H1
H-OT1-1-2P

2

1

2

H18
h-c313d118p2

1

H4
H-C313D110P2

1

H16
h-c157d47p2

1

H17
h-c157d47p2

1

H20
h-c157d47p2

1

H21
h-c157d47p2

1

SI stage:for modem cble and mic cable

A

B

C

D

+1.05V +3V
+1.05V
+1.05V
+1.05V 5VSUS

1.8VSUS +1.5V

1.8VSUS

+1.5V
+1.5V

SizeDocument NumberRev

Date:Sheet of

EC4470P
EC11*0.1U
EC12*0.1U
EC2*0.1U
EC8*0.1U

EC16*0.1U
EC17*0.1U

+5V

EC5*0.1U
EC6*0.1U

EC1*0.1U

EC10*0.1U
EC14*0.1U
EC13*0.1U

FOR EMI

PROJECT : OT2

Quanta Computer Inc.

DOCKING

+3V
5VSUS

+3V
+3V

+3V
+3V

+3VVA

3VPCUVIN
+3VVIN
+3VVIN

3242Thursday, March 22, 2007

E

1AB

5

AC power from docking or system AC

EE

DD

CC

BB

Normal:19.5 Volts
Airline:15.0 Volts

If AC voltage lower then 16.3V will
disable charger/charge LED/OS
charge icon.

AIR_NON_CHG#(26)

CC-SET(26)

Present AC:
When AC voltage level > 12.3 Volts.

8724_ACIN

3

PQ67

2N7002K

2

1

jack.Will not present at the same
time.

JP3

1
2
3
4

7

56

POWER JACK

PR40

8724_SHDN1#8724_SHDN1#8724_SHDN1#8724_SHDN1#8724_SHDN1#8724_SHDN1#

0_4

Change PR196 from

30.1K change to 16.5K

EC: SI1

PR196

16.5K/F_6

3VPCU

PR191

PR192

470_4

1M/F_4

PD15

CH501H-40

ACPRES(25,26)

PD20

SW1010C

2 1

2

21

12

PC125
.1U/50V_6

PC363

1U/25V_X6S_8

PR387
1M_4

PR204
10K_4

PR205
15K_6

3VPCU

PC362

1 2

1000P_4

JP3-1

JP3-2

PR41
10K_4

PU2
LMV331

8778REF(34,35)

3

EC:DB2

PQ50

2N7002E-T1-E3

1

2

ADP_ID(32,34)

PL7

FBMJ3216HS800

12

PC100
.1U/50V_6

PL6

FBMJ3216HS800 PR125

AIR_DET(34)

5VPCU

PC52

1 2

.01U/16V_6

5

1

+

4

3

-

2

8778REF

PC49

2200P_4

PC128
10U/10V_8

PR197

49.9K/F_4

12

PC141

PR209

*1000P_4

20K_6

PR210
10K_4

8724_LDO

13

PQ51
DTA124EUA

ACOK#ACOK#

CC-SET(26)

ACOK#ACOK#

EC: SI1

12

PC99
.1U/50V_6

PR43
75K/F_6

PR46

10.5K/F_6

EC: SI1

*40.2K/F_4

12

PC142
*1000P_4

PD19

2 1

CH501H-40

4

3VPCU

PR199
10K/F_4

PR200

PR213
1K_6

12

PC147
.1U/16V_6

DEL PR211-0ohm

VA

PD9

VA

SBM1040 L-F

2
1

21

PD16

CH501H-40

8724_DCIN

PR44
75K/F_6

PR47
15K/F_6

8724_ACIN

8724_DCIN

PR112

VCTL

0_4

ICTLICTLICTLICTL

REFIN

ACOK#
ICHGICHG
IINPIINP
SHDN#

CCV

CCI

12

CCSCLS

PC148
.01U/50V_6

12

SHDN#

12

PC184

PR211

.1U/16V_6

470K/F_4

I_SET(34)

3

12

12

PC146
1U/25V_8

27

PU11

CSSP

1 2

DCINLDO

10

ACIN

15

VCTL

MAX8765

13

ICTL

12

REFIN

11

ACOK

9

ICHG

28

IINP

8

SHDN

7

CCV

6

CCI

5

CCS

GND

PC149

14

.01U/50V_6

PC4
.1U/50V_6

26

CELLS

CSSN

DLOV

BST

DHI

DLO

PGND

CSIP
CSIN

BATT

REF

CLS

GND

29

VAD

PR10
0_4

CSSP

12

PC23

.1U/50V_6

PR183*0_4

CELLS

17

8724_DLOV

22

CHG_BST

24

CHG_DHCHG_DH

25

CHG_LX

23

LX

CHG_DL

21
20

19
18

MBAT+

16

8724_REF

4

3

CLS connect to REF
For Full-scale 75mV

PR1310K/F_4

PR12

100/F_4

PC19

1 2

.1U/50V_6

Float= 3 CELLS
REFIN=4CELLS

PC145
1U/10V_6

1 2

8724_LDO8724_LDO8724_LDO8724_LDO

PR212

0_4

PR214

PR203

3

ADAPTER 65W 19.5 Volts 3.33A
ADAPTER 90W 19.5 Volts 4.61A

PQ31

AO4407

1
2

PQ28

IMD2

12

PQ5
SI4814DY L-F

PR172

*2.2_6

3VPCU

PC101
*.1U/50V_6

EC: SI1

PR110
100K_4

5
4

PC42
2200P_4

3

PC120

*1000P_4

3

1

4

PR120
10K_4

PR124
*10K_4

2

PQ24
*2N7002E

PC43
.1U/50V_6

1 2

12

PR145

PC107

220K_6

.1U/50V_6

1 6
2

CSSN

PQ21
*2N7002E

REFIN

EC DB2

33_6

PC152
1U/10V_6

1 2

21

PD17

CH501H-40

0_4

12

PC132

.1U/50V_6

PC150
1U/10V_6

1 2

Change PR110 from
10K to 100K
Remove
PR113,PR130,PC105,PC24,PR131,PR132,PQ25,PQ26

AC_DISAC_DIS

3

1

123

D1

G1

876

MBAT_ID(26)

2

S1D2

3

AC_LATCHAC_LATCH

PR123
*1M_6

4

S2

G2

5

CSIP(34)
CSIN(34)

8
7
6
5

VA

VIN_CHGVIN_CHG

PL4

4.7uH L-F

AC_DIS_G(34)

PR141
*680K_6

12

PC108
*.1U/50V_6

VIN_PRO

CN18

BAT_CONN

2

VIN

PR118

220K/F_6

0_4

VIN

PD10

2 1

*UDZ2.7B

PR128
*680K_6

PR127
*680K_6

PL3

HI0805R800R_5A

PC45
10U/25V/1206

PR22

2

1

2

2P 1P

2P1P

15m/1W/3720 L-F

MBATMBAT
MB_DATAMB_DATA

4567

MB_CLK

3
12

MBCLK(26) MBDATA(26)

PD8
UDZS5.6B

DC/C-(34)

VIN

PC109
10U/25V/1206

1

MBAT+

PC6
.1U/50V_6

EC: SI2

PR135

PR134

100_4

100_4

PD7
UDZS5.6B

2 1

2 1

PD1

SBM1040 L-F

1

3

2

PQ3
AO4407

8

1

7

2

6

3

5

VA

4

PR115

*10K_4

PR116
10K_6

3

PQ29

2

2N7002E-T1-E3

1

When system with AC and DC can
support DC discharge for Battery
learning.

PC7

PC8

10U/25V/1206

10U/25V/1206

PL2

FBMJ3216HS800

PC106
.01U/50V_6

1

MBATR

MBAT+

PR393
100K_6

AA

PROJECT : OT2

SizeDocument NumberRev

5

4

3

2

Date:Sheet of

Quanta Computer Inc.

CHARGE(MAX1908/8724)

1

3342Thursday, March 22, 2007

1AC

5

4

3

2

1

EC: SI1

+5V

1 2

1

2

3

PC117
*.1U/16V_6

VA

GAIN 20

PU8

SHDN

GND

VCC

*SC310A

ADP_ID(32,33)

PR137

150K_6

PR242
220K_6

PR241
220K_6

OUT

CS-

CS+

8778REF

2

6

5

4

3

1

PR175
*0_4

PR185

*0_4

PR184
*0_4

*49.9K/F_4

PR160

100_4

5.63~5.76V

PQ62
2N7002E-T1-E3

PR182

*182K/F_6

PR181

4

CSIP(33)

CSIN(33)

1

PR161
191K/F_6

+5V

*.1U/16V_6

1 2

5

1

+

4

3

-

*LMV321
PU9

2

PC121

*.22U/10V_6

PQ40

IRLM5103

3

2

PR162

3.9K/F_4 PR167

PR164

22.6K/F_6

1
3

PR166
10K/F_4

PC118

VA

5

-

+

2

PR177

*1K_4

1 2

PU5
TL331

PR163

1M/F_4

PC114

3900P_6

PC111
.1U/50V_6

1 2

4

21

100K_4

VA

PD14

*CH501H-40

2

PR158
47K_6

CH501H-40

3

PQ42
SST3904

1 3

PD13

21

PR168

*39K/F_4

I_SET(33)

VA

PR144
220K_6

PR143
220K_6

+5V

PR27
*133K/F_6

PR28
*80.6K_6

2

2

DD

CELL_DET(26)

PR170
*100K_4

CC

EC: SI1

BB

AA

AC_DIS_G(33)

5

1 2

PU6B

6
5

EC: SI1

3VPCU

PR19

*100K_4

+5V

84

3

+

2

-

PC41
*0.027U/16V_6

-

7

+

*LM393

PR31

*330K_4

PR165

10K_4

3

PQ39
2N7002E-T1-E3

1

3

PQ38
2N7002E-T1-E3

1

PU6A
*LM393

PC110
*.1U/16V_6

1 2

1

PR18
*604K/F_6

+3V

PR30
*10K_4

AIR_DET(33)

+5V

PR17
*10K_4

+3V

PR29
10K_4

3

2

PQ4
*2N7002E

1

OCP#(14)

PQ44
IRLM5103

1

3

DC/C-(33)MAINON(22,25,31,36,37,38,39,40)

2

ADP_EN(26)

PROJECT : OT2

SizeDocument NumberRev

2

Date:Sheet of

Quanta Computer Inc.

CHARGER II

1

3442Thursday, March 22, 2007

1AB

5

DD

5 Volt +/- 5%
Design Current: 4.9 A
Maximum current:7A
OCP minimum 8A

5VPCU

CC

220U/6.3V_ESR25

S4_STATE_PWR(40)

BB

AA

PC187

EC:DB2

MAIND

+

+

PC57
220U/6.3V_ESR25

5VPCU

578

3 6

241

12

PC55
.1U/10V_4

5VPCU

578

3 6

241

12

PC56
.1U/10V_4

1 2

PQ9
SI4800BDY

.1U/10V_4

1 2

PQ10
SI4800BDY

PC140

.1U/10V_4

3.4A

5VSUS

PC151

3.8A

+5V

12

PC53
.1U/50V_6

12

PC54
.1U/10V_4

PC58
.1U/10V_4

PR49
0_4

PR48
*0_4

Place these CAPs
close to FETs

PL10

2.2UH/8A (DCR-18)

1 2

PQ52

AO4422

PQ53

AO4422

4

PR194
390K_4

12

PR195
150K_4

PR33

12

0_8

VIN

12

PC143
1000P_4

578

5V_DH

3 6

241

5V_LX

578

3 6

241

PR215
*22_8

1 2

PC153

*1500P_4

1 2

12VAL(40)

3VPCU

PC144
.1U/50V_6

PC137
.1U/50V_6

12VAL

PC25
.1U/50V_6

12

+

PC134

10U/25V/1206

PC139

0.1U/10V_4

5VPCU

PR207
402K/F_4

EN

PR206
0_4

PC136
.1U/50V_6

5V_DL

5VPCU

1

PD3
BAT54S

2

1

PD2
BAT54S

2

PC126
.1U/50V_6

PC26
.1U/50V_6

IAMT_OND_WOL(40)

PC183

0.1U/10V_4

1 2

9
10
11
12

PGOOD1PGOOD2

13
14
15
16
37
36

PR208

1 2

1_6

PC133

3

.1U/50V_6

PC130

.1U/50V_6

3

PR193

1 2

200K/F_4

PC364

*10P_4

PQ1

AO6402

6
5
2
1

3

PC131
.1U/50V_6

BYP
OUT1
FB1
ILIM1
PGOOD1
ON1
DH1
LX1
PAD
PAD

12

+3VM

4

12

PAD

PAD

PAD

333435

5V_AL

PC138

4.7U/10V_8

PC3
.1U/50V_6

3

8

LDO

LDOREFIN

ISL6236IRZA

BST1

DL1

17181920212223

12

2

5V_AL

PR57
100K_4

PR234

EN

PR236

*0_4

5V_AL

PC135
1U/10V_6

PR188
*0_4

8778REF

PR187

0_4

1234567

IN

REF

RTC

TON

VCC

ONLDO

32

REFIN2

31

ILIM2

30

OUT2

29

SKIP

28

PGOOD2

PU10

VDD

SECFB

PR190
39K/F_4

27

ON2

26

DH2

25

LX2

AGND

PGND

DL2

BST2

24

PR180

BST2

1 2

1_6

PR186

0_6

PR202
47_6

PC124

0.1U/10V_4

400K/500KHz

+5V_VCC1

PR179
402K/F_4

12

PR229
0_4

PC123
.1U/50V_6

0_4

+5V_VCC1

12

PC127
1U/10V_6

EN

1 2

1 2

PR198
*22_8

PC129
*1500P_4

3V_DL3V_DL3V_DL3V_DL3V_DL3V_DL3V_DL3V_DL3V_DL

3V_DH

876

3V_LX3V_LX3V_LX3V_LX

SYS_SHDN#(4)

VIN

578

3 6

241

578

3 6

241

PGOOD2

PGOOD1

3VPCU

5

PQ41
SI4804BDY-T1-E3

PQ49
AO4422

PQ48
AO4422

PR45
100K_4

.1U/10V_4

1 2

12

+

1 2

PC29

PC46
10U/25V/1206

12

PC48
1000P_4

Place these CAPs
close to FETs

PL9

1.5UH/9A (DCR-14)

3VPCU3VPCU

PR37
*100K_4

PR39
0_4

1 2

12

+

PC51
10U/25V/1206

PC47
.1U/50V_6

HWPG_3/5VPCU(31)

3.3 Volt +/- 5%
Design Current:7.5A
Maximum current:11A
OCP minimum 12A

+3.3V_ALWP

PC119

1 2

PC122

0.1U/10V_4

.1U/50V_6
PR178
0_4

PR32
*0_4

Close to Controller

.1U/50V_6

S5_OND(40)

PC34

3VPCU

+

EC:DB2

3V_S5

PC44

220U_4V_ESR25

876

123

PC2
.1U/50V_6

3VPCU

1

+

PC188

220U_4V_ESR25

5

PQ2
AO4812

4

+3VM_CK505

IAMT_OND(40)

PC12
.1U/50V_6

2.55A

+3V

123

4

PC113

.1U/10V_4

MAIND(36,40)

12

2A

3VSUS

12

PC115
.1U/10V_4

SUSD(40)

3VSUS(19,30,38,40)

PROJECT : OT2

SizeDocument NumberRev

5

4

3

2

Date:Sheet of

Quanta Computer Inc.

3v/5v/1.25v

1

3542Thursday, March 22, 2007

1AC

5

4

3

2

1

DD

VIN

PC173

PC86
10U/25V/1206

.01U/50V_6

( 7.32A )

PC156
*100P_4

PC158
*100P_4

+1.05VM

+1.05VM

578

12

PC77
.1U/10V_4

PC75

330UF/2V_ESR9

Ra

8717FB2

PR216
604/F_6

8717FB28717FB2

8717FB28717FB2

PR218

Rb

10K/F_4

PQ13
IRF7821

3 6

241

( 7.32A )

+1.05V

PC186
.1U/10V_4

+1.05VM(9,40)

CC

Vout=(1+Ra/Rb)*1

MAIND(35,40)

BB

PC365

*100P_4

IAMT_ON(31,37,40)

EC: SI1

PL12

1.5UH/9A (DCR-14)

1 2

PR221
487/F_6

PC157

.22U/10V_6

8717REF

PR95
120K/F_4

PR90
100K/F_4

PR79
10K/F_4

CH501H-40

1 2

PD18

8717ILIM28717ILIM18717ILIM1

PC174
1000P_4

PR80
*22_8

PC74
*1500P_4

PR82
120K/F_4

PR81
100K/F_4

578

PQ56
SI4392DY

3 6

241

578

PQ57
SI4856ADY

3 6

241

PR220
0_4

PC159
1U/10V_6

21

8717REF

8717ILIM2
8717ILIM1

8717FB2

PC160

.1U/50V_6

8717DH2

8717LX2

8717DL2

8717_ON1
8717_ON28717_ON28717_ON28717_ON2

1 2

13
14
15

16

12
11

6
7
8

28

2
4

10

8717BST2

PR217
0_6

PU12

BST2
DH2
LX2

DL2

CSH2
CSL2
ON1
ON2
ILIM2
ILIM1
SKIP1
SKIP2
FB2

1

VCC

MAX8717

PGND

18

PR83

0_6

PD5

DAP202U

PC164
1U/10V_6

BST1

GND

CSH1
CSL1

PGOOD1
PGOOD2

FSEL

AGND

19

VDD

DH1

REF

PR224

LX1

DL1

FB1

10_6

2

17
23

1 2

8717DH1

22

8717LX1

21

8717DL1

20

29

24
25

8717FB1

26

HWPG_1.5VM

27
9

8717REF

5

3

3

PC163
1U/10V_6

8717REF

8717BST1

1

5VPCU

PR225
0_6

PC162
.22U/10V_6

PC165
.1U/50V_6

PQ59

SI4856ADY

PC366

*100P_6

PR381
0_4

FSET= GND=200KHz
REF f = 300KHz
VCC f = 500KHz

578

3 6

578

3 6

VIN

PC154

PC155
1000P_4

.01U/50V_6

PQ58
SI4392DY

241

PR97
*22_8

1 2

PC89
*1500P_4

241

EC: SI1

PL13

1.5UH/9A (DCR-14)

1 2

EC: SI1

PR228
487/F_6

PC169

.22U/10V_6

PC82
10U/25V/1206

PC85
.1U/10V_4

12

PC179
330UF/2V_ESR9

( 6.28A/Peak )

+1.5VM

Rc

PR227

5.36K/F_6

+1.5VM

PC171
*100P_4

Vout=[1+(Rc/Rd)]*1

PR226

Rd

10K/F_4

HWPG_1.05VM(31)

+1.5VM

578

MAIND(35,40)

3 6

PC168
*100P_4

PQ64
IRF7821

(6A)

+1.5V

241

PC185
.1U/10V_4

+1.5VM

PC200
10U/10V_8

+3V

5VPCU

PR379
100K_4

HWPG_1.25V(31)

AA

PR223
0_4

MAINON(22,25,31,34,37,38,39,40)

PR237
0_4

PC195
*.1U/10V_4

PC194
.1U/10V_4

PU4
G938

1

VCC

6

DRV

2

GND

3

PGD

5

ADJ

4

EN

PQ66

AO6402

6
5
2
1

PC201
10U/10V_8

PR240

150/F_4

PR368
100/F_4

Vout1=(1+R1/R2)*0.5

4

PC356

PC357

10U/10V_8

3

PR369

47_4

10U/10V_8

PC355

33N_6

Max Current ? A

+1.25V

PC358
.1U/10V_4

+1.25V(10,15,40)

HWPG_1.25VM(31)

+1.5VM

PC199
10U/10V_8

+3VM

5VPCU

PR380
100K_4

PR201
0_4

.1U/10V_4

PC193
*.1U/10V_4

PR222

IAMT_ON(31,37,40)

0_4

PC192

PU14
G938

1

VCC

6

DRV

2

GND

3

PGD

5

ADJ

4

EN

PR367
100/F_4

PQ65

AO6402

6
524

1

PC198
10U/10V_8

3

PR189

150/F_4

Vout1=(1+R1/R2)*0.5

PR366

47_4

PC359
10U/10V_8

PC354

33N_6

PC360
10U/10V_8

Max Current ? A

+1.25VM

PC361
.1U/10V_4

+1.25VM(7,10,40)

PROJECT : OT2

SizeDocument NumberRev

5

4

3

2

Date:Sheet of

Quanta Computer Inc.

+-1.5V &VCCP+1.05V(MAX8743)

1

3642Thursday, March 22, 2007

1AC

5

DD

VIN

PL5

HI0805R800R-00/5A

9A

12

PC71
10U/25V/1206

12

PC91
10U/25V/1206

S0-S3

1.8VSUS

1.8VSUS(7,9,10,16,32)

PC98
220U/2V_ESR15

12

PC182
.1U/50V_6

CC

+

PC96
220U/2V_ESR15

+

Ra

Fix 1.8V Output

51116_V5FILT

PR232

*0_4

PC176
*100P_4

PR233
143K/F_4

Rb

PR235
100K/F_4

4

51116_VIN

12

PC94

PL14

.1U/50V_6

PC92
2200P_4

PR106
*2.2_6

PC97
*1000P_4

578

PQ61
SI4392DY

3 6

241

578

PQ63
SI4856ADY

3 6

241

PC95
10U/25V/1206

1.0UH/11A (DCR-9)

1 2

Ra=Vout-0.75/0.75*Rb
Rb value from 100K to 300K ohm

VBST_1

PC177
.1U/50V_6

1 2

51116_VDDQSET

4.7U/10V_8

51116_DRVH

51116_LX51116_LX51116_LX51116_LX

51116_DRVL

PR108

0_4

PC175

PR107
0_6

VBST

COMP51116_V5FILT

5VPCU

3

PR100

10_6

15

V5IN

TPS51116

VTTREF

GND

5

3

SMDDR_VREF

PGOOD

VLDOIN

VTTGND

MODE

VTTSNS

PAD

PAD

272829

51116_V5FILT

14

CS

V5FILT

S5
S3

NC
NC

VTT

PAD
PAD

PAD

PC180

0.033U/25V_6

1 2

PC93
1U/10V_6

16

13

51116_S5

11
10
23
12

7
1

4

24
2
25

26

PR231

6.98K/F_6

51116_CS

51116_PGOOD51116_PGOOD51116_PGOOD51116_PGOOD51116_PGOOD51116_PGOOD51116_PGOOD51116_PGOOD51116_PGOOD51116_PGOOD51116_PGOOD51116_PGOOD51116_PGOOD51116_PGOOD51116_PGOOD51116_PGOOD51116_PGOOD51116_PGOOD51116_PGOOD51116_PGOOD51116_PGOOD51116_PGOOD51116_PGOOD51116_PGOOD51116_PGOOD51116_PGOOD51116_PGOOD51116_PGOOD51116_PGOOD51116_PGOOD51116_PGOOD51116_PGOOD51116_PGOOD51116_PGOOD51116_PGOOD51116_PGOOD51116_PGOOD51116_PGOOD51116_PGOOD51116_PGOOD

PR3720_4
PR102*0_4

51116_S3

1.8VSUS

PC190

1 2

*4.7U/10V_8

51116_VTTSNS51116_VTTSNS51116_VTTSNS

SMDDR_VREF(7,16)

PR1010_4

PR104*0_4

PR3850_4
PR386*0_4

PC178
10U/10V_8

PR239
0_4

S0-S3

SMDDR_VREF

0.9V/10mA

12

PU13

22

VBST

21

DRVH

20

LL

19

DRVL

18

PGND

17

CS_GND

8

VDDQSNS

9

VDDQSET

6

COMP

PR238
0_4

PR375*0_4

PC181
10U/10V_8

2

HWPG_1.8VSUS(31)

SLP_S4#(14)
SUSON(31,40)

MAINON(22,25,31,34,36,38,39,40)
IAMT_ON(31,36,40)
SLP_S4#(14)

SMDDR_VTERM

S0-S3

SMDDR_VTERM

0.9V/1.5A

SMDDR_VTERM(16,31,40)

1

BB

V_TRIP(mV)=R_TRIP(Kohm)*10(uA)
I_OCP=V_trip/Rds_on+I_Ripple/2

VDDQSET VDDQ(V) VTTREF and Vtt Note
GND 2.5 V_ vddqsns/2 DDR
V5IN 1.8 V _vddqsns/2 DDR2

Mode Discharge Mode
V5IN No discharge
VDDQ Tracking discharge
Gnd Non-tracking discharge

FB Adjustable V_VDDQSNS/2 1.5V<VDDQ<3V

AA

PROJECT : OT2

SizeDocument NumberRev

5

4

3

2

Date:Sheet of

Quanta Computer Inc.

ti51116(1.8VSUS/DDR_VTERM)

1

3742Thursday, March 22, 2007

1AC

1

AA

BB

3VSUS

DFGT_VID_0(7)
DFGT_VID_1(7)
DFGT_VID_2(7)

+3V

PR383
30K_4

DFGT_VR_EN(7)

PR384
100K_4

CC

DFGT_VID_3(7)

DEL PR63 0-ohm

EC SI1

INT_VGA_PWRGD(31)

PR376
22K_4

PR378

22K_4

VRON(31,39)

MAINON(22,25,31,34,36,37,39,40)

5VPCU

EC 09.12 For power on sequence

EC SI1

PR382
22K_4

PR377

22K_4

2

5VPCU

PR71

PC70

10_6

10U/10V_8

8776VCC

12

PC67

2.2U/10V_6

3VSUS

PR370
100K_4

PR371
0_4

8776PG

PR75
22K_4

PR720_4
PR690_4

PR670_4

PR66

0_4

PR78
*0_4 PC66
PR60
*0_4

PR70
13K/F_4

*NTC 10K_6-B4.25K

3VSUS

PR52

100K_4

PR51

PC59

1 2

1000P_4

PC60

1U/10V_6

12

PR50

71.5K/F_4

8776REF

PR87
10K_4

8776VCC

25
26
27
28
29

32
31
30

15

PR53
10K_4

12

PC62

0.1U/10V_4

16

PU3

VCC

1

PWRGD

D0
D1
D2
D3
D4

SKIP
SHDN
STDBY

2

OFS

8

CCV

6

TIME

9

REF
GND

5

THRM

4

VRHOT

3

POUT

MAX8776

VIN

PR54

200K/F_4

19

7

TON

VDD

8776BST

24

BST

8776LX

22

LX

8776DH

23

DH

8776DL

20

DL

21

PGND

8776CSP

14

CSP

8776CSN

13

CSN

10

FB

11

GNDS

12

IC1

17

N.C.

18

IC2

PR58
0_6

PR56

*3.48K/F_4

1 2

PR59

8.45K/F_4

8776VCC

21

8776BST_R

PR74
0_6

3

PD4
*CH501H-40

12

12

PC69
.22U/10V_6

DEL PC68 100P

PC61
*4700P_4

PR55

30.1_4
PC63
1000P_4

12

PC64
1000P_4

PR61

1K_4

+VCCGFX

PR62

30.1_4

578

3 6

578

3 6

PR64
10_4

4

12

12

PC166
.1U/50V_6

PQ54
SI4392DY

241

PR219
*22_8

PQ55

1 2

SI4856ADY

PC161
*1500P_4

241

1 2

PC167
2200P_4

PR73
10K/F_6

1K/F_4

12

PC170
.1U/50V_6

PL11

1.0UH/11A (DCR-9)

1 2

PR68

NTC 10K_6-B4.25K

.068U/10V_6

PR88
1K/F_6

PR65

12

12

PC172
2200P_4

12

PC79
10U/25V/1206

12

PC73
330UF/2V_ESR9

VIN

12

12

PC72
10U/25V/1206

PC65
.01U/16V_6

5

7.7A

S0-S3

+VCCGFX

DD

PROJECT : OT2

SizeDocument NumberRev

1

2

3

4

Date:Sheet of

Quanta Computer Inc.

GMCH (MAX8776)

5

3842Thursday, March 22, 2007

1AC

A

B

C

D

E

F

G

H

DPRSLPVR DPRSTP#

1

12

PC20
10U/25V/1206

PR157
*10_4

1
0
0

12

PC15
330U/2V/ESR6

PR154
*10_4

1 X

0 1

12

PC14
330U/2V/ESR6

RVPS = RDROOP / (RSENSE x GM) = 5.1mV/A / (0.001 x 200uS) =25.5K
RTRC = RSENSE x 5k / ( RDROOP(AC) x # of Phases ) = 0.001 x 5k / ((5.1mV/A x 80%) x 1phases) =1.24K
RILIMPK = Battery V x RTRC / (IPK x RSENSE) = 8V x 1.24K / ( Ioutput peak x 0.001) OCP=17.7A

11

22

33

fsw=300kHZ*143kohm/Rosc
dV_Target/dt=12.5mV/us*71.5kohm/R_TIME

fsw=300KHZ*143Kohm/Rosc
fsw= 300KHz

PR26

71.5K/F_4

EC:SI2

PC30

1 2

.22U/10V_6

EC:SI2

H_VID0(5)
H_VID1(5)
H_VID2(5)
H_VID3(5)
H_VID4(5)
H_VID5(5)
H_VID6(5)

VRON(31,38)
MAINON(22,25,31,34,36,37,38,40)

PWROK(26,31)

PM_DPRSLPVR(7,14)

DELAY_VR_PWRGOOD(7,14,31)

VR_PWRGD_CLKEN#(14)

+1.05V

H_PROCHOT#(4)

8736VCC

VR_HOT#-Active Low when THRM Voltage
level below 1.5V

PR60_4
PR50_4
PR40_4
PR30_4
PR20_4
PR10_4
PR70_4

PR136499/F_6

PSI#(4)

+3V

+3V

PR151

56_4

PR149

13K/F_4

PR142

NTC 100K_6-B4.25K

EC:DB2

PR25
143K/F_4

PC32

1 2

2200P_4

PR23

825K/F_6

PR24

1.78K/F_6

PR146*0_4
PR140*0_4
PR3740_4

PR11*100K_4

PR90_4

PR152

1.91K/F_4
PR1500_4

PR148

1.91K/F_4

PC27

1 2

*100P_4

12

PC28
100P_4

PC33

1U/10V_6

8736OSC

8736TIME

8736CCV

8736ILIM

8736REF

8736TRC

8736SHDN#

PR8

PR16

0_4

PR147
*0_4

0_4

PR138

10_6

21

1 2

VCC

14 25

OSCBST1

15

TIME

17

CCV

16

ILIM

19

REF

18

TRC

34

D0

35

D1

36

D2

37

D3

38

D4

39
40

4

33

3

2

24

1 11

PGND

D5
D6

SHDN

DRSKP

PWM2

DPRSLPVR

PSI

PWM3

IMVPOK

CLKEN GNDS

MAX8736AGTL

22

VR_HOT

23

THRM

PU1

41

GND

42

GND

43

GND

GND

GND

GND

444546

GND

47

<Pin Numbers Visible>

CSP1

CSN1

CSP2

CSN2

CSP3

CSN3

VINVIN_8736_15VPCU8736VCC

PL1

12

12

2.2_6

PR14

8736VCC

8736VCC

8736GNDS

12

PR15

17.4K/F_4

12

PC31
4700P_4

EC:DB2

PC40
4700P_4

EC:DB2

21

CH501H-40

8736BST18736BST18736BST18736BST18736BST18736BST1

12

PC13
.22U/10V_6

<Voltage>

PD11

12

EC:SI2

PC22
4700P_4

PQ36
SI7336

PC5
10U/10V_8

30

1 2

VDD

8736BST

EC 0110

8736DH1

27

DH1

8736LX1

26

LX1

8736DL18736DL18736DL18736DL18736DL18736DL18736DL18736DL18736DL18736DL18736DL18736DL18736DL18736DL18736DL18736DL18736DL18736DL18736DL18736DL18736DL18736DL18736DL18736DL18736DL18736DL18736DL18736DL18736DL18736DL18736DL18736DL18736DL18736DL18736DL18736DL1

32

DL1

31

8736CSP18736CSP18736CSP18736CSP1

6

8736CSN1

5

28

8

EC:DB2

7

EC:DB2

29

10

9

20

GND

13

VPS

12

FBS

49

GND

50

GND

48

GND

VSSSENSE(5)

VCCSENSE(5)

52

4

3

1

52

4

3

1

EC:DB2

PR20

100_6

EC:DB2

PR21

100_6

PR1560_4

PR1530_4

PQ34
SI7392

12

PC37
*10U/25V_12

PR126

2.2_6

PC103
2200P_4

EC 0110

PC36

PC35

10U/25V/1206

10U/25V/1206

PC38

PC39

2200P_4

.1U/50V_6

PL8

0.36UH/25A

PR129

1.21K/F_6
PR230

NTC 10K_6-B4.25K

2.49K/F_6

EC DB2

PC11

.22U/10V_6

Intel Recommendation Option 1 :
250KHZ<= Fs <= 300K HZ

0.351uH<= Lo <=0.500uH +-20%
Low-Freq. Decoupling : ESR 1.5m Ohms ; ESL 1.8nH/6
SPCAP EEFSX0D331R * 6 or
POSCAP 2R5TPE330M9 * 6
Mid-Freq. Decoupling : 3m Ohms/32
MLCC 22uF_0805_X5R * 32 PCS.

VSSSENSE_1

VCCSENSE_1VCCSENSE_1

HI0805R800R-00/5A L-F

12

PR119

PC112
.1U/50V_6

12

PC17
330U/2V/ESR6

Parallel

44

PSI#
0
0
1
1

0
1
0
1

DPRSLPVR PSI#

1-phase pulse-skipping mode(low power)

1-phase forced-PWM mode(inteermediate power)0 0

All phase active,forced-PWM mode(full powr)

12

PC18
*30U/2V/ESR6

Vo VID6 VID5 VID4 VID3 VID2 VID1 VID0

----------------------------------------------

1.5000 0 0 0 0 0 0 0

----------------------------------------------

1.4375 0 0 0 0 1 0 1

----------------------------------------------

1.4000 0 0 0 1 0 0 0

----------------------------------------------

1.3000 0 0 1 0 0 0 0

----------------------------------------------

1.2875 0 0 1 0 0 0 1

----------------------------------------------

1.2000 0 0 1 1 0 0 0

----------------------------------------------

1.1500 0 0 1 1 1 0 0

----------------------------------------------

1.1000 0 1 0 0 0 0 0

----------------------------------------------

1.0000 0 1 0 1 0 0 0

----------------------------------------------

0.9625 0 1 0 1 0 1 1

----------------------------------------------

0.9000 0 1 1 0 0 0 0

----------------------------------------------

0.8375 0 1 1 0 1 0 1

----------------------------------------------

0.8000 0 1 1 1 0 0 0

----------------------------------------------

0.7625 0 1 1 1 0 1 1

----------------------------------------------

0.7500 0 1 1 1 1 0 0

----------------------------------------------

0.7000 1 0 0 0 0 0 0

----------------------------------------------

0.6000 1 0 0 1 0 0 0

----------------------------------------------

0.5000 1 0 1 0 0 0 0

----------------------------------------------

0.3000 1 1 0 0 0 0 0

----------------------------------------------

StateCPU Current
Deeper Sleep
Deeper Sleep
Active Mode
Active Mode

VCC_CORE

12

PC16

330U/2V/ESR6

VCC_CORE(5)

< 3A
> 3A
< 18A
> 15A

PROJECT : OT2

SizeDocument NumberRev

A

B

C

D

E

F

Date:Sheet of

G

Quanta Computer Inc.

MAX8736

3942Thursday, March 22, 2007

H

1AC

5

4

3

2

1

PR121
1M/F_4

3

2N7002E-T1-E3

1

VIN

PR391
1M_4

PR392
1M_4

PR84
22_8

3

PQ15
2N7002E-T1-E3

1

12VAL

PR122
1M/F_4

3

2

1

2

2

12

PC104
*2200P_6

PQ33
2N7002E-T1-E3

3

PQ70

2N7002EPT

1

12VAL

PR86
1M_6

3

PQ16
2N7002E-T1-E3

1

IAMT_OND_WOL(35)

12VAL

PR388
1M_6

PC78
2200P_4

PC367
2200P_4

S5_OND(35)

S4_STATE_PWR(35)

+3VM

PR155
1M/F_4 PQ32

2

PR159
1M/F_4

PQ60
DTC144EUA

1 3

2

PQ71

1 3

PV stager:add for HP request

3V_S5

VIN

PR85
1M_6

2

PR89
1M_6

S5_ON_G

PR92
22_8

PQ18
2N7002E-T1-E3

PR117
22_8

PQ30
2N7002E-T1-E3

12VAL

12VAL(35)

PR96
1M/F_4

2

12

PC88
*2200P_6

12VAL

PC116
2200P_4

IAMT_OND(35)

PR111
1M_6

3

PQ23
2N7002E-T1-E3

1

SUSD(35)

PC102
2200P_4

MAIND(35,36)

S4_STATE_PWRS4_STATE_PWR

S5_ON(31)

2

PQ37

DTC144EUA

LAN_WOL_EN(14)

IAMT_ON(31,36,37)

3VPCU

3

PC368

.1U/10V_4

1 2

2

1

PQ72

AO3403

500mA

3V_FP

12

PC369
.1U/10V_4

3

2

PQ19
2N7002E-T1-E3

1

+1.25V

PR76
22_8

3

PQ12
2N7002E-T1-E3

2

1

12VAL

PR169
1M_6

3

2

PQ43
2N7002E-T1-E3

1

VIN

1 3

2

S4_STATE(14)

DTC144EUA

PV stager:add for HP request

2

PQ14

1 3

DTC144EUA

VIN

DD

2

PQ27

DTC144EUA

SUSON(31,37)

2

PQ20

DTC144EUA

1 3

PQ47

DTC144EUA

2

IAMT_ON(31,36,37)

CC

MAINON(22,25,31,34,36,37,38,39)

BB

AA

PR99
1M/F_4

PR103
1M/F_4

1 3

SMDDR_VTERM

VIN

PR133
1M_6

2

PR139
1M_6

VIN

1 3

3

1

MAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_GMAINON_G

PR173
1M_6

PR171
1M_6

PR77
22_8

+1.25VM +1.05VM

PR91
22_8

3

PQ17
2N7002E-T1-E3

2

1

+3V +5V

3

PQ11
2N7002E-T1-E3

2

1

3VSUS

PR176
22_8

3

2

1

SUSON_GSUSON_G

2

PR114
22_8

PQ22
2N7002E-T1-E3

PQ45
2N7002E-T1-E3

DEL PR174, PQ46
For S4-STATE

3

1

3

2

1

PROJECT : OT2

SizeDocument NumberRev

5

4

3

2

Date:Sheet of

Quanta Computer Inc.

DISCHARGE

1

4042Thursday, March 22, 2007

1AC

5

MODEL

DB2 --->SI

OT2 MB

31OT2MBXXXX

DD

Date

2006.11

change from 5VSUS to +5v due to not support wake up from
suspend

change footprint to 0805 to easy prepare materialchange U2, C577 footprint

4

CHANGE LIST

Reason for change

3

2

1

Pagemodify list

change U35 pin13,15 to +5V

change power plan from 3VSUS to 3V_S5 at RP31 , R241 , R448 ,

avoild leakage cruuent

R538,change card bus switch poewr from 5VSUS to 5V

R452 Install, R46 on instal;delete R496,Add D32

Add D33,D34;delete R293 ,and add Q60

EC VCC2 pin is used in a comparator to sample when Vcc2 is going up
or down. It will draw some current. Approx 300ua

For auto boot issue

reserve R1029,add R1028 ,Q62 for auto power issue

R1005 install,R297 no install

remove Kill switch function

add for EA team easy test

CC

modify footprint firm right angle tyoe to straight type

change footprint for another vender for easy insertchange footprint for track point connector CN8

move D31 close to ICH8 to solve battery LED issue ,else it will cause LED function abnormally

add strapping options for CPU_BSEL{0:2} so we can hardwire the clock to the FSB frequency if neededR1036-R1044
PU13.11, add IAMT_ON control signal option with 0-Ohm NO INSTALL to control power up of 0.9V

This is to save system power in S3 when iAMT is disabled.

For ENERGY_DET, Change R18 to 1.4K, this is a change from Intel on LAN Energy Detect.

DB2 --->SI2

BB

AA

Date

2007.1

for internal mic issue

due to use 4MB flash partdelete CN24

schematic error and change to avoid leakage voltage

to avoid the ripple for signal CLK_PWRGD

tune Adp_Id signal for layout. to avoid overlayfor EMI suggestion

for EMI suggestionreseve C661,C662,C663

for EMI suggestion(modem)

add C643, and modify pin 1 for U47 OP circuit
and add C657

D31 close to ICH8 and pull up 10k(R1035)
to +3V

reserve L53, L54,add R1033,R1034WWAN noise --- ICH improvement

RP31 pin10 from 3V_S5 to 3VSUS

Lan crystal layoutchange Lan crystal layout for intel suggestion

add R1049 for intel suggestion

L8,L10,L14 change to BK1608LL680for EMI suggestion(CRT)

reserve R664, R1050 for Micfor EMI suggestion(internal Mic)

delete R280,R281 due to useless

delete Q61,add R1051;deleteD32,Add R1052Q61,D32 is for leakage voltage issue ,but will influence LAN function ,change to 0 ohm

remove Q37,R443,R426,CN1,R977

add R1031,R1032

CN36

add PR385

R18

C5 no installPWM signal(LCD)to avoid work abnormally

change R18 to 1.87kchange to 1.87K for Intel suggestion

PROJECT : OT2

SizeDocument NumberRev

5

4

3

2

Date:Sheet of

Quanta Computer Inc.

change list-1

1

4142Thursday, March 22, 2007

1ACustom

5

4

3

2

1

MODEL

DB2 --->SI2

OT2 MB

31OT2MBXXXX

DD

Date

2007.1

Reason for change

CHANGE LIST

modify listPage

change R30 to 82K,C32 to 0.1u ,and change R20 power source to 3VPCUFor LCD rush current issue

delete R341,R1025,L9,L13,L15,L8,L10,L14,R342,R95,R81due to no use

SI2--->PV

2007.1

CC

BB

AA

PROJECT : OT2

SizeDocument NumberRev

5

4

3

2

Date:Sheet of

Quanta Computer Inc.

change list-2

1

4242Thursday, March 22, 2007

1ACustom