Quanta JW8B, JW8C, Vostro 5460 Schematic
1
2
3
4
5
6
7
8
JW8B/C BLOCK DIAGRAM
A A
DDR3L SO-DIMM
1333 /1600 MT/S
Haswell ULT
PCIE X4
GPU
N14P-GV2 (25W)
DDR3L (2G )
USB3.0 Port
(Right)
USB3.0 Port *2
(Left)
Fingerprint
B B
Touch Panel
Camera
DSP:eS305
I2S
HP+MIC
Combo Jack x1
Subwoofer Conn
Speaker Conn
C C
AMP
APA2010
Digital Mic
Audio Codec
ALC290Q
Touch PAD
PS/2
Keyboard CONN
KBC
ITE 8528
USB2.0 / USB3.0
USB2.0 / USB3.0
USB2.0
USB2.0
USB2.0
HDA
I2C or SMBus
LPC
HSPI
15W
DC+GT2 / GT3
28W
DC+GT3
Lynx Point LP
MCP 1168pins
iPTT
40 mm X 24 mm
SPI
SPI ROM
64Mbit
24MHz
32.768KHz
DDI
eDP(x2 lanes) eDP to LVDS
SATA
SATA
Redriver
PS8401A
PS8620/8623
HDD Conn
mSATA Conn
USB2.0
PCIE
PCIE
PCIE
Bluetooth
WiFi
*Support AOAC
Card Reader
RTS5227E
GIGA LAN
RTL8111GUS
*Support S5 wake
HDMI CONN
LVDS Panel
3in1 Conn
RJ45
D D
1
2
PWM FAN
SPI ROM
64Mbit
3
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Friday, May 10, 2013
Date: Sheet of
Friday, May 10, 2013
Date: Sheet of
4
5
6
Friday, May 10, 2013
7
PROJECT :
Block Diagram
Block Diagram
Block Diagram
JW8B
JW8B
JW8B
1 57
1 57
1 57
A
A
A
8
1
2
3
4
5
6
7
8
USB3.0HSIO Port
1
A A
2
3
4
USB3.0_1
CN6
USB3.0_2
CN4
USB3.0_3
CN5
USB3.0_4
X
5
6
7
B B
8
9
PCIE SATA
PCIE1
X
PCIE2
Card Reader
PCIE3
GIGA LAN
PCIE4
WIFI
PCIE5
GPU 4X
PCIE5
GPU 4X
PCIE5
PCIE CLK
CLK0
X
CLK1
Card Reader
CLK2
GIGA LAN
CLK3
WIFI
CLK4
GPU 4X
CLK5
X
USB2.0
USB2.0_0
CN4
USB2.0_1
CN6
USB2.0_2
CN5
USB2.0_3
Finger Print
USB2.0_4
Camera
USB2.0_5
eTP
USB2.0_6
Blue Tooth
USB2.0_7
Touch Screen
GPU 4X
10
PCIE5
GPU 4X
11
PCIE6
X
12
PCIE6
X
13
PCIE6
X
C C
14
PCIE6
X
SATA3
X
SATA2
mSATA
SATA1
HDD
SATA0
X
D D
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Wednesday, June 19, 2013 2 57
Date: Sheet of
Wednesday, June 19, 2013 2 57
Date: Sheet of
1
2
3
4
5
6
Wednesday, June 19, 2013 2 57
7
PROJECT :
PORT ASSIGNMENT
PORT ASSIGNMENT
PORT ASSIGNMENT
JW8B
A
A
A
8
1
2
3
4
5
6
7
8
+3.3V_SUS
MB
2.2K2.2K
SMBCLK
AP2
SMBDATA
A A
AH1
+3.3V_RUN
DMN66D0LDW
DMN66D0LDW
SMB_PCH_SCLK
SMB_PCH_DAT
+3.3V_RUN
Touchpad
2.2K2.2K
SODIMM
+3.3V_SUS
Haswell
ULT
SMB_CLK0
AN1
SMB_DAT0
AK1
+3.3V_SUS
B B
AU3
SMB_CLK_ME1
AH3
SMB_DATA_ME1
+3.3V_ALW
2.2K2.2K
2.2K2.2K
Function
Thermal IC
Thermal IC G781-1P8 1001101xb (9Ah)
SMBUS
Charge IC
Battery
GPU N14P-GV2
NCT7718 1001100xb (98h)
Battery 00010110 (0X16h)
AddressIC
00010010 (0x12h)OZ8618NL
10011110 (0X9Eh)
2.2K2.2K
MB
115
116
SMBDAT1
SMBCLK1
+3.3V_ALW
C C
SIO
ITE8528E
110
SMBCLK0
111 SMBDAT0
4.7K4.7K
+3.3V_RUN
2.2K2.2K
94
SMBCLK3
95
SMBDAT3
+3.3V_SUS
DMN66D0LDW
DMN66D0LDW
330
330
0
0
V3.3_THERMAL2
V3.3_THERMAL
MOS
MOS
MOS
5
6
10
11
Battery
Charger
8
THERMAL(G781-1P8)
7
8
THERMAL(NCT7718)
7
GPU
MOS
D D
N-MOS
D9
GPU
D8
N-MOS
20
eDP to LVDS
21
PS8623
1
2
3
4
5
6
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Monday, July 08, 2013
Date: Sheet of
Monday, July 08, 2013
Date: Sheet of
Monday, July 08, 2013
7
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
SMBUS
SMBUS
SMBUS
JW8B
JW8B
JW8B
3 57
3 57
3 57
8
A
A
A
5
4
3
2
1
Adapter 65W
Charger
(BQ24715RGRR)
D D
Battery 3S1P
+3.3V_EN2 ALW_ON
C C
SUS_ON
B B
+PWR_SRC
TI
TPS51275RUKR
+3.3V_ALW
Load Switch
TPS22966DPUR
RUN_ON
+5V_ALW
+10V_ALW
SUS_ON
Load Switch
TPS22966DPUR
SLP_S4#
TI
TPS51362RVER
+V_VDDQ_VR
RUN_ON
TI
TPS51206DSQR
+0.6V_DDR_VTT
RUN_ON
RichTek
RT8068AZQW
+1.5V_RUN
DDR_PG_CTRL
MODPHY_EN
SLP_S4#
TI
TPS51362RVER
+1.05V_SUS
Load Switch
TPS22966DPUR
+1.05V_RUN+V1.05DX_MODPHY
RUN_ON
TI
TLV62130RGTR
+1.8V_SUS
Load Switch
TPS22965DSGR
+1.8V_RUN
VER : 1A
SLP_S4#
RUN_ON
IMVP_VR_ON
ON
NCP81101MNTWG
+VCCIN
+3.3V_SUS
A A
5
+3.3V_RUN
+5V_RUN+5V_SUS
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Friday, May 10, 2013 4 57
Date: Sheet of
Friday, May 10, 2013 4 57
Date: Sheet of
4
3
2
Friday, May 10, 2013 4 57
PROJECT :
Power Block Diagram
Power Block Diagram
Power Block Diagram
JW8B
JW8B
JW8B
1
A
A
A
5
Battery Mode
+VAD +12V_ALW
+5V_ALW
D D
+PWR_SRC
SUS MOS
SW ( IC )
2
G
10
1.05V
VR
EN
+PWR_SRC
C C
DDR/VTT
VR
S3
S4
RC Delay
+VAD
B B
+5V_ALW
+3.3V_ALW
+1.05V_SUS
+V_VDDQ
A A
RUN MOS
SW ( IC )
G
+5V_ALW
1.5V
VR
EN
5
+1.05V_SUS
1.05V_PWRGD
PG
+3.3V_SUS
+V_VDDQ
+DDR_VTTREF
+DDR_VTT
DDR_PWRGD
PG
RUN_ON
PG
11
9
SIO_SLP_S3#
SIO_SLP_S4#
+5V_RUN
+3.3V_RUN
+1.35V_RUN
+1.05V_RUN
23
+1.5V_RUN
1.5V_RUN_PWRGD
RUN_ON
17
16
19
20
21
22
28
1.5V_RUN_PWRGD
24
25
26
27
25
28
23
4
9
+3.3V_SUS
SVID
35
+V_VDDQ
+1.05V_RUN
4
SUS_ON
+PWR_SRC
IMVP
VR
LATCH
(POWER_SW_IN0#)
8
29
3
HWPG
+VCCIN
IMVP_PWRGD
PG
EN
H_VR_ENABLE_MCP
CPU
GFX PWR
MOS
SYS_PWROK
23
36
32
+3V_GFX+3.3V_ALW
+1.35V_GFX
+1.05V_GFX
3
BTN
6
SYS_PWR_SW#
(S5 start point.
(Only available when S5 -> S0)
EC
EC_PWROK
RUN_ON
VCCST_PWRGD#
30 30
33
31
G2
DGPU_PWR_EN
G4
G4
DGPU_VC_EN
3
SIO_SLP_S3#
G1
G3
SIO_SLP_S5#
SIO_SLP_S4#
151617
2
2
+3.3V_RTC_LDO
+PWR_SRC
3V/5VPWR
+3.3V_ALW
+5V_ALW
VR
EN2
3.3V_ALW_ON
4
6
ALW_ON
12
RSMRST#
13
AC_PRESENT
SIO_PWRBTN#
14 15
+PWR_SRC
+VGACORE
IMVP
EN1
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_S3#
30
EC_PWROK
30
VCCST_PWRGD#
37
PLTRST#
SYS_PWROK
36
EC_PWROK to SYS_PWROK delay 5-99mS
31
H_VR_ENABLE_MCP
33
IMVP_PWRGD
G1
DGPU_PWR_EN
G2
VR
DGPU
DGPU_VC_EN
PG
EN
DGPU_PWR_EN
2
G3
G1
1
1
+VCHGR+PWR_SRC
5
7
16
17
CHARGER
DPWROK
ACPRESENT
PWRBTN#
SLP_S5#
SLP_S4#
SLP_S3#
APWROK
PCH_PWROK
VCCST_PWRGD
PLTRST#
SYS_PWROK
Battery
Haswell ULT
35 34
SVID
VR_EN
VR_READY
GPIO54
All_DGPU_PWR DGPU_PWROK
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Friday, May 10, 2013 5 57
Date: Sheet of
Friday, May 10, 2013 5 57
Date: Sheet of
Friday, May 10, 2013 5 57
PROJECT :
POWER SEQUENCE
POWER SEQUENCE
POWER SEQUENCE
MCP
CPUPWRGOOD
G5
DGPU_HOLD_RST#
JW8B
1
GPIO17
GPIO50
G6
A
A
A
5
Power Sequence
4
3
Shark Bay ULT PSS, 490828, Rev1.1
2
1
(G3 to S0)
+PWR_SRC
+5V_ALW2 and +3.3V_RTC_LDO
POWER_ SW_IN0#
D D
LATCH
3.3V_ALW_ON
+3.3V_ALW
(EC on)
ALW_ON(EC)
+5V_ALW
+10V_ALW
SYS_PWR_SW#
SUS_ON(EC)
+3.3V_SUS
(PCH MCU on)(VCCDSW)
+5V_SUS
RSMRST#(EC)
(DPWROK, suspend power well)
SUSACK#(PCH IPU)
C C
SIO_PWRBTN#(EC)
SIO_SLP_S5#(PCH)
SIO_SLP_S4#(PCH)
+1.05V_SUS
+V_VDDQ_VR
(VDDQ)
+1.8V_SUS
(VDD1)
1.05V_PWRGD
1.2V_SUS_PWRGD
SIO_SLP_S3#(PCH)
+0.6V_DDR_VTT
RUN_ON(EC)
+1.05V_RUN
(VccCorePCH, VCCST, VCCASW)
B B
VCCST_PWRGD(EC)
+1.5V_RUN
1.5V_RUN_PWRGD
+3.3V_RUN
+5V_RUN
SIO_EXT_SCI#
SIO_EXT_SMI#
HWPG
(APWROK, ALL_SYS_PWRGD)
IMVP_VR_ON(EC)
(VR_EN)
CPU SVID BUS(CPU)
A A
+VCCIN
(VCCIN- CPU CORE)
IMVP_PWRGD
(VR_READY)
EC_PWROK(EC)
(PCH_PWROK(PWROK))
SYS_PWROK
PLTRST#(PCH)
5
G3 mode: > EC reset time + output ALW_ON
S5 mode: > Power button DE-BOUNCE time
G3 mode: Asserted by HW latch of power button event
S0 mode: Be keeped on high by ALW_ON
? ms (3.3_ALW_ON to +3.3V_ALW)
? ms (EC, EC reset time about 50.4ms, 1650 Tick*(1/32.768K))
? ms (ALW_ON to +5V_ALW)
? ms (ALW_ON to +10V_ALW)
G3 mode: EC don't care this event.
S5 mode: Upon power always exist, and this pin keeped on high. Start from this event.
500us
? ms (EC, ALW_ON to SUS_ON, EC)
? ms (SUS_ON to +3.3_SUS)
? ms (SUS_ON to +5V_SUS)
? ms (+3.3V_SUS to RSMRST#, t05=min 10ms)
(VCCDSW (+3.3V_SUS) to DPWROK (RSMRST#), t04=min 10ms)
For a non-DeepSx system SUS_ACK# will rise with +3.3V_SUS due to weak internal pull-up
? ms(EC, RSMRST# (DPWROK) to SIO_PWRBTN#)
minimum duration of PWRBTN# assertion=16ms. PWRBTN# can assert before or after than RSMRST#
? ms (RSMRST# to SLP_S5, t07=min 5ms)
? us (SIO_SLP_S5# to SIO_SLP_S4#, t09=min 30us)
? us (SIO_SLP_S4# to SIO_SLP_S3#, t10=min 30us)
4
(For a non-DeepSx system, DPWROK and RSMRST# go high at the same time)
Be keeped on low by tied to 1.5V_RUN_PWRGD during this OD period.
? ms (EC, SLP_S3# to RUN_ON)
? ms (VccSUS (+3.3_SUS) to VccASW (+1.05V_PCH), t29= min 0ms)
? ms (VCCSUS to VccCorePCH (+1.05V_SUS), t31=min 0ms)
? ms (VDDQ (+V_VDDQ_VR) to VCCST_PWRGD, tCPU01=min 1ms)
? ms(VCCST (+1.05V_RUN) to VCCST_PWRGD, tCPU00=min 1ms)
? ms (EC, RUN_ON to VCCST_PWRGD)
? ms (VCCASW (+1.05V_RUN) to APWROK (HW PG), t11=min 1ms)
? ms (VCCST_PWRGD to VR_EN (IMVP_VR_EN), tCPU05=max 100ns)
? ms (EC, HWPG to IMVP_VR_ON)
? ms(VDDQ (+V_VDDQ_VR) ramping&stable to VCCIN ramping, tCPU03=min 100ns)
? ms(VCCST (+1.05V_RUN) ramping&stable to VCCIN ramping, tCPU04=min 100ns)
valid
? ms(VR_EN (IMVP_VR_EN) asserted until VCCIN ramped to Vboot, tCPU07=max 2.5ms)
? ms(VccCorePCH (+1.05V_RUN) stable to PWROK (EC_PWROK), t41= min 5ms)
? ms(ALL_SYS_PWRGD (HWPG) to PWROK (EC_PWROK), t14= min 5ms)
? ms(APWROK (HWPG) to PWROK (EC_PWROK), t30= min 0ms)
? ms (EC, IMVP_VR_ON to EC_PWROK)
? ms(ALL_SYS_PWRGD (HWPG) to SYSPWROK, t15= min 99ms)
? ms(ALL_SYS_PWRGD (HWPG) to PLTRST#, tULT14=max 99ms)
S0G3
3
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Friday, May 10, 2013 6 57
Date: Sheet of
Friday, May 10, 2013 6 57
Date: Sheet of
2
Friday, May 10, 2013 6 57
PROJECT :
G3 to S0
G3 to S0
G3 to S0
JW8B
1
A
A
A
5
4
3
2
1
Haswell ULT (DISPLAY)
+VCCIOA_OUT
U14A
D D
C54
DDI1_TXN0
C55
DDI1_TXP0
B58
DDI1_TXN1
C58
DDI1_TXP1
B55
DDI1_TXN2
A55
DDI1_TXP2
A57
DDI1_TXN3
B57
DDI1_TXP3
[27]
[27]
[27]
[27]
[27]
[27]
[27]
[27]
INT_HDMI_TXN2
INT_HDMI_TXP2
INT_HDMI_TXN1
INT_HDMI_TXP1
INT_HDMI_TXN0
INT_HDMI_TXP0
INT_HDMI_TXCN
INT_HDMI_TXCP
INT_HDMI_TXN2
INT_HDMI_TXP2
INT_HDMI_TXN1
INT_HDMI_TXP1
INT_HDMI_TXN0
INT_HDMI_TXP0
INT_HDMI_TXCN
INT_HDMI_TXCP
C51
C50
C53
B54
C49
B50
A53
B53
DDI2_TXN0
DDI2_TXP0
DDI2_TXN1
DDI2_TXP1
DDI2_TXN2
DDI2_TXP2
DDI2_TXN3
DDI2_TXP3
HSW_ULT_DDR3L
1 OF 19
EDP_COMP
C45
EDP_TXN0
B46
EDP_TXP0
A47
EDP_TXN1
B47
EDP_TXP1
C47
EDP_TXN2
C46
EDP_TXP2
A49
EDPDDI
EDP_TXN3
EDP_TXP3
EDP_AUXN
EDP_AUXP
EDP_RCOMP
EDP_DISP_UTIL
B49
A45
B45
D20
A43
EDP_AUXN
EDP_AUXP
EDP_COMP
EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1
EDP_AUXN
EDP_AUXP
R290 *0_4_NC
[25]
[25]
[25]
[25]
HDMI_SCL
HDMI_SDA
[25]
[25]
LCD_PW MDP_UTIL
PIRQ_GPIO77
PIRQ_GPIO80
DGPU_PW R_EN
R22 24.9/F_4
RP2 2.2KX2
R40 10K_4
R308 10K_4
R36 10K_4R291 *0_4_NC
2
1
4
3
+3.3V_RUN
AD4
B8
A9
C6
U6
P4
N4
N2
U7
L1
L3
R5
L4
U14I
EDP_BKLCTL
EDP_BKLEN
EDP_VDDEN
PIRQA/GPIO77
PIRQB/GPIO78
PIRQC/GPIO79
PIRQD/GPIO80
PME
GPIO55
GPIO52
GPIO54
GPIO51
GPIO53
9 OF 19
+3V
+3V
+3V
+3V
+3V
C C
[25]
[42]
[42]
[12,40]
[54,55]
[42]
THERMAL_STP#_CTRL
B B
LCD_PW M
THERMAL_PWR_EN
FAN_PW R_EN
SMB_INT#
DGPU_PW R_EN
TP39
TP55
R293 *0_4_SHORT_NC
PIRQ_GPIO77
PIRQ_GPIO80
TP48
PCI_PME_N
DGPU_PW R_EN
R329*0_4_NC
eDP SIDEBAND
+3V
+3V
+3V
+3V
PCIE
HSW_ULT_DDR3L
DISPLAY
DDPB_CTRLCLK
DDPB_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPB_AUXN
DDPC_AUXN
DDPB_AUXP
DDPC_AUXP
DDPB_HPD
DDPC_HPD
EDP_HPD
B9
C9
D9
D11
C5
B6
B5
A6
C8
A8
D6
HDMI_SCL
HDMI_SDA
EDP_HP_R
12
HDMI_SCL
HDMI_SDA
need check have VGA function
R17
R287
1M_4
100K_4
[27]
[27]
INT_HDMI_HP
R16 1K_4
[27]
EDP_HP
[25]
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Tuesday, July 16, 2013
Date: Sheet of
Tuesday, July 16, 2013
Date: Sheet of
5
4
3
2
Tuesday, July 16, 2013
PROJECT :
Haswell ULT 1/12
Haswell ULT 1/12
Haswell ULT 1/12
1
JW8B
JW8B
JW8B
7 57
7 57
7 57
A
A
A
5
Haswell ULT (DDR3L)
4
3
2
1
U14C
AH63
SA_DQ0
D D
C C
B B
AH62
AK63
AK62
AH61
AH60
AK61
AK60
AM63
AM62
AP63
AP62
AM61
AM60
AP61
AP60
AP58
AR58
AM57
AK57
AL58
AK58
AR57
AN57
AP55
AR55
AM54
AK54
AL55
AK55
AR54
AN54
AY58
AW58
AY56
AW56
AV58
AU58
AV56
AU56
AY54
AW54
AY52
AW52
AV54
AU54
AV52
AU52
AK40
AK42
AM43
AM45
AK45
AK43
AM40
AM42
AM46
AK46
AM49
AK49
AM48
AK48
AM51
AK51
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
HSW_ULT_DDR3L
DDR CHANNEL A
SA_CLK#0
SA_CLK0
SA_CLK#1
SA_CLK1
SA_CKE0
SA_CKE1
SA_CKE2
SA_CKE3
SA_CS#0
SA_CS#1
SA_ODT0
SA_RAS
SA_WE
SA_CAS
SA_BA0
SA_BA1
SA_BA2
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15
SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7
SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7
SM_VREF_CA
SM_VREF_DQ0
SM_VREF_DQ1
[19]
M_B_DQ[63..0]
AU37
AV37
AW36
AY36
AU43
AW43
AY42
AY43
AP33
AR32
AP32
AY34
AW34
AU34
AU35
AV35
AY41
AU36
AY37
AR38
AP36
AU39
AR36
AV40
AW39
AY39
AU40
AP35
AW41
AU41
AR35
AV42
AU42
AJ61
AN62
AM58
AM55
AV57
AV53
AL43
AL48
AJ62
AN61
AN58
AN55
AW57
AW53
AL42
AL49
AP49
SM_VREF_CA
AR51
AP51
Check if not used. NC ?
12/25 Del SM_VREF_DQ0
SM_VREF_CA
SM_VREF_DQ1
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
[19]
[19]
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
AY31
AW31
AY29
AW29
AV31
AU31
AV29
AU29
AY27
AW27
AY25
AW25
AV27
AU27
AV25
AU25
AM29
AK29
AL28
AK28
AR29
AN29
AR28
AP28
AN26
AR26
AR25
AP25
AK26
AM26
AK25
AL25
AY23
AW23
AY21
AW21
AV23
AU23
AV21
AU21
AY19
AW19
AY17
AW17
AV19
AU19
AV17
AU17
AR21
AR22
AL21
AM22
AN22
AP21
AK21
AK22
AN20
AR20
AK18
AL18
AK20
AM20
AR18
AP18
U14D
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
HSW_ULT_DDR3L
DDR CHANNEL B
SB_CK#0
SB_CK0
SB_CK#1
SB_CK1
SB_CKE0
SB_CKE1
SB_CKE2
SB_CKE3
SB_CS#0
SB_CS#1
SB_ODT0
SB_RAS
SB_WE
SB_CAS
SB_BA0
SB_BA1
SB_BA2
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15
SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7
SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7
AM38
AN38
AK38
AL38
AY49
AU50
AW49
AV50
AM32
AK32
AL32
AM35
AK35
AM33
AL35
AM36
AU49
AP40
AR40
AP42
AR42
AR45
AP45
AW46
AY46
AY47
AU46
AK36
AV47
AU47
AK33
AR46
AP46
AW30
AV26
AN28
AN25
AW22
AV18
AN21
AN18
AV30
AW26
AM28
AM25
AV22
AW18
AM21
AM18
M_B_CLKN0
M_B_CLKP0
M_B_CLKN1
M_B_CLKP1
M_B_CKE0
M_B_CKE1
M_B_CS#0
M_B_CS#1
M_B_RAS#
M_B_WE#
M_B_CAS#
M_B_BS#0
M_B_BS#1
M_B_BS#2
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_DQSN0
M_B_DQSN1
M_B_DQSN2
M_B_DQSN3
M_B_DQSN4
M_B_DQSN5
M_B_DQSN6
M_B_DQSN7
M_B_DQSP0
M_B_DQSP1
M_B_DQSP2
M_B_DQSP3
M_B_DQSP4
M_B_DQSP5
M_B_DQSP6
M_B_DQSP7
M_B_CLKN0
M_B_CLKP0
M_B_CLKN1
M_B_CLKP1
M_B_CKE0
M_B_CKE1
M_B_CS#0
M_B_CS#1
M_B_RAS#
M_B_WE#
M_B_CAS#
M_B_BS#[2..0]
M_B_A[15..0]
M_B_DQSN[7..0]
M_B_DQSP[7..0]
[19]
[19]
[19]
[19]
[19]
[19]
[19]
[19]
[19]
[19]
[19]
[19]
[19]
[19]
[19]
3 OF 19
A A
5
4
3
4 OF 19
2
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Friday, May 10, 2013
Date: Sheet of
Friday, May 10, 2013
Date: Sheet of
Friday, May 10, 2013
PROJECT :
Haswell ULT 2/12
Haswell ULT 2/12
Haswell ULT 2/12
1
JW8B
JW8B
JW8B
8 57
8 57
8 57
A
A
A
5
4
3
2
1
GPIO Pull-up/Pull-down(CLG)
+3.3V_SUS
Hasswell ULT(GPIO,LPIO,MISC)
D D
+V1.05S_VCCST
U14J
not use function pin net
AUDIO_PWR_EN
GPIO8
GPIO15
KB_DET#
GPIO24
GPIO28
USB3.0_RD_EN
SLATE_MODE_HALL_IN
SNSR_HUB_RST_ACCEL_DRDY_N
C C
SENSOR_HUB_INT
LPT_LAN_RST#
SNR_HUB_EN
BT_WAKE#
GPIO33
SENSOR_STANDBY_N
DGPU_PW ROK[20,22]
[37]
[26]
USB_MCARD1_DET#[37]
PCIE_MCARD1_DET#[37]
[20]
[17]
[35]
[36]
[36]
[30]
D8 SDMK0340L-7-F
WLAN_ON/OFF#
LCD_DBC
DGPU_HOLD_RST#
MODPHY_EN
USB_LEFT_EN
SIO_EXT_SCI#[38]
DEVSLP1
DEVSLP2
ACZ_SPKR
21
GPIO17
SIO_WAKE_SCI#
LPT_CR_RST#
WLAN_ON/OFF#
LCD_DBC
USB_MCARD1_DET#
PCIE_MCARD1_DET#
DGPU_HOLD_RST#
MODPHY_EN
USB_LEFT_EN
USB2_CAM1_PWR_EN
SIO_EXT_SCI#
DEVSLP1
DEVSLP2
No Reboot Strap(GPIO81)
B B
NC
PU
Default
EN
+3.3V_RUN
TLS CONFIDENTIALITY STRAP(GPIO15)
NC
PU
A A
Default
EN
R1547
R1547_NC
+V3.3S_1.8S_LPSS_SDIO
P1
BMBUSY/GPIO76
AU2
AM7
AD6
AD5
AN5
AD7
AN3
AG6
AP1
AL4
AT5
AK4
AB6
AT3
AH4
AM4
AG5
AG3
AM3
AM2
Y1
T3
U4
Y3
P3
Y2
P2
C4
L2
N5
V2
+3V_S5
GPIO8
LAN_PHY_PWR_CTRL/GPIO12
+3V_S5
GPIO15
+3V
GPIO16
+3V
GPIO17
+3V_S5
GPIO24
DSW
GPIO27
+3V_S5
GPIO28
+3V_S5
GPIO26
+3V_S5
GPIO56
+3V_S5
GPIO57
+3V_S5
GPIO58
+3V_S5
GPIO59
+3V_S5
GPIO44
+3V_S5
GPIO47
+3V
GPIO48
+3V
GPIO49
+3V
GPIO50
HSIOPC/GPIO71
+3V_S5
GPIO13
+3V_S5
GPIO14
DSW
GPIO25
+3V_S5
GPIO45
+3V_S5
GPIO46
+3V_S5
GPIO9
+3V_S5
GPIO10
DEVSLP0/GPIO33
SDIO_POWER_EN/GPIO70
DEVSLP1/GPIO38
DEVSLP2/GPIO39
SPKR/GPIO81
10 OF 19
GPIO86:Boot BIOS Strap Bit
PUPDLPC
SPI (Default IPD)
R25
*1K_4_NC
GPIO66 : Top-Block Swap
ENABLE
DISABLE(Default)
R299
*1K_4_NC
BBS
+3V
+3V
+3V
+3V
+3V
+3V
HSW_ULT_DDR3L
DSW
GPIO
+3V
R24
*1K_4_NC
SDIO_D0
R300
*1K_4_NC
CPU/
MISC
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
UART0_RTS/GPIO93
SERIAL IO
+3V
UART0_CTS/GPIO94
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
+3V
THRMTRIP
+3V
RCIN/GPIO82
SERIRQ
PCH_OPI_RCOMP
RSVD
RSVD
GSPI0_CS/GPIO83
GSPI0_CLK/GPIO84
GSPI0_MISO/GPIO85
GSPI0_MOSI/GPIO86
GSPI1_CS/GPIO87
GSPI1_CLK/GPIO88
GSPI1_MISO/GPIO89
GSPI_MOSI/GPIO90
UART0_RXD/GPIO91
UART0_TXD/GPIO92
UART1_RXD/GPIO0
UART1_TXD/GPIO1
UART1_RST/GPIO2
UART1_CTS/GPIO3
I2C0_SDA/GPIO4
I2C0_SCL/GPIO5
I2C1_SDA/GPIO6
I2C1_SCL/GPIO7
SDIO_CLK/GPIO64
SDIO_CMD/GPIO65
SDIO_D0/GPIO66
SDIO_D1/GPIO67
SDIO_D2/GPIO68
SDIO_D3/GPIO69
R12
1K_4
D60
PCH_THRMTRIP#
V4
SIO_RCIN#
T4
IRQ_SERIRQ
AW15
PCH_OPIRCOMP DEVSLP2
AF20
AB21
R6
GSPI_CS
L6
DSP_RST#
N6
HDMI_PD#_LPT
L8
BBS
R7
L5
N7
TOUCHPANEL_EN
K2
TOUCH_PANEL_INTR#
J1
GPIO91
K3
GPIO92
J2
GPIO93
G1
GPIO94
K4
URAT1_RX
G2
URAT1_TX
J3
URAT1_RST
J4
URAT1_CTS
F2
I2C_DA0
F3
I2C_CK0
G4
I2C_DA1
F1
I2C_CK1
E3
SDIO_CK
F4
SDIO_CMD
D3
SDIO_D0
E4
SDIO_D1
C3
SDIO_D2
E2
SDIO_D3
SIO_RCIN# [38]
IRQ_SERIRQ
HDMI_PD#_LPT
BT_RADIO_DIS#
EC_CS_EXT
I2C_DA0
I2C_CK0
I2C_DA1
I2C_CK1
[38]
[27]
[37]
[38]
[31]
[31]
[40]
[40]
SIO_WAKE_SCI#
LCD_DBC
USB_LEFT_EN
SIO_EXT_SCI#
GPIO15
PCIE_MCARD1_DET#
DEVSLP1
SIO_RCIN#
AUDIO_PWR_EN
USB_MCARD1_DET#
GSPI_CS
IRQ_SERIRQNFC_IRQ_R
GPIO91
GPIO92
GPIO93
GPIO94
HDMI_PD#_LPT
DSP_RST#
TOUCH_PANEL_INTR#
TOUCHPANEL_EN
PCH_OPIRCOMP
I2C_DA0
I2C_CK0
I2C_DA1
I2C_CK1
URAT1_RST
URAT1_RX
URAT1_CTS
URAT1_TX
SDIO_CK
SDIO_CMD
SDIO_D1
SDIO_D2
SDIO_D3
GPIO8
GPIO24
GPIO28
NFC_IRQ_R
SENSOR_HUB_INT
LPT_CR_RST#
USB3.0_RD_EN
SLATE_MODE_HALL_IN
SNSR_HUB_RST_ACCEL_DRDY_N
LPT_LAN_RST#
SNR_HUB_EN
BT_WAKE#
USB2_CAM1_PWR_EN
KB_DET#
GPIO17
GPIO33
SENSOR_STANDBY_N
R124 10K_4
R337 10K_4
R344 10K_4
R352 10K_4
R65 10K_4
R323 10K_4
R307 *10K_4_NC
R34 *10K_4_NC
R53 10K_4
R314 10K_4
R48 10K_4
R42 10K_4
R38 10K_4
2
RP16 10KX2
RP15 10KX2
R32 10K_4
R28 *10K_4_NC
R305 10K_4
R39 10K_4
R397 49.9/F_4
1
4
3
4
3
2
1
50K
4
2
4
2
4
2
4
2
4
2
4
2
R358 10K_4
R69 10K_4
R66 10K_4
R345 10K_4
R84 10K_4
R74 10K_4
R338 10K_4
R125 10K_4
R336 10K_4
R77 10K_4
R81 10K_4
R123 10K_4
R365 10K_4
3
1
3
1
3
1
3
1
3
1
3
1
RP4 10KX2
RP14 10KX2
RP6 10KX2
RP5 10KX2
RP3 10KX2
RP1 10KX2
R298 10K_4
R322 10K_4
R45 10K_4
R310 10K_4
R297 10K_4
+3.3V_SUS
+3.3V_RUN
+3.3V_RUN
+3.3V_SUS
+3.3V_RUN
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Thursday, June 13, 2013
Date: Sheet of
Thursday, June 13, 2013
Date: Sheet of
5
4
3
2
Thursday, June 13, 2013
PROJECT :
Haswell ULT 3/12
Haswell ULT 3/12
Haswell ULT 3/12
1
JW8B
JW8B
JW8B
9 57
9 57
9 57
A
A
A
5
4
3
2
1
D D
[20]
PEG_RXN0
[20]
PEG_RXP0
[20]
PEG_TXN0
[20]
PEG_TXP0
[20]
PEG_RXN1
[20]
PEG_RXP1
[20]
GPU
C C
GIGA LAN
WIFI
USB3.0 Port (Left)
Cardreader
B B
[20]
[20]
[20]
[20]
[20]
[20]
[20]
[20]
[20]
[32]
[32]
[32]
[32]
[37]
[37]
[37]
[37]
[35]
[35]
[35]
[35]
[33]
[33]
[33]
[33]
+V1.05S_AUSB3PLL
PEG_TXN1
PEG_TXP1
PEG_RXN2
PEG_RXP2
PEG_TXN2
PEG_TXP2
PEG_RXN3
PEG_RXP3
PEG_TXN3
PEG_TXP3
PCIE_RXN3
PCIE_RXP3
PCIE_TXN3
PCIE_TXP3
PCIE_RXN4
PCIE_RXP4
PCIE_TXN4
PCIE_TXP4
USB3.0_RX3ÂUSB3.0_RX3+
USB3.0_TX3-
USB3.0_TX3+
PCIE_RXN2
PCIE_RXP2
PCIE_TXN2
PCIE_TXP2
1 2
R20 3K/F_4
1 2
R19 *0_4_SHORT_NC
PCIE_RCOMP
PCIE_IREF
Haswell ULT (PCIE,USB)
U14K
F10
PERN5_L0
E10
PERP5_L0
C23
PETN5_L0
C22
PETP5_L0
F8
PERN5_L1
E8
PERP5_L1
B23
PETN5_L1
A23
PETP5_L1
H10
PERN5_L2
G10
PERP5_L2
B21
PETN5_L2
C21
PETP5_L2
E6
PERN5_L3
F6
PERP5_L3
B22
PETN5_L3
A21
PETP5_L3
G11
PERN3
F11
PERP3
C29
PETN3
B30
PETP3
F13
PERN4
G13
PERP4
B29
PETN4
A29
PETP4
G17
PERN1/USB3RN3
F17
PERP1/USB3RP3
C30
PETN1/USB3TN3
C31
PETP1/USB3TP3
F15
PERN2/USB3RN4
G15
PERP2/USB3RP4
B31
PETN2/USB3TN4
A31
PETP2/USB3TP4
E15
RSVD
E13
RSVD
A27
PCIE_RCOMP
B27
PCIE_IREF
11 OF 19
HSW_ULT_DDR3L
PCIE USB
+3V_S5
+3V_S5
+3V_S5
+3V_S5
USB2N0
DSW
USB2P0
USB2N1
DSW
USB2P1
USB2N2
DSW
USB2P2
USB2N3
DSW
USB2P3
USB2N4
DSW
USB2P4
USB2N5
DSW
USB2P5
USB2N6
DSW
USB2P6
USB2N7
DSW
USB2P7
USB3RN1
USB3RP1
USB3TN1
USB3TP1
USB3RN2
USB3RP2
USB3TN2
USB3TP2
USBRBIAS
USBRBIAS
OC0/GPIO40
OC1/GPIO41
OC2/GPIO42
OC3/GPIO43
RSVD
RSVD
AN8
AM8
AR7
AT7
AR8
AP8
AR10
AT10
AM15
AL15
AM13
AN13
AP11
AN11
AR13
AP13
G20
H20
C33
B34
E18
F18
B33
A33
AJ10
AJ11
AN10
AM10
AL3
USB_OC0#
AT1
USB_OC1#
AH2
USB_OC2#
AV3
USB_RIGHT_EN
USB_BIAS
USBPLLMON_N
USBPLLMON_P
USBP0ÂUSBP0+
USBP1ÂUSBP1+
USBP2ÂUSBP2+
USBP3ÂUSBP3+
USBP4ÂUSBP4+
USBP5ÂUSBP5+
USBP6ÂUSBP6+
USBP7ÂUSBP7+
USB3.0_RX1ÂUSB3.0_RX1+
USB3.0_TX1ÂUSB3.0_TX1+
USB3.0_RX2ÂUSB3.0_RX2+
USB3.0_TX2ÂUSB3.0_TX2+
R105 22.6/F_4
R108 49.9/F_4
R107 49.9/F_4
USB_OC0# [35]
USB_OC1# [34]
USB_RIGHT_EN
[34]
[34]
[34]
[34]
[35]
[35]
[28]
[28]
[28]
[28]
[26]
[26]
[37]
[37]
[28]
[28]
[34]
[34]
[34]
[34]
[34]
[34]
[34]
[34]
USB3.0 Port (Power Share)
USB3.0 Port (Right)
USB3.0 Port (Left)
Finger Print
Camara
eTP Touch Panel
Bluetooth
Touch Panel ( JW8 )
USB3.0 Port
(Power Share)
USB3.0 Port (Right)
[34]
HARRIS_BEACH_CS REV 3.0
USB_OC0#
USB_OC1#
USB_OC2#
USB_RIGHT_EN
1 2
R88 10K_4
1 2
R350 10K_4
1 2
R332 10K_4
1 2
R388 *100K_4_NC
+3.3V_SUS
A A
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Monday, July 08, 2013
Date: Sheet of
Monday, July 08, 2013
Date: Sheet of
5
4
3
2
Monday, July 08, 2013
PROJECT :
Haswell ULT 4/12
Haswell ULT 4/12
Haswell ULT 4/12
1
JW8B
JW8B
JW8B
10 57
10 57
10 57
A
A
A
5
4
3
2
1
C457 15P/50V/_4
C458 15P/50V/_4
D D
+RTC_CELL
C C
[30]
[30]
12
Y3
32.768KHZ
R119 20K/F_4
R405 20K/F_4
C190
1U/6.3V_4
HDA_SYNC
HDA_RST#
PCH JTAG Debug (CLG)
MP remove(Intel)
XDP_TMS
XDP_TDI
PCH_JTAG_TDO
PCH_JTAGX
XDP_TCK1
B B
RSVD_PGDMON
HARRIS_BEACH_CS REV 3.0
R340 51_4
R63 51_4
R67 51_4
R346 *1K_4_NC
R351 *51_4_NC
R106 *1K_4_NC
RTC_X1
R385
10M_4
RTC_X2
RTC_RST#
SRTC_RST#
C450
1U/6.3V_4
R409 33_4
R393 33_4
+1.05V_SUS
12
C460 *33P/50V/NPO_4_NC
[30]
HDA_BITCLK
+3.3V_SUS
R396
*1K_4_NC
HDA_SYNC_R
HDA_RST#_R
DFXTESTMODE
HIGH - DFXTESTMODE DISABLED(DEFAULT)
LOW - DFXTESTMODE ENABLED
R411 33_4
[30]
HDA_SDIN0
[38]
PCH_MELOCK
[30]
HDA_SDOUT
XDP_TRST_CPU_N[18]
[18]
+RTC_CELL
XDP_TCK0
HDA_BITCLK_LHDA_BITCLK_L
R395 1K_4
R408 33_4
R120 1M_4
R394 *0_4_SHORT_NC
TP49
R347 0_4
RTC_X1
RTC_X2
SM_INTRUDER#
PCH_INTVRMEN
SRTC_RST#
RTC_RST#
HDA_BITCLK_R
HDA_SYNC_R
HDA_RST#_R
HDA_SDOUT_R
XDP_TCK1
XDP_TDI
PCH_JTAG_TDO
XDP_TMS
RSVD_PGDMON
PM_TEST_RST_N
PCH_JTAGX
PCH_EDM
R387
*0_4_SHORT_NC
Haswell ULT (RTC, HDA, JTAG, SATA)
U14E
AW5
RTCX1
AY5
RTCX2
AU6
INTRUDER
AV7
INTVRMEN
AV6
SRTCRST
AU7
RTCRST
AW8
HDA_BCLK/I2S0_SCLK
AV11
HDA_SYNC/I2S0_SFRM
AU8
HDA_RST/I2S_MCLK
AY10
HDA_SDI0/I2S0_RXD
AU12
HDA_SDI1/I2S1_RXD
AU11
HDA_SDO/I2S0_TXD
AW10
HDA_DOCK_EN/I2S1_TXD
AV10
HDA_DOCK_RST/I2S1_SFRM
AY8
I2S1_SCLK
AU62
PCH_TRST
AE62
PCH_TCK
AD61
PCH_TDI
AE61
PCH_TDO
AD62
PCH_TMS
AL11
RSVD
AC4
RSVD
AE63
JTAGX
AV2
RSVD
5 OF 19
HARRIS_BEACH_CS REV 3.0
HSW_ULT_DDR3L
RTC
AUDIO SATA
JTAG
SATA_RN0/PERN6_L3
SATA_RP0/PERP6_L3
SATA_TN0/PETN6_L3
SATA_TP0/PETP6_L3
SATA_RN1/PERN6_L2
SATA_RP1/PERP6_L2
SATA_TN1/PETN6_L2
SATA_TP1/PETP6_L2
SATA_RN2/PERN6_L1
SATA_RP2/PERP6_L1
SATA_TN2/PETN6_L1
SATA_TP2/PETP6_L1
SATA_RN3/PERN6_L0
SATA_RP3/PERP6_L0
SATA_TN3/PETN6_L0
SATA_TP3/PETP6_L0
+3V
SATA0GP/GPIO34
+3V
SATA1GP/GPIO35
+3V
SATA2GP/GPIO36
+3V
SATA3GP/GPIO37
SATA_RCOMP
SATA_IREF
RSVD
RSVD
SATALED
J5
H5
B15
A15
J8
H8
A17
B17
J6
H6
B14
C15
F5
E5
C17
D17
V1
U1
GPIO35
V6
GPIO36
AC1
GPIO37
A12
SATA_IREF
L11
K10
C12
SATA_RCOMP
U3
PCH_SATA_LED#
SATA_RXN1 [36]
SATA_RXP1 [36]
SATA_TXN1
SATA_TXP1
SATA_RXN2 [36]
SATA_RXP2 [36]
SATA_TXN2
SATA_TXP2
1 2
R318 10K
R294 3K/F_4
R51 10K_4
[36]
[36]
[36]
[36]
SMC_EXTSMI_N[38]
R319 10K_4
R46 10K_4
R328 10K_4
R288 *0_4_SHORT_NC
1 2
1 2
PCH_SATA_LED#
1 2
1 2
1 2
HDD
mSATA
+3.3V_RUN
+V1.05S_ASATA3PLL
+3.3V_RUN
[44]
PCH Strap Table
Pin Name Strap description
SPKR
HDA_SDO
INTVRMEN
A A
No reboot mode setting PWROK
Flash Descriptor Security
Override / Intel ME Debug Mode
Integrated 1.05V VRM enable ALWAYS
5
Sampled
PWROK
Configuration
0 = Default (weak pull-down 20K)
1 = Setting to No-Reboot mode
0 = Security Effect (Int PD)
1 = Can be Override
Should be always pull-up
4
+RTC_CELL
note
R407 *330K_4_NC
3
PCH_INTVRMEN
R392 330K_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Monday, July 08, 2013
Date: Sheet of
Monday, July 08, 2013
Date: Sheet of
2
Monday, July 08, 2013
PROJECT :
Haswell ULT 5/12
Haswell ULT 5/12
Haswell ULT 5/12
1
JW8B
JW8B
JW8B
11 57
11 57
11 57
A
A
A
5
4
3
2
1
Haswell ULT (CLK)
C422 12P/50V/_4
U14F
D D
PCIE_CLK_REQ0#
[33]
CLK_PCIE_CR_N
[33]
CLK_PCIE_CR_P
[33]
PCIE_CLK_REQ1#
[32]
CLK_PCIE_LANN
[32]
CLK_PCIE_LANP
[32]
PCIE_CLK_REQ2#
[37]
CLK_PCIE_WLANN
[37]
CLK_PCIE_WLANP
[37]
PCIE_CLK_REQ3#
[20]
CLK_PCIE_VGAN
[20]
CLK_PCIE_VGAP
[20]
PCIE_CLK_REQ4#
C C
CLK_PCIE_CR_N
CLK_PCIE_CR_P
PCIE_CLK_REQ1#
CLK_PCIE_LANN
CLK_PCIE_LANP
PCIE_CLK_REQ2#
CLK_PCIE_WLANN
CLK_PCIE_WLANP
PCIE_CLK_REQ3#
CLK_PCIE_VGAN
CLK_PCIE_VGAP
PCIE_CLK_REQ4#
PCIE_CLK_REQ5#
C43
CLKOUT_PCIE_N0
C42
CLKOUT_PCIE_P0
U2
PCIECLKRQ0/GPIO18
B41
CLKOUT_PCIE_N1
A41
CLKOUT_PCIE_P1
Y5
PCIECLKRQ1/GPIO19
C41
CLKOUT_PCIE_N2
B42
CLKOUT_PCIE_P2
AD1
PCIECLKRQ2/GPIO20
B38
CLKOUT_PCIE_N3
C37
CLKOUT_PCIE_P3
N1
PCIECLKRQ3/GPIO21
A39
CLKOUT_PCIE_N4
B39
CLKOUT_PCIE_P4
U5
PCIECLKRQ4/GPIO22
B37
CLKOUT_PCIE_N5
A37
CLKOUT_PCIE_P5
T2
PCIECLKRQ5/GPIO23
HSW_ULT_DDR3L
+3V
+3V
+3V
+3V
+3V
+3V
6 OF 19
CLOCK
SIGNALS
XTAL24_IN
XTAL24_OUT
RSVD
RSVD
DIFFCLK_BIASREF
TESTLOW_C35
TESTLOW_C34
TESTLOW_AK8
TESTLOW_AL8
CLKOUT_LPC_0
CLKOUT_LPC_1
CLKOUT_ITPXDP
CLKOUT_ITPXDP_P
A25
B25
K21
M21
C26
C35
C34
AK8
AL8
AN15
AP15
B35
A35
XTAL24_IN
XTAL24_OUT
TESTLOW _0
TESTLOW _1
TESTLOW _2
TESTLOW _3
LPC_CLK_0
LPC_CLK_1
EC5 *10P/50V_4_NC
R21 3K/F_4
RP13 10KX2
RP7 10KX2
R410 22_4
R116 22_4
R117 22_4
12
Haswell ULT (LPC/SPI/SMB/CLINK)
U14G
[37,38]
[37,38]
[37,38]
[37,38]
[37,38]
[39]
[39]
[39]
[39]
[39]
B B
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
EC13 *10P/50V_4_NC
12
PCH_SPI_CLK
PCH_SPI_CS0#
PCH_SPI_CS1#
PCH_SPI_SI
PCH_SPI_SO
AU14
AW12
AY12
AW11
AV12
AA3
AC2
AA2
AA4
AF1
Y7
Y4
Y6
LAD0
LAD1
LAD2
LAD3
LFRAME
SPI_CLK
SPI_CS0
SPI_CS1
SPI_CS2
SPI_MOSI
SPI_MISO
SPI_IO2
SPI_IO3
HSW_ULT_DDR3L
LPC
7 OF 19
SMBUS
+3V_S5
C-LINKSPI
+3V_S5
+3V_S5
+3V_S5
+3V_S5
SMBALERT/GPIO11
SMBCLK
SMBDATA
SML0ALERT/GPIO60
SML0CLK
SML1ALERT/PCHHOT/GPIO73
SML0DATA
SML1CLK/GPIO75
SML1DATA/GPIO74
CL_CLK
CL_DATA
CL_RST
AN2
PCH_SMB_ALERT#
AP2
SMBCLK
AH1
SMBDATA
AL2
CARD_+3.3V_EN
AN1
SMB_CLK0
AK1
SMB_DAT0
AU4
AU3
SMB_CLK_ME1
AH3
SMB_DATA_ME1
AF2
AD2
AF4
R333 *0_4_NC
R292
1M_4
1 2
3
1
3
1
1 2
1 2
1 2
4
3
Y1
24MHz
1
2
C423 12P/50V/_4
4
2
4
2
LPC_CLK_EC
+V1.05S_AXCK_LCPLL
LPC_CLK_EC
LPC_CLK_DEBUG
AP_24M
SMB_INT#
SMBus/Pull-up(CLG)
[38]
[37]
[31]
[7,40]
DMN66D0LDW-7
SMBCLK
Q34A
+3.3V_RUN
5
3 4
PCIE_CLK_REQ0#
PCIE_CLK_REQ1#
PCIE_CLK_REQ2#
PCIE_CLK_REQ3#
PCIE_CLK_REQ4#
PCIE_CLK_REQ5#
SMB_CLK0
SMB_DAT0
PCH_SMB_ALERT#
SMBCLK
SMBDATA
CARD_+3.3V_EN
SMB_DATA_ME1
SMB_CLK_ME1
2
4
RP22
2.2KX2
1
3
RN1 10KX4
1
2
3
4
5
6
7
8
RP17 10KX2
4
3
2
1
RP21 2.2KX2
3
1
RP19 10KX2
1
3
RP20 2.2KX2
3
1
R354 10K_4
RP23 2.2KX2
1
3
SMB_PCH_CLK
+3.3V_RUN
+3.3V_SUS
4
2
2
4
4
2
2
4
[19,40]
DMN66D0LDW-7
SMBDATA
SMB_CLK_ME1
A A
5
4
3
SMB_DATA_ME1
2
6 1
+3.3V_SUS
5
34
Q37A
DMN66D0LDW-7
2
Q37B
DMN66D0LDW-7
61
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Thursday, June 13, 2013
Date: Sheet of
Thursday, June 13, 2013
Date: Sheet of
Thursday, June 13, 2013
PROJECT :
Haswell ULT 6/12
Haswell ULT 6/12
Haswell ULT 6/12
SMBCLK1
SMBDAT1
SMB_PCH_DAT
[38]
[38]
JW8B
JW8B
JW8B
1
[19,40]
12 57
12 57
12 57
A
A
A
2
Q34B
5
4
3
2
1
Haswell ULT (SYSTEM POWER MANAGEMENT)
D D
U14H
ME_SUS_PWR_ACK_R
SYS_PWROK[38]
EC_PWROK[38,42]
[20,32,33,37]
[38]
[38]
[38]
[38]
[38]
C C
APWROK[38]
PLTRST#
RSMRST#
ME_SUS_PWR_ACK
SIO_PWRBTN#
AC_PRESENT
SLP_S0#
1 2
R109 *0_4_SHORT_NC
1 2
R324 *0_4_SHORT_NC
1 2
R391 *0_4_SHORT_NC
1 2
R62 *0_4_SHORT_NC
1 2
R103 *0_4_SHORT_NC
TP51
SUSACK#_R
SYS_PWROK_R
EC_PWROK_R
APWROK_R
PLTRST#
RSMRST#
ME_SUS_PWR_ACK_R
SIO_PWRBTN#
AC_PRESENT
PM_BATLOW#
PCH_SLP_WLAN#
AK2
SUSACK
AC3
SYS_RESET
AG2
SYS_PWROK
AY7
PCH_PWROK
AB5
APWROK
AG7
PLTRST
AW6
RSMRST
AV4
SUSWARN/SUSPWRDNACK/GPIO30
AL7
PWRBTN
AJ8
ACPRESENT/GPIO31
AN4
BATLOW/GPIO72
AF3
SLP_S0
AM5
SLP_WLAN/GPIO29
HSW_ULT_DDR3L
SYSTEM POWER MANAGEMENT
DSW
DSW
DSW
DSW
+3V_S5
DSW
8 OF 19
+3V
+3V_S5
+3V_S5
DSW
DSWVRMEN
DPWROK
DSW
WAKE
CLKRUN/GPIO32
SUS_STAT/GPIO61
SUSCLK/GPIO62
SLP_S5/GPIO63
DSW
SLP_S4
DSW
SLP_S3
DSW
SLP_A
DSW
SLP_SUS
DSW
SLP_LAN
AW7
AV5
AJ5
V5
AG4
AE6
AP5
AJ6
AT4
AL5
AP4
AJ7
DSWVRMEN
DPWROK_RSYS_RESET#
PCIE_WAKE#_R
CLKRUN#
TPM_LPC_PD
1 2
R403 *0_4_NC
1 2
R390 *_0_4_SHORT_NC
1 2
R134 *_0_4_SHORT_NC
CLKRUN#
TP50
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_S3#
TP53
[38]
[38]
[19,38,49]
[14,19,38,49]
RSMRST#
DPWROK
EC_WAKE#
[38]
[38]
PCH Pull-high/low(CLG)
ME_SUS_PWR_ACK_R
PCIE_WAKE#_R
AC_PRESENT
PM_BATLOW#
SIO_PWRBTN#
CLKRUN#
SYS_RESET#
RSMRST#
SYS_PWROK_R
DPWROK_R
APWROK_R
R102 10K_4
R131 10K_4
R78 *10K_4_NC
R122 10K_4
R121 *10K_4_NC
R43 8.2K/J_4
R331 10K_4
R404 10K_4
1 2
R327 *47K_4_NC
1 2
R389 *100K_4_NC
1 2
R60 *47K_4_NC
+RTC_CELL
+3.3V_SUS
+3.3V_SUS
+3.3V_RUN
R406
1 2
R135 *0_4_SHORT_NC
B B
+3.3V_RUN
DSWVRMEN
On Die DSW VR Enable
High = Enable (Default)
330K_4
Low = Disable
C193
*0.1U/16V_4_NC
U15
R114
100K_4
4
*TC7SH08FU_NC
[38]
BUF_PLT_RST#
1 2
A A
5
4
2
1
3 5
PLTRST#
3
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Monday, July 08, 2013
Date: Sheet of
Monday, July 08, 2013
Date: Sheet of
2
Monday, July 08, 2013
PROJECT :
Haswell ULT 7/12
Haswell ULT 7/12
Haswell ULT 7/12
1
JW8B
JW8B
JW8B
13 57
13 57
13 57
A
A
A
5
4
3
2
1
Haswell ULT MCP(POWER)
CPU VDDQ
Haswell ULT 15W : 4.2A Haswell ULT 15W : 32A
+V_VDDQ_CPU
12
C197
0.1U/16V_4
+VCCIN
H_CPU_SVIDALRT#
VR_SVID_CLK
VR_SVID_DATA
H_VR_ENABLE_MCP
VR_READY
TP45
TP47
TP40
TP43
VCCSENSE
FIVR_EN_BUF
MCP_RSVD_69
MCP_RSVD_70
MCP_RSVD_71
MCP_RSVD_72
+VCCIO_OUT
VR_SVID_CLK
1 2
R18 10K_4
+V1.05S_VCCST
AH26
AJ31
AJ33
AJ37
AN33
AP43
AR48
AY35
AY40
AY44
AY50
AC58
AB23
AD23
AA23
AE59
AD60
AD59
AA59
AE60
AC59
AG58
AC22
AE22
AE23
AB57
AD57
AG57
L59
J58
F59
N58
E63
A59
E20
L62
N63
L63
B59
F60
C59
D63
H59
P62
P60
P61
N59
N61
T59
U59
V59
C24
C28
C32
U14L
RSVD
RSVD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VCC
RSVD
RSVD
VCC_SENSE
RSVD
VCCIO_OUT
VCCIOA_OUT
RSVD
RSVD
RSVD
VIDALERT
VIDSCLK
VIDSOUT
VCCST_PWRGD
VR_EN
VR_READY
VSS
PWR_DEBUG
VSS
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VCCST
VCCST
VCCST
VCC
VCC
VCC
VCC
VCC
VCC
HSW_ULT_DDR3L
1.4A 32A
HSW ULT POWER
12 OF 19
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
C36
C40
C44
C48
C52
C56
E23
E25
E27
E29
E31
E33
E35
E37
E39
E41
E43
E45
E47
E49
E51
E53
E55
E57
F24
F28
F32
F36
F40
F44
F48
F52
F56
G23
G25
G27
G29
G31
G33
G35
G37
G39
G41
G43
G45
G47
G49
G51
G53
G55
G57
H23
J23
K23
K57
L22
M23
M57
P57
U57
W57
VCCST_PWRGD_L
[52]
H_VR_ENABLE_MCP
+V1.05S_VCCST
+V_VDDQ_CPU
C455 10U/6.3V_6
C456 10U/6.3V_6
C451 10U/6.3V_6
C452 10U/6.3V_6
C453 10U/6.3V_6
C454 10U/6.3V_6
C143 1U/6.3V_4
C144 1U/6.3V_4
1 2
C145 0.1U/16V_4
1 2
C146 0.1U/16V_4
2 1
D1 SDMK0340L-7-F
R491 1K_4
+VCCIOA_OUT
[52]
+VCCIN
D D
6X10UF MLCC
4X2.2UF MLCC
+V1.05S_VCCST
R14
10K_4
31
2
VCCST_PWRGD#[38]
C C
+V1.05S_VCCST
+3.3V_RUN
R15 *10K_4_NC
R9 *10K_4_NC
Q6
2N7002W
IMVP_PWRGD[52]
VR_READY
H_VR_ENABLE_MCP
+V1.05S_VCCST
+1.05V_RUN
1 2
R54 *0_8_SHORT_NC
CPU VCC
+VCCIN
C106 10U/6.3V_6
C83 10U/6.3V_6
C94 10U/6.3V_6
C107 10U/6.3V_6
C123 10U/6.3V_6
C132 10U/6.3V_6
C148 10U/6.3V_6
C72 10U/6.3V_6
C77 10U/6.3V_6
C76 10U/6.3V_6
C119 10U/6.3V_6
C158 10U/6.3V_6
C70 10U/6.3V_6
C75 10U/6.3V_6
C62 10U/6.3V_6
C82 10U/6.3V_6
C97 10U/6.3V_6
C71 10U/6.3V_6
C79 10U/6.3V_6
C69 10U/6.3V_6
C78 10U/6.3V_6
C63 10U/6.3V_6
C74 10U/6.3V_6
C73 10U/6.3V_6
1 2
C49 100P/50V_4
1 2
C51 100P/50V_4
C50 100P/50V_4
1 2
C52 100P/50V_4
1 2
1/21: 22Ux23 --> 10Ux23
23 X 22UF(0805 MLCC)
VCCSENSE
FIVR_EN_BUF
R304 100/F_4
R37 150_6
+VCCIN
VCCSENSE
+V1.05S_VCCST
[52]
B B
S3 Power reduce
A A
5
4
+V_VDDQ +V_VDDQ_CPU
R440
*ShortPAD_NC
1 2
3
2
SVID ALERT
H_CPU_SVIDALRT#
SVID DATA
VR_SVID_DATA
R312 43_4
+V1.05S_VCCST
+V1.05S_VCCST
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Monday, July 08, 2013
Date: Sheet of
Monday, July 08, 2013
Date: Sheet of
Monday, July 08, 2013
+VCCIO_OUT
R313
75_4
12
R320
130_4
Haswell ULT 8/12
Haswell ULT 8/12
Haswell ULT 8/12
R321
*75_4_NC
+VCCIO_OUT
12
R316
*130_4_NC
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
JW8B
JW8B
JW8B
1
VR_SVID_ALERT#
VR_SVID_DATA
14 57
14 57
14 57
[52]
[52]
A
A
A
5
Haswell ULT (GND)
4
3
2
1
D D
C C
B B
A11
A14
A18
A24
A28
A32
A36
A40
A44
A48
A52
A56
AA1
AA58
AB10
AB20
AB22
AB7
AC61
AD21
AD3
AD63
AE10
AE5
AE58
AF11
AF12
AF14
AF15
AF17
AF18
AG1
AG11
AG21
AG23
AG60
AG61
AG62
AG63
AH17
AH19
AH20
AH22
AH24
AH28
AH30
AH32
AH34
AH36
AH38
AH40
AH42
AH44
AH49
AH51
AH53
AH55
AH57
AJ13
AJ14
AJ23
AJ25
AJ27
AJ29
U14N
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
HSW_ULT_DDR3L
14 OF 19
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AP10
AP17
AP20
AP22
AP23
AP26
AP29
AP3
AP31
AP38
AP39
AP48
AP52
AP54
AP57
AR11
AR15
AR17
AR23
AR31
AR33
AR39
AR43
AR49
AR5
AR52
AT13
AT35
AT37
AT40
AT42
AT43
AT46
AT49
AT61
AT62
AT63
AU1
AU16
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU33
AU51
AU53
AU55
AU57
AU59
AV14
AV16
AV20
AV24
AV28
AV33
AV34
AV36
AV39
AV41
AV43
AV46
AV49
AV51
AV55
U14O
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
HSW_ULT_DDR3L
15 OF 19
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AV59
AV8
AW16
AW24
AW33
AW35
AW37
AW4
AW40
AW42
AW44
AW47
AW50
AW51
AW59
AW60
AY11
AY16
AY18
AY22
AY24
AY26
AY30
AY33
AY4
AY51
AY53
AY57
AY59
AY6
B20
B24
B26
B28
B32
B36
B4
B40
B44
B48
B52
B56
B60
C11
C14
C18
C20
C25
C27
C38
C39
C57
D12
D14
D18
D2
D21
D23
D25
D26
D27
D29
D30
D31
G18
G22
D33
D34
D35
D37
D38
D39
D41
D42
D43
D45
D46
D47
D49
D50
D51
D53
D54
D55
D57
D59
D62
E11
E17
F20
F26
F30
F34
F38
F42
F46
F50
F54
F58
F61
H13
U14P
D5
D8
G3
G5
G6
G8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
HSW_ULT_DDR3L
16 OF 19
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_SENSE
VSS
H17
H57
J10
J22
J59
J63
K1
K12
L13
L15
L17
L18
L20
L58
L61
L7
M22
N10
N3
P59
P63
R10
R22
R8
T1
T58
U20
U22
U61
U9
V10
V3
V7
W20
W22
Y10
Y59
Y63
V58
AH46
V23
E62
AH16
AT2
AU44
AV44
D15
F22
H22
J21
100/F_4
R306
U14R
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VSSSENSE
[52]
HSW_ULT_DDR3L
18 OF 19
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
N23
R23
T23
U10
AL1
AM11
AP7
AU10
AU15
AW14
AY14
U14Q
DC_TEST_AY2_AW2
DC_TEST_AY3_AW3
5
TP_DC_TEST_AY60
DC_TEST_AY61_AW61
DC_TEST_AY62_AW62
TP_DC_TEST_B2
DC_TEST_A3_B3
DC_TEST_A61_B61
DC_TEST_B62_B63
DC_TEST_C1_C2
TP65
TP57
A A
AY2
DAISY_CHAIN_NCTF_AY2
AY3
DAISY_CHAIN_NCTF_AY3
AY60
DAISY_CHAIN_NCTF_AY60
AY61
DAISY_CHAIN_NCTF_AY61
AY62
DAISY_CHAIN_NCTF_AY62
B2
DAISY_CHAIN_NCTF_B2
B3
DAISY_CHAIN_NCTF_B3
B61
DAISY_CHAIN_NCTF_B61
B62
DAISY_CHAIN_NCTF_B62
B63
DAISY_CHAIN_NCTF_B63
C1
DAISY_CHAIN_NCTF_C1
C2
DAISY_CHAIN_NCTF_C2
HSW_ULT_DDR3L
17 OF 19
4
DAISY_CHAIN_NCTF_A3
DAISY_CHAIN_NCTF_A4
DAISY_CHAIN_NCTF_A60
DAISY_CHAIN_NCTF_A61
DAISY_CHAIN_NCTF_A62
DAISY_CHAIN_NCTF_AV1
DAISY_CHAIN_NCTF_AW1
DAISY_CHAIN_NCTF_AW2
DAISY_CHAIN_NCTF_AW3
DAISY_CHAIN_NCTF_AW61
DAISY_CHAIN_NCTF_AW62
DAISY_CHAIN_NCTF_AW63
A3
A4
A60
A61
A62
AV1
AW1
AW2
AW3
AW61
AW62
AW63
DC_TEST_A3_B3
TP_DC_TEST_A4
TP_DC_TEST_A60
DC_TEST_A61_B61
TP_DC_TEST_A62
TP_DC_TEST_AV1
TP_DC_TEST_AW 1
DC_TEST_AY2_AW2
DC_TEST_AY3_AW3
DC_TEST_AY61_AW61
DC_TEST_AY62_AW62
TP_DC_TEST_AW 63
3
TP56
TP42
TP41
TP54
TP52
TP64
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Wednesday, July 17, 2013
Date: Sheet of
Wednesday, July 17, 2013
Date: Sheet of
2
Wednesday, July 17, 2013
PROJECT :
Haswell ULT 9/12
Haswell ULT 9/12
Haswell ULT 9/12
1
JW8B
JW8B
JW8B
15 57
15 57
15 57
A
A
A
5
4
3
2
1
U14S
NOA_RCOMP
TD_IREF
AC60
AC62
AC63
AA63
AA60
AA62
AA61
Y62
Y61
Y60
V62
V61
V60
U60
T63
T62
T61
T60
U63
U62
V63
J20
H18
B12
A5
E1
D1
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
CFG16
CFG18
CFG17
CFG19
CFG_RCOMP
RSVD
RSVD
RSVD
RSVD
RSVD
TD_IREF
CFG0
CFG1
D D
C C
TP25
TP26
TP8
TP7
TP24
TP20
TP22
TP5
TP6
TP28
TP23
TP27
TP21
R325 49.9/F_4
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15
NOA_STBN_0
NOA_STBN_1
NOA_STBP_0
NOA_STBP_1
R289
8.2K/F_4
HSW_ULT_DDR3L
RESERVED
19 OF 19
RSVD_TP
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD_TP
RSVD_TP
RSVD_TP
RSVD
RSVD
PROC_OPI_RCOMP
RSVD
RSVD
RSVD
VSS
VSS
RSVD
RSVD
AV63
MCP_RSVD_19
AU63
MCP_RSVD_20
C63
MCP_RSVD_21
C62
MCP_RSVD_22
B43
A51
MCP_RSVD_24
B51
MCP_RSVD_25
L60
MCP_RSVD_26
N60
W23
Y22
AY15
PROC_OPI_COMP
AV62
D58
P22
N21
P20
R20
TP35
TP29
TP1
TP2
TP17
TP3
TP4
R402 49.9/F_4
Processor Strapping
1 0
CFG0
EAR-STALL/NOT STALL RESET SEQUENCE
AFTER PCU PLL IS LOCKED
CFG1
PCH/ PCH LESS MODE SELECTION
(DEFAULT) NORMAL OPERATION; NO STALL STALL
(DEFAULT) NORMAL OPERATION PCH-LESS MODE
CFG0
CFG1
R339 *1K_4_NC
R334 *1K_4_NC
CFG3
PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)
B B
A A
CFG4
DISPLAY PORT PRESENCE STRAP
CFG 8
ALLOW THE USE OF NOA ON LOCKED UNITS
CFG9
NO SVID PROTOCOL CAPABLE VR CONNECTED
CFG10
SAFE MODE BOOT
5
DISABLED
NO PHYSICAL DISPLAY PORT ATTACHED TO
EMBEDDED DISPLAY PORT
DISABLED
NO PHYSICAL DISPLAY PORT ATTACHED TO
EMBEDDED DISPLAY PORT
DISABLED(DEFAULT); IN THIS CASE,
NOA WILL BE DISABLED IN LOCKED
UNITS AND ENABLED IN UN-LOCKED
UNITS
VRS SUPPORTING SVID PROTOCOL ARE
PRESENT
POWER FEATURES ACTIVATED
DURING RESET
4
ENABLED
AN EXTERNAL DISPLAY PORT DEVICE IS CONNECTED
TO THE EMBEDDED DISPLAY PORT
ENABLED
AN EXTERNAL DISPLAY PORT DEVICE IS CONNECTED
TO THE EMBEDDED DISPLAY PORT
ENABLED; NOA WILL BE AVAILABLE
REGARDLESS OF THE LOCKING OF THE UNIT
NO VR SUPPORTING SVID IS PRESENT. THE
CHIP WILL NOT GENERATE (OR RESPOND TO)
SVID ACTIVITY
POWER FEATURES (ESPECIALLY CLOCK
GATINE ARE NOT ACTIVATED
3
CFG3
R330 *1K_4_NC
CFG4
R61 1K_4
CFG8
R326 *1K_4_NC
CFG9
R58 *1K_4_NC
CFG10
R57 *1K_4_NC
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Friday, May 10, 2013
Date: Sheet of
Friday, May 10, 2013
Date: Sheet of
2
Friday, May 10, 2013
PROJECT :
Haswell ULT 10/12
Haswell ULT 10/12
Haswell ULT 10/12
1
JW8B
JW8B
JW8B
16 57
16 57
16 57
A
A
A
5
VCCHSIO
D D
+3.3V_SUS
+3.3V_SUS
C C
+V3.3DX_1.5DX_1.8DX_AUDIO
12
R118 *0_4_SHORT_NC
+DCPSUSBYP
C525 *0.47U/6.3V_4_NC
+1.05V_RUN
+V1.05DX_MODPHY
1.84A
+1.05V_SUS
+V3.3DX_1.5DX_1.8DX_AUDIO
+1.05V_SUS
114mA
C53 1U/6.3V_4
+1.05V_RUN
+3.3V_SUS
+3.3V_SUS
+3.3V_RUN
+3.3V_SUS
4
C11 10U/6.3V_6
C18 *1U/6.3V_4_NC
C84 1U/6.3V_4
C95 1U/6.3V_4
C88 1U/6.3V_4
*C80-->4.7U
C92 10U/6.3V_6
C66 1U/6.3V_4
C153 1U/6.3V_4
C130 1U/6.3V_4
1/21: 22U --> 10U
C128 10U/6.3V_6
C168 1U/6.3V_4
C115 1U/6.3V_4
+1.05V_RUN
C671U/6.3V_4
+V1.05S_AUSB3PLL
+V1.05S_ASATA3PLL
+V1.05S_APLLOPI
+V1.05S_AXCK_DCB
+V1.05S_AXCK_LCPLL
Haswell ULT PCH(POWER)
3.3 SUS: 205mA
1.05 SUS: 2066mA
1.05 RUN: 2578mA
3.3 RUN: 58mA
AA21
AH14
AH13
AH10
AE20
AE21
L10
B18
B11
Y20
W21
J13
AC9
AA9
W9
J18
K19
A20
J17
R21
T21
K18
M20
V21
U14M
K9
M9
N8
P9
V8
VCCHSIO
VCCHSIO
VCCHSIO
VCC1_05
VCC1_05
VCCUSB3PLL
VCCSATA3PL L
RSVD
VCCAPLL
VCCAPLL
DCPSUS3
VCCHDA
DCPSUS2
VCCSUS3_3
VCCSUS3_3
VCCDSW3 _3
VCC3_3
VCC3_3
VCCCLK
VCCCLK
VCCACLKPLL
VCCCLK
VCCCLK
VCCCLK
RSVD
RSVD
RSVD
VCCSUS3_3
VCCSUS3_3
13 OF 19
1.838A
57mA
10mA
11mA
25mA
62mA
114mA
200mA
41mA
42mA
31mA
LPT LP POWER
HSW_ULT_DDR3L
HSIO
OPI
USB3
HDA
VRM
GPIO/LPC
3
THERMAL SENSOR
SERIAL IO
SUS OSCILLATOR
RTC
SPI
CORE
USB2
1mA
1.632A
658mA
109mA
3mA
41mA
17mA
VCCSUS3_3
18mA
VCCASW
VCCASW
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
DCPSUSBYP
DCPSUSBYP
VCCASW
VCCASW
VCCASW
DCPSUS1
DCPSUS1
VCCTS1_5
VCCSDIO
VCCSDIO
1mA
DCPSUS4
VCC1_05
VCC1_05
VCCRTC
DCPRTC
VCCSPI
VCC3_3
VCC3_3
RSVD
+1.05V_RUN
AH11
AG10
AE7
+VCCRTCEXT
Y8
R56 *0_4_SHORT_NC
AG14
AG13
J11
H11
H15
AE8
AF22
AG19
AG20
+DCPSUSBYP
AE9
AF9
AG8
AD10
AD8
C154 1U/6.3V_4
J15
K14
K16
C91 0.1U/16V_4
U8
T9
C102 1U/6.3V_4
AB8
AC20
AG16
AG17
C151 1U/6.3V_4
L20 2.2uH_8
10U/6.3V_6
C196 1U/6.3V_4
12
C195 0.1U/16V_4
12
C155 0.1U/16V_4
C108 1U/6.3V_4
12
C131 0.1U/16V_4
12
12
C116 0.1U/16V_4
C118 10U/6.3V_6
C149 1U/6.3V_4
C152 1U/6.3V_4
12
C156 1U/6.3V_4
C150 1U/6.3V_4
+1.05V_SUS
+1.5V_RUN
+3.3V_RUN
12
+V1.05A_AOSCSUS
C121 1U/6.3V_4
+1.05V_RUN
12
C411
C425
0.1U/16V_4
2
C418
1U/6.3V_4
VCCSUS3
129mA
VCC1_05
2.6A
VCCASW
+1.05V_RUN
473mA
R315 *0_6_SHORT_NC
12
+1.05V_SUS
L8 2.2uH_8
+3.3V_SUS
+RTC_CELL
+3.3V_SUS
+1.05V_RUN
+1.05V_RUN
1/21: 22U --> 10U
C105 10U/6.3V_6
C64 1U/6.3V_4
+V3.3S_1.8S_LPSS_SDIO +3.3V_RUN
+V1.05S_AXCK_LCPLL
C117
10U/6.3V_6
12
1
+V1.05A_AOSCSUS
C120
0.1U/16V_4
1mA
C122
1U/6.3V_4
C417
0.1U/16V_4
12
C419
0.1U/16V_4
41mA
C424
1U/6.3V_4
42mA
C426
1U/6.3V_4
2
+V1.05DX_MODPHY +V1.05S_AUSB3PLL
+12V_ALW
1 2
1 2
4
+1.05V_SUS
61
2
12
PC12
1U/6.3V_4
DMN66D0LDW-7
Q3B
5
PQ1
FDMC7678
4
3
2
1
PC8
0.01U/16V_4
B B
R11
10K_4
DMN66D0LDW-7
Q3A
1 2
2
Q4
AP2319GN-HF
3 1
R4 330_4
R5 330_4
31
2
Q5
PMF780SN
+3.3V_RUN
R7
100K_4
1 2
PR14
*0_4_SHORT_NC
MODPHY_EN[9]
A A
1 2
5
1 2
R6
*10K_4_NC
34
5
1 2
PR12
100_4
+V1.05DX_MODPHY
1 2
R283 *0_12_NC
3
+1.05V_RUN
L21 2.2uH_8
10U/6.3V_6
*-->4.7U
+V1.05DX_MODPHY +V1.05S_ASATA3PLL
L19 2.2uH_8
*-->4.7U
C421
C415
10U/6.3V_6
12
+1.05V_RUN
L2 2.2uH_8
C12
10U/6.3V_6
+1.05V_RUN
L11 2.2uH_8
C129
10U/6.3V_6
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
Haswell ULT 11/12
Haswell ULT 11/12
Haswell ULT 11/12
Monday, July 08, 2013
Monday, July 08, 2013
Monday, July 08, 2013
+V1.05S_AXCK_DCB
12
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PROJECT :
PROJECT :
PROJECT :
C19
0.1U/16V_4
12
C126
0.1U/16V_4
1
C55
1U/6.3V_4
+V1.05S_APLLOPI
C127
1U/6.3V_4
JW8B
JW8B
JW8B
17 57
17 57
17 57
A
A
A
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