Quanta JM3 Schematic
JM3 Power--
JM3 Power
1. To know JM3 Power-Up Sequence.
2. More easy to find out the root-cause if system
Lock-Up of No-Power.
3. To realize each step before BIOS is working.
4. Summarized preliminary Power-Up sequence
diagram.
up Sequence
up Sequence
5. Power-up sequence after POWER_SW# in the
Nutshell.
Block
High Volt.
Section
DCIN+ DC_IN+
PCIRST#
CPURST#
Banias CPU
Montara GM
+DC_IN
FSB
HUB-LINK
12V
System on, Bat
powered only
BUS
Adapter is
alive
RBAT_7.2V
Section
ICH4
SDC_IN+
V-CHG
charging
VCCRTC
RTCRST#
1715PWROK
Charging
Charging
+RTCSRC
+RTC_PWR5V+RTC_PWR3_3V
PBATT+
SBATT+
Warm swap only
LIVE_ON_BATT
LIVE_ON_BATT
ACAV_IN
THERM_STP#
ALWON
SUSPWROK
shutdown
PWR_SRC
D/D Power
+3VALW,5VALW
+5VSUS,
+1_5VSUS
+2_5VSUS
+3VSUS
SUS_ON
PWRGOOD,
D/D
Section
AUX_EN
LPC
SIO
(MACALLEN)
X-BUS
Flash ROM
(8M bit)
+VCC1_2_GMCH,
VTT,
12V
Delay
(3~12mS)
DELAY_IMVP_PWRGD
VHCORE
(IMVP IV)
RUNPWROK
ICH4
+5VRUN, +3VRUN,
+1_5VRUN, +2_5VRUN,
+1_8VRUN
SLP_S3#
MACALLEN
(LPC47N254)
RUN_ON
Binchuan:
Binchuan:
(1).ADP-IN
(1).ADP-IN
(2).+DC_IN
(2).+DC_IN
(3).DC_IN+
(3).DC_IN+
Schematic page 29
Schematic page 29
DC_IN+
RBAT_7.2V30
R380
12
15K
Near JDCIN1
ADP-IN (1)
Near JDCIN1
C856
100P_50V
JDCIN1
POWER_JACK
H
98765
4
VZ0603M260APT
1
2
3
L27 BLM11B102S
12
D13R_VCC
+12V
C208
1000P
+3VALW
D44
DA204U
DCIN+
RV2
2
1
1
3
DCIN-
ADAPTER--
ADAPTER
D24
3
RB715F
TRACE:20MIL TRACE:20MIL
2
RV3
1 2
VZ0603M260APT
PS_ID 22,34
2
1
FL1 CM1922
12
RV1
VZ0603M260APT
SBATT_CH
21
D45
UDZ3.6B_NC
3
4
CM1922
12
R379
10K
2 1
1N5819HW
SYS_SUSPEND21
C855
+DC_IN (2)
100P_50V
Near JDCIN1
C857
.1U_50V
C858
0.01U_50V
D25
+DC_IN
C35
.47U_0805
25V
2
H
+RTCSRC
47K
12
Q49_G
3
47K
1
R27
240K
R22 47K
1 2
IN(P29)
IN(P29)
PWR_SRC
Q48
FDG316P
4
RP97
2
4
4P2R-S-100K
Q46
DTC144EUA
TRACE:20MIL
3
1
3
6
5
2
1
DC_IN+ (3)
Q37
1
2
3
FDS6679
4
8
7
6
5
DC_IN+
H
C38
.01U
H
L
C41
.1U_50V
Binchuan:
Binchuan:
H : High Level.
H : High Level.
L : Low Level
L : Low Level
And so on.
And so on.
12
C357
.1U_50V
C42
.1U_50V
+
C363
10U_25V_1210
12
R542
4.7K
Binchuan:
Binchuan:
(4). DC_IN+ to SDC_IN+
(4). DC_IN+ to SDC_IN+
Schematic page 37
Schematic page 37
H
DC_IN+
SDC_IN+(P31)
SDC_IN+(P31)
SDC_IN+(4)
H
Binchuan:
Binchuan:
(5). SDC_IN+ to PWR_SRC
(5). SDC_IN+ to PWR_SRC
Schematic page 36
Schematic page 36
PWR_SRC(P36)
PWR_SRC(P36)
H
PWR_SRC
H
Binchuan:
TRACE:20MIL
Binchuan:
+RTCSRC supply +RTC_PWR5V
+RTCSRC supply +RTC_PWR5V
and +RTC_PWR3_3V
and +RTC_PWR3_3V
DC_IN+
RBAT_7.2V30
R380
15K
D13R_VCC
12
+12V
C208
1000P
D24
2
1
RB715F
+
RTCSRC(P41,43)
+
RTCSRC(P41,43)
3
SBATT_CH
12
TRACE:20MIL TRACE:20MIL
R379
10K
SYS_SUSPEND21
+RTCSRC
D25
2 1
1N5819HW
2
+RTCSRC
47K
47K
H
3
Q48
FDG316P
4
RP97
2
4
4P2R-S-100K
Q46
DTC144EUA
3
1
3
PWR_SRC
6
5
2
H
1
PWR_SRC
+RTCSRC
+RTCSRC
R382 10K
H
C644
.1U_50V
1 2
C645
1U_25V
U35 MAX1615
1
IN
SOT23-5
OUT
5/3#
GNDSHDN
1
+RTCSRC
+RTCSRC
H
3
4
25
+RTC_PWR3_3V
C646
+RTC_PWR3_3V
10U_10V
H
R394 10K
1 2
C661
.1U_50V
C662
1U_25V
U39 MAX1615
1
IN
SOT23-5
OUT
5/3#
GNDSHDN
H
3
4
25
+RTC_PWR5V
C654
10U_10V
+RTC_PWR5V
Binchuan:
about Adaptor(Present).
Binchuan:
ACAV_IN will be
ACAV_IN will be
generated after
generated after
+RTC_PWR5V.
+RTC_PWR5V.
DC_IN+ (3)
H
ACAV_IN(P37)
+RTC_PWR5V
R468
75K/F
R471
12.7K/F
DC_IN+
12
12
1
12
R459
1K
R465 10K
1 2
R464 1M
1 2
U52
LM431SACMF
3 2
+RTC_PWR5V
2
12
H
1
Q61
39063
ACAV_IN 22,36,41
ACAV_IN
R458
100K
H
Binchuan:
Binchuan:
ACAV_IN generate to notice SIO
ACAV_IN generate to notice SIO
about Adaptor(Present).
Binchuan:
Binchuan:
MAX1999 use LDO to
MAX1999 use LDO to
output +5VALW&+3VALW
output +5VALW&+3VALW
while U50 pin 17(VCC)
while U50 pin 17(VCC)
has Power Source and
has Power Source and
Pin 6 is at Logic H.
Pin 6 is at Logic H.
PWR_SRC
+3
+3
VALW&+5VALW(P41)
VALW&+5VALW(P41)
H
H
H
THERM_STP#
VCC
SHDN
H
Binchuan:
Binchuan:
(6).As soon as +RTC_PWR3_3V on, then
(6).As soon as +RTC_PWR3_3V on, then
RTCRST# will be from Low ?High.
RTCRST# will be from Low ?High.
(Reset CMOS)
(Reset CMOS)
RTCRST#(P9)
RTCRST#(P9)
VCCRTC
+RTC_PWR3_3V
Binchuan:
Binchuan:
CLK_32KX1/X2 must
CLK_32KX1/X2 must
be generated, it’s for
be generated, it’s for
RTCCLK units(ICH4)
RTCCLK units(ICH4)
using to generate
using to generate
SLP_S3# &SLP_S5#.
SLP_S3# &SLP_S5#.
H
H
H
RTCRST#
ICH4
OSCILLATION
Binchuan:
Binchuan:
(A).POWER_SW# generate
(A).POWER_SW# generate
the POWER_SIO#, and If
the POWER_SIO#, and If
MACALLEN(SIO) is alive
MACALLEN(SIO) is alive
then it’ll assert SUN_ON to
then it’ll assert SUN_ON to
MAX1999 (3/5VSUS)
MAX1999 (3/5VSUS)
H-L-H
POWER_SW#
POWER_SIO#
POWER_SW#27,28
PWRSW_SIO#21
H-L-H
POWER_SW#(P41,P2
POWER_SW#
D26
2 1
RB751V
LIVE_ON_BATT22
+RTC_PWR5V
C650
.1U
ACAV_IN22,36,37
12
R391
10K
R397 100K
1 2
+RTC_PWR5V
5
1 6
+RTC_PWR5V
5
2
1
1 2
U36A
7WZ14
C657
.1U
NC7ST32
1)
U40
4
+RTC_PWR5V
5
2
1
C658
1 2
.1U
U41
7SH32
4
H-L-H
SUS_ON
MACALLEN(SIO)
H
Binchuan:
With respect of MAX1999, the SHDN# pin need
SUS_ON signal to generate 3/5/12V.
Binchuan:
THERM_STP# is OD and will be
THERM_STP# is OD and will be
generated its function after +3VSUS.
generated its function after +3VSUS.
MAX1999(P41)
SHDN#
MAX1999
ON3
ON5
SUS_ON
SUS_ON
Keep ‘H’
H
H
H
H
Binchuan:
Binchuan:
With respect of MAX1999, the SHDN# pin need
to at Logic ‘H’ and Enable ON3 & ON5 from
to at Logic ‘H’ and Enable ON3 & ON5 from
SUS_ON signal to generate 3/5/12V.
Binchuan:
Binchuan:
SUS_ON turn on +3/5VSUS power.
SUS_ON turn on +3/5VSUS power.
While MAX1999 stable then it
While MAX1999 stable then it
generate SUSPWROK_5V.
generate SUSPWROK_5V.
3/5/12V(P41)
15V
+5VSUS
+3VSUS
H
MAX1999
H
H
+12V
H
H
SUSPWROK_5V
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