Quanta FX6 Hepburn AMD UMA Schematic

1

2

3

4

5

6

7

8

Hepburn AMD Discrete GFX

A A

VER : A00

FAN & THERMAL

DDRII-SODIMM1

PG 16,17

DDRII-SODIMM2

PG 16,17

B B

C C

Panel Connector

PG 26

HDMI CONN.

PG 28

CRT CONN.

PG 27

VRAM

PG 23

E-SATA+USB CONN

PG 38

LVDS

HDMI

VGA

SATA - HDD

Fixed SATA ODD

PG 30

PG 30

PG 18,19,20,21,
22

800 MHz DDR II

LVDS

M82-S

632 BGA
25mmX25mm

SATA

SATA

PCIEx16

SATA

USB2.0
Azalia
USB2.0

AUDIO/AMP

IDT_92HD73C

PG 31

A-MIC

PG 32

D D

SPK conn

PG 31 PG 32

Audio
Jacks x3

Camera + D-MIC

PG 32

USER
INTERFACE

PG 44

1

2

3

AMD S1G2

64 X2

(638 S1 socket)

PG 3,4,5,6

HT_LINK

RS780M

528 FCBGA
21mmX21mm

PG 7,8,9,10,11

A_LINK

SB700

528 BGA
21mmX21mm

PG 12,13,14,15

KBC

ITE8512

FLASH
16Mbits

PG 41

LPC

PG 42

18X8

PS/2SPI

Touchpad

PG 43

4

CLOCK

SLG8SP628VTR(QFN)

PCIEx1

PCIEx1

PCIEx2

PCIEx1

USB2.0
USB2.0
USB2.0

USB2.0 x 4

USB2.0

33MHz PCI

CIR

PG 43

TSOP36136TS

Keyboard

PG 43

EMC1423

PG 29

PG 25

5

POWER

REGULATOR

+1.5V_RUN/+1.1V_RUN

PG 50

REGULATOR

+1.8V_SUS/+1.2V_ALW
/+0.9V_DDR_VTT

CPU VR

PG 53

DC/DC

+3.3V_ALW/+5V_ALW
+15V_ALW/+5V_SUS

PG 52

1.2V_ALW_SUS

PG 51,54 PG 60 PG 55

LAN

PG 33

5784M

EXPRESS-CARD

R5538

MINI-CARD

WLAN

MINI-CARD

WWAN

MINI-CARD

WPAN

USB conn x 4

Biometric

PG 37

PG 39

PG 40

PG 39

PG 38

PG 44

SYSTEM
RESET CIRCUIT

AC/BATT
CONNECTOR

M82_POWER+2.5V_RUNVCC_NB

RJ45/Magnetics

PG 34

1394

8-in-1 Card Reader

R5C833

6

PG 35

BATT
CHARGER

PG 47PG 45

RUN POWER SW

+5V/+3.3V/+1.8V/+1.2V_RUN
+3.3V/+1.2V_SUS

1394 CONN.

Card Reader CONN.

Title

Title

Title

BLOCK DIAGRAM

BLOCK DIAGRAM

BLOCK DIAGRAM

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

FX6 3A

FX6 3A

FX6 3A

Date: Sheet

Date: Sheet

Date: Sheet

7

PG 36

PG 36

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

PG 46PG 54PG 49

170Tuesday, May 20, 2008

170Tuesday, May 20, 2008

170Tuesday, May 20, 2008

of

of

of

8

1

INDEX

Pg# Description

Schematic Block Diagram

1

Index/Power States and USB/PCI/PCIe map

2

CPU page

3-6

RS780M page

7-11

12-15

A A

B B

C C

SB700 page
DDRII SO-DIMM(200P)

16-17

M82-S

18-23

24

LCD/CRT HYBRID

Clock Generator

25

LCD Conn.

26

CRT Conn

27

HDMI

28

FAN /THERMAL

29

SATA (HDD&CD_ROM)

30

31-32

Audio CODEC(92HD73)/Phone Jack
LOM /Switch

33-34

PC CARD/1394

35-36

EXPRESS

37

USB

38

Mini Card

39

WWAN

40

Flash ROM, RTC

41

ITE8512

42
43

TP/KB/CIR/BT
Switch,Keyboard & LED

44

System Reset Circuit

45

RUN POWER

46

Battery Charger

47

DCIN,Batt

48

1.8V_SUS,0.9VTT

49

1.5V_RUN AND 1.1V_RUN

50
51

+VCC_NB
+3.3V_ALW/+5V_SUS

52

VCC_VCORE

53
54

+1.2V_ALW_SUS

55

VGA_M82
Power Rail for system

56

Power Sequence Diagram

57

SMBUS BLOCK

58
59 Stitch caps and Screw hole.

POWER STATES

State

Signal

SLP
S3#

SLP
S5#

2

ALWAYS
PLANE

SUS
PLANE

RUN
PLANE

3

4

USB PORT#

0
1
2
3

SB700

4
5
6
7
10
11

PCI TABLE

REQ#/GNT#

CardBus AD17 REQ#1/GNT#1

PM TABLE

CLOCKS

State

power
plane

+15V_ALW
+5V_ALW
+3.3V_ALW +1.8V_SUS +1.5V_RUN

5

DESTINATION
Left side USB.
Left side USB.
IO board
IO board
WLAN
WWAN
WPAN
EXPRESS
Biometric
Camera

+5V_SUS
+3.3V_SUS

+0.9V_DDR_VTT
+1.2V_ALW_SUS

6

PIRQPCI DEVICE IDSEL

IRQ_SERIRQ

IRQD

+5V_RUN
+3.3V_RUN
+2.5V_RUN
+1.8V_RUN
+1.2V_RUN

+VCC_CORE
+NB_VCORE

7

8

PCI EXPRESS DESTINATION

Lane 1
Lane 2
Lane 3
Lane 4

WLAN
WPAN
LOM

EXPRESS CARD

Lane 5 WWAN

S0 (Full ON)

D D

S3 (Suspend to RAM)

S4 (Suspend to DISK) ON OFF

S5 (SOFT OFF) ON OFFLOW LOW

1

HIGH

HIGH

ON

LOW HIGH ON ON OFF

LOW HIGH

2

ON ON ON

OFF

OFF

OFF

OFF

OFF

3

S0

S3

S5 S4/AC

S5 S4 on Battery

4

ON

ON

ON

ON ON

ON

OFF

OFFOFF

5

OFF

OFF

OFF

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

6

Date: Sheet

COMPUTER

Index

Index

Index

FX6 3A

FX6 3A

FX6 3A

7

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of

of

270Tuesday, May 20, 2008

270Tuesday, May 20, 2008

270Tuesday, May 20, 2008

8

5

C672

C665

(19)

D D

C665
10U

10U

10

10
X7R

X7R
0805

0805

C672
10U

10U

10

10
X7R

X7R
0805

0805

C673

C673
10U

10U

10

10
X7R

X7R
0805

0805

4

+1.2V_RUN

C666

C666

0.22U

0.22U

10

10
X7R

X7R
0603

0603

C671

C671

0.22U

0.22U

10

10
X7R

X7R
0603

0603

C669

C669
180P

180P

50

50
NPO

NPO

C674

C674
180P

180P

50

50
NPO

NPO

3

2

1

Place close to socket

* If VLDT is connected only on one side,
one 4.7uF C101 cap should be added to
the island side

U30A

+1.2V_RUN +1.2V_RUN

C C

HT_CADIN07
HT_CADIN#07
HT_CADIN17
HT_CADIN#17
HT_CADIN27
HT_CADIN#27
HT_CADIN37
HT_CADIN#37
HT_CADIN47
HT_CADIN#47
HT_CADIN57
HT_CADIN#57
HT_CADIN67
HT_CADIN#67
HT_CADIN77
HT_CADIN#77
HT_CADIN87
HT_CADIN#87
HT_CADIN97
HT_CADIN#97

B B

A A

5

HT_CADIN107
HT_CADIN#107
HT_CADIN117
HT_CADIN#117
HT_CADIN127
HT_CADIN#127
HT_CADIN137
HT_CADIN#137
HT_CADIN147
HT_CADIN#147
HT_CADIN157
HT_CADIN#157

HT_CLKIN07
HT_CLKIN#07
HT_CLKIN17
HT_CLKIN#17

HT_CTLIN07
HT_CTLIN#07
HT_CTLIN17
HT_CTLIN#17

U30A

D1

VLDT_A0

D2

VLDT_A1

D3

VLDT_A2

D4

VLDT_A3

E3

L0_CADIN_H0

E2

L0_CADIN_L0

E1

L0_CADIN_H1

F1

L0_CADIN_L1

G3

L0_CADIN_H2

G2

L0_CADIN_L2

G1

L0_CADIN_H3

H1

L0_CADIN_L3

J1

L0_CADIN_H4

K1

L0_CADIN_L4

L3

L0_CADIN_H5

L2

L0_CADIN_L5

L1

L0_CADIN_H6

M1

L0_CADIN_L6

N3

L0_CADIN_H7

N2

L0_CADIN_L7

E5

L0_CADIN_H8

F5

L0_CADIN_L8

F3

L0_CADIN_H9

F4

L0_CADIN_L9

G5

L0_CADIN_H10

H5

L0_CADIN_L10

H3

L0_CADIN_H11

H4

L0_CADIN_L11

K3

L0_CADIN_H12

K4

L0_CADIN_L12

L5

L0_CADIN_H13

M5

L0_CADIN_L13

M3

L0_CADIN_H14

M4

L0_CADIN_L14

N5

L0_CADIN_H15

P5

L0_CADIN_L15

J3

L0_CLKIN_H0

J2

L0_CLKIN_L0

J5

L0_CLKIN_H1

K5

L0_CLKIN_L1

N1

L0_CTLIN_H0

P1

L0_CTLIN_L0

P3

L0_CTLIN_H1

P4

L0_CTLIN_L1

FOX_PZ6382A-284S-41F

FOX_PZ6382A-284S-41F

4

HT LINK

HT LINK

VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3

L0_CADOUT_H0

L0_CADOUT_L0

L0_CADOUT_H1

L0_CADOUT_L1

L0_CADOUT_H2

L0_CADOUT_L2

L0_CADOUT_H3

L0_CADOUT_L3

L0_CADOUT_H4

L0_CADOUT_L4

L0_CADOUT_H5

L0_CADOUT_L5

L0_CADOUT_H6

L0_CADOUT_L6

L0_CADOUT_H7

L0_CADOUT_L7

L0_CADOUT_H8

L0_CADOUT_L8

L0_CADOUT_H9

L0_CADOUT_L9

L0_CADOUT_H10

L0_CADOUT_L10

L0_CADOUT_H11

L0_CADOUT_L11

L0_CADOUT_H12

L0_CADOUT_L12

L0_CADOUT_H13

L0_CADOUT_L13

L0_CADOUT_H14

L0_CADOUT_L14

L0_CADOUT_H15

L0_CADOUT_L15

L0_CLKOUT_H0

L0_CLKOUT_L0

L0_CLKOUT_H1

L0_CLKOUT_L1

L0_CTLOUT_H0

L0_CTLOUT_L0

L0_CTLOUT_H1

L0_CTLOUT_L1

AE2
AE3
AE4
AE5

AD1
AC1
AC2
AC3
AB1
AA1
AA2
AA3
W2
W3
V1
U1
U2
U3
T1
R1
AD4
AD3
AD5
AC5
AB4
AB3
AB5
AA5
Y5
W5
V4
V3
V5
U5
T4
T3

Y1
W1
Y4
Y3

R2
R3
T5
R5

500mA

HT_CADOUT0 7
HT_CADOUT#0 7
HT_CADOUT1 7
HT_CADOUT#1 7
HT_CADOUT2 7
HT_CADOUT#2 7
HT_CADOUT3 7
HT_CADOUT#3 7
HT_CADOUT4 7
HT_CADOUT#4 7
HT_CADOUT5 7
HT_CADOUT#5 7
HT_CADOUT6 7
HT_CADOUT#6 7
HT_CADOUT7 7
HT_CADOUT#7 7
HT_CADOUT8 7
HT_CADOUT#8 7
HT_CADOUT9 7
HT_CADOUT#9 7
HT_CADOUT10 7
HT_CADOUT#10 7
HT_CADOUT11 7
HT_CADOUT#11 7
HT_CADOUT12 7
HT_CADOUT#12 7
HT_CADOUT13 7
HT_CADOUT#13 7
HT_CADOUT14 7
HT_CADOUT#14 7
HT_CADOUT15 7
HT_CADOUT#15 7

HT_CLKOUT0 7
HT_CLKOUT#0 7
HT_CLKOUT1 7
HT_CLKOUT#1 7

HT_CTLOUT0 7
HT_CTLOUT#0 7
HT_CTLOUT1 7
HT_CTLOUT#1 7

3

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

2

Date: Sheet

COMPUTER

S1G2 HT I/F

S1G2 HT I/F

S1G2 HT I/F

FX6 3A

FX6 3A

FX6 3A

of

of

of

370Tuesday, May 20, 2008

370Tuesday, May 20, 2008

370Tuesday, May 20, 2008

1

A

B

C

D

E

Notes for the SODIMM locations:

VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED

ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE

CPU_VTT_SUS_SENSE
should be routed as 10mils

4 4

KEEP TRACE TO RESISTORS LESS
THAN 1.0" FROM CPU PIN

+1.8V_SUS

3 3

2 2

1 1

and 10mils spacing from any
adjacent signals in X, Y, Z
directions.

U30B

U30B

D10

C235

C235

0.1U

0.1U

C240

C240

0.1U

0.1U

AD10
AF10

AE10

AA16

10

10
X7R

X7R

10

10
X7R

X7R

C10
B10

H16
T19

V22
U21
V19

T20
U19
U20
V20

J22
J20

N19
N20
E16
F16
Y16

P19
P20

N21
M20
N22
M19
M22
L20
M24
L21
L19
K22
R21
L22
K20
V24
K24
K19

R20
R23

J21

R19
T22
T24

VTT1
VTT2
VTT3
VTT4

MEMZP
MEMZN

RSVD_M1
MA0_ODT0

MA0_ODT1
MA1_ODT0
MA1_ODT1

MA0_CS_L0
MA0_CS_L1
MA1_CS_L0
MA1_CS_L1

MA_CKE0
MA_CKE1

MA_CLK_H5
MA_CLK_L5
MA_CLK_H1
MA_CLK_L1
MA_CLK_H7
MA_CLK_L7
MA_CLK_H4
MA_CLK_L4

MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15

MA_BANK0
MA_BANK1
MA_BANK2

MA_RAS_L
MA_CAS_L
MA_WE_L

MEM:CMD/CTRL/CLK

MEM:CMD/CTRL/CLK

FOX_PZ6382A-284S-41F

FOX_PZ6382A-284S-41F

+0.9V_CPU_M_VREF_SUS

C290

C290
1000P

1000P

50

50
X7R

X7R

39.2/F

39.2/F
R518

R518

M_ZP
M_ZN

39.2/F

39.2/F
R513

R513

DDR_CS0_DIMMA#16,17
DDR_CS1_DIMMA#16,17

DDR_CKE0_DIMMA16,17
DDR_CKE1_DIMMA16,17

M_CLK_DDR016

M_CLK_DDR#016

M_CLK_DDR116

M_CLK_DDR#116

DDR_A_MA[0..15]16,17 DDR_B_MA[0..15] 16,17

DDR_A_BS016,17
DDR_A_BS116,17
DDR_A_BS216,17

DDR_A_RAS#16,17
DDR_A_CAS#16,17

DDR_A_WE#16,17

T49T49

M_ODT016,17
M_ODT116,17

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

+1.8V_SUS

R151

R151
1K/F

1K/F

0603

0603

R192

R192
1K/F

1K/F

0603

0603

PLACE CLOSE TO CPU

sensing point for
op-amp feedback
routed near CPU

A

Place Capacitors for +0.9V_CPU_M_VREF_SUS < 1" from the RS780.
+0.9V_CPU_M_VREF_SUS trace length < 6", trace width > 15mils and
20mils spacing from any adjacent signals in X, Y, Z directions.

+0.9V_DDR_VTT+0.9V_DDR_VTT

W10

VTT5
VTT6
VTT7
VTT8
VTT9

VTT_SENSE

MEMVREF

RSVD_M2

MB0_ODT0
MB0_ODT1
MB1_ODT0

MB0_CS_L0
MB0_CS_L1
MB1_CS_L0

MB_CKE0
MB_CKE1

MB_CLK_H5

MB_CLK_L5

MB_CLK_H1

MB_CLK_L1

MB_CLK_H7

MB_CLK_L7

MB_CLK_H4

MB_CLK_L4

MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8

MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15

MB_BANK0
MB_BANK1
MB_BANK2

MB_RAS_L
MB_CAS_L

MB_WE_L

AC10
AB10
AA10
A10

Y10
W17
B18
W26

W23
Y26

V26
W25
U22

J25
H26

P22
R22
A17
A18
AF18
AF17
R26
R25

P24
N24
P26
N23
N26
L23
N25
L24
M26
K26
T26
L26
L25
W24
J23
J24

R24
U26
J26

U25
U24
U23

B

1750mA

CPU_VTT_SUS_SENSE
+0.9V_CPU_M_VREF_SUSMEM_MA_RESET#
MEM_MB_RESET#

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

C523

C523
*470P_NC

*470P_NC

50

50
X7R

X7R

T50T50

CPU_VTT_SUS_SENSE 49

M_ODT2 16,17
M_ODT3 16,17

DDR_CS0_DIMMB# 16,17
DDR_CS1_DIMMB# 16,17

DDR_CKE2_DIMMB 16,17
DDR_CKE3_DIMMB 16,17

M_CLK_DDR2 16
M_CLK_DDR#2 16
M_CLK_DDR3 16
M_CLK_DDR#3 16

DDR_B_BS0 16,17
DDR_B_BS1 16,17
DDR_B_BS2 16,17

DDR_B_RAS# 16,17
DDR_B_CAS# 16,17
DDR_B_WE# 16,17

DIMMA = CN5
DIMMB = CN6

Processor DDR2 Memory Interface

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61

To SODIMM socket B (Near/TOP)

DDR_B_DM[0..7]16 DDR_A_DM[0..7] 16

DDR_B_DQS[0..7]16

DDR_B_DQS#[0..7]16

C

DDR_B_D62
DDR_B_D63

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

DDR_B_DQS0
DDR_B_DQS#0
DDR_B_DQS1
DDR_B_DQS#1
DDR_B_DQS2
DDR_B_DQS#2
DDR_B_DQS3
DDR_B_DQS#3
DDR_B_DQS4
DDR_B_DQS#4
DDR_B_DQS5
DDR_B_DQS#5
DDR_B_DQS6
DDR_B_DQS#6
DDR_B_DQS7
DDR_B_DQS#7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

U30C

U30C

C11

MB_DATA0

A11

MB_DATA1

A14

MB_DATA2

B14

MB_DATA3

G11

MB_DATA4

E11

MB_DATA5

D12

MB_DATA6

A13

MB_DATA7

A15

MB_DATA8

A16

MB_DATA9

A19

MB_DATA10

A20

MB_DATA11

C14

MB_DATA12

D14

MB_DATA13

C18

MB_DATA14

D18

MB_DATA15

D20

MB_DATA16

A21

MB_DATA17

D24

MB_DATA18

C25

MB_DATA19

B20

MB_DATA20

C20

MB_DATA21

B24

MB_DATA22

C24

MB_DATA23

E23

MB_DATA24

E24

MB_DATA25

G25

MB_DATA26

G26

MB_DATA27

C26

MB_DATA28

D26

MB_DATA29

G23

MB_DATA30

G24

MB_DATA31

AA24

MB_DATA32

AA23

MB_DATA33

AD24

MB_DATA34

AE24

MB_DATA35

AA26

MB_DATA36

AA25

MB_DATA37

AD26

MB_DATA38

AE25

MB_DATA39

AC22

MB_DATA40

AD22

MB_DATA41

AE20

MB_DATA42

AF20

MB_DATA43

AF24

MB_DATA44

AF23

MB_DATA45

AC20

MB_DATA46

AD20

MB_DATA47

AD18

MB_DATA48

AE18

MB_DATA49

AC14

MB_DATA50

AD14

MB_DATA51

AF19

MB_DATA52

AC18

MB_DATA53

AF16

MB_DATA54

AF15

MB_DATA55

AF13

MB_DATA56

AC12

MB_DATA57

AB11

MB_DATA58

Y11

MB_DATA59

AE14

MB_DATA60

AF14

MB_DATA61

AF11

MB_DATA62

AD11

MB_DATA63

A12

MB_DM0

B16

MB_DM1

A22

MB_DM2

E25

MB_DM3

AB26

MB_DM4

AE22

MB_DM5

AC16

MB_DM6

AD12

MB_DM7

C12

MB_DQS_H0

B12

MB_DQS_L0

D16

MB_DQS_H1

C16

MB_DQS_L1

A24

MB_DQS_H2

A23

MB_DQS_L2

F26

MB_DQS_H3

E26

MB_DQS_L3

AC25

MB_DQS_H4

AC26

MB_DQS_L4

AF21

MB_DQS_H5

AF22

MB_DQS_L5

AE16

MB_DQS_H6

AD16

MB_DQS_L6

AF12

MB_DQS_H7

AE12

MB_DQS_L7

FOX_PZ6382A-284S-41F

FOX_PZ6382A-284S-41F

MEM:DATA

MEM:DATA

Athlon 64 S1
Processor Socket

D

MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8

MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63

MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7

MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7

G12
F12
H14
G14
H11
H12
C13
E13
H15
E15
E17
H17
E14
F14
C17
G17
G18
C19
D22
E20
E18
F18
B22
C23
F20
F22
H24
J19
E21
E22
H20
H22
Y24
AB24
AB22
AA21
W22
W21
Y22
AA22
Y20
AA20
AA18
AB18
AB21
AD21
AD19
Y18
AD17
W16
W14
Y14
Y17
AB17
AB15
AD15
AB13
AD13
Y12
W11
AB14
AA14
AB12
AA12

E12
C15
E19
F24
AC24
Y19
AB16
Y13

G13
H13
G16
G15
C22
C21
G22
G21
AD23
AC23
AB19
AB20
Y15
W15
W12
W13

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS#7

DDR_A_DQS[0..7]16

DDR_A_DQS#[0..7]16

Title

Title

Title

S1G2 DDRII MEMORY

S1G2 DDRII MEMORY

S1G2 DDRII MEMORY

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

FX6 3A

FX6 3A

FX6 3A

Date: Sheet

Date: Sheet

Date: Sheet

DDR_A_D[0..63] 16DDR_B_D[0..63]16

To SODIMM socket A (Far/Bottom)

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

E

of

of

of

470Tuesday, May 20, 2008

470Tuesday, May 20, 2008

470Tuesday, May 20, 2008

5

+3.3V_RUN

R117

R107 0R107 0

+5V_ALW2

3

2

1

LDT_RST#

+1.8V_SUS

R484

R484

R492

R492

390

390

390

390

CPU_CLKIN_SC_P
CPU_CLKIN_SC_N

R117

*20K_NC

*20K_NC

R135

R135
10K

10K

Q29

Q29
FDV301N

FDV301N

R4941KR494

1K

CPU_SIC
CPU_SID
CPU_ALERT

2

1

Q25

Q25
*FDV301N_NC

*FDV301N_NC

R101 0R101 0

CPU_PWRGD_SVID_REG

3

Q31

Q31
FDV301N

FDV301N

2

1

R116

R116
*34.8K_NC

*34.8K_NC

3

R131 *0_NCR131 *0_NC

+1.8V_RUN

R103

R103
300

300

CPU_LDT_REQ#_R

D D

+1.8V_RUN

R132

R132
300

300

+1.8V_RUN

+1.8V_RUN

SCLK3
SDATA3

C947

C947
*0.1U_NC

*0.1U_NC

16

16
X7R

X7R

R149

R149
300

300

R143

R143
300

300

R481 *0_NCR481 *0_NC
R487 *0_NCR487 *0_NC

50

50
X7R

X7R

50

50
X7R

X7R

CPU_PWRGD

D4

D4

*RB500V-40_NC

*RB500V-40_NC

LDT_STOP#

D9

RB500V-40D9RB500V-40

D6

RB500V-40D6RB500V-40

R502

R502
169/F

169/F

CPU_PWRGD12

LDT_STOP#9,12

C C

LDT_RST#9,12

SB_PWRGD13,45

B B

CPU_CLK25

CPU_CLK#25

1.KEEP TRACE TO RESISTOR LESS THAN 600MILS FROM CPU
PIN AND TRACE TO AC CAPS LESS THAN 1.2".

2.CPUCLK and CPUCLK# mismatch < 35 mils.

SCLK313

SDATA313

+1.8V_SUS

(20)

R142 0R142 0

C681 3900P

C681 3900P

C679 3900P

C679 3900P

4

C176

C176
*0.1U_NC

*0.1U_NC

10

10
X7R

X7R

CPU_LDT_REQ# 9

CPU_PWRGD_SVID_REG 53

CPU_PWRGD_SVID_REGCPU_PWRGD

L23 is filtered with a 30-300 nH
ferrite bead. and a current rating
of at least 3000mA.

L24

L24

BLM18PG330SN1B

BLM18PG330SN1B

0603

0603

C116

C116
100U

100U

6.3

6.3
Polymer

Polymer
3528

3528

+2.5V_CPU_VDDA_RUN

+2.5V_RUN

+

+

Place R151 and R152 < 1.5".
Route CPU_HTREF1/0 with 5mils trace
width and 10mils spacing from other
signals in X, Y, Z directions

CPU_VDD0_RUN_FB_H53
CPU_VDD0_RUN_FB_L53

CPU_VDD1_RUN_FB_H53
CPU_VDD1_RUN_FB_L53

3

CPU_THERMTRIP#

+2.5V_CPU_VDDA_RUN

LAYOUT: ROUTE VDDA TRACE APPROX.
50 mils WIDE (USE 2x25 mil TRACES TO
EXIT BALL FIELD) AND 500 mils LONG.
This trace should be kept at least 20 mils away from all other signals.

C120

C120

4.7U

4.7U

10

10
X7R

X7R
0805

0805

+2.5V_CPU_VDDA_RUN

C125

C125

0.22U

0.22U

10

10
X7R

X7R
0603

0603

+1.2V_RUN

T48T48

T47T47

T27T27

T26T26

C124

C124
3300P

3300P

50

50
X7R

X7R

R92 44.2/FR92 44.2/F
R94 44.2/FR94 44.2/F

CPU_VDD0_RUN_FB_H
CPU_VDD0_RUN_FB_L

CPU_VDD1_RUN_FB_H
CPU_VDD1_RUN_FB_L

T100T100
T97T97
T101T101

T102T102

CPU_TEST23_TSTUPD
CPU_TEST18_PLLTEST1

CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L

CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST24_SCANCLK1
CPU_TEST22_SCANSHIFTEN
CPU_TEST12_SCANSHIFTENB
CPU_TEST27_SINGLECHAIN

CPU_TEST9_ANALOGIN

R4710R471
0

T46T46
T44T44

T38T38
T36T36

T33T33
T35T35

T40T40

T95T95

+3.3V_RUN

R7761MR776
1M

3

Q106

Q106
FDV301N

FDV301N

2

1

40mA

CPU_CLKIN_SC_P
CPU_CLKIN_SC_N

LDT_RST#
CPU_PWRGD
LDT_STOP#
CPU_LDT_REQ#_R

CPU_SIC
CPU_SID
CPU_ALERT

CPU_HTREF0
CPU_HTREF1

CPU_VDD0_RUN_FB_H
CPU_VDD0_RUN_FB_L

CPU_VDD1_RUN_FB_H
CPU_VDD1_RUN_FB_L

CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI

31

Q105

Q105

2

2N7002W-7-F

2N7002W-7-F

C964

C964

0.1U

0.1U

10

10
X7R

X7R

SVC SVD

0 1.1V
0 1.0V
1 0.9V
1

F8
F9

A9
A8

B7
A7

F10

C6

AF4
AF5

AE6

R6

P6
F6

E6
Y6

AB6

G10

AA9
AC9
AD9
AF9

AD7
H10

G9

E9
E8

AB8
AF7
AE7
AE8
AC8
AF8

C2

AA6

A3
A5
B3
B5

C1

2

H_THERMTRIP# 52

2-Bit Boot VID Codes

Voltage Output
(CPU Power)

0
1
0
1

0.8V

U30D

U30D

VDDA1
VDDA2

CLKIN_H
CLKIN_L

RESET_L
PWROK
LDTSTOP_L
LDTREQ_L

SIC
SID
ALERT_L

HT_REF0
HT_REF1

VDD0_FB_H
VDD0_FB_L

VDD1_FB_H
VDD1_FB_L

DBRDY
TMS
TCK
TRST_L
TDI

TEST23
TEST18

TEST19
TEST25_H

TEST25_L
TEST21

TEST20
TEST24
TEST22
TEST12
TEST27

TEST9
TEST6

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5

KEY1
KEY2

SVC
SVD

THERMTRIP_L

PROCHOT_L

MEMHOT_L

THERMDC
THERMDA

VDDIO_FB_H
VDDIO_FB_L

VDDNB_FB_H
VDDNB_FB_L

DBREQ_L

TDO

TEST28_H
TEST28_L

TEST17
TEST16
TEST15
TEST14

TEST7

TEST10

TEST8

TEST29_H
TEST29_L

RSVD10

RSVD9
RSVD8
RSVD7
RSVD6

FOX_PZ6382A-284S-41F

FOX_PZ6382A-284S-41F

CPU_MEMHOT#_L

CPU_THERMTRIP#_1.8V CPU_THERMTRIP#

CPU_PROCHOT#

+1.8V_SUS

M11
W18

CPU_SVC_R

A6

CPU_SVD_R

A4

AF6
AC7
AA8

W7
W8

W9
Y9

H6
G6

E10
AE9

J7
H8

D7
E7
F7
C7

C3
K8

C4

C9
C8

H18
H19
AA7
D5
C5

R122 0R122 0
R97 0R97 0

CPU_THERMTRIP#_1.8V
CPU_PROCHOT#
CPU_MEMHOT#_L

H_THERMDC
H_THERMDA

Place C212< 100mils from CPU.

CPU_DBREQ#
CPU_TDO

CPU_TEST28_H_PLLCHRZ_P
CPU_TEST28_L_PLLCHRZ_N

CPU_TEST17_BP3CPU_TEST19_PLLTEST0
CPU_TEST16_BP2
CPU_TEST15_BP1
CPU_TEST14_BP0

CPU_TEST29_H_FBCLKOUT_P
CPU_TEST29_L_FBCLKOUT_N

R799 0R799 0

(16)

R503

R503

R93

R93

300

300

300

300

C185

C185
*220P/50V_NC

*220P/50V_NC

CPU_TEST23_TSTUPD
CPU_TEST21_SCANEN
CPU_TEST24_SCANCLK1

+1.8V_SUS

R87

R87
10K

10K
Q22

Q22

2

MMBT3904

MMBT3904

+1.8V_SUS

R493

R493
10K

10K

Q81

Q81

2

MMBT3904

MMBT3904

1 3

2N7002W-7-F

2N7002W-7-F

R86

R86
300

300

T19T19
T29T29

T24T24
T23T23
T30T30
T25T25

T34T34
T28T28

13

Q110

Q110

+3.3V_RUN

R1211KR121
1K

R90

R90
*680_NC

*680_NC

31

R991KR99
1K

1

CPU_MEMHOT# 16

CPU_THERMTRIP# 13

2

BID1 42

CPU_SVC 53
CPU_SVD 53

CPU_PROCHOT# 12

H_THERMDC 29

H_THERMDA 29
CPU_VDDIO_SUS_FB_H 49

CPU_VDDIO_SUS_FB_L 49
CPU_VDDNB_RUN_FB_H 53

CPU_VDDNB_RUN_FB_L 53

(18)

R791 *300_NCR791 *300_NC
R777 300R777 300
R778 300R778 300

HDT CONNECTOR

CN1

CN1

R177 *220_NCR177 *220_NC

R171 *220_NCR171 *220_NC

R179 *220_NCR179 *220_NC

R175 *220_NCR175 *220_NC

R164 300R164 300

CPU_DBREQ#
CPU_DBRDY

A A

CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO

+1.8V_SUS

GND1GND
Resreved13GND
Resreved25GND
DBREQ_L7GND
DBRDY9GND

11

TCK

13

TMS

15

TDI
TRST_L17GND

19

TDO
VDDIO121GND
VDDIO223RESET_L

GND
GND
GND

GND

GND

*HDT conn_NC

*HDT conn_NC

2
4
6
8
10
12

*4.7K_NC

*4.7K_NC

14
16
18
20
22
24
25

*100K_NC

*100K_NC

NOTE:HDT TERMINATION IS REQUIRED FOR REV.Ax SILICON ONLY.

5

R145

R145

R146

R146

+1.8V_RUN+3.3V_RUN

2

R147 0R147 0

R148

R148
*4.7K_NC

*4.7K_NC
Q34

Q34
*MMBT3904_NC

*MMBT3904_NC

13

LDT_RST#CPU_RESET#

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

4

3

2

Date: Sheet

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

S1G2 CTRL & DEBUG

S1G2 CTRL & DEBUG

S1G2 CTRL & DEBUG

FX6 3A

FX6 3A

FX6 3A

1

570Tuesday, May 20, 2008

570Tuesday, May 20, 2008

570Tuesday, May 20, 2008

of

of

of

5

4

3

2

1

PROCESSOR POWER AND GROUND

U30F

U30E

+CPU_VDD0_RUN +CPU_VDD1_RUN

D D

+CPU_VDDNB_RUN

C C

B B

+1.8V_SUS

U30E

G4

VDD0_1

H2

VDD0_2

J9

VDD0_3

J11

VDD0_4

J13

VDD0_5

J15

VDD0_6

K6

VDD0_7

K10

VDD0_8

K12

VDD0_9

K14

VDD0_10

L4

VDD0_11

L7

VDD0_12

L9

VDD0_13

L11

VDD0_14

L13

VDD0_15

L15

VDD0_16

M2

VDD0_17

M6

VDD0_18

M8

VDD0_19

M10

VDD0_20

N7

VDD0_21

N9

VDD0_22

N11

VDD0_23

K16

VDDNB_1

M16

VDDNB_2

P16

VDDNB_3

T16

VDDNB_4

V16

VDDNB_5

H25

VDDIO1

J17

VDDIO2

K18

VDDIO3

K21

VDDIO4

K23

VDDIO5

K25

VDDIO6

L17

VDDIO7

M18

VDDIO8

M21

VDDIO9

M23

VDDIO10

M25

VDDIO11

N17

VDDIO12

FOX_PZ6382A-284S-41F

FOX_PZ6382A-284S-41F

A1

P8

VDD1_1

P10

VDD1_2

R4

VDD1_3

R7

VDD1_4

R9

VDD1_5

R11

VDD1_6

T2

VDD1_7

T6

VDD1_8

T8

VDD1_9

T10

VDD1_10

T12

VDD1_11

T14

VDD1_12

U7

VDD1_13

U9

VDD1_14

U11

VDD1_15

U13

VDD1_16

U15

VDD1_17

V6

VDD1_18

V8

VDD1_19

V10

VDD1_20

V12

VDD1_21

V14

VDD1_22

W4

VDD1_23

Y2

VDD1_24

AC4

VDD1_25

AD2

VDD1_26

Y25

VDDIO27

V25

VDDIO26

V23

VDDIO25

V21

VDDIO24

V18

VDDIO23

U17

VDDIO22

T25

VDDIO21

T23

VDDIO20

T21

VDDIO19

T18

VDDIO18

R17

VDDIO17

P25

VDDIO16

P23

VDDIO15

P21

VDDIO14

P18

VDDIO13

Athlon 64 S1
Processor Socket

+1.8V_SUS

A26

S1g2

uPGA638

A A

Top View

AF1

5

4

U30F

AA4

VSS1

AA11

VSS2

AA13

VSS3

AA15

VSS4

AA17

VSS5

AA19

VSS6

AB2

VSS7

AB7

VSS8

AB9

VSS9

AB23

VSS10

AB25

VSS11

AC11

VSS12

AC13

VSS13

AC15

VSS14

AC17

VSS15

AC19

VSS16

AC21

VSS17

AD6

VSS18

AD8

VSS19

AD25

VSS20

AE11

VSS21

AE13

VSS22

AE15

VSS23

AE17

VSS24

AE19

VSS25

AE21

VSS26

AE23

VSS27

B4

VSS28

B6

VSS29

B8

VSS30

B9

VSS31

B11

VSS32

B13

VSS33

B15

VSS34

B17

VSS35

B19

VSS36

B21

VSS37

B23

VSS38

B25

VSS39

D6

VSS40

D8

VSS41

D9

VSS42

D11

VSS43

D13

VSS44

D15

VSS45

D17

VSS46

D19

VSS47

D21

VSS48

D23

VSS49

D25

VSS50

E4

VSS51

F2

VSS52

F11

VSS53

F13

VSS54

F15

VSS55

F17

VSS56

F19

VSS57

F21

VSS58

F23

VSS59

F25

VSS60

H7

VSS61

H9

VSS62

H21

VSS63

H23

VSS64

J4

VSS65

FOX_PZ6382A-284S-41F

FOX_PZ6382A-284S-41F

VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129

Athlon 64 S1
Processor Socket

J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
AC6
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6

BOTTOMSIDE DECOUPLING

+CPU_VDD0_RUN

C202

C191

C191
22U

22U

4

4
X6S

X6S
0805

0805

+CPU_VDD1_RUN

C190

C190
22U

22U

4

4
X6S

X6S
0805

0805

+1.8V_SUS

C309

C309
22U

22U

4

4
X6S

X6S
0805

0805

C202
22U

22U

4

4
X6S

X6S
0805

0805

C207

C207
22U

22U

4

4
X6S

X6S
0805

0805

C233

C233
22U

22U

4

4
X6S

X6S
0805

0805

C213

C213
22U

22U

4

4
X6S

X6S
0805

0805

C214

C214
22U

22U

4

4
X6S

X6S
0805

0805

C225

C225

0.22U

0.22U

10

10
X7R

X7R
0603

0603

C218

C218
22U

22U

4

4
X6S

X6S
0805

0805

C220

C220
22U

22U

4

4
X6S

X6S
0805

0805

C236

C236

0.22U

0.22U

10

10
X7R

X7R
0603

0603

C219

C219

0.22U

0.22U

10

10
X7R

X7R
0603

0603

C184

C184

0.22U

0.22U

10

10
X7R

X7R
0603

0603

C238

C238
180P

180P

50

50
NPO

NPO

C212

C212

0.01U

0.01U

16

16
X7R

X7R

C195

C195

0.01U

0.01U

16

16
X7R

X7R

C234

C234
180P

180P

50

50
NPO

NPO

DECOUPLING BETWEEN PROCESSOR AND DIMMs
PLACE CLOSE TO PROCESSOR AS POSSIBLE

+1.8V_SUS

C293

C293

4.7U

4.7U

10

10
X7R

X7R
0805

0805

+1.8V_SUS

C227

C227

0.01U

0.01U

16

16
X7R

X7R

+0.9V_DDR_VTT

C179

C179

4.7U

4.7U

10

10
X7R

X7R
0805

0805

+0.9V_DDR_VTT

C701

C701
1000P

1000P

50

50
X7R

X7R

3

C778

C778

4.7U

4.7U

10

10
X7R

X7R
0805

0805

C323

C323

0.01U

0.01U

16

16
X7R

X7R

C694

C694

4.7U

4.7U

10

10
X7R

X7R
0805

0805

C704

C704
1000P

1000P

50

50
X7R

X7R

C292

C292

4.7U

4.7U

10

10
X7R

X7R
0805

0805

C306

C306
180P

180P

50

50
NPO

NPO

C683

C683

4.7U

4.7U

10

10
X7R

X7R
0805

0805

C196

C196
1000P

1000P

50

50
X7R

X7R

C777

C777

4.7U

4.7U

10

10
X7R

X7R
0805

0805

C322,and C237 to be evenly spaced along
the VDDIO/VSS plane split

C322

C322
180P

180P

50

50
NPO

NPO

C161

C161

4.7U

4.7U

10

10
X7R

X7R
0805

0805

C187

C187
1000P

1000P

50

50
X7R

X7R

C284

C284

0.22U

0.22U

10

10
0603

0603
X7R

X7R

C237

C237
180P

180P

50

50
NPO

NPO

C685

C685

0.22U

0.22U

10

10
0603

0603
X7R

X7R

C204

C204
180P

180P

50

50
NPO

NPO

2

C768

C768

0.22U

0.22U

10

10
0603

0603
X7R

X7R

C684

C684

0.22U

0.22U

10

10
0603

0603
X7R

X7R

C245

C245
180P

180P

50

50
NPO

NPO

C194

C194
180P

180P

50

50
NPO

NPO

C203

C203
180P

180P

50

50
NPO

NPO

+CPU_VDDNB_RUN

C223

C217

C217
22U

22U

4

4
X6S

X6S
0805

0805

C285

C285

0.22U

0.22U

10

10
0603

0603
X7R

X7R

C691

C691

0.22U

0.22U

10

10
0603

0603
X7R

X7R

C686

C686
180P

180P

50

50
NPO

NPO

Title

Title

Title

S1G2 PWR & GND

S1G2 PWR & GND

S1G2 PWR & GND

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

FX6 3A

FX6 3A

FX6 3A

Date: Sheet

Date: Sheet

Date: Sheet

C223
22U

22U

4

4
X6S

X6S
0805

0805

C767

C767

0.22U

0.22U

10

10
0603

0603
X7R

X7R

C692

C692

0.22U

0.22U

10

10
0603

0603
X7R

X7R

C689

C689
180P

180P

50

50
NPO

NPO

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

C224

C224
22U

22U

4

4
X6S

X6S
0805

0805

1

of

of

of

670Tuesday, May 20, 2008

670Tuesday, May 20, 2008

670Tuesday, May 20, 2008

5

D D

HT_CADOUT03
HT_CADOUT#03
HT_CADOUT13
HT_CADOUT#13
HT_CADOUT23
HT_CADOUT#23
HT_CADOUT33
HT_CADOUT#33
HT_CADOUT43
HT_CADOUT#43
HT_CADOUT53
HT_CADOUT#53
HT_CADOUT63
HT_CADOUT#63
HT_CADOUT73

C C

B B

HT_CADOUT#73
HT_CADOUT83

HT_CADOUT#83
HT_CADOUT93
HT_CADOUT#93
HT_CADOUT103
HT_CADOUT#103
HT_CADOUT113
HT_CADOUT#113
HT_CADOUT123
HT_CADOUT#123
HT_CADOUT133
HT_CADOUT#133
HT_CADOUT143
HT_CADOUT#143
HT_CADOUT153
HT_CADOUT#153

HT_CLKOUT03
HT_CLKOUT#03
HT_CLKOUT13
HT_CLKOUT#13

HT_CTLOUT03
HT_CTLOUT#03
HT_CTLOUT13
HT_CTLOUT#13

4

R438 300/FR438 300/F

Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25

AC24
AC25

AB25
AB24
AA24
AA25

Y22

Y23
W21
W20

V21

V20

U20

U21

U19

U18

T22

T23

AB23
AA22

M22

M23

R21

R20

C23

A24

U22A

U22A

HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N

HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N

HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N

HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N

HT_RXCALP
HT_RXCALN

RS780M A13

RS780M A13

3

PART 1 OF 6

PART 1 OF 6

HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N

HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P

HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N

HT_TXCLK0P

HT_TXCLK0N

HT_TXCLK1P

HT_TXCLK1N

HYPER TRANSPORT CPU I/F

HYPER TRANSPORT CPU I/F

HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N

HT_TXCALP

HT_TXCALN

D24
D25
E24
E25
F24
F25
F23
F22
H23
H22
J25
J24
K24
K25
K23
K22

F21
G21
G20
H21
J20
J21
J18
K17
L19
J19
M19
L18
M21
P21
P18
M18

H24
H25
L21
L20

M24
M25
P19
R18

B24
B25

R440 300/FR440 300/F

Rev.A13

HT_CADIN0 3
HT_CADIN#0 3
HT_CADIN1 3
HT_CADIN#1 3
HT_CADIN2 3
HT_CADIN#2 3
HT_CADIN3 3
HT_CADIN#3 3
HT_CADIN4 3
HT_CADIN#4 3
HT_CADIN5 3
HT_CADIN#5 3
HT_CADIN6 3
HT_CADIN#6 3
HT_CADIN7 3
HT_CADIN#7 3

HT_CADIN8 3
HT_CADIN#8 3
HT_CADIN9 3
HT_CADIN#9 3
HT_CADIN10 3
HT_CADIN#10 3
HT_CADIN11 3
HT_CADIN#11 3
HT_CADIN12 3
HT_CADIN#12 3
HT_CADIN13 3
HT_CADIN#13 3
HT_CADIN14 3
HT_CADIN#14 3
HT_CADIN15 3
HT_CADIN#15 3

HT_CLKIN0 3
HT_CLKIN#0 3
HT_CLKIN1 3
HT_CLKIN#1 3

HT_CTLIN0 3
HT_CTLIN#0 3
HT_CTLIN1 3
HT_CTLIN#1 3

2

1

R438,R440

RS780

301

RX780 1.21K

A A

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

RS780-HT LINK I/F

RS780-HT LINK I/F

RS780-HT LINK I/F

FX6 3A

FX6 3A

FX6 3A

of

of

of

770Tuesday, May 20, 2008

770Tuesday, May 20, 2008

770Tuesday, May 20, 2008

1

5

D D

4

3

2

1

U22B

AE3
AD4
AE2
AD3
AD1
AD2

AA8
AA7
AA5

AA6

D4
C4
A3
B3
C2
C1
E5

F5
G5
G6
H5
H6

J6

J5

J7

J8

L5

L6
M8

L8
P7
M7
P5
M5
R8
P8
R6
R5
P4
P3

T4

T3

V5

W6

U5
U6
U8
U7

Y8
Y7

W5

Y5

U22B

GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N

GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
GPP_RX4P
GPP_RX4N
GPP_RX5P
GPP_RX5N

SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N

RS780M A13

RS780M A13

PART 2 OF 6

PART 2 OF 6

GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N

PCIE I/F GFX

PCIE I/F GFX

PCIE I/F GPP

PCIE I/F GPP

PCIE I/F SB

PCIE I/F SB

PCE_CALRP(PCE_BCALRP)
PCE_CALRN(PCE_BCALRN)

GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N

GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N

SB_TX0P

SB_TX0N

SB_TX1P

SB_TX1N

SB_TX2P

SB_TX2N

SB_TX3P

SB_TX3N

PCIE_MTX_GRX_P0

A5

PCIE_MTX_GRX_N0

B5

PCIE_MTX_GRX_P1

A4

PCIE_MTX_GRX_N1

B4

PCIE_MTX_GRX_P2

C3

PCIE_MTX_GRX_N2

B2

PCIE_MTX_GRX_P3

D1

PCIE_MTX_GRX_N3

D2

PCIE_MTX_GRX_P4

E2

PCIE_MTX_GRX_N4

E1

PCIE_MTX_GRX_P5

F4

PCIE_MTX_GRX_N5

F3

PCIE_MTX_GRX_P6

F1

PCIE_MTX_GRX_N6

F2

PCIE_MTX_GRX_P7

H4

PCIE_MTX_GRX_N7

H3

PCIE_MTX_GRX_P8

H1

PCIE_MTX_GRX_N8

H2

PCIE_MTX_GRX_P9

J2

PCIE_MTX_GRX_N9

J1

PCIE_MTX_GRX_P10

K4

PCIE_MTX_GRX_N10

K3

PCIE_MTX_GRX_P11

K1

PCIE_MTX_GRX_N11

K2

PCIE_MTX_GRX_P12

M4

PCIE_MTX_GRX_N12

M3

PCIE_MTX_GRX_P13

M1

PCIE_MTX_GRX_N13

M2

PCIE_MTX_GRX_P14

N2

PCIE_MTX_GRX_N14

N1

PCIE_MTX_GRX_P15

P1

PCIE_MTX_GRX_N15

P2
AC1

AC2

PCIE_TXP1_C

AB4

PCIE_TXN1_C

AB3

PCIE_TXP2_C

AA2

PCIE_TXN2_C

AA1

GLAN_TXP_C

Y1

GLAN_TXN_C

Y2

PCIE_TXP4_C

Y4

PCIE_TXN4_C

Y3

PCIE_TXP5_C

V1

PCIE_TXN5_C

V2

ALINK_NBTX_SBRX_P0

AD7

ALINK_NBTX_SBRX_N0

AE7

ALINK_NBTX_SBRX_P1

AE6

ALINK_NBTX_SBRX_N1

AD6

ALINK_NBTX_SBRX_P2

AB6

ALINK_NBTX_SBRX_N2

AC6

ALINK_NBTX_SBRX_P3

AD5

ALINK_NBTX_SBRX_N3

AE5

PCE_PCAL

AC8

PCE_NCAL

AB8

PCIE_MRX_GTX_P[0..15]18 PCIE_MTX_C_GRX_P[0..15] 18

PCIE_MRX_GTX_N[0..15]18

C C

WLAN <----­ WPAN <----- ----->WPAN

B B

GIGA LAN <-----

WWAN <----- ----->WWAN

PCIE_RX1+39
PCIE_RX1-39
PCIE_RX2+39
PCIE_RX2-39

PCIE_RX3-/GLAN_RX-33

PCIE_RX4+37
PCIE_RX4-37
PCIE_RX5+40
PCIE_RX5-40

ALINK_NBRX_SBTX_P012
ALINK_NBRX_SBTX_N012
ALINK_NBRX_SBTX_P112
ALINK_NBRX_SBTX_N112
ALINK_NBRX_SBTX_P212
ALINK_NBRX_SBTX_N212
ALINK_NBRX_SBTX_P312
ALINK_NBRX_SBTX_N312

PCIE_MRX_GTX_P0
PCIE_MRX_GTX_N0
PCIE_MRX_GTX_P1
PCIE_MRX_GTX_N1
PCIE_MRX_GTX_P2
PCIE_MRX_GTX_N2
PCIE_MRX_GTX_P3
PCIE_MRX_GTX_N3
PCIE_MRX_GTX_P4
PCIE_MRX_GTX_N4
PCIE_MRX_GTX_P5
PCIE_MRX_GTX_N5
PCIE_MRX_GTX_P6
PCIE_MRX_GTX_N6
PCIE_MRX_GTX_P7
PCIE_MRX_GTX_N7
PCIE_MRX_GTX_P8
PCIE_MRX_GTX_N8
PCIE_MRX_GTX_P9

PCIE_MRX_GTX_N9
PCIE_MRX_GTX_P10
PCIE_MRX_GTX_N10
PCIE_MRX_GTX_P11
PCIE_MRX_GTX_N11
PCIE_MRX_GTX_P12
PCIE_MRX_GTX_N12
PCIE_MRX_GTX_P13
PCIE_MRX_GTX_N13
PCIE_MRX_GTX_P14
PCIE_MRX_GTX_N14
PCIE_MRX_GTX_P15
PCIE_MRX_GTX_N15

Place near RS780

C581 0.1U/10VC581 0.1U/10V
C583 0.1U/10VC583 0.1U/10V
C575 0.1U/10VC575 0.1U/10V
C578 0.1U/10VC578 0.1U/10V
C572 0.1U/10VC572 0.1U/10V
C573 0.1U/10VC573 0.1U/10V
C535 0.1U/10VC535 0.1U/10V
C534 0.1U/10VC534 0.1U/10V
C550 0.1U/10VC550 0.1U/10V
C556 0.1U/10VC556 0.1U/10V
C555 0.1U/10VC555 0.1U/10V
C557 0.1U/10VC557 0.1U/10V
C544 0.1U/10VC544 0.1U/10V
C543 0.1U/10VC543 0.1U/10V
C536 0.1U/10VC536 0.1U/10V
C545 0.1U/10VC545 0.1U/10V
C551 0.1U/10VC551 0.1U/10V
C552 0.1U/10VC552 0.1U/10V
C538 0.1U/10VC538 0.1U/10V
C537 0.1U/10VC537 0.1U/10V
C547 0.1U/10VC547 0.1U/10V
C539 0.1U/10VC539 0.1U/10V
C554 0.1U/10VC554 0.1U/10V
C553 0.1U/10VC553 0.1U/10V
C559 0.1U/10VC559 0.1U/10V
C560 0.1U/10VC560 0.1U/10V
C540 0.1U/10VC540 0.1U/10V
C541 0.1U/10VC541 0.1U/10V
C563 0.1U/10VC563 0.1U/10V
C561 0.1U/10VC561 0.1U/10V
C546 0.1U/10VC546 0.1U/10V
C542 0.1U/10VC542 0.1U/10V

C19 .1U/10VC19 .1U/10V
C13 .1U/10VC13 .1U/10V
C571 .1U/10VC571 .1U/10V
C570 .1U/10VC570 .1U/10V
C567 .1U/10VC567 .1U/10V
C566 .1U/10VC566 .1U/10V
C569 .1U/10VC569 .1U/10V
C568 .1U/10VC568 .1U/10V
C564 .1U/10VC564 .1U/10V
C565 .1U/10VC565 .1U/10V

C584 .1U/10VC584 .1U/10V
C585 .1U/10VC585 .1U/10V
C582 .1U/10VC582 .1U/10V
C579 .1U/10VC579 .1U/10V
C15 .1U/10VC15 .1U/10V
C16 .1U/10VC16 .1U/10V
C574 .1U/10VC574 .1U/10V

C576 .1U/10VC576 .1U/10V
R40 1.27K/FR40 1.27K/F
R36 2K/FR36 2K/F

+NB_VDD_MUX

PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15

PCIE_TX1+ 39

PCIE_TX1- 39

PCIE_TX2+ 39

PCIE_TX2- 39

PCIE_TX3+/GLAN_TX+ 33PCIE_RX3+/GLAN_RX+33

PCIE_TX3-/GLAN_TX- 33

PCIE_TX4+ 37

PCIE_TX4- 37

PCIE_TX5+ 40

PCIE_TX5- 40

ALINK_NBTX_C_SBRX_P0 12
ALINK_NBTX_C_SBRX_N0 12
ALINK_NBTX_C_SBRX_P1 12
ALINK_NBTX_C_SBRX_N1 12
ALINK_NBTX_C_SBRX_P2 12
ALINK_NBTX_C_SBRX_N2 12
ALINK_NBTX_C_SBRX_P3 12
ALINK_NBTX_C_SBRX_N3 12

PCIE_MTX_C_GRX_N[0..15] 18

----->WLAN

----->GIGA LAN

----->EXPRESS CARDEXPRESS CARD <-----

A A

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

COMPUTER

RS780-PCIE I/F

RS780-PCIE I/F

RS780-PCIE I/F

FX6 3A

FX6 3A

FX6 3A

1

870Tuesday, May 20, 2008

870Tuesday, May 20, 2008

870Tuesday, May 20, 2008

of

of

of

C21

C21
*10U/10V/0805_NC

*10U/10V/0805_NC

+1.8V_HTPLL

C86

C86
*10U/10V/0805_NC

*10U/10V/0805_NC

R39 0R39 0

PLTRST#12,14,18,37,39,45
LDT_RST#5,12

5

R38 *4.7K_NCR38 *4.7K_NC
R37 *4.7K_NCR37 *4.7K_NC

+1.8V_RUN

L3

L3

BLM15AG221SN1D

BLM15AG221SN1D

+1.8V_RUN

L13

L13

BLM15AG221SN1D

BLM15AG221SN1D

D D

220 ohm @ 100MHz

LDT_STOP#5,12

CPU_LDT_REQ#5

C C

ALLOW_LDTSTOP12

+3.3V_RUN

+1.8V_RUN

1

R757 0R757 0

1

R758 0R758 0

+NB_VDD_MUX

BLM15AG221SN1D

BLM15AG221SN1D

C20

C20

2.2U

2.2U

220 ohm @ 100MHz220 ohm @ 100MHz

10

10
X5R

X5R
0603

0603

BLM15AG221SN1D

BLM15AG221SN1D

C84

C84

2.2U

2.2U

220 ohm @ 100MHz

10

10
X5R

X5R
0603

0603

Q68

Q68
*BSS138_NL_NC

*BSS138_NL_NC

2

3

Q15

Q15
*BSS138_NL_NC

*BSS138_NL_NC

2

3

DDC_CLK0/AUX0P
PE_GPIO2

R32 0R32 0
R31 *0_NCR31 *0_NC

L63

L63

L8

L8

+VDDG_NB

R414

R414
*4.7K_NC

*4.7K_NC

NB_LDT_STOP#

+VDDG_NB+1.8V_RUN

R42

R42
*4.7K_NC

*4.7K_NC

NB_ALLOW_LDTSTOP

SYSRESET#

+PLLVDD

C591

C591
*10U/10V/0805_NC

*10U/10V/0805_NC

+PLLVDD18+1.8V_RUN

C69

C69
*10U/10V/0805_NC

*10U/10V/0805_NC

STRAP_DEBUG_BUS_GPIO_ENABLEb

Enables the Test Debug Bus using GPIO.
RX780:NB_TV_C; RS740:RS740_DFT_GPIO5; RS780:VSYNC#
RS740/RS780 RX780
1 Disable Enable
0 Enable Disable

B B

+3.3V_RUN

R759 *3K_NCR759 *3K_NC
R418 *3K_NCR418 *3K_NC

R442 *3K_NCR442 *3K_NC

INT_VGAVSYNC

NB_TV_C

RS740/RS780: Enables Side port memory

RS740:RS740_DFT_GPIO0
RS780:HSYNC#

Selects if Memory SIDE PORT is available or not
1 = Memory Side port Not available
0 = Memory Side port available
Register Readback of strap: NB_CLKCFG:CLK_TOP_SPARE_D[1]

+3.3V_RUN

R419 *3K_NCR419 *3K_NC
R420 3KR420 3K

A A

DFT_GPIO1: LOAD_EEPROM_STRAPS

Selects Loading of STRAPS from EPROM
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use
default values if not connected
RS740/RX780: RS780_AUX_CAL RS780:SUS_STAT

PLTRST#12,14,18,37,39,45

5

INT_VGAHSYNC

D2

D2

SUS_STAT#_R

21

*SDMK0340L-7-F_NC

*SDMK0340L-7-F_NC

4

150mA 135mA

100mA

+3.3V_RUN

C593

C593

2.2U

2.2U

10

10
X5R

X5R
0603

0603

+1.8V_RUN

C65

C65

2.2U

2.2U

10

10

220 ohm @ 100MHz

X5R

X5R
0603

0603

R46 0R46 0

C42

C42

49.9/F

49.9/F

L5

L5

BK1608HS220-T

BK1608HS220-T

0603

0603

220 ohm @ 100MHz

L10

L10

BLM21PG221SN1D

BLM21PG221SN1D

0805

0805

+1.8V_RUN

NB_PWRGD45

HT_REFCLK25
HT_REFCLK#25

CLK_NB_14M25

CLK_NB_GFX25
CLK_NB_GFX#25

CLK_GPP_REFCLK25
CLK_GPP_REFCLK#25

CLK_NB_SBLINK25
CLK_NB_SBLINK#25

T130T130

STRP_DATA51

CLK_NB_14M

AC Term closely
clock pin for
length: 50 mils

R786 *4.7K_NCR786 *4.7K_NC

NOTE: ACCESS TO STRAP_DATA and I2C_CLK PINS IS MANDATORY.

4

+3.3V_AVDD+VDDA18PCIEPLL

C40

C40

2.2U

2.2U

10

10
X5R

X5R
0603

0603

+1.8V_AVDDQ

C80

C80

2.2U

2.2U

10

10
X5R

X5R
0603

0603

+3.3V_AVDD
+1.8V_AVDD

+1.8V_AVDDQ

+PLLVDD

+PLLVDD18

+1.8V_HTPLL

+VDDA18PCIEPLL

R416 300R416 300
R417 0R417 0

RX780->Pop

SUS_STAT#_R

U1

U1

1

NC

2

A1

3

A2

4

VSS

*AT24C04N-10SU-2.7_NC

*AT24C04N-10SU-2.7_NC

+1.8V_RUN +1.8V_AVDD

C72

C72

2.2U

2.2U

10

10
X5R

X5R
0603

0603

100mA

NB_TV_C

INT_VGAHSYNC
INT_VGAVSYNC

R444 715/FR444 715/F

+PLLVDD
+PLLVDD18

+VDDA18PCIEPLL

R33 0R33 0

NB_LDT_STOP#
NB_ALLOW_LDTSTOP

CLK_NB_14M
REFCLK_N

R28 *0_NCR28 *0_NC
R27 *0_NCR27 *0_NC

INT_LCD_DDCCLK
INT_LCD_DDCDAT
DDC_CLK0/AUX0P
PE_GPIO2

R18

R18
*10K_NC

*10K_NC

C8

C8
*0.1U_NC

*0.1U_NC

16

16
X7R

X7R

T6T6
T12T12
T4T4

T5T5
T7T7
T10T10

T90T90
T89T89

SYSRESET#

T85T85
T86T86

VCC

WP
SCL
SDA

R56

R56
0/0805

0/0805

8
7
6
5

3

+VDDG_NB

3

U22C

U22C

F12

AVDD1(NC)

E12

AVDD2(NC)

F14

AVDDDI(NC)

G15

AVSSDI(NC)

H15

AVDDQ(NC)

H14

AVSSQ(NC)

E17

C_Pr(DFT_GPIO5)

F17

Y(DFT_GPIO2)

F15

COMP_Pb(DFT_GPIO4)

G18

RED(DFT_GPIO0)

G17

REDb(NC)

E18

GREEN(DFT_GPIO1)

F18

GREENb(NC)

E19

BLUE(DFT_GPIO3)

F19

BLUEb(NC)

A11

DAC_HSYNC(PWM_GPIO4)

B11

DAC_VSYNC(PWM_GPIO6)

E8

DAC_SDA(PCE_TCALRN)

F8

DAC_SCL(PCE_RCALRN)

G14

DAC_RSET(PWM_GPIO1)

A12

PLLVDD(NC)

D14

PLLVDD18(NC)

B12

PLLVSS(NC)

H17

VDDA18HTPLL

D7

VDDA18PCIEPLL1

E7

VDDA18PCIEPLL2

D8

SYSRESETb

A10

POWERGOOD

C10

LDTSTOPb

C12

ALLOW_LDTSTOP

C25

HT_REFCLKP

C24

HT_REFCLKN

E11

REFCLK_P/OSCIN(OSCIN)

F11

REFCLK_N(PWM_GPIO3)

T2

GFX_REFCLKP

T1

GFX_REFCLKN

U1

GPP_REFCLKP

U2

GPP_REFCLKN

V4

GPPSB_REFCLKP(SB_REFCLKP)

V3

GPPSB_REFCLKN(SB_REFCLKN)

B9

I2C_CLK

A9

I2C_DATA

A8

DDC_CLK0/AUX0P(NC)

B8

DDC_DATA0/AUX0N(NC)

B7

DDC_CLK1/AUX1P(NC)

A7

DDC_DATA1/AUX1N(NC)

B10

STRP_DATA

G11

RSVD

C8

AUX_CAL(NC)

R35

R35
*150/F_NC

*150/F_NC

R14

R14
*2K_NC

*2K_NC

INT_LCD_DDCCLK
STRP_DATA

R112KR11
2K

C11

C11

R30

R30
*4.7K_NC

*4.7K_NC

*10P/50V_NC

*10P/50V_NC

PART 3 OF 6

PART 3 OF 6

TXOUT_L2N(DBG_GPIO0)
TXOUT_L3N(DBG_GPIO2)

TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)

TXOUT_U3P(PCIE_RESET_GPIO5)

CRT/TVOUT

CRT/TVOUT

TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)

LVTM

LVTM

PM

PM

LVDS_DIGON(PCE_TCALRP)

LVDS_BLON(PCE_RCALRP)

LVDS_ENA_BL(PWM_GPIO2)

CLOCKs PLL PWR

CLOCKs PLL PWR

MIS.

MIS.

+VDDG_NB

R34

R34
*4.7K_NC

*4.7K_NC

INT_LCD_DDCCLK
INT_LCD_DDCDAT

C14

C14

*10P/50V_NC

*10P/50V_NC

2

TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)

TXOUT_L3P(NC)

TXOUT_U0P(NC)
TXOUT_U0N(NC)

TXOUT_U2P(NC)
TXOUT_U2N(NC)

TXOUT_U3N(NC)

TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)

VDDLTP18(NC)
VSSLTP18(NC)

VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)

VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)

TMDS_HPD(NC)

HPD(NC)

TVCLKIN(PWM_GPIO5)

THERMALDIODE_P

THERMALDIODE_N

TESTMODE

RS780M A13

RS780M A13

+1.1V_RUN

2

A22
B22
A21
B21
B20
A20
A19
B19

B18
A18
A17
B17
D20
D21
D18
D19

B16
A16
D16
D17

A13
B13

A15
B15
A14
B14

C14
D15
C16
C18
C20
E20
C22

E9
F7
G12

D9
D10

D12
AE8

AD8
D13

+LPVDD_NB

+LVDDR18D

R47 0R47 0

SUS_STAT#_R

R49

R49

1.8K/F

1.8K/F

T91T91
T8T8
T9T9

T11T11
T13T13

T15T15
T14T14

180mA

T2T2

NB_THERMDA

C590

C590
*220P_NC

*220P_NC

50

50

NB_THERMDC

Place C590 close to U22.

R51

R51

Only for RS780

4.7K

4.7K

REFCLK_N

R48 0R48 0

R50

R50

4.7K

4.7K

1

RS740/RX780/RS780 POWER DIFFERENCE
TABLE

PIN NAME
AVDDDI

AVDDQ
PLLVDD19
VDDA18HTPLL +1.8V +1.8V

VDDLTP18
VDDLT18
VDDLT33

C597

C597

C598

C598

2.2U/10V

2.2U/10V

0.1U/10V

0.1U/10V

0603

0603

C62

C62

C63

C63

0.1U/10V

0.1U/10V

4.7U/6.3V

4.7U/6.3V

0603

0603

SUS_STAT# 13

T88T88

RX780/RS780 DEBUG PIN MAPPING

DEBUG_OUT0

T87T87

DEBUG_OUT1
DEBUG_OUT2
DEBUG_OUT3
DEBUG_OUT4
DEBUG_OUT5
DEBUG_OUT6
DEBUG_OUT7

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

COMPUTER

RS780-LVDS

RS780-LVDS

RS780-LVDS

FX6 3A

FX6 3A

FX6 3A

RX780 RS780

NC +3.3VAVDD
NC +1.8V
NC +1.8V

NC
+1.8V +1.8VVDDA18PCIEPLL

NC
NC NC

+VDDG_NB+3.3V_RUN

R29 0R29 0

+1.8V_RUN

L64

L64

BLM15AG221SN1D

BLM15AG221SN1D

220 ohm @ 100MHz

+1.8V_RUN

L7

L7

BLM15AG221SN1D

BLM15AG221SN1D

220 ohm @ 100MHz

SUS_STAT#

RED(DFT_GPIO0)
GREEN(DFT_GPIO1)
Y(DFT_GPIO2)
BLUE(DFT_GPIO3)
TXOUT_L2N(DBG_GPIO0)
TXCLK_LP(DBG_GPIO1)
TXOUT_L3N(DBG_GPIO2)
TXCLK_LN(DBG_GPIO3)
COMB_Pb(DFT_GPIO4)
C_Pr(DFT_GPIO5)

1

+1.1VPLLVDD NC
+1.8V

+1.8VNC
+1.8V

+3.3V_RUN

R52

R52

4.7K

4.7K

C52

C52

RS780RX780
LVDS_DIGON
LVDS_ENA_BL
LVDS_BLON
TMDS_HPD
AUX1N
AUX1P
HPD
AUX_CAL
X
X

970Tuesday, May 20, 2008

970Tuesday, May 20, 2008

970Tuesday, May 20, 2008

of

of

of

*10P/50V_NC

*10P/50V_NC

5

4

3

2

1

RS740/RX780/RS780 POWER DIFFERENCE TABLE

PIN NAME
VDDHT

D11

E14

E15

J12

K14

VSS3G8VSS4

VSS27

Y18

VSS28

AB11

(21)

VSS5

VSS29

AB15

J15

VSS6

VSS30

AB17

VSS7

VSS31

AB19

M11

L15

U22F

U22F
RS780M A13

RS780M A13

VSS8

VSS9

VSS10

VSS32

VSS34

VSS33

K11

AE20

AB21

U22E

U22E

J17

VDDHT_1

K16

VDDHT_2

L16

VDDHT_3

M16

VDDHT_4

P16

VDDHT_5

R16

VDDHT_6

T16

VDDHT_7

H18

VDDHTRX_1

G19

VDDHTRX_2

F20

VDDHTRX_3

E21

VDDHTRX_4

D22

VDDHTRX_5

B23

VDDHTRX_6

A23

VDDHTRX_7

AE25

VDDHTTX_1

AD24

VDDHTTX_2

AC23

VDDHTTX_3

AB22

VDDHTTX_4

AA21

VDDHTTX_5

Y20

VDDHTTX_6

W19

VDDHTTX_7

V18

VDDHTTX_8

U17

VDDHTTX_9

T17

VDDHTTX_10

R17

VDDHTTX_11

P17

VDDHTTX_12

M17

VDDHTTX_13

J10

VDDA18PCIE_1

P10

VDDA18PCIE_2

K10

VDDA18PCIE_3

M10

VDDA18PCIE_4

L10

VDDA18PCIE_5

W9

VDDA18PCIE_6

H9

VDDA18PCIE_7

T10

VDDA18PCIE_8

R10

VDDA18PCIE_9

Y9

VDDA18PCIE_10

AA9

VDDA18PCIE_11

AB9

VDDA18PCIE_12

AD9

VDDA18PCIE_13

AE9

VDDA18PCIE_14

U10

VDDA18PCIE_15

F9

VDDG18_1(VDD18_1)

G9

VDDG18_2(VDD18_2)

AE11

VDD18_MEM1(NC)

AD11

VDD18_MEM2(NC)

RS780M A13

RS780M A13

PART 5/6

PART 5/6

J4

R7

L1

L2

L4

L7

M6

N4

P6

R1

R2

R4

V7

U4

V8

V6

W1

W2

W4

W7

W8

Y6

AA4

AB5

AB1

AB7

H7

D D

C C

220 ohm @ 100MHz, 2A

B B

+3.3V_RUN

1.2V_RUN_ON42,45,46

A A

C87

C87
*2.2U_NC

*2.2U_NC

10

10
X5R

X5R
0603

0603

VSSAPCIE1A2VSSAPCIE2B1VSSAPCIE3D3VSSAPCIE4D5VSSAPCIE5E4VSSAPCIE6G1VSSAPCIE7G2VSSAPCIE8G4VSSAPCIE9

PART 6/6

PART 6/6

VSSAHT1

VSSAHT2

VSSAHT3

A25

E22

D23

G22

+1.1V_RUN +NB_VDD_MUX

+1.8V_RUN +VDDA18PCIE

220 ohm @ 100MHz, 2A

U6

U6

3

GND1
IN
EN

*TPS72501_NC

*TPS72501_NC

OUT

RESET#/FB

GND2

2
1

VSSAPCIE10

VSSAPCIE11

VSSAPCIE12

VSSAPCIE13

VSSAPCIE14

VSSAPCIE15

VSSAPCIE16

VSSAPCIE17

VSSAPCIE18

VSSAHT4

VSSAHT5

VSSAHT6

VSSAHT7

VSSAHT8

VSSAHT9

VSSAHT10

VSSAHT11

VSSAHT12

VSSAHT13

VSSAHT14

VSSAHT15

VSSAHT16

VSSAHT17

VSSAHT18

J22

L17

L22

L24

L25

H19

G24

G25

+1.2V_RUN +VDDHTTX

+1.35V_HT_VCC

BLM21PG221SN1D

BLM21PG221SN1D

0805

0805

4
5
6

P20

N22

R19

R22

R24

M20

R80

R80

0/0805

0/0805

BLM21PG221SN1D

BLM21PG221SN1D

*BLM21PG221SN1D_NC

*BLM21PG221SN1D_NC

L4

L4

80 ohm(4A)

BLM21PG221SN1D

BLM21PG221SN1D

0805

0805

220 ohm @ 100MHz, 2A

L71

L71

0805

0805

L12

L12

0805

0805

C26

C26

4.7U

4.7U

6.3

6.3
X5R

X5R
0603

0603

+1.35V_HT_VCC

R59

R59
*12.7K_NC

*12.7K_NC

R60

R60
*120K_NC

*120K_NC

R25

L22

L22

VSSAPCIE19

VSSAPCIE20

VSSAPCIE21

VSSAPCIE22

VSSAHT19

VSSAHT21

VSSAHT22

VSSAHT20

V19

U22

H20

W22

C636

C636

4.7U

4.7U

6.3

6.3
X5R

X5R
0603

0603

C27

C27

4.7U

4.7U

6.3

6.3
X5R

X5R
0603

0603

C82

C82
*1U_NC

*1U_NC

VSSAPCIE23

VSSAPCIE24

VSSAPCIE25

VSSAPCIE26

VSSAHT23

VSSAHT24

VSSAHT25

VSSAHT26

Y21

W24

W25

AD25

+VDDHTRX

VSSAPCIE27

VSSAPCIE28

VSSAPCIE29

VSSAHT27

VSS11

L12

C12

C12

4.7U

4.7U

6.3

6.3
X5R

X5R
0603

0603

C76

C76

4.7U

4.7U

6.3

6.3
X5R

X5R
0603

0603

C55

C55

0.1U

0.1U

16

16
X7R

X7R

C32

C32

0.1U

0.1U

16

16
X7R

X7R

+1.8V_RUN

AC3

VSSAPCIE30

VSSAPCIE31

VSSAPCIE32

VSSAPCIE33

VSSAPCIE34

VSSAPCIE35

GROUND

GROUND

VSS12

VSS13

VSS14

VSS15

VSS16

VSS17

T12

P12

P15

N13

R11

R14

M14

C59

C59

0.1U

0.1U

16

16
X7R

X7R

C77

C77

0.1U

0.1U

16

16
X7R

X7R

C66

C66

0.1U

0.1U

16

16
X7R

X7R

40mil Width

C25

C25

0.1U

0.1U

16

16
X7R

X7R

R424

R424

0/0805

0/0805

AC4

AE1

AE4

AB2

VSSAPCIE36

VSSAPCIE37

VSSAPCIE38

VSSAPCIE39

VSSAPCIE40

VSS18

VSS19

VSS20

VSS21

VSS22

V12

U14

U11

U15

C58

C58

0.1U

0.1U

16

16
X7R

X7R

C78

C78

0.1U

0.1U

16

16
X7R

X7R

C60

C60

0.1U

0.1U

16

16
X7R

X7R

C33

C33

0.1U

0.1U

16

16
X7R

X7R

+1.8V_RUN

+VDD18_MEM

VSS23

VSS24

W11

W15

C24

C24
1U

1U

10

10
X6S

X6S
0603

0603

C592

C592
*1U_NC

*1U_NC

10

10
X6S

X6S
0603

0603

AE14

VSS1

VSS25

AC12

VSS2

VSS26

AA14

C57

C57

0.1U

0.1U

16

16
X7R

X7R

C64

C64

0.1U

0.1U

16

16
X7R

X7R

C67

C67

0.1U

0.1U

16

16
X7R

X7R

C30

C30

0.1U

0.1U

16

16
X7R

X7R

VDDHTRX
VDDHTTX
VDDA18PCIE

VDD18_MEM
VDDPCIE
VDDC
VDD_MEM
VDDG33

***：Depopulate for RX780.

A6

VDDPCIE_1

B6

VDDPCIE_2

C6

VDDPCIE_3

D6

VDDPCIE_4

E6

VDDPCIE_5

F6

VDDPCIE_6

G7

VDDPCIE_7

H8

VDDPCIE_8

J9

VDDPCIE_9

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8

VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22

K9
M9
L9
P9
R9
T9
V9
U9

K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16

AE10
AA11
Y11
AD10
AB10
AC10

H11
H12

VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17

POWER

POWER

VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)

VDDG33_1(NC)
VDDG33_2(NC)

Work around for RS780 Rev.A11 errata.

5

4

3

RX780

+1.1V
+1.1V
+1.2V
+1.8V
+1.8VVDDG18
NC
+1.1V +1.1V
+1.1V
NC
NC

C28

C28

0.1U

0.1U

16

16
X7R

X7R

C29

C29

0.1U

0.1U

10

10
X7R

X7R

80mil Width

C380C38
0

20mil Width

C45

C45

0.1U

0.1U

16

16
X7R

X7R

RS780

+1.1V
+1.1V
+1.2V
+1.8V
+1.8V
+1.8V

+1.1V

+1.8V/1.5V
DDR2/DDR3

+3.3V

100 mil Width

C17

C17

C23

C23

1U

1U

0.1U

0.1U

10

10
X6S

X6S

16

16

0603

0603

X7R

X7R

C9

C9

C10

C10

10U

10U

10U

10U

4

4

4

4

X6S

X6S

X6S

X6S

0805

0805

0805

0805

C39

C39

C43

C43

0.1U

0.1U

0.1U

0.1U

10

10

10

10

X7R

X7R

X7R

X7R

C36

C36

C37

C37

*0.1U_NC

*0.1U_NC

*0.1U_NC

*0.1U_NC

16

16

16

16

X7R

X7R

X7R

X7R

+3.3V_VDDR

BLM15AG221SN1D

BLM15AG221SN1D

C31

C31

0.1U

0.1U

16

16
X7R

X7R

2

VDD_PCIE

C18

C18

C22

C22

BLM21PG221SN1D

1U

1U

10

10
X6S

X6S
0603

0603

C41

C41

0.1U

0.1U

10

10
X7R

X7R

C51

C51

0.1U

0.1U

10

10
X7R

X7R

BLM21PG221SN1D

4.7U

4.7U

6.3

6.3
X5R

X5R
0603

0603

+NB_VCORE

C50

C50

0.1U

0.1U

10

10
X7R

X7R

220 ohm @ 100MHz, 2A

*BLM21PG221SN1D_NC

*BLM21PG221SN1D_NC

C35

C35

C44

C44

*0.1U_NC

*0.1U_NC

*4.7U_NC

*4.7U_NC

6.3

6.3

16

16

X5R

X5R

X7R

X7R

0603

0603

+3.3V_RUN

L2

L2

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

+NB_VDD_MUX

L1

L1

0805

0805

C54

C54

0.1U

0.1U

10

10
X7R

X7R

+1.8V_RUN+1.8V_VDD_MEM

L6

L6

0805

0805

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

RS780-POWER

RS780-POWER

RS780-POWER

FX6 3A

FX6 3A

FX6 3A

1

10 70Tuesday, May 20, 2008

10 70Tuesday, May 20, 2008

10 70Tuesday, May 20, 2008

of

of

of

1

256-Mbit DDR2 16Mbit*16(4bank)

MEM_A0
MEM_A1
MEM_A2

A A

R415 *100_NCR415 *100_NC

L67

+1.8V_MEM_VDDQ

B B

L67
*SBK160808G221_NC

*SBK160808G221_NC

MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11
MEM_A12

MEM_BA0
MEM_BA1

MEM_DM1
MEM_DM0

MEM_RAS#
MEM_CAS#
MEM_WE#
MEM_CS#
MEM_CKE
MEM_ODT
MEM_CLKP

MEM_CLKN

C619

C619
*1U_NC

*1U_NC

10

10
X5R

X5R
0603

0603

Place This CAP near to
SDRAM with 0.2".

C C

+0.9V_MEM_VTT

+

+

C634

C634
*100U_NC

*100U_NC

6.3

6.3
3528

3528

+1.8V_RUN

D D

C88

C88
*22U_NC

*22U_NC

6.3

6.3
X5R

X5R
0805

0805

L62

L62

BLM21PG221SN1D

BLM21PG221SN1D

1.8V_RUN_ENABLE46

+1.8V_MEM_VDDQ

C577

C577
22U

22U

6.3

6.3
X5R

X5R
0805

0805

Local Frame Buffer(64MB) DDRII Power

1

2

U2

U2

M8

A0

M3

A1

M7

A2

N2

A3

N8

A4

N3

A5

N7

A6

P2

A7

P8

A8

P3

A9

M2

A10

P7

A11

R2

A12

L2

BA0

L3

BA1

B3

UDM

F3

LDM

K7

RAS

L7

CAS

K3

WE

L8

CS

K2

CKE

K9

ODT

J8

CLK

K8

CLK#

J1

VDDL

J7

VSSDL

A3

VSS_0

E3

VSS_1

J3

VSS_2

N1

VSS_3

P9

VSS_4

A7

VSSQ_0

B2

VSSQ_1

B8

VSSQ_2

D2

VSSQ_3

D8

VSSQ_4

E7

VSSQ_5

F2

VSSQ_6

F8

VSSQ_7

H2

VSSQ_8

H8

VSSQ_9

*HY5PS561621AFP-25_NC

*HY5PS561621AFP-25_NC

400M PBGA84

400M PBGA84
256M EP

256M EP

Q18

Q18
*BSC032N03S_NC

*BSC032N03S_NC

3
2
1

+

+

C580

C580
330U

330U

6.3

6.3
7343

7343

2

3

Bit
Swap

MEM_DQ6

G8

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

UDQS

UDQS#

LDQS

LDQS#

NC1

NC2

NC3

NC4

NC5

NC6

VREF

VDD_0
VDD_1
VDD_2
VDD_3
VDD_4

VDDQ_0
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9

9
8
7
6
5

4

C602

C602

C596

C596

1U

1U

1U

1U

6.3

6.3

6.3

6.3

X5R

X5R

X5R

X5R

MEM_DQ2

G2

MEM_DQ7

H7

MEM_DQ0

H3

MEM_DQ1

H1

MEM_DQ4

H9

MEM_DQ3

F1

MEM_DQ5

F9

MEM_DQ11

C8

MEM_DQ13

C2

MEM_DQ10

D7

MEM_DQ8

D3

MEM_DQ12

D1

MEM_DQ9

D9

MEM_DQ14

B1

MEM_DQ15

B9

MEM_DQS_P1

B7

MEM_DQS_N1

A8

MEM_DQS_P0

F7

MEM_DQS_N0

E8
A2

E2

MEM_BA2

L1
R3
R7
R8

MEM_VREF

J2

A1
E1
J9
M9
R1

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

+0.9V_DDR_VTT

C595

C595

0.1U

0.1U

10

10
X7R

X7R

+1.8V_MEM_VDDQ

C611

C611

0.1U

0.1U

10

10
X7R

X7R

3

4

+1.8V_MEM_VDDQ

T3T3

R42940.2/F R42940.2/F
R42840.2/F R42840.2/F

MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11
MEM_A12

MEM_BA0
MEM_BA1
MEM_BA2

MEM_RAS#
MEM_CAS#
MEM_WE#
MEM_CS#
MEM_CKE
MEM_ODT

MEM_CLKP
MEM_CLKN

MEM_COMP_P
MEM_COMP_N

AB12
AE16

AE15
AA12
AB16

AB14
AD14
AD13
AD15
AC16

AE13
AC14

AD16

AE17
AD17

W12

AD18

AB13

AB18

W14

AE12
AD12

5

V11

Y14

Y12

V14
V15

U22D

U22D

MEM_A0(NC)
MEM_A1(NC)
MEM_A2(NC)
MEM_A3(NC)
MEM_A4(NC)
MEM_A5(NC)
MEM_A6(NC)
MEM_A7(NC)
MEM_A8(NC)
MEM_A9(NC)
MEM_A10(NC)
MEM_A11(NC)
MEM_A12(NC)
MEM_A13(NC)

MEM_BA0(NC)
MEM_BA1(NC)
MEM_BA2(NC)

MEM_RASb(NC)
MEM_CASb(NC)
MEM_WEb(NC)
MEM_CSb(NC)
MEM_CKE(NC)
MEM_ODT(NC)

MEM_CKP(NC)
MEM_CKN(NC)

MEM_COMPP(NC)
MEM_COMPN(NC)

RS780M A13

RS780M A13

MEM_COMP_P and MEM_COMP_N trace
width >=10mils and 10mils spacing from
other Signals in X,Y,Z directions

Only for RS780

C620

C620
*0.1U_NC

*0.1U_NC

10

10
X7R

X7R

C621

C621
*0.1U_NC

*0.1U_NC

10

10
X7R

X7R

4

R435

R435
*1K/F_NC

*1K/F_NC

R436

R436
*1K/F_NC

*1K/F_NC

MEM_VREF

+1.8V_MEM_VDDQ+1.8V_MEM_VDDQ

C610

C610

0.1U

0.1U

10

10
X7R

X7R

C603

C603

0.1U

0.1U

10

10
X7R

X7R

5

PAR 4 OF 6

PAR 4 OF 6

MEM_DQ0/DVO_VSYNC(NC)

MEM_DQ1/DVO_HSYNC(NC)

MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)

SBD_MEM/DVO_I/F

SBD_MEM/DVO_I/F

R432

R432
1K/F

1K/F

MEM_VREF1

R431

R431
1K/F

1K/F

6

7

8

RS740/RX780/RS780 POWER DIFFERENCE TABLE

MEM_DQ2/DVO_DE(NC)

MEM_DQ3/DVO_D0(NC)

MEM_DQ4(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)

MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)

MEM_DQ12(NC)

MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)

MEM_DQS1P(NC)
MEM_DQS1N(NC)

MEM_DM0(NC)

MEM_DM1/DVO_D8(NC)

IOPLLVDD18(NC)

IOPLLVDD(NC)
IOPLLVSS(NC)

MEM_VREF(NC)

AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21

Y17
W18
AD20
AE21

W17
AE19

AE23
AE24

AD23
AE18

MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ8
MEM_DQ9
MEM_DQ10
MEM_DQ11
MEM_DQ12
MEM_DQ13
MEM_DQ14
MEM_DQ15

MEM_DQS_P0
MEM_DQS_N0
MEM_DQS_P1
MEM_DQS_N1

MEM_DM0
MEM_DM1

+1.8V_IOPLLVDD
+1.1V_IOPLLVDD

MEM_VREF1

PIN NAME
IOPLLVDD18 NC +1.8V
IOPLLVDD NC +1.1V

RX780 RS780

220 ohm @ 100MHz

L660L66

0
0

L690L69

C618

C618

C626

C626

*2.2U_NC

*2.2U_NC

10

10
0603

0603
X7R

X7R

*2.2U_NC

*2.2U_NC

10

10
X5R

X5R
0603

0603

ALL external components connected to
SPMEM signals must be removed for RX780.

At least 200mils wide and locate after DDR2 SDRAM

MEM_A8

RP23 *4P2R-47_NCRP23 *4P2R-47_NC

MEM_A0

MEM_A2
MEM_A6

MEM_A7
MEM_A9

MEM_A11
MEM_A4

MEM_BA0
MEM_BA2

MEM_A10
MEM_A5

MEM_BA1
MEM_A1

MEM_A12
MEM_A3

MEM_CS#
MEM_ODT

MEM_CAS#
MEM_RAS#

MEM_CKE
MEM_WE#

6

4
2

4
2

RP26 *4P2R-47_NCRP26 *4P2R-47_NC

4
2

RP24 *4P2R-47_NCRP24 *4P2R-47_NC

4
2

RP29 *4P2R-47_NCRP29 *4P2R-47_NC

4
2

RP31 *4P2R-47_NCRP31 *4P2R-47_NC

4
2

RP30 *4P2R-47_NCRP30 *4P2R-47_NC

4
2

RP27 *4P2R-47_NCRP27 *4P2R-47_NC

4
2

4
2

RP22 *4P2R-47_NCRP22 *4P2R-47_NC

4
2

RP28 *4P2R-47_NCRP28 *4P2R-47_NC

4
2

+0.9V_MEM_VTT

3
1

3
1

3
1

3
1

3
1

3
1

3
1

3
1

3
1

3
1

3
1

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

C628 *0.1U/10V_NCC628 *0.1U/10V_NC
C587 *0.1U/10V_NCC587 *0.1U/10V_NC
C586 *0.1U/10V_NCC586 *0.1U/10V_NCRP25 *4P2R-47_NCRP25 *4P2R-47_NC
C589 *0.1U/10V_NCC589 *0.1U/10V_NC

C629 *0.1U/10V_NCC629 *0.1U/10V_NC
C599 *0.1U/10V_NCC599 *0.1U/10V_NC

C608 *0.1U/10V_NCC608 *0.1U/10V_NC

C605 *0.1U/10V_NCC605 *0.1U/10V_NC

C616 *0.1U/10V_NCC616 *0.1U/10V_NC
C594 *0.1U/10V_NCC594 *0.1U/10V_NCRP21 *4P2R-47_NCRP21 *4P2R-47_NC
C630 *0.1U/10V_NCC630 *0.1U/10V_NC
C627 *0.1U/10V_NCC627 *0.1U/10V_NC

C588 *0.1U/10V_NCC588 *0.1U/10V_NC

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

RS780-SIDE PORT I/O

RS780-SIDE PORT I/O

RS780-SIDE PORT I/O

FX6 3A

FX6 3A

FX6 3A

7

+1.8V_MEM_VDDQ

+1.8V_MEM_VDDQ

+1.8V_MEM_VDDQ

+1.8V_MEM_VDDQ

+1.8V_MEM_VDDQ

+1.8V_MEM_VDDQ

11 70Tuesday, May 20, 2008

11 70Tuesday, May 20, 2008

11 70Tuesday, May 20, 2008

8

+1.8V_RUN
+NB_VDD_MUX

of

of

of

5

PLACE THESE PCIE AC COUPLING
CAPS CLOSE TO U39

PLTRST#9,14,18,37,39,45

ALINK_NBRX_SBTX_P08

Reserved for Rubuto.

J6

J6

PLTRST#

2

2

1

D D

C C

CPU_PWRGD

B B

A A

1

*3800/2/1_NC

*3800/2/1_NC

Place R686,R683
< 100mils from pins E27,E28,E29

+1.2V_RUN

+5V_ALW2 +3.3V_ALW

(20)

R378 *0_NCR378 *0_NC

Place the translation circuit for CPU_PWRGD close to the
SB700 to minimize stubbs when the circuit is No Stuff.

PLACE THESE COMPONENTS CLOSE TO SB700, AND
USE GROUND GUARD FOR 32K_X1 AND 32K_X2

ATi Recommend
Vendor: NSK
Part Number: NXG 32.768KAE12FUD 16 PPM.

R698

R698
*20M_NC

*20M_NC

+3.3V_RUN

PCI_GNT4#
PCI_REQ4#

Y6

Y6

32.768KHZ

32.768KHZ
R709 20MR709 20M

C895

C895
18P

18P

50

50
COG

COG

R271

R271
*1K_NC

*1K_NC

C374

C374
*0.1U_NC

*0.1U_NC

2

8
7
6
5

*AT24C04N-10SI-2.7_NC

*AT24C04N-10SI-2.7_NC

5

BLM21PG221SN1D

BLM21PG221SN1D

0805

0805

R374

R374
*10K_NC

*10K_NC

3

Q57

Q57
*FDV301N_NC

*FDV301N_NC

1

R701 0R701 0

14
23

C902

C902
18P

18P

50

50
COG

COG

VCC
WC
SCL
SDA

L47

L47

2

U18

U18

1

A0

2

A1

3

A2

4

GND

ALINK_NBRX_SBTX_N08

ALINK_NBRX_SBTX_P18

ALINK_NBRX_SBTX_N18

ALINK_NBRX_SBTX_P28

ALINK_NBRX_SBTX_N28

ALINK_NBRX_SBTX_P38

ALINK_NBRX_SBTX_N38

ALINK_NBTX_C_SBRX_P08
ALINK_NBTX_C_SBRX_N08
ALINK_NBTX_C_SBRX_P18
ALINK_NBTX_C_SBRX_N18
ALINK_NBTX_C_SBRX_P28
ALINK_NBTX_C_SBRX_N28
ALINK_NBTX_C_SBRX_P38
ALINK_NBTX_C_SBRX_N38

+1.2V_PCIE_PVDD_R

20mil Width

R375

R375
*10K_NC

*10K_NC

31

Q56

Q56

*2N7002W-7-F_NC

*2N7002W-7-F_NC

32K_X1

32K_X2

+1.2V_PCIE_VDDR

C446 AND C448 CLOSE
TO U31.P24

CLK_PCIE_SB25
CLK_PCIE_SB#25

CPU_PWRGD_Q 42

ALLOW_LDTSTOP9
CPU_PROCHOT#5
CPU_PWRGD5

LDT_STOP#5,9

LDT_RST#5,9

4

PLTRST#

C411 0.1U/10VC411 0.1U/10V
C408 0.1U/10VC408 0.1U/10V
C874 0.1U/10VC874 0.1U/10V
C877

C877
C884

C884
C881 0.1U/10VC881 0.1U/10V
C425 0.1U/10VC425 0.1U/10V
C415 0.1U/10VC415 0.1U/10V

R686 562/FR686 562/F
R683 2.05K/FR683 2.05K/F

4

R678 *8.2K_NCR678 *8.2K_NC

R679 33R679 33

ALINK_NBRX_C_SBTX_P0
ALINK_NBRX_C_SBTX_N0
ALINK_NBRX_C_SBTX_P1

0.1U/10V

0.1U/10V

ALINK_NBRX_C_SBTX_N1
ALINK_NBRX_C_SBTX_P2

0.1U/10V

0.1U/10V

ALINK_NBRX_C_SBTX_N2
ALINK_NBRX_C_SBTX_P3
ALINK_NBRX_C_SBTX_N3

C446

C446
10U

10U

4

4
X5R

X5R
0603

0603

R316 0R316 0

+1.8V_RUN

PCIE_CALRP
PCIE_CALRN

C448

C448
1U

1U

6.3

6.3
X5R

X5R

R338

R338
*10K_NC

*10K_NC

R344 0R344 0
R333 0R333 0

32K_X1

32K_X2

U39A

U39A

N2

A_RST#

V23

PCIE_TX0P

V22

PCIE_TX0N

V24

PCIE_TX1P

V25

PCIE_TX1N

U25

PCIE_TX2P

U24

PCIE_TX2N

T23

PCIE_TX3P

T22

PCIE_TX3N

U22

PCIE_RX0P

U21

PCIE_RX0N

U19

PCIE_RX1P

V19

PCIE_RX1N

R20

PCIE_RX2P

R21

PCIE_RX2N

R18

PCIE_RX3P

R17

PCIE_RX3N

T25

PCIE_CALRP

T24

PCIE_CALRN

P24

PCIE_PVDD

P25

PCIE_PVSS

N25

PCIE_RCLKP/NB_LNK_CLKP

N24

PCIE_RCLKN/NB_LNK_CLKN

K23

NB_DISP_CLKP

K22

NB_DISP_CLKN

M24

NB_HT_CLKP

M25

NB_HT_CLKN

P17

CPU_HT_CLKP

M18

CPU_HT_CLKN

M23

SLT_GFX_CLKP

M22

SLT_GFX_CLKN

J19

GPP_CLK0P

J18

GPP_CLK0N

L20

GPP_CLK1P

L19

GPP_CLK1N

M19

GPP_CLK2P

M20

GPP_CLK2N

N22

GPP_CLK3P

P22

GPP_CLK3N

L18

25M_48M_66M_OSC

J21

25M_X1

J20

25M_X2

A3

X1

B3

X2

F23

ALLOW_LDTSTP

F24

PROCHOT#

F22

LDT_PG

G25

LDT_STP#

G24

LDT_RST#

SB700 A12

SB700 A12

3

SB700

SB700

Part 1 of 5

Part 1 of 5

PCI EXPRESS INTERFACE

PCI EXPRESS INTERFACE

LPC

3

CPU

CPU

LPC

RTC

RTC

RTC XTAL

RTC XTAL

PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4

PCICLK5/GPIO41

PCI CLKS

PCI CLKS

PCIRST#

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8

AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

CBE0#
CBE1#
CBE2#

PCI INTERFACE

PCI INTERFACE

CLOCK GENERATOR

CLOCK GENERATOR

LDRQ1#/GNT5#/GPIO68

BMREQ#/REQ5#/GPIO65

CBE3#

FRAME#

DEVSEL#

IRDY#

TRDY#

PAR

STOP#
PERR#
SERR#
REQ0#
REQ1#
REQ2#

REQ3#/GPIO70
REQ4#/GPIO71

GNT0#
GNT1#
GNT2#

GNT3#/GPIO72
GNT4#/GPIO73

CLKRUN#

LOCK#

INTE#/GPIO33
INTF#/GPIO34
INTG#/GPIO35
INTH#/GPIO36

LPCCLK0
LPCCLK1

LAD0
LAD1
LAD2
LAD3

LFRAME#

LDRQ0#

SERIRQ

RTCCLK

INTRUDER_ALERT#

VBAT

Rev.A21

2

PCI_CLK0_R

P4

PCI_CLK1_R

P3

PCI_CLK2

P1

PCI_CLK3

P2

PCI_CLK4_R

T4

PCI_CLK5

T3

R682 *8.2K_NCR682 *8.2K_NC

N1

U2
P7
V4
T1
V3
U1
V1
V2
T2
W1
T9
R6
R7
R5
U8
U5
Y7
W8
V9
Y8
AA8
Y4
Y3
Y2
AA2
AB4
AA1
AB3
AB2
AC1
AC2
AD1
W2
U7
AA7
Y1
AA6
W5
AA5
Y5
U6
W6
W4
V7
AC3
AD4
AB7
AE6
AB6
AD2
AE4
AD5
AC6
AE5
AD6
V5

AD3
AC4
AE2
AE3

G22
E22
H24
H23
J25
J24
H25
H22
AB8
AD7
V15

C3
C2
B2

R680 33R680 33

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_FRAME#
PCI_DEVSEL#
PCI_IRDY#
PCI_TRDY#
PCI_PAR
PCI_STOP#
PCI_PERR#
PCI_SERR#
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#
PCI_REQ4#
PCI_GNT0#
PCI_GNT1#
PCI_GNT2#
PCI_GNT3#
PCI_GNT4#
CLKRUN#
LOCK#

PCI_PIRQA#
PCI_PIRQB#

R329 22R329 22
R340 22R340 22

LPC_LAD0LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
LPC_LDRQ0#
LPC_LDRQ1#

IRQ_SERIRQ

INTRUDER_ALERT# INTRUDER_ALERT#
+VBAT_IN

C893

C893

C894

C894

0.1U/16V

0.1U/16V

1U

1U

16

16

10

10

X7R

X7R

X6S

X6S
0603

0603

R309 22R309 22
R301 22R301 22

T73T73

R303 22R303 22

PCI_AD[0..31]

PCI_C_BE0# 35
PCI_C_BE1# 35
PCI_C_BE2# 35
PCI_C_BE3# 35
PCI_FRAME# 35
PCI_DEVSEL# 35
PCI_IRDY# 35
PCI_TRDY# 35
PCI_PAR 35
PCI_STOP# 35
PCI_PERR# 35
PCI_SERR# 35

T110T110

PCI_REQ1# 35

T107T107
T108T108

T66T66
T120T120

PCI_GNT1# 35

T113T113

T132T132
T57T57

CLKRUN# 35,42

T72T72

PCI_PIRQA# 35

PCI_PIRQB# 35

T131T131

LPCCLK0 14

LPCCLK1 14

LPC_LAD0 39,42

LPC_LAD1 39,42

LPC_LAD2 39,42

LPC_LAD3 39,42

LPC_LFRAME# 39,42

T77T77
T67T67

IRQ_SERIRQ 35,42

RTC_CLK 14

R708

R708
*0_NC

*0_NC

CMOS Clear
(Top or easy access place)

2

CLK_PCI_DEBUG
CLK_PCI_PCCARD

CLK_PCI_8512

PCI_AD[0..31] 35

R695 510/FR695 510/F

CLK_PCI_DEBUG 39
CLK_PCI_PCCARD 35
PCI_CLK2 14
PCI_CLK3 14
CLK_PCI_8512 14,42
PCI_CLK5 14

PCI_RST# 35

CLK_PCI_DEBUG
CLK_PCI_8512
CLK_PCI_PCCARD

PCI_REQ4#
PCI_REQ2#

PCI_REQ3#

+3.3V_RUN

+RTC_CELL

Title

Title

Title

SB700-PCIE/PCI/LPC

SB700-PCIE/PCI/LPC

SB700-PCIE/PCI/LPC

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

FX6 3A

FX6 3A

FX6 3A

Date: Sheet

Date: Sheet

Date: Sheet

6
7
8
9

10

Option to "Disable" clkrun.
Pulling it down will
keep the clocks running.

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

1

C445 *10P/50V_NCC445 *10P/50V_NC
C431 *10P/50V_NCC431 *10P/50V_NC
C406 10P/50VC406 10P/50V

1

+3.3V_RUN

5
4
3
2
1

+3.3V_RUN

R670

R670

8.2K

8.2K

R671

R671
*8.2K_NC

*8.2K_NC

R694

R694

PCI_REQ0#
PCI_REQ1#

*1M_NC

*1M_NC

12 70Tuesday, May 20, 2008

12 70Tuesday, May 20, 2008

12 70Tuesday, May 20, 2008

RP33

RP33

*10P8R-8.2k_NC

*10P8R-8.2k_NC

CLKRUN#

+RTC_CELL

of

of

of

5

+3.3V_ALW

R321 *2.2K_NCR321 *2.2K_NC
R322 *2.2K_NCR322 *2.2K_NC
R326 *2.2K_NCR326 *2.2K_NC

D D

+3.3V_SUS

R343 *10K_NCR343 *10K_NC
R364 *10K_NCR364 *10K_NC
R700 *10K_NCR700 *10K_NC
R703 *10K_NCR703 *10K_NC

R704 *10K_NCR704 *10K_NC

+3.3V_SUS

R693 *10K_NCR693 *10K_NC
R690 *10K_NCR690 *10K_NC
R318 *10K_NCR318 *10K_NC

C C

B B

A A

R331 *10K_NCR331 *10K_NC

R335 *10K_NCR335 *10K_NC
R691 *10K_NCR691 *10K_NC

R689 10KR689 10K
R317 *10K_NCR317 *10K_NC

+3.3V_RUN

R299 *10K_NCR299 *10K_NC
R668 2.2KR668 2.2K
R669 2.2KR669 2.2K

R787 *10K_NCR787 *10K_NC
R788 *10K_NCR788 *10K_NC

R311 *10K_NCR311 *10K_NC

CLK_SB_48M_R

R367

R367
*10_NC

*10_NC

C498

C498
*4.7P_NC

*4.7P_NC

50

50
NPO

NPO

SB_AZ_CODEC_SDOUT31
SB_AZ_CODEC_SYNC31

SB_AZ_CODEC_RST#14,31,42

SB_AZ_CODEC_BITCLK31

Close to U39

SB_TEST2
SB_TEST1
SB_TEST0

USB_OC0_1#
USB_OC2_3#
USB_OC6#
USB_OC4#

EXPRCRD_PWREN#

SIO_EXT_WAKE#42

SB_PCIE_WAKE#33,37,39,40

CPU_THERMTRIP#5

Delay 20ms after S5 powerOK

SATA_DET#
SIO_EXT_SMI#
SIO_EXT_SCI#
SB_PME#

SB_PCIE_WAKE#
SIO_EXT_WAKE#

SYS_RESET#
CPU_THERMTRIP#

SHUTDOWN#/GPIO5
SB_SMBCLK
SB_SMBDATA

EXPRCRD_PWREN#37,42

USB_OC2_3#38
USB_OC0_1#38

SB_AZ_CODEC_SDIN031

SB_AZ_CODEC_SDIN0
SB_AZ_CODEC_BITCLK

USB_OC2_3#
USB_OC0_1#

Close to SB.(~50 mils from
clock pin).

C463 *27P/50V_NCC463 *27P/50V_NC

SB_AZ_CODEC_SDOUT
SB_AZ_CODEC_SYNC

SB_AZ_CODEC_RST#
SB_AZ_CODEC_BITCLK

5

C886 *27P/50V_NCC886 *27P/50V_NC

R685 33R685 33
R315 33R315 33

R313 33R313 33
R687 33R687 33

C888 *27P/50V_NCC888 *27P/50V_NC
C457 *27P/50V_NCC457 *27P/50V_NC

SB_PME#35,42

SIO_SLP_S3#42

SIO_SLP_S5#42

SIO_PWRBTN#42

SB_PWRGD5,45

SUS_STAT#9

SIO_A20GATE42
SIO_RCIN#42

SIO_EXT_SCI#42

SIO_EXT_SMI#42

WD_PWRGD45

SB_RSMRST#42

SB_SMBCLK16,37,39,40
SB_SMBDATA16,37,39,40

THERM_ALERT#29

SPKR31

R365 0R365 0
R337 0R337 0

SB_AZ_SDOUT
SB_AZ_SYNC

SB_AZ_RST#
SB_AZ_BITCLK

4

R366 0R366 0
R330 0R330 0

4

T127T127
T128T128

SB_AZ_CODEC_SDIN0

SB_PME#
SIO_EXT_WAKE#

SIO_SLP_S3#
SIO_SLP_S5#
SIO_PWRBTN#

SUS_STAT#
SB_TEST2
SB_TEST1
SB_TEST0
SIO_A20GATE

SIO_EXT_SCI#

SYS_RESET#
SB_PCIE_WAKE#
SIO_EXT_SMI#SIO_EXT_SMI#

SB_RSMRST#

SPKR
SB_SMBCLK
SB_SMBDATA

SATA_DET#
SHUTDOWN#/GPIO5

USB_OC6#
EXPRCRD_PWREN#
USB_OC4#
JTAG_TDO
JTAG_TCK
JTAG_TDI
SB_JTAG_RST#

SB_AZ_BITCLK
SB_AZ_SDOUT

SB_AZ_SYNC
SB_AZ_RST#SB_AZ_RST#

U39D

U39D

E1

PCI_PME#/GEVENT4#

E2

RI#/EXTEVNT0#

H7

SLP_S2/GPM9#

F5

SLP_S3#

G1

SLP_S5#

H2

PWR_BTN#

H1

PWR_GOOD

K3

SUS_STAT#

H5

TEST2

H4

TEST1

H3

TEST0

Y15

GA20IN/GEVENT0#

W15

KBRST#/GEVENT1#

K4

LPC_PME#/GEVENT3#

K24

LPC_SMI#/EXTEVNT1#

F1

S3_STATE/GEVENT5#

J2

SYS_RESET#/GPM7#

H6

WAKE#/GEVENT8#

F2

BLINK/GPM6#

J6

SMBALERT#/THRMTRIP#/GEVENT2#

W14

NB_PWRGD

D3

RSMRST#

AE18

SATA_IS0#/GPIO10

AD18

CLK_REQ3#/SATA_IS1#/GPIO6

AA19

SMARTVOLT/SATA_IS2#/GPIO4

W17

CLK_REQ0#/SATA_IS3#/GPIO0

V17

CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39

W20

CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40

W21

SPKR/GPIO2

AA18

SCL0/GPOC0#

W18

SDA0/GPOC1#

K1

SCL1/GPOC2#

K2

SDA1/GPOC3#

AA20

DDC1_SCL/GPIO9

Y18

DDC1_SDA/GPIO8

C1

LLB#/GPIO66

Y19

SHUTDOWN#/GPIO5

G5

DDR3_RST#/GEVENT7#

B9

USB_OC6#/IR_TX1/GEVENT6#

B8

USB_OC5#/IR_TX0/GPM5#

A8

USB_OC4#/IR_RX0/GPM4#

A9

USB_OC3#/IR_RX1/GPM3#

E5

USB_OC2#/GPM2#

F8

USB_OC1#/GPM1#

E4

USB_OC0#/GPM0#

M1

AZ_BITCLK

M2

AZ_SDOUT

J7

AZ_SDIN0/GPIO42

J8

AZ_SDIN1/GPIO43

L8

AZ_SDIN2/GPIO44

M3

AZ_SDIN3/GPIO46

L6

AZ_SYNC

M4

AZ_RST#

L5

AZ_DOCK_RST#/GPM8#

H19

PS2_DAT/EC_GPIO0

H20

PS2_CLK/EC_GPIO1

H21

SPI_CS2#/EC_GPIO2

F25

IDE_RST#/F_RST#/EC_GPO3

D22

PS2KB_DAT/EC_GPIO4

E24

PS2KB_CLK/EC_GPIO5

E25

PS2M_DAT/EC_GPIO6

D23

PS2M_CLK/EC_GPIO7

SB700 A12

SB700 A12

3

SB700

SB700

ACPI / WAKE UP EVENTS

ACPI / WAKE UP EVENTS

USB OC

USB OC

HD AUDIO

HD AUDIO

EMBEDDED CTRL

EMBEDDED CTRL

3

Part 4 of 5

Part 4 of 5

USBCLK/14M_25M_48M_OSC

USB_RCOMP

USB MISC

USB MISC

USB_FSDP13+
USB_FSDM13-

USB_FSDP12+
USB_FSDM12-

USB 1.1

USB 1.1

USB_HSDP11+
USB_HSDM11-

USB_HSDP10+
USB_HSDM10-

USB_HSDP9+

USB_HSDM9-

USB_HSDP8+

USB_HSDM8-

USB_HSDP7+

USB_HSDM7-

USB_HSDP6+

USB_HSDM6-

USB_HSDP5+

USB_HSDM5-

USB_HSDP4+

USB 2.0

USB 2.0

USB_HSDM4-

GPIO

GPIO

USB_HSDP3+

USB_HSDM3-

USB_HSDP2+

USB_HSDM2-

USB_HSDP1+

USB_HSDM1-

USB_HSDP0+

USB_HSDM0-

KSO_16/EC_GPIO8
KSO_17/EC_GPIO9

EC_PWM0/EC_GPIO10

SCL2/EC_GPIO11

SDA2/EC_GPIO12
SCL3_LV/EC_GPIO13
SDA3_LV/EC_GPIO14

EC_PWM1/EC_GPIO15

EC_PWM2/EC_GPO16
EC_PWM3/EC_GPO17

KSI_0/EC_GPIO18
KSI_1/EC_GPIO19
KSI_2/EC_GPIO20
KSI_3/EC_GPIO21
KSI_4/EC_GPIO22
KSI_5/EC_GPIO23
KSI_6/EC_GPIO24
KSI_7/EC_GPIO25

KSO_0/EC_GPIO26
KSO_1/EC_GPIO27
KSO_2/EC_GPIO28
KSO_3/EC_GPIO29
KSO_4/EC_GPIO30
KSO_5/EC_GPIO31
KSO_6/EC_GPIO32
KSO_7/EC_GPIO33
KSO_8/EC_GPIO34
KSO_9/EC_GPIO35

KSO_10/EC_GPIO36

EMBEDDED CTRL

EMBEDDED CTRL

KSO_11/EC_GPIO37
KSO_12/EC_GPIO38
KSO_13/EC_GPIO39
KSO_14/EC_GPIO40
KSO_15/EC_GPIO41

Rev.A21

2

When External Clock Gen, used as 48M Clock input
When Internal Clock Gen, used as 48M Clock output

C8
G8

E6
E7

F7
E8

H11
J10

E11
F11

A11
B11

C10
D10

G11
H12

E12
E14

C12
D12

B12
A12

G12
G14

H14
H15

A13
B13

B14
A14

A18
B18
F21
D21
F19
E20
E21
E19
D19
E18

G20
G21
D25
D24
C25
C24
B25
C23

B24
B23
A23
C22
A22
B22
B21
A21
D20
C20
A20
B20
B19
A19
D18
C18

CLK_SB_48M_R
USB_RCOMP

STRAP pin to define
use LPC or SPI ROM

R699 0R699 0
R323 11.8K/FR323 11.8K/F

SB_USBP11+ 32
SB_USBP11- 32

SB_USBP10+ 44
SB_USBP10- 44

SB_USBP7+ 37
SB_USBP7- 37

SB_USBP6+ 39
SB_USBP6- 39

SB_USBP5+ 40
SB_USBP5- 40

SB_USBP4+ 39
SB_USBP4- 39

SB_USBP3+ 38
SB_USBP3- 38

SB_USBP2+ 38
SB_USBP2- 38

SB_USBP1+ 38
SB_USBP1- 38

SB_USBP0+ 38
SB_USBP0- 38

SCLK3 5

SDATA3 5

GP16 14
GP17 14

Symbol:
2N7002W-7-F

Camera

Biometric

EXPRESS

WPAN

WWAN

WLAN

IO board

IO board

Left side USB.

Left side USB.

D(3)

G(2)

S(1)

2

1

CLK_SB_48M 25

Place R323 near pin G8. Route it with 10mils
Trace width and 25mils spacing to any
signals in X, Y, Z directions.

SB JTAG

SB_TEST1
JTAG_TDI
JTAG_TDO
JTAG_TCK

+3.3V_SUS

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

COMPUTER

SB700-ACPI/USB/AC97

SB700-ACPI/USB/AC97

SB700-ACPI/USB/AC97

FX6 3A

FX6 3A

FX6 3A

1

T76T76
T78T78
T129T129
T81T81
T84T84
T111T111

TMS
TDI
TDO
TCK
GND
+3.3V

of

of

of

13 70Tuesday, May 20, 2008

13 70Tuesday, May 20, 2008

13 70Tuesday, May 20, 2008

5

R662

R662
10M

10M

C404

C404
1U

1U

6.3

6.3
X5R

X5R

C402

C402
1U

1U

10

10
X6S

X6S
0603

0603

SATA_TX0+_C
SATA_TX0-_C

SATA_TX1+_C
SATA_TX1-_C

SATA_CAL
SATA_X1
SATA_X2

SATA_X1

SATA_X2

C403

C403
*0.1U_NC

*0.1U_NC

10

10
X7R

X7R

C424

C424
*0.1U_NC

*0.1U_NC

10

10
X7R

X7R

LPC_CLK0

ENABLE PCI
MEM BOOT

DISABLE PCI
MEM BOOT

C401

C401
22U

22U

6.3

6.3
X5R

X5R
0805

0805

SATA_TX0+30

HDD

ODD

D D

ESATA

C C

C860 12P/50V/COGC860 12P/50V/COG

C859 12P/50V/COGC859 12P/50V/COG

+1.2V_RUN

B B

+3.3V_RUN

SATA_TX0-30
SATA_RX0-30

SATA_RX0+30

SATA_TX1+30

SATA_TX1-30
SATA_RX1-30

SATA_RX1+30

SATA_TX3+_C38
SATA_TX3-_C38

SATA_RX3-38
SATA_RX3+38

SATA_ACT#44

L45

L45

BLM15AG221SN1D

BLM15AG221SN1D

CAPS CLOSE TO THE
BALL OF U39

L46

L46

BLM15AG221SN1D

BLM15AG221SN1D

CAPS CLOSE TO THE
BALL OF U39

PCI_CLK2

A A

PULL
HIGH

PULL
LOW

BOOTFAIL
TIMER
ENABLED

BOOTFAIL
TIMER
DISABLED

DEFAULT

C853 0.01U/16VC853 0.01U/16V
C854 0.01U/16VC854 0.01U/16V

C856 0.01U/16VC856 0.01U/16V
C855 0.01U/16VC855 0.01U/16V

PLACE SATA AC COUPLING
CAPS CLOSE TO SB700

SATA_TX3+_C
SATA_TX3-_C

R307 1K/FR307 1K/F

+1.2V_PLLVDD_SATA
+3.3V_XTLVDD_SATA

Y5

Y5
25MHz

25MHz

2 1

30PPM

30PPM

SATA_X2_R

R661 0R661 0

+1.2V_PLLVDD_SATA

+3.3V_XTLVDD_SATA

PCI_CLK3

USE
DEBUG
STRAPS

IGNORE
DEBUG
STRAPS

DEFAULT DEFAULT DEFAULT

5

U39B

U39B

AD9

SATA_TX0+

AE9

SATA_TX0-

AB10

SATA_RX0-

AC10

SATA_RX0+

AE10

SATA_TX1+

AD10

SATA_TX1-

AD11

SATA_RX1-

AE11

SATA_RX1+

AB12

SATA_TX2+

AC12

SATA_TX2-

AE12

SATA_RX2-

AD12

SATA_RX2+

AD13

SATA_TX3+

AE13

SATA_TX3-

AB14

SATA_RX3-

AC14

SATA_RX3+

AE14

SATA_TX4+

AD14

SATA_TX4-

AD15

SATA_RX4-

AE15

SATA_RX4+

AB16

SATA_TX5+

AC16

SATA_TX5-

AE16

SATA_RX5-

AD16

SATA_RX5+

V12

SATA_CAL

Y12

SATA_X1

AA12

SATA_X2

W11

SATA_ACT#/GPIO67

AA11

PLLVDD_SATA_1

W12

XTLVDD_SATA

SB700 A12

SB700 A12

LPC_CLK1

CLKGEN
ENABLED

CLKGEN
DISABLED

RTC_CLK

INTERNAL
RTC

DEFAULT

EXT. RTC

(PD on X1,
apply
32KHz to
RTC_CLK)

4

SB700

SB700

Part 2 of 5

Part 2 of 5

SPI ROM

SPI ROM

SATA PWR SERIAL ATA

SATA PWR SERIAL ATA

TEMPIN3/TALERT#/GPIO64

HW MONITOR

HW MONITOR

SB_AZ_CODEC_RST#

EC
ENABLED

EC
DISABLED

DEFAULT

4

IDE_IORDY

IDE_DACK#

IDE_DRQ

IDE_IOR#
IDE_IOW#
IDE_CS1#
IDE_CS3#

IDE_D0/GPIO15
IDE_D1/GPIO16
IDE_D2/GPIO17
IDE_D3/GPIO18
IDE_D4/GPIO19
IDE_D5/GPIO20
IDE_D6/GPIO21
IDE_D7/GPIO22
IDE_D8/GPIO23

ATA 66/100/133

ATA 66/100/133

IDE_D9/GPIO24
IDE_D10/GPIO25
IDE_D11/GPIO26
IDE_D12/GPIO27
IDE_D13/GPIO28
IDE_D14/GPIO29
IDE_D15/GPIO30

SPI_DI/GPIO12

SPI_DO/GPIO11

SPI_CLK/GPIO47

SPI_HOLD#/GPIO31

SPI_CS#/GPIO32

LAN_RST#/GPIO13

ROM_RST#/GPIO14

FANOUT0/GPIO3

FANOUT1/GPIO48
FANOUT2/GPIO49

FANIN0/GPIO50

FANIN1/GPIO51

FANIN2/GPIO52

TEMP_COMM
TEMPIN0/GPIO61
TEMPIN1/GPIO62
TEMPIN2/GPIO63

VIN0/GPIO53
VIN1/GPIO54
VIN2/GPIO55
VIN3/GPIO56
VIN4/GPIO57
VIN5/GPIO58
VIN6/GPIO59
VIN7/GPIO60

IDE_IRQ

IDE_A0
IDE_A1
IDE_A2

AVDD
AVSS

IDE_DIORDY#

AA24

IDE_IRQ

AA25

IDE_DA0

Y22

IDE_DA1

AB23

IDE_DA2

Y23

IDE_DDACK#

AB24

IDE_DDREQ

AD25

IDE_DIOR#

AC25

IDE_DIOW#

AC24

IDE_DCS1#

Y25

IDE_DCS3#

Y24

IDE_DD0

AD24

IDE_DD1

AD23

IDE_DD2

AE22

IDE_DD3

AC22

IDE_DD4

AD21

IDE_DD5

AE20

IDE_DD6

AB20

IDE_DD7

AD19

IDE_DD8

AE19

IDE_DD9

AC20

IDE_DD10

AD20

IDE_DD11

AE21

IDE_DD12

AB22

IDE_DD13

AD22

IDE_DD14

AE23

IDE_DD15

AC23

G6

CAMERA_CBL_DET#

D2
D1
F4
F3

LAN_RST#

U15

SB700_ROM_RST#

J1

WLAN_RADIO_DIS#

M8

PCIE_MCARD1_DET#

M5

USB_MCARD1_DET#

M7

PCIE_MCARD2_DET#

P5

USB_MCARD2_DET#

P8

WPAN_RADIO_DIS_MINI#

R8

TEMP_COMM

C6

PCIE_MCARD3_DET#

B6

USB_MCARD3_DET#

A6

WWAN_RADIO_DIS#

A5
B5

SB_WWAN_PCIE_RST#

A4

SB_WLAN_PCIE_RST#

B4

SB_WPAN_PCIE_RST#

C4

SB_LOM_PCIE_RST#

D4

LBF_ID0

D5

LBF_ID1

D6

LBF_ID2

A7
B7

20mil Width

F6
G7

HWM_AGND TRACE AT
LEAST 10MIL WIDE

GP17

ROM TYPE:
H, H = Reserved

H, L = SPI ROM

L, H = LPC ROM

L, L = FWH ROM

C472

C472

2.2U

2.2U

10

10
X5R

X5R
0603

0603

HWM_AGND

GP16

DEFAULT

3

T124T124
T121T121
T68T68
T65T65
T70T70
T122T122
T60T60
T118T118
T61T61
T126T126
T71T71

T58T58
T115T115
T117T117
T63T63
T114T114
T116T116
T64T64
T123T123
T125T125
T69T69
T119T119
T62T62
T59T59
T56T56
T109T109
T112T112

R688 *0_NCR688 *0_NC

+3.3V_AVDD_HWM

L51

L51

C473

C473

0.1U

0.1U

10

10
X7R

X7R

R324 0R324 0

3

T75T75

T74T74
T79T79

T80T80

+3.3V_SUS

BLM15AG221SN1D

BLM15AG221SN1D

Close to SB700

BIOS should not enable the
internal GPIO pull up resistor

KB_LED_DET 43
CAMERA_CBL_DET# 32

LAN_RST# 18
PLTRST# 9,12,18,37,39,45

WLAN_RADIO_DIS# 39
PCIE_MCARD1_DET# 39
USB_MCARD1_DET# 39

PCIE_MCARD2_DET# 40
USB_MCARD2_DET# 40
WPAN_RADIO_DIS_MINI# 39

PCIE_MCARD3_DET# 39
USB_MCARD3_DET# 39
WWAN_RADIO_DIS# 40

SB_WWAN_PCIE_RST# 40
SB_WLAN_PCIE_RST# 39
SB_WPAN_PCIE_RST# 39

SB_LOM_PCIE_RST# 33

(11)

CLK_PCI_851212,42

SB_AZ_CODEC_RST#13,31,42

2

For Side port memory setting.

R350 10KR350 10K
R358 10KR358 10K
R363 10KR363 10K

Memory Vendor LBF_ID1 LBF_ID0LBF_ID2

Hynix

Qimonda

Samsung

CAMERA_CBL_DET#

PCIE_MCARD1_DET#
USB_MCARD1_DET#
PCIE_MCARD2_DET#
USB_MCARD2_DET#
PCIE_MCARD3_DET#
USB_MCARD3_DET#

SB_WPAN_PCIE_RST#
SB_WWAN_PCIE_RST#
SB_WLAN_PCIE_RST#
SB_LOM_PCIE_RST#

TEMP_COMM

1

+3.3V_RUN

R359

R359

R351

R351

*10K_NC

*10K_NC

*10K_NC

*10K_NC

00

0

0

0

1

R692 *100K_NCR692 *100K_NC

R314 100KR314 100K
R312 100KR312 100K
R573 100KR573 100K
R533 100KR533 100K
R658 100KR658 100K
R641 100KR641 100K

R345 20KR345 20K
R702 20KR702 20K
R346 20KR346 20K
R339 20KR339 20K

R766 0R766 0

R362

R362
*10K_NC

*10K_NC

LBF_ID0
LBF_ID1
LBF_ID2

0

1

0

+3.3V_ALW

+3.3V_RUN

REQUIRED
STRAPS

+3.3V_RUN +3.3V_RUN +3.3V_SUS +3.3V_SUS

R672

R672

R675

R675

R285

R285

R298

R298
*10K_NC

*10K_NC

PCI_CLK512
PCI_CLK212
PCI_CLK312

GP1613

GP1713
RTC_CLK12
LPCCLK012
LPCCLK112

R302

R302
*10K_NC

*10K_NC

2

*10K_NC

*10K_NC

R286

R286
*10K_NC

*10K_NC

*10K_NC

*10K_NC

R677

R677
10K

10K

R355

R355

*10K_NC

*10K_NC

2.2K

2.2K

R349

R349

R674

R674

*2.2K_NC

*2.2K_NC

10K

10K

Title

Title

Title

SB700-HDD/POWER

SB700-HDD/POWER

SB700-HDD/POWER

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

FX6 3A

FX6 3A

FX6 3A

Date: Sheet

Date: Sheet

Date: Sheet

+3.3V_RUN +3.3V_ALW +3.3V_ALW +3.3V_ALW+3.3V_RUN+3.3V_RUN

R697

R697

R353

R353

*10K_NC

*10K_NC

*2.2K_NC

*2.2K_NC

R352

R352

2.2K

2.2K

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

1

R328

R328
*10K_NC

*10K_NC

R325

R325
10K

10K

R336

R336
*10K_NC

*10K_NC

R332

R332
10K

10K

14 70Tuesday, May 20, 2008

14 70Tuesday, May 20, 2008

14 70Tuesday, May 20, 2008

R305

R305
*10K_NC

*10K_NC

R306

R306
10K

10K

of

of

of

5

+3.3V_RUN

C400

C400

0.1U

0.1U

10

10
X7R

L100

L100

X7R

+1.2V_PCIE_VDDR

BLM21PG221SN1D

BLM21PG221SN1D

0805

0805

L55

L55

+AVDD_USB+3.3V_SUS

D D

+1.2V_RUN

BLM21PG221SN1D

BLM21PG221SN1D

0805

0805

C C

BLM21PG221SN1D

BLM21PG221SN1D

0805

0805

B B

C399

C399

0.1U

0.1U

10

10
X7R

X7R

+3.3V_RUN

C887

C887
22U

22U

6.3

6.3
X5R

X5R
0805

0805

L44

L44

C494

C494
22U

22U

6.3

6.3
X5R

X5R
0805

0805

+

+

C375

C375
220U

220U

6.3

6.3
Polymer

Polymer
7343

7343

C447

C447
1U

1U

6.3

6.3
X5R

X5R

C412

C412
1U

1U

6.3

6.3
X5R

X5R

C407

C407
1U

1U

6.3

6.3
X5R

X5R

C444

C444
1U

1U

6.3

6.3
X5R

X5R

C461

C461
1U

1U

6.3

6.3
X5R

X5R

50mil Width

C409

C397

C397
*22U_NC

*22U_NC

6.3

6.3
X5R

X5R
0805

0805

C427

C427
*0.1U_NC

*0.1U_NC

10

10
X7R

X7R

C428

C428
*0.1U_NC

*0.1U_NC

10

10
X7R

X7R

C409
*0.1U_NC

*0.1U_NC

10

10
X7R

X7R

50mil Width

C450

C450

C890

C890

C889

C889

1U

1U

1U

1U

6.3

6.3

6.3

6.3
X5R

X5R

X5R

X5R

+1.2V_AVDD_SATA+1.2V_RUN +1.2V_ALW_SUS

C459

C459

C454

1U

1U

6.3

6.3
X5R

X5R

C454

1U

1U

0.1U

0.1U

6.3

6.3 C493

10

10

X5R

X5R

X7R

X7R

50mil Width

C398

C398
22U

22U

6.3

6.3
X5R

X5R
0805

0805

C423

C423
1U

1U

6.3

6.3
X5R

X5R

C405

C405
1U

1U

6.3

6.3
X5R

X5R

C414

C414

0.1U

0.1U

10

10
X7R

X7R

50mil Width

C486

C505

C505
1U

1U

6.3

6.3
X5R

X5R

C486
1U

1U

6.3

6.3
X5R

X5R

C489

C489
1U

1U

6.3

6.3
X5R

X5R

C476

C476

0.1U

0.1U

10

10
X7R

X7R

C484

C484

0.1U

0.1U

10

10
X7R

X7R

C469

C469
1U

1U

6.3

6.3
X5R

X5R

C426

C426
*0.1U_NC

*0.1U_NC

10

10
X7R

X7R

C460

C460

0.1U

0.1U

10

10
X7R

X7R

C413

C413

0.1U

0.1U

10

10
X7R

X7R

C479

C479

0.1U

0.1U

10

10
X7R

X7R

4

AA4
AB5

AB21

AA21
AA22
AE25

AA14
AB18
AA15

AA17
AC18
AD17

AE17

G15
G17
G18

T15
U16

U17

Y20

P18
P19
P20
P21
R22
R24
R25

A16
B16
C16
D16
D17
E17
F15
F17
F18

M9
U9

V8

W7

U39C

U39C

L9

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8

Y6

VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12

VDD33_18_1
VDD33_18_2
VDD33_18_3
VDD33_18_4

PCIE_VDDR_1
PCIE_VDDR_2
PCIE_VDDR_3
PCIE_VDDR_4
PCIE_VDDR_5
PCIE_VDDR_6
PCIE_VDDR_7

AVDD_SATA_1
AVDD_SATA_4
AVDD_SATA_2
AVDD_SATA_3
AVDD_SATA_5
AVDD_SATA_6
AVDD_SATA_7

AVDDTX_0
AVDDTX_1
AVDDTX_2
AVDDTX_3
AVDDTX_4
AVDDTX_5
AVDDRX_0
AVDDRX_1
AVDDRX_2
AVDDRX_3
AVDDRX_4
AVDDRX_5

SB700 A12

SB700 A12

SB700

SB700

Part 3 of 5

Part 3 of 5

PCI/GPIO I/O

PCI/GPIO I/O

IDE/FLSH I/O

IDE/FLSH I/O

POWER

POWER

A-LINK I/O

A-LINK I/O

3.3V_S5 I/OCORE S5

3.3V_S5 I/OCORE S5

SATA I/O

SATA I/O

USB_PHY_1.2V_1
USB_PHY_1.2V_2

PLL CLKGEN I/O

PLL CLKGEN I/O

USB I/O

USB I/O

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8

CORE S0

CORE S0

VDD_9

CKVDD_1.2V_1
CKVDD_1.2V_2
CKVDD_1.2V_3
CKVDD_1.2V_4

S5_3.3V_1
S5_3.3V_2
S5_3.3V_3
S5_3.3V_4
S5_3.3V_5
S5_3.3V_6
S5_3.3V_7

S5_1.2V_1
S5_1.2V_2

V5_VREF
AVDDCK_3.3V
AVDDCK_1.2V

AVDDC

L15
M12
M14
N13
P12
P14
R11
R15
T16

L21
L22
L24
L25

A17
A24
B17
J4
J5
L1
L2

G2
G4

A10
B10

AE7
J16
K17
E9

3

+1.2V_VDD

C502

C502
1U

1U

10

10
X6S

X6S
0603

0603

+1.2V_CKVDD

C465

C465

2.2U

2.2U

10

10
X5R

X5R
0603

0603

C493
22U

22U

6.3

6.3
X5R

X5R
0805

0805

C478

C478
1U

1U

6.3

6.3
X5R

X5R

C904

C904

0.1U

0.1U

10

10
X7R

X7R

+V5_VREF1
+3.3V_AVDDCK
+1.2V_AVDDCK
+3.3V_AVDDC

100mil Width

C501

C501

C503

C503

1U

1U

1U

1U

10

10

10

10

X6S

X6S

X6S

X6S

0603

0603

0603

0603

30mil Width

C466

C467

C467

2.2U

2.2U

2.2U

2.2U

10

10

10

10

X5R

X5R

X5R

X5R

0603

0603

0603

0603

50mil Width

C519

C519

C490

C490

1U

1U

1U

1U

6.3

6.3

6.3

6.3
X5R

X5R

X5R

X5R

20mil Width

C482

C482

C487

C487

1U

1U

1U

1U

6.3

6.3

6.3

6.3

X5R

X5R

X5R

X5R

20mil Width

C903

C903

C906

C906

0.1U

0.1U

1U

1U

10

10

6.3

6.3

X7R

X7R

X5R

X5R

20mil Width
20mil Width

C474

C474

2.2U

2.2U

10

10
X5R

X5R
0603

0603

C481

C481

0.1U

0.1U

10

10
X7R

X7R

C500

C500
1U

1U

10

10
X6S

X6S
0603

0603

C464

C464
10U

10U

4

4
X5R

X5R
0603

0603

C515

C515

0.1U

0.1U

10

10
X7R

X7R

C485

C485
1U

1U

6.3

6.3
X5R

X5R

C905

C905
1U

1U

6.3

6.3
X5R

X5R

L52

L52

BLM15AG221SN1D

BLM15AG221SN1D

+3.3V_AVDDC

C506

C506

2.2U

2.2U

10

10
X5R

X5R
0603

0603

C449

C449

C499

C499

0.1U

0.1U

22U

22U

10

10

6.3

6.3
X7R

X7R

X5R

X5R
0805

0805

L48

L48
BLM21PG221SN1D

BLM21PG221SN1D

C511

C511

0.1U

0.1U

10

10
X7R

X7R

+1.2V_SUS

C910

C910
22U

22U

6.3

6.3
X5R

X5R
0805

0805

+1.2V_RUN

L54

L54

BLM15AG221SN1D

BLM15AG221SN1D

2

L56

L56

FBMJ4516HS111-T

FBMJ4516HS111-T

1806

1806

L53

L53

*FBMJ4516HS111-T_NC

*FBMJ4516HS111-T_NC

C462

C462

0.1U

0.1U

10

10
X7R

X7R

+1.2V_RUN

0805

0805C466

R361 *0_NC 0805R361 *0_NC 0805

R368 *0_NC 0805R368 *0_NC 0805

PJP10

PJP10

POWER_JP

POWER_JP

1806

1806

Note: FBMJ4516HS111-T
was 110 ohm@100MHz
4A DC 0.014ohm

+3.3V_ALW

+3.3V_SUS+3.3V_ALW_R

12

(5)

Use shape short Jump.

L50

L50

BLM15AG221SN1D

BLM15AG221SN1D

C471

C471

2.2U

2.2U

10

10
X5R

X5R
0603

0603

+3.3V_SUS

+3.3V_RUN

+1.2V_ALW_SUS

+1.2V_RUN

T10
U10
U11
U12

V11

V14

Y11

Y14

Y17
AA9
AB9

AB11
AB13
AB15
AB17

AC8
AD8
AE8

A15

B15
C14

D11
D13
D14
D15

E15

F12

F14

H17

K10

K12

K14

K15

H18

K25
M16
M17
M21

P16

W9

Y9

D8
D9

G9

H9

J9
J11
J12
J14
J15

J17
J22

F9

U39E

U39E

AVSS_SATA_1
AVSS_SATA_2
AVSS_SATA_3
AVSS_SATA_4
AVSS_SATA_5
AVSS_SATA_6
AVSS_SATA_7
AVSS_SATA_8
AVSS_SATA_9
AVSS_SATA_10
AVSS_SATA_11
AVSS_SATA_12
AVSS_SATA_13
AVSS_SATA_14
AVSS_SATA_15
AVSS_SATA_16
AVSS_SATA_17
AVSS_SATA_18
AVSS_SATA_19
AVSS_SATA_20

AVSS_USB_1
AVSS_USB_2
AVSS_USB_3
AVSS_USB_4
AVSS_USB_5
AVSS_USB_6
AVSS_USB_7
AVSS_USB_8
AVSS_USB_9
AVSS_USB_10
AVSS_USB_11
AVSS_USB_12
AVSS_USB_13
AVSS_USB_14
AVSS_USB_15
AVSS_USB_16
AVSS_USB_17
AVSS_USB_18
AVSS_USB_19
AVSS_USB_20
AVSS_USB_21
AVSS_USB_22
AVSS_USB_23
AVSS_USB_24

PCIE_CK_VSS_1
PCIE_CK_VSS_2
PCIE_CK_VSS_3
PCIE_CK_VSS_4
PCIE_CK_VSS_5
PCIE_CK_VSS_6
PCIE_CK_VSS_7
PCIE_CK_VSS_8

AVSSC

SB700 A12

SB700 A12

SB700

SB700

PCIE_CK_VSS_9
PCIE_CK_VSS_10
PCIE_CK_VSS_11
PCIE_CK_VSS_12
PCIE_CK_VSS_13
PCIE_CK_VSS_14
PCIE_CK_VSS_15
PCIE_CK_VSS_16
PCIE_CK_VSS_17
PCIE_CK_VSS_18
PCIE_CK_VSS_19
PCIE_CK_VSS_20
PCIE_CK_VSS_21

Part 5 of 5

Part 5 of 5

1

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8

VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42

GROUND

GROUND

VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50

AVSSCK

A2
A25
B1
D7
F20
G19
H8
K9
K11
K16
L4
L7
L10
L11
L12
L14
L16
M6
M10
M11
M13
M15
N4
N12
N14
P6
P9
P10
P11
P13
P15
R1
R2
R4
R9
R10
R12
R14
T11
T12
T14
U4
U14
V6
Y21
AB1
AB19
AB25
AE1
AE24

P23
R16
R19
T17
U18
U20
V18
V20
V21
W19
W22
W24
W25

L17

+5V_RUN

A A

+3.3V_RUN

5

R664 1KR664 1K

D32

D32

2 1

SDMK0340L-7-F SOD-323

SDMK0340L-7-F SOD-323

+V5_VREF1

C847

C847
1U

1U

6.3

6.3
X5R

X5R

4

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

3

2

Date: Sheet

COMPUTER

SB700-POWER

SB700-POWER

SB700-POWER

FX6 3A

FX6 3A

FX6 3A

of

of

of

15 70Tuesday, May 20, 2008

15 70Tuesday, May 20, 2008

15 70Tuesday, May 20, 2008

1

A

+1.8V_SUS +1.8V_SUS

CN5

CN5

1

VREF

3

DDR_A_D1
DDR_A_D0

DDR_A_DQS#0
DDR_A_DQS0

4 4

DDR_CKE0_DIMMA4,17

3 3

DDR_A_BS24,17

DDR_A_BS04,17
DDR_A_WE#4,17

DDR_A_CAS#4,17

DDR_CS1_DIMMA#4,17

2 2

SB_SMBDATA13,37,39,40

SB_SMBCLK13,37,39,40

+3.3V_RUN

1 1

DDR_A_D6
DDR_A_D7

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D14

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D19

DDR_A_D18

DDR_A_D25

DDR_A_DM3

DDR_A_D30
DDR_A_D27

DDR_A_MA12
DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3
DDR_A_MA1

DDR_A_MA10
DDR_A_BS0
DDR_A_WE#

DDR_A_CAS#

M_ODT14,17

M_ODT1
DDR_A_D36

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D39 DDR_A_D34
DDR_A_D38

DDR_A_D40
DDR_A_D41

DDR_A_DM5
DDR_A_D46 DDR_A_D42

DDR_A_D47

DDR_A_D49 DDR_A_D48

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D54
DDR_A_D55

DDR_A_D60
DDR_A_DM7
DDR_A_D63

DDR_A_D62
SB_SMBDATA

SB_SMBCLK

C364

C365

C365

2.2U

2.2U

10

10
X7R

X7R
0603

0603

C364

0.1U

0.1U

10

10
X7R

X7R

A

VSS47

5

DQ0

7

DQ1

9

VSS37

11

DQS#0

13

DQS0

15

VSS48

17

DQ2

19

DQ3

21

VSS38

23

DQ8

25

DQ9

27

VSS49

29

DQS#1

31

DQS1

33

VSS39

35

DQ10

37

DQ11

39

VSS50

41

VSS18

43

DQ16

45

DQ17

47

VSS1

49

DQS#2

51

DQS2

53

VSS19

55

DQ18

57

DQ19

59

VSS22

61

DQ24

63

DQ25

65

VSS23

67

DM3

69

NC4

71

VSS9

73

DQ26

75

DQ27

77

VSS4

79

CKE0

81

VDD7

83

NC1

85

A16_BA2

87

VDD9

89

A12

91

A9

93

A8

95

VDD5

97

A5

99

A3

101

A1

103

VDD10

105

A10/AP

107

BA0

109

WE#

111

VDD2

113

CAS#

115

S1#

117

VDD3

119

ODT1

121

VSS11

123

DQ32

125

DQ33

127

VSS26

129

DQS#4

131

DQS4

133

VSS2

135

DQ34

137

DQ35

139

VSS27

141

DQ40

143

DQ41

145

VSS29

147

DM5

149

VSS51

151

DQ42

153

DQ43

155

VSS40

157

DQ48

159

DQ49

161

VSS52

163

NCTEST

165

VSS30

167

DQS#6

169

DQS6

171

VSS31

173

DQ50

175

DQ51

177

VSS33

179

DQ56

181

DQ57

183

VSS3

185

DM7

187

VSS34

189

DQ58

191

DQ59

193

VSS14

195

SDA

197

SCL

199

VDD(SPD)

201

GNDPAD1

203

H1

TYCO_1775804-2

TYCO_1775804-2

CLOCK 0,1

2

VSS46

4

DQ4

6

DQ5

8

VSS15

10

DM0

12

VSS5

14

DQ6

16

DQ7

18

VSS16

20

DQ12

22

DQ13

24

VSS17

26

DM1

28

VSS53

30

CK0

32

CK0#

34

VSS41

36

DQ14

38

DQ15

40

VSS54

42

VSS20

44

DQ20

46

DQ21

48

VSS6

50

NC3

52

DM2

54

VSS21

56

DQ22

58

DQ23

60

VSS24

62

DQ28

64

DQ29

66

VSS25

68

DQS#3

70

DQS3

72

VSS10

74

DQ30

76

DQ31

78

VSS8

80

CKE1

82

VDD8

84

A15

86

A14

88

VDD11

90

PC4800 DDR2 SDRAM

SO-DIMM (200P)

PC4800 DDR2 SDRAM

SO-DIMM (200P)

A11

92

A7

94

A6

96

VDD4

98

A4

100

A2

102

A0

104

VDD12

106

BA1

108

RAS#

110

S0#

112

VDD1

114

ODT0

116

A13

118

VDD6

120

NC2

122

VSS12

124

DQ36

126

DQ37

128

VSS28

130

DM4

132

VSS42

134

DQ38

136

DQ39

138

VSS55

140

DQ44

142

DQ45

144

VSS43

146

DQS#5

148

DQS5

150

VSS56

152

DQ46

154

DQ47

156

VSS44

158

DQ52

160

DQ53

162

VSS57

164

CK1

166

CK1#

168

VSS45

170

DM6

172

VSS32

174

DQ54

176

DQ55

178

VSS35

180

DQ60

182

DQ61

184

VSS7

186

DQS#7

188

DQS7

190

VSS36

192

DQ62

194

DQ63

196

VSS13

198

SA0

200

SA1

202

GNDPAD2

204

H2

DDR_A_D5
DDR_A_D4

DDR_A_DM0
DDR_A_D2

DDR_A_D3
DDR_A_D12

DDR_A_D13
DDR_A_DM1

M_CLK_DDR0
M_CLK_DDR#0

DDR_A_D11
DDR_A_D15

DDR_A_D20
DDR_A_D21

DDR_A_DM2
DDR_A_D22

DDR_A_D23
DDR_A_D28

DDR_A_D29DDR_A_D24
DDR_A_DQS#3

DDR_A_DQS3

DDR_A_D31
DDR_A_D26

DDR_A_MA15
DDR_A_MA14

DDR_A_MA11
DDR_A_MA7
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2
DDR_A_MA0

DDR_A_BS1
DDR_A_RAS#

M_ODT0

DDR_A_MA13

DDR_A_D33
DDR_A_D32DDR_A_D37

DDR_A_DM4
DDR_A_D35

DDR_A_D44
DDR_A_D45

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D43
DDR_A_D53DDR_A_D52

M_CLK_DDR1
M_CLK_DDR#1

DDR_A_DM6
DDR_A_D50

DDR_A_D51
DDR_A_D56DDR_A_D61

DDR_A_D57
DDR_A_DQS#7

DDR_A_DQS7
DDR_A_D58

DDR_A_D59

R270

R270
10K

10K

B

C348

C348

2.2U

2.2U

10

10
X7R

X7R
0603

0603

Place C348 2.2uF and C342 0.1uF <
500mils from DDR connector

M_CLK_DDR0 4
M_CLK_DDR#0 4

CPU_MEMHOT# CPU_MEMHOT#

R263 0R263 0

DDR_CKE1_DIMMA 4,17

DDR_A_BS1 4,17
DDR_A_RAS# 4,17
DDR_CS0_DIMMA# 4,17

M_ODT0 4,17

M_CLK_DDR0

C246

C246

1.5P/50V

1.5P/50V

M_CLK_DDR#0
M_CLK_DDR1

C703

C703

1.5P/50V

1.5P/50V

M_CLK_DDR#1

PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH

M_CLK_DDR1 4
M_CLK_DDR#1 4

R269

R269
10K

10K

SMbus address A0 SMbus address A4

B

C342

C342

0.1U

0.1U

10

10
X7R

X7R

DDR_A_DM[0..7] 4 DDR_B_DM[0..7] 4
DDR_A_D[0..63] 4

DDR_A_DQS[0..7] 4
DDR_A_DQS#[0..7] 4
DDR_A_MA[0..15] 4,17

DDR_CKE2_DIMMB4,17

DDR_B_BS24,17

DDR_B_BS04,17
DDR_B_WE#4,17

DDR_B_CAS#4,17

DDR_CS1_DIMMB#4,17

+3.3V_RUN

DDR_B_D4
DDR_B_D5

DDR_B_DQS#0
DDR_B_DQS0

DDR_B_D3
DDR_B_D2

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10 DDR_B_D15
DDR_B_D14 DDR_B_D11

DDR_B_DQS#2
DDR_B_DQS2

M_ODT34,17

C390

C390

2.2U

2.2U

10

10
X7R

X7R
0603

0603

C

+1.8V_SUS +1.8V_SUS

BOT-DOWNBOT_UP

CN6

CN6

1

VREF

3

VSS47

5

DQ0

7

DQ1

9

VSS37

11

DQS#0

13

DQS0

15

VSS48

17

DQ2

19

DQ3

21

VSS38

23

DQ8

25

DQ9

27

VSS49

29

DQS#1

31

DQS1

33

VSS39

35

DQ10

37

DQ11

39

VSS50

41

DDR_B_D16
DDR_B_D21

DDR_B_D18
DDR_B_D19

DDR_B_D25
DDR_B_D29 DDR_B_D24

DDR_B_DM3

DDR_B_D27
DDR_B_D31

DDR_B_BS2

DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

DDR_B_MA10

DDR_B_BS0

DDR_B_WE#
DDR_B_CAS#

M_ODT3
DDR_B_D37

DDR_B_D36
DDR_B_DQS#4

DDR_B_DQS4
DDR_B_D34

DDR_B_D38
DDR_B_D40 DDR_B_D41

DDR_B_D45
DDR_B_DM5
DDR_B_D42

DDR_B_D46
DDR_B_D53

DDR_B_D52

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D54

DDR_B_D60
DDR_B_DM7
DDR_B_D58

DDR_B_D59
SB_SMBDATA

SB_SMBCLK

C391

C391

0.1U

0.1U

10

10
X7R

X7R

VSS18

43

DQ16

45

DQ17

47

VSS1

49

DQS#2

51

DQS2

53

VSS19

55

DQ18

57

DQ19

59

VSS22

61

DQ24

63

DQ25

65

VSS23

67

DM3

69

NC4

71

VSS9

73

DQ26

75

DQ27

77

VSS4

79

CKE0

81

VDD7

83

NC1

85

A16_BA2

87

VDD9

89

A12

91

A9

93

A8

95

VDD5

97

A5

99

A3

101

A1

103

VDD10

105

A10/AP

107

BA0

109

WE#

111

VDD2

113

CAS#

115

S1#

117

VDD3

119

ODT1

121

VSS11

123

DQ32

125

DQ33

127

VSS26

129

DQS#4

131

DQS4

133

VSS2

135

DQ34

137

DQ35

139

VSS27

141

DQ40

143

DQ41

145

VSS29

147

DM5

149

VSS51

151

DQ42

153

DQ43

155

VSS40

157

DQ48

159

DQ49

161

VSS52

163

NCTEST

165

VSS30

167

DQS#6

169

DQS6

171

VSS31

173

DQ50

175

DQ51

177

VSS33

179

DQ56

181

DQ57

183

VSS3

185

DM7

187

VSS34

189

DQ58

191

DQ59

193

VSS14

195

SDA

197

SCL

199

VDD(SPD)

201

GNDPAD1

203

H1

TYCO_292406-4

TYCO_292406-4

CLOCK 2,3

C

2

VSS46

DQ4
DQ5

VSS15

DM0

VSS5

DQ6
DQ7

VSS16

DQ12
DQ13

VSS17

DM1

VSS53

CK0

CK0#

VSS41

DQ14
DQ15

VSS54
VSS20

DQ20
DQ21

VSS6

NC3

DM2

VSS21

DQ22
DQ23

VSS24

DQ28
DQ29

VSS25

DQS#3

DQS3

VSS10

DQ30
DQ31

VSS8
CKE1
VDD8

A15
A14

VDD11

PC4800 DDR2 SDRAM

SO-DIMM (200P)

PC4800 DDR2 SDRAM

SO-DIMM (200P)

A11

A7
A6

VDD4

A4
A2
A0

VDD12

BA1

RAS#

S0#
VDD1
ODT0

A13
VDD6

NC2

VSS12

DQ36
DQ37

VSS28

DM4

VSS42

DQ38
DQ39

VSS55

DQ44
DQ45

VSS43

DQS#5

DQS5

VSS56

DQ46
DQ47

VSS44

DQ52
DQ53

VSS57

CK1

CK1#

VSS45

DM6

VSS32

DQ54
DQ55

VSS35

DQ60
DQ61

VSS7

DQS#7

DQS7

VSS36

DQ62
DQ63

VSS13

SA0
SA1

GNDPAD2

H2

DDR_B_D1

4

DDR_B_D0

6
8

DDR_B_DM0

10
12

DDR_B_D7

14

DDR_B_D6

16
18

DDR_B_D12

20

DDR_B_D13

22
24

DDR_B_DM1

26
28
30
32
34
36
38
40

42

DDR_B_D20

44

DDR_B_D17

46
48

NC_PM_EXTTS#1NC_PM_EXTTS#0

50

DDR_B_DM2

52
54

DDR_B_D22

56

DDR_B_D23

58
60

DDR_B_D28

62
64
66

DDR_B_DQS#3

68

DDR_B_DQS3

70
72

DDR_B_D30

74

DDR_B_D26

76
78
80
82

DDR_B_MA15

84

DDR_B_MA14

86
88

DDR_B_MA11

90

DDR_B_MA7

92

DDR_B_MA6

94
96

DDR_B_MA4

98

DDR_B_MA2

100

DDR_B_MA0

102
104
106
108
110
112
114

DDR_B_MA13

116
118
120
122

DDR_B_D33

124

DDR_B_D32

126
128

DDR_B_DM4

130
132

DDR_B_D35

134

DDR_B_D39

136
138

DDR_B_D44

140
142
144

DDR_B_DQS#5

146

DDR_B_DQS5

148
150

DDR_B_D43

152

DDR_B_D47

154
156

DDR_B_D48

158

DDR_B_D49

160
162
164
166
168

DDR_B_DM6

170
172

DDR_B_D51

174

DDR_B_D55

176
178

DDR_B_D56DDR_B_D57

180

DDR_B_D61

182
184

DDR_B_DQS#7

186

DDR_B_DQS7

188
190

DDR_B_D62

192

DDR_B_D63

194
196
198
200
202
204

R296

R296
10K

10K

CKE 2,3CKE 0,1

R289 0R289 0

R297 10KR297 10K

D

C865

C865

2.2U

2.2U

10

10
X7R

X7R
0603

0603

Place C865 2.2uF and C864 0.1uF <
500mils from DDR connector

M_CLK_DDR2 4
M_CLK_DDR#2 4

DDR_B_D[0..63] 4

DDR_B_DQS[0..7] 4
DDR_B_DQS#[0..7] 4
DDR_B_MA[0..15] 4,17

DDR_CKE3_DIMMB 4,17

DDR_B_BS1 4,17
DDR_B_RAS# 4,17

DDR_CS0_DIMMB# 4,17
M_ODT2 4,17

PLACE CLOSE TO PROCESSOR
WITHIN 1.5 INCH

M_CLK_DDR2

C722

C722

1.5P/50V

1.5P/50V

M_CLK_DDR#2
M_CLK_DDR3

C720

C720

1.5P/50V

1.5P/50V

M_CLK_DDR#3

M_CLK_DDR3 4
M_CLK_DDR#3 4

+3.3V_RUN

D

E

+0.9V_DDR_REF+0.9V_DDR_REF

C864

C864

0.1U

0.1U

10

10
X7R

X7R

CPU_MEMHOT# 5

+1.8V_SUS

C829 2.2U/10V/0603C829 2.2U/10V/0603
C826 2.2U/10V/0603C826 2.2U/10V/0603
C828 2.2U/10V/0603C828 2.2U/10V/0603
C382 2.2U/10V/0603C382 2.2U/10V/0603
C381 2.2U/10V/0603C381 2.2U/10V/0603

C443 2.2U/10V/0603C443 2.2U/10V/0603
C440 2.2U/10V/0603C440 2.2U/10V/0603
C383 2.2U/10V/0603C383 2.2U/10V/0603
C441 2.2U/10V/0603C441 2.2U/10V/0603
C429 2.2U/10V/0603C429 2.2U/10V/0603

C436 0.1U/10VC436 0.1U/10V
C380 0.1U/10VC380 0.1U/10V
C386 0.1U/10VC386 0.1U/10V
C825 0.1U/10VC825 0.1U/10V

C378 0.1U/10VC378 0.1U/10V
C827 0.1U/10VC827 0.1U/10V
C387 0.1U/10VC387 0.1U/10V
C385 0.1U/10VC385 0.1U/10V

Note:
Place C829,C826,C828,C382,C381 and
C443,C440,C383,C441,429 close to CN5
Place C436,C380,C386,C825,C378 and
C827,C387,C385 close to CN6

+1.8V_SUS

R238

R238

C339

C339

+0.9V_DDR_REF

0.1U

0.1U

1K

1K

10

10

1%

1%

X7R

X7R

R239

R239
1K

1K

1%

1%

C343

C343

0.1U

0.1U

10

10
X7R

X7R

C347

C347
1000P

1000P

50

50
X7R

X7R

Note: Place close to DIMM

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

COMPUTER

DDRII SODIMMX2

DDRII SODIMMX2

DDRII SODIMMX2

FX6 3A

FX6 3A

FX6 3A

E

of

of

of

16 70Tuesday, May 20, 2008

16 70Tuesday, May 20, 2008

16 70Tuesday, May 20, 2008

1

+0.9V_DDR_VTT

C421 0.1U/10VC421 0.1U/10V
C372 0.1U/10VC372 0.1U/10V

A A

B B

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9V_DDR_VTT

C C

C358 0.1U/10VC358 0.1U/10V
C419 0.1U/10VC419 0.1U/10V
C438 0.1U/10VC438 0.1U/10V

C360 0.1U/10VC360 0.1U/10V
C418 0.1U/10VC418 0.1U/10V
C394 0.1U/10VC394 0.1U/10V
C370 0.1U/10VC370 0.1U/10V
C359 0.1U/10VC359 0.1U/10V

C389 0.1U/10VC389 0.1U/10V
C357 0.1U/10VC357 0.1U/10V
C420 0.1U/10VC420 0.1U/10V
C355 0.1U/10VC355 0.1U/10V
C422 0.1U/10VC422 0.1U/10V

C366 0.1U/10VC366 0.1U/10V
C367 0.1U/10VC367 0.1U/10V
C417 0.1U/10VC417 0.1U/10V
C416 0.1U/10VC416 0.1U/10V
C373 0.1U/10VC373 0.1U/10V

C356 0.1U/10VC356 0.1U/10V
C371 0.1U/10VC371 0.1U/10V RP7
C393 0.1U/10VC393 0.1U/10V
C369 0.1U/10VC369 0.1U/10V
C354 0.1U/10VC354 0.1U/10V

C392 0.1U/10VC392 0.1U/10V
C379 0.1U/10VC379 0.1U/10V
C395 0.1U/10VC395 0.1U/10V
C361 0.1U/10VC361 0.1U/10V
C396 0.1U/10VC396 0.1U/10V

Note: Reserve stitching function for CN5.

+1.8V_SUS

+0.9V_DDR_VTT

C439

C439

0.1U

0.1U

16

16
X7R

X7R

+1.8V_SUS

C435

C435

0.1U

0.1U

16

16
X7R

X7R

+0.9V_DDR_VTT

+1.8V_SUS

C349

C349
*0.1U_NC

*0.1U_NC

16

16
X7R

X7R

+0.9V_DDR_VTT

2

+1.8V_SUS

C353

C353
*0.1U_NC

*0.1U_NC

16

16
X7R

X7R

+0.9V_DDR_VTT

+1.8V_SUS

C377

C377

0.1U

0.1U

16

16
X7R

X7R

+0.9V_DDR_VTT

3

+1.8V_SUS

C376

C376
*0.1U_NC

*0.1U_NC

16

16
X7R

X7R

+0.9V_DDR_VTT

+1.8V_SUS

C432

C432
*0.1U_NC

*0.1U_NC

16

16
X7R

X7R

+0.9V_DDR_VTT

+1.8V_SUS

C433

C433

0.1U

0.1U

16

16
X7R

X7R

+0.9V_DDR_VTT

4

DDR_A_BS04,16

DDR_CKE0_DIMMA4,16

DDR_A_BS24,16

DDR_CKE1_DIMMA4,16

DDR_A_BS14,16

DDR_B_BS04,16

DDR_B_WE#4,16

DDR_CKE2_DIMMB4,16

DDR_B_BS24,16

5

DDR_A_MA[0..15]4,16

DDR_A_MA3
DDR_A_MA1

DDR_A_MA12
DDR_A_MA9

DDR_A_MA5
DDR_A_MA8

DDR_B_MA[0..15]4,16

DDR_B_MA8
DDR_B_MA5

DDR_B_MA3
DDR_B_MA1

DDR_B_MA9
DDR_B_MA12

DDR_B_MA2
DDR_B_MA0

DDR_B_MA6
DDR_B_MA4

DDR_B_BS14,16

DDR_A_MA[0..15]

1
3

R254 47R254 47

1
3

R252 47R252 47
R251 47R251 47

R262 47R262 47

1
3

R265 47R265 47

DDR_B_MA[0..15]

R277 47R277 47
R278 47R278 47

1
3

1
3

1
3

R275 47R275 47
R274 47R274 47

1
3

1
3

R292 47R292 47

4P2R-47

4P2R-47

4P2R-47

4P2R-47

4P2R-47

4P2R-47

4P2R-47

4P2R-47

4P2R-47

4P2R-47

4P2R-47

4P2R-47

4P2R-47

4P2R-47

4P2R-47

4P2R-47

6

2
4

2
4

2
4

2
4

2
4

2
4

2
4

2
4

RP8

RP8

RP6

RP6

RP7

RP14

RP14

RP15

RP15

RP13

RP13

RP19

RP19

RP18

RP18

+0.9V_DDR_VTT

+0.9V_DDR_VTT

RP17

RP17

RP16

RP16

RP11

RP11

RP12

RP12

R253 47R253 47
R257 47R257 47
R256 47R256 47
R258 47R258 47

R267 47R267 47
R264 47R264 47

R266 47R266 47

RP10

RP10

RP9

RP9

R255 47R255 47
R268 47R268 47

1
3

R279 47R279 47
R280 47R280 47
R293 47R293 47
R290 47R290 47

R294 47R294 47
R291 47R291 47

R281 47R281 47

1
3

R276 47R276 47
R295 47R295 47

1
3

4P2R-47

4P2R-47

1
3

1
3

1
3

4P2R-47

4P2R-47

4P2R-47

4P2R-47

4P2R-47

4P2R-47

4P2R-47

4P2R-47

4P2R-47

4P2R-47

7

DDR_A_MA4

2

DDR_A_MA6

4

DDR_A_MA0

2

DDR_A_MA2

4

DDR_CS0_DIMMA#
DDR_A_RAS#

M_ODT0

DDR_A_MA11

2

DDR_A_MA7

4

DDR_A_MA14

2

DDR_A_MA15

4

DDR_A_MA10
DDR_A_MA13

DDR_B_MA14

2

DDR_B_MA11

4

DDR_CS0_DIMMB#
DDR_B_RAS#

M_ODT3

DDR_B_MA15

2

DDR_B_MA7

4

DDR_B_MA10
DDR_B_MA13

8

DDR_A_WE# 4,16
DDR_A_CAS# 4,16
DDR_CS1_DIMMA# 4,16
M_ODT1 4,16

DDR_CS0_DIMMA# 4,16
DDR_A_RAS# 4,16

M_ODT0 4,16

DDR_B_CAS# 4,16
DDR_CS1_DIMMB# 4,16
M_ODT2 4,16
DDR_CKE3_DIMMB 4,16

DDR_CS0_DIMMB# 4,16
DDR_B_RAS# 4,16

M_ODT3 4,16

Note: Reserve stitching function for CN6.

D D

+1.8V_SUS

+0.9V_DDR_VTT

C384

C384

0.1U

0.1U

16

16
X7R

X7R

+1.8V_SUS

C434

C434
*0.1U_NC

*0.1U_NC

16

16
X7R

X7R

+0.9V_DDR_VTT

1

+1.8V_SUS

C350

C350

0.1U

0.1U

16

16
X7R

X7R

+0.9V_DDR_VTT

+1.8V_SUS

C437

C437
*0.1U_NC

*0.1U_NC

16

16
X7R

X7R

+0.9V_DDR_VTT

2

+1.8V_SUS

C351

C351
*0.1U_NC

*0.1U_NC

16

16
X7R

X7R

+0.9V_DDR_VTT

+1.8V_SUS

C352

C352
*0.1U_NC

*0.1U_NC

16

16
X7R

X7R

+0.9V_DDR_VTT

3

+1.8V_SUS

C388

C388

0.1U

0.1U

16

16
X7R

X7R

+0.9V_DDR_VTT

+1.8V_SUS

C430

C430

0.1U

0.1U

16

16
X7R

X7R

+0.9V_DDR_VTT

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

4

5

6

Date: Sheet

COMPUTER

DDRII TERMINATION

DDRII TERMINATION

DDRII TERMINATION

FX6 3A

FX6 3A

FX6 3A

of

of

of

17 70Tuesday, May 20, 2008

17 70Tuesday, May 20, 2008

7

17 70Tuesday, May 20, 2008

8

5

D D

PCIE_MTX_C_GRX_P[0..15]8
PCIE_MTX_C_GRX_N[0..15]8

C C

B B

PLTRST#9,12,14,37,39,45

LAN_RST#14

R159

R159

R1580R158

*0_NC

*0_NC

0

A A

PCIE_RST#

4

PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N15

PCIE_MTX_C_GRX_P14
PCIE_MTX_C_GRX_N14

PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N13

PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N12

PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N11

PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N10

PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N9

PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N8

PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N7

PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N6

PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N5

PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N4

PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3

PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_N2

PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N1

PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0

CLK_PCIE_VGA25
CLK_PCIE_VGA#25

AC30
AC31

AC29
AB29

AB31
AB30

AA31
AA30

W30
W31

W29

V29

V31
V30

U31
U30

P30
P31

P29
N29

N31
N30

M31
M30

K30
K31

K29

J29

J31
J30

H31
H30

AD29
AD30

AC28
AC27

AG25

U25A

U25A

PCIE_RX0P
PCIE_RX0N

PCIE_RX1P
PCIE_RX1N

PCIE_RX2P
PCIE_RX2N

PCIE_RX3P
PCIE_RX3N

PCIE_RX4P
PCIE_RX4N

PCIE_RX5P
PCIE_RX5N

PCIE_RX6P
PCIE_RX6N

PCIE_RX7P
PCIE_RX7N

PCIE_RX8P
PCIE_RX8N

PCIE_RX9P
PCIE_RX9N

PCIE_RX10P
PCIE_RX10N

PCIE_RX11P
PCIE_RX11N

PCIE_RX12P
PCIE_RX12N

PCIE_RX13P
PCIE_RX13N

PCIE_RX14P
PCIE_RX14N

PCIE_RX15P
PCIE_RX15N

Clock

Clock

PCIE_REFCLKP
PCIE_REFCLKN

SM BUS

SM BUS

NC_SMBCLK
NC_SMBDATA

PERSTB

M82-S A11

M82-S A11

3

PART 1 OF 6

PART 1 OF 6

P

P
C

C
I

I

-

­E

E
X

X
P

P
R

R
E

E
S

S
S

S

I

I
N

N
T

T
E

E
R

R
F

F
A

A
C

C
E

E

PCIE_TX0P
PCIE_TX0N

PCIE_TX1P
PCIE_TX1N

PCIE_TX2P
PCIE_TX2N

PCIE_TX3P
PCIE_TX3N

PCIE_TX4P
PCIE_TX4N

PCIE_TX5P
PCIE_TX5N

PCIE_TX6P
PCIE_TX6N

PCIE_TX7P
PCIE_TX7N

PCIE_TX8P
PCIE_TX8N

PCIE_TX9P
PCIE_TX9N

PCIE_TX10P
PCIE_TX10N

PCIE_TX11P
PCIE_TX11N

PCIE_TX12P
PCIE_TX12N

PCIE_TX13P
PCIE_TX13N

PCIE_TX14P
PCIE_TX14N

PCIE_TX15P
PCIE_TX15N

Calibration

Calibration

PCIE_CALRN
PCIE_CALRP

NC_1
NC_2

AA28
AA27

AA25
AA24

Y28
Y27

Y25
Y24

V28
V27

V25
V24

T28
T27

T25
T24

P28
P27

P25
P24

M28
M27

M25
M24

L28
L27

L25
L24

J28
J27

G28
G27

AF25
AE25

AE23
AH30

PCIE_MRX_GTX_C_P15
PCIE_MRX_GTX_C_N15

PCIE_MRX_GTX_C_P14
PCIE_MRX_GTX_C_N14

PCIE_MRX_GTX_C_P13
PCIE_MRX_GTX_C_N13

PCIE_MRX_GTX_C_P12
PCIE_MRX_GTX_C_N12

PCIE_MRX_GTX_C_P11
PCIE_MRX_GTX_C_N11

PCIE_MRX_GTX_C_P10
PCIE_MRX_GTX_C_N10

PCIE_MRX_GTX_C_P9
PCIE_MRX_GTX_C_N9

PCIE_MRX_GTX_C_P8
PCIE_MRX_GTX_C_N8

PCIE_MRX_GTX_C_P7
PCIE_MRX_GTX_C_N7

PCIE_MRX_GTX_C_P6
PCIE_MRX_GTX_C_N6

PCIE_MRX_GTX_C_P5
PCIE_MRX_GTX_C_N5

PCIE_MRX_GTX_C_P4
PCIE_MRX_GTX_C_N4

PCIE_MRX_GTX_C_P3
PCIE_MRX_GTX_C_N3

PCIE_MRX_GTX_C_P2
PCIE_MRX_GTX_C_N2

PCIE_MRX_GTX_C_P1
PCIE_MRX_GTX_C_N1

PCIE_MRX_GTX_C_P0
PCIE_MRX_GTX_C_N0

R84 2K/FR84 2K/F

R83

R83

1.27K/F

1.27K/F

2

+PCIE_VDDC

1

PCIE_MRX_GTX_P[0..15]8
PCIE_MRX_GTX_N[0..15]8

PCIE_MRX_GTX_P0 PCIE_MRX_GTX_C_P0
PCIE_MRX_GTX_P1
PCIE_MRX_GTX_P2
PCIE_MRX_GTX_P3
PCIE_MRX_GTX_P4
PCIE_MRX_GTX_P5
PCIE_MRX_GTX_P6
PCIE_MRX_GTX_P7
PCIE_MRX_GTX_P8
PCIE_MRX_GTX_P9
PCIE_MRX_GTX_P10
PCIE_MRX_GTX_P11
PCIE_MRX_GTX_P12
PCIE_MRX_GTX_P13
PCIE_MRX_GTX_P14
PCIE_MRX_GTX_P15

PCIE_MRX_GTX_N0
PCIE_MRX_GTX_N1
PCIE_MRX_GTX_N2
PCIE_MRX_GTX_N3
PCIE_MRX_GTX_N4
PCIE_MRX_GTX_N5
PCIE_MRX_GTX_N6
PCIE_MRX_GTX_N7
PCIE_MRX_GTX_N8
PCIE_MRX_GTX_N9
PCIE_MRX_GTX_N10
PCIE_MRX_GTX_N11
PCIE_MRX_GTX_N12
PCIE_MRX_GTX_N13
PCIE_MRX_GTX_N14
PCIE_MRX_GTX_N15

C198 0.1U/ 10VC198 0.1U/ 10V
C192 0.1U/ 10VC192 0.1U/ 10V
C169 0.1U/ 10VC169 0.1U/ 10V
C178 0.1U/ 10VC178 0.1U/ 10V
C154 0.1U/ 10VC154 0.1U/ 10V
C166 0.1U/ 10VC166 0.1U/ 10V
C141 0.1U/ 10VC141 0.1U/ 10V
C151 0.1U/ 10VC151 0.1U/ 10V
C134 0.1U/ 10VC134 0.1U/ 10V
C145 0.1U/ 10VC145 0.1U/ 10V
C127 0.1U/ 10VC127 0.1U/ 10V
C129 0.1U/ 10VC129 0.1U/ 10V
C121 0.1U/ 10VC121 0.1U/ 10V
C123 0.1U/ 10VC123 0.1U/ 10V
C112 0.1U/ 10VC112 0.1U/ 10V
C117 0.1U/ 10VC117 0.1U/ 10V

C189 0.1U/ 10VC189 0.1U/ 10V
C186 0.1U/ 10VC186 0.1U/ 10V
C172 0.1U/ 10VC172 0.1U/ 10V
C171 0.1U/ 10VC171 0.1U/ 10V
C163 0.1U/ 10VC163 0.1U/ 10V
C162 0.1U/ 10VC162 0.1U/ 10V
C147 0.1U/ 10VC147 0.1U/ 10V
C148 0.1U/ 10VC148 0.1U/ 10V
C140 0.1U/ 10VC140 0.1U/ 10V
C139 0.1U/ 10VC139 0.1U/ 10V
C128 0.1U/ 10VC128 0.1U/ 10V
C133 0.1U/ 10VC133 0.1U/ 10V
C119 0.1U/ 10VC119 0.1U/ 10V
C126 0.1U/ 10VC126 0.1U/ 10V
C115 0.1U/ 10VC115 0.1U/ 10V
C114 0.1U/ 10VC114 0.1U/ 10V

PCIE_MRX_GTX_C_P1
PCIE_MRX_GTX_C_P2
PCIE_MRX_GTX_C_P3
PCIE_MRX_GTX_C_P4
PCIE_MRX_GTX_C_P5
PCIE_MRX_GTX_C_P6
PCIE_MRX_GTX_C_P7
PCIE_MRX_GTX_C_P8
PCIE_MRX_GTX_C_P9
PCIE_MRX_GTX_C_P10
PCIE_MRX_GTX_C_P11
PCIE_MRX_GTX_C_P12
PCIE_MRX_GTX_C_P13
PCIE_MRX_GTX_C_P14
PCIE_MRX_GTX_C_P15

PCIE_MRX_GTX_C_N0
PCIE_MRX_GTX_C_N1
PCIE_MRX_GTX_C_N2
PCIE_MRX_GTX_C_N3
PCIE_MRX_GTX_C_N4
PCIE_MRX_GTX_C_N5
PCIE_MRX_GTX_C_N6
PCIE_MRX_GTX_C_N7
PCIE_MRX_GTX_C_N8
PCIE_MRX_GTX_C_N9
PCIE_MRX_GTX_C_N10
PCIE_MRX_GTX_C_N11
PCIE_MRX_GTX_C_N12
PCIE_MRX_GTX_C_N13
PCIE_MRX_GTX_C_N14
PCIE_MRX_GTX_C_N15

Title

Title

Title

M82S_PCIE

M82S_PCIE

M82S_PCIE

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

FX6 3A

B

FX6 3A

B

FX6 3A

B

of

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet

18 70Tuesday, May 20, 2008

18 70Tuesday, May 20, 2008

18 70Tuesday, May 20, 2008

1

5

MEMORY APERTURE SIZE SELECT

RAM_CFG0

RAM_CFG1

MEMORY
SIZE

128MB

256MB

64MB

D D

512MB

+3.3V_DELAY

MEMORY STRAPS

400MHz 256MB(32M*16) Samsung

400MHz 256MB(32M*16) Hynix

500MHz 256MB(32M*16) Samsung

500MHz 256MB(32M*16) Qimonda

+1.8V_RUN

C C

GPIO Straps
table

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO10

ATI Usage
recommended settings

+3.3V_DELAY

B B

CLK_VGA_27M_SS25

Layout Note:
Place R476, R461, R474,
R473 close to M82.

A A

CLK_VGA_27M_NSS25

RAM_CFG2

RAM_CFG3

R497 10KR497 10K
R489 *10K_NCR489 *10K_NC
R498 *10K_NCR498 *10K_NC
R111 *10K_NCR111 *10K_NC

GPIO13 GPIO12 GPIO11

GPIO9

0

X

001

X

X

100

X

00

100

RAM_CFG0
RAM_CFG1
RAM_CFG2
RAM_CFG3

RAM_TYPE
_CFG3

01

0

R468 *10K_NCR468 *10K_NC
R467 *10K_NCR467 *10K_NC
R469 10KR469 10K
R470 *10K_NCR470 *10K_NC

RAM_TYPE_CFG0
RAM_TYPE_CFG1
RAM_TYPE_CFG2
RAM_TYPE_CFG3

DESCRIPTION OF DEFAULT SETTINGS

PCIE FULL TX OUTPUT SWING
PCIE TRANSMITTER DE-EMPHASIS ENABLED
ATI reserved configuration straps.
ATI reserved configuration straps.
DEBUG SIGNALS MUXED OUT
Allows either PCIe 2.5GT/s or 5.0GT/s operation
ATI Internal use only
Serial ROM clock to ROM.

R104 10KR104 10K
R485 10KR485 10K
R480 *10K_NCR480 *10K_NC
R102 *10K_NCR102 *10K_NC
R491 *10K_NCR491 *10K_NC
R490 *10K_NCR490 *10K_NC
R106 *10K_NCR106 *10K_NC
R488 *10K_NCR488 *10K_NC
R110 10KR110 10K
R126 *10K_NCR126 *10K_NC
R100 10KR100 10K
R72 10KR72 10K

R125 10KR125 10K

0= DO NOT INSTALL RESISTOR, X = DESIGN DEPENDANT,
RSVD = ATI RESERVED (DO NOT INSTALL)

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO10
HDMI_HD_EN
TEMP_FAIL#
GFX_CLKREQ#
VGAHSYNC

Strap pin for
HDMI enable.

TEMP_FAIL#

R474 100/FR474 100/F
R473 120/FR473 120/F

5

RAM_TYPE

RAM_TYPE
_CFG2

_CFG1

RAM_TYPE
_CFG0

00

1

001

1

10

000

1

ATI

FX6

Usage

Usage

X
X
RSVD
RSVD
0
X
0

1
1
0
0
0
0
0
0

R476 *0_NCR476 *0_NC

CLK_VGA_27M_SS_RCLK_VGA_27M_SS

R462 0R462 0

R461

R461
*10K_NC

*10K_NC

4

PANEL_BKEN42

GFX_CORE_CNTRL055

THERMAL_INT#22

TEMP_FAIL#20

GFX_CORE_CNTRL155

BB_ENA20

+1.8V_RUN

VREFG VOLTAGE DIVIDER IS
(VREFG = VDDR4,5(1.8V) / 3 = .6V)
PLACE VREF DIVIDER
AND CAP CLOSE TO ASIC

R82

R82
499/F

499/F

R74

R74
249/F

249/F

4

C94

C94

0.1U

0.1U

10

10
X7R

X7R

XTAIN

RAM_TYPE_CFG0
RAM_TYPE_CFG1
RAM_TYPE_CFG2
RAM_TYPE_CFG3

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6

HDMI_HD_EN
RAM_CFG3
GPIO10
RAM_CFG0
RAM_CFG1
RAM_CFG2

T98 PADT98 PAD

R499 0R499 0

CLK_VGA_27M_SS_R

R113 0R113 0

T31 PADT31 PAD

TEMP_FAIL#

R112 0R112 0

T99 PADT99 PAD

GFX_CLKREQ#

R127 1KR127 1K

T37 PADT37 PAD
T42 PADT42 PAD
T43 PADT43 PAD
T32 PADT32 PAD

T21 PADT21 PAD
T20 PADT20 PAD
T22 PADT22 PAD
T93 PADT93 PAD
T94 PADT94 PAD

+DPLL_PVDD

+PCIE_PVDD

+MPVDD

+DPLL_VDDC

R70 1KR70 1K

U25B

U25B

AJ4

TXCM_DPA0P

AJ5

TXCP_DPA0N

AL5

TX0M_DPA1P

AK5

TX0P_DPA1N

AL6

TX1M_DPA2P

AK6

TX1P_DPA2N

AK8

TX2M_DPA3P

AL8

TX2P_DPA3N

AD9

DVALID

AE7

PSYNC_NEW

AK4

DVPCNTL_MVP_0

AL3

DVPCNTL_MVP_1

V2

DVPCNTL_0

V1

DVPCNTL_1

W3

DVPCNTL_2

W1

DVPCLK

Y1

DVPDATA_0

Y2

DVPDATA_1

Y3

DVPDATA_2

AA2

DVPDATA_3

AA3

DVPDATA_4

AB1

DVPDATA_5

AB2

DVPDATA_6

AB3

DVPDATA_7

AC1

DVPDATA_8

AC3

DVPDATA_9

AD1

DVPDATA_10

AD2

DVPDATA_11

AD3

DVPDATA_12

AF3

DVPDATA_13

AG3

DVPDATA_14

AH3

DVPDATA_15

AG1

DVPDATA_16

AH2

DVPDATA_17

AH1

DVPDATA_18

AJ3

DVPDATA_19

AJ1

DVPDATA_20

AJ2

DVPDATA_21

AK2

DVPDATA_22

AK3

DVPDATA_23

Y4

GPIO_0

V3

GPIO_1

V4

GPIO_2

V5

GPIO_3

U3

GPIO_4

U2

GPIO_5

T4

GPIO_6

T5

GPIO_7_BLON

T7

GPIO_8_ROMSO

T8

GPIO_9_ROMSI

R1

GPIO_10_ROMSCK

R2

GPIO_11

R3

GPIO_12

P1

GPIO_13

P3

GPIO_14_HPD2

N1

GPIO_15_PWRCNTL0

N2

GPIO_16_SSIN

P4

GPIO_17_THERMAL_INT

P7

GPIO_18_HPD3

P8

GPIO_19_CTF

P5

GPIO_20_PWRCNTL1

V7

GPIO_21_BB_EN

N3

GPIO_22_ROMCSB

Y5

GPIO_23_CLKREQB

M4

GPIO_24_JMODE

M5

GPIO_25_TDI

M7

GPIO_26_TCK

M8

GPIO_27_TMS

L8

GPIO_28_TDO

Y8

GEN_A

Y7

GEN_B

V8

GEN_C

AH6

GEN_D_HPD4

AG6

GEN_E

AC11

VREFG

AH12

DPLL_PVDD

AG12

DPLL_PVSS

AH31

PCIE_PVDD

A9

MPVDD

B9

MPVSS

AE12

DPLL_VDDC

AJ31

XTALIN

AJ30

XTALOUT

AH26

TESTEN

AD12

PLLTEST

M82-S A11

M82-S A11

3

GENERAL

GENERAL
PURPOSE

PURPOSE
I/O

I/O

3

EXT TMDS

EXT TMDS
DVO

DVO

PLL &

PLL &
XTAL

XTAL

TEST

TEST

PART 2 OF 6

PART 2 OF 6

INTEGRATED

INTEGRATED
TMDS/DP PORT

TMDS/DP PORT

DAC1 / CRT

DAC1 / CRT

DAC2 (TV/CRT2)

DAC2 (TV/CRT2)

SERIAL

SERIAL
BUSES

BUSES

DDC3DATA_DP3_AUXN

DDC3CLK_DP3_AUXP

DDC4DATA_DP4_AUXN

DDC4CLK_DP4_AUXP

THERMAL

THERMAL

TXCM_DPB0P
TXCP_DPB0N

TX0M_DPB1P

TX0P_DPB1N

TX1M_DPB2P

TX1P_DPB2N

TX2M_DPB3P

TX2P_DPB3N

DPA_PVDD
DPA_PVSS

DPB_PVDD
DPB_PVSS

DPA_VDDR_1
DPA_VDDR_2

DPB_VDDR_1
DPB_VDDR_2

DPB_VSSR_5
DPB_VSSR_4
DPB_VSSR_3
DPB_VSSR_2
DPB_VSSR_1

DPA_VSSR_5
DPA_VSSR_4
DPA_VSSR_3
DPA_VSSR_2
DPA_VSSR_1

DP_CALR

HPD1

HSYNC
VSYNC

RSET
AVDD

AVSSQ

VDD1DI

VSS1DI

R2B

G2B

B2B

COMP

V2SYNC
H2SYNC

A2VDD

A2VDDQ

A2VSSQ

VDD2DI

VSS2DI

R2SET

SCL
SDA

DDC1DATA

DDC1CLK

DDC2DATA

DDC2CLK

TS_FDO

DPLUS

DMINUS

RB

GB

BB

R

G

B

R2

G2

B2

C

Y

AK9
AL9

AJ9
AJ10

AL10
AK10

AL11
AK11

AL7
AK7

AE11
AF11

AJ12
AJ13

AK13
AL13

AL12
AK12
AJ11
AH9
AH11

AJ8
AF7
AG7
AJ7
AH7

AG11
AA8
AL28

AK28
AL27

AK27
AL26

AK26
AK29

AK30
AJ28
AL29
AH28
AJ27
AJ26
AL17

AK17
AL15

AK15
AL14

AK14
AJ17
AJ15
AJ14
AE16

AF16
AH14
AH16
AG16
AF18
AE18
AG14

AA5
AA4

AJ29
AH29

AC5
AC4

AF4
AH4

G_DAT_DDC2_L

AF9

G_CLK_DDC2_L

AG9
AE14
AE5

AE4

+TPVDD

+DPA_VDDR

+DPB_VDDR

VIP_3

R466 0R466 0

R458 0R458 0

R455 0R455 0

VGAHSYNC

R76 499/FR76 499/F

+AVDD

+VDD1D_2D

+A2VDD
+A2VDDQ

+VDD1D_2D

R96 715/FR96 715/F

LCD_DDCDAT
LCD_DDCCLK

2

R472 0R472 0

R95 150R95 150

R79 0R79 0
R77 0R77 0

2

VGA_RED

VGA_GRN

VGA_BLU

LCD_DDCDAT 26
LCD_DDCCLK 26

HDMI_SDA 28
HDMI_SCL 28

G_DAT_DDC2 27
G_CLK_DDC2 27

VGA_THERMDP 22

VGA_THERMDN 22

1

HDMI_CLK- 28
HDMI_CLK+ 28

HDMI_TX0- 28
HDMI_TX0+ 28

HDMI_TX1- 28
HDMI_TX1+ 28

HDMI_TX2- 28
HDMI_TX2+ 28

HDMI_DET 28

VGA_RED 27

VGA_GRN 27

VGA_BLU 27

VGAHSYNC 27
VGAVSYNC 27

Title

Title

Title

M82S_IO

M82S_IO

M82S_IO

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

FX6 3A

Custom

FX6 3A

Custom

FX6 3A

Custom

Date: Sheet

Date: Sheet of

Date: Sheet of

WITH M8x ASIC
INSTALL M8x STRAP RESISTORS
AND
DO NOT INSTALL M7x STRAP RESISTORS
WITH M7x ASIC
INSTALL M7x STRAP RESISTORS
AND
DO NOT INSTALL M8x STRAP RESISTORS

VGA_RED
VGA_GRN
VGA_BLU

R465

R465

R464

R464

150/F

150/F

150/F

150/F

OPTIONAL 0 OHM STRAPS TO GROUND
FOR RB,GB,BB AND R2B,G2B,B2B
SEE DAC1_RGB AND DAC2_RGB SHEETS

PLACE OR RESISTORS CLOSE TO ASIC

LCD_DDCDAT
LCD_DDCCLK

3.3V TO 5V LEVEL SHIFT LOGIC REQUIRED
IF DDC1,DDC2 USED ON M8x OR DDC1,DDC2,DDC3
(DDC4 NOT AVAILABLE) USED ON M7x
DDC3,DDC4 ARE 5V TOLERANT ON M8x

DIS only

Layout Note:

R463

R463

Place 150 ohm

150/F

150/F

termination resistors
close to ATI CHIP.

+3.3V_DELAY

R1 2.2KR1 2.2K
R5 2.2KR5 2.2K

19 70Tuesday, May 20, 2008

19 70Tuesday, May 20, 2008

19 70Tuesday, May 20, 2008

1

of

5

U25E

U25E

AA26

PCIE_VSS_1

AA29

PCIE_VSS_2

AC26

PCIE_VSS_3

AD31

PCIE_VSS_4

AE29

PCIE_VSS_5

AE30

D D

C C

B B

TEMP_FAIL#
is High
active.

A A

TEMP_FAIL#19

RUN_ON26,42,46,49,50,52,55

5

AE31

F28
G26
G29
G30
G31

H29

L26

L29

L30

L31
M26
M29

P26

R29

R30

R31

T26

U29

V26

Y26

Y29

Y30

Y31

A13

C18

A24

A30
AA1

AA11
AA14
AA17
AA20

AA6
AC2
AC7
AE3

AL4

AD14
AF12
AF14
AD16
AD18

AE6
AG2
AE9

AH25

AK1

AK31

AJ6

AL2

AL30

C13

J25
J26

A2

B1

M82-S A11

M82-S A11

PCIE_VSS_6
PCIE_VSS_7
PCIE_VSS_8
PCIE_VSS_9
PCIE_VSS_10
PCIE_VSS_11
PCIE_VSS_12
PCIE_VSS_13
PCIE_VSS_14
PCIE_VSS_15
PCIE_VSS_16
PCIE_VSS_17
PCIE_VSS_18
PCIE_VSS_19
PCIE_VSS_20
PCIE_VSS_21
PCIE_VSS_22
PCIE_VSS_23
PCIE_VSS_24
PCIE_VSS_25
PCIE_VSS_26
PCIE_VSS_27
PCIE_VSS_28
PCIE_VSS_29
PCIE_VSS_30
PCIE_VSS_31
PCIE_VSS_32

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32

2

Part 5 of 6

Part 5 of 6

PCI-Express GND

PCI-Express GND

CORE GND

CORE GND

31

Q74

Q74
*2N7002W-7-F_NC

*2N7002W-7-F_NC

VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98

VSS_99
VSS_100
VSS_101
VSS_102

R456

R456
*100K_NC

*100K_NC

B25
J8
B5
D11
C17
C22
C27
D29
C3
C6
D3
D28
F29
D4
F11
F12
F14
F16
F18
F20
F21
F23
F25
F7
F9
G3
G6
H23
J3
J4
J6
K1
L12
L15
L18
L21
L6
M11
M14
M17
M20
M6
P12
P15
P18
P21
P6
AC21
R14
R17
R20
T6
U1
U12
U15
U18
U21
AE20
V14
V17
V20
P2
V6
W2
Y12
Y15
Y18
Y21
Y6
M9

+3.3V_SUS+3.3V_SUS

U23

U23

53

*74AHC1G08GW_NC

*74AHC1G08GW_NC

1

4

2

R443 0R443 0

4

+1.8V_RUN

C206

C206
10U

10U

6.3

6.3
X5R

X5R
0603

0603

C682

C682
1U

1U

10

10
X5R

X5R
0603

0603

C197

C197
1U

1U

10

10
X5R

X5R
0603

0603

+3.3V_DELAY

C90

C90
10U

10U

6.3

6.3
X5R

X5R
0603

0603

+1.8V_RUN

C229

C229
10U

10U

6.3

6.3
X5R

X5R
0603

0603

+3.3V_DELAY +3.3V_RUN

R445

R445

75K

75K

OPTIONAL RC NETWORK
TO FINE TUNE
POWER SEQUENCING

4

C698

C698
10U

10U

6.3

6.3
X5R

X5R
0603

0603

C687

C687
1U

1U

10

10
X5R

X5R
0603

0603

C201

C201
1U

1U

10

10
X5R

X5R
0603

0603

C635

C635

0.1U

0.1U

10

10
X5R

X5R

C146

C146
1U

1U

10

10
X5R

X5R
0603

0603

C289

C289

0.1U

0.1U

10

10
X7R

X7R
0402

0402

+BBN

3

C700

C700
10U

10U

6.3

6.3
X5R

X5R
0603

0603

C301

C301
1U

1U

10

10
X5R

X5R
0603

0603

C208

C208
1U

1U

10

10
X5R

X5R
0603

0603

( 3.3V @ 50MA VDDR3)

C142

C142
1U

1U

10

10
X5R

X5R
0603

0603

C675

C675
1U

1U

10

10
X5R

X5R
0603

0603

+VDD_MEM_CLK0
+VDD_MEM_CLK1

Q72

Q72
SI2303BDS-T1-E3

SI2303BDS-T1-E3

3

2

3

C300

C300
10U

10U

6.3

6.3
X5R

X5R
0603

0603

C688

C688
1U

1U

10

10
X5R

X5R
0603

0603

C205

C205
1U

1U

10

10
X5R

X5R
0603

0603

+VDD_CT

C175

C175
1U

1U

10

10
X5R

X5R
0603

0603

2

31

Q73

Q73

2N7002W-7-F

2N7002W-7-F

C135

C135
1U

1U

10

10
X5R

X5R
0603

0603

1

C658

C658
1U

1U

10

10
X5R

X5R
0603

0603

C159

C159
1U

1U

10

10
X5R

X5R
0603

0603

R446

R446
100K

100K

C104

C104
1U

1U

10

10
X5R

X5R
0603

0603

A15
A22
A28

H11
H12
H14
H16
H18
H20
H21
B31

AA9

AC18
AC16
AC14
AC12

AF1
AF2

AE1
AE2

AD11

A10
A19

B10
B19

V11
U11

R11
P11

J11
J20
J21

A4
A8
B8
C9
D1
H1

M1

Y9
V9

T9

L9

M2
M3

L4

U25D

U25D

VDDR1_1
VDDR1_2
VDDR1_3
VDDR1_4
VDDR1_5
VDDR1_6
VDDR1_7
VDDR1_8
VDDR1_9
VDDR1_10
VDDR1_11
VDDR1_12
VDDR1_13
VDDR1_14
VDDR1_15
VDDR1_16
VDDR1_17
VDDR1_18

VDD_CT_1
VDD_CT_2
VDD_CT_3
VDD_CT_4
VDD_CT_5
VDD_CT_6
VDD_CT_7
VDD_CT_8

VDDR3_1
VDDR3_2
VDDR3_3
VDDR3_4

VDDR4_1
VDDR4_2

VDDR5_1
VDDR5_2

RSVD_1
RSVD_2
RSVD_3
RSVD_4

VDDRH_1
VDDRH_2

VSSRH_1
VSSRH_2

BBN_1
BBN_2

BBP_1
BBP_2

M82-S A11

M82-S A11

BB_ENA19

PART 4 OF 6

PART 4 OF 6

I/O Internal

I/O Internal

Memory

I/O

Clock

Memory

I/O

Clock

+BBN

C699

C699
1U

1U

10

10
X5R

X5R
0603

0603

Memory I/O

Memory I/O

P

P
O

O
W

W
E

E
R

R

Back Bias

Back Bias

Q33

Q33
SI2303BDS-T1-E3

SI2303BDS-T1-E3

3

2

R105

R105
10K

10K

2

PCIE_VDDR_1
PCIE_VDDR_2
PCIE_VDDR_3
PCIE_VDDR_4
PCIE_VDDR_5
PCIE_VDDR_6
PCIE_VDDR_7
PCIE_VDDR_8

PCIE_VDDC_1
PCIE_VDDC_2
PCIE_VDDC_3
PCIE_VDDC_4
PCIE_VDDC_5
PCIE_VDDC_6
PCIE_VDDC_7
PCIE_VDDC_8

PCIE_VDDC_9
PCIE_VDDC_10
PCIE_VDDC_11

PCI-Express

PCI-Express

PCIE_VDDC_12

VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8

VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15

Core

Core

VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDDC_23
VDDC_24
VDDC_25
VDDC_26
VDDC_27
VDDC_28
VDDC_29
VDDC_30
VDDC_31
VDDC_32
VDDC_33

VDDCI_1
VDDCI_2
VDDCI_3
VDDCI_4

2

31

Q32

Q32

2N7002W-7-F

2N7002W-7-F

2

1

AF30
AF31
AF29
AF27
AF28
AG29
AG30
AG31

AA23
AC24
AC25
AE26
AE27
AE28
L23
M23
P23
T23
V23
Y23

L11
L14
L17
L20
M12
M15
M18
M21
AC20
P14
P17
P20
R12
R15
R18
R21
AD20
U14
U17
U20
V12
V15
V18
V21
Y11
Y14
Y17
Y20
AA12
AA15
AA18
AA21
P9

J12
J14
J16
J18

1

+1.8V_RUN

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet of

Date: Sheet of

+PCIE_VDDR

+PCIE_VDDC

C97

C97

C177

C177

C152

1U

1U

10

10
X5R

X5R
0603

0603

C188

C188
1U

1U

10

10
X5R

X5R
0603

0603

C181

C181
1U

1U

10

10
X5R

X5R
0603

0603

C150

C150
1U

1U

10

10
X5R

X5R
0603

0603

C199

C199
1U

1U

10

10
X5R

X5R
0603

0603

C152
1U

1U

10

10
X5R

X5R
0603

0603

C168

C168
1U

1U

10

10
X5R

X5R
0603

0603

C155

C155
1U

1U

10

10
X5R

X5R
0603

0603

C182

C182
1U

1U

10

10
X5R

X5R
0603

0603

C209

C209
1U

1U

10

10
X5R

X5R
0603

0603

+VCC_GFX_CORE

+5V_RUN

1

10U

10U

6.3

6.3
X5R

X5R
0603

0603

C91

C91
10U

10U

6.3

6.3
X5R

X5R
0603

0603

C106

C106
10U

10U

6.3

6.3
X5R

X5R
0603

0603

C174

C174
10U

10U

6.3

6.3
X5R

X5R
0603

0603

C193

C193
1U

1U

10

10
X5R

X5R
0603

0603

Q84

Q84
2N7002W-7-F

2N7002W-7-F

3 1

2

R524 100KR524 100K

M82S_POWER

M82S_POWER

M82S_POWER

FX6 3A

FX6 3A

FX6 3A

+VCC_GFX_CORE

C89

C89

C167

C167

1U

1U

1U

1U

10

10

10

10

X5R

X5R

X5R

X5R

0603

0603

0603

0603

C180

C180

C136

C136

1U

1U

1U

1U

10

10

10

10

X5R

X5R

X5R

X5R

0603

0603

0603

0603

C156

C156

C157

C157

1U

1U

1U

1U

10

10

10

10

X5R

X5R

X5R

X5R

0603

0603

0603

0603

C170

C170

C143

C143

1U

1U

1U

1U

10

10

10

10

X5R

X5R

X5R

X5R

0603

0603

0603

0603

L80 BLM15BD121SN1DL80 BLM15BD121SN1D

C709

C709
1U

1U

10

10
X5R

X5R
0603

0603

of

20 70Tuesday, May 20, 2008

20 70Tuesday, May 20, 2008

20 70Tuesday, May 20, 2008

5

L23

+1.8V_RUN

+3.3V_DELAY

D D

+1.8V_RUN

+1.8V_RUN

+1.8V_RUN

C C

+1.8V_RUN

+1.8V_RUN

B B

+1.8V_RUN

+1.8V_RUN

+1.1V_GFX_PCIE

A A

+1.1V_GFX_PCIE

L23

*BLM15BD121SN1D_NC

*BLM15BD121SN1D_NC

L15

L15

*BLM15BD121SN1D_NC

*BLM15BD121SN1D_NC

(3.3V @ 250MA LVDDR)

L17

L17

BLM18PG471SN1D

BLM18PG471SN1D

(1.8V @ 100MA LVDDC)
(1.8V @ 400MA LVDDC,LVDDR)

L21 BLM15BD121SN1DL21 BLM15BD121SN1D

(1.8V @ 30MA LPVDD)

L78 BLM15BD121SN1DL78 BLM15BD121SN1D

(1.8V @ 40MA PCIE_PVDD)

L18 BLM15BD121SN1DL18 BLM15BD121SN1D

(1.8V @ 2MA A2VDDQ)

L76 BLM15BD121SN1DL76 BLM15BD121SN1D

(1.8V @ 65MA AVDD)

BLM15BD121SN1DL26 BLM15BD121SN1DL26

(VDD_CT 1.8V
@ 110MA (VDD_CT)

L19

L19

*BLM15BD121SN1D_NC

*BLM15BD121SN1D_NC

L14

L14

BLM15BD121SN1D

BLM15BD121SN1D

L73

L73

BLM15BD121SN1D

BLM15BD121SN1D

(1.8V @ 100MA EACH SINGLE LINK)
(1.1V @ 200MA EACH SINGLE LINK)

5

C649

C649
10U

10U

6.3

6.3
X5R

X5R
0603

0603

C158

C158
10U

10U

6.3

6.3
X5R

X5R
0603

0603

C100

C100
10U

10U

6.3

6.3
X5R

X5R
0603

0603

C662

C662
10U

10U

6.3

6.3
X5R

X5R
0603

0603

C95

C95
10U

10U

6.3

6.3
X5R

X5R
0603

0603

C109

C109
1U

1U

10

10
X5R

X5R
0603

0603

C663

C663
1U

1U

10

10
X5R

X5R
0603

0603

C144

C144
1U

1U

10

10
X5R

X5R
0603

0603

C92

C92
10U

10U

6.3

6.3
X5R

X5R
0603

0603

C105

C105
10U

10U

6.3

6.3
X5R

X5R
0603

0603

C102

C102
1U

1U

10

10
X5R

X5R
0603

0603

C653

C653
1U

1U

10

10
X5R

X5R
0603

0603

C103

C103
10U

10U

6.3

6.3
X5R

X5R
0603

0603

C647

C647
10U

10U

6.3

6.3
X5R

X5R
0603

0603

C131

C131

0.1U

0.1U

10

10
X5R

X5R

C664

C664

0.1U

0.1U

10

10
X5R

X5R

C183

C183

0.1U

0.1U

10

10
X5R

X5R

C101

C101
1U

1U

10

10
X5R

X5R
0603

0603

C132

C132
1U

1U

10

10
X5R

X5R
0603

0603

C108

C108

0.1U

0.1U

10

10
X5R

X5R

C660

C660

0.1U

0.1U

10

10
X5R

X5R

C96

C96
1U

1U

10

10
X5R

X5R
0603

0603

C655

C655
1U

1U

10

10
X5R

X5R
0603

0603

C130

C130

0.1U

0.1U

10

10
X5R

X5R

C98

C98

0.1U

0.1U

10

10
X5R

X5R

+LPVDD

+PCIE_PVDD

+A2VDDQ

+AVDD

+VDD_CT

C110

C110

0.1U

0.1U

10

10
X5R

X5R

C651

C651

0.1U

0.1U

10

10
X5R

X5R

+3.3V_DELAY

4

+LVDDR

R750R75
0

+LVDDC

+1.8V_RUN

+1.8V_RUN

+1.8V_RUN

+1.8V_RUN

R454

R454
*0_NC

*0_NC

L72 BLM15BD121SN1DL72 BLM15BD121SN1D

(1.8V @ 40MA DPLL_PVDD)

L75 BLM15BD121SN1DL75 BLM15BD121SN1D

(3.3V @ 135MA A2VDD)

L16 BLM15BD121SN1DL16 BLM15BD121SN1D

( 1.8V @ 100MA VDD1DI,VDD2DI)

L77

L77

BLM15BD121SN1D

BLM15BD121SN1D

BLM18PG471SN1D

BLM18PG471SN1D

(1.8V @ 400MA PCIE_VDDR)

+DPA_VDDR

+DPB_VDDR

4

FOR M7x
INSTALL LVDDR TO +3.3V AND
LVDDC TO 1.8V
WITH SEPARATE FILTERS
DO NOT INSTALL STRAP RESISTOR
FOR M8x
INSTALL LVDDR AND LVDDC TO +1.8V
WITH THE ONE LVDDC FILTER
DO NOT INSTALL LVDDR FILTER
INSTALL STRAP RESISTOR

+DPLL_PVDD

C644

C644

C641

C641

C646

1U

1U

10

10
X5R

X5R
0603

0603

C657

C657
1U

1U

10

10
X5R

X5R
0603

0603

C99

C99
1U

1U

10

10
X5R

X5R
0603

0603

C138

C138
1U

1U

10

10
X5R

X5R
0603

0603

C667

C667
1U

1U

10

10
X5R

X5R
0603

0603

C646

0.1U

0.1U

10

10
X5R

X5R

C650

C650

0.1U

0.1U

10

10
X5R

X5R

C93

C93

0.1U

0.1U

10

10
X5R

X5R

C661

C661

0.1U

0.1U

10

10
X5R

X5R

C668

C668

0.1U

0.1U

10

10
X5R

X5R

+A2VDD

+VDD1D_2D

+TPVDD

+PCIE_VDDR

10U

10U

6.3

6.3
X5R

X5R
0603

0603

C645

C645
10U

10U

6.3

6.3
X5R

X5R
0603

0603

C107

C107
10U

10U

6.3

6.3
X5R

X5R
0603

0603

C654

C654
10U

10U

6.3

6.3
X5R

X5R
0603

( 1.8V@ 20mA for Single link and 40mA for Dual-Link )

L79

L79

FOR M8x
INSTALL DPA_VDDR TO +1.1V AND
DPB_VDDR TO +1.1V
WITH SEPARATE FILTERS
DO NOT INSTALL STRAP RESISTOR
FOR M7x
INSTALL DPA_VDDR AND DPB_VDDR TO +1.8V
WITH THE ONE DPA_VDDR FILTER
DO NOT INSTALL DPB_VDDR FILTER
INSTALL STRAP RESISTOR

0603

C670

C670
10U

10U

6.3

6.3
X5R

X5R
0603

0603

PLACE ALL DECOUPLING AS CLOSE TO ASIC AS POSSIBLE

3

3

2

+1.8V_RUN

+1.8V_RUN

120R_2A

+1.1V_GFX_PCIE

120R_450mA

+VCC_GFX_CORE

2

1

L30

L30

BLM15BD121SN1D

BLM15BD121SN1D

C242

C242

C241

C241

1U

1U

10U

10U

10

10

6.3

6.3
X5R

X5R

X5R

X5R

0603

0603

0603

L83

L83

BLM15BD121SN1D

BLM15BD121SN1D

L20 FBM-11-160808-121-A20TL20 FBM-11-160808-121-A20T

L74

L74

BLM15BD121SN1D

BLM15BD121SN1D

L81

L81

GMLB-160808-0120L-N8

GMLB-160808-0120L-N8

Title

Title

Title

M82S_POWER RAIL SELECT

M82S_POWER RAIL SELECT

M82S_POWER RAIL SELECT

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

FX6 3A

FX6 3A

FX6 3A

Date: Sheet

Date: Sheet

Date: Sheet

0603

C721

C721

C228

C228

10U

10U

1U

1U

6.3

6.3

10

10

X5R

X5R

X5R

X5R

0603

0603

0603

0603

C165

C165
10U

10U

6.3

6.3
X5R

X5R
0603

0603

C118

C118
10U

10U

6.3

6.3
X5R

X5R
0603

0603

C656

C656
10U

10U

6.3

6.3
X5R

X5R
0603

0603

C696

C696

C707

C707

1U

1U

10U

10U

10

10

6.3

6.3
X5R

X5R

X5R

X5R

0603

0603

0603

0603

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

C153

C153
1U

1U

10

10
X5R

X5R
0603

0603

C113

C113
1U

1U

10

10
X5R

X5R
0603

0603

C648

C648
1U

1U

10

10
X5R

X5R
0603

0603

+VDD_MEM_CLK0

(1.8V @ MA VDDRHA_1
INCLUDED IN VDDR1)

C231

C231

0.1U

0.1U

10

10
X5R

X5R

+VDD_MEM_CLK1

(1.8V @ MA VDDRHA_2
INCLUDED IN VDDR1)

C730

C730

0.1U

0.1U

10

10
X5R

X5R

+PCIE_VDDC

(PCIE_VDDC 1.1V @ 1A )

C173

C173

0.1U

0.1U

10

10
X5R

X5R

C122

C122

0.1U

0.1U

10

10
X5R

X5R

+DPLL_VDDC

(DPLL_VDDC 1.1V @ 100 MA)

C652

C652

0.1U

0.1U

10

10
X5R

X5R

+MPVDD

( .95V-1.1V @ 230MA MPVDD)

C702

C702

0.1U

0.1U

10

10
X5R

X5R

21 70Tuesday, May 20, 2008

21 70Tuesday, May 20, 2008

21 70Tuesday, May 20, 2008

1

of

of

of

5

+1.8V_RUN

R530

R530
100/F

100/F

R526

R526
100/F

100/F

ODTA0
ODTA1

RASA0#
RASA1#

CASA0#
CASA1#

WEA0#
WEA1#

CKEA0
CKEA1

CSA0_0#
CSA1_0#

CLKA0
CLKA0#

CLKA1

CLKA1#
WDQSA[7..0]
RDQSA[7..0]
DQMA#[7..0]
MDA[63..0]
MAA[11..0]

BA[1..0]

A12

+1.8V_RUN

C706

C706

0.1U

0.1U

10

10
X7R

X7R

R156

R156
100/F

100/F

R163

R163
100/F

100/F

R136

R136

4.7K

4.7K

C243

C243

0.1U

0.1U

10

10
X7R

X7R

R137

R137

4.7K

4.7K

R120

R120
240

240

ODTA023
ODTA123

RASA0#23

D D

C C

B B

RASA1#23
CASA0#23

CASA1#23
WEA0#23

WEA1#23

CKEA023

CKEA123
CSA0_0#23

CSA1_0#23

CLKA023
CLKA0#23

CLKA123
CLKA1#23

WDQSA[7..0]23
RDQSA[7..0]23
DQMA#[7..0]23

MDA[63..0]23
MAA[11..0]23

BA[1..0]23

A1223

PLACE MVREF DIVIDERS
AND CAPS CLOSE TO ASIC

DIVIDER RESISTORS DDR2 DDR3
MVREF TO 1.8V
MVREF TO GND

40.2R100R
100R100R

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17

MDA18

MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

MVREFD
MVREFS

TEST_MCLK
TEST_YCLK
MEMTEST

4

U25C

U25C

Part 3 of 6

Part 3 of 6

E29
E30
E31
D31
C29
B29
B30
A29
E26
D26
E25
D25
G23
G21
E21
D21
C28
B28
B27
A27
C25
A25
C24
B24
C23
B23
A23
B22
C20
B20
A20
C19

F30
F31

C8
C7
B7
A7
A5
C4
B4
A3
G9
E9
D9
G7
G5

F5

G4

F4
B3
B2
C2
C1
E3

F3

F2

F1
G2
G1
H3
H2
K2

L3

L2

L1

L5

L7

J7

DQ_0
DQ_1
DQ_2
DQ_3
DQ_4
DQ_5
DQ_6
DQ_7
DQ_8
DQ_9
DQ_10
DQ_11
DQ_12
DQ_13
DQ_14
DQ_15
DQ_16
DQ_17
DQ_18
DQ_19
DQ_20
DQ_21
DQ_22
DQ_23
DQ_24
DQ_25
DQ_26
DQ_27
DQ_28
DQ_29
DQ_30
DQ_31
DQ_32
DQ_33
DQ_34
DQ_35
DQ_36
DQ_37
DQ_38
DQ_39
DQ_40
DQ_41
DQ_42
DQ_43
DQ_44
DQ_45
DQ_46
DQ_47
DQ_48
DQ_49
DQ_50
DQ_51
DQ_52
DQ_53
DQ_54
DQ_55
DQ_56
DQ_57
DQ_58
DQ_59
DQ_60
DQ_61
DQ_62
DQ_63

MVREFD
MVREFS

TEST_MCLK
TEST_YCLK
MEMTEST

M82-S A11

M82-S A11

SMBCLK242,43

MEMORY

MEMORY
INTERFACE

INTERFACE

write strobe read strobe

write strobe read strobe

B14

MA_0

A14

MA_1

B13

MA_2

E14

MA_3

B17

MA_4

A17

MA_5

C15

MA_6

G16

MA_7

E16

MA_8

C14

MA_9

A12

MA_10

B12

MA_11

C12

MA_BA0

D14

MA_BA1

B15

MA_A12

G14

MA_BA2

D30

DQMb_0

G25

DQMb_1

C26

DQMb_2

C21

DQMb_3

C5

DQMb_4

D6

DQMb_5

D2

DQMb_6

K3

DQMb_7

C30

QS_0

D23

QS_1

B26

QS_2

B21

QS_3

B6

QS_4

E7

QS_5

E2

QS_6

J2

QS_7

C31

QS_0B

E23

QS_1B

A26

QS_2B

A21

QS_3B

A6

QS_4B

D7

QS_5B

E1

QS_6B

J1

QS_7B

E20

ODT0

C11

ODT1

A18

CLK0

A11

CLK1

B18

CLK0b

B11

CLK1b

G20

RAS0b

D12

RAS1b

D20

CAS0b

E12

CAS1b

E18

CS0b_0

G18

CS0b_1

G11

CS1b_0

E11

CS1b_1

D18

CKE0

G12

CKE1

D16

WE0b

C10

WE1b

J5

DRAM_RST

+3.3V_DELAY +3.3V_DELAY

2

3 1

Q21 2N7002W-7-FQ21 2N7002W-7-F

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
BA0
BA1
A12
BA2

DQMA#0
DQMA#1
DQMA#2
DQMA#3
DQMA#4
DQMA#5
DQMA#6
DQMA#7

RDQSA0
RDQSA1
RDQSA2
RDQSA3
RDQSA4
RDQSA5
RDQSA6
RDQSA7

WDQSA0
WDQSA1
WDQSA2
WDQSA3
WDQSA4
WDQSA5
WDQSA6
WDQSA7

ODTA0
ODTA1

CLKA0
CLKA1

CLKA0#
CLKA1#

RASA0#
RASA1#

CASA0#
CASA1#

CSA0_0#
CSA0_1#

CSA1_0#
CSA1_1#

CKEA0
CKEA1

WEA0#
WEA1#

R139 4.7KR139 4.7K

R68

R68

4.7K

4.7K

R65

R65

4.7K

4.7K

GFX_SCLK

3

T39T39

FOR DUAL RANK CONNECTIONS

T45T45

T41T41

USE THE CSxB_1 CHIP SELECT PINS

+1.8V_RUN

THERMAL_INT#19

GFX_SCLK
GFX_SDATA

R67 *0_NCR67 *0_NC

+LVDDR

+LVDDC

+LPVDD

GPIO17_INT#

2

BIA_PWM

U25F

U25F

PART 6 OF 6

PART 6 OF 6

AF20

LVDDR_1

AG20

LVDDR_2

AJ18

LVDDC_1

AH20

LVDDC_2

AF23

LVSSR_1

AF21

LVSSR_2

AL18

LVSSR_3

AJ22

LVSSR_4

AJ25

LVSSR_5

AK18

LVSSR_6

AK23

LVSSR_7

AK25

LVSSR_8

AJ21

LVSSR_9

AL23

LVSSR_10

AL25

LVSSR_11

AG18

LPVDD

AH18

LPVSS

M82-S A11

M82-S A11

THERMAL MONITOR

U8

U8

8

SCLK

7

SDATA

6

ALERT#

5

GND

ADM1032ARM

ADM1032ARM

VDD

D+

D-

THERM#

R98 10KR98 10K

VARY_BL

Control

Control

LVDS channel

LVDS channel

TXCLK_UP

TXCLK_UN
TXOUT_U0P
TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N

TXCLK_LP

TXCLK_LN
TXOUT_L0P
TXOUT_L0N
TXOUT_L1P
TXOUT_L1N
TXOUT_L2P
TXOUT_L2N
TXOUT_L3P
TXOUT_L3N

+3.3V_DELAY

1
2
3

MB_THERM#

4

C659

C659

0.1U

0.1U

10

10
X7R

X7R

DIGON

AA7
AC6

AD21
AE21
AJ24
AJ23
AK24
AL24
AG21
AH21
AG23
AH23

AL19
AK19
AJ20
AJ19
AK20
AL20
AK21
AL21
AK22
AL22

BIA_PWM

T18T18
T17T17

T16T16
T96T96

C137

C137
2200P

2200P

50

50
X7R

X7R

1

BIA_PWM 26

EN_LCDVDD 26

LCD_BCLK+ 26
LCD_BCLK- 26
LCD_B0+ 26
LCD_B0- 26
LCD_B1+ 26
LCD_B1- 26
LCD_B2+ 26
LCD_B2- 26

LCD_ACLK+ 26
LCD_ACLK- 26
LCD_A0+ 26
LCD_A0- 26
LCD_A1+ 26
LCD_A1- 26
LCD_A2+ 26
LCD_A2- 26

VGA_THERMDP 19

VGA_THERMDN 19

A A

SMBDAT242,43

5

4

+3.3V_DELAY

2

3 1

Q19 2N7002W-7-FQ19 2N7002W-7-F

GFX_SDATA

3

MB_THERM#
THERMAL_INT#

Title

Title

Title

M82S_MEMORY/LVDS/THERM

M82S_MEMORY/LVDS/THERM

M82S_MEMORY/LVDS/THERM

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

FX6 3A

Custom

FX6 3A

Custom

FX6 3A

Custom

Date: Sheet

Date: Sheet of

2

Date: Sheet of

R81 10KR81 10K
R73 10KR73 10K

1

22 70Tuesday, May 20, 2008

22 70Tuesday, May 20, 2008

22 70Tuesday, May 20, 2008

+3.3V_DELAY

of