QUANTA fm9b, fmd3a Schematics

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8

FM9B HANKS Intel UMA

VER : 3A
PWA:

A A

POWER

CONNECTOR

PG 53

SYSTEM
RESET CIRCUIT

BATT
CHARGER

RUN POWER SW

+3.3V_SUS/+5V_SUS
+5V/+3.3V/+1.8V

PG 42

PG 45

PG 52

Arrandale

FAN & THERMAL

SMSC1422

PG 38

CLOCK

SLG8SP585VTR
(QFN-32)

PG 15

POWER

+1.5V_SUS/+0.75V_DDR_VTT
+1.05V_PCH
+1.05V_VTT

DDR3-SODIMM1

B B

PG 13

DDR3-SODIMM2

PG 14

Dual Channel DDR3
800/1066 1.5V

SATA-ODD

PG 35

SATA

( rPGA 989 )

PG 3,4,5,6

DMI X 4FDI

LVDS
HDMI

PI3VDP411LSZDE

PG 23

VGA

SATA-HDD
& Fall Sensor

E-SATA Combo

C C

with USB CONN

PG 35

SN75LVCP412

PG 33PG 33

SATA

SATA

PCH

(HM55)

USB2.0 x 3
PCIEx1

PCIEx1
USB2.0

USB conn x 3

PG 33, 34

IHDA

PCIEx2
USB2.0

USB2.0 92HD73C

AUDIO/AMP

PG 39

Camera + D-MIC

PG 40

USB2.0

PG 7,8,9,10,11,12

SPI

LPC

Audio
SPK conn

PG 39 PG 40

D D

1

Audio
Jacks x3

USER
INTERFACE

PG 37

FLASH
4Mbyts

KBC

ITE8502

SPI PS/2

FLASH
1Mbyts

PG 30

2

3

17X8

PG 29

Touchpad

PG 36

PG 30

Keyboard

PG 36

4

5

6

PWB:

PG 47
PG 48

DC/DCAC/BATT

+3.3V_ALW/+5V_ALW/
+15V_ALW

PG 49

CPU VRREGULATOR

Panel Connector

HDMI CONN.

CRT CONN.

PG 24

PG 23

PG 25

LAN
RTL8111DL\RJ45\Transformer

EXPRESS/Card Reader/1394
R5U230

MINI-CARD

WLAN

MINI-CARD

WWAN

Bluetooth BTB Conn
BT365

Title

Title

Title

Schematic Block Diagram1

Schematic Block Diagram1

Schematic Block Diagram1

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

FM9B 3A

FM9B 3A

FM9B 3A

Date: Sheet of

Date: Sheet of

Date: Sheet of

PG 32

PG 31

PG 32

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

7

PG 51

PG 46

PG 41

PG 26,28

1 65Monday, October 05, 2009

1 65Monday, October 05, 2009

1 65Monday, October 05, 2009

8

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7

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Table of Contents Power States

PAGE DESCRIPTION

1

Schematic Block Diagram

2

Front Page

3-6

Clarksfield/Auburndale

7-12

PCH

13-14

A A

B B

DDRIII SO-DIMM(204P)

15

Clock Generator

16-22

BLANK PAGE

23

HDMI CONN

24

LCD CONN

25

CRT CONN

26

R5U230
BLANK PAGE

27
28

Express/CRard/1394

29

SIO (ITE8502)

30

FLASH / RTC

31

MINI-Card (WWAN)

32

MINI-Card (WLAN\WPAN)
Left PUSB/ESATA

33
34

Right USB
SATA (HDD & CD_ROM)

35

TP / KEYBOARD

36

SWITCH / /LED

37
38

FAN / THERMAL
Azelia CODEC

39
40

AUDIO CONN

41

LAN(RTL8111DL/RJ-45)

42

System Reset Circuit

43

Blank Page

44451.8V_RUN(RT9018/RT9024)

POWER PLANE

+PWR_SRC
+RTC_CELL

10V~+19V

+3.0V~+3.3V

24,30,45,46,47,48,49,50,51
08,11,29,30

DESCRIPTION

MAIN POWER
RTC

LARGE POWER S0~S537,46,52,53 MAIN POWER+5V+5V_ALW2
+5V_ALW
+3.3V_ALW
+5V_SUS
+3.3V_SUS
+1.5V_SUS
+0.75V_DDR_VTT
+5V_RUN
+3.3V_RUN
+1.8V_RUN
+1.05V_VTT 03,05,10,11,49,60+1.1V
+1.5V_RUN
+5V_HDD

+5V

+5V
+3.3V
+1.5V
+0.75V
+5V
+3.3V
+1.8V

+1.5V
+5V

13,33,44,46,47,48,49,50,51,52
29,30,35,36,37,42,44,45,46,47,51,52,53
11,33,34,37,51,52

07,08,09,10,11,13,14,19,24,28,29,37,41,42,44
,48,49,50,52

03,05,13,14,47,50,52
13,14,47,52
11,18,24,25,35,36,38,39,40,51,52

3,7,8,9,10,11,13,14,15,17,24,25,26,28,29,30
,31,32,33,35,37,38,39,40,41,42,46,51,52,60

05,11,44,52

11,28,31,32,52
35

LARGE POWER

8051 POWER 3.3V_ALW_ON S0~S5+3.3V

SLP_S5# CTRLD POWER

SLP_S5# CTRLD POWER

SODIMM POWER

SODIMM POWER

SLP_S3# CTRLD POWER

SLP_S3# CTRLD POWER

SDVO POWER

CPU POWER RUN_ON

Express Card/Min Card

HDD Power
+1.05V_PCH PCH POWER+1.05V 08,09,11,15,48 RUN_ON
+VCC_CORE
+LCDVCC
+5V_MOD

+0.7V~+1.77V

+3.3V
+5V

05,51
24
35

CPU CORE POWER

LCD Power

MOD Power

Charger (MAX8731)

46

3V/5V (TPS51427A)

1.5_DDR/0.75(TPS51116)

47

1.05V_PCH(TPS51218)

48

1.05_VTT(TPS51218)

C C

49
50

GFX_VCORE (MAX17028)

51

CPU CORE(MAX17036)

52

Run Power Switch
DCin & Batt

54

PAD & SCREW

55

EMI CAP

56

SMBUS BLOCK

57

THERMAL MAP

58

Power Block Diagram

59

Power sequence Block
XDP

60

GND PLANE PAGE

GND

ALL53

DESCRIPTION

CONTROL
SIGNAL

ALW_ON

SUS_ON
SUS_ON
SUS_ON
RUN_ON
RUN_ON
RUN_ON
RUN_ON

RUN_ON
HDDC_EN

IMVP_VR_ON
LCDVCC_TST_EN

& ENVDD
MODC_EN

ACTIVE INVOLTAGE PAGE

S0~S5
S0~S5

S0~S5

D D

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

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2

3

4

5

6

Date: Sheet of

COMPUTER

Index & Power Status

Index & Power Status

Index & Power Status

FM9B 3A

FM9B 3A

FM9B 3A

7

2 65Thursday, October 01, 2009

2 65Thursday, October 01, 2009

2 65Thursday, October 01, 2009

8

5

4

3

2

1

83

91

U26A

U26A

FDI_TXN0
FDI_TXN1
FDI_TXN2
FDI_TXN3
FDI_TXN4
FDI_TXN5
FDI_TXN6
FDI_TXN7

FDI_TXP0
FDI_TXP1
FDI_TXP2
FDI_TXP3
FDI_TXP4
FDI_TXP5
FDI_TXP6
FDI_TXP7

A24

DMI_RX#[0]

C23

DMI_RX#[1]

B22

DMI_RX#[2]

A21

DMI_RX#[3]

B24

DMI_RX[0]

D23

DMI_RX[1]

B23

DMI_RX[2]

A22

DMI_RX[3]

D24

DMI_TX#[0]

G24

DMI_TX#[1]

F23

DMI_TX#[2]

H23

DMI_TX#[3]

D25

DMI_TX[0]

F24

DMI_TX[1]

E23

DMI_TX[2]

G23

DMI_TX[3]

E22

FDI_TX#[0]

D21

FDI_TX#[1]

D19

FDI_TX#[2]

D18

FDI_TX#[3]

G21

FDI_TX#[4]

E19

FDI_TX#[5]

F21

FDI_TX#[6]

G18

FDI_TX#[7]

D22

FDI_TX[0]

C21

FDI_TX[1]

D20

FDI_TX[2]

C18

FDI_TX[3]

G22

FDI_TX[4]

E20

FDI_TX[5]

F20

FDI_TX[6]

G19

FDI_TX[7]

F17

FDI_FSYNC[0]

E17

FDI_FSYNC[1]

C17

FDI_INT

F18

FDI_LSYNC[0]

D17

FDI_LSYNC[1]

Clarksfield/Auburndale

Clarksfield/Auburndale

R96

R96

49.9/F

49.9/F

+1.05V_VTT

R95

R95

49.9/F

49.9/F

R91

R91
*68_NC

*68_NC

DMI_TXN07

D D

C C

B B

A A

DMI_TXN17
DMI_TXN27
DMI_TXN37

DMI_TXP07
DMI_TXP17
DMI_TXP27
DMI_TXP37

DMI_RXN07
DMI_RXN17
DMI_RXN27
DMI_RXN37

DMI_RXP07
DMI_RXP17
DMI_RXP27
DMI_RXP37

FDI_TXN[7:0]7

FDI_TXP[7:0]7

FDI_FSYNC07
FDI_FSYNC17

FDI_LSYNC07
FDI_LSYNC17

FDI_INT7

Processor
Pullups

H_CATERR#
H_PROCHOT#_D
H_CPURST#

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RBIAS
PEG_RX#[0]

PEG_RX#[1]
PEG_RX#[2]

DMI Intel(R) FDI

DMI Intel(R) FDI

PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]

PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]

PCI EXPRESS -- GRAPHICS

PCI EXPRESS -- GRAPHICS

PEG_TX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

Processor Compensation Signals

B26
A26
B27
A25

K35
J34
J33
G35
G32
F34
F31
D35
E33
C33
D32
B32
C31
B28
B30
A31

J35
H34
H33
F35
G33
E34
F32
D34
F33
B33
D31
A32
C30
A28
B29
A30

L33
M35
M33
M30
L31
K32
M29
J31
K29
H30
H29
F29
E28
D29
D27
C26

L34
M34
M32
L30
M31
K31
M28
H31
K28
G30
G29
F28
E27
D28
C27
C25

PEG_ICOMPI

R137

R137

49.9/F

49.9/F

R72

R72

49.9/F

49.9/F

R370 49.9/FR370 49.9/F

R368 750/FR368 750/F

R138

R138

R139

R139

20/F

20/F

20/F

20/F

H_COMP0
H_COMP1
H_COMP2
H_COMP3

+1.5V_SUS

R140

R140

1.1K/F

1.1K/F

R141

R141
3K/F

3K/F

30

88

PM_DRAM_PWRGD

Q2

H_CPUDET#29

H_PECI10

H_THERM10

H_CPURST#60

PM_SYNC7

H_PWRGOOD10,60

PM_DRAM_PWRGD7

H_VTTPWRGD42

H_PWRGD_XDP60

PLTRST#9,26,28,29,31,32,41

R230 *0_shortR230 *0_short

R136 *0_shortR136 *0_short

R178 *0_shortR178 *0_short

R143 1.5K/FR143 1.5K/F

DDR3 Compensation Signals

SM_RCOMP_2
SM_RCOMP_1
SM_RCOMP_0

R112

R112

R113

R113

R114

R114
130/F

130/F

24.9/F

24.9/F

100/F

100/F

H_COMP3
H_COMP2
H_COMP1
H_COMP0

TP_SKT0CC#

H_CATERR#

H_PECI_ISO

H_PROCHOT#_D

H_CPURST#

PM_DRAM_PWRGD

R142

R142
750/F

750/F

U26B

U26B

AT23

COMP3

AT24

COMP2

G16

COMP1

AT26

COMP0

AH24

SKTOCC#

AK14

CATERR#

AT15

PECI

AN26

PROCHOT#

AK15

THERMTRIP#

AP26

RESET_OBS#

AL15

PM_SYNC

AN14

VCCPWRGOOD_1

AN27

VCCPWRGOOD_0

AK13

SM_DRAMPWROK

AM15

VTTPWRGOOD

AM26

TAPPWRGOOD

AL14

RSTIN#

Clarksfield/Auburndale

Clarksfield/Auburndale

CPU THERMTRIP

H_THERM

MMST3904-7-F

MMST3904-7-F

83

91

MISC THERMAL

MISC THERMAL

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLOCKS

CLOCKS

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

PM_EXT_TS#[0]
PM_EXT_TS#[1]

DDR3

MISC

DDR3

MISC

PWR MANAGEMENT

PWR MANAGEMENT

JTAG & BPM

JTAG & BPM

BCLK

BCLK#

BCLK_ITP

BCLK_ITP#

PEG_CLK

PEG_CLK#

PRDY#

PREQ#

TRST#

TDI_M

TDO_M

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

A16
B16

AR30
AT30

E16
D16

A18
A17

F6

SM_RCOMP_0

AL1

SM_RCOMP_1

AM1

SM_RCOMP_2

AN1
AN15

AP15

AT28

XDP_PREQ#

AP27

XDP_TCLK

AN28

TCK

XDP_TMS

AP28

TMS

XDP_TRST#

AT27

XDP_TDI_R

AT29

TDI

XDP_TDO_R

AR27

TDO

XDP_TDI_M

AR29

XDP_TDO_M

AP29

H_DBR#_R

AN25

XDP_OBS0_R

AJ22

XDP_OBS1_R

AK22

XDP_OBS2_R

AK24

XDP_OBS3_R

AJ24

XDP_OBS4_R

AJ25

XDP_OBS5_R

AH22

XDP_OBS6_R

AK23

XDP_OBS7_R

AH23

CLK_CPU_BCLK 10
CLK_CPU_BCLK# 10

BCLK_ITP 60
BCLK_ITP# 60

CLK_PCIE_3GPLL 9
CLK_PCIE_3GPLL# 9

DREFSSCLK 9
DREFSSCLK# 9

DDR3_DRAMRST# 13,14

R154 10KR154 10K
R155 10KR155 10K

R153 *0_shortR153 *0_short
R177 *0_shortR177 *0_short

XDP_PRDY# 60
XDP_PREQ# 60

XDP_TCLK 60
XDP_TMS 60
XDP_TRST# 60

T39T39
T38T38
T40T40

R119 *0_shortR119 *0_short

R106 *0_shortR106 *0_short
R120 *0_shortR120 *0_short
R110 *0_shortR110 *0_short
R105 *0_shortR105 *0_short
R108 *0_shortR108 *0_short
R109 *0_shortR109 *0_short
R121 *0_shortR121 *0_short
R111 *0_shortR111 *0_short

XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3
XDP_OBS4
XDP_OBS5
XDP_OBS6
XDP_OBS7

R156

R156

*12.4K/F_NC

*12.4K/F_NC

+1.05V_VTT

PM_EXTTS#0 13
PM_EXTTS#1 14

Q2

XDP_DBRESET# 7,60
XDP_OBS[0:7] 60

12
12

Q2

2

Q11

Q11

T7T7

T3T3

+3.3V_RUN

1 3

XDP_TMS
XDP_TDI_R
XDP_PREQ#
XDP_TCLK

R198

R198
10M

10M

2

12

C227

C227

0.1U

0.1U

16

16

PM_THRMTRIP# 46

31

Q12

Q12
2N7002W-7-F

2N7002W-7-F

R89 *51_NCR89 *51_NC
R435 *51_NCR435 *51_NC
R90 *51_NCR90 *51_NC
R104 *51_NCR104 *51_NC

+1.05V_VTT

XDP_TDI_R
XDP_TDO_M

XDP_TDI_M
XDP_TDO_R

R415 0R415 0

R416 *0_NCR416 *0_NC
R4020R402
0

R414 *0_NCR414 *0_NC

R417 0R417 0

XDP_TDI 60
XDP_TDO 60

XDP_TRST#

R43451R434
51

QUANTA

QUANTA

QUANTA

COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

COMPUTER

AUBURNDA 1/4

AUBURNDA 1/4

AUBURNDA 1/4

FM9B 3A

FM9B 3A

FM9B 3A

1

3 65Thursday, October 01, 2009

3 65Thursday, October 01, 2009

3 65Thursday, October 01, 2009

5

4

3

2

1

83

U26C

U26C

91

D D

M_A_DQ[63:0]13

C C

B B

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

M_A_BS013
M_A_BS113
M_A_BS213

M_A_CAS#13
M_A_RAS#13
M_A_WE#13

C10

D10

H10

G10

AH5
AF5
AK6
AK7
AF6
AG5

AJ10
AL10

AK12

AK8

AK11

AN8

AM10

AR11
AL11

AM9

AN9
AT11
AP12

AM12

AN12

AM13

AT14
AT12
AL13
AR14
AP14

AC3

AB2

AE1

AB3

AE9

A10

B10
E10

F10

J10

AJ7
AJ6

AJ9

AL7
AL8

C7

A7

A8

D8

E6
F7
E9
B7
E7

C6
G8

K7

J8

G7

J7

L7
M6
M8

L9

L6

K8
N8

P9

U7

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

AUBURNDALE/CLARKSFIELD PROCESSOR (DDR3)

AA6

SA_CK[0]

AA7

SA_CK#[0]

P7

SA_CKE[0]

Y6

SA_CK[1]

Y5

SA_CK#[1]

P6

SA_CKE[1]

AE2

SA_CS#[0]

AE8

SA_CS#[1]

AD8

SA_ODT[0]

AF9

SA_ODT[1]

M_A_DM0

B9

SA_DM[0]
SA_DM[1]
SA_DM[2]
SA_DM[3]
SA_DM[4]
SA_DM[5]
SA_DM[6]
SA_DM[7]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

D7
H7
M7
AG6
AM7
AN10
AN13

C9
F8
J9
N9
AH7
AK9
AP11
AT13

C8
F9
H9
M9
AH8
AK10
AN11
AR13

Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9

M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7

M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

M_A_CLK0 13
M_A_CLK0# 13
M_A_CKE0 13

M_A_CLK1 13
M_A_CLK1# 13
M_A_CKE1 13

M_A_CS0# 13
M_A_CS1# 13

M_A_ODT0 13
M_A_ODT1 13

M_A_DM[7:0] 13

M_A_DQS#[7:0] 13

M_A_DQS[7:0] 13

M_A_A[15:0] 13

M_B_DQ[63:0]14

M_B_BS014
M_B_BS114
M_B_BS214

M_B_CAS#14
M_B_RAS#14
M_B_WE#14

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60M_A_A0
M_B_DQ61
M_B_DQ62
M_B_DQ63

91

AF3
AG1

AK1
AG4
AG3

AH4
AK3

AK4
AM6
AN2

AK5

AK2
AM4
AM3

AP3
AN5

AT4
AN6
AN4
AN3

AT5

AT6
AN7

AP6

AP8

AT9

AT7

AP9

AR10
AT10

AB1

AC5

AC6

AJ3

AJ4

W5

B5
A5
C3
B3
E4
A6
A4
C4
D1
D2
F2
F1
C2
F5
F3
G4
H6
G2

J6

J3
G1
G5

J2

J1

J5
K2

L3
M1
K5
K4
M4
N5

R7

Y7

U26D

U26D

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

83

W8

SB_CK[0]

W9

SB_CK#[0]

M3

SB_CKE[0]

V7

SB_CK[1]

V6

SB_CK#[1]

M2

SB_CKE[1]

AB8

SB_CS#[0]

AD6

SB_CS#[1]

AC7

SB_ODT[0]

AD1

SB_ODT[1]

M_B_DM0

D4

SB_DM[0]
SB_DM[1]
SB_DM[2]
SB_DM[3]
SB_DM[4]
SB_DM[5]
SB_DM[6]
SB_DM[7]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

DDR SYSTEM MEMORY - B

DDR SYSTEM MEMORY - B

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

E1
H3
K1
AH1
AL2
AR4
AT8

D5
F4
J4
L4
AH2
AL4
AR5
AR8

C5
E3
H4
M5
AG2
AL5
AP5
AR7

U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1

M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7

M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

M_B_CLK0 14
M_B_CLK0# 14
M_B_CKE0 14

M_B_CLK1 14
M_B_CLK1# 14
M_B_CKE1 14

M_B_CS0# 14
M_B_CS1# 14

M_B_ODT0 14
M_B_ODT1 14

M_B_DM[7:0] 14

M_B_DQS#[7:0] 14

M_B_DQS[7:0] 14

M_B_A[15:0] 14

Clarksfield/Auburndale

Clarksfield/Auburndale

A A

5

Channel A DQ[15,32,48,54], DM[5]
Requires minimum 12mils spacing
with all other signals, including data signals.

4

Channel B DQ[16,18,36,42,56,57,60,61,62]
Requires minimum 12mils spacing
with all other signals, including data signals.

3

Clarksfield/Auburndale

Clarksfield/Auburndale

2

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

COMPUTER

AUBURNDA 2/4

AUBURNDA 2/4

AUBURNDA 2/4

FM9B 3A

FM9B 3A

FM9B 3A

4 65Thursday, October 01, 2009

4 65Thursday, October 01, 2009

4 65Thursday, October 01, 2009

1

5

91

U26F

CPU Core Power

U26F

83

+VCC_CORE

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

D D

C C

B B

A A

VCC6

AG29

VCC7

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

Clarksfield/Auburndale

Clarksfield/Auburndale

1.1V RAIL POWER

1.1V RAIL POWER

CPU CORE SUPPLY

CPU CORE SUPPLY

POWER

POWER

PROC_DPRSLPVR

CPU VIDS

CPU VIDS

VSS_SENSE_VTT

SENSE LINES

SENSE LINES

VTT0_1
VTT0_2
VTT0_3
VTT0_4
VTT0_5
VTT0_6
VTT0_7
VTT0_8

VTT0_9
VTT0_10
VTT0_11
VTT0_12
VTT0_13
VTT0_14
VTT0_15
VTT0_16
VTT0_17
VTT0_18
VTT0_19
VTT0_20
VTT0_21
VTT0_22
VTT0_23
VTT0_24
VTT0_25
VTT0_26
VTT0_27
VTT0_28
VTT0_29
VTT0_30
VTT0_31
VTT0_32

VTT0_33
VTT0_34
VTT0_35
VTT0_36
VTT0_37
VTT0_38
VTT0_39
VTT0_40
VTT0_41
VTT0_42
VTT0_43
VTT0_44

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

VTT_SELECT

ISENSE

VCC_SENSE
VSS_SENSE

VTT_SENSE

AH14
AH12
AH11
AH10
J14
J13
H14
H12
G14
G13
G12
G11
F14
F13
F12
F11
E14
E12
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

AF10
AE10
AC10
AB10
Y10
W10
U10
T10
J12
J11
J16
J15

VTT0_43,VTT0_44:
CRB(V1.0)P13
Why add 0ohm?? Is it trace width control??

VTT0_43,VTT0_44:(Intel feedback)
They are connected to hidden page for
intel validation purpose.

AN33

PSI#

VID0

AK35

VID1

AK33

VID2

AK34

VID3

AL35

VID4

AL33

VID5

AM33

VID6

AM35

DPRSLPVR

AM34

G15

AN35

AJ34
AJ35

B15

TP_VSS_SENSE_VTT

A15

VSS_SENSE_VTT:
SC(V1.0)P20
Connect VSS_SENSE_VTT to GND
or can be left floating.
Note: CRB has the VSS_SENSE_VTT floating.

AUBURNDALE/CLARKSFIELD PROCESSOR (POWER)

5

C440

C440
10U

10U

C29

C29
22U

22U

C408

C408
22U

22U

4

C99

C99
10U

10U

+1.05V_VTT

C28

C28
22U

22U

C55

C55
22U

22U

H_PSI# 51

VID0 51
VID1 51
VID2 51
VID3 51
VID4 51
VID5 51
VID6 51
DPRSLPVR 51

T5T5

I_MON 51

VTT_SENSE 49

T36T36

4

+1.05V_VTT

C56

C119

C119
10U

10U

C409

C409
22U

22U

C79

C79
10U

10U

+VCC_GFX_CORE

+1.05V_VTT

C56

C25

C25

10U

10U

10U

10U

+

+

C209

C209

C186

C186

330U

330U

22U

22U

7343

7343

2.5

2.5

+1.05V_VTT

C77

C77
10U

10U

C208

C208
22U

22U

C406

C406
*10U_NC

*10U_NC

C185

C185
10U

10U

3

C441

C441
22U

22U

C422

C423

C423

22U

22U

22U

22U

56

+VCC_CORE

VCC_SENSE & VSS_SENSE:
SC(V1.0)P19

R380

R380

100- ±1% pull-down to GND near processor

100/F

100/F

VCCSENSE 51
VSSSENSE 51

R381

R381
100/F

100/F

PROC_DPRSLPVR:
SC(V1.0)P19:
It is important to have the resistor stuffing options
in the design f or the Turbo fu nctionality.
The stuffing an d no-stuffing o f the resistors
will depend on the POC configu ration of AUB
and CFD
CRB(V1.0)P67:
uses 1K pull-up and pull-down resistors
CRB default set ting is "1"

C385

C385
22U

22U

C407

C407
*10U_NC

*10U_NC

C187

C187
10U

10U

C120

C120
22U

22U

3

AUBURNDALE/CLARKSFIELD PROCESSOR (GRAPHICS POWER)

83

91

U26G

U26G

AT21

VAXG1

AT19

VAXG2

AT18

VAXG3

AT16

VAXG4

AR21

VAXG5

AR19

VAXG6

AR18

VAXG7

AR16

VAXG8

AP21

VAXG9

AP19

VAXG10

AP18

VAXG11

AP16

VAXG12

AN21

VAXG13

AN19

VAXG14

AN18

VAXG15

AN16

VAXG16

AM21

VAXG17

AM19

VAXG18

AM18

VAXG19

AM16

VAXG20

AL21

VAXG21

AL19

VAXG22

AL18

VAXG23

AL16

VAXG24

AK21

VAXG25

AK19

VAXG26

AK18

VAXG27

AK16

VAXG28

AJ21

VAXG29

AJ19

VAXG30

AJ18

VAXG31

AJ16

VAXG32

AH21

VAXG33

AH19

VAXG34

AH18

VAXG35

AH16

VAXG36

J24

VTT1_45

J23

VTT1_46

H25

VTT1_47

K26

VTT1_48

J27

VTT1_49

J26

C405

C405
22U

22U

VTT1_50

J25

VTT1_51

H27

VTT1_52

G28

VTT1_53

G27

VTT1_54

G26

VTT1_55

F26

VTT1_56

E26

VTT1_57

E25

VTT1_58

Clarksfield/Auburndale

Clarksfield/Auburndale

Note:
For Validating IMVP VR R814 should be STUFF
and R827 NO_STUFF

3

2

GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
GFX_VID[4]
GFX_VID[5]
GFX_VID[6]

GFX_VR_EN

GFX_IMON

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18

VTT0_59
VTT0_60
VTT0_61
VTT0_62

VTT1_63
VTT1_64
VTT1_65
VTT1_66
VTT1_67
VTT1_68

VCCPLL1
VCCPLL2
VCCPLL3

R191KR19
1K

R358

R358
*1K_NC

*1K_NC

R201KR20
1K

R357

R357
*1K_NC

*1K_NC

AR22
AT22

AM22
AP22
AN22
AP23
AM23
AP24
AN24

AR25
AT25
AM24

AJ1
AF1
AE7
AE4
AC1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1

P10
N10
L10
K10

J22
J20
J18
H21
H20
H19

L26
L27
M26

R211KR21
1K

R356

R356
*1K_NC

*1K_NC

VAXG_SENSE

VSSAXG_SENSE

SENSE

LINES

SENSE

LINES

GRAPHICS

GRAPHICS

GFX_DPRSLPVR

GRAPHICS VIDs

GRAPHICS VIDs

FDI PEG & DMI

FDI PEG & DMI

POWER

POWER

DDR3 - 1.5V RAILS

DDR3 - 1.5V RAILS

1.1V1.8V

1.1V1.8V

VID0
VID1
VID2
VID3
VID4
VID5
VID6
DPRSLPVR
H_PSI#

+1.05V_VTT

R22

R22
*1K_NC

*1K_NC

R3551KR355
1K

GFXVR_EN

C801UC80
1U

C511UC51
1U

R23

R23
*1K_NC

*1K_NC

R3541KR354
1K

VCC_AXG_SENSE 50
VSS_AXG_SENSE 50

GFXVR_VID_0 50
GFXVR_VID_1 50
GFXVR_VID_2 50
GFXVR_VID_3 50
GFXVR_VID_4 50
GFXVR_VID_5 50
GFXVR_VID_6 50

GFXVR_DPRSLPVR 50

R413 *1K/F_NCR413 *1K/F_NC

C821UC82

C1001UC100

1U

1U

C98

C98

C78

C78

10U

10U

10U

10U

C404

C404

C381

C381

22U

22U

22U

22UC422

C54

C54

C521UC52

2.2U

2.2U

1U

R241KR24

R25

R25

1K

*1K_NC

*1K_NC

R3521KR352

R353

R353

1K

*1K_NC

*1K_NC

2

R92 4.7K/FR92 4.7K/F

+1.5V_SUS

C1011UC101

C811UC81

1U

1U

+

+

C137

C137

C165

C165

330U

330U

22U

22U

7343

7343

2.5

2.5

+1.05V_VTT

+

+

C23

C23
*330U_NC

*330U_NC

7343

7343

2.5

2.5

+1.8V_RUN

C53

C53

C411

C411

4.7U/6.3V

4.7U/6.3V

22U

22U

R400

R400

R3991KR399

*1K_NC

*1K_NC

1K

R3981KR398

R397

R397

1K

*1K_NC

*1K_NC

GFXVR_EN 50

GFXVR_IMON 50

+VCC_CORE

C102

C102
22U

22U

C113

C113
22U

22U

C412

C412
22U

22U

C94

C94

C117

C117

10U

10U

10U

10U

C97

C97

C112

C112

10U

10U

10U

10U

+

+

+

+

C71

C71
*470U_NC

*470U_NC

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

COMPUTER

AUBURNDA 3/4

AUBURNDA 3/4

AUBURNDA 3/4

FM9B 3A

FM9B 3A

FM9B 3A

C114

C114
22U

22U

C69

C69
22U

22U

C76

C76
330U

330U

2

2
7343

7343

1

C410

C410
22U

22U

C72

C72
22U

22U

C92

C92

C96

C96

10U

10U

10U

10U

C93

C93

C75

C75

10U

10U

10U

10U

C115

C115

C456

22U

22U

C455

C455
22U

22U

C443

C443
10U

10U

C118

C118
10U

10U

C456
22U

22U

C397

C397
22U

22U

C442

C442
10U

10U

C425

C425
10U

10U

C116

C116
22U

22U

C73

C73
22U

22U

C426

C426

C95

C95

10U

10U

10U

10U

C74

C74

C70

C70

10U

10U

10U

10U

80

5 65Thursday, October 01, 2009

5 65Thursday, October 01, 2009

1

5 65Thursday, October 01, 2009

5

AUBURNDALE/CLARKSFIELD PROCESSOR (GND) AUBURNDALE/CLARKSFIELD PROCESSOR( RESERVED, CFG)

91

AT20
AT17
AR31
AR28
AR26
AR24
AR23
AR20
AR17

D D

AR15
AR12

AP20
AP17
AP13
AP10

AN34
AN31
AN23
AN20

AN17
AM29
AM27
AM25
AM20
AM17
AM14
AM11

AL34

AL31

C C

AL23

AL20

AL17

AL12

AK29

AK27

AK25

AK20

AK17

AJ31

AJ23

AJ20

AJ17

AJ14

AJ11

AH35
AH34
AH33
AH32
AH31
AH30
AH29

B B

AH28
AH27
AH26
AH20
AH17
AH13

AG10

AE35

83 83 83

U26H

U26H

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11

AR9

VSS12

AR6

VSS13

AR3

VSS14
VSS15
VSS16
VSS17
VSS18

AP7

VSS19

AP4

VSS20

AP2

VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33

AM8

VSS34

AM5

VSS35

AM2

VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42

AL9

VSS43

AL6

VSS44

AL3

VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56

AJ8

VSS57

AJ5

VSS58

AJ2

VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72

AH9

VSS73

AH6

VSS74

AH3

VSS75
VSS76

AF8

VSS77

AF4

VSS78

AF2

VSS79
VSS80

Clarksfield/Auburndale

Clarksfield/Auburndale

VSS

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30

U26I

U26I

91 91

K27

VSS161

K9

VSS162

K6

VSS163

K3

VSS164

J32

VSS165

J30

VSS166

J21

VSS167

J19

VSS168

H35

VSS169

H32

VSS170

H28

VSS171

H26

VSS172

H24

VSS173

H22

VSS174

H18

VSS175

H15

VSS176

H13

VSS177

H11

VSS178

H8

VSS179

H5

VSS180

H2

VSS181

G34

VSS182

G31

VSS183

G20

VSS184

G9

VSS185

G6

VSS186

G3

VSS187

F30

VSS188

F27

VSS189

F25

VSS190

F22

VSS191

F19

VSS192

F16

VSS193

E35

VSS194

E32

VSS195

E29

VSS196

E24

VSS197

E21

VSS198

E18

VSS199

E13

VSS200

E11

VSS201

E8

VSS202

E5

VSS203

E2

VSS204

D33

VSS205

D30

VSS206

D26

VSS207

D9

VSS208

D6

VSS209

D3

VSS210

C34

VSS211

C32

VSS212

C29

VSS213

C28

VSS214

C24

VSS215

C22

VSS216

C20

VSS217

C19

VSS218

C16

VSS219

B31

VSS220

B25

VSS221

B21

VSS222

B18

VSS223

B17

VSS224

B13

VSS225

B11

VSS226

B8

VSS227

B6

VSS228

B4

VSS229

A29

VSS230

A27

VSS231

A23

VSS232

A9

VSS233

Clarksfield/Auburndale

Clarksfield/Auburndale

4

VSS

VSS

3

AP25

AL25
AL24
AL22
AJ33

+M_VREF_DQ_DIMM0
+M_VREF_DQ_DIMM1

CFG0

AM30
AM28
AP31

CFG3

AL32

CFG4

AL30
AM31
AN29

CFG7

AM32
AK32
AK31
AK28

AJ28
AN30
AN32

AJ32

AJ29

AJ30
AK30

AT35

VSS_NCTF1

AT1

VSS_NCTF2

AR34

VSS_NCTF3

B34

VSS_NCTF4

B2

VSS_NCTF5

B1

VSS_NCTF6

A35

VSS_NCTF7

NCTF

NCTF

R71 *0_shortR71 *0_short
R369 *0_shortR369 *0_short

TP_RSVD17_R
TP_RSVD18_R

Q2

U26E

U26E

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5

AG9

RSVD6

M27

RSVD7

L28

RSVD8

J17

SA_DIMM_VREF

H17

SB_DIMM_VREF

G25

RSVD11

G17

RSVD12

E31

RSVD13

E30

RSVD14

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]

H16

RSVD_TP_86

B19

RSVD15

A19

RSVD16

A20

RSVD17

B20

RSVD18

U9

RSVD19

T9

RSVD20

AC9

RSVD21

AB9

RSVD22

C1

RSVD_NCTF_23

A3

RSVD_NCTF_24

J29

RSVD26

J28

RSVD27

A34

RSVD_NCTF_28

A33

RSVD_NCTF_29

C35

RSVD_NCTF_30

B35

RSVD_NCTF_31

Clarksfield/Auburndale

Clarksfield/Auburndale

2

AJ13

RSVD32

AJ12

RSVD33

AH25

RSVD34

AK26

RSVD35

AL26

RSVD36

RSVD38
RSVD39

RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
RSVD53

RSVD58

KEY
RSVD62
RSVD63
RSVD64
RSVD65

AR2
AJ26

AJ27

AP1
AT2

AT3
AR1

AL28
AL29
AP30
AP32
AL27
AT31
AT32
AP33
AR33
AT33
AT34
AP35
AR35
AR32

E15
F15
A2
D15
C15
AJ15
AH15

RSVD64_R
RSVD65_R

RESERVED

RESERVED

RSVD_NCTF_37

RSVD_NCTF_40
RSVD_NCTF_41

RSVD_NCTF_42
RSVD_NCTF_43

RSVD_NCTF_54
RSVD_NCTF_55
RSVD_NCTF_56
RSVD_NCTF_57

RSVD_TP_59
RSVD_TP_60

1

R93 *0_shortR93 *0_short
R94 *0_shortR94 *0_short

Q2

VSS

AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3

V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9

AP34

Q2

Can be left NC is Intel CRM

R396

R396

implementation; ESD/DG

*0_short

*0_short

recommendation to GND

RSVD_TP_66
RSVD_TP_67
RSVD_TP_68
RSVD_TP_69
RSVD_TP_70
RSVD_TP_71
RSVD_TP_72
RSVD_TP_73
RSVD_TP_74
RSVD_TP_75

RSVD_TP_76
RSVD_TP_77
RSVD_TP_78
RSVD_TP_79
RSVD_TP_80
RSVD_TP_81
RSVD_TP_82
RSVD_TP_83
RSVD_TP_84
RSVD_TP_85

1 0

CFG4

A A

The Clarkfield processor's PCI Express interface may
not meet PCI Express 2.0 jitter specifications. Intel
recommends placing a 3.01K +/- 5% pull down resistor to
VSS on CFG[7] pin for both rPGA and BGA components.
This pull down resistor should be removed when this
issue is fixed.

5

22

CFG0
CFG3
CFG4
CFG7

4

R176 *3.01K/F_NCR176 *3.01K/F_NC
R107 *3.01K/F_NCR107 *3.01K/F_NC
R174 *3.01K/F_NCR174 *3.01K/F_NC
R175 *3.01K/F_NCR175 *3.01K/F_NC

(Display Port
Presence)

CFG0
(PCI-Epress
Configuration Select)

CFG3
(PCI-Epress Static
Lane Reversal)

Disabled; No Physical Display Port
attached to Embedded Diplay Port

Single PEG

Normal Operation Lane Numbers Reversed

3

Enabled; An external Display port
device is connected to the Embedded
Display port

Bifurcation enabled

2

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

COMPUTER

AUBURNDA 4/4

AUBURNDA 4/4

AUBURNDA 4/4

FM9B 3A

FM9B 3A

FM9B 3A

1

6 65Thursday, October 01, 2009

6 65Thursday, October 01, 2009

6 65Thursday, October 01, 2009

5

4

3

2

1

IBEX PEAK-M (DMI,FDI,GPIO)

858592

U29C

U29C

DMI_RXN03

D D

C C

B B

DMI_RXN13
DMI_RXN23
DMI_RXN33

DMI_RXP03
DMI_RXP13
DMI_RXP23
DMI_RXP33

DMI_TXN03
DMI_TXN13
DMI_TXN23
DMI_TXN33

DMI_TXP03
DMI_TXP13
DMI_TXP23
DMI_TXP33

+1.05V_PCH

XDP_DBRESET#3,60

PCH_PWRGD29

R374 49.9/FR374 49.9/F

R165 *0_shortR165 *0_short

R458 *0_shortR458 *0_short

R167 *0_shortR167 *0_short

Q2

PM_DRAM_PW RGD3

ICH_RSMRST#29

SUS_PWR_ACK29

SIO_PWRBTN#29

AC_PRESENT29

DMI_ZCOMP

SYS_PWROK

PWROK

MEPWROK

LAN_RST#

ICH_RSMRST#

PM_BATLOW#

PM_RI#

107

+3.3V_RUN

CLKRUN#
LCD_DDCDAT
LCD_DDCCLK
L_CTRL_CLK
L_CTRL_DATA

A A

XDP_DBRESET#

37

PM_RI#
PCIE_WAKE#
PM_BATLOW#

R410 10KR410 10K
R132 2.2KR132 2.2K
R133 2.2KR133 2.2K
R134 10KR134 10K
R135 10KR135 10K
R350 1KR350 1K

R480 10KR480 10K
R188 1KR188 1K
R465 8.2KR465 8.2K

12
12

5

PCH_PWRGD
ICH_RSMRST#
LAN_RST#

+3.3V_SUS

BC24

DMI0RXN

BJ22

DMI1RXN

AW20

DMI2RXN

BJ20

DMI3RXN

BD24

DMI0RXP

BG22

DMI1RXP

BA20

DMI2RXP

BG20

DMI3RXP

BE22

DMI0TXN

BF21

DMI1TXN

BD20

DMI2TXN

BE18

DMI3TXN

BD22

DMI0TXP

BH21

DMI1TXP

BC20

DMI2TXP

BD18

DMI3TXP

BH25

DMI_ZCOMP

BF25

DMI_IRCOMP

T6

SYS_RESET#

M6

SYS_PWROK

B17

PWROK

K5

MEPWROK

A10

LAN_RST#

D9

DRAMPWROK

C16

RSMRST#

M1

SUS_PWR_DN_ACK / GPIO30

P5

PWRBTN#

P7

ACPRESENT / GPIO31

A6

BATLOW# / GPIO72

F14

RI#

IbexPeak-M_R1P0

IbexPeak-M_R1P0

107

R168 10KR168 10K
R477 10KR477 10K
R461 10KR461 10K

115

DMI

FDI

DMI

FDI

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

System Power Management

System Power Management

SLP_LAN# / GPIO29

Close to VGA side

PANEL_BKEN

4

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1

SLP_S4#

SLP_S3#

SLP_M#

PMSYNCH

VGA_BLU
VGA_GRN
VGA_RED

ENVDD

FDI_INT

WAKE#

BA18
BH17
BD16
BJ16
BA16
BE14
BA14
BC12

BB18
BF17
BC16
BG16
AW16
BD14
BB14
BD12

BJ14
BF13
BH13
BJ12
BG14

PCIE_WAKE#

J12

CLKRUN#

Y1

RSV_LPCPD#

P8

ICH_SUSCLK

F3

SLP_S5#_R

E4

SLP_S4#_R

H7

SLP_S3#_R

P12

SLP_M#_R

K8

N2

TP23

BJ10

PM_SLP_LAN#_R

F6

R405 150/FR405 150/F
R404 150/FR404 150/F
R403 150/FR403 150/F
R173 100KR173 100K
R170 100KR170 100K

FDI_TXN0 3
FDI_TXN1 3
FDI_TXN2 3
FDI_TXN3 3
FDI_TXN4 3
FDI_TXN5 3
FDI_TXN6 3
FDI_TXN7 3

FDI_TXP0 3
FDI_TXP1 3
FDI_TXP2 3
FDI_TXP3 3
FDI_TXP4 3
FDI_TXP5 3
FDI_TXP6 3
FDI_TXP7 3

FDI_INT 3
FDI_FSYNC0 3
FDI_FSYNC1 3
FDI_LSYNC0 3
FDI_LSYNC1 3

PCIE_WAKE# 28,32,41

CLKRUN# 29

T15T15

T50T50

SIO_SLP_S5# 29

T60T60

82

SIO_SLP_S3# 29

T24T24

T37T37

PM_SYNC 3

T22T22

PANEL_BKEN29

ENVDD24

BIA_PWM24

LCD_DDCCLK24
LCD_DDCDAT24

T12

T12

LCD_ACLK-24
LCD_ACLK+24

LCD_A0-24
LCD_A1-24
LCD_A2-24

T11

T11

LCD_A0+24
LCD_A1+24
LCD_A2+24

T10

T10

LCD_BCLK-24
LCD_BCLK+24

LCD_B0-24
LCD_B1-24
LCD_B2-24

Q5

LCD_B0+24
LCD_B1+24
LCD_B2+24

VGA_BLU25
VGA_GRN25
VGA_RED25

G_CLK_DDC225
G_DAT_DDC225

VGAHSYNC25
VGAVSYNC25

PANEL_BKEN
ENVDD

LCD_DDCCLK
LCD_DDCDAT

L_CTRL_CLK
L_CTRL_DATA

R118 2.37KR118 2.37K

LVDS_VBG

PAD

PAD

LVDSA_DATA#3

PAD

PAD

LVDSA_DATA3

PAD

PAD

Q5

R528 33R528 33
R529 33R529 33

76

R131 1KR131 1K

VGA_BLU
VGA_GRN
VGA_RED

For UMA HDMI Function

+3.3V_RUN

12
12
12
12
12

3

DPB_LANE0_N
DPB_LANE0_P

DPB_LANE1_N
DPB_LANE1_P

DPB_LANE2_N
DPB_LANE2_P

DPB_LANE3_N
DPB_LANE3_P

IBEX PEAK-M (LVDS,DDI)

92

115

LVDS

LVDS

CRT

CRT

MB_HDMID_SCL
MB_HDMID_SDA

HDMID_DATA2_N 23
HDMID_DATA2_P 23

HDMID_DATA1_N 23
HDMID_DATA1_P 23

HDMID_DATA0_N 23
HDMID_DATA0_P 23

HDMID_CLK_N 23
HDMID_CLK_P 23

2

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

Digital Display Interface

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

SDVO_STALLN
SDVO_STALLP

SDVO_INTN
SDVO_INTP

DDPB_AUXN
DDPB_AUXP

DDPB_HPD

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPC_AUXN
DDPC_AUXP

DDPC_HPD

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

DDPD_AUXN
DDPD_AUXP

DDPD_HPD

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

DPB_HPD_Q

T48
T47

Y48

AB48

Y45

AB46

V48

AP39
AP41

AT43
AT42

AV53
AV51

BB47
BA52
AY48
AV47

BB48
BA50
AY49
AV48

AP48
AP47

AY53
AT49
AU52
AT53

AY51
AT48
AU50
AT51

AA52
AB53
AD53

V51
V53

Y53
Y51

AD48
AB51

1 2

R436 2.2KR436 2.2K

1 2

R438 2.2KR438 2.2K

C47 0.1UC47 0.1U
C48 0.1UC48 0.1U

C50 0.1UC50 0.1U
C49 0.1UC49 0.1U

C65 0.1UC65 0.1U
C66 0.1UC66 0.1U

C68 0.1UC68 0.1U
C67 0.1UC67 0.1U

U29D

U29D

L_BKLTEN
L_VDD_EN

L_BKLTCTL
L_DDC_CLK

L_DDC_DATA
L_CTRL_CLK

L_CTRL_DATA
LVD_IBG

LVD_VBG
LVD_VREFH

LVD_VREFL

LVDSA_CLK#
LVDSA_CLK

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

LVDSB_CLK#
LVDSB_CLK

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

CRT_BLUE
CRT_GREEN
CRT_RED

CRT_DDC_CLK
CRT_DDC_DATA

CRT_HSYNC
CRT_VSYNC

DAC_IREF
CRT_IRTN

IbexPeak-M_R1P0

IbexPeak-M_R1P0

BJ46
BG46

BJ48
BG48

BF45
BH45

MB_HDMID_SCL

T51

MB_HDMID_SDA

T53

R384 *1K_NCR384 *1K_NC

BG44

R385 *1K_NCR385 *1K_NC

BJ44

DPB_HPD_Q

AU38

DPB_LANE0_N

BD42

DPB_LANE0_P

BC42

DPB_LANE1_N

BJ42

DPB_LANE1_P

BG42

DPB_LANE2_N

BB40

DPB_LANE2_P

BA40

DPB_LANE3_N

AW38

DPB_LANE3_P

BA38

Y49
AB49

BE44
BD44
AV40

BE40
BD40
BF41
BH41
BD38
BC38
BB36
BA36

U50
U52

BC46
BD46
AT38

BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36

+5V_RUN

1

R383

R383

R382 *0_NCR382 *0_NC

100K

100K

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

COMPUTER

IBEX PEAK-M 2/6

IBEX PEAK-M 2/6

IBEX PEAK-M 2/6

FM9B 3A

FM9B 3A

FM9B 3A

Q45

Q45

2

2N7002K-T1-E3

2N7002K-T1-E3

MB_HDMID_SCL 23
MB_HDMID_SDA 23

69

3

1

+1.05V_PCH

MB_HDMID_HPD 23

7 65Wednesday, October 07, 2009

7 65Wednesday, October 07, 2009

7 65Wednesday, October 07, 2009

Display port BDisplay port CDisplay port D

SDVO

5

4

3

2

1

C492

C492
*27P_NC

*27P_NC

50

50

No Reboot strap.

Low = Default.
High = No Reboot.

Res. of TDO
PCH ES1 stage : NC
PCH ES2 stage : pop

+RTC_CELL

ACZ_BIT_CLK

ACZ_SYNC
ACZ_RST#
ACZ_SDOUT

R4761MR476
1M

107

R459 20KR459 20K

C4811UC481

1U

R475 20KR475 20K

C4931UC493

1U

INTVRMEN(Internal Voltage Regulator Enable) :
This signal enables the internal 1.05 V regulators.
This signal must be always pulled-up to VccRTC.

Flash Descriptor Security Override

Low = Enabled

GPIO33

High = Disabled

99

R191 *1K_NCR191 *1K_NC

1 2

(Internal 20K/F pull high to +3.3V_RUN)

Note : GPIO33 is a signal used for Flash
Descriptor Security Override/ME Debug
Mode.This signal should be only asserted
lowthrough an external pull-down in
manufacturing or debug environments
ONLY.

33

R440 51R440 51

Note : Only pop when PCH is production
stage & need "JTAG boundary Scan".
Remember to depop XDP side Res.

4

GPIO33

PCH_JTAG_TCK_BUF

C495

C495

18P/50V

18P/50V

23

Y4

32.768KHZY432.768KHZ

C494

C494

18P/50V

18P/50V

4 1

Cap values depend on Xtal

+RTC_CELL

8

JTAG
Test Pads are need to put on
the same side of mother board.

R460 330KR460 330K

SPKR39

ICH_AZ_CODEC_SDIN039

KB_LED_DET36

T42T42
T43T43
T41T41
T46T46
T47T47

SPI_CLK30
SPI_CS0#30

SPI_SI30
SPI_SO30

R478

R478
10M

10M

ACZ_BIT_CLK
ACZ_SYNC
SPKR
ACZ_RST#

ACZ_SDOUT

GPIO33

PCH_JTAG_TCK_BUF
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_RST#

T9T9

3

IBEX PEAK-M (HDA,JTAG,SATA)

85 92

115

RTCIHDA

RTCIHDA

SPI JTAG

SPI JTAG

FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

FWH4 / LFRAME#

LDRQ1# / GPIO23

LPC

LPC

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN

SATA

SATA

SATA4TXP
SATA5RXN

SATA5RXP
SATA5TXN
SATA5TXP

SATAICOMPO

SATAICOMPI

SATALED#

SATA0GP / GPIO21
SATA1GP / GPIO19

LDRQ0#

SERIRQ

RTC_X1
RTC_X2

RTC_RST#
SRTC_RST#
SM_INTRUDER#
PCH_INVRMEN

SPI_CLK
SPI_CS0#
SPI_CS1#

SPI_SI
SPI_SO

U29A

U29A

B13

RTCX1

D13

RTCX2

C14

RTCRST#

D17

SRTCRST#

A16

INTRUDER#

A14

INTVRMEN

A30

HDA_BCLK

D29

HDA_SYNC

P1

SPKR

C30

HDA_RST#

G30

HDA_SDIN0

F30

HDA_SDIN1

E32

HDA_SDIN2

F32

HDA_SDIN3

B29

HDA_SDO

H32

HDA_DOCK_EN# / GPIO33

J30

HDA_DOCK_RST# / GPIO13

M3

JTAG_TCK

K3

JTAG_TMS

K1

JTAG_TDI

J2

JTAG_TDO

J4

TRST#

BA2

SPI_CLK

AV3

SPI_CS0#

AY3

SPI_CS1#

AY1

SPI_MOSI

AV1

SPI_MISO

IbexPeak-M_R1P0

IbexPeak-M_R1P0

D33
B33
C32
A32

C34
A34

F34
AB9

AK7
AK6
AK11
AK9

AH6
AH5
AH9
AH8

AF11
AF9
AF7

SATA port 2/3 are not support in HM55 .

AF6

They are only in PM 55

AH3
AH1
AF3
AF1

AD9
AD8
AD6
AD5

AD3
AD1
AB3
AB1

AF16

SATA_COMP

1 2
1 2

R129 37.4/FR129 37.4/F

R424 100KR424 100K

+3.3V_RUN

AF15

T3

Y9
V1

SATA_ACT#

R151 10KR151 10K
R418 10KR418 10K

107

2

LPC_LAD0 29,32
LPC_LAD1 29,32
LPC_LAD2 29,32
LPC_LAD3 29,32

LPC_LFRAME# 29,32

IRQ_SERIRQ 29

SATA_RX0- 35
SATA_RX0+ 35
SATA_TX0- 35
SATA_TX0+ 35

SATA_RX1- 35
SATA_RX1+ 35
SATA_TX1- 35
SATA_TX1+ 35

SATA_RX4- 33
SATA_RX4+ 33
SATA_TX4- 33
SATA_TX4+ 33

+1.05V_PCH

+3.3V_RUN

SATA_ACT# 29

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

SATA HDD

SATA ODD

Distance between the PCH and
cap on the "P" signal should be
identical distace between the
PCH and cap on the "N" signal
for the same pair.

E-SATA

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

IBEX PEAK-M 1/6

IBEX PEAK-M 1/6

IBEX PEAK-M 1/6

FM9B 3A

FM9B 3A

FM9B 3A

1

8 65Thursday, October 01, 2009

8 65Thursday, October 01, 2009

8 65Thursday, October 01, 2009

D D

R443

R443
*20K_NC

*20K_NC

R467

R467
*10K_NC

*10K_NC

R454 33R454 33

R455 33R455 33
R453 33R453 33
R456 33R456 33

SPKR

77

PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_RST#

117

NC all Res. when
PCH is
production stage.

ICH_AZ_CODEC_BITCLK39

C C

ICH_AZ_CODEC_SYNC39
ICH_AZ_CODEC_RST #29,39
ICH_AZ_CODEC_SDOUT39

Place all series terms close to PCH except for SDIN input
lines,which should be close to source.Placement of R773, R775,
R776 & R777 should equal distance to the T split trace point.
Basically, keep the same distance from T for all series
termination resistors.

+3.3V_RUN

B B

A A

+3.3V_SUS

R445

R445
*200_NC

*200_NC

R444

R444
*100_NC

*100_NC

1 2

R420 *1K_NCR420 *1K_NC

Res. of TDI near PCH

R442

R442
*200_NC

*200_NC

R441

R441
*100_NC

*100_NC

R468

R468
*200_NC

*200_NC

R469

R469
*100_NC

*100_NC

SPKR

5

5

4

3

2

1

IBEX PEAK-M (PCI,USB,NVRAM)

85

92

U29E

U29E

H40

AD0

N34

AD1

C44

AD2

A38

AD3

C36

AD4

J34

AD5

A40

AD6

D45

D D

PCI_PIRQA#

T27T27

PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

T44T44

26

C C

PCIRST#:
DG(V1.0) P277
Can be left unconnected.

PAR:
SC(V1.0) P36
Can be left unconnected
if not using PCI.

PME:
DG(V1.0) P277
Can be left unconnected.

CLK_LPC_DEBUG32

B B

CLK_PCI_850229

CLKOUT_PCI[0..4]:

15

22 ohm series resistor is recommend
(single & double load) on PDG v1.1

Reserve capacitor pads for
improving WWAN.

CLK_LPC_DEBUG
CLK_PCI_8502

15

66

HDMI_PWR_CTRL23

USB_MCARD1_DET#32

GNT3#10

PCH_IRQH_GPIO235

14

BT_DET#32

66

0214

R196 22/FR196 22/F
R171 22/FR171 22/F

CLK_PCI_FB CLK_PCI_FB_C

R172 22/FR172 22/F

50

50

C226 *27P_NC

C226 *27P_NC

50

50

C217 *27P_NC

C217 *27P_NC

PCI_REQ0#
HDMI_PWR_CTRL
SB_WWAN_PCIE_RST#

T48T48

USB_MCARD1_DET#
PCI_GNT0#

GNT#1

T28T28

GNT#2

T26T26

PCH_IRQH_GPIO2
SB_WLAN_PCIE_RST#

T29T29

BT_DET#
PCH_IRQH_GPIO5

T59T59

PCI_RST#

T23T23

PCI_SERR#
PCI_PERR#

PCI_IRDY#
PCI_DEVSEL#

PCI_FRAME#
PCI_PLOCK#
PCI_STOP#

PCI_TRDY#
PME#

T14T14

PCI_PLTRST#

CLK_LPC_DEBUG_C
CLK_PCI_8502_C

RSV_SMBALERT#
RSV_ICH_CL_RST1#
ICH_SMBCLK
ICH_SMBDATA
SMB_CLK_ME0
SMB_DATA_ME0
SMB_CLK_ME1
SMB_DATA_ME1
LPD_SPI_INTR#

PEG_CLKREQ#

AD7

E36

AD8

H48

AD9

E40

AD10

C40

AD11

M48

AD12

M45

AD13

F53

AD14

M40

AD15

M43

AD16

J36

AD17

K48

AD18

F40

AD19

C42

AD20

K46

AD21

M51

AD22

J52

AD23

K51

AD24

L34

AD25

F42

AD26

J40

AD27

G46

AD28

F44

AD29

M47

AD30

H36

AD31

J50

C/BE0#

G42

C/BE1#

H47

C/BE2#

G34

C/BE3#

G38

PIRQA#

H51

PIRQB#

B37

PIRQC#

A44

PIRQD#

F51

REQ0#

A46

REQ1# / GPIO50

B45

REQ2# / GPIO52

M53

REQ3# / GPIO54

F48

GNT0#

K45

GNT1# / GPIO51

F36

GNT2# / GPIO53

H53

GNT3# / GPIO55

B41

PIRQE# / GPIO2

K53

PIRQF# / GPIO3

A36

PIRQG# / GPIO4

A48

PIRQH# / GPIO5

K6

PCIRST#

E44

SERR#

E50

PERR#

A42

IRDY#

H44

PAR

F46

DEVSEL#

C46

FRAME#

D49

PLOCK#

D41

STOP#

C48

TRDY#

M7

PME#

D5

PLTRST#

N52

CLKOUT_PCI0

P53

CLKOUT_PCI1

P46

CLKOUT_PCI2

P51

CLKOUT_PCI3

P48

CLKOUT_PCI4

IbexPeak-M_R1P0

IbexPeak-M_R1P0

+3.3V_SUS

R48110K R48110K
R18710K R18710K
R4622.2K R4622.2K
R4632.2K R4632.2K
R4642.2K R4642.2K
R2022.2K R2022.2K
R2282.2K R2282.2K
R2292.2K R2292.2K R450 8.2KR450 8.2K
R47910K R47910K

R48610K R48610K

107

Non-iAMT

A A

C223 0.047U

C223 0.047U

10

10

PCI_PLTRST#

Add Buffers as needed for
Loading and fanout concerns.

+3.3V_SUS

5

U11

U11

2
1

4

TC7SZ32FU(T5L,F,T)

TC7SZ32FU(T5L,F,T)

5

PLTRST# 3,26,28,29,31,32,41

115

NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11

NVRAM

NVRAM

NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15

PCI

PCI

USB

USB

14

BT_DET#
PCH_IRQH_GPIO2
SB_WWAN_PCIE_RST#

66

SB_WLAN_PCIE_RST#

OC7#
OC5#
OC4#
OC3#

+3.3V_SUS

PCH_IRQH_GPIO5
PCI_REQ0#
PCI_PIRQB#

USB_MCARD1_DET#

+3.3V_RUN

PCI_STOP#
PCI_PIRQA#
PCI_PIRQC#
PCI_IRDY#

+3.3V_RUN

NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3

NV_DQS0
NV_DQS1

NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8
NV_DQ9 / NV_IO9

NV_ALE

NV_CLE

NV_RCOMP

NV_RB#

NV_WR#0_RE#
NV_WR#1_RE#

NV_WE#_CK0
NV_WE#_CK1

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N

USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43

OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

RP1

RP1

6
7
8
9

10

10P8R-8.2K

10P8R-8.2K

RP10

RP10

6
7
8
9

10

10P8R-8.2K

10P8R-8.2K

RP2

RP2

6
7
8
9

10

10P8R-8.2K

10P8R-8.2K

4

AY9
BD1
AP15
BD8

AV9
BG8

AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6

BD3
AY6

AU2
AV7
AY8

AY5
AV11

BF5

H18
J18
A18
C18
N20
P20
J20
L20
F20
G20
A20
C20
M22
N22
B21
D21
H22
J22
E22
F22
A22
C22
G24
H24
L24
M24
A24
C24

B25
D25

N16
J16
F16
L16
E14
G16
F12
T15

NV_ALE 10
NV_CLE 10

ICH_USBP0- 33
ICH_USBP0+ 33
ICH_USBP1- 33
ICH_USBP1+ 33
ICH_USBP2- 34
ICH_USBP2+ 34

ICH_USBP4- 32
ICH_USBP4+ 32
ICH_USBP5- 31
ICH_USBP5+ 31

USB port 6/7 are not support in HM55 .
They are only in PM 55

ICH_USBP8- 32
ICH_USBP8+ 32
ICH_USBP9- 28
ICH_USBP9+ 28

ICH_USBP11- 40
ICH_USBP11+ 40
ICH_USBP12- 37
ICH_USBP12+ 37

USB_BIAS

R457 22.6/FR457 22.6/F

OC0#
OC1#
OC2#
OC3#
OC4#
OC5#
OC6#
OC7#

OC0#~OC7#:
DG(V1.0)P214
Pin Default Port Mapping
OC0# Port0,Port1
OC1# Port2,Port3

R452 8.2KR452 8.2K
R451 8.2KR451 8.2K

R439 8.2KR439 8.2K

107

5
4
3
2
1

5
4
3
2
1

5
4
3
2
1

+3.3V_SUS

OC2#
OC6#
OC1#
OC0#

+3.3V_RUN

PCI_TRDY#
PCI_FRAME#
HDMI_PWR_CTRL
PCI_PIRQD#

+3.3V_RUN

PCI_SERR#
PCI_PERR#
PCI_PLOCK#
PCI_DEVSEL#

OC0# 33
OC1# 34

+3.3V_RUN

Left Side pair Top
Left Side pair bottom

Right Side pair top (Cable)

Mini Card (WLAN)
Mini Card (WWAN)

Mini Card (WPAN)
Express Card

Camera
Touch Screen Module

Note : place these
resistors near to PCIe
Slots

Place TX DC blocking caps close PCH.

PCIE_RX1-31

MiniWWAN

MiniWLAN

Express Card

Card Reader

Giga Bit LOM

MiniWLAN

MiniWWAN

Express Card

PCIE_RX1+31
PCIE_TX1-31
PCIE_TX1+31

PCIE_RX2-32
PCIE_RX2+32
PCIE_TX2-32
PCIE_TX2+32

PCIE_RX4-28
PCIE_RX4+28
PCIE_TX4-28
PCIE_TX4+28

PCIE_RX5-26
PCIE_RX5+26
PCIE_TX5-26
PCIE_TX5+26

PCIE_RX6-/GLAN_RX-41
PCIE_RX6+/GLAN_RX+41

PCIE_TX6-/GLAN_TX-41
PCIE_TX6+/GLAN_TX+41

PCI-E port 7/8 are not support in HM55 .
They are only in PM 55

CLK_PCIE_MINI1#32
CLK_PCIE_MINI132

Card Reader

CLK_PCIE_CARD_READER#26
CLK_PCIE_CARD_READER26

CLK_PCIE_REQ2#26

CLK_PCIE_MINI2#31
CLK_PCIE_MINI231

CLK_PCIE_EXPCARD#28
CLK_PCIE_EXPCARD28

CARD_CLK_REQ#28

24

Card Reader

CLK_PCIE_LOM#41

Giga Bit LOM

CLK_PCIE_LOM41

PCIE Clock Request

+3.3V_SUS

+3.3V_RUN

PCIECLKRQ{0,3,4,5,6,7}# should have a
10K pull-up to +V3.3A.PCIECLKRQ{1,2}
should have a 10K pull-up to +3.3S

53

Boot BIOS Strap

PCI_GNT0# GNT#1

0 0
0
1
1 1

1
0

R482 10KR482 10K
R163 10KR163 10K
R183 10KR183 10K
R162 10KR162 10K
R484 10KR484 10K

R427 10KR427 10K
R426 10KR426 10K

R169 *1K_NCR169 *1K_NC
R152 *1K_NCR152 *1K_NC

Boot BIOS Location
LPC
PCI
Reserved (NAND)
SPI

3

CLK_PCIE_REQ3#
CARD_CLK_REQ#_R
CLK_PCIE_REQ5#
CLK_PEG0_REQ#
LOM_CLK_REQ#_R

MINI1CLK_REQ#_R
CLK_PCIE_REQ2#_R

MINI1CLK_REQ#32

LOM_CLK_REQ#41

PCI_GNT0#
GNT#1

C447 *0.1U_NCC447 *0.1U_NC
C446 *0.1U_NCC446 *0.1U_NC

87

C107 0.1UC107 0.1U
C108 0.1UC108 0.1U

C110 0.1UC110 0.1U
C109 0.1UC109 0.1U

C445 0.1UC445 0.1U
C444 0.1UC444 0.1U

C153 0.1UC153 0.1U
C152 0.1UC152 0.1U

24

R423 *0_shortR423 *0_short

68

R421 *0_shortR421 *0_short

Q2

CLK_PCIE_REQ3#

36

R166 *0_shortR166 *0_short

Q2

CLK_PCIE_REQ5#

36

R483 *0_shortR483 *0_short

36

24

24

75

IBEX PEAK-M (PCI-E,SMBUS,CLK)

85

92

Q13

Q13

2

2N7002W-7-F

2N7002W-7-F

31

Q14

Q14

2

2N7002W-7-F

2N7002W-7-F

31

115

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML1ALERT# / GPIO74

SMBus

SMBus

SML1DATA / GPIO75

PCI-E*

PCI-E*

Link

Link

Controller

Controller

PEG_A_CLKRQ# / GPIO47

PEG

PEG

CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P

From CLK BUFFER

From CLK BUFFER

CLKIN_SATA_N / CKSSCD_N

CLKIN_SATA_P / CKSSCD_P

CLKIN_PCILOOPBACK

CLKOUTFLEX0 / GPIO64

CLKOUTFLEX1 / GPIO65

CLKOUTFLEX2 / GPIO66

CLKOUTFLEX3 / GPIO67

Clock Flex

Clock Flex

20

SMBCLK1 29

SMBDAT1 29

SML1CLK / GPIO58

CLKOUT_PEG_A_N

CLKOUT_PEG_A_P

U29B

U29B

BG30

PERN1

BJ30

PCIE_TXN1_C
PCIE_TXP1_C

PCIE_TXN2_C
PCIE_TXP2_C

PCIE_TXN4_C
PCIE_TXP4_C

PCIE_TXN5_C
PCIE_TXP5_C

PCIE_TXN6_C
PCIE_TXP6_C

CLK_PEG0_REQ#

MINI1CLK_REQ#_R

CLK_PCIE_REQ2#_R

CARD_CLK_REQ#_R

LOM_CLK_REQ#_R

Q2

DG(V1.1) P256: XTAL_OUT and XTAL_IN
are the signal names for the PHY.
Intel feedback:
Fully-Integrated Clocking is a stretch
goal for Calpella platforma nd maybe
enabled in ES2 Si. Recommend
customers to have 25-MHz crystal as
a BOM stuff option.

SMB_CLK_ME1

SMB_DATA_ME1

PERP1

BF29

PETN1

BH29

PETP1

AW30

PERN2

BA30

PERP2

BC30

PETN2

BD30

PETP2

AU30

PERN3

AT30

PERP3

AU32

PETN3

AV32

PETP3

BA32

PERN4

BB32

PERP4

BD32

PETN4

BE32

PETP4

BF33

PERN5

BH33

PERP5

BG32

PETN5

BJ32

PETP5

BA34

PERN6

AW34

PERP6

BC34

PETN6

BD34

PETP6

AT34

PERN7

AU34

PERP7

AU36

PETN7

AV36

PETP7

BG34

PERN8

BJ34

PERP8

BG36

PETN8

BJ36

PETP8

AK48

CLKOUT_PCIE0N

AK47

CLKOUT_PCIE0P

P9

PCIECLKRQ0# / GPIO73

AM43

CLKOUT_PCIE1N

AM45

CLKOUT_PCIE1P

U4

PCIECLKRQ1# / GPIO18

AM47

CLKOUT_PCIE2N

AM48

CLKOUT_PCIE2P

N4

PCIECLKRQ2# / GPIO20

AH42

CLKOUT_PCIE3N

AH41

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

AM51

CLKOUT_PCIE4N

AM53

CLKOUT_PCIE4P

M9

PCIECLKRQ4# / GPIO26

AJ50

CLKOUT_PCIE5N

AJ52

CLKOUT_PCIE5P

H6

PCIECLKRQ5# / GPIO44

AK53

CLKOUT_PEG_B_N

AK51

CLKOUT_PEG_B_P

P13

PEG_B_CLKRQ# / GPIO56

IbexPeak-M_R1P0

IbexPeak-M_R1P0

CLKOUT_PEG_A_P/N,CLKOUT_PEG_B_P/N,
CLKOUT_DMI_P/N,support GEN-1 and GEN-2

+3.3V_SUS

+3.3V_SUS

2

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1
CL_DATA1
CL_RST1#

CLKOUT_DMI_N
CLKOUT_DMI_P

CLKIN_DMI_N

CLKIN_DMI_P

CLKIN_BCLK_N
CLKIN_BCLK_P

CLKIN_DOT_96N
CLKIN_DOT_96P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

RSV_SMBALERT#

B9

ICH_SMBCLK

H14

ICH_SMBDATA

C8

RSV_ICH_CL_RST1#

J14

SMB_CLK_ME0

C6

SMB_DATA_ME0

G8

LPD_SPI_INTR#

M14

SMB_CLK_ME1

E10

SMB_DATA_ME1

G12

T13
T11
T9

PEG_CLKREQ#

H1

AD43
AD45

AN4
AN2

AT1
AT3

AW24
BA24

AP3
AP1

F18
E18

AH13
AH12

P41

CLK_PCI_FB

J42

XTAL25_IN

AH51

XTAL25_OUT

AH53

XCLK_RCOMP

AF38

CLK_FLEX0

T45

CLK_FLEX1

P43

CLK_FLEX2

T42

CLK_FLEX3

N50

CLKOUTFLEX3:
EDS(V1.0) :support 48MHz
33MHz and 14.31818MHz.

CLKOUTFLEX[0..3]:
PDG v1.1: 22 ohm series resistor is
recommend (PCI & non PCI routing,
single & double load)

T49T49

ICH_SMBCLK 13,14,32,60
ICH_SMBDATA 13,14,32,60

T25T25

T16T16

SML0CLK/SML0DATA:
DG(V1.1) P255: The 82577 SMBus
signals
(SMB_DATA and SMB_CLK) cannot be
connected to any other
devices other than the PCH.
Connect the SMB_DATA and SMB_CLK
pins
to the PCH SML0DATA and SML0CLK
pins,
respectively.

T51T51

CLK_PCIE_3GPLL# 3
CLK_PCIE_3GPLL 3

DREFSSCLK# 3
DREFSSCLK 3

CLK_BUF_PCIE_3GPLL# 15
CLK_BUF_PCIE_3GPLL 15

CLK_BUF_BCLK_N 15
CLK_BUF_BCLK_P 15

CLK_BUF_DREFCLK# 15
CLK_BUF_DREFCLK 15

CLK_BUF_DREFSSCLK# 15
CLK_BUF_DREFSSCLK 15

CLK_ICH_14M 15

CLKIN_PCILOOPBACK:
PDG (V1.1): 22 ohm series resistor
is recommend

0214

R130 90.9/FR130 90.9/F

+1.05V_PCH

T19T19

T17T17

T20T20

T18T18

25MHz Clock for DCI Function

Y5

25MHzY525MHz

1

12

4

12

Q2

101

123

12

C691

C691

27P/50V

27P/50V

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

COMPUTER

IBEX PEAK-M 3/6

IBEX PEAK-M 3/6

IBEX PEAK-M 3/6

FM9B 3A

FM9B 3A

FM9B 3A

0214

XTAL25_IN

R4111MR411
1M

XTAL25_OUT

C692

C692
27P/50V

27P/50V

9 65Monday, October 12, 2009

9 65Monday, October 12, 2009

9 65Monday, October 12, 2009

31
101

Q6

5

S_GPIO

R185 *0_NCR185 *0_NC

SIO_EXT_SMI#
SIO_EXT_SCI#
SIO_EXT_WAKE#
RSV_WOL_EN

LAN_PHY_PWR_CTRL
TEST_WOOFER_EN
SATA4GP
PCIE_MCARD1_DET#_R
PCIE_MCARD2_DET#

GPIO27
TP_PCH_GPIO28
USB_MCARD2_DET#
GPIO35
SATA2GP
SATA3GP
WLAN_RADIO_DIS#
CRB_SV_DET
GPIO45
GPIO46
SV_SET_UP
SATA5GP
GPIO57

SIO_EXT_SMI#29
SIO_EXT_SCI#29

D D

LAN_PCIE_PWR_CTRL29,41

PCIE_MCARD1_DET#32

GPIO24 register not cleared by CF9h reset event.
GPIO27 reserve for internal VR.

BT_RADIO_DIS#32

C C

WWAN_RADIO_DIS#31

CRIT_TEMP_REP#29

SIO_EXT_WAKE#29

TEST_WOOFER_EN39

Q2

R205 *0_shortR205 *0_short

PCIE_MCARD2_DET#31

R128 *10K_NCR128 *10K_NC

USB_MCARD2_DET#31

WLAN_RADIO_DIS#32

R429 *0_shortR429 *0_short

Q2

87

R148 *0_NCR148 *0_NC
R409 *0_shortR409 *0_short

Q2

B B

4

115

92

85

AB12

M11

AB7

AB13

AB6

BE1

BE53

BF53

BH1

BH2
BH52
BH53

BJ49
BJ50

BJ52
BJ53

C38
D37

F10

AA2
F38

H10

V13

AA4

A49
A50

A52
A53

B52
B53

BF1

BJ1
BJ2
BJ4

BJ5

D53
E53

IBEX PEAK-M (GPIO,VSS_NCTF,RSVD)

U29F

U29F

Y3

BMBUSY# / GPIO0
TACH1 / GPIO1
TACH2 / GPIO6

J32

TACH3 / GPIO7
GPIO8

K9

LAN_PHY_PWR_CTRL / GPIO12

T7

GPIO15
SATA4GP / GPIO16
TACH0 / GPIO17

Y7

SCLOCK / GPIO22
GPIO24
GPIO27
GPIO28
STP_PCI# / GPIO34

V6

SATACLKREQ# / GPIO35
SATA2GP / GPIO36
SATA3GP / GPIO37

V3

SLOAD / GPIO38

P3

SDATAOUT0 / GPIO39

H3

PCIECLKRQ6# / GPIO45

F1

PCIECLKRQ7# / GPIO46
SDATAOUT1 / GPIO48
SATA5GP / GPIO49

F8

GPIO57

A4

VSS_NCTF_1
VSS_NCTF_2

A5

VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6

B2

VSS_NCTF_7

B4

VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26

D1

VSS_NCTF_27

D2

VSS_NCTF_28
VSS_NCTF_29

E1

VSS_NCTF_30
VSS_NCTF_31

IbexPeak-M_R1P0

IbexPeak-M_R1P0

MISC

MISC

CLKOUT_BCLK0_N / CLKOUT_PCIE8N
CLKOUT_BCLK0_P / CLKOUT_PCIE8P

GPIO

GPIO

CPU

CPU

NCTF

NCTF

RSVD

RSVD

CLKOUT_PCIE6N
CLKOUT_PCIE6P

CLKOUT_PCIE7N
CLKOUT_PCIE7P

A20GATE

PECI

RCIN#

PROCPWRGD

THRMTRIP#

TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18

TP19
NC_1
NC_2
NC_3
NC_4
NC_5

INIT3_3V#

TP24

TP1
TP2
TP3
TP4
TP5
TP6
TP7
TP8
TP9

AH45
AH46

AF48
AF47

U2

AM3
AM1
BG10
T1
BE10
BD10

BA22
AW22
BB22
AY45
AY46
AV43
AV45
AF13
M18
N18
AJ24
AK41
AK42
M32
N32
M30
N30
H12
AA23
AB45
AB38
AB42
AB41
T39

P6
C10

3

PCH_THRMTRIP#_R

SIO_A20GATE 29

CLK_CPU_BCLK# 3
CLK_CPU_BCLK 3
H_PECI 3
SIO_RCIN# 29
H_PWRGOOD 3,60

R88 56/FR88 56/F

(Both these should be close to PCH)

2

+1.05V_VTT

R87

R87
56/F

56/F

TEST_WOOFER_EN
RSV_WOL_EN
TP_PCH_GPIO28
GPIO45
GPIO46
GPIO57
LAN_PHY_PWR_CTRL

SIO_EXT_SMI#
SIO_EXT_SCI#
SIO_EXT_WAKE#
PCIE_MCARD2_DET#

PCIE_MCARD1_DET#_R

WLAN_RADIO_DIS#
CRB_SV_DET

SIO_RCIN#

H_THERM 3

SIO_A20GATE
SATA2GP
SATA5GP
SATA3GP
SATA4GP
USB_MCARD2_DET#

40

DMI Termination Voltage

NV_CLE

NV_ALE9
NV_CLE9

Danbury Technology Enabled

NV_ALE

Set to Vcc when LOW
Set to Vcc/2 when HIGH

R103 *1K_NCR103 *1K_NC
R102 *1K_NCR102 *1K_NC

High = Enable
Low = Disable

1

R487 1KR487 1K
R204 10KR204 10K
R161 10KR161 10K
R466 10KR466 10K
R485 10KR485 10K
R203 10KR203 10K
R184 10KR184 10K

R193 10KR193 10K
R194 10KR194 10K
R192 10KR192 10K
R149 10KR149 10K

R195 10KR195 10K
R422 10KR422 10K
R425 10KR425 10K

R419 10KR419 10K
R428 10KR428 10K
R146 10KR146 10K
R406 10KR406 10K
R127 10KR127 10K
R407 10KR407 10K
R164 10KR164 10K

+3.3V_SUS

+3.3V_RUN

107

+NVRAM_VCCQ

107

R150 10KR150 10K

A A

R437 *1K_NCR437 *1K_NC

A16 swap override Strap/Top-Block
Swap Override jumper

GNT3#

GPIO35

GNT3# 9

Low = A16 swap
override/Top-Block
Swap Override enabled
High = Default

5

34

R186 *1K_NCR186 *1K_NC

Integrated Clock Chip Enable

(Reserve to validate for future platforms)

RSV_WOL_EN

RSV_WOL_EN

Enable when sampled low
Disable when sampled high

4

+3.3V_RUN

107

S_GPIO
SV_SET_UP

R408 10KR408 10K
R147 10KR147 10K

SV_SET_UP 1-X High = Strong (Default)

3

6

BMBUSY#:
If not used, require a weak pull-up (8.2- KΩ to 10 kΩ) to Vcc3_3.
CRB(V1.0)P28: it has 1K PU and 100 ohm on this net for validation purpose.

BMBUSY#:(Intel feedback)
Follow CRB checklist, 1K is
for intel BIOS validation purpose.

Title

Title

Title

IBEX PEAK-M 4/6

IBEX PEAK-M 4/6

IBEX PEAK-M 4/6

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

FM9B 3A

FM9B 3A

FM9B 3A

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

10 65Thursday, October 01, 2009

10 65Thursday, October 01, 2009

10 65Thursday, October 01, 2009

1

5

U29G

IBEX PEAK-M (POWER)

D D

VCCAPLLEXP = 100mA max

VCCAPLLEXP:
This pin can be left as no connect in
On-Die VR enabled mode (default).

Q2

+1.05V_PCH

+1.05V_PCH

VCCIO = 3.208A max

C C

L40 *1uH_NCL40 *1uH_NC

C106

C106
10U

10U

10

10
805

805

+1.05V_PCH

+1.05V_PCH

C1511UC151
1U

+3.3V_RUN

VCCCORE=1.524A max

C1771UC177

C91

C91
10U

10U

1U

10

10
805

805

+1.05V_LAN_VCCAPLL_EXP

C427

C427
*10U_NC

*10U_NC

C1481UC148

C1501UC150
1U

C1491UC149

1U

1U

VCC3_3 = 0.357A max

C205

C205

0.1U

0.1U

VCCFDIPLL = 100mA max

+1.05V_PCH

B B

A A

L41 *1uH_NCL41 *1uH_NC

5

VCCVRM = 0.035A max

+1.5VS_1.8VS

+1.05V_VCCFDIPLL

+1.05V_PCH

C428

C428
*10U_NC

*10U_NC

VCCIO = 3.208A max

+1.05V_PCH

U29G

AB24

VCCCORE[1]

AB26

VCCCORE[2]

AB28

VCCCORE[3]

AD26

VCCCORE[4]

AD28

VCCCORE[5]

AF26

VCCCORE[6]

AF28

VCCCORE[7]

AF30

VCCCORE[8]

AF31

VCCCORE[9]

AH26

VCCCORE[10]

AH28

VCCCORE[11]

AH30

VCCCORE[12]

AH31

VCCCORE[13]

AJ30

VCCCORE[14]

AJ31

VCCCORE[15]

AK24

VCCIO[24]

BJ24

VCCAPLLEXP

AN20

VCCIO[25]

AN22

VCCIO[26]

AN23

VCCIO[27]

AN24

VCCIO[28]

AN26

VCCIO[29]

AN28

VCCIO[30]

BJ26

VCCIO[31]

BJ28

VCCIO[32]

AT26

VCCIO[33]

AT28

VCCIO[34]

AU26

VCCIO[35]

AU28

VCCIO[36]

AV26

VCCIO[37]

AV28

VCCIO[38]

AW26

VCCIO[39]

AW28

VCCIO[40]

BA26

VCCIO[41]

BA28

VCCIO[42]

BB26

VCCIO[43]

BB28

VCCIO[44]

BC26

VCCIO[45]

BC28

VCCIO[46]

BD26

VCCIO[47]

BD28

VCCIO[48]

BE26

VCCIO[49]

BE28

VCCIO[50]

BG26

VCCIO[51]

BG28

VCCIO[52]

BH27

VCCIO[53]

AN30

VCCIO[54]

AN31

VCCIO[55]

AN35

VCC3_3[1]

AT22

VCCVRM[1]

BJ18

VCCFDIPLL

AM23

VCCIO[1]

IbexPeak-M_R1P0

IbexPeak-M_R1P0

+1.8V_RUN

+3.3V_RUN

L19 10uHL19 10uH

L18 10uHL18 10uH

R117 *0_NCR117 *0_NC
R386 *0_NCR386 *0_NC
R388 0R388 0
R389 0R389 0
R387 *0_NCR387 *0_NC

+1.05V_PCH

PCH EDS(V1.0) P84
+NVRAM_VCCQ:

1.8 V supply for Dual Channel NAND interface.
This power is supplied by core
well. If unused, this pin should
be connected to Vcc3_3.

4

85

92

POWER

POWER

VCC CORE

VCC CORE

PCI E*

PCI E*

+1.1V_VCCADPLLA

+

+

C136

C136
220U

220U

3528

3528

+1.1V_VCCADPLLB

+

+

C135

C135
220U

220U

3528

3528

4

115

VCCADAC[1]
VCCADAC[2]

VSSA_DAC[1]

CRTLVDS

CRTLVDS

VSSA_DAC[2]

AE50
AE52
AF53
AF51

+VCCA_DAC_1_2

C472

C472

0.01U

0.01U

C470

C470
22U

22U

6.3

6.3
805

805

C464

C464
*1U_NC

*1U_NC

HCB1608KF-471T10

HCB1608KF-471T10
C471

C471

0.1U

0.1U

Q8

AH38

VCCALVDS

AH39

VSSA_LVDS

VCC3_3[2]
VCC3_3[3]
VCC3_3[4]

VCCVRM[2]

VCCDMI[1]
VCCDMI[2]

VCCPNAND[1]
VCCPNAND[2]
VCCPNAND[3]
VCCPNAND[4]
VCCPNAND[5]
VCCPNAND[6]
VCCPNAND[7]
VCCPNAND[8]
VCCPNAND[9]

VCCME3_3[1]
VCCME3_3[2]
VCCME3_3[3]
VCCME3_3[4]

AP43
AP45
AT46
AT45

AB34
AB35
AD35

AT24

AT16
AU16

AM16
AK16
AK20
AK19
AK15
AK13
AM12
AM13
AM15

AM8
AM9
AP11
AP9

VCCTX_LVDS[1]
VCCTX_LVDS[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]

HVCMOS

HVCMOS

DMI

DMI

NAND / SPI

NAND / SPI

FDI

FDI

VCCME3_3:
EDS(V1.0)P84:supply for the Intel Management Engine.This is a separate power plane
that may or may not be powered in S3–S5 states.
This plane must be on in S0
and other times the Intel Management Engine is used.

+1.5VS_1.8VS+1.5V_RUN

+NVRAM_VCCQ

C1341UC134
1U

C1331UC133
1U

+3.3V_RUN

C155

C155

C154

C154

0.01U

0.01U

0.01U

0.01U

+3.3V_RUN

C183

C183

0.1U

0.1U

VCCVRM = 0.035A max

+1.5VS_1.8VS

VCCDMI = 0.061A max

VCCPNAND = 0.156A max

VCCME3_3 = 0.085A max

C1471UC147
1U

+NVRAM_VCCQ

C146

C146

0.1U

0.1U

+3.3V_RUN

C216

C216

0.1U

0.1U

R115 *0_shortR115 *0_short
R116 *0_NCR116 *0_NC

VCCME = 1.998A max

+1.05V_PCH

91

L44 0.1uHL44 0.1uH
C469

C469
22U

22U

VCC3_3 = 0.357A max

+1.05V_PCH

Q2

+1.05V_VTT
+1.05V_PCH

3

L45

L45

+3.3V_RUN

118

106

VCCACLK = 100mA max

+1.8V_RUN

3

T61T61
T62T62

C1781UC178

1U

C90

C90

C111

C111

22U

22U

22U

22U

C199 0.1UC199 0.1U

+1.5VS_1.8VS

VCCADPLLA = 0.072A max

+1.1V_VCCADPLLA

VCCADPLLB = 0.073A max

+1.1V_VCCADPLLB

VCCIO = 3.208A max

+1.05V_PCH

C1841UC184
1U

C198 0.1UC198 0.1U

C176 0.1UC176 0.1U

VCCSUS3_3 = 0.163A max

+3.3V_SUS

VCC3_3 = 0.357A max

+3.3V_RUN

V_CPU>1mA

+1.05V_VTT

C429

C429

4.7U

4.7U

+RTC_CELL

VCCRTC = 2mA max

VCCADAC = 100mA max

DCPSUSBYP

C200

C200

0.1U

0.1U

C2071UC207

1U

DCPRTC

C1801UC180

C1821UC182

1U

1U

DCPSST

DCPSUS

C203

C203

0.1U

0.1U

C206

C206

0.1U

0.1U

C132

C132

C131

C131

0.1U

0.1U

0.1U

0.1U

C483

C483
C4821UC482
1U

0.1U

0.1U

C484

C484

0.1U

0.1U

AP51
AP53

AF23
AF24

AD38
AD39
AD41
AF43
AF41
AF42

AU24

BB51
BB53

BD51
BD53

AH23
AJ35
AH35

AF34
AH34
AF32

AT18

AU18

U29J

U29J

VCCACLK[1]
VCCACLK[2]

VCCLAN[1]
VCCLAN[2]

Y20

DCPSUSBYP

VCCME[1]
VCCME[2]
VCCME[3]
VCCME[4]
VCCME[5]
VCCME[6]

V39

VCCME[7]

V41

VCCME[8]

V42

VCCME[9]

Y39

VCCME[10]

Y41

VCCME[11]

Y42

VCCME[12]

V9

DCPRTC

VCCVRM[3]

VCCADPLLA[1]
VCCADPLLA[2]

VCCADPLLB[1]
VCCADPLLB[2]

VCCIO[21]
VCCIO[22]
VCCIO[23]

VCCIO[2]
VCCIO[3]
VCCIO[4]

V12

DCPSST

Y22

DCPSUS

P18

VCCSUS3_3[29]

U19

VCCSUS3_3[30]

U20

VCCSUS3_3[31]

U22

VCCSUS3_3[32]

V15

VCC3_3[5]

V16

VCC3_3[6]

Y16

VCC3_3[7]

V_CPU_IO[1]

V_CPU_IO[2]

A12

VCCRTC

IbexPeak-M_R1P0

IbexPeak-M_R1P0

2

85

92

115

POWER

POWER

Clock and Miscellaneous

Clock and Miscellaneous

CPU

CPU

RTC PCI/GPIO/LPC

RTC PCI/GPIO/LPC

USB

USB

PCI/GPIO/LPC

PCI/GPIO/LPC

SATA

SATA

HDA

HDA

VCCSUS3_3[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCCSUS3_3[6]
VCCSUS3_3[7]
VCCSUS3_3[8]

VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]
VCCSUS3_3[21]
VCCSUS3_3[22]
VCCSUS3_3[23]
VCCSUS3_3[24]
VCCSUS3_3[25]
VCCSUS3_3[26]
VCCSUS3_3[27]

VCCSUS3_3[28]

VCCSATAPLL[1]
VCCSATAPLL[2]

2

VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]

VCCIO[56]

V5REF_SUS

V5REF

VCC3_3[8]

VCC3_3[9]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]

VCC3_3[14]

VCCIO[9]

VCCVRM[4]

VCCIO[10]

VCCIO[11]

VCCIO[12]

VCCIO[13]

VCCIO[14]

VCCIO[15]

VCCIO[16]

VCCIO[17]

VCCIO[18]

VCCIO[19]

VCCIO[20]
VCCME[13]

VCCME[14]
VCCME[15]
VCCME[16]

VCCSUSHDA

V24
V26
Y24
Y26

V28
U28
U26
U24
P28
P26
N28
N26
M28
M26
L28
L26
J28
J26
H28
H26
G28
G26
F28
F26
E28
E26
C28
C26
B27
A28
A26

U23
V23
F24

K49

J38
L38
M36
N36
P36
U35

AD13

AK3
AK1

AH22

AT20

AH19
AD20
AF22
AD19

AF20
AF19
AH20

AB19
AB20
AB22
AD22

AA34
Y34
Y35
AA35

L30

+V5REF_SUS

+V5REF

C174

C174
*1U_NC

*1U_NC

C2011UC201
1U

C215

C215

C202

C202

0.1U

0.1U

0.1U

0.1U

VCCIO = 3.208A max

+1.05V_PCH

R189 100R189 100
D9 SDM10K45-7-FD9 SDM10K45-7-F

C2241UC224
1U

R197 100R197 100

D8 SDM10K45-7-FD8 SDM10K45-7-F
C2251UC225
1U

C181

C181

0.1U

0.1U

C175

C175

0.1U

0.1U

+1.05V_VCCSATAPLL

C173

C173
*10U_NC

*10U_NC

VCCVRM = 0.035A max

+1.5VS_1.8VS

VCCME = 1.998A max

+1.05V_PCH

R190 *0_shortR190 *0_short

C2041UC204
1U

+1.05V_PCH

+3.3V_SUS

1 2

21

1 2

21

VCC3_3 = 0.357A max

+3.3V_RUN

L20 *10uH_NCL20 *10uH_NC

VCCIO = 3.208A max

C1791UC179
1U

Q2

+3.3V_SUS

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

COMPUTER

IBEX PEAK-M 5/6

IBEX PEAK-M 5/6

IBEX PEAK-M 5/6

FM9B 3A

FM9B 3A

FM9B 3A

1

VCCIO = 3.208A max

VCCSUS3_3 = 0.163A max

11
35

+5V_SUS

V5REF_SUS>1mA

+3.3V_SUS

V5REF>1mA

+5V_RUN
+3.3V_RUN

+1.05V_PCH

+1.05V_PCH

VCCSUSHDA = 6mA max

1

11 65W ednesday, October 07, 2009

11 65W ednesday, October 07, 2009

11 65W ednesday, October 07, 2009

5

4

3

2

1

U29I

U29I

AY7

VSS[159]

BG12
BB12
BB16
BB20
BB24
BB30
BB34
BB38
BB42
BB49

BC10
BC14
BC18

BC2
BC22
BC32
BC36
BC40
BC44
BC52

BH9
BD48
BD49

BD5
BE12
BE16
BE20
BE24
BE30
BE34
BE38
BE42
BE46
BE48
BE50

BE6

BE8

BF3

BF49

BF51
BG18
BG24

BG4
BG50
BH11
BH15
BH19
BH23
BH31
BH35
BH39
BH43
BH47

BH7

C12

C50

D51

G10

G14

G18

G22

G32

G36

G40

G44

G52

AF39

H16

H20

H30

H34

H38

H42

B11
B15
B19
B23
B31
B35
B39
B43
B47

BB5

E12
E16
E20
E24
E30
E34
E38
E42
E46
E48

F49

B7

E6
E8

F5

G2

VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]

IbexPeak-M_R1P0

IbexPeak-M_R1P0

3

IBEX PEAK-M (GND)

D D

85859292115

U29H

U29H

AB16

VSS[0]

AA19

VSS[1]

AA20

VSS[2]

AA22

VSS[3]

AM19

VSS[4]

AA24

VSS[5]

AA26

VSS[6]

AA28

VSS[7]

AA30

VSS[8]

AA31

VSS[9]

AA32

VSS[10]

AB11

VSS[11]

AB15

VSS[12]

AB23

VSS[13]

AB30

VSS[14]

AB31

VSS[15]

AB32

VSS[16]

AB39

VSS[17]

AB43

VSS[18]

AB47

C C

B B

A A

5

AB5
AB8

AC2
AC52
AD11
AD12
AD16
AD23
AD30
AD31
AD32
AD34
AU22
AD42
AD46
AD49

AD7

AE2

AE4

AF12

Y13
AH49

AU4

AF35
AP13
AN34

AF45

AF46

AF49

AF5
AF8

AG2
AG52
AH11
AH15
AH16
AH24
AH32
AV18
AH43
AH47

AH7

AJ19
AJ20

AJ22
AJ23
AJ26
AJ28
AJ32
AJ34

AT5
AK12

AM41
AN19
AK26
AK22
AK23
AK28

AJ2

AJ4

VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]

IbexPeak-M_R1P0

IbexPeak-M_R1P0

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

AK30
AK31
AK32
AK34
AK35
AK38
AK43
AK46
AK49
AK5
AK8
AL2
AL52
AM11
BB44
AD24
AM20
AM22
AM24
AM26
AM28
BA42
AM30
AM31
AM32
AM34
AM35
AM38
AM39
AM42
AU20
AM46
AV22
AM49
AM7
AA50
BB10
AN32
AN50
AN52
AP12
AP42
AP46
AP49
AP5
AP8
AR2
AR52
AT11
BA12
AH48
AT32
AT36
AT41
AT47
AT7
AV12
AV16
AV20
AV24
AV30
AV34
AV38
AV42
AV46
AV49
AV5
AV8
AW14
AW18
AW2
BF9
AW32
AW36
AW40
AW52
AY11
AY43
AY47

4

115

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[326]
VSS[327]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[332]
VSS[333]
VSS[334]
VSS[335]
VSS[336]
VSS[337]
VSS[338]
VSS[339]
VSS[340]
VSS[341]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
VSS[353]
VSS[354]
VSS[355]
VSS[356]
VSS[366]

H49
H5
J24
K11
K43
K47
K7
L14
L18
L2
L22
L32
L36
L40
L52
M12
M16
M20
N38
M34
M38
M42
M46
M49
M5
M8
N24
P11
AD15
P22
P30
P32
P34
P42
P45
P47
R2
R52
T12
T41
T46
T49
T5
T8
U30
U31
U32
U34
P38
V11
P16
V19
V20
V22
V30
V31
V32
V34
V35
V38
V43
V45
V46
V47
V49
V5
V7
V8
W2
W52
Y11
Y12
Y15
Y19
Y23
Y28
Y30
Y31
Y32
Y38
Y43
Y46
P49
Y5
Y6
Y8
P24
T43
AD51
AT8
AD47
Y47
AT12
AM6
AT13
AM5
AK45
AK39
AV14

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

COMPUTER

IBEX PEAK-M 6/6

IBEX PEAK-M 6/6

IBEX PEAK-M 6/6

FM9B 3A

FM9B 3A

FM9B 3A

12 65Thursday, October 01, 2009

12 65Thursday, October 01, 2009

12 65Thursday, October 01, 2009

1

5

M_A_A[15:0]4

D D

M_A_BS04
M_A_BS14
M_A_BS24
M_A_CS0#4
M_A_CS1#4
M_A_CLK04
M_A_CLK0#4
M_A_CLK14
M_A_CLK1#4
M_A_CKE04
M_A_CKE14

107

R207 10KR207 10K
R206 10KR206 10K

C C

B B

M_A_CAS#4
M_A_RAS#4
M_A_WE#4

WLAN_SMBCLK14,28,31,32,35
WLAN_SMBDATA14,28,31,32,35

M_A_ODT04
M_A_ODT14

M_A_DM[7:0]4

M_A_DQS[7:0]4

M_A_DQS#[7:0]4

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15

DIMM0_SA0

DIMM0_SA1
WLAN_SMBCLK
WLAN_SMBDATA

M_A_DM0

M_A_DM1

M_A_DM2

M_A_DM3

M_A_DM4

M_A_DM5

M_A_DM6

M_A_DM7

M_A_DQS0

M_A_DQS1

M_A_DQS2

M_A_DQS3

M_A_DQS4

M_A_DQS5

M_A_DQS6

M_A_DQS7

M_A_DQS#0

M_A_DQS#1

M_A_DQS#2

M_A_DQS#3

M_A_DQS#4

M_A_DQS#5

M_A_DQS#6

M_A_DQS#7

107

119

109
108

114
121
101
103
102
104

115
110
113
197
201
202
200

116
120

136
153
170
187

137
154
171
188

135
152
169
186

98
97
96
95
92
91
90
86
89
85

84
83

80
78

79

73
74

11
28
46
63

12
29
47
64

10
27
45
62

JDIM2A

JDIM2A

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15

BA0
BA1
BA2
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE#
SA0
SA1
SCL
SDA

ODT0
ODT1

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7

2-2013311-1

2-2013311-1

4

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

PC2100 DDR3 SDRAM SO-DIMM

PC2100 DDR3 SDRAM SO-DIMM

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

(204P)

(204P)

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

3

M_A_DQ[63:0] 4

PM_EXTTS#03

DDR3_DRAMRST#3,14

+SMDDR_VREF_DIMM0

27

+1.5V_SUS +DDR_VTTREF

R122

R122

R123

R123

1K/F

1K/F

*0_NC

*0_NC

12

R144

R144
1K/F

1K/F

C188

C188

0.1U

0.1U

16

16

+3.3V_RUN

+SMDDR_VREF_DQ0

+SMDDR_VREF_DIMM0

+1.5V_SUS

PM_EXTTS#0

75
76
81
82
87
88
93
94

99
100
105
106
111
112
117
118
123
124

199

77
122
125

198

30

1

126

2
3
8

9
13
14
19
20
25
26
31
32
37
38
43

JDIM2B

JDIM2B

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

VDDSPD
NC1

NC2
NCTEST

EVENT#
RESET#

VREF_DQ
VREF_CA

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15

2-2013311-1

2-2013311-1

M2 VREF

2

1

4949

44

PC2100 DDR3 SDRAM SO-DIMM

PC2100 DDR3 SDRAM SO-DIMM

(204P)

(204P)

VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52

VTT1
VTT2

48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196

203
204

G1

G1

G2

G2

+3.3V_RUN

R474 *10K/F_NCR474 *10K/F_NC

Intel is requesting that customers implement
all methods (M1 and M2 and M3
described below) to generate and control
Reference voltage for Data/Strobe inputs
(VREFDQ) on Clarksfield based platforms.
for fine tuning of the VREFDQ levels to
optimize the voltage and timing margins.

M1:Fixed voltage resistor divider or
DDR Voltage Regulator drives the Vref
M2:A set of Digital potentiometers
and op amps are added on the motherboard (one pair
for each channel). This circuit is controlled by
SMBUS (SMB_CLK & SMB_DATA) on PCH.
M3:Intel investigating future processor
VREF_DQ generation to replace M1 and M2. This
would require routing processor signal balls
J17 and H17 to SO-DIMM connectors
directly.

+0.75V_DDR_VTT

11

PM_EXTTS#0

82

3

+1.5V_SUS

C454

C454
10U

10U

C162

C162

10U

10U

+3.3V_RUN

C241

C241

2.2U/6.3V/0603

2.2U/6.3V/0603

A A

Place these Caps near So-Dimm1.

C468

C468

C439

C439

10U

10U

10U

10U

C143

C143
10U

10U

C240

C240

0.1U

0.1U

5

C463

C463

C160

C160

0.1U

0.1U

10U

10U R41

+0.75V_DDR_VTT

C2661UC266
1U

C438

C438

0.1U

0.1U

C2701UC270
1U

C139

C139

0.1U

0.1U

C122

C122

0.1U

0.1U

C142

C142

0.1U

0.1U

C2671UC267
1U

+

+

C121

C121
330U

330U

7343

7343

2.5

2.5

C2711UC271
1U

+SMDDR_VREF_DIMM0

C189

C189

0.1U

0.1U

C280

C280
10U

10U

10

10
805

805

4

C157

C157

2.2U/6.3V/0603

2.2U/6.3V/0603

C269

C269
10U

10U

10

10
805

805

C158

C158

0.1U

0.1U

27

C156

C156

2.2U/6.3V/0603

2.2U/6.3V/0603

C268

C268
10U

10U

10

10
805

805

+1.5V_SUS +DDR_VTTREF

R41
1K/F

1K/F

12

R42

R42
1K/F

1K/F

3

R40

R40
*0_NC

*0_NC

C26

C26

0.1U

0.1U

16

16

21

R57 0R57 0

M1 VREF

+SMDDR_VREF_DQ0

M3 VREF

+SMDDR_VREF_DQ0 +M_VREF_DQ_DIMM0

R56 *0_NCR56 *0_NC

46

VREF_DQ

R57 R56

R40
(+DDR_VTTREF)

Stuff

X

X

Stuff

X

X

2

M1

M3

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

COMPUTER

DDR3 DIMM-0

DDR3 DIMM-0

DDR3 DIMM-0

FM9B 3A

FM9B 3A

FM9B 3A

13 65Thursday, October 01, 2009

13 65Thursday, October 01, 2009

13 65Thursday, October 01, 2009

1

5

M_B_A[15:0]4

D D

M_B_BS04
M_B_BS14
M_B_BS24
M_B_CS0#4
M_B_CS1#4
M_B_CLK04
M_B_CLK0#4
M_B_CLK14
M_B_CLK1#4
M_B_CKE04
M_B_CKE14

107

R234 10KR234 10K
R209 10KR209 10K

+3.3V_RUN

C C

B B

M_B_CAS#4
M_B_RAS#4
M_B_WE#4

WLAN_SMBCLK13,28,31,32,35
WLAN_SMBDATA13,28,31,32,35

M_B_ODT04
M_B_ODT14

M_B_DM[7:0]4

M_B_DQS[7:0]4

M_B_DQS#[7:0]4

M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15

DIMM1_SA0

DIMM1_SA1
WLAN_SMBCLK
WLAN_SMBDATA

M_B_DM0

M_B_DM1

M_B_DM2

M_B_DM3

M_B_DM4

M_B_DM5

M_B_DM6

M_B_DM7

M_B_DQS0

M_B_DQS1

M_B_DQS2

M_B_DQS3

M_B_DQS4

M_B_DQS5

M_B_DQS6

M_B_DQS7

M_B_DQS#0

M_B_DQS#1

M_B_DQS#2

M_B_DQS#3

M_B_DQS#4

M_B_DQS#5

M_B_DQS#6

M_B_DQS#7

98
97
96
95
92
91
90
86
89
85

107

84
83

119

80
78

109
108

79
114
121
101
103
102
104

73

74
115
110
113
197
201
202
200

116
120

11

28

46

63
136
153
170
187

12

29

47

64
137
154
171
188

10

27

45

62
135
152
169
186

JDIM1A

JDIM1A

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15

BA0
BA1
BA2
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE#
SA0
SA1
SCL
SDA

ODT0
ODT1

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7

2-2013290-1

2-2013290-1

4

M_B_DQ0M_B_A0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

+1.5V_SUS +DDR_VTTREF

PC2100 DDR3 SDRAM SO-DIMM

PC2100 DDR3 SDRAM SO-DIMM

5

DQ0

7

DQ1

15

DQ2

17

DQ3

4

DQ4

6

DQ5

16

DQ6

18

DQ7

21

DQ8

23

DQ9

33

DQ10

35

DQ11

22

DQ12

24

DQ13

34

DQ14

36

DQ15

39

DQ16

41

DQ17

51

DQ18

53

DQ19

40

DQ20

42

DQ21

50

DQ22

52

DQ23

57

DQ24

59

DQ25

67

DQ26

69

DQ27

56

DQ28

58

DQ29

68

DQ30

70

DQ31

129

DQ32

131

DQ33

141

DQ34

143

DQ35

130

DQ36

132

DQ37

140

DQ38

142

DQ39

147

DQ40

149

DQ41

157

DQ42

159

DQ43

146

DQ44

148

DQ45

158

(204P)

(204P)

DQ46

160

DQ47

163

DQ48

165

DQ49

175

DQ50

177

DQ51

164

DQ52

166

DQ53

174

DQ54

176

DQ55

181

DQ56

183

DQ57

191

DQ58

193

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

3

3

M_B_DQ[63:0] 4

DDR3_DRAMRST#3,13

+SMDDR_VREF_DIMM1

27

R124

R124
1K/F

1K/F

12

R145

R145
1K/F

1K/F

PM_EXTTS#13

+SMDDR_VREF_DQ1

R125

R125
*0_NC

*0_NC

+SMDDR_VREF_DIMM1

C190

C190

0.1U

0.1U

16

16

+3.3V_RUN

M2 VREF

+1.5V_SUS

PM_EXTTS#1

100
105
106
111
112
117
118
123
124

199

122
125

198

126

75
76
81
82
87
88
93
94
99

77

30

1

2
3
8

9
13
14
19
20
25
26
31
32
37
38
43

JDIM1B

JDIM1B

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

VDDSPD
NC1

NC2
NCTEST

EVENT#
RESET#

VREF_DQ
VREF_CA

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15

2-2013290-1

2-2013290-1

82

2

1

4949

44

PC2100 DDR3 SDRAM SO-DIMM

PC2100 DDR3 SDRAM SO-DIMM

(204P)

(204P)

VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52

VTT1
VTT2

48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196

203
204

G1

G1

G2

G2

+0.75V_DDR_VTT

+3.3V_RUN

R208

R208
*10K_NC

*10K_NC

12

107

PM_EXTTS#1

+1.5V_SUS

C163

C163
10U

10U

C164

C164
10U

10U

+3.3V_RUN

C243

C243

2.2U/6.3V/0603

2.2U/6.3V/0603

A A

Place these Caps near So-Dimm2.

C123

C123

C159

C145

C145
10U

10U

C242

C242

0.1U

0.1U

C159
10U

10U

C144

C144
10U

10U

+0.75V_DDR_VTT

5

C193

C193

10U

10U

0.1U

0.1U

C138

C138

C141

C141

0.1U

0.1U

0.1U

0.1U

C2741UC274

C2451UC245

1U

1U

C194

C194

0.1U

0.1U

C140

C140

0.1U

0.1U

C2441UC244
1U

+

+

C83

C83
330U

330U

7343

7343

2.5

2.5

C2751UC275
1U

+SMDDR_VREF_DIMM1

C191

C191

2.2U/6.3V/0603

2.2U/6.3V/0603

C210

C210

0.1U

0.1U

C247

C247
10U

10U

10

10
805

805

4

C276

C276
10U

10U

10

10
805

805

C192

C192

0.1U

0.1U

27

C161

C161

2.2U/6.3V/0603

2.2U/6.3V/0603

C246

C246
10U

10U

10

10
805

805

+1.5V_SUS +DDR_VTTREF

R44

R44
1K/F

1K/F

12

R45

R45
1K/F

1K/F

C27

C27

0.1U

0.1U

16

16

3

R43

R43
*0_NC

*0_NC

21

R59 0R59 0

M1 VREF

+SMDDR_VREF_DQ1+SMDDR_VREF_DQ1

VREF_DQ

46

M1

M3

+M_VREF_DQ_DIMM1

R58 *0_NCR58 *0_NC

R59 R58

X

Stuff

X

Stuff

M3 VREF

R43
(+DDR_VTTREF)

X

X

2

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

COMPUTER

DDR3 DIMM-1

DDR3 DIMM-1

DDR3 DIMM-1

FM9B 3A

FM9B 3A

FM9B 3A

14 65Thursday, October 01, 2009

14 65Thursday, October 01, 2009

14 65Thursday, October 01, 2009

1

5

D D

4

3

2

1

+3.3V_RUN

L38 BLM21PG600SN1D

L38 BLM21PG600SN1D

805

805

8

C C

CK_PWRGD_R42

CLK_ICH_14M9

IDT: 0.1uFx5pcs, 10uFx1pcs

C413

C413

C403

C403
10U

10U

0.1uF near the every power pin.

+3.3V_RUN

CLK_ICH_14M

Place the 33 ohm
resistors close to the CK 505

0.1U

0.1U

C414

C414

C416

C416

0.1U

0.1U

0.1U

0.1U

R375 10KR375 10K
R371 33R371 33

U25

U25

C400

C400

0.1U

0.1U

+3.3V_CLK_VDD

+VDDIO_CLK

CPU_SEL

XTAL_OUT
XTAL_IN

EC_SMBDAT0
EC_SMBCLK0

1

VDD_USB

5

VDD_LCD

17

VDD_SRC

24

VDD_CPU

29

VDD_REF

15

VDD_SRC_IO

18

VDD_CPU_IO

9

VSS_SATA

2

VSS_USB

8

VSS_LCD

12

VSS_SRC

21

VSS_CPU

26

VSS_REF

16

CPU_STOP#

25

CK_PWRGD/PD#_3.3

30

REF_0/CPU_SEL

27

XOUT

28

XIN

31

SDATA

32

SCLK

SLG8SP585VTR

SLG8SP585VTR

CK505

CK505

QFN32

QFN32

CPU-0

CPU-0#

CPU-1

CPU-1#

DOT96T_LPR

DOT96C_LPR

SRC-1

SRC-1#

SATA

SATA#

27MHz_nonSS

27MHz_SS

GND

23
22

20
19

3
4

13
14

10
11

6
7

33

40mil

C417

C417

0.1U

0.1U

EC_SMBDAT038
EC_SMBCLK038

Place within 0.5" of CLKGEN

CLK_BUF_BCLK_P
CLK_BUF_BCLK_N

CLK_BUF_DREFCLK
CLK_BUF_DREFCLK#

CLK_BUF_PCIE_3GPLL
CLK_BUF_PCIE_3GPLL#

CLK_BUF_DREFSSCLK
CLK_BUF_DREFSSCLK#

Realtek: 0.1uFx3pcs, 22uFx1pcs

CLK_BUF_BCLK_P 9
CLK_BUF_BCLK_N 9

CLK_BUF_DREFCLK 9
CLK_BUF_DREFCLK# 9

CLK_BUF_PCIE_3GPLL 9
CLK_BUF_PCIE_3GPLL# 9

CLK_BUF_DREFSSCLK 9
CLK_BUF_DREFSSCLK# 9

IDT: 0.1uFx2pcs, 10uFx1pcs

Realtek: 0.1uFx6pcs, 22uFx1pcs

+3.3V_RUN

Add capacitor pads for improving WWAN.

C398

C398

*27P_NC

*27P_NC

50

50

CLK_ICH_14M

B B

XTAL_IN XTAL_OUT

C401

C401
33P

33P

50

50

Y3

Y3

21

14.318MHZ

14.318MHZ
C402

C402
33P

33P

1 2

50

50

R376 *0_NCR376 *0_NC

+1.05V_PCH

R377 *0_shortR377 *0_short

SLG,IDT: +1.05V
Realtek: +3.3V

L39 BLM21PG600SN1D

L39 BLM21PG600SN1D

805

805

HP: 10u x2pcs

Q2

Place each 0.1uF cap as close as
possible to each VDD IO pin. Place
the 10uF caps on the VDD_IO plane.

C418

C418
10U

10U

40mil

C430

C430

0.1U

0.1U

+VDDIO_CLK

C415

C415

0.1U

0.1U

+VDDIO_CLK:
SLG date sheet (V0.2) P15: Min 1.05V,Max3.465V.

+3.3V_RUN

7

R372

R372
*4.7K_NC

*4.7K_NC

A A

1 2

CPU_SEL

R373

R373

4.7K

4.7K

1 2

5

C399

C399
*10P/50V_NC

*10P/50V_NC

EMI Capacitor

PIN 30 CPU_0 CPU_1

0(default)

1(0.7V-1.5V)

133MHz

100MHz 100MHz

133MHz

4

CPU_SEL:
SLG date sheet (V0.2) P15:
High Voltage: Min 0.7V, Max 1.5V.
Low Voltage: Min Vss-0.3V, Max 0.35V.
Realtek date sheet(V1.2) P11:
High Voltage: Min 0.7V, Max 1.5V.
Low Voltage: Min Vss-0.3V, Max 0.35V.
IDT date sheet(V0.7) P10:
High Voltage: Min 0.7V, Max 1.5V.
Low Voltage: Min Vss-0.3V, Max 0.35V.

3

2

Realtek date sheet(V1.2) P11: Min 1.05V,Max 3.3V.
IDT date sheet(V0.7) P10: Min 0.9975V,Max 3.465V.

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

Date: Sheet of

COMPUTER

Clock Generator

Clock Generator

Clock Generator

FM9B 3A

FM9B 3A

FM9B 3A

15 65Thursday, October 01, 2009

15 65Thursday, October 01, 2009

15 65Thursday, October 01, 2009

1

5

D D

C C

4

3

2

1

BLANK PAGE FOR PAGE
NUMBER SAME AS DISCRETE

B B

A A

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

VGA-M92-XT (PCIe)

VGA-M92-XT (PCIe)

VGA-M92-XT (PCIe)

FM9B 3A

FM9B 3A

FM9B 3A

1

16 65Thursday, October 01, 2009

16 65Thursday, October 01, 2009

16 65Thursday, October 01, 2009

5

D D

C C

4

3

2

1

BLANK PAGE FOR PAGE
NUMBER SAME AS DISCRETE

B B

A A

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

COMPUTER

Title

Title

Title

VGA-M92-XT (PCIe)

VGA-M92-XT (PCIe)

VGA-M92-XT (PCIe)

Size Docum ent Number Rev

Size Docum ent Number Rev

Size Docum ent Number Rev

FM9B 3A

FM9B 3A

FM9B 3A

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

1

17 65Thursday, October 01, 2 009

17 65Thursday, October 01, 2 009

17 65Thursday, October 01, 2 009

5

D D

C C

4

3

2

1

BLANK PAGE FOR PAGE
NUMBER SAME AS DISCRETE

B B

A A

QUANTA

QUANTA

QUANTA
COMPUTER

COMPUTER

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet of

Date: Sheet of

5

4

3

2

Date: Sheet of

COMPUTER

VGA-M92-XT (PCIe)

VGA-M92-XT (PCIe)

VGA-M92-XT (PCIe)

FM9B 3A

FM9B 3A

FM9B 3A

1

18 65Thursday, October 01, 2009

18 65Thursday, October 01, 2009

18 65Thursday, October 01, 2009